51859 lines
1.8 MiB
51859 lines
1.8 MiB
<?xml version="1.0" encoding="UTF-8"?>
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<!-- ============================================================================ -->
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<!-- Atmel Microcontroller Software Support -->
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<!-- SAM Software Package License -->
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<!-- ============================================================================ -->
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<!-- Copyright (c) %copyright_year%, Atmel Corporation -->
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<!-- -->
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<!-- All rights reserved. -->
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<!-- -->
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<!-- Redistribution and use in source and binary forms, with or without -->
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<!-- modification, are permitted provided that the following condition is met: -->
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<!-- -->
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<!-- - Redistributions of source code must retain the above copyright notice, -->
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<!-- this list of conditions and the disclaimer below. -->
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<!-- -->
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<!-- Atmel's name may not be used to endorse or promote products derived from -->
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<!-- this software without specific prior written permission. -->
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<!-- -->
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<!-- DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -->
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<!-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -->
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<!-- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -->
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<!-- DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -->
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<!-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -->
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<!-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -->
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<!-- OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -->
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<!-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -->
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<!-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -->
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<!-- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -->
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<!-- ============================================================================ -->
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<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
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<vendor>Atmel</vendor>
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<name>ATSAM4S2B</name>
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<series>SAM4S</series>
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<version>0</version>
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<description>Atmel ATSAM4S2B Microcontroller</description>
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<cpu>
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<name>CM4</name>
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<revision>r0p1</revision>
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<endian>selectable</endian>
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<mpuPresent>true</mpuPresent>
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<fpuPresent>false</fpuPresent>
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<nvicPrioBits>4</nvicPrioBits>
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<vendorSystickConfig>false</vendorSystickConfig>
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</cpu>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<peripherals>
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<peripheral>
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<name>HSMCI</name>
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<version>6449P</version>
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<description>High Speed MultiMedia Card Interface</description>
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<prependToName>HSMCI_</prependToName>
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<baseAddress>0x40000000</baseAddress>
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<addressBlock>
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<offset>0</offset>
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<size>0x4000</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>HSMCI</name>
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<value>18</value>
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</interrupt>
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<registers>
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<register>
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<name>CR</name>
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<description>Control Register</description>
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<addressOffset>0x00000000</addressOffset>
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<size>32</size>
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<access>write-only</access>
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<fields>
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<field>
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<name>MCIEN</name>
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<description>Multi-Media Interface Enable</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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<access>write-only</access>
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</field>
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<field>
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<name>MCIDIS</name>
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<description>Multi-Media Interface Disable</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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<access>write-only</access>
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</field>
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<field>
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<name>PWSEN</name>
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<description>Power Save Mode Enable</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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<access>write-only</access>
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</field>
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<field>
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<name>PWSDIS</name>
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<description>Power Save Mode Disable</description>
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<bitOffset>3</bitOffset>
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<bitWidth>1</bitWidth>
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<access>write-only</access>
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</field>
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<field>
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<name>SWRST</name>
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<description>Software Reset</description>
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<bitOffset>7</bitOffset>
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<bitWidth>1</bitWidth>
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<access>write-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>MR</name>
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<description>Mode Register</description>
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<addressOffset>0x00000004</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>CLKDIV</name>
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<description>Clock Divider</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>PWSDIV</name>
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<description>Power Saving Divider</description>
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<bitOffset>8</bitOffset>
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<bitWidth>3</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>RDPROOF</name>
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<description>Read Proof Enable</description>
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<bitOffset>11</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>WRPROOF</name>
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<description>Write Proof Enable</description>
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<bitOffset>12</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>FBYTE</name>
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<description>Force Byte Transfer</description>
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<bitOffset>13</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>PADV</name>
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<description>Padding Value</description>
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<bitOffset>14</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>PDCMODE</name>
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<description>PDC-oriented Mode</description>
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<bitOffset>15</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>DTOR</name>
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<description>Data Timeout Register</description>
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<addressOffset>0x00000008</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>DTOCYC</name>
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<description>Data Timeout Cycle Number</description>
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<bitOffset>0</bitOffset>
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<bitWidth>4</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>DTOMUL</name>
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<description>Data Timeout Multiplier</description>
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<bitOffset>4</bitOffset>
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<bitWidth>3</bitWidth>
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<access>read-write</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>1</name>
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<description>DTOCYC</description>
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<value>0x0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>16</name>
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<description>DTOCYC x 16</description>
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<value>0x1</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>128</name>
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<description>DTOCYC x 128</description>
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<value>0x2</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>256</name>
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<description>DTOCYC x 256</description>
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<value>0x3</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>1024</name>
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<description>DTOCYC x 1024</description>
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<value>0x4</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>4096</name>
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<description>DTOCYC x 4096</description>
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<value>0x5</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>65536</name>
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<description>DTOCYC x 65536</description>
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<value>0x6</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>1048576</name>
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<description>DTOCYC x 1048576</description>
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<value>0x7</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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</fields>
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</register>
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<register>
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<name>SDCR</name>
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<description>SD/SDIO Card Register</description>
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<addressOffset>0x0000000C</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>SDCSEL</name>
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<description>SDCard/SDIO Slot</description>
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<bitOffset>0</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-write</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>SLOTA</name>
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<description>Slot A is selected.</description>
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<value>0x0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SLOTB</name>
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<description>-</description>
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<value>0x1</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SLOTC</name>
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<description>-</description>
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<value>0x2</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SLOTD</name>
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<description>-</description>
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<value>0x3</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>SDCBUS</name>
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<description>SDCard/SDIO Bus Width</description>
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<bitOffset>6</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-write</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>1</name>
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<description>1 bit</description>
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<value>0x0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>4</name>
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<description>4 bits</description>
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<value>0x2</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>8</name>
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<description>8 bits</description>
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<value>0x3</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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</fields>
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</register>
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<register>
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<name>ARGR</name>
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<description>Argument Register</description>
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<addressOffset>0x00000010</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>ARG</name>
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<description>Command Argument</description>
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<bitOffset>0</bitOffset>
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<bitWidth>32</bitWidth>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>CMDR</name>
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<description>Command Register</description>
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<addressOffset>0x00000014</addressOffset>
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<size>32</size>
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<access>write-only</access>
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<fields>
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<field>
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<name>CMDNB</name>
|
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<description>Command Number</description>
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<bitOffset>0</bitOffset>
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<bitWidth>6</bitWidth>
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<access>write-only</access>
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</field>
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<field>
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<name>RSPTYP</name>
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<description>Response Type</description>
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<bitOffset>6</bitOffset>
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<bitWidth>2</bitWidth>
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<access>write-only</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>NORESP</name>
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<description>No response</description>
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<value>0x0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>48_BIT</name>
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<description>48-bit response</description>
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<value>0x1</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>136_BIT</name>
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<description>136-bit response</description>
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<value>0x2</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>R1B</name>
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<description>R1b response type</description>
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<value>0x3</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>SPCMD</name>
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<description>Special Command</description>
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<bitOffset>8</bitOffset>
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<bitWidth>3</bitWidth>
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<access>write-only</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>STD</name>
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<description>Not a special CMD.</description>
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<value>0x0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>INIT</name>
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<description>Initialization CMD: 74 clock cycles for initialization sequence.</description>
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<value>0x1</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SYNC</name>
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<description>Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command.</description>
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<value>0x2</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>CE_ATA</name>
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<description>CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line.</description>
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<value>0x3</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>IT_CMD</name>
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<description>Interrupt command: Corresponds to the Interrupt Mode (CMD40).</description>
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<value>0x4</value>
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</enumeratedValue>
|
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<enumeratedValue>
|
|
<name>IT_RESP</name>
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<description>Interrupt response: Corresponds to the Interrupt Mode (CMD40).</description>
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<value>0x5</value>
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</enumeratedValue>
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<enumeratedValue>
|
|
<name>BOR</name>
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<description>Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly.</description>
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<value>0x6</value>
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</enumeratedValue>
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<enumeratedValue>
|
|
<name>EBO</name>
|
|
<description>End Boot Operation. This command allows the host processor to terminate the boot operation mode.</description>
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<value>0x7</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>OPDCMD</name>
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<description>Open Drain Command</description>
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<bitOffset>11</bitOffset>
|
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<bitWidth>1</bitWidth>
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<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push pull command.</description>
|
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<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPENDRAIN</name>
|
|
<description>Open drain command.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
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<field>
|
|
<name>MAXLAT</name>
|
|
<description>Max Latency for Command to Response</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
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<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>5</name>
|
|
<description>5-cycle max latency.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64</name>
|
|
<description>64-cycle max latency.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRCMD</name>
|
|
<description>Transfer Command</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_DATA</name>
|
|
<description>No data transfer</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_DATA</name>
|
|
<description>Start data transfer</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_DATA</name>
|
|
<description>Stop data transfer</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRDIR</name>
|
|
<description>Transfer Direction</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WRITE</name>
|
|
<description>Write.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRTYP</name>
|
|
<description>Transfer Type</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SINGLE</name>
|
|
<description>MMC/SD Card Single Block</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MULTIPLE</name>
|
|
<description>MMC/SD Card Multiple Block</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STREAM</name>
|
|
<description>MMC Stream</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BYTE</name>
|
|
<description>SDIO Byte</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BLOCK</name>
|
|
<description>SDIO Block</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IOSPCMD</name>
|
|
<description>SDIO Special Command</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STD</name>
|
|
<description>Not an SDIO Special Command</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUSPEND</name>
|
|
<description>SDIO Suspend Command</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESUME</name>
|
|
<description>SDIO Resume Command</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATACS</name>
|
|
<description>ATA with Command Completion Signal</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal operation mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMPLETION</name>
|
|
<description>This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOOT_ACK</name>
|
|
<description>Boot Operation Acknowledge</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BLKR</name>
|
|
<description>Block Register</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BCNT</name>
|
|
<description>MMC/SDIO Block Count - SDIO Byte Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BLKLEN</name>
|
|
<description>Data Block Length</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSTOR</name>
|
|
<description>Completion Signal Timeout Register</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CSTOCYC</name>
|
|
<description>Completion Signal Timeout Cycle Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSTOMUL</name>
|
|
<description>Completion Signal Timeout Multiplier</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CSTOCYC x 1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16</name>
|
|
<description>CSTOCYC x 16</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128</name>
|
|
<description>CSTOCYC x 128</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256</name>
|
|
<description>CSTOCYC x 256</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1024</name>
|
|
<description>CSTOCYC x 1024</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4096</name>
|
|
<description>CSTOCYC x 4096</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>65536</name>
|
|
<description>CSTOCYC x 65536</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1048576</name>
|
|
<description>CSTOCYC x 1048576</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>RSPR[%s]</name>
|
|
<description>Response Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RSP</name>
|
|
<description>Response</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDR</name>
|
|
<description>Receive Data Register</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data to Read</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDR</name>
|
|
<description>Transmit Data Register</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data to Write</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000C0E5</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDRDY</name>
|
|
<description>Command Ready (cleared by writing in HSMCI_CMDR)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receiver Ready (cleared by reading HSMCI_RDR)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Ready (cleared by writing in HSMCI_TDR)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BLKE</name>
|
|
<description>Data Block Ended (cleared on read)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTIP</name>
|
|
<description>Data Transfer in Progress (cleared at the end of CRC16 calculation)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NOTBUSY</name>
|
|
<description>HSMCI Not Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of RX Buffer (cleared by writing HSMCI_RCR or HSMCI_RNCR(1))</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of TX Buffer (cleared by writing HSMCI_TCR or HSMCI_TNCR(1))</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SDIOIRQA</name>
|
|
<description>SDIO Interrupt for Slot A (cleared on read)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SDIOWAIT</name>
|
|
<description>SDIO Read Wait Operation Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CSRCV</name>
|
|
<description>CE-ATA Completion Signal Received (cleared on read)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>RX Buffer Full (cleared by writing HSMCI_RCR or HSMCI_RNCR(1))</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>TX Buffer Empty (cleared by writing HSMCI_TCR or HSMCI_TNCR(1))</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RINDE</name>
|
|
<description>Response Index Error (cleared by writing in HSMCI_CMDR)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RDIRE</name>
|
|
<description>Response Direction Error (cleared by writing in HSMCI_CMDR)</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RCRCE</name>
|
|
<description>Response CRC Error (cleared by writing in HSMCI_CMDR)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RENDE</name>
|
|
<description>Response End Bit Error (cleared by writing in HSMCI_CMDR)</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RTOE</name>
|
|
<description>Response Time-out Error (cleared by writing in HSMCI_CMDR)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCRCE</name>
|
|
<description>Data CRC Error (cleared on read)</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOE</name>
|
|
<description>Data Time-out Error (cleared on read)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CSTOE</name>
|
|
<description>Completion Signal Time-out Error (cleared on read)</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FIFOEMPTY</name>
|
|
<description>FIFO empty flag</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>XFRDONE</name>
|
|
<description>Transfer Done flag</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKRCV</name>
|
|
<description>Boot Operation Acknowledge Received (cleared on read)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKRCVE</name>
|
|
<description>Boot Operation Acknowledge Error (cleared on read)</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNRE</name>
|
|
<description>Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0)</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CMDRDY</name>
|
|
<description>Command Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receiver Ready Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Ready Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BLKE</name>
|
|
<description>Data Block Ended Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTIP</name>
|
|
<description>Data Transfer in Progress Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NOTBUSY</name>
|
|
<description>Data Not Busy Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SDIOIRQA</name>
|
|
<description>SDIO Interrupt for Slot A Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SDIOWAIT</name>
|
|
<description>SDIO Read Wait Operation Status Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CSRCV</name>
|
|
<description>Completion Signal Received Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RINDE</name>
|
|
<description>Response Index Error Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RDIRE</name>
|
|
<description>Response Direction Error Interrupt Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RCRCE</name>
|
|
<description>Response CRC Error Interrupt Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RENDE</name>
|
|
<description>Response End Bit Error Interrupt Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RTOE</name>
|
|
<description>Response Time-out Error Interrupt Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCRCE</name>
|
|
<description>Data CRC Error Interrupt Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOE</name>
|
|
<description>Data Time-out Error Interrupt Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CSTOE</name>
|
|
<description>Completion Signal Timeout Error Interrupt Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FIFOEMPTY</name>
|
|
<description>FIFO empty Interrupt enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>XFRDONE</name>
|
|
<description>Transfer Done Interrupt enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKRCV</name>
|
|
<description>Boot Acknowledge Interrupt Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKRCVE</name>
|
|
<description>Boot Acknowledge Error Interrupt Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Interrupt Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNRE</name>
|
|
<description>Underrun Interrupt Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CMDRDY</name>
|
|
<description>Command Ready Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receiver Ready Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Ready Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BLKE</name>
|
|
<description>Data Block Ended Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTIP</name>
|
|
<description>Data Transfer in Progress Interrupt Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NOTBUSY</name>
|
|
<description>Data Not Busy Interrupt Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SDIOIRQA</name>
|
|
<description>SDIO Interrupt for Slot A Interrupt Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SDIOWAIT</name>
|
|
<description>SDIO Read Wait Operation Status Interrupt Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CSRCV</name>
|
|
<description>Completion Signal received interrupt Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RINDE</name>
|
|
<description>Response Index Error Interrupt Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RDIRE</name>
|
|
<description>Response Direction Error Interrupt Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RCRCE</name>
|
|
<description>Response CRC Error Interrupt Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RENDE</name>
|
|
<description>Response End Bit Error Interrupt Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RTOE</name>
|
|
<description>Response Time-out Error Interrupt Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCRCE</name>
|
|
<description>Data CRC Error Interrupt Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOE</name>
|
|
<description>Data Time-out Error Interrupt Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CSTOE</name>
|
|
<description>Completion Signal Time out Error Interrupt Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FIFOEMPTY</name>
|
|
<description>FIFO empty Interrupt Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>XFRDONE</name>
|
|
<description>Transfer Done Interrupt Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKRCV</name>
|
|
<description>Boot Acknowledge Interrupt Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKRCVE</name>
|
|
<description>Boot Acknowledge Error Interrupt Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Interrupt Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNRE</name>
|
|
<description>Underrun Interrupt Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDRDY</name>
|
|
<description>Command Ready Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receiver Ready Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Ready Interrupt Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BLKE</name>
|
|
<description>Data Block Ended Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTIP</name>
|
|
<description>Data Transfer in Progress Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NOTBUSY</name>
|
|
<description>Data Not Busy Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SDIOIRQA</name>
|
|
<description>SDIO Interrupt for Slot A Interrupt Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SDIOWAIT</name>
|
|
<description>SDIO Read Wait Operation Status Interrupt Mask</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CSRCV</name>
|
|
<description>Completion Signal Received Interrupt Mask</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Mask</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Mask</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RINDE</name>
|
|
<description>Response Index Error Interrupt Mask</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RDIRE</name>
|
|
<description>Response Direction Error Interrupt Mask</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RCRCE</name>
|
|
<description>Response CRC Error Interrupt Mask</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RENDE</name>
|
|
<description>Response End Bit Error Interrupt Mask</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RTOE</name>
|
|
<description>Response Time-out Error Interrupt Mask</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCRCE</name>
|
|
<description>Data CRC Error Interrupt Mask</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOE</name>
|
|
<description>Data Time-out Error Interrupt Mask</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CSTOE</name>
|
|
<description>Completion Signal Time-out Error Interrupt Mask</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FIFOEMPTY</name>
|
|
<description>FIFO Empty Interrupt Mask</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>XFRDONE</name>
|
|
<description>Transfer Done Interrupt Mask</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKRCV</name>
|
|
<description>Boot Operation Acknowledge Received Interrupt Mask</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKRCVE</name>
|
|
<description>Boot Operation Acknowledge Error Interrupt Mask</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Interrupt Mask</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNRE</name>
|
|
<description>Underrun Interrupt Mask</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>Configuration Register</description>
|
|
<addressOffset>0x00000054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FIFOMODE</name>
|
|
<description>HSMCI Internal FIFO control mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FERRCTRL</name>
|
|
<description>Flow Error flag reset control mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSMODE</name>
|
|
<description>High Speed Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSYNC</name>
|
|
<description>Synchronize on the last block</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPMR</name>
|
|
<description>Write Protection Mode Register</description>
|
|
<addressOffset>0x000000E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protect Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPKEY</name>
|
|
<description>Write Protect Key</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.</description>
|
|
<value>0x4D4349</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPSR</name>
|
|
<description>Write Protection Status Register</description>
|
|
<addressOffset>0x000000E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>WPVS</name>
|
|
<description>Write Protection Violation Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPVSRC</name>
|
|
<description>Write Protection Violation Source</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>256</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<dimIndex>0-255</dimIndex>
|
|
<name>FIFO[%s]</name>
|
|
<description>FIFO Memory Aperture0</description>
|
|
<addressOffset>0x00000200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data to Read or Data to Write</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RPR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXPTR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<description>Receive Counter Register</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCTR</name>
|
|
<description>Receive Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPR</name>
|
|
<description>Transmit Pointer Register</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXPTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<addressOffset>0x0000010C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNPR</name>
|
|
<description>Receive Next Pointer Register</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNPTR</name>
|
|
<description>Receive Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNCR</name>
|
|
<description>Receive Next Counter Register</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNCTR</name>
|
|
<description>Receive Next Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNPR</name>
|
|
<description>Transmit Next Pointer Register</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNPTR</name>
|
|
<description>Transmit Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNCR</name>
|
|
<description>Transmit Next Counter Register</description>
|
|
<addressOffset>0x0000011C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNCTR</name>
|
|
<description>Transmit Counter Next</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTCR</name>
|
|
<description>Transfer Control Register</description>
|
|
<addressOffset>0x00000120</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXTDIS</name>
|
|
<description>Receiver Transfer Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTDIS</name>
|
|
<description>Transmitter Transfer Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTSR</name>
|
|
<description>Transfer Status Register</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SSC</name>
|
|
<version>6078O</version>
|
|
<description>Synchronous Serial Controller</description>
|
|
<prependToName>SSC_</prependToName>
|
|
<baseAddress>0x40004000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SSC</name>
|
|
<value>22</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receive Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receive Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmit Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDIS</name>
|
|
<description>Transmit Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMR</name>
|
|
<description>Clock Mode Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Clock Divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCMR</name>
|
|
<description>Receive Clock Mode Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKS</name>
|
|
<description>Receive Clock Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MCK</name>
|
|
<description>Divided Clock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TK</name>
|
|
<description>TK Clock signal</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RK</name>
|
|
<description>RK pin</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CKO</name>
|
|
<description>Receive Clock Output Mode Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None, RK pin is an input</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS</name>
|
|
<description>Continuous Receive Clock, RK pin is an output</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSFER</name>
|
|
<description>Receive Clock only during data transfers, RK pin is an output</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CKI</name>
|
|
<description>Receive Clock Inversion</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKG</name>
|
|
<description>Receive Clock Gating Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN_RF_LOW</name>
|
|
<description>Receive Clock enabled only if RF Low</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN_RF_HIGH</name>
|
|
<description>Receive Clock enabled only if RF High</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Receive Start Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS</name>
|
|
<description>Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSMIT</name>
|
|
<description>Transmit start</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RF_LOW</name>
|
|
<description>Detection of a low level on RF signal</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RF_HIGH</name>
|
|
<description>Detection of a high level on RF signal</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RF_FALLING</name>
|
|
<description>Detection of a falling edge on RF signal</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RF_RISING</name>
|
|
<description>Detection of a rising edge on RF signal</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RF_LEVEL</name>
|
|
<description>Detection of any level change on RF signal</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RF_EDGE</name>
|
|
<description>Detection of any edge on RF signal</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_0</name>
|
|
<description>Compare 0</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Receive Stop Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STTDLY</name>
|
|
<description>Receive Start Delay</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PERIOD</name>
|
|
<description>Receive Period Divider Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFMR</name>
|
|
<description>Receive Frame Mode Register</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATLEN</name>
|
|
<description>Data Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOOP</name>
|
|
<description>Loop Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>Most Significant Bit First</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATNB</name>
|
|
<description>Data Number per Frame</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSLEN</name>
|
|
<description>Receive Frame Sync Length</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSOS</name>
|
|
<description>Receive Frame Sync Output Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None, RF pin is an input</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGATIVE</name>
|
|
<description>Negative Pulse, RF pin is an output</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSITIVE</name>
|
|
<description>Positive Pulse, RF pin is an output</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Driven Low during data transfer, RF pin is an output</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Driven High during data transfer, RF pin is an output</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLING</name>
|
|
<description>Toggling at each start of data transfer, RF pin is an output</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSEDGE</name>
|
|
<description>Frame Sync Edge Detection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POSITIVE</name>
|
|
<description>Positive Edge Detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGATIVE</name>
|
|
<description>Negative Edge Detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSLEN_EXT</name>
|
|
<description>FSLEN Field Extension</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCMR</name>
|
|
<description>Transmit Clock Mode Register</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKS</name>
|
|
<description>Transmit Clock Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MCK</name>
|
|
<description>Divided Clock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RK</name>
|
|
<description>RK Clock signal</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TK</name>
|
|
<description>TK pin</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CKO</name>
|
|
<description>Transmit Clock Output Mode Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None, TK pin is an input</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS</name>
|
|
<description>Continuous Transmit Clock, TK pin is an output</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSFER</name>
|
|
<description>Transmit Clock only during data transfers, TK pin is an output</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CKI</name>
|
|
<description>Transmit Clock Inversion</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKG</name>
|
|
<description>Transmit Clock Gating Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN_TF_LOW</name>
|
|
<description>Transmit Clock enabled only if TF Low</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN_TF_HIGH</name>
|
|
<description>Transmit Clock enabled only if TF High</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Transmit Start Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS</name>
|
|
<description>Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RECEIVE</name>
|
|
<description>Receive start</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TF_LOW</name>
|
|
<description>Detection of a low level on TF signal</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TF_HIGH</name>
|
|
<description>Detection of a high level on TF signal</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TF_FALLING</name>
|
|
<description>Detection of a falling edge on TF signal</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TF_RISING</name>
|
|
<description>Detection of a rising edge on TF signal</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TF_LEVEL</name>
|
|
<description>Detection of any level change on TF signal</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TF_EDGE</name>
|
|
<description>Detection of any edge on TF signal</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STTDLY</name>
|
|
<description>Transmit Start Delay</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PERIOD</name>
|
|
<description>Transmit Period Divider Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TFMR</name>
|
|
<description>Transmit Frame Mode Register</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATLEN</name>
|
|
<description>Data Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATDEF</name>
|
|
<description>Data Default Value</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>Most Significant Bit First</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATNB</name>
|
|
<description>Data Number per Frame</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSLEN</name>
|
|
<description>Transmit Frame Sync Length</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSOS</name>
|
|
<description>Transmit Frame Sync Output Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None, TF pin is an input</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGATIVE</name>
|
|
<description>Negative Pulse, TF pin is an output</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSITIVE</name>
|
|
<description>Positive Pulse, TF pin is an output</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Driven Low during data transfer</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Driven High during data transfer</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLING</name>
|
|
<description>Toggling at each start of data transfer</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSDEN</name>
|
|
<description>Frame Sync Data Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSEDGE</name>
|
|
<description>Frame Sync Edge Detection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POSITIVE</name>
|
|
<description>Positive Edge Detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGATIVE</name>
|
|
<description>Negative Edge Detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSLEN_EXT</name>
|
|
<description>FSLEN Field Extension</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RHR</name>
|
|
<description>Receive Holding Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDAT</name>
|
|
<description>Receive Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR</name>
|
|
<description>Transmit Holding Register</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TDAT</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSHR</name>
|
|
<description>Receive Sync. Holding Register</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RSDAT</name>
|
|
<description>Receive Synchronization Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSHR</name>
|
|
<description>Transmit Sync. Holding Register</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSDAT</name>
|
|
<description>Transmit Synchronization Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RC0R</name>
|
|
<description>Receive Compare 0 Register</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CP0</name>
|
|
<description>Receive Compare Data 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RC1R</name>
|
|
<description>Receive Compare 1 Register</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CP1</name>
|
|
<description>Receive Compare Data 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000CC</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Transmit Empty</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmission</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receive Ready</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRUN</name>
|
|
<description>Receive Overrun</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Reception</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CP0</name>
|
|
<description>Compare 0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CP1</name>
|
|
<description>Compare 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXSYN</name>
|
|
<description>Transmit Sync</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXSYN</name>
|
|
<description>Receive Sync</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmit Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receive Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Transmit Empty Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmission Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receive Ready Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRUN</name>
|
|
<description>Receive Overrun Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Reception Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CP0</name>
|
|
<description>Compare 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CP1</name>
|
|
<description>Compare 1 Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXSYN</name>
|
|
<description>Tx Sync Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXSYN</name>
|
|
<description>Rx Sync Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Ready Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Transmit Empty Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmission Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receive Ready Interrupt Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRUN</name>
|
|
<description>Receive Overrun Interrupt Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Reception Interrupt Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CP0</name>
|
|
<description>Compare 0 Interrupt Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CP1</name>
|
|
<description>Compare 1 Interrupt Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXSYN</name>
|
|
<description>Tx Sync Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXSYN</name>
|
|
<description>Rx Sync Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Ready Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Transmit Empty Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmission Interrupt Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receive Ready Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRUN</name>
|
|
<description>Receive Overrun Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Reception Interrupt Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CP0</name>
|
|
<description>Compare 0 Interrupt Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CP1</name>
|
|
<description>Compare 1 Interrupt Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXSYN</name>
|
|
<description>Tx Sync Interrupt Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXSYN</name>
|
|
<description>Rx Sync Interrupt Mask</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPMR</name>
|
|
<description>Write Protection Mode Register</description>
|
|
<addressOffset>0x000000E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPKEY</name>
|
|
<description>Write Protection Key</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.</description>
|
|
<value>0x535343</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPSR</name>
|
|
<description>Write Protection Status Register</description>
|
|
<addressOffset>0x000000E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPVS</name>
|
|
<description>Write Protection Violation Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPVSRC</name>
|
|
<description>Write Protect Violation Source</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RPR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXPTR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<description>Receive Counter Register</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCTR</name>
|
|
<description>Receive Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPR</name>
|
|
<description>Transmit Pointer Register</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXPTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<addressOffset>0x0000010C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNPR</name>
|
|
<description>Receive Next Pointer Register</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNPTR</name>
|
|
<description>Receive Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNCR</name>
|
|
<description>Receive Next Counter Register</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNCTR</name>
|
|
<description>Receive Next Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNPR</name>
|
|
<description>Transmit Next Pointer Register</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNPTR</name>
|
|
<description>Transmit Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNCR</name>
|
|
<description>Transmit Next Counter Register</description>
|
|
<addressOffset>0x0000011C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNCTR</name>
|
|
<description>Transmit Counter Next</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTCR</name>
|
|
<description>Transfer Control Register</description>
|
|
<addressOffset>0x00000120</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXTDIS</name>
|
|
<description>Receiver Transfer Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTDIS</name>
|
|
<description>Transmitter Transfer Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTSR</name>
|
|
<description>Transfer Status Register</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI</name>
|
|
<version>6088ZF</version>
|
|
<description>Serial Peripheral Interface</description>
|
|
<prependToName>SPI_</prependToName>
|
|
<baseAddress>0x40008000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI</name>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SPIEN</name>
|
|
<description>SPI Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SPIDIS</name>
|
|
<description>SPI Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>SPI Software Reset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LASTXFER</name>
|
|
<description>Last Transfer</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MR</name>
|
|
<description>Mode Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MSTR</name>
|
|
<description>Master/Slave Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCSDEC</name>
|
|
<description>Chip Select Decode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MODFDIS</name>
|
|
<description>Mode Fault Detection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDRBT</name>
|
|
<description>Wait Data Read Before Transfer</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LLB</name>
|
|
<description>Local Loopback Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Peripheral Chip Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DLYBCS</name>
|
|
<description>Delay Between Chip Selects</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDR</name>
|
|
<description>Receive Data Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RD</name>
|
|
<description>Receive Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Peripheral Chip Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDR</name>
|
|
<description>Transmit Data Register</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TD</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Peripheral Chip Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LASTXFER</name>
|
|
<description>Last Transfer</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000F0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Register Full (cleared by reading SPI_RDR)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Register Empty (cleared by writing SPI_TDR)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MODF</name>
|
|
<description>Mode Fault Error (cleared on read)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRES</name>
|
|
<description>Overrun Error Status (cleared on read)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of RX Buffer (cleared by writing SPI_RCR or SPI_RNCR)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of TX Buffer (cleared by writing SPI_TCR or SPI_TNCR)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>RX Buffer Full (cleared by writing SPI_RCR or SPI_RNCR)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>TX Buffer Empty (cleared by writing SPI_TCR or SPI_TNCR)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NSSR</name>
|
|
<description>NSS Rising (cleared on read)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Transmission Registers Empty (cleared by writing SPI_TDR)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNDES</name>
|
|
<description>Underrun Error Status (Slave mode only) (cleared on read)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SPIENS</name>
|
|
<description>SPI Enable Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Register Full Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>SPI Transmit Data Register Empty Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MODF</name>
|
|
<description>Mode Fault Error Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRES</name>
|
|
<description>Overrun Error Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NSSR</name>
|
|
<description>NSS Rising Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Transmission Registers Empty Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNDES</name>
|
|
<description>Underrun Error Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Register Full Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>SPI Transmit Data Register Empty Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MODF</name>
|
|
<description>Mode Fault Error Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRES</name>
|
|
<description>Overrun Error Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NSSR</name>
|
|
<description>NSS Rising Interrupt Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Transmission Registers Empty Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNDES</name>
|
|
<description>Underrun Error Interrupt Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Register Full Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>SPI Transmit Data Register Empty Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MODF</name>
|
|
<description>Mode Fault Error Interrupt Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRES</name>
|
|
<description>Overrun Error Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NSSR</name>
|
|
<description>NSS Rising Interrupt Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Transmission Registers Empty Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNDES</name>
|
|
<description>Underrun Error Interrupt Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>CSR[%s]</name>
|
|
<description>Chip Select Register</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NCPHA</name>
|
|
<description>Clock Phase</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSNAAT</name>
|
|
<description>Chip Select Not Active After Transfer (Ignored if CSAAT = 1)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSAAT</name>
|
|
<description>Chip Select Active After Transfer</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Bits Per Transfer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>8_BIT</name>
|
|
<description>8 bits for transfer</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BIT</name>
|
|
<description>9 bits for transfer</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10_BIT</name>
|
|
<description>10 bits for transfer</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11_BIT</name>
|
|
<description>11 bits for transfer</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>12_BIT</name>
|
|
<description>12 bits for transfer</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>13_BIT</name>
|
|
<description>13 bits for transfer</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>14_BIT</name>
|
|
<description>14 bits for transfer</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>15_BIT</name>
|
|
<description>15 bits for transfer</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16_BIT</name>
|
|
<description>16 bits for transfer</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCBR</name>
|
|
<description>Serial Clock Bit Rate</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DLYBS</name>
|
|
<description>Delay Before SPCK</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DLYBCT</name>
|
|
<description>Delay Between Consecutive Transfers</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPMR</name>
|
|
<description>Write Protection Mode Register</description>
|
|
<addressOffset>0x000000E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPKEY</name>
|
|
<description>Write Protection Key</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.</description>
|
|
<value>0x535049</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPSR</name>
|
|
<description>Write Protection Status Register</description>
|
|
<addressOffset>0x000000E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPVS</name>
|
|
<description>Write Protection Violation Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPVSRC</name>
|
|
<description>Write Protection Violation Source</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RPR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXPTR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<description>Receive Counter Register</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCTR</name>
|
|
<description>Receive Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPR</name>
|
|
<description>Transmit Pointer Register</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXPTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<addressOffset>0x0000010C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNPR</name>
|
|
<description>Receive Next Pointer Register</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNPTR</name>
|
|
<description>Receive Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNCR</name>
|
|
<description>Receive Next Counter Register</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNCTR</name>
|
|
<description>Receive Next Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNPR</name>
|
|
<description>Transmit Next Pointer Register</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNPTR</name>
|
|
<description>Transmit Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNCR</name>
|
|
<description>Transmit Next Counter Register</description>
|
|
<addressOffset>0x0000011C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNCTR</name>
|
|
<description>Transmit Counter Next</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTCR</name>
|
|
<description>Transfer Control Register</description>
|
|
<addressOffset>0x00000120</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXTDIS</name>
|
|
<description>Receiver Transfer Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTDIS</name>
|
|
<description>Transmitter Transfer Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTSR</name>
|
|
<description>Transfer Status Register</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TC0</name>
|
|
<version>6082ZG</version>
|
|
<description>Timer Counter 0</description>
|
|
<groupName>TC</groupName>
|
|
<prependToName>TC0_</prependToName>
|
|
<baseAddress>0x40010000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TC0</name>
|
|
<value>23</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TC1</name>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TC2</name>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CCR0</name>
|
|
<description>Channel Control Register (channel = 0)</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CLKEN</name>
|
|
<description>Counter Clock Enable Command</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIS</name>
|
|
<description>Counter Clock Disable Command</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SWTRG</name>
|
|
<description>Software Trigger Command</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMR0</name>
|
|
<description>Channel Mode Register (channel = 0)</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TCCLKS</name>
|
|
<description>Clock Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK1</name>
|
|
<description>Clock selected: internal MCK/2 clock signal (from PMC)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK2</name>
|
|
<description>Clock selected: internal MCK/8 clock signal (from PMC)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK3</name>
|
|
<description>Clock selected: internal MCK/32 clock signal (from PMC)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK4</name>
|
|
<description>Clock selected: internal MCK/128 clock signal (from PMC)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK5</name>
|
|
<description>Clock selected: internal SLCK clock signal (from PMC)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC0</name>
|
|
<description>Clock selected: XC0</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC1</name>
|
|
<description>Clock selected: XC1</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC2</name>
|
|
<description>Clock selected: XC2</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKI</name>
|
|
<description>Clock Invert</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BURST</name>
|
|
<description>Burst Signal Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>The clock is not gated by an external signal.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC0</name>
|
|
<description>XC0 is ANDed with the selected clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC1</name>
|
|
<description>XC1 is ANDed with the selected clock.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC2</name>
|
|
<description>XC2 is ANDed with the selected clock.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDBSTOP</name>
|
|
<description>Counter Clock Stopped with RB Loading</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LDBDIS</name>
|
|
<description>Counter Clock Disable with RB Loading</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETRGEDG</name>
|
|
<description>External Trigger Edge Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>The clock is not gated by an external signal.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edge</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Each edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABETRG</name>
|
|
<description>TIOA or TIOB External Trigger Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPCTRG</name>
|
|
<description>RC Compare Trigger Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAVE</name>
|
|
<description>Waveform Mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRA</name>
|
|
<description>RA Loading Edge Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edge of TIOA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edge of TIOA</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Each edge of TIOA</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDRB</name>
|
|
<description>RB Loading Edge Selection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edge of TIOA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edge of TIOA</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Each edge of TIOA</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMR0_WAVEFORM_MODE</name>
|
|
<description>Channel Mode Register (channel = 0)</description>
|
|
<alternateGroup>WAVEFORM_MODE</alternateGroup>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TCCLKS</name>
|
|
<description>Clock Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK1</name>
|
|
<description>Clock selected: internal MCK/2 clock signal (from PMC)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK2</name>
|
|
<description>Clock selected: internal MCK/8 clock signal (from PMC)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK3</name>
|
|
<description>Clock selected: internal MCK/32 clock signal (from PMC)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK4</name>
|
|
<description>Clock selected: internal MCK/128 clock signal (from PMC)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK5</name>
|
|
<description>Clock selected: internal SLCK clock signal (from PMC)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC0</name>
|
|
<description>Clock selected: XC0</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC1</name>
|
|
<description>Clock selected: XC1</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC2</name>
|
|
<description>Clock selected: XC2</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKI</name>
|
|
<description>Clock Invert</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BURST</name>
|
|
<description>Burst Signal Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>The clock is not gated by an external signal.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC0</name>
|
|
<description>XC0 is ANDed with the selected clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC1</name>
|
|
<description>XC1 is ANDed with the selected clock.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC2</name>
|
|
<description>XC2 is ANDed with the selected clock.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPCSTOP</name>
|
|
<description>Counter Clock Stopped with RC Compare</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPCDIS</name>
|
|
<description>Counter Clock Disable with RC Compare</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EEVTEDG</name>
|
|
<description>External Event Edge Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edge</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Each edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEVT</name>
|
|
<description>External Event Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIOB</name>
|
|
<description>TIOB</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC0</name>
|
|
<description>XC0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC1</name>
|
|
<description>XC1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC2</name>
|
|
<description>XC2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENETRG</name>
|
|
<description>External Event Trigger Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAVSEL</name>
|
|
<description>Waveform Selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UP</name>
|
|
<description>UP mode without automatic trigger on RC Compare</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDOWN</name>
|
|
<description>UPDOWN mode without automatic trigger on RC Compare</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UP_RC</name>
|
|
<description>UP mode with automatic trigger on RC Compare</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDOWN_RC</name>
|
|
<description>UPDOWN mode with automatic trigger on RC Compare</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAVE</name>
|
|
<description>Waveform Mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACPA</name>
|
|
<description>RA Compare Effect on TIOA</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACPC</name>
|
|
<description>RC Compare Effect on TIOA</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AEEVT</name>
|
|
<description>External Event Effect on TIOA</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASWTRG</name>
|
|
<description>Software Trigger Effect on TIOA</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCPB</name>
|
|
<description>RB Compare Effect on TIOB</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCPC</name>
|
|
<description>RC Compare Effect on TIOB</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEEVT</name>
|
|
<description>External Event Effect on TIOB</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSWTRG</name>
|
|
<description>Software Trigger Effect on TIOB</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMMR0</name>
|
|
<description>Stepper Motor Mode Register (channel = 0)</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GCEN</name>
|
|
<description>Gray Count Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DOWN</name>
|
|
<description>Down Count</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CV0</name>
|
|
<description>Counter Value (channel = 0)</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CV</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RA0</name>
|
|
<description>Register A (channel = 0)</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RA</name>
|
|
<description>Register A</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RB0</name>
|
|
<description>Register B (channel = 0)</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RB</name>
|
|
<description>Register B</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RC0</name>
|
|
<description>Register C (channel = 0)</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RC</name>
|
|
<description>Register C</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR0</name>
|
|
<description>Status Register (channel = 0)</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COVFS</name>
|
|
<description>Counter Overflow Status (cleared on read)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOVRS</name>
|
|
<description>Load Overrun Status (cleared on read)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPAS</name>
|
|
<description>RA Compare Status (cleared on read)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPBS</name>
|
|
<description>RB Compare Status (cleared on read)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPCS</name>
|
|
<description>RC Compare Status (cleared on read)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRAS</name>
|
|
<description>RA Loading Status (cleared on read)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRBS</name>
|
|
<description>RB Loading Status (cleared on read)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ETRGS</name>
|
|
<description>External Trigger Status (cleared on read)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKSTA</name>
|
|
<description>Clock Enabling Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MTIOA</name>
|
|
<description>TIOA Mirror</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MTIOB</name>
|
|
<description>TIOB Mirror</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER0</name>
|
|
<description>Interrupt Enable Register (channel = 0)</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>COVFS</name>
|
|
<description>Counter Overflow</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOVRS</name>
|
|
<description>Load Overrun</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPAS</name>
|
|
<description>RA Compare</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPBS</name>
|
|
<description>RB Compare</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPCS</name>
|
|
<description>RC Compare</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRAS</name>
|
|
<description>RA Loading</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRBS</name>
|
|
<description>RB Loading</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ETRGS</name>
|
|
<description>External Trigger</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR0</name>
|
|
<description>Interrupt Disable Register (channel = 0)</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>COVFS</name>
|
|
<description>Counter Overflow</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOVRS</name>
|
|
<description>Load Overrun</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPAS</name>
|
|
<description>RA Compare</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPBS</name>
|
|
<description>RB Compare</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPCS</name>
|
|
<description>RC Compare</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRAS</name>
|
|
<description>RA Loading</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRBS</name>
|
|
<description>RB Loading</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ETRGS</name>
|
|
<description>External Trigger</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR0</name>
|
|
<description>Interrupt Mask Register (channel = 0)</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COVFS</name>
|
|
<description>Counter Overflow</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOVRS</name>
|
|
<description>Load Overrun</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPAS</name>
|
|
<description>RA Compare</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPBS</name>
|
|
<description>RB Compare</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPCS</name>
|
|
<description>RC Compare</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRAS</name>
|
|
<description>RA Loading</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRBS</name>
|
|
<description>RB Loading</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ETRGS</name>
|
|
<description>External Trigger</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR1</name>
|
|
<description>Channel Control Register (channel = 1)</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CLKEN</name>
|
|
<description>Counter Clock Enable Command</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIS</name>
|
|
<description>Counter Clock Disable Command</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SWTRG</name>
|
|
<description>Software Trigger Command</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMR1</name>
|
|
<description>Channel Mode Register (channel = 1)</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TCCLKS</name>
|
|
<description>Clock Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK1</name>
|
|
<description>Clock selected: internal MCK/2 clock signal (from PMC)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK2</name>
|
|
<description>Clock selected: internal MCK/8 clock signal (from PMC)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK3</name>
|
|
<description>Clock selected: internal MCK/32 clock signal (from PMC)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK4</name>
|
|
<description>Clock selected: internal MCK/128 clock signal (from PMC)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK5</name>
|
|
<description>Clock selected: internal SLCK clock signal (from PMC)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC0</name>
|
|
<description>Clock selected: XC0</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC1</name>
|
|
<description>Clock selected: XC1</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC2</name>
|
|
<description>Clock selected: XC2</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKI</name>
|
|
<description>Clock Invert</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BURST</name>
|
|
<description>Burst Signal Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>The clock is not gated by an external signal.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC0</name>
|
|
<description>XC0 is ANDed with the selected clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC1</name>
|
|
<description>XC1 is ANDed with the selected clock.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC2</name>
|
|
<description>XC2 is ANDed with the selected clock.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDBSTOP</name>
|
|
<description>Counter Clock Stopped with RB Loading</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LDBDIS</name>
|
|
<description>Counter Clock Disable with RB Loading</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETRGEDG</name>
|
|
<description>External Trigger Edge Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>The clock is not gated by an external signal.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edge</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Each edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABETRG</name>
|
|
<description>TIOA or TIOB External Trigger Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPCTRG</name>
|
|
<description>RC Compare Trigger Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAVE</name>
|
|
<description>Waveform Mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRA</name>
|
|
<description>RA Loading Edge Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edge of TIOA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edge of TIOA</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Each edge of TIOA</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDRB</name>
|
|
<description>RB Loading Edge Selection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edge of TIOA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edge of TIOA</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Each edge of TIOA</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMR1_WAVEFORM_MODE</name>
|
|
<description>Channel Mode Register (channel = 1)</description>
|
|
<alternateGroup>WAVEFORM_MODE</alternateGroup>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TCCLKS</name>
|
|
<description>Clock Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK1</name>
|
|
<description>Clock selected: internal MCK/2 clock signal (from PMC)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK2</name>
|
|
<description>Clock selected: internal MCK/8 clock signal (from PMC)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK3</name>
|
|
<description>Clock selected: internal MCK/32 clock signal (from PMC)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK4</name>
|
|
<description>Clock selected: internal MCK/128 clock signal (from PMC)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK5</name>
|
|
<description>Clock selected: internal SLCK clock signal (from PMC)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC0</name>
|
|
<description>Clock selected: XC0</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC1</name>
|
|
<description>Clock selected: XC1</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC2</name>
|
|
<description>Clock selected: XC2</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKI</name>
|
|
<description>Clock Invert</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BURST</name>
|
|
<description>Burst Signal Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>The clock is not gated by an external signal.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC0</name>
|
|
<description>XC0 is ANDed with the selected clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC1</name>
|
|
<description>XC1 is ANDed with the selected clock.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC2</name>
|
|
<description>XC2 is ANDed with the selected clock.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPCSTOP</name>
|
|
<description>Counter Clock Stopped with RC Compare</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPCDIS</name>
|
|
<description>Counter Clock Disable with RC Compare</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EEVTEDG</name>
|
|
<description>External Event Edge Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edge</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Each edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEVT</name>
|
|
<description>External Event Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIOB</name>
|
|
<description>TIOB</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC0</name>
|
|
<description>XC0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC1</name>
|
|
<description>XC1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC2</name>
|
|
<description>XC2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENETRG</name>
|
|
<description>External Event Trigger Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAVSEL</name>
|
|
<description>Waveform Selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UP</name>
|
|
<description>UP mode without automatic trigger on RC Compare</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDOWN</name>
|
|
<description>UPDOWN mode without automatic trigger on RC Compare</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UP_RC</name>
|
|
<description>UP mode with automatic trigger on RC Compare</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDOWN_RC</name>
|
|
<description>UPDOWN mode with automatic trigger on RC Compare</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAVE</name>
|
|
<description>Waveform Mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACPA</name>
|
|
<description>RA Compare Effect on TIOA</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACPC</name>
|
|
<description>RC Compare Effect on TIOA</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AEEVT</name>
|
|
<description>External Event Effect on TIOA</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASWTRG</name>
|
|
<description>Software Trigger Effect on TIOA</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCPB</name>
|
|
<description>RB Compare Effect on TIOB</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCPC</name>
|
|
<description>RC Compare Effect on TIOB</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEEVT</name>
|
|
<description>External Event Effect on TIOB</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSWTRG</name>
|
|
<description>Software Trigger Effect on TIOB</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMMR1</name>
|
|
<description>Stepper Motor Mode Register (channel = 1)</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GCEN</name>
|
|
<description>Gray Count Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DOWN</name>
|
|
<description>Down Count</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CV1</name>
|
|
<description>Counter Value (channel = 1)</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CV</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RA1</name>
|
|
<description>Register A (channel = 1)</description>
|
|
<addressOffset>0x00000054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RA</name>
|
|
<description>Register A</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RB1</name>
|
|
<description>Register B (channel = 1)</description>
|
|
<addressOffset>0x00000058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RB</name>
|
|
<description>Register B</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RC1</name>
|
|
<description>Register C (channel = 1)</description>
|
|
<addressOffset>0x0000005C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RC</name>
|
|
<description>Register C</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR1</name>
|
|
<description>Status Register (channel = 1)</description>
|
|
<addressOffset>0x00000060</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COVFS</name>
|
|
<description>Counter Overflow Status (cleared on read)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOVRS</name>
|
|
<description>Load Overrun Status (cleared on read)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPAS</name>
|
|
<description>RA Compare Status (cleared on read)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPBS</name>
|
|
<description>RB Compare Status (cleared on read)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPCS</name>
|
|
<description>RC Compare Status (cleared on read)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRAS</name>
|
|
<description>RA Loading Status (cleared on read)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRBS</name>
|
|
<description>RB Loading Status (cleared on read)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ETRGS</name>
|
|
<description>External Trigger Status (cleared on read)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKSTA</name>
|
|
<description>Clock Enabling Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MTIOA</name>
|
|
<description>TIOA Mirror</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MTIOB</name>
|
|
<description>TIOB Mirror</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER1</name>
|
|
<description>Interrupt Enable Register (channel = 1)</description>
|
|
<addressOffset>0x00000064</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>COVFS</name>
|
|
<description>Counter Overflow</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOVRS</name>
|
|
<description>Load Overrun</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPAS</name>
|
|
<description>RA Compare</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPBS</name>
|
|
<description>RB Compare</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPCS</name>
|
|
<description>RC Compare</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRAS</name>
|
|
<description>RA Loading</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRBS</name>
|
|
<description>RB Loading</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ETRGS</name>
|
|
<description>External Trigger</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR1</name>
|
|
<description>Interrupt Disable Register (channel = 1)</description>
|
|
<addressOffset>0x00000068</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>COVFS</name>
|
|
<description>Counter Overflow</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOVRS</name>
|
|
<description>Load Overrun</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPAS</name>
|
|
<description>RA Compare</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPBS</name>
|
|
<description>RB Compare</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPCS</name>
|
|
<description>RC Compare</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRAS</name>
|
|
<description>RA Loading</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRBS</name>
|
|
<description>RB Loading</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ETRGS</name>
|
|
<description>External Trigger</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR1</name>
|
|
<description>Interrupt Mask Register (channel = 1)</description>
|
|
<addressOffset>0x0000006C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COVFS</name>
|
|
<description>Counter Overflow</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOVRS</name>
|
|
<description>Load Overrun</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPAS</name>
|
|
<description>RA Compare</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPBS</name>
|
|
<description>RB Compare</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPCS</name>
|
|
<description>RC Compare</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRAS</name>
|
|
<description>RA Loading</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRBS</name>
|
|
<description>RB Loading</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ETRGS</name>
|
|
<description>External Trigger</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR2</name>
|
|
<description>Channel Control Register (channel = 2)</description>
|
|
<addressOffset>0x00000080</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CLKEN</name>
|
|
<description>Counter Clock Enable Command</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIS</name>
|
|
<description>Counter Clock Disable Command</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SWTRG</name>
|
|
<description>Software Trigger Command</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMR2</name>
|
|
<description>Channel Mode Register (channel = 2)</description>
|
|
<addressOffset>0x00000084</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TCCLKS</name>
|
|
<description>Clock Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK1</name>
|
|
<description>Clock selected: internal MCK/2 clock signal (from PMC)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK2</name>
|
|
<description>Clock selected: internal MCK/8 clock signal (from PMC)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK3</name>
|
|
<description>Clock selected: internal MCK/32 clock signal (from PMC)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK4</name>
|
|
<description>Clock selected: internal MCK/128 clock signal (from PMC)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK5</name>
|
|
<description>Clock selected: internal SLCK clock signal (from PMC)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC0</name>
|
|
<description>Clock selected: XC0</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC1</name>
|
|
<description>Clock selected: XC1</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC2</name>
|
|
<description>Clock selected: XC2</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKI</name>
|
|
<description>Clock Invert</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BURST</name>
|
|
<description>Burst Signal Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>The clock is not gated by an external signal.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC0</name>
|
|
<description>XC0 is ANDed with the selected clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC1</name>
|
|
<description>XC1 is ANDed with the selected clock.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC2</name>
|
|
<description>XC2 is ANDed with the selected clock.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDBSTOP</name>
|
|
<description>Counter Clock Stopped with RB Loading</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LDBDIS</name>
|
|
<description>Counter Clock Disable with RB Loading</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETRGEDG</name>
|
|
<description>External Trigger Edge Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>The clock is not gated by an external signal.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edge</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Each edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABETRG</name>
|
|
<description>TIOA or TIOB External Trigger Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPCTRG</name>
|
|
<description>RC Compare Trigger Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAVE</name>
|
|
<description>Waveform Mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRA</name>
|
|
<description>RA Loading Edge Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edge of TIOA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edge of TIOA</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Each edge of TIOA</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDRB</name>
|
|
<description>RB Loading Edge Selection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edge of TIOA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edge of TIOA</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Each edge of TIOA</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMR2_WAVEFORM_MODE</name>
|
|
<description>Channel Mode Register (channel = 2)</description>
|
|
<alternateGroup>WAVEFORM_MODE</alternateGroup>
|
|
<addressOffset>0x00000084</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TCCLKS</name>
|
|
<description>Clock Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK1</name>
|
|
<description>Clock selected: internal MCK/2 clock signal (from PMC)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK2</name>
|
|
<description>Clock selected: internal MCK/8 clock signal (from PMC)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK3</name>
|
|
<description>Clock selected: internal MCK/32 clock signal (from PMC)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK4</name>
|
|
<description>Clock selected: internal MCK/128 clock signal (from PMC)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLOCK5</name>
|
|
<description>Clock selected: internal SLCK clock signal (from PMC)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC0</name>
|
|
<description>Clock selected: XC0</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC1</name>
|
|
<description>Clock selected: XC1</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC2</name>
|
|
<description>Clock selected: XC2</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKI</name>
|
|
<description>Clock Invert</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BURST</name>
|
|
<description>Burst Signal Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>The clock is not gated by an external signal.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC0</name>
|
|
<description>XC0 is ANDed with the selected clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC1</name>
|
|
<description>XC1 is ANDed with the selected clock.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC2</name>
|
|
<description>XC2 is ANDed with the selected clock.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPCSTOP</name>
|
|
<description>Counter Clock Stopped with RC Compare</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPCDIS</name>
|
|
<description>Counter Clock Disable with RC Compare</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EEVTEDG</name>
|
|
<description>External Event Edge Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edge</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Each edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEVT</name>
|
|
<description>External Event Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIOB</name>
|
|
<description>TIOB</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC0</name>
|
|
<description>XC0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC1</name>
|
|
<description>XC1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XC2</name>
|
|
<description>XC2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENETRG</name>
|
|
<description>External Event Trigger Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAVSEL</name>
|
|
<description>Waveform Selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UP</name>
|
|
<description>UP mode without automatic trigger on RC Compare</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDOWN</name>
|
|
<description>UPDOWN mode without automatic trigger on RC Compare</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UP_RC</name>
|
|
<description>UP mode with automatic trigger on RC Compare</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDOWN_RC</name>
|
|
<description>UPDOWN mode with automatic trigger on RC Compare</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAVE</name>
|
|
<description>Waveform Mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACPA</name>
|
|
<description>RA Compare Effect on TIOA</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACPC</name>
|
|
<description>RC Compare Effect on TIOA</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AEEVT</name>
|
|
<description>External Event Effect on TIOA</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASWTRG</name>
|
|
<description>Software Trigger Effect on TIOA</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCPB</name>
|
|
<description>RB Compare Effect on TIOB</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCPC</name>
|
|
<description>RC Compare Effect on TIOB</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEEVT</name>
|
|
<description>External Event Effect on TIOB</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSWTRG</name>
|
|
<description>Software Trigger Effect on TIOB</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMMR2</name>
|
|
<description>Stepper Motor Mode Register (channel = 2)</description>
|
|
<addressOffset>0x00000088</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GCEN</name>
|
|
<description>Gray Count Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DOWN</name>
|
|
<description>Down Count</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CV2</name>
|
|
<description>Counter Value (channel = 2)</description>
|
|
<addressOffset>0x00000090</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CV</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RA2</name>
|
|
<description>Register A (channel = 2)</description>
|
|
<addressOffset>0x00000094</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RA</name>
|
|
<description>Register A</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RB2</name>
|
|
<description>Register B (channel = 2)</description>
|
|
<addressOffset>0x00000098</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RB</name>
|
|
<description>Register B</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RC2</name>
|
|
<description>Register C (channel = 2)</description>
|
|
<addressOffset>0x0000009C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RC</name>
|
|
<description>Register C</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR2</name>
|
|
<description>Status Register (channel = 2)</description>
|
|
<addressOffset>0x000000A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COVFS</name>
|
|
<description>Counter Overflow Status (cleared on read)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOVRS</name>
|
|
<description>Load Overrun Status (cleared on read)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPAS</name>
|
|
<description>RA Compare Status (cleared on read)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPBS</name>
|
|
<description>RB Compare Status (cleared on read)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPCS</name>
|
|
<description>RC Compare Status (cleared on read)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRAS</name>
|
|
<description>RA Loading Status (cleared on read)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRBS</name>
|
|
<description>RB Loading Status (cleared on read)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ETRGS</name>
|
|
<description>External Trigger Status (cleared on read)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKSTA</name>
|
|
<description>Clock Enabling Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MTIOA</name>
|
|
<description>TIOA Mirror</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MTIOB</name>
|
|
<description>TIOB Mirror</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER2</name>
|
|
<description>Interrupt Enable Register (channel = 2)</description>
|
|
<addressOffset>0x000000A4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>COVFS</name>
|
|
<description>Counter Overflow</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOVRS</name>
|
|
<description>Load Overrun</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPAS</name>
|
|
<description>RA Compare</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPBS</name>
|
|
<description>RB Compare</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPCS</name>
|
|
<description>RC Compare</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRAS</name>
|
|
<description>RA Loading</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRBS</name>
|
|
<description>RB Loading</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ETRGS</name>
|
|
<description>External Trigger</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR2</name>
|
|
<description>Interrupt Disable Register (channel = 2)</description>
|
|
<addressOffset>0x000000A8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>COVFS</name>
|
|
<description>Counter Overflow</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOVRS</name>
|
|
<description>Load Overrun</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPAS</name>
|
|
<description>RA Compare</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPBS</name>
|
|
<description>RB Compare</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPCS</name>
|
|
<description>RC Compare</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRAS</name>
|
|
<description>RA Loading</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRBS</name>
|
|
<description>RB Loading</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ETRGS</name>
|
|
<description>External Trigger</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR2</name>
|
|
<description>Interrupt Mask Register (channel = 2)</description>
|
|
<addressOffset>0x000000AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COVFS</name>
|
|
<description>Counter Overflow</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOVRS</name>
|
|
<description>Load Overrun</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPAS</name>
|
|
<description>RA Compare</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPBS</name>
|
|
<description>RB Compare</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPCS</name>
|
|
<description>RC Compare</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRAS</name>
|
|
<description>RA Loading</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDRBS</name>
|
|
<description>RB Loading</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ETRGS</name>
|
|
<description>External Trigger</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCR</name>
|
|
<description>Block Control Register</description>
|
|
<addressOffset>0x000000C0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SYNC</name>
|
|
<description>Synchro Command</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BMR</name>
|
|
<description>Block Mode Register</description>
|
|
<addressOffset>0x000000C4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TC0XC0S</name>
|
|
<description>External Clock Signal 0 Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TCLK0</name>
|
|
<description>Signal connected to XC0: TCLK0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIOA1</name>
|
|
<description>Signal connected to XC0: TIOA1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIOA2</name>
|
|
<description>Signal connected to XC0: TIOA2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC1XC1S</name>
|
|
<description>External Clock Signal 1 Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TCLK1</name>
|
|
<description>Signal connected to XC1: TCLK1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIOA0</name>
|
|
<description>Signal connected to XC1: TIOA0</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIOA2</name>
|
|
<description>Signal connected to XC1: TIOA2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC2XC2S</name>
|
|
<description>External Clock Signal 2 Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TCLK2</name>
|
|
<description>Signal connected to XC2: TCLK2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIOA0</name>
|
|
<description>Signal connected to XC2: TIOA0</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIOA1</name>
|
|
<description>Signal connected to XC2: TIOA1</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QDEN</name>
|
|
<description>Quadrature Decoder Enabled</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POSEN</name>
|
|
<description>Position Enabled</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SPEEDEN</name>
|
|
<description>Speed Enabled</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>QDTRANS</name>
|
|
<description>Quadrature Decoding Transparent</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EDGPHA</name>
|
|
<description>Edge on PHA Count Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INVA</name>
|
|
<description>Inverted PHA</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INVB</name>
|
|
<description>Inverted PHB</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INVIDX</name>
|
|
<description>Inverted Index</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWAP</name>
|
|
<description>Swap PHA and PHB</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IDXPHB</name>
|
|
<description>Index Pin is PHB Pin</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAXFILT</name>
|
|
<description>Maximum Filter</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>QIER</name>
|
|
<description>QDEC Interrupt Enable Register</description>
|
|
<addressOffset>0x000000C8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>IDX</name>
|
|
<description>Index</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIRCHG</name>
|
|
<description>Direction Change</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>QERR</name>
|
|
<description>Quadrature Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>QIDR</name>
|
|
<description>QDEC Interrupt Disable Register</description>
|
|
<addressOffset>0x000000CC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>IDX</name>
|
|
<description>Index</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIRCHG</name>
|
|
<description>Direction Change</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>QERR</name>
|
|
<description>Quadrature Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>QIMR</name>
|
|
<description>QDEC Interrupt Mask Register</description>
|
|
<addressOffset>0x000000D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IDX</name>
|
|
<description>Index</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIRCHG</name>
|
|
<description>Direction Change</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>QERR</name>
|
|
<description>Quadrature Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>QISR</name>
|
|
<description>QDEC Interrupt Status Register</description>
|
|
<addressOffset>0x000000D4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IDX</name>
|
|
<description>Index</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIRCHG</name>
|
|
<description>Direction Change</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>QERR</name>
|
|
<description>Quadrature Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Direction</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMR</name>
|
|
<description>Fault Mode Register</description>
|
|
<addressOffset>0x000000D8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENCF0</name>
|
|
<description>Enable Compare Fault Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENCF1</name>
|
|
<description>Enable Compare Fault Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPMR</name>
|
|
<description>Write Protection Mode Register</description>
|
|
<addressOffset>0x000000E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPKEY</name>
|
|
<description>Write Protection Key</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.</description>
|
|
<value>0x54494D</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TWI0</name>
|
|
<version>6212Z</version>
|
|
<description>Two-wire Interface 0</description>
|
|
<groupName>TWI</groupName>
|
|
<prependToName>TWI0_</prependToName>
|
|
<baseAddress>0x40018000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TWI0</name>
|
|
<value>19</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Send a START Condition</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Send a STOP Condition</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MSEN</name>
|
|
<description>TWI Master Mode Enabled</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MSDIS</name>
|
|
<description>TWI Master Mode Disabled</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SVEN</name>
|
|
<description>TWI Slave Mode Enabled</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SVDIS</name>
|
|
<description>TWI Slave Mode Disabled</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>QUICK</name>
|
|
<description>SMBus Quick Command</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMR</name>
|
|
<description>Master Mode Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IADRSZ</name>
|
|
<description>Internal Device Address Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No internal device address</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_BYTE</name>
|
|
<description>One-byte internal device address</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_BYTE</name>
|
|
<description>Two-byte internal device address</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_BYTE</name>
|
|
<description>Three-byte internal device address</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MREAD</name>
|
|
<description>Master Read Direction</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DADR</name>
|
|
<description>Device Address</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMR</name>
|
|
<description>Slave Mode Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SADR</name>
|
|
<description>Slave Address</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IADR</name>
|
|
<description>Internal Address Register</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IADR</name>
|
|
<description>Internal Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CWGR</name>
|
|
<description>Clock Waveform Generator Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLDIV</name>
|
|
<description>Clock Low Divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHDIV</name>
|
|
<description>Clock High Divider</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKDIV</name>
|
|
<description>Clock Divider</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000F009</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOMP</name>
|
|
<description>Transmission Completed (cleared by writing TWI_THR)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receive Holding Register Ready (cleared by reading TWI_RHR)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Holding Register Ready (cleared by writing TWI_THR)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SVREAD</name>
|
|
<description>Slave Read</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SVACC</name>
|
|
<description>Slave Access</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GACC</name>
|
|
<description>General Call Access (cleared on read)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error (cleared on read)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Not Acknowledged (cleared on read)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBLST</name>
|
|
<description>Arbitration Lost (cleared on read)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCLWS</name>
|
|
<description>Clock Wait State</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOSACC</name>
|
|
<description>End Of Slave Access (cleared on read)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of RX buffer (cleared by writing TWI_RCR or TWI_RNCR)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of TX buffer (cleared by writing TWI_TCR or TWI_TNCR)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>RX Buffer Full (cleared by writing TWI_RCR or TWI_RNCR)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>TX Buffer Empty (cleared by writing TWI_TCR or TWI_TNCR)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOMP</name>
|
|
<description>Transmission Completed Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receive Holding Register Ready Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Holding Register Ready Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SVACC</name>
|
|
<description>Slave Access Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GACC</name>
|
|
<description>General Call Access Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Not Acknowledge Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBLST</name>
|
|
<description>Arbitration Lost Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCL_WS</name>
|
|
<description>Clock Wait State Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOSACC</name>
|
|
<description>End Of Slave Access Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOMP</name>
|
|
<description>Transmission Completed Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receive Holding Register Ready Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Holding Register Ready Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SVACC</name>
|
|
<description>Slave Access Interrupt Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GACC</name>
|
|
<description>General Call Access Interrupt Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Not Acknowledge Interrupt Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBLST</name>
|
|
<description>Arbitration Lost Interrupt Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCL_WS</name>
|
|
<description>Clock Wait State Interrupt Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOSACC</name>
|
|
<description>End Of Slave Access Interrupt Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOMP</name>
|
|
<description>Transmission Completed Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receive Holding Register Ready Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Holding Register Ready Interrupt Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SVACC</name>
|
|
<description>Slave Access Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GACC</name>
|
|
<description>General Call Access Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Not Acknowledge Interrupt Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBLST</name>
|
|
<description>Arbitration Lost Interrupt Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCL_WS</name>
|
|
<description>Clock Wait State Interrupt Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOSACC</name>
|
|
<description>End Of Slave Access Interrupt Mask</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Mask</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Mask</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Mask</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Mask</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RHR</name>
|
|
<description>Receive Holding Register</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>Master or Slave Receive Holding Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR</name>
|
|
<description>Transmit Holding Register</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>Master or Slave Transmit Holding Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RPR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXPTR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<description>Receive Counter Register</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCTR</name>
|
|
<description>Receive Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPR</name>
|
|
<description>Transmit Pointer Register</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXPTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<addressOffset>0x0000010C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNPR</name>
|
|
<description>Receive Next Pointer Register</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNPTR</name>
|
|
<description>Receive Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNCR</name>
|
|
<description>Receive Next Counter Register</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNCTR</name>
|
|
<description>Receive Next Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNPR</name>
|
|
<description>Transmit Next Pointer Register</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNPTR</name>
|
|
<description>Transmit Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNCR</name>
|
|
<description>Transmit Next Counter Register</description>
|
|
<addressOffset>0x0000011C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNCTR</name>
|
|
<description>Transmit Counter Next</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTCR</name>
|
|
<description>Transfer Control Register</description>
|
|
<addressOffset>0x00000120</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXTDIS</name>
|
|
<description>Receiver Transfer Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTDIS</name>
|
|
<description>Transmitter Transfer Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTSR</name>
|
|
<description>Transfer Status Register</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TWI1</name>
|
|
<version>6212Z</version>
|
|
<description>Two-wire Interface 1</description>
|
|
<groupName>TWI</groupName>
|
|
<prependToName>TWI1_</prependToName>
|
|
<baseAddress>0x4001C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TWI1</name>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Send a START Condition</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Send a STOP Condition</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MSEN</name>
|
|
<description>TWI Master Mode Enabled</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MSDIS</name>
|
|
<description>TWI Master Mode Disabled</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SVEN</name>
|
|
<description>TWI Slave Mode Enabled</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SVDIS</name>
|
|
<description>TWI Slave Mode Disabled</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>QUICK</name>
|
|
<description>SMBus Quick Command</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMR</name>
|
|
<description>Master Mode Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IADRSZ</name>
|
|
<description>Internal Device Address Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No internal device address</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_BYTE</name>
|
|
<description>One-byte internal device address</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_BYTE</name>
|
|
<description>Two-byte internal device address</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_BYTE</name>
|
|
<description>Three-byte internal device address</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MREAD</name>
|
|
<description>Master Read Direction</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DADR</name>
|
|
<description>Device Address</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMR</name>
|
|
<description>Slave Mode Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SADR</name>
|
|
<description>Slave Address</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IADR</name>
|
|
<description>Internal Address Register</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IADR</name>
|
|
<description>Internal Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CWGR</name>
|
|
<description>Clock Waveform Generator Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLDIV</name>
|
|
<description>Clock Low Divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHDIV</name>
|
|
<description>Clock High Divider</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKDIV</name>
|
|
<description>Clock Divider</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000F009</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOMP</name>
|
|
<description>Transmission Completed (cleared by writing TWI_THR)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receive Holding Register Ready (cleared by reading TWI_RHR)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Holding Register Ready (cleared by writing TWI_THR)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SVREAD</name>
|
|
<description>Slave Read</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SVACC</name>
|
|
<description>Slave Access</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GACC</name>
|
|
<description>General Call Access (cleared on read)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error (cleared on read)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Not Acknowledged (cleared on read)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBLST</name>
|
|
<description>Arbitration Lost (cleared on read)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCLWS</name>
|
|
<description>Clock Wait State</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOSACC</name>
|
|
<description>End Of Slave Access (cleared on read)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of RX buffer (cleared by writing TWI_RCR or TWI_RNCR)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of TX buffer (cleared by writing TWI_TCR or TWI_TNCR)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>RX Buffer Full (cleared by writing TWI_RCR or TWI_RNCR)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>TX Buffer Empty (cleared by writing TWI_TCR or TWI_TNCR)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOMP</name>
|
|
<description>Transmission Completed Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receive Holding Register Ready Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Holding Register Ready Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SVACC</name>
|
|
<description>Slave Access Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GACC</name>
|
|
<description>General Call Access Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Not Acknowledge Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBLST</name>
|
|
<description>Arbitration Lost Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCL_WS</name>
|
|
<description>Clock Wait State Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOSACC</name>
|
|
<description>End Of Slave Access Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOMP</name>
|
|
<description>Transmission Completed Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receive Holding Register Ready Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Holding Register Ready Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SVACC</name>
|
|
<description>Slave Access Interrupt Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GACC</name>
|
|
<description>General Call Access Interrupt Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Not Acknowledge Interrupt Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBLST</name>
|
|
<description>Arbitration Lost Interrupt Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCL_WS</name>
|
|
<description>Clock Wait State Interrupt Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOSACC</name>
|
|
<description>End Of Slave Access Interrupt Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOMP</name>
|
|
<description>Transmission Completed Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receive Holding Register Ready Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Holding Register Ready Interrupt Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SVACC</name>
|
|
<description>Slave Access Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GACC</name>
|
|
<description>General Call Access Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Not Acknowledge Interrupt Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBLST</name>
|
|
<description>Arbitration Lost Interrupt Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCL_WS</name>
|
|
<description>Clock Wait State Interrupt Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOSACC</name>
|
|
<description>End Of Slave Access Interrupt Mask</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Mask</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Mask</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Mask</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Mask</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RHR</name>
|
|
<description>Receive Holding Register</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>Master or Slave Receive Holding Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR</name>
|
|
<description>Transmit Holding Register</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>Master or Slave Transmit Holding Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RPR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXPTR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<description>Receive Counter Register</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCTR</name>
|
|
<description>Receive Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPR</name>
|
|
<description>Transmit Pointer Register</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXPTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<addressOffset>0x0000010C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNPR</name>
|
|
<description>Receive Next Pointer Register</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNPTR</name>
|
|
<description>Receive Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNCR</name>
|
|
<description>Receive Next Counter Register</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNCTR</name>
|
|
<description>Receive Next Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNPR</name>
|
|
<description>Transmit Next Pointer Register</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNPTR</name>
|
|
<description>Transmit Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNCR</name>
|
|
<description>Transmit Next Counter Register</description>
|
|
<addressOffset>0x0000011C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNCTR</name>
|
|
<description>Transmit Counter Next</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTCR</name>
|
|
<description>Transfer Control Register</description>
|
|
<addressOffset>0x00000120</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXTDIS</name>
|
|
<description>Receiver Transfer Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTDIS</name>
|
|
<description>Transmitter Transfer Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTSR</name>
|
|
<description>Transfer Status Register</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PWM</name>
|
|
<version>6343T</version>
|
|
<description>Pulse Width Modulation Controller</description>
|
|
<prependToName>PWM_</prependToName>
|
|
<baseAddress>0x40020000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PWM</name>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CLK</name>
|
|
<description>PWM Clock Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIVA</name>
|
|
<description>CLKA Divide Factor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKA_POFF</name>
|
|
<description>CLKA clock is turned off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PREA</name>
|
|
<description>CLKA clock is clock selected by PREA</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PREA</name>
|
|
<description>CLKA Source Clock Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLK</name>
|
|
<description>Peripheral clock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV2</name>
|
|
<description>Peripheral clock/2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV4</name>
|
|
<description>Peripheral clock/4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV8</name>
|
|
<description>Peripheral clock/8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV16</name>
|
|
<description>Peripheral clock/16</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV32</name>
|
|
<description>Peripheral clock/32</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV64</name>
|
|
<description>Peripheral clock/64</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV128</name>
|
|
<description>Peripheral clock/128</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV256</name>
|
|
<description>Peripheral clock/256</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV512</name>
|
|
<description>Peripheral clock/512</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV1024</name>
|
|
<description>Peripheral clock/1024</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIVB</name>
|
|
<description>CLKB Divide Factor</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKB_POFF</name>
|
|
<description>CLKB clock is turned off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PREB</name>
|
|
<description>CLKB clock is clock selected by PREB</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PREB</name>
|
|
<description>CLKB Source Clock Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLK</name>
|
|
<description>Peripheral clock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV2</name>
|
|
<description>Peripheral clock/2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV4</name>
|
|
<description>Peripheral clock/4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV8</name>
|
|
<description>Peripheral clock/8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV16</name>
|
|
<description>Peripheral clock/16</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV32</name>
|
|
<description>Peripheral clock/32</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV64</name>
|
|
<description>Peripheral clock/64</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV128</name>
|
|
<description>Peripheral clock/128</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV256</name>
|
|
<description>Peripheral clock/256</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV512</name>
|
|
<description>Peripheral clock/512</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_DIV1024</name>
|
|
<description>Peripheral clock/1024</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENA</name>
|
|
<description>PWM Enable Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CHID0</name>
|
|
<description>Channel ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID1</name>
|
|
<description>Channel ID</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID2</name>
|
|
<description>Channel ID</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID3</name>
|
|
<description>Channel ID</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIS</name>
|
|
<description>PWM Disable Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CHID0</name>
|
|
<description>Channel ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID1</name>
|
|
<description>Channel ID</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID2</name>
|
|
<description>Channel ID</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID3</name>
|
|
<description>Channel ID</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>PWM Status Register</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHID0</name>
|
|
<description>Channel ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID1</name>
|
|
<description>Channel ID</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID2</name>
|
|
<description>Channel ID</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID3</name>
|
|
<description>Channel ID</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER1</name>
|
|
<description>PWM Interrupt Enable Register 1</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CHID0</name>
|
|
<description>Counter Event on Channel 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID1</name>
|
|
<description>Counter Event on Channel 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID2</name>
|
|
<description>Counter Event on Channel 2 Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID3</name>
|
|
<description>Counter Event on Channel 3 Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCHID0</name>
|
|
<description>Fault Protection Trigger on Channel 0 Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCHID1</name>
|
|
<description>Fault Protection Trigger on Channel 1 Interrupt Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCHID2</name>
|
|
<description>Fault Protection Trigger on Channel 2 Interrupt Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCHID3</name>
|
|
<description>Fault Protection Trigger on Channel 3 Interrupt Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR1</name>
|
|
<description>PWM Interrupt Disable Register 1</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CHID0</name>
|
|
<description>Counter Event on Channel 0 Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID1</name>
|
|
<description>Counter Event on Channel 1 Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID2</name>
|
|
<description>Counter Event on Channel 2 Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID3</name>
|
|
<description>Counter Event on Channel 3 Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCHID0</name>
|
|
<description>Fault Protection Trigger on Channel 0 Interrupt Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCHID1</name>
|
|
<description>Fault Protection Trigger on Channel 1 Interrupt Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCHID2</name>
|
|
<description>Fault Protection Trigger on Channel 2 Interrupt Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCHID3</name>
|
|
<description>Fault Protection Trigger on Channel 3 Interrupt Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR1</name>
|
|
<description>PWM Interrupt Mask Register 1</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHID0</name>
|
|
<description>Counter Event on Channel 0 Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID1</name>
|
|
<description>Counter Event on Channel 1 Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID2</name>
|
|
<description>Counter Event on Channel 2 Interrupt Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID3</name>
|
|
<description>Counter Event on Channel 3 Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCHID0</name>
|
|
<description>Fault Protection Trigger on Channel 0 Interrupt Mask</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCHID1</name>
|
|
<description>Fault Protection Trigger on Channel 1 Interrupt Mask</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCHID2</name>
|
|
<description>Fault Protection Trigger on Channel 2 Interrupt Mask</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCHID3</name>
|
|
<description>Fault Protection Trigger on Channel 3 Interrupt Mask</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR1</name>
|
|
<description>PWM Interrupt Status Register 1</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHID0</name>
|
|
<description>Counter Event on Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID1</name>
|
|
<description>Counter Event on Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID2</name>
|
|
<description>Counter Event on Channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHID3</name>
|
|
<description>Counter Event on Channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCHID0</name>
|
|
<description>Fault Protection Trigger on Channel 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCHID1</name>
|
|
<description>Fault Protection Trigger on Channel 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCHID2</name>
|
|
<description>Fault Protection Trigger on Channel 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCHID3</name>
|
|
<description>Fault Protection Trigger on Channel 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCM</name>
|
|
<description>PWM Sync Channels Mode Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SYNC0</name>
|
|
<description>Synchronous Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SYNC1</name>
|
|
<description>Synchronous Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SYNC2</name>
|
|
<description>Synchronous Channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SYNC3</name>
|
|
<description>Synchronous Channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UPDM</name>
|
|
<description>Synchronous Channels Update Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODE0</name>
|
|
<description>Manual write of double buffer registers and manual update of synchronous channels</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE1</name>
|
|
<description>Manual write of double buffer registers and automatic update of synchronous channels</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE2</name>
|
|
<description>Automatic write of duty-cycle update registers by the Peripheral DMA Controller and automatic update of synchronous channels</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTRM</name>
|
|
<description>Peripheral DMA Controller Transfer Request Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PTRCS</name>
|
|
<description>Peripheral DMA Controller Transfer Request Comparison Selection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCUC</name>
|
|
<description>PWM Sync Channels Update Control Register</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDULOCK</name>
|
|
<description>Synchronous Channels Update Unlock</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCUP</name>
|
|
<description>PWM Sync Channels Update Period Register</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPR</name>
|
|
<description>Update Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UPRCNT</name>
|
|
<description>Update Period Counter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCUPUPD</name>
|
|
<description>PWM Sync Channels Update Period Update Register</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>UPRUPD</name>
|
|
<description>Update Period Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER2</name>
|
|
<description>PWM Interrupt Enable Register 2</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>WRDY</name>
|
|
<description>Write Ready for Synchronous Channels Update Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>PDC End of TX Buffer Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>PDC TX Buffer Empty Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNRE</name>
|
|
<description>Synchronous Channels Update Underrun Error Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM0</name>
|
|
<description>Comparison 0 Match Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM1</name>
|
|
<description>Comparison 1 Match Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM2</name>
|
|
<description>Comparison 2 Match Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM3</name>
|
|
<description>Comparison 3 Match Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM4</name>
|
|
<description>Comparison 4 Match Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM5</name>
|
|
<description>Comparison 5 Match Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM6</name>
|
|
<description>Comparison 6 Match Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM7</name>
|
|
<description>Comparison 7 Match Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU0</name>
|
|
<description>Comparison 0 Update Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU1</name>
|
|
<description>Comparison 1 Update Interrupt Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU2</name>
|
|
<description>Comparison 2 Update Interrupt Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU3</name>
|
|
<description>Comparison 3 Update Interrupt Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU4</name>
|
|
<description>Comparison 4 Update Interrupt Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU5</name>
|
|
<description>Comparison 5 Update Interrupt Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU6</name>
|
|
<description>Comparison 6 Update Interrupt Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU7</name>
|
|
<description>Comparison 7 Update Interrupt Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR2</name>
|
|
<description>PWM Interrupt Disable Register 2</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>WRDY</name>
|
|
<description>Write Ready for Synchronous Channels Update Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>PDC End of TX Buffer Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>PDC TX Buffer Empty Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNRE</name>
|
|
<description>Synchronous Channels Update Underrun Error Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM0</name>
|
|
<description>Comparison 0 Match Interrupt Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM1</name>
|
|
<description>Comparison 1 Match Interrupt Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM2</name>
|
|
<description>Comparison 2 Match Interrupt Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM3</name>
|
|
<description>Comparison 3 Match Interrupt Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM4</name>
|
|
<description>Comparison 4 Match Interrupt Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM5</name>
|
|
<description>Comparison 5 Match Interrupt Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM6</name>
|
|
<description>Comparison 6 Match Interrupt Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM7</name>
|
|
<description>Comparison 7 Match Interrupt Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU0</name>
|
|
<description>Comparison 0 Update Interrupt Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU1</name>
|
|
<description>Comparison 1 Update Interrupt Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU2</name>
|
|
<description>Comparison 2 Update Interrupt Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU3</name>
|
|
<description>Comparison 3 Update Interrupt Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU4</name>
|
|
<description>Comparison 4 Update Interrupt Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU5</name>
|
|
<description>Comparison 5 Update Interrupt Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU6</name>
|
|
<description>Comparison 6 Update Interrupt Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU7</name>
|
|
<description>Comparison 7 Update Interrupt Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR2</name>
|
|
<description>PWM Interrupt Mask Register 2</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WRDY</name>
|
|
<description>Write Ready for Synchronous Channels Update Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>PDC End of TX Buffer Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>PDC TX Buffer Empty Interrupt Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNRE</name>
|
|
<description>Synchronous Channels Update Underrun Error Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM0</name>
|
|
<description>Comparison 0 Match Interrupt Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM1</name>
|
|
<description>Comparison 1 Match Interrupt Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM2</name>
|
|
<description>Comparison 2 Match Interrupt Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM3</name>
|
|
<description>Comparison 3 Match Interrupt Mask</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM4</name>
|
|
<description>Comparison 4 Match Interrupt Mask</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM5</name>
|
|
<description>Comparison 5 Match Interrupt Mask</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM6</name>
|
|
<description>Comparison 6 Match Interrupt Mask</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM7</name>
|
|
<description>Comparison 7 Match Interrupt Mask</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU0</name>
|
|
<description>Comparison 0 Update Interrupt Mask</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU1</name>
|
|
<description>Comparison 1 Update Interrupt Mask</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU2</name>
|
|
<description>Comparison 2 Update Interrupt Mask</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU3</name>
|
|
<description>Comparison 3 Update Interrupt Mask</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU4</name>
|
|
<description>Comparison 4 Update Interrupt Mask</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU5</name>
|
|
<description>Comparison 5 Update Interrupt Mask</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU6</name>
|
|
<description>Comparison 6 Update Interrupt Mask</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU7</name>
|
|
<description>Comparison 7 Update Interrupt Mask</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR2</name>
|
|
<description>PWM Interrupt Status Register 2</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WRDY</name>
|
|
<description>Write Ready for Synchronous Channels Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>PDC End of TX Buffer</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>PDC TX Buffer Empty</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNRE</name>
|
|
<description>Synchronous Channels Update Underrun Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM0</name>
|
|
<description>Comparison 0 Match</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM1</name>
|
|
<description>Comparison 1 Match</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM2</name>
|
|
<description>Comparison 2 Match</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM3</name>
|
|
<description>Comparison 3 Match</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM4</name>
|
|
<description>Comparison 4 Match</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM5</name>
|
|
<description>Comparison 5 Match</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM6</name>
|
|
<description>Comparison 6 Match</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPM7</name>
|
|
<description>Comparison 7 Match</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU0</name>
|
|
<description>Comparison 0 Update</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU1</name>
|
|
<description>Comparison 1 Update</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU2</name>
|
|
<description>Comparison 2 Update</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU3</name>
|
|
<description>Comparison 3 Update</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU4</name>
|
|
<description>Comparison 4 Update</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU5</name>
|
|
<description>Comparison 5 Update</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU6</name>
|
|
<description>Comparison 6 Update</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPU7</name>
|
|
<description>Comparison 7 Update</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OOV</name>
|
|
<description>PWM Output Override Value Register</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OOVH0</name>
|
|
<description>Output Override Value for PWMH output of the channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OOVH1</name>
|
|
<description>Output Override Value for PWMH output of the channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OOVH2</name>
|
|
<description>Output Override Value for PWMH output of the channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OOVH3</name>
|
|
<description>Output Override Value for PWMH output of the channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OOVL0</name>
|
|
<description>Output Override Value for PWML output of the channel 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OOVL1</name>
|
|
<description>Output Override Value for PWML output of the channel 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OOVL2</name>
|
|
<description>Output Override Value for PWML output of the channel 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OOVL3</name>
|
|
<description>Output Override Value for PWML output of the channel 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OS</name>
|
|
<description>PWM Output Selection Register</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OSH0</name>
|
|
<description>Output Selection for PWMH output of the channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSH1</name>
|
|
<description>Output Selection for PWMH output of the channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSH2</name>
|
|
<description>Output Selection for PWMH output of the channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSH3</name>
|
|
<description>Output Selection for PWMH output of the channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSL0</name>
|
|
<description>Output Selection for PWML output of the channel 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSL1</name>
|
|
<description>Output Selection for PWML output of the channel 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSL2</name>
|
|
<description>Output Selection for PWML output of the channel 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSL3</name>
|
|
<description>Output Selection for PWML output of the channel 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSS</name>
|
|
<description>PWM Output Selection Set Register</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>OSSH0</name>
|
|
<description>Output Selection Set for PWMH output of the channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSH1</name>
|
|
<description>Output Selection Set for PWMH output of the channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSH2</name>
|
|
<description>Output Selection Set for PWMH output of the channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSH3</name>
|
|
<description>Output Selection Set for PWMH output of the channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSL0</name>
|
|
<description>Output Selection Set for PWML output of the channel 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSL1</name>
|
|
<description>Output Selection Set for PWML output of the channel 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSL2</name>
|
|
<description>Output Selection Set for PWML output of the channel 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSL3</name>
|
|
<description>Output Selection Set for PWML output of the channel 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSC</name>
|
|
<description>PWM Output Selection Clear Register</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>OSCH0</name>
|
|
<description>Output Selection Clear for PWMH output of the channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSCH1</name>
|
|
<description>Output Selection Clear for PWMH output of the channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSCH2</name>
|
|
<description>Output Selection Clear for PWMH output of the channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSCH3</name>
|
|
<description>Output Selection Clear for PWMH output of the channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSCL0</name>
|
|
<description>Output Selection Clear for PWML output of the channel 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSCL1</name>
|
|
<description>Output Selection Clear for PWML output of the channel 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSCL2</name>
|
|
<description>Output Selection Clear for PWML output of the channel 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSCL3</name>
|
|
<description>Output Selection Clear for PWML output of the channel 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSSUPD</name>
|
|
<description>PWM Output Selection Set Update Register</description>
|
|
<addressOffset>0x00000054</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>OSSUPH0</name>
|
|
<description>Output Selection Set for PWMH output of the channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSUPH1</name>
|
|
<description>Output Selection Set for PWMH output of the channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSUPH2</name>
|
|
<description>Output Selection Set for PWMH output of the channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSUPH3</name>
|
|
<description>Output Selection Set for PWMH output of the channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSUPL0</name>
|
|
<description>Output Selection Set for PWML output of the channel 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSUPL1</name>
|
|
<description>Output Selection Set for PWML output of the channel 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSUPL2</name>
|
|
<description>Output Selection Set for PWML output of the channel 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSUPL3</name>
|
|
<description>Output Selection Set for PWML output of the channel 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSCUPD</name>
|
|
<description>PWM Output Selection Clear Update Register</description>
|
|
<addressOffset>0x00000058</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>OSCUPH0</name>
|
|
<description>Output Selection Clear for PWMH output of the channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSCUPH1</name>
|
|
<description>Output Selection Clear for PWMH output of the channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSCUPH2</name>
|
|
<description>Output Selection Clear for PWMH output of the channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSCUPH3</name>
|
|
<description>Output Selection Clear for PWMH output of the channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSCUPL0</name>
|
|
<description>Output Selection Clear for PWML output of the channel 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSCUPL1</name>
|
|
<description>Output Selection Clear for PWML output of the channel 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSCUPL2</name>
|
|
<description>Output Selection Clear for PWML output of the channel 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSCUPL3</name>
|
|
<description>Output Selection Clear for PWML output of the channel 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMR</name>
|
|
<description>PWM Fault Mode Register</description>
|
|
<addressOffset>0x0000005C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FPOL</name>
|
|
<description>Fault Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FMOD</name>
|
|
<description>Fault Activation Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FFIL</name>
|
|
<description>Fault Filtering</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSR</name>
|
|
<description>PWM Fault Status Register</description>
|
|
<addressOffset>0x00000060</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FIV</name>
|
|
<description>Fault Input Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FS</name>
|
|
<description>Fault Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCR</name>
|
|
<description>PWM Fault Clear Register</description>
|
|
<addressOffset>0x00000064</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>FCLR</name>
|
|
<description>Fault Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FPV</name>
|
|
<description>PWM Fault Protection Value Register</description>
|
|
<addressOffset>0x00000068</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FPVH0</name>
|
|
<description>Fault Protection Value for PWMH output on channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FPVH1</name>
|
|
<description>Fault Protection Value for PWMH output on channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FPVH2</name>
|
|
<description>Fault Protection Value for PWMH output on channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FPVH3</name>
|
|
<description>Fault Protection Value for PWMH output on channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FPVL0</name>
|
|
<description>Fault Protection Value for PWML output on channel 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FPVL1</name>
|
|
<description>Fault Protection Value for PWML output on channel 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FPVL2</name>
|
|
<description>Fault Protection Value for PWML output on channel 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FPVL3</name>
|
|
<description>Fault Protection Value for PWML output on channel 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FPE</name>
|
|
<description>PWM Fault Protection Enable Register</description>
|
|
<addressOffset>0x0000006C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FPE0</name>
|
|
<description>Fault Protection Enable for channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FPE1</name>
|
|
<description>Fault Protection Enable for channel 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FPE2</name>
|
|
<description>Fault Protection Enable for channel 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FPE3</name>
|
|
<description>Fault Protection Enable for channel 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>ELMR[%s]</name>
|
|
<description>PWM Event Line 0 Mode Register</description>
|
|
<addressOffset>0x0000007C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>CSEL0</name>
|
|
<description>Comparison 0 Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL1</name>
|
|
<description>Comparison 1 Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL2</name>
|
|
<description>Comparison 2 Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL3</name>
|
|
<description>Comparison 3 Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL4</name>
|
|
<description>Comparison 4 Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL5</name>
|
|
<description>Comparison 5 Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL6</name>
|
|
<description>Comparison 6 Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL7</name>
|
|
<description>Comparison 7 Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMMR</name>
|
|
<description>PWM Stepper Motor Mode Register</description>
|
|
<addressOffset>0x000000B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GCEN0</name>
|
|
<description>Gray Count ENable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GCEN1</name>
|
|
<description>Gray Count ENable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DOWN0</name>
|
|
<description>DOWN Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DOWN1</name>
|
|
<description>DOWN Count</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPCR</name>
|
|
<description>PWM Write Protection Control Register</description>
|
|
<addressOffset>0x000000E4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>WPCMD</name>
|
|
<description>Write Protection Command</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SW_PROT</name>
|
|
<description>Disables the software write protection of the register groups of which the bit WPRGx is at '1'.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SW_PROT</name>
|
|
<description>Enables the software write protection of the register groups of which the bit WPRGx is at '1'.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_HW_PROT</name>
|
|
<description>Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WPRG0</name>
|
|
<description>Write Protection Register Group 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPRG1</name>
|
|
<description>Write Protection Register Group 1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPRG2</name>
|
|
<description>Write Protection Register Group 2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPRG3</name>
|
|
<description>Write Protection Register Group 3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPRG4</name>
|
|
<description>Write Protection Register Group 4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPRG5</name>
|
|
<description>Write Protection Register Group 5</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPKEY</name>
|
|
<description>Write Protection Key</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0</description>
|
|
<value>0x50574D</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPSR</name>
|
|
<description>PWM Write Protection Status Register</description>
|
|
<addressOffset>0x000000E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPSWS0</name>
|
|
<description>Write Protect SW Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPSWS1</name>
|
|
<description>Write Protect SW Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPSWS2</name>
|
|
<description>Write Protect SW Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPSWS3</name>
|
|
<description>Write Protect SW Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPSWS4</name>
|
|
<description>Write Protect SW Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPSWS5</name>
|
|
<description>Write Protect SW Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPVS</name>
|
|
<description>Write Protect Violation Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPHWS0</name>
|
|
<description>Write Protect HW Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPHWS1</name>
|
|
<description>Write Protect HW Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPHWS2</name>
|
|
<description>Write Protect HW Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPHWS3</name>
|
|
<description>Write Protect HW Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPHWS4</name>
|
|
<description>Write Protect HW Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPHWS5</name>
|
|
<description>Write Protect HW Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPVSRC</name>
|
|
<description>Write Protect Violation Source</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPV0</name>
|
|
<description>PWM Comparison 0 Value Register</description>
|
|
<addressOffset>0x00000130</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CV</name>
|
|
<description>Comparison x Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CVM</name>
|
|
<description>Comparison x Value Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPVUPD0</name>
|
|
<description>PWM Comparison 0 Value Update Register</description>
|
|
<addressOffset>0x00000134</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CVUPD</name>
|
|
<description>Comparison x Value Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CVMUPD</name>
|
|
<description>Comparison x Value Mode Update</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPM0</name>
|
|
<description>PWM Comparison 0 Mode Register</description>
|
|
<addressOffset>0x00000138</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Comparison x Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTR</name>
|
|
<description>Comparison x Trigger</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPR</name>
|
|
<description>Comparison x Period</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPRCNT</name>
|
|
<description>Comparison x Period Counter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPR</name>
|
|
<description>Comparison x Update Period</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPRCNT</name>
|
|
<description>Comparison x Update Period Counter</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPMUPD0</name>
|
|
<description>PWM Comparison 0 Mode Update Register</description>
|
|
<addressOffset>0x0000013C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CENUPD</name>
|
|
<description>Comparison x Enable Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTRUPD</name>
|
|
<description>Comparison x Trigger Update</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPRUPD</name>
|
|
<description>Comparison x Period Update</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPRUPD</name>
|
|
<description>Comparison x Update Period Update</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPV1</name>
|
|
<description>PWM Comparison 1 Value Register</description>
|
|
<addressOffset>0x00000140</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CV</name>
|
|
<description>Comparison x Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CVM</name>
|
|
<description>Comparison x Value Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPVUPD1</name>
|
|
<description>PWM Comparison 1 Value Update Register</description>
|
|
<addressOffset>0x00000144</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CVUPD</name>
|
|
<description>Comparison x Value Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CVMUPD</name>
|
|
<description>Comparison x Value Mode Update</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPM1</name>
|
|
<description>PWM Comparison 1 Mode Register</description>
|
|
<addressOffset>0x00000148</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Comparison x Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTR</name>
|
|
<description>Comparison x Trigger</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPR</name>
|
|
<description>Comparison x Period</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPRCNT</name>
|
|
<description>Comparison x Period Counter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPR</name>
|
|
<description>Comparison x Update Period</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPRCNT</name>
|
|
<description>Comparison x Update Period Counter</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPMUPD1</name>
|
|
<description>PWM Comparison 1 Mode Update Register</description>
|
|
<addressOffset>0x0000014C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CENUPD</name>
|
|
<description>Comparison x Enable Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTRUPD</name>
|
|
<description>Comparison x Trigger Update</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPRUPD</name>
|
|
<description>Comparison x Period Update</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPRUPD</name>
|
|
<description>Comparison x Update Period Update</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPV2</name>
|
|
<description>PWM Comparison 2 Value Register</description>
|
|
<addressOffset>0x00000150</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CV</name>
|
|
<description>Comparison x Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CVM</name>
|
|
<description>Comparison x Value Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPVUPD2</name>
|
|
<description>PWM Comparison 2 Value Update Register</description>
|
|
<addressOffset>0x00000154</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CVUPD</name>
|
|
<description>Comparison x Value Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CVMUPD</name>
|
|
<description>Comparison x Value Mode Update</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPM2</name>
|
|
<description>PWM Comparison 2 Mode Register</description>
|
|
<addressOffset>0x00000158</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Comparison x Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTR</name>
|
|
<description>Comparison x Trigger</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPR</name>
|
|
<description>Comparison x Period</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPRCNT</name>
|
|
<description>Comparison x Period Counter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPR</name>
|
|
<description>Comparison x Update Period</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPRCNT</name>
|
|
<description>Comparison x Update Period Counter</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPMUPD2</name>
|
|
<description>PWM Comparison 2 Mode Update Register</description>
|
|
<addressOffset>0x0000015C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CENUPD</name>
|
|
<description>Comparison x Enable Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTRUPD</name>
|
|
<description>Comparison x Trigger Update</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPRUPD</name>
|
|
<description>Comparison x Period Update</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPRUPD</name>
|
|
<description>Comparison x Update Period Update</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPV3</name>
|
|
<description>PWM Comparison 3 Value Register</description>
|
|
<addressOffset>0x00000160</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CV</name>
|
|
<description>Comparison x Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CVM</name>
|
|
<description>Comparison x Value Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPVUPD3</name>
|
|
<description>PWM Comparison 3 Value Update Register</description>
|
|
<addressOffset>0x00000164</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CVUPD</name>
|
|
<description>Comparison x Value Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CVMUPD</name>
|
|
<description>Comparison x Value Mode Update</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPM3</name>
|
|
<description>PWM Comparison 3 Mode Register</description>
|
|
<addressOffset>0x00000168</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Comparison x Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTR</name>
|
|
<description>Comparison x Trigger</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPR</name>
|
|
<description>Comparison x Period</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPRCNT</name>
|
|
<description>Comparison x Period Counter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPR</name>
|
|
<description>Comparison x Update Period</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPRCNT</name>
|
|
<description>Comparison x Update Period Counter</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPMUPD3</name>
|
|
<description>PWM Comparison 3 Mode Update Register</description>
|
|
<addressOffset>0x0000016C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CENUPD</name>
|
|
<description>Comparison x Enable Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTRUPD</name>
|
|
<description>Comparison x Trigger Update</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPRUPD</name>
|
|
<description>Comparison x Period Update</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPRUPD</name>
|
|
<description>Comparison x Update Period Update</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPV4</name>
|
|
<description>PWM Comparison 4 Value Register</description>
|
|
<addressOffset>0x00000170</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CV</name>
|
|
<description>Comparison x Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CVM</name>
|
|
<description>Comparison x Value Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPVUPD4</name>
|
|
<description>PWM Comparison 4 Value Update Register</description>
|
|
<addressOffset>0x00000174</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CVUPD</name>
|
|
<description>Comparison x Value Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CVMUPD</name>
|
|
<description>Comparison x Value Mode Update</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPM4</name>
|
|
<description>PWM Comparison 4 Mode Register</description>
|
|
<addressOffset>0x00000178</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Comparison x Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTR</name>
|
|
<description>Comparison x Trigger</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPR</name>
|
|
<description>Comparison x Period</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPRCNT</name>
|
|
<description>Comparison x Period Counter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPR</name>
|
|
<description>Comparison x Update Period</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPRCNT</name>
|
|
<description>Comparison x Update Period Counter</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPMUPD4</name>
|
|
<description>PWM Comparison 4 Mode Update Register</description>
|
|
<addressOffset>0x0000017C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CENUPD</name>
|
|
<description>Comparison x Enable Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTRUPD</name>
|
|
<description>Comparison x Trigger Update</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPRUPD</name>
|
|
<description>Comparison x Period Update</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPRUPD</name>
|
|
<description>Comparison x Update Period Update</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPV5</name>
|
|
<description>PWM Comparison 5 Value Register</description>
|
|
<addressOffset>0x00000180</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CV</name>
|
|
<description>Comparison x Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CVM</name>
|
|
<description>Comparison x Value Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPVUPD5</name>
|
|
<description>PWM Comparison 5 Value Update Register</description>
|
|
<addressOffset>0x00000184</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CVUPD</name>
|
|
<description>Comparison x Value Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CVMUPD</name>
|
|
<description>Comparison x Value Mode Update</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPM5</name>
|
|
<description>PWM Comparison 5 Mode Register</description>
|
|
<addressOffset>0x00000188</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Comparison x Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTR</name>
|
|
<description>Comparison x Trigger</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPR</name>
|
|
<description>Comparison x Period</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPRCNT</name>
|
|
<description>Comparison x Period Counter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPR</name>
|
|
<description>Comparison x Update Period</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPRCNT</name>
|
|
<description>Comparison x Update Period Counter</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPMUPD5</name>
|
|
<description>PWM Comparison 5 Mode Update Register</description>
|
|
<addressOffset>0x0000018C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CENUPD</name>
|
|
<description>Comparison x Enable Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTRUPD</name>
|
|
<description>Comparison x Trigger Update</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPRUPD</name>
|
|
<description>Comparison x Period Update</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPRUPD</name>
|
|
<description>Comparison x Update Period Update</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPV6</name>
|
|
<description>PWM Comparison 6 Value Register</description>
|
|
<addressOffset>0x00000190</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CV</name>
|
|
<description>Comparison x Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CVM</name>
|
|
<description>Comparison x Value Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPVUPD6</name>
|
|
<description>PWM Comparison 6 Value Update Register</description>
|
|
<addressOffset>0x00000194</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CVUPD</name>
|
|
<description>Comparison x Value Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CVMUPD</name>
|
|
<description>Comparison x Value Mode Update</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPM6</name>
|
|
<description>PWM Comparison 6 Mode Register</description>
|
|
<addressOffset>0x00000198</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Comparison x Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTR</name>
|
|
<description>Comparison x Trigger</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPR</name>
|
|
<description>Comparison x Period</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPRCNT</name>
|
|
<description>Comparison x Period Counter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPR</name>
|
|
<description>Comparison x Update Period</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPRCNT</name>
|
|
<description>Comparison x Update Period Counter</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPMUPD6</name>
|
|
<description>PWM Comparison 6 Mode Update Register</description>
|
|
<addressOffset>0x0000019C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CENUPD</name>
|
|
<description>Comparison x Enable Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTRUPD</name>
|
|
<description>Comparison x Trigger Update</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPRUPD</name>
|
|
<description>Comparison x Period Update</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPRUPD</name>
|
|
<description>Comparison x Update Period Update</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPV7</name>
|
|
<description>PWM Comparison 7 Value Register</description>
|
|
<addressOffset>0x000001A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CV</name>
|
|
<description>Comparison x Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CVM</name>
|
|
<description>Comparison x Value Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPVUPD7</name>
|
|
<description>PWM Comparison 7 Value Update Register</description>
|
|
<addressOffset>0x000001A4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CVUPD</name>
|
|
<description>Comparison x Value Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CVMUPD</name>
|
|
<description>Comparison x Value Mode Update</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPM7</name>
|
|
<description>PWM Comparison 7 Mode Register</description>
|
|
<addressOffset>0x000001A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Comparison x Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTR</name>
|
|
<description>Comparison x Trigger</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPR</name>
|
|
<description>Comparison x Period</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPRCNT</name>
|
|
<description>Comparison x Period Counter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPR</name>
|
|
<description>Comparison x Update Period</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPRCNT</name>
|
|
<description>Comparison x Update Period Counter</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPMUPD7</name>
|
|
<description>PWM Comparison 7 Mode Update Register</description>
|
|
<addressOffset>0x000001AC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CENUPD</name>
|
|
<description>Comparison x Enable Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTRUPD</name>
|
|
<description>Comparison x Trigger Update</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPRUPD</name>
|
|
<description>Comparison x Period Update</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CUPRUPD</name>
|
|
<description>Comparison x Update Period Update</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMR0</name>
|
|
<description>PWM Channel Mode Register (ch_num = 0)</description>
|
|
<addressOffset>0x00000200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPRE</name>
|
|
<description>Channel Pre-scaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MCK</name>
|
|
<description>Peripheral clock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_2</name>
|
|
<description>Peripheral clock/2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_4</name>
|
|
<description>Peripheral clock/4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_8</name>
|
|
<description>Peripheral clock/8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_16</name>
|
|
<description>Peripheral clock/16</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_32</name>
|
|
<description>Peripheral clock/32</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_64</name>
|
|
<description>Peripheral clock/64</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_128</name>
|
|
<description>Peripheral clock/128</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_256</name>
|
|
<description>Peripheral clock/256</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_512</name>
|
|
<description>Peripheral clock/512</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_1024</name>
|
|
<description>Peripheral clock/1024</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKA</name>
|
|
<description>Clock A</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKB</name>
|
|
<description>Clock B</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CALG</name>
|
|
<description>Channel Alignment</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Channel Polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CES</name>
|
|
<description>Counter Event Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTE</name>
|
|
<description>Dead-Time Generator Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTHI</name>
|
|
<description>Dead-Time PWMHx Output Inverted</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTLI</name>
|
|
<description>Dead-Time PWMLx Output Inverted</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CDTY0</name>
|
|
<description>PWM Channel Duty Cycle Register (ch_num = 0)</description>
|
|
<addressOffset>0x00000204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CDTY</name>
|
|
<description>Channel Duty-Cycle</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CDTYUPD0</name>
|
|
<description>PWM Channel Duty Cycle Update Register (ch_num = 0)</description>
|
|
<addressOffset>0x00000208</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CDTYUPD</name>
|
|
<description>Channel Duty-Cycle Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPRD0</name>
|
|
<description>PWM Channel Period Register (ch_num = 0)</description>
|
|
<addressOffset>0x0000020C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPRD</name>
|
|
<description>Channel Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPRDUPD0</name>
|
|
<description>PWM Channel Period Update Register (ch_num = 0)</description>
|
|
<addressOffset>0x00000210</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CPRDUPD</name>
|
|
<description>Channel Period Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCNT0</name>
|
|
<description>PWM Channel Counter Register (ch_num = 0)</description>
|
|
<addressOffset>0x00000214</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Channel Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DT0</name>
|
|
<description>PWM Channel Dead Time Register (ch_num = 0)</description>
|
|
<addressOffset>0x00000218</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTH</name>
|
|
<description>Dead-Time Value for PWMHx Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTL</name>
|
|
<description>Dead-Time Value for PWMLx Output</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTUPD0</name>
|
|
<description>PWM Channel Dead Time Update Register (ch_num = 0)</description>
|
|
<addressOffset>0x0000021C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DTHUPD</name>
|
|
<description>Dead-Time Value Update for PWMHx Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTLUPD</name>
|
|
<description>Dead-Time Value Update for PWMLx Output</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMR1</name>
|
|
<description>PWM Channel Mode Register (ch_num = 1)</description>
|
|
<addressOffset>0x00000220</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPRE</name>
|
|
<description>Channel Pre-scaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MCK</name>
|
|
<description>Peripheral clock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_2</name>
|
|
<description>Peripheral clock/2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_4</name>
|
|
<description>Peripheral clock/4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_8</name>
|
|
<description>Peripheral clock/8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_16</name>
|
|
<description>Peripheral clock/16</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_32</name>
|
|
<description>Peripheral clock/32</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_64</name>
|
|
<description>Peripheral clock/64</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_128</name>
|
|
<description>Peripheral clock/128</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_256</name>
|
|
<description>Peripheral clock/256</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_512</name>
|
|
<description>Peripheral clock/512</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_1024</name>
|
|
<description>Peripheral clock/1024</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKA</name>
|
|
<description>Clock A</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKB</name>
|
|
<description>Clock B</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CALG</name>
|
|
<description>Channel Alignment</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Channel Polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CES</name>
|
|
<description>Counter Event Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTE</name>
|
|
<description>Dead-Time Generator Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTHI</name>
|
|
<description>Dead-Time PWMHx Output Inverted</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTLI</name>
|
|
<description>Dead-Time PWMLx Output Inverted</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CDTY1</name>
|
|
<description>PWM Channel Duty Cycle Register (ch_num = 1)</description>
|
|
<addressOffset>0x00000224</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CDTY</name>
|
|
<description>Channel Duty-Cycle</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CDTYUPD1</name>
|
|
<description>PWM Channel Duty Cycle Update Register (ch_num = 1)</description>
|
|
<addressOffset>0x00000228</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CDTYUPD</name>
|
|
<description>Channel Duty-Cycle Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPRD1</name>
|
|
<description>PWM Channel Period Register (ch_num = 1)</description>
|
|
<addressOffset>0x0000022C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPRD</name>
|
|
<description>Channel Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPRDUPD1</name>
|
|
<description>PWM Channel Period Update Register (ch_num = 1)</description>
|
|
<addressOffset>0x00000230</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CPRDUPD</name>
|
|
<description>Channel Period Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCNT1</name>
|
|
<description>PWM Channel Counter Register (ch_num = 1)</description>
|
|
<addressOffset>0x00000234</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Channel Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DT1</name>
|
|
<description>PWM Channel Dead Time Register (ch_num = 1)</description>
|
|
<addressOffset>0x00000238</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTH</name>
|
|
<description>Dead-Time Value for PWMHx Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTL</name>
|
|
<description>Dead-Time Value for PWMLx Output</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTUPD1</name>
|
|
<description>PWM Channel Dead Time Update Register (ch_num = 1)</description>
|
|
<addressOffset>0x0000023C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DTHUPD</name>
|
|
<description>Dead-Time Value Update for PWMHx Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTLUPD</name>
|
|
<description>Dead-Time Value Update for PWMLx Output</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMR2</name>
|
|
<description>PWM Channel Mode Register (ch_num = 2)</description>
|
|
<addressOffset>0x00000240</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPRE</name>
|
|
<description>Channel Pre-scaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MCK</name>
|
|
<description>Peripheral clock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_2</name>
|
|
<description>Peripheral clock/2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_4</name>
|
|
<description>Peripheral clock/4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_8</name>
|
|
<description>Peripheral clock/8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_16</name>
|
|
<description>Peripheral clock/16</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_32</name>
|
|
<description>Peripheral clock/32</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_64</name>
|
|
<description>Peripheral clock/64</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_128</name>
|
|
<description>Peripheral clock/128</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_256</name>
|
|
<description>Peripheral clock/256</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_512</name>
|
|
<description>Peripheral clock/512</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_1024</name>
|
|
<description>Peripheral clock/1024</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKA</name>
|
|
<description>Clock A</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKB</name>
|
|
<description>Clock B</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CALG</name>
|
|
<description>Channel Alignment</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Channel Polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CES</name>
|
|
<description>Counter Event Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTE</name>
|
|
<description>Dead-Time Generator Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTHI</name>
|
|
<description>Dead-Time PWMHx Output Inverted</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTLI</name>
|
|
<description>Dead-Time PWMLx Output Inverted</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CDTY2</name>
|
|
<description>PWM Channel Duty Cycle Register (ch_num = 2)</description>
|
|
<addressOffset>0x00000244</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CDTY</name>
|
|
<description>Channel Duty-Cycle</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CDTYUPD2</name>
|
|
<description>PWM Channel Duty Cycle Update Register (ch_num = 2)</description>
|
|
<addressOffset>0x00000248</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CDTYUPD</name>
|
|
<description>Channel Duty-Cycle Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPRD2</name>
|
|
<description>PWM Channel Period Register (ch_num = 2)</description>
|
|
<addressOffset>0x0000024C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPRD</name>
|
|
<description>Channel Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPRDUPD2</name>
|
|
<description>PWM Channel Period Update Register (ch_num = 2)</description>
|
|
<addressOffset>0x00000250</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CPRDUPD</name>
|
|
<description>Channel Period Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCNT2</name>
|
|
<description>PWM Channel Counter Register (ch_num = 2)</description>
|
|
<addressOffset>0x00000254</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Channel Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DT2</name>
|
|
<description>PWM Channel Dead Time Register (ch_num = 2)</description>
|
|
<addressOffset>0x00000258</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTH</name>
|
|
<description>Dead-Time Value for PWMHx Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTL</name>
|
|
<description>Dead-Time Value for PWMLx Output</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTUPD2</name>
|
|
<description>PWM Channel Dead Time Update Register (ch_num = 2)</description>
|
|
<addressOffset>0x0000025C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DTHUPD</name>
|
|
<description>Dead-Time Value Update for PWMHx Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTLUPD</name>
|
|
<description>Dead-Time Value Update for PWMLx Output</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMR3</name>
|
|
<description>PWM Channel Mode Register (ch_num = 3)</description>
|
|
<addressOffset>0x00000260</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPRE</name>
|
|
<description>Channel Pre-scaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MCK</name>
|
|
<description>Peripheral clock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_2</name>
|
|
<description>Peripheral clock/2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_4</name>
|
|
<description>Peripheral clock/4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_8</name>
|
|
<description>Peripheral clock/8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_16</name>
|
|
<description>Peripheral clock/16</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_32</name>
|
|
<description>Peripheral clock/32</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_64</name>
|
|
<description>Peripheral clock/64</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_128</name>
|
|
<description>Peripheral clock/128</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_256</name>
|
|
<description>Peripheral clock/256</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_512</name>
|
|
<description>Peripheral clock/512</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK_DIV_1024</name>
|
|
<description>Peripheral clock/1024</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKA</name>
|
|
<description>Clock A</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKB</name>
|
|
<description>Clock B</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CALG</name>
|
|
<description>Channel Alignment</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Channel Polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CES</name>
|
|
<description>Counter Event Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTE</name>
|
|
<description>Dead-Time Generator Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTHI</name>
|
|
<description>Dead-Time PWMHx Output Inverted</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTLI</name>
|
|
<description>Dead-Time PWMLx Output Inverted</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CDTY3</name>
|
|
<description>PWM Channel Duty Cycle Register (ch_num = 3)</description>
|
|
<addressOffset>0x00000264</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CDTY</name>
|
|
<description>Channel Duty-Cycle</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CDTYUPD3</name>
|
|
<description>PWM Channel Duty Cycle Update Register (ch_num = 3)</description>
|
|
<addressOffset>0x00000268</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CDTYUPD</name>
|
|
<description>Channel Duty-Cycle Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPRD3</name>
|
|
<description>PWM Channel Period Register (ch_num = 3)</description>
|
|
<addressOffset>0x0000026C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPRD</name>
|
|
<description>Channel Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPRDUPD3</name>
|
|
<description>PWM Channel Period Update Register (ch_num = 3)</description>
|
|
<addressOffset>0x00000270</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CPRDUPD</name>
|
|
<description>Channel Period Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCNT3</name>
|
|
<description>PWM Channel Counter Register (ch_num = 3)</description>
|
|
<addressOffset>0x00000274</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Channel Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DT3</name>
|
|
<description>PWM Channel Dead Time Register (ch_num = 3)</description>
|
|
<addressOffset>0x00000278</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTH</name>
|
|
<description>Dead-Time Value for PWMHx Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTL</name>
|
|
<description>Dead-Time Value for PWMLx Output</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTUPD3</name>
|
|
<description>PWM Channel Dead Time Update Register (ch_num = 3)</description>
|
|
<addressOffset>0x0000027C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DTHUPD</name>
|
|
<description>Dead-Time Value Update for PWMHx Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTLUPD</name>
|
|
<description>Dead-Time Value Update for PWMLx Output</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPR</name>
|
|
<description>Transmit Pointer Register</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXPTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<addressOffset>0x0000010C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNPR</name>
|
|
<description>Transmit Next Pointer Register</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNPTR</name>
|
|
<description>Transmit Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNCR</name>
|
|
<description>Transmit Next Counter Register</description>
|
|
<addressOffset>0x0000011C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNCTR</name>
|
|
<description>Transmit Counter Next</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTCR</name>
|
|
<description>Transfer Control Register</description>
|
|
<addressOffset>0x00000120</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXTDIS</name>
|
|
<description>Receiver Transfer Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTDIS</name>
|
|
<description>Transmitter Transfer Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTSR</name>
|
|
<description>Transfer Status Register</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USART0</name>
|
|
<version>6089ZO</version>
|
|
<description>Universal Synchronous Asynchronous Receiver Transmitter 0</description>
|
|
<groupName>USART</groupName>
|
|
<prependToName>USART0_</prependToName>
|
|
<baseAddress>0x40024000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USART0</name>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RSTRX</name>
|
|
<description>Reset Receiver</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTTX</name>
|
|
<description>Reset Transmitter</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receiver Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDIS</name>
|
|
<description>Transmitter Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTSTA</name>
|
|
<description>Reset Status Bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STTBRK</name>
|
|
<description>Start Break</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STPBRK</name>
|
|
<description>Stop Break</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STTTO</name>
|
|
<description>Clear TIMEOUT Flag and Start Time-out After Next Character Received</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SENDA</name>
|
|
<description>Send Address</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTIT</name>
|
|
<description>Reset Iterations</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTNACK</name>
|
|
<description>Reset Non Acknowledge</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RETTO</name>
|
|
<description>Start Time-out Immediately</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTREN</name>
|
|
<description>Data Terminal Ready Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTRDIS</name>
|
|
<description>Data Terminal Ready Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RTSEN</name>
|
|
<description>Request to Send Pin Control</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RTSDIS</name>
|
|
<description>Request to Send Pin Control</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR_SPI_MODE</name>
|
|
<description>Control Register</description>
|
|
<alternateGroup>SPI_MODE</alternateGroup>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RSTRX</name>
|
|
<description>Reset Receiver</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTTX</name>
|
|
<description>Reset Transmitter</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receiver Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDIS</name>
|
|
<description>Transmitter Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTSTA</name>
|
|
<description>Reset Status Bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCS</name>
|
|
<description>Force SPI Chip Select</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RCS</name>
|
|
<description>Release SPI Chip Select</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MR</name>
|
|
<description>Mode Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>USART_MODE</name>
|
|
<description>USART Mode of Operation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RS485</name>
|
|
<description>RS485</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HW_HANDSHAKING</name>
|
|
<description>Hardware Handshaking</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODEM</name>
|
|
<description>Modem</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IS07816_T_0</name>
|
|
<description>IS07816 Protocol: T = 0</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IS07816_T_1</name>
|
|
<description>IS07816 Protocol: T = 1</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRDA</name>
|
|
<description>IrDA</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_MASTER</name>
|
|
<description>SPI master</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_SLAVE</name>
|
|
<description>SPI Slave</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCLKS</name>
|
|
<description>Clock Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MCK</name>
|
|
<description>Peripheral clock is selected</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV</name>
|
|
<description>Peripheral clock divided (DIV=8) is selected</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCK</name>
|
|
<description>Serial clock (SCK) is selected</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHRL</name>
|
|
<description>Character Length</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>5_BIT</name>
|
|
<description>Character length is 5 bits</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BIT</name>
|
|
<description>Character length is 6 bits</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BIT</name>
|
|
<description>Character length is 7 bits</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BIT</name>
|
|
<description>Character length is 8 bits</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNC</name>
|
|
<description>Synchronous Mode Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PAR</name>
|
|
<description>Parity Type</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even parity</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd parity</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPACE</name>
|
|
<description>Parity forced to 0 (Space)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MARK</name>
|
|
<description>Parity forced to 1 (Mark)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No parity</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MULTIDROP</name>
|
|
<description>Multidrop mode</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NBSTOP</name>
|
|
<description>Number of Stop Bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1_BIT</name>
|
|
<description>1 stop bit</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_5_BIT</name>
|
|
<description>1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_BIT</name>
|
|
<description>2 stop bits</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHMODE</name>
|
|
<description>Channel Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTOMATIC</name>
|
|
<description>Automatic Echo. Receiver input is connected to the TXD pin.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCAL_LOOPBACK</name>
|
|
<description>Local Loopback. Transmitter output is connected to the Receiver Input.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REMOTE_LOOPBACK</name>
|
|
<description>Remote Loopback. RXD pin is internally connected to the TXD pin.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>Bit Order</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MODE9</name>
|
|
<description>9-bit Character Length</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKO</name>
|
|
<description>Clock Output Select</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OVER</name>
|
|
<description>Oversampling Mode</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INACK</name>
|
|
<description>Inhibit Non Acknowledge</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DSNACK</name>
|
|
<description>Disable Successive NACK</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VAR_SYNC</name>
|
|
<description>Variable Synchronization of Command/Data Sync Start Frame Delimiter</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INVDATA</name>
|
|
<description>Inverted Data</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAX_ITERATION</name>
|
|
<description>Maximum Number of Automatic Iteration</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILTER</name>
|
|
<description>Receive Line Filter</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAN</name>
|
|
<description>Manchester Encoder/Decoder Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MODSYNC</name>
|
|
<description>Manchester Synchronization Mode</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ONEBIT</name>
|
|
<description>Start Frame Delimiter Selector</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MR_SPI_MODE</name>
|
|
<description>Mode Register</description>
|
|
<alternateGroup>SPI_MODE</alternateGroup>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>USART_MODE</name>
|
|
<description>USART Mode of Operation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPI_MASTER</name>
|
|
<description>SPI master</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_SLAVE</name>
|
|
<description>SPI Slave</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCLKS</name>
|
|
<description>Clock Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MCK</name>
|
|
<description>Peripheral clock is selected</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV</name>
|
|
<description>Peripheral clock divided (DIV=8) is selected</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCK</name>
|
|
<description>Serial Clock SLK is selected</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHRL</name>
|
|
<description>Character Length</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>8_BIT</name>
|
|
<description>Character length is 8 bits</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>SPI Clock Phase</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>SPI Clock Polarity</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKO</name>
|
|
<description>Clock Output Select</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WRDBT</name>
|
|
<description>Wait Read Data Before Transfer</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>RXRDY Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>TXRDY Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>Receiver Break Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Enable (available in all USART modes of operation)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Enable (available in all USART modes of operation)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARE</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>Time-out Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>TXEMPTY Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ITER</name>
|
|
<description>Max number of Repetitions Reached Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Enable (available in all USART modes of operation)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Non Acknowledge Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RIIC</name>
|
|
<description>Ring Indicator Input Change Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DSRIC</name>
|
|
<description>Data Set Ready Input Change Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCDIC</name>
|
|
<description>Data Carrier Detect Input Change Interrupt Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSIC</name>
|
|
<description>Clear to Send Input Change Interrupt Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MANE</name>
|
|
<description>Manchester Error Interrupt Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER_SPI_MODE</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<alternateGroup>SPI_MODE</alternateGroup>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>RXRDY Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>TXRDY Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>TXEMPTY Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNRE</name>
|
|
<description>SPI Underrun Error Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>RXRDY Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>TXRDY Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>Receiver Break Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Transfer Interrupt Disable (available in all USART modes of operation)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Disable (available in all USART modes of operation)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>Framing Error Interrupt Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARE</name>
|
|
<description>Parity Error Interrupt Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>Time-out Interrupt Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>TXEMPTY Interrupt Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ITER</name>
|
|
<description>Max Number of Repetitions Reached Interrupt Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Disable (available in all USART modes of operation)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Disable (available in all USART modes of operation)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Non Acknowledge Interrupt Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RIIC</name>
|
|
<description>Ring Indicator Input Change Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DSRIC</name>
|
|
<description>Data Set Ready Input Change Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCDIC</name>
|
|
<description>Data Carrier Detect Input Change Interrupt Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSIC</name>
|
|
<description>Clear to Send Input Change Interrupt Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MANE</name>
|
|
<description>Manchester Error Interrupt Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR_SPI_MODE</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<alternateGroup>SPI_MODE</alternateGroup>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>RXRDY Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>TXRDY Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Transfer Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>TXEMPTY Interrupt Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNRE</name>
|
|
<description>SPI Underrun Error Interrupt Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>RXRDY Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>TXRDY Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>Receiver Break Interrupt Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Mask (available in all USART modes of operation)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Mask (available in all USART modes of operation)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>Framing Error Interrupt Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARE</name>
|
|
<description>Parity Error Interrupt Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>Time-out Interrupt Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>TXEMPTY Interrupt Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ITER</name>
|
|
<description>Max Number of Repetitions Reached Interrupt Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Mask (available in all USART modes of operation)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Mask (available in all USART modes of operation)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Non Acknowledge Interrupt Mask</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RIIC</name>
|
|
<description>Ring Indicator Input Change Mask</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DSRIC</name>
|
|
<description>Data Set Ready Input Change Mask</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCDIC</name>
|
|
<description>Data Carrier Detect Input Change Interrupt Mask</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSIC</name>
|
|
<description>Clear to Send Input Change Interrupt Mask</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MANE</name>
|
|
<description>Manchester Error Interrupt Mask</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR_SPI_MODE</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<alternateGroup>SPI_MODE</alternateGroup>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>RXRDY Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>TXRDY Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>TXEMPTY Interrupt Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNRE</name>
|
|
<description>SPI Underrun Error Interrupt Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Mask</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Mask</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSR</name>
|
|
<description>Channel Status Register</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receiver Ready (cleared by reading US_RHR)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmitter Ready (cleared by writing US_THR)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of RX Buffer (cleared by writing US_RCR or US_RNCR)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of TX Buffer (cleared by writing US_TCR or US_TNCR)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>Framing Error (cleared by writing a one to bit US_CR.RSTSTA)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARE</name>
|
|
<description>Parity Error (cleared by writing a one to bit US_CR.RSTSTA)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>Receiver Time-out (cleared by writing a one to bit US_CR.STTTO)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Transmitter Empty (cleared by writing US_THR)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ITER</name>
|
|
<description>Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>TX Buffer Empty (cleared by writing US_TCR or US_TNCR)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>RX Buffer Full (cleared by writing US_RCR or US_RNCR)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RIIC</name>
|
|
<description>Ring Indicator Input Change Flag (cleared on read)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DSRIC</name>
|
|
<description>Data Set Ready Input Change Flag (cleared on read)</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCDIC</name>
|
|
<description>Data Carrier Detect Input Change Flag (cleared on read)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSIC</name>
|
|
<description>Clear to Send Input Change Flag (cleared on read)</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RI</name>
|
|
<description>Image of RI Input</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DSR</name>
|
|
<description>Image of DSR Input</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCD</name>
|
|
<description>Image of DCD Input</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>Image of CTS Input</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MANERR</name>
|
|
<description>Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSR_SPI_MODE</name>
|
|
<description>Channel Status Register</description>
|
|
<alternateGroup>SPI_MODE</alternateGroup>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receiver Ready (cleared by reading US_RHR)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmitter Ready (cleared by writing US_THR)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of RX Buffer (cleared by writing US_RCR or US_RNCR)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of TX Buffer (cleared by writing US_TCR or US_TNCR)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Transmitter Empty (cleared by writing US_THR)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNRE</name>
|
|
<description>Underrun Error (cleared by writing a one to bit US_CR.RSTSTA)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>TX Buffer Empty (cleared by writing US_TCR or US_TNCR)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>RX Buffer Full (cleared by writing US_RCR or US_RNCR)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RHR</name>
|
|
<description>Receive Holding Register</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCHR</name>
|
|
<description>Received Character</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXSYNH</name>
|
|
<description>Received Sync</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR</name>
|
|
<description>Transmit Holding Register</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TXCHR</name>
|
|
<description>Character to be Transmitted</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXSYNH</name>
|
|
<description>Sync Field to be Transmitted</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRGR</name>
|
|
<description>Baud Rate Generator Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CD</name>
|
|
<description>Clock Divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FP</name>
|
|
<description>Fractional Part</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTOR</name>
|
|
<description>Receiver Time-out Register</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TO</name>
|
|
<description>Time-out Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TTGR</name>
|
|
<description>Transmitter Timeguard Register</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TG</name>
|
|
<description>Timeguard Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIDI</name>
|
|
<description>FI DI Ratio Register</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000174</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FI_DI_RATIO</name>
|
|
<description>FI Over DI Ratio Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NER</name>
|
|
<description>Number of Errors Register</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NB_ERRORS</name>
|
|
<description>Number of Errors</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>IrDA Filter Register</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IRDA_FILTER</name>
|
|
<description>IrDA Filter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAN</name>
|
|
<description>Manchester Configuration Register</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x30011004</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TX_PL</name>
|
|
<description>Transmitter Preamble Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_PP</name>
|
|
<description>Transmitter Preamble Pattern</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALL_ONE</name>
|
|
<description>The preamble is composed of '1's</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALL_ZERO</name>
|
|
<description>The preamble is composed of '0's</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ZERO_ONE</name>
|
|
<description>The preamble is composed of '01's</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE_ZERO</name>
|
|
<description>The preamble is composed of '10's</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TX_MPOL</name>
|
|
<description>Transmitter Manchester Polarity</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RX_PL</name>
|
|
<description>Receiver Preamble Length</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RX_PP</name>
|
|
<description>Receiver Preamble Pattern detected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALL_ONE</name>
|
|
<description>The preamble is composed of '1's</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALL_ZERO</name>
|
|
<description>The preamble is composed of '0's</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ZERO_ONE</name>
|
|
<description>The preamble is composed of '01's</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE_ZERO</name>
|
|
<description>The preamble is composed of '10's</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RX_MPOL</name>
|
|
<description>Receiver Manchester Polarity</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ONE</name>
|
|
<description>Must Be Set to 1</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DRIFT</name>
|
|
<description>Drift Compensation</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPMR</name>
|
|
<description>Write Protection Mode Register</description>
|
|
<addressOffset>0x000000E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPKEY</name>
|
|
<description>Write Protection Key</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.</description>
|
|
<value>0x555341</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPSR</name>
|
|
<description>Write Protection Status Register</description>
|
|
<addressOffset>0x000000E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPVS</name>
|
|
<description>Write Protection Violation Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPVSRC</name>
|
|
<description>Write Protection Violation Source</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RPR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXPTR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<description>Receive Counter Register</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCTR</name>
|
|
<description>Receive Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPR</name>
|
|
<description>Transmit Pointer Register</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXPTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<addressOffset>0x0000010C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNPR</name>
|
|
<description>Receive Next Pointer Register</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNPTR</name>
|
|
<description>Receive Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNCR</name>
|
|
<description>Receive Next Counter Register</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNCTR</name>
|
|
<description>Receive Next Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNPR</name>
|
|
<description>Transmit Next Pointer Register</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNPTR</name>
|
|
<description>Transmit Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNCR</name>
|
|
<description>Transmit Next Counter Register</description>
|
|
<addressOffset>0x0000011C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNCTR</name>
|
|
<description>Transmit Counter Next</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTCR</name>
|
|
<description>Transfer Control Register</description>
|
|
<addressOffset>0x00000120</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXTDIS</name>
|
|
<description>Receiver Transfer Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTDIS</name>
|
|
<description>Transmitter Transfer Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTSR</name>
|
|
<description>Transfer Status Register</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USART1</name>
|
|
<version>6089ZO</version>
|
|
<description>Universal Synchronous Asynchronous Receiver Transmitter 1</description>
|
|
<groupName>USART</groupName>
|
|
<prependToName>USART1_</prependToName>
|
|
<baseAddress>0x40028000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USART1</name>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RSTRX</name>
|
|
<description>Reset Receiver</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTTX</name>
|
|
<description>Reset Transmitter</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receiver Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDIS</name>
|
|
<description>Transmitter Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTSTA</name>
|
|
<description>Reset Status Bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STTBRK</name>
|
|
<description>Start Break</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STPBRK</name>
|
|
<description>Stop Break</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STTTO</name>
|
|
<description>Clear TIMEOUT Flag and Start Time-out After Next Character Received</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SENDA</name>
|
|
<description>Send Address</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTIT</name>
|
|
<description>Reset Iterations</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTNACK</name>
|
|
<description>Reset Non Acknowledge</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RETTO</name>
|
|
<description>Start Time-out Immediately</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTREN</name>
|
|
<description>Data Terminal Ready Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTRDIS</name>
|
|
<description>Data Terminal Ready Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RTSEN</name>
|
|
<description>Request to Send Pin Control</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RTSDIS</name>
|
|
<description>Request to Send Pin Control</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR_SPI_MODE</name>
|
|
<description>Control Register</description>
|
|
<alternateGroup>SPI_MODE</alternateGroup>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RSTRX</name>
|
|
<description>Reset Receiver</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTTX</name>
|
|
<description>Reset Transmitter</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receiver Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDIS</name>
|
|
<description>Transmitter Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTSTA</name>
|
|
<description>Reset Status Bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCS</name>
|
|
<description>Force SPI Chip Select</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RCS</name>
|
|
<description>Release SPI Chip Select</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MR</name>
|
|
<description>Mode Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>USART_MODE</name>
|
|
<description>USART Mode of Operation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RS485</name>
|
|
<description>RS485</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HW_HANDSHAKING</name>
|
|
<description>Hardware Handshaking</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODEM</name>
|
|
<description>Modem</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IS07816_T_0</name>
|
|
<description>IS07816 Protocol: T = 0</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IS07816_T_1</name>
|
|
<description>IS07816 Protocol: T = 1</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRDA</name>
|
|
<description>IrDA</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_MASTER</name>
|
|
<description>SPI master</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_SLAVE</name>
|
|
<description>SPI Slave</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCLKS</name>
|
|
<description>Clock Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MCK</name>
|
|
<description>Peripheral clock is selected</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV</name>
|
|
<description>Peripheral clock divided (DIV=8) is selected</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCK</name>
|
|
<description>Serial clock (SCK) is selected</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHRL</name>
|
|
<description>Character Length</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>5_BIT</name>
|
|
<description>Character length is 5 bits</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BIT</name>
|
|
<description>Character length is 6 bits</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BIT</name>
|
|
<description>Character length is 7 bits</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BIT</name>
|
|
<description>Character length is 8 bits</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNC</name>
|
|
<description>Synchronous Mode Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PAR</name>
|
|
<description>Parity Type</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even parity</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd parity</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPACE</name>
|
|
<description>Parity forced to 0 (Space)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MARK</name>
|
|
<description>Parity forced to 1 (Mark)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No parity</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MULTIDROP</name>
|
|
<description>Multidrop mode</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NBSTOP</name>
|
|
<description>Number of Stop Bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1_BIT</name>
|
|
<description>1 stop bit</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_5_BIT</name>
|
|
<description>1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_BIT</name>
|
|
<description>2 stop bits</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHMODE</name>
|
|
<description>Channel Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTOMATIC</name>
|
|
<description>Automatic Echo. Receiver input is connected to the TXD pin.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCAL_LOOPBACK</name>
|
|
<description>Local Loopback. Transmitter output is connected to the Receiver Input.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REMOTE_LOOPBACK</name>
|
|
<description>Remote Loopback. RXD pin is internally connected to the TXD pin.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>Bit Order</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MODE9</name>
|
|
<description>9-bit Character Length</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKO</name>
|
|
<description>Clock Output Select</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OVER</name>
|
|
<description>Oversampling Mode</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INACK</name>
|
|
<description>Inhibit Non Acknowledge</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DSNACK</name>
|
|
<description>Disable Successive NACK</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VAR_SYNC</name>
|
|
<description>Variable Synchronization of Command/Data Sync Start Frame Delimiter</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INVDATA</name>
|
|
<description>Inverted Data</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAX_ITERATION</name>
|
|
<description>Maximum Number of Automatic Iteration</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILTER</name>
|
|
<description>Receive Line Filter</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAN</name>
|
|
<description>Manchester Encoder/Decoder Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MODSYNC</name>
|
|
<description>Manchester Synchronization Mode</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ONEBIT</name>
|
|
<description>Start Frame Delimiter Selector</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MR_SPI_MODE</name>
|
|
<description>Mode Register</description>
|
|
<alternateGroup>SPI_MODE</alternateGroup>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>USART_MODE</name>
|
|
<description>USART Mode of Operation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPI_MASTER</name>
|
|
<description>SPI master</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_SLAVE</name>
|
|
<description>SPI Slave</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCLKS</name>
|
|
<description>Clock Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MCK</name>
|
|
<description>Peripheral clock is selected</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV</name>
|
|
<description>Peripheral clock divided (DIV=8) is selected</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCK</name>
|
|
<description>Serial Clock SLK is selected</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHRL</name>
|
|
<description>Character Length</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>8_BIT</name>
|
|
<description>Character length is 8 bits</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>SPI Clock Phase</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>SPI Clock Polarity</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKO</name>
|
|
<description>Clock Output Select</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WRDBT</name>
|
|
<description>Wait Read Data Before Transfer</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>RXRDY Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>TXRDY Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>Receiver Break Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Enable (available in all USART modes of operation)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Enable (available in all USART modes of operation)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARE</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>Time-out Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>TXEMPTY Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ITER</name>
|
|
<description>Max number of Repetitions Reached Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Enable (available in all USART modes of operation)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Non Acknowledge Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RIIC</name>
|
|
<description>Ring Indicator Input Change Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DSRIC</name>
|
|
<description>Data Set Ready Input Change Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCDIC</name>
|
|
<description>Data Carrier Detect Input Change Interrupt Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSIC</name>
|
|
<description>Clear to Send Input Change Interrupt Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MANE</name>
|
|
<description>Manchester Error Interrupt Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER_SPI_MODE</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<alternateGroup>SPI_MODE</alternateGroup>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>RXRDY Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>TXRDY Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>TXEMPTY Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNRE</name>
|
|
<description>SPI Underrun Error Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>RXRDY Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>TXRDY Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>Receiver Break Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Transfer Interrupt Disable (available in all USART modes of operation)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Disable (available in all USART modes of operation)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>Framing Error Interrupt Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARE</name>
|
|
<description>Parity Error Interrupt Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>Time-out Interrupt Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>TXEMPTY Interrupt Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ITER</name>
|
|
<description>Max Number of Repetitions Reached Interrupt Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Disable (available in all USART modes of operation)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Disable (available in all USART modes of operation)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Non Acknowledge Interrupt Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RIIC</name>
|
|
<description>Ring Indicator Input Change Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DSRIC</name>
|
|
<description>Data Set Ready Input Change Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCDIC</name>
|
|
<description>Data Carrier Detect Input Change Interrupt Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSIC</name>
|
|
<description>Clear to Send Input Change Interrupt Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MANE</name>
|
|
<description>Manchester Error Interrupt Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR_SPI_MODE</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<alternateGroup>SPI_MODE</alternateGroup>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>RXRDY Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>TXRDY Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Transfer Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>TXEMPTY Interrupt Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNRE</name>
|
|
<description>SPI Underrun Error Interrupt Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>RXRDY Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>TXRDY Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>Receiver Break Interrupt Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Mask (available in all USART modes of operation)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Mask (available in all USART modes of operation)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>Framing Error Interrupt Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARE</name>
|
|
<description>Parity Error Interrupt Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>Time-out Interrupt Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>TXEMPTY Interrupt Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ITER</name>
|
|
<description>Max Number of Repetitions Reached Interrupt Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Mask (available in all USART modes of operation)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Mask (available in all USART modes of operation)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Non Acknowledge Interrupt Mask</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RIIC</name>
|
|
<description>Ring Indicator Input Change Mask</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DSRIC</name>
|
|
<description>Data Set Ready Input Change Mask</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCDIC</name>
|
|
<description>Data Carrier Detect Input Change Interrupt Mask</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSIC</name>
|
|
<description>Clear to Send Input Change Interrupt Mask</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MANE</name>
|
|
<description>Manchester Error Interrupt Mask</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR_SPI_MODE</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<alternateGroup>SPI_MODE</alternateGroup>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>RXRDY Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>TXRDY Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>TXEMPTY Interrupt Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNRE</name>
|
|
<description>SPI Underrun Error Interrupt Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Mask</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Mask</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSR</name>
|
|
<description>Channel Status Register</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receiver Ready (cleared by reading US_RHR)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmitter Ready (cleared by writing US_THR)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of RX Buffer (cleared by writing US_RCR or US_RNCR)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of TX Buffer (cleared by writing US_TCR or US_TNCR)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>Framing Error (cleared by writing a one to bit US_CR.RSTSTA)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARE</name>
|
|
<description>Parity Error (cleared by writing a one to bit US_CR.RSTSTA)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>Receiver Time-out (cleared by writing a one to bit US_CR.STTTO)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Transmitter Empty (cleared by writing US_THR)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ITER</name>
|
|
<description>Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>TX Buffer Empty (cleared by writing US_TCR or US_TNCR)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>RX Buffer Full (cleared by writing US_RCR or US_RNCR)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RIIC</name>
|
|
<description>Ring Indicator Input Change Flag (cleared on read)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DSRIC</name>
|
|
<description>Data Set Ready Input Change Flag (cleared on read)</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCDIC</name>
|
|
<description>Data Carrier Detect Input Change Flag (cleared on read)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSIC</name>
|
|
<description>Clear to Send Input Change Flag (cleared on read)</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RI</name>
|
|
<description>Image of RI Input</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DSR</name>
|
|
<description>Image of DSR Input</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCD</name>
|
|
<description>Image of DCD Input</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>Image of CTS Input</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MANERR</name>
|
|
<description>Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSR_SPI_MODE</name>
|
|
<description>Channel Status Register</description>
|
|
<alternateGroup>SPI_MODE</alternateGroup>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receiver Ready (cleared by reading US_RHR)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmitter Ready (cleared by writing US_THR)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of RX Buffer (cleared by writing US_RCR or US_RNCR)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of TX Buffer (cleared by writing US_TCR or US_TNCR)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Transmitter Empty (cleared by writing US_THR)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNRE</name>
|
|
<description>Underrun Error (cleared by writing a one to bit US_CR.RSTSTA)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>TX Buffer Empty (cleared by writing US_TCR or US_TNCR)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>RX Buffer Full (cleared by writing US_RCR or US_RNCR)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RHR</name>
|
|
<description>Receive Holding Register</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCHR</name>
|
|
<description>Received Character</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXSYNH</name>
|
|
<description>Received Sync</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR</name>
|
|
<description>Transmit Holding Register</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TXCHR</name>
|
|
<description>Character to be Transmitted</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXSYNH</name>
|
|
<description>Sync Field to be Transmitted</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRGR</name>
|
|
<description>Baud Rate Generator Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CD</name>
|
|
<description>Clock Divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FP</name>
|
|
<description>Fractional Part</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTOR</name>
|
|
<description>Receiver Time-out Register</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TO</name>
|
|
<description>Time-out Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TTGR</name>
|
|
<description>Transmitter Timeguard Register</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TG</name>
|
|
<description>Timeguard Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIDI</name>
|
|
<description>FI DI Ratio Register</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000174</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FI_DI_RATIO</name>
|
|
<description>FI Over DI Ratio Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NER</name>
|
|
<description>Number of Errors Register</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NB_ERRORS</name>
|
|
<description>Number of Errors</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>IrDA Filter Register</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IRDA_FILTER</name>
|
|
<description>IrDA Filter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAN</name>
|
|
<description>Manchester Configuration Register</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x30011004</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TX_PL</name>
|
|
<description>Transmitter Preamble Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_PP</name>
|
|
<description>Transmitter Preamble Pattern</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALL_ONE</name>
|
|
<description>The preamble is composed of '1's</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALL_ZERO</name>
|
|
<description>The preamble is composed of '0's</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ZERO_ONE</name>
|
|
<description>The preamble is composed of '01's</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE_ZERO</name>
|
|
<description>The preamble is composed of '10's</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TX_MPOL</name>
|
|
<description>Transmitter Manchester Polarity</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RX_PL</name>
|
|
<description>Receiver Preamble Length</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RX_PP</name>
|
|
<description>Receiver Preamble Pattern detected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALL_ONE</name>
|
|
<description>The preamble is composed of '1's</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALL_ZERO</name>
|
|
<description>The preamble is composed of '0's</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ZERO_ONE</name>
|
|
<description>The preamble is composed of '01's</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE_ZERO</name>
|
|
<description>The preamble is composed of '10's</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RX_MPOL</name>
|
|
<description>Receiver Manchester Polarity</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ONE</name>
|
|
<description>Must Be Set to 1</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DRIFT</name>
|
|
<description>Drift Compensation</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPMR</name>
|
|
<description>Write Protection Mode Register</description>
|
|
<addressOffset>0x000000E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPKEY</name>
|
|
<description>Write Protection Key</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.</description>
|
|
<value>0x555341</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPSR</name>
|
|
<description>Write Protection Status Register</description>
|
|
<addressOffset>0x000000E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPVS</name>
|
|
<description>Write Protection Violation Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPVSRC</name>
|
|
<description>Write Protection Violation Source</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RPR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXPTR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<description>Receive Counter Register</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCTR</name>
|
|
<description>Receive Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPR</name>
|
|
<description>Transmit Pointer Register</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXPTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<addressOffset>0x0000010C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNPR</name>
|
|
<description>Receive Next Pointer Register</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNPTR</name>
|
|
<description>Receive Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNCR</name>
|
|
<description>Receive Next Counter Register</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNCTR</name>
|
|
<description>Receive Next Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNPR</name>
|
|
<description>Transmit Next Pointer Register</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNPTR</name>
|
|
<description>Transmit Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNCR</name>
|
|
<description>Transmit Next Counter Register</description>
|
|
<addressOffset>0x0000011C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNCTR</name>
|
|
<description>Transmit Counter Next</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTCR</name>
|
|
<description>Transfer Control Register</description>
|
|
<addressOffset>0x00000120</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXTDIS</name>
|
|
<description>Receiver Transfer Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTDIS</name>
|
|
<description>Transmitter Transfer Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTSR</name>
|
|
<description>Transfer Status Register</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UDP</name>
|
|
<version>6083Z</version>
|
|
<description>USB Device Port</description>
|
|
<prependToName>UDP_</prependToName>
|
|
<baseAddress>0x40034000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UDP</name>
|
|
<value>34</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>FRM_NUM</name>
|
|
<description>Frame Number Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FRM_NUM</name>
|
|
<description>Frame Number as Defined in the Packet Field Formats</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRM_ERR</name>
|
|
<description>Frame Error</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRM_OK</name>
|
|
<description>Frame OK</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GLB_STAT</name>
|
|
<description>Global State Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000010</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FADDEN</name>
|
|
<description>Function Address Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CONFG</name>
|
|
<description>Configured</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ESR</name>
|
|
<description>Enable Send Resume</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSMINPR</name>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMWUPE</name>
|
|
<description>Remote Wakeup Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FADDR</name>
|
|
<description>Function Address Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000100</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FADD</name>
|
|
<description>Function Address Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FEN</name>
|
|
<description>Function Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>EP0INT</name>
|
|
<description>Enable Endpoint 0 Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP1INT</name>
|
|
<description>Enable Endpoint 1 Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP2INT</name>
|
|
<description>Enable Endpoint 2Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP3INT</name>
|
|
<description>Enable Endpoint 3 Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP4INT</name>
|
|
<description>Enable Endpoint 4 Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP5INT</name>
|
|
<description>Enable Endpoint 5 Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP6INT</name>
|
|
<description>Enable Endpoint 6 Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP7INT</name>
|
|
<description>Enable Endpoint 7 Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXSUSP</name>
|
|
<description>Enable UDP Suspend Interrupt</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRSM</name>
|
|
<description>Enable UDP Resume Interrupt</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EXTRSM</name>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SOFINT</name>
|
|
<description>Enable Start Of Frame Interrupt</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Enable UDP Bus Wakeup Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>EP0INT</name>
|
|
<description>Disable Endpoint 0 Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP1INT</name>
|
|
<description>Disable Endpoint 1 Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP2INT</name>
|
|
<description>Disable Endpoint 2 Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP3INT</name>
|
|
<description>Disable Endpoint 3 Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP4INT</name>
|
|
<description>Disable Endpoint 4 Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP5INT</name>
|
|
<description>Disable Endpoint 5 Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP6INT</name>
|
|
<description>Disable Endpoint 6 Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP7INT</name>
|
|
<description>Disable Endpoint 7 Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXSUSP</name>
|
|
<description>Disable UDP Suspend Interrupt</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRSM</name>
|
|
<description>Disable UDP Resume Interrupt</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EXTRSM</name>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SOFINT</name>
|
|
<description>Disable Start Of Frame Interrupt</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Disable USB Bus Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00001200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EP0INT</name>
|
|
<description>Mask Endpoint 0 Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP1INT</name>
|
|
<description>Mask Endpoint 1 Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP2INT</name>
|
|
<description>Mask Endpoint 2 Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP3INT</name>
|
|
<description>Mask Endpoint 3 Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP4INT</name>
|
|
<description>Mask Endpoint 4 Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP5INT</name>
|
|
<description>Mask Endpoint 5 Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP6INT</name>
|
|
<description>Mask Endpoint 6 Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP7INT</name>
|
|
<description>Mask Endpoint 7 Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXSUSP</name>
|
|
<description>Mask UDP Suspend Interrupt</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRSM</name>
|
|
<description>Mask UDP Resume Interrupt.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EXTRSM</name>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SOFINT</name>
|
|
<description>Mask Start Of Frame Interrupt</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BIT12</name>
|
|
<description>UDP_IMR Bit 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>USB Bus Wakeup Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<description>Interrupt Status Register</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>EP0INT</name>
|
|
<description>Endpoint 0 Interrupt Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP1INT</name>
|
|
<description>Endpoint 1 Interrupt Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP2INT</name>
|
|
<description>Endpoint 2 Interrupt Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP3INT</name>
|
|
<description>Endpoint 3 Interrupt Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP4INT</name>
|
|
<description>Endpoint 4 Interrupt Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP5INT</name>
|
|
<description>Endpoint 5 Interrupt Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP6INT</name>
|
|
<description>Endpoint 6 Interrupt Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP7INT</name>
|
|
<description>Endpoint 7Interrupt Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXSUSP</name>
|
|
<description>UDP Suspend Interrupt Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRSM</name>
|
|
<description>UDP Resume Interrupt Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EXTRSM</name>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SOFINT</name>
|
|
<description>Start of Frame Interrupt Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDBUSRES</name>
|
|
<description>End of BUS Reset Interrupt Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>UDP Resume Interrupt Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>Interrupt Clear Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXSUSP</name>
|
|
<description>Clear UDP Suspend Interrupt</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRSM</name>
|
|
<description>Clear UDP Resume Interrupt</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EXTRSM</name>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SOFINT</name>
|
|
<description>Clear Start Of Frame Interrupt</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDBUSRES</name>
|
|
<description>Clear End of Bus Reset Interrupt</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Clear Wakeup Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RST_EP</name>
|
|
<description>Reset Endpoint Register</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EP0</name>
|
|
<description>Reset Endpoint 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EP1</name>
|
|
<description>Reset Endpoint 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EP2</name>
|
|
<description>Reset Endpoint 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EP3</name>
|
|
<description>Reset Endpoint 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EP4</name>
|
|
<description>Reset Endpoint 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EP5</name>
|
|
<description>Reset Endpoint 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EP6</name>
|
|
<description>Reset Endpoint 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EP7</name>
|
|
<description>Reset Endpoint 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>CSR[%s]</name>
|
|
<description>Endpoint Control and Status Register</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOMP</name>
|
|
<description>Generates an IN Packet with Data Previously Written in the DPR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RX_DATA_BK0</name>
|
|
<description>Receive Data Bank 0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXSETUP</name>
|
|
<description>Received Setup</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALLSENT</name>
|
|
<description>Stall Sent</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPKTRDY</name>
|
|
<description>Transmit Packet Ready</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FORCESTALL</name>
|
|
<description>Force Stall (used by Control, Bulk and Isochronous Endpoints)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RX_DATA_BK1</name>
|
|
<description>Receive Data Bank 1 (only used by endpoints with ping-pong attributes)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Transfer Direction (only available for control endpoints) (Read/Write)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type (Read/Write)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CTRL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO_OUT</name>
|
|
<description>Isochronous OUT</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK_OUT</name>
|
|
<description>Bulk OUT</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT_OUT</name>
|
|
<description>Interrupt OUT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO_IN</name>
|
|
<description>Isochronous IN</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK_IN</name>
|
|
<description>Bulk IN</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT_IN</name>
|
|
<description>Interrupt IN</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTGLE</name>
|
|
<description>Data Toggle (Read-only)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPEDS</name>
|
|
<description>Endpoint Enable Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBYTECNT</name>
|
|
<description>Number of Bytes Available in the FIFO (Read-only)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSR0_ISOCHRONOUS</name>
|
|
<description>Endpoint Control and Status Register</description>
|
|
<alternateGroup>ISOCHRONOUS</alternateGroup>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOMP</name>
|
|
<description>Generates an IN Packet with Data Previously Written in the DPR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RX_DATA_BK0</name>
|
|
<description>Receive Data Bank 0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXSETUP</name>
|
|
<description>Received Setup</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ISOERROR</name>
|
|
<description>A CRC error has been detected in an isochronous transfer</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPKTRDY</name>
|
|
<description>Transmit Packet Ready</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FORCESTALL</name>
|
|
<description>Force Stall (used by Control, Bulk and Isochronous Endpoints)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RX_DATA_BK1</name>
|
|
<description>Receive Data Bank 1 (only used by endpoints with ping-pong attributes)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Transfer Direction (only available for control endpoints) (Read/Write)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type (Read/Write)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CTRL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO_OUT</name>
|
|
<description>Isochronous OUT</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO_IN</name>
|
|
<description>Isochronous IN</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK_OUT</name>
|
|
<description>Bulk OUT</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK_IN</name>
|
|
<description>Bulk IN</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT_OUT</name>
|
|
<description>Interrupt OUT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT_IN</name>
|
|
<description>Interrupt IN</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTGLE</name>
|
|
<description>Data Toggle (Read-only)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPEDS</name>
|
|
<description>Endpoint Enable Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBYTECNT</name>
|
|
<description>Number of Bytes Available in the FIFO (Read-only)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>FDR[%s]</name>
|
|
<description>Endpoint FIFO Data Register</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>FIFO_DATA</name>
|
|
<description>FIFO Data Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXVC</name>
|
|
<description>Transceiver Control Register</description>
|
|
<addressOffset>0x00000074</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000100</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXVDIS</name>
|
|
<description>Transceiver Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PUON</name>
|
|
<description>Pull-up On</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC</name>
|
|
<version>6489ZA</version>
|
|
<description>Analog-to-Digital Converter</description>
|
|
<prependToName>ADC_</prependToName>
|
|
<baseAddress>0x40038000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC</name>
|
|
<value>29</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start Conversion</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOCAL</name>
|
|
<description>Automatic Calibration of ADC</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MR</name>
|
|
<description>Mode Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRGEN</name>
|
|
<description>Trigger Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Hardware triggers are disabled. Starting a conversion is only possible by software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Hardware trigger selected by TRGSEL field is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRGSEL</name>
|
|
<description>Trigger Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_TRIG0</name>
|
|
<description>External trigger</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_TRIG1</name>
|
|
<description>TIO Output of the Timer Counter Channel 0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_TRIG2</name>
|
|
<description>TIO Output of the Timer Counter Channel 1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_TRIG3</name>
|
|
<description>TIO Output of the Timer Counter Channel 2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_TRIG4</name>
|
|
<description>PWM Event Line 0</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_TRIG5</name>
|
|
<description>PWM Event Line 1</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEEP</name>
|
|
<description>Sleep Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal Mode: The ADC core and reference voltage circuitry are kept ON between conversions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLEEP</name>
|
|
<description>Sleep Mode: The wake-up time can be modified by programming FWUP bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FWUP</name>
|
|
<description>Fast Wake Up</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>If SLEEP is 1, then both ADC core and reference voltage circuitry are OFF between conversions</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ON</name>
|
|
<description>If SLEEP is 1, then Fast Wake-up Sleep mode: The voltage reference is ON between conversions and ADC core is OFF</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FREERUN</name>
|
|
<description>Free Run Mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Normal Mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ON</name>
|
|
<description>Free Run Mode: Never wait for any trigger.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCAL</name>
|
|
<description>Prescaler Rate Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STARTUP</name>
|
|
<description>Startup Time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SUT0</name>
|
|
<description>0 periods of ADCCLK</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUT8</name>
|
|
<description>8 periods of ADCCLK</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUT16</name>
|
|
<description>16 periods of ADCCLK</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUT24</name>
|
|
<description>24 periods of ADCCLK</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUT64</name>
|
|
<description>64 periods of ADCCLK</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUT80</name>
|
|
<description>80 periods of ADCCLK</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUT96</name>
|
|
<description>96 periods of ADCCLK</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUT112</name>
|
|
<description>112 periods of ADCCLK</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUT512</name>
|
|
<description>512 periods of ADCCLK</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUT576</name>
|
|
<description>576 periods of ADCCLK</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUT640</name>
|
|
<description>640 periods of ADCCLK</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUT704</name>
|
|
<description>704 periods of ADCCLK</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUT768</name>
|
|
<description>768 periods of ADCCLK</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUT832</name>
|
|
<description>832 periods of ADCCLK</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUT896</name>
|
|
<description>896 periods of ADCCLK</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUT960</name>
|
|
<description>960 periods of ADCCLK</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETTLING</name>
|
|
<description>Analog Settling Time</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AST3</name>
|
|
<description>3 periods of ADCCLK</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AST5</name>
|
|
<description>5 periods of ADCCLK</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AST9</name>
|
|
<description>9 periods of ADCCLK</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AST17</name>
|
|
<description>17 periods of ADCCLK</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANACH</name>
|
|
<description>Analog Change</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALLOWED</name>
|
|
<description>Allows different analog settings for each channel. See ADC_CGR and ADC_COR registers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRACKTIM</name>
|
|
<description>Tracking Time</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRANSFER</name>
|
|
<description>Hold Time</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USEQ</name>
|
|
<description>Use Sequence Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NUM_ORDER</name>
|
|
<description>Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG_ORDER</name>
|
|
<description>User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert the same channel several times.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEQR1</name>
|
|
<description>Channel Sequence Register 1</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>USCH1</name>
|
|
<description>User Sequence Number 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USCH2</name>
|
|
<description>User Sequence Number 2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USCH3</name>
|
|
<description>User Sequence Number 3</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USCH4</name>
|
|
<description>User Sequence Number 4</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USCH5</name>
|
|
<description>User Sequence Number 5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USCH6</name>
|
|
<description>User Sequence Number 6</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USCH7</name>
|
|
<description>User Sequence Number 7</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USCH8</name>
|
|
<description>User Sequence Number 8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEQR2</name>
|
|
<description>Channel Sequence Register 2</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>USCH9</name>
|
|
<description>User Sequence Number 9</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USCH10</name>
|
|
<description>User Sequence Number 10</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USCH11</name>
|
|
<description>User Sequence Number 11</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USCH12</name>
|
|
<description>User Sequence Number 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USCH13</name>
|
|
<description>User Sequence Number 13</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USCH14</name>
|
|
<description>User Sequence Number 14</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USCH15</name>
|
|
<description>User Sequence Number 15</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHER</name>
|
|
<description>Channel Enable Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel 2 Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel 3 Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<description>Channel 4 Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<description>Channel 5 Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<description>Channel 6 Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<description>Channel 7 Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<description>Channel 8 Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<description>Channel 9 Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<description>Channel 10 Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<description>Channel 11 Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<description>Channel 12 Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<description>Channel 13 Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<description>Channel 14 Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<description>Channel 15 Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHDR</name>
|
|
<description>Channel Disable Register</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel 2 Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel 3 Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<description>Channel 4 Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<description>Channel 5 Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<description>Channel 6 Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<description>Channel 7 Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<description>Channel 8 Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<description>Channel 9 Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<description>Channel 10 Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<description>Channel 11 Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<description>Channel 12 Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<description>Channel 13 Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<description>Channel 14 Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<description>Channel 15 Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHSR</name>
|
|
<description>Channel Status Register</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel 2 Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel 3 Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<description>Channel 4 Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<description>Channel 5 Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<description>Channel 6 Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<description>Channel 7 Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<description>Channel 8 Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<description>Channel 9 Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<description>Channel 10 Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<description>Channel 11 Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<description>Channel 12 Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<description>Channel 13 Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<description>Channel 14 Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<description>Channel 15 Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCDR</name>
|
|
<description>Last Converted Data Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LDATA</name>
|
|
<description>Last Data Converted</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHNB</name>
|
|
<description>Channel Number</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>EOC0</name>
|
|
<description>End of Conversion Interrupt Enable 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC1</name>
|
|
<description>End of Conversion Interrupt Enable 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC2</name>
|
|
<description>End of Conversion Interrupt Enable 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC3</name>
|
|
<description>End of Conversion Interrupt Enable 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC4</name>
|
|
<description>End of Conversion Interrupt Enable 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC5</name>
|
|
<description>End of Conversion Interrupt Enable 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC6</name>
|
|
<description>End of Conversion Interrupt Enable 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC7</name>
|
|
<description>End of Conversion Interrupt Enable 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC8</name>
|
|
<description>End of Conversion Interrupt Enable 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC9</name>
|
|
<description>End of Conversion Interrupt Enable 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC10</name>
|
|
<description>End of Conversion Interrupt Enable 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC11</name>
|
|
<description>End of Conversion Interrupt Enable 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC12</name>
|
|
<description>End of Conversion Interrupt Enable 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC13</name>
|
|
<description>End of Conversion Interrupt Enable 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC14</name>
|
|
<description>End of Conversion Interrupt Enable 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC15</name>
|
|
<description>End of Conversion Interrupt Enable 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOCAL</name>
|
|
<description>End of Calibration Sequence</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Data Ready Interrupt Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GOVRE</name>
|
|
<description>General Overrun Error Interrupt Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMPE</name>
|
|
<description>Comparison Event Interrupt Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>EOC0</name>
|
|
<description>End of Conversion Interrupt Disable 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC1</name>
|
|
<description>End of Conversion Interrupt Disable 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC2</name>
|
|
<description>End of Conversion Interrupt Disable 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC3</name>
|
|
<description>End of Conversion Interrupt Disable 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC4</name>
|
|
<description>End of Conversion Interrupt Disable 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC5</name>
|
|
<description>End of Conversion Interrupt Disable 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC6</name>
|
|
<description>End of Conversion Interrupt Disable 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC7</name>
|
|
<description>End of Conversion Interrupt Disable 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC8</name>
|
|
<description>End of Conversion Interrupt Disable 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC9</name>
|
|
<description>End of Conversion Interrupt Disable 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC10</name>
|
|
<description>End of Conversion Interrupt Disable 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC11</name>
|
|
<description>End of Conversion Interrupt Disable 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC12</name>
|
|
<description>End of Conversion Interrupt Disable 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC13</name>
|
|
<description>End of Conversion Interrupt Disable 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC14</name>
|
|
<description>End of Conversion Interrupt Disable 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC15</name>
|
|
<description>End of Conversion Interrupt Disable 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOCAL</name>
|
|
<description>End of Calibration Sequence</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Data Ready Interrupt Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GOVRE</name>
|
|
<description>General Overrun Error Interrupt Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMPE</name>
|
|
<description>Comparison Event Interrupt Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EOC0</name>
|
|
<description>End of Conversion Interrupt Mask 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC1</name>
|
|
<description>End of Conversion Interrupt Mask 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC2</name>
|
|
<description>End of Conversion Interrupt Mask 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC3</name>
|
|
<description>End of Conversion Interrupt Mask 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC4</name>
|
|
<description>End of Conversion Interrupt Mask 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC5</name>
|
|
<description>End of Conversion Interrupt Mask 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC6</name>
|
|
<description>End of Conversion Interrupt Mask 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC7</name>
|
|
<description>End of Conversion Interrupt Mask 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC8</name>
|
|
<description>End of Conversion Interrupt Mask 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC9</name>
|
|
<description>End of Conversion Interrupt Mask 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC10</name>
|
|
<description>End of Conversion Interrupt Mask 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC11</name>
|
|
<description>End of Conversion Interrupt Mask 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC12</name>
|
|
<description>End of Conversion Interrupt Mask 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC13</name>
|
|
<description>End of Conversion Interrupt Mask 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC14</name>
|
|
<description>End of Conversion Interrupt Mask 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC15</name>
|
|
<description>End of Conversion Interrupt Mask 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOCAL</name>
|
|
<description>End of Calibration Sequence</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Data Ready Interrupt Mask</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GOVRE</name>
|
|
<description>General Overrun Error Interrupt Mask</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMPE</name>
|
|
<description>Comparison Event Interrupt Mask</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Buffer Interrupt Mask</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full Interrupt Mask</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<description>Interrupt Status Register</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EOC0</name>
|
|
<description>End of Conversion 0 (automatically set / cleared)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC1</name>
|
|
<description>End of Conversion 1 (automatically set / cleared)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC2</name>
|
|
<description>End of Conversion 2 (automatically set / cleared)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC3</name>
|
|
<description>End of Conversion 3 (automatically set / cleared)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC4</name>
|
|
<description>End of Conversion 4 (automatically set / cleared)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC5</name>
|
|
<description>End of Conversion 5 (automatically set / cleared)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC6</name>
|
|
<description>End of Conversion 6 (automatically set / cleared)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC7</name>
|
|
<description>End of Conversion 7 (automatically set / cleared)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC8</name>
|
|
<description>End of Conversion 8 (automatically set / cleared)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC9</name>
|
|
<description>End of Conversion 9 (automatically set / cleared)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC10</name>
|
|
<description>End of Conversion 10 (automatically set / cleared)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC11</name>
|
|
<description>End of Conversion 11 (automatically set / cleared)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC12</name>
|
|
<description>End of Conversion 12 (automatically set / cleared)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC13</name>
|
|
<description>End of Conversion 13 (automatically set / cleared)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC14</name>
|
|
<description>End of Conversion 14 (automatically set / cleared)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC15</name>
|
|
<description>End of Conversion 15 (automatically set / cleared)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOCAL</name>
|
|
<description>End of Calibration Sequence</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Data Ready (automatically set / cleared)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GOVRE</name>
|
|
<description>General Overrun Error (cleared on read)</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMPE</name>
|
|
<description>Comparison Event (cleared on read)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receive Transfer (cleared by writing ADC_RCR or ADC_RNCR)</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full (cleared by writing ADC_RCR or ADC_RNCR)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OVER</name>
|
|
<description>Overrun Status Register</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVRE0</name>
|
|
<description>Overrun Error 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE1</name>
|
|
<description>Overrun Error 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE2</name>
|
|
<description>Overrun Error 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE3</name>
|
|
<description>Overrun Error 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE4</name>
|
|
<description>Overrun Error 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE5</name>
|
|
<description>Overrun Error 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE6</name>
|
|
<description>Overrun Error 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE7</name>
|
|
<description>Overrun Error 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE8</name>
|
|
<description>Overrun Error 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE9</name>
|
|
<description>Overrun Error 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE10</name>
|
|
<description>Overrun Error 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE11</name>
|
|
<description>Overrun Error 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE12</name>
|
|
<description>Overrun Error 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE13</name>
|
|
<description>Overrun Error 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE14</name>
|
|
<description>Overrun Error 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE15</name>
|
|
<description>Overrun Error 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMR</name>
|
|
<description>Extended Mode Register</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMPMODE</name>
|
|
<description>Comparison Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Generates an event when the converted data is lower than the low threshold of the window.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Generates an event when the converted data is higher than the high threshold of the window.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IN</name>
|
|
<description>Generates an event when the converted data is in the comparison window.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUT</name>
|
|
<description>Generates an event when the converted data is out of the comparison window.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSEL</name>
|
|
<description>Comparison Selected Channel</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPALL</name>
|
|
<description>Compare All Channels</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Tag of the ADC_LCDR</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CWR</name>
|
|
<description>Compare Window Register</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LOWTHRES</name>
|
|
<description>Low Threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HIGHTHRES</name>
|
|
<description>High Threshold</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CGR</name>
|
|
<description>Channel Gain Register</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GAIN0</name>
|
|
<description>Gain for Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF0_5</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF1</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2_DIFF2</name>
|
|
<description>Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4_DIFF2</name>
|
|
<description>Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GAIN1</name>
|
|
<description>Gain for Channel 1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF0_5</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF1</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2_DIFF2</name>
|
|
<description>Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4_DIFF2</name>
|
|
<description>Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GAIN2</name>
|
|
<description>Gain for Channel 2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF0_5</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF1</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2_DIFF2</name>
|
|
<description>Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4_DIFF2</name>
|
|
<description>Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GAIN3</name>
|
|
<description>Gain for Channel 3</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF0_5</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF1</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2_DIFF2</name>
|
|
<description>Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4_DIFF2</name>
|
|
<description>Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GAIN4</name>
|
|
<description>Gain for Channel 4</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF0_5</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF1</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2_DIFF2</name>
|
|
<description>Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4_DIFF2</name>
|
|
<description>Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GAIN5</name>
|
|
<description>Gain for Channel 5</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF0_5</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF1</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2_DIFF2</name>
|
|
<description>Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4_DIFF2</name>
|
|
<description>Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GAIN6</name>
|
|
<description>Gain for Channel 6</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF0_5</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF1</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2_DIFF2</name>
|
|
<description>Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4_DIFF2</name>
|
|
<description>Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GAIN7</name>
|
|
<description>Gain for Channel 7</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF0_5</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF1</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2_DIFF2</name>
|
|
<description>Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4_DIFF2</name>
|
|
<description>Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GAIN8</name>
|
|
<description>Gain for Channel 8</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF0_5</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF1</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2_DIFF2</name>
|
|
<description>Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4_DIFF2</name>
|
|
<description>Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GAIN9</name>
|
|
<description>Gain for Channel 9</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF0_5</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF1</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2_DIFF2</name>
|
|
<description>Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4_DIFF2</name>
|
|
<description>Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GAIN10</name>
|
|
<description>Gain for Channel 10</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF0_5</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF1</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2_DIFF2</name>
|
|
<description>Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4_DIFF2</name>
|
|
<description>Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GAIN11</name>
|
|
<description>Gain for Channel 11</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF0_5</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF1</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2_DIFF2</name>
|
|
<description>Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4_DIFF2</name>
|
|
<description>Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GAIN12</name>
|
|
<description>Gain for Channel 12</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF0_5</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF1</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2_DIFF2</name>
|
|
<description>Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4_DIFF2</name>
|
|
<description>Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GAIN13</name>
|
|
<description>Gain for Channel 13</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF0_5</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF1</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2_DIFF2</name>
|
|
<description>Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4_DIFF2</name>
|
|
<description>Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GAIN14</name>
|
|
<description>Gain for Channel 14</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF0_5</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF1</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2_DIFF2</name>
|
|
<description>Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4_DIFF2</name>
|
|
<description>Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GAIN15</name>
|
|
<description>Gain for Channel 15</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF0_5</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE1_DIFF1</name>
|
|
<description>Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE2_DIFF2</name>
|
|
<description>Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE4_DIFF2</name>
|
|
<description>Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COR</name>
|
|
<description>Channel Offset Register</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OFF0</name>
|
|
<description>Offset for Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OFF1</name>
|
|
<description>Offset for Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OFF2</name>
|
|
<description>Offset for Channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OFF3</name>
|
|
<description>Offset for Channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OFF4</name>
|
|
<description>Offset for Channel 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OFF5</name>
|
|
<description>Offset for Channel 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OFF6</name>
|
|
<description>Offset for Channel 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OFF7</name>
|
|
<description>Offset for Channel 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OFF8</name>
|
|
<description>Offset for Channel 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OFF9</name>
|
|
<description>Offset for Channel 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OFF10</name>
|
|
<description>Offset for Channel 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OFF11</name>
|
|
<description>Offset for Channel 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OFF12</name>
|
|
<description>Offset for Channel 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OFF13</name>
|
|
<description>Offset for Channel 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OFF14</name>
|
|
<description>Offset for Channel 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OFF15</name>
|
|
<description>Offset for Channel 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFF0</name>
|
|
<description>Differential Inputs for Channel 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFF1</name>
|
|
<description>Differential Inputs for Channel 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFF2</name>
|
|
<description>Differential Inputs for Channel 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFF3</name>
|
|
<description>Differential Inputs for Channel 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFF4</name>
|
|
<description>Differential Inputs for Channel 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFF5</name>
|
|
<description>Differential Inputs for Channel 5</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFF6</name>
|
|
<description>Differential Inputs for Channel 6</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFF7</name>
|
|
<description>Differential Inputs for Channel 7</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFF8</name>
|
|
<description>Differential Inputs for Channel 8</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFF9</name>
|
|
<description>Differential Inputs for Channel 9</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFF10</name>
|
|
<description>Differential Inputs for Channel 10</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFF11</name>
|
|
<description>Differential Inputs for Channel 11</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFF12</name>
|
|
<description>Differential Inputs for Channel 12</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFF13</name>
|
|
<description>Differential Inputs for Channel 13</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFF14</name>
|
|
<description>Differential Inputs for Channel 14</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFF15</name>
|
|
<description>Differential Inputs for Channel 15</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>CDR[%s]</name>
|
|
<description>Channel Data Register</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Converted Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACR</name>
|
|
<description>Analog Control Register</description>
|
|
<addressOffset>0x00000094</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000100</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSON</name>
|
|
<description>Temperature Sensor On</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IBCTL</name>
|
|
<description>ADC Bias Current Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPMR</name>
|
|
<description>Write Protection Mode Register</description>
|
|
<addressOffset>0x000000E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPKEY</name>
|
|
<description>Write Protection Key</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0</description>
|
|
<value>0x414443</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPSR</name>
|
|
<description>Write Protection Status Register</description>
|
|
<addressOffset>0x000000E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPVS</name>
|
|
<description>Write Protection Violation Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPVSRC</name>
|
|
<description>Write Protection Violation Source</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RPR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXPTR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<description>Receive Counter Register</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCTR</name>
|
|
<description>Receive Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNPR</name>
|
|
<description>Receive Next Pointer Register</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNPTR</name>
|
|
<description>Receive Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNCR</name>
|
|
<description>Receive Next Counter Register</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNCTR</name>
|
|
<description>Receive Next Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTCR</name>
|
|
<description>Transfer Control Register</description>
|
|
<addressOffset>0x00000120</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXTDIS</name>
|
|
<description>Receiver Transfer Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTDIS</name>
|
|
<description>Transmitter Transfer Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTSR</name>
|
|
<description>Transfer Status Register</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DACC</name>
|
|
<version>6461K</version>
|
|
<description>Digital-to-Analog Converter Controller</description>
|
|
<prependToName>DACC_</prependToName>
|
|
<baseAddress>0x4003C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DACC</name>
|
|
<value>30</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MR</name>
|
|
<description>Mode Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRGEN</name>
|
|
<description>Trigger Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>External trigger mode disabled. DACC in free-running mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>External trigger mode enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRGSEL</name>
|
|
<description>Trigger Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TRGSEL0</name>
|
|
<description>External trigger</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRGSEL1</name>
|
|
<description>TIO Output of the Timer Counter Channel 0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRGSEL2</name>
|
|
<description>TIO Output of the Timer Counter Channel 1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRGSEL3</name>
|
|
<description>TIO Output of the Timer Counter Channel 2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRGSEL4</name>
|
|
<description>PWM Event Line 0</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRGSEL5</name>
|
|
<description>PWM Event Line 1</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WORD</name>
|
|
<description>Word Transfer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALF</name>
|
|
<description>Half-word transfer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WORD</name>
|
|
<description>Word transfer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONE</name>
|
|
<description>Must Be Set to 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USER_SEL</name>
|
|
<description>User Channel Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CHANNEL0</name>
|
|
<description>Channel 0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHANNEL1</name>
|
|
<description>Channel 1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Tag Selection Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Tag selection mode disabled. Using USER_SEL to select the channel for the conversion.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Tag selection mode enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAXS</name>
|
|
<description>Maximum Speed Mode</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAXIMUM</name>
|
|
<description>Maximum speed mode enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STARTUP</name>
|
|
<description>Startup Time Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>0 periods of peripheral clock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8</name>
|
|
<description>8 periods of peripheral clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16</name>
|
|
<description>16 periods of peripheral clock</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>24</name>
|
|
<description>24 periods of peripheral clock</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64</name>
|
|
<description>64 periods of peripheral clock</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>80</name>
|
|
<description>80 periods of peripheral clock</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>96</name>
|
|
<description>96 periods of peripheral clock</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>112</name>
|
|
<description>112 periods of peripheral clock</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512</name>
|
|
<description>512 periods of peripheral clock</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>576</name>
|
|
<description>576 periods of peripheral clock</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>640</name>
|
|
<description>640 periods of peripheral clock</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>704</name>
|
|
<description>704 periods of peripheral clock</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>768</name>
|
|
<description>768 periods of peripheral clock</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>832</name>
|
|
<description>832 periods of peripheral clock</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>896</name>
|
|
<description>896 periods of peripheral clock</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>960</name>
|
|
<description>960 periods of peripheral clock</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1024</name>
|
|
<description>1024 periods of peripheral clock</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1088</name>
|
|
<description>1088 periods of peripheral clock</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1152</name>
|
|
<description>1152 periods of peripheral clock</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1216</name>
|
|
<description>1216 periods of peripheral clock</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1280</name>
|
|
<description>1280 periods of peripheral clock</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1344</name>
|
|
<description>1344 periods of peripheral clock</description>
|
|
<value>0x15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1408</name>
|
|
<description>1408 periods of peripheral clock</description>
|
|
<value>0x16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1472</name>
|
|
<description>1472 periods of peripheral clock</description>
|
|
<value>0x17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1536</name>
|
|
<description>1536 periods of peripheral clock</description>
|
|
<value>0x18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1600</name>
|
|
<description>1600 periods of peripheral clock</description>
|
|
<value>0x19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1664</name>
|
|
<description>1664 periods of peripheral clock</description>
|
|
<value>0x1A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1728</name>
|
|
<description>1728 periods of peripheral clock</description>
|
|
<value>0x1B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1792</name>
|
|
<description>1792 periods of peripheral clock</description>
|
|
<value>0x1C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1856</name>
|
|
<description>1856 periods of peripheral clock</description>
|
|
<value>0x1D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1920</name>
|
|
<description>1920 periods of peripheral clock</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1984</name>
|
|
<description>1984 periods of peripheral clock</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2048</name>
|
|
<description>2048 periods of peripheral clock</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2112</name>
|
|
<description>2112 periods of peripheral clock</description>
|
|
<value>0x21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2176</name>
|
|
<description>2176 periods of peripheral clock</description>
|
|
<value>0x22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2240</name>
|
|
<description>2240 periods of peripheral clock</description>
|
|
<value>0x23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2304</name>
|
|
<description>2304 periods of peripheral clock</description>
|
|
<value>0x24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2368</name>
|
|
<description>2368 periods of peripheral clock</description>
|
|
<value>0x25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2432</name>
|
|
<description>2432 periods of peripheral clock</description>
|
|
<value>0x26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2496</name>
|
|
<description>2496 periods of peripheral clock</description>
|
|
<value>0x27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2560</name>
|
|
<description>2560 periods of peripheral clock</description>
|
|
<value>0x28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2624</name>
|
|
<description>2624 periods of peripheral clock</description>
|
|
<value>0x29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2688</name>
|
|
<description>2688 periods of peripheral clock</description>
|
|
<value>0x2A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2752</name>
|
|
<description>2752 periods of peripheral clock</description>
|
|
<value>0x2B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2816</name>
|
|
<description>2816 periods of peripheral clock</description>
|
|
<value>0x2C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2880</name>
|
|
<description>2880 periods of peripheral clock</description>
|
|
<value>0x2D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2944</name>
|
|
<description>2944 periods of peripheral clock</description>
|
|
<value>0x2E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3008</name>
|
|
<description>3008 periods of peripheral clock</description>
|
|
<value>0x2F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3072</name>
|
|
<description>3072 periods of peripheral clock</description>
|
|
<value>0x30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3136</name>
|
|
<description>3136 periods of peripheral clock</description>
|
|
<value>0x31</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3200</name>
|
|
<description>3200 periods of peripheral clock</description>
|
|
<value>0x32</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3264</name>
|
|
<description>3264 periods of peripheral clock</description>
|
|
<value>0x33</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3328</name>
|
|
<description>3328 periods of peripheral clock</description>
|
|
<value>0x34</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3392</name>
|
|
<description>3392 periods of peripheral clock</description>
|
|
<value>0x35</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3456</name>
|
|
<description>3456 periods of peripheral clock</description>
|
|
<value>0x36</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3520</name>
|
|
<description>3520 periods of peripheral clock</description>
|
|
<value>0x37</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3584</name>
|
|
<description>3584 periods of peripheral clock</description>
|
|
<value>0x38</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3648</name>
|
|
<description>3648 periods of peripheral clock</description>
|
|
<value>0x39</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3712</name>
|
|
<description>3712 periods of peripheral clock</description>
|
|
<value>0x3A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3776</name>
|
|
<description>3776 periods of peripheral clock</description>
|
|
<value>0x3B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3840</name>
|
|
<description>3840 periods of peripheral clock</description>
|
|
<value>0x3C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3904</name>
|
|
<description>3904 periods of peripheral clock</description>
|
|
<value>0x3D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3968</name>
|
|
<description>3968 periods of peripheral clock</description>
|
|
<value>0x3E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4032</name>
|
|
<description>4032 periods of peripheral clock</description>
|
|
<value>0x3F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHER</name>
|
|
<description>Channel Enable Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHDR</name>
|
|
<description>Channel Disable Register</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHSR</name>
|
|
<description>Channel Status Register</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CDR</name>
|
|
<description>Conversion Data Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data to Convert</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC</name>
|
|
<description>End of Conversion Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Ready Interrupt Disable.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC</name>
|
|
<description>End of Conversion Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Ready Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC</name>
|
|
<description>End of Conversion Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmit Buffer Interrupt Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<description>Interrupt Status Register</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmit Ready Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOC</name>
|
|
<description>End of Conversion Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of DMA Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmit Buffer Empty</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACR</name>
|
|
<description>Analog Current Register</description>
|
|
<addressOffset>0x00000094</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IBCTLCH0</name>
|
|
<description>Analog Output Current Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IBCTLCH1</name>
|
|
<description>Analog Output Current Control</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IBCTLDACCORE</name>
|
|
<description>Bias Current Control for DAC Core</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPMR</name>
|
|
<description>Write Protection Mode Register</description>
|
|
<addressOffset>0x000000E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPKEY</name>
|
|
<description>Write Protection Key</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.</description>
|
|
<value>0x444143</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPSR</name>
|
|
<description>Write Protection Status Register</description>
|
|
<addressOffset>0x000000E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPVS</name>
|
|
<description>Write Protection Violation Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPVSRC</name>
|
|
<description>Write Protection Violation Source</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPR</name>
|
|
<description>Transmit Pointer Register</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXPTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<addressOffset>0x0000010C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNPR</name>
|
|
<description>Transmit Next Pointer Register</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNPTR</name>
|
|
<description>Transmit Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNCR</name>
|
|
<description>Transmit Next Counter Register</description>
|
|
<addressOffset>0x0000011C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNCTR</name>
|
|
<description>Transmit Counter Next</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTCR</name>
|
|
<description>Transfer Control Register</description>
|
|
<addressOffset>0x00000120</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXTDIS</name>
|
|
<description>Receiver Transfer Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTDIS</name>
|
|
<description>Transmitter Transfer Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTSR</name>
|
|
<description>Transfer Status Register</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ACC</name>
|
|
<version>6490G</version>
|
|
<description>Analog Comparator Controller</description>
|
|
<prependToName>ACC_</prependToName>
|
|
<baseAddress>0x40040000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ACC</name>
|
|
<value>33</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MR</name>
|
|
<description>Mode Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SELMINUS</name>
|
|
<description>Selection for Minus Comparator Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TS</name>
|
|
<description>Select TS</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADVREF</name>
|
|
<description>Select ADVREF</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Select DAC0</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC1</name>
|
|
<description>Select DAC1</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD0</name>
|
|
<description>Select AD0</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD1</name>
|
|
<description>Select AD1</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD2</name>
|
|
<description>Select AD2</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD3</name>
|
|
<description>Select AD3</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELPLUS</name>
|
|
<description>Selection For Plus Comparator Input</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AD0</name>
|
|
<description>Select AD0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD1</name>
|
|
<description>Select AD1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD2</name>
|
|
<description>Select AD2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD3</name>
|
|
<description>Select AD3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD4</name>
|
|
<description>Select AD4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD5</name>
|
|
<description>Select AD5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD6</name>
|
|
<description>Select AD6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD7</name>
|
|
<description>Select AD7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACEN</name>
|
|
<description>Analog Comparator Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Analog comparator disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Analog comparator enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGETYP</name>
|
|
<description>Edge Type</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Only rising edge of comparator output</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edge of comparator output</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANY</name>
|
|
<description>Any edge of comparator output</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert Comparator Output</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>Analog comparator output is directly processed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>Analog comparator output is inverted prior to being processed.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELFS</name>
|
|
<description>Selection Of Fault Source</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CE</name>
|
|
<description>The CE flag is used to drive the FAULT output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT</name>
|
|
<description>The output of the analog comparator flag is used to drive the FAULT output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Fault Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>The FAULT output is tied to 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>The FAULT output is driven by the signal defined by SELFS.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CE</name>
|
|
<description>Comparison Edge</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CE</name>
|
|
<description>Comparison Edge</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CE</name>
|
|
<description>Comparison Edge</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<description>Interrupt Status Register</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CE</name>
|
|
<description>Comparison Edge (cleared on read)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCO</name>
|
|
<description>Synchronized Comparator Output</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Flag Mask</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACR</name>
|
|
<description>Analog Control Register</description>
|
|
<addressOffset>0x00000094</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ISEL</name>
|
|
<description>Current Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOPW</name>
|
|
<description>Low-power option.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HISP</name>
|
|
<description>High-speed option.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>Hysteresis Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPMR</name>
|
|
<description>Write Protection Mode Register</description>
|
|
<addressOffset>0x000000E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPKEY</name>
|
|
<description>Write Protection Key</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.</description>
|
|
<value>0x414343</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPSR</name>
|
|
<description>Write Protection Status Register</description>
|
|
<addressOffset>0x000000E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPVS</name>
|
|
<description>Write Protection Violation Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CRCCU</name>
|
|
<version>11001I</version>
|
|
<description>Cyclic Redundancy Check Calculation Unit</description>
|
|
<prependToName>CRCCU_</prependToName>
|
|
<baseAddress>0x40044000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CRCCU</name>
|
|
<value>32</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>DSCR</name>
|
|
<description>CRCCU Descriptor Base Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DSCR</name>
|
|
<description>Descriptor Base Address</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>23</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_EN</name>
|
|
<description>CRCCU DMA Enable Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_DIS</name>
|
|
<description>CRCCU DMA Disable Register</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DMADIS</name>
|
|
<description>DMA Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_SR</name>
|
|
<description>CRCCU DMA Status Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMASR</name>
|
|
<description>DMA Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_IER</name>
|
|
<description>CRCCU DMA Interrupt Enable Register</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DMAIER</name>
|
|
<description>Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_IDR</name>
|
|
<description>CRCCU DMA Interrupt Disable Register</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DMAIDR</name>
|
|
<description>Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_IMR</name>
|
|
<description>CRCCU DMA Interrupt Mask Register</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAIMR</name>
|
|
<description>Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_ISR</name>
|
|
<description>CRCCU DMA Interrupt Status Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAISR</name>
|
|
<description>Interrupt Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>CRCCU Control Register</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>CRC Computation Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MR</name>
|
|
<description>CRCCU Mode Register</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>CRC Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMPARE</name>
|
|
<description>CRC Compare</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PTYPE</name>
|
|
<description>Primitive Polynomial</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CCITT8023</name>
|
|
<description>Polynom 0x04C11DB7</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CASTAGNOLI</name>
|
|
<description>Polynom 0x1EDC6F41</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCITT16</name>
|
|
<description>Polynom 0x1021</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIVIDER</name>
|
|
<description>Request Divider</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>CRCCU Status Register</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CRC</name>
|
|
<description>Cyclic Redundancy Check Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>CRCCU Interrupt Enable Register</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>ERRIER</name>
|
|
<description>CRC Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>CRCCU Interrupt Disable Register</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>ERRIDR</name>
|
|
<description>CRC Error Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>CRCCU Interrupt Mask Register</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ERRIMR</name>
|
|
<description>CRC Error Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<description>CRCCU Interrupt Status Register</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ERRISR</name>
|
|
<description>CRC Error Interrupt Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MATRIX</name>
|
|
<version>6499B</version>
|
|
<description>AHB Bus Matrix</description>
|
|
<baseAddress>0x400E0200</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x200</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>MATRIX_MCFG[%s]</name>
|
|
<description>Master Configuration Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>ULBT</name>
|
|
<description>Undefined Length Burst Type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INFINITE</name>
|
|
<description>No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SINGLE</name>
|
|
<description>The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR_BEAT</name>
|
|
<description>The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EIGHT_BEAT</name>
|
|
<description>The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SIXTEEN_BEAT</name>
|
|
<description>The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<dimIndex>0-4</dimIndex>
|
|
<name>MATRIX_SCFG[%s]</name>
|
|
<description>Slave Configuration Register</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>SLOT_CYCLE</name>
|
|
<description>Maximum Number of Allowed Cycles for a Burst</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEFMSTR_TYPE</name>
|
|
<description>Default Master Type</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_DEFAULT</name>
|
|
<description>At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LAST</name>
|
|
<description>At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FIXED</name>
|
|
<description>At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIXED_DEFMSTR</name>
|
|
<description>Fixed Default Master</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBT</name>
|
|
<description>Arbitration Type</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ROUND_ROBIN</name>
|
|
<description>Round-robin arbitration</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FIXED_PRIORITY</name>
|
|
<description>Fixed priority arbitration</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MATRIX_PRAS0</name>
|
|
<description>Priority Register A for Slave 0</description>
|
|
<addressOffset>0x00000080</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M0PR</name>
|
|
<description>Master 0 Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M1PR</name>
|
|
<description>Master 1 Priority</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M2PR</name>
|
|
<description>Master 2 Priority</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M3PR</name>
|
|
<description>Master 3 Priority</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M4PR</name>
|
|
<description>Master 4 Priority</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MATRIX_PRAS1</name>
|
|
<description>Priority Register A for Slave 1</description>
|
|
<addressOffset>0x00000088</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M0PR</name>
|
|
<description>Master 0 Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M1PR</name>
|
|
<description>Master 1 Priority</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M2PR</name>
|
|
<description>Master 2 Priority</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M3PR</name>
|
|
<description>Master 3 Priority</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M4PR</name>
|
|
<description>Master 4 Priority</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MATRIX_PRAS2</name>
|
|
<description>Priority Register A for Slave 2</description>
|
|
<addressOffset>0x00000090</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M0PR</name>
|
|
<description>Master 0 Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M1PR</name>
|
|
<description>Master 1 Priority</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M2PR</name>
|
|
<description>Master 2 Priority</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M3PR</name>
|
|
<description>Master 3 Priority</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M4PR</name>
|
|
<description>Master 4 Priority</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MATRIX_PRAS3</name>
|
|
<description>Priority Register A for Slave 3</description>
|
|
<addressOffset>0x00000098</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M0PR</name>
|
|
<description>Master 0 Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M1PR</name>
|
|
<description>Master 1 Priority</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M2PR</name>
|
|
<description>Master 2 Priority</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M3PR</name>
|
|
<description>Master 3 Priority</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M4PR</name>
|
|
<description>Master 4 Priority</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MATRIX_PRAS4</name>
|
|
<description>Priority Register A for Slave 4</description>
|
|
<addressOffset>0x000000A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M0PR</name>
|
|
<description>Master 0 Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M1PR</name>
|
|
<description>Master 1 Priority</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M2PR</name>
|
|
<description>Master 2 Priority</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M3PR</name>
|
|
<description>Master 3 Priority</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M4PR</name>
|
|
<description>Master 4 Priority</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCFG_SYSIO</name>
|
|
<description>System I/O Configuration register</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SYSIO4</name>
|
|
<description>PB4 or TDI Assignment</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SYSIO5</name>
|
|
<description>PB5 or TDO/TRACESWO Assignment</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SYSIO6</name>
|
|
<description>PB6 or TMS/SWDIO Assignment</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SYSIO7</name>
|
|
<description>PB7 or TCK/SWCLK Assignment</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SYSIO10</name>
|
|
<description>PB10 or DDM Assignment</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SYSIO11</name>
|
|
<description>PB11 or DDP Assignment</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SYSIO12</name>
|
|
<description>PB12 or ERASE Assignment</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCFG_SMCNFCS</name>
|
|
<description>SMC Chip Select NAND Flash Assignment Register</description>
|
|
<addressOffset>0x0000011C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMC_NFCS0</name>
|
|
<description>SMC NAND Flash Chip Select 0 Assignment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SMC_NFCS1</name>
|
|
<description>SMC NAND Flash Chip Select 1 Assignment</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SMC_NFCS2</name>
|
|
<description>SMC NAND Flash Chip Select 2 Assignment</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SMC_NFCS3</name>
|
|
<description>SMC NAND Flash Chip Select 3 Assignment</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MATRIX_WPMR</name>
|
|
<description>Write Protection Mode Register</description>
|
|
<addressOffset>0x000001E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPKEY</name>
|
|
<description>Write Protect Key</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.</description>
|
|
<value>0x4D4154</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MATRIX_WPSR</name>
|
|
<description>Write Protection Status Register</description>
|
|
<addressOffset>0x000001E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPVS</name>
|
|
<description>Write Protection Violation Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPVSRC</name>
|
|
<description>Write Protection Violation Source</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PMC</name>
|
|
<version>11116V</version>
|
|
<description>Power Management Controller</description>
|
|
<baseAddress>0x400E0400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x140</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PMC</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PMC_SCER</name>
|
|
<description>System Clock Enable Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>UDP</name>
|
|
<description>USB Device Port Clock Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCK0</name>
|
|
<description>Programmable Clock 0 Output Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCK1</name>
|
|
<description>Programmable Clock 1 Output Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCK2</name>
|
|
<description>Programmable Clock 2 Output Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_SCDR</name>
|
|
<description>System Clock Disable Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>UDP</name>
|
|
<description>USB Device Port Clock Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCK0</name>
|
|
<description>Programmable Clock 0 Output Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCK1</name>
|
|
<description>Programmable Clock 1 Output Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCK2</name>
|
|
<description>Programmable Clock 2 Output Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_SCSR</name>
|
|
<description>System Clock Status Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UDP</name>
|
|
<description>USB Device Port Clock Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCK0</name>
|
|
<description>Programmable Clock 0 Output Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCK1</name>
|
|
<description>Programmable Clock 1 Output Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCK2</name>
|
|
<description>Programmable Clock 2 Output Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_PCER0</name>
|
|
<description>Peripheral Clock Enable Register 0</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PID8</name>
|
|
<description>Peripheral Clock 8 Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID9</name>
|
|
<description>Peripheral Clock 9 Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID10</name>
|
|
<description>Peripheral Clock 10 Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID11</name>
|
|
<description>Peripheral Clock 11 Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID12</name>
|
|
<description>Peripheral Clock 12 Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID13</name>
|
|
<description>Peripheral Clock 13 Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID14</name>
|
|
<description>Peripheral Clock 14 Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID15</name>
|
|
<description>Peripheral Clock 15 Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID16</name>
|
|
<description>Peripheral Clock 16 Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID17</name>
|
|
<description>Peripheral Clock 17 Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID18</name>
|
|
<description>Peripheral Clock 18 Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID19</name>
|
|
<description>Peripheral Clock 19 Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID20</name>
|
|
<description>Peripheral Clock 20 Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID21</name>
|
|
<description>Peripheral Clock 21 Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID22</name>
|
|
<description>Peripheral Clock 22 Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID23</name>
|
|
<description>Peripheral Clock 23 Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID24</name>
|
|
<description>Peripheral Clock 24 Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID25</name>
|
|
<description>Peripheral Clock 25 Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID26</name>
|
|
<description>Peripheral Clock 26 Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID27</name>
|
|
<description>Peripheral Clock 27 Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID28</name>
|
|
<description>Peripheral Clock 28 Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID29</name>
|
|
<description>Peripheral Clock 29 Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID30</name>
|
|
<description>Peripheral Clock 30 Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID31</name>
|
|
<description>Peripheral Clock 31 Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_PCDR0</name>
|
|
<description>Peripheral Clock Disable Register 0</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PID8</name>
|
|
<description>Peripheral Clock 8 Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID9</name>
|
|
<description>Peripheral Clock 9 Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID10</name>
|
|
<description>Peripheral Clock 10 Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID11</name>
|
|
<description>Peripheral Clock 11 Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID12</name>
|
|
<description>Peripheral Clock 12 Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID13</name>
|
|
<description>Peripheral Clock 13 Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID14</name>
|
|
<description>Peripheral Clock 14 Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID15</name>
|
|
<description>Peripheral Clock 15 Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID16</name>
|
|
<description>Peripheral Clock 16 Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID17</name>
|
|
<description>Peripheral Clock 17 Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID18</name>
|
|
<description>Peripheral Clock 18 Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID19</name>
|
|
<description>Peripheral Clock 19 Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID20</name>
|
|
<description>Peripheral Clock 20 Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID21</name>
|
|
<description>Peripheral Clock 21 Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID22</name>
|
|
<description>Peripheral Clock 22 Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID23</name>
|
|
<description>Peripheral Clock 23 Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID24</name>
|
|
<description>Peripheral Clock 24 Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID25</name>
|
|
<description>Peripheral Clock 25 Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID26</name>
|
|
<description>Peripheral Clock 26 Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID27</name>
|
|
<description>Peripheral Clock 27 Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID28</name>
|
|
<description>Peripheral Clock 28 Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID29</name>
|
|
<description>Peripheral Clock 29 Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID30</name>
|
|
<description>Peripheral Clock 30 Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID31</name>
|
|
<description>Peripheral Clock 31 Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_PCSR0</name>
|
|
<description>Peripheral Clock Status Register 0</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PID8</name>
|
|
<description>Peripheral Clock 8 Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID9</name>
|
|
<description>Peripheral Clock 9 Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID10</name>
|
|
<description>Peripheral Clock 10 Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID11</name>
|
|
<description>Peripheral Clock 11 Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID12</name>
|
|
<description>Peripheral Clock 12 Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID13</name>
|
|
<description>Peripheral Clock 13 Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID14</name>
|
|
<description>Peripheral Clock 14 Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID15</name>
|
|
<description>Peripheral Clock 15 Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID16</name>
|
|
<description>Peripheral Clock 16 Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID17</name>
|
|
<description>Peripheral Clock 17 Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID18</name>
|
|
<description>Peripheral Clock 18 Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID19</name>
|
|
<description>Peripheral Clock 19 Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID20</name>
|
|
<description>Peripheral Clock 20 Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID21</name>
|
|
<description>Peripheral Clock 21 Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID22</name>
|
|
<description>Peripheral Clock 22 Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID23</name>
|
|
<description>Peripheral Clock 23 Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID24</name>
|
|
<description>Peripheral Clock 24 Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID25</name>
|
|
<description>Peripheral Clock 25 Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID26</name>
|
|
<description>Peripheral Clock 26 Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID27</name>
|
|
<description>Peripheral Clock 27 Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID28</name>
|
|
<description>Peripheral Clock 28 Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID29</name>
|
|
<description>Peripheral Clock 29 Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID30</name>
|
|
<description>Peripheral Clock 30 Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID31</name>
|
|
<description>Peripheral Clock 31 Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CKGR_MOR</name>
|
|
<description>Main Oscillator Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000008</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MOSCXTEN</name>
|
|
<description>Main Crystal Oscillator Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MOSCXTBY</name>
|
|
<description>Main Crystal Oscillator Bypass</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAITMODE</name>
|
|
<description>Wait Mode Command (Write-only)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MOSCRCEN</name>
|
|
<description>Main On-Chip RC Oscillator Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MOSCRCF</name>
|
|
<description>Main On-Chip RC Oscillator Frequency Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>4_MHz</name>
|
|
<description>The fast RC oscillator frequency is at 4 MHz (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_MHz</name>
|
|
<description>The fast RC oscillator frequency is at 8 MHz</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>12_MHz</name>
|
|
<description>The fast RC oscillator frequency is at 12 MHz</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MOSCXTST</name>
|
|
<description>Main Crystal Oscillator Start-up Time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Write Access Password</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation.Always reads as 0.</description>
|
|
<value>0x37</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MOSCSEL</name>
|
|
<description>Main Oscillator Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CFDEN</name>
|
|
<description>Clock Failure Detector Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CKGR_MCFR</name>
|
|
<description>Main Clock Frequency Register</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MAINF</name>
|
|
<description>Main Clock Frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAINFRDY</name>
|
|
<description>Main Clock Frequency Measure Ready</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RCMEAS</name>
|
|
<description>RC Oscillator Frequency Measure (write-only)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CKGR_PLLAR</name>
|
|
<description>PLLA Register</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00003F00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIVA</name>
|
|
<description>PLLA Front_End Divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLACOUNT</name>
|
|
<description>PLLA Counter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MULA</name>
|
|
<description>PLLA Multiplier</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ONE</name>
|
|
<description>Must Be Set to 1</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CKGR_PLLBR</name>
|
|
<description>PLLB Register</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00003F00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIVB</name>
|
|
<description>PLLB Front-End Divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLBCOUNT</name>
|
|
<description>PLLB Counter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MULB</name>
|
|
<description>PLLB Multiplier</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_MCKR</name>
|
|
<description>Master Clock Register</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CSS</name>
|
|
<description>Master Clock Source Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLOW_CLK</name>
|
|
<description>Slow Clock is selected</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAIN_CLK</name>
|
|
<description>Main Clock is selected</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLLA_CLK</name>
|
|
<description>PLLA Clock is selected</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLLB_CLK</name>
|
|
<description>PLLBClock is selected</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRES</name>
|
|
<description>Processor Clock Prescaler</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLK_1</name>
|
|
<description>Selected clock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_2</name>
|
|
<description>Selected clock divided by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_4</name>
|
|
<description>Selected clock divided by 4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_8</name>
|
|
<description>Selected clock divided by 8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_16</name>
|
|
<description>Selected clock divided by 16</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_32</name>
|
|
<description>Selected clock divided by 32</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_64</name>
|
|
<description>Selected clock divided by 64</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_3</name>
|
|
<description>Selected clock divided by 3</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLLADIV2</name>
|
|
<description>PLLA Divisor by 2</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLBDIV2</name>
|
|
<description>PLLB Divisor by 2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_USB</name>
|
|
<description>USB Clock Register</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>USBS</name>
|
|
<description>USB Input Clock Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBDIV</name>
|
|
<description>Divider for USB Clock</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>PMC_PCK[%s]</name>
|
|
<description>Programmable Clock 0 Register</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>CSS</name>
|
|
<description>Master Clock Source Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLOW_CLK</name>
|
|
<description>Slow Clock is selected</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAIN_CLK</name>
|
|
<description>Main Clock is selected</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLLA_CLK</name>
|
|
<description>PLLA Clock is selected</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLLB_CLK</name>
|
|
<description>PLLB Clock is selected</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCK</name>
|
|
<description>Master Clock is selected</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRES</name>
|
|
<description>Programmable Clock Prescaler</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLK_1</name>
|
|
<description>Selected clock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_2</name>
|
|
<description>Selected clock divided by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_4</name>
|
|
<description>Selected clock divided by 4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_8</name>
|
|
<description>Selected clock divided by 8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_16</name>
|
|
<description>Selected clock divided by 16</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_32</name>
|
|
<description>Selected clock divided by 32</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_64</name>
|
|
<description>Selected clock divided by 64</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00000060</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>MOSCXTS</name>
|
|
<description>Main Crystal Oscillator Status Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCKA</name>
|
|
<description>PLLA Lock Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCKB</name>
|
|
<description>PLLB Lock Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MCKRDY</name>
|
|
<description>Master Clock Ready Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCKRDY0</name>
|
|
<description>Programmable Clock Ready 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCKRDY1</name>
|
|
<description>Programmable Clock Ready 1 Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCKRDY2</name>
|
|
<description>Programmable Clock Ready 2 Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MOSCSELS</name>
|
|
<description>Main Oscillator Selection Status Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MOSCRCS</name>
|
|
<description>Main On-Chip RC Status Interrupt Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CFDEV</name>
|
|
<description>Clock Failure Detector Event Interrupt Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_IDR</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<addressOffset>0x00000064</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>MOSCXTS</name>
|
|
<description>Main Crystal Oscillator Status Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCKA</name>
|
|
<description>PLLA Lock Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCKB</name>
|
|
<description>PLLB Lock Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MCKRDY</name>
|
|
<description>Master Clock Ready Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCKRDY0</name>
|
|
<description>Programmable Clock Ready 0 Interrupt Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCKRDY1</name>
|
|
<description>Programmable Clock Ready 1 Interrupt Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCKRDY2</name>
|
|
<description>Programmable Clock Ready 2 Interrupt Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MOSCSELS</name>
|
|
<description>Main Oscillator Selection Status Interrupt Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MOSCRCS</name>
|
|
<description>Main On-Chip RC Status Interrupt Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CFDEV</name>
|
|
<description>Clock Failure Detector Event Interrupt Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00000068</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00030008</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MOSCXTS</name>
|
|
<description>Main Crystal Oscillator Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCKA</name>
|
|
<description>PLLA Lock Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCKB</name>
|
|
<description>PLLB Lock Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MCKRDY</name>
|
|
<description>Master Clock Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSCSELS</name>
|
|
<description>Slow Clock Oscillator Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCKRDY0</name>
|
|
<description>Programmable Clock Ready Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCKRDY1</name>
|
|
<description>Programmable Clock Ready Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCKRDY2</name>
|
|
<description>Programmable Clock Ready Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MOSCSELS</name>
|
|
<description>Main Oscillator Selection Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MOSCRCS</name>
|
|
<description>Main On-Chip RC Oscillator Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CFDEV</name>
|
|
<description>Clock Failure Detector Event</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CFDS</name>
|
|
<description>Clock Failure Detector Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FOS</name>
|
|
<description>Clock Failure Detector Fault Output Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x0000006C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MOSCXTS</name>
|
|
<description>Main Crystal Oscillator Status Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCKA</name>
|
|
<description>PLLA Lock Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCKB</name>
|
|
<description>PLLB Lock Interrupt Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MCKRDY</name>
|
|
<description>Master Clock Ready Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCKRDY0</name>
|
|
<description>Programmable Clock Ready 0 Interrupt Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCKRDY1</name>
|
|
<description>Programmable Clock Ready 1 Interrupt Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCKRDY2</name>
|
|
<description>Programmable Clock Ready 2 Interrupt Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MOSCSELS</name>
|
|
<description>Main Oscillator Selection Status Interrupt Mask</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MOSCRCS</name>
|
|
<description>Main On-Chip RC Status Interrupt Mask</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CFDEV</name>
|
|
<description>Clock Failure Detector Event Interrupt Mask</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_FSMR</name>
|
|
<description>Fast Startup Mode Register</description>
|
|
<addressOffset>0x00000070</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FSTT0</name>
|
|
<description>Fast Startup Input Enable 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTT1</name>
|
|
<description>Fast Startup Input Enable 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTT2</name>
|
|
<description>Fast Startup Input Enable 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTT3</name>
|
|
<description>Fast Startup Input Enable 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTT4</name>
|
|
<description>Fast Startup Input Enable 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTT5</name>
|
|
<description>Fast Startup Input Enable 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTT6</name>
|
|
<description>Fast Startup Input Enable 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTT7</name>
|
|
<description>Fast Startup Input Enable 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTT8</name>
|
|
<description>Fast Startup Input Enable 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTT9</name>
|
|
<description>Fast Startup Input Enable 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTT10</name>
|
|
<description>Fast Startup Input Enable 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTT11</name>
|
|
<description>Fast Startup Input Enable 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTT12</name>
|
|
<description>Fast Startup Input Enable 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTT13</name>
|
|
<description>Fast Startup Input Enable 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTT14</name>
|
|
<description>Fast Startup Input Enable 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTT15</name>
|
|
<description>Fast Startup Input Enable 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTTAL</name>
|
|
<description>RTT Alarm Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTCAL</name>
|
|
<description>RTC Alarm Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBAL</name>
|
|
<description>USB Alarm Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LPM</name>
|
|
<description>Low-power Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FLPM</name>
|
|
<description>Flash Low-power Mode</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLASH_STANDBY</name>
|
|
<description>Flash is in Standby Mode when system enters Wait Mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_DEEP_POWERDOWN</name>
|
|
<description>Flash is in Deep-power-down mode when system enters Wait Mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_IDLE</name>
|
|
<description>Idle mode</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_FSPR</name>
|
|
<description>Fast Startup Polarity Register</description>
|
|
<addressOffset>0x00000074</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FSTP0</name>
|
|
<description>Fast Startup Input Polarityx</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTP1</name>
|
|
<description>Fast Startup Input Polarityx</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTP2</name>
|
|
<description>Fast Startup Input Polarityx</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTP3</name>
|
|
<description>Fast Startup Input Polarityx</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTP4</name>
|
|
<description>Fast Startup Input Polarityx</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTP5</name>
|
|
<description>Fast Startup Input Polarityx</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTP6</name>
|
|
<description>Fast Startup Input Polarityx</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTP7</name>
|
|
<description>Fast Startup Input Polarityx</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTP8</name>
|
|
<description>Fast Startup Input Polarityx</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTP9</name>
|
|
<description>Fast Startup Input Polarityx</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTP10</name>
|
|
<description>Fast Startup Input Polarityx</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTP11</name>
|
|
<description>Fast Startup Input Polarityx</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTP12</name>
|
|
<description>Fast Startup Input Polarityx</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTP13</name>
|
|
<description>Fast Startup Input Polarityx</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTP14</name>
|
|
<description>Fast Startup Input Polarityx</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTP15</name>
|
|
<description>Fast Startup Input Polarityx</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_FOCR</name>
|
|
<description>Fault Output Clear Register</description>
|
|
<addressOffset>0x00000078</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>FOCLR</name>
|
|
<description>Fault Output Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_WPMR</name>
|
|
<description>Write Protection Mode Register</description>
|
|
<addressOffset>0x000000E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPKEY</name>
|
|
<description>Write Protection Key</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.</description>
|
|
<value>0x504D43</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_WPSR</name>
|
|
<description>Write Protection Status Register</description>
|
|
<addressOffset>0x000000E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPVS</name>
|
|
<description>Write Protection Violation Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPVSRC</name>
|
|
<description>Write Protection Violation Source</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_PCER1</name>
|
|
<description>Peripheral Clock Enable Register 1</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PID32</name>
|
|
<description>Peripheral Clock 32 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID33</name>
|
|
<description>Peripheral Clock 33 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID34</name>
|
|
<description>Peripheral Clock 34 Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_PCDR1</name>
|
|
<description>Peripheral Clock Disable Register 1</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PID32</name>
|
|
<description>Peripheral Clock 32 Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID33</name>
|
|
<description>Peripheral Clock 33 Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID34</name>
|
|
<description>Peripheral Clock 34 Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_PCSR1</name>
|
|
<description>Peripheral Clock Status Register 1</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PID32</name>
|
|
<description>Peripheral Clock 32 Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID33</name>
|
|
<description>Peripheral Clock 33 Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PID34</name>
|
|
<description>Peripheral Clock 34 Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMC_OCR</name>
|
|
<description>Oscillator Calibration Register</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00404040</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CAL4</name>
|
|
<description>RC Oscillator Calibration bits for 4 MHz</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL4</name>
|
|
<description>Selection of RC Oscillator Calibration bits for 4 MHz</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CAL8</name>
|
|
<description>RC Oscillator Calibration bits for 8 MHz</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL8</name>
|
|
<description>Selection of RC Oscillator Calibration bits for 8 MHz</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CAL12</name>
|
|
<description>RC Oscillator Calibration bits for 12 MHz</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL12</name>
|
|
<description>Selection of RC Oscillator Calibration bits for 12 MHz</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART0</name>
|
|
<version>6418O</version>
|
|
<description>Universal Asynchronous Receiver Transmitter 0</description>
|
|
<groupName>UART</groupName>
|
|
<prependToName>UART0_</prependToName>
|
|
<baseAddress>0x400E0600</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x128</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART0</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RSTRX</name>
|
|
<description>Reset Receiver</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTTX</name>
|
|
<description>Reset Transmitter</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receiver Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDIS</name>
|
|
<description>Transmitter Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTSTA</name>
|
|
<description>Reset Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MR</name>
|
|
<description>Mode Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PAR</name>
|
|
<description>Parity Type</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even Parity</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd Parity</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPACE</name>
|
|
<description>Space: parity forced to 0</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MARK</name>
|
|
<description>Mark: parity forced to 1</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No parity</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHMODE</name>
|
|
<description>Channel Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTOMATIC</name>
|
|
<description>Automatic echo</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCAL_LOOPBACK</name>
|
|
<description>Local loopback</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REMOTE_LOOPBACK</name>
|
|
<description>Remote loopback</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Enable RXRDY Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Enable TXRDY Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>Enable End of Receive Transfer Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>Enable End of Transmit Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Enable Overrun Error Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>Enable Framing Error Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARE</name>
|
|
<description>Enable Parity Error Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Enable TXEMPTY Interrupt</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Enable Buffer Empty Interrupt</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Enable Buffer Full Interrupt</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Disable RXRDY Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Disable TXRDY Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>Disable End of Receive Transfer Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>Disable End of Transmit Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Disable Overrun Error Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>Disable Framing Error Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARE</name>
|
|
<description>Disable Parity Error Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Disable TXEMPTY Interrupt</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Disable Buffer Empty Interrupt</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Disable Buffer Full Interrupt</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Mask RXRDY Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Disable TXRDY Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>Mask End of Receive Transfer Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>Mask End of Transmit Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Mask Overrun Error Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>Mask Framing Error Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARE</name>
|
|
<description>Mask Parity Error Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Mask TXEMPTY Interrupt</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Mask TXBUFE Interrupt</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Mask RXBUFF Interrupt</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receiver Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmitter Ready</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receiver Transfer</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmitter Transfer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>Framing Error</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARE</name>
|
|
<description>Parity Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Transmitter Empty</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmission Buffer Empty</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RHR</name>
|
|
<description>Receive Holding Register</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCHR</name>
|
|
<description>Received Character</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR</name>
|
|
<description>Transmit Holding Register</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TXCHR</name>
|
|
<description>Character to be Transmitted</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRGR</name>
|
|
<description>Baud Rate Generator Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CD</name>
|
|
<description>Clock Divisor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RPR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXPTR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<description>Receive Counter Register</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCTR</name>
|
|
<description>Receive Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPR</name>
|
|
<description>Transmit Pointer Register</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXPTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<addressOffset>0x0000010C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNPR</name>
|
|
<description>Receive Next Pointer Register</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNPTR</name>
|
|
<description>Receive Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNCR</name>
|
|
<description>Receive Next Counter Register</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNCTR</name>
|
|
<description>Receive Next Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNPR</name>
|
|
<description>Transmit Next Pointer Register</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNPTR</name>
|
|
<description>Transmit Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNCR</name>
|
|
<description>Transmit Next Counter Register</description>
|
|
<addressOffset>0x0000011C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNCTR</name>
|
|
<description>Transmit Counter Next</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTCR</name>
|
|
<description>Transfer Control Register</description>
|
|
<addressOffset>0x00000120</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXTDIS</name>
|
|
<description>Receiver Transfer Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTDIS</name>
|
|
<description>Transmitter Transfer Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTSR</name>
|
|
<description>Transfer Status Register</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CHIPID</name>
|
|
<version>6417ZB</version>
|
|
<description>Chip Identifier</description>
|
|
<prependToName>CHIPID_</prependToName>
|
|
<baseAddress>0x400E0740</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x200</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CIDR</name>
|
|
<description>Chip ID Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>VERSION</name>
|
|
<description>Version of the Device</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPROC</name>
|
|
<description>Embedded Processor</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ARM946ES</name>
|
|
<description>ARM946ES</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARM7TDMI</name>
|
|
<description>ARM7TDMI</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM3</name>
|
|
<description>Cortex-M3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARM920T</name>
|
|
<description>ARM920T</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARM926EJS</name>
|
|
<description>ARM926EJS</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CA5</name>
|
|
<description>Cortex-A5</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM4</name>
|
|
<description>Cortex-M4</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NVPSIZ</name>
|
|
<description>Nonvolatile Program Memory Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8K</name>
|
|
<description>8 Kbytes</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16K</name>
|
|
<description>16 Kbytes</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32K</name>
|
|
<description>32 Kbytes</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64K</name>
|
|
<description>64 Kbytes</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128K</name>
|
|
<description>128 Kbytes</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>160K</name>
|
|
<description>160 Kbytes</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256K</name>
|
|
<description>256 Kbytes</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512K</name>
|
|
<description>512 Kbytes</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1024K</name>
|
|
<description>1024 Kbytes</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2048K</name>
|
|
<description>2048 Kbytes</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NVPSIZ2</name>
|
|
<description>Second Nonvolatile Program Memory Size</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8K</name>
|
|
<description>8 Kbytes</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16K</name>
|
|
<description>16 Kbytes</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32K</name>
|
|
<description>32 Kbytes</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64K</name>
|
|
<description>64 Kbytes</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128K</name>
|
|
<description>128 Kbytes</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256K</name>
|
|
<description>256 Kbytes</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512K</name>
|
|
<description>512 Kbytes</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1024K</name>
|
|
<description>1024 Kbytes</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2048K</name>
|
|
<description>2048 Kbytes</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRAMSIZ</name>
|
|
<description>Internal SRAM Size</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>48K</name>
|
|
<description>48 Kbytes</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>192K</name>
|
|
<description>192 Kbytes</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>384K</name>
|
|
<description>384 Kbytes</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6K</name>
|
|
<description>6 Kbytes</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>24K</name>
|
|
<description>24 Kbytes</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4K</name>
|
|
<description>4 Kbytes</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>80K</name>
|
|
<description>80 Kbytes</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>160K</name>
|
|
<description>160 Kbytes</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8K</name>
|
|
<description>8 Kbytes</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16K</name>
|
|
<description>16 Kbytes</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32K</name>
|
|
<description>32 Kbytes</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64K</name>
|
|
<description>64 Kbytes</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128K</name>
|
|
<description>128 Kbytes</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256K</name>
|
|
<description>256 Kbytes</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>96K</name>
|
|
<description>96 Kbytes</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512K</name>
|
|
<description>512 Kbytes</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARCH</name>
|
|
<description>Architecture Identifier</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAM4SxA</name>
|
|
<description>SAM4SxA (48-pin version)</description>
|
|
<value>0x88</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAM4SxB</name>
|
|
<description>SAM4SxB (64-pin version)</description>
|
|
<value>0x89</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAM4SxC</name>
|
|
<description>SAM4SxC (100-pin version)</description>
|
|
<value>0x8A</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NVPTYP</name>
|
|
<description>Nonvolatile Program Memory Type</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ROM</name>
|
|
<description>ROM</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ROMLESS</name>
|
|
<description>ROMless or on-chip Flash</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH</name>
|
|
<description>Embedded Flash Memory</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ROM_FLASH</name>
|
|
<description>ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRAM</name>
|
|
<description>SRAM emulating ROM</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXT</name>
|
|
<description>Extension Flag</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXID</name>
|
|
<description>Chip ID Extension Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>EXID</name>
|
|
<description>Chip ID Extension</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART1</name>
|
|
<version>6418O</version>
|
|
<description>Universal Asynchronous Receiver Transmitter 1</description>
|
|
<groupName>UART</groupName>
|
|
<prependToName>UART1_</prependToName>
|
|
<baseAddress>0x400E0800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x128</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART1</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RSTRX</name>
|
|
<description>Reset Receiver</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTTX</name>
|
|
<description>Reset Transmitter</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receiver Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDIS</name>
|
|
<description>Transmitter Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTSTA</name>
|
|
<description>Reset Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MR</name>
|
|
<description>Mode Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PAR</name>
|
|
<description>Parity Type</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even Parity</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd Parity</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPACE</name>
|
|
<description>Space: parity forced to 0</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MARK</name>
|
|
<description>Mark: parity forced to 1</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No parity</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHMODE</name>
|
|
<description>Channel Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTOMATIC</name>
|
|
<description>Automatic echo</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCAL_LOOPBACK</name>
|
|
<description>Local loopback</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REMOTE_LOOPBACK</name>
|
|
<description>Remote loopback</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Enable RXRDY Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Enable TXRDY Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>Enable End of Receive Transfer Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>Enable End of Transmit Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Enable Overrun Error Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>Enable Framing Error Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARE</name>
|
|
<description>Enable Parity Error Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Enable TXEMPTY Interrupt</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Enable Buffer Empty Interrupt</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Enable Buffer Full Interrupt</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Disable RXRDY Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Disable TXRDY Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>Disable End of Receive Transfer Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>Disable End of Transmit Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Disable Overrun Error Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>Disable Framing Error Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARE</name>
|
|
<description>Disable Parity Error Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Disable TXEMPTY Interrupt</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Disable Buffer Empty Interrupt</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Disable Buffer Full Interrupt</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Mask RXRDY Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Disable TXRDY Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>Mask End of Receive Transfer Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>Mask End of Transmit Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Mask Overrun Error Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>Mask Framing Error Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARE</name>
|
|
<description>Mask Parity Error Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Mask TXEMPTY Interrupt</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Mask TXBUFE Interrupt</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Mask RXBUFF Interrupt</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receiver Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmitter Ready</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Receiver Transfer</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDTX</name>
|
|
<description>End of Transmitter Transfer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>Framing Error</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARE</name>
|
|
<description>Parity Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>Transmitter Empty</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBUFE</name>
|
|
<description>Transmission Buffer Empty</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Receive Buffer Full</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RHR</name>
|
|
<description>Receive Holding Register</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCHR</name>
|
|
<description>Received Character</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR</name>
|
|
<description>Transmit Holding Register</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TXCHR</name>
|
|
<description>Character to be Transmitted</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRGR</name>
|
|
<description>Baud Rate Generator Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CD</name>
|
|
<description>Clock Divisor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RPR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXPTR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<description>Receive Counter Register</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCTR</name>
|
|
<description>Receive Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPR</name>
|
|
<description>Transmit Pointer Register</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXPTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<addressOffset>0x0000010C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTR</name>
|
|
<description>Transmit Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNPR</name>
|
|
<description>Receive Next Pointer Register</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNPTR</name>
|
|
<description>Receive Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNCR</name>
|
|
<description>Receive Next Counter Register</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNCTR</name>
|
|
<description>Receive Next Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNPR</name>
|
|
<description>Transmit Next Pointer Register</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNPTR</name>
|
|
<description>Transmit Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TNCR</name>
|
|
<description>Transmit Next Counter Register</description>
|
|
<addressOffset>0x0000011C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXNCTR</name>
|
|
<description>Transmit Counter Next</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTCR</name>
|
|
<description>Transfer Control Register</description>
|
|
<addressOffset>0x00000120</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXTDIS</name>
|
|
<description>Receiver Transfer Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTDIS</name>
|
|
<description>Transmitter Transfer Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTSR</name>
|
|
<description>Transfer Status Register</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EFC0</name>
|
|
<version>6450X</version>
|
|
<description>Embedded Flash Controller 0</description>
|
|
<groupName>EFC</groupName>
|
|
<prependToName>EFC0_</prependToName>
|
|
<baseAddress>0x400E0A00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x200</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>EFC0</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>FMR</name>
|
|
<description>EEFC Flash Mode Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x04000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FRDY</name>
|
|
<description>Flash Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FWS</name>
|
|
<description>Flash Wait State</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCOD</name>
|
|
<description>Sequential Code Optimization Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FAM</name>
|
|
<description>Flash Access Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLOE</name>
|
|
<description>Code Loop Optimization Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCR</name>
|
|
<description>EEFC Flash Command Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>FCMD</name>
|
|
<description>Flash Command</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GETD</name>
|
|
<description>Get Flash descriptor</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WP</name>
|
|
<description>Write page</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WPL</name>
|
|
<description>Write page and lock</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EWP</name>
|
|
<description>Erase page and write page</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EWPL</name>
|
|
<description>Erase page and write page then lock</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EA</name>
|
|
<description>Erase all</description>
|
|
<value>0x05</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPA</name>
|
|
<description>Erase pages</description>
|
|
<value>0x07</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLB</name>
|
|
<description>Set lock bit</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLB</name>
|
|
<description>Clear lock bit</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GLB</name>
|
|
<description>Get lock bit</description>
|
|
<value>0x0A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPB</name>
|
|
<description>Set GPNVM bit</description>
|
|
<value>0x0B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CGPB</name>
|
|
<description>Clear GPNVM bit</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GGPB</name>
|
|
<description>Get GPNVM bit</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STUI</name>
|
|
<description>Start read unique identifier</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPUI</name>
|
|
<description>Stop read unique identifier</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCALB</name>
|
|
<description>Get CALIB bit</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ES</name>
|
|
<description>Erase sector</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WUS</name>
|
|
<description>Write user signature</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EUS</name>
|
|
<description>Erase user signature</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STUS</name>
|
|
<description>Start read user signature</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPUS</name>
|
|
<description>Stop read user signature</description>
|
|
<value>0x15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FARG</name>
|
|
<description>Flash Command Argument</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FKEY</name>
|
|
<description>Flash Writing Protection Key</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started.</description>
|
|
<value>0x5A</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSR</name>
|
|
<description>EEFC Flash Status Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FRDY</name>
|
|
<description>Flash Ready Status (cleared when Flash is busy)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCMDE</name>
|
|
<description>Flash Command Error Status (cleared on read or by writing EEFC_FCR)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FLOCKE</name>
|
|
<description>Flash Lock Error Status (cleared on read)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FLERR</name>
|
|
<description>Flash Error Status (cleared when a programming operation starts)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRR</name>
|
|
<description>EEFC Flash Result Register</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FVALUE</name>
|
|
<description>Flash Result Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PIOA</name>
|
|
<version>11004U</version>
|
|
<description>Parallel Input/Output Controller A</description>
|
|
<groupName>PIO</groupName>
|
|
<prependToName>PIOA_</prependToName>
|
|
<baseAddress>0x400E0E00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x200</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PIOA</name>
|
|
<value>11</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PER</name>
|
|
<description>PIO Enable Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDR</name>
|
|
<description>PIO Disable Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSR</name>
|
|
<description>PIO Status Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OER</name>
|
|
<description>Output Enable Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODR</name>
|
|
<description>Output Disable Register</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSR</name>
|
|
<description>Output Status Register</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFER</name>
|
|
<description>Glitch Input Filter Enable Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFDR</name>
|
|
<description>Glitch Input Filter Disable Register</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFSR</name>
|
|
<description>Glitch Input Filter Status Register</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SODR</name>
|
|
<description>Set Output Data Register</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CODR</name>
|
|
<description>Clear Output Data Register</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODSR</name>
|
|
<description>Output Data Status Register</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDSR</name>
|
|
<description>Pin Data Status Register</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<description>Interrupt Status Register</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDER</name>
|
|
<description>Multi-driver Enable Register</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDDR</name>
|
|
<description>Multi-driver Disable Register</description>
|
|
<addressOffset>0x00000054</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDSR</name>
|
|
<description>Multi-driver Status Register</description>
|
|
<addressOffset>0x00000058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUDR</name>
|
|
<description>Pull-up Disable Register</description>
|
|
<addressOffset>0x00000060</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUER</name>
|
|
<description>Pull-up Enable Register</description>
|
|
<addressOffset>0x00000064</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUSR</name>
|
|
<description>Pad Pull-up Status Register</description>
|
|
<addressOffset>0x00000068</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>ABCDSR[%s]</name>
|
|
<description>Peripheral Select Register</description>
|
|
<addressOffset>0x00000070</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFSCDR</name>
|
|
<description>Input Filter Slow Clock Disable Register</description>
|
|
<addressOffset>0x00000080</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFSCER</name>
|
|
<description>Input Filter Slow Clock Enable Register</description>
|
|
<addressOffset>0x00000084</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFSCSR</name>
|
|
<description>Input Filter Slow Clock Status Register</description>
|
|
<addressOffset>0x00000088</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCDR</name>
|
|
<description>Slow Clock Divider Debouncing Register</description>
|
|
<addressOffset>0x0000008C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Slow Clock Divider Selection for Debouncing</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPDDR</name>
|
|
<description>Pad Pull-down Disable Register</description>
|
|
<addressOffset>0x00000090</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPDER</name>
|
|
<description>Pad Pull-down Enable Register</description>
|
|
<addressOffset>0x00000094</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPDSR</name>
|
|
<description>Pad Pull-down Status Register</description>
|
|
<addressOffset>0x00000098</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OWER</name>
|
|
<description>Output Write Enable</description>
|
|
<addressOffset>0x000000A0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OWDR</name>
|
|
<description>Output Write Disable</description>
|
|
<addressOffset>0x000000A4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OWSR</name>
|
|
<description>Output Write Status Register</description>
|
|
<addressOffset>0x000000A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AIMER</name>
|
|
<description>Additional Interrupt Modes Enable Register</description>
|
|
<addressOffset>0x000000B0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AIMDR</name>
|
|
<description>Additional Interrupt Modes Disable Register</description>
|
|
<addressOffset>0x000000B4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AIMMR</name>
|
|
<description>Additional Interrupt Modes Mask Register</description>
|
|
<addressOffset>0x000000B8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ESR</name>
|
|
<description>Edge Select Register</description>
|
|
<addressOffset>0x000000C0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LSR</name>
|
|
<description>Level Select Register</description>
|
|
<addressOffset>0x000000C4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ELSR</name>
|
|
<description>Edge/Level Status Register</description>
|
|
<addressOffset>0x000000C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FELLSR</name>
|
|
<description>Falling Edge/Low-Level Select Register</description>
|
|
<addressOffset>0x000000D0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REHLSR</name>
|
|
<description>Rising Edge/High-Level Select Register</description>
|
|
<addressOffset>0x000000D4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRLHSR</name>
|
|
<description>Fall/Rise - Low/High Status Register</description>
|
|
<addressOffset>0x000000D8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCKSR</name>
|
|
<description>Lock Status</description>
|
|
<addressOffset>0x000000E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPMR</name>
|
|
<description>Write Protection Mode Register</description>
|
|
<addressOffset>0x000000E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPKEY</name>
|
|
<description>Write Protection Key</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.</description>
|
|
<value>0x50494F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPSR</name>
|
|
<description>Write Protection Status Register</description>
|
|
<addressOffset>0x000000E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPVS</name>
|
|
<description>Write Protection Violation Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPVSRC</name>
|
|
<description>Write Protection Violation Source</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCHMITT</name>
|
|
<description>Schmitt Trigger Register</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SCHMITT0</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT1</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT2</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT3</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT4</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT5</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT6</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT7</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT8</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT9</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT10</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT11</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT12</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT13</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT14</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT15</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT16</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT17</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT18</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT19</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT20</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT21</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT22</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT23</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT24</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT25</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT26</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT27</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT28</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT29</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT30</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT31</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCMR</name>
|
|
<description>Parallel Capture Mode Register</description>
|
|
<addressOffset>0x00000150</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PCEN</name>
|
|
<description>Parallel Capture Mode Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Parallel Capture Mode Data Size</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BYTE</name>
|
|
<description>The reception data in the PIO_PCRHR is a byte (8-bit)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALFWORD</name>
|
|
<description>The reception data in the PIO_PCRHR is a half-word (16-bit)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WORD</name>
|
|
<description>The reception data in the PIO_PCRHR is a word (32-bit)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALWYS</name>
|
|
<description>Parallel Capture Mode Always Sampling</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HALFS</name>
|
|
<description>Parallel Capture Mode Half Sampling</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRSTS</name>
|
|
<description>Parallel Capture Mode First Sample</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCIER</name>
|
|
<description>Parallel Capture Interrupt Enable Register</description>
|
|
<addressOffset>0x00000154</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Parallel Capture Mode Data Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Parallel Capture Mode Overrun Error Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Reception Transfer Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Reception Buffer Full Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCIDR</name>
|
|
<description>Parallel Capture Interrupt Disable Register</description>
|
|
<addressOffset>0x00000158</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Parallel Capture Mode Data Ready Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Parallel Capture Mode Overrun Error Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Reception Transfer Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Reception Buffer Full Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCIMR</name>
|
|
<description>Parallel Capture Interrupt Mask Register</description>
|
|
<addressOffset>0x0000015C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Parallel Capture Mode Data Ready Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Parallel Capture Mode Overrun Error Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Reception Transfer Interrupt Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Reception Buffer Full Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCISR</name>
|
|
<description>Parallel Capture Interrupt Status Register</description>
|
|
<addressOffset>0x00000160</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Parallel Capture Mode Data Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Parallel Capture Mode Overrun Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCRHR</name>
|
|
<description>Parallel Capture Reception Holding Register</description>
|
|
<addressOffset>0x00000164</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDATA</name>
|
|
<description>Parallel Capture Mode Reception Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RPR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<addressOffset>0x00000168</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXPTR</name>
|
|
<description>Receive Pointer Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<description>Receive Counter Register</description>
|
|
<addressOffset>0x0000016C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCTR</name>
|
|
<description>Receive Counter Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNPR</name>
|
|
<description>Receive Next Pointer Register</description>
|
|
<addressOffset>0x00000178</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNPTR</name>
|
|
<description>Receive Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNCR</name>
|
|
<description>Receive Next Counter Register</description>
|
|
<addressOffset>0x0000017C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNCTR</name>
|
|
<description>Receive Next Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTCR</name>
|
|
<description>Transfer Control Register</description>
|
|
<addressOffset>0x00000188</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXTDIS</name>
|
|
<description>Receiver Transfer Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTDIS</name>
|
|
<description>Transmitter Transfer Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTSR</name>
|
|
<description>Transfer Status Register</description>
|
|
<addressOffset>0x0000018C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receiver Transfer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmitter Transfer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PIOB</name>
|
|
<version>11004U</version>
|
|
<description>Parallel Input/Output Controller B</description>
|
|
<groupName>PIO</groupName>
|
|
<prependToName>PIOB_</prependToName>
|
|
<baseAddress>0x400E1000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x200</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PIOB</name>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PER</name>
|
|
<description>PIO Enable Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>PIO Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDR</name>
|
|
<description>PIO Disable Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>PIO Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSR</name>
|
|
<description>PIO Status Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>PIO Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OER</name>
|
|
<description>Output Enable Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODR</name>
|
|
<description>Output Disable Register</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Output Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSR</name>
|
|
<description>Output Status Register</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Output Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFER</name>
|
|
<description>Glitch Input Filter Enable Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Input Filter Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFDR</name>
|
|
<description>Glitch Input Filter Disable Register</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Input Filter Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFSR</name>
|
|
<description>Glitch Input Filter Status Register</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Input Filter Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SODR</name>
|
|
<description>Set Output Data Register</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Set Output Data</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CODR</name>
|
|
<description>Clear Output Data Register</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Clear Output Data</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODSR</name>
|
|
<description>Output Data Status Register</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDSR</name>
|
|
<description>Pin Data Status Register</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Output Data Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Input Change Interrupt Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Input Change Interrupt Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Input Change Interrupt Mask</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<description>Interrupt Status Register</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Input Change Interrupt Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDER</name>
|
|
<description>Multi-driver Enable Register</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Multi-drive Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDDR</name>
|
|
<description>Multi-driver Disable Register</description>
|
|
<addressOffset>0x00000054</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Multi-drive Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDSR</name>
|
|
<description>Multi-driver Status Register</description>
|
|
<addressOffset>0x00000058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Multi-drive Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUDR</name>
|
|
<description>Pull-up Disable Register</description>
|
|
<addressOffset>0x00000060</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Pull-Up Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUER</name>
|
|
<description>Pull-up Enable Register</description>
|
|
<addressOffset>0x00000064</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Pull-Up Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUSR</name>
|
|
<description>Pad Pull-up Status Register</description>
|
|
<addressOffset>0x00000068</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Pull-Up Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>ABCDSR[%s]</name>
|
|
<description>Peripheral Select Register</description>
|
|
<addressOffset>0x00000070</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Peripheral Select</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFSCDR</name>
|
|
<description>Input Filter Slow Clock Disable Register</description>
|
|
<addressOffset>0x00000080</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Peripheral Clock Glitch Filtering Select</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFSCER</name>
|
|
<description>Input Filter Slow Clock Enable Register</description>
|
|
<addressOffset>0x00000084</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Slow Clock Debouncing Filtering Select</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFSCSR</name>
|
|
<description>Input Filter Slow Clock Status Register</description>
|
|
<addressOffset>0x00000088</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Glitch or Debouncing Filter Selection Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCDR</name>
|
|
<description>Slow Clock Divider Debouncing Register</description>
|
|
<addressOffset>0x0000008C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Slow Clock Divider Selection for Debouncing</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPDDR</name>
|
|
<description>Pad Pull-down Disable Register</description>
|
|
<addressOffset>0x00000090</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Pull-Down Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPDER</name>
|
|
<description>Pad Pull-down Enable Register</description>
|
|
<addressOffset>0x00000094</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Pull-Down Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPDSR</name>
|
|
<description>Pad Pull-down Status Register</description>
|
|
<addressOffset>0x00000098</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Pull-Down Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OWER</name>
|
|
<description>Output Write Enable</description>
|
|
<addressOffset>0x000000A0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Output Write Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OWDR</name>
|
|
<description>Output Write Disable</description>
|
|
<addressOffset>0x000000A4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Output Write Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OWSR</name>
|
|
<description>Output Write Status Register</description>
|
|
<addressOffset>0x000000A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Output Write Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AIMER</name>
|
|
<description>Additional Interrupt Modes Enable Register</description>
|
|
<addressOffset>0x000000B0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Additional Interrupt Modes Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AIMDR</name>
|
|
<description>Additional Interrupt Modes Disable Register</description>
|
|
<addressOffset>0x000000B4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Additional Interrupt Modes Disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AIMMR</name>
|
|
<description>Additional Interrupt Modes Mask Register</description>
|
|
<addressOffset>0x000000B8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>IO Line Index</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ESR</name>
|
|
<description>Edge Select Register</description>
|
|
<addressOffset>0x000000C0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Edge Interrupt Selection</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LSR</name>
|
|
<description>Level Select Register</description>
|
|
<addressOffset>0x000000C4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Level Interrupt Selection</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ELSR</name>
|
|
<description>Edge/Level Status Register</description>
|
|
<addressOffset>0x000000C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FELLSR</name>
|
|
<description>Falling Edge/Low-Level Select Register</description>
|
|
<addressOffset>0x000000D0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Falling Edge/Low-Level Interrupt Selection</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REHLSR</name>
|
|
<description>Rising Edge/High-Level Select Register</description>
|
|
<addressOffset>0x000000D4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Rising Edge/High-Level Interrupt Selection</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRLHSR</name>
|
|
<description>Fall/Rise - Low/High Status Register</description>
|
|
<addressOffset>0x000000D8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Edge/Level Interrupt Source Selection</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCKSR</name>
|
|
<description>Lock Status</description>
|
|
<addressOffset>0x000000E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P8</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P10</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P11</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P12</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P13</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P14</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P15</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P16</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P17</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P18</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P19</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P20</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P21</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P22</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P23</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P24</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P25</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P26</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P27</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P28</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P29</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P30</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P31</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPMR</name>
|
|
<description>Write Protection Mode Register</description>
|
|
<addressOffset>0x000000E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPKEY</name>
|
|
<description>Write Protection Key</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.</description>
|
|
<value>0x50494F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPSR</name>
|
|
<description>Write Protection Status Register</description>
|
|
<addressOffset>0x000000E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPVS</name>
|
|
<description>Write Protection Violation Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WPVSRC</name>
|
|
<description>Write Protection Violation Source</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCHMITT</name>
|
|
<description>Schmitt Trigger Register</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SCHMITT0</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT1</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT2</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT3</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT4</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT5</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT6</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT7</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT8</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT9</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT10</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT11</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT12</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT13</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT14</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT15</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT16</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT17</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT18</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT19</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT20</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT21</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT22</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT23</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT24</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT25</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT26</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT27</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT28</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT29</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT30</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCHMITT31</name>
|
|
<description>Schmitt Trigger Control</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCMR</name>
|
|
<description>Parallel Capture Mode Register</description>
|
|
<addressOffset>0x00000150</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PCEN</name>
|
|
<description>Parallel Capture Mode Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Parallel Capture Mode Data Size</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BYTE</name>
|
|
<description>The reception data in the PIO_PCRHR is a byte (8-bit)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALFWORD</name>
|
|
<description>The reception data in the PIO_PCRHR is a half-word (16-bit)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WORD</name>
|
|
<description>The reception data in the PIO_PCRHR is a word (32-bit)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALWYS</name>
|
|
<description>Parallel Capture Mode Always Sampling</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HALFS</name>
|
|
<description>Parallel Capture Mode Half Sampling</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRSTS</name>
|
|
<description>Parallel Capture Mode First Sample</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCIER</name>
|
|
<description>Parallel Capture Interrupt Enable Register</description>
|
|
<addressOffset>0x00000154</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Parallel Capture Mode Data Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Parallel Capture Mode Overrun Error Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Reception Transfer Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Reception Buffer Full Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCIDR</name>
|
|
<description>Parallel Capture Interrupt Disable Register</description>
|
|
<addressOffset>0x00000158</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Parallel Capture Mode Data Ready Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Parallel Capture Mode Overrun Error Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Reception Transfer Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Reception Buffer Full Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCIMR</name>
|
|
<description>Parallel Capture Interrupt Mask Register</description>
|
|
<addressOffset>0x0000015C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Parallel Capture Mode Data Ready Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Parallel Capture Mode Overrun Error Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<description>End of Reception Transfer Interrupt Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<description>Reception Buffer Full Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCISR</name>
|
|
<description>Parallel Capture Interrupt Status Register</description>
|
|
<addressOffset>0x00000160</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Parallel Capture Mode Data Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Parallel Capture Mode Overrun Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDRX</name>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBUFF</name>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCRHR</name>
|
|
<description>Parallel Capture Reception Holding Register</description>
|
|
<addressOffset>0x00000164</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDATA</name>
|
|
<description>Parallel Capture Mode Reception Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RSTC</name>
|
|
<version>11009J</version>
|
|
<description>Reset Controller</description>
|
|
<groupName>SYSC</groupName>
|
|
<prependToName>RSTC_</prependToName>
|
|
<baseAddress>0x400E1400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x200</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PROCRST</name>
|
|
<description>Processor Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERRST</name>
|
|
<description>Peripheral Reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EXTRST</name>
|
|
<description>External Reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>System Reset Key</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation.</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>URSTS</name>
|
|
<description>User Reset Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTTYP</name>
|
|
<description>Reset Type</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GENERAL_RST</name>
|
|
<description>First power-up reset</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BACKUP_RST</name>
|
|
<description>Return from Backup Mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDT_RST</name>
|
|
<description>Watchdog fault occurred</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOFT_RST</name>
|
|
<description>Processor reset required by the software</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USER_RST</name>
|
|
<description>NRST pin detected low</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NRSTL</name>
|
|
<description>NRST Pin Level</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRCMP</name>
|
|
<description>Software Reset Command in Progress</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MR</name>
|
|
<description>Mode Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>URSTEN</name>
|
|
<description>User Reset Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>URSTIEN</name>
|
|
<description>User Reset Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERSTL</name>
|
|
<description>External Reset Length</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Write Access Password</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation.Always reads as 0.</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SUPC</name>
|
|
<version>6452Z</version>
|
|
<description>Supply Controller</description>
|
|
<groupName>SYSC</groupName>
|
|
<prependToName>SUPC_</prependToName>
|
|
<baseAddress>0x400E1410</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x200</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Supply Controller Control Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>VROFF</name>
|
|
<description>Voltage Regulator Off</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_VREG</name>
|
|
<description>If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTALSEL</name>
|
|
<description>Crystal Oscillator Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_SEL</name>
|
|
<description>If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Password</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation.</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMMR</name>
|
|
<description>Supply Controller Supply Monitor Mode Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMTH</name>
|
|
<description>Supply Monitor Threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SMSMPL</name>
|
|
<description>Supply Monitor Sampling Period</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMD</name>
|
|
<description>Supply Monitor disabled</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSM</name>
|
|
<description>Continuous Supply Monitor</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32SLCK</name>
|
|
<description>Supply Monitor enabled one SLCK period every 32 SLCK periods</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256SLCK</name>
|
|
<description>Supply Monitor enabled one SLCK period every 256 SLCK periods</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2048SLCK</name>
|
|
<description>Supply Monitor enabled one SLCK period every 2,048 SLCK periods</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMRSTEN</name>
|
|
<description>Supply Monitor Reset Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_ENABLE</name>
|
|
<description>The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMIEN</name>
|
|
<description>Supply Monitor Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_ENABLE</name>
|
|
<description>The SUPC interrupt signal is not affected when a supply monitor detection occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The SUPC interrupt signal is asserted when a supply monitor detection occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MR</name>
|
|
<description>Supply Controller Mode Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00005A00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BODRSTEN</name>
|
|
<description>Brownout Detector Reset Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_ENABLE</name>
|
|
<description>The core reset signal vddcore_nreset is not affected when a brownout detection occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The core reset signal, vddcore_nreset is asserted when a brownout detection occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BODDIS</name>
|
|
<description>Brownout Detector Disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The core brownout detector is enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The core brownout detector is disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONREG</name>
|
|
<description>Voltage Regulator Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONREG_UNUSED</name>
|
|
<description>Internal voltage regulator is not used (external power supply is used).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONREG_USED</name>
|
|
<description>Internal voltage regulator is used.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSCBYPASS</name>
|
|
<description>Oscillator Bypass</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect. Clock selection depends on the value of XTALSEL (SUPC_CR).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BYPASS</name>
|
|
<description>The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Password Key</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation.</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WUMR</name>
|
|
<description>Supply Controller Wake-up Mode Register</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMEN</name>
|
|
<description>Supply Monitor Wake-up Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_ENABLE</name>
|
|
<description>The supply monitor detection has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The supply monitor detection forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTTEN</name>
|
|
<description>Real-time Timer Wake-up Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_ENABLE</name>
|
|
<description>The RTT alarm signal has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The RTT alarm signal forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCEN</name>
|
|
<description>Real-time Clock Wake-up Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_ENABLE</name>
|
|
<description>The RTC alarm signal has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The RTC alarm signal forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPDBCEN0</name>
|
|
<description>Low-power Debouncer Enable WKUP0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_ENABLE</name>
|
|
<description>The WKUP0 input pin is not connected to the low-power debouncer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPDBCEN1</name>
|
|
<description>Low-power Debouncer Enable WKUP1</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_ENABLE</name>
|
|
<description>The WKUP1 input pin is not connected to the low-power debouncer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPDBCCLR</name>
|
|
<description>Low-power Debouncer Clear</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_ENABLE</name>
|
|
<description>A low-power debounce event does not create an immediate clear on the first half of GPBR registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPDBC</name>
|
|
<description>Wake-up Inputs Debouncer Period</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IMMEDIATE</name>
|
|
<description>Immediate, no debouncing, detected active at least on one Slow Clock edge.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_SCLK</name>
|
|
<description>WKUPx shall be in its active state for at least 3 SLCK periods</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32_SCLK</name>
|
|
<description>WKUPx shall be in its active state for at least 32 SLCK periods</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_SCLK</name>
|
|
<description>WKUPx shall be in its active state for at least 512 SLCK periods</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4096_SCLK</name>
|
|
<description>WKUPx shall be in its active state for at least 4,096 SLCK periods</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32768_SCLK</name>
|
|
<description>WKUPx shall be in its active state for at least 32,768 SLCK periods</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPDBC</name>
|
|
<description>Low-power Debouncer Period</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable the low-power debouncers.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_RTCOUT0</name>
|
|
<description>WKUP0/1 in active state for at least 2 RTCOUTx clock periods</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_RTCOUT0</name>
|
|
<description>WKUP0/1 in active state for at least 3 RTCOUTx clock periods</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_RTCOUT0</name>
|
|
<description>WKUP0/1 in active state for at least 4 RTCOUTx clock periods</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5_RTCOUT0</name>
|
|
<description>WKUP0/1 in active state for at least 5 RTCOUTx clock periods</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_RTCOUT0</name>
|
|
<description>WKUP0/1 in active state for at least 6 RTCOUTx clock periods</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_RTCOUT0</name>
|
|
<description>WKUP0/1 in active state for at least 7 RTCOUTx clock periods</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_RTCOUT0</name>
|
|
<description>WKUP0/1 in active state for at least 8 RTCOUTx clock periods</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WUIR</name>
|
|
<description>Supply Controller Wake-up Inputs Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WKUPEN0</name>
|
|
<description>Wake-up Input Enable 0 to 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The corresponding wake-up input has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPEN1</name>
|
|
<description>Wake-up Input Enable 0 to 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The corresponding wake-up input has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPEN2</name>
|
|
<description>Wake-up Input Enable 0 to 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The corresponding wake-up input has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPEN3</name>
|
|
<description>Wake-up Input Enable 0 to 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The corresponding wake-up input has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPEN4</name>
|
|
<description>Wake-up Input Enable 0 to 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The corresponding wake-up input has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPEN5</name>
|
|
<description>Wake-up Input Enable 0 to 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The corresponding wake-up input has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPEN6</name>
|
|
<description>Wake-up Input Enable 0 to 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The corresponding wake-up input has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPEN7</name>
|
|
<description>Wake-up Input Enable 0 to 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The corresponding wake-up input has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPEN8</name>
|
|
<description>Wake-up Input Enable 0 to 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The corresponding wake-up input has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPEN9</name>
|
|
<description>Wake-up Input Enable 0 to 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The corresponding wake-up input has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPEN10</name>
|
|
<description>Wake-up Input Enable 0 to 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The corresponding wake-up input has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPEN11</name>
|
|
<description>Wake-up Input Enable 0 to 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The corresponding wake-up input has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPEN12</name>
|
|
<description>Wake-up Input Enable 0 to 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The corresponding wake-up input has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPEN13</name>
|
|
<description>Wake-up Input Enable 0 to 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The corresponding wake-up input has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPEN14</name>
|
|
<description>Wake-up Input Enable 0 to 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The corresponding wake-up input has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPEN15</name>
|
|
<description>Wake-up Input Enable 0 to 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The corresponding wake-up input has no wake-up effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPT0</name>
|
|
<description>Wake-up Input Type 0 to 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPT1</name>
|
|
<description>Wake-up Input Type 0 to 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPT2</name>
|
|
<description>Wake-up Input Type 0 to 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPT3</name>
|
|
<description>Wake-up Input Type 0 to 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPT4</name>
|
|
<description>Wake-up Input Type 0 to 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPT5</name>
|
|
<description>Wake-up Input Type 0 to 5</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPT6</name>
|
|
<description>Wake-up Input Type 0 to 6</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPT7</name>
|
|
<description>Wake-up Input Type 0 to 7</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPT8</name>
|
|
<description>Wake-up Input Type 0 to 8</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPT9</name>
|
|
<description>Wake-up Input Type 0 to 9</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPT10</name>
|
|
<description>Wake-up Input Type 0 to 10</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPT11</name>
|
|
<description>Wake-up Input Type 0 to 11</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPT12</name>
|
|
<description>Wake-up Input Type 0 to 12</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPT13</name>
|
|
<description>Wake-up Input Type 0 to 13</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPT14</name>
|
|
<description>Wake-up Input Type 0 to 14</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPT15</name>
|
|
<description>Wake-up Input Type 0 to 15</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Supply Controller Status Register</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WKUPS</name>
|
|
<description>WKUP Wake-up Status (cleared on read)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESENT</name>
|
|
<description>At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMWS</name>
|
|
<description>Supply Monitor Detection Wake-up Status (cleared on read)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESENT</name>
|
|
<description>At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BODRSTS</name>
|
|
<description>Brownout Detector Reset Status (cleared on read)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No core brownout rising edge event has been detected since the last read of the SUPC_SR.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESENT</name>
|
|
<description>At least one brownout output rising edge event has been detected since the last read of the SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMRSTS</name>
|
|
<description>Supply Monitor Reset Status (cleared on read)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No supply monitor detection has generated a core reset since the last read of the SUPC_SR.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESENT</name>
|
|
<description>At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMS</name>
|
|
<description>Supply Monitor Status (cleared on read)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No supply monitor detection since the last read of SUPC_SR.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESENT</name>
|
|
<description>At least one supply monitor detection since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOS</name>
|
|
<description>Supply Monitor Output Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The supply monitor detected VDDIO higher than its threshold at its last measurement.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The supply monitor detected VDDIO lower than its threshold at its last measurement.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSCSEL</name>
|
|
<description>32-kHz Oscillator Selection Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RC</name>
|
|
<description>The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYST</name>
|
|
<description>The slow clock, SLCK, is generated by the 32 kHz crystal oscillator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPDBCS0</name>
|
|
<description>Low-power Debouncer Wake-up Status on WKUP0 (cleared on read)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESENT</name>
|
|
<description>At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPDBCS1</name>
|
|
<description>Low-power Debouncer Wake-up Status on WKUP1 (cleared on read)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESENT</name>
|
|
<description>At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIS0</name>
|
|
<description>WKUPx Input Status (cleared on read)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIS1</name>
|
|
<description>WKUPx Input Status (cleared on read)</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIS2</name>
|
|
<description>WKUPx Input Status (cleared on read)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIS3</name>
|
|
<description>WKUPx Input Status (cleared on read)</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIS4</name>
|
|
<description>WKUPx Input Status (cleared on read)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIS5</name>
|
|
<description>WKUPx Input Status (cleared on read)</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIS6</name>
|
|
<description>WKUPx Input Status (cleared on read)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIS7</name>
|
|
<description>WKUPx Input Status (cleared on read)</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIS8</name>
|
|
<description>WKUPx Input Status (cleared on read)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIS9</name>
|
|
<description>WKUPx Input Status (cleared on read)</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIS10</name>
|
|
<description>WKUPx Input Status (cleared on read)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIS11</name>
|
|
<description>WKUPx Input Status (cleared on read)</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIS12</name>
|
|
<description>WKUPx Input Status (cleared on read)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIS13</name>
|
|
<description>WKUPx Input Status (cleared on read)</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIS14</name>
|
|
<description>WKUPx Input Status (cleared on read)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIS15</name>
|
|
<description>WKUPx Input Status (cleared on read)</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS</name>
|
|
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN</name>
|
|
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RTT</name>
|
|
<version>6081M</version>
|
|
<description>Real-time Timer</description>
|
|
<groupName>SYSC</groupName>
|
|
<prependToName>RTT_</prependToName>
|
|
<baseAddress>0x400E1430</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x200</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MR</name>
|
|
<description>Mode Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00008000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RTPRES</name>
|
|
<description>Real-time Timer Prescaler Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALMIEN</name>
|
|
<description>Alarm Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTTINCIEN</name>
|
|
<description>Real-time Timer Increment Interrupt Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTTRST</name>
|
|
<description>Real-time Timer Restart</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTTDIS</name>
|
|
<description>Real-time Timer Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTC1HZ</name>
|
|
<description>Real-Time Clock 1Hz Clock Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AR</name>
|
|
<description>Alarm Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ALMV</name>
|
|
<description>Alarm Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VR</name>
|
|
<description>Value Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CRTV</name>
|
|
<description>Current Real-time Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ALMS</name>
|
|
<description>Real-time Alarm Status (cleared on read)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RTTINC</name>
|
|
<description>Prescaler Roll-over Status (cleared on read)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>WDT</name>
|
|
<version>6080I</version>
|
|
<description>Watchdog Timer</description>
|
|
<groupName>SYSC</groupName>
|
|
<prependToName>WDT_</prependToName>
|
|
<baseAddress>0x400E1450</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x200</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>WDRSTT</name>
|
|
<description>Watchdog Restart</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Password</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PASSWD</name>
|
|
<description>Writing any other value in this field aborts the write operation.</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MR</name>
|
|
<description>Mode Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3FFF2FFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WDV</name>
|
|
<description>Watchdog Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDFIEN</name>
|
|
<description>Watchdog Fault Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDRSTEN</name>
|
|
<description>Watchdog Reset Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDRPROC</name>
|
|
<description>Watchdog Reset Processor</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDDIS</name>
|
|
<description>Watchdog Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDD</name>
|
|
<description>Watchdog Delta Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDDBGHLT</name>
|
|
<description>Watchdog Debug Halt</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDIDLEHLT</name>
|
|
<description>Watchdog Idle Halt</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WDUNF</name>
|
|
<description>Watchdog Underflow (cleared on read)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WDERR</name>
|
|
<description>Watchdog Error (cleared on read)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RTC</name>
|
|
<version>6056U</version>
|
|
<description>Real-time Clock</description>
|
|
<groupName>SYSC</groupName>
|
|
<prependToName>RTC_</prependToName>
|
|
<baseAddress>0x400E1460</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x200</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDTIM</name>
|
|
<description>Update Request Time Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UPDCAL</name>
|
|
<description>Update Request Calendar Register</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVSEL</name>
|
|
<description>Time Event Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MINUTE</name>
|
|
<description>Minute change</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HOUR</name>
|
|
<description>Hour change</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MIDNIGHT</name>
|
|
<description>Every day at midnight</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOON</name>
|
|
<description>Every day at noon</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CALEVSEL</name>
|
|
<description>Calendar Event Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WEEK</name>
|
|
<description>Week change (every Monday at time 00:00:00)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MONTH</name>
|
|
<description>Month change (every 01 of each month at time 00:00:00)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YEAR</name>
|
|
<description>Year change (every January 1 at time 00:00:00)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MR</name>
|
|
<description>Mode Register</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HRMOD</name>
|
|
<description>12-/24-hour Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PERSIAN</name>
|
|
<description>PERSIAN Calendar</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEGPPM</name>
|
|
<description>NEGative PPM Correction</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CORRECTION</name>
|
|
<description>Slow Clock Correction</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HIGHPPM</name>
|
|
<description>HIGH PPM Correction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUT0</name>
|
|
<description>RTCOUT0 OutputSource Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_WAVE</name>
|
|
<description>No waveform, stuck at '0'</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FREQ1HZ</name>
|
|
<description>1 Hz square wave</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FREQ32HZ</name>
|
|
<description>32 Hz square wave</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FREQ64HZ</name>
|
|
<description>64 Hz square wave</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FREQ512HZ</name>
|
|
<description>512 Hz square wave</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALARM_TOGGLE</name>
|
|
<description>Output toggles when alarm flag rises</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALARM_FLAG</name>
|
|
<description>Output is a copy of the alarm flag</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PROG_PULSE</name>
|
|
<description>Duty cycle programmable pulse</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUT1</name>
|
|
<description>RTCOUT1 Output Source Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_WAVE</name>
|
|
<description>No waveform, stuck at '0'</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FREQ1HZ</name>
|
|
<description>1 Hz square wave</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FREQ32HZ</name>
|
|
<description>32 Hz square wave</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FREQ64HZ</name>
|
|
<description>64 Hz square wave</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FREQ512HZ</name>
|
|
<description>512 Hz square wave</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALARM_TOGGLE</name>
|
|
<description>Output toggles when alarm flag rises</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALARM_FLAG</name>
|
|
<description>Output is a copy of the alarm flag</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PROG_PULSE</name>
|
|
<description>Duty cycle programmable pulse</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>THIGH</name>
|
|
<description>High Duration of the Output Pulse</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>H_31MS</name>
|
|
<description>31.2 ms</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_16MS</name>
|
|
<description>15.6 ms</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_4MS</name>
|
|
<description>3.91 ms</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_976US</name>
|
|
<description>976 us</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_488US</name>
|
|
<description>488 us</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_122US</name>
|
|
<description>122 us</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_30US</name>
|
|
<description>30.5 us</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_15US</name>
|
|
<description>15.2 us</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPERIOD</name>
|
|
<description>Period of the Output Pulse</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>P_1S</name>
|
|
<description>1 second</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_500MS</name>
|
|
<description>500 ms</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_250MS</name>
|
|
<description>250 ms</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_125MS</name>
|
|
<description>125 ms</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMR</name>
|
|
<description>Time Register</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEC</name>
|
|
<description>Current Second</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MIN</name>
|
|
<description>Current Minute</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HOUR</name>
|
|
<description>Current Hour</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AMPM</name>
|
|
<description>Ante Meridiem Post Meridiem Indicator</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALR</name>
|
|
<description>Calendar Register</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x01A11020</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CENT</name>
|
|
<description>Current Century</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>YEAR</name>
|
|
<description>Current Year</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MONTH</name>
|
|
<description>Current Month</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DAY</name>
|
|
<description>Current Day in Current Week</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATE</name>
|
|
<description>Current Day in Current Month</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMALR</name>
|
|
<description>Time Alarm Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEC</name>
|
|
<description>Second Alarm</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SECEN</name>
|
|
<description>Second Alarm Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MIN</name>
|
|
<description>Minute Alarm</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MINEN</name>
|
|
<description>Minute Alarm Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HOUR</name>
|
|
<description>Hour Alarm</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AMPM</name>
|
|
<description>AM/PM Indicator</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HOUREN</name>
|
|
<description>Hour Alarm Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALALR</name>
|
|
<description>Calendar Alarm Register</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x01010000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MONTH</name>
|
|
<description>Month Alarm</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTHEN</name>
|
|
<description>Month Alarm Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATE</name>
|
|
<description>Date Alarm</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATEEN</name>
|
|
<description>Date Alarm Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ACKUPD</name>
|
|
<description>Acknowledge for Update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FREERUN</name>
|
|
<description>Time and calendar registers cannot be updated.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Time and calendar registers can be updated.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALARM</name>
|
|
<description>Alarm Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_ALARMEVENT</name>
|
|
<description>No alarm matching condition occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALARMEVENT</name>
|
|
<description>An alarm matching condition has occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEC</name>
|
|
<description>Second Event</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_SECEVENT</name>
|
|
<description>No second event has occurred since the last clear.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SECEVENT</name>
|
|
<description>At least one second event has occurred since the last clear.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMEV</name>
|
|
<description>Time Event</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_TIMEVENT</name>
|
|
<description>No time event has occurred since the last clear.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMEVENT</name>
|
|
<description>At least one time event has occurred since the last clear.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CALEV</name>
|
|
<description>Calendar Event</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_CALEVENT</name>
|
|
<description>No calendar event has occurred since the last clear.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CALEVENT</name>
|
|
<description>At least one calendar event has occurred since the last clear.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDERR</name>
|
|
<description>Time and/or Date Free Running Error</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CORRECT</name>
|
|
<description>The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR_TIMEDATE</name>
|
|
<description>The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCCR</name>
|
|
<description>Status Clear Command Register</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>ACKCLR</name>
|
|
<description>Acknowledge Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ALRCLR</name>
|
|
<description>Alarm Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SECCLR</name>
|
|
<description>Second Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMCLR</name>
|
|
<description>Time Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CALCLR</name>
|
|
<description>Calendar Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TDERRCLR</name>
|
|
<description>Time and/or Date Free Running Error Clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>ACKEN</name>
|
|
<description>Acknowledge Update Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ALREN</name>
|
|
<description>Alarm Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SECEN</name>
|
|
<description>Second Event Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEN</name>
|
|
<description>Time Event Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CALEN</name>
|
|
<description>Calendar Event Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TDERREN</name>
|
|
<description>Time and/or Date Error Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>ACKDIS</name>
|
|
<description>Acknowledge Update Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ALRDIS</name>
|
|
<description>Alarm Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SECDIS</name>
|
|
<description>Second Event Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMDIS</name>
|
|
<description>Time Event Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CALDIS</name>
|
|
<description>Calendar Event Interrupt Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TDERRDIS</name>
|
|
<description>Time and/or Date Error Interrupt Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>Acknowledge Update Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ALR</name>
|
|
<description>Alarm Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SEC</name>
|
|
<description>Second Event Interrupt Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIM</name>
|
|
<description>Time Event Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CAL</name>
|
|
<description>Calendar Event Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TDERR</name>
|
|
<description>Time and/or Date Error Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VER</name>
|
|
<description>Valid Entry Register</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NVTIM</name>
|
|
<description>Non-valid Time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NVCAL</name>
|
|
<description>Non-valid Calendar</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NVTIMALR</name>
|
|
<description>Non-valid Time Alarm</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NVCALALR</name>
|
|
<description>Non-valid Calendar Alarm</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPBR</name>
|
|
<version>6378H</version>
|
|
<description>General Purpose Backup Registers</description>
|
|
<groupName>SYSC</groupName>
|
|
<prependToName>GPBR_</prependToName>
|
|
<baseAddress>0x400E1490</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x200</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>GPBR[%s]</name>
|
|
<description>General Purpose Backup Register</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>GPBR_VALUE</name>
|
|
<description>Value of GPBR x</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device>
|