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RMUL2025/lib/cmsis_svd/data/ArteryTek/AT32F421xx_v2.svd

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<?xml version="1.0" encoding="utf-8"?>
<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
Copyright (C) 2012-2014 ARM Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
for demonstration purposes only.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>Keil</vendor> <!-- device vendor name -->
<vendorID>ArteryTek</vendorID> <!-- device vendor short name -->
<name>AT32F421xx_v2</name> <!-- name of part-->
<series>AT32F421</series> <!-- device series the device belongs to -->
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
<description>ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 200MHz, etc. </description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
suitable processor architectures. This file can be freely distributed.\n
Modifications to this file shall be clearly marked.\n
\n
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM4</name>
<revision>r0p1</revision>
<endian>little</endian>
<mpuPresent>false</mpuPresent>
<fpuPresent>true</fpuPresent>
<nvicPrioBits>4</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
and register that do not define "size" themselves -->
<access>read-write</access> <!-- default access permission for all subsequent registers -->
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
<peripherals>
<peripheral>
<name>PWC</name>
<description>Power control</description>
<groupName>PWC</groupName>
<baseAddress>0x40007000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTRL</name>
<displayName>CTRL</displayName>
<description>Power control register
(PWC_CTRL)</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VRSEL</name>
<description>Voltage regulator state select when deepsleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPSEL</name>
<description>Low power mode select when Cortex-M4F sleepdeep</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLSWEF</name>
<description>Clear SWEF flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLSEF</name>
<description>Clear SEF flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVMEN</name>
<description>Power voltage monitoring enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVMSEL</name>
<description>Power voltage monitoring boundary select</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>BPWEN</name>
<description>Battery powered domain write enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRLSTS</name>
<displayName>CTRLSTS</displayName>
<description>Power control and status register
(PWC_CTRLSTS)</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWEF</name>
<description>Standby wake-up event flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SEF</name>
<description>Standby mode entry flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PVMOF</name>
<description>Power voltage monitoring output flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SWPEN1</name>
<description>Standby wake-up pin1 enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWPEN2</name>
<description>Standby wake-up pin2 enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWPEN6</name>
<description>Standby wake-up pin2 enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWPEN7</name>
<description>Standby wake-up pin2 enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTRL2</name>
<displayName>CTRL2</displayName>
<description>Power control and status register2
(PWC_CTRL2)</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VREXLPEN</name>
<description>Voltage regulator extra low power mode enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CRM</name>
<description>Clock and reset management</description>
<groupName>CRM</groupName>
<baseAddress>0x40021000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CRM</name>
<description>CRM global interrupt</description>
<value>4</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<displayName>CTRL</displayName>
<description>Clock control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000083</resetValue>
<fields>
<field>
<name>HICKEN</name>
<description>High speed internal clock enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HICKSTBL</name>
<description>High speed internal clock ready flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HICKTRIM</name>
<description>High speed internal clock trimming</description>
<bitOffset>2</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HICKCAL</name>
<description>High speed internal clock calibration</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HEXTEN</name>
<description>High speed exernal crystal enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEXTSTBL</name>
<description>High speed exernal crystal ready flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HEXTBYPS</name>
<description>High speed exernal crystal bypass</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CFDEN</name>
<description>Clock failure detection enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLLEN</name>
<description>PLL enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLLSTBL</name>
<description>PLL clock ready flag</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CFG</name>
<displayName>CFG</displayName>
<description>Clock configuration register
(CRM_CFG)</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCLKSEL</name>
<description>System clock select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SCLKSTS</name>
<description>System Clock select Status</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>AHBDIV</name>
<description>AHB division</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APB1DIV</name>
<description>APB1 division</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APB2DIV</name>
<description>APB2 division</description>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ADCDIV1_0</name>
<description>ADC division bit1 and bit0</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLLRCS</name>
<description>PLL reference clock select</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLLHEXTDIV</name>
<description>HEXT division selection for PLL entry clock</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLLMULT3_0</name>
<description>PLL Multiplication Factor bit3 to bit0</description>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLKOUT_SEL</name>
<description>Clock output selection bit2 to bit0</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ADCDIV2</name>
<description>ADC division bit2</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLLMULT5_4</name>
<description>PLL Multiplication Factor bit5 and bit4</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLKINT</name>
<displayName>CLKINT</displayName>
<description>Clock interrupt register
(CRM_CLKINT)</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LICKSTBLF</name>
<description>LICK ready interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LEXTSTBLF</name>
<description>LEXT ready interrupt flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HICKSTBLF</name>
<description>HICK ready interrupt flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HEXTSTBLF</name>
<description>HEXT ready interrupt flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PLLSTBLF</name>
<description>PLL ready interrupt flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CFDF</name>
<description>Clock failure detection interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LICKSTBLIEN</name>
<description>LICK ready interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LEXTSTBLIEN</name>
<description>LEXT ready interrupt enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HICKSTBLIEN</name>
<description>HICK ready interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEXTSTBLIEN</name>
<description>HEXT ready interrupt enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLLSTBLIEN</name>
<description>PLL ready interrupt enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LICKSTBLFC</name>
<description>LICK ready interrupt clear</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>LEXTSTBLFC</name>
<description>LEXT ready interrupt clear</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>HICKSTBLFC</name>
<description>HICK ready interrupt clear</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>HEXTSTBLFC</name>
<description>HEXT ready interrupt clear</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>PLLSTBLFC</name>
<description>PLL ready interrupt clear</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CFDFC</name>
<description>Clock failure detection interrupt clear</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>APB2RST</name>
<displayName>APB2RST</displayName>
<description>APB2 peripheral reset register
(CRM_APB2RST)</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000000000</resetValue>
<fields>
<field>
<name>SCFGCMPRST</name>
<description>System config and comparator reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXINTRST</name>
<description>External interrupt reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADCRST</name>
<description>ADC reset</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR1RST</name>
<description>TMR1 reset</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI1RST</name>
<description>SPI1 reset</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USART1RST</name>
<description>USART1 reset</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR15RST</name>
<description>Timer15 reset</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR16RST</name>
<description>Timer16 reset</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR17RST</name>
<description>Timer17 reset</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB1RST</name>
<displayName>APB1RST</displayName>
<description>APB1 peripheral reset register
(CRM_APB1RST)</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TMR3RST</name>
<description>Timer 3 reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR6RST</name>
<description>Timer 6 reset</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR14RST</name>
<description>Timer 14 reset</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WWDTRST</name>
<description>Window watchdog timer reset</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI2RST</name>
<description>SPI2 reset</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USART2RST</name>
<description>USART 2 reset</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C1RST</name>
<description>I2C1 reset</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C2RST</name>
<description>I2C2 reset</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWCRST</name>
<description>Power controller reset</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBEN</name>
<displayName>AHBEN</displayName>
<description>AHB Peripheral Clock enable register
(CRM_AHBEN)</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000014</resetValue>
<fields>
<field>
<name>DMAEN</name>
<description>DMA clock enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRAMEN</name>
<description>SRAM interface clock
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLASHEN</name>
<description>FLASH clock enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCEN</name>
<description>CRC clock enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOAEN</name>
<description>I/O port A clock enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOBEN</name>
<description>I/O port B clock enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOCEN</name>
<description>I/O port C clock enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOFEN</name>
<description>I/O port F clock enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB2EN</name>
<displayName>APB2EN</displayName>
<description>APB2 peripheral clock enable register
(CRM_APB2EN)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCFGCMPEN</name>
<description>Syscfg and comparator clock enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADCEN</name>
<description>ADC clock enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR1EN</name>
<description>Timer1 clock enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI1EN</name>
<description>SPI1 clock enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USART1EN</name>
<description>USART1 clock enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR15EN</name>
<description>Timer15 clock enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR16EN</name>
<description>Timer16 clock enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR17EN</name>
<description>Timer17 clock enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB1EN</name>
<displayName>APB1EN</displayName>
<description>APB1 peripheral clock enable register
(CRM_APB1EN)</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TMR3EN</name>
<description>Timer3 clock enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR6EN</name>
<description>Timer6 clock enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR14EN</name>
<description>Timer14 clock enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WWDTEN</name>
<description>Window watchdog timer clock
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI2EN</name>
<description>SPI2 clock enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USART2EN</name>
<description>USART2 clock enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C1EN</name>
<description>I2C1 clock enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C2EN</name>
<description>I2C2 clock enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWCEN</name>
<description>Power clock enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BPDC</name>
<displayName>BPDC</displayName>
<description>Battery powered domain control register
(CRM_BPDC)</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LEXTEN</name>
<description>Low speed external crystal enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LEXTSTBL</name>
<description>Low speed external crystal ready</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LEXTBYPS</name>
<description>Low speed external crystal bypass</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ERTCSEL</name>
<description>ERTC clock selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ERTCEN</name>
<description>ERTC clock enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BPDRST</name>
<description>Battery powered domain software reset</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTRLSTS</name>
<displayName>CTRLSTS</displayName>
<description>Control/status register
(CRM_CTRLSTS)</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x0C000000</resetValue>
<fields>
<field>
<name>LICKEN</name>
<description>Low speed internal clock enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LICKSTBL</name>
<description>Low speed internal clock ready</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RSTFC</name>
<description>Reset flag clear</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NRSTF</name>
<description>PIN reset flag</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PORRSTF</name>
<description>POR/LVR reset flag</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWRSTF</name>
<description>Software reset flag</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WDTRSTF</name>
<description>Watchdog timer reset flag</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WWDTRSTF</name>
<description>Window watchdog timer reset flag</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LPRSTF</name>
<description>Low-power reset flag</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>AHBRST</name>
<displayName>AHBRST</displayName>
<description>AHB reset register
</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GPIOARST</name>
<description>IO port A reset</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOBRST</name>
<description>IO port B reset</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOCRST</name>
<description>IO port C reset</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOFRST</name>
<description>IO port F reset</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PLL</name>
<displayName>PLL</displayName>
<description>PLL configuration register
(CRM_PLL)</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<resetValue>0x00001F10</resetValue>
<fields>
<field>
<name>PLL_FR</name>
<description>PLL_FR</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLL_MS</name>
<description>PLL_MS</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLL_NS</name>
<description>PLL_NS</description>
<bitOffset>8</bitOffset>
<bitWidth>9</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLL_FREF</name>
<description>PLL entry clock reference frequency</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLLCFGEN</name>
<description>PLL config enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MISC1</name>
<displayName>MISC1</displayName>
<description>Miscellaneous register1 </description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HICKCAL_KEY</name>
<description>HICKCAL write key value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLKOUT_SEL3</name>
<description>Clock output bit3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HICKDIV</name>
<description>HICK 6 divider selection</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLKOUTDIV</name>
<description>Clock output division</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MISC2</name>
<displayName>MISC2</displayName>
<description>Miscellaneous register2 </description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<resetValue>0x0000000D</resetValue>
<fields>
<field>
<name>AUTO_STEP_EN</name>
<description>AUTO_STEP_EN</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HICK_TO_SCLK</name>
<description>HICK to system clock</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOA</name>
<description>General purpose I/Os</description>
<groupName>GPIO</groupName>
<baseAddress>0x48000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CFGR</name>
<displayName>CFGR</displayName>
<description>GPIO configuration register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IOMC15</name>
<description>GPIOx pin 15 mode configurate</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IOMC14</name>
<description>GPIOx pin 14 mode configurate</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IOMC13</name>
<description>GPIOx pin 13 mode configurate</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IOMC12</name>
<description>GPIOx pin 12 mode configurate</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IOMC11</name>
<description>GPIOx pin 11 mode configurate</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IOMC10</name>
<description>GPIOx pin 10 mode configurate</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IOMC9</name>
<description>GPIOx pin 9 mode configurate</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IOMC8</name>
<description>GPIOx pin 8 mode configurate</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IOMC7</name>
<description>GPIOx pin 7 mode configurate</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IOMC6</name>
<description>GPIOx pin 6 mode configurate</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IOMC5</name>
<description>GPIOx pin 5 mode configurate</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IOMC4</name>
<description>GPIOx pin 4 mode configurate</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IOMC3</name>
<description>GPIOx pin 3 mode configurate</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IOMC2</name>
<description>GPIOx pin 2 mode configurate</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IOMC1</name>
<description>GPIOx pin 1 mode configurate</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IOMC0</name>
<description>GPIOx pin 0 mode configurate</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OMODE</name>
<displayName>OMODE</displayName>
<description>GPIO output mode register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OM15</name>
<description>GPIOx pin 15 outpu mode configurate</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OM14</name>
<description>GPIOx pin 14 outpu mode configurate</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OM13</name>
<description>GPIOx pin 13 outpu mode configurate</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OM12</name>
<description>GPIOx pin 12 outpu mode configurate</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OM11</name>
<description>GPIOx pin 11 outpu mode configurate</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OM10</name>
<description>GPIOx pin 10 outpu mode configurate</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OM9</name>
<description>GPIOx pin 9 outpu mode configurate</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OM8</name>
<description>GPIOx pin 8 outpu mode configurate</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OM7</name>
<description>GPIOx pin 7 outpu mode configurate</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OM6</name>
<description>GPIOx pin 6 outpu mode configurate</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OM5</name>
<description>GPIOx pin 5 outpu mode configurate</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OM4</name>
<description>GPIOx pin 4 outpu mode configurate</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OM3</name>
<description>GPIOx pin 3 outpu mode configurate</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OM2</name>
<description>GPIOx pin 2 outpu mode configurate</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OM1</name>
<description>GPIOx pin 1 outpu mode configurate</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OM0</name>
<description>GPIOx pin 0 outpu mode configurate</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ODRVR</name>
<displayName>ODRVR</displayName>
<description>GPIO drive capability register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ODRV15</name>
<description>GPIOx pin 15 output drive capability</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ODRV14</name>
<description>GPIOx pin 14 output drive capability</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ODRV13</name>
<description>GPIOx pin 13 output drive capability</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ODRV12</name>
<description>GPIOx pin 12 output drive capability</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ODRV11</name>
<description>GPIOx pin 11 output drive capability</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ODRV10</name>
<description>GPIOx pin 10 output drive capability</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ODRV9</name>
<description>GPIOx pin 9 output drive capability</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ODRV8</name>
<description>GPIOx pin 8 output drive capability</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ODRV7</name>
<description>GPIOx pin 7 output drive capability</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ODRV6</name>
<description>GPIOx pin 6 output drive capability</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ODRV5</name>
<description>GPIOx pin 5 output drive capability</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ODRV4</name>
<description>GPIOx pin 4 output drive capability</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ODRV3</name>
<description>GPIOx pin 3 output drive capability</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ODRV2</name>
<description>GPIOx pin 2 output drive capability</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ODRV1</name>
<description>GPIOx pin 1 output drive capability</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ODRV0</name>
<description>GPIOx pin 0 output drive capability</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PULL</name>
<displayName>PULL</displayName>
<description>GPIO pull-up/pull-down register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PULL15</name>
<description>GPIOx pin 15 pull configuration</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PULL14</name>
<description>GPIOx pin 14 pull configuration</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PULL13</name>
<description>GPIOx pin 13 pull configuration</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PULL12</name>
<description>GPIOx pin 12 pull configuration</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PULL11</name>
<description>GPIOx pin 11 pull configuration</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PULL10</name>
<description>GPIOx pin 10 pull configuration</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PULL9</name>
<description>GPIOx pin 9 pull configuration</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PULL8</name>
<description>GPIOx pin 8 pull configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PULL7</name>
<description>GPIOx pin 7 pull configuration</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PULL6</name>
<description>GPIOx pin 6 pull configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PULL5</name>
<description>GPIOx pin 5 pull configuration</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PULL4</name>
<description>GPIOx pin 4 pull configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PULL3</name>
<description>GPIOx pin 3 pull configuration</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PULL2</name>
<description>GPIOx pin 2 pull configuration</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PULL1</name>
<description>GPIOx pin 1 pull configuration</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PULL0</name>
<description>GPIOx pin 0 pull configuration</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDT</name>
<displayName>IDT</displayName>
<description>GPIO input data register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDT0</name>
<description>Port input data</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDT1</name>
<description>Port input data</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDT2</name>
<description>Port input data</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDT3</name>
<description>Port input data</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDT4</name>
<description>Port input data</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDT5</name>
<description>Port input data</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDT6</name>
<description>Port input data</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDT7</name>
<description>Port input data</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDT8</name>
<description>Port input data</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDT9</name>
<description>Port input data</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDT10</name>
<description>Port input data</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDT11</name>
<description>Port input data</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDT12</name>
<description>Port input data</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDT13</name>
<description>Port input data</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDT14</name>
<description>Port input data</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDT15</name>
<description>Port input data</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ODT</name>
<displayName>ODT</displayName>
<description>GPIO output data register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ODT0</name>
<description>Port output data</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODT1</name>
<description>Port output data</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODT2</name>
<description>Port output data</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODT3</name>
<description>Port output data</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODT4</name>
<description>Port output data</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODT5</name>
<description>Port output data</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODT6</name>
<description>Port output data</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODT7</name>
<description>Port output data</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODT8</name>
<description>Port output data</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODT9</name>
<description>Port output data</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODT10</name>
<description>Port output data</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODT11</name>
<description>Port output data</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODT12</name>
<description>Port output data</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODT13</name>
<description>Port output data</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODT14</name>
<description>Port output data</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODT15</name>
<description>Port output data</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<displayName>SCR</displayName>
<description>Port bit set/clear register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IOSB0</name>
<description>Set bit 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOSB1</name>
<description>Set bit 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOSB2</name>
<description>Set bit 1</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOSB3</name>
<description>Set bit 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOSB4</name>
<description>Set bit 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOSB5</name>
<description>Set bit 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOSB6</name>
<description>Set bit 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOSB7</name>
<description>Set bit 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOSB8</name>
<description>Set bit 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOSB9</name>
<description>Set bit 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOSB10</name>
<description>Set bit 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOSB11</name>
<description>Set bit 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOSB12</name>
<description>Set bit 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOSB13</name>
<description>Set bit 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOSB14</name>
<description>Set bit 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOSB15</name>
<description>Set bit 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB0</name>
<description>Clear bit 0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB1</name>
<description>Clear bit 1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB2</name>
<description>Clear bit 2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB3</name>
<description>Clear bit 3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB4</name>
<description>Clear bit 4</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB5</name>
<description>Clear bit 5</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB6</name>
<description>Clear bit 6</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB7</name>
<description>Clear bit 7</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB8</name>
<description>Clear bit 8</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB9</name>
<description>Clear bit 9</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB10</name>
<description>Clear bit 10</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB11</name>
<description>Clear bit 11</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB12</name>
<description>Clear bit 12</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB13</name>
<description>Clear bit 13</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB14</name>
<description>Clear bit 14</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB15</name>
<description>Clear bit 15</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPR</name>
<displayName>WPR</displayName>
<description>Port write protect
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WPEN0</name>
<description>Write protect enable 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPEN1</name>
<description>Write protect enable 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPEN2</name>
<description>Write protect enable 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPEN3</name>
<description>Write protect enable 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPEN4</name>
<description>Write protect enable 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPEN5</name>
<description>Write protect enable 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPEN6</name>
<description>Write protect enable 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPEN7</name>
<description>Write protect enable 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPEN8</name>
<description>Write protect enable 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPEN9</name>
<description>Write protect enable 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPEN10</name>
<description>Write protect enable 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPEN11</name>
<description>Write protect enable 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPEN12</name>
<description>Write protect enable 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPEN13</name>
<description>Write protect enable 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPEN14</name>
<description>Write protect enable 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPEN15</name>
<description>Write protect enable 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPSEQ</name>
<description>Write protect sequence</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MUXL</name>
<displayName>MUXL</displayName>
<description>GPIO muxing function low register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MUXL7</name>
<description>GPIOx pin 7 muxing</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MUXL6</name>
<description>GPIOx pin 6 muxing</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MUXL5</name>
<description>GPIOx pin 5 muxing</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MUXL4</name>
<description>GPIOx pin 4 muxing</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MUXL3</name>
<description>GPIOx pin 3 muxing</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MUXL2</name>
<description>GPIOx pin 2 muxing</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MUXL1</name>
<description>GPIOx pin 1 muxing</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MUXL0</name>
<description>GPIOx pin 0 muxing</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>MUXH</name>
<displayName>MUXH</displayName>
<description>GPIO muxing function high register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MUXH15</name>
<description>GPIOx pin 15 muxing</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MUXH14</name>
<description>GPIOx pin 14 muxing</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MUXH13</name>
<description>GPIOx pin 13 muxing</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MUXH12</name>
<description>GPIOx pin 12 muxing</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MUXH11</name>
<description>GPIOx pin 11 muxing</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MUXH10</name>
<description>GPIOx pin 10 muxing</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MUXH9</name>
<description>GPIOx pin 9 muxing</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MUXH8</name>
<description>GPIOx pin 8 muxing</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLR</name>
<displayName>CLR</displayName>
<description>GPIO bit reset register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IOCB0</name>
<description>Clear bit 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB1</name>
<description>Clear bit 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB2</name>
<description>Clear bit 1</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB3</name>
<description>Clear bit 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB4</name>
<description>Clear bit 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB5</name>
<description>Clear bit 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB6</name>
<description>Clear bit 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB7</name>
<description>Clear bit 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB8</name>
<description>Clear bit 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB9</name>
<description>Clear bit 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB10</name>
<description>Clear bit 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB11</name>
<description>Clear bit 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB12</name>
<description>Clear bit 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB13</name>
<description>Clear bit 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB14</name>
<description>Clear bit 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOCB15</name>
<description>Clear bit 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HDRV</name>
<displayName>HDRV</displayName>
<description>Huge current driver</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HDRV0</name>
<description>Port x driver bit y</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDRV1</name>
<description>Port x driver bit y</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDRV2</name>
<description>Port x driver bit y</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDRV3</name>
<description>Port x driver bit y</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDRV4</name>
<description>Port x driver bit y</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDRV5</name>
<description>Port x driver bit y</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDRV6</name>
<description>Port x driver bit y</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDRV7</name>
<description>Port x driver bit y</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDRV8</name>
<description>Port x driver bit y</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDRV9</name>
<description>Port x driver bit y</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDRV10</name>
<description>Port x driver bit y</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDRV11</name>
<description>Port x driver bit y</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDRV12</name>
<description>Port x driver bit y</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDRV13</name>
<description>Port x driver bit y</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDRV14</name>
<description>Port x driver bit y</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDRV15</name>
<description>Port x driver bit y</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="GPIOA">
<name>GPIOB</name>
<baseAddress>0x48000400</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOA">
<name>GPIOC</name>
<baseAddress>0x48000800</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOA">
<name>GPIOF</name>
<baseAddress>0x48001400</baseAddress>
</peripheral>
<peripheral>
<name>EXINT</name>
<description>EXINT</description>
<groupName>EXINT</groupName>
<baseAddress>0x40010400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PVM</name>
<description>PVM interrupt connect to EXTI line16</description>
<value>1</value>
</interrupt>
<interrupt>
<name>ERTC</name>
<description>ERTC interrupt connect to EXTI line17_19</description>
<value>2</value>
</interrupt>
<interrupt>
<name>EXTINT1_0</name>
<description>EXINT Line1_0 interrupt</description>
<value>5</value>
</interrupt>
<interrupt>
<name>EXTINT3_2</name>
<description>EXINT Line3_2 interrupt</description>
<value>6</value>
</interrupt>
<interrupt>
<name>EXTINT15_4</name>
<description>EXINT Line15_4 interrupt</description>
<value>7</value>
</interrupt>
<registers>
<register>
<name>INTEN</name>
<displayName>INTEN</displayName>
<description>Interrupt enable register (EXTINT_INTEN)</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INTEN0</name>
<description>Interrupt enable or disable on line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN1</name>
<description>Interrupt enable or disable on line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN2</name>
<description>Interrupt enable or disable on line 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN3</name>
<description>Interrupt enable or disable on line 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN4</name>
<description>Interrupt enable or disable on line 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN5</name>
<description>Interrupt enable or disable on line 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN6</name>
<description>Interrupt enable or disable on line 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN7</name>
<description>Interrupt enable or disable on line 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN8</name>
<description>Interrupt enable or disable on line 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN9</name>
<description>Interrupt enable or disable on line 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN10</name>
<description>Interrupt enable or disable on line 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN11</name>
<description>Interrupt enable or disable on line 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN12</name>
<description>Interrupt enable or disable on line 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN13</name>
<description>Interrupt enable or disable on line 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN14</name>
<description>Interrupt enable or disable on line 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN15</name>
<description>Interrupt enable or disable on line 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN16</name>
<description>Interrupt enable or disable on line 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN17</name>
<description>Interrupt enable or disable on line 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN19</name>
<description>Interrupt enable or disable on line 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTEN21</name>
<description>Interrupt enable or disable on line 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EVTEN</name>
<displayName>EVTEN</displayName>
<description>Event enable register (EXTINT_EVTEN)</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EVTEN0</name>
<description>Event enable or disable on line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN1</name>
<description>Event enable or disable on line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN2</name>
<description>Event enable or disable on line 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN3</name>
<description>Event enable or disable on line 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN4</name>
<description>Event enable or disable on line 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN5</name>
<description>Event enable or disable on line 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN6</name>
<description>Event enable or disable on line 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN7</name>
<description>Event enable or disable on line 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN8</name>
<description>Event enable or disable on line 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN9</name>
<description>Event enable or disable on line 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN10</name>
<description>Event enable or disable on line 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN11</name>
<description>Event enable or disable on line 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN12</name>
<description>Event enable or disable on line 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN13</name>
<description>Event enable or disable on line 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN14</name>
<description>Event enable or disable on line 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN15</name>
<description>Event enable or disable on line 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN16</name>
<description>Event enable or disable on line 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN17</name>
<description>Event enable or disable on line 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN19</name>
<description>Event enable or disable on line 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTEN21</name>
<description>Event enable or disable on line 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>POLCFG1</name>
<displayName>POLCFG1</displayName>
<description>Rising polarity configuration register(EXTINT_POLCFG1)</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RP0</name>
<description>Rising polarity configuration bit of line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP1</name>
<description>Rising polarity configuration bit of line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP2</name>
<description>Rising polarity configuration bit of line 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP3</name>
<description>Rising polarity configuration bit of line 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP4</name>
<description>Rising polarity configuration bit of line 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP5</name>
<description>Rising polarity configuration bit of line 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP6</name>
<description>Rising polarity configuration bit of linee 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP7</name>
<description>Rising polarity configuration bit of line 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP8</name>
<description>Rising polarity configuration bit of line 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP9</name>
<description>Rising polarity configuration bit of line 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP10</name>
<description>Rising polarity configuration bit of line 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP11</name>
<description>Rising polarity configuration bit of line 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP12</name>
<description>Rising polarity configuration bit of line 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP13</name>
<description>Rising polarity configuration bit of line 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP14</name>
<description>Rising polarity configuration bit of line 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP15</name>
<description>Rising polarity configuration bit of line 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP16</name>
<description>Rising polarity configuration bit of line 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP17</name>
<description>Rising polarity configuration bit of line 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP19</name>
<description>Rising polarity configuration bit of line 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RP21</name>
<description>Rising polarity configuration bit of line 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>POLCFG2</name>
<displayName>POLCFG2</displayName>
<description>Falling polarity configuration register(EXTINT_POLCFG2)</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FP0</name>
<description>Falling polarity event configuration bit of line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP1</name>
<description>Falling polarity event configuration bit of line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP2</name>
<description>Falling polarity event configuration bit of line 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP3</name>
<description>Falling polarity event configuration bit of line 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP4</name>
<description>Falling polarity event configuration bit of line 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP5</name>
<description>Falling polarity event configuration bit of line 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP6</name>
<description>Falling polarity event configuration bit of line 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP7</name>
<description>Falling polarity event configuration bit of line 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP8</name>
<description>Falling polarity event configuration bit of line 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP9</name>
<description>Falling polarity event configuration bit of line 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP10</name>
<description>Falling polarity event configuration bit of line 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP11</name>
<description>Falling polarity event configuration bit of line 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP12</name>
<description>Falling polarity event configuration bit of line 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP13</name>
<description>Falling polarity event configuration bit of line 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP14</name>
<description>Falling polarity event configuration bit of line 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP15</name>
<description>Falling polarity event configuration bit of line 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP16</name>
<description>Falling polarity event configuration bit of line 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP17</name>
<description>Falling polarity event configuration bit of line 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP19</name>
<description>Falling polarity event configuration bit of line 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FP21</name>
<description>Falling polarity event configuration bit of line 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWTRG</name>
<displayName>SWTRG</displayName>
<description>Software triggle register
(EXTINT_SWIE)</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWT0</name>
<description>Software triggle on line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT1</name>
<description>Software triggle on line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT2</name>
<description>Software triggle on line 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT3</name>
<description>Software triggle on line 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT4</name>
<description>Software triggle on line 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT5</name>
<description>Software triggle on line 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT6</name>
<description>Software triggle on line 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT7</name>
<description>Software triggle on line 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT8</name>
<description>Software triggle on line 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT9</name>
<description>Software triggle on line 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT10</name>
<description>Software triggle on line 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT11</name>
<description>Software triggle on line 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT12</name>
<description>Software triggle on line 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT13</name>
<description>Software triggle on line 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT14</name>
<description>Software triggle on line 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT15</name>
<description>Software triggle on line 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT16</name>
<description>Software triggle on line 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT17</name>
<description>Software triggle on line 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT19</name>
<description>Software triggle on line 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWT21</name>
<description>Software triggle on line 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INTSTS</name>
<displayName>INTSTS</displayName>
<description>Interrupt status register (EXTINT_INTSTS)</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LINE0</name>
<description>Line 0 state bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE1</name>
<description>Line 1 state bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE2</name>
<description>Line 2 state bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE3</name>
<description>Line 3 state bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE4</name>
<description>Line 4 state bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE5</name>
<description>Line 5 state bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE6</name>
<description>Line 6 state bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE7</name>
<description>Line 7 state bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE8</name>
<description>Line 8 state bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE9</name>
<description>Line 9 state bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE10</name>
<description>Line 10 state bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE11</name>
<description>Line 11 state bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE12</name>
<description>Line 12 state bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE13</name>
<description>Line 13 state bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE14</name>
<description>Line 14 state bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE15</name>
<description>Line 15 state bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE16</name>
<description>Line 16 state bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE17</name>
<description>Line 17 state bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE19</name>
<description>Line 19 state bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINE21</name>
<description>Line 21 state bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMA1</name>
<description>DMA controller</description>
<groupName>DMA</groupName>
<baseAddress>0x40020000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMA1_Channel1</name>
<description>DMA1 Channel1 global interrupt</description>
<value>9</value>
</interrupt>
<interrupt>
<name>DMA1_Channel3_2</name>
<description>DMA1 Channel2 global interrupt</description>
<value>10</value>
</interrupt>
<interrupt>
<name>DMA1_Channel5_4</name>
<description>DMA1 Channel3 global interrupt</description>
<value>11</value>
</interrupt>
<registers>
<register>
<name>STS</name>
<displayName>STS</displayName>
<description>DMA status register
(DMA_STS)</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GF1</name>
<description>Channel 1 Global event flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FDTF1</name>
<description>Channel 1 full data transfer event flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDTF1</name>
<description>Channel 1 half data transfer event flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRF1</name>
<description>Channel 1 data transfer error event flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GF2</name>
<description>Channel 2 Global event flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FDTF2</name>
<description>Channel 2 full data transfer event flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDTF2</name>
<description>Channel 2 half data transfer event flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRF2</name>
<description>Channel 2 data transfer error event flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GF3</name>
<description>Channel 3 Global event flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FDTF3</name>
<description>Channel 3 full data transfer event flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDTF3</name>
<description>Channel 3 half data transfer event flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRF3</name>
<description>Channel 3 data transfer error event flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GF4</name>
<description>Channel 4 Global event flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FDTF4</name>
<description>Channel 4 full data transfer event flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDTF4</name>
<description>Channel 4 half data transfer event flag</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRF4</name>
<description>Channel 4 data transfer error event flag</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GF5</name>
<description>Channel 5 Global event flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FDTF5</name>
<description>Channel 5 full data transfer event flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDTF5</name>
<description>Channel 5 half data transfer event flag</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRF5</name>
<description>Channel 5 data transfer error event flag</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLR</name>
<displayName>CLR</displayName>
<description>DMA flag clear register
(DMA_CLR)</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GFC1</name>
<description>Channel 1 Global flag clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GFC2</name>
<description>Channel 2 Global flag clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GFC3</name>
<description>Channel 3 Global flag clear</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GFC4</name>
<description>Channel 4 Global flag clear</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GFC5</name>
<description>Channel 5 Global flag clear</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FDTFC1</name>
<description>Channel 1 full data transfer flag clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FDTFC2</name>
<description>Channel 2 full data transfer flag clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FDTFC3</name>
<description>Channel 3 full data transfer flag clear</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FDTFC4</name>
<description>Channel 4 full data transfer flag clear</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FDTFC5</name>
<description>Channel 5 full data transfer flag clear</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDTFC1</name>
<description>Channel 1 half data transfer flag clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDTFC2</name>
<description>Channel 2 half data transfer flag clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDTFC3</name>
<description>Channel 3 half data transfer flag clear</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDTFC4</name>
<description>Channel 4 half data transfer flag clear</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDTFC5</name>
<description>Channel 5 half data transfer flag clear</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRFC1</name>
<description>Channel 1 data transfer error flag clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRFC2</name>
<description>Channel 2 data transfer error flag clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRFC3</name>
<description>Channel 3 data transfer error flag clear</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRFC4</name>
<description>Channel 4 data transfer error flag clear</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRFC5</name>
<description>Channel 5 data transfer error flag clear</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1CTRL</name>
<displayName>C1CTRL</displayName>
<description>DMA channel configuration register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CHEN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FDTIEN</name>
<description>Full data transfer interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDTIEN</name>
<description>Half data transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRIEN</name>
<description>Data transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTD</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LM</name>
<description>Loop mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINCM</name>
<description>Peripheral address increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINCM</name>
<description>Memory address increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWIDTH</name>
<description>Peripheral data bit width</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MWIDTH</name>
<description>Memory data bit width</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CHPL</name>
<description>Channel Priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>M2M</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1DTCNT</name>
<displayName>C1DTCNT</displayName>
<description>DMA channel 1 number of data to transfer register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1PADDR</name>
<displayName>C1PADDR</displayName>
<description>DMA channel 1 peripheral base address register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PADDR</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1MADDR</name>
<displayName>C1MADDR</displayName>
<description>DMA channel 1 memory base address register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MADDR</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2CTRL</name>
<displayName>C2CTRL</displayName>
<description>DMA channel configuration register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CHEN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FDTIEN</name>
<description>Full data transfer interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDTIEN</name>
<description>Half data transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRIEN</name>
<description>Data transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTD</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LM</name>
<description>Loop mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINCM</name>
<description>Peripheral address increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINCM</name>
<description>Memory address increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWIDTH</name>
<description>Peripheral data bit width</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MWIDTH</name>
<description>Memory data bit width</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CHPL</name>
<description>Channel Priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>M2M</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2DTCNT</name>
<displayName>C2DTCNT</displayName>
<description>DMA channel 2 number of data to transfer register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2PADDR</name>
<displayName>C2PADDR</displayName>
<description>DMA channel 2 peripheral base address register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PADDR</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2MADDR</name>
<displayName>C2MADDR</displayName>
<description>DMA channel 2 memory base address register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MADDR</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3CTRL</name>
<displayName>C3CTRL</displayName>
<description>DMA channel configuration register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CHEN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FDTIEN</name>
<description>Full data transfer interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDTIEN</name>
<description>Half data transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRIEN</name>
<description>Data transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTD</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LM</name>
<description>Loop mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINCM</name>
<description>Peripheral address increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINCM</name>
<description>Memory address increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWIDTH</name>
<description>Peripheral data bit width</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MWIDTH</name>
<description>Memory data bit width</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CHPL</name>
<description>Channel Priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>M2M</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3DTCNT</name>
<displayName>C3DTCNT</displayName>
<description>DMA channel 3 number of data to transfer register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3PADDR</name>
<displayName>C3PADDR</displayName>
<description>DMA channel 3 peripheral base address register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PADDR</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3MADDR</name>
<displayName>C3MADDR</displayName>
<description>DMA channel 3 memory base address register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MADDR</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4CTRL</name>
<displayName>C4CTRL</displayName>
<description>DMA channel configuration register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CHEN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FDTIEN</name>
<description>Full data transfer interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDTIEN</name>
<description>Half data transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRIEN</name>
<description>Data transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTD</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LM</name>
<description>Loop mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINCM</name>
<description>Peripheral address increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINCM</name>
<description>Memory address increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWIDTH</name>
<description>Peripheral data bit width</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MWIDTH</name>
<description>Memory data bit width</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CHPL</name>
<description>Channel Priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>M2M</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4DTCNT</name>
<displayName>C4DTCNT</displayName>
<description>DMA channel 4 number of data to transfer register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4PADDR</name>
<displayName>C4PADDR</displayName>
<description>DMA channel 4 peripheral base address register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PADDR</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4MADDR</name>
<displayName>C4MADDR</displayName>
<description>DMA channel 4 memory base address register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MADDR</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5CTRL</name>
<displayName>C5CTRL</displayName>
<description>DMA channel configuration register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CHEN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FDTIEN</name>
<description>Full data transfer interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDTIEN</name>
<description>Half data transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRIEN</name>
<description>Data transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTD</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LM</name>
<description>Loop mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINCM</name>
<description>Peripheral address increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINCM</name>
<description>Memory address increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWIDTH</name>
<description>Peripheral data bit width</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MWIDTH</name>
<description>Memory data bit width</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CHPL</name>
<description>Channel Priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>M2M</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5DTCNT</name>
<displayName>C5DTCNT</displayName>
<description>DMA channel 5 number of data to transfer register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5PADDR</name>
<displayName>C5PADDR</displayName>
<description>DMA channel 5 peripheral base address register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PADDR</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5MADDR</name>
<displayName>C5MADDR</displayName>
<description>DMA channel 5 memory base address register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MADDR</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ERTC</name>
<description>Real-time clock</description>
<groupName>ERTC</groupName>
<baseAddress>0x40002800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>TIME</name>
<displayName>TIME</displayName>
<description>time register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AMPM</name>
<description>AM/PM notation</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HT</name>
<description>Hour tens</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>HU</name>
<description>Hour units</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MT</name>
<description>Minute tens</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MU</name>
<description>Minute units</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ST</name>
<description>Second tens</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SU</name>
<description>Second units</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATE</name>
<displayName>DATE</displayName>
<description>date register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00002101</resetValue>
<fields>
<field>
<name>YT</name>
<description>Year tens</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>YU</name>
<description>Year units</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>WK</name>
<description>Week</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MT</name>
<description>Month tens</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MU</name>
<description>Month units</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DT</name>
<description>Date tens</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DU</name>
<description>Date units</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<displayName>CTRL</displayName>
<description>control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CALOEN</name>
<description>Calibration output enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTSEL</name>
<description>Output source selection</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OUTP</name>
<description>Output polarity</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALOSEL</name>
<description>Calibration output selection</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BPR</name>
<description>Battery power domain data register</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEC1H</name>
<description>Decrease 1 hour</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADD1H</name>
<description>Add 1 hour</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSIEN</name>
<description>Timestamp interrupt enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALAIEN</name>
<description>Alarm A interrupt enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSEN</name>
<description>Timestamp enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALAEN</name>
<description>Alarm A enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HM</name>
<description>Hour mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DREN</name>
<description>Date/time register direct read enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCDEN</name>
<description>Reference clock detection enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSEDG</name>
<description>Timestamp trigger edge</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>STS</name>
<displayName>STS</displayName>
<description>initialization and status
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<resetValue>0x00000007</resetValue>
<fields>
<field>
<name>ALAWF</name>
<description>Alarm A register allows write flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TADJF</name>
<description>Time adjustment flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INITF</name>
<description>Calendar initialization flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>UPDF</name>
<description>Calendar update flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IMF</name>
<description>Enter initialization mode flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>IMEN</name>
<description>Initialization mode enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ALAF</name>
<description>Alarm A flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TSF</name>
<description>Timestamp flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TSOF</name>
<description>Timestamp overflow flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TP1F</name>
<description>Tamper detection 1 flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CALUPDF</name>
<description>Calibration value update completed flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DIV</name>
<displayName>DIV</displayName>
<description>Diveder register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x007F00FF</resetValue>
<fields>
<field>
<name>DIVA</name>
<description>Diveder A</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>DIVB</name>
<description>Diveder B</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>ALA</name>
<displayName>ALA</displayName>
<description>Alarm A register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MASK4</name>
<description>Date/week mask</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKSEL</name>
<description>Date/week mode select</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT</name>
<description>Date tens</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DU</name>
<description>Date units</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MASK3</name>
<description>Hours mask</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AMPM</name>
<description>AM/PM</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HT</name>
<description>Hour tens</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>HU</name>
<description>Hour units</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MASK2</name>
<description>Minutes mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MT</name>
<description>Minute tens</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MU</name>
<description>Minute units</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MASK1</name>
<description>Seconds mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST</name>
<description>Second tens</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SU</name>
<description>Second units</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>WP</name>
<displayName>WP</displayName>
<description>write protection register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMD</name>
<description>Command register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SBS</name>
<displayName>SBS</displayName>
<description>sub second register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SBS</name>
<description>Sub second value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TADJ</name>
<displayName>TADJ</displayName>
<description>time adjust register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD1S</name>
<description>Add 1 second</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DECSBS</name>
<description>Decrease sub-second value</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSTM</name>
<displayName>TSTM</displayName>
<description>time stamp time register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AMPM</name>
<description>AMPM</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HT</name>
<description>Hour tens</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>HU</name>
<description>Hour units</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MT</name>
<description>Minute tens</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MU</name>
<description>Minute units</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ST</name>
<description>Second tens</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SU</name>
<description>Second units</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSDT</name>
<displayName>TSDT</displayName>
<description>timestamp date register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WK</name>
<description>Week</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MT</name>
<description>Month tens</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MU</name>
<description>Month units</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DT</name>
<description>Date tens</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DU</name>
<description>Date units</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSSBS</name>
<displayName>TSSBS</displayName>
<description>timestamp sub second register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SBS</name>
<description>Sub second value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCAL</name>
<displayName>SCAL</displayName>
<description>calibration register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>Add ERTC clock</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAL8</name>
<description>8-second calibration period</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAL16</name>
<description>16 second calibration period</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEC</name>
<description>Decrease ERTC clock</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>TAMP</name>
<displayName>TAMP</displayName>
<description>tamper and alternate function configuration
register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUTTYPE</name>
<description>Output type</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TPPU</name>
<description>Tamper detection pull-up</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TPPR</name>
<description>Tamper detection pre-charge time</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TPFLT</name>
<description>Tamper detection filter time</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TPFREQ</name>
<description>Tamper detection frequency</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TPTSEN</name>
<description>Tamper detection timestamp enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TPIEN</name>
<description>Tamper detection interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TP1EDG</name>
<description>Tamper detection 1 valid edge</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TP1EN</name>
<description>Tamper detection 1 enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ALASBS</name>
<displayName>ALASBS</displayName>
<description>alarm A sub second register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SBSMSK</name>
<description>Sub-second mask</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SBS</name>
<description>Sub-seconds value</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>BPR1DT</name>
<displayName>BPR1DT</displayName>
<description>Battery powered domain register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DT</name>
<description>Battery powered domain data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BPR2DT</name>
<displayName>BPR2DT</displayName>
<description>Battery powered domain register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DT</name>
<description>Battery powered domain data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BPR3DT</name>
<displayName>BPR3DT</displayName>
<description>Battery powered domain register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DT</name>
<description>Battery powered domain data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BPR4DT</name>
<displayName>BPR4DT</displayName>
<description>Battery powered domain register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DT</name>
<description>Battery powered domain data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BPR5DT</name>
<displayName>BPR5DT</displayName>
<description>Battery powered domain register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DT</name>
<description>Battery powered domain data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>WDT</name>
<description>Watchdog</description>
<groupName>WDT</groupName>
<baseAddress>0x40003000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CMD</name>
<displayName>CMD</displayName>
<description>Command register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMD</name>
<description>Command register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIV</name>
<displayName>DIV</displayName>
<description>Division register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIV</name>
<description>Division divider</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLD</name>
<displayName>RLD</displayName>
<description>Reload register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000FFF</resetValue>
<fields>
<field>
<name>RLD</name>
<description>Reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>STS</name>
<displayName>STS</displayName>
<description>Status register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIVF</name>
<description>Division value update complete flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RLDF</name>
<description>Reload value update complete flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>WWDT</name>
<description>Window watchdog</description>
<groupName>WWDT</groupName>
<baseAddress>0x40002C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>WWDT</name>
<description>Window Watchdog interrupt</description>
<value>0</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<displayName>CTRL</displayName>
<description>Control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000007F</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Decrement counter</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>WWDTEN</name>
<description>Window watchdog enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFG</name>
<displayName>CFG</displayName>
<description>Configuration register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000007F</resetValue>
<fields>
<field>
<name>WIN</name>
<description>Window value</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>DIV</name>
<description>Clock division value</description>
<bitOffset>7</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RLDIEN</name>
<description>Reload counter interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>STS</name>
<displayName>STS</displayName>
<description>Status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RLDF</name>
<description>Reload counter interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TMR1</name>
<description>Advanced timer</description>
<groupName>TIMER</groupName>
<baseAddress>0x40012C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TMR1_CH</name>
<description>TMR1 channel interrupt</description>
<value>14</value>
</interrupt>
<interrupt>
<name>TMR1_BRK_OVF_TRG_HALL</name>
<description>TMR1 overflow brake trigger hall interrupt</description>
<value>13</value>
</interrupt>
<registers>
<register>
<name>CTRL1</name>
<displayName>CTRL1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CLKDIV</name>
<description>Clock divider</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PRBEN</name>
<description>Period buffer enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TWCMSEL</name>
<description>Two-way count mode
selection</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OWCDIR</name>
<description>One-way count direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OCMEN</name>
<description>One cycle mode enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFS</name>
<description>Overflow event source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFEN</name>
<description>Overflow event enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMREN</name>
<description>TMR enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL2</name>
<displayName>CTRL2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>C4IOS</name>
<description>Channel 4 idle output state</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3CIOS</name>
<description>Channel 3 complementary idle output state</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3IOS</name>
<description>Channel 3 idle output state</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2CIOS</name>
<description>Channel 2 complementary idle output state</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2IOS</name>
<description>Channel 2 idle output state</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1CIOS</name>
<description>Channel 1 complementary idle output state</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1IOS</name>
<description>Channel 1 idle output state</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1INSEL</name>
<description>C1IN selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PTOS</name>
<description>Primary TMR output selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DRS</name>
<description>DMA request source</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCFS</name>
<description>Channel control bit fresh select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBCTRL</name>
<description>Channel buffer control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>STCTRL</name>
<displayName>STCTRL</displayName>
<description>Subordinate TMR control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ESP</name>
<description>External signal polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECMBEN</name>
<description>External clock mode B enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESDIV</name>
<description>External signal divider</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ESF</name>
<description>External signal filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STS</name>
<description>Subordinate TMR synchronization</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STIS</name>
<description>Subordinate TMR input selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMSEL</name>
<description>Subordinate TMR mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDEN</name>
<displayName>IDEN</displayName>
<description>Interrupt/DMA enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TDEN</name>
<description>Trigger DMA request enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HALLDE</name>
<description>HALL DMA request enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C4DEN</name>
<description>Channel 4 DMA request
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3DEN</name>
<description>Channel 3 DMA request
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2DEN</name>
<description>Channel 2 DMA request
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1DEN</name>
<description>Channel 1 DMA request
enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFDEN</name>
<description>Overflow DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRKIE</name>
<description>Brake interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIEN</name>
<description>Trigger interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HALLIEN</name>
<description>HALL interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C4IEN</name>
<description>Channel 4 interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3IEN</name>
<description>Channel 3 interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2IEN</name>
<description>Channel 2 interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1IEN</name>
<description>Channel 1 interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFIEN</name>
<description>Overflow interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISTS</name>
<displayName>ISTS</displayName>
<description>Interrupt status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>C4RF</name>
<description>Channel 4 recapture flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3RF</name>
<description>Channel 3 recapture flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2RF</name>
<description>Channel 2 recapture flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1RF</name>
<description>Channel 1 recapture flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRKIF</name>
<description>Brake interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRGIF</name>
<description>Trigger interrupt flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HALLIF</name>
<description>HALL interrupt flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C4IF</name>
<description>Channel 4 interrupt flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3IF</name>
<description>Channel 3 interrupt flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2IF</name>
<description>Channel 2 interrupt flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1IF</name>
<description>Channel 1 interrupt flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFIF</name>
<description>Overflow interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWEVT</name>
<displayName>SWEVT</displayName>
<description>Software event register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BRKSWTR</name>
<description>Brake event triggered by software</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRGSWTR</name>
<description>Trigger event triggered by software</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HALLSWTR</name>
<description>HALL event triggered by software</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C4SWTR</name>
<description>Channel 4 event triggered by software</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3SWTR</name>
<description>Channel 3 event triggered by software</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2SWTR</name>
<description>Channel 2 event triggered by software</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1SWTR</name>
<description>Channel 1 event triggered by software</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFSWTR</name>
<description>Overflow event triggered by software</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM1_OUTPUT</name>
<displayName>CM1_OUTPUT</displayName>
<description>Channel output mode register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C2OSEN</name>
<description>Channel 2 output switch enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2OCTRL</name>
<description>Channel 2 output control</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>C2OBEN</name>
<description>Channel 2 output buffer enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2OIEN</name>
<description>Channel 2 output immediately enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2C</name>
<description>Channel 2 configure</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C1OSEN</name>
<description>Channel 1 output switch enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1OCTRL</name>
<description>Channel 1 output control</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>C1OBEN</name>
<description>Channel 1 output buffer enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1OIEN</name>
<description>Channel 1 output immediately enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1C</name>
<description>Channel 1 configure</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM1_INPUT</name>
<displayName>CM1_INPUT</displayName>
<description>Channel input mode register 1</description>
<alternateRegister>CM1_OUTPUT</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C2DF</name>
<description>Channel 2 digital filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>C2IDIV</name>
<description>Channel 2 input divider</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C2C</name>
<description>Channel 2 configure</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C1DF</name>
<description>Channel 1 digital filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>C1IDIV</name>
<description>Channel 1 input divider</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C1C</name>
<description>Channel 1 configure</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM2_OUTPUT</name>
<displayName>CM2_OUTPUT</displayName>
<description>Channel output mode register 2</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C4OSEN</name>
<description>Channel 4 output switch enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C4OCTRL</name>
<description>Channel 4 output control</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>C4OBEN</name>
<description>Channel 4 output buffer enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C4OIEN</name>
<description>Channel 4 output immediately enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C4C</name>
<description>Channel 4 configure</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C3OSEN</name>
<description>Channel 3 output switch enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3OCTRL</name>
<description>Channel 3 output control</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>C3OBEN</name>
<description>Channel 3 output buffer enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3OIEN</name>
<description>Channel 3 output immediately enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3C</name>
<description>Channel 3 configure</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM2_INPUT</name>
<displayName>CM2_INPUT</displayName>
<description>Channel input mode register 2</description>
<alternateRegister>CM2_OUTPUT</alternateRegister>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C4DF</name>
<description>Channel 4 digital filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>C4IDIV</name>
<description>Channel 4 input divider</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C4C</name>
<description>Channel 4 configure</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C3DF</name>
<description>Channel 3 digital filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>C3IDIV</name>
<description>Channel 3 input divider</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C3C</name>
<description>Channel 3 configure</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCTRL</name>
<displayName>CCTRL</displayName>
<description>Channel control
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>C4P</name>
<description>Channel 4 Polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C4EN</name>
<description>Channel 4 enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3CP</name>
<description>Channel 3 complementary polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3CEN</name>
<description>Channel 3 complementary enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3P</name>
<description>Channel 3 Polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3EN</name>
<description>Channel 3 enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2CP</name>
<description>Channel 2 complementary polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2CEN</name>
<description>Channel 2 complementary enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2P</name>
<description>Channel 2 Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2EN</name>
<description>Channel 2 enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1CP</name>
<description>Channel 1 complementary polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1CEN</name>
<description>Channel 1 complementary enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1P</name>
<description>Channel 1 Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1EN</name>
<description>Channel 1 enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CVAL</name>
<displayName>CVAL</displayName>
<description>Counter value</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CVAL</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIV</name>
<displayName>DIV</displayName>
<description>Divider value</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DIV</name>
<description>Divider value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PR</name>
<displayName>PR</displayName>
<description>Period value</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PR</name>
<description>Period value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RPR</name>
<displayName>RPR</displayName>
<description>Repetition of period value</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>RPR</name>
<description>Repetition of period value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1DT</name>
<displayName>C1DT</displayName>
<description>Channel 1 data register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C1DT</name>
<description>Channel 1 data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2DT</name>
<displayName>C2DT</displayName>
<description>Channel 2 data register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C2DT</name>
<description>Channel 2 data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3DT</name>
<displayName>C3DT</displayName>
<description>Channel 3 data register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C3DT</name>
<description>Channel 3 data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4DT</name>
<displayName>C4DT</displayName>
<description>Channel 4 data register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C4DT</name>
<description>Channel 4 data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRK</name>
<displayName>BRK</displayName>
<description>Brake register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>OEN</name>
<description>Output enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AOEN</name>
<description>Automatic output enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRKV</name>
<description>Brake input validity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRKEN</name>
<description>Brake enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCSOEN</name>
<description>Frozen channel status when
holistic output enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCSODIS</name>
<description>Frozen channel status when
holistic output disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPC</name>
<description>Write protected configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTC</name>
<description>Dead-time configuration</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMACTRL</name>
<displayName>DMACTRL</displayName>
<description>DMA control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DTB</name>
<description>DMA transfer bytes</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>ADDR</name>
<description>DMA transfer address offset</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMADT</name>
<displayName>DMADT</displayName>
<description>DMA data register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DMADT</name>
<description>DMA data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TMR3</name>
<description>General purpose timer</description>
<groupName>TIMER</groupName>
<baseAddress>0x40000400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TMR3</name>
<description>TMR3 global interrupt</description>
<value>16</value>
</interrupt>
<registers>
<register>
<name>CTRL1</name>
<displayName>CTRL1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CLKDIV</name>
<description>Clock divider</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PRBEN</name>
<description>Period buffer enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TWCMSEL</name>
<description>Two-way count mode
selection</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OWCDIR</name>
<description>One-way count direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OCMEN</name>
<description>One cycle mode enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFS</name>
<description>Overflow event source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFEN</name>
<description>Overflow event enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMREN</name>
<description>TMR enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL2</name>
<displayName>CTRL2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>C1INSEL</name>
<description>C1IN selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PTOS</name>
<description>Primary TMR output selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DRS</name>
<description>DMA request source</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>STCTRL</name>
<displayName>STCTRL</displayName>
<description>Subordinate TMR control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ESP</name>
<description>External signal polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECMBEN</name>
<description>External clock mode B enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESDIV</name>
<description>External signal divider</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ESF</name>
<description>External signal filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STS</name>
<description>Subordinate TMR synchronization</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STIS</name>
<description>Subordinate TMR input selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMSEL</name>
<description>Subordinate TMR mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDEN</name>
<displayName>IDEN</displayName>
<description>Interrupt/DMA enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TDEN</name>
<description>Trigger DMA request enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C4DEN</name>
<description>Channel 4 DMA request
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3DEN</name>
<description>Channel 3 DMA request
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2DEN</name>
<description>Channel 2 DMA request
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1DEN</name>
<description>Channel 1 DMA request
enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFDEN</name>
<description>Overflow DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIEN</name>
<description>Trigger interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C4IEN</name>
<description>Channel 4 interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3IEN</name>
<description>Channel 3 interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2IEN</name>
<description>Channel 2 interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1IEN</name>
<description>Channel 1 interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFIEN</name>
<description>Overflow interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISTS</name>
<displayName>ISTS</displayName>
<description>Interrupt status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>C4RF</name>
<description>Channel 4 recapture flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3RF</name>
<description>Channel 3 recapture flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2RF</name>
<description>Channel 2 recapture flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1RF</name>
<description>Channel 1 recapture flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRGIF</name>
<description>Trigger interrupt flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C4IF</name>
<description>Channel 4 interrupt flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3IF</name>
<description>Channel 3 interrupt flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2IF</name>
<description>Channel 2 interrupt flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1IF</name>
<description>Channel 1 interrupt flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFIF</name>
<description>Overflow interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWEVT</name>
<displayName>SWEVT</displayName>
<description>Software event register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TRGSWTR</name>
<description>Trigger event triggered by software</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C4SWTR</name>
<description>Channel 4 event triggered by software</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3SWTR</name>
<description>Channel 3 event triggered by software</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2SWTR</name>
<description>Channel 2 event triggered by software</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1SWTR</name>
<description>Channel 1 event triggered by software</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFSWTR</name>
<description>Overflow event triggered by software</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM1_OUTPUT</name>
<displayName>CM1_OUTPUT</displayName>
<description>Channel output mode register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C2OSEN</name>
<description>Channel 2 output switch enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2OCTRL</name>
<description>Channel 2 output control</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>C2OBEN</name>
<description>Channel 2 output buffer enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2OIEN</name>
<description>Channel 2 output immediately enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2C</name>
<description>Channel 2 configure</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C1OSEN</name>
<description>Channel 1 output switch enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1OCTRL</name>
<description>Channel 1 output control</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>C1OBEN</name>
<description>Channel 1 output buffer enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1OIEN</name>
<description>Channel 1 output immediately enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1C</name>
<description>Channel 1 configure</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM1_INPUT</name>
<displayName>CM1_INPUT</displayName>
<description>Channel input mode register 1</description>
<alternateRegister>CM1_OUTPUT</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C2DF</name>
<description>Channel 2 digital filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>C2IDIV</name>
<description>Channel 2 input divider</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C2C</name>
<description>Channel 2 configure</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C1DF</name>
<description>Channel 1 digital filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>C1IDIV</name>
<description>Channel 1 input divider</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C1C</name>
<description>Channel 1 configure</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM2_OUTPUT</name>
<displayName>CM2_OUTPUT</displayName>
<description>Channel output mode register 2</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C4OSEN</name>
<description>Channel 4 output switch enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C4OCTRL</name>
<description>Channel 4 output control</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>C4OBEN</name>
<description>Channel 4 output buffer enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C4OIEN</name>
<description>Channel 4 output immediately enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C4C</name>
<description>Channel 4 configure</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C3OSEN</name>
<description>Channel 3 output switch enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3OCTRL</name>
<description>Channel 3 output control</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>C3OBEN</name>
<description>Channel 3 output buffer enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3OIEN</name>
<description>Channel 3 output immediately enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3C</name>
<description>Channel 3 configure</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM2_INPUT</name>
<displayName>CM2_INPUT</displayName>
<description>Channel input mode register 2</description>
<alternateRegister>CM2_OUTPUT</alternateRegister>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C4DF</name>
<description>Channel 4 digital filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>C4IDIV</name>
<description>Channel 4 input divider</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C4C</name>
<description>Channel 4 configure</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C3DF</name>
<description>Channel 3 digital filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>C3IDIV</name>
<description>Channel 3 input divider</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C3C</name>
<description>Channel 3 configure</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCTRL</name>
<displayName>CCTRL</displayName>
<description>Channel control
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>C4P</name>
<description>Channel 4 Polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C4EN</name>
<description>Channel 4 enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3P</name>
<description>Channel 3 Polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C3EN</name>
<description>Channel 3 enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2P</name>
<description>Channel 2 Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2EN</name>
<description>Channel 2 enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1P</name>
<description>Channel 1 Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1EN</name>
<description>Channel 1 enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CVAL</name>
<displayName>CVAL</displayName>
<description>Counter value</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CVAL</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIV</name>
<displayName>DIV</displayName>
<description>Divider value</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DIV</name>
<description>Divider value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PR</name>
<displayName>PR</displayName>
<description>Period value</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PR</name>
<description>Period value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1DT</name>
<displayName>C1DT</displayName>
<description>Channel 1 data register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C1DT</name>
<description>Channel 1 data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2DT</name>
<displayName>C2DT</displayName>
<description>Channel 2 data register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C2DT</name>
<description>Channel 2 data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3DT</name>
<displayName>C3DT</displayName>
<description>Channel 3 data register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C3DT</name>
<description>Channel 3 data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4DT</name>
<displayName>C4DT</displayName>
<description>Channel 4 data register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C4DT</name>
<description>Channel 4 data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMACTRL</name>
<displayName>DMACTRL</displayName>
<description>DMA control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DTB</name>
<description>DMA transfer bytes</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>ADDR</name>
<description>DMA transfer address offset</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMADT</name>
<displayName>DMADT</displayName>
<description>DMA data register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DMADT</name>
<description>DMA data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TMR14</name>
<description>General purpose timer</description>
<groupName>TIMER</groupName>
<baseAddress>0x40002000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TMR14</name>
<description>TMR14 global interrupt</description>
<value>19</value>
</interrupt>
<registers>
<register>
<name>CTRL1</name>
<displayName>CTRL1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CLKDIV</name>
<description>Clock divider</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PRBEN</name>
<description>Period buffer enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFS</name>
<description>Overflow event source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFEN</name>
<description>Overflow event enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMREN</name>
<description>TMR enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDEN</name>
<displayName>IDEN</displayName>
<description>Interrupt/DMA enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>C1IEN</name>
<description>Channel 1 interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFIEN</name>
<description>Overflow interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISTS</name>
<displayName>ISTS</displayName>
<description>Interrupt status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>C1RF</name>
<description>Channel 1 recapture flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1IF</name>
<description>Channel 1 interrupt flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFIF</name>
<description>Overflow interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWEVT</name>
<displayName>SWEVT</displayName>
<description>Software event register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>C1SWTR</name>
<description>Channel 1 event triggered by software</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFSWTR</name>
<description>Overflow event triggered by software</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM1_OUTPUT</name>
<displayName>CM1_OUTPUT</displayName>
<description>Channel output mode register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C1OCTRL</name>
<description>Channel 1 output control</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>C1OBEN</name>
<description>Channel 1 output buffer enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1OIEN</name>
<description>Channel 1 output immediately enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1C</name>
<description>Channel 1 configure</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM1_INPUT</name>
<displayName>CM1_INPUT</displayName>
<description>Channel input mode register 1</description>
<alternateRegister>CM1_OUTPUT</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C1DF</name>
<description>Channel 1 digital filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>C1IDIV</name>
<description>Channel 1 input divider</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C1C</name>
<description>Channel 1 configure</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCTRL</name>
<displayName>CCTRL</displayName>
<description>Channel control
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>C1CP</name>
<description>Channel 1 complementary polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1P</name>
<description>Channel 1 Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1EN</name>
<description>Channel 1 enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CVAL</name>
<displayName>CVAL</displayName>
<description>Counter value</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CVAL</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIV</name>
<displayName>DIV</displayName>
<description>Divider value</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DIV</name>
<description>Divider value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PR</name>
<displayName>PR</displayName>
<description>Period value</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PR</name>
<description>Period value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1DT</name>
<displayName>C1DT</displayName>
<description>Channel 1 data register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C1DT</name>
<description>Channel 1 data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TMR15</name>
<description>Advanced timer</description>
<groupName>TIMER</groupName>
<baseAddress>0x40014000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TMR15</name>
<description>TMR15 global interrupt</description>
<value>20</value>
</interrupt>
<registers>
<register>
<name>CTRL1</name>
<displayName>CTRL1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CLKDIV</name>
<description>Clock divider</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PRBEN</name>
<description>Period buffer enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OCMEN</name>
<description>One cycle mode enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFS</name>
<description>Overflow event source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFEN</name>
<description>Overflow event enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMREN</name>
<description>TMR enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL2</name>
<displayName>CTRL2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>C2IOS</name>
<description>Channel 2 idle output state</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1CIOS</name>
<description>Channel 1 complementary idle output state</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1IOS</name>
<description>Channel 1 idle output state</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PTOS</name>
<description>Primary TMR output selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DRS</name>
<description>DMA request source</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCFS</name>
<description>Channel control bit fresh select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBCTRL</name>
<description>Channel buffer control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>STCTRL</name>
<displayName>STCTRL</displayName>
<description>Subordinate TMR control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>STS</name>
<description>Subordinate TMR synchronization</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STIS</name>
<description>Subordinate TMR input selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMSEL</name>
<description>Subordinate TMR mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDEN</name>
<displayName>IDEN</displayName>
<description>Interrupt/DMA enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TDEN</name>
<description>Trigger DMA request enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HALLDE</name>
<description>HALL DMA request enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2DEN</name>
<description>Channel 2 DMA request
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1DEN</name>
<description>Channel 1 DMA request
enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFDEN</name>
<description>Overflow DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRKIE</name>
<description>Brake interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIEN</name>
<description>Trigger interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HALLIEN</name>
<description>HALL interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2IEN</name>
<description>Channel 2 interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1IEN</name>
<description>Channel 1 interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFIEN</name>
<description>Overflow interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISTS</name>
<displayName>ISTS</displayName>
<description>Interrupt status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>C2RF</name>
<description>Channel 2 recapture flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1RF</name>
<description>Channel 1 recapture flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRKIF</name>
<description>Brake interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRGIF</name>
<description>Trigger interrupt flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HALLIF</name>
<description>HALL interrupt flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2IF</name>
<description>Channel 2 interrupt flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1IF</name>
<description>Channel 1 interrupt flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFIF</name>
<description>Overflow interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWEVT</name>
<displayName>SWEVT</displayName>
<description>Software event register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BRKSWTR</name>
<description>Brake event triggered by software</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRGSWTR</name>
<description>Trigger event triggered by software</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HALLSWTR</name>
<description>HALL event triggered by software</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2SWTR</name>
<description>Channel 2 event triggered by software</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1SWTR</name>
<description>Channel 1 event triggered by software</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFSWTR</name>
<description>Overflow event triggered by software</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM1_OUTPUT</name>
<displayName>CM1_OUTPUT</displayName>
<description>Channel output mode register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C2OSEN</name>
<description>Channel 2 output switch enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2OCTRL</name>
<description>Channel 2 output control</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>C2OBEN</name>
<description>Channel 2 output buffer enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2OIEN</name>
<description>Channel 2 output immediately enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2C</name>
<description>Channel 2 configure</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C1OSEN</name>
<description>Channel 1 output switch enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1OCTRL</name>
<description>Channel 1 output control</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>C1OBEN</name>
<description>Channel 1 output buffer enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1OIEN</name>
<description>Channel 1 output immediately enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1C</name>
<description>Channel 1 configure</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM1_INPUT</name>
<displayName>CM1_INPUT</displayName>
<description>Channel input mode register 1</description>
<alternateRegister>CM1_OUTPUT</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C2DF</name>
<description>Channel 2 digital filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>C2IDIV</name>
<description>Channel 2 input divider</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C2C</name>
<description>Channel 2 configure</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C1DF</name>
<description>Channel 1 digital filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>C1IDIV</name>
<description>Channel 1 input divider</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C1C</name>
<description>Channel 1 configure</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCTRL</name>
<displayName>CCTRL</displayName>
<description>Channel control
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>C2P</name>
<description>Channel 2 Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2EN</name>
<description>Channel 2 enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1CP</name>
<description>Channel 1 complementary polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1CEN</name>
<description>Channel 1 complementary enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1P</name>
<description>Channel 1 Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1EN</name>
<description>Channel 1 enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CVAL</name>
<displayName>CVAL</displayName>
<description>Counter value</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CVAL</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIV</name>
<displayName>DIV</displayName>
<description>Divider value</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DIV</name>
<description>Divider value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PR</name>
<displayName>PR</displayName>
<description>Period value</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PR</name>
<description>Period value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RPR</name>
<displayName>RPR</displayName>
<description>Repetition of period value</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>RPR</name>
<description>Repetition of period value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1DT</name>
<displayName>C1DT</displayName>
<description>Channel 1 data register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C1DT</name>
<description>Channel 1 data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2DT</name>
<displayName>C2DT</displayName>
<description>Channel 2 data register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C2DT</name>
<description>Channel 2 data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRK</name>
<displayName>BRK</displayName>
<description>Brake register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>OEN</name>
<description>Output enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AOEN</name>
<description>Automatic output enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRKV</name>
<description>Brake input validity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRKEN</name>
<description>Brake enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCSOEN</name>
<description>Frozen channel status when
holistic output enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCSODIS</name>
<description>Frozen channel status when
holistic output disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPC</name>
<description>Write protected configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTC</name>
<description>Dead-time configuration</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMACTRL</name>
<displayName>DMACTRL</displayName>
<description>DMA control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DTB</name>
<description>DMA transfer bytes</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>ADDR</name>
<description>DMA transfer address offset</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMADT</name>
<displayName>DMADT</displayName>
<description>DMA data register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DMADT</name>
<description>DMA data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TMR16</name>
<description>General purpose timer</description>
<groupName>TIMER</groupName>
<baseAddress>0x40014400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TMR16</name>
<description>TMR16 global interrupt</description>
<value>21</value>
</interrupt>
<registers>
<register>
<name>CTRL1</name>
<displayName>CTRL1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CLKDIV</name>
<description>Clock divider</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PRBEN</name>
<description>Period buffer enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OCMEN</name>
<description>One cycle mode enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFS</name>
<description>Overflow event source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFEN</name>
<description>Overflow event enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMREN</name>
<description>TMR enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL2</name>
<displayName>CTRL2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>C1CIOS</name>
<description>Channel 1 complementary idle output state</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1IOS</name>
<description>Channel 1 idle output state</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRS</name>
<description>DMA request source</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCFS</name>
<description>Channel control bit fresh select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBCTRL</name>
<description>Channel buffer control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDEN</name>
<displayName>IDEN</displayName>
<description>Interrupt/DMA enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>C1DEN</name>
<description>Channel 1 DMA request
enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFDEN</name>
<description>Overflow DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRKIE</name>
<description>Brake interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HALLIEN</name>
<description>HALL interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1IEN</name>
<description>Channel 1 interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFIEN</name>
<description>Overflow interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISTS</name>
<displayName>ISTS</displayName>
<description>Interrupt status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>C1RF</name>
<description>Channel 1 recapture flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRKIF</name>
<description>Brake interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HALLIF</name>
<description>HALL interrupt flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C4IF</name>
<description>Channel 4 interrupt flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1IF</name>
<description>Channel 1 interrupt flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFIF</name>
<description>Overflow interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWEVT</name>
<displayName>SWEVT</displayName>
<description>Software event register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BRKSWTR</name>
<description>Brake event triggered by software</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HALLSWTR</name>
<description>HALL event triggered by software</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1SWTR</name>
<description>Channel 1 event triggered by software</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFSWTR</name>
<description>Overflow event triggered by software</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM1_OUTPUT</name>
<displayName>CM1_OUTPUT</displayName>
<description>Channel output mode register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C1OSEN</name>
<description>Channel 1 output switch enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1OCTRL</name>
<description>Channel 1 output control</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>C1OBEN</name>
<description>Channel 1 output buffer enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1OIEN</name>
<description>Channel 1 output immediately enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1C</name>
<description>Channel 1 configure</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM1_INPUT</name>
<displayName>CM1_INPUT</displayName>
<description>Channel input mode register 1</description>
<alternateRegister>CM1_OUTPUT</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C1DF</name>
<description>Channel 1 digital filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>C1IDIV</name>
<description>Channel 1 input divider</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C1C</name>
<description>Channel 1 configure</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCTRL</name>
<displayName>CCTRL</displayName>
<description>Channel control
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>C1CP</name>
<description>Channel 1 complementary polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1CEN</name>
<description>Channel 1 complementary enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1P</name>
<description>Channel 1 Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1EN</name>
<description>Channel 1 enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CVAL</name>
<displayName>CVAL</displayName>
<description>Counter value</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CVAL</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIV</name>
<displayName>DIV</displayName>
<description>Divider value</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DIV</name>
<description>Divider value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PR</name>
<displayName>PR</displayName>
<description>Period value</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PR</name>
<description>Period value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RPR</name>
<displayName>RPR</displayName>
<description>Repetition of period value</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>RPR</name>
<description>Repetition of period value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1DT</name>
<displayName>C1DT</displayName>
<description>Channel 1 data register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C1DT</name>
<description>Channel 1 data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRK</name>
<displayName>BRK</displayName>
<description>Brake register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>OEN</name>
<description>Output enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AOEN</name>
<description>Automatic output enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRKV</name>
<description>Brake input validity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRKEN</name>
<description>Brake enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCSOEN</name>
<description>Frozen channel status when
holistic output enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCSODIS</name>
<description>Frozen channel status when
holistic output disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPC</name>
<description>Write protected configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTC</name>
<description>Dead-time configuration</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMACTRL</name>
<displayName>DMACTRL</displayName>
<description>DMA control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DTB</name>
<description>DMA transfer bytes</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>ADDR</name>
<description>DMA transfer address offset</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMADT</name>
<displayName>DMADT</displayName>
<description>DMA data register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DMADT</name>
<description>DMA data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="TMR16">
<name>TMR17</name>
<baseAddress>0x40014800</baseAddress>
<interrupt>
<name>TMR17</name>
<description>TMR17 global interrupt</description>
<value>22</value>
</interrupt>
</peripheral>
<peripheral>
<name>TMR6</name>
<description>Basic timer</description>
<groupName>TIMER</groupName>
<baseAddress>0x40001000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TMR6</name>
<description>TMR6 global interrupt</description>
<value>17</value>
</interrupt>
<registers>
<register>
<name>CTRL1</name>
<displayName>CTRL1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PRBEN</name>
<description>Period buffer enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OCMEN</name>
<description>One cycle mode enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFS</name>
<description>Overflow event source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFEN</name>
<description>Overflow event enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMREN</name>
<description>TMR enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL2</name>
<displayName>CTRL2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PTOS</name>
<description>Primary TMR output selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDEN</name>
<displayName>IDEN</displayName>
<description>Interrupt/DMA enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>OVFDEN</name>
<description>Overflow DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFIEN</name>
<description>Overflow interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISTS</name>
<displayName>ISTS</displayName>
<description>Interrupt status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>OVFIF</name>
<description>Overflow interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWEVT</name>
<displayName>SWEVT</displayName>
<description>Software event register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>OVFSWTR</name>
<description>Overflow event triggered by software</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CVAL</name>
<displayName>CVAL</displayName>
<description>Counter value</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CVAL</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIV</name>
<displayName>DIV</displayName>
<description>Divider value</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DIV</name>
<description>Divider value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PR</name>
<displayName>PR</displayName>
<description>Period value</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PR</name>
<description>Period value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>I2C1</name>
<description>Inter integrated circuit</description>
<groupName>I2C</groupName>
<baseAddress>0x40005400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C1_EVT</name>
<description>I2C1 event interrupt</description>
<value>31</value>
</interrupt>
<interrupt>
<name>I2C1_ERR</name>
<description>I2C1 error interrupt</description>
<value>32</value>
</interrupt>
<registers>
<register>
<name>CTRL1</name>
<displayName>CTRL1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>RESET</name>
<description>I2C peripheral reset</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBALERT</name>
<description>SMBus alert pin set</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECTEN</name>
<description>Request PEC transmission enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MACKCTRL</name>
<description>Master receiving mode acknowledge control</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKEN</name>
<description>Acknowledge enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GENSTOP</name>
<description>Stop generation</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GENSTART</name>
<description>Start generation</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STRETCH</name>
<description>Clock stretching mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GCAEN</name>
<description>General call address enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECEN</name>
<description>PEC calculation enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARPEN</name>
<description>SMBus address resolution protocol enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBMODE</name>
<description>SMBus device mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERMODE</name>
<description>I2C peripheral mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2CEN</name>
<description>Peripheral enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL2</name>
<displayName>CTRL2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DMAEND</name>
<description>DMA transfer end indication</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAEN</name>
<description>DMA transfer enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATAIEN</name>
<description>Data transmission interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTIEN</name>
<description>Event interrupt enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIEN</name>
<description>Error interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKFREQ</name>
<description>Input clock frequency</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>OADDR1</name>
<displayName>OADDR1</displayName>
<description>Own address register 1</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ADDR1MODE</name>
<description>Address mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDR1</name>
<description>Own address 1</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>OADDR2</name>
<displayName>OADDR2</displayName>
<description>Own address register 2</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ADDR2</name>
<description>Own address 2</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ADDR2EN</name>
<description>Own address 2 enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DT</name>
<displayName>DT</displayName>
<description>Data register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DT</name>
<description>data register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>STS1</name>
<displayName>STS1</displayName>
<description>Status register 1</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ALERTF</name>
<description>SMBus alert</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TMOUT</name>
<description>Timeout error</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PECERR</name>
<description>PEC receive error</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OUF</name>
<description>Overflow or underflow</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ACKFAIL</name>
<description>Acknowledge failure</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ARLOST</name>
<description>Arbitration lost (master
mode)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BUSERR</name>
<description>Bus error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TDBE</name>
<description>Transmit data buffer empty
(transmitters)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RDBF</name>
<description>Receive data buffer full
(receivers)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>STOPF</name>
<description>Stop detection (slave
mode)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ADDRHF</name>
<description>address header match (Master
mode)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TDC</name>
<description>Transmit data complete</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ADDR7F</name>
<description>Address sent (master mode)/matched
(slave mode)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>STARTF</name>
<description>Start bit (Master mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>STS2</name>
<displayName>STS2</displayName>
<description>Status register 2</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PECVAL</name>
<description>PEC value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ADDR2F</name>
<description>Received address 2</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOSTADDRF</name>
<description>SMBus host address receiving</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEVADDRF</name>
<description>SMBus device address receiving</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GCADDRF</name>
<description>General call address reception</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIRF</name>
<description>Transmission direction</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSYF</name>
<description>Bus busy</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRMODE</name>
<description>Transmission mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLKCTRL</name>
<displayName>CLKCTRL</displayName>
<description>Clock control register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>SPEEDMODE</name>
<description>Speed mode selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTYMODE</name>
<description>Fast mode duty cycle</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPEED</name>
<description>I2C bus speed config</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>TMRISE</name>
<displayName>TMRISE</displayName>
<description>TRISE register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0002</resetValue>
<fields>
<field>
<name>RISETIME</name>
<description>I2C bus rise time</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="I2C1">
<name>I2C2</name>
<baseAddress>0x40005800</baseAddress>
<interrupt>
<name>I2C2_EVT</name>
<description>I2C2 event interrupt</description>
<value>33</value>
</interrupt>
<interrupt>
<name>I2C2_ERR</name>
<description>I2C2 error interrupt</description>
<value>34</value>
</interrupt>
</peripheral>
<peripheral>
<name>SPI1</name>
<description>Serial peripheral interface</description>
<groupName>SPI</groupName>
<baseAddress>0x40013000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI1</name>
<description>SPI1 global interrupt</description>
<value>35</value>
</interrupt>
<registers>
<register>
<name>CTRL1</name>
<displayName>CTRL1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>SLBEN</name>
<description>Single line bidirectional half-duplex enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLBTD</name>
<description>Single line bidirectional half-duplex transmission direction</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCEN</name>
<description>CRC calculation enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NTC</name>
<description>Next transmission CRC</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBN</name>
<description>frame bit num</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORA</name>
<description>Only receive active</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWCSEN</name>
<description>Software CS enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWCSIL</name>
<description>Software CS internal level</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LTF</name>
<description>LSB transmit first</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPIEN</name>
<description>SPI enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MDIV2_0</name>
<description>Master clock frequency division bit2-0</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MSTEN</name>
<description>Master enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKPOL</name>
<description>Clock polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKPHA</name>
<description>Clock phase</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL2</name>
<displayName>CTRL2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>MDIV3</name>
<description>Master clock frequency division bit3</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDBEIE</name>
<description>Transmit data buffer empty interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDBFIE</name>
<description>Receive data buffer full interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIE</name>
<description>Error interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HWCSOE</name>
<description>Hardware CS output enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMATEN</name>
<description>DMA transmit enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAREN</name>
<description>DMA receive enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>STS</name>
<displayName>STS</displayName>
<description>status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x0002</resetValue>
<fields>
<field>
<name>BF</name>
<description>Busy flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ROERR</name>
<description>Receiver overflow error</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MMERR</name>
<description>Master mode error</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CCERR</name>
<description>CRC calculation error</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TUERR</name>
<description>Transmitter underload error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ACS</name>
<description>Audio channel state</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TDBE</name>
<description>Transmit data buffer empty</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RDBF</name>
<description>Receive data buffer full</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DT</name>
<displayName>DT</displayName>
<description>data register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DT</name>
<description>Data value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPOLY</name>
<displayName>CPOLY</displayName>
<description>CRC polynomial register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0007</resetValue>
<fields>
<field>
<name>CPOLY</name>
<description>CRC polynomial</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RCRC</name>
<displayName>RCRC</displayName>
<description>Receive CRC register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>RCRC</name>
<description>Receive CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TCRC</name>
<displayName>TCRC</displayName>
<description>Transmit CRC register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TCRC</name>
<description>Transmit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>I2SCTRL</name>
<displayName>I2SCTRL</displayName>
<description>I2S control register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>I2SMSEL</name>
<description>I2S mode select</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2SEN</name>
<description>I2S Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPERSEL</name>
<description>I2S operation select</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCMFSSEL</name>
<description>PCM frame synchronization select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STDSEL</name>
<description>I2S standard select</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>I2SCLKPOL</name>
<description>I2S clock polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2SDBN</name>
<description>I2S data bit num</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>I2SCBN</name>
<description>I2S channel bit num</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>I2SCLK</name>
<displayName>I2SCLK</displayName>
<description>I2S clock register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>00000010</resetValue>
<fields>
<field>
<name>I2SDIV9_8</name>
<description>I2S division bit9 and bit8</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>I2SMCLKOE</name>
<description>I2S master clock output enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2SODD</name>
<description>Odd result for I2S division</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2SDIV7_0</name>
<description>I2S division bit7 to bit0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="SPI1">
<name>SPI2</name>
<baseAddress>0x40003800</baseAddress>
<interrupt>
<name>SPI2</name>
<description>SPI2 global interrupt</description>
<value>36</value>
</interrupt>
</peripheral>
<peripheral>
<name>USART1</name>
<description>Universal synchronous asynchronous receiver
transmitter</description>
<groupName>USART</groupName>
<baseAddress>0x40013800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>USART1</name>
<description>USART1 global interrupt</description>
<value>27</value>
</interrupt>
<registers>
<register>
<name>STS</name>
<displayName>STS</displayName>
<description>Status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00C0</resetValue>
<fields>
<field>
<name>CTSCF</name>
<description>CTS change flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BFF</name>
<description>Break frame flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TDBE</name>
<description>Transmit data buffer empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TDC</name>
<description>Transmit data complete</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RDBF</name>
<description>Receive data buffer full</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IDLEF</name>
<description>IDLE flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ROERR</name>
<description>Receiver overflow error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NERR</name>
<description>Noise error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FERR</name>
<description>Framing error</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PERR</name>
<description>Parity error</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DT</name>
<displayName>DT</displayName>
<description>Data register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DT</name>
<description>Data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>BAUDR</name>
<displayName>BAUDR</displayName>
<description>Baud rate register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DIV</name>
<description>Division</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL1</name>
<displayName>CTRL1</displayName>
<description>Control register 1</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>UEN</name>
<description>USART enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBN</name>
<description>Data bit num</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUM</name>
<description>Wake up mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEN</name>
<description>Parity enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSEL</name>
<description>Parity selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERRIEN</name>
<description>PERR interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDBEIEN</name>
<description>TDBE interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCIEN</name>
<description>TDC interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDBFIEN</name>
<description>RDBF interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEIEN</name>
<description>IDLE interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEN</name>
<description>Transmitter enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REN</name>
<description>Receiver enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RM</name>
<description>Receiver mute</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBF</name>
<description>Send break frame</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL2</name>
<displayName>CTRL2</displayName>
<description>Control register 2</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TRPSWAP</name>
<description>Transmit receive pin swap</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINEN</name>
<description>LIN mode enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOPBN</name>
<description>STOP bit num</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CLKEN</name>
<description>Clock enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKPOL</name>
<description>Clock polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKPHA</name>
<description>Clock phase</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBCP</name>
<description>Last bit clock pulse</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BFIEN</name>
<description>Break frame interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BFBN</name>
<description>Break frame bit num</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID</name>
<description>USART identification</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL3</name>
<displayName>CTRL3</displayName>
<description>Control register 3</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CTSCFIEN</name>
<description>CTSCF interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSEN</name>
<description>CTS enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTSEN</name>
<description>RTS enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMATEN</name>
<description>DMA transmitter enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAREN</name>
<description>DMA receiver enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCMEN</name>
<description>Smartcard mode enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCNACKEN</name>
<description>Smartcard NACK enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLBEN</name>
<description>Single line bidirectional half-duplex enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRDALP</name>
<description>IrDA low-power mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRDAEN</name>
<description>IrDA enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIEN</name>
<description>Error interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GDIV</name>
<displayName>GDIV</displayName>
<description>Guard time and division register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>SCGT</name>
<description>Smart card guard time value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ISDIV</name>
<description>IrDA/smartcard division value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="USART1">
<name>USART2</name>
<baseAddress>0x40004400</baseAddress>
<interrupt>
<name>USART2</name>
<description>USART2 global interrupt</description>
<value>28</value>
</interrupt>
</peripheral>
<peripheral>
<name>ADC</name>
<description>Analog to digital converter</description>
<groupName>ADC</groupName>
<baseAddress>0x40012400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ADC1_2</name>
<description>ADC1 and ADC2 global interrupt</description>
<value>18</value>
</interrupt>
<registers>
<register>
<name>STS</name>
<displayName>STS</displayName>
<description>status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OCCS</name>
<description>Ordinary channel conversion start flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCCS</name>
<description>Preempted channel conversion start flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCCE</name>
<description>Preempted channels conversion end flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCE</name>
<description>Channels conversion end flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VMOR</name>
<description>Voltage monitoring out of range flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL1</name>
<displayName>CTRL1</displayName>
<description>control register 1</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OCVMEN</name>
<description>Voltage monitoring enable on ordinary channels</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCVMEN</name>
<description>Voltage monitoring enable on preempted channels</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OCPCNT</name>
<description>Partitioned mode conversion count of ordinary channels</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PCPEN</name>
<description>Partitioned mode enable on preempted channels</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OCPEN</name>
<description>Partitioned mode enable on ordinary channels</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCAUTOEN</name>
<description>Preempted group automatic conversion enable after ordinary group</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VMSGEN</name>
<description>Voltage monitoring enable on a single channel</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SQEN</name>
<description>Sequence mode enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCCEIEN</name>
<description>Conversion end interrupt enable for preempted channels</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VMORIEN</name>
<description>Voltage monitoring out of range interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCEIEN</name>
<description>Channel conversion end interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VMCSEL</name>
<description>Voltage monitoring channel select</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL2</name>
<displayName>CTRL2</displayName>
<description>control register 2</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ITSRVEN</name>
<description>Internal temperature sensor and VINTRV enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OCSWTRG</name>
<description>Conversion trigger by software of ordinary channels</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCSWTRG</name>
<description>Conversion trigger by software of preempted channels</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OCTEN</name>
<description>Trigger mode enable for ordinary channels conversion</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OCTESEL</name>
<description>Low bit of trigger event select for ordinary channels conversion</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PCTEN</name>
<description>Trigger mode enable for preempted channels conversion</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCTESEL</name>
<description>Low bit of trigger event select for preempted channels conversion</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DTALIGN</name>
<description>Data alignment</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OCDMAEN</name>
<description>DMA transfer enable of ordinary channels</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADCALINIT</name>
<description>initialize A/D calibration</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADCAL</name>
<description>A/D Calibration</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RPEN</name>
<description>Repeat mode enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADCEN</name>
<description>A/D converter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SPT1</name>
<displayName>SPT1</displayName>
<description>sample time register 1</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CSPT17</name>
<description>Selection sample time of channel ADC_IN17</description>
<bitOffset>21</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CSPT16</name>
<description>Selection sample time of channel ADC_IN16</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CSPT15</name>
<description>Selection sample time of channel ADC_IN15</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CSPT14</name>
<description>Selection sample time of channel ADC_IN14</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CSPT13</name>
<description>Selection sample time of channel ADC_IN13</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CSPT12</name>
<description>Selection sample time of channel ADC_IN12</description>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CSPT11</name>
<description>Selection sample time of channel ADC_IN11</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CSPT10</name>
<description>Selection sample time of channel ADC_IN10</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SPT2</name>
<displayName>SPT2</displayName>
<description>sample time register 2</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CSPT9</name>
<description>Selection sample time of channel ADC_IN9</description>
<bitOffset>27</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CSPT8</name>
<description>Selection sample time of channel ADC_IN8</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CSPT7</name>
<description>Selection sample time of channel ADC_IN7</description>
<bitOffset>21</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CSPT6</name>
<description>Selection sample time of channel ADC_IN6</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CSPT5</name>
<description>Selection sample time of channel ADC_IN5</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CSPT4</name>
<description>Selection sample time of channel ADC_IN4</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CSPT3</name>
<description>Selection sample time of channel ADC_IN3</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CSPT2</name>
<description>Selection sample time of channel ADC_IN2</description>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CSPT1</name>
<description>Selection sample time of channel ADC_IN1</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CSPT0</name>
<description>Selection sample time of channel ADC_IN0</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCDTO1</name>
<displayName>PCDTO1</displayName>
<description>Preempted channel 1 data offset register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PCDTO1</name>
<description>Data offset for Preempted channel 1</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCDTO2</name>
<displayName>PCDTO2</displayName>
<description>Preempted channel 2 data offset register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PCDTO2</name>
<description>Data offset for Preempted channel 2</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCDTO3</name>
<displayName>PCDTO3</displayName>
<description>Preempted channel 3 data offset register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PCDTO3</name>
<description>Data offset for Preempted channel 3</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCDTO4</name>
<displayName>PCDTO4</displayName>
<description>Preempted channel 4 data offset register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PCDTO4</name>
<description>Data offset for Preempted channel 4</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>VMHB</name>
<displayName>VMHB</displayName>
<description>Voltage monitoring high boundary register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000FFF</resetValue>
<fields>
<field>
<name>VMHB</name>
<description>Voltage monitoring high boundary</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>VMLB</name>
<displayName>VMLB</displayName>
<description>Voltage monitoring low boundary register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VMLB</name>
<description>Voltage monitoring low boundary</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>OSQ1</name>
<displayName>OSQ1</displayName>
<description>Ordinary sequence register 1</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OCLEN</name>
<description>Ordinary conversion sequence length</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>OSN16</name>
<description>Number of 16th conversion in ordinary sequence</description>
<bitOffset>15</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OSN15</name>
<description>Number of 15th conversion in ordinary sequence</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OSN14</name>
<description>Number of 14th conversion in ordinary sequence</description>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OSN13</name>
<description>Number of 13th conversion in ordinary sequence</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>OSQ2</name>
<displayName>OSQ2</displayName>
<description>Ordinary sequence register 2</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OSN12</name>
<description>Number of 12th conversion in ordinary sequence</description>
<bitOffset>25</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OSN11</name>
<description>Number of 11th conversion in ordinary sequence</description>
<bitOffset>20</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OSN10</name>
<description>Number of 10th conversion in ordinary sequence</description>
<bitOffset>15</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OSN9</name>
<description>Number of 8th conversion in ordinary sequence</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OSN8</name>
<description>Number of 7th conversion in ordinary sequence</description>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OSN7</name>
<description>Number of 13th conversion in ordinary sequence</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>OSQ3</name>
<displayName>OSQ3</displayName>
<description>Ordinary sequence register 3</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OSN6</name>
<description>Number of 6th conversion in ordinary sequence</description>
<bitOffset>25</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OSN5</name>
<description>Number of 5th conversion in ordinary sequence</description>
<bitOffset>20</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OSN4</name>
<description>Number of 4th conversion in ordinary sequence</description>
<bitOffset>15</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OSN3</name>
<description>number of 3rd conversion in ordinary sequence</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OSN2</name>
<description>Number of 2nd conversion in ordinary sequence</description>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OSN1</name>
<description>Number of 1st conversion in ordinary sequence</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PSQ</name>
<displayName>PSQ</displayName>
<description>Preempted sequence register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PCLEN</name>
<description>Preempted conversion sequence length</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSN4</name>
<description>Number of 4th conversion in Preempted sequence</description>
<bitOffset>15</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>PSN3</name>
<description>Number of 3rd conversion in Preempted sequence</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>PSN2</name>
<description>Number of 2nd conversion in Preempted sequence</description>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>PSN1</name>
<description>Number of 1st conversion in Preempted sequence</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDT1</name>
<displayName>PDT1</displayName>
<description>Preempted data register 1</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PDT1</name>
<description>Preempted data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDT2</name>
<displayName>PDT2</displayName>
<description>Preempted data register 2</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PDT2</name>
<description>Preempted data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDT3</name>
<displayName>PDT3</displayName>
<description>Preempted data register 3</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PDT3</name>
<description>Preempted data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDT4</name>
<displayName>PDT4</displayName>
<description>Preempted data register 4</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PDT4</name>
<description>Preempted data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ODT</name>
<displayName>ODT</displayName>
<description>Ordinary data register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ODT</name>
<description>Conversion data of ordinary channel</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CMP</name>
<description>Comparator</description>
<groupName>CMP</groupName>
<baseAddress>0x4001001C</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x3E4</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ADC_CMP</name>
<description>ADC and CMP interrupt</description>
<value>12</value>
</interrupt>
<registers>
<register>
<name>CTRLSTS</name>
<displayName>CTRLSTS</displayName>
<description>CMP control/status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMPEN</name>
<description>Comparator enable bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CMPIS</name>
<description>Comparator input shift</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CMPSSEL</name>
<description>Comparator speed selection</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CMPINVSEL</name>
<description>Comparator inverting selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CMPNINVSEL</name>
<description>Comparator non-inverting input selection</description>
<bitOffset>7</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CMPTAG</name>
<description>Comparator output target</description>
<bitOffset>10</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CMPP</name>
<description>Comparator polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CMPHYST</name>
<description>Comparator hysteresis</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CMPBLANKING</name>
<description>Comparator blanking</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRGEN</name>
<description>Comparator brgen</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SCALEN</name>
<description>Comparator scalen</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CMPVALUE</name>
<description>Comparator output value</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CMPWP</name>
<description>Comparator write protect</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>G_FILTER_EN</name>
<displayName>G_FILTER_EN</displayName>
<description>G_FILTER_EN</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>GFE</name>
<description>Glitch filter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HIGH_PULSE</name>
<displayName>HIGH_PULSE</displayName>
<description>HIGH_PULSE</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>H_PULSE_CNT</name>
<description>High pulse Count</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>LOW_PULSE</name>
<displayName>LOW_PULSE</displayName>
<description>LOW_PULSE</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>L_PULSE_CNT</name>
<description>Low pulse Count</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DEBUG</name>
<description>Debug support</description>
<groupName>DEBUG</groupName>
<baseAddress>0xE0042000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>IDCODE</name>
<displayName>IDCODE</displayName>
<description>DEBUG_IDCODE</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PID</name>
<description>PID</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<displayName>CTRL</displayName>
<description>DEBUG_CTRL</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>SLEEP_DEBUG</name>
<description>SLEEP_DEBUG</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEEPSLEEP_DEBUG</name>
<description>DEEPSLEEP_DEBUG</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STANDBY_DEBUG</name>
<description>STANDBY_DEBUG</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDT_PAUSE</name>
<description>WDT_PAUSE</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WWDT_PAUSE</name>
<description>WWDT_PAUSE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR1_PAUSE</name>
<description>TMR1_PAUSE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR3_PAUSE</name>
<description>TMR3_PAUSE</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERTC_PAUSE</name>
<description>ERTC_PAUSE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C1_SMBUS_TIMEOUT</name>
<description>I2C1_SMBUS_TIMEOUT</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C2_SMBUS_TIMEOUT</name>
<description>I2C2_SMBUS_TIMEOUT</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR6_PAUSE</name>
<description>TMR6_PAUSE</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERTC_512_PAUSE</name>
<description>ERTC_512_PAUSE</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR15_PAUSE</name>
<description>TMR15_PAUSE</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR16_PAUSE</name>
<description>TMR16_PAUSE</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR17_PAUSE</name>
<description>TMR17_PAUSE</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR14_PAUSE</name>
<description>TMR14_PAUSE</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CRC</name>
<description>CRC calculation unit</description>
<groupName>CRC</groupName>
<baseAddress>0x40023000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DT</name>
<displayName>DT</displayName>
<description>Data register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>DT</name>
<description>Data Register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CDT</name>
<displayName>CDT</displayName>
<description>Common data register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CDT</name>
<description>Common Data</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<displayName>CTRL</displayName>
<description>Control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RST</name>
<description>Reset bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>POLY_SIZE</name>
<description>Polynomial size</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>REVID</name>
<description>Reverse input data</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>REVOD</name>
<description>Reverse output data</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDT</name>
<displayName>IDT</displayName>
<description>Initial data register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>IDT</name>
<description>Initial Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>POLY</name>
<displayName>POLY</displayName>
<description>Polynomial coefficient register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x04C11DB7</resetValue>
<fields>
<field>
<name>POLY</name>
<description>polynomial coefficient</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FLASH</name>
<description>Flash memory controler</description>
<groupName>FLASH</groupName>
<baseAddress>0x40022000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FLASH</name>
<description>Flash global interrupt</description>
<value>3</value>
</interrupt>
<registers>
<register>
<name>PSR</name>
<displayName>PSR</displayName>
<description>Performance selection register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000030</resetValue>
<fields>
<field>
<name>WTCYC</name>
<description>Wait cycle</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HFCYC_EN</name>
<description>Half cycle acceleration access enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PFT_EN</name>
<description>Prefetch enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PFT_ENF</name>
<description>Prefetch enabled flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PFT_EN2</name>
<description>Prefetch enable 2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PFT_ENF2</name>
<description>Prefetch enabled flag 2</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PFT_LAT_DIS</name>
<description>Prefetch latency disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UNLOCK</name>
<displayName>UNLOCK</displayName>
<description>Unlock register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UKVAL</name>
<description>Unlock key value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>USD_UNLOCK</name>
<displayName>USD_UNLOCK</displayName>
<description>USD unlock register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>USD_UKVAL</name>
<description>User system data Unlock key value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>STS</name>
<displayName>STS</displayName>
<description>Status register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ODF</name>
<description>Operate done flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPPERR</name>
<description>Erase/program protection error</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRGMERR</name>
<description>program error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OBF</name>
<description>Operate busy flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<displayName>CTRL</displayName>
<description>Control register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00020080</resetValue>
<fields>
<field>
<name>FPRGM</name>
<description>Flash program</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SECERS</name>
<description>Sector erase</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BANKERS</name>
<description>Bank erase</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USDPRGM</name>
<description>User system data program</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USDERS</name>
<description>User system data erase</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERSTR</name>
<description>Erasing start</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPLK</name>
<description>Operation lock</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USDULKS</name>
<description>User system data unlock success</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIE</name>
<description>Error interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODFIE</name>
<description>Operation done flag interrupt enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAP_HL_DIS</name>
<description>FAP high level disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPMEN</name>
<description>Low power mode enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADDR</name>
<displayName>ADDR</displayName>
<description>Address register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FA</name>
<description>Flash Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>USD</name>
<displayName>USD</displayName>
<description>User system data register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x03FFFFFC</resetValue>
<fields>
<field>
<name>USDERR</name>
<description>User system data error</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAP</name>
<description>FLASH access protection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nWDT_ATO_EN</name>
<description>WDT auto enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nDEPSLP_RST</name>
<description>Deepsleep reset</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nSTDBY_RST</name>
<description>Standby reset</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nBOOT1</name>
<description>boot1</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USER_D0</name>
<description>User data 0</description>
<bitOffset>10</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>USER_D1</name>
<description>User data 1</description>
<bitOffset>18</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>FAP_HL</name>
<description>FAP high level</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EPPS</name>
<displayName>EPPS</displayName>
<description>Erase/program protection status register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>EPPS</name>
<description>Erase/program protection status</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLIB_STS0</name>
<displayName>SLIB_STS0</displayName>
<description>sLib status 0 register</description>
<addressOffset>0x74</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BTM_AP_ENF</name>
<description>Boot memory store application code enabled flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM_SLIB_ENF</name>
<description>Extension memory sLib enabled flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLIB_ENF</name>
<description>sLib enabled flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM_SLIB_INST_SS</name>
<description>Extension memory sLib instruction start sector</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLIB_STS1</name>
<displayName>SLIB_STS1</displayName>
<description>sLib status 1 register</description>
<addressOffset>0x78</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLIB_SS</name>
<description>sLib start sector</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>SLIB_INST_SS</name>
<description>sLib instruction start sector</description>
<bitOffset>11</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>SLIB_ES</name>
<description>sLib end sector</description>
<bitOffset>22</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLIB_PWD_CLR</name>
<displayName>SLIB_PWD_CLR</displayName>
<description>SLIB password clear register</description>
<addressOffset>0x7C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<access>write-only</access>
<fields>
<field>
<name>SLIB_PCLR_VAL</name>
<description>sLib password clear value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLIB_MISC_STS</name>
<displayName>SLIB_MISC_STS</displayName>
<description>sLib misc status register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<resetValue>0x01000000</resetValue>
<fields>
<field>
<name>SLIB_PWD_ERR</name>
<description>sLib password error</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SLIB_PWD_OK</name>
<description>sLib password ok</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SLIB_ULKF</name>
<description>sLib unlock flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CRC_ADDR</name>
<displayName>CRC_ADDR</displayName>
<description>Flash CRC data start address register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CRC_ADDR</name>
<description>CRC address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CRC_CTRL</name>
<displayName>CRC_CTRL</displayName>
<description>Flash CRC controll register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CRC_SN</name>
<description>CRC sector numbler</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CRC_STRT</name>
<description>CRC start</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CRC_CHKR</name>
<displayName>CRC_CHKR</displayName>
<description>FLASH CRC check result register</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FCRC_OUT</name>
<description>CRC32 verification result of flash user code or SLIB code</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLIB_SET_PWD</name>
<displayName>SLIB_SET_PWD</displayName>
<description>sLib password setting register</description>
<addressOffset>0x160</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLIB_PSET_VAL</name>
<description>sLib password setting val</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLIB_SET_RANGE</name>
<displayName>SLIB_SET_RANGE</displayName>
<description>Configure sLib range register</description>
<addressOffset>0x164</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLIB_SS_SET</name>
<description>sLib start sector setting</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>SLIB_ISS_SET</name>
<description>sLib instruction start sector setting</description>
<bitOffset>11</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>SLIB_ES_SET</name>
<description>sLib end sector setting</description>
<bitOffset>22</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>EM_SLIB_SET</name>
<displayName>EM_SLIB_SET</displayName>
<description>Extension momery slib set register</description>
<addressOffset>0x168</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EM_SLIB_SET</name>
<description>Extension memory sLib setting</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>EM_SLIB_ISS_SET</name>
<description>Extension memory sLib instruction start sector setting</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>BTM_MODE_SET</name>
<displayName>BTM_MODE_SET</displayName>
<description>Boot memory mode setting register</description>
<addressOffset>0x16C</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BTM_MODE_SET</name>
<description>Boot memory mode setting</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLIB_UNLOCK</name>
<displayName>SLIB_UNLOCK</displayName>
<description>sLib unlock register</description>
<addressOffset>0x170</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLIB_UKVAL</name>
<description>sLib unlock key value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>NVIC</name>
<description>Nested Vectored Interrupt
Controller</description>
<groupName>NVIC</groupName>
<baseAddress>0xE000E000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1001</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ICTR</name>
<displayName>ICTR</displayName>
<description>Interrupt Controller Type
Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INTLINESNUM</name>
<description>Total number of interrupt lines in
groups</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>STIR</name>
<displayName>STIR</displayName>
<description>Software Triggered Interrupt
Register</description>
<addressOffset>0xF00</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INTID</name>
<description>interrupt to be triggered</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISER0</name>
<displayName>ISER0</displayName>
<description>Interrupt Set-Enable Register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETENA</name>
<description>SETENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISER1</name>
<displayName>ISER1</displayName>
<description>Interrupt Set-Enable Register</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETENA</name>
<description>SETENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICER0</name>
<displayName>ICER0</displayName>
<description>Interrupt Clear-Enable
Register</description>
<addressOffset>0x180</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRENA</name>
<description>CLRENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICER1</name>
<displayName>ICER1</displayName>
<description>Interrupt Clear-Enable
Register</description>
<addressOffset>0x184</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRENA</name>
<description>CLRENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISPR0</name>
<displayName>ISPR0</displayName>
<description>Interrupt Set-Pending Register</description>
<addressOffset>0x200</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETPEND</name>
<description>SETPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISPR1</name>
<displayName>ISPR1</displayName>
<description>Interrupt Set-Pending Register</description>
<addressOffset>0x204</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETPEND</name>
<description>SETPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICPR0</name>
<displayName>ICPR0</displayName>
<description>Interrupt Clear-Pending
Register</description>
<addressOffset>0x280</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRPEND</name>
<description>CLRPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICPR1</name>
<displayName>ICPR1</displayName>
<description>Interrupt Clear-Pending
Register</description>
<addressOffset>0x284</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRPEND</name>
<description>CLRPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IABR0</name>
<displayName>IABR0</displayName>
<description>Interrupt Active Bit Register</description>
<addressOffset>0x300</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACTIVE</name>
<description>ACTIVE</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IABR1</name>
<displayName>IABR1</displayName>
<description>Interrupt Active Bit Register</description>
<addressOffset>0x304</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACTIVE</name>
<description>ACTIVE</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR0</name>
<displayName>IPR0</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x400</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR1</name>
<displayName>IPR1</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x404</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR2</name>
<displayName>IPR2</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x408</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR3</name>
<displayName>IPR3</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x40C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR4</name>
<displayName>IPR4</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x410</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR5</name>
<displayName>IPR5</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x414</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR6</name>
<displayName>IPR6</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x418</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR7</name>
<displayName>IPR7</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x41C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR8</name>
<displayName>IPR8</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x420</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR9</name>
<displayName>IPR9</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x424</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR10</name>
<displayName>IPR10</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x428</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR11</name>
<displayName>IPR11</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x42C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR12</name>
<displayName>IPR12</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x430</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR13</name>
<displayName>IPR13</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x434</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR14</name>
<displayName>IPR14</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x438</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCFG</name>
<description>System configuration controller</description>
<groupName>SCFG</groupName>
<baseAddress>0x40010000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1C</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CFG1</name>
<displayName>CFG1</displayName>
<description>configuration register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TMR17_DMA_RMP</name>
<description>TMR17 DMA remap</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMR16_DMA_RMP</name>
<description>TMR16 DMA remap</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USART1_RX_DMA_RMP</name>
<description>USART1 receive DMA remap</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USART1_TX_DMA_RMP</name>
<description>USART1 transmit DMA remap</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADC_DMA_RMP</name>
<description>ADC DMA remap</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IR_SRC_SEL</name>
<description>IRTMR source select</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IR_POL</name>
<description>IRTMR Polariyt select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PA11_12_RMP</name>
<description>PA11 PA12 Remap</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_MAP_SEL</name>
<description>Memory address mapping selection bits</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXINTC1</name>
<displayName>EXINTC1</displayName>
<description>external interrupt configuration register 1</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>EXINT3</name>
<description>EXINT 3 configuration bits</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXINT2</name>
<description>EXINT 2 configuration bits</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXINT1</name>
<description>EXINT 1 configuration bits</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXINT0</name>
<description>EXINT 0 configuration bits</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXINTC2</name>
<displayName>EXINTC2</displayName>
<description>external interrupt configuration register 2</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>EXINT7</name>
<description>EXINT 7 configuration bits</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXINT6</name>
<description>EXINT 6 configuration bits</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXINT5</name>
<description>EXINT 5 configuration bits</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXINT4</name>
<description>EXINT 4 configuration bits</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXINTC3</name>
<displayName>EXINTC3</displayName>
<description>external interrupt configuration register 3</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>EXINT11</name>
<description>EXINT 11 configuration bits</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXINT10</name>
<description>EXINT 10 configuration bits</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXINT9</name>
<description>EXINT 9 configuration bits</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXINT8</name>
<description>EXINT 8 configuration bits</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXINTC4</name>
<displayName>EXINTC4</displayName>
<description>external interrupt configuration register
4</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>EXINT15</name>
<description>EXINT 15 configuration bits</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXINT14</name>
<description>EXINT 14 configuration bits</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXINT13</name>
<description>EXINT 13 configuration bits</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXINT12</name>
<description>EXINT 12 configuration bits</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>
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