Texas Instruments TI TM4C1233H6PGE TM4C 11073 ARM Cortex-M4 Tiva TM4C Device \n Software License Agreement\n \n Texas Instruments (TI) is supplying this software for use solely and\n exclusively on TI's microcontroller products. The software is owned by\n TI and/or its suppliers, and is protected under applicable copyright\n laws. You may not combine this software with "viral" open-source\n software in order to form a larger program.\n \n THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.\n NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT\n NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY\n CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL\n DAMAGES, FOR ANY REASON WHATSOEVER.\n \n CM4 r1p2 little true true 3 false system_TM4C123 8 32 32 read-write 0 0 WATCHDOG0 Register map for WATCHDOG0 peripheral WATCHDOG WATCHDOG0 0x40000000 0 0x00001000 registers WATCHDOG018 LOAD Watchdog Load 0x00000000 WDT_LOAD Watchdog Load Value [31:0] VALUE Watchdog Value 0x00000004 WDT_VALUE Watchdog Value [31:0] CTL Watchdog Control 0x00000008 WDT_CTL_INTEN Watchdog Interrupt Enable [0:0] WDT_CTL_RESEN Watchdog Reset Enable [1:1] WDT_CTL_INTTYPE Watchdog Interrupt Type [2:2] WDT_CTL_WRC Write Complete [31:31] ICR Watchdog Interrupt Clear 0x0000000C write-only WDT_ICR Watchdog Interrupt Clear [31:0] write-only RIS Watchdog Raw Interrupt Status 0x00000010 WDT_RIS_WDTRIS Watchdog Raw Interrupt Status [0:0] MIS Watchdog Masked Interrupt Status 0x00000014 WDT_MIS_WDTMIS Watchdog Masked Interrupt Status [0:0] TEST Watchdog Test 0x00000418 WDT_TEST_STALL Watchdog Stall Enable [8:8] LOCK Watchdog Lock 0x00000C00 WDT_LOCK Watchdog Lock [31:0] WDT_LOCK_UNLOCKED Unlocked 0x0 WDT_LOCK_LOCKED Locked 0x1 WDT_LOCK_UNLOCK Unlocks the watchdog timer 0x1acce551 WATCHDOG1 WATCHDOG1 0x40001000 GPIOA Register map for GPIOA peripheral GPIO GPIOA 0x40004000 0 0x00001000 registers GPIOA0 DATA GPIO Data 0x000003FC DIR GPIO Direction 0x00000400 IS GPIO Interrupt Sense 0x00000404 IBE GPIO Interrupt Both Edges 0x00000408 IEV GPIO Interrupt Event 0x0000040C IM GPIO Interrupt Mask 0x00000410 GPIO_IM_GPIO GPIO Interrupt Mask Enable [7:0] RIS GPIO Raw Interrupt Status 0x00000414 GPIO_RIS_GPIO GPIO Interrupt Raw Status [7:0] MIS GPIO Masked Interrupt Status 0x00000418 GPIO_MIS_GPIO GPIO Masked Interrupt Status [7:0] ICR GPIO Interrupt Clear 0x0000041C write-only GPIO_ICR_GPIO GPIO Interrupt Clear [7:0] write-only AFSEL GPIO Alternate Function Select 0x00000420 DR2R GPIO 2-mA Drive Select 0x00000500 DR4R GPIO 4-mA Drive Select 0x00000504 DR8R GPIO 8-mA Drive Select 0x00000508 ODR GPIO Open Drain Select 0x0000050C PUR GPIO Pull-Up Select 0x00000510 PDR GPIO Pull-Down Select 0x00000514 SLR GPIO Slew Rate Control Select 0x00000518 DEN GPIO Digital Enable 0x0000051C LOCK GPIO Lock 0x00000520 GPIO_LOCK GPIO Lock [31:0] GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b CR GPIO Commit 0x00000524 read-only AMSEL GPIO Analog Mode Select 0x00000528 PCTL GPIO Port Control 0x0000052C ADCCTL GPIO ADC Control 0x00000530 DMACTL GPIO DMA Control 0x00000534 SI GPIO Select Interrupt 0x00000538 GPIO_SI_SUM Summary Interrupt [0:0] GPIOB GPIOB 0x40005000 GPIOB1 GPIOC GPIOC 0x40006000 GPIOC2 GPIOD GPIOD 0x40007000 GPIOD3 SSI0 Register map for SSI0 peripheral SSI SSI0 0x40008000 0 0x00001000 registers SSI07 CR0 SSI Control 0 0x00000000 SSI_CR0_DSS SSI Data Size Select [3:0] SSI_CR0_DSS_4 4-bit data 0x3 SSI_CR0_DSS_5 5-bit data 0x4 SSI_CR0_DSS_6 6-bit data 0x5 SSI_CR0_DSS_7 7-bit data 0x6 SSI_CR0_DSS_8 8-bit data 0x7 SSI_CR0_DSS_9 9-bit data 0x8 SSI_CR0_DSS_10 10-bit data 0x9 SSI_CR0_DSS_11 11-bit data 0xa SSI_CR0_DSS_12 12-bit data 0xb SSI_CR0_DSS_13 13-bit data 0xc SSI_CR0_DSS_14 14-bit data 0xd SSI_CR0_DSS_15 15-bit data 0xe SSI_CR0_DSS_16 16-bit data 0xf SSI_CR0_FRF SSI Frame Format Select [5:4] SSI_CR0_FRF_MOTO Freescale SPI Frame Format 0x0 SSI_CR0_FRF_TI Texas Instruments Synchronous Serial Frame Format 0x1 SSI_CR0_FRF_NMW MICROWIRE Frame Format 0x2 SSI_CR0_SPO SSI Serial Clock Polarity [6:6] SSI_CR0_SPH SSI Serial Clock Phase [7:7] SSI_CR0_SCR SSI Serial Clock Rate [15:8] CR1 SSI Control 1 0x00000004 SSI_CR1_LBM SSI Loopback Mode [0:0] SSI_CR1_SSE SSI Synchronous Serial Port Enable [1:1] SSI_CR1_MS SSI Master/Slave Select [2:2] SSI_CR1_SOD SSI Slave Mode Output Disable [3:3] SSI_CR1_EOT End of Transmission [4:4] DR SSI Data 0x00000008 SSI_DR_DATA SSI Receive/Transmit Data [15:0] SR SSI Status 0x0000000C SSI_SR_TFE SSI Transmit FIFO Empty [0:0] SSI_SR_TNF SSI Transmit FIFO Not Full [1:1] SSI_SR_RNE SSI Receive FIFO Not Empty [2:2] SSI_SR_RFF SSI Receive FIFO Full [3:3] SSI_SR_BSY SSI Busy Bit [4:4] CPSR SSI Clock Prescale 0x00000010 SSI_CPSR_CPSDVSR SSI Clock Prescale Divisor [7:0] IM SSI Interrupt Mask 0x00000014 SSI_IM_RORIM SSI Receive Overrun Interrupt Mask [0:0] SSI_IM_RTIM SSI Receive Time-Out Interrupt Mask [1:1] SSI_IM_RXIM SSI Receive FIFO Interrupt Mask [2:2] SSI_IM_TXIM SSI Transmit FIFO Interrupt Mask [3:3] RIS SSI Raw Interrupt Status 0x00000018 SSI_RIS_RORRIS SSI Receive Overrun Raw Interrupt Status [0:0] SSI_RIS_RTRIS SSI Receive Time-Out Raw Interrupt Status [1:1] SSI_RIS_RXRIS SSI Receive FIFO Raw Interrupt Status [2:2] SSI_RIS_TXRIS SSI Transmit FIFO Raw Interrupt Status [3:3] MIS SSI Masked Interrupt Status 0x0000001C SSI_MIS_RORMIS SSI Receive Overrun Masked Interrupt Status [0:0] SSI_MIS_RTMIS SSI Receive Time-Out Masked Interrupt Status [1:1] SSI_MIS_RXMIS SSI Receive FIFO Masked Interrupt Status [2:2] SSI_MIS_TXMIS SSI Transmit FIFO Masked Interrupt Status [3:3] ICR SSI Interrupt Clear 0x00000020 write-only SSI_ICR_RORIC SSI Receive Overrun Interrupt Clear [0:0] write-only SSI_ICR_RTIC SSI Receive Time-Out Interrupt Clear [1:1] write-only DMACTL SSI DMA Control 0x00000024 SSI_DMACTL_RXDMAE Receive DMA Enable [0:0] SSI_DMACTL_TXDMAE Transmit DMA Enable [1:1] CC SSI Clock Configuration 0x00000FC8 SSI_CC_CS SSI Baud Clock Source [3:0] SSI_CC_CS_SYSPLL Either the system clock (if the PLL bypass is in effect) or the PLL output (default) 0x0 SSI_CC_CS_PIOSC PIOSC 0x5 SSI1 SSI1 0x40009000 SSI134 SSI2 SSI2 0x4000A000 SSI257 SSI3 SSI3 0x4000B000 SSI358 UART0 Register map for UART0 peripheral UART UART0 0x4000C000 0 0x00001000 registers UART05 DR UART Data 0x00000000 UART_DR_DATA Data Transmitted or Received [7:0] UART_DR_FE UART Framing Error [8:8] UART_DR_PE UART Parity Error [9:9] UART_DR_BE UART Break Error [10:10] UART_DR_OE UART Overrun Error [11:11] RSR UART Receive Status/Error Clear 0x00000004 UART_RSR_FE UART Framing Error [0:0] UART_RSR_PE UART Parity Error [1:1] UART_RSR_BE UART Break Error [2:2] UART_RSR_OE UART Overrun Error [3:3] ECR UART Receive Status/Error Clear UART_ALT 0x00000004 UART_ECR_DATA Error Clear [7:0] FR UART Flag 0x00000018 UART_FR_CTS Clear To Send [0:0] UART_FR_DSR Data Set Ready [1:1] UART_FR_DCD Data Carrier Detect [2:2] UART_FR_BUSY UART Busy [3:3] UART_FR_RXFE UART Receive FIFO Empty [4:4] UART_FR_TXFF UART Transmit FIFO Full [5:5] UART_FR_RXFF UART Receive FIFO Full [6:6] UART_FR_TXFE UART Transmit FIFO Empty [7:7] UART_FR_RI Ring Indicator [8:8] ILPR UART IrDA Low-Power Register 0x00000020 UART_ILPR_ILPDVSR IrDA Low-Power Divisor [7:0] IBRD UART Integer Baud-Rate Divisor 0x00000024 UART_IBRD_DIVINT Integer Baud-Rate Divisor [15:0] FBRD UART Fractional Baud-Rate Divisor 0x00000028 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor [5:0] LCRH UART Line Control 0x0000002C UART_LCRH_BRK UART Send Break [0:0] UART_LCRH_PEN UART Parity Enable [1:1] UART_LCRH_EPS UART Even Parity Select [2:2] UART_LCRH_STP2 UART Two Stop Bits Select [3:3] UART_LCRH_FEN UART Enable FIFOs [4:4] UART_LCRH_WLEN UART Word Length [6:5] UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 UART_LCRH_SPS UART Stick Parity Select [7:7] CTL UART Control 0x00000030 UART_CTL_UARTEN UART Enable [0:0] UART_CTL_SIREN UART SIR Enable [1:1] UART_CTL_SIRLP UART SIR Low-Power Mode [2:2] UART_CTL_SMART ISO 7816 Smart Card Support [3:3] UART_CTL_EOT End of Transmission [4:4] UART_CTL_HSE High-Speed Enable [5:5] UART_CTL_LBE UART Loop Back Enable [7:7] UART_CTL_TXE UART Transmit Enable [8:8] UART_CTL_RXE UART Receive Enable [9:9] UART_CTL_DTR Data Terminal Ready [10:10] UART_CTL_RTS Request to Send [11:11] UART_CTL_RTSEN Enable Request to Send [14:14] UART_CTL_CTSEN Enable Clear To Send [15:15] IFLS UART Interrupt FIFO Level Select 0x00000034 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select [2:0] UART_IFLS_TX1_8 TX FIFO <= 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO <= 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO <= 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO <= 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO <= 7/8 full 0x4 UART_IFLS_RX UART Receive Interrupt FIFO Level Select [5:3] UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 IM UART Interrupt Mask 0x00000038 UART_IM_RIMIM UART Ring Indicator Modem Interrupt Mask [0:0] UART_IM_CTSMIM UART Clear to Send Modem Interrupt Mask [1:1] UART_IM_DCDMIM UART Data Carrier Detect Modem Interrupt Mask [2:2] UART_IM_DSRMIM UART Data Set Ready Modem Interrupt Mask [3:3] UART_IM_RXIM UART Receive Interrupt Mask [4:4] UART_IM_TXIM UART Transmit Interrupt Mask [5:5] UART_IM_RTIM UART Receive Time-Out Interrupt Mask [6:6] UART_IM_FEIM UART Framing Error Interrupt Mask [7:7] UART_IM_PEIM UART Parity Error Interrupt Mask [8:8] UART_IM_BEIM UART Break Error Interrupt Mask [9:9] UART_IM_OEIM UART Overrun Error Interrupt Mask [10:10] UART_IM_9BITIM 9-Bit Mode Interrupt Mask [12:12] RIS UART Raw Interrupt Status 0x0000003C UART_RIS_RIRIS UART Ring Indicator Modem Raw Interrupt Status [0:0] UART_RIS_CTSRIS UART Clear to Send Modem Raw Interrupt Status [1:1] UART_RIS_DCDRIS UART Data Carrier Detect Modem Raw Interrupt Status [2:2] UART_RIS_DSRRIS UART Data Set Ready Modem Raw Interrupt Status [3:3] UART_RIS_RXRIS UART Receive Raw Interrupt Status [4:4] UART_RIS_TXRIS UART Transmit Raw Interrupt Status [5:5] UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status [6:6] UART_RIS_FERIS UART Framing Error Raw Interrupt Status [7:7] UART_RIS_PERIS UART Parity Error Raw Interrupt Status [8:8] UART_RIS_BERIS UART Break Error Raw Interrupt Status [9:9] UART_RIS_OERIS UART Overrun Error Raw Interrupt Status [10:10] UART_RIS_9BITRIS 9-Bit Mode Raw Interrupt Status [12:12] MIS UART Masked Interrupt Status 0x00000040 UART_MIS_RIMIS UART Ring Indicator Modem Masked Interrupt Status [0:0] UART_MIS_CTSMIS UART Clear to Send Modem Masked Interrupt Status [1:1] UART_MIS_DCDMIS UART Data Carrier Detect Modem Masked Interrupt Status [2:2] UART_MIS_DSRMIS UART Data Set Ready Modem Masked Interrupt Status [3:3] UART_MIS_RXMIS UART Receive Masked Interrupt Status [4:4] UART_MIS_TXMIS UART Transmit Masked Interrupt Status [5:5] UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status [6:6] UART_MIS_FEMIS UART Framing Error Masked Interrupt Status [7:7] UART_MIS_PEMIS UART Parity Error Masked Interrupt Status [8:8] UART_MIS_BEMIS UART Break Error Masked Interrupt Status [9:9] UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status [10:10] UART_MIS_9BITMIS 9-Bit Mode Masked Interrupt Status [12:12] ICR UART Interrupt Clear 0x00000044 write-only UART_ICR_RIMIC UART Ring Indicator Modem Interrupt Clear [0:0] write-only UART_ICR_CTSMIC UART Clear to Send Modem Interrupt Clear [1:1] write-only UART_ICR_DCDMIC UART Data Carrier Detect Modem Interrupt Clear [2:2] write-only UART_ICR_DSRMIC UART Data Set Ready Modem Interrupt Clear [3:3] write-only UART_ICR_RXIC Receive Interrupt Clear [4:4] write-only UART_ICR_TXIC Transmit Interrupt Clear [5:5] write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear [6:6] write-only UART_ICR_FEIC Framing Error Interrupt Clear [7:7] write-only UART_ICR_PEIC Parity Error Interrupt Clear [8:8] write-only UART_ICR_BEIC Break Error Interrupt Clear [9:9] write-only UART_ICR_OEIC Overrun Error Interrupt Clear [10:10] write-only UART_ICR_9BITIC 9-Bit Mode Interrupt Clear [12:12] write-only DMACTL UART DMA Control 0x00000048 UART_DMACTL_RXDMAE Receive DMA Enable [0:0] UART_DMACTL_TXDMAE Transmit DMA Enable [1:1] UART_DMACTL_DMAERR DMA on Error [2:2] _9BITADDR UART 9-Bit Self Address 0x000000A4 UART_9BITADDR_ADDR Self Address for 9-Bit Mode [7:0] UART_9BITADDR_9BITEN Enable 9-Bit Mode [15:15] _9BITAMASK UART 9-Bit Self Address Mask 0x000000A8 UART_9BITAMASK_MASK Self Address Mask for 9-Bit Mode [7:0] PP UART Peripheral Properties 0x00000FC0 UART_PP_SC Smart Card Support [0:0] UART_PP_NB 9-Bit Support [1:1] CC UART Clock Configuration 0x00000FC8 UART_CC_CS UART Baud Clock Source [3:0] UART_CC_CS_SYSCLK The system clock (default) 0x0 UART_CC_CS_PIOSC PIOSC 0x5 UART1 UART1 0x4000D000 UART16 UART2 UART2 0x4000E000 UART233 UART3 UART3 0x4000F000 UART359 UART4 UART4 0x40010000 UART460 UART5 UART5 0x40011000 UART561 UART6 UART6 0x40012000 UART662 UART7 UART7 0x40013000 UART763 I2C0 Register map for I2C0 peripheral I2C I2C0 0x40020000 0 0x00001000 registers I2C08 MSA I2C Master Slave Address 0x00000000 I2C_MSA_RS Receive not send [0:0] I2C_MSA_SA I2C Slave Address [7:1] MCS I2C Master Control/Status 0x00000004 I2C_MCS_RUN I2C Master Enable [0:0] I2C_MCS_START Generate START [1:1] I2C_MCS_ADRACK Acknowledge Address [2:2] I2C_MCS_ACK Data Acknowledge Enable [3:3] I2C_MCS_ARBLST Arbitration Lost [4:4] I2C_MCS_IDLE I2C Idle [5:5] I2C_MCS_CLKTO Clock Timeout Error [7:7] MCS I2C Master Control/Status I2C0_ALT 0x00000004 I2C_MCS_BUSY I2C Busy [0:0] I2C_MCS_ERROR Error [1:1] I2C_MCS_STOP Generate STOP [2:2] I2C_MCS_DATACK Acknowledge Data [3:3] I2C_MCS_HS High-Speed Enable [4:4] I2C_MCS_BUSBSY Bus Busy [6:6] MDR I2C Master Data 0x00000008 I2C_MDR_DATA Data Transferred [7:0] MTPR I2C Master Timer Period 0x0000000C I2C_MTPR_TPR Timer Period [6:0] I2C_MTPR_HS High-Speed Enable [7:7] MIMR I2C Master Interrupt Mask 0x00000010 I2C_MIMR_IM Master Interrupt Mask [0:0] I2C_MIMR_CLKIM Clock Timeout Interrupt Mask [1:1] MRIS I2C Master Raw Interrupt Status 0x00000014 I2C_MRIS_RIS Master Raw Interrupt Status [0:0] I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status [1:1] MMIS I2C Master Masked Interrupt Status 0x00000018 I2C_MMIS_MIS Masked Interrupt Status [0:0] I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status [1:1] MICR I2C Master Interrupt Clear 0x0000001C write-only I2C_MICR_IC Master Interrupt Clear [0:0] write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear [1:1] write-only MCR I2C Master Configuration 0x00000020 I2C_MCR_LPBK I2C Loopback [0:0] I2C_MCR_MFE I2C Master Function Enable [4:4] I2C_MCR_SFE I2C Slave Function Enable [5:5] I2C_MCR_GFE I2C Glitch Filter Enable [6:6] MCLKOCNT I2C Master Clock Low Timeout Count 0x00000024 I2C_MCLKOCNT_CNTL I2C Master Count [7:0] MBMON I2C Master Bus Monitor 0x0000002C I2C_MBMON_SCL I2C SCL Status [0:0] I2C_MBMON_SDA I2C SDA Status [1:1] MCR2 I2C Master Configuration 2 0x00000038 I2C_MCR2_GFPW I2C Glitch Filter Pulse Width [6:4] I2C_MCR2_GFPW_BYPASS Bypass 0x0 I2C_MCR2_GFPW_1 1 clock 0x1 I2C_MCR2_GFPW_2 2 clocks 0x2 I2C_MCR2_GFPW_3 3 clocks 0x3 I2C_MCR2_GFPW_4 4 clocks 0x4 I2C_MCR2_GFPW_8 8 clocks 0x5 I2C_MCR2_GFPW_16 16 clocks 0x6 I2C_MCR2_GFPW_32 32 clocks 0x7 SOAR I2C Slave Own Address 0x00000800 I2C_SOAR_OAR I2C Slave Own Address [6:0] SCSR I2C Slave Control/Status 0x00000804 I2C_SCSR_RREQ Receive Request [0:0] I2C_SCSR_FBR First Byte Received [2:2] I2C_SCSR_OAR2SEL OAR2 Address Matched [3:3] SCSR I2C Slave Control/Status I2C0_ALT 0x00000804 I2C_SCSR_DA Device Active [0:0] I2C_SCSR_TREQ Transmit Request [1:1] SDR I2C Slave Data 0x00000808 I2C_SDR_DATA Data for Transfer [7:0] SIMR I2C Slave Interrupt Mask 0x0000080C I2C_SIMR_DATAIM Data Interrupt Mask [0:0] I2C_SIMR_STARTIM Start Condition Interrupt Mask [1:1] I2C_SIMR_STOPIM Stop Condition Interrupt Mask [2:2] SRIS I2C Slave Raw Interrupt Status 0x00000810 I2C_SRIS_DATARIS Data Raw Interrupt Status [0:0] I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status [1:1] I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status [2:2] SMIS I2C Slave Masked Interrupt Status 0x00000814 I2C_SMIS_DATAMIS Data Masked Interrupt Status [0:0] I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status [1:1] I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status [2:2] SICR I2C Slave Interrupt Clear 0x00000818 write-only I2C_SICR_DATAIC Data Interrupt Clear [0:0] write-only I2C_SICR_STARTIC Start Condition Interrupt Clear [1:1] write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear [2:2] write-only SOAR2 I2C Slave Own Address 2 0x0000081C I2C_SOAR2_OAR2 I2C Slave Own Address 2 [6:0] I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable [7:7] SACKCTL I2C Slave ACK Control 0x00000820 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable [0:0] I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value [1:1] PP I2C Peripheral Properties 0x00000FC0 I2C_PP_HS High-Speed Capable [0:0] PC I2C Peripheral Configuration 0x00000FC4 I2C_PC_HS High-Speed Capable [0:0] I2C1 I2C1 0x40021000 I2C137 I2C2 I2C2 0x40022000 I2C268 I2C3 I2C3 0x40023000 I2C369 GPIOE GPIOE 0x40024000 GPIOE4 GPIOF GPIOF 0x40025000 GPIOF30 GPIOG GPIOG 0x40026000 GPIOG31 GPIOH GPIOH 0x40027000 GPIOH32 TIMER0 Register map for TIMER0 peripheral TIMER TIMER0 0x40030000 0 0x00001000 registers TIMER0A19 TIMER0B20 CFG GPTM Configuration 0x00000000 TIMER_CFG GPTM Configuration [2:0] TIMER_CFG_32_BIT_TIMER 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT 16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR 0x4 TAMR GPTM Timer A Mode 0x00000004 TIMER_TAMR_TAMR GPTM Timer A Mode [1:0] TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TACMR GPTM Timer A Capture Mode [2:2] TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select [3:3] TIMER_TAMR_TACDIR GPTM Timer A Count Direction [4:4] TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable [5:5] TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger [6:6] TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode [7:7] TIMER_TAMR_TAILD GPTM Timer A Interval Load Write [8:8] TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable [9:9] TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update [10:10] TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation [11:11] TBMR GPTM Timer B Mode 0x00000008 TIMER_TBMR_TBMR GPTM Timer B Mode [1:0] TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode [2:2] TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select [3:3] TIMER_TBMR_TBCDIR GPTM Timer B Count Direction [4:4] TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable [5:5] TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger [6:6] TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode [7:7] TIMER_TBMR_TBILD GPTM Timer B Interval Load Write [8:8] TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable [9:9] TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update [10:10] TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation [11:11] CTL GPTM Control 0x0000000C TIMER_CTL_TAEN GPTM Timer A Enable [0:0] TIMER_CTL_TASTALL GPTM Timer A Stall Enable [1:1] TIMER_CTL_TAEVENT GPTM Timer A Event Mode [3:2] TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_RTCEN GPTM RTC Stall Enable [4:4] TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable [5:5] TIMER_CTL_TAPWML GPTM Timer A PWM Output Level [6:6] TIMER_CTL_TBEN GPTM Timer B Enable [8:8] TIMER_CTL_TBSTALL GPTM Timer B Stall Enable [9:9] TIMER_CTL_TBEVENT GPTM Timer B Event Mode [11:10] TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable [13:13] TIMER_CTL_TBPWML GPTM Timer B PWM Output Level [14:14] SYNC GPTM Synchronize 0x00000010 TIMER_SYNC_SYNCT0 Synchronize GPTM 16/32-Bit Timer 0 [1:0] TIMER_SYNC_SYNCT0_NONE GPTM 16/32-Bit Timer 0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM 16/32-Bit Timer 0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM 16/32-Bit Timer 0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM 16/32-Bit Timer 0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM 16/32-Bit Timer 1 [3:2] TIMER_SYNC_SYNCT1_NONE GPTM 16/32-Bit Timer 1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM 16/32-Bit Timer 1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM 16/32-Bit Timer 1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM 16/32-Bit Timer 1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM 16/32-Bit Timer 2 [5:4] TIMER_SYNC_SYNCT2_NONE GPTM 16/32-Bit Timer 2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM 16/32-Bit Timer 2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM 16/32-Bit Timer 2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM 16/32-Bit Timer 2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM 16/32-Bit Timer 3 [7:6] TIMER_SYNC_SYNCT3_NONE GPTM 16/32-Bit Timer 3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM 16/32-Bit Timer 3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM 16/32-Bit Timer 3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM 16/32-Bit Timer 3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM 16/32-Bit Timer 4 [9:8] TIMER_SYNC_SYNCT4_NONE GPTM 16/32-Bit Timer 4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM 16/32-Bit Timer 4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM 16/32-Bit Timer 4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM 16/32-Bit Timer 4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM 16/32-Bit Timer 5 [11:10] TIMER_SYNC_SYNCT5_NONE GPTM 16/32-Bit Timer 5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM 16/32-Bit Timer 5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM 16/32-Bit Timer 5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM 16/32-Bit Timer 5 is triggered 0x3 TIMER_SYNC_SYNCWT0 Synchronize GPTM 32/64-Bit Timer 0 [13:12] TIMER_SYNC_SYNCWT0_NONE GPTM 32/64-Bit Timer 0 is not affected 0x0 TIMER_SYNC_SYNCWT0_TA A timeout event for Timer A of GPTM 32/64-Bit Timer 0 is triggered 0x1 TIMER_SYNC_SYNCWT0_TB A timeout event for Timer B of GPTM 32/64-Bit Timer 0 is triggered 0x2 TIMER_SYNC_SYNCWT0_TATB A timeout event for both Timer A and Timer B of GPTM 32/64-Bit Timer 0 is triggered 0x3 TIMER_SYNC_SYNCWT1 Synchronize GPTM 32/64-Bit Timer 1 [15:14] TIMER_SYNC_SYNCWT1_NONE GPTM 32/64-Bit Timer 1 is not affected 0x0 TIMER_SYNC_SYNCWT1_TA A timeout event for Timer A of GPTM 32/64-Bit Timer 1 is triggered 0x1 TIMER_SYNC_SYNCWT1_TB A timeout event for Timer B of GPTM 32/64-Bit Timer 1 is triggered 0x2 TIMER_SYNC_SYNCWT1_TATB A timeout event for both Timer A and Timer B of GPTM 32/64-Bit Timer 1 is triggered 0x3 TIMER_SYNC_SYNCWT2 Synchronize GPTM 32/64-Bit Timer 2 [17:16] TIMER_SYNC_SYNCWT2_NONE GPTM 32/64-Bit Timer 2 is not affected 0x0 TIMER_SYNC_SYNCWT2_TA A timeout event for Timer A of GPTM 32/64-Bit Timer 2 is triggered 0x1 TIMER_SYNC_SYNCWT2_TB A timeout event for Timer B of GPTM 32/64-Bit Timer 2 is triggered 0x2 TIMER_SYNC_SYNCWT2_TATB A timeout event for both Timer A and Timer B of GPTM 32/64-Bit Timer 2 is triggered 0x3 TIMER_SYNC_SYNCWT3 Synchronize GPTM 32/64-Bit Timer 3 [19:18] TIMER_SYNC_SYNCWT3_NONE GPTM 32/64-Bit Timer 3 is not affected 0x0 TIMER_SYNC_SYNCWT3_TA A timeout event for Timer A of GPTM 32/64-Bit Timer 3 is triggered 0x1 TIMER_SYNC_SYNCWT3_TB A timeout event for Timer B of GPTM 32/64-Bit Timer 3 is triggered 0x2 TIMER_SYNC_SYNCWT3_TATB A timeout event for both Timer A and Timer B of GPTM 32/64-Bit Timer 3 is triggered 0x3 TIMER_SYNC_SYNCWT4 Synchronize GPTM 32/64-Bit Timer 4 [21:20] TIMER_SYNC_SYNCWT4_NONE GPTM 32/64-Bit Timer 4 is not affected 0x0 TIMER_SYNC_SYNCWT4_TA A timeout event for Timer A of GPTM 32/64-Bit Timer 4 is triggered 0x1 TIMER_SYNC_SYNCWT4_TB A timeout event for Timer B of GPTM 32/64-Bit Timer 4 is triggered 0x2 TIMER_SYNC_SYNCWT4_TATB A timeout event for both Timer A and Timer B of GPTM 32/64-Bit Timer 4 is triggered 0x3 TIMER_SYNC_SYNCWT5 Synchronize GPTM 32/64-Bit Timer 5 [23:22] TIMER_SYNC_SYNCWT5_NONE GPTM 32/64-Bit Timer 5 is not affected 0x0 TIMER_SYNC_SYNCWT5_TA A timeout event for Timer A of GPTM 32/64-Bit Timer 5 is triggered 0x1 TIMER_SYNC_SYNCWT5_TB A timeout event for Timer B of GPTM 32/64-Bit Timer 5 is triggered 0x2 TIMER_SYNC_SYNCWT5_TATB A timeout event for both Timer A and Timer B of GPTM 32/64-Bit Timer 5 is triggered 0x3 IMR GPTM Interrupt Mask 0x00000018 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask [0:0] TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask [1:1] TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask [2:2] TIMER_IMR_RTCIM GPTM RTC Interrupt Mask [3:3] TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask [4:4] TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask [8:8] TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask [9:9] TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask [10:10] TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask [11:11] TIMER_IMR_WUEIM GPTM Write Update Error Interrupt Mask [16:16] RIS GPTM Raw Interrupt Status 0x0000001C TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt [0:0] TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt [1:1] TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt [2:2] TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt [3:3] TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt [4:4] TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt [8:8] TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt [9:9] TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt [10:10] TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt [11:11] TIMER_RIS_WUERIS GPTM Write Update Error Raw Interrupt [16:16] MIS GPTM Masked Interrupt Status 0x00000020 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt [0:0] TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt [1:1] TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt [2:2] TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt [3:3] TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt [4:4] TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt [8:8] TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt [9:9] TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt [10:10] TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt [11:11] TIMER_MIS_WUEMIS GPTM Write Update Error Masked Interrupt [16:16] ICR GPTM Interrupt Clear 0x00000024 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt [0:0] write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear [1:1] write-only TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear [2:2] write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear [3:3] write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear [4:4] write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear [8:8] write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear [9:9] write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear [10:10] write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear [11:11] write-only TIMER_ICR_WUECINT 32/64-Bit GPTM Write Update Error Interrupt Clear [16:16] write-only TAILR GPTM Timer A Interval Load 0x00000028 TBILR GPTM Timer B Interval Load 0x0000002C TAMATCHR GPTM Timer A Match 0x00000030 TBMATCHR GPTM Timer B Match 0x00000034 TAPR GPTM Timer A Prescale 0x00000038 TIMER_TAPR_TAPSR GPTM Timer A Prescale [7:0] TIMER_TAPR_TAPSRH GPTM Timer A Prescale High Byte [15:8] TBPR GPTM Timer B Prescale 0x0000003C TIMER_TBPR_TBPSR GPTM Timer B Prescale [7:0] TIMER_TBPR_TBPSRH GPTM Timer B Prescale High Byte [15:8] TAPMR GPTM TimerA Prescale Match 0x00000040 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match [7:0] TIMER_TAPMR_TAPSMRH GPTM Timer A Prescale Match High Byte [15:8] TBPMR GPTM TimerB Prescale Match 0x00000044 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match [7:0] TIMER_TBPMR_TBPSMRH GPTM Timer B Prescale Match High Byte [15:8] TAR GPTM Timer A 0x00000048 TBR GPTM Timer B 0x0000004C TAV GPTM Timer A Value 0x00000050 TBV GPTM Timer B Value 0x00000054 RTCPD GPTM RTC Predivide 0x00000058 TIMER_RTCPD_RTCPD RTC Predivide Counter Value [15:0] TAPS GPTM Timer A Prescale Snapshot 0x0000005C TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot [15:0] TBPS GPTM Timer B Prescale Snapshot 0x00000060 TIMER_TBPS_PSS GPTM Timer A Prescaler Value [15:0] TAPV GPTM Timer A Prescale Value 0x00000064 TIMER_TAPV_PSV GPTM Timer A Prescaler Value [15:0] TBPV GPTM Timer B Prescale Value 0x00000068 TIMER_TBPV_PSV GPTM Timer B Prescaler Value [15:0] PP GPTM Peripheral Properties 0x00000FC0 TIMER_PP_SIZE Count Size [3:0] TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 TIMER1 TIMER1 0x40031000 TIMER1A21 TIMER1B22 TIMER2 TIMER2 0x40032000 TIMER2A23 TIMER2B24 TIMER3 TIMER3 0x40033000 TIMER3A35 TIMER3B36 TIMER4 TIMER4 0x40034000 TIMER4A70 TIMER4B71 TIMER5 TIMER5 0x40035000 TIMER5A92 TIMER5B93 WTIMER0 Register map for WTIMER0 peripheral TIMER WTIMER0 0x40036000 0 0x00001000 registers WTIMER0A94 WTIMER0B95 CFG GPTM Configuration 0x00000000 TIMER_CFG GPTM Configuration [2:0] TIMER_CFG_32_BIT_TIMER 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT 16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR 0x4 TAMR GPTM Timer A Mode 0x00000004 TIMER_TAMR_TAMR GPTM Timer A Mode [1:0] TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TACMR GPTM Timer A Capture Mode [2:2] TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select [3:3] TIMER_TAMR_TACDIR GPTM Timer A Count Direction [4:4] TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable [5:5] TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger [6:6] TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode [7:7] TIMER_TAMR_TAILD GPTM Timer A Interval Load Write [8:8] TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable [9:9] TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update [10:10] TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation [11:11] TBMR GPTM Timer B Mode 0x00000008 TIMER_TBMR_TBMR GPTM Timer B Mode [1:0] TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode [2:2] TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select [3:3] TIMER_TBMR_TBCDIR GPTM Timer B Count Direction [4:4] TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable [5:5] TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger [6:6] TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode [7:7] TIMER_TBMR_TBILD GPTM Timer B Interval Load Write [8:8] TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable [9:9] TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update [10:10] TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation [11:11] CTL GPTM Control 0x0000000C TIMER_CTL_TAEN GPTM Timer A Enable [0:0] TIMER_CTL_TASTALL GPTM Timer A Stall Enable [1:1] TIMER_CTL_TAEVENT GPTM Timer A Event Mode [3:2] TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_RTCEN GPTM RTC Stall Enable [4:4] TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable [5:5] TIMER_CTL_TAPWML GPTM Timer A PWM Output Level [6:6] TIMER_CTL_TBEN GPTM Timer B Enable [8:8] TIMER_CTL_TBSTALL GPTM Timer B Stall Enable [9:9] TIMER_CTL_TBEVENT GPTM Timer B Event Mode [11:10] TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable [13:13] TIMER_CTL_TBPWML GPTM Timer B PWM Output Level [14:14] SYNC GPTM Synchronize 0x00000010 TIMER_SYNC_SYNCT0 Synchronize GPTM 16/32-Bit Timer 0 [1:0] TIMER_SYNC_SYNCT0_NONE GPTM 16/32-Bit Timer 0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM 16/32-Bit Timer 0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM 16/32-Bit Timer 0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM 16/32-Bit Timer 0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM 16/32-Bit Timer 1 [3:2] TIMER_SYNC_SYNCT1_NONE GPTM 16/32-Bit Timer 1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM 16/32-Bit Timer 1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM 16/32-Bit Timer 1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM 16/32-Bit Timer 1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM 16/32-Bit Timer 2 [5:4] TIMER_SYNC_SYNCT2_NONE GPTM 16/32-Bit Timer 2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM 16/32-Bit Timer 2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM 16/32-Bit Timer 2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM 16/32-Bit Timer 2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM 16/32-Bit Timer 3 [7:6] TIMER_SYNC_SYNCT3_NONE GPTM 16/32-Bit Timer 3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM 16/32-Bit Timer 3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM 16/32-Bit Timer 3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM 16/32-Bit Timer 3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM 16/32-Bit Timer 4 [9:8] TIMER_SYNC_SYNCT4_NONE GPTM 16/32-Bit Timer 4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM 16/32-Bit Timer 4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM 16/32-Bit Timer 4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM 16/32-Bit Timer 4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM 16/32-Bit Timer 5 [11:10] TIMER_SYNC_SYNCT5_NONE GPTM 16/32-Bit Timer 5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM 16/32-Bit Timer 5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM 16/32-Bit Timer 5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM 16/32-Bit Timer 5 is triggered 0x3 TIMER_SYNC_SYNCWT0 Synchronize GPTM 32/64-Bit Timer 0 [13:12] TIMER_SYNC_SYNCWT0_NONE GPTM 32/64-Bit Timer 0 is not affected 0x0 TIMER_SYNC_SYNCWT0_TA A timeout event for Timer A of GPTM 32/64-Bit Timer 0 is triggered 0x1 TIMER_SYNC_SYNCWT0_TB A timeout event for Timer B of GPTM 32/64-Bit Timer 0 is triggered 0x2 TIMER_SYNC_SYNCWT0_TATB A timeout event for both Timer A and Timer B of GPTM 32/64-Bit Timer 0 is triggered 0x3 TIMER_SYNC_SYNCWT1 Synchronize GPTM 32/64-Bit Timer 1 [15:14] TIMER_SYNC_SYNCWT1_NONE GPTM 32/64-Bit Timer 1 is not affected 0x0 TIMER_SYNC_SYNCWT1_TA A timeout event for Timer A of GPTM 32/64-Bit Timer 1 is triggered 0x1 TIMER_SYNC_SYNCWT1_TB A timeout event for Timer B of GPTM 32/64-Bit Timer 1 is triggered 0x2 TIMER_SYNC_SYNCWT1_TATB A timeout event for both Timer A and Timer B of GPTM 32/64-Bit Timer 1 is triggered 0x3 TIMER_SYNC_SYNCWT2 Synchronize GPTM 32/64-Bit Timer 2 [17:16] TIMER_SYNC_SYNCWT2_NONE GPTM 32/64-Bit Timer 2 is not affected 0x0 TIMER_SYNC_SYNCWT2_TA A timeout event for Timer A of GPTM 32/64-Bit Timer 2 is triggered 0x1 TIMER_SYNC_SYNCWT2_TB A timeout event for Timer B of GPTM 32/64-Bit Timer 2 is triggered 0x2 TIMER_SYNC_SYNCWT2_TATB A timeout event for both Timer A and Timer B of GPTM 32/64-Bit Timer 2 is triggered 0x3 TIMER_SYNC_SYNCWT3 Synchronize GPTM 32/64-Bit Timer 3 [19:18] TIMER_SYNC_SYNCWT3_NONE GPTM 32/64-Bit Timer 3 is not affected 0x0 TIMER_SYNC_SYNCWT3_TA A timeout event for Timer A of GPTM 32/64-Bit Timer 3 is triggered 0x1 TIMER_SYNC_SYNCWT3_TB A timeout event for Timer B of GPTM 32/64-Bit Timer 3 is triggered 0x2 TIMER_SYNC_SYNCWT3_TATB A timeout event for both Timer A and Timer B of GPTM 32/64-Bit Timer 3 is triggered 0x3 TIMER_SYNC_SYNCWT4 Synchronize GPTM 32/64-Bit Timer 4 [21:20] TIMER_SYNC_SYNCWT4_NONE GPTM 32/64-Bit Timer 4 is not affected 0x0 TIMER_SYNC_SYNCWT4_TA A timeout event for Timer A of GPTM 32/64-Bit Timer 4 is triggered 0x1 TIMER_SYNC_SYNCWT4_TB A timeout event for Timer B of GPTM 32/64-Bit Timer 4 is triggered 0x2 TIMER_SYNC_SYNCWT4_TATB A timeout event for both Timer A and Timer B of GPTM 32/64-Bit Timer 4 is triggered 0x3 TIMER_SYNC_SYNCWT5 Synchronize GPTM 32/64-Bit Timer 5 [23:22] TIMER_SYNC_SYNCWT5_NONE GPTM 32/64-Bit Timer 5 is not affected 0x0 TIMER_SYNC_SYNCWT5_TA A timeout event for Timer A of GPTM 32/64-Bit Timer 5 is triggered 0x1 TIMER_SYNC_SYNCWT5_TB A timeout event for Timer B of GPTM 32/64-Bit Timer 5 is triggered 0x2 TIMER_SYNC_SYNCWT5_TATB A timeout event for both Timer A and Timer B of GPTM 32/64-Bit Timer 5 is triggered 0x3 IMR GPTM Interrupt Mask 0x00000018 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask [0:0] TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask [1:1] TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask [2:2] TIMER_IMR_RTCIM GPTM RTC Interrupt Mask [3:3] TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask [4:4] TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask [8:8] TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask [9:9] TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask [10:10] TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask [11:11] TIMER_IMR_WUEIM GPTM Write Update Error Interrupt Mask [16:16] RIS GPTM Raw Interrupt Status 0x0000001C TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt [0:0] TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt [1:1] TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt [2:2] TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt [3:3] TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt [4:4] TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt [8:8] TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt [9:9] TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt [10:10] TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt [11:11] TIMER_RIS_WUERIS GPTM Write Update Error Raw Interrupt [16:16] MIS GPTM Masked Interrupt Status 0x00000020 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt [0:0] TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt [1:1] TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt [2:2] TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt [3:3] TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt [4:4] TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt [8:8] TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt [9:9] TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt [10:10] TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt [11:11] TIMER_MIS_WUEMIS GPTM Write Update Error Masked Interrupt [16:16] ICR GPTM Interrupt Clear 0x00000024 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt [0:0] write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear [1:1] write-only TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear [2:2] write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear [3:3] write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear [4:4] write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear [8:8] write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear [9:9] write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear [10:10] write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear [11:11] write-only TIMER_ICR_WUECINT 32/64-Bit GPTM Write Update Error Interrupt Clear [16:16] write-only TAILR GPTM Timer A Interval Load 0x00000028 TBILR GPTM Timer B Interval Load 0x0000002C TAMATCHR GPTM Timer A Match 0x00000030 TBMATCHR GPTM Timer B Match 0x00000034 TAPR GPTM Timer A Prescale 0x00000038 TIMER_TAPR_TAPSR GPTM Timer A Prescale [7:0] TIMER_TAPR_TAPSRH GPTM Timer A Prescale High Byte [15:8] TBPR GPTM Timer B Prescale 0x0000003C TIMER_TBPR_TBPSR GPTM Timer B Prescale [7:0] TIMER_TBPR_TBPSRH GPTM Timer B Prescale High Byte [15:8] TAPMR GPTM TimerA Prescale Match 0x00000040 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match [7:0] TIMER_TAPMR_TAPSMRH GPTM Timer A Prescale Match High Byte [15:8] TBPMR GPTM TimerB Prescale Match 0x00000044 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match [7:0] TIMER_TBPMR_TBPSMRH GPTM Timer B Prescale Match High Byte [15:8] TAR GPTM Timer A 0x00000048 TBR GPTM Timer B 0x0000004C TAV GPTM Timer A Value 0x00000050 TBV GPTM Timer B Value 0x00000054 RTCPD GPTM RTC Predivide 0x00000058 TIMER_RTCPD_RTCPD RTC Predivide Counter Value [15:0] TAPS GPTM Timer A Prescale Snapshot 0x0000005C TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot [15:0] TBPS GPTM Timer B Prescale Snapshot 0x00000060 TIMER_TBPS_PSS GPTM Timer A Prescaler Value [15:0] TAPV GPTM Timer A Prescale Value 0x00000064 TIMER_TAPV_PSV GPTM Timer A Prescaler Value [15:0] TBPV GPTM Timer B Prescale Value 0x00000068 TIMER_TBPV_PSV GPTM Timer B Prescaler Value [15:0] PP GPTM Peripheral Properties 0x00000FC0 TIMER_PP_SIZE Count Size [3:0] TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 WTIMER1 WTIMER1 0x40037000 WTIMER1A96 WTIMER1B97 ADC0 Register map for ADC0 peripheral ADC ADC0 0x40038000 0 0x00001000 registers ADC0SS014 ADC0SS115 ADC0SS216 ADC0SS317 ACTSS ADC Active Sample Sequencer 0x00000000 ADC_ACTSS_ASEN0 ADC SS0 Enable [0:0] ADC_ACTSS_ASEN1 ADC SS1 Enable [1:1] ADC_ACTSS_ASEN2 ADC SS2 Enable [2:2] ADC_ACTSS_ASEN3 ADC SS3 Enable [3:3] ADC_ACTSS_BUSY ADC Busy [16:16] RIS ADC Raw Interrupt Status 0x00000004 ADC_RIS_INR0 SS0 Raw Interrupt Status [0:0] ADC_RIS_INR1 SS1 Raw Interrupt Status [1:1] ADC_RIS_INR2 SS2 Raw Interrupt Status [2:2] ADC_RIS_INR3 SS3 Raw Interrupt Status [3:3] ADC_RIS_INRDC Digital Comparator Raw Interrupt Status [16:16] IM ADC Interrupt Mask 0x00000008 ADC_IM_MASK0 SS0 Interrupt Mask [0:0] ADC_IM_MASK1 SS1 Interrupt Mask [1:1] ADC_IM_MASK2 SS2 Interrupt Mask [2:2] ADC_IM_MASK3 SS3 Interrupt Mask [3:3] ADC_IM_DCONSS0 Digital Comparator Interrupt on SS0 [16:16] ADC_IM_DCONSS1 Digital Comparator Interrupt on SS1 [17:17] ADC_IM_DCONSS2 Digital Comparator Interrupt on SS2 [18:18] ADC_IM_DCONSS3 Digital Comparator Interrupt on SS3 [19:19] ISC ADC Interrupt Status and Clear 0x0000000C ADC_ISC_IN0 SS0 Interrupt Status and Clear [0:0] ADC_ISC_IN1 SS1 Interrupt Status and Clear [1:1] ADC_ISC_IN2 SS2 Interrupt Status and Clear [2:2] ADC_ISC_IN3 SS3 Interrupt Status and Clear [3:3] ADC_ISC_DCINSS0 Digital Comparator Interrupt Status on SS0 [16:16] ADC_ISC_DCINSS1 Digital Comparator Interrupt Status on SS1 [17:17] ADC_ISC_DCINSS2 Digital Comparator Interrupt Status on SS2 [18:18] ADC_ISC_DCINSS3 Digital Comparator Interrupt Status on SS3 [19:19] OSTAT ADC Overflow Status 0x00000010 ADC_OSTAT_OV0 SS0 FIFO Overflow [0:0] ADC_OSTAT_OV1 SS1 FIFO Overflow [1:1] ADC_OSTAT_OV2 SS2 FIFO Overflow [2:2] ADC_OSTAT_OV3 SS3 FIFO Overflow [3:3] EMUX ADC Event Multiplexer Select 0x00000014 ADC_EMUX_EM0 SS0 Trigger Select [3:0] ADC_EMUX_EM0_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM0_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM0_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM0_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM0_EXTERNAL External (GPIO PB4) 0x4 ADC_EMUX_EM0_TIMER Timer 0x5 ADC_EMUX_EM0_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM1 SS1 Trigger Select [7:4] ADC_EMUX_EM1_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM1_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM1_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM1_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM1_EXTERNAL External (GPIO PB4) 0x4 ADC_EMUX_EM1_TIMER Timer 0x5 ADC_EMUX_EM1_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM2 SS2 Trigger Select [11:8] ADC_EMUX_EM2_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM2_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM2_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM2_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM2_EXTERNAL External (GPIO PB4) 0x4 ADC_EMUX_EM2_TIMER Timer 0x5 ADC_EMUX_EM2_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM3 SS3 Trigger Select [15:12] ADC_EMUX_EM3_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM3_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM3_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM3_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM3_EXTERNAL External (GPIO PB4) 0x4 ADC_EMUX_EM3_TIMER Timer 0x5 ADC_EMUX_EM3_ALWAYS Always (continuously sample) 0xf USTAT ADC Underflow Status 0x00000018 ADC_USTAT_UV0 SS0 FIFO Underflow [0:0] ADC_USTAT_UV1 SS1 FIFO Underflow [1:1] ADC_USTAT_UV2 SS2 FIFO Underflow [2:2] ADC_USTAT_UV3 SS3 FIFO Underflow [3:3] SSPRI ADC Sample Sequencer Priority 0x00000020 ADC_SSPRI_SS0 SS0 Priority [1:0] ADC_SSPRI_SS1 SS1 Priority [5:4] ADC_SSPRI_SS2 SS2 Priority [9:8] ADC_SSPRI_SS3 SS3 Priority [13:12] SPC ADC Sample Phase Control 0x00000024 ADC_SPC_PHASE Phase Difference [3:0] ADC_SPC_PHASE_0 ADC sample lags by 0.0 0x0 ADC_SPC_PHASE_22_5 ADC sample lags by 22.5 0x1 ADC_SPC_PHASE_45 ADC sample lags by 45.0 0x2 ADC_SPC_PHASE_67_5 ADC sample lags by 67.5 0x3 ADC_SPC_PHASE_90 ADC sample lags by 90.0 0x4 ADC_SPC_PHASE_112_5 ADC sample lags by 112.5 0x5 ADC_SPC_PHASE_135 ADC sample lags by 135.0 0x6 ADC_SPC_PHASE_157_5 ADC sample lags by 157.5 0x7 ADC_SPC_PHASE_180 ADC sample lags by 180.0 0x8 ADC_SPC_PHASE_202_5 ADC sample lags by 202.5 0x9 ADC_SPC_PHASE_225 ADC sample lags by 225.0 0xa ADC_SPC_PHASE_247_5 ADC sample lags by 247.5 0xb ADC_SPC_PHASE_270 ADC sample lags by 270.0 0xc ADC_SPC_PHASE_292_5 ADC sample lags by 292.5 0xd ADC_SPC_PHASE_315 ADC sample lags by 315.0 0xe ADC_SPC_PHASE_337_5 ADC sample lags by 337.5 0xf PSSI ADC Processor Sample Sequence Initiate 0x00000028 ADC_PSSI_SS0 SS0 Initiate [0:0] ADC_PSSI_SS1 SS1 Initiate [1:1] ADC_PSSI_SS2 SS2 Initiate [2:2] ADC_PSSI_SS3 SS3 Initiate [3:3] ADC_PSSI_SYNCWAIT Synchronize Wait [27:27] ADC_PSSI_GSYNC Global Synchronize [31:31] SAC ADC Sample Averaging Control 0x00000030 ADC_SAC_AVG Hardware Averaging Control [2:0] ADC_SAC_AVG_OFF No hardware oversampling 0x0 ADC_SAC_AVG_2X 2x hardware oversampling 0x1 ADC_SAC_AVG_4X 4x hardware oversampling 0x2 ADC_SAC_AVG_8X 8x hardware oversampling 0x3 ADC_SAC_AVG_16X 16x hardware oversampling 0x4 ADC_SAC_AVG_32X 32x hardware oversampling 0x5 ADC_SAC_AVG_64X 64x hardware oversampling 0x6 DCISC ADC Digital Comparator Interrupt Status and Clear 0x00000034 ADC_DCISC_DCINT0 Digital Comparator 0 Interrupt Status and Clear [0:0] ADC_DCISC_DCINT1 Digital Comparator 1 Interrupt Status and Clear [1:1] ADC_DCISC_DCINT2 Digital Comparator 2 Interrupt Status and Clear [2:2] ADC_DCISC_DCINT3 Digital Comparator 3 Interrupt Status and Clear [3:3] ADC_DCISC_DCINT4 Digital Comparator 4 Interrupt Status and Clear [4:4] ADC_DCISC_DCINT5 Digital Comparator 5 Interrupt Status and Clear [5:5] ADC_DCISC_DCINT6 Digital Comparator 6 Interrupt Status and Clear [6:6] ADC_DCISC_DCINT7 Digital Comparator 7 Interrupt Status and Clear [7:7] CTL ADC Control 0x00000038 ADC_CTL_VREF Voltage Reference Select [1:0] ADC_CTL_VREF_INTERNAL The internal reference as the voltage reference 0x0 ADC_CTL_VREF_EXT_3V A 3.0 V external VREFA input is the voltage reference. The ADC conversion range is 0.0 V to the external reference value 0x1 ADC_CTL_DITHER Dither Mode Enable [6:6] SSMUX0 ADC Sample Sequence Input Multiplexer Select 0 0x00000040 ADC_SSMUX0_MUX0 1st Sample Input Select [3:0] ADC_SSMUX0_MUX1 2nd Sample Input Select [7:4] ADC_SSMUX0_MUX2 3rd Sample Input Select [11:8] ADC_SSMUX0_MUX3 4th Sample Input Select [15:12] ADC_SSMUX0_MUX4 5th Sample Input Select [19:16] ADC_SSMUX0_MUX5 6th Sample Input Select [23:20] ADC_SSMUX0_MUX6 7th Sample Input Select [27:24] ADC_SSMUX0_MUX7 8th Sample Input Select [31:28] SSCTL0 ADC Sample Sequence Control 0 0x00000044 ADC_SSCTL0_D0 1st Sample Diff Input Select [0:0] ADC_SSCTL0_END0 1st Sample is End of Sequence [1:1] ADC_SSCTL0_IE0 1st Sample Interrupt Enable [2:2] ADC_SSCTL0_TS0 1st Sample Temp Sensor Select [3:3] ADC_SSCTL0_D1 2nd Sample Diff Input Select [4:4] ADC_SSCTL0_END1 2nd Sample is End of Sequence [5:5] ADC_SSCTL0_IE1 2nd Sample Interrupt Enable [6:6] ADC_SSCTL0_TS1 2nd Sample Temp Sensor Select [7:7] ADC_SSCTL0_D2 3rd Sample Diff Input Select [8:8] ADC_SSCTL0_END2 3rd Sample is End of Sequence [9:9] ADC_SSCTL0_IE2 3rd Sample Interrupt Enable [10:10] ADC_SSCTL0_TS2 3rd Sample Temp Sensor Select [11:11] ADC_SSCTL0_D3 4th Sample Diff Input Select [12:12] ADC_SSCTL0_END3 4th Sample is End of Sequence [13:13] ADC_SSCTL0_IE3 4th Sample Interrupt Enable [14:14] ADC_SSCTL0_TS3 4th Sample Temp Sensor Select [15:15] ADC_SSCTL0_D4 5th Sample Diff Input Select [16:16] ADC_SSCTL0_END4 5th Sample is End of Sequence [17:17] ADC_SSCTL0_IE4 5th Sample Interrupt Enable [18:18] ADC_SSCTL0_TS4 5th Sample Temp Sensor Select [19:19] ADC_SSCTL0_D5 6th Sample Diff Input Select [20:20] ADC_SSCTL0_END5 6th Sample is End of Sequence [21:21] ADC_SSCTL0_IE5 6th Sample Interrupt Enable [22:22] ADC_SSCTL0_TS5 6th Sample Temp Sensor Select [23:23] ADC_SSCTL0_D6 7th Sample Diff Input Select [24:24] ADC_SSCTL0_END6 7th Sample is End of Sequence [25:25] ADC_SSCTL0_IE6 7th Sample Interrupt Enable [26:26] ADC_SSCTL0_TS6 7th Sample Temp Sensor Select [27:27] ADC_SSCTL0_D7 8th Sample Diff Input Select [28:28] ADC_SSCTL0_END7 8th Sample is End of Sequence [29:29] ADC_SSCTL0_IE7 8th Sample Interrupt Enable [30:30] ADC_SSCTL0_TS7 8th Sample Temp Sensor Select [31:31] SSFIFO0 ADC Sample Sequence Result FIFO 0 0x00000048 ADC_SSFIFO0_DATA Conversion Result Data [11:0] SSFSTAT0 ADC Sample Sequence FIFO 0 Status 0x0000004C ADC_SSFSTAT0_TPTR FIFO Tail Pointer [3:0] ADC_SSFSTAT0_HPTR FIFO Head Pointer [7:4] ADC_SSFSTAT0_EMPTY FIFO Empty [8:8] ADC_SSFSTAT0_FULL FIFO Full [12:12] SSOP0 ADC Sample Sequence 0 Operation 0x00000050 ADC_SSOP0_S0DCOP Sample 0 Digital Comparator Operation [0:0] ADC_SSOP0_S1DCOP Sample 1 Digital Comparator Operation [4:4] ADC_SSOP0_S2DCOP Sample 2 Digital Comparator Operation [8:8] ADC_SSOP0_S3DCOP Sample 3 Digital Comparator Operation [12:12] ADC_SSOP0_S4DCOP Sample 4 Digital Comparator Operation [16:16] ADC_SSOP0_S5DCOP Sample 5 Digital Comparator Operation [20:20] ADC_SSOP0_S6DCOP Sample 6 Digital Comparator Operation [24:24] ADC_SSOP0_S7DCOP Sample 7 Digital Comparator Operation [28:28] SSDC0 ADC Sample Sequence 0 Digital Comparator Select 0x00000054 ADC_SSDC0_S0DCSEL Sample 0 Digital Comparator Select [3:0] ADC_SSDC0_S1DCSEL Sample 1 Digital Comparator Select [7:4] ADC_SSDC0_S2DCSEL Sample 2 Digital Comparator Select [11:8] ADC_SSDC0_S3DCSEL Sample 3 Digital Comparator Select [15:12] ADC_SSDC0_S4DCSEL Sample 4 Digital Comparator Select [19:16] ADC_SSDC0_S5DCSEL Sample 5 Digital Comparator Select [23:20] ADC_SSDC0_S6DCSEL Sample 6 Digital Comparator Select [27:24] ADC_SSDC0_S7DCSEL Sample 7 Digital Comparator Select [31:28] SSEMUX0 ADC Sample Sequence Extended Input Multiplexer Select 0 0x00000058 ADC_SSEMUX0_EMUX0 1st Sample Input Select (Upper Bit) [0:0] ADC_SSEMUX0_EMUX1 2th Sample Input Select (Upper Bit) [4:4] ADC_SSEMUX0_EMUX2 3rd Sample Input Select (Upper Bit) [8:8] ADC_SSEMUX0_EMUX3 4th Sample Input Select (Upper Bit) [12:12] ADC_SSEMUX0_EMUX4 5th Sample Input Select (Upper Bit) [16:16] ADC_SSEMUX0_EMUX5 6th Sample Input Select (Upper Bit) [20:20] ADC_SSEMUX0_EMUX6 7th Sample Input Select (Upper Bit) [24:24] ADC_SSEMUX0_EMUX7 8th Sample Input Select (Upper Bit) [28:28] SSMUX1 ADC Sample Sequence Input Multiplexer Select 1 0x00000060 ADC_SSMUX1_MUX0 1st Sample Input Select [3:0] ADC_SSMUX1_MUX1 2nd Sample Input Select [7:4] ADC_SSMUX1_MUX2 3rd Sample Input Select [11:8] ADC_SSMUX1_MUX3 4th Sample Input Select [15:12] SSCTL1 ADC Sample Sequence Control 1 0x00000064 ADC_SSCTL1_D0 1st Sample Diff Input Select [0:0] ADC_SSCTL1_END0 1st Sample is End of Sequence [1:1] ADC_SSCTL1_IE0 1st Sample Interrupt Enable [2:2] ADC_SSCTL1_TS0 1st Sample Temp Sensor Select [3:3] ADC_SSCTL1_D1 2nd Sample Diff Input Select [4:4] ADC_SSCTL1_END1 2nd Sample is End of Sequence [5:5] ADC_SSCTL1_IE1 2nd Sample Interrupt Enable [6:6] ADC_SSCTL1_TS1 2nd Sample Temp Sensor Select [7:7] ADC_SSCTL1_D2 3rd Sample Diff Input Select [8:8] ADC_SSCTL1_END2 3rd Sample is End of Sequence [9:9] ADC_SSCTL1_IE2 3rd Sample Interrupt Enable [10:10] ADC_SSCTL1_TS2 3rd Sample Temp Sensor Select [11:11] ADC_SSCTL1_D3 4th Sample Diff Input Select [12:12] ADC_SSCTL1_END3 4th Sample is End of Sequence [13:13] ADC_SSCTL1_IE3 4th Sample Interrupt Enable [14:14] ADC_SSCTL1_TS3 4th Sample Temp Sensor Select [15:15] SSFIFO1 ADC Sample Sequence Result FIFO 1 0x00000068 ADC_SSFIFO1_DATA Conversion Result Data [11:0] SSFSTAT1 ADC Sample Sequence FIFO 1 Status 0x0000006C ADC_SSFSTAT1_TPTR FIFO Tail Pointer [3:0] ADC_SSFSTAT1_HPTR FIFO Head Pointer [7:4] ADC_SSFSTAT1_EMPTY FIFO Empty [8:8] ADC_SSFSTAT1_FULL FIFO Full [12:12] SSOP1 ADC Sample Sequence 1 Operation 0x00000070 ADC_SSOP1_S0DCOP Sample 0 Digital Comparator Operation [0:0] ADC_SSOP1_S1DCOP Sample 1 Digital Comparator Operation [4:4] ADC_SSOP1_S2DCOP Sample 2 Digital Comparator Operation [8:8] ADC_SSOP1_S3DCOP Sample 3 Digital Comparator Operation [12:12] SSDC1 ADC Sample Sequence 1 Digital Comparator Select 0x00000074 ADC_SSDC1_S0DCSEL Sample 0 Digital Comparator Select [3:0] ADC_SSDC1_S1DCSEL Sample 1 Digital Comparator Select [7:4] ADC_SSDC1_S2DCSEL Sample 2 Digital Comparator Select [11:8] ADC_SSDC1_S3DCSEL Sample 3 Digital Comparator Select [15:12] SSEMUX1 ADC Sample Sequence Extended Input Multiplexer Select 1 0x00000078 ADC_SSEMUX1_EMUX0 1st Sample Input Select (Upper Bit) [0:0] ADC_SSEMUX1_EMUX1 2th Sample Input Select (Upper Bit) [4:4] ADC_SSEMUX1_EMUX2 3rd Sample Input Select (Upper Bit) [8:8] ADC_SSEMUX1_EMUX3 4th Sample Input Select (Upper Bit) [12:12] SSMUX2 ADC Sample Sequence Input Multiplexer Select 2 0x00000080 ADC_SSMUX2_MUX0 1st Sample Input Select [3:0] ADC_SSMUX2_MUX1 2nd Sample Input Select [7:4] ADC_SSMUX2_MUX2 3rd Sample Input Select [11:8] ADC_SSMUX2_MUX3 4th Sample Input Select [15:12] SSCTL2 ADC Sample Sequence Control 2 0x00000084 ADC_SSCTL2_D0 1st Sample Diff Input Select [0:0] ADC_SSCTL2_END0 1st Sample is End of Sequence [1:1] ADC_SSCTL2_IE0 1st Sample Interrupt Enable [2:2] ADC_SSCTL2_TS0 1st Sample Temp Sensor Select [3:3] ADC_SSCTL2_D1 2nd Sample Diff Input Select [4:4] ADC_SSCTL2_END1 2nd Sample is End of Sequence [5:5] ADC_SSCTL2_IE1 2nd Sample Interrupt Enable [6:6] ADC_SSCTL2_TS1 2nd Sample Temp Sensor Select [7:7] ADC_SSCTL2_D2 3rd Sample Diff Input Select [8:8] ADC_SSCTL2_END2 3rd Sample is End of Sequence [9:9] ADC_SSCTL2_IE2 3rd Sample Interrupt Enable [10:10] ADC_SSCTL2_TS2 3rd Sample Temp Sensor Select [11:11] ADC_SSCTL2_D3 4th Sample Diff Input Select [12:12] ADC_SSCTL2_END3 4th Sample is End of Sequence [13:13] ADC_SSCTL2_IE3 4th Sample Interrupt Enable [14:14] ADC_SSCTL2_TS3 4th Sample Temp Sensor Select [15:15] SSFIFO2 ADC Sample Sequence Result FIFO 2 0x00000088 ADC_SSFIFO2_DATA Conversion Result Data [11:0] SSFSTAT2 ADC Sample Sequence FIFO 2 Status 0x0000008C ADC_SSFSTAT2_TPTR FIFO Tail Pointer [3:0] ADC_SSFSTAT2_HPTR FIFO Head Pointer [7:4] ADC_SSFSTAT2_EMPTY FIFO Empty [8:8] ADC_SSFSTAT2_FULL FIFO Full [12:12] SSOP2 ADC Sample Sequence 2 Operation 0x00000090 ADC_SSOP2_S0DCOP Sample 0 Digital Comparator Operation [0:0] ADC_SSOP2_S1DCOP Sample 1 Digital Comparator Operation [4:4] ADC_SSOP2_S2DCOP Sample 2 Digital Comparator Operation [8:8] ADC_SSOP2_S3DCOP Sample 3 Digital Comparator Operation [12:12] SSDC2 ADC Sample Sequence 2 Digital Comparator Select 0x00000094 ADC_SSDC2_S0DCSEL Sample 0 Digital Comparator Select [3:0] ADC_SSDC2_S1DCSEL Sample 1 Digital Comparator Select [7:4] ADC_SSDC2_S2DCSEL Sample 2 Digital Comparator Select [11:8] ADC_SSDC2_S3DCSEL Sample 3 Digital Comparator Select [15:12] SSEMUX2 ADC Sample Sequence Extended Input Multiplexer Select 2 0x00000098 ADC_SSEMUX2_EMUX0 1st Sample Input Select (Upper Bit) [0:0] ADC_SSEMUX2_EMUX1 2th Sample Input Select (Upper Bit) [4:4] ADC_SSEMUX2_EMUX2 3rd Sample Input Select (Upper Bit) [8:8] ADC_SSEMUX2_EMUX3 4th Sample Input Select (Upper Bit) [12:12] SSMUX3 ADC Sample Sequence Input Multiplexer Select 3 0x000000A0 ADC_SSMUX3_MUX0 1st Sample Input Select [3:0] SSCTL3 ADC Sample Sequence Control 3 0x000000A4 ADC_SSCTL3_D0 1st Sample Diff Input Select [0:0] ADC_SSCTL3_END0 1st Sample is End of Sequence [1:1] ADC_SSCTL3_IE0 1st Sample Interrupt Enable [2:2] ADC_SSCTL3_TS0 1st Sample Temp Sensor Select [3:3] SSFIFO3 ADC Sample Sequence Result FIFO 3 0x000000A8 ADC_SSFIFO3_DATA Conversion Result Data [11:0] SSFSTAT3 ADC Sample Sequence FIFO 3 Status 0x000000AC ADC_SSFSTAT3_TPTR FIFO Tail Pointer [3:0] ADC_SSFSTAT3_HPTR FIFO Head Pointer [7:4] ADC_SSFSTAT3_EMPTY FIFO Empty [8:8] ADC_SSFSTAT3_FULL FIFO Full [12:12] SSOP3 ADC Sample Sequence 3 Operation 0x000000B0 ADC_SSOP3_S0DCOP Sample 0 Digital Comparator Operation [0:0] SSDC3 ADC Sample Sequence 3 Digital Comparator Select 0x000000B4 ADC_SSDC3_S0DCSEL Sample 0 Digital Comparator Select [3:0] SSEMUX3 ADC Sample Sequence Extended Input Multiplexer Select 3 0x000000B8 ADC_SSEMUX3_EMUX0 1st Sample Input Select (Upper Bit) [0:0] DCRIC ADC Digital Comparator Reset Initial Conditions 0x00000D00 write-only ADC_DCRIC_DCINT0 Digital Comparator Interrupt 0 [0:0] write-only ADC_DCRIC_DCINT1 Digital Comparator Interrupt 1 [1:1] write-only ADC_DCRIC_DCINT2 Digital Comparator Interrupt 2 [2:2] write-only ADC_DCRIC_DCINT3 Digital Comparator Interrupt 3 [3:3] write-only ADC_DCRIC_DCINT4 Digital Comparator Interrupt 4 [4:4] write-only ADC_DCRIC_DCINT5 Digital Comparator Interrupt 5 [5:5] write-only ADC_DCRIC_DCINT6 Digital Comparator Interrupt 6 [6:6] write-only ADC_DCRIC_DCINT7 Digital Comparator Interrupt 7 [7:7] write-only ADC_DCRIC_DCTRIG0 Digital Comparator Trigger 0 [16:16] write-only ADC_DCRIC_DCTRIG1 Digital Comparator Trigger 1 [17:17] write-only ADC_DCRIC_DCTRIG2 Digital Comparator Trigger 2 [18:18] write-only ADC_DCRIC_DCTRIG3 Digital Comparator Trigger 3 [19:19] write-only ADC_DCRIC_DCTRIG4 Digital Comparator Trigger 4 [20:20] write-only ADC_DCRIC_DCTRIG5 Digital Comparator Trigger 5 [21:21] write-only ADC_DCRIC_DCTRIG6 Digital Comparator Trigger 6 [22:22] write-only ADC_DCRIC_DCTRIG7 Digital Comparator Trigger 7 [23:23] write-only DCCTL0 ADC Digital Comparator Control 0 0x00000E00 ADC_DCCTL0_CIM Comparison Interrupt Mode [1:0] ADC_DCCTL0_CIM_ALWAYS Always 0x0 ADC_DCCTL0_CIM_ONCE Once 0x1 ADC_DCCTL0_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL0_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL0_CIC Comparison Interrupt Condition [3:2] ADC_DCCTL0_CIC_LOW Low Band 0x0 ADC_DCCTL0_CIC_MID Mid Band 0x1 ADC_DCCTL0_CIC_HIGH High Band 0x3 ADC_DCCTL0_CIE Comparison Interrupt Enable [4:4] DCCTL1 ADC Digital Comparator Control 1 0x00000E04 ADC_DCCTL1_CIM Comparison Interrupt Mode [1:0] ADC_DCCTL1_CIM_ALWAYS Always 0x0 ADC_DCCTL1_CIM_ONCE Once 0x1 ADC_DCCTL1_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL1_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL1_CIC Comparison Interrupt Condition [3:2] ADC_DCCTL1_CIC_LOW Low Band 0x0 ADC_DCCTL1_CIC_MID Mid Band 0x1 ADC_DCCTL1_CIC_HIGH High Band 0x3 ADC_DCCTL1_CIE Comparison Interrupt Enable [4:4] DCCTL2 ADC Digital Comparator Control 2 0x00000E08 ADC_DCCTL2_CIM Comparison Interrupt Mode [1:0] ADC_DCCTL2_CIM_ALWAYS Always 0x0 ADC_DCCTL2_CIM_ONCE Once 0x1 ADC_DCCTL2_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL2_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL2_CIC Comparison Interrupt Condition [3:2] ADC_DCCTL2_CIC_LOW Low Band 0x0 ADC_DCCTL2_CIC_MID Mid Band 0x1 ADC_DCCTL2_CIC_HIGH High Band 0x3 ADC_DCCTL2_CIE Comparison Interrupt Enable [4:4] DCCTL3 ADC Digital Comparator Control 3 0x00000E0C ADC_DCCTL3_CIM Comparison Interrupt Mode [1:0] ADC_DCCTL3_CIM_ALWAYS Always 0x0 ADC_DCCTL3_CIM_ONCE Once 0x1 ADC_DCCTL3_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL3_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL3_CIC Comparison Interrupt Condition [3:2] ADC_DCCTL3_CIC_LOW Low Band 0x0 ADC_DCCTL3_CIC_MID Mid Band 0x1 ADC_DCCTL3_CIC_HIGH High Band 0x3 ADC_DCCTL3_CIE Comparison Interrupt Enable [4:4] DCCTL4 ADC Digital Comparator Control 4 0x00000E10 ADC_DCCTL4_CIM Comparison Interrupt Mode [1:0] ADC_DCCTL4_CIM_ALWAYS Always 0x0 ADC_DCCTL4_CIM_ONCE Once 0x1 ADC_DCCTL4_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL4_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL4_CIC Comparison Interrupt Condition [3:2] ADC_DCCTL4_CIC_LOW Low Band 0x0 ADC_DCCTL4_CIC_MID Mid Band 0x1 ADC_DCCTL4_CIC_HIGH High Band 0x3 ADC_DCCTL4_CIE Comparison Interrupt Enable [4:4] DCCTL5 ADC Digital Comparator Control 5 0x00000E14 ADC_DCCTL5_CIM Comparison Interrupt Mode [1:0] ADC_DCCTL5_CIM_ALWAYS Always 0x0 ADC_DCCTL5_CIM_ONCE Once 0x1 ADC_DCCTL5_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL5_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL5_CIC Comparison Interrupt Condition [3:2] ADC_DCCTL5_CIC_LOW Low Band 0x0 ADC_DCCTL5_CIC_MID Mid Band 0x1 ADC_DCCTL5_CIC_HIGH High Band 0x3 ADC_DCCTL5_CIE Comparison Interrupt Enable [4:4] DCCTL6 ADC Digital Comparator Control 6 0x00000E18 ADC_DCCTL6_CIM Comparison Interrupt Mode [1:0] ADC_DCCTL6_CIM_ALWAYS Always 0x0 ADC_DCCTL6_CIM_ONCE Once 0x1 ADC_DCCTL6_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL6_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL6_CIC Comparison Interrupt Condition [3:2] ADC_DCCTL6_CIC_LOW Low Band 0x0 ADC_DCCTL6_CIC_MID Mid Band 0x1 ADC_DCCTL6_CIC_HIGH High Band 0x3 ADC_DCCTL6_CIE Comparison Interrupt Enable [4:4] DCCTL7 ADC Digital Comparator Control 7 0x00000E1C ADC_DCCTL7_CIM Comparison Interrupt Mode [1:0] ADC_DCCTL7_CIM_ALWAYS Always 0x0 ADC_DCCTL7_CIM_ONCE Once 0x1 ADC_DCCTL7_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL7_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL7_CIC Comparison Interrupt Condition [3:2] ADC_DCCTL7_CIC_LOW Low Band 0x0 ADC_DCCTL7_CIC_MID Mid Band 0x1 ADC_DCCTL7_CIC_HIGH High Band 0x3 ADC_DCCTL7_CIE Comparison Interrupt Enable [4:4] DCCMP0 ADC Digital Comparator Range 0 0x00000E40 ADC_DCCMP0_COMP0 Compare 0 [11:0] ADC_DCCMP0_COMP1 Compare 1 [27:16] DCCMP1 ADC Digital Comparator Range 1 0x00000E44 ADC_DCCMP1_COMP0 Compare 0 [11:0] ADC_DCCMP1_COMP1 Compare 1 [27:16] DCCMP2 ADC Digital Comparator Range 2 0x00000E48 ADC_DCCMP2_COMP0 Compare 0 [11:0] ADC_DCCMP2_COMP1 Compare 1 [27:16] DCCMP3 ADC Digital Comparator Range 3 0x00000E4C ADC_DCCMP3_COMP0 Compare 0 [11:0] ADC_DCCMP3_COMP1 Compare 1 [27:16] DCCMP4 ADC Digital Comparator Range 4 0x00000E50 ADC_DCCMP4_COMP0 Compare 0 [11:0] ADC_DCCMP4_COMP1 Compare 1 [27:16] DCCMP5 ADC Digital Comparator Range 5 0x00000E54 ADC_DCCMP5_COMP0 Compare 0 [11:0] ADC_DCCMP5_COMP1 Compare 1 [27:16] DCCMP6 ADC Digital Comparator Range 6 0x00000E58 ADC_DCCMP6_COMP0 Compare 0 [11:0] ADC_DCCMP6_COMP1 Compare 1 [27:16] DCCMP7 ADC Digital Comparator Range 7 0x00000E5C ADC_DCCMP7_COMP0 Compare 0 [11:0] ADC_DCCMP7_COMP1 Compare 1 [27:16] PP ADC Peripheral Properties 0x00000FC0 ADC_PP_MSR Maximum ADC Sample Rate [3:0] ADC_PP_MSR_125K 125 ksps 0x1 ADC_PP_MSR_250K 250 ksps 0x3 ADC_PP_MSR_500K 500 ksps 0x5 ADC_PP_MSR_1M 1 Msps 0x7 ADC_PP_CH ADC Channel Count [9:4] ADC_PP_DC Digital Comparator Count [15:10] ADC_PP_TYPE ADC Architecture [17:16] ADC_PP_TYPE_SAR SAR 0x0 ADC_PP_RSL Resolution [22:18] ADC_PP_TS Temperature Sensor [23:23] PC ADC Peripheral Configuration 0x00000FC4 ADC_PC_SR ADC Sample Rate [3:0] ADC_PC_SR_125K 125 ksps 0x1 ADC_PC_SR_250K 250 ksps 0x3 ADC_PC_SR_500K 500 ksps 0x5 ADC_PC_SR_1M 1 Msps 0x7 CC ADC Clock Configuration 0x00000FC8 ADC_CC_CS ADC Clock Source [3:0] ADC_CC_CS_SYSPLL Either the system clock (if the PLL bypass is in effect) or the 16 MHz clock derived from PLL / 25 (default) 0x0 ADC_CC_CS_PIOSC PIOSC 0x1 ADC1 ADC1 0x40039000 ADC1SS048 ADC1SS149 ADC1SS250 ADC1SS351 COMP Register map for COMP peripheral COMP COMP 0x4003C000 0 0x00001000 registers COMP025 COMP126 COMP227 ACMIS Analog Comparator Masked Interrupt Status 0x00000000 COMP_ACMIS_IN0 Comparator 0 Masked Interrupt Status [0:0] COMP_ACMIS_IN1 Comparator 1 Masked Interrupt Status [1:1] COMP_ACMIS_IN2 Comparator 2 Masked Interrupt Status [2:2] ACRIS Analog Comparator Raw Interrupt Status 0x00000004 COMP_ACRIS_IN0 Comparator 0 Interrupt Status [0:0] COMP_ACRIS_IN1 Comparator 1 Interrupt Status [1:1] COMP_ACRIS_IN2 Comparator 2 Interrupt Status [2:2] ACINTEN Analog Comparator Interrupt Enable 0x00000008 COMP_ACINTEN_IN0 Comparator 0 Interrupt Enable [0:0] COMP_ACINTEN_IN1 Comparator 1 Interrupt Enable [1:1] COMP_ACINTEN_IN2 Comparator 2 Interrupt Enable [2:2] ACREFCTL Analog Comparator Reference Voltage Control 0x00000010 COMP_ACREFCTL_VREF Resistor Ladder Voltage Ref [3:0] COMP_ACREFCTL_RNG Resistor Ladder Range [8:8] COMP_ACREFCTL_EN Resistor Ladder Enable [9:9] ACSTAT0 Analog Comparator Status 0 0x00000020 COMP_ACSTAT0_OVAL Comparator Output Value [1:1] ACCTL0 Analog Comparator Control 0 0x00000024 COMP_ACCTL0_CINV Comparator Output Invert [1:1] COMP_ACCTL0_ISEN Interrupt Sense [3:2] COMP_ACCTL0_ISEN_LEVEL Level sense, see ISLVAL 0x0 COMP_ACCTL0_ISEN_FALL Falling edge 0x1 COMP_ACCTL0_ISEN_RISE Rising edge 0x2 COMP_ACCTL0_ISEN_BOTH Either edge 0x3 COMP_ACCTL0_ISLVAL Interrupt Sense Level Value [4:4] COMP_ACCTL0_TSEN Trigger Sense [6:5] COMP_ACCTL0_TSEN_LEVEL Level sense, see TSLVAL 0x0 COMP_ACCTL0_TSEN_FALL Falling edge 0x1 COMP_ACCTL0_TSEN_RISE Rising edge 0x2 COMP_ACCTL0_TSEN_BOTH Either edge 0x3 COMP_ACCTL0_TSLVAL Trigger Sense Level Value [7:7] COMP_ACCTL0_ASRCP Analog Source Positive [10:9] COMP_ACCTL0_ASRCP_PIN Pin value of Cn+ 0x0 COMP_ACCTL0_ASRCP_PIN0 Pin value of C0+ 0x1 COMP_ACCTL0_ASRCP_REF Internal voltage reference 0x2 COMP_ACCTL0_TOEN Trigger Output Enable [11:11] ACSTAT1 Analog Comparator Status 1 0x00000040 COMP_ACSTAT1_OVAL Comparator Output Value [1:1] ACCTL1 Analog Comparator Control 1 0x00000044 COMP_ACCTL1_CINV Comparator Output Invert [1:1] COMP_ACCTL1_ISEN Interrupt Sense [3:2] COMP_ACCTL1_ISEN_LEVEL Level sense, see ISLVAL 0x0 COMP_ACCTL1_ISEN_FALL Falling edge 0x1 COMP_ACCTL1_ISEN_RISE Rising edge 0x2 COMP_ACCTL1_ISEN_BOTH Either edge 0x3 COMP_ACCTL1_ISLVAL Interrupt Sense Level Value [4:4] COMP_ACCTL1_TSEN Trigger Sense [6:5] COMP_ACCTL1_TSEN_LEVEL Level sense, see TSLVAL 0x0 COMP_ACCTL1_TSEN_FALL Falling edge 0x1 COMP_ACCTL1_TSEN_RISE Rising edge 0x2 COMP_ACCTL1_TSEN_BOTH Either edge 0x3 COMP_ACCTL1_TSLVAL Trigger Sense Level Value [7:7] COMP_ACCTL1_ASRCP Analog Source Positive [10:9] COMP_ACCTL1_ASRCP_PIN Pin value of Cn+ 0x0 COMP_ACCTL1_ASRCP_PIN0 Pin value of C0+ 0x1 COMP_ACCTL1_ASRCP_REF Internal voltage reference (VIREF) 0x2 COMP_ACCTL1_TOEN Trigger Output Enable [11:11] ACSTAT2 Analog Comparator Status 2 0x00000060 COMP_ACSTAT2_OVAL Comparator Output Value [1:1] ACCTL2 Analog Comparator Control 2 0x00000064 COMP_ACCTL2_CINV Comparator Output Invert [1:1] COMP_ACCTL2_ISEN Interrupt Sense [3:2] COMP_ACCTL2_ISEN_LEVEL Level sense, see ISLVAL 0x0 COMP_ACCTL2_ISEN_FALL Falling edge 0x1 COMP_ACCTL2_ISEN_RISE Rising edge 0x2 COMP_ACCTL2_ISEN_BOTH Either edge 0x3 COMP_ACCTL2_ISLVAL Interrupt Sense Level Value [4:4] COMP_ACCTL2_TSEN Trigger Sense [6:5] COMP_ACCTL2_TSEN_LEVEL Level sense, see TSLVAL 0x0 COMP_ACCTL2_TSEN_FALL Falling edge 0x1 COMP_ACCTL2_TSEN_RISE Rising edge 0x2 COMP_ACCTL2_TSEN_BOTH Either edge 0x3 COMP_ACCTL2_TSLVAL Trigger Sense Level Value [7:7] COMP_ACCTL2_ASRCP Analog Source Positive [10:9] COMP_ACCTL2_ASRCP_PIN Pin value of Cn+ 0x0 COMP_ACCTL2_ASRCP_PIN0 Pin value of C0+ 0x1 COMP_ACCTL2_ASRCP_REF Internal voltage reference (VIREF) 0x2 COMP_ACCTL2_TOEN Trigger Output Enable [11:11] PP Analog Comparator Peripheral Properties 0x00000FC0 COMP_PP_CMP0 Comparator 0 Present [0:0] COMP_PP_CMP1 Comparator 1 Present [1:1] COMP_PP_CMP2 Comparator 2 Present [2:2] COMP_PP_C0O Comparator Output 0 Present [16:16] COMP_PP_C1O Comparator Output 1 Present [17:17] COMP_PP_C2O Comparator Output 2 Present [18:18] GPIOJ GPIOJ 0x4003D000 GPIOJ54 CAN0 Register map for CAN0 peripheral CAN CAN0 0x40040000 0 0x00001000 registers CAN039 CTL CAN Control 0x00000000 CAN_CTL_INIT Initialization [0:0] CAN_CTL_IE CAN Interrupt Enable [1:1] CAN_CTL_SIE Status Interrupt Enable [2:2] CAN_CTL_EIE Error Interrupt Enable [3:3] CAN_CTL_DAR Disable Automatic-Retransmission [5:5] CAN_CTL_CCE Configuration Change Enable [6:6] CAN_CTL_TEST Test Mode Enable [7:7] STS CAN Status 0x00000004 CAN_STS_LEC Last Error Code [2:0] CAN_STS_LEC_NONE No Error 0x0 CAN_STS_LEC_STUFF Stuff Error 0x1 CAN_STS_LEC_FORM Format Error 0x2 CAN_STS_LEC_ACK ACK Error 0x3 CAN_STS_LEC_BIT1 Bit 1 Error 0x4 CAN_STS_LEC_BIT0 Bit 0 Error 0x5 CAN_STS_LEC_CRC CRC Error 0x6 CAN_STS_LEC_NOEVENT No Event 0x7 CAN_STS_TXOK Transmitted a Message Successfully [3:3] CAN_STS_RXOK Received a Message Successfully [4:4] CAN_STS_EPASS Error Passive [5:5] CAN_STS_EWARN Warning Status [6:6] CAN_STS_BOFF Bus-Off Status [7:7] ERR CAN Error Counter 0x00000008 CAN_ERR_TEC Transmit Error Counter [7:0] CAN_ERR_REC Receive Error Counter [14:8] CAN_ERR_RP Received Error Passive [15:15] BIT CAN Bit Timing 0x0000000C CAN_BIT_BRP Baud Rate Prescaler [5:0] CAN_BIT_SJW (Re)Synchronization Jump Width [7:6] CAN_BIT_TSEG1 Time Segment Before Sample Point [11:8] CAN_BIT_TSEG2 Time Segment after Sample Point [14:12] INT CAN Interrupt 0x00000010 CAN_INT_INTID Interrupt Identifier [15:0] CAN_INT_INTID_NONE No interrupt pending 0x0 CAN_INT_INTID_STATUS Status Interrupt 0x8000 TST CAN Test 0x00000014 CAN_TST_BASIC Basic Mode [2:2] CAN_TST_SILENT Silent Mode [3:3] CAN_TST_LBACK Loopback Mode [4:4] CAN_TST_TX Transmit Control [6:5] CAN_TST_TX_CANCTL CAN Module Control 0x0 CAN_TST_TX_SAMPLE Sample Point 0x1 CAN_TST_TX_DOMINANT Driven Low 0x2 CAN_TST_TX_RECESSIVE Driven High 0x3 CAN_TST_RX Receive Observation [7:7] BRPE CAN Baud Rate Prescaler Extension 0x00000018 CAN_BRPE_BRPE Baud Rate Prescaler Extension [3:0] IF1CRQ CAN IF1 Command Request 0x00000020 CAN_IF1CRQ_MNUM Message Number [5:0] CAN_IF1CRQ_BUSY Busy Flag [15:15] IF1CMSK CAN IF1 Command Mask 0x00000024 CAN_IF1CMSK_DATAB Access Data Byte 4 to 7 [0:0] CAN_IF1CMSK_DATAA Access Data Byte 0 to 3 [1:1] CAN_IF1CMSK_NEWDAT Access New Data [2:2] CAN_IF1CMSK_CLRINTPND Clear Interrupt Pending Bit [3:3] CAN_IF1CMSK_CONTROL Access Control Bits [4:4] CAN_IF1CMSK_ARB Access Arbitration Bits [5:5] CAN_IF1CMSK_MASK Access Mask Bits [6:6] CAN_IF1CMSK_WRNRD Write, Not Read [7:7] IF1CMSK CAN IF1 Command Mask CAN0_ALT 0x00000024 CAN_IF1CMSK_TXRQST Access Transmission Request [2:2] IF1MSK1 CAN IF1 Mask 1 0x00000028 CAN_IF1MSK1_IDMSK Identifier Mask [15:0] IF1MSK2 CAN IF1 Mask 2 0x0000002C CAN_IF1MSK2_IDMSK Identifier Mask [12:0] CAN_IF1MSK2_MDIR Mask Message Direction [14:14] CAN_IF1MSK2_MXTD Mask Extended Identifier [15:15] IF1ARB1 CAN IF1 Arbitration 1 0x00000030 CAN_IF1ARB1_ID Message Identifier [15:0] IF1ARB2 CAN IF1 Arbitration 2 0x00000034 CAN_IF1ARB2_ID Message Identifier [12:0] CAN_IF1ARB2_DIR Message Direction [13:13] CAN_IF1ARB2_XTD Extended Identifier [14:14] CAN_IF1ARB2_MSGVAL Message Valid [15:15] IF1MCTL CAN IF1 Message Control 0x00000038 CAN_IF1MCTL_DLC Data Length Code [3:0] CAN_IF1MCTL_EOB End of Buffer [7:7] CAN_IF1MCTL_TXRQST Transmit Request [8:8] CAN_IF1MCTL_RMTEN Remote Enable [9:9] CAN_IF1MCTL_RXIE Receive Interrupt Enable [10:10] CAN_IF1MCTL_TXIE Transmit Interrupt Enable [11:11] CAN_IF1MCTL_UMASK Use Acceptance Mask [12:12] CAN_IF1MCTL_INTPND Interrupt Pending [13:13] CAN_IF1MCTL_MSGLST Message Lost [14:14] CAN_IF1MCTL_NEWDAT New Data [15:15] IF1DA1 CAN IF1 Data A1 0x0000003C CAN_IF1DA1_DATA Data [15:0] IF1DA2 CAN IF1 Data A2 0x00000040 CAN_IF1DA2_DATA Data [15:0] IF1DB1 CAN IF1 Data B1 0x00000044 CAN_IF1DB1_DATA Data [15:0] IF1DB2 CAN IF1 Data B2 0x00000048 CAN_IF1DB2_DATA Data [15:0] IF2CRQ CAN IF2 Command Request 0x00000080 CAN_IF2CRQ_MNUM Message Number [5:0] CAN_IF2CRQ_BUSY Busy Flag [15:15] IF2CMSK CAN IF2 Command Mask 0x00000084 CAN_IF2CMSK_DATAB Access Data Byte 4 to 7 [0:0] CAN_IF2CMSK_DATAA Access Data Byte 0 to 3 [1:1] CAN_IF2CMSK_NEWDAT Access New Data [2:2] CAN_IF2CMSK_CLRINTPND Clear Interrupt Pending Bit [3:3] CAN_IF2CMSK_CONTROL Access Control Bits [4:4] CAN_IF2CMSK_ARB Access Arbitration Bits [5:5] CAN_IF2CMSK_MASK Access Mask Bits [6:6] CAN_IF2CMSK_WRNRD Write, Not Read [7:7] IF2CMSK CAN IF2 Command Mask CAN0_ALT 0x00000084 CAN_IF2CMSK_TXRQST Access Transmission Request [2:2] IF2MSK1 CAN IF2 Mask 1 0x00000088 CAN_IF2MSK1_IDMSK Identifier Mask [15:0] IF2MSK2 CAN IF2 Mask 2 0x0000008C CAN_IF2MSK2_IDMSK Identifier Mask [12:0] CAN_IF2MSK2_MDIR Mask Message Direction [14:14] CAN_IF2MSK2_MXTD Mask Extended Identifier [15:15] IF2ARB1 CAN IF2 Arbitration 1 0x00000090 CAN_IF2ARB1_ID Message Identifier [15:0] IF2ARB2 CAN IF2 Arbitration 2 0x00000094 CAN_IF2ARB2_ID Message Identifier [12:0] CAN_IF2ARB2_DIR Message Direction [13:13] CAN_IF2ARB2_XTD Extended Identifier [14:14] CAN_IF2ARB2_MSGVAL Message Valid [15:15] IF2MCTL CAN IF2 Message Control 0x00000098 CAN_IF2MCTL_DLC Data Length Code [3:0] CAN_IF2MCTL_EOB End of Buffer [7:7] CAN_IF2MCTL_TXRQST Transmit Request [8:8] CAN_IF2MCTL_RMTEN Remote Enable [9:9] CAN_IF2MCTL_RXIE Receive Interrupt Enable [10:10] CAN_IF2MCTL_TXIE Transmit Interrupt Enable [11:11] CAN_IF2MCTL_UMASK Use Acceptance Mask [12:12] CAN_IF2MCTL_INTPND Interrupt Pending [13:13] CAN_IF2MCTL_MSGLST Message Lost [14:14] CAN_IF2MCTL_NEWDAT New Data [15:15] IF2DA1 CAN IF2 Data A1 0x0000009C CAN_IF2DA1_DATA Data [15:0] IF2DA2 CAN IF2 Data A2 0x000000A0 CAN_IF2DA2_DATA Data [15:0] IF2DB1 CAN IF2 Data B1 0x000000A4 CAN_IF2DB1_DATA Data [15:0] IF2DB2 CAN IF2 Data B2 0x000000A8 CAN_IF2DB2_DATA Data [15:0] TXRQ1 CAN Transmission Request 1 0x00000100 CAN_TXRQ1_TXRQST Transmission Request Bits [15:0] TXRQ2 CAN Transmission Request 2 0x00000104 CAN_TXRQ2_TXRQST Transmission Request Bits [15:0] NWDA1 CAN New Data 1 0x00000120 CAN_NWDA1_NEWDAT New Data Bits [15:0] NWDA2 CAN New Data 2 0x00000124 CAN_NWDA2_NEWDAT New Data Bits [15:0] MSG1INT CAN Message 1 Interrupt Pending 0x00000140 CAN_MSG1INT_INTPND Interrupt Pending Bits [15:0] MSG2INT CAN Message 2 Interrupt Pending 0x00000144 CAN_MSG2INT_INTPND Interrupt Pending Bits [15:0] MSG1VAL CAN Message 1 Valid 0x00000160 CAN_MSG1VAL_MSGVAL Message Valid Bits [15:0] MSG2VAL CAN Message 2 Valid 0x00000164 CAN_MSG2VAL_MSGVAL Message Valid Bits [15:0] WTIMER2 WTIMER2 0x4004C000 WTIMER2A98 WTIMER2B99 WTIMER3 WTIMER3 0x4004D000 WTIMER3A100 WTIMER3B101 WTIMER4 WTIMER4 0x4004E000 WTIMER4A102 WTIMER4B103 WTIMER5 WTIMER5 0x4004F000 WTIMER5A104 WTIMER5B105 USB0 Register map for USB0 peripheral USB USB0 0x40050000 0 0x00001000 registers USB044 FADDR USB Device Functional Address 0x00000000 8 USB_FADDR Function Address [6:0] POWER USB Power 0x00000001 8 USB_POWER_PWRDNPHY Power Down PHY [0:0] USB_POWER_SUSPEND SUSPEND Mode [1:1] USB_POWER_RESUME RESUME Signaling [2:2] USB_POWER_RESET RESET Signaling [3:3] USB_POWER_SOFTCONN Soft Connect/Disconnect [6:6] USB_POWER_ISOUP Isochronous Update [7:7] TXIS USB Transmit Interrupt Status 0x00000002 16 USB_TXIS_EP0 TX and RX Endpoint 0 Interrupt [0:0] USB_TXIS_EP1 TX Endpoint 1 Interrupt [1:1] USB_TXIS_EP2 TX Endpoint 2 Interrupt [2:2] USB_TXIS_EP3 TX Endpoint 3 Interrupt [3:3] USB_TXIS_EP4 TX Endpoint 4 Interrupt [4:4] USB_TXIS_EP5 TX Endpoint 5 Interrupt [5:5] USB_TXIS_EP6 TX Endpoint 6 Interrupt [6:6] USB_TXIS_EP7 TX Endpoint 7 Interrupt [7:7] RXIS USB Receive Interrupt Status 0x00000004 16 USB_RXIS_EP1 RX Endpoint 1 Interrupt [1:1] USB_RXIS_EP2 RX Endpoint 2 Interrupt [2:2] USB_RXIS_EP3 RX Endpoint 3 Interrupt [3:3] USB_RXIS_EP4 RX Endpoint 4 Interrupt [4:4] USB_RXIS_EP5 RX Endpoint 5 Interrupt [5:5] USB_RXIS_EP6 RX Endpoint 6 Interrupt [6:6] USB_RXIS_EP7 RX Endpoint 7 Interrupt [7:7] TXIE USB Transmit Interrupt Enable 0x00000006 16 USB_TXIE_EP0 TX and RX Endpoint 0 Interrupt Enable [0:0] USB_TXIE_EP1 TX Endpoint 1 Interrupt Enable [1:1] USB_TXIE_EP2 TX Endpoint 2 Interrupt Enable [2:2] USB_TXIE_EP3 TX Endpoint 3 Interrupt Enable [3:3] USB_TXIE_EP4 TX Endpoint 4 Interrupt Enable [4:4] USB_TXIE_EP5 TX Endpoint 5 Interrupt Enable [5:5] USB_TXIE_EP6 TX Endpoint 6 Interrupt Enable [6:6] USB_TXIE_EP7 TX Endpoint 7 Interrupt Enable [7:7] RXIE USB Receive Interrupt Enable 0x00000008 16 USB_RXIE_EP1 RX Endpoint 1 Interrupt Enable [1:1] USB_RXIE_EP2 RX Endpoint 2 Interrupt Enable [2:2] USB_RXIE_EP3 RX Endpoint 3 Interrupt Enable [3:3] USB_RXIE_EP4 RX Endpoint 4 Interrupt Enable [4:4] USB_RXIE_EP5 RX Endpoint 5 Interrupt Enable [5:5] USB_RXIE_EP6 RX Endpoint 6 Interrupt Enable [6:6] USB_RXIE_EP7 RX Endpoint 7 Interrupt Enable [7:7] IS USB General Interrupt Status 0x0000000A 8 USB_IS_SUSPEND SUSPEND Signaling Detected [0:0] USB_IS_RESUME RESUME Signaling Detected [1:1] USB_IS_SOF Start of Frame [3:3] IS USB General Interrupt Status USB0_ALT 0x0000000A 8 USB_IS_RESET RESET Signaling Detected [2:2] IE USB Interrupt Enable 0x0000000B 8 USB_IE_SUSPND Enable SUSPEND Interrupt [0:0] USB_IE_RESUME Enable RESUME Interrupt [1:1] USB_IE_SOF Enable Start-of-Frame Interrupt [3:3] USB_IE_DISCON Enable Disconnect Interrupt [5:5] IE USB Interrupt Enable USB0_ALT 0x0000000B 8 USB_IE_RESET Enable RESET Interrupt [2:2] FRAME USB Frame Value 0x0000000C 16 USB_FRAME Frame Number [10:0] EPIDX USB Endpoint Index 0x0000000E 8 USB_EPIDX_EPIDX Endpoint Index [3:0] TEST USB Test Mode 0x0000000F 8 USB_TEST_FORCEFS Force Full-Speed Mode [5:5] USB_TEST_FIFOACC FIFO Access [6:6] FIFO0 USB FIFO Endpoint 0 0x00000020 USB_FIFO0_EPDATA Endpoint Data [31:0] FIFO1 USB FIFO Endpoint 1 0x00000024 USB_FIFO1_EPDATA Endpoint Data [31:0] FIFO2 USB FIFO Endpoint 2 0x00000028 USB_FIFO2_EPDATA Endpoint Data [31:0] FIFO3 USB FIFO Endpoint 3 0x0000002C USB_FIFO3_EPDATA Endpoint Data [31:0] FIFO4 USB FIFO Endpoint 4 0x00000030 USB_FIFO4_EPDATA Endpoint Data [31:0] FIFO5 USB FIFO Endpoint 5 0x00000034 USB_FIFO5_EPDATA Endpoint Data [31:0] FIFO6 USB FIFO Endpoint 6 0x00000038 USB_FIFO6_EPDATA Endpoint Data [31:0] FIFO7 USB FIFO Endpoint 7 0x0000003C USB_FIFO7_EPDATA Endpoint Data [31:0] TXFIFOSZ USB Transmit Dynamic FIFO Sizing 0x00000062 8 USB_TXFIFOSZ_SIZE Max Packet Size [3:0] USB_TXFIFOSZ_SIZE_8 8 0x0 USB_TXFIFOSZ_SIZE_16 16 0x1 USB_TXFIFOSZ_SIZE_32 32 0x2 USB_TXFIFOSZ_SIZE_64 64 0x3 USB_TXFIFOSZ_SIZE_128 128 0x4 USB_TXFIFOSZ_SIZE_256 256 0x5 USB_TXFIFOSZ_SIZE_512 512 0x6 USB_TXFIFOSZ_SIZE_1024 1024 0x7 USB_TXFIFOSZ_SIZE_2048 2048 0x8 USB_TXFIFOSZ_DPB Double Packet Buffer Support [4:4] RXFIFOSZ USB Receive Dynamic FIFO Sizing 0x00000063 8 USB_RXFIFOSZ_SIZE Max Packet Size [3:0] USB_RXFIFOSZ_SIZE_8 8 0x0 USB_RXFIFOSZ_SIZE_16 16 0x1 USB_RXFIFOSZ_SIZE_32 32 0x2 USB_RXFIFOSZ_SIZE_64 64 0x3 USB_RXFIFOSZ_SIZE_128 128 0x4 USB_RXFIFOSZ_SIZE_256 256 0x5 USB_RXFIFOSZ_SIZE_512 512 0x6 USB_RXFIFOSZ_SIZE_1024 1024 0x7 USB_RXFIFOSZ_SIZE_2048 2048 0x8 USB_RXFIFOSZ_DPB Double Packet Buffer Support [4:4] TXFIFOADD USB Transmit FIFO Start Address 0x00000064 16 USB_TXFIFOADD_ADDR Transmit/Receive Start Address [8:0] RXFIFOADD USB Receive FIFO Start Address 0x00000066 16 USB_RXFIFOADD_ADDR Transmit/Receive Start Address [8:0] CONTIM USB Connect Timing 0x0000007A 8 USB_CONTIM_WTID Wait ID [3:0] USB_CONTIM_WTCON Connect Wait [7:4] FSEOF USB Full-Speed Last Transaction to End of Frame Timing 0x0000007D 8 USB_FSEOF_FSEOFG Full-Speed End-of-Frame Gap [7:0] LSEOF USB Low-Speed Last Transaction to End of Frame Timing 0x0000007E 8 USB_LSEOF_LSEOFG Low-Speed End-of-Frame Gap [7:0] CSRL0 USB Control and Status Endpoint 0 Low 0x00000102 8 write-only USB_CSRL0_RXRDY Receive Packet Ready [0:0] write-only USB_CSRL0_TXRDY Transmit Packet Ready [1:1] write-only USB_CSRL0_STALLED Endpoint Stalled [2:2] write-only USB_CSRL0_DATAEND Data End [3:3] write-only USB_CSRL0_SETEND Setup End [4:4] write-only USB_CSRL0_STALL Send Stall [5:5] write-only USB_CSRL0_RXRDYC RXRDY Clear [6:6] write-only USB_CSRL0_SETENDC Setup End Clear [7:7] write-only CSRH0 USB Control and Status Endpoint 0 High 0x00000103 8 write-only USB_CSRH0_FLUSH Flush FIFO [0:0] write-only COUNT0 USB Receive Byte Count Endpoint 0 0x00000108 8 USB_COUNT0_COUNT FIFO Count [6:0] TXMAXP1 USB Maximum Transmit Data Endpoint 1 0x00000110 16 USB_TXMAXP1_MAXLOAD Maximum Payload [10:0] TXCSRL1 USB Transmit Control and Status Endpoint 1 Low 0x00000112 8 USB_TXCSRL1_TXRDY Transmit Packet Ready [0:0] USB_TXCSRL1_FIFONE FIFO Not Empty [1:1] USB_TXCSRL1_FLUSH Flush FIFO [3:3] USB_TXCSRL1_STALLED Endpoint Stalled [5:5] USB_TXCSRL1_CLRDT Clear Data Toggle [6:6] TXCSRL1 USB Transmit Control and Status Endpoint 1 Low USB0_ALT 0x00000112 8 USB_TXCSRL1_UNDRN Underrun [2:2] USB_TXCSRL1_STALL Send STALL [4:4] TXCSRH1 USB Transmit Control and Status Endpoint 1 High 0x00000113 8 USB_TXCSRH1_DMAMOD DMA Request Mode [2:2] USB_TXCSRH1_FDT Force Data Toggle [3:3] USB_TXCSRH1_DMAEN DMA Request Enable [4:4] USB_TXCSRH1_MODE Mode [5:5] USB_TXCSRH1_ISO Isochronous Transfers [6:6] USB_TXCSRH1_AUTOSET Auto Set [7:7] RXMAXP1 USB Maximum Receive Data Endpoint 1 0x00000114 16 USB_RXMAXP1_MAXLOAD Maximum Payload [10:0] RXCSRL1 USB Receive Control and Status Endpoint 1 Low 0x00000116 8 USB_RXCSRL1_RXRDY Receive Packet Ready [0:0] USB_RXCSRL1_FULL FIFO Full [1:1] USB_RXCSRL1_OVER Overrun [2:2] USB_RXCSRL1_DATAERR Data Error [3:3] USB_RXCSRL1_FLUSH Flush FIFO [4:4] USB_RXCSRL1_STALL Send STALL [5:5] USB_RXCSRL1_STALLED Endpoint Stalled [6:6] USB_RXCSRL1_CLRDT Clear Data Toggle [7:7] RXCSRH1 USB Receive Control and Status Endpoint 1 High 0x00000117 8 USB_RXCSRH1_DMAMOD DMA Request Mode [3:3] USB_RXCSRH1_PIDERR PID Error [4:4] USB_RXCSRH1_DMAEN DMA Request Enable [5:5] USB_RXCSRH1_AUTOCL Auto Clear [7:7] RXCSRH1 USB Receive Control and Status Endpoint 1 High USB0_ALT 0x00000117 8 USB_RXCSRH1_DISNYET Disable NYET [4:4] USB_RXCSRH1_ISO Isochronous Transfers [6:6] RXCOUNT1 USB Receive Byte Count Endpoint 1 0x00000118 16 USB_RXCOUNT1_COUNT Receive Packet Count [12:0] TXMAXP2 USB Maximum Transmit Data Endpoint 2 0x00000120 16 USB_TXMAXP2_MAXLOAD Maximum Payload [10:0] TXCSRL2 USB Transmit Control and Status Endpoint 2 Low 0x00000122 8 USB_TXCSRL2_TXRDY Transmit Packet Ready [0:0] USB_TXCSRL2_FIFONE FIFO Not Empty [1:1] USB_TXCSRL2_FLUSH Flush FIFO [3:3] USB_TXCSRL2_STALLED Endpoint Stalled [5:5] USB_TXCSRL2_CLRDT Clear Data Toggle [6:6] TXCSRL2 USB Transmit Control and Status Endpoint 2 Low USB0_ALT 0x00000122 8 USB_TXCSRL2_UNDRN Underrun [2:2] USB_TXCSRL2_STALL Send STALL [4:4] TXCSRH2 USB Transmit Control and Status Endpoint 2 High 0x00000123 8 USB_TXCSRH2_DMAMOD DMA Request Mode [2:2] USB_TXCSRH2_FDT Force Data Toggle [3:3] USB_TXCSRH2_DMAEN DMA Request Enable [4:4] USB_TXCSRH2_MODE Mode [5:5] USB_TXCSRH2_ISO Isochronous Transfers [6:6] USB_TXCSRH2_AUTOSET Auto Set [7:7] RXMAXP2 USB Maximum Receive Data Endpoint 2 0x00000124 16 USB_RXMAXP2_MAXLOAD Maximum Payload [10:0] RXCSRL2 USB Receive Control and Status Endpoint 2 Low 0x00000126 8 USB_RXCSRL2_RXRDY Receive Packet Ready [0:0] USB_RXCSRL2_FULL FIFO Full [1:1] USB_RXCSRL2_OVER Overrun [2:2] USB_RXCSRL2_DATAERR Data Error [3:3] USB_RXCSRL2_FLUSH Flush FIFO [4:4] USB_RXCSRL2_STALL Send STALL [5:5] USB_RXCSRL2_STALLED Endpoint Stalled [6:6] USB_RXCSRL2_CLRDT Clear Data Toggle [7:7] RXCSRH2 USB Receive Control and Status Endpoint 2 High 0x00000127 8 USB_RXCSRH2_DMAMOD DMA Request Mode [3:3] USB_RXCSRH2_PIDERR PID Error [4:4] USB_RXCSRH2_DMAEN DMA Request Enable [5:5] USB_RXCSRH2_AUTOCL Auto Clear [7:7] RXCSRH2 USB Receive Control and Status Endpoint 2 High USB0_ALT 0x00000127 8 USB_RXCSRH2_DISNYET Disable NYET [4:4] USB_RXCSRH2_ISO Isochronous Transfers [6:6] RXCOUNT2 USB Receive Byte Count Endpoint 2 0x00000128 16 USB_RXCOUNT2_COUNT Receive Packet Count [12:0] TXMAXP3 USB Maximum Transmit Data Endpoint 3 0x00000130 16 USB_TXMAXP3_MAXLOAD Maximum Payload [10:0] TXCSRL3 USB Transmit Control and Status Endpoint 3 Low 0x00000132 8 USB_TXCSRL3_TXRDY Transmit Packet Ready [0:0] USB_TXCSRL3_FIFONE FIFO Not Empty [1:1] USB_TXCSRL3_FLUSH Flush FIFO [3:3] USB_TXCSRL3_STALLED Endpoint Stalled [5:5] USB_TXCSRL3_CLRDT Clear Data Toggle [6:6] TXCSRL3 USB Transmit Control and Status Endpoint 3 Low USB0_ALT 0x00000132 8 USB_TXCSRL3_UNDRN Underrun [2:2] USB_TXCSRL3_STALL Send STALL [4:4] TXCSRH3 USB Transmit Control and Status Endpoint 3 High 0x00000133 8 USB_TXCSRH3_DMAMOD DMA Request Mode [2:2] USB_TXCSRH3_FDT Force Data Toggle [3:3] USB_TXCSRH3_DMAEN DMA Request Enable [4:4] USB_TXCSRH3_MODE Mode [5:5] USB_TXCSRH3_ISO Isochronous Transfers [6:6] USB_TXCSRH3_AUTOSET Auto Set [7:7] RXMAXP3 USB Maximum Receive Data Endpoint 3 0x00000134 16 USB_RXMAXP3_MAXLOAD Maximum Payload [10:0] RXCSRL3 USB Receive Control and Status Endpoint 3 Low 0x00000136 8 USB_RXCSRL3_RXRDY Receive Packet Ready [0:0] USB_RXCSRL3_FULL FIFO Full [1:1] USB_RXCSRL3_OVER Overrun [2:2] USB_RXCSRL3_DATAERR Data Error [3:3] USB_RXCSRL3_FLUSH Flush FIFO [4:4] USB_RXCSRL3_STALL Send STALL [5:5] USB_RXCSRL3_STALLED Endpoint Stalled [6:6] USB_RXCSRL3_CLRDT Clear Data Toggle [7:7] RXCSRH3 USB Receive Control and Status Endpoint 3 High 0x00000137 8 USB_RXCSRH3_DMAMOD DMA Request Mode [3:3] USB_RXCSRH3_PIDERR PID Error [4:4] USB_RXCSRH3_DMAEN DMA Request Enable [5:5] USB_RXCSRH3_AUTOCL Auto Clear [7:7] RXCSRH3 USB Receive Control and Status Endpoint 3 High USB0_ALT 0x00000137 8 USB_RXCSRH3_DISNYET Disable NYET [4:4] USB_RXCSRH3_ISO Isochronous Transfers [6:6] RXCOUNT3 USB Receive Byte Count Endpoint 3 0x00000138 16 USB_RXCOUNT3_COUNT Receive Packet Count [12:0] TXMAXP4 USB Maximum Transmit Data Endpoint 4 0x00000140 16 USB_TXMAXP4_MAXLOAD Maximum Payload [10:0] TXCSRL4 USB Transmit Control and Status Endpoint 4 Low 0x00000142 8 USB_TXCSRL4_TXRDY Transmit Packet Ready [0:0] USB_TXCSRL4_FIFONE FIFO Not Empty [1:1] USB_TXCSRL4_FLUSH Flush FIFO [3:3] USB_TXCSRL4_STALLED Endpoint Stalled [5:5] USB_TXCSRL4_CLRDT Clear Data Toggle [6:6] TXCSRL4 USB Transmit Control and Status Endpoint 4 Low USB0_ALT 0x00000142 8 USB_TXCSRL4_UNDRN Underrun [2:2] USB_TXCSRL4_STALL Send STALL [4:4] TXCSRH4 USB Transmit Control and Status Endpoint 4 High 0x00000143 8 USB_TXCSRH4_DMAMOD DMA Request Mode [2:2] USB_TXCSRH4_FDT Force Data Toggle [3:3] USB_TXCSRH4_DMAEN DMA Request Enable [4:4] USB_TXCSRH4_MODE Mode [5:5] USB_TXCSRH4_ISO Isochronous Transfers [6:6] USB_TXCSRH4_AUTOSET Auto Set [7:7] RXMAXP4 USB Maximum Receive Data Endpoint 4 0x00000144 16 USB_RXMAXP4_MAXLOAD Maximum Payload [10:0] RXCSRL4 USB Receive Control and Status Endpoint 4 Low 0x00000146 8 USB_RXCSRL4_RXRDY Receive Packet Ready [0:0] USB_RXCSRL4_FULL FIFO Full [1:1] USB_RXCSRL4_OVER Overrun [2:2] USB_RXCSRL4_DATAERR Data Error [3:3] USB_RXCSRL4_FLUSH Flush FIFO [4:4] USB_RXCSRL4_STALL Send STALL [5:5] USB_RXCSRL4_STALLED Endpoint Stalled [6:6] USB_RXCSRL4_CLRDT Clear Data Toggle [7:7] RXCSRH4 USB Receive Control and Status Endpoint 4 High 0x00000147 8 USB_RXCSRH4_DMAMOD DMA Request Mode [3:3] USB_RXCSRH4_PIDERR PID Error [4:4] USB_RXCSRH4_DMAEN DMA Request Enable [5:5] USB_RXCSRH4_AUTOCL Auto Clear [7:7] RXCSRH4 USB Receive Control and Status Endpoint 4 High USB0_ALT 0x00000147 8 USB_RXCSRH4_DISNYET Disable NYET [4:4] USB_RXCSRH4_ISO Isochronous Transfers [6:6] RXCOUNT4 USB Receive Byte Count Endpoint 4 0x00000148 16 USB_RXCOUNT4_COUNT Receive Packet Count [12:0] TXMAXP5 USB Maximum Transmit Data Endpoint 5 0x00000150 16 USB_TXMAXP5_MAXLOAD Maximum Payload [10:0] TXCSRL5 USB Transmit Control and Status Endpoint 5 Low 0x00000152 8 USB_TXCSRL5_TXRDY Transmit Packet Ready [0:0] USB_TXCSRL5_FIFONE FIFO Not Empty [1:1] USB_TXCSRL5_FLUSH Flush FIFO [3:3] USB_TXCSRL5_STALLED Endpoint Stalled [5:5] USB_TXCSRL5_CLRDT Clear Data Toggle [6:6] TXCSRL5 USB Transmit Control and Status Endpoint 5 Low USB0_ALT 0x00000152 8 USB_TXCSRL5_UNDRN Underrun [2:2] USB_TXCSRL5_STALL Send STALL [4:4] TXCSRH5 USB Transmit Control and Status Endpoint 5 High 0x00000153 8 USB_TXCSRH5_DMAMOD DMA Request Mode [2:2] USB_TXCSRH5_FDT Force Data Toggle [3:3] USB_TXCSRH5_DMAEN DMA Request Enable [4:4] USB_TXCSRH5_MODE Mode [5:5] USB_TXCSRH5_ISO Isochronous Transfers [6:6] USB_TXCSRH5_AUTOSET Auto Set [7:7] RXMAXP5 USB Maximum Receive Data Endpoint 5 0x00000154 16 USB_RXMAXP5_MAXLOAD Maximum Payload [10:0] RXCSRL5 USB Receive Control and Status Endpoint 5 Low 0x00000156 8 USB_RXCSRL5_RXRDY Receive Packet Ready [0:0] USB_RXCSRL5_FULL FIFO Full [1:1] USB_RXCSRL5_OVER Overrun [2:2] USB_RXCSRL5_DATAERR Data Error [3:3] USB_RXCSRL5_FLUSH Flush FIFO [4:4] USB_RXCSRL5_STALL Send STALL [5:5] USB_RXCSRL5_STALLED Endpoint Stalled [6:6] USB_RXCSRL5_CLRDT Clear Data Toggle [7:7] RXCSRH5 USB Receive Control and Status Endpoint 5 High 0x00000157 8 USB_RXCSRH5_DMAMOD DMA Request Mode [3:3] USB_RXCSRH5_PIDERR PID Error [4:4] USB_RXCSRH5_DMAEN DMA Request Enable [5:5] USB_RXCSRH5_AUTOCL Auto Clear [7:7] RXCSRH5 USB Receive Control and Status Endpoint 5 High USB0_ALT 0x00000157 8 USB_RXCSRH5_DISNYET Disable NYET [4:4] USB_RXCSRH5_ISO Isochronous Transfers [6:6] RXCOUNT5 USB Receive Byte Count Endpoint 5 0x00000158 16 USB_RXCOUNT5_COUNT Receive Packet Count [12:0] TXMAXP6 USB Maximum Transmit Data Endpoint 6 0x00000160 16 USB_TXMAXP6_MAXLOAD Maximum Payload [10:0] TXCSRL6 USB Transmit Control and Status Endpoint 6 Low 0x00000162 8 USB_TXCSRL6_TXRDY Transmit Packet Ready [0:0] USB_TXCSRL6_FIFONE FIFO Not Empty [1:1] USB_TXCSRL6_FLUSH Flush FIFO [3:3] USB_TXCSRL6_STALLED Endpoint Stalled [5:5] USB_TXCSRL6_CLRDT Clear Data Toggle [6:6] TXCSRL6 USB Transmit Control and Status Endpoint 6 Low USB0_ALT 0x00000162 8 USB_TXCSRL6_UNDRN Underrun [2:2] USB_TXCSRL6_STALL Send STALL [4:4] TXCSRH6 USB Transmit Control and Status Endpoint 6 High 0x00000163 8 USB_TXCSRH6_DMAMOD DMA Request Mode [2:2] USB_TXCSRH6_FDT Force Data Toggle [3:3] USB_TXCSRH6_DMAEN DMA Request Enable [4:4] USB_TXCSRH6_MODE Mode [5:5] USB_TXCSRH6_ISO Isochronous Transfers [6:6] USB_TXCSRH6_AUTOSET Auto Set [7:7] RXMAXP6 USB Maximum Receive Data Endpoint 6 0x00000164 16 USB_RXMAXP6_MAXLOAD Maximum Payload [10:0] RXCSRL6 USB Receive Control and Status Endpoint 6 Low 0x00000166 8 USB_RXCSRL6_RXRDY Receive Packet Ready [0:0] USB_RXCSRL6_FULL FIFO Full [1:1] USB_RXCSRL6_OVER Overrun [2:2] USB_RXCSRL6_DATAERR Data Error [3:3] USB_RXCSRL6_FLUSH Flush FIFO [4:4] USB_RXCSRL6_STALL Send STALL [5:5] USB_RXCSRL6_STALLED Endpoint Stalled [6:6] USB_RXCSRL6_CLRDT Clear Data Toggle [7:7] RXCSRH6 USB Receive Control and Status Endpoint 6 High 0x00000167 8 USB_RXCSRH6_DMAMOD DMA Request Mode [3:3] USB_RXCSRH6_PIDERR PID Error [4:4] USB_RXCSRH6_DMAEN DMA Request Enable [5:5] USB_RXCSRH6_AUTOCL Auto Clear [7:7] RXCSRH6 USB Receive Control and Status Endpoint 6 High USB0_ALT 0x00000167 8 USB_RXCSRH6_DISNYET Disable NYET [4:4] USB_RXCSRH6_ISO Isochronous Transfers [6:6] RXCOUNT6 USB Receive Byte Count Endpoint 6 0x00000168 16 USB_RXCOUNT6_COUNT Receive Packet Count [12:0] TXMAXP7 USB Maximum Transmit Data Endpoint 7 0x00000170 16 USB_TXMAXP7_MAXLOAD Maximum Payload [10:0] TXCSRL7 USB Transmit Control and Status Endpoint 7 Low 0x00000172 8 USB_TXCSRL7_TXRDY Transmit Packet Ready [0:0] USB_TXCSRL7_FIFONE FIFO Not Empty [1:1] USB_TXCSRL7_FLUSH Flush FIFO [3:3] USB_TXCSRL7_STALLED Endpoint Stalled [5:5] USB_TXCSRL7_CLRDT Clear Data Toggle [6:6] TXCSRL7 USB Transmit Control and Status Endpoint 7 Low USB0_ALT 0x00000172 8 USB_TXCSRL7_UNDRN Underrun [2:2] USB_TXCSRL7_STALL Send STALL [4:4] TXCSRH7 USB Transmit Control and Status Endpoint 7 High 0x00000173 8 USB_TXCSRH7_DMAMOD DMA Request Mode [2:2] USB_TXCSRH7_FDT Force Data Toggle [3:3] USB_TXCSRH7_DMAEN DMA Request Enable [4:4] USB_TXCSRH7_MODE Mode [5:5] USB_TXCSRH7_ISO Isochronous Transfers [6:6] USB_TXCSRH7_AUTOSET Auto Set [7:7] RXMAXP7 USB Maximum Receive Data Endpoint 7 0x00000174 16 USB_RXMAXP7_MAXLOAD Maximum Payload [10:0] RXCSRL7 USB Receive Control and Status Endpoint 7 Low 0x00000176 8 USB_RXCSRL7_RXRDY Receive Packet Ready [0:0] USB_RXCSRL7_FULL FIFO Full [1:1] USB_RXCSRL7_OVER Overrun [2:2] USB_RXCSRL7_DATAERR Data Error [3:3] USB_RXCSRL7_FLUSH Flush FIFO [4:4] USB_RXCSRL7_STALL Send STALL [5:5] USB_RXCSRL7_STALLED Endpoint Stalled [6:6] USB_RXCSRL7_CLRDT Clear Data Toggle [7:7] RXCSRH7 USB Receive Control and Status Endpoint 7 High 0x00000177 8 USB_RXCSRH7_DMAMOD DMA Request Mode [3:3] USB_RXCSRH7_PIDERR PID Error [4:4] USB_RXCSRH7_DMAEN DMA Request Enable [5:5] USB_RXCSRH7_AUTOCL Auto Clear [7:7] RXCSRH7 USB Receive Control and Status Endpoint 7 High USB0_ALT 0x00000177 8 USB_RXCSRH7_DISNYET Disable NYET [4:4] USB_RXCSRH7_ISO Isochronous Transfers [6:6] RXCOUNT7 USB Receive Byte Count Endpoint 7 0x00000178 16 USB_RXCOUNT7_COUNT Receive Packet Count [12:0] RXDPKTBUFDIS USB Receive Double Packet Buffer Disable 0x00000340 16 USB_RXDPKTBUFDIS_EP1 EP1 RX Double-Packet Buffer Disable [1:1] USB_RXDPKTBUFDIS_EP2 EP2 RX Double-Packet Buffer Disable [2:2] USB_RXDPKTBUFDIS_EP3 EP3 RX Double-Packet Buffer Disable [3:3] USB_RXDPKTBUFDIS_EP4 EP4 RX Double-Packet Buffer Disable [4:4] USB_RXDPKTBUFDIS_EP5 EP5 RX Double-Packet Buffer Disable [5:5] USB_RXDPKTBUFDIS_EP6 EP6 RX Double-Packet Buffer Disable [6:6] USB_RXDPKTBUFDIS_EP7 EP7 RX Double-Packet Buffer Disable [7:7] TXDPKTBUFDIS USB Transmit Double Packet Buffer Disable 0x00000342 16 USB_TXDPKTBUFDIS_EP1 EP1 TX Double-Packet Buffer Disable [1:1] USB_TXDPKTBUFDIS_EP2 EP2 TX Double-Packet Buffer Disable [2:2] USB_TXDPKTBUFDIS_EP3 EP3 TX Double-Packet Buffer Disable [3:3] USB_TXDPKTBUFDIS_EP4 EP4 TX Double-Packet Buffer Disable [4:4] USB_TXDPKTBUFDIS_EP5 EP5 TX Double-Packet Buffer Disable [5:5] USB_TXDPKTBUFDIS_EP6 EP6 TX Double-Packet Buffer Disable [6:6] USB_TXDPKTBUFDIS_EP7 EP7 TX Double-Packet Buffer Disable [7:7] DRRIS USB Device RESUME Raw Interrupt Status 0x00000410 USB_DRRIS_RESUME RESUME Interrupt Status [0:0] DRIM USB Device RESUME Interrupt Mask 0x00000414 USB_DRIM_RESUME RESUME Interrupt Mask [0:0] DRISC USB Device RESUME Interrupt Status and Clear 0x00000418 write-only USB_DRISC_RESUME RESUME Interrupt Status and Clear [0:0] write-only DMASEL USB DMA Select 0x00000450 USB_DMASEL_DMAARX DMA A RX Select [3:0] USB_DMASEL_DMAATX DMA A TX Select [7:4] USB_DMASEL_DMABRX DMA B RX Select [11:8] USB_DMASEL_DMABTX DMA B TX Select [15:12] USB_DMASEL_DMACRX DMA C RX Select [19:16] USB_DMASEL_DMACTX DMA C TX Select [23:20] PP USB Peripheral Properties 0x00000FC0 USB_PP_TYPE Controller Type [3:0] USB_PP_TYPE_0 The first-generation USB controller 0x0 USB_PP_PHY PHY Present [4:4] USB_PP_USB USB Capability [7:6] USB_PP_USB_DEVICE DEVICE 0x1 USB_PP_USB_HOSTDEVICE HOST 0x2 USB_PP_USB_OTG OTG 0x3 USB_PP_ECNT Endpoint Count [15:8] GPIOA_AHB GPIOA_AHB 0x40058000 GPIOA0 GPIOB_AHB GPIOB_AHB 0x40059000 GPIOB1 GPIOC_AHB GPIOC_AHB 0x4005A000 GPIOC2 GPIOD_AHB GPIOD_AHB 0x4005B000 GPIOD3 GPIOE_AHB GPIOE_AHB 0x4005C000 GPIOE4 GPIOF_AHB GPIOF_AHB 0x4005D000 GPIOF30 GPIOG_AHB GPIOG_AHB 0x4005E000 GPIOG31 GPIOH_AHB GPIOH_AHB 0x4005F000 GPIOH32 GPIOJ_AHB GPIOJ_AHB 0x40060000 GPIOJ54 GPIOK GPIOK 0x40061000 GPIOK55 GPIOL GPIOL 0x40062000 GPIOL56 GPIOM GPIOM 0x40063000 GPIOM111 GPION GPION 0x40064000 GPION112 GPIOP GPIOP 0x40065000 GPIOP0116 GPIOP1117 GPIOP2118 GPIOP3119 GPIOP4120 GPIOP5121 GPIOP6122 GPIOP7123 EEPROM Register map for EEPROM peripheral EEPROM EEPROM 0x400AF000 0 0x00001000 registers EESIZE EEPROM Size Information 0x00000000 EEPROM_EESIZE_WORDCNT Number of 32-Bit Words [15:0] EEPROM_EESIZE_BLKCNT Number of 16-Word Blocks [26:16] EEBLOCK EEPROM Current Block 0x00000004 EEPROM_EEBLOCK_BLOCK Current Block [15:0] EEOFFSET EEPROM Current Offset 0x00000008 EEPROM_EEOFFSET_OFFSET Current Address Offset [3:0] EERDWR EEPROM Read-Write 0x00000010 EEPROM_EERDWR_VALUE EEPROM Read or Write Data [31:0] EERDWRINC EEPROM Read-Write with Increment 0x00000014 EEPROM_EERDWRINC_VALUE EEPROM Read or Write Data with Increment [31:0] EEDONE EEPROM Done Status 0x00000018 EEPROM_EEDONE_WORKING EEPROM Working [0:0] EEPROM_EEDONE_WKERASE Working on an Erase [2:2] EEPROM_EEDONE_WKCOPY Working on a Copy [3:3] EEPROM_EEDONE_NOPERM Write Without Permission [4:4] EEPROM_EEDONE_WRBUSY Write Busy [5:5] EEPROM_EEDONE_INVPL Invalid Program Voltage Level [8:8] EESUPP EEPROM Support Control and Status 0x0000001C EEPROM_EESUPP_START Start Erase [0:0] EEPROM_EESUPP_EREQ Erase Required [1:1] EEPROM_EESUPP_ERETRY Erase Must Be Retried [2:2] EEPROM_EESUPP_PRETRY Programming Must Be Retried [3:3] EEUNLOCK EEPROM Unlock 0x00000020 EEPROM_EEUNLOCK_UNLOCK EEPROM Unlock [31:0] EEPROT EEPROM Protection 0x00000030 EEPROM_EEPROT_PROT Protection Control [2:0] EEPROM_EEPROT_PROT_RWNPW This setting is the default. If there is no password, the block is not protected and is readable and writable 0x0 EEPROM_EEPROT_PROT_RWPW If there is a password, the block is readable or writable only when unlocked 0x1 EEPROM_EEPROT_PROT_RONPW If there is no password, the block is readable, not writable 0x2 EEPROM_EEPROT_ACC Access Control [3:3] EEPASS0 EEPROM Password 0x00000034 EEPROM_EEPASS0_PASS Password [31:0] EEPASS1 EEPROM Password 0x00000038 EEPROM_EEPASS1_PASS Password [31:0] EEPASS2 EEPROM Password 0x0000003C EEPROM_EEPASS2_PASS Password [31:0] EEINT EEPROM Interrupt 0x00000040 EEPROM_EEINT_INT Interrupt Enable [0:0] EEHIDE EEPROM Block Hide 0x00000050 EEPROM_EEHIDE_HN Hide Block [31:1] EEDBGME EEPROM Debug Mass Erase 0x00000080 EEPROM_EEDBGME_ME Mass Erase [0:0] EEPROM_EEDBGME_KEY Erase Key [31:16] PP EEPROM Peripheral Properties 0x00000FC0 EEPROM_PP_SIZE EEPROM Size [4:0] I2C4 I2C4 0x400C0000 I2C4109 I2C5 I2C5 0x400C1000 I2C5110 SYSEXC Register map for SYSEXC peripheral SYSEXC SYSEXC 0x400F9000 0 0x00001000 registers SYSEXC106 RIS System Exception Raw Interrupt Status 0x00000000 SYSEXC_RIS_FPIDCRIS Floating-Point Input Denormal Exception Raw Interrupt Status [0:0] SYSEXC_RIS_FPDZCRIS Floating-Point Divide By 0 Exception Raw Interrupt Status [1:1] SYSEXC_RIS_FPIOCRIS Floating-Point Invalid Operation Raw Interrupt Status [2:2] SYSEXC_RIS_FPUFCRIS Floating-Point Underflow Exception Raw Interrupt Status [3:3] SYSEXC_RIS_FPOFCRIS Floating-Point Overflow Exception Raw Interrupt Status [4:4] SYSEXC_RIS_FPIXCRIS Floating-Point Inexact Exception Raw Interrupt Status [5:5] IM System Exception Interrupt Mask 0x00000004 SYSEXC_IM_FPIDCIM Floating-Point Input Denormal Exception Interrupt Mask [0:0] SYSEXC_IM_FPDZCIM Floating-Point Divide By 0 Exception Interrupt Mask [1:1] SYSEXC_IM_FPIOCIM Floating-Point Invalid Operation Interrupt Mask [2:2] SYSEXC_IM_FPUFCIM Floating-Point Underflow Exception Interrupt Mask [3:3] SYSEXC_IM_FPOFCIM Floating-Point Overflow Exception Interrupt Mask [4:4] SYSEXC_IM_FPIXCIM Floating-Point Inexact Exception Interrupt Mask [5:5] MIS System Exception Masked Interrupt Status 0x00000008 SYSEXC_MIS_FPIDCMIS Floating-Point Input Denormal Exception Masked Interrupt Status [0:0] SYSEXC_MIS_FPDZCMIS Floating-Point Divide By 0 Exception Masked Interrupt Status [1:1] SYSEXC_MIS_FPIOCMIS Floating-Point Invalid Operation Masked Interrupt Status [2:2] SYSEXC_MIS_FPUFCMIS Floating-Point Underflow Exception Masked Interrupt Status [3:3] SYSEXC_MIS_FPOFCMIS Floating-Point Overflow Exception Masked Interrupt Status [4:4] SYSEXC_MIS_FPIXCMIS Floating-Point Inexact Exception Masked Interrupt Status [5:5] IC System Exception Interrupt Clear 0x0000000C write-only SYSEXC_IC_FPIDCIC Floating-Point Input Denormal Exception Interrupt Clear [0:0] write-only SYSEXC_IC_FPDZCIC Floating-Point Divide By 0 Exception Interrupt Clear [1:1] write-only SYSEXC_IC_FPIOCIC Floating-Point Invalid Operation Interrupt Clear [2:2] write-only SYSEXC_IC_FPUFCIC Floating-Point Underflow Exception Interrupt Clear [3:3] write-only SYSEXC_IC_FPOFCIC Floating-Point Overflow Exception Interrupt Clear [4:4] write-only SYSEXC_IC_FPIXCIC Floating-Point Inexact Exception Interrupt Clear [5:5] write-only HIB Register map for HIB peripheral HIB HIB 0x400FC000 0 0x00001000 registers HIB43 RTCC Hibernation RTC Counter 0x00000000 HIB_RTCC RTC Counter [31:0] RTCM0 Hibernation RTC Match 0 0x00000004 HIB_RTCM0 RTC Match 0 [31:0] RTCLD Hibernation RTC Load 0x0000000C HIB_RTCLD RTC Load [31:0] CTL Hibernation Control 0x00000010 HIB_CTL_RTCEN RTC Timer Enable [0:0] HIB_CTL_HIBREQ Hibernation Request [1:1] HIB_CTL_RTCWEN RTC Wake-up Enable [3:3] HIB_CTL_PINWEN External WAKE Pin Enable [4:4] HIB_CTL_CLK32EN Clocking Enable [6:6] HIB_CTL_VABORT Power Cut Abort Enable [7:7] HIB_CTL_VDD3ON VDD Powered [8:8] HIB_CTL_BATWKEN Wake on Low Battery [9:9] HIB_CTL_BATCHK Check Battery Status [10:10] HIB_CTL_VBATSEL Select for Low-Battery Comparator [14:13] HIB_CTL_VBATSEL_1_9V 1.9 Volts 0x0 HIB_CTL_VBATSEL_2_1V 2.1 Volts (default) 0x1 HIB_CTL_VBATSEL_2_3V 2.3 Volts 0x2 HIB_CTL_VBATSEL_2_5V 2.5 Volts 0x3 HIB_CTL_OSCBYP Oscillator Bypass [16:16] HIB_CTL_OSCDRV Oscillator Drive Capability [17:17] HIB_CTL_WRC Write Complete/Capable [31:31] IM Hibernation Interrupt Mask 0x00000014 HIB_IM_RTCALT0 RTC Alert 0 Interrupt Mask [0:0] HIB_IM_LOWBAT Low Battery Voltage Interrupt Mask [2:2] HIB_IM_EXTW External Wake-Up Interrupt Mask [3:3] HIB_IM_WC External Write Complete/Capable Interrupt Mask [4:4] RIS Hibernation Raw Interrupt Status 0x00000018 HIB_RIS_RTCALT0 RTC Alert 0 Raw Interrupt Status [0:0] HIB_RIS_LOWBAT Low Battery Voltage Raw Interrupt Status [2:2] HIB_RIS_EXTW External Wake-Up Raw Interrupt Status [3:3] HIB_RIS_WC Write Complete/Capable Raw Interrupt Status [4:4] MIS Hibernation Masked Interrupt Status 0x0000001C HIB_MIS_RTCALT0 RTC Alert 0 Masked Interrupt Status [0:0] HIB_MIS_LOWBAT Low Battery Voltage Masked Interrupt Status [2:2] HIB_MIS_EXTW External Wake-Up Masked Interrupt Status [3:3] HIB_MIS_WC Write Complete/Capable Masked Interrupt Status [4:4] IC Hibernation Interrupt Clear 0x00000020 HIB_IC_RTCALT0 RTC Alert0 Masked Interrupt Clear [0:0] HIB_IC_LOWBAT Low Battery Voltage Masked Interrupt Clear [2:2] HIB_IC_EXTW External Wake-Up Masked Interrupt Clear [3:3] HIB_IC_WC Write Complete/Capable Masked Interrupt Clear [4:4] RTCT Hibernation RTC Trim 0x00000024 HIB_RTCT_TRIM RTC Trim Value [15:0] RTCSS Hibernation RTC Sub Seconds 0x00000028 HIB_RTCSS_RTCSSC RTC Sub Seconds Count [14:0] HIB_RTCSS_RTCSSM RTC Sub Seconds Match [30:16] DATA Hibernation Data 0x00000030 HIB_DATA_RTD Hibernation Module NV Data [31:0] FLASH_CTRL Register map for FLASH_CTRL peripheral FLASH_CTRL FLASH_CTRL 0x400FD000 0 0x00001000 registers 0x1000 0x00001000 registers FLASH_CTRL29 FMA Flash Memory Address 0x00000000 FLASH_FMA_OFFSET Address Offset [17:0] FMD Flash Memory Data 0x00000004 FLASH_FMD_DATA Data Value [31:0] FMC Flash Memory Control 0x00000008 FLASH_FMC_WRITE Write a Word into Flash Memory [0:0] FLASH_FMC_ERASE Erase a Page of Flash Memory [1:1] FLASH_FMC_MERASE Mass Erase Flash Memory [2:2] FLASH_FMC_COMT Commit Register Value [3:3] FLASH_FMC_WRKEY FLASH write key [31:17] FCRIS Flash Controller Raw Interrupt Status 0x0000000C FLASH_FCRIS_ARIS Access Raw Interrupt Status [0:0] FLASH_FCRIS_PRIS Programming Raw Interrupt Status [1:1] FLASH_FCRIS_ERIS EEPROM Raw Interrupt Status [2:2] FLASH_FCRIS_VOLTRIS VOLTSTAT Raw Interrupt Status [9:9] FLASH_FCRIS_INVDRIS Invalid Data Raw Interrupt Status [10:10] FLASH_FCRIS_ERRIS ERVER Raw Interrupt Status [11:11] FLASH_FCRIS_PROGRIS PROGVER Raw Interrupt Status [13:13] FCIM Flash Controller Interrupt Mask 0x00000010 FLASH_FCIM_AMASK Access Interrupt Mask [0:0] FLASH_FCIM_PMASK Programming Interrupt Mask [1:1] FLASH_FCIM_EMASK EEPROM Interrupt Mask [2:2] FLASH_FCIM_VOLTMASK VOLT Interrupt Mask [9:9] FLASH_FCIM_INVDMASK Invalid Data Interrupt Mask [10:10] FLASH_FCIM_ERMASK ERVER Interrupt Mask [11:11] FLASH_FCIM_PROGMASK PROGVER Interrupt Mask [13:13] FCMISC Flash Controller Masked Interrupt Status and Clear 0x00000014 FLASH_FCMISC_AMISC Access Masked Interrupt Status and Clear [0:0] FLASH_FCMISC_PMISC Programming Masked Interrupt Status and Clear [1:1] FLASH_FCMISC_EMISC EEPROM Masked Interrupt Status and Clear [2:2] FLASH_FCMISC_VOLTMISC VOLT Masked Interrupt Status and Clear [9:9] FLASH_FCMISC_INVDMISC Invalid Data Masked Interrupt Status and Clear [10:10] FLASH_FCMISC_ERMISC ERVER Masked Interrupt Status and Clear [11:11] FLASH_FCMISC_PROGMISC PROGVER Masked Interrupt Status and Clear [13:13] FMC2 Flash Memory Control 2 0x00000020 FLASH_FMC2_WRBUF Buffered Flash Memory Write [0:0] FWBVAL Flash Write Buffer Valid 0x00000030 FLASH_FWBVAL_FWB Flash Memory Write Buffer [31:0] FWBN Flash Write Buffer n 0x00000100 FLASH_FWBN_DATA Data [31:0] FSIZE Flash Size 0x00000FC0 FLASH_FSIZE_SIZE Flash Size [15:0] FLASH_FSIZE_SIZE_8KB 8 KB of Flash 0x3 FLASH_FSIZE_SIZE_16KB 16 KB of Flash 0x7 FLASH_FSIZE_SIZE_32KB 32 KB of Flash 0xf FLASH_FSIZE_SIZE_64KB 64 KB of Flash 0x1f FLASH_FSIZE_SIZE_96KB 96 KB of Flash 0x2f FLASH_FSIZE_SIZE_128KB 128 KB of Flash 0x3f FLASH_FSIZE_SIZE_192KB 192 KB of Flash 0x5f FLASH_FSIZE_SIZE_256KB 256 KB of Flash 0x7f SSIZE SRAM Size 0x00000FC4 FLASH_SSIZE_SIZE SRAM Size [15:0] FLASH_SSIZE_SIZE_2KB 2 KB of SRAM 0x7 FLASH_SSIZE_SIZE_4KB 4 KB of SRAM 0xf FLASH_SSIZE_SIZE_6KB 6 KB of SRAM 0x17 FLASH_SSIZE_SIZE_8KB 8 KB of SRAM 0x1f FLASH_SSIZE_SIZE_12KB 12 KB of SRAM 0x2f FLASH_SSIZE_SIZE_16KB 16 KB of SRAM 0x3f FLASH_SSIZE_SIZE_20KB 20 KB of SRAM 0x4f FLASH_SSIZE_SIZE_24KB 24 KB of SRAM 0x5f FLASH_SSIZE_SIZE_32KB 32 KB of SRAM 0x7f ROMSWMAP ROM Software Map 0x00000FCC ROMSWMAP ROM Software Map FLASH_CTRL_ALT 0x00000FCC FLASH_ROMSWMAP_SAFERTOS SafeRTOS Present [0:0] RMCTL ROM Control 0x000010F0 FLASH_RMCTL_BA Boot Alias [0:0] BOOTCFG Boot Configuration 0x000011D0 FLASH_BOOTCFG_DBG0 Debug Control 0 [0:0] FLASH_BOOTCFG_DBG1 Debug Control 1 [1:1] FLASH_BOOTCFG_KEY KEY Select [4:4] FLASH_BOOTCFG_EN Boot GPIO Enable [8:8] FLASH_BOOTCFG_POL Boot GPIO Polarity [9:9] FLASH_BOOTCFG_PIN Boot GPIO Pin [12:10] FLASH_BOOTCFG_PIN_0 Pin 0 0x0 FLASH_BOOTCFG_PIN_1 Pin 1 0x1 FLASH_BOOTCFG_PIN_2 Pin 2 0x2 FLASH_BOOTCFG_PIN_3 Pin 3 0x3 FLASH_BOOTCFG_PIN_4 Pin 4 0x4 FLASH_BOOTCFG_PIN_5 Pin 5 0x5 FLASH_BOOTCFG_PIN_6 Pin 6 0x6 FLASH_BOOTCFG_PIN_7 Pin 7 0x7 FLASH_BOOTCFG_PORT Boot GPIO Port [15:13] FLASH_BOOTCFG_PORT_A Port A 0x0 FLASH_BOOTCFG_PORT_B Port B 0x1 FLASH_BOOTCFG_PORT_C Port C 0x2 FLASH_BOOTCFG_PORT_D Port D 0x3 FLASH_BOOTCFG_PORT_E Port E 0x4 FLASH_BOOTCFG_PORT_F Port F 0x5 FLASH_BOOTCFG_PORT_G Port G 0x6 FLASH_BOOTCFG_PORT_H Port H 0x7 FLASH_BOOTCFG_NW Not Written [31:31] USERREG0 User Register 0 0x000011E0 FLASH_USERREG0_DATA User Data [31:0] USERREG1 User Register 1 0x000011E4 FLASH_USERREG1_DATA User Data [31:0] USERREG2 User Register 2 0x000011E8 FLASH_USERREG2_DATA User Data [31:0] USERREG3 User Register 3 0x000011EC FLASH_USERREG3_DATA User Data [31:0] FMPRE0 Flash Memory Protection Read Enable 0 0x00001200 FMPRE1 Flash Memory Protection Read Enable 1 0x00001204 FMPRE2 Flash Memory Protection Read Enable 2 0x00001208 FMPRE3 Flash Memory Protection Read Enable 3 0x0000120C FMPPE0 Flash Memory Protection Program Enable 0 0x00001400 FMPPE1 Flash Memory Protection Program Enable 1 0x00001404 FMPPE2 Flash Memory Protection Program Enable 2 0x00001408 FMPPE3 Flash Memory Protection Program Enable 3 0x0000140C SYSCTL Register map for SYSCTL peripheral SYSCTL SYSCTL 0x400FE000 0 0x00001000 registers SYSCTL28 DID0 Device Identification 0 0x00000000 SYSCTL_DID0_MIN Minor Revision [7:0] SYSCTL_DID0_MIN_0 Initial device, or a major revision update 0x0 SYSCTL_DID0_MIN_1 First metal layer change 0x1 SYSCTL_DID0_MIN_2 Second metal layer change 0x2 SYSCTL_DID0_MAJ Major Revision [15:8] SYSCTL_DID0_MAJ_REVA Revision A (initial device) 0x0 SYSCTL_DID0_MAJ_REVB Revision B (first base layer revision) 0x1 SYSCTL_DID0_MAJ_REVC Revision C (second base layer revision) 0x2 SYSCTL_DID0_CLASS Device Class [23:16] SYSCTL_DID0_CLASS_BLIZZARD Tiva(TM) C Series Blizzard-class microcontrollers 0x5 SYSCTL_DID0_VER DID0 Version [30:28] SYSCTL_DID0_VER_1 Second version of the DID0 register format 0x1 DID1 Device Identification 1 0x00000004 SYSCTL_DID1_QUAL Qualification Status [1:0] SYSCTL_DID1_QUAL_ES Engineering Sample (unqualified) 0x0 SYSCTL_DID1_QUAL_PP Pilot Production (unqualified) 0x1 SYSCTL_DID1_QUAL_FQ Fully Qualified 0x2 SYSCTL_DID1_ROHS RoHS-Compliance [2:2] SYSCTL_DID1_PKG Package Type [4:3] SYSCTL_DID1_PKG_SOIC SOIC package 0x0 SYSCTL_DID1_PKG_QFP LQFP package 0x1 SYSCTL_DID1_PKG_BGA BGA package 0x2 SYSCTL_DID1_TEMP Temperature Range [7:5] SYSCTL_DID1_TEMP_C Commercial temperature range (0C to 70C) 0x0 SYSCTL_DID1_TEMP_I Industrial temperature range (-40C to 85C) 0x1 SYSCTL_DID1_TEMP_E Extended temperature range (-40C to 105C) 0x2 SYSCTL_DID1_PINCNT Package Pin Count [15:13] SYSCTL_DID1_PINCNT_28 28-pin package 0x0 SYSCTL_DID1_PINCNT_48 48-pin package 0x1 SYSCTL_DID1_PINCNT_100 100-pin package 0x2 SYSCTL_DID1_PINCNT_64 64-pin package 0x3 SYSCTL_DID1_PINCNT_144 144-pin package 0x4 SYSCTL_DID1_PINCNT_157 157-pin package 0x5 SYSCTL_DID1_PRTNO Part Number [23:16] SYSCTL_DID1_FAM Family [27:24] SYSCTL_DID1_VER DID1 Version [31:28] DC0 Device Capabilities 0 0x00000008 SYSCTL_DC0_FLASHSZ Flash Size [15:0] SYSCTL_DC0_FLASHSZ_8KB 8 KB of Flash 0x3 SYSCTL_DC0_FLASHSZ_16KB 16 KB of Flash 0x7 SYSCTL_DC0_FLASHSZ_32KB 32 KB of Flash 0xf SYSCTL_DC0_FLASHSZ_64KB 64 KB of Flash 0x1f SYSCTL_DC0_FLASHSZ_96KB 96 KB of Flash 0x2f SYSCTL_DC0_FLASHSZ_128K 128 KB of Flash 0x3f SYSCTL_DC0_FLASHSZ_192K 192 KB of Flash 0x5f SYSCTL_DC0_FLASHSZ_256K 256 KB of Flash 0x7f SYSCTL_DC0_SRAMSZ SRAM Size [31:16] SYSCTL_DC0_SRAMSZ_2KB 2 KB of SRAM 0x7 SYSCTL_DC0_SRAMSZ_4KB 4 KB of SRAM 0xf SYSCTL_DC0_SRAMSZ_6KB 6 KB of SRAM 0x17 SYSCTL_DC0_SRAMSZ_8KB 8 KB of SRAM 0x1f SYSCTL_DC0_SRAMSZ_12KB 12 KB of SRAM 0x2f SYSCTL_DC0_SRAMSZ_16KB 16 KB of SRAM 0x3f SYSCTL_DC0_SRAMSZ_20KB 20 KB of SRAM 0x4f SYSCTL_DC0_SRAMSZ_24KB 24 KB of SRAM 0x5f SYSCTL_DC0_SRAMSZ_32KB 32 KB of SRAM 0x7f DC1 Device Capabilities 1 0x00000010 SYSCTL_DC1_JTAG JTAG Present [0:0] SYSCTL_DC1_SWD SWD Present [1:1] SYSCTL_DC1_SWO SWO Trace Port Present [2:2] SYSCTL_DC1_WDT0 Watchdog Timer 0 Present [3:3] SYSCTL_DC1_PLL PLL Present [4:4] SYSCTL_DC1_TEMP Temp Sensor Present [5:5] SYSCTL_DC1_HIB Hibernation Module Present [6:6] SYSCTL_DC1_MPU MPU Present [7:7] SYSCTL_DC1_ADC0SPD Max ADC0 Speed [9:8] SYSCTL_DC1_ADC0SPD_125K 125K samples/second 0x0 SYSCTL_DC1_ADC0SPD_250K 250K samples/second 0x1 SYSCTL_DC1_ADC0SPD_500K 500K samples/second 0x2 SYSCTL_DC1_ADC0SPD_1M 1M samples/second 0x3 SYSCTL_DC1_ADC1SPD Max ADC1 Speed [11:10] SYSCTL_DC1_ADC1SPD_125K 125K samples/second 0x0 SYSCTL_DC1_ADC1SPD_250K 250K samples/second 0x1 SYSCTL_DC1_ADC1SPD_500K 500K samples/second 0x2 SYSCTL_DC1_ADC1SPD_1M 1M samples/second 0x3 SYSCTL_DC1_MINSYSDIV System Clock Divider [15:12] SYSCTL_DC1_MINSYSDIV_100 Divide VCO (400MHZ) by 5 minimum 0x1 SYSCTL_DC1_MINSYSDIV_66 Divide VCO (400MHZ) by 2*2 + 2 = 6 minimum 0x2 SYSCTL_DC1_MINSYSDIV_50 Specifies a 50-MHz CPU clock with a PLL divider of 4 0x3 SYSCTL_DC1_MINSYSDIV_40 Specifies a 40-MHz CPU clock with a PLL divider of 5 0x4 SYSCTL_DC1_MINSYSDIV_25 Specifies a 25-MHz clock with a PLL divider of 8 0x7 SYSCTL_DC1_MINSYSDIV_20 Specifies a 20-MHz clock with a PLL divider of 10 0x9 SYSCTL_DC1_ADC0 ADC Module 0 Present [16:16] SYSCTL_DC1_ADC1 ADC Module 1 Present [17:17] SYSCTL_DC1_PWM0 PWM Module 0 Present [20:20] SYSCTL_DC1_PWM1 PWM Module 1 Present [21:21] SYSCTL_DC1_CAN0 CAN Module 0 Present [24:24] SYSCTL_DC1_CAN1 CAN Module 1 Present [25:25] SYSCTL_DC1_WDT1 Watchdog Timer1 Present [28:28] DC2 Device Capabilities 2 0x00000014 SYSCTL_DC2_UART0 UART Module 0 Present [0:0] SYSCTL_DC2_UART1 UART Module 1 Present [1:1] SYSCTL_DC2_UART2 UART Module 2 Present [2:2] SYSCTL_DC2_SSI0 SSI Module 0 Present [4:4] SYSCTL_DC2_SSI1 SSI Module 1 Present [5:5] SYSCTL_DC2_QEI0 QEI Module 0 Present [8:8] SYSCTL_DC2_QEI1 QEI Module 1 Present [9:9] SYSCTL_DC2_I2C0 I2C Module 0 Present [12:12] SYSCTL_DC2_I2C0HS I2C Module 0 Speed [13:13] SYSCTL_DC2_I2C1 I2C Module 1 Present [14:14] SYSCTL_DC2_I2C1HS I2C Module 1 Speed [15:15] SYSCTL_DC2_TIMER0 Timer Module 0 Present [16:16] SYSCTL_DC2_TIMER1 Timer Module 1 Present [17:17] SYSCTL_DC2_TIMER2 Timer Module 2 Present [18:18] SYSCTL_DC2_TIMER3 Timer Module 3 Present [19:19] SYSCTL_DC2_COMP0 Analog Comparator 0 Present [24:24] SYSCTL_DC2_COMP1 Analog Comparator 1 Present [25:25] SYSCTL_DC2_COMP2 Analog Comparator 2 Present [26:26] SYSCTL_DC2_I2S0 I2S Module 0 Present [28:28] SYSCTL_DC2_EPI0 EPI Module 0 Present [30:30] DC3 Device Capabilities 3 0x00000018 SYSCTL_DC3_PWM0 PWM0 Pin Present [0:0] SYSCTL_DC3_PWM1 PWM1 Pin Present [1:1] SYSCTL_DC3_PWM2 PWM2 Pin Present [2:2] SYSCTL_DC3_PWM3 PWM3 Pin Present [3:3] SYSCTL_DC3_PWM4 PWM4 Pin Present [4:4] SYSCTL_DC3_PWM5 PWM5 Pin Present [5:5] SYSCTL_DC3_C0MINUS C0- Pin Present [6:6] SYSCTL_DC3_C0PLUS C0+ Pin Present [7:7] SYSCTL_DC3_C0O C0o Pin Present [8:8] SYSCTL_DC3_C1MINUS C1- Pin Present [9:9] SYSCTL_DC3_C1PLUS C1+ Pin Present [10:10] SYSCTL_DC3_C1O C1o Pin Present [11:11] SYSCTL_DC3_C2MINUS C2- Pin Present [12:12] SYSCTL_DC3_C2PLUS C2+ Pin Present [13:13] SYSCTL_DC3_C2O C2o Pin Present [14:14] SYSCTL_DC3_PWMFAULT PWM Fault Pin Present [15:15] SYSCTL_DC3_ADC0AIN0 ADC Module 0 AIN0 Pin Present [16:16] SYSCTL_DC3_ADC0AIN1 ADC Module 0 AIN1 Pin Present [17:17] SYSCTL_DC3_ADC0AIN2 ADC Module 0 AIN2 Pin Present [18:18] SYSCTL_DC3_ADC0AIN3 ADC Module 0 AIN3 Pin Present [19:19] SYSCTL_DC3_ADC0AIN4 ADC Module 0 AIN4 Pin Present [20:20] SYSCTL_DC3_ADC0AIN5 ADC Module 0 AIN5 Pin Present [21:21] SYSCTL_DC3_ADC0AIN6 ADC Module 0 AIN6 Pin Present [22:22] SYSCTL_DC3_ADC0AIN7 ADC Module 0 AIN7 Pin Present [23:23] SYSCTL_DC3_CCP0 CCP0 Pin Present [24:24] SYSCTL_DC3_CCP1 CCP1 Pin Present [25:25] SYSCTL_DC3_CCP2 CCP2 Pin Present [26:26] SYSCTL_DC3_CCP3 CCP3 Pin Present [27:27] SYSCTL_DC3_CCP4 CCP4 Pin Present [28:28] SYSCTL_DC3_CCP5 CCP5 Pin Present [29:29] SYSCTL_DC3_32KHZ 32KHz Input Clock Available [31:31] DC4 Device Capabilities 4 0x0000001C SYSCTL_DC4_GPIOA GPIO Port A Present [0:0] SYSCTL_DC4_GPIOB GPIO Port B Present [1:1] SYSCTL_DC4_GPIOC GPIO Port C Present [2:2] SYSCTL_DC4_GPIOD GPIO Port D Present [3:3] SYSCTL_DC4_GPIOE GPIO Port E Present [4:4] SYSCTL_DC4_GPIOF GPIO Port F Present [5:5] SYSCTL_DC4_GPIOG GPIO Port G Present [6:6] SYSCTL_DC4_GPIOH GPIO Port H Present [7:7] SYSCTL_DC4_GPIOJ GPIO Port J Present [8:8] SYSCTL_DC4_ROM Internal Code ROM Present [12:12] SYSCTL_DC4_UDMA Micro-DMA Module Present [13:13] SYSCTL_DC4_CCP6 CCP6 Pin Present [14:14] SYSCTL_DC4_CCP7 CCP7 Pin Present [15:15] SYSCTL_DC4_PICAL PIOSC Calibrate [18:18] SYSCTL_DC4_E1588 1588 Capable [24:24] SYSCTL_DC4_EMAC0 Ethernet MAC Layer 0 Present [28:28] SYSCTL_DC4_EPHY0 Ethernet PHY Layer 0 Present [30:30] DC5 Device Capabilities 5 0x00000020 SYSCTL_DC5_PWM0 PWM0 Pin Present [0:0] SYSCTL_DC5_PWM1 PWM1 Pin Present [1:1] SYSCTL_DC5_PWM2 PWM2 Pin Present [2:2] SYSCTL_DC5_PWM3 PWM3 Pin Present [3:3] SYSCTL_DC5_PWM4 PWM4 Pin Present [4:4] SYSCTL_DC5_PWM5 PWM5 Pin Present [5:5] SYSCTL_DC5_PWM6 PWM6 Pin Present [6:6] SYSCTL_DC5_PWM7 PWM7 Pin Present [7:7] SYSCTL_DC5_PWMESYNC PWM Extended SYNC Active [20:20] SYSCTL_DC5_PWMEFLT PWM Extended Fault Active [21:21] SYSCTL_DC5_PWMFAULT0 PWM Fault 0 Pin Present [24:24] SYSCTL_DC5_PWMFAULT1 PWM Fault 1 Pin Present [25:25] SYSCTL_DC5_PWMFAULT2 PWM Fault 2 Pin Present [26:26] SYSCTL_DC5_PWMFAULT3 PWM Fault 3 Pin Present [27:27] DC6 Device Capabilities 6 0x00000024 SYSCTL_DC6_USB0 USB Module 0 Present [1:0] SYSCTL_DC6_USB0_DEV USB0 is Device Only 0x1 SYSCTL_DC6_USB0_HOSTDEV USB is Device or Host 0x2 SYSCTL_DC6_USB0_OTG USB0 is OTG 0x3 SYSCTL_DC6_USB0PHY USB Module 0 PHY Present [4:4] DC7 Device Capabilities 7 0x00000028 SYSCTL_DC7_DMACH0 USB_EP1_RX / UART2_RX [0:0] SYSCTL_DC7_DMACH1 USB_EP1_TX / UART2_TX [1:1] SYSCTL_DC7_DMACH2 USB_EP2_RX / Timer3A [2:2] SYSCTL_DC7_DMACH3 USB_EP2_TX / Timer3B [3:3] SYSCTL_DC7_DMACH4 USB_EP3_RX / Timer2A [4:4] SYSCTL_DC7_DMACH5 USB_EP3_TX / Timer2B [5:5] SYSCTL_DC7_DMACH6 ETH_RX / Timer2A [6:6] SYSCTL_DC7_DMACH7 ETH_TX / Timer2B [7:7] SYSCTL_DC7_DMACH8 UART0_RX / UART1_RX [8:8] SYSCTL_DC7_DMACH9 UART0_TX / UART1_TX [9:9] SYSCTL_DC7_DMACH10 SSI0_RX / SSI1_RX [10:10] SYSCTL_DC7_DMACH11 SSI0_TX / SSI1_TX [11:11] SYSCTL_DC7_DMACH12 CAN0_RX / UART2_RX [12:12] SYSCTL_DC7_DMACH13 CAN0_TX / UART2_TX [13:13] SYSCTL_DC7_DMACH14 ADC0_SS0 / Timer2A [14:14] SYSCTL_DC7_DMACH15 ADC0_SS1 / Timer2B [15:15] SYSCTL_DC7_DMACH16 ADC0_SS2 [16:16] SYSCTL_DC7_DMACH17 ADC0_SS3 [17:17] SYSCTL_DC7_DMACH18 Timer0A / Timer1A [18:18] SYSCTL_DC7_DMACH19 Timer0B / Timer1B [19:19] SYSCTL_DC7_DMACH20 Timer1A / EPI0_NBRFIFO [20:20] SYSCTL_DC7_DMACH21 Timer1B / EPI0_WFIFO [21:21] SYSCTL_DC7_DMACH22 UART1_RX / CAN2_RX [22:22] SYSCTL_DC7_DMACH23 UART1_TX / CAN2_TX [23:23] SYSCTL_DC7_DMACH24 SSI1_RX / ADC1_SS0 [24:24] SYSCTL_DC7_DMACH25 SSI1_TX / ADC1_SS1 [25:25] SYSCTL_DC7_DMACH26 CAN1_RX / ADC1_SS2 [26:26] SYSCTL_DC7_DMACH27 CAN1_TX / ADC1_SS3 [27:27] SYSCTL_DC7_DMACH28 I2S0_RX / CAN1_RX [28:28] SYSCTL_DC7_DMACH29 I2S0_TX / CAN1_TX [29:29] SYSCTL_DC7_DMACH30 SW [30:30] DC8 Device Capabilities 8 ADC Channels 0x0000002C SYSCTL_DC8_ADC0AIN0 ADC Module 0 AIN0 Pin Present [0:0] SYSCTL_DC8_ADC0AIN1 ADC Module 0 AIN1 Pin Present [1:1] SYSCTL_DC8_ADC0AIN2 ADC Module 0 AIN2 Pin Present [2:2] SYSCTL_DC8_ADC0AIN3 ADC Module 0 AIN3 Pin Present [3:3] SYSCTL_DC8_ADC0AIN4 ADC Module 0 AIN4 Pin Present [4:4] SYSCTL_DC8_ADC0AIN5 ADC Module 0 AIN5 Pin Present [5:5] SYSCTL_DC8_ADC0AIN6 ADC Module 0 AIN6 Pin Present [6:6] SYSCTL_DC8_ADC0AIN7 ADC Module 0 AIN7 Pin Present [7:7] SYSCTL_DC8_ADC0AIN8 ADC Module 0 AIN8 Pin Present [8:8] SYSCTL_DC8_ADC0AIN9 ADC Module 0 AIN9 Pin Present [9:9] SYSCTL_DC8_ADC0AIN10 ADC Module 0 AIN10 Pin Present [10:10] SYSCTL_DC8_ADC0AIN11 ADC Module 0 AIN11 Pin Present [11:11] SYSCTL_DC8_ADC0AIN12 ADC Module 0 AIN12 Pin Present [12:12] SYSCTL_DC8_ADC0AIN13 ADC Module 0 AIN13 Pin Present [13:13] SYSCTL_DC8_ADC0AIN14 ADC Module 0 AIN14 Pin Present [14:14] SYSCTL_DC8_ADC0AIN15 ADC Module 0 AIN15 Pin Present [15:15] SYSCTL_DC8_ADC1AIN0 ADC Module 1 AIN0 Pin Present [16:16] SYSCTL_DC8_ADC1AIN1 ADC Module 1 AIN1 Pin Present [17:17] SYSCTL_DC8_ADC1AIN2 ADC Module 1 AIN2 Pin Present [18:18] SYSCTL_DC8_ADC1AIN3 ADC Module 1 AIN3 Pin Present [19:19] SYSCTL_DC8_ADC1AIN4 ADC Module 1 AIN4 Pin Present [20:20] SYSCTL_DC8_ADC1AIN5 ADC Module 1 AIN5 Pin Present [21:21] SYSCTL_DC8_ADC1AIN6 ADC Module 1 AIN6 Pin Present [22:22] SYSCTL_DC8_ADC1AIN7 ADC Module 1 AIN7 Pin Present [23:23] SYSCTL_DC8_ADC1AIN8 ADC Module 1 AIN8 Pin Present [24:24] SYSCTL_DC8_ADC1AIN9 ADC Module 1 AIN9 Pin Present [25:25] SYSCTL_DC8_ADC1AIN10 ADC Module 1 AIN10 Pin Present [26:26] SYSCTL_DC8_ADC1AIN11 ADC Module 1 AIN11 Pin Present [27:27] SYSCTL_DC8_ADC1AIN12 ADC Module 1 AIN12 Pin Present [28:28] SYSCTL_DC8_ADC1AIN13 ADC Module 1 AIN13 Pin Present [29:29] SYSCTL_DC8_ADC1AIN14 ADC Module 1 AIN14 Pin Present [30:30] SYSCTL_DC8_ADC1AIN15 ADC Module 1 AIN15 Pin Present [31:31] PBORCTL Brown-Out Reset Control 0x00000030 SYSCTL_PBORCTL_BOR1 VDD under BOR1 Event Action [1:1] SYSCTL_PBORCTL_BOR0 VDD under BOR0 Event Action [2:2] SRCR0 Software Reset Control 0 0x00000040 SYSCTL_SRCR0_WDT0 WDT0 Reset Control [3:3] SYSCTL_SRCR0_HIB HIB Reset Control [6:6] SYSCTL_SRCR0_ADC0 ADC0 Reset Control [16:16] SYSCTL_SRCR0_ADC1 ADC1 Reset Control [17:17] SYSCTL_SRCR0_CAN0 CAN0 Reset Control [24:24] SYSCTL_SRCR0_WDT1 WDT1 Reset Control [28:28] SRCR1 Software Reset Control 1 0x00000044 SYSCTL_SRCR1_UART0 UART0 Reset Control [0:0] SYSCTL_SRCR1_UART1 UART1 Reset Control [1:1] SYSCTL_SRCR1_UART2 UART2 Reset Control [2:2] SYSCTL_SRCR1_SSI0 SSI0 Reset Control [4:4] SYSCTL_SRCR1_SSI1 SSI1 Reset Control [5:5] SYSCTL_SRCR1_I2C0 I2C0 Reset Control [12:12] SYSCTL_SRCR1_I2C1 I2C1 Reset Control [14:14] SYSCTL_SRCR1_TIMER0 Timer 0 Reset Control [16:16] SYSCTL_SRCR1_TIMER1 Timer 1 Reset Control [17:17] SYSCTL_SRCR1_TIMER2 Timer 2 Reset Control [18:18] SYSCTL_SRCR1_TIMER3 Timer 3 Reset Control [19:19] SYSCTL_SRCR1_COMP0 Analog Comp 0 Reset Control [24:24] SYSCTL_SRCR1_COMP1 Analog Comp 1 Reset Control [25:25] SYSCTL_SRCR1_COMP2 Analog Comp 2 Reset Control [26:26] SRCR2 Software Reset Control 2 0x00000048 SYSCTL_SRCR2_GPIOA Port A Reset Control [0:0] SYSCTL_SRCR2_GPIOB Port B Reset Control [1:1] SYSCTL_SRCR2_GPIOC Port C Reset Control [2:2] SYSCTL_SRCR2_GPIOD Port D Reset Control [3:3] SYSCTL_SRCR2_GPIOE Port E Reset Control [4:4] SYSCTL_SRCR2_GPIOF Port F Reset Control [5:5] SYSCTL_SRCR2_GPIOG Port G Reset Control [6:6] SYSCTL_SRCR2_GPIOH Port H Reset Control [7:7] SYSCTL_SRCR2_GPIOJ Port J Reset Control [8:8] SYSCTL_SRCR2_UDMA Micro-DMA Reset Control [13:13] SYSCTL_SRCR2_USB0 USB0 Reset Control [16:16] RIS Raw Interrupt Status 0x00000050 SYSCTL_RIS_MOFRIS Main Oscillator Fault Raw Interrupt Status [3:3] SYSCTL_RIS_PLLLRIS PLL Lock Raw Interrupt Status [6:6] SYSCTL_RIS_USBPLLLRIS USB PLL Lock Raw Interrupt Status [7:7] SYSCTL_RIS_MOSCPUPRIS MOSC Power Up Raw Interrupt Status [8:8] SYSCTL_RIS_VDDARIS VDDA Power OK Event Raw Interrupt Status [10:10] IMC Interrupt Mask Control 0x00000054 SYSCTL_IMC_MOFIM Main Oscillator Fault Interrupt Mask [3:3] SYSCTL_IMC_PLLLIM PLL Lock Interrupt Mask [6:6] SYSCTL_IMC_USBPLLLIM USB PLL Lock Interrupt Mask [7:7] SYSCTL_IMC_MOSCPUPIM MOSC Power Up Interrupt Mask [8:8] SYSCTL_IMC_VDDAIM VDDA Power OK Interrupt Mask [10:10] MISC Masked Interrupt Status and Clear 0x00000058 SYSCTL_MISC_MOFMIS Main Oscillator Fault Masked Interrupt Status [3:3] SYSCTL_MISC_PLLLMIS PLL Lock Masked Interrupt Status [6:6] SYSCTL_MISC_USBPLLLMIS USB PLL Lock Masked Interrupt Status [7:7] SYSCTL_MISC_MOSCPUPMIS MOSC Power Up Masked Interrupt Status [8:8] SYSCTL_MISC_VDDAMIS VDDA Power OK Masked Interrupt Status [10:10] RESC Reset Cause 0x0000005C SYSCTL_RESC_EXT External Reset [0:0] SYSCTL_RESC_POR Power-On Reset [1:1] SYSCTL_RESC_BOR Brown-Out Reset [2:2] SYSCTL_RESC_WDT0 Watchdog Timer 0 Reset [3:3] SYSCTL_RESC_SW Software Reset [4:4] SYSCTL_RESC_WDT1 Watchdog Timer 1 Reset [5:5] SYSCTL_RESC_MOSCFAIL MOSC Failure Reset [16:16] RCC Run-Mode Clock Configuration 0x00000060 SYSCTL_RCC_MOSCDIS Main Oscillator Disable [0:0] SYSCTL_RCC_OSCSRC Oscillator Source [5:4] SYSCTL_RCC_OSCSRC_MAIN MOSC 0x0 SYSCTL_RCC_OSCSRC_INT IOSC 0x1 SYSCTL_RCC_OSCSRC_INT4 IOSC/4 0x2 SYSCTL_RCC_OSCSRC_30 30 kHz 0x3 SYSCTL_RCC_XTAL Crystal Value [10:6] SYSCTL_RCC_XTAL_4MHZ 4 MHz 0x6 SYSCTL_RCC_XTAL_4_09MHZ 4.096 MHz 0x7 SYSCTL_RCC_XTAL_4_91MHZ 4.9152 MHz 0x8 SYSCTL_RCC_XTAL_5MHZ 5 MHz 0x9 SYSCTL_RCC_XTAL_5_12MHZ 5.12 MHz 0xa SYSCTL_RCC_XTAL_6MHZ 6 MHz 0xb SYSCTL_RCC_XTAL_6_14MHZ 6.144 MHz 0xc SYSCTL_RCC_XTAL_7_37MHZ 7.3728 MHz 0xd SYSCTL_RCC_XTAL_8MHZ 8 MHz 0xe SYSCTL_RCC_XTAL_8_19MHZ 8.192 MHz 0xf SYSCTL_RCC_XTAL_10MHZ 10 MHz 0x10 SYSCTL_RCC_XTAL_12MHZ 12 MHz 0x11 SYSCTL_RCC_XTAL_12_2MHZ 12.288 MHz 0x12 SYSCTL_RCC_XTAL_13_5MHZ 13.56 MHz 0x13 SYSCTL_RCC_XTAL_14_3MHZ 14.31818 MHz 0x14 SYSCTL_RCC_XTAL_16MHZ 16 MHz 0x15 SYSCTL_RCC_XTAL_16_3MHZ 16.384 MHz 0x16 SYSCTL_RCC_XTAL_18MHZ 18.0 MHz 0x17 SYSCTL_RCC_XTAL_20MHZ 20.0 MHz 0x18 SYSCTL_RCC_XTAL_24MHZ 24.0 MHz 0x19 SYSCTL_RCC_XTAL_25MHZ 25.0 MHz 0x1a SYSCTL_RCC_BYPASS PLL Bypass [11:11] SYSCTL_RCC_PWRDN PLL Power Down [13:13] SYSCTL_RCC_USESYSDIV Enable System Clock Divider [22:22] SYSCTL_RCC_SYSDIV System Clock Divisor [26:23] SYSCTL_RCC_ACG Auto Clock Gating [27:27] GPIOHBCTL GPIO High-Performance Bus Control 0x0000006C SYSCTL_GPIOHBCTL_PORTA Port A Advanced High-Performance Bus [0:0] SYSCTL_GPIOHBCTL_PORTB Port B Advanced High-Performance Bus [1:1] SYSCTL_GPIOHBCTL_PORTC Port C Advanced High-Performance Bus [2:2] SYSCTL_GPIOHBCTL_PORTD Port D Advanced High-Performance Bus [3:3] SYSCTL_GPIOHBCTL_PORTE Port E Advanced High-Performance Bus [4:4] SYSCTL_GPIOHBCTL_PORTF Port F Advanced High-Performance Bus [5:5] SYSCTL_GPIOHBCTL_PORTG Port G Advanced High-Performance Bus [6:6] SYSCTL_GPIOHBCTL_PORTH Port H Advanced High-Performance Bus [7:7] SYSCTL_GPIOHBCTL_PORTJ Port J Advanced High-Performance Bus [8:8] RCC2 Run-Mode Clock Configuration 2 0x00000070 SYSCTL_RCC2_OSCSRC2 Oscillator Source 2 [6:4] SYSCTL_RCC2_OSCSRC2_MO MOSC 0x0 SYSCTL_RCC2_OSCSRC2_IO PIOSC 0x1 SYSCTL_RCC2_OSCSRC2_IO4 PIOSC/4 0x2 SYSCTL_RCC2_OSCSRC2_30 30 kHz 0x3 SYSCTL_RCC2_OSCSRC2_32 32.768 kHz 0x7 SYSCTL_RCC2_BYPASS2 PLL Bypass 2 [11:11] SYSCTL_RCC2_PWRDN2 Power-Down PLL 2 [13:13] SYSCTL_RCC2_USBPWRDN Power-Down USB PLL [14:14] SYSCTL_RCC2_SYSDIV2LSB Additional LSB for SYSDIV2 [22:22] SYSCTL_RCC2_SYSDIV2 System Clock Divisor 2 [28:23] SYSCTL_RCC2_DIV400 Divide PLL as 400 MHz vs. 200 MHz [30:30] SYSCTL_RCC2_USERCC2 Use RCC2 [31:31] MOSCCTL Main Oscillator Control 0x0000007C SYSCTL_MOSCCTL_CVAL Clock Validation for MOSC [0:0] SYSCTL_MOSCCTL_MOSCIM MOSC Failure Action [1:1] SYSCTL_MOSCCTL_NOXTAL No Crystal Connected [2:2] RCGC0 Run Mode Clock Gating Control Register 0 0x00000100 SYSCTL_RCGC0_WDT0 WDT0 Clock Gating Control [3:3] SYSCTL_RCGC0_HIB HIB Clock Gating Control [6:6] SYSCTL_RCGC0_ADC0SPD ADC0 Sample Speed [9:8] SYSCTL_RCGC0_ADC0SPD_125K 125K samples/second 0x0 SYSCTL_RCGC0_ADC0SPD_250K 250K samples/second 0x1 SYSCTL_RCGC0_ADC0SPD_500K 500K samples/second 0x2 SYSCTL_RCGC0_ADC0SPD_1M 1M samples/second 0x3 SYSCTL_RCGC0_ADC1SPD ADC1 Sample Speed [11:10] SYSCTL_RCGC0_ADC1SPD_125K 125K samples/second 0x0 SYSCTL_RCGC0_ADC1SPD_250K 250K samples/second 0x1 SYSCTL_RCGC0_ADC1SPD_500K 500K samples/second 0x2 SYSCTL_RCGC0_ADC1SPD_1M 1M samples/second 0x3 SYSCTL_RCGC0_ADC0 ADC0 Clock Gating Control [16:16] SYSCTL_RCGC0_ADC1 ADC1 Clock Gating Control [17:17] SYSCTL_RCGC0_CAN0 CAN0 Clock Gating Control [24:24] SYSCTL_RCGC0_WDT1 WDT1 Clock Gating Control [28:28] RCGC1 Run Mode Clock Gating Control Register 1 0x00000104 SYSCTL_RCGC1_UART0 UART0 Clock Gating Control [0:0] SYSCTL_RCGC1_UART1 UART1 Clock Gating Control [1:1] SYSCTL_RCGC1_UART2 UART2 Clock Gating Control [2:2] SYSCTL_RCGC1_SSI0 SSI0 Clock Gating Control [4:4] SYSCTL_RCGC1_SSI1 SSI1 Clock Gating Control [5:5] SYSCTL_RCGC1_I2C0 I2C0 Clock Gating Control [12:12] SYSCTL_RCGC1_I2C1 I2C1 Clock Gating Control [14:14] SYSCTL_RCGC1_TIMER0 Timer 0 Clock Gating Control [16:16] SYSCTL_RCGC1_TIMER1 Timer 1 Clock Gating Control [17:17] SYSCTL_RCGC1_TIMER2 Timer 2 Clock Gating Control [18:18] SYSCTL_RCGC1_TIMER3 Timer 3 Clock Gating Control [19:19] SYSCTL_RCGC1_COMP0 Analog Comparator 0 Clock Gating [24:24] SYSCTL_RCGC1_COMP1 Analog Comparator 1 Clock Gating [25:25] SYSCTL_RCGC1_COMP2 Analog Comparator 2 Clock Gating [26:26] RCGC2 Run Mode Clock Gating Control Register 2 0x00000108 SYSCTL_RCGC2_GPIOA Port A Clock Gating Control [0:0] SYSCTL_RCGC2_GPIOB Port B Clock Gating Control [1:1] SYSCTL_RCGC2_GPIOC Port C Clock Gating Control [2:2] SYSCTL_RCGC2_GPIOD Port D Clock Gating Control [3:3] SYSCTL_RCGC2_GPIOE Port E Clock Gating Control [4:4] SYSCTL_RCGC2_GPIOF Port F Clock Gating Control [5:5] SYSCTL_RCGC2_GPIOG Port G Clock Gating Control [6:6] SYSCTL_RCGC2_GPIOH Port H Clock Gating Control [7:7] SYSCTL_RCGC2_GPIOJ Port J Clock Gating Control [8:8] SYSCTL_RCGC2_UDMA Micro-DMA Clock Gating Control [13:13] SYSCTL_RCGC2_USB0 USB0 Clock Gating Control [16:16] SCGC0 Sleep Mode Clock Gating Control Register 0 0x00000110 SYSCTL_SCGC0_WDT0 WDT0 Clock Gating Control [3:3] SYSCTL_SCGC0_HIB HIB Clock Gating Control [6:6] SYSCTL_SCGC0_ADC0 ADC0 Clock Gating Control [16:16] SYSCTL_SCGC0_ADC1 ADC1 Clock Gating Control [17:17] SYSCTL_SCGC0_CAN0 CAN0 Clock Gating Control [24:24] SYSCTL_SCGC0_WDT1 WDT1 Clock Gating Control [28:28] SCGC1 Sleep Mode Clock Gating Control Register 1 0x00000114 SYSCTL_SCGC1_UART0 UART0 Clock Gating Control [0:0] SYSCTL_SCGC1_UART1 UART1 Clock Gating Control [1:1] SYSCTL_SCGC1_UART2 UART2 Clock Gating Control [2:2] SYSCTL_SCGC1_SSI0 SSI0 Clock Gating Control [4:4] SYSCTL_SCGC1_SSI1 SSI1 Clock Gating Control [5:5] SYSCTL_SCGC1_I2C0 I2C0 Clock Gating Control [12:12] SYSCTL_SCGC1_I2C1 I2C1 Clock Gating Control [14:14] SYSCTL_SCGC1_TIMER0 Timer 0 Clock Gating Control [16:16] SYSCTL_SCGC1_TIMER1 Timer 1 Clock Gating Control [17:17] SYSCTL_SCGC1_TIMER2 Timer 2 Clock Gating Control [18:18] SYSCTL_SCGC1_TIMER3 Timer 3 Clock Gating Control [19:19] SYSCTL_SCGC1_COMP0 Analog Comparator 0 Clock Gating [24:24] SYSCTL_SCGC1_COMP1 Analog Comparator 1 Clock Gating [25:25] SYSCTL_SCGC1_COMP2 Analog Comparator 2 Clock Gating [26:26] SCGC2 Sleep Mode Clock Gating Control Register 2 0x00000118 SYSCTL_SCGC2_GPIOA Port A Clock Gating Control [0:0] SYSCTL_SCGC2_GPIOB Port B Clock Gating Control [1:1] SYSCTL_SCGC2_GPIOC Port C Clock Gating Control [2:2] SYSCTL_SCGC2_GPIOD Port D Clock Gating Control [3:3] SYSCTL_SCGC2_GPIOE Port E Clock Gating Control [4:4] SYSCTL_SCGC2_GPIOF Port F Clock Gating Control [5:5] SYSCTL_SCGC2_GPIOG Port G Clock Gating Control [6:6] SYSCTL_SCGC2_GPIOH Port H Clock Gating Control [7:7] SYSCTL_SCGC2_GPIOJ Port J Clock Gating Control [8:8] SYSCTL_SCGC2_UDMA Micro-DMA Clock Gating Control [13:13] SYSCTL_SCGC2_USB0 USB0 Clock Gating Control [16:16] DCGC0 Deep Sleep Mode Clock Gating Control Register 0 0x00000120 SYSCTL_DCGC0_WDT0 WDT0 Clock Gating Control [3:3] SYSCTL_DCGC0_HIB HIB Clock Gating Control [6:6] SYSCTL_DCGC0_ADC0 ADC0 Clock Gating Control [16:16] SYSCTL_DCGC0_ADC1 ADC1 Clock Gating Control [17:17] SYSCTL_DCGC0_CAN0 CAN0 Clock Gating Control [24:24] SYSCTL_DCGC0_WDT1 WDT1 Clock Gating Control [28:28] DCGC1 Deep-Sleep Mode Clock Gating Control Register 1 0x00000124 SYSCTL_DCGC1_UART0 UART0 Clock Gating Control [0:0] SYSCTL_DCGC1_UART1 UART1 Clock Gating Control [1:1] SYSCTL_DCGC1_UART2 UART2 Clock Gating Control [2:2] SYSCTL_DCGC1_SSI0 SSI0 Clock Gating Control [4:4] SYSCTL_DCGC1_SSI1 SSI1 Clock Gating Control [5:5] SYSCTL_DCGC1_I2C0 I2C0 Clock Gating Control [12:12] SYSCTL_DCGC1_I2C1 I2C1 Clock Gating Control [14:14] SYSCTL_DCGC1_TIMER0 Timer 0 Clock Gating Control [16:16] SYSCTL_DCGC1_TIMER1 Timer 1 Clock Gating Control [17:17] SYSCTL_DCGC1_TIMER2 Timer 2 Clock Gating Control [18:18] SYSCTL_DCGC1_TIMER3 Timer 3 Clock Gating Control [19:19] SYSCTL_DCGC1_COMP0 Analog Comparator 0 Clock Gating [24:24] SYSCTL_DCGC1_COMP1 Analog Comparator 1 Clock Gating [25:25] SYSCTL_DCGC1_COMP2 Analog Comparator 2 Clock Gating [26:26] DCGC2 Deep Sleep Mode Clock Gating Control Register 2 0x00000128 SYSCTL_DCGC2_GPIOA Port A Clock Gating Control [0:0] SYSCTL_DCGC2_GPIOB Port B Clock Gating Control [1:1] SYSCTL_DCGC2_GPIOC Port C Clock Gating Control [2:2] SYSCTL_DCGC2_GPIOD Port D Clock Gating Control [3:3] SYSCTL_DCGC2_GPIOE Port E Clock Gating Control [4:4] SYSCTL_DCGC2_GPIOF Port F Clock Gating Control [5:5] SYSCTL_DCGC2_GPIOG Port G Clock Gating Control [6:6] SYSCTL_DCGC2_GPIOH Port H Clock Gating Control [7:7] SYSCTL_DCGC2_GPIOJ Port J Clock Gating Control [8:8] SYSCTL_DCGC2_UDMA Micro-DMA Clock Gating Control [13:13] SYSCTL_DCGC2_USB0 USB0 Clock Gating Control [16:16] DSLPCLKCFG Deep Sleep Clock Configuration 0x00000144 SYSCTL_DSLPCLKCFG_O Clock Source [6:4] SYSCTL_DSLPCLKCFG_O_IGN MOSC 0x0 SYSCTL_DSLPCLKCFG_O_IO PIOSC 0x1 SYSCTL_DSLPCLKCFG_O_30 30 kHz 0x3 SYSCTL_DSLPCLKCFG_O_32 32.768 kHz 0x7 SYSCTL_DSLPCLKCFG_D Divider Field Override [28:23] SYSPROP System Properties 0x0000014C SYSCTL_SYSPROP_FPU FPU Present [0:0] PIOSCCAL Precision Internal Oscillator Calibration 0x00000150 SYSCTL_PIOSCCAL_UT User Trim Value [6:0] SYSCTL_PIOSCCAL_UPDATE Update Trim [8:8] SYSCTL_PIOSCCAL_CAL Start Calibration [9:9] SYSCTL_PIOSCCAL_UTEN Use User Trim Value [31:31] PIOSCSTAT Precision Internal Oscillator Statistics 0x00000154 SYSCTL_PIOSCSTAT_CT Calibration Trim Value [6:0] SYSCTL_PIOSCSTAT_CR Calibration Result [9:8] SYSCTL_PIOSCSTAT_CRNONE Calibration has not been attempted 0x0 SYSCTL_PIOSCSTAT_CRPASS The last calibration operation completed to meet 1% accuracy 0x1 SYSCTL_PIOSCSTAT_CRFAIL The last calibration operation failed to meet 1% accuracy 0x2 SYSCTL_PIOSCSTAT_DT Default Trim Value [22:16] PLLFREQ0 PLL Frequency 0 0x00000160 SYSCTL_PLLFREQ0_MINT PLL M Integer Value [9:0] SYSCTL_PLLFREQ0_MFRAC PLL M Fractional Value [19:10] PLLFREQ1 PLL Frequency 1 0x00000164 SYSCTL_PLLFREQ1_N PLL N Value [4:0] SYSCTL_PLLFREQ1_Q PLL Q Value [12:8] PLLSTAT PLL Status 0x00000168 SYSCTL_PLLSTAT_LOCK PLL Lock [0:0] DC9 Device Capabilities 9 ADC Digital Comparators 0x00000190 SYSCTL_DC9_ADC0DC0 ADC0 DC0 Present [0:0] SYSCTL_DC9_ADC0DC1 ADC0 DC1 Present [1:1] SYSCTL_DC9_ADC0DC2 ADC0 DC2 Present [2:2] SYSCTL_DC9_ADC0DC3 ADC0 DC3 Present [3:3] SYSCTL_DC9_ADC0DC4 ADC0 DC4 Present [4:4] SYSCTL_DC9_ADC0DC5 ADC0 DC5 Present [5:5] SYSCTL_DC9_ADC0DC6 ADC0 DC6 Present [6:6] SYSCTL_DC9_ADC0DC7 ADC0 DC7 Present [7:7] SYSCTL_DC9_ADC1DC0 ADC1 DC0 Present [16:16] SYSCTL_DC9_ADC1DC1 ADC1 DC1 Present [17:17] SYSCTL_DC9_ADC1DC2 ADC1 DC2 Present [18:18] SYSCTL_DC9_ADC1DC3 ADC1 DC3 Present [19:19] SYSCTL_DC9_ADC1DC4 ADC1 DC4 Present [20:20] SYSCTL_DC9_ADC1DC5 ADC1 DC5 Present [21:21] SYSCTL_DC9_ADC1DC6 ADC1 DC6 Present [22:22] SYSCTL_DC9_ADC1DC7 ADC1 DC7 Present [23:23] NVMSTAT Non-Volatile Memory Information 0x000001A0 SYSCTL_NVMSTAT_FWB 32 Word Flash Write Buffer Active [0:0] PPWD Watchdog Timer Peripheral Present 0x00000300 SYSCTL_PPWD_P0 Watchdog Timer 0 Present [0:0] SYSCTL_PPWD_P1 Watchdog Timer 1 Present [1:1] PPTIMER Timer Peripheral Present 0x00000304 SYSCTL_PPTIMER_P0 Timer 0 Present [0:0] SYSCTL_PPTIMER_P1 Timer 1 Present [1:1] SYSCTL_PPTIMER_P2 Timer 2 Present [2:2] SYSCTL_PPTIMER_P3 Timer 3 Present [3:3] SYSCTL_PPTIMER_P4 Timer 4 Present [4:4] SYSCTL_PPTIMER_P5 Timer 5 Present [5:5] PPGPIO General-Purpose Input/Output Peripheral Present 0x00000308 SYSCTL_PPGPIO_P0 GPIO Port A Present [0:0] SYSCTL_PPGPIO_P1 GPIO Port B Present [1:1] SYSCTL_PPGPIO_P2 GPIO Port C Present [2:2] SYSCTL_PPGPIO_P3 GPIO Port D Present [3:3] SYSCTL_PPGPIO_P4 GPIO Port E Present [4:4] SYSCTL_PPGPIO_P5 GPIO Port F Present [5:5] SYSCTL_PPGPIO_P6 GPIO Port G Present [6:6] SYSCTL_PPGPIO_P7 GPIO Port H Present [7:7] SYSCTL_PPGPIO_P8 GPIO Port J Present [8:8] SYSCTL_PPGPIO_P9 GPIO Port K Present [9:9] SYSCTL_PPGPIO_P10 GPIO Port L Present [10:10] SYSCTL_PPGPIO_P11 GPIO Port M Present [11:11] SYSCTL_PPGPIO_P12 GPIO Port N Present [12:12] SYSCTL_PPGPIO_P13 GPIO Port P Present [13:13] SYSCTL_PPGPIO_P14 GPIO Port Q Present [14:14] PPDMA Micro Direct Memory Access Peripheral Present 0x0000030C SYSCTL_PPDMA_P0 uDMA Module Present [0:0] PPHIB Hibernation Peripheral Present 0x00000314 SYSCTL_PPHIB_P0 Hibernation Module Present [0:0] PPUART Universal Asynchronous Receiver/Transmitter Peripheral Present 0x00000318 SYSCTL_PPUART_P0 UART Module 0 Present [0:0] SYSCTL_PPUART_P1 UART Module 1 Present [1:1] SYSCTL_PPUART_P2 UART Module 2 Present [2:2] SYSCTL_PPUART_P3 UART Module 3 Present [3:3] SYSCTL_PPUART_P4 UART Module 4 Present [4:4] SYSCTL_PPUART_P5 UART Module 5 Present [5:5] SYSCTL_PPUART_P6 UART Module 6 Present [6:6] SYSCTL_PPUART_P7 UART Module 7 Present [7:7] PPSSI Synchronous Serial Interface Peripheral Present 0x0000031C SYSCTL_PPSSI_P0 SSI Module 0 Present [0:0] SYSCTL_PPSSI_P1 SSI Module 1 Present [1:1] SYSCTL_PPSSI_P2 SSI Module 2 Present [2:2] SYSCTL_PPSSI_P3 SSI Module 3 Present [3:3] PPI2C Inter-Integrated Circuit Peripheral Present 0x00000320 SYSCTL_PPI2C_P0 I2C Module 0 Present [0:0] SYSCTL_PPI2C_P1 I2C Module 1 Present [1:1] SYSCTL_PPI2C_P2 I2C Module 2 Present [2:2] SYSCTL_PPI2C_P3 I2C Module 3 Present [3:3] SYSCTL_PPI2C_P4 I2C Module 4 Present [4:4] SYSCTL_PPI2C_P5 I2C Module 5 Present [5:5] PPUSB Universal Serial Bus Peripheral Present 0x00000328 SYSCTL_PPUSB_P0 USB Module Present [0:0] PPCAN Controller Area Network Peripheral Present 0x00000334 SYSCTL_PPCAN_P0 CAN Module 0 Present [0:0] SYSCTL_PPCAN_P1 CAN Module 1 Present [1:1] PPADC Analog-to-Digital Converter Peripheral Present 0x00000338 SYSCTL_PPADC_P0 ADC Module 0 Present [0:0] SYSCTL_PPADC_P1 ADC Module 1 Present [1:1] PPACMP Analog Comparator Peripheral Present 0x0000033C SYSCTL_PPACMP_P0 Analog Comparator Module Present [0:0] PPPWM Pulse Width Modulator Peripheral Present 0x00000340 SYSCTL_PPPWM_P0 PWM Module 0 Present [0:0] SYSCTL_PPPWM_P1 PWM Module 1 Present [1:1] PPQEI Quadrature Encoder Interface Peripheral Present 0x00000344 SYSCTL_PPQEI_P0 QEI Module 0 Present [0:0] SYSCTL_PPQEI_P1 QEI Module 1 Present [1:1] PPEEPROM EEPROM Peripheral Present 0x00000358 SYSCTL_PPEEPROM_P0 EEPROM Module Present [0:0] PPWTIMER Wide Timer Peripheral Present 0x0000035C SYSCTL_PPWTIMER_P0 Wide Timer 0 Present [0:0] SYSCTL_PPWTIMER_P1 Wide Timer 1 Present [1:1] SYSCTL_PPWTIMER_P2 Wide Timer 2 Present [2:2] SYSCTL_PPWTIMER_P3 Wide Timer 3 Present [3:3] SYSCTL_PPWTIMER_P4 Wide Timer 4 Present [4:4] SYSCTL_PPWTIMER_P5 Wide Timer 5 Present [5:5] SRWD Watchdog Timer Software Reset 0x00000500 SYSCTL_SRWD_R0 Watchdog Timer 0 Software Reset [0:0] SYSCTL_SRWD_R1 Watchdog Timer 1 Software Reset [1:1] SRTIMER Timer Software Reset 0x00000504 SYSCTL_SRTIMER_R0 Timer 0 Software Reset [0:0] SYSCTL_SRTIMER_R1 Timer 1 Software Reset [1:1] SYSCTL_SRTIMER_R2 Timer 2 Software Reset [2:2] SYSCTL_SRTIMER_R3 Timer 3 Software Reset [3:3] SYSCTL_SRTIMER_R4 Timer 4 Software Reset [4:4] SYSCTL_SRTIMER_R5 Timer 5 Software Reset [5:5] SRGPIO General-Purpose Input/Output Software Reset 0x00000508 SYSCTL_SRGPIO_R0 GPIO Port A Software Reset [0:0] SYSCTL_SRGPIO_R1 GPIO Port B Software Reset [1:1] SYSCTL_SRGPIO_R2 GPIO Port C Software Reset [2:2] SYSCTL_SRGPIO_R3 GPIO Port D Software Reset [3:3] SYSCTL_SRGPIO_R4 GPIO Port E Software Reset [4:4] SYSCTL_SRGPIO_R5 GPIO Port F Software Reset [5:5] SYSCTL_SRGPIO_R6 GPIO Port G Software Reset [6:6] SYSCTL_SRGPIO_R7 GPIO Port H Software Reset [7:7] SYSCTL_SRGPIO_R8 GPIO Port J Software Reset [8:8] SYSCTL_SRGPIO_R9 GPIO Port K Software Reset [9:9] SYSCTL_SRGPIO_R10 GPIO Port L Software Reset [10:10] SYSCTL_SRGPIO_R11 GPIO Port M Software Reset [11:11] SYSCTL_SRGPIO_R12 GPIO Port N Software Reset [12:12] SYSCTL_SRGPIO_R13 GPIO Port P Software Reset [13:13] SRDMA Micro Direct Memory Access Software Reset 0x0000050C SYSCTL_SRDMA_R0 uDMA Module Software Reset [0:0] SRHIB Hibernation Software Reset 0x00000514 SYSCTL_SRHIB_R0 Hibernation Module Software Reset [0:0] SRUART Universal Asynchronous Receiver/Transmitter Software Reset 0x00000518 SYSCTL_SRUART_R0 UART Module 0 Software Reset [0:0] SYSCTL_SRUART_R1 UART Module 1 Software Reset [1:1] SYSCTL_SRUART_R2 UART Module 2 Software Reset [2:2] SYSCTL_SRUART_R3 UART Module 3 Software Reset [3:3] SYSCTL_SRUART_R4 UART Module 4 Software Reset [4:4] SYSCTL_SRUART_R5 UART Module 5 Software Reset [5:5] SYSCTL_SRUART_R6 UART Module 6 Software Reset [6:6] SYSCTL_SRUART_R7 UART Module 7 Software Reset [7:7] SRSSI Synchronous Serial Interface Software Reset 0x0000051C SYSCTL_SRSSI_R0 SSI Module 0 Software Reset [0:0] SYSCTL_SRSSI_R1 SSI Module 1 Software Reset [1:1] SYSCTL_SRSSI_R2 SSI Module 2 Software Reset [2:2] SYSCTL_SRSSI_R3 SSI Module 3 Software Reset [3:3] SRI2C Inter-Integrated Circuit Software Reset 0x00000520 SYSCTL_SRI2C_R0 I2C Module 0 Software Reset [0:0] SYSCTL_SRI2C_R1 I2C Module 1 Software Reset [1:1] SYSCTL_SRI2C_R2 I2C Module 2 Software Reset [2:2] SYSCTL_SRI2C_R3 I2C Module 3 Software Reset [3:3] SYSCTL_SRI2C_R4 I2C Module 4 Software Reset [4:4] SYSCTL_SRI2C_R5 I2C Module 5 Software Reset [5:5] SRUSB Universal Serial Bus Software Reset 0x00000528 SYSCTL_SRUSB_R0 USB Module Software Reset [0:0] SRCAN Controller Area Network Software Reset 0x00000534 SYSCTL_SRCAN_R0 CAN Module 0 Software Reset [0:0] SRADC Analog-to-Digital Converter Software Reset 0x00000538 SYSCTL_SRADC_R0 ADC Module 0 Software Reset [0:0] SYSCTL_SRADC_R1 ADC Module 1 Software Reset [1:1] SRACMP Analog Comparator Software Reset 0x0000053C SYSCTL_SRACMP_R0 Analog Comparator Module 0 Software Reset [0:0] SREEPROM EEPROM Software Reset 0x00000558 SYSCTL_SREEPROM_R0 EEPROM Module Software Reset [0:0] SRWTIMER Wide Timer Software Reset 0x0000055C SYSCTL_SRWTIMER_R0 Wide Timer 0 Software Reset [0:0] SYSCTL_SRWTIMER_R1 Wide Timer 1 Software Reset [1:1] SYSCTL_SRWTIMER_R2 Wide Timer 2 Software Reset [2:2] SYSCTL_SRWTIMER_R3 Wide Timer 3 Software Reset [3:3] SYSCTL_SRWTIMER_R4 Wide Timer 4 Software Reset [4:4] SYSCTL_SRWTIMER_R5 Wide Timer 5 Software Reset [5:5] RCGCWD Watchdog Timer Run Mode Clock Gating Control 0x00000600 SYSCTL_RCGCWD_R0 Watchdog Timer 0 Run Mode Clock Gating Control [0:0] SYSCTL_RCGCWD_R1 Watchdog Timer 1 Run Mode Clock Gating Control [1:1] RCGCTIMER Timer Run Mode Clock Gating Control 0x00000604 SYSCTL_RCGCTIMER_R0 Timer 0 Run Mode Clock Gating Control [0:0] SYSCTL_RCGCTIMER_R1 Timer 1 Run Mode Clock Gating Control [1:1] SYSCTL_RCGCTIMER_R2 Timer 2 Run Mode Clock Gating Control [2:2] SYSCTL_RCGCTIMER_R3 Timer 3 Run Mode Clock Gating Control [3:3] SYSCTL_RCGCTIMER_R4 Timer 4 Run Mode Clock Gating Control [4:4] SYSCTL_RCGCTIMER_R5 Timer 5 Run Mode Clock Gating Control [5:5] RCGCGPIO General-Purpose Input/Output Run Mode Clock Gating Control 0x00000608 SYSCTL_RCGCGPIO_R0 GPIO Port A Run Mode Clock Gating Control [0:0] SYSCTL_RCGCGPIO_R1 GPIO Port B Run Mode Clock Gating Control [1:1] SYSCTL_RCGCGPIO_R2 GPIO Port C Run Mode Clock Gating Control [2:2] SYSCTL_RCGCGPIO_R3 GPIO Port D Run Mode Clock Gating Control [3:3] SYSCTL_RCGCGPIO_R4 GPIO Port E Run Mode Clock Gating Control [4:4] SYSCTL_RCGCGPIO_R5 GPIO Port F Run Mode Clock Gating Control [5:5] SYSCTL_RCGCGPIO_R6 GPIO Port G Run Mode Clock Gating Control [6:6] SYSCTL_RCGCGPIO_R7 GPIO Port H Run Mode Clock Gating Control [7:7] SYSCTL_RCGCGPIO_R8 GPIO Port J Run Mode Clock Gating Control [8:8] SYSCTL_RCGCGPIO_R9 GPIO Port K Run Mode Clock Gating Control [9:9] SYSCTL_RCGCGPIO_R10 GPIO Port L Run Mode Clock Gating Control [10:10] SYSCTL_RCGCGPIO_R11 GPIO Port M Run Mode Clock Gating Control [11:11] SYSCTL_RCGCGPIO_R12 GPIO Port N Run Mode Clock Gating Control [12:12] SYSCTL_RCGCGPIO_R13 GPIO Port P Run Mode Clock Gating Control [13:13] RCGCDMA Micro Direct Memory Access Run Mode Clock Gating Control 0x0000060C SYSCTL_RCGCDMA_R0 uDMA Module Run Mode Clock Gating Control [0:0] RCGCHIB Hibernation Run Mode Clock Gating Control 0x00000614 SYSCTL_RCGCHIB_R0 Hibernation Module Run Mode Clock Gating Control [0:0] RCGCUART Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control 0x00000618 SYSCTL_RCGCUART_R0 UART Module 0 Run Mode Clock Gating Control [0:0] SYSCTL_RCGCUART_R1 UART Module 1 Run Mode Clock Gating Control [1:1] SYSCTL_RCGCUART_R2 UART Module 2 Run Mode Clock Gating Control [2:2] SYSCTL_RCGCUART_R3 UART Module 3 Run Mode Clock Gating Control [3:3] SYSCTL_RCGCUART_R4 UART Module 4 Run Mode Clock Gating Control [4:4] SYSCTL_RCGCUART_R5 UART Module 5 Run Mode Clock Gating Control [5:5] SYSCTL_RCGCUART_R6 UART Module 6 Run Mode Clock Gating Control [6:6] SYSCTL_RCGCUART_R7 UART Module 7 Run Mode Clock Gating Control [7:7] RCGCSSI Synchronous Serial Interface Run Mode Clock Gating Control 0x0000061C SYSCTL_RCGCSSI_R0 SSI Module 0 Run Mode Clock Gating Control [0:0] SYSCTL_RCGCSSI_R1 SSI Module 1 Run Mode Clock Gating Control [1:1] SYSCTL_RCGCSSI_R2 SSI Module 2 Run Mode Clock Gating Control [2:2] SYSCTL_RCGCSSI_R3 SSI Module 3 Run Mode Clock Gating Control [3:3] RCGCI2C Inter-Integrated Circuit Run Mode Clock Gating Control 0x00000620 SYSCTL_RCGCI2C_R0 I2C Module 0 Run Mode Clock Gating Control [0:0] SYSCTL_RCGCI2C_R1 I2C Module 1 Run Mode Clock Gating Control [1:1] SYSCTL_RCGCI2C_R2 I2C Module 2 Run Mode Clock Gating Control [2:2] SYSCTL_RCGCI2C_R3 I2C Module 3 Run Mode Clock Gating Control [3:3] SYSCTL_RCGCI2C_R4 I2C Module 4 Run Mode Clock Gating Control [4:4] SYSCTL_RCGCI2C_R5 I2C Module 5 Run Mode Clock Gating Control [5:5] RCGCUSB Universal Serial Bus Run Mode Clock Gating Control 0x00000628 SYSCTL_RCGCUSB_R0 USB Module Run Mode Clock Gating Control [0:0] RCGCCAN Controller Area Network Run Mode Clock Gating Control 0x00000634 SYSCTL_RCGCCAN_R0 CAN Module 0 Run Mode Clock Gating Control [0:0] RCGCADC Analog-to-Digital Converter Run Mode Clock Gating Control 0x00000638 SYSCTL_RCGCADC_R0 ADC Module 0 Run Mode Clock Gating Control [0:0] SYSCTL_RCGCADC_R1 ADC Module 1 Run Mode Clock Gating Control [1:1] RCGCACMP Analog Comparator Run Mode Clock Gating Control 0x0000063C SYSCTL_RCGCACMP_R0 Analog Comparator Module 0 Run Mode Clock Gating Control [0:0] RCGCEEPROM EEPROM Run Mode Clock Gating Control 0x00000658 SYSCTL_RCGCEEPROM_R0 EEPROM Module Run Mode Clock Gating Control [0:0] RCGCWTIMER Wide Timer Run Mode Clock Gating Control 0x0000065C SYSCTL_RCGCWTIMER_R0 Wide Timer 0 Run Mode Clock Gating Control [0:0] SYSCTL_RCGCWTIMER_R1 Wide Timer 1 Run Mode Clock Gating Control [1:1] SYSCTL_RCGCWTIMER_R2 Wide Timer 2 Run Mode Clock Gating Control [2:2] SYSCTL_RCGCWTIMER_R3 Wide Timer 3 Run Mode Clock Gating Control [3:3] SYSCTL_RCGCWTIMER_R4 Wide Timer 4 Run Mode Clock Gating Control [4:4] SYSCTL_RCGCWTIMER_R5 Wide Timer 5 Run Mode Clock Gating Control [5:5] SCGCWD Watchdog Timer Sleep Mode Clock Gating Control 0x00000700 SYSCTL_SCGCWD_S0 Watchdog Timer 0 Sleep Mode Clock Gating Control [0:0] SYSCTL_SCGCWD_S1 Watchdog Timer 1 Sleep Mode Clock Gating Control [1:1] SCGCTIMER Timer Sleep Mode Clock Gating Control 0x00000704 SYSCTL_SCGCTIMER_S0 Timer 0 Sleep Mode Clock Gating Control [0:0] SYSCTL_SCGCTIMER_S1 Timer 1 Sleep Mode Clock Gating Control [1:1] SYSCTL_SCGCTIMER_S2 Timer 2 Sleep Mode Clock Gating Control [2:2] SYSCTL_SCGCTIMER_S3 Timer 3 Sleep Mode Clock Gating Control [3:3] SYSCTL_SCGCTIMER_S4 Timer 4 Sleep Mode Clock Gating Control [4:4] SYSCTL_SCGCTIMER_S5 Timer 5 Sleep Mode Clock Gating Control [5:5] SCGCGPIO General-Purpose Input/Output Sleep Mode Clock Gating Control 0x00000708 SYSCTL_SCGCGPIO_S0 GPIO Port A Sleep Mode Clock Gating Control [0:0] SYSCTL_SCGCGPIO_S1 GPIO Port B Sleep Mode Clock Gating Control [1:1] SYSCTL_SCGCGPIO_S2 GPIO Port C Sleep Mode Clock Gating Control [2:2] SYSCTL_SCGCGPIO_S3 GPIO Port D Sleep Mode Clock Gating Control [3:3] SYSCTL_SCGCGPIO_S4 GPIO Port E Sleep Mode Clock Gating Control [4:4] SYSCTL_SCGCGPIO_S5 GPIO Port F Sleep Mode Clock Gating Control [5:5] SYSCTL_SCGCGPIO_S6 GPIO Port G Sleep Mode Clock Gating Control [6:6] SYSCTL_SCGCGPIO_S7 GPIO Port H Sleep Mode Clock Gating Control [7:7] SYSCTL_SCGCGPIO_S8 GPIO Port J Sleep Mode Clock Gating Control [8:8] SYSCTL_SCGCGPIO_S9 GPIO Port K Sleep Mode Clock Gating Control [9:9] SYSCTL_SCGCGPIO_S10 GPIO Port L Sleep Mode Clock Gating Control [10:10] SYSCTL_SCGCGPIO_S11 GPIO Port M Sleep Mode Clock Gating Control [11:11] SYSCTL_SCGCGPIO_S12 GPIO Port N Sleep Mode Clock Gating Control [12:12] SYSCTL_SCGCGPIO_S13 GPIO Port P Sleep Mode Clock Gating Control [13:13] SCGCDMA Micro Direct Memory Access Sleep Mode Clock Gating Control 0x0000070C SYSCTL_SCGCDMA_S0 uDMA Module Sleep Mode Clock Gating Control [0:0] SCGCHIB Hibernation Sleep Mode Clock Gating Control 0x00000714 SYSCTL_SCGCHIB_S0 Hibernation Module Sleep Mode Clock Gating Control [0:0] SCGCUART Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control 0x00000718 SYSCTL_SCGCUART_S0 UART Module 0 Sleep Mode Clock Gating Control [0:0] SYSCTL_SCGCUART_S1 UART Module 1 Sleep Mode Clock Gating Control [1:1] SYSCTL_SCGCUART_S2 UART Module 2 Sleep Mode Clock Gating Control [2:2] SYSCTL_SCGCUART_S3 UART Module 3 Sleep Mode Clock Gating Control [3:3] SYSCTL_SCGCUART_S4 UART Module 4 Sleep Mode Clock Gating Control [4:4] SYSCTL_SCGCUART_S5 UART Module 5 Sleep Mode Clock Gating Control [5:5] SYSCTL_SCGCUART_S6 UART Module 6 Sleep Mode Clock Gating Control [6:6] SYSCTL_SCGCUART_S7 UART Module 7 Sleep Mode Clock Gating Control [7:7] SCGCSSI Synchronous Serial Interface Sleep Mode Clock Gating Control 0x0000071C SYSCTL_SCGCSSI_S0 SSI Module 0 Sleep Mode Clock Gating Control [0:0] SYSCTL_SCGCSSI_S1 SSI Module 1 Sleep Mode Clock Gating Control [1:1] SYSCTL_SCGCSSI_S2 SSI Module 2 Sleep Mode Clock Gating Control [2:2] SYSCTL_SCGCSSI_S3 SSI Module 3 Sleep Mode Clock Gating Control [3:3] SCGCI2C Inter-Integrated Circuit Sleep Mode Clock Gating Control 0x00000720 SYSCTL_SCGCI2C_S0 I2C Module 0 Sleep Mode Clock Gating Control [0:0] SYSCTL_SCGCI2C_S1 I2C Module 1 Sleep Mode Clock Gating Control [1:1] SYSCTL_SCGCI2C_S2 I2C Module 2 Sleep Mode Clock Gating Control [2:2] SYSCTL_SCGCI2C_S3 I2C Module 3 Sleep Mode Clock Gating Control [3:3] SYSCTL_SCGCI2C_S4 I2C Module 4 Sleep Mode Clock Gating Control [4:4] SYSCTL_SCGCI2C_S5 I2C Module 5 Sleep Mode Clock Gating Control [5:5] SCGCUSB Universal Serial Bus Sleep Mode Clock Gating Control 0x00000728 SYSCTL_SCGCUSB_S0 USB Module Sleep Mode Clock Gating Control [0:0] SCGCCAN Controller Area Network Sleep Mode Clock Gating Control 0x00000734 SYSCTL_SCGCCAN_S0 CAN Module 0 Sleep Mode Clock Gating Control [0:0] SCGCADC Analog-to-Digital Converter Sleep Mode Clock Gating Control 0x00000738 SYSCTL_SCGCADC_S0 ADC Module 0 Sleep Mode Clock Gating Control [0:0] SYSCTL_SCGCADC_S1 ADC Module 1 Sleep Mode Clock Gating Control [1:1] SCGCACMP Analog Comparator Sleep Mode Clock Gating Control 0x0000073C SYSCTL_SCGCACMP_S0 Analog Comparator Module 0 Sleep Mode Clock Gating Control [0:0] SCGCEEPROM EEPROM Sleep Mode Clock Gating Control 0x00000758 SYSCTL_SCGCEEPROM_S0 EEPROM Module Sleep Mode Clock Gating Control [0:0] SCGCWTIMER Wide Timer Sleep Mode Clock Gating Control 0x0000075C SYSCTL_SCGCWTIMER_S0 Wide Timer 0 Sleep Mode Clock Gating Control [0:0] SYSCTL_SCGCWTIMER_S1 Wide Timer 1 Sleep Mode Clock Gating Control [1:1] SYSCTL_SCGCWTIMER_S2 Wide Timer 2 Sleep Mode Clock Gating Control [2:2] SYSCTL_SCGCWTIMER_S3 Wide Timer 3 Sleep Mode Clock Gating Control [3:3] SYSCTL_SCGCWTIMER_S4 Wide Timer 4 Sleep Mode Clock Gating Control [4:4] SYSCTL_SCGCWTIMER_S5 Wide Timer 5 Sleep Mode Clock Gating Control [5:5] DCGCWD Watchdog Timer Deep-Sleep Mode Clock Gating Control 0x00000800 SYSCTL_DCGCWD_D0 Watchdog Timer 0 Deep-Sleep Mode Clock Gating Control [0:0] SYSCTL_DCGCWD_D1 Watchdog Timer 1 Deep-Sleep Mode Clock Gating Control [1:1] DCGCTIMER Timer Deep-Sleep Mode Clock Gating Control 0x00000804 SYSCTL_DCGCTIMER_D0 Timer 0 Deep-Sleep Mode Clock Gating Control [0:0] SYSCTL_DCGCTIMER_D1 Timer 1 Deep-Sleep Mode Clock Gating Control [1:1] SYSCTL_DCGCTIMER_D2 Timer 2 Deep-Sleep Mode Clock Gating Control [2:2] SYSCTL_DCGCTIMER_D3 Timer 3 Deep-Sleep Mode Clock Gating Control [3:3] SYSCTL_DCGCTIMER_D4 Timer 4 Deep-Sleep Mode Clock Gating Control [4:4] SYSCTL_DCGCTIMER_D5 Timer 5 Deep-Sleep Mode Clock Gating Control [5:5] DCGCGPIO General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control 0x00000808 SYSCTL_DCGCGPIO_D0 GPIO Port A Deep-Sleep Mode Clock Gating Control [0:0] SYSCTL_DCGCGPIO_D1 GPIO Port B Deep-Sleep Mode Clock Gating Control [1:1] SYSCTL_DCGCGPIO_D2 GPIO Port C Deep-Sleep Mode Clock Gating Control [2:2] SYSCTL_DCGCGPIO_D3 GPIO Port D Deep-Sleep Mode Clock Gating Control [3:3] SYSCTL_DCGCGPIO_D4 GPIO Port E Deep-Sleep Mode Clock Gating Control [4:4] SYSCTL_DCGCGPIO_D5 GPIO Port F Deep-Sleep Mode Clock Gating Control [5:5] SYSCTL_DCGCGPIO_D6 GPIO Port G Deep-Sleep Mode Clock Gating Control [6:6] SYSCTL_DCGCGPIO_D7 GPIO Port H Deep-Sleep Mode Clock Gating Control [7:7] SYSCTL_DCGCGPIO_D8 GPIO Port J Deep-Sleep Mode Clock Gating Control [8:8] SYSCTL_DCGCGPIO_D9 GPIO Port K Deep-Sleep Mode Clock Gating Control [9:9] SYSCTL_DCGCGPIO_D10 GPIO Port L Deep-Sleep Mode Clock Gating Control [10:10] SYSCTL_DCGCGPIO_D11 GPIO Port M Deep-Sleep Mode Clock Gating Control [11:11] SYSCTL_DCGCGPIO_D12 GPIO Port N Deep-Sleep Mode Clock Gating Control [12:12] SYSCTL_DCGCGPIO_D13 GPIO Port P Deep-Sleep Mode Clock Gating Control [13:13] DCGCDMA Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control 0x0000080C SYSCTL_DCGCDMA_D0 uDMA Module Deep-Sleep Mode Clock Gating Control [0:0] DCGCHIB Hibernation Deep-Sleep Mode Clock Gating Control 0x00000814 SYSCTL_DCGCHIB_D0 Hibernation Module Deep-Sleep Mode Clock Gating Control [0:0] DCGCUART Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control 0x00000818 SYSCTL_DCGCUART_D0 UART Module 0 Deep-Sleep Mode Clock Gating Control [0:0] SYSCTL_DCGCUART_D1 UART Module 1 Deep-Sleep Mode Clock Gating Control [1:1] SYSCTL_DCGCUART_D2 UART Module 2 Deep-Sleep Mode Clock Gating Control [2:2] SYSCTL_DCGCUART_D3 UART Module 3 Deep-Sleep Mode Clock Gating Control [3:3] SYSCTL_DCGCUART_D4 UART Module 4 Deep-Sleep Mode Clock Gating Control [4:4] SYSCTL_DCGCUART_D5 UART Module 5 Deep-Sleep Mode Clock Gating Control [5:5] SYSCTL_DCGCUART_D6 UART Module 6 Deep-Sleep Mode Clock Gating Control [6:6] SYSCTL_DCGCUART_D7 UART Module 7 Deep-Sleep Mode Clock Gating Control [7:7] DCGCSSI Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control 0x0000081C SYSCTL_DCGCSSI_D0 SSI Module 0 Deep-Sleep Mode Clock Gating Control [0:0] SYSCTL_DCGCSSI_D1 SSI Module 1 Deep-Sleep Mode Clock Gating Control [1:1] SYSCTL_DCGCSSI_D2 SSI Module 2 Deep-Sleep Mode Clock Gating Control [2:2] SYSCTL_DCGCSSI_D3 SSI Module 3 Deep-Sleep Mode Clock Gating Control [3:3] DCGCI2C Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control 0x00000820 SYSCTL_DCGCI2C_D0 I2C Module 0 Deep-Sleep Mode Clock Gating Control [0:0] SYSCTL_DCGCI2C_D1 I2C Module 1 Deep-Sleep Mode Clock Gating Control [1:1] SYSCTL_DCGCI2C_D2 I2C Module 2 Deep-Sleep Mode Clock Gating Control [2:2] SYSCTL_DCGCI2C_D3 I2C Module 3 Deep-Sleep Mode Clock Gating Control [3:3] SYSCTL_DCGCI2C_D4 I2C Module 4 Deep-Sleep Mode Clock Gating Control [4:4] SYSCTL_DCGCI2C_D5 I2C Module 5 Deep-Sleep Mode Clock Gating Control [5:5] DCGCUSB Universal Serial Bus Deep-Sleep Mode Clock Gating Control 0x00000828 SYSCTL_DCGCUSB_D0 USB Module Deep-Sleep Mode Clock Gating Control [0:0] DCGCCAN Controller Area Network Deep-Sleep Mode Clock Gating Control 0x00000834 SYSCTL_DCGCCAN_D0 CAN Module 0 Deep-Sleep Mode Clock Gating Control [0:0] DCGCADC Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control 0x00000838 SYSCTL_DCGCADC_D0 ADC Module 0 Deep-Sleep Mode Clock Gating Control [0:0] SYSCTL_DCGCADC_D1 ADC Module 1 Deep-Sleep Mode Clock Gating Control [1:1] DCGCACMP Analog Comparator Deep-Sleep Mode Clock Gating Control 0x0000083C SYSCTL_DCGCACMP_D0 Analog Comparator Module 0 Deep-Sleep Mode Clock Gating Control [0:0] DCGCEEPROM EEPROM Deep-Sleep Mode Clock Gating Control 0x00000858 SYSCTL_DCGCEEPROM_D0 EEPROM Module Deep-Sleep Mode Clock Gating Control [0:0] DCGCWTIMER Wide Timer Deep-Sleep Mode Clock Gating Control 0x0000085C SYSCTL_DCGCWTIMER_D0 Wide Timer 0 Deep-Sleep Mode Clock Gating Control [0:0] SYSCTL_DCGCWTIMER_D1 Wide Timer 1 Deep-Sleep Mode Clock Gating Control [1:1] SYSCTL_DCGCWTIMER_D2 Wide Timer 2 Deep-Sleep Mode Clock Gating Control [2:2] SYSCTL_DCGCWTIMER_D3 Wide Timer 3 Deep-Sleep Mode Clock Gating Control [3:3] SYSCTL_DCGCWTIMER_D4 Wide Timer 4 Deep-Sleep Mode Clock Gating Control [4:4] SYSCTL_DCGCWTIMER_D5 Wide Timer 5 Deep-Sleep Mode Clock Gating Control [5:5] PRWD Watchdog Timer Peripheral Ready 0x00000A00 SYSCTL_PRWD_R0 Watchdog Timer 0 Peripheral Ready [0:0] SYSCTL_PRWD_R1 Watchdog Timer 1 Peripheral Ready [1:1] PRTIMER Timer Peripheral Ready 0x00000A04 SYSCTL_PRTIMER_R0 Timer 0 Peripheral Ready [0:0] SYSCTL_PRTIMER_R1 Timer 1 Peripheral Ready [1:1] SYSCTL_PRTIMER_R2 Timer 2 Peripheral Ready [2:2] SYSCTL_PRTIMER_R3 Timer 3 Peripheral Ready [3:3] SYSCTL_PRTIMER_R4 Timer 4 Peripheral Ready [4:4] SYSCTL_PRTIMER_R5 Timer 5 Peripheral Ready [5:5] PRGPIO General-Purpose Input/Output Peripheral Ready 0x00000A08 SYSCTL_PRGPIO_R0 GPIO Port A Peripheral Ready [0:0] SYSCTL_PRGPIO_R1 GPIO Port B Peripheral Ready [1:1] SYSCTL_PRGPIO_R2 GPIO Port C Peripheral Ready [2:2] SYSCTL_PRGPIO_R3 GPIO Port D Peripheral Ready [3:3] SYSCTL_PRGPIO_R4 GPIO Port E Peripheral Ready [4:4] SYSCTL_PRGPIO_R5 GPIO Port F Peripheral Ready [5:5] SYSCTL_PRGPIO_R6 GPIO Port G Peripheral Ready [6:6] SYSCTL_PRGPIO_R7 GPIO Port H Peripheral Ready [7:7] SYSCTL_PRGPIO_R8 GPIO Port J Peripheral Ready [8:8] SYSCTL_PRGPIO_R9 GPIO Port K Peripheral Ready [9:9] SYSCTL_PRGPIO_R10 GPIO Port L Peripheral Ready [10:10] SYSCTL_PRGPIO_R11 GPIO Port M Peripheral Ready [11:11] SYSCTL_PRGPIO_R12 GPIO Port N Peripheral Ready [12:12] SYSCTL_PRGPIO_R13 GPIO Port P Peripheral Ready [13:13] PRDMA Micro Direct Memory Access Peripheral Ready 0x00000A0C SYSCTL_PRDMA_R0 uDMA Module Peripheral Ready [0:0] PRHIB Hibernation Peripheral Ready 0x00000A14 SYSCTL_PRHIB_R0 Hibernation Module Peripheral Ready [0:0] PRUART Universal Asynchronous Receiver/Transmitter Peripheral Ready 0x00000A18 SYSCTL_PRUART_R0 UART Module 0 Peripheral Ready [0:0] SYSCTL_PRUART_R1 UART Module 1 Peripheral Ready [1:1] SYSCTL_PRUART_R2 UART Module 2 Peripheral Ready [2:2] SYSCTL_PRUART_R3 UART Module 3 Peripheral Ready [3:3] SYSCTL_PRUART_R4 UART Module 4 Peripheral Ready [4:4] SYSCTL_PRUART_R5 UART Module 5 Peripheral Ready [5:5] SYSCTL_PRUART_R6 UART Module 6 Peripheral Ready [6:6] SYSCTL_PRUART_R7 UART Module 7 Peripheral Ready [7:7] PRSSI Synchronous Serial Interface Peripheral Ready 0x00000A1C SYSCTL_PRSSI_R0 SSI Module 0 Peripheral Ready [0:0] SYSCTL_PRSSI_R1 SSI Module 1 Peripheral Ready [1:1] SYSCTL_PRSSI_R2 SSI Module 2 Peripheral Ready [2:2] SYSCTL_PRSSI_R3 SSI Module 3 Peripheral Ready [3:3] PRI2C Inter-Integrated Circuit Peripheral Ready 0x00000A20 SYSCTL_PRI2C_R0 I2C Module 0 Peripheral Ready [0:0] SYSCTL_PRI2C_R1 I2C Module 1 Peripheral Ready [1:1] SYSCTL_PRI2C_R2 I2C Module 2 Peripheral Ready [2:2] SYSCTL_PRI2C_R3 I2C Module 3 Peripheral Ready [3:3] SYSCTL_PRI2C_R4 I2C Module 4 Peripheral Ready [4:4] SYSCTL_PRI2C_R5 I2C Module 5 Peripheral Ready [5:5] PRUSB Universal Serial Bus Peripheral Ready 0x00000A28 SYSCTL_PRUSB_R0 USB Module Peripheral Ready [0:0] PRCAN Controller Area Network Peripheral Ready 0x00000A34 SYSCTL_PRCAN_R0 CAN Module 0 Peripheral Ready [0:0] PRADC Analog-to-Digital Converter Peripheral Ready 0x00000A38 SYSCTL_PRADC_R0 ADC Module 0 Peripheral Ready [0:0] SYSCTL_PRADC_R1 ADC Module 1 Peripheral Ready [1:1] PRACMP Analog Comparator Peripheral Ready 0x00000A3C SYSCTL_PRACMP_R0 Analog Comparator Module 0 Peripheral Ready [0:0] PREEPROM EEPROM Peripheral Ready 0x00000A58 SYSCTL_PREEPROM_R0 EEPROM Module Peripheral Ready [0:0] PRWTIMER Wide Timer Peripheral Ready 0x00000A5C SYSCTL_PRWTIMER_R0 Wide Timer 0 Peripheral Ready [0:0] SYSCTL_PRWTIMER_R1 Wide Timer 1 Peripheral Ready [1:1] SYSCTL_PRWTIMER_R2 Wide Timer 2 Peripheral Ready [2:2] SYSCTL_PRWTIMER_R3 Wide Timer 3 Peripheral Ready [3:3] SYSCTL_PRWTIMER_R4 Wide Timer 4 Peripheral Ready [4:4] SYSCTL_PRWTIMER_R5 Wide Timer 5 Peripheral Ready [5:5] UDMA Register map for UDMA peripheral UDM UDMA 0x400FF000 0 0x00001000 registers UDMA46 UDMAERR47 STAT DMA Status 0x00000000 UDMA_STAT_MASTEN Master Enable Status [0:0] UDMA_STAT_STATE Control State Machine Status [7:4] UDMA_STAT_STATE_IDLE Idle 0x0 UDMA_STAT_STATE_RD_CTRL Reading channel controller data 0x1 UDMA_STAT_STATE_RD_SRCENDP Reading source end pointer 0x2 UDMA_STAT_STATE_RD_DSTENDP Reading destination end pointer 0x3 UDMA_STAT_STATE_RD_SRCDAT Reading source data 0x4 UDMA_STAT_STATE_WR_DSTDAT Writing destination data 0x5 UDMA_STAT_STATE_WAIT Waiting for uDMA request to clear 0x6 UDMA_STAT_STATE_WR_CTRL Writing channel controller data 0x7 UDMA_STAT_STATE_STALL Stalled 0x8 UDMA_STAT_STATE_DONE Done 0x9 UDMA_STAT_STATE_UNDEF Undefined 0xa UDMA_STAT_DMACHANS Available uDMA Channels Minus 1 [20:16] CFG DMA Configuration 0x00000004 write-only UDMA_CFG_MASTEN Controller Master Enable [0:0] write-only CTLBASE DMA Channel Control Base Pointer 0x00000008 UDMA_CTLBASE_ADDR Channel Control Base Address [31:10] ALTBASE DMA Alternate Channel Control Base Pointer 0x0000000C UDMA_ALTBASE_ADDR Alternate Channel Address Pointer [31:0] WAITSTAT DMA Channel Wait-on-Request Status 0x00000010 UDMA_WAITSTAT_WAITREQ Channel [n] Wait Status [31:0] SWREQ DMA Channel Software Request 0x00000014 write-only UDMA_SWREQ Channel [n] Software Request [31:0] write-only USEBURSTSET DMA Channel Useburst Set 0x00000018 UDMA_USEBURSTSET_SET Channel [n] Useburst Set [31:0] USEBURSTCLR DMA Channel Useburst Clear 0x0000001C write-only UDMA_USEBURSTCLR_CLR Channel [n] Useburst Clear [31:0] write-only REQMASKSET DMA Channel Request Mask Set 0x00000020 UDMA_REQMASKSET_SET Channel [n] Request Mask Set [31:0] REQMASKCLR DMA Channel Request Mask Clear 0x00000024 write-only UDMA_REQMASKCLR_CLR Channel [n] Request Mask Clear [31:0] write-only ENASET DMA Channel Enable Set 0x00000028 UDMA_ENASET_SET Channel [n] Enable Set [31:0] ENACLR DMA Channel Enable Clear 0x0000002C write-only UDMA_ENACLR_CLR Clear Channel [n] Enable Clear [31:0] write-only ALTSET DMA Channel Primary Alternate Set 0x00000030 UDMA_ALTSET_SET Channel [n] Alternate Set [31:0] ALTCLR DMA Channel Primary Alternate Clear 0x00000034 write-only UDMA_ALTCLR_CLR Channel [n] Alternate Clear [31:0] write-only PRIOSET DMA Channel Priority Set 0x00000038 UDMA_PRIOSET_SET Channel [n] Priority Set [31:0] PRIOCLR DMA Channel Priority Clear 0x0000003C write-only UDMA_PRIOCLR_CLR Channel [n] Priority Clear [31:0] write-only ERRCLR DMA Bus Error Clear 0x0000004C UDMA_ERRCLR_ERRCLR uDMA Bus Error Status [0:0] CHASGN DMA Channel Assignment 0x00000500 UDMA_CHASGN Channel [n] Assignment Select [31:0] UDMA_CHASGN_PRIMARY Use the primary channel assignment 0x0 UDMA_CHASGN_SECONDARY Use the secondary channel assignment 0x1 CHIS DMA Channel Interrupt Status 0x00000504 UDMA_CHIS Channel [n] Interrupt Status [31:0] CHMAP0 DMA Channel Map Select 0 0x00000510 UDMA_CHMAP0_CH0SEL uDMA Channel 0 Source Select [3:0] UDMA_CHMAP0_CH1SEL uDMA Channel 1 Source Select [7:4] UDMA_CHMAP0_CH2SEL uDMA Channel 2 Source Select [11:8] UDMA_CHMAP0_CH3SEL uDMA Channel 3 Source Select [15:12] UDMA_CHMAP0_CH4SEL uDMA Channel 4 Source Select [19:16] UDMA_CHMAP0_CH5SEL uDMA Channel 5 Source Select [23:20] UDMA_CHMAP0_CH6SEL uDMA Channel 6 Source Select [27:24] UDMA_CHMAP0_CH7SEL uDMA Channel 7 Source Select [31:28] CHMAP1 DMA Channel Map Select 1 0x00000514 UDMA_CHMAP1_CH8SEL uDMA Channel 8 Source Select [3:0] UDMA_CHMAP1_CH9SEL uDMA Channel 9 Source Select [7:4] UDMA_CHMAP1_CH10SEL uDMA Channel 10 Source Select [11:8] UDMA_CHMAP1_CH11SEL uDMA Channel 11 Source Select [15:12] UDMA_CHMAP1_CH12SEL uDMA Channel 12 Source Select [19:16] UDMA_CHMAP1_CH13SEL uDMA Channel 13 Source Select [23:20] UDMA_CHMAP1_CH14SEL uDMA Channel 14 Source Select [27:24] UDMA_CHMAP1_CH15SEL uDMA Channel 15 Source Select [31:28] CHMAP2 DMA Channel Map Select 2 0x00000518 UDMA_CHMAP2_CH16SEL uDMA Channel 16 Source Select [3:0] UDMA_CHMAP2_CH17SEL uDMA Channel 17 Source Select [7:4] UDMA_CHMAP2_CH18SEL uDMA Channel 18 Source Select [11:8] UDMA_CHMAP2_CH19SEL uDMA Channel 19 Source Select [15:12] UDMA_CHMAP2_CH20SEL uDMA Channel 20 Source Select [19:16] UDMA_CHMAP2_CH21SEL uDMA Channel 21 Source Select [23:20] UDMA_CHMAP2_CH22SEL uDMA Channel 22 Source Select [27:24] UDMA_CHMAP2_CH23SEL uDMA Channel 23 Source Select [31:28] CHMAP3 DMA Channel Map Select 3 0x0000051C UDMA_CHMAP3_CH24SEL uDMA Channel 24 Source Select [3:0] UDMA_CHMAP3_CH25SEL uDMA Channel 25 Source Select [7:4] UDMA_CHMAP3_CH26SEL uDMA Channel 26 Source Select [11:8] UDMA_CHMAP3_CH27SEL uDMA Channel 27 Source Select [15:12] UDMA_CHMAP3_CH28SEL uDMA Channel 28 Source Select [19:16] UDMA_CHMAP3_CH29SEL uDMA Channel 29 Source Select [23:20] UDMA_CHMAP3_CH30SEL uDMA Channel 30 Source Select [27:24] UDMA_CHMAP3_CH31SEL uDMA Channel 31 Source Select [31:28] FLASH FLASH Memory Map for TM4C1233H6PGE 0x00000000 0 0x00040000 FLASH Memory ROM ROM Memory Map for TM4C1233H6PGE 0x01000000 0 0x00008c00 ROM Boot Loader/TivaWare SRAM SRAM Memory Map for TM4C1233H6PGE 0x20000000 0 0x00008000 SRAM