MB9AF34xL 1.7 MB9AF34xL 8 32 32 read-write 0x00000000 0x00000000 FLASH_IF Flash Memory FLASH_IF 0x40000000 0x4 0x8 registers 0x20 0xC registers 0x100 0x4 registers FRWTR Flash Read Wait Register 0x04 32 read-write 0x00000000 0x00000003 RWT Read Wait Cycle 0 1 read-write FSTR Flash Status Register 0x08 32 read-only 0x00000000 0x0000003F PGMS Flash Program Status 5 5 read-only SERS Flash Sector Erase Status 4 4 read-only ESPS Flash Erase Suspend Status 3 3 read-only CERS Flash Chip Erase Status 2 2 read-only HNG Flash Hang flag 1 1 read-only RDY Flash Rdy 0 0 read-only FICR Flash Interrupt Control Register 0x20 32 read-write 0x00000000 0x00000003 HANGIE HANG Interrupt Enable 1 1 read-write RDYIE RDY Interrupt Enable 0 0 read-write FISR Flash Interrupt Status Register 0x24 32 read-write 0x00000000 0x00000003 HANGIF HANG Interrupt Flag 1 1 read-write RDYIF RDY Interrupt Flag 0 0 read-write FICLR Flash Interrupt Clear Register 0x28 32 write-only 0x00000000 0x00000003 HANGC HANG Interrupt Clear 1 1 read-write RDYC RDY Interrupt Clear 0 0 read-write CRTRMM CR Trimming Data Mirror Register 0x100 32 read-only 0x00000000 0x00000000 TRMM CR Trimming Data Mirror 0 9 read-only CRG Clock Unit Registers CRG 0x40010000 0x0 0x1 registers 0x4 0x1 registers 0x8 0x6 registers 0x10 0x1 registers 0x14 0x1 registers 0x18 0x1 registers 0x1C 0x1 registers 0x20 0x1 registers 0x28 0x1 registers 0x30 0x1 registers 0x34 0x1 registers 0x38 0x1 registers 0x3C 0x1 registers 0x40 0x2 registers 0x44 0x1 registers 0x48 0x2 registers 0x4C 0x2 registers 0x50 0x2 registers 0x54 0x1 registers 0x60 0x1 registers 0x64 0x1 registers 0x68 0x1 registers CSV 0 OSC_PLL_WC_RTC 24 SCM_CTL System Clock Mode Control Register 0x0 8 read-write 0x00 0xFA RCS Master clock switch control bits 5 7 read-write PLLE PLL oscillation enable bit 4 4 read-write SOSCE Sub clock oscillation enable bit 3 3 read-write MOSCE Main clock oscillation enable bit 1 1 read-write SCM_STR System Clock Mode Status Register 0x4 8 read-only 0x00 0xFA RCM Master clock selection bits 5 7 read-only PLRDY PLL oscillation stable bit 4 4 read-only SORDY Sub clock oscillation stable bit 3 3 read-only MORDY Main clock oscillation stable bit 1 1 read-only BSC_PSR Base Clock Prescaler Register 0x10 8 read-write 0x00 0x07 BSR Base clock frequency division ratio setting bit 0 2 read-write APBC0_PSR APB0 Prescaler Register 0x14 8 read-write 0x00 0x03 APBC0 APB0 bus clock frequency division ratio setting bit 0 1 read-write APBC1_PSR APB1 Prescaler Register 0x18 8 read-write 0x80 0x93 APBC1EN APB1 clock enable bit 7 7 read-write APBC1RST APB1 bus reset control bit 4 4 read-write APBC1 APB1 bus clock frequency division ratio setting bit 0 1 read-write APBC2_PSR APB2 Prescaler Register 0x1C 8 read-write 0x80 0x93 APBC2EN APB2 clock enable bit 7 7 read-write APBC2RST APB2 bus reset control bit 4 4 read-write APBC2 APB2 bus clock frequency division ratio setting bit 0 1 read-write SWC_PSR Software Watchdog Clock Prescaler Register 0x20 8 read-write 0x00 0x03 TESTB TEST bit 7 7 read-write SWDS Software watchdog clock frequency division ratio setting bit 0 1 read-write TTC_PSR Trace Clock Prescaler Register 0x28 8 read-write 0x00 0x03 TTC Trace clock frequency division ratio setting bit 0 1 read-write CSW_TMR Clock Stabilization Wait Time Register 0x30 8 read-write 0x00 0x7F SOWT Sub clock stabilization wait time setup bit 4 6 read-write MOWT Main clock stabilization wait time setup bit 0 3 read-write PSW_TMR PLL Clock Stabilization Wait Time Setup Register 0x34 8 read-write 0x00 0x17 PINC PLL input clock select bit 4 4 read-write POWT PLL clock stabilization wait time setup bit 0 2 read-write PLL_CTL1 PLL Control Register 1 0x38 8 read-write 0x00 0xFF PLLK PLL input clock frequency division ratio setting bit 4 7 read-write PLLM PLL VCO clock frequency division ratio setting bit 0 3 read-write PLL_CTL2 PLL Control Register 2 0x3C 8 read-write 0x00 0x3F PLLN PLL feedback frequency division ratio setting bit 0 5 read-write DBWDT_CTL Debug Break Watchdog Timer Control Register 0x54 8 read-write 0x00 0xA0 DPHWBE HW-WDG debug mode break bit 7 7 read-write DPSWBE SW-WDG debug mode break bit 5 5 read-write INT_ENR Interrupt Enable Register 0x60 8 read-write 0x00 0x27 FCSE Anomalous frequency detection interrupt enable bit 5 5 read-write PCSE PLL oscillation stabilization completion interrupt enable bit 2 2 read-write SCSE Sub oscillation stabilization completion interrupt enable bit 1 1 read-write MCSE Main oscillation stabilization completion interrupt enable bit 0 0 read-write INT_STR Interrupt Status Register 0x64 8 read-only 0x00 0x27 FCSI Anomalous frequency detection interrupt status bit 5 5 read-only PCSI PLL oscillation stabilization completion interrupt status bit 2 2 read-only SCSI Sub oscillation stabilization completion interrupt status bit 1 1 read-only MCSI Main oscillation stabilization completion interrupt status bit 0 0 read-only INT_CLR Interrupt Clear Register 0x68 8 write-only 0x00 0x27 FCSC Anomalous frequency detection interrupt cause clear bit 5 5 write-only PCSC PLL oscillation stabilization completion interrupt cause clear bit 2 2 write-only SCSC Sub oscillation stabilization completion interrupt cause clear bit 1 1 write-only MCSC Main oscillation stabilization completion interrupt cause clear bit 0 0 write-only RST_STR Reset Cause Register 0xC 16 read-only 0x0001 0x01F3 SRST Software reset flag 8 8 read-only FCSR Flag for anomalous frequency detection reset 7 7 read-only CSVR Clock failure detection reset flag 6 6 read-only HWDG Hardware watchdog reset flag 5 5 read-only SWDG Software watchdog reset flag 4 4 read-only INITX INITX pin input reset flag 1 1 read-only PONR Power-on reset/low-voltage detection reset flag 0 0 read-only STB_CTL Standby Mode Control Register 0x8 32 read-write 0x00000000 0xFFFF0017 KEY Standby mode control write control bit 16 31 read-write SPL Standby pin level setting bit 4 4 read-write DSTM Deep standby mode select bit 2 2 read-write STM Standby mode selection bit 0 1 read-write CSV_CTL CSV control register 0x40 16 read-write 0x7003 0x7303 FCD FCS count cycle setting bits 12 14 read-write FCSRE FCS reset output enable bit 9 9 read-write FCSDE FCS function enable bit 8 8 read-write SCSVE Sub CSV function enable bit 1 1 read-write MCSVE Main CSV function enable bit 0 0 read-write CSV_STR CSV status register 0x44 8 read-only 0x00 0x03 SCMF Sub clock failure detection flag 1 1 read-only MCMF Main clock failure detection flag 0 0 read-only FCSWH_CTL Frequency detection window setting register 0x48 16 read-write 0xFFFF 0xFFFF FCSWL_CTL Frequency detection window setting register 0x4C 16 read-write 0x0000 0xFFFF FCSWD_CTL Frequency detection counter register 0x50 16 read-only 0x0000 0xFFFF CRTRIM CR Trimming Registers CRTRIM 0x4002E000 0x0 0x1 registers 0x4 0x2 registers 0xC 0x4 registers MCR_PSR High-speed CR oscillation Frequency Division Setup Register 0x0 8 read-write 0x01 0x03 CSR High-speed CR oscillation frequency division ratio setting bits 0 1 read-write MCR_FTRM High-speed CR oscillation Frequency Trimming Register 0x4 16 read-write 0x0180 0x03FF TRD Frequency trimming setup bits 0 9 read-write MCR_RLR High-Speed CR Oscillation Register Write-Protect Register 0xC 32 read-write 0x00000001 0xFFFFFFFF TRMLCK Register write-protect bits 0 31 read-write SWWDT Software Watchdog Timer SWWDT 0x40012000 0x0 0x4 registers 0x4 0x4 registers 0x8 0x1 registers 0xC 0x4 registers 0x10 0x1 registers 0xC00 0x4 registers SWDT 1 WDOGLOAD Software Watchdog Timer Load Register 0x0 32 read-write 0xFFFFFFFF 0xFFFFFFFF WDOGVALUE Software Watchdog Timer Value Register 0x4 32 read-only 0xFFFFFFFF 0xFFFFFFFF WDOGCONTROL Software Watchdog Timer Control Register 0x8 8 read-write 0x00 0x03 RESEN Reset enable bit of the software watchdog 1 1 read-write INTEN Interrupt and counter enable bit of the software watchdog 0 0 read-write WDOGINTCLR Software Watchdog Timer Clear Register 0xC 32 read-write 0xFFFFFFFF 0xFFFFFFFF WDOGRIS Software Watchdog Timer Interrupt Status Register 0x10 8 read-only 0x00 0x01 RIS Software watchdog interrupt status bit 0 0 read-only WDOGLOCK Software Watchdog Timer Lock Register 0xC00 32 read-write 0x00000000 0xFFFFFFFF HWWDT Hardware Watchdog Timer HWWDT 0x40011000 0x0 0x4 registers 0x4 0x4 registers 0x8 0x4 registers 0xC 0x1 registers 0x10 0x1 registers 0xC00 0x4 registers WDG_LDR Hardware Watchdog Timer Load Register 0x0 32 read-write 0x0000FFFF 0xFFFFFFFF WDG_VLR Hardware Watchdog Timer Value Register 0x4 32 read-only 0x00000000 0xFFFFFFFF WDG_CTL Hardware Watchdog Timer Control Register 0x8 32 read-write 0x00000003 0x00000003 RESEN Hardware watchdog reset enable bit 1 1 read-write INTEN Hardware watchdog interrupt and counter enable bit 0 0 read-write WDG_ICL Hardware Watchdog Timer Clear Register 0xC 8 read-write 0xFF 0x00 WDG_RIS Hardware Watchdog Timer Interrupt Status Register 0x10 1 read-only 0xFF 0x00 RIS Hardware watchdog interrupt status bit 0 0 read-only WDG_LCK Hardware Watchdog Timer Lock Register 0xC00 32 read-write 0x00000001 0xFFFFFFFF DTIM Dual Timer DTIM 0x40015000 0x0 0x1C registers 0x20 0x1C registers DTIM_QDU 6 TIMER1LOAD Load Register DualTimer1 0x0 32 read-write 0x00000000 0xFFFFFFFF TIMER1VALUE Value Register 0x4 32 read-only 0xFFFFFFFF 0xFFFFFFFF TIMER1CONTROL Control Register 0x8 32 read-write 0x00000020 0x000000EF TimerEn Enable bit 7 7 read-write TimerMode Mode bit 6 6 read-write IntEnable Interrupt enable bit 5 5 read-write TimerPre Prescale bits 2 3 read-write TimerSize Counter size bit 1 1 read-write OneShot One-shot mode bit 0 0 read-write TIMER1INTCLR Interrupt Clear Register 0xC 32 write-only 0x00000000 0x00000000 TIMER1RIS Interrupt Status Register 0x10 32 read-only 0x00000000 0x00000001 TIMER1RIS Interrupt Status Register bit 0 0 read-only TIMER1MIS Masked Interrupt Status Register 0x14 32 read-only 0x00000000 0x00000001 TIMER1MIS Masked Interrupt Status bit 0 0 read-only TIMER1BGLOAD Background Load Register 0x18 32 read-write 0x00000000 0xFFFFFFFF TIMER2LOAD Load Register 0x20 TIMER2VALUE Value Register 0x24 TIMER2CONTROL Control Register 0x28 TIMER2INTCLR Interrupt Clear Register 0x2C TIMER2RIS Interrupt Status Register 0x30 TIMER2MIS Masked Interrupt Status Register 0x34 TIMER2BGLOAD Background Load Register 0x38 BTIOSEL03 Base Timer I/O Select BTIOSEL03 0x40025100 0x0 0x2 registers BTSEL0123 I/O Select Register 0x00 16 read-write 0x0000 0xFF00 SEL23_ I/O select bits for Ch.2/Ch.3 12 15 read-write SEL01_ I/O select bits for Ch.0/Ch.1 8 11 read-write BTIOSEL47 Base Timer I/O Select BTIOSEL47 0x40025300 0x0 0x2 registers 0x0 0x2 registers BTSEL4567 I/O Select Register 0x00 16 read-write 0x0000 0xFF00 SEL67_ I/O select bits for Ch.6/Ch.7 12 15 read-write SEL45_ I/O select bits for Ch.4/Ch.5 8 11 read-write SBSSR Software-based Simultaneous Startup Register SBSSR 0x40025F00 0x0FC 0x2 registers BTSSSR Software-based Simultaneous Startup Register 0xFC 16 write-only 0x0000 0x0000 SSSR15 Bit15 of BTSSSR 15 15 write-only SSSR14 Bit14 of BTSSSR 14 14 write-only SSSR13 Bit13 of BTSSSR 13 13 write-only SSSR12 Bit12 of BTSSSR 12 12 write-only SSSR11 Bit11 of BTSSSR 11 11 write-only SSSR10 Bit10 of BTSSSR 10 10 write-only SSSR9 Bit9 of BTSSSR 9 9 write-only SSSR8 Bit8 of BTSSSR 8 8 write-only SSSR7 Bit7 of BTSSSR 7 7 write-only SSSR6 Bit6 of BTSSSR 6 6 write-only SSSR5 Bit5 of BTSSSR 5 5 write-only SSSR4 Bit4 of BTSSSR 4 4 write-only SSSR3 Bit3 of BTSSSR 3 3 write-only SSSR2 Bit2 of BTSSSR 2 2 write-only SSSR1 Bit1 of BTSSSR 1 1 write-only SSSR0 Bit0 of BTSSSR 0 0 write-only BT0 Base Timer 0 BT0 0x40025000 0x0 0x2 registers 0x4 0x2 registers 0x8 0x2 registers 0xC 0x2 registers 0x10 0x2 registers BTIM0_7 31 PWM_TMCR Timer Control Register PWM 0x0C 16 read-write 0x0000 0x7F7F CKS2_0 Count clock selection bit 12 14 read-write RTGEN Restart enable bit 11 11 read-write PMSK Pulse output mask bit 10 10 read-write EGS Trigger input edge selection bits 8 9 read-write FMD Timer function selection bits 4 6 read-write OSEL Output polarity specification bit 3 3 read-write MDSE Mode selection bit 2 2 read-write CTEN Count operation enable bit 1 1 read-write STRG Software trigger bit 0 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write 0x00 0x01 CKS3 Count clock selection bit 0 0 read-write PWM_STC Status Control Register PWM 0x10 8 read-write 0x00 0x77 TGIE Trigger interrupt request enable bit 6 6 read-write DTIE Duty match interrupt request enable bit 5 5 read-write UDIE Underflow interrupt request enable bit 4 4 read-write TGIR Trigger interrupt request bit 2 2 read-write DTIR Duty match interrupt request bit 1 1 read-write UDIR Underflow interrupt request bit 0 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x00 16 read-write 0x0000 0x0000 PWM_PDUT PWM Duty Set Register PWM 0x04 16 read-write 0x0000 0x0000 PWM_TMR Timer Register PWM 0x08 16 read-only 0x0000 0xFFFF PPG_TMCR Timer Control Register PPG 0x0C 16 read-write 0x0000 0x7F7F CKS2_0 Count clock selection bit 12 14 read-write RTGEN Restart enable bit 11 11 read-write PMSK Pulse output mask bit 10 10 read-write EGS Trigger input edge selection bits 8 9 read-write FMD Timer function selection bits 4 6 read-write OSEL Output polarity specification bit 3 3 read-write MDSE Mode selection bit 2 2 read-write CTEN Count operation enable bit 1 1 read-write STRG Software trigger bit 0 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write 0x00 0x01 CKS3 Count clock selection bit 1 1 read-write PPG_STC Status Control Register PPG 0x10 8 read-write 0x00 0x55 TGIE Trigger interrupt request enable bit 6 6 read-write UDIE Underflow interrupt request enable bit 4 4 read-write TGIR Trigger interrupt request bit 2 2 read-write UDIR Underflow interrupt request bit 0 0 read-write PPG_PRLL LOW Width Reload Register PPG 0x00 16 read-write 0x0000 0x0000 PPG_PRLH HIGH Width Reload Register PPG 0x04 16 read-write 0x0000 0x0000 PPG_TMR Timer Register PPG 0x08 16 read-only 0x0000 0xFFFF RT_TMCR Timer Control Register RT 0x0C 16 read-write 0x0000 0x73FF CKS2_0 Count clock selection bit 12 14 read-write EGS Trigger input edge selection bits 8 9 read-write T32 32-bit timer selection bit 7 7 read-write FMD Timer function selection bits 4 6 read-write OSEL Output polarity specification bit 3 3 read-write MDSE Mode selection bit 2 2 read-write CTEN Timer enable bit 1 1 read-write STRG Software trigger bit 0 0 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write 0x00 0x01 CKS3 Count clock selection bit 0 0 read-write RT_STC Status Control Register RT 0x10 8 read-write 0x00 0x55 TGIE Trigger interrupt request enable bit 6 6 read-write UDIE Underflow interrupt request enable bit 4 4 read-write TGIR Trigger interrupt request bit 2 2 read-write UDIR Underflow interrupt request bit 0 0 read-write RT_PCSR PWM Cycle Set Register RT 0x00 16 read-write 0x0000 0x0000 RT_TMR Timer Register RT 0x08 16 read-only 0x0000 0x0000 PWC_TMCR Timer Control Register PWC 0x0C 16 read-write 0x0000 0x77F6 CKS2_0 Count clock selection bit 12 14 read-write EGS Measurement edge selection bits 8 10 read-write T32 32-bit timer selection bit 7 7 read-write FMD Timer function selection bits 4 6 read-write MDSE Mode selection bit 2 2 read-write CTEN Timer enable bit 1 1 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write 0x00 0x01 CKS3 Count clock selection bit 0 0 read-write PWC_STC Status Control Register PWC 0x10 8 read-write 0x00 0xD5 ERR Error flag bit 7 7 read-only EDIE Measurement completion interrupt request enable bit 6 6 read-write OVIE Overflow interrupt request enable bit 4 4 read-write EDIR Measurement completion interrupt request bit 2 2 read-only OVIR Overflow interrupt request bit 0 0 read-write PWC_DTBF Data Buffer Register PWC 0x04 16 read-only 0x0000 0xFFFF BT1 0x40025040 BT2 0x40025080 BT3 0x400250C0 BT4 0x40025200 BT5 0x40025240 BT6 0x40025280 BT7 0x400252C0 WC Watch Counter WC 0x4003A000 0x0 0x3 registers 0x10 0x2 registers 0x14 0x1 registers WCRD Watch Counter Read Register 0x0 8 read-only 0x00 0x3F CTR counter value 0 5 read-only WCRL Watch Counter Reload Register 0x01 8 read-write 0x00 0x3F RLC reload value 0 5 read-write WCCR Watch Counter Control Register 0x02 8 read-write 0x00 0xCF WCEN Watch counter operation enable bit 7 7 read-write WCOP Watch counter operating state flag 6 6 read-only CS Count clock select bits 2 3 read-write WCIE Interrupt request enable bit 1 1 read-write WCIF Interrupt request flag bit 0 0 read-write CLK_SEL Clock Selection Register 0x10 16 read-write 0x0000 0x0101 SEL_OUT Output clock selection bit 8 8 read-write SEL_IN Input clock selection bit 0 0 read-write CLK_EN Division Clock Enable Register 0x14 8 read-write 0x00 0x03 CLK_EN_R Division clock enable read bit 1 1 read-write CLK_EN Division clock enable bit 0 0 read-write ADC0 ADC0 Registers ADC0 0x40027000 0x0 0x2 registers 0x8 0x2 registers 0xC 0x4 registers 0x10 0x2 registers 0x14 0x2 registers 0x18 0x2 registers 0x1C 0x4 registers 0x20 0x1 registers 0x24 0x1 registers 0x26 0x2 registers 0x28 0x2 registers 0x2C 0x2 registers 0x30 0x2 registers 0x34 0x1 registers 0x38 0x2 registers 0x3C 0x2 registers ADC0 25 ADCR A/D Control Register 0x1 8 read-write 0x00 0xEF SCIF Scan conversion interrupt request bit 7 7 read-write PCIF Priority conversion interrupt request bit 6 6 read-write CMPIF Conversion result comparison interrupt request bit 5 5 read-write SCIE Scan conversion interrupt enable bit 3 3 read-write PCIE Priority conversion interrupt enable bit 2 2 read-write CMPIE Conversion result comparison interrupt enable bit 1 1 read-write OVRIE FIFO overrun interrupt enable bit 0 0 read-write ADSR A/D Status Register 0x0 8 read-write 0x00 0xC7 ADSTP A/D conversion forced stop bit 7 7 read-write FDAS FIFO data placement selection bit 6 6 read-write PCNS Priority conversion pending flag 2 2 read-write PCS Priority conversion status flag 1 1 read-write SCS Scan conversion status flag 0 0 read-write SCCR Scan Conversion Control Register 0x9 8 read-write 0x80 0xF7 SEMP Scan conversion FIFO empty bit 7 7 read-only SFUL Scan conversion FIFO full bit 6 6 read-only SOVR Scan conversion overrun flag 5 5 read-write SFCLR Scan conversion FIFO clear bit 4 4 read-write RPT Scan conversion repeat bit 2 2 read-write SHEN Scan conversion timer start enable bit 1 1 read-write SSTR Scan conversion start bit 0 0 read-write SFNS Scan Conversion FIFO Stage Count Setup Register 0x8 8 read-write 0x00 0x0F SFS Scan conversion FIFO stage count setting bit 0 3 read-write SCFD Scan Conversion FIFO Data Register 0xC 32 read-only 0x00000000 0xFFF0131F SD Scan conversion result 20 31 read-only INVL A/D conversion result disable bit 12 12 read-only RS Scan conversion start factor 8 9 read-only CS Conversion input channel bits 0 4 read-only SCIS3 Scan Conversion Input Selection Register 3 0x11 8 read-write 0x00 0xFF AN31 Bit7 of SCIS3 7 7 read-write AN30 Bit6 of SCIS3 6 6 read-write AN29 Bit5 of SCIS3 5 5 read-write AN28 Bit4 of SCIS3 4 4 read-write AN27 Bit3 of SCIS3 3 3 read-write AN26 Bit2 of SCIS3 2 2 read-write AN25 Bit1 of SCIS3 1 1 read-write AN24 Bit0 of SCIS3 0 0 read-write SCIS2 Scan Conversion Input Selection Register 2 0x10 8 read-write 0x00 0xFF AN23 Bit7 of SCIS2 7 7 read-write AN22 Bit6 of SCIS2 6 6 read-write AN21 Bit5 of SCIS2 5 5 read-write AN20 Bit4 of SCIS2 4 4 read-write AN19 Bit3 of SCIS2 3 3 read-write AN18 Bit2 of SCIS2 2 2 read-write AN17 Bit1 of SCIS2 1 1 read-write AN16 Bit0 of SCIS2 0 0 read-write SCIS1 Scan Conversion Input Selection Register 1 0x15 8 read-write 0x00 0xFF AN15 Bit7 of SCIS1 7 7 read-write AN14 Bit6 of SCIS1 6 6 read-write AN13 Bit5 of SCIS1 5 5 read-write AN12 Bit4 of SCIS1 4 4 read-write AN11 Bit3 of SCIS1 3 3 read-write AN10 Bit2 of SCIS1 2 2 read-write AN9 Bit1 of SCIS1 1 1 read-write AN8 Bit0 of SCIS1 0 0 read-write SCIS0 Scan Conversion Input Selection Register 0 0x14 8 read-write 0x00 0xFF AN7 Bit7 of SCIS0 7 7 read-write AN6 Bit6 of SCIS0 6 6 read-write AN5 Bit5 of SCIS0 5 5 read-write AN4 Bit4 of SCIS0 4 4 read-write AN3 Bit3 of SCIS0 3 3 read-write AN2 Bit2 of SCIS0 2 2 read-write AN1 Bit1 of SCIS0 1 1 read-write AN0 Bit0 of SCIS0 0 0 read-write PFNS Priority Conversion FIFO Stage Count Setup Register 0x18 8 read-write 0x00 0x33 TEST Test bits 4 5 read-only PFS Priority conversion FIFO stage count setting bits 0 1 read-write PCCR Priority Conversion Control Register 0x19 8 read-write 0x80 0xFF PEMP Priority conversion FIFO empty bit 7 7 read-only PFUL Priority conversion FIFO full bit 6 6 read-only POVR Priority conversion overrun flag 5 5 read-write PFCLR Priority conversion FIFO clear bit 4 4 read-write ESCE External trigger analog input selection bit 3 3 read-write PEEN Priority conversion external start enable bit 2 2 read-write PHEN Priority conversion timer start enable bit 1 1 read-write PSTR Priority conversion start bit 0 0 read-write PCFD Priority Conversion FIFO Data Register 0x1C 32 read-only 0x00000000 0xFFF0131F PD Priority conversion result 20 31 read-only INVL A/D conversion result disable bit 12 12 read-only RS Scan conversion start factor 8 9 read-only PC Conversion input channel bits 0 4 read-only PCIS Priority Conversion Input Selection Register 0x20 8 read-write 0x00 0xFF P2A Priority level 2 analog input selection 3 7 read-write P1A Priority level 1 analog input selection 0 2 read-write CMPCR A/D Comparison Control Register 0x24 8 read-write 0x00 0xFF CMPEN Conversion result comparison function operation enable bit 7 7 read-write CMD Comparison mode 1 5 6 read-write CCH Comparison mode 0 0 4 read-write CMPD A/D Comparison Value Setup Register 0x26 16 read-write 0x0000 0xFFC0 CMAD A/D conversion result value setting bits 6 15 read-write ADSS3 Sampling Time Selection Register 3 0x29 8 read-write 0x00 0xFF TS31 Bit7 of ADSS3 7 7 read-write TS30 Bit6 of ADSS3 6 6 read-write TS29 Bit5 of ADSS3 5 5 read-write TS28 Bit4 of ADSS3 4 4 read-write TS27 Bit3 of ADSS3 3 3 read-write TS26 Bit2 of ADSS3 2 2 read-write TS25 Bit1 of ADSS3 1 1 read-write TS24 Bit0 of ADSS3 0 0 read-write ADSS2 Sampling Time Selection Register 2 0x28 8 read-write 0x00 0xFF TS23 Bit7 of ADSS2 7 7 read-write TS22 Bit6 of ADSS2 6 6 read-write TS21 Bit5 of ADSS2 5 5 read-write TS20 Bit4 of ADSS2 4 4 read-write TS19 Bit3 of ADSS2 3 3 read-write TS18 Bit2 of ADSS2 2 2 read-write TS17 Bit1 of ADSS2 1 1 read-write TS16 Bit0 of ADSS2 0 0 read-write ADSS1 Sampling Time Selection Register 1 0x2D 8 read-write 0x00 0xFF TS15 Bit7 of ADSS1 7 7 read-write TS14 Bit6 of ADSS1 6 6 read-write TS13 Bit5 of ADSS1 5 5 read-write TS12 Bit4 of ADSS1 4 4 read-write TS11 Bit3 of ADSS1 3 3 read-write TS10 Bit2 of ADSS1 2 2 read-write TS9 Bit1 of ADSS1 1 1 read-write TS8 Bit0 of ADSS1 0 0 read-write ADSS0 Sampling Time Selection Register 0 0x2C 8 read-write 0x00 0xFF TS7 Bit7 of ADSS0 7 7 read-write TS6 Bit6 of ADSS0 6 6 read-write TS5 Bit5 of ADSS0 5 5 read-write TS4 Bit4 of ADSS0 4 4 read-write TS3 Bit3 of ADSS0 3 3 read-write TS2 Bit2 of ADSS0 2 2 read-write TS1 Bit1 of ADSS0 1 1 read-write TS0 Bit0 of ADSS0 0 0 read-write ADST1 Sampling Time Setup Register 1 0x30 8 read-write 0x10 0xFF STX1 Sampling time N times setting bits 5 7 read-write ST Sampling time setting bits 0 4 read-write ADST0 Sampling Time Setup Register 0 0x31 8 read-write 0x10 0xFF STX0 Sampling time N times setting bits 5 7 read-write ST Sampling time setting bits 0 4 read-write ADCT Comparison Time Setup Register 0x34 8 read-write 0x07 0x07 CT Compare clock frequency division ratio setting bits 0 7 read-write PRTSL Priority Conversion Timer Trigger Selection Register 0x38 8 read-write 0x00 0x0F PRTSL Priority conversion timer trigger selection bit 0 3 read-write SCTSL Scan Conversion Timer Trigger Selection Register 0x39 8 read-write 0x00 0x0F SCTSL Scan conversion timer trigger selection bit 0 3 read-write ADCEN A/D Operation Enable Setup Register 0x3C 16 read-write 0xFF00 0xFF03 ENBLTIME Basic cycle selection bit 8 15 read-write READY A/D operation enable state bit 1 1 read-only ENBL A/D operation enable bit 0 0 read-write ADC1 0x40027100 ADC1 26 EXTI External Interrupt and NMI Control EXTI 0x40030000 0x0 0x2 registers 0x4 0x2 registers 0x8 0x2 registers 0xC 0x4 registers 0x14 0x1 registers 0x18 0x1 registers EXTINT0_7 4 EXTINT8_15 5 ENIR Enable Interrupt Request Register 0x0 16 read-write 0x0000 0x807F EN15 Bit15 of ENIR 15 15 read-write EN6 Bit6 of ENIR 6 6 read-write EN5 Bit5 of ENIR 5 5 read-write EN4 Bit4 of ENIR 4 4 read-write EN3 Bit3 of ENIR 3 3 read-write EN2 Bit2 of ENIR 2 2 read-write EN1 Bit1 of ENIR 1 1 read-write EN0 Bit0 of ENIR 0 0 read-write EIRR External Interrupt Request Register 0x4 16 read-only 0x0000 0x0000 ER15 Bit15 of EIRR 15 15 read-only ER6 Bit6 of EIRR 6 6 read-only ER5 Bit5 of EIRR 5 5 read-only ER4 Bit4 of EIRR 4 4 read-only ER3 Bit3 of EIRR 3 3 read-only ER2 Bit2 of EIRR 2 2 read-only ER1 Bit1 of EIRR 1 1 read-only ER0 Bit0 of EIRR 0 0 read-only EICL External Interrupt Clear Register 0x8 16 read-write 0xFFFF 0x807F ECL15 Bit15 of EICL 15 15 read-write ECL6 Bit6 of EICL 6 6 read-write ECL5 Bit5 of EICL 5 5 read-write ECL4 Bit4 of EICL 4 4 read-write ECL3 Bit3 of EICL 3 3 read-write ECL2 Bit2 of EICL 2 2 read-write ECL1 Bit1 of EICL 1 1 read-write ECL0 Bit0 of EICL 0 0 read-write ELVR External Interrupt Level Register 0xC 32 read-write 0x00000000 0xC0003FFF LB15 Bit31 of ELVR 31 31 read-write LA15 Bit30 of ELVR 30 30 read-write LB6 Bit13 of ELVR 13 13 read-write LA6 Bit12 of ELVR 12 12 read-write LB5 Bit11 of ELVR 11 11 read-write LA5 Bit10 of ELVR 10 10 read-write LB4 Bit9 of ELVR 9 9 read-write LA4 Bit8 of ELVR 8 8 read-write LB3 Bit7 of ELVR 7 7 read-write LA3 Bit6 of ELVR 6 6 read-write LB2 Bit5 of ELVR 5 5 read-write LA2 Bit4 of ELVR 4 4 read-write LB1 Bit3 of ELVR 3 3 read-write LA1 Bit2 of ELVR 2 2 read-write LB0 Bit1 of ELVR 1 1 read-write LA0 Bit0 of ELVR 0 0 read-write NMIRR Non Maskable Interrupt Request Register 0x14 8 read-only 0x00 0x01 NR NMI interrupt request detection bit 0 0 read-only NMICL Non Maskable Interrupt Clear Register 0x18 8 read-write 0x01 0x01 NCL NMI interrupt cause clear bit 0 0 read-write INTREQ Interrupts INTREQ 0x40031000 0x0 0x4 registers 0xB 0x1 registers 0xC 0x4 registers 0x10 0xC4 registers 0x210 0x8 registers DRQSEL DMA Request Selection Register 0x0 32 read-write 0x0 0xFFFFFFFF EXINT3 The interrupt signal of the external interrupt ch.3 is output as a transfer request to the DMAC (including extension). 31 31 read-write EXINT2 The interrupt signal of the external interrupt ch.2 is output as a transfer request to the DMAC (including extension). 30 30 read-write EXINT1 The interrupt signal of the external interrupt ch.1 is output as a transfer request to the DMAC (including extension). 29 29 read-write EXINT0 The interrupt signal of the external interrupt ch.0 is output as a transfer request to the DMAC (including extension). 28 28 read-write MFS7TX The transmission interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC (including extension). 27 27 read-write MFS7RX The reception interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC (including extension). 26 26 read-write MFS6TX The transmission interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC (including extension). 25 25 read-write MFS6RX The reception interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC (including extension). 24 24 read-write MFS5TX The transmission interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC (including extension). 23 23 read-write MFS5RX The reception interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC (including extension). 22 22 read-write MFS4TX The transmission interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC (including extension). 21 21 read-write MFS4RX The reception interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC (including extension). 20 20 read-write MFS3TX The transmission interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC (including extension). 19 19 read-write MFS3RX The reception interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC (including extension). 18 18 read-write MFS2TX The transmission interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC (including extension). 17 17 read-write MFS2RX The reception interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC (including extension). 16 16 read-write MFS1TX The transmission interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC (including extension). 15 15 read-write MFS1RX The reception interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC (including extension). 14 14 read-write MFS0TX The transmission interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC (including extension). 13 13 read-write MFS0RX The reception interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC (including extension). 12 12 read-write IRQ0BT6 The IRQ0 interrupt signal of the base timer ch.6 is output as a transfer request to the DMAC. 11 11 read-write IRQ0BT4 The IRQ0 interrupt signal of the base timer ch.4 is output as a transfer request to the DMAC. 10 10 read-write IRQ0BT2 The IRQ0 interrupt signal of the base timer ch.3 is output as a transfer request to the DMAC. 9 9 read-write IRQ0BT0 The IRQ0 interrupt signal of the base timer ch.0 is output as a transfer request to the DMAC. 8 8 read-write ADCSCAN2 The scan conversion interrupt signal of the A/D converter unit 2 is output as a transfer request to the DMAC. 7 7 read-write ADCSCAN1 The scan conversion interrupt signal of the A/D converter unit 1 is output as a transfer request to the DMAC. 6 6 read-write ADCSCAN0 The scan conversion interrupt signal of the A/D converter unit 0 is output as a transfer request to the DMAC. 5 5 read-write USBEP5 The EP5 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC. 4 4 read-write USBEP4 The EP4 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC. 3 3 read-write USBEP3 The EP3 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC. 2 2 read-write USBEP2 The EP2 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC. 1 1 read-write USBEP1 The EP1 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC. 0 0 read-write ODDPKS USB ch.0 Odd Packet Size DMA Enable Register 0xB 8 read-write 0x0 0x1F ODDPKS4 "When the transfer destination address of DMAC is USB.EP5DT, the bit width of the last transfer data is converted to Byte." 4 4 read-write ODDPKS3 "When the transfer destination address of DMAC is USB.EP4DT, the bit width of the last transfer data is converted to Byte." 3 3 read-write ODDPKS2 "When the transfer destination address of DMAC is USB.EP3DT, the bit width of the last transfer data is converted to Byte." 2 2 read-write ODDPKS1 "When the transfer destination address of DMAC is USB.EP2DT, the bit width of the last transfer data is converted to Byte." 1 1 read-write ODDPKS0 "When the transfer destination address of DMAC is USB.EP1DT, the bit width of the last transfer data is converted to Byte." 0 0 read-write IRQCMODE Interrupt Factor Vector Relocate Setting Register 0xC 32 read-write 0x0 0x1 IRQCMODE Interrupt Factor Vector Relocate Setting 0 0 read-write EXC02MON EXC02 batch read register 0x10 32 read-only 0x0 0x3 HWINT Hardware watchdog timer interrupt request 1 1 read-only NMI External NMIX pin interrupt request 0 0 read-only IRQ00MON IRQ00 Batch Read Register 0x14 32 read-only 0x0 0x1 FCSINT Anomalous frequency detection by CSV interrupt request 0 0 read-only IRQ01MON IRQ01 Batch Read Register 0x18 32 read-only 0x0 0x1 SWWDTINT Software watchdog timer interrupt request 0 0 read-only IRQ02MON IRQ02 Batch Read Register 0x1C 32 read-only 0x0 0x1 LVDINT Low voltage detection (LVD) interrupt request 0 0 read-only IRQ04MON IRQ04 Batch Read Register 0x24 32 read-only 0x0 0x7F EXTINT6 Interrupt request on external interrupt ch.6 6 6 read-only EXTINT5 Interrupt request on external interrupt ch.5 5 5 read-only EXTINT4 Interrupt request on external interrupt ch.4 4 4 read-only EXTINT3 Interrupt request on external interrupt ch.3 3 3 read-only EXTINT2 Interrupt request on external interrupt ch.2 2 2 read-only EXTINT1 Interrupt request on external interrupt ch.1 1 1 read-only EXTINT0 Interrupt request on external interrupt ch.0 0 0 read-only IRQ05MON IRQ05 Batch Read Register 0x28 32 read-only 0x0 0x80 EXTINT7 Interrupt request on external interrupt ch.15 7 7 read-only IRQ06MON IRQ06 Batch Read Register 0x2C 32 read-only 0x0 0x03 TIMINT2 Dual timer 2 interrupt request 1 1 read-only TIMINT1 Dual timer 1 interrupt request 0 0 read-only IRQ07MON IRQ07 Batch Read Register 0x30 32 read-only 0x0 0x1 MFSINT Reception interrupt request on MFS ch.0 0 0 read-only IRQ08MON IRQ08 Batch Read Register 0x34 32 read-only 0x0 0x3 MFSINT1 Status interrupt request on MFS ch.0 1 1 read-only MFSINT0 Transmission interrupt request on MFS ch.0 0 0 read-only IRQ09MON IRQ09 Batch Read Register 0x38 32 read-only 0x0 0x1 MFSINT Reception interrupt request on MFS ch.1 0 0 read-only IRQ10MON IRQ10 Batch Read Register 0x3C 32 read-only 0x0 0x3 MFSINT1 Status interrupt request on MFS ch.1 1 1 read-only MFSINT0 Transmission interrupt request on MFS ch.1 0 0 read-only IRQ11MON IRQ11 Batch Read Register 0x40 32 read-only 0x0 0x1 MFSINT Reception interrupt request on MFS ch.2 0 0 read-only IRQ12MON IRQ12 Batch Read Register 0x44 32 read-only 0x0 0x3 MFSINT1 Status interrupt request on MFS ch.2 1 1 read-only MFSINT0 Transmission interrupt request on MFS ch.2 0 0 read-only IRQ13MON IRQ13 Batch Read Register 0x48 32 read-only 0x0 0x1 MFSINT Reception interrupt request on MFS ch.3 0 0 read-only IRQ14MON IRQ14 Batch Read Register 0x4C 32 read-only 0x0 0x3 MFSINT1 Status interrupt request on MFS ch.3 1 1 read-only MFSINT0 Transmission interrupt request on MFS ch.3 0 0 read-only IRQ15MON IRQ15 Batch Read Register 0x50 32 read-only 0x0 0x1 MFSINT Reception interrupt request on MFS ch.4 0 0 read-only IRQ16MON IRQ16 Batch Read Register 0x54 32 read-only 0x0 0x3 MFSINT1 Status interrupt request on MFS ch.4 1 1 read-only MFSINT0 Transmission interrupt request on MFS ch.4 0 0 read-only IRQ17MON IRQ17 Batch Read Register 0x58 32 read-only 0x0 0x1 MFSINT Reception interrupt request on MFS ch.5 0 0 read-only IRQ18MON IRQ18 Batch Read Register 0x5C 32 read-only 0x0 0x3 MFSINT1 Status interrupt request on MFS ch.5 1 1 read-only MFSINT0 Transmission interrupt request on MFS ch.5 0 0 read-only IRQ19MON IRQ19 Batch Read Register 0x60 32 read-only 0x0 0x1 MFSINT Reception interrupt request on MFS ch.6 0 0 read-only IRQ20MON IRQ20 Batch Read Register 0x64 32 read-only 0x0 0x3 MFSINT1 Status interrupt request on MFS ch.6 1 1 read-only MFSINT0 Transmission interrupt request on MFS ch.6 0 0 read-only IRQ21MON IRQ21 Batch Read Register 0x68 32 read-only 0x0 0x1 MFSINT Reception interrupt request on MFS ch.7 0 0 read-only IRQ22MON IRQ22 Batch Read Register 0x6C 32 read-only 0x0 0x3 MFSINT1 Status interrupt request on MFS ch.7 1 1 read-only MFSINT0 Transmission interrupt request on MFS ch.7 0 0 read-only IRQ24MON IRQ24 Batch Read Register 0x74 32 read-only 0x0 0x3F RTCINT RTC interrupt request 5 5 read-only WCINT Watch counter interrupt request 4 4 read-only UPLLINT Stabilization wait completion interrupt request for USB or USB/Ethernet PLL oscillation. 3 3 read-only MPLLINT Stabilization wait completion interrupt request for main PLL oscillation 2 2 read-only SOSCINT Stabilization wait completion interrupt request for sub-clock oscillation 1 1 read-only MOSCINT Stabilization wait completion interrupt request for main clock oscillation 0 0 read-only IRQ25MON IRQ25 Batch Read Register 0x78 32 read-only 0x0 0xF ADCINT3 Conversion result comparison interrupt request in the corresponding A/D unit 0. 3 3 read-only ADCINT2 FIFO overrun interrupt request in the corresponding A/D unit 0. 2 2 read-only ADCINT1 Scan conversion interrupt request in the corresponding A/D unit 0. 1 1 read-only ADCINT0 Priority conversion interrupt request in the corresponding A/D unit 0. 0 0 read-only IRQ26MON IRQ26 Batch Read Register 0x7C 32 read-only 0x0 0xF ADCINT3 Conversion result comparison interrupt request in the corresponding A/D unit 1 3 3 read-only ADCINT2 FIFO overrun interrupt request in the corresponding A/D unit 1 2 2 read-only ADCINT1 Scan conversion interrupt request in the corresponding A/D unit 1 1 1 read-only ADCINT0 Priority conversion interrupt request in the corresponding A/D unit 1 0 0 read-only IRQ31MON IRQ31 Batch Read Register 0x90 32 read-only 0x0 0xFFFF BTINT15 IRQ1 interrupt request on the base timer ch.7 15 15 read-only BTINT14 IRQ0 interrupt request on the base timer ch.7 14 14 read-only BTINT13 IRQ1 interrupt request on the base timer ch.6 13 13 read-only BTINT12 IRQ0 interrupt request on the base timer ch.6 12 12 read-only BTINT11 IRQ1 interrupt request on the base timer ch.5 11 11 read-only BTINT10 IRQ0 interrupt request on the base timer ch.5 10 10 read-only BTINT9 IRQ1 interrupt request on the base timer ch.4 9 9 read-only BTINT8 IRQ0 interrupt request on the base timer ch.4 8 8 read-only BTINT7 IRQ1 interrupt request on the base timer ch.3 7 7 read-only BTINT6 IRQ0 interrupt request on the base timer ch.3 6 6 read-only BTINT5 IRQ1 interrupt request on the base timer ch.2 5 5 read-only BTINT4 IRQ0 interrupt request on the base timer ch.2 4 4 read-only BTINT3 IRQ1 interrupt request on the base timer ch.1 3 3 read-only BTINT2 IRQ0 interrupt request on the base timer ch.1 2 2 read-only BTINT1 IRQ1 interrupt request on the base timer ch.0 1 1 read-only BTINT0 IRQ0 interrupt request on the base timer ch.0 0 0 read-only IRQ34MON IRQ34 Batch Read Register 0x9C 32 read-only 0x0 0x1F USB0INT4 Endpoint 5 DRQ interrupt request on the USB ch.0 4 4 read-only USB0INT3 Endpoint 4 DRQ interrupt request on the USB ch.0 3 3 read-only USB0INT2 Endpoint 3 DRQ interrupt request on the USB ch.0 2 2 read-only USB0INT1 Endpoint 2 DRQ interrupt request on the USB ch.0 1 1 read-only USB0INT0 Endpoint 1 DRQ interrupt request on the USB ch.0 0 0 read-only IRQ35MON IRQ35 Batch Read Register 0xA0 32 read-only 0x0 0x3F USB0INT5 "Status (SOFIRQ, CMPIRO) interrupt request on the USB ch.0 " 5 5 read-only USB0INT4 "Status (DIRQ, URIRQ, RWKIRQ, CNNIRQ) interrupt request on the USB ch.0 " 4 4 read-only USB0INT3 Status (SPK) interrupt request on the USB ch.0 3 3 read-only USB0INT2 "Status (SUSP, SOF, BRST, CONF, WKUP) interrupt request on the USB ch.0 " 2 2 read-only USB0INT1 Endpoint 0 DRQO interrupt request on the USB ch.0 1 1 read-only USB0INT0 Endpoint 0 DRQI interrupt request on the USB ch.0 0 0 read-only IRQ36MON IRQ36 Batch Read Register 0xA4 32 read-only 0x0 0x20 RCEC0INT Interrupt request for HDMI-CEC/Remote Control Reception ch.0 5 5 read-only IRQ37MON IRQ37 Batch Read Register 0xA8 32 read-only 0x0 0x40 RCEC1INT Interrupt request for HDMI-CEC/Remote Control Reception ch.1 6 6 read-only IRQ38MON IRQ38 Batch Read Register 0xAC 32 read-only 0x0 0x1 DMAINT Interrupt request on DMA ch.0. 0 0 read-only IRQ39MON IRQ39 Batch Read Register 0xB0 32 read-only 0x0 0x1 DMAINT Interrupt request on DMA ch.1. 0 0 read-only IRQ40MON IRQ40 Batch Read Register 0xB4 32 read-only 0x0 0x1 DMAINT Interrupt request on DMA ch.2. 0 0 read-only IRQ41MON IRQ41 Batch Read Register 0xB8 32 read-only 0x0 0x1 DMAINT Interrupt request on DMA ch.3. 0 0 read-only IRQ42MON IRQ42 Batch Read Register 0xBC 32 read-only 0x0 0x1 DMAINT Interrupt request on DMA ch.4. 0 0 read-only IRQ43MON IRQ43 Batch Read Register 0xC0 32 read-only 0x0 0x1 DMAINT Interrupt request on DMA ch.5. 0 0 read-only IRQ44MON IRQ44 Batch Read Register 0xC4 32 read-only 0x0 0x1 DMAINT Interrupt request on DMA ch.6. 0 0 read-only IRQ45MON IRQ45 Batch Read Register 0xC8 32 read-only 0x0 0x1 DMAINT Interrupt request on DMA ch.7. 0 0 read-only IRQ47MON IRQ47 Batch Read Register 0xD0 32 read-only 0x0 0x0800 FLASHINT "RDY, HANG interrupt request for flash " 11 11 read-only RCINTSEL0 Interrupt Factor Selection Register 0 0x210 32 read-write 0x0 0xFFFFFFFF INTSEL3 select the interrupt factor of the interrupt vector No.22. 24 31 read-write INTSEL2 select the interrupt factor of the interrupt vector No.21. 16 23 read-write INTSEL1 select the interrupt factor of the interrupt vector No.20. 8 15 read-write INTSEL0 select the interrupt factor of the interrupt vector No.19. 0 7 read-write RCINTSEL1 Interrupt Factor Selection Register 1 0x214 32 read-write 0x0 0xFFFFFFFF INTSEL7 select the interrupt factor of the interrupt vector No.26. 24 31 read-write INTSEL6 select the interrupt factor of the interrupt vector No.25. 16 23 read-write INTSEL5 select the interrupt factor of the interrupt vector No.24. 8 15 read-write INTSEL4 select the interrupt factor of the interrupt vector No.23. 0 7 read-write GPIO General-purpose I/O ports GPIO 0x40033000 0x0 0x740 registers PFR0 Port function setting register 0 0x0 32 read-write 0x0000001F 0x0000FC1F PF Bit15 of PFR0 15 15 read-write PE Bit14 of PFR0 14 14 read-write PD Bit13 of PFR0 13 13 read-write PC Bit12 of PFR0 12 12 read-write PB Bit11 of PFR0 11 11 read-write PA Bit10 of PFR0 10 10 read-write P4 Bit4 of PFR0 4 4 read-write P3 Bit3 of PFR0 3 3 read-write P2 Bit2 of PFR0 2 2 read-write P1 Bit1 of PFR0 1 1 read-write P0 Bit0 of PFR0 0 0 read-write PFR1 Port function setting register 1 0x4 32 read-write 0x00000000 0x000003BF P9 Bit9 of PFR1 9 9 read-write P8 Bit8 of PFR1 8 8 read-write P7 Bit7 of PFR1 7 7 read-write P5 Bit5 of PFR1 5 5 read-write P4 Bit4 of PFR1 4 4 read-write P3 Bit3 of PFR1 3 3 read-write P2 Bit2 of PFR1 2 2 read-write P1 Bit1 of PFR1 1 1 read-write P0 Bit0 of PFR1 0 0 read-write PFR2 Port function setting register 2 0x8 32 read-write 0x00000000 0x0000000E P3 Bit3 of PFR2 3 3 read-write P2 Bit2 of PFR2 2 2 read-write P1 Bit1 of PFR2 1 1 read-write PFR3 Port function setting register 3 0xC 32 read-write 0x00000000 0x0000FE0F PF Bit15 of PFR3 15 15 read-write PE Bit14 of PFR3 14 14 read-write PD Bit13 of PFR3 13 13 read-write PC Bit12 of PFR3 12 12 read-write PB Bit11 of PFR3 11 11 read-write PA Bit10 of PFR3 10 10 read-write P9 Bit9 of PFR3 9 9 read-write P3 Bit3 of PFR3 3 3 read-write P2 Bit2 of PFR3 2 2 read-write P1 Bit1 of PFR3 1 1 read-write P0 Bit0 of PFR3 0 0 read-write PFR4 Port function setting register 4 0x10 32 read-write 0x00000000 0x00007EC0 PE Bit14 of PFR4 14 14 read-write PD Bit13 of PFR4 13 13 read-write PC Bit12 of PFR4 12 12 read-write PB Bit11 of PFR4 11 11 read-write PA Bit10 of PFR4 10 10 read-write P9 Bit9 of PFR4 9 9 read-write P7 Bit7 of PFR4 7 7 read-write P6 Bit6 of PFR4 6 6 read-write PFR5 Port function setting register 5 0x14 32 read-write 0x00000000 0x00000007 P2 Bit2 of PFR5 2 2 read-write P1 Bit1 of PFR5 1 1 read-write P0 Bit0 of PFR5 0 0 read-write PFR6 Port function setting register 6 0x18 32 read-write 0x00000000 0x00000007 P2 Bit2 of PFR6 2 2 read-write P1 Bit1 of PFR6 1 1 read-write P0 Bit0 of PFR6 0 0 read-write PFR8 Port function setting register 8 0x20 32 read-write 0x00000000 0x00000003 P1 Bit1 of PFR8 1 1 read-write P0 Bit0 of PFR8 0 0 read-write PFRE Port function setting register E 0x38 32 read-write 0x00000000 0x0000000D P3 Bit3 of PFRE 3 3 read-write P2 Bit2 of PFRE 2 2 read-write P0 Bit0 of PFRE 0 0 read-write PCR0 Pull-up Setting Register 0 0x100 PCR1 Pull-up Setting Register 1 0x104 PCR2 Pull-up Setting Register 2 0x108 PCR3 Pull-up Setting Register 3 0x10C PCR4 Pull-up Setting Register 4 0x110 PCR5 Pull-up Setting Register 5 0x114 PCR6 Pull-up Setting Register 6 0x118 PCRE Pull-up Setting Register E 0x138 DDR0 Port input/output direction setting register 0 0x200 32 read-write 0x00000000 0x0000FC1F PF Bit15 of DDR0 15 15 read-write PE Bit14 of DDR0 14 14 read-write PD Bit13 of DDR0 13 13 read-write PC Bit12 of DDR0 12 12 read-write PB Bit11 of DDR0 11 11 read-write PA Bit10 of DDR0 10 10 read-write P4 Bit4 of DDR0 4 4 read-write P3 Bit3 of DDR0 3 3 read-write P2 Bit2 of DDR0 2 2 read-write P1 Bit1 of DDR0 1 1 read-write P0 Bit0 of DDR0 0 0 read-write DDR1 Port input/output direction setting register 1 0x204 DDR2 Port input/output direction setting register 2 0x208 DDR3 Port input/output direction setting register 3 0x20C DDR4 Port input/output direction setting register 4 0x210 DDR5 Port input/output direction setting register 5 0x214 DDR6 Port input/output direction setting register 6 0x218 DDR8 Port input/output direction setting register 8 0x220 DDRE Port input/output direction setting register E 0x238 PDIR0 Port input data register 0 0x300 PDIR1 Port input data register 1 0x304 PDIR2 Port input data register 2 0x308 PDIR3 Port input data register 3 0x30C PDIR4 Port input data register 4 0x310 PDIR5 Port input data register 5 0x314 PDIR6 Port input data register 6 0x318 PDIR8 Port input data register 8 0x320 PDIRE Port input data register E 0x338 PDOR0 Port output data register 0 0x400 PDOR1 Port output data register 1 0x404 PDOR2 Port output data register 2 0x408 PDOR3 Port output data register 3 0x40C PDOR4 Port output data register 4 0x410 PDOR5 Port output data register 5 0x414 PDOR6 Port output data register 6 0x418 PDOR8 Port output data register 8 0x420 PDORE Port output data register E 0x438 ADE Analog input setting register 0x500 32 read-write 0x000703BF 0x000703BF AN18 Bit18 of ADE 18 18 read-write AN17 Bit17 of ADE 17 17 read-write AN16 Bit16 of ADE 16 16 read-write AN9 Bit9 of ADE 9 9 read-write AN8 Bit8 of ADE 8 8 read-write AN7 Bit7 of ADE 7 7 read-write AN5 Bit5 of ADE 5 5 read-write AN4 Bit4 of ADE 4 4 read-write AN3 Bit3 of ADE 3 3 read-write AN2 Bit2 of ADE 2 2 read-write AN1 Bit1 of ADE 1 1 read-write AN0 Bit0 of ADE 0 0 read-write SPSR Special port setting register 0x580 32 read-write 0x00000005 0x0000001F USB0C USBch0 pin setting bit 4 4 read-write MAINXC Main clock(oscillation) pin setting bit 2 3 read-write SUBXC Sub clock(oscillation) pin setting bit 0 1 read-write EPFR00 Extended pin function setting register 00 0x600 32 read-write 0x00030000 0x000302F7 JTAGEN1S JTAG function select bit1 17 17 read-write JTAGEN0B JTAG function select bit0 16 16 read-write USBP0E USBch0 function select bit 9 9 read-write SUBOUTE Sub clock divide output function select bit 6 7 read-write RTCCOE RTC clock output select bit 4 5 read-write CROUTE Internal high-speed CR oscillation output function select bit 1 2 read-write NMIS NMIX function select bit 0 0 read-write EPFR04 Extended pin function setting register 04 0x610 32 read-write 0x00000000 0x3F3C3F7C TIOB3S TIOB3 input select bit 28 29 read-write TIOA3E TIOA3E output select bit 26 27 read-write TIOA3S TIOA3 input select bit 24 25 read-write TIOB2S TIOB2 input select bit 20 21 read-write TIOA2E TIOA2 output select bit 18 19 read-write TIOB1S TIOB1 input select bit 12 13 read-write TIOA1E TIOA1E output select bit 10 11 read-write TIOA1S TIOA1 input select bit 8 9 read-write TIOB0S TIOB0 input select bit 4 6 read-write TIOA0E TIOA0 output select bit 2 3 read-write EPFR05 Extended pin function setting register 05 0x614 32 read-write 0x00000000 0x3F3C3F3C TIOB7S TIOB7 input select Bit 28 29 read-write TIOA7E TIOA7E output select bit 26 27 read-write TIOA7S TIOA7 input select bit 24 25 read-write TIOB6S TIOB6 input select bit 20 21 read-write TIOA6E TIOA6 output select bit 18 19 read-write TIOB5S TIOB5 input select bit 12 13 read-write TIOA5E TIOA5E output select bit 10 11 read-write TIOA5S TIOA5 input select bit 8 9 read-write TIOB4S TIOB4 input select bit 4 5 read-write TIOA4E TIOA4 output select bit 2 3 read-write EPFR06 Extended pin function setting register 06 0x618 32 read-write 0x00000000 0xC0003FFF EINT15S External interrupt 15 input select bit 30 31 read-write EINT06S External interrupt 6 input select bit 12 13 read-write EINT05S External interrupt 5 input select bit 10 11 read-write EINT04S External interrupt 4 input select bit 8 9 read-write EINT03S External interrupt 3 input select bit 6 7 read-write EINT02S External interrupt 2 input select bit 4 5 read-write EINT01S External interrupt 1 input select bit 2 3 read-write EINT00S External interrupt 0 input select bit 0 1 read-write EPFR07 Extended pin function setting register 07 0x61C 32 read-write 0x00000000 0x0FFFFFF0 SCK3B SCK3 input/output select bit 26 27 read-write SOT3B SOT3B input/output select bit 24 25 read-write SIN3S SIN3S input select bit 22 23 read-write SCK2B SCK2 input/output select bit 20 21 read-write SOT2B SOT2B input/output select bit 18 19 read-write SIN2S SIN2S input select bit 16 17 read-write SCK1B SCK1 input/output select bit 14 15 read-write SOT1B SCK1B input/output select bit 12 13 read-write SIN1S SIN1S input select bit 10 11 read-write SCK0B SCK0 input/output select bit 8 9 read-write SOT0B SOT0B input/output select bit 6 7 read-write SIN0S SIN0S input select bit 4 5 read-write EPFR08 Extended pin function setting register 08 0x620 32 read-write 0x00000000 0x0FFFFFF0 SCK7B SCK7 input/output select bit 26 27 read-write SOT7B SOT7B input/output select bit 24 25 read-write SIN7S SIN7S input select bit 22 23 read-write SCK6B SCK6 input/output select bit 20 21 read-write SOT6B SOT6B input/output select bit 18 19 read-write SIN6S SIN6S input select bit 16 17 read-write SCK5B SCK5 input/output select bit 14 15 read-write SOT5B SOT5B input/output select bit 12 13 read-write SIN5S SIN5S input select bit 10 11 read-write SCK4B SCK4 input/output select bit 8 9 read-write SOT4B SOT4B input/output select bit 6 7 read-write SIN4S SIN4S input select bit 4 5 read-write EPFR09 Extended pin function setting register 09 0x624 32 read-write 0x00000000 0x000FF000 ADTRG1S ADTRG1 input select bit 16 19 read-write ADTRG0S ADTRG0 input select bit 12 15 read-write EPFR14 Extended pin function setting register 14 0x638 32 read-write 0x00000000 0xC0000000 CEC1B CEC1 Input/Output Select bit 31 31 read-write CEC0B CEC0 Input/Output Select bit 30 30 read-write PZR0 Port Pseudo Open Drain Setting Register 0 0x700 32 read-write 0x00000000 0x00001C00 PC Bit12 of PZR0 12 12 read-write PB Bit11 of PZR0 11 11 read-write PA Bit10 of PZR0 10 10 read-write PZR4 Port Pseudo Open Drain Setting Register 4 0x710 32 read-write 0x00000000 0x00007000 PE Bit14 of PZR4 14 14 read-write PD Bit13 of PZR4 13 13 read-write PC Bit12 of PZR4 12 12 read-write PZR6 Port Pseudo Open Drain Setting Register 6 0x718 32 read-write 0x00000000 0x00000001 P0 Bit0 of PZR6 0 0 read-write HDMICEC0 HDMI-CEC ch.0 HDMICEC0 0x40034000 0x0 0x1 registers 0x4 0x1 registers 0x8 0x1 registers 0xC 0x1 registers 0x40 0x2 registers 0x44 0x2 registers 0x49 0x1 registers 0x4C 0x2 registers 0x50 0x2 registers 0x54 0x2 registers 0x58 0x2 registers 0x5C 0x2 registers 0x61 0x1 registers 0x64 0x2 registers HDMICEC0 36 TXCTRL Transmission Control Register 0x0 8 read-write 0x00 0x3D IBREN Bus error detection interrupt enable bit 5 5 read-write ITSTEN transmission status interrupt enable bit 4 4 read-write EOM EOM setting bit 3 3 read-write START START setting bit 2 2 read-write TXEN Transmission operation enable bit 0 0 read-write TXDATA Transmission Data Register 0x4 8 read-write 0x00 0xFF TXDATA Transmission Data 0 7 read-write TXSTS Transmission Status Register 0x8 8 read-write 0x00 0x31 IBR Bus error detection interrupt request bit 5 5 read-write ITST Transmission status interrupt request bit 4 4 read-write ACKSV ACK cycle value bit 0 0 read-write SFREE Signal Free Time Setting Register 0xC 8 read-write 0x00 0x0F SFREE Signal free time setting bits 0 3 read-write RCST Reception Interrupt Control Register 0x40 8 read-write 0x00 0xFF STIE Start bit interrupt enable bit 7 7 read-write ACKIE ACK interrupt enable bit 6 6 read-write OVFIE Counter overflow interrupt enable bit 5 5 read-write OVFSEL Counter overflow detection condition setting bit 4 4 read-write ST Start bit detection bit 3 3 read-write ACK ACK: ACK detection bit 2 2 read-write EOM EOM detection bit 1 1 read-write OVF Counter overflow detection bit 0 0 read-write RCCR Reception Control Register 0x41 8 read-write 0x00 0x8F THSEL Threshold selection bit 7 7 read-write ADRCE Address comparison enable bit 3 3 read-write MOD1 Operation mode setting bits 2 2 read-write MOD0 Operation mode setting bits 1 1 read-write EN Operation enable bit 0 0 read-write RCDAHW "H" Width Setting Register A 0x44 8 read-write 0x00 0xFF RCDAHW "H" Width Setting A 0 7 read-write RCSHW Start Bit "H" Width Setting Register 0x45 8 read-write 0x00 0xFF RCSHW Start Bit "H" Width Setting 0 7 read-write RCDBHW "H" Width Setting Register B 0x49 8 read-write 0x00 0xFF RCDBHW "H" Width Setting B 0 7 read-write RCADR2 Device Address Setting Register 2 0x4C 8 read-write 0x00 0x1F RCADR2 Device Address 2 0 4 read-write RCADR1 Device Address Setting Register 1 0x4D 8 read-write 0x00 0x1F RCADR1 Device Address 1 0 4 read-write RCDTHL Data Save Register (High-Low) 0x50 8 read-only 0x00 0xFF RCDTHL RCDTHL 0 7 read-only RCDTHH Data Save Register (High-High) 0x51 8 read-only 0x00 0xFF RCDTHH RCDTHH 0 7 read-only RCDTLL Data Save Register (Low-Low) 0x54 8 read-only 0x00 0xFF RCDTLL RCDTLL 0 7 read-only RCDTLH Data Save Register (Low-High) 0x55 8 read-only 0x00 0xFF RCDTLH RCDTLH 0 7 read-only RCCKD Clock Division Setting Register 0x58 16 read-write 0x0000 0x1FFF CKSEL Operating clock selection bit 12 12 read-write CKDIV Operating clock division setting bits 0 11 read-write RCRHW Repeat Code "H" Width Setting Register 0x5C 8 read-write 0x00 0xFF RCRHW "Repeat code "H" width setting bits" 0 7 read-write RCRC Repeat Code Interrupt Control Register 0x5D 8 read-write 0x00 0x11 RCIE Repeat Code Interrupt enable bit 4 4 read-write RC Repeat code detection flag bit 0 0 read-write RCLE Data Bit Width Violation Control Register 0x61 8 read-write 0x00 0xFB LELIE Maximum data bit width violation interrupt enable bit 7 7 read-write LESIE Minimum data bit width violation interrupt enable bit 6 6 read-write LELE Maximum data bit width violation detection enable bit 5 5 read-write LESE Minimum data bit width violation detection enable bit 4 4 read-write EPE Error pulse output enable bit 3 3 read-write LEL Maximum data bit width violation detection flag bit 1 1 read-write LES Minimum data bit width violation detection flag bit 0 0 read-write RCLESW Minimum Data Bit Width Setting Register 0x64 8 read-write 0x00 0xFF RCLESW Minimum data bit width setting bits 0 7 read-write RCLELW Maximum Data Bit Width Setting Register 0x65 8 read-write 0x00 0xFF RCLELW Maximum data bit width setting bits 0 7 read-write HDMICEC1 0x40034100 HDMICEC1 37 LVD Low-voltage Detection LVD 0x40035000 0x0 0x2 registers 0x4 0x1 registers 0x8 0x1 registers 0xC 0x5 registers LVD 2 LVD_CTL Low-voltage Detection Voltage Control Register 0x0 16 read-write 0x8010 0xFCFC LVDRE Low-voltage detection reset operation enable bit 15 15 read-write SVHR Low-voltage detection reset voltage setting bits 10 14 read-write LVDIE Low-voltage detection interrupt enable bit 7 7 read-write SVHI Low-voltage detection interrupt voltage setting bits 2 6 read-write LVD_STR Low-voltage Detection Interrupt Register 0x4 8 read-only 0x00 0x80 LVDIR Low-voltage detection interrupt bit 7 7 read-only LVD_CLR Low-voltage Detection Interrupt Clear Register 0x8 8 read-write 0x80 0x80 LVDCL Low-voltage detection interrupt clear bit 7 7 read-write LVD_RLR Low-voltage Detection Voltage Protection Register 0xC 32 read-write 0x00000001 0xFFFFFFFF LVDLCK Low-voltage Detection Voltage Control Register protection bits 0 31 read-write LVD_STR2 Low-voltage Detection Circuit Status Register 0x10 8 read-only 0x40 0xC0 LVDIRDY Low-voltage detection interrupt status flag 7 7 read-only LVDRRDY Low-voltage detection reset status flag 6 6 read-only DS Low Power Consumption Mode DS 0x40035100 0x0 0x1 registers 0x4 0x1 registers 0x700 0x1 registers 0x704 0x1 registers 0x708 0x2 registers 0x70C 0x2 registers 0x710 0x1 registers 0x714 0x1 registers 0x800 0x16 registers REG_CTL Sub Oscillation Circuit Power Supply Control Register 0x0 8 read-write 0x04 0x06 ISUBSEL Sub oscillation circuit current setting bits 1 2 read-write RCK_CTL Sub Clock Control Register 0x4 8 read-write 0x01 0x03 CECCKE CEC clock control bit 1 1 read-write RTCCKE RTC clock control bit 0 0 read-write PMD_CTL RTC Mode Control Register 0x700 8 read-write 0x00 0x01 RTCE RTC mode control bit 0 0 read-write WRFSR Deep Standby Return Cause Register 1 0x704 8 read-write 0x00 0x03 WLVDH Low-voltage detection reset return bit 1 1 read-write WINITX INITX pin input reset return bit 0 0 read-write WIFSR Deep Standby Return Cause Register 2 0x708 16 read-only 0x0000 0x033F WCEC1I CEC ch.1 interrupt return bit 9 9 read-only WCEC0I CEC ch.0 interrupt return bit 8 8 read-only WUI3 WKUP pin input return bit 3 5 5 read-only WUI2 WKUP pin input return bit 2 4 4 read-only WUI1 WKUP pin input return bit 1 3 3 read-only WUI0 WKUP pin input return bit 0 2 2 read-only WLVDI LVD interrupt return bit 1 1 read-only WRTCI RTC interrupt return bit 0 0 read-only WIER Deep Standby Return Enable Register 0x70C 16 read-write 0x0000 0x033B WCEC1E HDMI-CEC/ Remote Control Reception ch.1 interrupt return enable bit 9 9 read-write WCEC0E HDMI-CEC/ Remote Control Reception ch.0 interrupt return enable bit 8 8 read-write WUI3E WKUP pin input return enable bit 3 5 5 read-write WUI2E WKUP pin input return enable bit 2 4 4 read-write WUI1E WKUP pin input return enable bit 1 3 3 read-write WLVDE LVD interrupt return enable bit 1 1 read-write WRTCE RTC interrupt return enable bit 0 0 read-write WILVR WKUP Pin Input Level Register 0x710 8 read-write 0x00 0x07 WUI3LV WKUP pin input level select bit 3 2 2 read-write WUI2LV WKUP pin input level select bit 2 1 1 read-write WUI1LV WKUP pin input level select bit 1 0 0 read-write DSRAMR Deep Standby RAM Retention Register 0x714 8 read-write 0x00 0x03 SRAMR On-chip SRAM retention control bits 0 1 read-write BUR01 Backup Registers from 1 0x800 8 read-write 0x00 0xFF BUR02 Backup Registers from 2 0x801 8 read-write 0x00 0xFF BUR03 Backup Registers from 3 0x802 8 read-write 0x00 0xFF BUR04 Backup Registers from 4 0x803 8 read-write 0x00 0xFF BUR05 Backup Registers from 5 0x804 8 read-write 0x00 0xFF BUR06 Backup Registers from 6 0x805 8 read-write 0x00 0xFF BUR07 Backup Registers from 7 0x806 8 read-write 0x00 0xFF BUR08 Backup Registers from 8 0x807 8 read-write 0x00 0xFF BUR09 Backup Registers from 9 0x808 8 read-write 0x00 0xFF BUR10 Backup Registers from 10 0x809 8 read-write 0x00 0xFF BUR11 Backup Registers from 11 0x80A 8 read-write 0x00 0xFF BUR12 Backup Registers from 12 0x80B 8 read-write 0x00 0xFF BUR13 Backup Registers from 13 0x80C 8 read-write 0x00 0xFF BUR14 Backup Registers from 14 0x80D 8 read-write 0x00 0xFF BUR15 Backup Registers from 15 0x80E 8 read-write 0x00 0xFF BUR16 Backup Registers from 16 0x80F 8 read-write 0x00 0xFF MFS0 Multi-function Serial Interface 0 MFS0 0x40038000 0x0 0x2 registers 0x4 0x2 registers 0x8 0x2 registers 0xC 0x2 registers 0x10 0x2 registers 0x1D 0x1 registers MFS0RX 7 MFS0TX 8 UART_SCR Serial Control Register UART 0x1 8 read-write 0x00 0x9F UPCL Programmable Clear bit 7 7 read-write RIE Received interrupt enable bit 4 4 read-write TIE Transmit interrupt enable bit 3 3 read-write TBIE Transmit bus idle interrupt enable bit 2 2 read-write RXE Received operation enable bit 1 1 read-write TXE Transmission operation enable bit 0 0 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write 0x00 0xFD MD Operation mode set bit 5 7 read-write WUCR Wake-up control bit 4 4 read-write SBL Stop bit length select bit 3 3 read-write BDS Transfer direction select bit 2 2 read-write SOE Serial data output enable bit 0 0 read-write UART_SSR Serial Status Register UART 0x5 8 read-write 0x03 0xBF REC Received error flag clear bit 7 7 read-write PE Parity error flag bit (only functions in operation mode 0) 5 5 read-only FRE Framing error flag bit 4 4 read-only ORE Overrun error flag bit 3 3 read-only RDRF Received data full flag bit 2 2 read-only TDRE Transmit data empty flag bit 1 1 read-only TBI Transmit bus idle flag 0 0 read-only UART_ESCR Extended Communication Control Register UART 0x4 8 read-write 0x00 0xFF FLWEN Flow control enable bit 7 7 read-write ESBL Extension stop bit length select bit 6 6 read-write INV Inverted serial data format bit 5 5 read-write PEN Parity enable bit (only functions in operation mode 0) 4 4 read-write P Parity select bit (only functions in operation mode 0) 3 3 read-write L Data length select bit 0 2 read-write UART_RDR Received Data Register UART 0x8 16 read-only 0x0000 0x01FF UART_TDR Transmit Data Register UART 0x8 16 write-only 0x01FF 0x01FF UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write 0x0000 0xFFFF EXT External clock select bit 15 15 read-write BGR1 Baud Rate Generator Registers 1 8 14 read-write BGR0 Baud Rate Generator Registers 0 0 7 read-write CSIO_SCR Serial Control Register CSIO 0x1 8 read-write 0x00 0xFF UPCL Programmable clear bit 7 7 read-write MS Master/Slave function select bit 6 6 read-write SPI SPI corresponding bit 5 5 read-write RIE Received interrupt enable bit 4 4 read-write TIE Transmit interrupt enable bit 3 3 read-write TBIE Transmit bus idle interrupt enable bit 2 2 read-write RXE Data received enable bit 1 1 read-write TXE Data transmission enable bit 0 0 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write 0x00 0xFF MD Operation mode set bits 5 7 read-write WUCR Wake-up control bit 4 4 read-write SCINV Serial clock invert bit 3 3 read-write BDS Transfer direction select bit 2 2 read-write SCKE Master mode serial clock output enable bit 1 1 read-write SOE Serial data output enable bit 0 0 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write 0x03 0x8F REC Received error flag clear bit 7 7 read-write ORE Overrun error flag bit 3 3 read-only RDRF Received data full flag bit 2 2 read-only TDRE Transmit data empty flag bit 1 1 read-only TBI Transmit bus idle flag bit 0 0 read-only CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write 0x00 0x9F SOP Serial output pin set bit 7 7 read-write WT Data transmit/received wait select bits 3 4 read-write L Data length select bits 0 2 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only 0x0000 0x01FF CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only 0x01FF 0x01FF CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write 0x0000 0x7FFF BGR1 Baud Rate Generator Registers 1 8 14 read-write BGR0 Baud Rate Generator Registers 0 0 7 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write 0x00 0xFF MSS Master/slave select bit 7 7 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 6 read-write ACKE Data byte acknowledge enable bit 5 5 read-write WSEL Wait selection bit 4 4 read-write CNDE Condition detection interrupt enable bit 3 3 read-write INTE Interrupt enable bit 2 2 read-write BER Bus error flag bit 1 1 read-only INT interrupt flag bit 0 0 read-write I2C_SMR Serial Mode Register I2C 0x0 8 read-write 0x00 0xFC MD operation mode set bits 5 7 read-write WUCR Wake-up control bit 4 4 read-write RIE Received interrupt enable bit 3 3 read-write TIE Transmit interrupt enable bit 2 2 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write 0x00 0xFF FBT First byte bit 7 7 read-only RACK Acknowledge flag bit 6 6 read-only RSA Reserved address detection bit 5 5 read-only TRX Data direction bit 4 4 read-only AL Arbitration lost bit 3 3 read-only RSC Iteration start condition check bit 2 2 read-write SPC Stop condition check bit 1 1 read-write BB Bus state bit 0 0 read-only I2C_SSR Serial Status Register I2C 0x5 8 read-write 0x03 0xFF REC Received error flag clear bit 7 7 read-write TSET Transmit empty flag set bit 6 6 read-write DMA DMA mode enable bit 5 5 read-write TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 4 read-write ORE Overrun error flag bit 3 3 read-only RDRF Received data full flag bit 2 2 read-only TDRE Transmit data empty flag bit 1 1 read-only TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 0 read-only I2C_RDR Received Data Register I2C 0x8 16 read-only 0x0000 0x00FF I2C_TDR Transmit Data Register I2C 0x8 16 write-only 0x00FF 0x00FF I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write 0x7F 0xFF EN I2C interface operation enable bit 7 7 read-write SM Slave address mask bits 0 6 read-write I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write 0x00 0xFF SAEN Slave address enable bit 7 7 read-write SA 7-bit slave address 0 6 read-write I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write 0x0000 0x7FFF BGR1 Baud Rate Generator Registers 1 8 14 read-write BGR0 Baud Rate Generator Registers 0 0 7 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write 0x0C 0x3F SDAS SDA status bit 5 5 read-write SCLS SCL status bit 4 4 read-write SDAC SDA output control bit 3 3 read-write SCLC SCL output control bit 2 2 read-write SOCE Serial output enabled bit 1 1 read-write BEC Bus error control bit 0 0 read-write MFS1 0x40038100 MFS1RX 9 MFS1TX 10 MFS2 0x40038200 MFS2RX 11 MFS2TX 12 MFS3 0x40038300 MFS3RX 13 MFS3TX 14 MFS4 Multi-function Serial Interface 4 MFS4 0x40038400 0x0 0x2 registers 0x4 0x2 registers 0x8 0x2 registers 0xC 0x2 registers 0x10 0x2 registers 0x14 0x2 registers 0x18 0x2 registers 0x1D 0x1 registers MFS4RX 15 MFS4TX 16 UART_SCR Serial Control Register UART 0x1 8 read-write 0x00 0x9F UPCL Programmable Clear bit 7 7 read-write RIE Received interrupt enable bit 4 4 read-write TIE Transmit interrupt enable bit 3 3 read-write TBIE Transmit bus idle interrupt enable bit 2 2 read-write RXE Received operation enable bit 1 1 read-write TXE Transmission operation enable bit 0 0 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write 0x00 0xFD MD Operation mode set bit 5 7 read-write WUCR Wake-up control bit 4 4 read-write SBL Stop bit length select bit 3 3 read-write BDS Transfer direction select bit 2 2 read-write SOE Serial data output enable bit 0 0 read-write UART_SSR Serial Status Register UART 0x5 8 read-write 0x03 0xBF REC Received error flag clear bit 7 7 read-write PE Parity error flag bit (only functions in operation mode 0) 5 5 read-only FRE Framing error flag bit 4 4 read-only ORE Overrun error flag bit 3 3 read-only RDRF Received data full flag bit 2 2 read-only TDRE Transmit data empty flag bit 1 1 read-only TBI Transmit bus idle flag 0 0 read-only UART_ESCR Extended Communication Control Register UART 0x4 8 read-write 0x00 0xFF FLWEN Flow control enable bit 7 7 read-write ESBL Extension stop bit length select bit 6 6 read-write INV Inverted serial data format bit 5 5 read-write PEN Parity enable bit (only functions in operation mode 0) 4 4 read-write P Parity select bit (only functions in operation mode 0) 3 3 read-write L Data length select bit 0 2 read-write UART_RDR Received Data Register UART 0x8 16 read-only 0x0000 0x01FF UART_TDR Transmit Data Register UART 0x8 16 write-only 0x01FF 0x01FF UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write 0x0000 0xFFFF EXT External clock select bit 15 15 read-write BGR1 Baud Rate Generator Registers 1 8 14 read-write BGR0 Baud Rate Generator Registers 0 0 7 read-write UART_FCR1 FIFO Control Register 1 UART 0x15 8 read-write 0x04 0x1F FLSTE Re-transmission data lost detect enable bit 4 4 read-write FRIIE Received FIFO idle detection enable bit 3 3 read-write FDRQ Transmit FIFO data request bit 2 2 read-write FTIE Transmit FIFO interrupt enable bit 1 1 read-write FSEL FIFO select bit 0 0 read-write UART_FCR0 FIFO Control Register 0 UART 0x14 8 read-write 0x00 0x7F FLST FIFO re-transmit data lost flag bit 6 6 read-only FLD FIFO pointer reload bit 5 5 read-write FSET FIFO pointer save bit 4 4 read-write FCL2 FIFO2 reset bit 3 3 read-write FCL1 FIFO1 reset bit 2 2 read-write FE2 FIFO2 operation enable bit 1 1 read-write FE1 FIFO1 operation enable bit 0 0 read-write UART_FBYTE1 FIFO Byte Register 1 UART 0x18 8 read-write 0x00 0xFF UART_FBYTE2 FIFO Byte Register 2 UART 0x19 8 read-write 0x00 0xFF CSIO_SCR Serial Control Register CSIO 0x1 8 read-write 0x00 0xFF UPCL Programmable clear bit 7 7 read-write MS Master/Slave function select bit 6 6 read-write SPI SPI corresponding bit 5 5 read-write RIE Received interrupt enable bit 4 4 read-write TIE Transmit interrupt enable bit 3 3 read-write TBIE Transmit bus idle interrupt enable bit 2 2 read-write RXE Data received enable bit 1 1 read-write TXE Data transmission enable bit 0 0 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write 0x00 0xFF MD Operation mode set bits 5 7 read-write WUCR Wake-up control bit 4 4 read-write SCINV Serial clock invert bit 3 3 read-write BDS Transfer direction select bit 2 2 read-write SCKE Master mode serial clock output enable bit 1 1 read-write SOE Serial data output enable bit 0 0 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write 0x03 0x8F REC Received error flag clear bit 7 7 read-write ORE Overrun error flag bit 3 3 read-only RDRF Received data full flag bit 2 2 read-only TDRE Transmit data empty flag bit 1 1 read-only TBI Transmit bus idle flag bit 0 0 read-only CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write 0x00 0x9F SOP Serial output pin set bit 7 7 read-write WT Data transmit/received wait select bits 3 4 read-write L Data length select bits 0 2 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only 0x0000 0x01FF CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only 0x01FF 0x01FF CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write 0x0000 0x7FFF BGR1 Baud Rate Generator Registers 1 8 14 read-write BGR0 Baud Rate Generator Registers 0 0 7 read-write CSIO_FCR1 FIFO Control Register 1 CSIO 0x15 8 read-write 0x04 0x1F FLSTE Re-transmission data lost detect enable bit 4 4 read-write FRIIE Received FIFO idle detection enable bit 3 3 read-write FDRQ Transmit FIFO data request bit 2 2 read-write FTIE Transmit FIFO interrupt enable bit 1 1 read-write FSEL FIFO select bit 0 0 read-write CSIO_FCR0 FIFO Control Register 0 CSIO 0x14 8 read-write 0x00 0x7F FLST FIFO re-transmit data lost flag bit 6 6 read-only FLD FIFO pointer reload bit 5 5 read-write FSET FIFO pointer save bit 4 4 read-write FCL2 FIFO2 reset bit 3 3 read-write FCL1 FIFO1 reset bit 2 2 read-write FE2 FIFO2 operation enable bit 1 1 read-write FE1 FIFO1 operation enable bit 0 0 read-write CSIO_FBYTE1 FIFO Byte Register 1 CSIO 0x18 8 read-write 0x00 0xFF CSIO_FBYTE2 FIFO Byte Register 2 CSIO 0x19 8 read-write 0x00 0xFF I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write 0x00 0xFF MSS Master/slave select bit 7 7 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 6 read-write ACKE Data byte acknowledge enable bit 5 5 read-write WSEL Wait selection bit 4 4 read-write CNDE Condition detection interrupt enable bit 3 3 read-write INTE Interrupt enable bit 2 2 read-write BER Bus error flag bit 1 1 read-only INT interrupt flag bit 0 0 read-write I2C_SMR Serial Mode Register I2C 0x0 8 read-write 0x00 0xFC MD operation mode set bits 5 7 read-write WUCR Wake-up control bit 4 4 read-write RIE Received interrupt enable bit 3 3 read-write TIE Transmit interrupt enable bit 2 2 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write 0x00 0xFF FBT First byte bit 7 7 read-only RACK Acknowledge flag bit 6 6 read-only RSA Reserved address detection bit 5 5 read-only TRX Data direction bit 4 4 read-only AL Arbitration lost bit 3 3 read-only RSC Iteration start condition check bit 2 2 read-write SPC Stop condition check bit 1 1 read-write BB Bus state bit 0 0 read-only I2C_SSR Serial Status Register I2C 0x5 8 read-write 0x03 0xFF REC Received error flag clear bit 7 7 read-write TSET Transmit empty flag set bit 6 6 read-write DMA DMA mode enable bit 5 5 read-write TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 4 read-write ORE Overrun error flag bit 3 3 read-only RDRF Received data full flag bit 2 2 read-only TDRE Transmit data empty flag bit 1 1 read-only TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 0 read-only I2C_RDR Received Data Register I2C 0x8 16 read-only 0x0000 0x00FF I2C_TDR Transmit Data Register I2C 0x8 16 write-only 0x00FF 0x00FF I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write 0x7F 0xFF EN I2C interface operation enable bit 7 7 read-write SM Slave address mask bits 0 6 read-write I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write 0x00 0xFF SAEN Slave address enable bit 7 7 read-write SA 7-bit slave address 0 6 read-write I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write 0x0000 0x7FFF BGR1 Baud Rate Generator Registers 1 8 14 read-write BGR0 Baud Rate Generator Registers 0 0 7 read-write I2C_FCR1 FIFO Control Register 1 I2C 0x15 8 read-write 0x04 0x1F FLSTE Re-transmission data lost detect enable bit 4 4 read-write FRIIE Received FIFO idle detection enable bit 3 3 read-write FDRQ Transmit FIFO data request bit 2 2 read-write FTIE Transmit FIFO interrupt enable bit 1 1 read-write FSEL FIFO select bit 0 0 read-write I2C_FCR0 FIFO Control Register 0 I2C 0x14 8 read-write 0x00 0x7F FLST FIFO re-transmit data lost flag bit 6 6 read-only FLD FIFO pointer reload bit 5 5 read-write FSET FIFO pointer save bit 4 4 read-write FCL2 FIFO2 reset bit 3 3 read-write FCL1 FIFO1 reset bit 2 2 read-write FE2 FIFO2 operation enable bit 1 1 read-write FE1 FIFO1 operation enable bit 0 0 read-write I2C_FBYTE1 FIFO Byte Register 1 I2C 0x18 8 read-write 0x0000 0xFFFF I2C_FBYTE2 FIFO Byte Register 2 I2C 0x19 8 read-write 0x0000 0xFFFF I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write 0x0C 0x3F SDAS SDA status bit 5 5 read-write SCLS SCL status bit 4 4 read-write SDAC SDA output control bit 3 3 read-write SCLC SCL output control bit 2 2 read-write SOCE Serial output enabled bit 1 1 read-write BEC Bus error control bit 0 0 read-write MFS5 0x40038500 MFS5RX 17 MFS5TX 18 MFS6 0x40038600 MFS6RX 19 MFS6TX 20 MFS7 0x40038700 MFS7RX 21 MFS7TX 22 RTC REAL-TIME CLOCK RTC 0x4003B000 0x0 0x13 registers 0x15 0x3 registers 0x19 0x2 registers 0x1C 0x4 registers 0x20 0x2 registers 0x24 0x3 registers 0x28 0x2 registers 0x2C 0x1 registers 0x30 0x1 registers WTCR1 Control Register 1 0x0 32 read-write 0x00000000 0xFFFF1F7D INTCRIE Year/month/date/hour/minute/second/day of the week counter value read completion interrupt enable bit 31 31 read-write INTERIE Time rewrite error interrupt enable bit 30 30 read-write INTALIE Alarm interrupt enable bit 29 29 read-write INTTMIE Timer interrupt enable bit 28 28 read-write INTHIE 1-hour interrupt enable bit 27 27 read-write INTMIE 1-minute interrupt enable bit 26 26 read-write INTSIE 1-second interrupt enable bit 25 25 read-write INTSSIE 0.5-second interrupt enable bit 24 24 read-write INTCRI Year/month/date/hour/minute/second/day of the week counter value read completion interrupt flag bit 23 23 read-write INTERI Time rewrite error interrupt flag bit 22 22 read-write INTALI Alarm interrupt flag bit 21 21 read-write INTTMI Timer interrupt flag bit 20 20 read-write INTHI 1-hour interrupt flag bit 19 19 read-write INTMI 1-minute interrupt flag bit 18 18 read-write INTSI 1-second interrupt flag bit 17 17 read-write INTSSI 0.5-second interrupt flag bit 16 16 read-write YEN Alarm year register enable bit 12 12 read-write MOEN Alarm month register enable bit 11 11 read-write DEN Alarm date register enable bit 10 10 read-write HEN Alarm hour register enable bit 9 9 read-write MIEN Alarm minute register enable bit 8 8 read-write BUSY Busy bit 6 6 read-only SCRST Sub second generation/1-second generation counter reset bit 5 5 read-write SCST 1-second clock output stop bit 4 4 read-write SRST RTC reset bit 3 3 read-write RUN RTC count block operation bit 2 2 read-only ST Start bit 0 0 read-write WTCR2 Control Register 2 0x4 32 read-write 0x00000000 0x00000701 TMRUN Timer counter operation bit 10 10 read-only TMEN Timer counter control bit 9 9 read-write TMST Timer counter start bit 8 8 read-write CREAD Year/month/date/hour/minute/second/day of the week counter value read control bit 0 0 read-write WTBR Counter Cycle Setting Register 0x8 32 read-write 0x00000000 0x00FFFFFF BR23 Bit23 of WTBR 23 23 read-write BR22 Bit22 of WTBR 22 22 read-write BR21 Bit21 of WTBR 21 21 read-write BR20 Bit20 of WTBR 20 20 read-write BR19 Bit19 of WTBR 19 19 read-write BR18 Bit18 of WTBR 18 18 read-write BR17 Bit17 of WTBR 17 17 read-write BR16 Bit16 of WTBR 16 16 read-write BR15 Bit15 of WTBR 15 15 read-write BR14 Bit14 of WTBR 14 14 read-write BR13 Bit13 of WTBR 13 13 read-write BR12 Bit12 of WTBR 12 12 read-write BR11 Bit11 of WTBR 11 11 read-write BR10 Bit10 of WTBR 10 10 read-write BR9 Bit9 of WTBR 9 9 read-write BR8 Bit8 of WTBR 8 8 read-write BR7 Bit7 of WTBR 7 7 read-write BR6 Bit6 of WTBR 6 6 read-write BR5 Bit5 of WTBR 5 5 read-write BR4 Bit4 of WTBR 4 4 read-write BR3 Bit3 of WTBR 3 3 read-write BR2 Bit2 of WTBR 2 2 read-write BR1 Bit1 of WTBR 1 1 read-write BR0 Bit0 of WTBR 0 0 read-write WTDR Date Register 0xF 8 read-write 0x00 0x3F TD the second digit of the date 4 5 read-write D the first digit of the date 0 3 read-write WTHR Hour register 0xE 8 read-write 0x00 0x3F TH the second digit of the hour 4 5 read-write H the first digit of the hour 0 3 read-write WTMIR Minute Register 0xD 8 read-write 0x00 0x7F TMI the second digit of the minute 4 6 read-write MI the first digit of the minute 0 3 read-write WTSR Second Register 0xC 8 read-write 0x00 0x7F TS the second digit of the second 4 6 read-write S the first digit of the second 0 3 read-write WTYR Year Register 0x12 8 read-write 0x00 0xFF TY the second digit of the year 4 7 read-write Y the first digit of the year 0 3 read-write WTMOR Month Register 0x11 8 read-write 0x00 0x1F TMO the second digit in the month 4 4 read-write MO the first digit of the month 0 3 read-write WTDW Day of the Week Register 0x10 8 read-write 0x00 0x7 DW Day of the week 0 2 read-write ALDR Alarm Date Register 0x17 8 read-write 0x00 0x3F TAD the second digit of the alarm-set date 4 5 read-write AD the first digit of the alarm-set date 0 3 read-write ALHR Alarm Hour Register 0x16 8 read-write 0x00 0x3F TAH the second digit of the alarm-set hour 4 5 read-write AH the first digit of the alarm-set hour 0 3 read-write ALMIR Alarm Minute Register 0x15 8 read-write 0x00 0x7F TAMI the second digit of the alarm-set minute 4 6 read-write AMI the first digit of the alarm-set minute 0 3 read-write ALYR Alarm Years Register 0x1A 8 read-write 0x00 0xFF TAY the second digit of the alarm-set year 4 7 read-write AY the first digit of the alarm-set year 0 3 read-write ALMOR Alarm Month Register 0x19 8 read-write 0x00 0x1F TAMO the second digit of the alarm-set month 4 4 read-write AMO the first digit of the alarm-set month 0 3 read-write WTTR Timer Setting Register 0x1C 32 read-write 0x00000000 0x0003FFFF TM17 Bit17 of WTTR 17 17 read-write TM16 Bit16 of WTTR 16 16 read-write TM15 Bit15 of WTTR 15 15 read-write TM14 Bit14 of WTTR 14 14 read-write TM13 Bit13 of WTTR 13 13 read-write TM12 Bit12 of WTTR 12 12 read-write TM11 Bit11 of WTTR 11 11 read-write TM10 Bit10 of WTTR 10 10 read-write TM9 Bit9 of WTTR 9 9 read-write TM8 Bit8 of WTTR 8 8 read-write TM7 Bit7 of WTTR 7 7 read-write TM6 Bit6 of WTTR 6 6 read-write TM5 Bit5 of WTTR 5 5 read-write TM4 Bit4 of WTTR 4 4 read-write TM3 Bit3 of WTTR 3 3 read-write TM2 Bit2 of WTTR 2 2 read-write TM1 Bit1 of WTTR 1 1 read-write TM0 Bit0 of WTTR 0 0 read-write WTCLKS Clock Selection Register 0x20 8 read-write 0x00 0x01 WTCLKS Input clock selection bit 0 0 read-write WTCLKM Selection Clock Status Register 0x21 8 read-only 0x00 0x03 WTCLKM Clock selection status bit 0 1 read-only WTCAL Frequency Correction Value Setting Register 0x24 16 read-write 0x0000 0x03FF WTCAL Frequency correction value 0 9 read-write WTCALEN Frequency Correction Enable Register 0x26 8 read-write 0x00 0x01 WTCALEN Frequency correction enable bit 0 0 read-write WTDIV Divider Ratio Setting Register 0x28 8 read-write 0x00 0x0F WTDIV Divider ratio 0 3 read-write WTDIVEN Divider Output Enable Register 0x29 8 read-write 0x00 0x03 WTDIVRDY Divider status bit 1 1 read-only WTDIVEN Divider enable bit 0 0 read-write WTCALPRD Frequency Correction Cycle Setting Register 0x2C 8 read-write 0x13 0x3F WTCALPRD frequency correction value 0 5 read-write WTCOSEL RTCCO Output Selection Register 0x30 8 read-write 0x00 0x01 WTCOSEL RTCCO output selection bit 0 0 read-write CRC CRC Registers CRC 0x40039000 0x0 0x1 registers 0x4 0x4 registers 0x8 0x4 registers 0x4 0xC registers CRCCR CRC Control Register 0x0 8 read-write 0x00 0x7F FXOR Initialization bit 6 6 read-write CRCLSF Final XOR control bit 5 5 read-write CRCLTE CRC result bit-order setting bit 4 4 read-write LSBFST CRC result byte-order setting bit 3 3 read-write LTLEND Bit-order setting bit 2 2 read-write CRC32 Byte-order setting bit 1 1 read-write INIT CRC mode selection bit 0 0 read-write CRCINIT Initial Value Register 0x4 32 read-write 0xFFFFFFFF 0xFFFFFFFF D Initial value 0 31 read-write CRCIN Input Data Register 0x8 32 read-write 0x00000000 0xFFFFFFFF D Input data 0 31 read-write CRCR CRC Register 0xC 32 read-only 0xFFFFFFFF 0xFFFFFFFF D CRC Data 0 31 read-only USBCLK USB Clock USBCLK 0x40036000 0x0 0x1 registers 0x4 0x1 registers 0x8 0x1 registers 0xC 0x1 registers 0x10 0x1 registers 0x14 0x1 registers 0x18 0x1 registers 0x1C 0x1 registers 0x20 0x1 registers 0x24 0x1 registers 0x30 0x1 registers UCCR USB Clock Control Register 0x00 8 read-write 0x00 0x03 UCSEL USB clock selection bit 1 1 read-write UCEN USB clock output enable bit 0 0 read-write UPCR1 USB-PLL Control Register 1 0x04 8 read-write 0x00 0x03 UPINC USB-PLL input clock selection bit 1 1 read-write UPLLEN USB-PLL oscillation enable bit 0 0 read-write UPCR2 USB-PLL Control Register 2 0x08 8 read-write 0x00 0x07 UPOWT USB-PLL oscillation stabilization wait time setting bit 0 2 read-write UPCR3 USB-PLL Control Register 3 0x0C 8 read-write 0x00 0x1F UPLLK Frequency division ratio (K) setting bit of the USB-PLL clock 0 4 read-write UPCR4 USB-PLL Control Register 4 0x10 8 read-write 0x17 0x1F UPLLN Frequency division ratio (N) setting bit of the USB-PLL clock 0 4 read-write UPCR5 USB-PLL Control Register 5 0x24 8 read-write 0x04 0x0F UPLLM Frequency division ratio (M) setting bit of the USB-PLL clock 0 3 read-write UP_STR USB-PLL Status Register 0x14 8 read-only 0x00 0x01 UPRDY USB-PLL oscillation stabilization bit 0 0 read-only UPINT_ENR USB-PLL Interrupt Source Enable Register 0x18 8 read-write 0x00 0x01 UPCSE USB-PLL oscillation stabilization wait complete interrupt enable bit 0 0 read-write UPINT_STR USB-PLL Interrupt Source Status Register 0x20 8 read-only 0x00 0x01 UPCSI USB-PLL interrupt source status bit 0 0 read-only UPINT_CLR USB-PLL Interrupt Source Clear Register 0x1C 8 write-only 0x00 0x01 UPCSC USB-PLL oscillation stabilization interrupt source clear bit 0 0 write-only USBEN USB Enable Register 0x30 8 read-write 0x00 0x01 USBEN USB enable bit 0 0 read-write USB0 USB0 Function USB0 0x40040000 0x2100 0x2 registers 0x2104 0x2 registers 0x2108 0x2 registers 0x210C 0x2 registers 0x2110 0x2 registers 0x2114 0x2 registers 0x2118 0x2 registers 0x211C 0x1 registers 0x2120 0x2 registers 0x2124 0x2 registers 0x2128 0x2 registers 0x212C 0x2 registers 0x2130 0x2 registers 0x2134 0x2 registers 0x2138 0x2 registers 0x213C 0x2 registers 0x2140 0x2 registers 0x2144 0x2 registers 0x2148 0x2 registers 0x214C 0x2 registers 0x2150 0x2 registers 0x2154 0x2 registers 0x2158 0x2 registers 0x215C 0x2 registers 0x2160 0x2 registers 0x2164 0x2 registers 0x2168 0x2 registers 0x216C 0x2 registers 0x2170 0x2 registers 0x2174 0x2 registers USB0F 34 USB0F_USB0H 35 UDCC UDC Control Register 0x2120 16 read-write 0x00A0 0x00FB RST Function Reset bit 7 7 read-write RESUM Resume Setting bit 6 6 read-write HCONX Host Connection bit 5 5 read-write USTP USB Operating Clock Stop bit 4 4 read-write STALCLREN Endpoint 1 to 5 STAL bit Clear Select bit 3 3 read-write RFBK Data Toggle Mode Select bit 1 1 read-write PWC Power Control bit 0 0 read-write EP0C EP0 Control Register 0x2124 16 read-write 0x0040 0x027F STAL Endpoint 0 Stall Setting bit 9 9 read-write PKS0 Packet Size Endpoint 0 Setting bits 0 6 read-write EP1C EP1 Control Register 0x2128 16 read-write 0x6100 0xFFFF EPEN Endpoint Enable bit 15 15 read-write TYPE Endpoint Transfer Type Select bits 13 14 read-write DIR Endpoint Transfer Direction Select bit 12 12 read-write DMAE DMA Automatic Transfer Enable bit 11 11 read-write NULE Null Automatic Transfer Enable bit 10 10 read-write STAL Endpoint Stall Setting bit 9 9 read-write PKS Packet Size Setting bits 0 8 read-write EP2C EP2 Control Register 0x212C 16 read-write 0x6040 0xFE7F EPEN Endpoint Enable bit 15 15 read-write TYPE Endpoint Transfer Type Select bits 13 14 read-write DIR Endpoint Transfer Direction Select bit 12 12 read-write DMAE DMA Automatic Transfer Enable bit 11 11 read-write NULE Null Automatic Transfer Enable bit 10 10 read-write STAL Endpoint Stall Setting bit 9 9 read-write PKS Packet Size Setting bits 0 6 read-write EP3C EP3 Control Register 0x2130 EP4C EP4 Control Register 0x2134 EP5C EP5 Control Register 0x2138 TMSP Time Stamp Register 0x213C 16 read-only 0x0000 0x07FF TMSP Time Stamp bits 0 10 read-only UDCS UDC Status Register 0x2140 8 read-write 0x00 0x3F SUSP Suspend detection bit 5 5 read-write SOF SOF Detection bit 4 4 read-write BRST Bus Reset Detection bit 3 3 read-write WKUP Wake-up Detection bit 2 2 read-write SETP Setup Stage Detection bit 1 1 read-write CONF Configuration Detection bit 0 0 read-write UDCIE UDC Interrupt Enable Register 0x2141 8 read-write 0x00 0x3F SUSPIE Suspend Interrupt Enable bit 5 5 read-write SOFIE SOF Reception Interrupt Enable bit 4 4 read-write BRSTIE Bus Reset Enable bit 3 3 read-write WKUPIE Wake-up Interrupt Enable bit 2 2 read-write CONFN Configuration Number Indication bit 1 1 read-only CONFIE Configuration Interrupt Enable bit 0 0 read-write EP0IS EP0I Status Register 0x2144 16 read-write 0x8400 0xC400 BFINI Send Buffer Initialization bit 15 15 read-write DRQIIE Send Data Interrupt Enable bit 14 14 read-write DRQI Send/Receive Data Interrupt Request bit 10 10 read-write EP0OS EP0O Status Register 0x2148 16 read-write 0x8000 0xE67F BFINI Receive Buffer Initialization bit 15 15 read-write DRQOIE Receive Data Interrupt Enable bit 14 14 read-write SPKIE Short Packet Interrupt Enable bit 13 13 read-write DRQO Receive Data Interrupt Request bit 10 10 read-write SPK Short Packet Interrupt Request bit 9 9 read-write SIZE Packet Size Indication bit 0 6 read-only EP1S EP1 Status Register 0x214C 16 read-write 0x8000 0xEFFF BFINI Send/Receive Buffer Initialization bit 15 15 read-write DRQIE Packet Transfer Interrupt Enable bit 14 14 read-write SPKIE Short Packet Interrupt Enable bit 13 13 read-write BUSY Busy Flag bit 11 11 read-only DRQ Packet Transfer Interrupt Request bit 10 10 read-write SPK Short Packet Interrupt Request bit 9 9 read-write SIZE packet SIZE 0 8 read-only EP2S EP2 Status Register 0x2150 16 read-write 0x8000 0xEFFF BFINI Send/Receive Buffer Initialization bit 15 15 read-write DRQIE Packet Transfer Interrupt Enable bit 14 14 read-write SPKIE Short Packet Interrupt Enable bit 13 13 read-write BUSY Busy Flag bit 11 11 read-only DRQ Packet Transfer Interrupt Request bit 10 10 read-write SPK Short Packet Interrupt Request bit 9 9 read-write SIZE packet SIZE 0 6 read-only EP3S EP3 Status Register 0x2154 EP4S EP4 Status Register 0x2158 EP5S EP5 Status Register 0x215C EP0DT EP0 Data Register 0x2160 16 read-write 0x0000 0x0000 BFDT Endpoint Send/Receive Buffer Data 0 15 read-write EP1DT EP1 Data Register 0x2164 EP2DT EP2 Data Register 0x2168 EP3DT EP3 Data Register 0x216C EP4DT EP4 Data Register 0x2170 EP5DT EP5 Data Register 0x2174 HCNT Host Control Register 0x2100 16 read-write 0x0100 0x07FF SOFSTEP SOF interrupt occurrence selection bit 10 10 read-write CANCEL token cancellation enable bit 9 9 read-write RETRY retry enable bit 8 8 read-write RWKIRE resume interrupt enable bit 7 7 read-write URIRE bus reset interrupt enable bit 6 6 read-write CMPIRE token completion interrupt enable bit 5 5 read-write CNNIRE device connection detection interrupt enable bit 4 4 read-write DIRE device disconnection detection interrupt enable bit 3 3 read-write SOFIRE SOF interrupt enable bit 2 2 read-write URST bus reset bit 1 1 read-write HOST host mode bit 0 0 read-write HIRQ Host Interrupt Register 0x2104 8 read-write 0x00 0xBF TCAN token cancellation flag 7 7 read-write RWKIRQ remote Wake-up end flag 5 5 read-write URIRQ bus reset end flag 4 4 read-write CMPIRQ token completion flag 3 3 read-write CNNIRQ device connection detection flag 2 2 read-write DIRQ device disconnection detection flag 1 1 read-write SOFIRQ SOF starting flag 0 0 read-write HERR Host Error Status Register 0x2105 8 read-write 0x03 0xFF LSTSOF lost SOF flag 7 7 read-write RERR receive error flag 6 6 read-write TOUT timeout flag 5 5 read-write CRC CRC error flag 4 4 read-write TGERR toggle error flag 3 3 read-write STUFF stuffing error flag 2 2 read-write HS handshake status flags 0 1 read-write HSTATE Host Status Register 0x2108 8 read-write 0x12 0x3F ALIVE specify the keep-alive function in the low-speed mode 5 5 read-write CLKSEL USB operation clock selection bit 4 4 read-write SOFBUSY SOF busy flag 3 3 read-write SUSP suspend setting bit 2 2 read-write TMODE transmission mode flag 1 1 read-only CSTAT connection status flag 0 0 read-only HFCOMP SOF Interrupt Frame Compare Register 0x2109 8 read-write 0x00 0xFF FRAMECOMP frame compare data 0 7 read-write HRTIMER Retry Timer Setup Register 0x210C 16 read-write 0x0000 0xFFFF RTIMER1 retry timer setting 1 8 15 read-write RTIMER0 retry timer setting 0 0 7 read-write HRTIMER2 Retry Timer Setup Register 2 0x2110 8 read-write 0x00 0x03 RTIMER2 retry timer setting 2 0 1 read-write HADR Host Address Register 0x2111 8 read-write 0x00 0x7F ADDRESS Host Address 0 6 read-write HEOF EOF Setup Register 0x2114 16 read-write 0x0000 0x3FFF EOF1 End Frame 1 8 13 read-write EOF0 End Frame 0 0 7 read-write HFRAME Frame Setup Register 0x2118 16 read-write 0x0000 0x07FF FRAME1 Frame Setup 1 8 10 read-write FRAME0 Frame Setup 0 0 7 read-write HTOKEN Host Token Endpoint Register 0x211C 8 read-write 0x00 0xFF TGGL toggle bit 7 7 read-write TKNEN token enable bits 4 6 read-write ENDPT endpoint bits 0 3 read-write DMAC DMAC Registers DMAC 0x40060000 0x0 0x4 registers 0x10 0x80 registers DMAC0 38 DMAC1 39 DMAC2 40 DMAC3 41 DMAC4 42 DMAC5 43 DMAC6 44 DMAC7 45 DMACR Entire DMAC Configuration Register 0x0 32 read-write 0x00000000 0xDF000000 DE DMA Enable (all-channel operation enable bit) 31 31 read-write DS DMA Stop 30 30 read-write PR Priority Rotation 28 28 read-write DH DMA Halt (All-channel pause bit) 24 27 read-write DMACA0 Configuration A Register 0x10 32 read-write 0x00000000 0xFF9FFFFF EB Enable bit (individual-channel operation enable bit) 31 31 read-write PB Pause bit (individual-channel pause bit) 30 30 read-write ST Software Trigger 29 29 read-write IS Input Select 23 28 read-write BC Block Count 16 19 read-write TC Transfer Count 0 15 read-write DMACB0 Configuration B Register 0x14 32 read-write 0x00000000 0x3FFF0001 MS Mode Select 28 29 read-write TW Transfer Width 26 27 read-write FS Fixed Source 25 25 read-write FD Fixed Destination 24 24 read-write RC Reload Count (BC/TC reload) 23 23 read-write RS Reload Source 22 22 read-write RD Reload Destination 21 21 read-write EI Error Interrupt (unsuccessful transfer completion interrupt enable) 20 20 read-write CI Completion Interrupt (successful transfer completion interrupt enable) 19 19 read-write SS Stop Status (stop status notification) 16 18 read-write EM Enable bit Mask (EB bit clear mask) 0 0 read-write DMACSA0 Transfer Source Address Register 0x18 32 read-write 0x00000000 0xFFFFFFFF DMACDA0 Transfer Destination Address Register 0x1C 32 read-write 0x00000000 0xFFFFFFFF DMACA1 Configuration A Register 1 0x20 DMACB1 Configuration B Register 1 0x24 DMACSA1 Transfer Source Address Register 1 0x28 DMACDA1 Transfer Destination Address Register 1 0x2C DMACA2 Configuration A Register 2 0x30 DMACB2 Configuration B Register 2 0x34 DMACSA2 Transfer Source Address Register 2 0x38 DMACDA2 Transfer Destination Address Register 2 0x3C DMACA3 Configuration A Register 3 0x40 DMACB3 Configuration B Register 3 0x44 DMACSA3 Transfer Source Address Register 3 0x48 DMACDA3 Transfer Destination Address Register 3 0x4C DMACA4 Configuration A Register 4 0x50 DMACB4 Configuration B Register 4 0x54 DMACSA4 Transfer Source Address Register 4 0x58 DMACDA4 Transfer Destination Address Register 4 0x5C DMACA5 Configuration A Register 5 0x60 DMACB5 Configuration B Register 5 0x64 DMACSA5 Transfer Source Address Register 5 0x68 DMACDA5 Transfer Destination Address Register 5 0x6C DMACA6 Configuration A Register 6 0x70 DMACB6 Configuration B Register 6 0x74 DMACSA6 Transfer Source Address Register 6 0x78 DMACDA6 Transfer Destination Address Register 6 0x7C DMACA7 Configuration A Register 7 0x80 DMACB7 Configuration B Register 7 0x84 DMACSA7 Transfer Source Address Register 7 0x88 DMACDA7 Transfer Destination Address Register 7 0x8C