Silicon Labs SLAB EFR32FG22C121F256GM40 EFR32 C Flex Gecko 38.4 MHz, 6dBm, Proprietary 8 32 32 read-write 0 4294967295 EMU_S 1 EMU_S Registers 0x40004000 0x00000000 0x00001000 registers EMU 6 EMUDG 29 EMUSE 30 DECBOD No Description 0x010 read-write 0x00000022 0x00000033 DECBODEN DECBOD enable 0 1 read-write DECBODMASK DECBOD Mask 1 1 read-write DECOVMBODEN Over Voltage Monitor enable 4 1 read-write DECOVMBODMASK Over Voltage Monitor Mask 5 1 read-write BOD3SENSE No Description 0x020 read-write 0x00000000 0x00000077 AVDDBODEN AVDD BOD enable 0 1 read-write VDDIO0BODEN VDDIO0 BOD enable 1 1 read-write VDDIO1BODEN VDDIO1 BOD enable 2 1 read-write VREGVDDCMPCTRL No Description 0x03C read-write 0x00000006 0x00000007 VREGINCMPEN VREGVDD comparator enable 0 1 read-write THRESSEL VREGVDD comparator threshold programming 1 2 read-write PD1PARETCTRL No Description 0x040 read-write 0x00000000 0x0000FFFF PD1PARETDIS Disable PD1 Partial Retention 0 16 read-write RETAIN Retain associated registers when in EM2/3 0 NORETAIN Do not retain associcated registers when in EM2/3 1 LOCK No Description 0x060 write-only 0x0000ADE8 0x0000FFFF LOCKKEY Lock Key 0 16 write-only UNLOCK Unlock EMU register 44520 IF No Description 0x064 read-write 0x00000000 0xEB070000 AVDDBOD AVDD BOD Interrupt flag 16 1 read-write IOVDD0BOD VDDIO0 BOD Interrupt flag 17 1 read-write EM23WAKEUP EM23 Wake up Interrupt flag 24 1 read-write VSCALEDONE Vscale done Interrupt flag 25 1 read-write TEMPAVG Temperature Average Interrupt flag 27 1 read-write TEMP Temperature Interrupt flag 29 1 read-write TEMPLOW Temperature low Interrupt flag 30 1 read-write TEMPHIGH Temperature high Interrupt flag 31 1 read-write IEN No Description 0x068 read-write 0x00000000 0xEB070000 AVDDBOD AVDD BOD Interrupt enable 16 1 read-write IOVDD0BOD VDDIO0 BOD Interrupt enable 17 1 read-write EM23WAKEUP EM23 Wake up Interrupt enable 24 1 read-write VSCALEDONE Vscale done Interrupt enable 25 1 read-write TEMPAVG Temperature Interrupt enable 27 1 read-write TEMP Temperature Interrupt enable 29 1 read-write TEMPLOW Temperature low Interrupt enable 30 1 read-write TEMPHIGH Temperature high Interrupt enable 31 1 read-write EM4CTRL No Description 0x06C read-write 0x00000000 0x00000133 EM4ENTRY EM4 entry request 0 2 read-write EM4IORETMODE EM4 IO retention mode 4 2 read-write DISABLE No Retention: Pads enter reset state when entering EM4 0 EM4EXIT Retention through EM4: Pads enter reset state when exiting EM4 1 SWUNLATCH Retention through EM4 and Wakeup: software writes UNLATCH register to remove retention 2 BOD3SENSEEM4WU Set BOD3SENSE as EM4 wakeup 8 1 read-write CMD No Description 0x070 write-only 0x00000000 0x00020E12 EM4UNLATCH EM4 unlatch 1 1 write-only TEMPAVGREQ Temperature Average Request 4 1 write-only EM01VSCALE1 Scale voltage to Vscale1 10 1 write-only EM01VSCALE2 Scale voltage to Vscale2 11 1 write-only RSTCAUSECLR Reset Cause Clear 17 1 write-only CTRL No Description 0x074 read-write 0x00000200 0xE0010309 EM2DBGEN Enable debugging in EM2 0 1 read-write TEMPAVGNUM Averaged Temperature samples num 3 1 read-write N16 16 measurements 0 N64 64 measurements 1 EM23VSCALE EM2/EM3 Vscale 8 2 read-write VSCALE0 VSCALE0. 0.9v 0 VSCALE1 VSCALE1. 1.0v 1 VSCALE2 VSCALE2. 1.1v 2 FLASHPWRUPONDEMAND Enable flash on demand wakeup 16 1 read-write EFPDIRECTMODEEN EFP Direct Mode Enable 29 1 read-write EFPDRVDECOUPLE EFP drives DECOUPLE 30 1 read-write EFPDRVDVDD EFP drives DVDD 31 1 read-write TEMPLIMITS No Description 0x078 read-write 0x01FF0000 0x01FF01FF TEMPLOW Temp Low limit 0 9 read-write TEMPHIGH Temp High limit 16 9 read-write STATUS No Description 0x084 read-only 0x00000080 0xFF0054FF LOCK Lock status 0 1 read-only UNLOCKED All EMU lockable registers are unlocked. 0 LOCKED All EMU lockable registers are locked. 1 FIRSTTEMPDONE First Temp done 1 1 read-only TEMPACTIVE Temp active 2 1 read-only TEMPAVGACTIVE Temp Average active 3 1 read-only VSCALEBUSY Vscale busy 4 1 read-only VSCALEFAILED Vscale failed 5 1 read-only VSCALE Vscale status 6 2 read-only VSCALE0 Voltage scaling set to 0.9v 0 VSCALE1 Voltage scaling set to 1.0v 1 VSCALE2 Voltage scaling set to 1.1v 2 RACACTIVE RAC active 10 1 read-only EM4IORET EM4 IO retention status 12 1 read-only EM2ENTERED EM2 entered 14 1 read-only TEMP No Description 0x088 read-only 0x00000000 0x07FF07FF TEMPLSB Temperature measured decimal part 0 2 read-only TEMP Temperature measured 2 9 read-only TEMPAVG Averaged Temperature 16 11 read-only RSTCTRL No Description 0x090 read-write 0x40010407 0xC001C5CF WDOG0RMODE Enable WDOG0 reset 0 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset except some EMU registers 1 SYSRMODE Enable M33 System reset 2 1 read-write DISABLED Reset request is blocked 0 ENABLED Device is reset except some EMU registers 1 LOCKUPRMODE Enable M33 Lockup reset 3 1 read-write DISABLED Reset Request is Block 0 ENABLED The entire device is reset except some EMU registers 1 AVDDBODRMODE Enable AVDD BOD reset 6 1 read-write DISABLED Reset Request is block 0 ENABLED The entire device is reset except some EMU registers 1 IOVDD0BODRMODE Enable VDDIO0 BOD reset 7 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset except some EMU registers 1 DECBODRMODE Enable DECBOD reset 10 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset 1 DCIRMODE DCI System reset 16 1 read-write DISABLED Reset request blocked 0 ENABLED The entire device is reset except some EMU registers 1 RSTCAUSE No Description 0x094 read-only 0x00000000 0x8001FFFF POR Power On Reset 0 1 read-only PIN Pin Reset 1 1 read-only EM4 EM4 Wakeup Reset 2 1 read-only WDOG0 Watchdog 0 Reset 3 1 read-only LOCKUP M33 Core Lockup Reset 5 1 read-only SYSREQ M33 Core Sys Reset 6 1 read-only DVDDBOD HVBOD Reset 7 1 read-only DVDDLEBOD LEBOD Reset 8 1 read-only DECBOD LVBOD Reset 9 1 read-only AVDDBOD LEBOD1 Reset 10 1 read-only IOVDD0BOD LEBOD2 Reset 11 1 read-only DCI DCI reset 16 1 read-only VREGIN DCDC VREGIN comparator 31 1 read-only DGIF No Description 0x0A0 read-write 0x00000000 0xE1000000 EM23WAKEUPDGIF EM23 Wake up Interrupt flag 24 1 read-write TEMPDGIF Temperature Interrupt flag 29 1 read-write TEMPLOWDGIF Temperature low Interrupt flag 30 1 read-write TEMPHIGHDGIF Temperature high Interrupt flag 31 1 read-write DGIEN No Description 0x0A4 read-write 0x00000000 0xE1000000 EM23WAKEUPDGIEN EM23 Wake up Interrupt enable 24 1 read-write TEMPDGIEN Temperature Interrupt enable 29 1 read-write TEMPLOWDGIEN Temperature low Interrupt enable 30 1 read-write TEMPHIGHDGIEN Temperature high Interrupt enable 31 1 read-write EFPIF No Description 0x100 read-write 0x00000000 0x00000001 EFPIF EFP Interrupt Flag 0 1 read-write EFPIEN No Description 0x104 read-write 0x00000000 0x00000001 EFPIEN EFP Interrupt enable 0 1 read-write CMU_S 1 CMU_S Registers 0x40008000 0x00000000 0x00001000 registers CMU 46 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only STATUS No Description 0x008 read-only 0x00000000 0xC0030001 CALRDY Calibration Ready 0 1 read-only WDOGLOCK Configuration Lock Status for WDOG 30 1 read-only UNLOCKED WDOG configuration lock is unlocked 0 LOCKED WDOG configuration lock is locked 1 LOCK Configuration Lock Status 31 1 read-only UNLOCKED Configuration lock is unlocked 0 LOCKED Configuration lock is locked 1 LOCK No Description 0x010 write-only 0x000093F7 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write this value to unlock 37879 WDOGLOCK No Description 0x014 write-only 0x00005257 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write this value to unlock 37879 IF No Description 0x020 read-write 0x00000000 0x00000003 CALRDY Calibration Ready Interrupt Flag 0 1 read-write CALOF Calibration Overflow Interrupt Flag 1 1 read-write IEN No Description 0x024 read-write 0x00000000 0x00000003 CALRDY Calibration Ready Interrupt Enable 0 1 read-write CALOF Calibration Overflow Interrupt Enable 1 1 read-write CALCMD No Description 0x050 write-only 0x00000000 0x00000003 CALSTART Calibration Start 0 1 write-only CALSTOP Calibration Stop 1 1 write-only CALCTRL No Description 0x054 read-write 0x00000000 0xFF8FFFFF CALTOP Calibration Counter Top Value 0 20 read-write CONT Continuous Calibration 23 1 read-write UPSEL Calibration Up-counter Select 24 4 read-write DISABLED Up-counter is not clocked 0 PRS PRS CMU_CALUP consumer is clocking up-counter 1 HFXO HFXO is clocking up-counter 2 LFXO LFXO is clocking up-counter 3 HFRCODPLL HFRCODPLL is clocking up-counter 4 FSRCO FSRCO is clocking up-counter 8 LFRCO LFRCO is clocking up-counter 9 ULFRCO ULFRCO is clocking up-counter 10 DOWNSEL Calibration Down-counter Select 28 4 read-write DISABLED Down-counter is not clocked 0 HCLK HCLK is clocking down-counter 1 PRS PRS CMU_CALDN consumer is clocking down-counter 2 HFXO HFXO is clocking down-counter 3 LFXO LFXO is clocking down-counter 4 HFRCODPLL HFRCODPLL is clocking down-counter 5 FSRCO FSRCO is clocking down-counter 9 LFRCO LFRCO is clocking down-counter 10 ULFRCO ULFRCO is clocking down-counter 11 CALCNT No Description 0x058 read-only 0x00000000 0x000FFFFF CALCNT Calibration Result Counter Value 0 20 read-only CLKEN0 No Description 0x064 read-write 0x00000000 0xFFFFFFFF LDMA Enable Bus Clock 0 1 read-write LDMAXBAR Enable Bus Clock 1 1 read-write RADIOAES Enable Bus Clock 2 1 read-write GPCRC Enable Bus Clock 3 1 read-write TIMER0 Enable Bus Clock 4 1 read-write TIMER1 Enable Bus Clock 5 1 read-write TIMER2 Enable Bus Clock 6 1 read-write TIMER3 Enable Bus Clock 7 1 read-write USART0 Enable Bus Clock 8 1 read-write USART1 Enable Bus Clock 9 1 read-write IADC0 Enable Bus Clock 10 1 read-write AMUXCP0 Enable Bus Clock 11 1 read-write LETIMER0 Enable Bus Clock 12 1 read-write WDOG0 Enable Bus Clock 13 1 read-write I2C0 Enable Bus Clock 14 1 read-write I2C1 Enable Bus Clock 15 1 read-write SYSCFG Enable Bus Clock 16 1 read-write DPLL0 Enable Bus Clock 17 1 read-write HFRCO0 Enable Bus Clock 18 1 read-write HFXO0 Enable Bus Clock 19 1 read-write FSRCO Enable Bus Clock 20 1 read-write LFRCO Enable Bus Clock 21 1 read-write LFXO Enable Bus Clock 22 1 read-write ULFRCO Enable Bus Clock 23 1 read-write EUART0 Enable Bus Clock 24 1 read-write PDM Enable Bus Clock 25 1 read-write GPIO Enable Bus Clock 26 1 read-write PRS Enable Bus Clock 27 1 read-write BURAM Enable Bus Clock 28 1 read-write BURTC Enable Bus Clock 29 1 read-write RTCC Enable Bus Clock 30 1 read-write DCDC Enable Bus Clock 31 1 read-write CLKEN1 No Description 0x068 read-write 0x00000000 0x0007FFFF AGC Enable Bus Clock 0 1 read-write MODEM Enable Bus Clock 1 1 read-write RFCRC Enable Bus Clock 2 1 read-write FRC Enable Bus Clock 3 1 read-write PROTIMER Enable Bus Clock 4 1 read-write RAC Enable Bus Clock 5 1 read-write SYNTH Enable Bus Clock 6 1 read-write RDSCRATCHPAD Enable Bus Clock 7 1 read-write RDMAILBOX0 Enable Bus Clock 8 1 read-write RDMAILBOX1 Enable Bus Clock 9 1 read-write PRORTC Enable Bus Clock 10 1 read-write BUFC Enable Bus Clock 11 1 read-write IFADCDEBUG Enable Bus Clock 12 1 read-write CRYPTOACC Enable Bus Clock 13 1 read-write RFSENSE Enable Bus Clock 14 1 read-write SMU Enable Bus Clock 15 1 read-write ICACHE0 Enable Bus Clock 16 1 read-write MSC Enable Bus Clock 17 1 read-write TIMER4 Enable Bus Clock 18 1 read-write SYSCLKCTRL No Description 0x070 read-write 0x00000001 0x0001F507 CLKSEL Clock Select 0 3 read-write FSRCO FSRCO is clocking SYSCLK 1 HFRCODPLL HFRCODPLL is clocking SYSCLK 2 HFXO HFXO is clocking SYSCLK 3 CLKIN0 CLKIN0 is clocking SYSCLK 4 PCLKPRESC PCLK Prescaler 10 1 read-write DIV1 PCLK is HCLK divided by 1 0 DIV2 PCLK is HCLK divided by 2 1 HCLKPRESC HCLK Prescaler 12 4 read-write DIV1 HCLK is SYSCLK divided by 1 0 DIV2 HCLK is SYSCLK divided by 2 1 DIV4 HCLK is SYSCLK divided by 4 3 DIV8 HCLK is SYSCLK divided by 8 7 DIV16 HCLK is SYSCLK divided by 16 15 RHCLKPRESC Radio HCLK Prescaler 16 1 read-write DIV1 Radio HCLK is SYSCLK divided by 1 0 DIV2 Radio HCLK is SYSCLK divided by 2 1 TRACECLKCTRL No Description 0x080 read-write 0x00000000 0x00000030 PRESC TRACECLK Prescaler 4 2 read-write DIV1 TRACECLK is SYSCLK divided by 1 0 DIV2 TRACECLK is SYSCLK divided by 2 1 DIV4 TRACECLK is SYSCLK divided by 4 3 EXPORTCLKCTRL No Description 0x090 read-write 0x00000000 0x1F0F0F0F CLKOUTSEL0 Clock Output Select 0 0 4 read-write DISABLED CLKOUT0 is not clocked 0 HCLK HCLK is clocking CLKOUT0 1 HFEXPCLK EXPORTCLK is clocking CLKOUT0 2 ULFRCO ULFRCO is clocking CLKOUT0 3 LFRCO LFRCO is clocking CLKOUT0 4 LFXO LFXO is clocking CLKOUT0 5 HFRCODPLL HFRCODPLL is clocking CLKOUT0 6 HFXO HFXO is clocking CLKOUT0 7 FSRCO FSRCO is clocking CLKOUT0 8 CLKOUTSEL1 Clock Output Select 1 8 4 read-write DISABLED CLKOUT1 is not clocked 0 HCLK HCLK is clocking CLKOUT1 1 HFEXPCLK EXPORTCLK is clocking CLKOUT1 2 ULFRCO ULFRCO is clocking CLKOUT1 3 LFRCO LFRCO is clocking CLKOUT1 4 LFXO LFXO is clocking CLKOUT1 5 HFRCODPLL HFRCODPLL is clocking CLKOUT1 6 HFXO HFXO is clocking CLKOUT1 7 FSRCO FSRCO is clocking CLKOUT1 8 CLKOUTSEL2 Clock Output Select 2 16 4 read-write DISABLED CLKOUT2 is not clocked 0 HCLK HCLK is clocking CLKOUT2 1 HFEXPCLK EXPORTCLK is clocking CLKOUT2 2 ULFRCO ULFRCO is clocking CLKOUT2 3 LFRCO LFRCO is clocking CLKOUT2 4 LFXO LFXO is clocking CLKOUT2 5 HFRCODPLL HFRCODPLL is clocking CLKOUT2 6 HFXO HFXO is clocking CLKOUT2 7 FSRCO FSRCO is clocking CLKOUT2 8 PRESC EXPORTCLK Prescaler 24 5 read-write DPLLREFCLKCTRL No Description 0x100 read-write 0x00000000 0x00000003 CLKSEL Clock Select 0 2 read-write DISABLED DPLLREFCLK is not clocked 0 HFXO HFXO is clocking DPLLREFCLK 1 LFXO LFXO is clocking DPLLREFCLK 2 CLKIN0 CLKIN0 is clocking DPLLREFCLK 3 EM01GRPACLKCTRL No Description 0x120 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write HFRCODPLL HFRCODPLL is clocking EM01GRPACLK 1 HFXO HFXO is clocking EM01GRPACLK 2 FSRCO FSRCO is clocking EM01GRPACLK 3 EM01GRPBCLKCTRL No Description 0x124 read-write 0x00000001 0x00000007 CLKSEL Clock Select 0 3 read-write HFRCODPLL HFRCODPLL is clocking EM01GRPBCLK 1 HFXO HFXO is clocking EM01GRPBCLK 2 FSRCO FSRCO is clocking EM01GRPBCLK 3 CLKIN0 CLKIN0 is clocking EM01GRPBCLK 4 HFRCODPLLRT HFRCODPLL (re-timed) is clocking EM01GRPBCLK 5 HFXORT HFXO (re-timed) is clocking EM01GRPBCLK 6 EM23GRPACLKCTRL No Description 0x140 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking EM23GRPACLK 1 LFXO LFXO is clocking EM23GRPACLK 2 ULFRCO ULFRCO is clocking EM23GRPACLK 3 EM4GRPACLKCTRL No Description 0x160 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking EM4GRPACLK 1 LFXO LFXO is clocking EM4GRPACLK 2 ULFRCO ULFRCO is clocking EM4GRPACLK 3 IADCCLKCTRL No Description 0x180 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write EM01GRPACLK EM01GRPACLK is clocking IADCCLK 1 FSRCO FSRCO is clocking IADCCLK 2 WDOG0CLKCTRL No Description 0x200 read-write 0x00000001 0x00000007 CLKSEL Clock Select 0 3 read-write LFRCO LFRCO is clocking WDOG0CLK 1 LFXO LFXO is clocking WDOG0CLK 2 ULFRCO ULFRCO is clocking WDOG0CLK 3 HCLKDIV1024 HCLKDIV1024 is clocking WDOG0CLK 4 EUART0CLKCTRL No Description 0x220 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write DISABLED UART is not clocked 0 EM01GRPACLK EM01GRPACLK is clocking UART 1 EM23GRPACLK EM23GRPACLK is clocking UART 2 RTCCCLKCTRL No Description 0x240 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking RTCCCLK 1 LFXO LFXO is clocking RTCCCLK 2 ULFRCO ULFRCO is clocking RTCCCLK 3 PRORTCCLKCTRL No Description 0x248 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking PRORTCCLK 1 LFXO LFXO is clocking PRORTCCLK 2 ULFRCO ULFRCO is clocking PRORTCCLK 3 CRYPTOACCCLKCTRL No Description 0x260 read-write 0x00000000 0x00000003 PKEN PK Enable 0 1 read-write AESEN AES Enable 1 1 read-write RADIOCLKCTRL No Description 0x280 read-write 0x00000000 0x80000001 EN Enable 0 1 read-write DBGCLK Enable Clock for Debugger 31 1 read-write HFXO0_S 2 HFXO0_S Registers 0x4000C000 0x00000000 0x00001000 registers HFXO0 44 IPVERSION No Description 0x000 read-only 0x00000002 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only XTALCFG No Description 0x010 read-write 0x044334CB 0x0FFFFFFF COREBIASSTARTUPI Intermediate Startup Core Bias Current 0 6 read-write COREBIASSTARTUP Startup Core Bias Current 6 6 read-write CTUNEXISTARTUP Startup Tuning Capacitance on XI 12 4 read-write CTUNEXOSTARTUP Startup Tuning Capacitance on XO 16 4 read-write TIMEOUTSTEADY Steady State Timeout 20 4 read-write T16US The steady state timeout is set to 16 us minimum. The maximum can be +40%. 0 T41US The steady state timeout is set to 41 us minimum. The maximum can be +40%. 1 T83US The steady state timeout is set to 83 us minimum. The maximum can be +40%. 2 T125US The steady state timeout is set to 125 us minimum. The maximum can be +40%. 3 T166US The steady state timeout is set to 166 us minimum. The maximum can be +40%. 4 T208US The steady state timeout is set to 208 us minimum. The maximum can be +40%. 5 T250US The steady state timeout is set to 250 us minimum. The maximum can be +40%. 6 T333US The steady state timeout is set to 333 us minimum. The maximum can be +40%. 7 T416US The steady state timeout is set to 416 us minimum. The maximum can be +40%. 8 T500US The steady state timeout is set to 500 us minimum. The maximum can be +40%. 9 T666US The steady state timeout is set to 666 us minimum. The maximum can be +40%. 10 T833US The steady state timeout is set to 833 us minimum. The maximum can be +40%. 11 T1666US The steady state timeout is set to 1666 us minimum. The maximum can be +40%. 12 T2500US The steady state timeout is set to 2500 us minimum. The maximum can be +40%. 13 T4166US The steady state timeout is set to 4166 us minimum. The maximum can be +40%. 14 T7500US The steady state timeout is set to 7500 us minimum. The maximum can be +40%. 15 TIMEOUTCBLSB Core Bias LSB Change Timeout 24 4 read-write T8US The core bias LSB change timeout is set to 8 us minimum. The maximum can be +40%. 0 T20US The core bias LSB change timeout is set to 20 us minimum. The maximum can be +40%. 1 T41US The core bias LSB change timeout is set to 41 us minimum. The maximum can be +40%. 2 T62US The core bias LSB change timeout is set to 62 us minimum. The maximum can be +40%. 3 T83US The core bias LSB change timeout is set to 83 us minimum. The maximum can be +40%. 4 T104US The core bias LSB change timeout is set to 104 us minimum. The maximum can be +40%. 5 T125US The core bias LSB change timeout is set to 125 us minimum. The maximum can be +40%. 6 T166US The core bias LSB change timeout is set to 166 us minimum. The maximum can be +40%. 7 T208US The core bias LSB change timeout is set to 208 us minimum. The maximum can be +40%. 8 T250US The core bias LSB change timeout is set to 250 us minimum. The maximum can be +40%. 9 T333US The core bias LSB change timeout is set to 333 us minimum. The maximum can be +40%. 10 T416US The core bias LSB change timeout is set to 416 us minimum. The maximum can be +40%. 11 T833US The core bias LSB change timeout is set to 833 us minimum. The maximum can be +40%. 12 T1250US The core bias LSB change timeout is set to 1250 us minimum. The maximum can be +40%. 13 T2083US The core bias LSB change timeout is set to 2083 us minimum. The maximum can be +40%. 14 T3750US The core bias LSB change timeout is set to 3750 us minimum. The maximum can be +40%. 15 XTALCTRL No Description 0x018 read-write 0x0F8C8C10 0x8FFFFFFF COREBIASANA Core Bias Current 0 8 read-write CTUNEXIANA Tuning Capacitance on XI 8 8 read-write CTUNEXOANA Tuning Capacitance on XO 16 8 read-write CTUNEFIXANA Fixed Tuning Capacitance 24 2 read-write NONE Remove fixed capacitance on XI and XO nodes 0 XI Adds fixed capacitance on XI node 1 XO Adds fixed capacitance on XO node 2 BOTH Adds fixed capacitance on both XI and XO nodes 3 COREDGENANA Core Degeneration 26 2 read-write NONE Do not apply core degeneration resistence 0 DGEN33 Apply 33 ohm core degeneration resistence 1 DGEN50 Apply 50 ohm core degeneration resistence 2 DGEN100 Apply 100 ohm core degeneration resistence 3 SKIPCOREBIASOPT Skip Core Bias Optimization 31 1 read-write CFG No Description 0x020 read-write 0x10000000 0xF000000D MODE Crystal Oscillator Mode 0 1 read-write XTAL crystal oscillator 0 EXTCLK external sinusoidal clock can be supplied on XI pin. 1 ENXIDCBIASANA Enable XI Internal DC Bias 2 1 read-write SQBUFSCHTRGANA Squaring Buffer Schmitt Trigger 3 1 read-write DISABLE Squaring buffer schmitt trigger is disabled 0 ENABLE Squaring buffer schmitt trigger is enabled 1 CTRL No Description 0x028 read-write 0x00000002 0x80000037 FORCEEN Force Enable 0 1 read-write DISONDEMAND Disable On-demand Mode 1 1 read-write KEEPWARM Keep Warm 2 1 read-write FORCEXI2GNDANA Force XI Pin to Ground 4 1 read-write DISABLE Disabled (not pulled) 0 ENABLE Enabled (pulled) 1 FORCEXO2GNDANA Force XO Pin to Ground 5 1 read-write DISABLE Disabled (not pulled) 0 ENABLE Enabled (pulled) 1 CMD No Description 0x050 write-only 0x00000000 0x00000003 COREBIASOPT Core Bias Optimizaton 0 1 write-only MANUALOVERRIDE Manual Override 1 1 write-only STATUS No Description 0x058 read-only 0x00000000 0xC00F0003 RDY Ready Status 0 1 read-only COREBIASOPTRDY Core Bias Optimization Ready 1 1 read-only ENS Enabled Status 16 1 read-only HWREQ Oscillator Requested by Hardware 17 1 read-only ISWARM Oscillator Is Kept Warm 19 1 read-only FSMLOCK FSM Lock Status 30 1 read-only UNLOCKED FSM lock is unlocked 0 LOCKED FSM lock is locked 1 LOCK Configuration Lock Status 31 1 read-only UNLOCKED Configuration lock is unlocked 0 LOCKED Configuration lock is locked 1 IF No Description 0x070 read-write 0x00000000 0xE0000003 RDY Ready Interrupt 0 1 read-write COREBIASOPTRDY Core Bias Optimization Ready Interrupt 1 1 read-write DNSERR Did Not Start Error Interrupt 29 1 read-write COREBIASOPTERR Core Bias Optimization Error Interrupt 31 1 read-write IEN No Description 0x074 read-write 0x00000000 0xE0000003 RDY Ready Interrupt 0 1 read-write COREBIASOPTRDY Core Bias Optimization Ready Interrupt 1 1 read-write DNSERR Did Not Start Error Interrupt 29 1 read-write COREBIASOPTERR Core Bias Optimization Error Interrupt 31 1 read-write LOCK No Description 0x080 write-only 0x0000580E 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write this value to unlock 22542 HFRCO0_S 1 HFRCO0_S Registers 0x40010000 0x00000000 0x00001000 registers HFRCO0 45 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only CTRL No Description 0x004 read-write 0x00000000 0x00000003 FORCEEN Force Enable 0 1 read-write DISONDEMAND Disable On-demand 1 1 read-write CAL No Description 0x008 read-write 0xA8689F7F 0xFFFFBF7F TUNING Tuning Value 0 7 read-write FINETUNING Fine Tuning Value 8 6 read-write LDOHP LDO High Power Mode 15 1 read-write FREQRANGE Frequency Range 16 5 read-write CMPBIAS Comparator Bias Current 21 3 read-write CLKDIV Locally Divide HFRCO Clock Output 24 2 read-write DIV1 Divide by 1. 0 DIV2 Divide by 2. 1 DIV4 Divide by 4. 2 CMPSEL Comparator Load Select 26 2 read-write IREFTC Tempco Trim on Comparator Current 28 4 read-write STATUS No Description 0x00C read-only 0x00000000 0x80010007 RDY Ready 0 1 read-only FREQBSY Frequency Updating Busy 1 1 read-only SYNCBUSY Synchronization Busy 2 1 read-only ENS Enable Status 16 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED HFRCO is unlocked 0 LOCKED HFRCO is locked 1 IF No Description 0x010 read-write 0x00000000 0x00000001 RDY Ready Interrupt Flag 0 1 read-write IEN No Description 0x014 read-write 0x00000000 0x00000001 RDY RDY Interrupt Enable 0 1 read-write LOCK No Description 0x01C write-only 0x00008195 0x0000FFFF LOCKKEY Lock Key 0 16 write-only UNLOCK Unlock code 33173 FSRCO_S 0 FSRCO_S Registers 0x40018000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version 0 32 read-only DPLL0_S 0 DPLL0_S Registers 0x4001C000 0x00000000 0x00001000 registers DPLL0 50 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Module Enable 0 1 read-write CFG No Description 0x008 read-write 0x00000000 0x00000047 MODE Operating Mode Control 0 1 read-write FLL Frequency Lock Mode 0 PLL Phase Lock Mode 1 EDGESEL Reference Edge Select 1 1 read-write AUTORECOVER Automatic Recovery Control 2 1 read-write DITHEN Dither Enable Control 6 1 read-write CFG1 No Description 0x00C read-write 0x00000000 0x0FFF0FFF M Factor M 0 12 read-write N Factor N 16 12 read-write IF No Description 0x010 read-write 0x00000000 0x00000007 LOCK Lock Interrupt Flag 0 1 read-write LOCKFAILLOW Lock Failure Low Interrupt Flag 1 1 read-write LOCKFAILHIGH Lock Failure High Interrupt Flag 2 1 read-write IEN No Description 0x014 read-write 0x00000000 0x00000007 LOCK LOCK interrupt Enable 0 1 read-write LOCKFAILLOW LOCKFAILLOW Interrupe Enable 1 1 read-write LOCKFAILHIGH LOCKFAILHIGH Interrupt Enable 2 1 read-write STATUS No Description 0x018 read-only 0x00000000 0x80000003 RDY Ready Status 0 1 read-only ENS Enable Status 1 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED 0 LOCKED 1 LOCK No Description 0x024 write-only 0x00007102 0x0000FFFF LOCKKEY Lock Key 0 16 write-only UNLOCK 28930 LFXO_S 0 LFXO_S Registers 0x40020000 0x00000000 0x00001000 registers LFXO 22 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CTRL No Description 0x004 read-write 0x00000002 0x00000033 FORCEEN LFXO Force Enable 0 1 read-write DISONDEMAND LFXO Disable On-demand requests 1 1 read-write FAILDETEN LFXO Failure Detection Enable 4 1 read-write FAILDETEM4WUEN LFXO Failure Detection EM4WU Enable 5 1 read-write CFG Do not write to this register unless the oscillator is forced off. The oscillator is forced off if DISONDEMAND is set and FORCEEN is cleared. 0x008 read-write 0x00000701 0x00000733 AGC LFXO AGC Enable 0 1 read-write HIGHAMPL LFXO High Amplitude Enable 1 1 read-write MODE LFXO Mode 4 2 read-write XTAL A 32768Hz crystal should be connected to the LF crystal pads. Voltage must not exceed VDDIO. 0 BUFEXTCLK An external sine source with minimum amplitude 100mv (zero-to-peak) and maximum amplitude 500mV (zero-to-peak) should be connected in series with LFXTAL_I pin. Minimum voltage should be larger than ground and maximum voltage smaller than VDDIO. The sine source does not need to be ac coupled externally as it is ac couples inside LFXO. LFXTAL_O is free to be used as a general purpose GPIO. 1 DIGEXTCLK An external 32KHz CMOS clock should be provided on LFXTAL_I. LFXTAL_O is free to be used as a general purpose GPIO. 2 TIMEOUT LFXO Start-up Delay 8 3 read-write CYCLES2 Timeout period of 2 cycles 0 CYCLES256 Timeout period of 256 cycles 1 CYCLES1K Timeout period of 1024 cycles 2 CYCLES2K Timeout period of 2048 cycles 3 CYCLES4K Timeout period of 4096 cycles 4 CYCLES8K Timeout period of 8192 cycles 5 CYCLES16K Timeout period of 16384 cycles 6 CYCLES32K Timeout period of 32768 cycles 7 STATUS No Description 0x010 read-only 0x00000000 0x80010001 RDY LFXO Ready Status 0 1 read-only ENS LFXO Enable Status 16 1 read-only LOCK LFXO Locked Status 31 1 read-only UNLOCKED LFXO lockable registers are not locked 0 LOCKED LFXO lockable registers are locked 1 CAL Do not write to this register unless CALBSY in SYNCBUSY register is low. 0x014 read-write 0x00000200 0x0000037F CAPTUNE Internal Capacitance Tuning 0 7 read-write GAIN LFXO Startup Gain 8 2 read-write IF No Description 0x018 read-write 0x00000000 0x0000000F RDY LFXO Ready Interrupt Flag 0 1 read-write POSEDGE Rising Edge Interrupt Flag 1 1 read-write NEGEDGE Falling Edge Interrupt Flag 2 1 read-write FAIL LFXO Failure Interrupt Flag 3 1 read-write IEN No Description 0x01C read-write 0x00000000 0x0000000F RDY LFXO Ready Interrupt Enable 0 1 read-write POSEDGE Rising Edge Interrupt Enable 1 1 read-write NEGEDGE Falling Edge Interrupt Enable 2 1 read-write FAIL LFXO Failure Interrupt Enable 3 1 read-write SYNCBUSY No Description 0x020 read-only 0x00000000 0x00000001 CAL LFXO Synchronization status 0 1 read-only LOCK No Description 0x024 write-only 0x00001A20 0x0000FFFF LOCKKEY Lock Key 0 16 write-only UNLOCK Unlock LFXO lockable registers 6688 LFRCO_S 1 LFRCO_S Registers 0x40024000 0x00000000 0x00001000 registers LFRCO 23 IPVERSION Contains the LFRCO ip version 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only CTRL Control register 0x004 read-write 0x00000000 0x00000003 FORCEEN Force Enable 0 1 read-write DISONDEMAND Disable On-Demand 1 1 read-write STATUS Status register 0x008 read-only 0x00000000 0x80010001 RDY Ready Status 0 1 read-only ENS Enabled Status 16 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED Access to configuration registers not locked 0 LOCKED Access to configuration registers locked 1 IF Interrupt flag register 0x014 read-write 0x00000000 0x00070707 RDY Ready Flag 0 1 read-write POSEDGE Rising Edge Flag 1 1 read-write NEGEDGE Falling Edge Flag 2 1 read-write TCDONE Temperature Check Done Flag 8 1 read-write CALDONE Calibration Done Flag 9 1 read-write TEMPCHANGE Temperature Change Flag 10 1 read-write SCHEDERR Scheduling Error Flag 16 1 read-write TCOOR Temperature Check Out Of Range Flag 17 1 read-write CALOOR Calibration Out Of Range Flag 18 1 read-write IEN Interrupt enable register 0x018 read-write 0x00000000 0x00070707 RDY Ready Enable 0 1 read-write POSEDGE Rising Edge Enable 1 1 read-write NEGEDGE Falling Edge Enable 2 1 read-write TCDONE Temperature Check Done Enable 8 1 read-write CALDONE Calibration Done Enable 9 1 read-write TEMPCHANGE Temperature Change Enable 10 1 read-write SCHEDERR Scheduling Error Enable 16 1 read-write TCOOR Temperature Check Out Of Range Enable 17 1 read-write CALOOR Calibration Out Of Range Enable 18 1 read-write LOCK Configuration lock register. Locks and unlocks access to configuration registers. 0x020 write-only 0x00000000 0x0000FFFF LOCKKEY Lock Key 0 16 write-only LOCK Lock Configuration Registers 0 UNLOCK Unlock Configuration Registers 3987 CFG Configuration register 0x024 read-write 0x00000000 0x00000001 HIGHPRECEN High Precision Enable 0 1 read-write NOMCAL Nominal calibration register 0x02C read-write 0x0005B8D8 0x001FFFFF NOMCALCNT Nominal Calibration Count 0 21 read-write NOMCALINV Nominal calibration inverted register 0x030 read-write 0x0000597A 0x0001FFFF NOMCALCNTINV Nominal Calibration Count Inverted 0 17 read-write CMD Command register 0x034 write-only 0x00000000 0x00000001 REDUCETCINT Reduce Temperature Check Interval 0 1 write-only ULFRCO_S 0 ULFRCO_S Registers 0x40028000 0x00000000 0x00001000 registers ULFRCO 24 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION ULFRCO IP version 0 32 read-only STATUS No Description 0x008 read-only 0x00000000 0x00010001 RDY Ready Status 0 1 read-only ENS Enable Status 16 1 read-only IF No Description 0x014 read-write 0x00000000 0x00000007 RDY Ready Interrupt Flag 0 1 read-write POSEDGE Positive Edge Interrupt Flag 1 1 read-write NEGEDGE Negative Edge Interrupt Flag 2 1 read-write IEN No Description 0x018 read-write 0x00000000 0x00000007 RDY Enable Ready Interrupt 0 1 read-write POSEDGE Enable Positive Edge Interrupt 1 1 read-write NEGEDGE Enable Negative Edge Interrupt 2 1 read-write MSC_S 1 MSC_S Registers 0x40030000 0x00000000 0x00001000 registers MSC 49 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only READCTRL No Description 0x008 read-write 0x00200000 0x00301002 DOUTBUFEN Flash dout pipeline buffer enable 12 1 read-write MODE Read Mode 20 2 read-write WS0 Zero wait-states inserted in fetch or read transfers 0 WS1 One wait-state inserted for each fetch or read transfer 1 WS2 Two wait-states inserted for eatch fetch or read transfer 2 WS3 Three wait-states inserted for eatch fetch or read transfer 3 WRITECTRL No Description 0x00C read-write 0x00000000 0x0000000B WREN Enable Write/Erase Controller 0 1 read-write IRQERASEABORT Abort Page Erase on Interrupt 1 1 read-write LPWRITE Low-Power Erase 3 1 read-write WRITECMD No Description 0x010 write-only 0x00000000 0x00001126 ERASEPAGE Erase Page 1 1 write-only WRITEEND End Write Mode 2 1 write-only ERASEABORT Abort erase sequence 5 1 write-only ERASEMAIN0 Mass erase region 0 8 1 write-only CLEARWDATA Clear WDATA state 12 1 write-only ADDRB No Description 0x014 read-write 0x00000000 0xFFFFFFFF ADDRB Page Erase or Write Address Buffer 0 32 read-write WDATA No Description 0x018 read-write 0x00000000 0xFFFFFFFF DATAW Write Data 0 32 read-write STATUS No Description 0x01C read-only 0x08000008 0xF901007F BUSY Erase/Write Busy 0 1 read-only LOCKED Access Locked 1 1 read-only INVADDR Invalid Write Address or Erase Page 2 1 read-only WDATAREADY WDATA Write Ready 3 1 read-only ERASEABORTED Erase Operation Aborted 4 1 read-only PENDING Write Command In Queue 5 1 read-only TIMEOUT Write Command Timeout 6 1 read-only REGLOCK Register Lock Status 16 1 read-only UNLOCKED Register lock is unlocked 0 LOCKED Register lock is locked. 1 PWRON Flash Power On Status 24 1 read-only WREADY Flash Write Ready 27 1 read-only PWRUPCKBDFAILCOUNT Flash power up checkerboard pattern chec 28 4 read-only IF No Description 0x020 read-write 0x00000000 0x00000307 ERASE Host Erase Done Interrupt Read Flag 0 1 read-write WRITE Host Write Done Interrupt Read Flag 1 1 read-write WDATAOV Host write buffer overflow 2 1 read-write PWRUPF Flash Power Up Sequence Complete Flag 8 1 read-write PWROFF Flash Power Off Sequence Complete Flag 9 1 read-write IEN No Description 0x024 read-write 0x00000000 0x00000307 ERASE Erase Done Interrupt enable 0 1 read-write WRITE Write Done Interrupt enable 1 1 read-write WDATAOV write data buffer overflow irq enable 2 1 read-write PWRUPF Flash Power Up Seq done irq enable 8 1 read-write PWROFF Flash Power Off Seq done irq enable 9 1 read-write USERDATASIZE No Description 0x034 read-only 0x00000004 0x0000003F USERDATASIZE User Data Size 0 6 read-only CMD No Description 0x038 write-only 0x00000000 0x00000011 PWRUP Flash Power Up Command 0 1 write-only PWROFF Flash power off/sleep command 4 1 write-only LOCK No Description 0x03C write-only 0x00000000 0x0000FFFF LOCKKEY Configuration Lock 0 16 write-only LOCK Key to lock the register lock 0 UNLOCK Key to unlock the register lock. 7025 MISCLOCKWORD No Description 0x040 read-write 0x00000011 0x00000011 MELOCKBIT Mass Erase Lock 0 1 read-write UDLOCKBIT User Data Lock 4 1 read-write PWRCTRL No Description 0x050 read-write 0x00100002 0x00FF0013 PWROFFONEM1ENTRY Power down Flash macro when enter EM1 0 1 read-write PWROFFONEM1PENTRY Power down Flash macro when enter EM1P 1 1 read-write PWROFFENTRYAGAIN POWER down flash again in EM1/EM1p 4 1 read-write PWROFFDLY Power down delay 16 8 read-write PAGELOCK0 No Description 0x120 read-write 0x00000000 0xFFFFFFFF LOCKBIT page lock bit 0 32 read-write PAGELOCK1 No Description 0x124 read-write 0x00000000 0xFFFFFFFF LOCKBIT page lock bit 0 32 read-write ICACHE0_S 0 ICACHE0_S Registers 0x40034000 0x00000000 0x00001000 registers ICACHE0 17 IPVERSION The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION. 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only CTRL No Description 0x004 read-write 0x00000000 0x00000007 CACHEDIS Cache Disable 0 1 read-write USEMPU Use MPU 1 1 read-write AUTOFLUSHDIS Automatic Flushing Disable 2 1 read-write PCHITS No Description 0x008 read-only 0x00000000 0xFFFFFFFF PCHITS Performance Counter Hits 0 32 read-only PCMISSES No Description 0x00C read-only 0x00000000 0xFFFFFFFF PCMISSES Performance Counter Misses 0 32 read-only PCAHITS No Description 0x010 read-only 0x00000000 0xFFFFFFFF PCAHITS Performance Counter Advanced Hits 0 32 read-only STATUS No Description 0x014 read-only 0x00000000 0x00000001 PCRUNNING PC Running 0 1 read-only CMD No Description 0x018 write-only 0x00000000 0x00000007 FLUSH Flush 0 1 write-only STARTPC Start Performance Counters 1 1 write-only STOPPC Stop Performance Counters 2 1 write-only LPMODE No Description 0x01C read-write 0x00000023 0x000000F3 LPLEVEL Low Power Level 0 2 read-write BASIC Base instruction cache functionality 0 ADVANCED Advanced buffering mode, where the cache uses the fetch pattern to predict highly accessed data and store it in low-energy memory 1 MINACTIVITY Minimum activity mode, which allows the cache to minimize activity in logic that it predicts has a low probability being used. This mode can introduce wait-states into the instruction fetch stream when the cache exits one of its low-activity states. The number of wait-states introduced is small, but users running with 0-wait-state memory and wishing to reduce the variability that the cache might introduce with additional wait-states may wish to lower the cache low-power level. Note, this mode includes the advanced buffering mode functionality. 3 NESTFACTOR Low Power Nest Factor 4 4 read-write IF No Description 0x020 read-write 0x00000000 0x00000107 HITOF Hit Overflow Interrupt Flag 0 1 read-write MISSOF Miss Overflow Interrupt Flag 1 1 read-write AHITOF Advanced Hit Overflow Interrupt Flag 2 1 read-write RAMERROR RAM error Interrupt Flag 8 1 read-write IEN No Description 0x024 read-write 0x00000000 0x00000107 HITOF Hit Overflow Interrupt Enable 0 1 read-write MISSOF Miss Overflow Interrupt Enable 1 1 read-write AHITOF Advanced Hit Overflow Interrupt Enable 2 1 read-write RAMERROR RAM error Interrupt Enable 8 1 read-write PRS_S 1 PRS_S Registers 0x40038000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only ASYNC_SWPULSE No Description 0x008 write-only 0x00000000 0x00000FFF CH0PULSE Channel pulse 0 1 write-only CH1PULSE Channel pulse 1 1 write-only CH2PULSE Channel pulse 2 1 write-only CH3PULSE Channel pulse 3 1 write-only CH4PULSE Channel pulse 4 1 write-only CH5PULSE Channel pulse 5 1 write-only CH6PULSE Channel pulse 6 1 write-only CH7PULSE Channel pulse 7 1 write-only CH8PULSE Channel pulse 8 1 write-only CH9PULSE Channel pulse 9 1 write-only CH10PULSE Channel pulse 10 1 write-only CH11PULSE Channel pulse 11 1 write-only ASYNC_SWLEVEL No Description 0x00C read-write 0x00000000 0x00000FFF CH0LEVEL Channel Level 0 1 read-write CH1LEVEL Channel Level 1 1 read-write CH2LEVEL Channel Level 2 1 read-write CH3LEVEL Channel Level 3 1 read-write CH4LEVEL Channel Level 4 1 read-write CH5LEVEL Channel Level 5 1 read-write CH6LEVEL Channel Level 6 1 read-write CH7LEVEL Channel Level 7 1 read-write CH8LEVEL Channel Level 8 1 read-write CH9LEVEL Channel Level 9 1 read-write CH10LEVEL Channel Level 10 1 read-write CH11LEVEL Channel Level 11 1 read-write ASYNC_PEEK No Description 0x010 read-only 0x00000000 0x00000FFF CH0VAL Channel 0 Current Value 0 1 read-only CH1VAL Channel 1 Current Value 1 1 read-only CH2VAL Channel 2 Current Value 2 1 read-only CH3VAL Channel 3 Current Value 3 1 read-only CH4VAL Channel 4 Current Value 4 1 read-only CH5VAL Channel 5 Current Value 5 1 read-only CH6VAL Channel 6 Current Value 6 1 read-only CH7VAL Channel 7 Current Value 7 1 read-only CH8VAL Channel 8 Current Value 8 1 read-only CH9VAL Channel 9 Current Value 9 1 read-only CH10VAL Channel 10 Current Value 10 1 read-only CH11VAL Channel 11 Current Value 11 1 read-only SYNC_PEEK No Description 0x014 read-only 0x00000000 0x0000000F CH0VAL Channel Value 0 1 read-only CH1VAL Channel Value 1 1 read-only CH2VAL Channel Value 2 1 read-only CH3VAL Channel Value 3 1 read-only ASYNC_CH0_CTRL No Description 0x018 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH1_CTRL No Description 0x01C read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH2_CTRL No Description 0x020 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH3_CTRL No Description 0x024 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH4_CTRL No Description 0x028 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH5_CTRL No Description 0x02C read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH6_CTRL No Description 0x030 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH7_CTRL No Description 0x034 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH8_CTRL No Description 0x038 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH9_CTRL No Description 0x03C read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH10_CTRL No Description 0x040 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH11_CTRL No Description 0x044 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write SYNC_CH0_CTRL No Description 0x048 read-write 0x00000000 0x00007F07 SIGSEL Signal Select 0 3 read-write SOURCESEL Source Select 8 7 read-write SYNC_CH1_CTRL No Description 0x04C read-write 0x00000000 0x00007F07 SIGSEL Signal Select 0 3 read-write SOURCESEL Source Select 8 7 read-write SYNC_CH2_CTRL No Description 0x050 read-write 0x00000000 0x00007F07 SIGSEL Signal Select 0 3 read-write SOURCESEL Source Select 8 7 read-write SYNC_CH3_CTRL No Description 0x054 read-write 0x00000000 0x00007F07 SIGSEL Signal Select 0 3 read-write SOURCESEL Source Select 8 7 read-write CONSUMER_CMU_CALDN CALDN Consumer Register 0x058 read-write 0x00000000 0x0000000F PRSSEL CALDN async channel select 0 4 read-write CONSUMER_CMU_CALUP CALUP Consumer Register 0x05C read-write 0x00000000 0x0000000F PRSSEL CALUP async channel select 0 4 read-write CONSUMER_IADC0_SCANTRIGGER SCAN Consumer Register 0x064 read-write 0x00000000 0x0000030F PRSSEL SCAN async channel select 0 4 read-write SPRSSEL SCAN sync channel select 8 2 read-write CONSUMER_IADC0_SINGLETRIGGER SINGLE Consumer Register 0x068 read-write 0x00000000 0x0000030F PRSSEL SINGLE async channel select 0 4 read-write SPRSSEL SINGLE sync channel select 8 2 read-write CONSUMER_LDMAXBAR_DMAREQ0 DMAREQ0 Consumer Register 0x06C read-write 0x00000000 0x0000000F PRSSEL DMAREQ0 async channel select 0 4 read-write CONSUMER_LDMAXBAR_DMAREQ1 DMAREQ1 Consumer Register 0x070 read-write 0x00000000 0x0000000F PRSSEL DMAREQ1 async channel select 0 4 read-write CONSUMER_LETIMER0_CLEAR CLEAR Consumer Register 0x074 read-write 0x00000000 0x0000000F PRSSEL CLEAR async channel select 0 4 read-write CONSUMER_LETIMER0_START START Consumer Register 0x078 read-write 0x00000000 0x0000000F PRSSEL START async channel select 0 4 read-write CONSUMER_LETIMER0_STOP STOP Consumer Register 0x07C read-write 0x00000000 0x0000000F PRSSEL STOP async channel select 0 4 read-write CONSUMER_EUART0_RX RX Consumer Register 0x080 read-write 0x00000000 0x0000000F PRSSEL RX async channel select 0 4 read-write CONSUMER_EUART0_TRIGGER TRIGGER Consumer Register 0x084 read-write 0x00000000 0x0000000F PRSSEL TRIGGER async channel select 0 4 read-write CONSUMER_MODEM_DIN DIN Consumer Register 0x088 read-write 0x00000000 0x0000000F PRSSEL DIN async channel select 0 4 read-write CONSUMER_RAC_CLR CLR Consumer Register 0x0C0 read-write 0x00000000 0x0000000F PRSSEL CLR async channel select 0 4 read-write CONSUMER_RAC_CTIIN0 CTI Consumer Register 0x0C4 read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_RAC_CTIIN1 CTI Consumer Register 0x0C8 read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_RAC_CTIIN2 CTI Consumer Register 0x0CC read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_RAC_CTIIN3 CTI Consumer Register 0x0D0 read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_RAC_FORCETX FORCETX Consumer Register 0x0D4 read-write 0x00000000 0x0000000F PRSSEL FORCETX async channel select 0 4 read-write CONSUMER_RAC_RXDIS RXDIS Consumer Register 0x0D8 read-write 0x00000000 0x0000000F PRSSEL RXDIS async channel select 0 4 read-write CONSUMER_RAC_RXEN RXEN Consumer Register 0x0DC read-write 0x00000000 0x0000000F PRSSEL RXEN async channel select 0 4 read-write CONSUMER_RAC_SEQ SEQ Consumer Register 0x0E0 read-write 0x00000000 0x0000000F PRSSEL SEQ async channel select 0 4 read-write CONSUMER_RAC_TXEN TXEN Consumer Register 0x0E4 read-write 0x00000000 0x0000000F PRSSEL TXEN async channel select 0 4 read-write CONSUMER_RTCC_CC0 CC0 Consumer Register 0x0E8 read-write 0x00000000 0x0000000F PRSSEL CC0 async channel select 0 4 read-write CONSUMER_RTCC_CC1 CC1 Consumer Register 0x0EC read-write 0x00000000 0x0000000F PRSSEL CC1 async channel select 0 4 read-write CONSUMER_RTCC_CC2 CC2 Consumer Register 0x0F0 read-write 0x00000000 0x0000000F PRSSEL CC2 async channel select 0 4 read-write CONSUMER_CORE_CTIIN0 CTI Consumer Register 0x0F8 read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_CORE_CTIIN1 CTI Consumer Register 0x0FC read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_CORE_CTIIN2 CTI Consumer Register 0x100 read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_CORE_CTIIN3 CTI Consumer Register 0x104 read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_CORE_M33RXEV M33 Consumer Register 0x108 read-write 0x00000000 0x0000000F PRSSEL M33 async channel select 0 4 read-write CONSUMER_TIMER0_CC0 CC0 Consumer Register 0x10C read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER0_CC1 CC1 Consumer Register 0x110 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER0_CC2 CC2 Consumer Register 0x114 read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER0_DTI DTI Consumer Register 0x118 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER0_DTIFS1 DTI Consumer Register 0x11C read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER0_DTIFS2 DTI Consumer Register 0x120 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER1_CC0 CC0 Consumer Register 0x124 read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER1_CC1 CC1 Consumer Register 0x128 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER1_CC2 CC2 Consumer Register 0x12C read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER1_DTI DTI Consumer Register 0x130 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER1_DTIFS1 DTI Consumer Register 0x134 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER1_DTIFS2 DTI Consumer Register 0x138 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER2_CC0 CC0 Consumer Register 0x13C read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER2_CC1 CC1 Consumer Register 0x140 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER2_CC2 CC2 Consumer Register 0x144 read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER2_DTI DTI Consumer Register 0x148 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER2_DTIFS1 DTI Consumer Register 0x14C read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER2_DTIFS2 DTI Consumer Register 0x150 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER3_CC0 CC0 Consumer Register 0x154 read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER3_CC1 CC1 Consumer Register 0x158 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER3_CC2 CC2 Consumer Register 0x15C read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER3_DTI DTI Consumer Register 0x160 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER3_DTIFS1 DTI Consumer Register 0x164 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER3_DTIFS2 DTI Consumer Register 0x168 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER4_CC0 CC0 Consumer Register 0x16C read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER4_CC1 CC1 Consumer Register 0x170 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER4_CC2 CC2 Consumer Register 0x174 read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER4_DTI DTI Consumer Register 0x178 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER4_DTIFS1 DTI Consumer Register 0x17C read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER4_DTIFS2 DTI Consumer Register 0x180 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_USART0_CLK CLK Consumer Register 0x184 read-write 0x00000000 0x0000000F PRSSEL CLK async channel select 0 4 read-write CONSUMER_USART0_IR IR Consumer Register 0x188 read-write 0x00000000 0x0000000F PRSSEL IR async channel select 0 4 read-write CONSUMER_USART0_RX RX Consumer Register 0x18C read-write 0x00000000 0x0000000F PRSSEL RX async channel select 0 4 read-write CONSUMER_USART0_TRIGGER TRIGGER Consumer Register 0x190 read-write 0x00000000 0x0000000F PRSSEL TRIGGER async channel select 0 4 read-write CONSUMER_USART1_CLK CLK Consumer Register 0x194 read-write 0x00000000 0x0000000F PRSSEL CLK async channel select 0 4 read-write CONSUMER_USART1_IR IR Consumer Register 0x198 read-write 0x00000000 0x0000000F PRSSEL IR async channel select 0 4 read-write CONSUMER_USART1_RX RX Consumer Register 0x19C read-write 0x00000000 0x0000000F PRSSEL RX async channel select 0 4 read-write CONSUMER_USART1_TRIGGER TRIGGER Consumer Register 0x1A0 read-write 0x00000000 0x0000000F PRSSEL TRIGGER async channel select 0 4 read-write CONSUMER_WDOG0_SRC0 SRC0 Consumer Register 0x1A4 read-write 0x00000000 0x0000000F PRSSEL SRC0 async channel select 0 4 read-write CONSUMER_WDOG0_SRC1 SRC1 Consumer Register 0x1A8 read-write 0x00000000 0x0000000F PRSSEL SRC1 async channel select 0 4 read-write GPIO_S 1 GPIO_S Registers 0x4003C000 0x00000000 0x00001000 registers GPIO_ODD 25 GPIO_EVEN 26 PORTA_CTRL Port control 0x000 read-write 0x00400040 0x10701070 SLEWRATE Slew Rate 4 3 read-write DINDIS Data In Disable 12 1 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write DINDISALT Data In Disable Alt 28 1 read-write PORTA_MODEL mode low 0x004 read-write 0x00000000 0xFFFFFFFF MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE4 MODE n 16 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE5 MODE n 20 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE6 MODE n 24 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE7 MODE n 28 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTA_MODEH mode high 0x00C read-write 0x00000000 0x0000000F MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTA_DOUT data out 0x010 read-write 0x00000000 0x000001FF DOUT Data output 0 9 read-write PORTA_DIN data in 0x014 read-only 0x00000000 0x000001FF DIN Data input 0 9 read-only PORTB_CTRL Port control 0x030 read-write 0x00400040 0x10701070 SLEWRATE Slew Rate 4 3 read-write DINDIS Data In Disable 12 1 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write DINDISALT Data In Disable Alt 28 1 read-write PORTB_MODEL mode low 0x034 read-write 0x00000000 0x000FFFFF MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE4 MODE n 16 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTB_DOUT data out 0x040 read-write 0x00000000 0x0000001F DOUT Data output 0 5 read-write PORTB_DIN data in 0x044 read-only 0x00000000 0x0000001F DIN Data input 0 5 read-only PORTC_CTRL Port control 0x060 read-write 0x00400040 0x10701070 SLEWRATE Slew Rate 4 3 read-write DINDIS Data In Disable 12 1 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write DINDISALT Data In Disable Alt 28 1 read-write PORTC_MODEL mode low 0x064 read-write 0x00000000 0xFFFFFFFF MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE4 MODE n 16 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE5 MODE n 20 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE6 MODE n 24 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE7 MODE n 28 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTC_DOUT data out 0x070 read-write 0x00000000 0x000000FF DOUT Data output 0 8 read-write PORTC_DIN data in 0x074 read-only 0x00000000 0x000000FF DIN Data input 0 8 read-only PORTD_CTRL Port control 0x090 read-write 0x00400040 0x10701070 SLEWRATE Slew Rate 4 3 read-write DINDIS Data In Disable 12 1 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write DINDISALT Data In Disable Alt 28 1 read-write PORTD_MODEL mode low 0x094 read-write 0x00000000 0x0000FFFF MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTD_DOUT data out 0x0A0 read-write 0x00000000 0x0000000F DOUT Data output 0 4 read-write PORTD_DIN data in 0x0A4 read-only 0x00000000 0x0000000F DIN Data input 0 4 read-only LOCK No Description 0x300 write-only 0x0000A534 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Unlock code 42292 GPIOLOCKSTATUS No Description 0x310 read-only 0x00000000 0x00000001 LOCK GPIO LOCK status 0 1 read-only UNLOCKED Registers are unlocked 0 LOCKED Registers are locked 1 ABUSALLOC A Bus allocation 0x320 read-write 0x00000000 0x0F0F0F0F AEVEN0 A Bus Even 0 0 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 AEVEN1 A Bus Even 1 8 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 AODD0 A Bus Odd 0 16 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 AODD1 A Bus Odd 1 24 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 BBUSALLOC B Bus allocation 0x324 read-write 0x00000000 0x0F0F0F0F BEVEN0 B Bus Even 0 0 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 BEVEN1 B Bus Even 1 8 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 BODD0 B Bus Odd 0 16 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 BODD1 B Bus Odd 1 24 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 CDBUSALLOC CD Bus allocation 0x328 read-write 0x00000000 0x0F0F0F0F CDEVEN0 CD Bus Even 0 0 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 CDEVEN1 CD Bus Even 1 8 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 CDODD0 CD Bus Odd 0 16 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 CDODD1 CD Bus Odd 1 24 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 EXTIPSELL External Interrupt Port Select Low 0x400 read-write 0x00000000 0x33333333 EXTIPSEL0 External Interrupt Port Select 0 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL1 External Interrupt Port Select 4 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL2 External Interrupt Port Select 8 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL3 External Interrupt Port Select 12 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL4 External Interrupt Port Select 16 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL5 External Interrupt Port Select 20 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL6 External Interrupt Port Select 24 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL7 External Interrupt Port Select 28 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSELH External interrupt Port Select High 0x404 read-write 0x00000000 0x00003333 EXTIPSEL0 External Interrupt Port Select 0 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL1 External Interrupt Port Select 4 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL2 External Interrupt Port Select 8 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL3 External Interrupt Port Select 12 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPINSELL External Interrupt Pin Select Low 0x408 read-write 0x00000000 0x33333333 EXTIPINSEL0 External Interrupt Pin select 0 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL1 External Interrupt Pin select 4 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL2 External Interrupt Pin select 8 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL3 External Interrupt Pin select 12 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL4 External Interrupt Pin select 16 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL5 External Interrupt Pin select 20 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL6 External Interrupt Pin select 24 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL7 External Interrupt Pin select 28 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSELH External Interrupt Pin Select High 0x40C read-write 0x00000000 0x00003333 EXTIPINSEL0 External Interrupt Pin select 0 2 read-write OFFSET8 OFFSET=8 0 OFFSET9 OFFSET=9 1 OFFSET10 OFFSET=10 2 OFFSET11 OFFSET=11 3 EXTIPINSEL1 External Interrupt Pin select 4 2 read-write OFFSET8 OFFSET=8 0 OFFSET9 OFFSET=9 1 OFFSET10 OFFSET=10 2 OFFSET11 OFFSET=11 3 EXTIPINSEL2 External Interrupt Pin select 8 2 read-write OFFSET8 OFFSET=8 0 OFFSET9 OFFSET=9 1 OFFSET10 OFFSET=10 2 OFFSET11 OFFSET=11 3 EXTIPINSEL3 External Interrupt Pin select 12 2 read-write OFFSET8 OFFSET=8 0 OFFSET9 OFFSET=9 1 OFFSET10 OFFSET=10 2 OFFSET11 OFFSET=11 3 EXTIRISE External Interrupt Rising Edge Trigger 0x410 read-write 0x00000000 0x00000FFF EXTIRISE EXT Int Rise 0 12 read-write EXTIFALL External Interrupt Falling Edge Trigger 0x414 read-write 0x00000000 0x00000FFF EXTIFALL EXT Int FALL 0 12 read-write IF Interrupt Flag 0x420 read-write 0x00000000 0x0FFF0FFF EXTIF0 External Pin Flag 0 1 read-write EXTIF1 External Pin Flag 1 1 read-write EXTIF2 External Pin Flag 2 1 read-write EXTIF3 External Pin Flag 3 1 read-write EXTIF4 External Pin Flag 4 1 read-write EXTIF5 External Pin Flag 5 1 read-write EXTIF6 External Pin Flag 6 1 read-write EXTIF7 External Pin Flag 7 1 read-write EXTIF8 External Pin Flag 8 1 read-write EXTIF9 External Pin Flag 9 1 read-write EXTIF10 External Pin Flag 10 1 read-write EXTIF11 External Pin Flag 11 1 read-write EM4WU EM4 wake up 16 12 read-write IEN Interrupt Enable 0x424 read-write 0x00000000 0x0FFF0FFF EXTIEN0 External Pin Enable 0 1 read-write EXTIEN1 External Pin Enable 1 1 read-write EXTIEN2 External Pin Enable 2 1 read-write EXTIEN3 External Pin Enable 3 1 read-write EXTIEN4 External Pin Enable 4 1 read-write EXTIEN5 External Pin Enable 5 1 read-write EXTIEN6 External Pin Enable 6 1 read-write EXTIEN7 External Pin Enable 7 1 read-write EXTIEN8 External Pin Enable 8 1 read-write EXTIEN9 External Pin Enable 9 1 read-write EXTIEN10 External Pin Enable 10 1 read-write EXTIEN11 External Pin Enable 11 1 read-write EM4WUIEN0 EM4 Wake Up Interrupt En 16 1 read-write EM4WUIEN1 EM4 Wake Up Interrupt En 17 1 read-write EM4WUIEN2 EM4 Wake Up Interrupt En 18 1 read-write EM4WUIEN3 EM4 Wake Up Interrupt En 19 1 read-write EM4WUIEN4 EM4 Wake Up Interrupt En 20 1 read-write EM4WUIEN5 EM4 Wake Up Interrupt En 21 1 read-write EM4WUIEN6 EM4 Wake Up Interrupt En 22 1 read-write EM4WUIEN7 EM4 Wake Up Interrupt En 23 1 read-write EM4WUIEN8 EM4 Wake Up Interrupt En 24 1 read-write EM4WUIEN9 EM4 Wake Up Interrupt En 25 1 read-write EM4WUIEN10 EM4 Wake Up Interrupt En 26 1 read-write EM4WUIEN11 EM4 Wake Up Interrupt En 27 1 read-write EM4WUEN No Description 0x42C read-write 0x00000000 0x0FFF0000 EM4WUEN EM4 wake up enable 16 12 read-write EM4WUPOL No Description 0x430 read-write 0x00000000 0x0FFF0000 EM4WUPOL EM4 Wake-Up Polarity 16 12 read-write DBGROUTEPEN No Description 0x440 read-write 0x0000000F 0x0000000F SWCLKTCKPEN Route Pin Enable 0 1 read-write SWDIOTMSPEN Route Location 0 1 1 read-write TDOPEN JTAG Test Debug Output Pin Enable 2 1 read-write TDIPEN JTAG Test Debug Input Pin Enable 3 1 read-write TRACEROUTEPEN No Description 0x444 read-write 0x00000000 0x00000007 SWVPEN Serial Wire Viewer Output Pin Enable 0 1 read-write TRACECLKPEN Trace Clk Pin Enable 1 1 read-write TRACEDATA0PEN Trace Data0 Pin Enable 2 1 read-write CMU_ROUTEEN CMU pin enable 0x450 read-write 0x00000000 0x0000000F CLKOUT0PEN CLKOUT0 pin enable control bit 0 1 read-write CLKOUT1PEN CLKOUT1 pin enable control bit 1 1 read-write CLKOUT2PEN CLKOUT2 pin enable control bit 2 1 read-write CMU_CLKIN0ROUTE CLKIN0 port/pin select 0x454 read-write 0x00000000 0x000F0003 PORT CLKIN0 port select register 0 2 read-write PIN CLKIN0 pin select register 16 4 read-write CMU_CLKOUT0ROUTE CLKOUT0 port/pin select 0x458 read-write 0x00000000 0x000F0003 PORT CLKOUT0 port select register 0 2 read-write PIN CLKOUT0 pin select register 16 4 read-write CMU_CLKOUT1ROUTE CLKOUT1 port/pin select 0x45C read-write 0x00000000 0x000F0003 PORT CLKOUT1 port select register 0 2 read-write PIN CLKOUT1 pin select register 16 4 read-write CMU_CLKOUT2ROUTE CLKOUT2 port/pin select 0x460 read-write 0x00000000 0x000F0003 PORT CLKOUT2 port select register 0 2 read-write PIN CLKOUT2 pin select register 16 4 read-write DCDC_ROUTEEN DCDC pin enable 0x46C read-write 0x00000000 0x00000003 DCDCCOREHIDDENPEN DCDCCOREHIDDEN pin enable control bit 0 1 read-write FRC_ROUTEEN FRC pin enable 0x47C read-write 0x00000000 0x00000007 DCLKPEN DCLK pin enable control bit 0 1 read-write DFRAMEPEN DFRAME pin enable control bit 1 1 read-write DOUTPEN DOUT pin enable control bit 2 1 read-write FRC_DCLKROUTE DCLK port/pin select 0x480 read-write 0x00000000 0x000F0003 PORT DCLK port select register 0 2 read-write PIN DCLK pin select register 16 4 read-write FRC_DFRAMEROUTE DFRAME port/pin select 0x484 read-write 0x00000000 0x000F0003 PORT DFRAME port select register 0 2 read-write PIN DFRAME pin select register 16 4 read-write FRC_DOUTROUTE DOUT port/pin select 0x488 read-write 0x00000000 0x000F0003 PORT DOUT port select register 0 2 read-write PIN DOUT pin select register 16 4 read-write I2C0_ROUTEEN I2C0 pin enable 0x490 read-write 0x00000000 0x00000003 SCLPEN SCL pin enable control bit 0 1 read-write SDAPEN SDA pin enable control bit 1 1 read-write I2C0_SCLROUTE SCL port/pin select 0x494 read-write 0x00000000 0x000F0003 PORT SCL port select register 0 2 read-write PIN SCL pin select register 16 4 read-write I2C0_SDAROUTE SDA port/pin select 0x498 read-write 0x00000000 0x000F0003 PORT SDA port select register 0 2 read-write PIN SDA pin select register 16 4 read-write I2C1_ROUTEEN I2C1 pin enable 0x4A0 read-write 0x00000000 0x00000003 SCLPEN SCL pin enable control bit 0 1 read-write SDAPEN SDA pin enable control bit 1 1 read-write I2C1_SCLROUTE SCL port/pin select 0x4A4 read-write 0x00000000 0x000F0003 PORT SCL port select register 0 2 read-write PIN SCL pin select register 16 4 read-write I2C1_SDAROUTE SDA port/pin select 0x4A8 read-write 0x00000000 0x000F0003 PORT SDA port select register 0 2 read-write PIN SDA pin select register 16 4 read-write LETIMER0_ROUTEEN LETIMER pin enable 0x4B0 read-write 0x00000000 0x00000003 OUT0PEN OUT0 pin enable control bit 0 1 read-write OUT1PEN OUT1 pin enable control bit 1 1 read-write LETIMER0_OUT0ROUTE OUT0 port/pin select 0x4B4 read-write 0x00000000 0x000F0003 PORT OUT0 port select register 0 2 read-write PIN OUT0 pin select register 16 4 read-write LETIMER0_OUT1ROUTE OUT1 port/pin select 0x4B8 read-write 0x00000000 0x000F0003 PORT OUT1 port select register 0 2 read-write PIN OUT1 pin select register 16 4 read-write EUART0_ROUTEEN EUART pin enable 0x4C0 read-write 0x00000000 0x00000003 RTSPEN RTS pin enable control bit 0 1 read-write TXPEN TX pin enable control bit 1 1 read-write EUART0_CTSROUTE CTS port/pin select 0x4C4 read-write 0x00000000 0x000F0003 PORT CTS port select register 0 2 read-write PIN CTS pin select register 16 4 read-write EUART0_RTSROUTE RTS port/pin select 0x4C8 read-write 0x00000000 0x000F0003 PORT RTS port select register 0 2 read-write PIN RTS pin select register 16 4 read-write EUART0_RXROUTE RX port/pin select 0x4CC read-write 0x00000000 0x000F0003 PORT RX port select register 0 2 read-write PIN RX pin select register 16 4 read-write EUART0_TXROUTE TX port/pin select 0x4D0 read-write 0x00000000 0x000F0003 PORT TX port select register 0 2 read-write PIN TX pin select register 16 4 read-write MODEM_ROUTEEN MODEM pin enable 0x4D8 read-write 0x00000000 0x00007FFF ANT0PEN ANT0 pin enable control bit 0 1 read-write ANT1PEN ANT1 pin enable control bit 1 1 read-write ANTROLLOVERPEN ANTROLLOVER pin enable control bit 2 1 read-write ANTRR0PEN ANTRR0 pin enable control bit 3 1 read-write ANTRR1PEN ANTRR1 pin enable control bit 4 1 read-write ANTRR2PEN ANTRR2 pin enable control bit 5 1 read-write ANTRR3PEN ANTRR3 pin enable control bit 6 1 read-write ANTRR4PEN ANTRR4 pin enable control bit 7 1 read-write ANTRR5PEN ANTRR5 pin enable control bit 8 1 read-write ANTSWENPEN ANTSWEN pin enable control bit 9 1 read-write ANTSWUSPEN ANTSWUS pin enable control bit 10 1 read-write ANTTRIGPEN ANTTRIG pin enable control bit 11 1 read-write ANTTRIGSTOPPEN ANTTRIGSTOP pin enable control bit 12 1 read-write DCLKPEN DCLK pin enable control bit 13 1 read-write DOUTPEN DOUT pin enable control bit 14 1 read-write MODEM_ANT0ROUTE ANT0 port/pin select 0x4DC read-write 0x00000000 0x000F0003 PORT ANT0 port select register 0 2 read-write PIN ANT0 pin select register 16 4 read-write MODEM_ANT1ROUTE ANT1 port/pin select 0x4E0 read-write 0x00000000 0x000F0003 PORT ANT1 port select register 0 2 read-write PIN ANT1 pin select register 16 4 read-write MODEM_ANTROLLOVERROUTE ANTROLLOVER port/pin select 0x4E4 read-write 0x00000000 0x000F0003 PORT ANTROLLOVER port select register 0 2 read-write PIN ANTROLLOVER pin select register 16 4 read-write MODEM_ANTRR0ROUTE ANTRR0 port/pin select 0x4E8 read-write 0x00000000 0x000F0003 PORT ANTRR0 port select register 0 2 read-write PIN ANTRR0 pin select register 16 4 read-write MODEM_ANTRR1ROUTE ANTRR1 port/pin select 0x4EC read-write 0x00000000 0x000F0003 PORT ANTRR1 port select register 0 2 read-write PIN ANTRR1 pin select register 16 4 read-write MODEM_ANTRR2ROUTE ANTRR2 port/pin select 0x4F0 read-write 0x00000000 0x000F0003 PORT ANTRR2 port select register 0 2 read-write PIN ANTRR2 pin select register 16 4 read-write MODEM_ANTRR3ROUTE ANTRR3 port/pin select 0x4F4 read-write 0x00000000 0x000F0003 PORT ANTRR3 port select register 0 2 read-write PIN ANTRR3 pin select register 16 4 read-write MODEM_ANTRR4ROUTE ANTRR4 port/pin select 0x4F8 read-write 0x00000000 0x000F0003 PORT ANTRR4 port select register 0 2 read-write PIN ANTRR4 pin select register 16 4 read-write MODEM_ANTRR5ROUTE ANTRR5 port/pin select 0x4FC read-write 0x00000000 0x000F0003 PORT ANTRR5 port select register 0 2 read-write PIN ANTRR5 pin select register 16 4 read-write MODEM_ANTSWENROUTE ANTSWEN port/pin select 0x500 read-write 0x00000000 0x000F0003 PORT ANTSWEN port select register 0 2 read-write PIN ANTSWEN pin select register 16 4 read-write MODEM_ANTSWUSROUTE ANTSWUS port/pin select 0x504 read-write 0x00000000 0x000F0003 PORT ANTSWUS port select register 0 2 read-write PIN ANTSWUS pin select register 16 4 read-write MODEM_ANTTRIGROUTE ANTTRIG port/pin select 0x508 read-write 0x00000000 0x000F0003 PORT ANTTRIG port select register 0 2 read-write PIN ANTTRIG pin select register 16 4 read-write MODEM_ANTTRIGSTOPROUTE ANTTRIGSTOP port/pin select 0x50C read-write 0x00000000 0x000F0003 PORT ANTTRIGSTOP port select register 0 2 read-write PIN ANTTRIGSTOP pin select register 16 4 read-write MODEM_DCLKROUTE DCLK port/pin select 0x510 read-write 0x00000000 0x000F0003 PORT DCLK port select register 0 2 read-write PIN DCLK pin select register 16 4 read-write MODEM_DINROUTE DIN port/pin select 0x514 read-write 0x00000000 0x000F0003 PORT DIN port select register 0 2 read-write PIN DIN pin select register 16 4 read-write MODEM_DOUTROUTE DOUT port/pin select 0x518 read-write 0x00000000 0x000F0003 PORT DOUT port select register 0 2 read-write PIN DOUT pin select register 16 4 read-write PDM_ROUTEEN PDM pin enable 0x520 read-write 0x00000000 0x00000001 CLKPEN CLK pin enable control bit 0 1 read-write PDM_CLKROUTE CLK port/pin select 0x524 read-write 0x00000000 0x000F0003 PORT CLK port select register 0 2 read-write PIN CLK pin select register 16 4 read-write PDM_DAT0ROUTE DAT0 port/pin select 0x528 read-write 0x00000000 0x000F0003 PORT DAT0 port select register 0 2 read-write PIN DAT0 pin select register 16 4 read-write PDM_DAT1ROUTE DAT1 port/pin select 0x52C read-write 0x00000000 0x000F0003 PORT DAT1 port select register 0 2 read-write PIN DAT1 pin select register 16 4 read-write PRS0_ROUTEEN PRS0 pin enable 0x534 read-write 0x00000000 0x0000FFFF ASYNCH0PEN ASYNCH0 pin enable control bit 0 1 read-write ASYNCH1PEN ASYNCH1 pin enable control bit 1 1 read-write ASYNCH2PEN ASYNCH2 pin enable control bit 2 1 read-write ASYNCH3PEN ASYNCH3 pin enable control bit 3 1 read-write ASYNCH4PEN ASYNCH4 pin enable control bit 4 1 read-write ASYNCH5PEN ASYNCH5 pin enable control bit 5 1 read-write ASYNCH6PEN ASYNCH6 pin enable control bit 6 1 read-write ASYNCH7PEN ASYNCH7 pin enable control bit 7 1 read-write ASYNCH8PEN ASYNCH8 pin enable control bit 8 1 read-write ASYNCH9PEN ASYNCH9 pin enable control bit 9 1 read-write ASYNCH10PEN ASYNCH10 pin enable control bit 10 1 read-write ASYNCH11PEN ASYNCH11 pin enable control bit 11 1 read-write SYNCH0PEN SYNCH0 pin enable control bit 12 1 read-write SYNCH1PEN SYNCH1 pin enable control bit 13 1 read-write SYNCH2PEN SYNCH2 pin enable control bit 14 1 read-write SYNCH3PEN SYNCH3 pin enable control bit 15 1 read-write PRS0_ASYNCH0ROUTE ASYNCH0 port/pin select 0x538 read-write 0x00000000 0x000F0003 PORT ASYNCH0 port select register 0 2 read-write PIN ASYNCH0 pin select register 16 4 read-write PRS0_ASYNCH1ROUTE ASYNCH1 port/pin select 0x53C read-write 0x00000000 0x000F0003 PORT ASYNCH1 port select register 0 2 read-write PIN ASYNCH1 pin select register 16 4 read-write PRS0_ASYNCH2ROUTE ASYNCH2 port/pin select 0x540 read-write 0x00000000 0x000F0003 PORT ASYNCH2 port select register 0 2 read-write PIN ASYNCH2 pin select register 16 4 read-write PRS0_ASYNCH3ROUTE ASYNCH3 port/pin select 0x544 read-write 0x00000000 0x000F0003 PORT ASYNCH3 port select register 0 2 read-write PIN ASYNCH3 pin select register 16 4 read-write PRS0_ASYNCH4ROUTE ASYNCH4 port/pin select 0x548 read-write 0x00000000 0x000F0003 PORT ASYNCH4 port select register 0 2 read-write PIN ASYNCH4 pin select register 16 4 read-write PRS0_ASYNCH5ROUTE ASYNCH5 port/pin select 0x54C read-write 0x00000000 0x000F0003 PORT ASYNCH5 port select register 0 2 read-write PIN ASYNCH5 pin select register 16 4 read-write PRS0_ASYNCH6ROUTE ASYNCH6 port/pin select 0x550 read-write 0x00000000 0x000F0003 PORT ASYNCH6 port select register 0 2 read-write PIN ASYNCH6 pin select register 16 4 read-write PRS0_ASYNCH7ROUTE ASYNCH7 port/pin select 0x554 read-write 0x00000000 0x000F0003 PORT ASYNCH7 port select register 0 2 read-write PIN ASYNCH7 pin select register 16 4 read-write PRS0_ASYNCH8ROUTE ASYNCH8 port/pin select 0x558 read-write 0x00000000 0x000F0003 PORT ASYNCH8 port select register 0 2 read-write PIN ASYNCH8 pin select register 16 4 read-write PRS0_ASYNCH9ROUTE ASYNCH9 port/pin select 0x55C read-write 0x00000000 0x000F0003 PORT ASYNCH9 port select register 0 2 read-write PIN ASYNCH9 pin select register 16 4 read-write PRS0_ASYNCH10ROUTE ASYNCH10 port/pin select 0x560 read-write 0x00000000 0x000F0003 PORT ASYNCH10 port select register 0 2 read-write PIN ASYNCH10 pin select register 16 4 read-write PRS0_ASYNCH11ROUTE ASYNCH11 port/pin select 0x564 read-write 0x00000000 0x000F0003 PORT ASYNCH11 port select register 0 2 read-write PIN ASYNCH11 pin select register 16 4 read-write PRS0_SYNCH0ROUTE SYNCH0 port/pin select 0x568 read-write 0x00000000 0x000F0003 PORT SYNCH0 port select register 0 2 read-write PIN SYNCH0 pin select register 16 4 read-write PRS0_SYNCH1ROUTE SYNCH1 port/pin select 0x56C read-write 0x00000000 0x000F0003 PORT SYNCH1 port select register 0 2 read-write PIN SYNCH1 pin select register 16 4 read-write PRS0_SYNCH2ROUTE SYNCH2 port/pin select 0x570 read-write 0x00000000 0x000F0003 PORT SYNCH2 port select register 0 2 read-write PIN SYNCH2 pin select register 16 4 read-write PRS0_SYNCH3ROUTE SYNCH3 port/pin select 0x574 read-write 0x00000000 0x000F0003 PORT SYNCH3 port select register 0 2 read-write PIN SYNCH3 pin select register 16 4 read-write TIMER0_ROUTEEN TIMER0 pin enable 0x57C read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER0_CC0ROUTE CC0 port/pin select 0x580 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER0_CC1ROUTE CC1 port/pin select 0x584 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER0_CC2ROUTE CC2 port/pin select 0x588 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER0_CDTI0ROUTE CDTI0 port/pin select 0x58C read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER0_CDTI1ROUTE CDTI1 port/pin select 0x590 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER0_CDTI2ROUTE CDTI2 port/pin select 0x594 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write TIMER1_ROUTEEN TIMER1 pin enable 0x59C read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER1_CC0ROUTE CC0 port/pin select 0x5A0 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER1_CC1ROUTE CC1 port/pin select 0x5A4 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER1_CC2ROUTE CC2 port/pin select 0x5A8 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER1_CDTI0ROUTE CDTI0 port/pin select 0x5AC read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER1_CDTI1ROUTE CDTI1 port/pin select 0x5B0 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER1_CDTI2ROUTE CDTI2 port/pin select 0x5B4 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write TIMER2_ROUTEEN TIMER2 pin enable 0x5BC read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER2_CC0ROUTE CC0 port/pin select 0x5C0 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER2_CC1ROUTE CC1 port/pin select 0x5C4 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER2_CC2ROUTE CC2 port/pin select 0x5C8 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER2_CDTI0ROUTE CDTI0 port/pin select 0x5CC read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER2_CDTI1ROUTE CDTI1 port/pin select 0x5D0 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER2_CDTI2ROUTE CDTI2 port/pin select 0x5D4 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write TIMER3_ROUTEEN TIMER3 pin enable 0x5DC read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER3_CC0ROUTE CC0 port/pin select 0x5E0 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER3_CC1ROUTE CC1 port/pin select 0x5E4 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER3_CC2ROUTE CC2 port/pin select 0x5E8 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER3_CDTI0ROUTE CDTI0 port/pin select 0x5EC read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER3_CDTI1ROUTE CDTI1 port/pin select 0x5F0 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER3_CDTI2ROUTE CDTI2 port/pin select 0x5F4 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write TIMER4_ROUTEEN TIMER4 pin enable 0x5FC read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER4_CC0ROUTE CC0 port/pin select 0x600 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER4_CC1ROUTE CC1 port/pin select 0x604 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER4_CC2ROUTE CC2 port/pin select 0x608 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER4_CDTI0ROUTE CDTI0 port/pin select 0x60C read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER4_CDTI1ROUTE CDTI1 port/pin select 0x610 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER4_CDTI2ROUTE CDTI2 port/pin select 0x614 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write USART0_ROUTEEN USART0 pin enable 0x61C read-write 0x00000000 0x0000001F CSPEN CS pin enable control bit 0 1 read-write RTSPEN RTS pin enable control bit 1 1 read-write RXPEN RX pin enable control bit 2 1 read-write CLKPEN SCLK pin enable control bit 3 1 read-write TXPEN TX pin enable control bit 4 1 read-write USART0_CSROUTE CS port/pin select 0x620 read-write 0x00000000 0x000F0003 PORT CS port select register 0 2 read-write PIN CS pin select register 16 4 read-write USART0_CTSROUTE CTS port/pin select 0x624 read-write 0x00000000 0x000F0003 PORT CTS port select register 0 2 read-write PIN CTS pin select register 16 4 read-write USART0_RTSROUTE RTS port/pin select 0x628 read-write 0x00000000 0x000F0003 PORT RTS port select register 0 2 read-write PIN RTS pin select register 16 4 read-write USART0_RXROUTE RX port/pin select 0x62C read-write 0x00000000 0x000F0003 PORT RX port select register 0 2 read-write PIN RX pin select register 16 4 read-write USART0_CLKROUTE SCLK port/pin select 0x630 read-write 0x00000000 0x000F0003 PORT SCLK port select register 0 2 read-write PIN SCLK pin select register 16 4 read-write USART0_TXROUTE TX port/pin select 0x634 read-write 0x00000000 0x000F0003 PORT TX port select register 0 2 read-write PIN TX pin select register 16 4 read-write USART1_ROUTEEN USART1 pin enable 0x63C read-write 0x00000000 0x0000001F CSPEN CS pin enable control bit 0 1 read-write RTSPEN RTS pin enable control bit 1 1 read-write RXPEN RX pin enable control bit 2 1 read-write CLKPEN SCLK pin enable control bit 3 1 read-write TXPEN TX pin enable control bit 4 1 read-write USART1_CSROUTE CS port/pin select 0x640 read-write 0x00000000 0x000F0003 PORT CS port select register 0 2 read-write PIN CS pin select register 16 4 read-write USART1_CTSROUTE CTS port/pin select 0x644 read-write 0x00000000 0x000F0003 PORT CTS port select register 0 2 read-write PIN CTS pin select register 16 4 read-write USART1_RTSROUTE RTS port/pin select 0x648 read-write 0x00000000 0x000F0003 PORT RTS port select register 0 2 read-write PIN RTS pin select register 16 4 read-write USART1_RXROUTE RX port/pin select 0x64C read-write 0x00000000 0x000F0003 PORT RX port select register 0 2 read-write PIN RX pin select register 16 4 read-write USART1_CLKROUTE SCLK port/pin select 0x650 read-write 0x00000000 0x000F0003 PORT SCLK port select register 0 2 read-write PIN SCLK pin select register 16 4 read-write USART1_TXROUTE TX port/pin select 0x654 read-write 0x00000000 0x000F0003 PORT TX port select register 0 2 read-write PIN TX pin select register 16 4 read-write LDMA_S 0 LDMA_S Registers 0x40040000 0x00000000 0x00001000 registers LDMA 21 IPVERSION No Description 0x000 read-only 0x00000000 0x000000FF IPVERSION IPVERSION 0 8 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN LDMA module enable and disable register 0 1 read-write CTRL No Description 0x008 read-write 0x1E000000 0x9F000000 NUMFIXED Number of Fixed Priority Channels 24 5 read-write CORERST Reset DMA controller 31 1 read-write STATUS No Description 0x00C read-only 0x1F100000 0x1F1F1FFB ANYBUSY Any DMA Channel Busy 0 1 read-only ANYREQ Any DMA Channel Request Pending 1 1 read-only CHGRANT Granted Channel Number 3 5 read-only CHERROR Errant Channel Number 8 5 read-only FIFOLEVEL FIFO Level 16 5 read-only CHNUM Number of Channels 24 5 read-only SYNCSWSET No Description 0x010 write-only 0x00000000 0x000000FF SYNCSWSET DMA SYNC Software Trigger Set 0 8 write-only SYNCSWCLR No Description 0x014 write-only 0x00000000 0x000000FF SYNCSWCLR DMA SYNC Software Trigger Clear 0 8 write-only SYNCHWEN No Description 0x018 read-write 0x00000000 0x00FF00FF SYNCSETEN Hardware Sync Trigger Set Enable 0 8 read-write SYNCCLREN Hardware Sync Trigger Clear Enable 16 8 read-write SYNCHWSEL No Description 0x01C read-write 0x00000000 0x00FF00FF SYNCSETEDGE Hardware Sync Trigger Set Edge Select 0 8 read-write RISE Use rising edge detection 0 FALL Use falling edge detection 1 SYNCCLREDGE Hardware Sync Trigger Clear Edge Select 16 8 read-write RISE Use rising edge detection 0 FALL Use falling edge detection 1 SYNCSTATUS No Description 0x020 read-only 0x00000000 0x000000FF SYNCTRIG sync trig status 0 8 read-only CHEN No Description 0x024 write-only 0x00000000 0x000000FF CHEN Channel Enables 0 8 write-only CHDIS No Description 0x028 write-only 0x00000000 0x000000FF CHDIS DMA Channel disable 0 8 write-only CHSTATUS No Description 0x02C read-only 0x00000000 0x000000FF CHSTATUS DMA Channel Status 0 8 read-only CHBUSY No Description 0x030 read-only 0x00000000 0x000000FF BUSY Channels Busy 0 8 read-only CHDONE No Description 0x034 read-write 0x00000000 0x000000FF CHDONE0 DMA Channel Link done intr flag 0 1 read-write CHDONE1 DMA Channel Link done intr flag 1 1 read-write CHDONE2 DMA Channel Link done intr flag 2 1 read-write CHDONE3 DMA Channel Link done intr flag 3 1 read-write CHDONE4 DMA Channel Link done intr flag 4 1 read-write CHDONE5 DMA Channel Link done intr flag 5 1 read-write CHDONE6 DMA Channel Link done intr flag 6 1 read-write CHDONE7 DMA Channel Link done intr flag 7 1 read-write DBGHALT No Description 0x038 read-write 0x00000000 0x000000FF DBGHALT DMA Debug Halt 0 8 read-write SWREQ No Description 0x03C write-only 0x00000000 0x000000FF SWREQ Software Transfer Requests 0 8 write-only REQDIS No Description 0x040 read-write 0x00000000 0x000000FF REQDIS DMA Request Disables 0 8 read-write REQPEND No Description 0x044 read-only 0x00000000 0x000000FF REQPEND DMA Requests Pending 0 8 read-only LINKLOAD No Description 0x048 write-only 0x00000000 0x000000FF LINKLOAD DMA Link Loads 0 8 write-only REQCLEAR No Description 0x04C write-only 0x00000000 0x000000FF REQCLEAR DMA Request Clear 0 8 write-only IF No Description 0x050 read-write 0x00000000 0x800000FF DONE0 DMA Structure Operation Done 0 1 read-write DONE1 DMA Structure Operation Done 1 1 read-write DONE2 DMA Structure Operation Done 2 1 read-write DONE3 DMA Structure Operation Done 3 1 read-write DONE4 DMA Structure Operation Done 4 1 read-write DONE5 DMA Structure Operation Done 5 1 read-write DONE6 DMA Structure Operation Done 6 1 read-write DONE7 DMA Structure Operation Done 7 1 read-write ERROR Error Flag 31 1 read-write IEN No Description 0x054 read-write 0x00000000 0x800000FF CHDONE Enable or disable the done interrupt 0 8 read-write ERROR Enable or disable the error interrupt 31 1 read-write CH0_CFG No Description 0x05C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH0_LOOP No Description 0x060 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH0_CTRL No Description 0x064 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH0_SRC No Description 0x068 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH0_DST No Description 0x06C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH0_LINK No Description 0x070 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH1_CFG No Description 0x08C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH1_LOOP No Description 0x090 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH1_CTRL No Description 0x094 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH1_SRC No Description 0x098 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH1_DST No Description 0x09C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH1_LINK No Description 0x0A0 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH2_CFG No Description 0x0BC read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH2_LOOP No Description 0x0C0 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH2_CTRL No Description 0x0C4 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH2_SRC No Description 0x0C8 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH2_DST No Description 0x0CC read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH2_LINK No Description 0x0D0 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH3_CFG No Description 0x0EC read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH3_LOOP No Description 0x0F0 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH3_CTRL No Description 0x0F4 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH3_SRC No Description 0x0F8 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH3_DST No Description 0x0FC read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH3_LINK No Description 0x100 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH4_CFG No Description 0x11C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH4_LOOP No Description 0x120 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH4_CTRL No Description 0x124 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH4_SRC No Description 0x128 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH4_DST No Description 0x12C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH4_LINK No Description 0x130 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH5_CFG No Description 0x14C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH5_LOOP No Description 0x150 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH5_CTRL No Description 0x154 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH5_SRC No Description 0x158 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH5_DST No Description 0x15C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH5_LINK No Description 0x160 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH6_CFG No Description 0x17C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH6_LOOP No Description 0x180 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH6_CTRL No Description 0x184 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH6_SRC No Description 0x188 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH6_DST No Description 0x18C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH6_LINK No Description 0x190 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH7_CFG No Description 0x1AC read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH7_LOOP No Description 0x1B0 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH7_CTRL No Description 0x1B4 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH7_SRC No Description 0x1B8 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH7_DST No Description 0x1BC read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH7_LINK No Description 0x1C0 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LDMAXBAR_S 1 LDMAXBAR_S Registers 0x40044000 0x00000000 0x00001000 registers CH0_REQSEL No Description 0x000 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH1_REQSEL No Description 0x004 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH2_REQSEL No Description 0x008 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH3_REQSEL No Description 0x00C read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH4_REQSEL No Description 0x010 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH5_REQSEL No Description 0x014 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH6_REQSEL No Description 0x018 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH7_REQSEL No Description 0x01C read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write TIMER0_S 0 TIMER0_S Registers 0x40048000 0x00000000 0x00001000 registers TIMER0 7 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 RETIMESEL PWM output retime select 12 1 read-write ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0xFFFFFFFF TOP Counter Top Value 0 32 read-write TOPB No Description 0x020 read-write 0x00000000 0xFFFFFFFF TOPB Counter Top Buffer Register 0 32 read-write CNT No Description 0x024 read-write 0x00000000 0xFFFFFFFF CNT Counter Value 0 32 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0xFFFFFFFF OCB Output Compare Value Buffer 0 32 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0xFFFFFFFF ICF Input Capture FIFO 0 32 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0xFFFFFFFF ICOF Input Capture FIFO Overflow 0 32 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0xFFFFFFFF OCB Output Compare Value Buffer 0 32 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0xFFFFFFFF ICF Input Capture FIFO 0 32 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0xFFFFFFFF ICOF Input Capture FIFO Overflow 0 32 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0xFFFFFFFF OCB Output Compare Value Buffer 0 32 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0xFFFFFFFF ICF Input Capture FIFO 0 32 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0xFFFFFFFF ICOF Input Capture FIFO Overflow 0 32 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 TIMER1_S 0 TIMER1_S Registers 0x4004C000 0x00000000 0x00001000 registers TIMER1 8 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 RETIMESEL PWM output retime select 12 1 read-write ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0x0000FFFF TOP Counter Top Value 0 16 read-write TOPB No Description 0x020 read-write 0x00000000 0x0000FFFF TOPB Counter Top Buffer Register 0 16 read-write CNT No Description 0x024 read-write 0x00000000 0x0000FFFF CNT Counter Value 0 16 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 TIMER2_S 0 TIMER2_S Registers 0x40050000 0x00000000 0x00001000 registers TIMER2 9 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 RETIMESEL PWM output retime select 12 1 read-write ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0x0000FFFF TOP Counter Top Value 0 16 read-write TOPB No Description 0x020 read-write 0x00000000 0x0000FFFF TOPB Counter Top Buffer Register 0 16 read-write CNT No Description 0x024 read-write 0x00000000 0x0000FFFF CNT Counter Value 0 16 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 TIMER3_S 0 TIMER3_S Registers 0x40054000 0x00000000 0x00001000 registers TIMER3 10 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 RETIMESEL PWM output retime select 12 1 read-write ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0x0000FFFF TOP Counter Top Value 0 16 read-write TOPB No Description 0x020 read-write 0x00000000 0x0000FFFF TOPB Counter Top Buffer Register 0 16 read-write CNT No Description 0x024 read-write 0x00000000 0x0000FFFF CNT Counter Value 0 16 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 TIMER4_S 0 TIMER4_S Registers 0x40058000 0x00000000 0x00001000 registers TIMER4 11 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 RETIMESEL PWM output retime select 12 1 read-write ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0x0000FFFF TOP Counter Top Value 0 16 read-write TOPB No Description 0x020 read-write 0x00000000 0x0000FFFF TOPB Counter Top Buffer Register 0 16 read-write CNT No Description 0x024 read-write 0x00000000 0x0000FFFF CNT Counter Value 0 16 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 USART0_S 0 USART0_S Registers 0x4005C000 0x00000000 0x00001000 registers USART0_RX 13 USART0_TX 14 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IPVERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN USART Enable 0 1 read-write CTRL No Description 0x008 read-write 0x00000000 0xF3FFFF7F SYNC USART Synchronous Mode 0 1 read-write DISABLE The USART operates in asynchronous mode 0 ENABLE The USART operates in synchronous mode 1 LOOPBK Loopback Enable 1 1 read-write DISABLE The receiver is connected to and receives data from U(S)n_RX 0 ENABLE The receiver is connected to and receives data from U(S)n_TX 1 CCEN Collision Check Enable 2 1 read-write DISABLE Collision check is disabled 0 ENABLE Collision check is enabled. The receiver must be enabled for the check to be performed 1 MPM Multi-Processor Mode 3 1 read-write DISABLE The 9th bit of incoming frames has no special function 0 ENABLE An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set 1 MPAB Multi-Processor Address-Bit 4 1 read-write OVS Oversampling 5 2 read-write X16 Regular UART mode with 16X oversampling in asynchronous mode 0 X8 Double speed with 8X oversampling in asynchronous mode 1 X6 6X oversampling in asynchronous mode 2 X4 Quadruple speed with 4X oversampling in asynchronous mode 3 CLKPOL Clock Polarity 8 1 read-write IDLELOW The bus clock used in synchronous mode has a low base value 0 IDLEHIGH The bus clock used in synchronous mode has a high base value 1 CLKPHA Clock Edge For Setup/Sample 9 1 read-write SAMPLELEADING Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode 0 SAMPLETRAILING Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode 1 MSBF Most Significant Bit First 10 1 read-write DISABLE Data is sent with the least significant bit first 0 ENABLE Data is sent with the most significant bit first 1 CSMA Action On Chip Select In Main Mode 11 1 read-write NOACTION No action taken 0 GOTOSLAVEMODE Go to secondary mode 1 TXBIL TX Buffer Interrupt Level 12 1 read-write EMPTY TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALFFULL TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full. 1 RXINV Receiver Input Invert 13 1 read-write DISABLE Input is passed directly to the receiver 0 ENABLE Input is inverted before it is passed to the receiver 1 TXINV Transmitter output Invert 14 1 read-write DISABLE Output from the transmitter is passed unchanged to U(S)n_TX 0 ENABLE Output from the transmitter is inverted before it is passed to U(S)n_TX 1 CSINV Chip Select Invert 15 1 read-write DISABLE Chip select is active low 0 ENABLE Chip select is active high 1 AUTOCS Automatic Chip Select 16 1 read-write AUTOTRI Automatic TX Tristate 17 1 read-write DISABLE The output on U(S)n_TX when the transmitter is idle is defined by TXINV 0 ENABLE U(S)n_TX is tristated whenever the transmitter is idle 1 SCMODE SmartCard Mode 18 1 read-write SCRETRANS SmartCard Retransmit 19 1 read-write SKIPPERRF Skip Parity Error Frames 20 1 read-write BIT8DV Bit 8 Default Value 21 1 read-write ERRSDMA Halt DMA On Error 22 1 read-write DISABLE Framing and parity errors have no effect on DMA requests from the USART 0 ENABLE DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set 1 ERRSRX Disable RX On Error 23 1 read-write DISABLE Framing and parity errors have no effect on receiver 0 ENABLE Framing and parity errors disable the receiver 1 ERRSTX Disable TX On Error 24 1 read-write DISABLE Received framing and parity errors have no effect on transmitter 0 ENABLE Received framing and parity errors disable the transmitter 1 SSSEARLY Synchronous Secondary Setup Early 25 1 read-write BYTESWAP Byteswap In Double Accesses 28 1 read-write DISABLE Normal byte order 0 ENABLE Byte order swapped 1 AUTOTX Always Transmit When RX Not Full 29 1 read-write MVDIS Majority Vote Disable 30 1 read-write SMSDELAY Synchronous Main Sample Delay 31 1 read-write FRAME No Description 0x00C read-write 0x00001005 0x0000330F DATABITS Data-Bit Mode 0 4 read-write FOUR Each frame contains 4 data bits 1 FIVE Each frame contains 5 data bits 2 SIX Each frame contains 6 data bits 3 SEVEN Each frame contains 7 data bits 4 EIGHT Each frame contains 8 data bits 5 NINE Each frame contains 9 data bits 6 TEN Each frame contains 10 data bits 7 ELEVEN Each frame contains 11 data bits 8 TWELVE Each frame contains 12 data bits 9 THIRTEEN Each frame contains 13 data bits 10 FOURTEEN Each frame contains 14 data bits 11 FIFTEEN Each frame contains 15 data bits 12 SIXTEEN Each frame contains 16 data bits 13 PARITY Parity-Bit Mode 8 2 read-write NONE Parity bits are not used 0 EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. 2 ODD Odd parity is used. Parity bits are automatically generated and checked by hardware. 3 STOPBITS Stop-Bit Mode 12 2 read-write HALF The transmitter generates a half stop bit. Stop-bits are not verified by receiver 0 ONE One stop bit is generated and verified 1 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies the first stop bit 2 TWO The transmitter generates two stop bits. The receiver checks the first stop-bit only 3 TRIGCTRL No Description 0x010 read-write 0x00000000 0x00001FF0 RXTEN Receive Trigger Enable 4 1 read-write TXTEN Transmit Trigger Enable 5 1 read-write AUTOTXTEN AUTOTX Trigger Enable 6 1 read-write TXARX0EN Enable Transmit Trigger after RX End of 7 1 read-write TXARX1EN Enable Transmit Trigger after RX End of 8 1 read-write TXARX2EN Enable Transmit Trigger after RX End of 9 1 read-write RXATX0EN Enable Receive Trigger after TX end of f 10 1 read-write RXATX1EN Enable Receive Trigger after TX end of f 11 1 read-write RXATX2EN Enable Receive Trigger after TX end of f 12 1 read-write CMD No Description 0x014 write-only 0x00000000 0x00000FFF RXEN Receiver Enable 0 1 write-only RXDIS Receiver Disable 1 1 write-only TXEN Transmitter Enable 2 1 write-only TXDIS Transmitter Disable 3 1 write-only MASTEREN Main Mode Enable 4 1 write-only MASTERDIS Main Mode Disable 5 1 write-only RXBLOCKEN Receiver Block Enable 6 1 write-only RXBLOCKDIS Receiver Block Disable 7 1 write-only TXTRIEN Transmitter Tristate Enable 8 1 write-only TXTRIDIS Transmitter Tristate Disable 9 1 write-only CLEARTX Clear TX 10 1 write-only CLEARRX Clear RX 11 1 write-only STATUS No Description 0x018 read-only 0x00002040 0x00037FFF RXENS Receiver Enable Status 0 1 read-only TXENS Transmitter Enable Status 1 1 read-only MASTER SPI Main Mode 2 1 read-only RXBLOCK Block Incoming Data 3 1 read-only TXTRI Transmitter Tristated 4 1 read-only TXC TX Complete 5 1 read-only TXBL TX Buffer Level 6 1 read-only RXDATAV RX Data Valid 7 1 read-only RXFULL RX FIFO Full 8 1 read-only TXBDRIGHT TX Buffer Expects Double Right Data 9 1 read-only TXBSRIGHT TX Buffer Expects Single Right Data 10 1 read-only RXDATAVRIGHT RX Data Right 11 1 read-only RXFULLRIGHT RX Full of Right Data 12 1 read-only TXIDLE TX Idle 13 1 read-only TIMERRESTARTED The USART Timer restarted itself 14 1 read-only TXBUFCNT TX Buffer Count 16 2 read-only CLKDIV No Description 0x01C read-write 0x00000000 0x807FFFF8 DIV Fractional Clock Divider 3 20 read-write AUTOBAUDEN AUTOBAUD detection enable 31 1 read-write RXDATAX No Description 0x020 read-only 0x00000000 0x0000C1FF RXDATA RX Data 0 9 read-only PERR Data Parity Error 14 1 read-only FERR Data Framing Error 15 1 read-only RXDATA No Description 0x024 read-only 0x00000000 0x000000FF RXDATA RX Data 0 8 read-only RXDOUBLEX No Description 0x028 read-only 0x00000000 0xC1FFC1FF RXDATA0 RX Data 0 0 9 read-only PERR0 Data Parity Error 0 14 1 read-only FERR0 Data Framing Error 0 15 1 read-only RXDATA1 RX Data 1 16 9 read-only PERR1 Data Parity Error 1 30 1 read-only FERR1 Data Framing Error 1 31 1 read-only RXDOUBLE No Description 0x02C read-only 0x00000000 0x0000FFFF RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDATAXP No Description 0x030 read-only 0x00000000 0x0000C1FF RXDATAP RX Data Peek 0 9 read-only PERRP Data Parity Error Peek 14 1 read-only FERRP Data Framing Error Peek 15 1 read-only RXDOUBLEXP No Description 0x034 read-only 0x00000000 0xC1FFC1FF RXDATAP0 RX Data 0 Peek 0 9 read-only PERRP0 Data Parity Error 0 Peek 14 1 read-only FERRP0 Data Framing Error 0 Peek 15 1 read-only RXDATAP1 RX Data 1 Peek 16 9 read-only PERRP1 Data Parity Error 1 Peek 30 1 read-only FERRP1 Data Framing Error 1 Peek 31 1 read-only TXDATAX No Description 0x038 write-only 0x00000000 0x0000F9FF TXDATAX TX Data 0 9 write-only UBRXAT Unblock RX After Transmission 11 1 write-only TXTRIAT Set TXTRI After Transmission 12 1 write-only TXBREAK Transmit Data As Break 13 1 write-only TXDISAT Clear TXEN After Transmission 14 1 write-only RXENAT Enable RX After Transmission 15 1 write-only TXDATA No Description 0x03C write-only 0x00000000 0x000000FF TXDATA TX Data 0 8 write-only TXDOUBLEX No Description 0x040 write-only 0x00000000 0xF9FFF9FF TXDATA0 TX Data 0 9 write-only UBRXAT0 Unblock RX After Transmission 11 1 write-only TXTRIAT0 Set TXTRI After Transmission 12 1 write-only TXBREAK0 Transmit Data As Break 13 1 write-only TXDISAT0 Clear TXEN After Transmission 14 1 write-only RXENAT0 Enable RX After Transmission 15 1 write-only TXDATA1 TX Data 16 9 write-only UBRXAT1 Unblock RX After Transmission 27 1 write-only TXTRIAT1 Set TXTRI After Transmission 28 1 write-only TXBREAK1 Transmit Data As Break 29 1 write-only TXDISAT1 Clear TXEN After Transmission 30 1 write-only RXENAT1 Enable RX After Transmission 31 1 write-only TXDOUBLE No Description 0x044 write-only 0x00000000 0x0000FFFF TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only IF No Description 0x048 read-write 0x00000002 0x0001FFFF TXC TX Complete Interrupt Flag 0 1 read-write TXBL TX Buffer Level Interrupt Flag 1 1 read-write RXDATAV RX Data Valid Interrupt Flag 2 1 read-write RXFULL RX Buffer Full Interrupt Flag 3 1 read-write RXOF RX Overflow Interrupt Flag 4 1 read-write RXUF RX Underflow Interrupt Flag 5 1 read-write TXOF TX Overflow Interrupt Flag 6 1 read-write TXUF TX Underflow Interrupt Flag 7 1 read-write PERR Parity Error Interrupt Flag 8 1 read-write FERR Framing Error Interrupt Flag 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write SSM Chip-Select In Main Mode Interrupt Flag 11 1 read-write CCF Collision Check Fail Interrupt Flag 12 1 read-write TXIDLE TX Idle Interrupt Flag 13 1 read-write TCMP0 Timer comparator 0 Interrupt Flag 14 1 read-write TCMP1 Timer comparator 1 Interrupt Flag 15 1 read-write TCMP2 Timer comparator 2 Interrupt Flag 16 1 read-write IEN No Description 0x04C read-write 0x00000000 0x0001FFFF TXC TX Complete Interrupt Enable 0 1 read-write TXBL TX Buffer Level Interrupt Enable 1 1 read-write RXDATAV RX Data Valid Interrupt Enable 2 1 read-write RXFULL RX Buffer Full Interrupt Enable 3 1 read-write RXOF RX Overflow Interrupt Enable 4 1 read-write RXUF RX Underflow Interrupt Enable 5 1 read-write TXOF TX Overflow Interrupt Enable 6 1 read-write TXUF TX Underflow Interrupt Enable 7 1 read-write PERR Parity Error Interrupt Enable 8 1 read-write FERR Framing Error Interrupt Enable 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write SSM Chip-Select In Main Mode Interrupt Flag 11 1 read-write CCF Collision Check Fail Interrupt Enable 12 1 read-write TXIDLE TX Idle Interrupt Enable 13 1 read-write TCMP0 Timer comparator 0 Interrupt Enable 14 1 read-write TCMP1 Timer comparator 1 Interrupt Enable 15 1 read-write TCMP2 Timer comparator 2 Interrupt Enable 16 1 read-write IRCTRL No Description 0x050 read-write 0x00000000 0x0000008F IREN Enable IrDA Module 0 1 read-write IRPW IrDA TX Pulse Width 1 2 read-write ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 0 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 2 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 3 IRFILT IrDA RX Filter 3 1 read-write DISABLE No filter enabled 0 ENABLE Filter enabled. IrDA pulse must be high for at least 5 consecutive clock cycles to be detected 1 I2SCTRL No Description 0x054 read-write 0x00000000 0x0000071F EN Enable I2S Mode 0 1 read-write MONO Stero or Mono 1 1 read-write JUSTIFY Justification of I2S Data 2 1 read-write LEFT Data is left-justified 0 RIGHT Data is right-justified 1 DMASPLIT Separate DMA Request For Left/Right Data 3 1 read-write DELAY Delay on I2S data 4 1 read-write FORMAT I2S Word Format 8 3 read-write W32D32 32-bit word, 32-bit data 0 W32D24M 32-bit word, 32-bit data with 8 lsb masked 1 W32D24 32-bit word, 24-bit data 2 W32D16 32-bit word, 16-bit data 3 W32D8 32-bit word, 8-bit data 4 W16D16 16-bit word, 16-bit data 5 W16D8 16-bit word, 8-bit data 6 W8D8 8-bit word, 8-bit data 7 TIMING No Description 0x058 read-write 0x00000000 0x77770000 TXDELAY TX frame start delay 16 3 read-write DISABLE Disable - TXDELAY in USARTn_CTRL can be used for legacy 0 ONE Start of transmission is delayed for 1 baud-times 1 TWO Start of transmission is delayed for 2 baud-times 2 THREE Start of transmission is delayed for 3 baud-times 3 SEVEN Start of transmission is delayed for 7 baud-times 4 TCMP0 Start of transmission is delayed for TCMPVAL0 baud-times 5 TCMP1 Start of transmission is delayed for TCMPVAL1 baud-times 6 TCMP2 Start of transmission is delayed for TCMPVAL2 baud-times 7 CSSETUP Chip Select Setup 20 3 read-write ZERO CS is not asserted before start of transmission 0 ONE CS is asserted for 1 baud-times before start of transmission 1 TWO CS is asserted for 2 baud-times before start of transmission 2 THREE CS is asserted for 3 baud-times before start of transmission 3 SEVEN CS is asserted for 7 baud-times before start of transmission 4 TCMP0 CS is asserted before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted before the start of transmission for TCMPVAL2 baud-times 7 ICS Inter-character spacing 24 3 read-write ZERO There is no space between charcters 0 ONE Create a space of 1 baud-times before start of transmission 1 TWO Create a space of 2 baud-times before start of transmission 2 THREE Create a space of 3 baud-times before start of transmission 3 SEVEN Create a space of 7 baud-times before start of transmission 4 TCMP0 Create a space of before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 Create a space of before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 Create a space of before the start of transmission for TCMPVAL2 baud-times 7 CSHOLD Chip Select Hold 28 3 read-write ZERO Disable CS being asserted after the end of transmission 0 ONE CS is asserted for 1 baud-times after the end of transmission 1 TWO CS is asserted for 2 baud-times after the end of transmission 2 THREE CS is asserted for 3 baud-times after the end of transmission 3 SEVEN CS is asserted for 7 baud-times after the end of transmission 4 TCMP0 CS is asserted after the end of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted after the end of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted after the end of transmission for TCMPVAL2 baud-times 7 CTRLX No Description 0x05C read-write 0x00000000 0x8000808F DBGHALT Debug halt 0 1 read-write DISABLE Continue to transmit until TX buffer is empty 0 ENABLE Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock; otherwise, each single step could transmit multiple frames instead of just transmitting one frame. 1 CTSINV CTS Pin Inversion 1 1 read-write DISABLE The USn_CTS pin is low true 0 ENABLE The USn_CTS pin is high true 1 CTSEN CTS Function enabled 2 1 read-write DISABLE Ingore CTS 0 ENABLE Stop transmitting when CTS is negated 1 RTSINV RTS Pin Inversion 3 1 read-write DISABLE The USn_RTS pin is low true 0 ENABLE The USn_RTS pin is high true 1 RXPRSEN PRS RX Enable 7 1 read-write CLKPRSEN PRS CLK Enable 15 1 read-write TIMECMP0 No Description 0x060 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 0. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 0 is disabled 0 TXEOF Comparator 0 and timer are started at TX end of frame 1 TXC Comparator 0 and timer are started at TX Complete 2 RXACT Comparator 0 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 0 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 0 20 3 read-write TCMP0 Comparator 0 is disabled when the counter equals TCMPVAL and triggers a TCMP0 event 0 TXST Comparator 0 is disabled at TX start TX Engine 1 RXACT Comparator 0 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 0 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP0 24 1 read-write DISABLE Disable the timer restarting on TCMP0 0 ENABLE Enable the timer restarting on TCMP0 1 TIMECMP1 No Description 0x064 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 1. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 1 is disabled 0 TXEOF Comparator 1 and timer are started at TX end of frame 1 TXC Comparator 1 and timer are started at TX Complete 2 RXACT Comparator 1 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 1 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 1 20 3 read-write TCMP1 Comparator 1 is disabled when the counter equals TCMPVAL and triggers a TCMP1 event 0 TXST Comparator 1 is disabled at TX start TX Engine 1 RXACT Comparator 1 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 1 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP1 24 1 read-write DISABLE Disable the timer restarting on TCMP1 0 ENABLE Enable the timer restarting on TCMP1 1 TIMECMP2 No Description 0x068 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 2. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 2 is disabled 0 TXEOF Comparator 2 and timer are started at TX end of frame 1 TXC Comparator 2 and timer are started at TX Complete 2 RXACT Comparator 2 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 2 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 2 20 3 read-write TCMP2 Comparator 2 is disabled when the counter equals TCMPVAL and triggers a TCMP2 event 0 TXST Comparator 2 is disabled at TX start TX Engine 1 RXACT Comparator 2 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 2 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP2 24 1 read-write DISABLE Disable the timer restarting on TCMP2 0 ENABLE Enable the timer restarting on TCMP2 1 USART1_S 0 USART1_S Registers 0x40060000 0x00000000 0x00001000 registers USART1_RX 15 USART1_TX 16 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IPVERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN USART Enable 0 1 read-write CTRL No Description 0x008 read-write 0x00000000 0xF3FFFF7F SYNC USART Synchronous Mode 0 1 read-write DISABLE The USART operates in asynchronous mode 0 ENABLE The USART operates in synchronous mode 1 LOOPBK Loopback Enable 1 1 read-write DISABLE The receiver is connected to and receives data from U(S)n_RX 0 ENABLE The receiver is connected to and receives data from U(S)n_TX 1 CCEN Collision Check Enable 2 1 read-write DISABLE Collision check is disabled 0 ENABLE Collision check is enabled. The receiver must be enabled for the check to be performed 1 MPM Multi-Processor Mode 3 1 read-write DISABLE The 9th bit of incoming frames has no special function 0 ENABLE An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set 1 MPAB Multi-Processor Address-Bit 4 1 read-write OVS Oversampling 5 2 read-write X16 Regular UART mode with 16X oversampling in asynchronous mode 0 X8 Double speed with 8X oversampling in asynchronous mode 1 X6 6X oversampling in asynchronous mode 2 X4 Quadruple speed with 4X oversampling in asynchronous mode 3 CLKPOL Clock Polarity 8 1 read-write IDLELOW The bus clock used in synchronous mode has a low base value 0 IDLEHIGH The bus clock used in synchronous mode has a high base value 1 CLKPHA Clock Edge For Setup/Sample 9 1 read-write SAMPLELEADING Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode 0 SAMPLETRAILING Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode 1 MSBF Most Significant Bit First 10 1 read-write DISABLE Data is sent with the least significant bit first 0 ENABLE Data is sent with the most significant bit first 1 CSMA Action On Chip Select In Main Mode 11 1 read-write NOACTION No action taken 0 GOTOSLAVEMODE Go to secondary mode 1 TXBIL TX Buffer Interrupt Level 12 1 read-write EMPTY TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALFFULL TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full. 1 RXINV Receiver Input Invert 13 1 read-write DISABLE Input is passed directly to the receiver 0 ENABLE Input is inverted before it is passed to the receiver 1 TXINV Transmitter output Invert 14 1 read-write DISABLE Output from the transmitter is passed unchanged to U(S)n_TX 0 ENABLE Output from the transmitter is inverted before it is passed to U(S)n_TX 1 CSINV Chip Select Invert 15 1 read-write DISABLE Chip select is active low 0 ENABLE Chip select is active high 1 AUTOCS Automatic Chip Select 16 1 read-write AUTOTRI Automatic TX Tristate 17 1 read-write DISABLE The output on U(S)n_TX when the transmitter is idle is defined by TXINV 0 ENABLE U(S)n_TX is tristated whenever the transmitter is idle 1 SCMODE SmartCard Mode 18 1 read-write SCRETRANS SmartCard Retransmit 19 1 read-write SKIPPERRF Skip Parity Error Frames 20 1 read-write BIT8DV Bit 8 Default Value 21 1 read-write ERRSDMA Halt DMA On Error 22 1 read-write DISABLE Framing and parity errors have no effect on DMA requests from the USART 0 ENABLE DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set 1 ERRSRX Disable RX On Error 23 1 read-write DISABLE Framing and parity errors have no effect on receiver 0 ENABLE Framing and parity errors disable the receiver 1 ERRSTX Disable TX On Error 24 1 read-write DISABLE Received framing and parity errors have no effect on transmitter 0 ENABLE Received framing and parity errors disable the transmitter 1 SSSEARLY Synchronous Secondary Setup Early 25 1 read-write BYTESWAP Byteswap In Double Accesses 28 1 read-write DISABLE Normal byte order 0 ENABLE Byte order swapped 1 AUTOTX Always Transmit When RX Not Full 29 1 read-write MVDIS Majority Vote Disable 30 1 read-write SMSDELAY Synchronous Main Sample Delay 31 1 read-write FRAME No Description 0x00C read-write 0x00001005 0x0000330F DATABITS Data-Bit Mode 0 4 read-write FOUR Each frame contains 4 data bits 1 FIVE Each frame contains 5 data bits 2 SIX Each frame contains 6 data bits 3 SEVEN Each frame contains 7 data bits 4 EIGHT Each frame contains 8 data bits 5 NINE Each frame contains 9 data bits 6 TEN Each frame contains 10 data bits 7 ELEVEN Each frame contains 11 data bits 8 TWELVE Each frame contains 12 data bits 9 THIRTEEN Each frame contains 13 data bits 10 FOURTEEN Each frame contains 14 data bits 11 FIFTEEN Each frame contains 15 data bits 12 SIXTEEN Each frame contains 16 data bits 13 PARITY Parity-Bit Mode 8 2 read-write NONE Parity bits are not used 0 EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. 2 ODD Odd parity is used. Parity bits are automatically generated and checked by hardware. 3 STOPBITS Stop-Bit Mode 12 2 read-write HALF The transmitter generates a half stop bit. Stop-bits are not verified by receiver 0 ONE One stop bit is generated and verified 1 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies the first stop bit 2 TWO The transmitter generates two stop bits. The receiver checks the first stop-bit only 3 TRIGCTRL No Description 0x010 read-write 0x00000000 0x00001FF0 RXTEN Receive Trigger Enable 4 1 read-write TXTEN Transmit Trigger Enable 5 1 read-write AUTOTXTEN AUTOTX Trigger Enable 6 1 read-write TXARX0EN Enable Transmit Trigger after RX End of 7 1 read-write TXARX1EN Enable Transmit Trigger after RX End of 8 1 read-write TXARX2EN Enable Transmit Trigger after RX End of 9 1 read-write RXATX0EN Enable Receive Trigger after TX end of f 10 1 read-write RXATX1EN Enable Receive Trigger after TX end of f 11 1 read-write RXATX2EN Enable Receive Trigger after TX end of f 12 1 read-write CMD No Description 0x014 write-only 0x00000000 0x00000FFF RXEN Receiver Enable 0 1 write-only RXDIS Receiver Disable 1 1 write-only TXEN Transmitter Enable 2 1 write-only TXDIS Transmitter Disable 3 1 write-only MASTEREN Main Mode Enable 4 1 write-only MASTERDIS Main Mode Disable 5 1 write-only RXBLOCKEN Receiver Block Enable 6 1 write-only RXBLOCKDIS Receiver Block Disable 7 1 write-only TXTRIEN Transmitter Tristate Enable 8 1 write-only TXTRIDIS Transmitter Tristate Disable 9 1 write-only CLEARTX Clear TX 10 1 write-only CLEARRX Clear RX 11 1 write-only STATUS No Description 0x018 read-only 0x00002040 0x00037FFF RXENS Receiver Enable Status 0 1 read-only TXENS Transmitter Enable Status 1 1 read-only MASTER SPI Main Mode 2 1 read-only RXBLOCK Block Incoming Data 3 1 read-only TXTRI Transmitter Tristated 4 1 read-only TXC TX Complete 5 1 read-only TXBL TX Buffer Level 6 1 read-only RXDATAV RX Data Valid 7 1 read-only RXFULL RX FIFO Full 8 1 read-only TXBDRIGHT TX Buffer Expects Double Right Data 9 1 read-only TXBSRIGHT TX Buffer Expects Single Right Data 10 1 read-only RXDATAVRIGHT RX Data Right 11 1 read-only RXFULLRIGHT RX Full of Right Data 12 1 read-only TXIDLE TX Idle 13 1 read-only TIMERRESTARTED The USART Timer restarted itself 14 1 read-only TXBUFCNT TX Buffer Count 16 2 read-only CLKDIV No Description 0x01C read-write 0x00000000 0x807FFFF8 DIV Fractional Clock Divider 3 20 read-write AUTOBAUDEN AUTOBAUD detection enable 31 1 read-write RXDATAX No Description 0x020 read-only 0x00000000 0x0000C1FF RXDATA RX Data 0 9 read-only PERR Data Parity Error 14 1 read-only FERR Data Framing Error 15 1 read-only RXDATA No Description 0x024 read-only 0x00000000 0x000000FF RXDATA RX Data 0 8 read-only RXDOUBLEX No Description 0x028 read-only 0x00000000 0xC1FFC1FF RXDATA0 RX Data 0 0 9 read-only PERR0 Data Parity Error 0 14 1 read-only FERR0 Data Framing Error 0 15 1 read-only RXDATA1 RX Data 1 16 9 read-only PERR1 Data Parity Error 1 30 1 read-only FERR1 Data Framing Error 1 31 1 read-only RXDOUBLE No Description 0x02C read-only 0x00000000 0x0000FFFF RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDATAXP No Description 0x030 read-only 0x00000000 0x0000C1FF RXDATAP RX Data Peek 0 9 read-only PERRP Data Parity Error Peek 14 1 read-only FERRP Data Framing Error Peek 15 1 read-only RXDOUBLEXP No Description 0x034 read-only 0x00000000 0xC1FFC1FF RXDATAP0 RX Data 0 Peek 0 9 read-only PERRP0 Data Parity Error 0 Peek 14 1 read-only FERRP0 Data Framing Error 0 Peek 15 1 read-only RXDATAP1 RX Data 1 Peek 16 9 read-only PERRP1 Data Parity Error 1 Peek 30 1 read-only FERRP1 Data Framing Error 1 Peek 31 1 read-only TXDATAX No Description 0x038 write-only 0x00000000 0x0000F9FF TXDATAX TX Data 0 9 write-only UBRXAT Unblock RX After Transmission 11 1 write-only TXTRIAT Set TXTRI After Transmission 12 1 write-only TXBREAK Transmit Data As Break 13 1 write-only TXDISAT Clear TXEN After Transmission 14 1 write-only RXENAT Enable RX After Transmission 15 1 write-only TXDATA No Description 0x03C write-only 0x00000000 0x000000FF TXDATA TX Data 0 8 write-only TXDOUBLEX No Description 0x040 write-only 0x00000000 0xF9FFF9FF TXDATA0 TX Data 0 9 write-only UBRXAT0 Unblock RX After Transmission 11 1 write-only TXTRIAT0 Set TXTRI After Transmission 12 1 write-only TXBREAK0 Transmit Data As Break 13 1 write-only TXDISAT0 Clear TXEN After Transmission 14 1 write-only RXENAT0 Enable RX After Transmission 15 1 write-only TXDATA1 TX Data 16 9 write-only UBRXAT1 Unblock RX After Transmission 27 1 write-only TXTRIAT1 Set TXTRI After Transmission 28 1 write-only TXBREAK1 Transmit Data As Break 29 1 write-only TXDISAT1 Clear TXEN After Transmission 30 1 write-only RXENAT1 Enable RX After Transmission 31 1 write-only TXDOUBLE No Description 0x044 write-only 0x00000000 0x0000FFFF TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only IF No Description 0x048 read-write 0x00000002 0x0001FFFF TXC TX Complete Interrupt Flag 0 1 read-write TXBL TX Buffer Level Interrupt Flag 1 1 read-write RXDATAV RX Data Valid Interrupt Flag 2 1 read-write RXFULL RX Buffer Full Interrupt Flag 3 1 read-write RXOF RX Overflow Interrupt Flag 4 1 read-write RXUF RX Underflow Interrupt Flag 5 1 read-write TXOF TX Overflow Interrupt Flag 6 1 read-write TXUF TX Underflow Interrupt Flag 7 1 read-write PERR Parity Error Interrupt Flag 8 1 read-write FERR Framing Error Interrupt Flag 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write SSM Chip-Select In Main Mode Interrupt Flag 11 1 read-write CCF Collision Check Fail Interrupt Flag 12 1 read-write TXIDLE TX Idle Interrupt Flag 13 1 read-write TCMP0 Timer comparator 0 Interrupt Flag 14 1 read-write TCMP1 Timer comparator 1 Interrupt Flag 15 1 read-write TCMP2 Timer comparator 2 Interrupt Flag 16 1 read-write IEN No Description 0x04C read-write 0x00000000 0x0001FFFF TXC TX Complete Interrupt Enable 0 1 read-write TXBL TX Buffer Level Interrupt Enable 1 1 read-write RXDATAV RX Data Valid Interrupt Enable 2 1 read-write RXFULL RX Buffer Full Interrupt Enable 3 1 read-write RXOF RX Overflow Interrupt Enable 4 1 read-write RXUF RX Underflow Interrupt Enable 5 1 read-write TXOF TX Overflow Interrupt Enable 6 1 read-write TXUF TX Underflow Interrupt Enable 7 1 read-write PERR Parity Error Interrupt Enable 8 1 read-write FERR Framing Error Interrupt Enable 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write SSM Chip-Select In Main Mode Interrupt Flag 11 1 read-write CCF Collision Check Fail Interrupt Enable 12 1 read-write TXIDLE TX Idle Interrupt Enable 13 1 read-write TCMP0 Timer comparator 0 Interrupt Enable 14 1 read-write TCMP1 Timer comparator 1 Interrupt Enable 15 1 read-write TCMP2 Timer comparator 2 Interrupt Enable 16 1 read-write IRCTRL No Description 0x050 read-write 0x00000000 0x0000008F IREN Enable IrDA Module 0 1 read-write IRPW IrDA TX Pulse Width 1 2 read-write ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 0 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 2 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 3 IRFILT IrDA RX Filter 3 1 read-write DISABLE No filter enabled 0 ENABLE Filter enabled. IrDA pulse must be high for at least 5 consecutive clock cycles to be detected 1 I2SCTRL No Description 0x054 read-write 0x00000000 0x0000071F EN Enable I2S Mode 0 1 read-write MONO Stero or Mono 1 1 read-write JUSTIFY Justification of I2S Data 2 1 read-write LEFT Data is left-justified 0 RIGHT Data is right-justified 1 DMASPLIT Separate DMA Request For Left/Right Data 3 1 read-write DELAY Delay on I2S data 4 1 read-write FORMAT I2S Word Format 8 3 read-write W32D32 32-bit word, 32-bit data 0 W32D24M 32-bit word, 32-bit data with 8 lsb masked 1 W32D24 32-bit word, 24-bit data 2 W32D16 32-bit word, 16-bit data 3 W32D8 32-bit word, 8-bit data 4 W16D16 16-bit word, 16-bit data 5 W16D8 16-bit word, 8-bit data 6 W8D8 8-bit word, 8-bit data 7 TIMING No Description 0x058 read-write 0x00000000 0x77770000 TXDELAY TX frame start delay 16 3 read-write DISABLE Disable - TXDELAY in USARTn_CTRL can be used for legacy 0 ONE Start of transmission is delayed for 1 baud-times 1 TWO Start of transmission is delayed for 2 baud-times 2 THREE Start of transmission is delayed for 3 baud-times 3 SEVEN Start of transmission is delayed for 7 baud-times 4 TCMP0 Start of transmission is delayed for TCMPVAL0 baud-times 5 TCMP1 Start of transmission is delayed for TCMPVAL1 baud-times 6 TCMP2 Start of transmission is delayed for TCMPVAL2 baud-times 7 CSSETUP Chip Select Setup 20 3 read-write ZERO CS is not asserted before start of transmission 0 ONE CS is asserted for 1 baud-times before start of transmission 1 TWO CS is asserted for 2 baud-times before start of transmission 2 THREE CS is asserted for 3 baud-times before start of transmission 3 SEVEN CS is asserted for 7 baud-times before start of transmission 4 TCMP0 CS is asserted before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted before the start of transmission for TCMPVAL2 baud-times 7 ICS Inter-character spacing 24 3 read-write ZERO There is no space between charcters 0 ONE Create a space of 1 baud-times before start of transmission 1 TWO Create a space of 2 baud-times before start of transmission 2 THREE Create a space of 3 baud-times before start of transmission 3 SEVEN Create a space of 7 baud-times before start of transmission 4 TCMP0 Create a space of before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 Create a space of before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 Create a space of before the start of transmission for TCMPVAL2 baud-times 7 CSHOLD Chip Select Hold 28 3 read-write ZERO Disable CS being asserted after the end of transmission 0 ONE CS is asserted for 1 baud-times after the end of transmission 1 TWO CS is asserted for 2 baud-times after the end of transmission 2 THREE CS is asserted for 3 baud-times after the end of transmission 3 SEVEN CS is asserted for 7 baud-times after the end of transmission 4 TCMP0 CS is asserted after the end of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted after the end of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted after the end of transmission for TCMPVAL2 baud-times 7 CTRLX No Description 0x05C read-write 0x00000000 0x8000808F DBGHALT Debug halt 0 1 read-write DISABLE Continue to transmit until TX buffer is empty 0 ENABLE Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock; otherwise, each single step could transmit multiple frames instead of just transmitting one frame. 1 CTSINV CTS Pin Inversion 1 1 read-write DISABLE The USn_CTS pin is low true 0 ENABLE The USn_CTS pin is high true 1 CTSEN CTS Function enabled 2 1 read-write DISABLE Ingore CTS 0 ENABLE Stop transmitting when CTS is negated 1 RTSINV RTS Pin Inversion 3 1 read-write DISABLE The USn_RTS pin is low true 0 ENABLE The USn_RTS pin is high true 1 RXPRSEN PRS RX Enable 7 1 read-write CLKPRSEN PRS CLK Enable 15 1 read-write TIMECMP0 No Description 0x060 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 0. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 0 is disabled 0 TXEOF Comparator 0 and timer are started at TX end of frame 1 TXC Comparator 0 and timer are started at TX Complete 2 RXACT Comparator 0 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 0 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 0 20 3 read-write TCMP0 Comparator 0 is disabled when the counter equals TCMPVAL and triggers a TCMP0 event 0 TXST Comparator 0 is disabled at TX start TX Engine 1 RXACT Comparator 0 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 0 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP0 24 1 read-write DISABLE Disable the timer restarting on TCMP0 0 ENABLE Enable the timer restarting on TCMP0 1 TIMECMP1 No Description 0x064 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 1. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 1 is disabled 0 TXEOF Comparator 1 and timer are started at TX end of frame 1 TXC Comparator 1 and timer are started at TX Complete 2 RXACT Comparator 1 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 1 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 1 20 3 read-write TCMP1 Comparator 1 is disabled when the counter equals TCMPVAL and triggers a TCMP1 event 0 TXST Comparator 1 is disabled at TX start TX Engine 1 RXACT Comparator 1 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 1 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP1 24 1 read-write DISABLE Disable the timer restarting on TCMP1 0 ENABLE Enable the timer restarting on TCMP1 1 TIMECMP2 No Description 0x068 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 2. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 2 is disabled 0 TXEOF Comparator 2 and timer are started at TX end of frame 1 TXC Comparator 2 and timer are started at TX Complete 2 RXACT Comparator 2 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 2 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 2 20 3 read-write TCMP2 Comparator 2 is disabled when the counter equals TCMPVAL and triggers a TCMP2 event 0 TXST Comparator 2 is disabled at TX start TX Engine 1 RXACT Comparator 2 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 2 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP2 24 1 read-write DISABLE Disable the timer restarting on TCMP2 0 ENABLE Enable the timer restarting on TCMP2 1 BURTC_S 0 BURTC_S Registers 0x40064000 0x00000000 0x00001000 registers BURTC 18 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN BURTC Enable 0 1 read-write CFG No Description 0x008 read-write 0x00000000 0x000000F3 DEBUGRUN Debug Mode Run Enable 0 1 read-write DISABLE BURTC is frozen in debug mode 0 ENABLE BURTC is running in debug mode 1 COMPTOP Compare Channel is Top Value 1 1 read-write DISABLE The top value of the BURTC is 4294967295 (0xFFFFFFFF) 0 ENABLE The top value of the BURTC is given by COMP 1 CNTPRESC Counter prescaler value. 4 4 read-write DIV1 CLK_CNT = (BURTC LF CLK)/1 0 DIV2 CLK_CNT = (BURTC LF CLK)/2 1 DIV4 CLK_CNT = (BURTC LF CLK)/4 2 DIV8 CLK_CNT = (BURTC LF CLK)/8 3 DIV16 CLK_CNT = (BURTC LF CLK)/16 4 DIV32 CLK_CNT = (BURTC LF CLK)/32 5 DIV64 CLK_CNT = (BURTC LF CLK)/64 6 DIV128 CLK_CNT = (BURTC LF CLK)/128 7 DIV256 CLK_CNT = (BURTC LF CLK)/256 8 DIV512 CLK_CNT = (BURTC LF CLK)/512 9 DIV1024 CLK_CNT = (BURTC LF CLK)/1024 10 DIV2048 CLK_CNT = (BURTC LF CLK)/2048 11 DIV4096 CLK_CNT = (BURTC LF CLK)/4096 12 DIV8192 CLK_CNT = (BURTC LF CLK)/8192 13 DIV16384 CLK_CNT = (BURTC LF CLK)/16384 14 DIV32768 CLK_CNT = (BURTC LF CLK)/32768 15 CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start BURTC counter 0 1 write-only STOP Stop BURTC counter 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x00000003 RUNNING BURTC running status 0 1 read-only LOCK Configuration Lock Status 1 1 read-only UNLOCKED All BURTC lockable registers are unlocked. 0 LOCKED All BURTC lockable registers are locked. 1 IF No Description 0x014 read-write 0x00000000 0x00000003 OF Overflow Interrupt Flag 0 1 read-write COMP Compare Match Interrupt Flag 1 1 read-write IEN No Description 0x018 read-write 0x00000000 0x00000003 OF Overflow Interrupt Flag 0 1 read-write COMP Compare Match Interrupt Flag 1 1 read-write PRECNT No Description 0x01C read-write 0x00000000 0x00007FFF PRECNT Pre-Counter Value 0 15 read-write CNT No Description 0x020 read-write 0x00000000 0xFFFFFFFF CNT Counter Value 0 32 read-write EM4WUEN No Description 0x024 read-write 0x00000000 0x00000003 OFEM4WUEN Overflow EM4 Wakeup Enable 0 1 read-write COMPEM4WUEN Compare Match EM4 Wakeup Enable 1 1 read-write SYNCBUSY No Description 0x028 read-only 0x00000000 0x0000003F START Sync busy for START 0 1 read-only STOP Sync busy for STOP 1 1 read-only PRECNT Sync busy for PRECNT 2 1 read-only CNT Sync busy for CNT 3 1 read-only COMP Sync busy for COMP 4 1 read-only EN Sync busy for EN 5 1 read-only LOCK No Description 0x02C write-only 0x0000AEE8 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write to unlock all BURTC lockable registers 44776 COMP No Description 0x030 read-write 0x00000000 0xFFFFFFFF COMP Compare Value 0 32 read-write I2C1_S 0 I2C1_S Registers 0x40068000 0x00000000 0x00001000 registers I2C1 28 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN module enable 0 1 read-write DISABLE Disable Peripheral Clock 0 ENABLE Enable Peripheral Clock 1 CTRL No Description 0x008 read-write 0x00000000 0x0037B3FF CORERST Soft Reset the internal state registers 0 1 read-write DISABLE No change to internal state registers 0 ENABLE Reset the internal state registers 1 SLAVE Addressable as Follower 1 1 read-write DISABLE All addresses will be responded to with a NACK 0 ENABLE Addresses matching the programmed follower address or the general call address (if enabled) require a response from software. Other addresses are automatically responded to with a NACK. 1 AUTOACK Automatic Acknowledge 2 1 read-write DISABLE Software must give one ACK command for each ACK transmitted on the I2C bus. 0 ENABLE Addresses that are not automatically NACK'ed, and all data is automatically acknowledged. 1 AUTOSE Automatic STOP when Empty 3 1 read-write DISABLE A stop must be sent manually when no more data is to be transmitted. 0 ENABLE The leader automatically sends a STOP when no more data is available for transmission. 1 AUTOSN Automatic STOP on NACK 4 1 read-write DISABLE Stop is not automatically sent if a NACK is received from a follower. 0 ENABLE The leader automatically sends a STOP if a NACK is received from a follower. 1 ARBDIS Arbitration Disable 5 1 read-write DISABLE When a device loses arbitration, the ARBIF interrupt flag is set and the bus is released. 0 ENABLE When a device loses arbitration, the ARBIF interrupt flag is set, but communication proceeds. 1 GCAMEN General Call Address Match Enable 6 1 read-write DISABLE General call address will be NACK'ed if it is not included by the follower address and address mask. 0 ENABLE When a general call address is received, a software response is required 1 TXBIL TX Buffer Interrupt Level 7 1 read-write EMPTY TXBL status and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALF_FULL TXBL status and the TXBL interrupt flag are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full 1 CLHR Clock Low High Ratio 8 2 read-write STANDARD Nlow=4 and Nhigh=4, and the Nlow:Nhigh ratio is 4:4 0 ASYMMETRIC Nlow=6 and Nhigh=3, and the Nlow:Nhigh ratio is 6:3 1 FAST Nlow=11 and Nhigh=6, and the Nlow:Nhigh ratio is 11:6 2 BITO Bus Idle Timeout 12 2 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 GIBITO Go Idle on Bus Idle Timeout 15 1 read-write DISABLE A bus idle timeout has no effect on the bus state. 0 ENABLE A bus idle timeout tells the I2C module that the bus is idle, allowing new transfers to be initiated. 1 CLTO Clock Low Timeout 16 3 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 I2C320PCC Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout. 4 I2C1024PCC Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout. 5 SCLMONEN SCL Monitor Enable 20 1 read-write DISABLE Disable SCL monitor 0 ENABLE Enable SCL monitor 1 SDAMONEN SDA Monitor Enable 21 1 read-write DISABLE Disable SDA Monitor 0 ENABLE Enable SDA Monitor 1 CMD No Description 0x00C write-only 0x00000000 0x000000FF START Send start condition 0 1 write-only STOP Send stop condition 1 1 write-only ACK Send ACK 2 1 write-only NACK Send NACK 3 1 write-only CONT Continue transmission 4 1 write-only ABORT Abort transmission 5 1 write-only CLEARTX Clear TX 6 1 write-only CLEARPC Clear Pending Commands 7 1 write-only STATE No Description 0x010 read-only 0x00000001 0x000000FF BUSY Bus Busy 0 1 read-only MASTER Leader 1 1 read-only TRANSMITTER Transmitter 2 1 read-only NACKED Nack Received 3 1 read-only BUSHOLD Bus Held 4 1 read-only STATE Transmission State 5 3 read-only IDLE No transmission is being performed. 0 WAIT Waiting for idle. Will send a start condition as soon as the bus is idle. 1 START Start transmit phase 2 ADDR Address transmit or receive phase 3 ADDRACK Address ack/nack transmit or receive phase 4 DATA Data transmit or receive phase 5 DATAACK Data ack/nack transmit or receive phase 6 STATUS No Description 0x014 read-only 0x00000080 0x00000FFF PSTART Pending START 0 1 read-only PSTOP Pending STOP 1 1 read-only PACK Pending ACK 2 1 read-only PNACK Pending NACK 3 1 read-only PCONT Pending continue 4 1 read-only PABORT Pending abort 5 1 read-only TXC TX Complete 6 1 read-only TXBL TX Buffer Level 7 1 read-only RXDATAV RX Data Valid 8 1 read-only RXFULL RX FIFO Full 9 1 read-only TXBUFCNT TX Buffer Count 10 2 read-only CLKDIV No Description 0x018 read-write 0x00000000 0x000001FF DIV Clock Divider 0 9 read-write SADDR No Description 0x01C read-write 0x00000000 0x000000FE ADDR Follower address 1 7 read-write SADDRMASK No Description 0x020 read-write 0x00000000 0x000000FE SADDRMASK Follower Address Mask 1 7 read-write RXDATA No Description 0x024 read-only 0x00000000 0x000000FF RXDATA RX Data 0 8 read-only RXDOUBLE No Description 0x028 read-only 0x00000000 0x0000FFFF RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDATAP No Description 0x02C read-only 0x00000000 0x000000FF RXDATAP RX Data Peek 0 8 read-only RXDOUBLEP No Description 0x030 read-only 0x00000000 0x0000FFFF RXDATAP0 RX Data 0 Peek 0 8 read-only RXDATAP1 RX Data 1 Peek 8 8 read-only TXDATA No Description 0x034 write-only 0x00000000 0x000000FF TXDATA TX Data 0 8 write-only TXDOUBLE No Description 0x038 write-only 0x00000000 0x0000FFFF TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only IF No Description 0x03C read-write 0x00000000 0x001FFFFF START START condition Interrupt Flag 0 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write ADDR Address Interrupt Flag 2 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write ACK Acknowledge Received Interrupt Flag 6 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write MSTOP Leader STOP Condition Interrupt Flag 8 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write SSTOP Follower STOP condition Interrupt Flag 16 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write IEN No Description 0x040 read-write 0x00000000 0x001FFFFF START START condition Interrupt Flag 0 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write ADDR Address Interrupt Flag 2 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write ACK Acknowledge Received Interrupt Flag 6 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write MSTOP Leader STOP Condition Interrupt Flag 8 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write SSTOP Follower STOP condition Interrupt Flag 16 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write SYSCFG_S_CFGNS 1 SYSCFG_S_CFGNS Registers 0x40078000 0x00000000 0x00001000 registers SYSCFG 20 SW0 52 SW1 53 SW2 54 SW3 55 CFGNSTCALIB Configure to define the system tick for the M33. 0x01C read-write 0x01004A37 0x03FFFFFF TENMS Ten Milliseconds 0 24 read-write SKEW Skew 24 1 read-write NOREF No Reference 25 1 read-write REF Reference clock is implemented 0 NOREF Reference clock is not implemented 1 ROOTNSDATA0 Generic data space for user to pass to root, e.g., address of struct in mem 0x600 read-write 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write ROOTNSDATA1 Generic data space for user to pass to root, e.g., address of struct in mem 0x604 read-write 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write SYSCFG_S 1 SYSCFG_S Registers 0x4007C000 0x00000000 0x00001000 registers SYSCFG 20 SW0 52 SW1 53 SW2 54 SW3 55 IF Read to get system status. 0x000 read-write 0x00000000 0x3303000F SW0 Software Interrupt 0 0 1 read-write SW1 Software Interrupt 1 1 1 read-write SW2 Software Interrupt 2 2 1 read-write SW3 Software Interrupt 3 3 1 read-write RAMERR1B RAM 1-Bit Error Interrupt Flag 16 1 read-write RAMERR2B RAM 2-Bit Error Interrupt Flag 17 1 read-write SEQRAMERR1B SEQRAM 1-Bit Error Interrupt Flag 24 1 read-write SEQRAMERR2B SEQRAM 2-Bit Error Interrupt Flag 25 1 read-write FRCRAMERR1B FRCRAM 1-Bit Error Interrupt Flag 28 1 read-write FRCRAMERR2B FRCRAM 2-Bit Error Interrupt Flag 29 1 read-write IEN Write to enable interrupts. 0x004 read-write 0x00000000 0x3303000F SW0 Software interrupt 0 0 1 read-write SW1 Software interrupt 1 1 1 read-write SW2 Software interrupt 2 2 1 read-write SW3 Software interrupt 3 3 1 read-write RAMERR1B RAM 1-bit Error Interrupt Enable 16 1 read-write RAMERR2B RAM 2-bit Error Interrupt Enable 17 1 read-write SEQRAMERR1B SEQRAM 1-bit Error Interrupt Enable 24 1 read-write SEQRAMERR2B SEQRAM 2-bit Error Interrupt Enable 25 1 read-write FRCRAMERR1B FRCRAM 1-bit Error Interrupt Enable 28 1 read-write FRCRAMERR2B FRCRAM 2-bit Error Interrupt Enable 29 1 read-write CHIPREVHW Read to get the hard-wired chip revision. 0x010 read-write 0x00000C01 0xFF0FFFFF MAJOR Hardwired Chip Revision Major value 0 6 read-write FAMILY Hardwired Chip Family value 6 6 read-write MINOR Hardwired Chip Revision Minor value 12 8 read-write CHIPREV Read to get the chip revision programmed by feature configuration. 0x014 read-write 0x00000000 0x000FFFFF MAJOR Chip Revision Major value 0 6 read-write FAMILY Chip Family value 6 6 read-write MINOR Chip Revision Minor value 12 8 read-write CFGSYSTIC Configure the source of the system tick for the M33. 0x020 read-write 0x00000000 0x00000001 SYSTICEXTCLKEN SysTick External Clock Enable 0 1 read-write CTRL Configure to provide general RAM configuration. 0x200 read-write 0x00000021 0x00000021 ADDRFAULTEN Invalid Address Bus Fault Response Enable 0 1 read-write RAMECCERRFAULTEN Two bit ECC Error Bus Fault Response Enable 5 1 read-write DMEM0RETNCTRL Configure to provide general RAM retention configuration. 0x208 read-write 0x00000000 0x00000003 RAMRETNCTRL DMEM0 blockset retention control 0 2 read-write ALLON None of the RAM blocks powered down 0 BLK0 Power down RAM block 0 1 BLK1 Power down RAM block 1 2 DMEM0ECCADDR Read to get status of the DMEM0 ECC error address. 0x210 read-only 0x00000000 0xFFFFFFFF DMEM0ECCADDR DMEM0 RAM ECC Error Address 0 32 read-only DMEM0ECCCTRL Configure to set RAM ECC control. 0x214 read-write 0x00000000 0x00000003 RAMECCEN RAM ECC Enable 0 1 read-write RAMECCEWEN RAM ECC Error Writeback Enable 1 1 read-write RADIORAMRETNCTRL Configure SEQRAM Retention controls. 0x400 read-write 0x00000000 0x00000103 SEQRAMRETNCTRL SEQRAM Retention Control 0 2 read-write ALLON SEQRAM not powered down 0 BLK0 Power down SEQRAM block 0 1 BLK1 Power down SEQRAM block 1 2 ALLOFF Power down all SEQRAM blocks 3 FRCRAMRETNCTRL FRCRAM Retention Control 8 1 read-write ALLON FRCRAM not powered down 0 ALLOFF Power down FRCRAM 1 RADIOECCCTRL Configure to set RAM ECC control. 0x408 read-write 0x00000000 0x00000303 SEQRAMECCEN SEQRAM ECC Enable 0 1 read-write SEQRAMECCEWEN SEQRAM ECC Error Writeback Enable 1 1 read-write FRCRAMECCEN FRCRAM ECC Enable 8 1 read-write FRCRAMECCEWEN FRCRAM ECC Error Writeback Enable 9 1 read-write SEQRAMECCADDR Read to get status of the SEQRAM ECC error address. 0x410 read-only 0x00000000 0xFFFFFFFF SEQRAMECCADDR SEQRAM ECC Address 0 32 read-only FRCRAMECCADDR Read to get status of the FRCRAM ECC error address. 0x414 read-only 0x00000000 0xFFFFFFFF FRCRAMECCADDR FRCRAM ECC Error Address 0 32 read-only ROOTDATA0 Data in this register is passed to the trusted root firmware upon reset. 0x600 read-write 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write ROOTDATA1 Data in this register is passed to the trusted root firmware upon reset. 0x604 read-write 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write ROOTLOCKSTATUS This register returns the status of the SE managed locks. 0x608 read-only 0x011F0107 0x011F0117 BUSLOCK Bus Lock 0 1 read-only REGLOCK Register Lock 1 1 read-only MFRLOCK Manufacture Lock 2 1 read-only ROOTMODELOCK Root Mode Lock 4 1 read-only ROOTDBGLOCK Root Debug Lock 8 1 read-only USERDBGLOCK User Invasive Debug Lock 16 1 read-only USERNIDLOCK User Non-invasive Debug Lock 17 1 read-only USERSPIDLOCK User Secure Invasive Debug Lock 18 1 read-only USERSPNIDLOCK User Secure Non-invasive Debug Lock 19 1 read-only USERDBGAPLOCK User Debug Access Port Lock 20 1 read-only RADIODBGLOCK Radio Debug Lock 24 1 read-only BURAM_S 0 BURAM_S Registers 0x40080000 0x00000000 0x00001000 registers RET0_REG No Description 0x000 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET1_REG No Description 0x004 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET2_REG No Description 0x008 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET3_REG No Description 0x00C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET4_REG No Description 0x010 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET5_REG No Description 0x014 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET6_REG No Description 0x018 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET7_REG No Description 0x01C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET8_REG No Description 0x020 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET9_REG No Description 0x024 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET10_REG No Description 0x028 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET11_REG No Description 0x02C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET12_REG No Description 0x030 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET13_REG No Description 0x034 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET14_REG No Description 0x038 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET15_REG No Description 0x03C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET16_REG No Description 0x040 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET17_REG No Description 0x044 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET18_REG No Description 0x048 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET19_REG No Description 0x04C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET20_REG No Description 0x050 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET21_REG No Description 0x054 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET22_REG No Description 0x058 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET23_REG No Description 0x05C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET24_REG No Description 0x060 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET25_REG No Description 0x064 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET26_REG No Description 0x068 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET27_REG No Description 0x06C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET28_REG No Description 0x070 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET29_REG No Description 0x074 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET30_REG No Description 0x078 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET31_REG No Description 0x07C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write GPCRC_S 0 GPCRC_S Registers 0x40088000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN CRC Enable 0 1 read-write DISABLE Disable CRC function. Reordering functions are still available. Only BITREVERSE and BYTEREVERSE bits are configurable in this mode. 0 ENABLE Writes to INPUTDATA registers will result in CRC operations. 1 CTRL No Description 0x008 read-write 0x00000000 0x00002710 POLYSEL Polynomial Select 4 1 read-write CRC32 CRC-32 (0x04C11DB7) polynomial selected 0 CRC16 16-bit CRC programmable polynomial selected 1 BYTEMODE Byte Mode Enable 8 1 read-write BITREVERSE Byte-level Bit Reverse Enable 9 1 read-write NORMAL No reverse 0 REVERSED Reverse bit order in each byte 1 BYTEREVERSE Byte Reverse Mode 10 1 read-write NORMAL No reverse: B3, B2, B1, B0 0 REVERSED Reverse byte order. For 32-bit: B0, B1, B2, B3; For 16-bit: 0, 0, B0, B1 1 AUTOINIT Auto Init Enable 13 1 read-write CMD No Description 0x00C write-only 0x00000000 0x80000001 INIT Initialization Enable 0 1 write-only INIT No Description 0x010 read-write 0x00000000 0xFFFFFFFF INIT CRC Initialization Value 0 32 read-write POLY No Description 0x014 read-write 0x00000000 0x0000FFFF POLY CRC Polynomial Value 0 16 read-write INPUTDATA No Description 0x018 write-only 0x00000000 0xFFFFFFFF INPUTDATA Input Data for 32-bit 0 32 write-only INPUTDATAHWORD No Description 0x01C write-only 0x00000000 0x0000FFFF INPUTDATAHWORD Input Data for 16-bit 0 16 write-only INPUTDATABYTE No Description 0x020 write-only 0x00000000 0x000000FF INPUTDATABYTE Input Data for 8-bit 0 8 write-only DATA No Description 0x024 read-only 0x00000000 0xFFFFFFFF DATA CRC Data Register 0 32 read-only DATAREV No Description 0x028 read-only 0x00000000 0xFFFFFFFF DATAREV Data Reverse Value 0 32 read-only DATABYTEREV No Description 0x02C read-only 0x00000000 0xFFFFFFFF DATABYTEREV Data Byte Reverse Value 0 32 read-only DCDC_S 0 DCDC_S Registers 0x40094000 0x00000000 0x00001000 registers IPVERSION IPVERSION 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IPVERSION 0 32 read-only EN Enable 0x004 read-write 0x00000000 0x00000001 EN Enable 0 1 read-write DISABLE Disable 0 ENABLE Enable 1 CTRL Control 0x008 read-write 0x00000044 0x00000077 MODE DCDC/Bypass Mode Control 0 1 read-write BYPASS DCDC is OFF, bypass switch is enabled 0 DCDCREGULATION Request DCDC regulation, bypass switch disabled 1 DCMONLYEN DCDC DCM Only Enable 2 1 read-write DUALMODE Support higher load current at lower battery voltage by working in CCM mode 0 DCMONLYEN DCM only mode for normal operation, this is the default setting 1 IPKTMAXCTRL Peak Current Timeout Control 4 3 read-write OFF Ton_max disabled 0 TMAX_0P35us 0.35us 1 TMAX_0P63us 0.63us 2 TMAX_0P91us 0.91us 3 TMAX_1P19us 1.19us 4 TMAX_1P47us 1.47us 5 TMAX_1P75us 1.75us 6 TMAX_2P03us 2.03us 7 EM01CTRL0 EM01 Configurations 0x010 read-write 0x00000109 0x0000030F IPKVAL EM01 Peak Current Setting 0 4 read-write Load36mA Ipeak = 90mA, IL = 36mA 3 Load40mA Ipeak = 100mA, IL = 40mA 4 Load44mA Ipeak = 110mA, IL = 44mA 5 Load48mA Ipeak = 120mA, IL = 48mA 6 Load52mA Ipeak = 130mA, IL = 52mA 7 Load56mA Ipeak = 140mA, IL = 56mA 8 Load60mA Ipeak = 150mA, IL = 60mA 9 DRVSPEED EM01 Drive Speed Setting 8 2 read-write BEST_EMI Lowest Efficiency, Lowest EMI.. Small decrease in efficiency from default setting 0 DEFAULT_SETTING Default Efficiency, Acceptable EMI level 1 INTERMEDIATE Small increase in efficiency from the default setting 2 BEST_EFFICIENCY Highest Efficiency, Highest EMI.. Small increase in efficiency from INTERMEDIATE setting 3 EM23CTRL0 EM23 Configurations 0x014 read-write 0x00000103 0x0000030F IPKVAL EM23 Peak Current Setting 0 4 read-write LOAD5MA Ipeak = 90mA, IL = 5 mA 3 LOAD10MA Ipeak = 150mA, IL = 10 mA 9 DRVSPEED EM23 Drive Speed Setting 8 2 read-write BEST_EMI Lowest Efficiency, Lowest EMI.. Small decrease in efficiency from default setting 0 DEFAULT_SETTING Default Efficiency, Acceptable EMI level 1 INTERMEDIATE Small increase in efficiency from the default setting 2 BEST_EFFICIENCY Highest Efficiency, Highest EMI.. Small increase in efficiency from INTERMEDIATE setting 3 IF Interrupt Flags 0x024 read-write 0x00000000 0x000000FF BYPSW Bypass Switch Enabled 0 1 read-write WARM DCDC Warmup Time Done 1 1 read-write RUNNING DCDC Running 2 1 read-write VREGINLOW VREGVDD below threshold 3 1 read-write VREGINHIGH VREGVDD above threshold 4 1 read-write REGULATION DCDC in regulation 5 1 read-write TMAX Ton_max Timeout Reached 6 1 read-write EM4ERR EM4 Entry Request Error 7 1 read-write IEN Interrupt Enable 0x028 read-write 0x00000000 0x000000FF BYPSW Bypass Switch Enabled Interrupt Enable 0 1 read-write WARM DCDC Warmup Time Done Interrupt Enable 1 1 read-write RUNNING DCDC Running Interrupt Enable 2 1 read-write VREGINLOW VREGVDD below threshold Interrupt Enable 3 1 read-write VREGINHIGH VREGVDD above threshold Interrupt Enable 4 1 read-write REGULATION DCDC in Regulation Interrupt Enable 5 1 read-write TMAX Ton_max Timeout Interrupt Enable 6 1 read-write EM4ERR EM4 Entry Req Interrupt Enable 7 1 read-write STATUS DCDC Status Register 0x02C read-only 0x00000000 0x0000001F BYPSW Bypass Switch is currently enabled 0 1 read-only WARM DCDC Warmup Done 1 1 read-only RUNNING DCDC is running 2 1 read-only VREGIN VREGVDD comparator status 3 1 read-only BYPCMPOUT Bypass Comparator Output 4 1 read-only LOCK No Description 0x040 write-only 0x00000000 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCKKEY Value to write to unlock 43981 LOCKSTATUS No Description 0x044 read-only 0x00000000 0x00000001 LOCK Lock Status 0 1 read-only UNLOCKED Unlocked State 0 LOCKED LOCKED STATE 1 PDM_S 0 PDM_S Registers 0x40098000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP VERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN PDM enable 0 1 read-write DISABLE Disable module 0 ENABLE Enable module 1 CTRL No Description 0x008 read-write 0x00000000 0x000FFF1F GAIN Selects Gain factor of DCF 0 5 read-write DSR Down sampling rate of Decimation filter 8 12 read-write CMD No Description 0x00C write-only 0x00000000 0x00010111 START Start DCF 0 1 write-only STOP Stop DCF 4 1 write-only CLEAR Clear DCF 8 1 write-only FIFOFL FIFO Flush 16 1 write-only STATUS No Description 0x010 read-only 0x00000020 0x00000731 ACT PDM is active 0 1 read-only FULL FIFO FULL Status 4 1 read-only EMPTY FIFO EMPTY Status 5 1 read-only FIFOCNT FIFO CNT 8 3 read-only CFG0 No Description 0x014 read-write 0x00000000 0x03013713 FORDER Filter order 0 2 read-write SECOND Second order filter. 0 THIRD Third order filter. 1 FOURTH Fourth order filter. 2 FIFTH Fifth order filter. 3 NUMCH Number of Channels 4 1 read-write ONE One channel. 0 TWO Two channels. 1 DATAFORMAT Filter output format 8 3 read-write RIGHT16 Right aligned 16-bit, left bits are sign extended. 0 DOUBLE16 Pack two 16-bit samples into one 32-bit word. 1 RIGHT24 Right aligned 24bit, left bits are sign extended. 2 FULL32BIT 32 bit data. 3 LEFT16 Left aligned 16-bit, right bits are zeros. 4 LEFT24 Left aligned 24-bit, right bits are zeros. 5 RAW32BIT RAW 32 bit data from Integrator. 6 FIFODVL Data Valid level in FIFO 12 2 read-write ONE Atleast one word. 0 TWO Two words. 1 THREE Three words. 2 FOUR Four words. 3 STEREOMODECH01 Stereo mode CH01 16 1 read-write DISABLE No Stereo mode. 0 CH01ENABLE CH0 and CH1 in Stereo mode. 1 CH0CLKPOL CH0 CLK Polarity 24 1 read-write NORMAL Input data clocked on rising clock edge. 0 INVERT Input data clocked on falling clock edge. 1 CH1CLKPOL CH1 CLK Polarity 25 1 read-write NORMAL Input data clocked on rising clock edge. 0 INVERT Input data clocked on falling clock edge. 1 CFG1 No Description 0x018 read-write 0x00000000 0x030003FF PRESC Prescalar Setting for PDM sample 0 10 read-write DLYMUXSEL Data delay buffer mux selection 24 2 read-write RXDATA No Description 0x020 read-only 0x00000000 0xFFFFFFFF RXDATA PDM received data 0 32 read-only IF No Description 0x040 read-write 0x00000000 0x0000000F DV Data Valid Interrupt Flag 0 1 read-write DVL Data Valid Level Interrupt Flag 1 1 read-write OF FIFO Overflow Interrupt Flag 2 1 read-write UF FIFO Undeflow Interrupt Flag 3 1 read-write IEN No Description 0x044 read-write 0x00000000 0x0000000F DV Data Valid Interrupt Enable 0 1 read-write DVL Data Valid Level Interrupt Enable 1 1 read-write OF FIFO Overflow Interrupt Enable 2 1 read-write UF FIFO Undeflow Interrupt Enable 3 1 read-write SYNCBUSY No Description 0x060 read-only 0x00000000 0x00000009 SYNCBUSY sync busy 0 1 read-only FIFOFLBUSY FIFO Flush Sync busy 3 1 read-only RFSENSE_S 0 RFSENSE_S Registers 0x4009C000 0x00000000 0x00001000 registers EN Block enables 0x000 read-write 0x00000000 0x00000001 EN RFSENSE Enable 0 1 read-write EM4WUEN No Description 0x004 read-write 0x00000000 0x00000001 EM4WUEN EM4 WakeUp Enable 0 1 read-write CFG Configures RFSENSE digital logic behavior 0x008 read-write 0x03800000 0x0780000D PREAMBLELEN Number of Preamble bits 0 1 read-write SYNCWORDLEN Synword Length 2 2 read-write ENERGYDUR RFSENSE Energy Duration 23 3 read-write dur1ms 1ms duration 0 dur2ms 2ms duration 1 dur4ms 4ms duration 2 dur8ms 8ms duration 3 dur16ms 16ms duration 4 dur32ms 32ms duration 5 dur64ms 64ms duration 6 dur128ms 128ms duration 7 LEGACYMODE RFSENSE Legacy Mode 26 1 read-write SYNCWORD No Description 0x00C read-write 0x00000000 0xFFFFFFFF SYNCWORD Sync Word 0 32 read-write THDSEL No Description 0x010 read-write 0x00000080 0x000000FF THDSEL Threshold Select 0 8 read-write IF No Description 0x020 read-write 0x00000000 0x00000003 RFSENSE RFSENSE Interrupt Flag 0 1 read-write SEQ Sequencer Interrupt Flag 1 1 read-write IEN No Description 0x024 read-write 0x00000000 0x00000003 RFSENSE RFSENSE Interrrupt Enable 0 1 read-write SEQ Sequencer Interrupt Enable 1 1 read-write CALCFG No Description 0x028 read-write 0x01050010 0x130F70FF CALPERIOD Calibration Period 0 8 read-write DISCMCAL Disable Common Mode Calibration 12 1 read-write DISPTATCAL Disable PTAT Calibration 13 1 read-write ENCALPUP Enable Calibration at Power Up 14 1 read-write PTATCALSTEPS PTAT Calibration Steps 16 2 read-write STEPS2 0 STEPS4 1 STEPS6 2 STEPS8 3 CMCALSTEPS CM Calibration Steps 18 2 read-write STEPS2 0 STEPS4 1 STEPS6 2 STEPS8 3 CALSTEPCLKS Clocks per calibration step settling 24 2 read-write PTATCALMODE PTAT Calibration mode 28 1 read-write RFEN No Description 0x02C read-write 0x00000060 0x0000007F ENBG Enable Bandgap 0 1 read-write BGSTART Bandgap Startup Signal 1 1 read-write PTATISO Isolate PTAT core 2 1 read-write PTATSTART PTAT Startup signal 3 1 read-write SUPFLTN Disable supply filtering 4 1 read-write DCEN DC Bias Enable 5 1 read-write RESETN Reset RFSENSE data flop 6 1 read-write MODESEL No Description 0x030 read-write 0x00000000 0x00000007 MODESEL Mode Select 0 3 read-write NORMAL_OP Normal operation 0 CM_CAL Common-mode calibration 1 REF_CAL Bandgap Reference calibration 2 NORMAL_OP2 Normal operation mode-2 3 DM_A_CAL Differntial A calibration 4 DM_B_CAL Differential B calibration 5 DM_A_CAL2 Differential A mode-2 calibration 6 DM_B_CAL2 Differential B mode-2 calibration 7 CMPCONF No Description 0x034 read-write 0x00000000 0x00000007 CHP Invert Comparator IO 0 1 read-write HYS Enable Hysteresis 1 1 read-write PLSN Disable Comparator reset pulse 2 1 read-write TRIMPTAT IPTAT Calbiration trim values 0x038 read-write 0x00000420 0x0000073F TRIMRES PTAT reference resistor trim 0 6 read-write TRIMCURR PTAT current trim 8 3 read-write m80pct Reduce PTAT current by 80% 0 m60pct Reduce PTAT current by 60% 1 m40pct Reduce PTAT current by 40% 2 m20pct Reduce PTAT current by 20% 3 default Default PTAT current 4 p20pct Increase PTAT current by 20% 5 p40pct Increase PTAT current by 40% 6 p60pct Increase PTAT current by 60% 7 TRIMBG BandGap Calibration trim values 0x03C read-write 0x00000088 0x000000FF TRIMREF Reference Trim 0 4 read-write TRIMTC TempCo Trim 4 4 read-write TRIMDAC RFSENSE DAC trim values 0x040 read-write 0x00007F7F 0x03FFFFFF TRIMCM Trim Common Mode 0 8 read-write CMPOSCAL Comparator Offset Calibration value 8 8 read-write TRIMDM Trim Differential Mode 16 9 read-write INVDM Invert Differential offset polarity 25 1 read-write SPARE No Description 0x044 read-write 0x00000000 0x000000F1 SPARE Spare register 0 1 read-write DIGSPARE Digital Spare registers 4 4 read-write SWCTRL Enable Software Control of the FSM signals 0x060 read-write 0x00000010 0x0000001F SWCTRL New BitField 0 4 read-write ANACLKINV Invert Analog clock 4 1 read-write DIAGCTRL No Description 0x064 read-write 0x00000000 0x00000003 DIAGABYPN Diag buffer bypass 0 1 read-write ENBYPASS Enable DIAGA buffer bypass 0 DISBYPASS Disable DIAGA buffer bypass 1 DIAGACHP Diag buffer chop 1 1 read-write DISABLE Disable DIAGA buffer chop 0 ENABLE Enable DIAGA buffer chop 1 STATUS No Description 0x068 read-only 0x00000000 0x0FF73F1F RFSENSEDATA RFSENSE data input from analog 0 1 read-only FIRSTTRIPDONE First RFSENSE trip done 1 1 read-only PREAMBLEDET Preamble Detected 2 1 read-only SYNCDET Syncword Detected 3 1 read-only CALRUNNING Calibration Running 4 1 read-only CALTRIMRES Calibration Resistor Trim value 8 6 read-only CALTRIMCURR Calibration Current Trim value 16 3 read-only CALTRIMCM Calibration Common mode Trim value 20 8 read-only RADIOAES_S 1 RADIOAES_S Registers 0x44000000 0x00000000 0x00001000 registers AES 47 FETCHADDR Fetcher: Start address of data block. In direct mode, this register is written by the software. In scatter-gather mode, this register is updated after each processed descriptor. 0x000 read-write 0x00000000 0xFFFFFFFF ADDR Start address of data block 0 32 read-write FETCHLEN Fetcher: Length of data block. In direct mode, this register is written by the software. In scatter-gather mode, this register is not used. 0x008 read-write 0x00000000 0x3FFFFFFF LENGTH Length of data block 0 28 read-write CONSTADDR Constant address 28 1 read-write REALIGN Realign lengh 29 1 read-write FETCHTAG Fetcher: User tag. In direct mode, this register is written by the software. In scatter-gather mode, this register is not used. 0x00C read-write 0x00000000 0xFFFFFFFF TAG User tag 0 32 read-write PUSHADDR Pusher: Start address of data block (LSB). In direct mode, this register is written by the software. In scatter-gather mode, this register is updated after each processed descriptor. 0x010 read-write 0x00000000 0xFFFFFFFF ADDR Start address of data block 0 32 read-write PUSHLEN Pusher: Length of data block. In direct mode, this register is written by the software. In scatter-gather mode, this register is not used. 0x018 read-write 0x00000000 0x7FFFFFFF LENGTH Start address of data block 0 28 read-write CONSTADDR Constant address 28 1 read-write REALIGN Realign length 29 1 read-write DISCARD Discard data 30 1 read-write IEN Interrupt enable 0x01C read-write 0x00000000 0x0000003F FETCHERENDOFBLOCK End of block interrupt enable 0 1 read-write FETCHERSTOPPED Stopped interrupt enable 1 1 read-write FETCHERERROR Error interrupt enable 2 1 read-write PUSHERENDOFBLOCK End of block interrupt enable 3 1 read-write PUSHERSTOPPED Stopped interrupt enable 4 1 read-write PUSHERERROR Error interrupt enable 5 1 read-write IF Interrupt flag register 0x028 read-only 0x00000000 0x0000003F FETCHERENDOFBLOCK End of block interrupt flag 0 1 read-only FETCHERSTOPPED Stopped interrupt flag 1 1 read-only FETCHERERROR Error interrupt flag 2 1 read-only PUSHERENDOFBLOCK End of block interrupt flag 3 1 read-only PUSHERSTOPPED Stopped interrupt flag 4 1 read-only PUSHERERROR Error interrupt flag 5 1 read-only IF_CLR Writing a '1' clears the interrupt status. Writing a '0' has no effect. 0x030 write-only 0x00000000 0x0000003F FETCHERENDOFBLOCK End of block interrupt flag clear 0 1 write-only FETCHERSTOPPED Stopped interrupt flag clear 1 1 write-only FETCHERERROR Error interrupt flag clear 2 1 write-only PUSHERENDOFBLOCK FETCHERENDOFBLOCKIFC 3 1 write-only PUSHERSTOPPED FETCHERSTOPPEDIFC 4 1 write-only PUSHERERROR FETCHERERRORIFC 5 1 write-only CTRL Control register, called CONFIG in Barco datasheet. 0x034 read-write 0x00000000 0x0000001F FETCHERSCATTERGATHER Fetcher scatter/gather 0 1 read-write PUSHERSCATTERGATHER Pusher scatter/gather 1 1 read-write STOPFETCHER Stop fetcher 2 1 read-write STOPPUSHER Stop pusher 3 1 read-write SWRESET Software reset 4 1 read-write CMD Command register for starting the fetcher and pusher 0x038 write-only 0x00000000 0x00000003 STARTFETCHER Start fetch 0 1 write-only STARTPUSHER Start push 1 1 write-only STATUS Status register 0x03C read-only 0x00000000 0xFFFF0073 FETCHERBSY Fetcher busy 0 1 read-only PUSHERBSY Pusher busy 1 1 read-only NOTEMPTY Not empty flag from input FIFO (fetcher) 4 1 read-only WAITING Pusher waiting for FIFO 5 1 read-only SOFTRSTBSY Software reset busy 6 1 read-only FIFODATANUM Number of data in output FIFO 16 16 read-only INCL_IPS_HW_CFG No Description 0x400 read-only 0x00000001 0x000007FF g_IncludeAES Generic g_IncludeAES value 0 1 read-only g_IncludeAESGCM Generic g_IncludeAESGCM value 1 1 read-only g_IncludeAESXTS Generic g_IncludeAESXTS value 2 1 read-only g_IncludeDES Generic g_IncludeDES value 3 1 read-only g_IncludeHASH Generic g_IncludeHASH value 4 1 read-only g_IncludeChachaPoly Generic g_IncludeChachaPoly value 5 1 read-only g_IncludeSHA3 Generic g_IncludeSHA3 value 6 1 read-only g_IncludeZUC Generic g_IncludeZUC value 7 1 read-only g_IncludeSM4 Generic g_IncludeSM4 value 8 1 read-only g_IncludePKE Generic g_IncludePKE value 9 1 read-only g_IncludeNDRNG Generic g_IncludeNDRNG value 10 1 read-only BA411E_HW_CFG_1 No Description 0x404 read-only 0x05010127 0x070301FF g_AesModesPoss AES Modes Supported 0 9 read-only g_CS Generic g_CS value 16 1 read-only g_UseMasking Generic g_UseMasking value 17 1 read-only g_Keysize Generic g_Keysize value 24 3 read-only BA411E_HW_CFG_2 No Description 0x408 read-only 0x00000080 0x0000FFFF g_CtrSize Generic g_CtrSize value 0 16 read-only BA413_HW_CFG No Description 0x40C read-only 0x00000000 0x0007007F g_HashMaskFunc Generic g_HashMaskFunc value 0 7 read-only g_HashPadding Generic g_HashPadding value 16 1 read-only g_HMAC_enabled Generic g_HMAC_enabled value 17 1 read-only g_HashVerifyDigest Generic g_HashVerifyDigest value 18 1 read-only BA418_HW_CFG No Description 0x410 read-only 0x00000001 0x00000001 g_Sha3CtxtEn Generic g_Sha3CtxtEn value 0 1 read-only BA419_HW_CFG No Description 0x414 read-only 0x00000000 0x0000007F g_SM4ModesPoss Generic g_SM4ModesPoss value 0 7 read-only SMU_S 1 SMU_S Registers 0x44008000 0x00000000 0x00001000 registers SMU_SECURE 3 SMU_PRIVILEGED 4 IPVERSION The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION. 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only STATUS Read to get SMU status. 0x004 read-only 0x00000000 0x00000003 SMULOCK SMU Lock 0 1 read-only UNLOCKED SMULOCK is Unlocked 0 LOCKED SMULOCK is Locked 1 SMUPRGERR SMU Programming Error 1 1 read-only LOCK Access to Lock/unlock the SMU Configuration. 0x008 write-only 0x00000000 0x00FFFFFF SMULOCKKEY SMU Lock/Key 0 24 write-only UNLOCK Unlocks Registers 11325013 IF Read to get status of SMU interrupts. 0x00C read-write 0x00000000 0x00030005 PPUPRIV PPU Privilege Interrupt Flag 0 1 read-write PPUINST PPU Instruction Interrupt Flag 2 1 read-write PPUSEC PPU Security Interrupt Flag 16 1 read-write BMPUSEC BMPU Security Interrupt Flag 17 1 read-write IEN Write to Enable/Disable SMU interrupts. 0x010 read-write 0x00000000 0x00030005 PPUPRIV PPU Privilege Interrupt Enable 0 1 read-write PPUINST PPU Instruction Interrupt Enable 2 1 read-write PPUSEC PPU Security Interrupt Enable 16 1 read-write BMPUSEC BMPU Security Interrupt Enable 17 1 read-write M33CTRL Holds the M33 control settings. 0x020 read-write 0x00000000 0x0000001F LOCKSVTAIRCR LOCKSVTAIRCR control of M33 CPU 0 1 read-write LOCKNSVTOR LOCKNSVTOR control of M33 CPU 1 1 read-write LOCKSMPU LOCKSMPU control of M33 CPU 2 1 read-write LOCKNSMPU LOCKNSMPU control of M33 CPU 3 1 read-write LOCKSAU LOCKSAU control of M33 CPU 4 1 read-write PPUPATD0 Set peripheral bits to 1 to mark as privileged access only. 0x040 read-write 0xFFFFFFFF 0xFFFFFFFF EMU EMU Privileged Access 1 1 read-write CMU CMU Privileged Access 2 1 read-write HFXO0 HFXO0 Privileged Access 3 1 read-write HFRCO0 HFRCO0 Privileged Access 4 1 read-write FSRCO FSRCO Privileged Access 5 1 read-write DPLL0 DPLL0 Privileged Access 6 1 read-write LFXO LFXO Privileged Access 7 1 read-write LFRCO LFRCO Privileged Access 8 1 read-write ULFRCO ULFRCO Privileged Access 9 1 read-write MSC MSC Privileged Access 10 1 read-write ICACHE0 ICACHE0 Privileged Access 11 1 read-write PRS PRS Privileged Access 12 1 read-write GPIO GPIO Privileged Access 13 1 read-write LDMA LDMA Privileged Access 14 1 read-write LDMAXBAR LDMAXBAR Privileged Access 15 1 read-write TIMER0 TIMER0 Privileged Access 16 1 read-write TIMER1 TIMER1 Privileged Access 17 1 read-write TIMER2 TIMER2 Privileged Access 18 1 read-write TIMER3 TIMER3 Privileged Access 19 1 read-write TIMER4 TIMER4 Privileged Access 20 1 read-write USART0 USART0 Privileged Access 21 1 read-write USART1 USART1 Privileged Access 22 1 read-write BURTC BURTC Privileged Access 23 1 read-write I2C1 I2C1 Privileged Access 24 1 read-write CHIPTESTCTRL CHIPTESTCTRL Privileged Access 25 1 read-write SYSCFGCFGNS SYSCFGCFGNS Privileged Access 26 1 read-write SYSCFG SYSCFG Privileged Access 27 1 read-write BURAM BURAM Privileged Access 28 1 read-write IFADCDEBUG IFADCDEBUG Privileged Access 29 1 read-write GPCRC GPCRC Privileged Access 30 1 read-write DCI DCI Privileged Access 31 1 read-write PPUPATD1 Set peripheral bits to 1 to mark as privileged access only. 0x044 read-write 0x0000FFFF 0x0000FFFF DCDC DCDC Privileged Access 1 1 read-write PDM PDM Privileged Access 2 1 read-write RFSENSE RFSENSE Privileged Access 3 1 read-write RADIOAES RADIOAES Privileged Access 4 1 read-write SMU SMU Privileged Access 5 1 read-write SMUCFGNS SMUCFGNS Privileged Access 6 1 read-write RTCC RTCC Privileged Access 7 1 read-write LETIMER0 LETIMER0 Privileged Access 8 1 read-write IADC0 IADC0 Privileged Access 9 1 read-write I2C0 I2C0 Privileged Access 10 1 read-write WDOG0 WDOG0 Privileged Access 11 1 read-write AMUXCP0 AMUXCP0 Privileged Access 12 1 read-write EUART0 EUART0 Privileged Access 13 1 read-write CRYPTOACC CRYPTOACC Privileged Access 14 1 read-write AHBRADIO AHBRADIO Privileged Access 15 1 read-write PPUSATD0 Set peripheral bits to 1 to mark as secure access only. 0x060 read-write 0xFFFFFFFF 0xFFFFFFFF EMU EMU Secure Access 1 1 read-write CMU CMU Secure Access 2 1 read-write HFXO0 HFXO0 Secure Access 3 1 read-write HFRCO0 HFRCO0 Secure Access 4 1 read-write FSRCO FSRCO Secure Access 5 1 read-write DPLL0 DPLL0 Secure Access 6 1 read-write LFXO LFXO Secure Access 7 1 read-write LFRCO LFRCO Secure Access 8 1 read-write ULFRCO ULFRCO Secure Access 9 1 read-write MSC MSC Secure Access 10 1 read-write ICACHE0 ICACHE0 Secure Access 11 1 read-write PRS PRS Secure Access 12 1 read-write GPIO GPIO Secure Access 13 1 read-write LDMA LDMA Secure Access 14 1 read-write LDMAXBAR LDMAXBAR Secure Access 15 1 read-write TIMER0 TIMER0 Secure Access 16 1 read-write TIMER1 TIMER1 Secure Access 17 1 read-write TIMER2 TIMER2 Secure Access 18 1 read-write TIMER3 TIMER3 Secure Access 19 1 read-write TIMER4 TIMER4 Secure Access 20 1 read-write USART0 USART0 Secure Access 21 1 read-write USART1 USART1 Secure Access 22 1 read-write BURTC BURTC Secure Access 23 1 read-write I2C1 I2C1 Secure Access 24 1 read-write CHIPTESTCTRL CHIPTESTCTRL Secure Access 25 1 read-write SYSCFGCFGNS SYSCFGCFGNS Secure Access 26 1 read-write SYSCFG SYSCFG Secure Access 27 1 read-write BURAM BURAM Secure Access 28 1 read-write IFADCDEBUG IFADCDEBUG Secure Access 29 1 read-write GPCRC GPCRC Secure Access 30 1 read-write DCI DCI Secure Access 31 1 read-write PPUSATD1 Set peripheral bits to 1 to mark as secure access only. 0x064 read-write 0x0000FFFF 0x0000FFFF DCDC DCDC Secure Access 1 1 read-write PDM PDM Secure Access 2 1 read-write RFSENSE RFSENSE Secure Access 3 1 read-write RADIOAES RADIOAES Secure Access 4 1 read-write SMU SMU Secure Access 5 1 read-write SMUCFGNS SMUCFGNS Secure Access 6 1 read-write RTCC RTCC Secure Access 7 1 read-write LETIMER0 LETIMER0 Secure Access 8 1 read-write IADC0 IADC0 Secure Access 9 1 read-write I2C0 I2C0 Secure Access 10 1 read-write WDOG0 WDOG0 Secure Access 11 1 read-write AMUXCP0 AMUXCP0 Secure Access 12 1 read-write EUART0 EUART0 Secure Access 13 1 read-write CRYPTOACC CRYPTOACC Secure Access 14 1 read-write AHBRADIO AHBRADIO Secure Access 15 1 read-write PPUFS Read to get fault status of SMU. 0x140 read-only 0x00000000 0x000000FF PPUFSPERIPHID Peripheral ID 0 8 read-only BMPUPATD0 Set master bits to 1 to mark as a privileged master. 0x150 read-write 0x0000001F 0x0000001F RADIOAES RADIO AES DMA privileged mode 0 1 read-write CRYPTOACC CRYPTOACC DMA privileged mode 1 1 read-write RADIOSUBSYSTEM RADIO subsystem masters privileged mode 2 1 read-write RADIOIFADCDEBUG RADIO IFADC debug privileged mode 3 1 read-write LDMA MCU LDMA privileged mode 4 1 read-write BMPUSATD0 Set master bits to 1 to mark as a secure master. 0x170 read-write 0x0000001F 0x0000001F RADIOAES RADIOAES DMA secure mode 0 1 read-write CRYPTOACC CRYPTOACC DMA secure mode 1 1 read-write RADIOSUBSYSTEM RADIO subsystem masters secure mode 2 1 read-write RADIOIFADCDEBUG RADIO IFADC debug secure mode 3 1 read-write LDMA MCU LDMA secure mode 4 1 read-write BMPUFS Read to get status about the master that triggered a fault. 0x250 read-only 0x00000000 0x000000FF BMPUFSMASTERID Master ID 0 8 read-only BMPUFSADDR Read to get the access address that triggered a fault. 0x254 read-only 0x00000000 0xFFFFFFFF BMPUFSADDR Fault Address 0 32 read-only ESAURTYPES0 Write to specify if a region is secure or non-secure. 0x260 read-write 0x00000000 0x00001000 ESAUR3NS Region 3 Non-Secure Type 12 1 read-write ESAURTYPES1 Write to specify if a region is secure or non-secure. 0x264 read-write 0x00000000 0x00001000 ESAUR11NS Region 11 Non-Secure Type 12 1 read-write ESAUMRB01 Specify the boundary between regions 0 and 1. 0x270 read-write 0x02000000 0x0FFFF000 ESAUMRB01 Moveable Region Boundary 0-1 12 16 read-write ESAUMRB12 Specify the boundary between regions 1 and 2. 0x274 read-write 0x04000000 0x0FFFF000 ESAUMRB12 Moveable Region Boundary 1-2 12 16 read-write ESAUMRB45 Specify the boundary between regions 4 and 5. 0x280 read-write 0x02000000 0x0FFFF000 ESAUMRB45 Moveable Region Boundary 4-5 12 16 read-write ESAUMRB56 Specify the boundary between regions 5 and 6. 0x284 read-write 0x04000000 0x0FFFF000 ESAUMRB56 Moveable Region Boundary 5-6 12 16 read-write SMU_S_CFGNS 1 SMU_S_CFGNS Registers 0x4400C000 0x00000000 0x00001000 registers SMU_SECURE 3 SMU_PRIVILEGED 4 NSSTATUS Register for status flags. 0x004 read-only 0x00000000 0x00000001 SMUNSLOCK SMUNS Lock Status 0 1 read-only UNLOCKED SMUNSLOCK Unlocked 0 LOCKED SMUNSLOCK Locked 1 NSLOCK Register used to lock/unlock access to the register file. 0x008 write-only 0x00000000 0x00FFFFFF SMUNSLOCKKEY SMU Non-Secure Lock/Key 0 24 write-only UNLOCK Unlocks Registers 11325013 NSIF Register for interrupt status flags. 0x00C read-write 0x00000000 0x00000005 PPUNSPRIVIF PPUNS Privilege Interrupt Flag 0 1 read-write PPUNSINSTIF PPUNS Instruction Interrupt Flag 2 1 read-write NSIEN Register used for enabling/disabling interrupts. 0x010 read-write 0x00000000 0x00000005 PPUNSPRIVIEN PPUNS Privilege Interrupt Enable 0 1 read-write PPUNSINSTIEN PPUNS Instruction Interrupt Enable 2 1 read-write PPUNSPATD0 Set peripheral bits to 1 to mark as privileged access only. 0x040 read-write 0x00000000 0xFFFFFFFF EMU EMU Privileged Access 1 1 read-write CMU CMU Privileged Access 2 1 read-write HFXO0 HFXO0 Privileged Access 3 1 read-write HFRCO0 HFRCO0 Privileged Access 4 1 read-write FSRCO FSRCO Privileged Access 5 1 read-write DPLL0 DPLL0 Privileged Access 6 1 read-write LFXO LFXO Privileged Access 7 1 read-write LFRCO LFRCO Privileged Access 8 1 read-write ULFRCO ULFRCO Privileged Access 9 1 read-write MSC MSC Privileged Access 10 1 read-write ICACHE0 ICACHE0 Privileged Access 11 1 read-write PRS PRS Privileged Access 12 1 read-write GPIO GPIO Privileged Access 13 1 read-write LDMA LDMA Privileged Access 14 1 read-write LDMAXBAR LDMAXBAR Privileged Access 15 1 read-write TIMER0 TIMER0 Privileged Access 16 1 read-write TIMER1 TIMER1 Privileged Access 17 1 read-write TIMER2 TIMER2 Privileged Access 18 1 read-write TIMER3 TIMER3 Privileged Access 19 1 read-write TIMER4 TIMER4 Privileged Access 20 1 read-write USART0 USART0 Privileged Access 21 1 read-write USART1 USART1 Privileged Access 22 1 read-write BURTC BURTC Privileged Access 23 1 read-write I2C1 I2C1 Privileged Access 24 1 read-write CHIPTESTCTRL CHIPTESTCTRL Privileged Access 25 1 read-write SYSCFGCFGNS SYSCFGCFGNS Privileged Access 26 1 read-write SYSCFG SYSCFG Privileged Access 27 1 read-write BURAM BURAM Privileged Access 28 1 read-write IFADCDEBUG IFADCDEBUG Privileged Access 29 1 read-write GPCRC GPCRC Privileged Access 30 1 read-write DCI DCI Privileged Access 31 1 read-write PPUNSPATD1 Set peripheral bits to 1 to mark as privileged access only. 0x044 read-write 0x00000000 0x0000FFFF DCDC DCDC Privileged Access 1 1 read-write PDM PDM Privileged Access 2 1 read-write RFSENSE RFSENSE Privileged Access 3 1 read-write RADIOAES RADIOAES Privileged Access 4 1 read-write SMU SMU Privileged Access 5 1 read-write SMUCFGNS SMUCFGNS Privileged Access 6 1 read-write RTCC RTCC Privileged Access 7 1 read-write LETIMER0 LETIMER0 Privileged Access 8 1 read-write IADC0 IADC0 Privileged Access 9 1 read-write I2C0 I2C0 Privileged Access 10 1 read-write WDOG0 WDOG0 Privileged Access 11 1 read-write AMUXCP0 AMUXCP0 Privileged Access 12 1 read-write EUART0 EUART0 Privileged Access 13 1 read-write CRYPTOACC CRYPTOACC Privileged Access 14 1 read-write AHBRADIO AHBRADIO Privileged Access 15 1 read-write PPUNSFS Read this register to query the fault status. 0x140 read-only 0x00000000 0x000000FF PPUFSPERIPHID Peripheral ID 0 8 read-only BMPUNSPATD0 Write to set BMPU priveledged attributes. 0x150 read-write 0x00000000 0x0000001F RADIOAES RADIO AES DMA privileged mode 0 1 read-write CRYPTOACC CRYPTOACC DMA privileged mode 1 1 read-write RADIOSUBSYSTEM RADIO subsystem masters privileged mode 2 1 read-write RADIOIFADCDEBUG RADIO IFADC debug privileged mode 3 1 read-write LDMA MCU LDMA privileged mode 4 1 read-write RTCC_S 1 RTCC_S Registers 0x48000000 0x00000000 0x00001000 registers RTCC 12 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP VERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN RTCC Enable 0 1 read-write CFG No Description 0x008 read-write 0x00000000 0x000000FF DEBUGRUN Debug Mode Run Enable 0 1 read-write X0 RTCC is frozen in debug mode 0 X1 RTCC is running in debug mode 1 PRECNTCCV0TOP Pre-counter CCV0 top value enable. 1 1 read-write CNTCCV1TOP CCV1 top value enable 2 1 read-write CNTTICK Counter prescaler mode. 3 1 read-write PRESC CNT register ticks according to configuration in CNTPRESC. 0 CCV0MATCH CNT register ticks when PRECNT matches RTCC_CC0_OC[14:0] 1 CNTPRESC Counter prescaler value. 4 4 read-write DIV1 CLK_CNT = (RTCC LF CLK)/1 0 DIV2 CLK_CNT = (RTCC LF CLK)/2 1 DIV4 CLK_CNT = (RTCC LF CLK)/4 2 DIV8 CLK_CNT = (RTCC LF CLK)/8 3 DIV16 CLK_CNT = (RTCC LF CLK)/16 4 DIV32 CLK_CNT = (RTCC LF CLK)/32 5 DIV64 CLK_CNT = (RTCC LF CLK)/64 6 DIV128 CLK_CNT = (RTCC LF CLK)/128 7 DIV256 CLK_CNT = (RTCC LF CLK)/256 8 DIV512 CLK_CNT = (RTCC LF CLK)/512 9 DIV1024 CLK_CNT = (RTCC LF CLK)/1024 10 DIV2048 CLK_CNT = (RTCC LF CLK)/2048 11 DIV4096 CLK_CNT = (RTCC LF CLK)/4096 12 DIV8192 CLK_CNT = (RTCC LF CLK)/8192 13 DIV16384 CLK_CNT = (RTCC LF CLK)/16384 14 DIV32768 CLK_CNT = (RTCC LF CLK)/32768 15 CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start RTCC main counter 0 1 write-only STOP Stop RTCC main counter 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x00000003 RUNNING RTCC running status 0 1 read-only RTCCLOCKSTATUS Lock Status 1 1 read-only UNLOCKED RTCC registers are unlocked 0 LOCKED RTCC registers are locked 1 IF No Description 0x014 read-write 0x00000000 0x000003FF OF Overflow Interrupt Flag 0 1 read-write CNTTICK Main counter tick 1 1 read-write CC0 CC Channel n Interrupt Flag 4 1 read-write CC1 CC Channel n Interrupt Flag 6 1 read-write CC2 CC Channel n Interrupt Flag 8 1 read-write IEN No Description 0x018 read-write 0x00000000 0x000003FF OF OF Interrupt Enable 0 1 read-write CNTTICK CNTTICK Interrupt Enable 1 1 read-write CC0 CC Channel n Interrupt Enable 4 1 read-write CC1 CC Channel n Interrupt Enable 6 1 read-write CC2 CC Channel n Interrupt Enable 8 1 read-write PRECNT No Description 0x01C read-write 0x00000000 0x00007FFF PRECNT Pre-Counter Value 0 15 read-write CNT No Description 0x020 read-write 0x00000000 0xFFFFFFFF CNT Counter Value 0 32 read-write COMBCNT No Description 0x024 read-only 0x00000000 0xFFFFFFFF PRECNT Pre-Counter Value 0 15 read-only CNTLSB Counter Value 15 17 read-only SYNCBUSY No Description 0x028 read-only 0x00000000 0x0000000F START Sync busy for START 0 1 read-only STOP Sync busy for STOP 1 1 read-only PRECNT Sync busy for PRECNT 2 1 read-only CNT Sync busy for CNT 3 1 read-only LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write to unlock RTCC lockable registers 44776 CC0_CTRL No Description 0x030 read-write 0x00000000 0x000000FF MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 CC0_OCVALUE No Description 0x034 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC0_ICVALUE No Description 0x038 read-only 0x00000000 0xFFFFFFFF IC Input Capture Value 0 32 read-only CC1_CTRL No Description 0x03C read-write 0x00000000 0x000000FF MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 CC1_OCVALUE No Description 0x040 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC1_ICVALUE No Description 0x044 read-only 0x00000000 0xFFFFFFFF IC Input Capture Value 0 32 read-only CC2_CTRL No Description 0x048 read-write 0x00000000 0x000000FF MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 CC2_OCVALUE No Description 0x04C read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC2_ICVALUE No Description 0x050 read-only 0x00000000 0xFFFFFFFF IC Input Capture Value 0 32 read-only LETIMER0_S 0 LETIMER0_S Registers 0x4A000000 0x00000000 0x00001000 registers LETIMER0 19 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN module en 0 1 read-write CTRL No Description 0x008 read-write 0x00000000 0x000F13FF REPMODE Repeat Mode 0 2 read-write FREE When started, the LETIMER counts down until it is stopped by software 0 ONESHOT The counter counts REP0 times. When REP0 reaches zero, the counter stops 1 BUFFERED The counter counts REP0 times. If REP1 has been written, it is loaded into REP0 when REP0 reaches zero, otherwise the counter stops 2 DOUBLE Both REP0 and REP1 are decremented when the LETIMER wraps around. The LETIMER counts until both REP0 and REP1 are zero 3 UFOA0 Underflow Output Action 0 2 2 read-write NONE LETIMERn_OUT0 is held at its idle value as defined by OPOL0 0 TOGGLE LETIMERn_OUT0 is toggled on CNT underflow 1 PULSE LETIMERn_OUT0 is held active for one LETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL0 2 PWM LETIMERn_OUT0 is set idle on CNT underflow, and active on compare match with COMP1 3 UFOA1 Underflow Output Action 1 4 2 read-write NONE LETIMERn_OUT1 is held at its idle value as defined by OPOL1 0 TOGGLE LETIMERn_OUT1 is toggled on CNT underflow 1 PULSE LETIMERn_OUT1 is held active for one LETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL1 2 PWM LETIMERn_OUT1 is set idle on CNT underflow, and active on compare match with COMP1 3 OPOL0 Output 0 Polarity 6 1 read-write OPOL1 Output 1 Polarity 7 1 read-write BUFTOP Buffered Top 8 1 read-write DISABLE TOP is only written by software 0 ENABLE TOP is set to TOPBUFF value when REP0 reaches 0 1 CNTTOPEN Compare Value 0 Is Top Value 9 1 read-write DISABLE The top value of the LETIMER is 16777215 (0xFFFFFF) 0 ENABLE The top value of the LETIMER is given by TOP 1 DEBUGRUN Debug Mode Run Enable 12 1 read-write DISABLE LETIMER is frozen in debug mode 0 ENABLE LETIMER is running in debug mode 1 CNTPRESC Counter prescaler value 16 4 read-write DIV1 CLK_CNT = (LETIMER LF CLK)/1 0 DIV2 CLK_CNT = (LETIMER LF CLK)/2 1 DIV4 CLK_CNT = (LETIMER LF CLK)/4 2 DIV8 CLK_CNT = (LETIMER LF CLK)/8 3 DIV16 CLK_CNT = (LETIMER LF CLK)/16 4 DIV32 CLK_CNT = (LETIMER LF CLK)/32 5 DIV64 CLK_CNT = (LETIMER LF CLK)/64 6 DIV128 CLK_CNT = (LETIMER LF CLK)/128 7 DIV256 CLK_CNT = (LETIMER LF CLK)/256 8 CMD No Description 0x00C write-only 0x00000000 0x0000001F START Start LETIMER 0 1 write-only STOP Stop LETIMER 1 1 write-only CLEAR Clear LETIMER 2 1 write-only CTO0 Clear Toggle Output 0 3 1 write-only CTO1 Clear Toggle Output 1 4 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x00000001 RUNNING LETIMER Running 0 1 read-only CNT No Description 0x018 read-write 0x00000000 0x00FFFFFF CNT Counter Value 0 24 read-write COMP0 No Description 0x01C read-write 0x00000000 0x00FFFFFF COMP0 Compare Value 0 0 24 read-write COMP1 No Description 0x020 read-write 0x00000000 0x00FFFFFF COMP1 Compare Value 1 0 24 read-write TOP No Description 0x024 read-write 0x00000000 0x00FFFFFF TOP Counter TOP Value 0 24 read-write TOPBUFF No Description 0x028 read-write 0x00000000 0x00FFFFFF TOPBUFF Buffered Counter TOP Value 0 24 read-write REP0 No Description 0x02C read-write 0x00000000 0x000000FF REP0 Repeat Counter 0 0 8 read-write REP1 No Description 0x030 read-write 0x00000000 0x000000FF REP1 Repeat Counter 1 0 8 read-write IF No Description 0x034 read-write 0x00000000 0x0000001F COMP0 Compare Match 0 Interrupt Flag 0 1 read-write COMP1 Compare Match 1 Interrupt Flag 1 1 read-write UF Underflow Interrupt Flag 2 1 read-write REP0 Repeat Counter 0 Interrupt Flag 3 1 read-write REP1 Repeat Counter 1 Interrupt Flag 4 1 read-write IEN No Description 0x038 read-write 0x00000000 0x0000001F COMP0 Compare Match 0 Interrupt Enable 0 1 read-write COMP1 Compare Match 1 Interrupt Enable 1 1 read-write UF Underflow Interrupt Enable 2 1 read-write REP0 Repeat Counter 0 Interrupt Enable 3 1 read-write REP1 Repeat Counter 1 Interrupt Enable 4 1 read-write SYNCBUSY No Description 0x040 read-only 0x00000000 0x000003FD CNT Sync busy for CNT 0 1 read-only TOP Sync busy for TOP 2 1 read-only REP0 Sync busy for REP0 3 1 read-only REP1 Sync busy for REP1 4 1 read-only START Sync busy for START 5 1 read-only STOP Sync busy for STOP 6 1 read-only CLEAR Sync busy for CLEAR 7 1 read-only CTO0 Sync busy for CTO0 8 1 read-only CTO1 Sync busy for CTO1 9 1 read-only PRSMODE No Description 0x050 read-write 0x00000000 0x0CCC0000 PRSSTARTMODE PRS Start Mode 18 2 read-write NONE PRS cannot start the LETIMER 0 RISING Rising edge of selected PRS input can start the LETIMER 1 FALLING Falling edge of selected PRS input can start the LETIMER 2 BOTH Both the rising or falling edge of the selected PRS input can start the LETIMER 3 PRSSTOPMODE PRS Stop Mode 22 2 read-write NONE PRS cannot stop the LETIMER 0 RISING Rising edge of selected PRS input can stop the LETIMER 1 FALLING Falling edge of selected PRS input can stop the LETIMER 2 BOTH Both the rising or falling edge of the selected PRS input can stop the LETIMER 3 PRSCLEARMODE PRS Clear Mode 26 2 read-write NONE PRS cannot clear the LETIMER 0 RISING Rising edge of selected PRS input can clear the LETIMER 1 FALLING Falling edge of selected PRS input can clear the LETIMER 2 BOTH Both the rising or falling edge of the selected PRS input can clear the LETIMER 3 IADC0_S 1 IADC0_S Registers 0x4A004000 0x00000000 0x00001000 registers IADC 48 IPVERSION IPVERSION 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only EN Enable 0x004 read-write 0x00000000 0x00000001 EN Enable IADC Module 0 1 read-write DISABLE Disable 0 ENABLE Enable 1 CTRL Control 0x008 read-write 0x00000000 0x707F003F EM23WUCONVERT EM23 Wakeup on Conversion 0 1 read-write WUDVL When using suspend mode, conversions performed in EM2 or EM3 should not wake up the DMA until the FIFO's DVL setting is reached. This saves more power for large OSR settings or infrequent sampling. 0 WUCONVERT When using suspend mode, conversions performed in EM2 or EM3 will wake up the DMA and keep it awake until the conversions are done, regardless of the DVL setting. This mode burns more power, but it is useful when the conversion rate is faster than the time for the DMA to cycle through wake up and going back to sleep as it converts more than 4 scan table entries. Without using the wake up on conversion mode, the FIFO may overflow while the DMA is going in and out of sleep. 1 ADCCLKSUSPEND0 ADC_CLK Suspend - PRS0 1 1 read-write PRSWUDIS Normal mode which does not disable the ADC_CLK. 0 PRSWUEN ADCCLKWUEN will gate off ADC_CLK until the trigger is detected provided the internal timer is not selected as the trigger. Once the trigger is detected the ADC_CLK will be started, the band gap will be started, the ADC will be warmed up, and the SCAN Table and the Single entry will be converted. Once the conversions are done, the ADC_CLK will be gated off. 1 ADCCLKSUSPEND1 ADC_CLK Suspend - PRS1 2 1 read-write PRSWUDIS Normal mode which does not disable the ADC_CLK. 0 PRSWUEN ADCCLKWUEN will gate off ADC_CLK until the trigger is detected provided the internal timer is not selected as the trigger. Once the trigger is detected the ADC_CLK will be started, the band gap will be started, the ADC will be warmed up, and the SCAN Table and the Single entry will be converted. Once the conversions are done, the ADC_CLK will be gated off. 1 DBGHALT Debug Halt 3 1 read-write NORMAL Continue operation as normal during debug mode 0 HALT Complete the current conversion and then halt during debug mode 1 WARMUPMODE Warmup Mode 4 2 read-write NORMAL Shut down the IADC after conversions have completed. 0 KEEPINSTANDBY Switch to standby mode after conversions have completed. The next warmup time will require 1us. 1 KEEPWARM Keep IADC fully powered after conversions have completed. 2 TIMEBASE Time Base 16 7 read-write HSCLKRATE High Speed Clock Rate 28 3 read-write DIV1 Use CMU_CLK_ADC directly. The source clock must be 40 MHz or less. 0 DIV2 Divide CMU_CLK_ADC by 2 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 1 DIV3 Divide CMU_CLK_ADC by 3 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 2 DIV4 Divide CMU_CLK_ADC by 4 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 3 CMD Command 0x00C write-only 0x00000000 0x0303001B SINGLESTART Single Queue Start 0 1 write-only SINGLESTOP Single Queue Stop 1 1 write-only SCANSTART Scan Queue Start 3 1 write-only SCANSTOP Scan Queue Stop 4 1 write-only TIMEREN Timer Enable 16 1 write-only TIMERDIS Timer Disable 17 1 write-only SINGLEFIFOFLUSH Flush the Single FIFO 24 1 write-only SCANFIFOFLUSH Flush the Scan FIFO 25 1 write-only TIMER Timer 0x010 read-write 0x00000000 0x0000FFFF TIMER Timer Period 0 16 read-write STATUS Status 0x014 read-only 0x00000000 0x4131CF5B SINGLEQEN Single Queue Enabled 0 1 read-only SINGLEQUEUEPENDING Single Queue Pending 1 1 read-only SCANQEN Scan Queued Enabled 3 1 read-only SCANQUEUEPENDING Scan Queue Pending 4 1 read-only CONVERTING Converting 6 1 read-only SINGLEFIFODV SINGLEFIFO Data Valid 8 1 read-only SCANFIFODV SCANFIFO Data Valid 9 1 read-only SINGLEFIFOFLUSHING The Single FIFO is flushing 14 1 read-only SCANFIFOFLUSHING The Scan FIFO is flushing 15 1 read-only TIMERACTIVE Timer Active 16 1 read-only SINGLEWRITEPENDING SINGLE write pending 20 1 read-only MASKREQWRITEPENDING MASKREQ write pending 21 1 read-only SYNCBUSY SYNCBUSY 24 1 read-only ADCWARM ADCWARM 30 1 read-only MASKREQ Mask Request 0x018 read-write 0x00000000 0x0000FFFF MASKREQ Scan Queue Mask Request 0 16 read-write STMASK Scan Table Mask 0x01C read-only 0x00000000 0x0000FFFF STMASK Scan Table Mask 0 16 read-only CMPTHR Comparator Threshold 0x020 read-write 0x00000000 0xFFFFFFFF ADLT ADC Less Than or Equal to Threshold 0 16 read-write ADGT ADC Greater Than or Equal to Threshold 16 16 read-write IF Interrupt Flag 0x024 read-write 0x00000000 0x800F338F SINGLEFIFODVL Single FIFO Data Valid Level 0 1 read-write SCANFIFODVL Scan FIFO Data Valid Level 1 1 read-write SINGLECMP Single Result Window Compare 2 1 read-write SCANCMP Scan Result Window Compare 3 1 read-write SCANENTRYDONE Scan Entry Done 7 1 read-write SCANTABLEDONE Scan Table Done 8 1 read-write SINGLEDONE Single Conversion Done 9 1 read-write POLARITYERR Polarity Error 12 1 read-write PORTALLOCERR Port Allocation Error 13 1 read-write SINGLEFIFOOF Single FIFO Overflow 16 1 read-write SCANFIFOOF Scan FIFO Overflow 17 1 read-write SINGLEFIFOUF Single FIFO Underflow 18 1 read-write SCANFIFOUF Scan FIFO Underflow 19 1 read-write EM23ABORTERROR EM2/3 Abort Error 31 1 read-write IEN Interrupt Enable 0x028 read-write 0x00000000 0x800F338F SINGLEFIFODVL Single FIFO Data Valid Level Enable 0 1 read-write SCANFIFODVL Scan FIFO Data Valid Level Enable 1 1 read-write SINGLECMP Single Result Window Compare Enable 2 1 read-write SCANCMP Scan Result Window Compare Enable 3 1 read-write SCANENTRYDONE Scan Entry Done Enable 7 1 read-write SCANTABLEDONE Scan Table Done Enable 8 1 read-write SINGLEDONE Single Conversion Done Enable 9 1 read-write POLARITYERR Polarity Error Enable 12 1 read-write PORTALLOCERR Port Allocation Error Enable 13 1 read-write SINGLEFIFOOF Single FIFO Overflow Enable 16 1 read-write SCANFIFOOF Scan FIFO Overflow Enable 17 1 read-write SINGLEFIFOUF Single FIFO Underflow Enable 18 1 read-write SCANFIFOUF Scan FIFO Underflow Enable 19 1 read-write EM23ABORTERROR EM2/3 Abort Error Enable 31 1 read-write TRIGGER Trigger 0x02C read-write 0x00000000 0x00011717 SCANTRIGSEL Scan Trigger Select 0 3 read-write IMMEDIATE Immediate triggering. The scan queue will be disabled once all conversions in the scan table are complete, unless TRIGGERACTION is set to continuous. 0 TIMER Triggers when the local timer count reaches zero. 1 PRSCLKGRP Triggers on PRS0 from a timer module that is using the same clock group as the ADC and has been programmed to use the same clock source as the ADC. The prescale may be different between the ADC and the timer module. 2 PRSPOS Triggers on asynchronous PRS0 positive edge. Requires PRS0 to go low for 3 ADC_CLKs before another positive edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. 3 PRSNEG Triggers on asynchronous PRS0 negative edge. Requires PRS0 to go high for 3 ADC_CLKs before another negative edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. PRSNEG should only be used when the trigger source is from a module that remains powered during EM23. For modules (ie: TIMER) that power down during EM23, PRSPOS should be used for an asynchronous trigger, and PRSCLKGRP should be used for a synchronous trigger. 4 SCANTRIGACTION Scan Trigger Action 4 1 read-write ONCE For TRIGSEL=IMMEDIATE, goes through the scan table once and disables queue. For TRIGSEL = TIMER, PRSCLKGRP, PRSPOS, PRSNEG, goes through the scan table once per trigger. 0 CONTINUOUS Goes through the scan table, converts each entry with a mask bit set, and puts it back into the scan queue to repeat again continuously. The queues are first come first serve. If both queues are triggered, the single queue will get to convert after each scan table completes. The scan queue will get to convert after each single conversion completes. 1 SINGLETRIGSEL Single Trigger Select 8 3 read-write IMMEDIATE Immediate triggering. The single queue will be disabled once the conversion is complete, unless TRIGGERACTION is set to continuous. 0 TIMER Triggers when the local timer count reaches zero. 1 PRSCLKGRP Triggers on PRS1 from a timer module that is using the same clock group as the ADC and has been programmed to use the same clock source as the ADC. The prescale may be different between the ADC and the timer module. 2 PRSPOS Triggers on asynchronous PRS1 positive edge. Requires PRS1 to go low for 3 ADC_CLKs before another positive edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. 3 PRSNEG Triggers on asynchronous PRS1 negative edge. Requires PRS1 to go high for 3 ADC_CLKs before another negative edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. PRSNEG should only be used when the trigger source is from a module that remains powered during EM23. For modules (ie: TIMER) that power down during EM23, PRSPOS should be used for an asynchronous trigger, and PRSCLKGRP should be used for a synchronous trigger. 4 SINGLETRIGACTION Single Trigger Action 12 1 read-write ONCE For TRIGSEL=IMMEDIATE, converts the single queue once and disables queue. For TRIGSEL = TIMER, PRSCLKGRP, PRSPOS, PRSNEG, converts the single queue once per trigger.ask. 0 CONTINUOUS Converts the single queue, then checks for a pending scan queue before converting the single queue again continuously. The queues are first come first serve. If both queues are continuous, the IADC alternates between them. 1 SINGLETAILGATE Single Tailgate Enable 16 1 read-write TAILGATEOFF The single queue is ready to start warming up and converting once the trigger had been detected. 0 TAILGATEON After the single queue's trigger is detected, it must wait until the end of a scan operation before the Single queue can be converted. 1 CFG0 Configration 0x048 read-write 0x00002060 0x30E770FF ADCMODE ADC Mode 0 2 read-write NORMAL High speed mode with a maximum CLK_ADC of 10 MHz. 0 OSRHS High Speed OSR 2 3 read-write HISPD2 High speed over sampling of 2x. 0 HISPD4 High speed over sampling of 4x. 1 HISPD8 High speed over sampling of 8x. 2 HISPD16 High speed over sampling of 16x. 3 HISPD32 HIgh speed over sampling of 32x. 4 HISPD64 High speed over sampling of 64x. 5 ANALOGGAIN Analog Gain 12 3 read-write ANAGAIN0P5 Analog gain of 0.5x. 1 ANAGAIN1 Analog gain of 1x. 2 ANAGAIN2 Analog gain of 2x. 3 ANAGAIN3 Analog gain of 3x. 4 ANAGAIN4 Analog gain of 4x. 5 REFSEL Reference Select 16 3 read-write VBGR Internal 1.21 V reference. 0 VREF External Reference. (Calibrated for 1.25V nominal.) 1 VDDX AVDD (unbuffered) 3 VDDX0P8BUF AVDD (buffered) * 0.8 4 DIGAVG Digital Averaging 21 3 read-write AVG1 Collect one output word (no digital averaging). 0 AVG2 Collect and average 2 digital output words. 1 AVG4 Collect and average 4 digital output words. 2 AVG8 Collect and average 8 digital output words. 3 AVG16 Collect and average 16 digital output words. 4 TWOSCOMPL Two's Complement 28 2 read-write AUTO Automatic: Single ended measurements are reported as unipolar and differential measurements are reported as bipolar. 0 FORCEUNIPOLAR Force all measurements to result in unipolar output. Negative differential numbers will saturate to 0. 1 FORCEBIPOLAR Force all measurements to result in bipolar output. Single ended measurements are half the range, but allow for small negative measurements. 2 SCALE0 Scale 0x050 read-write 0x8002C000 0xFFFFFFFF OFFSET Offset 0 18 read-write GAIN13LSB Gain 13 LSBs 18 13 read-write GAIN3MSB Gain 3 MSBs 31 1 read-write GAIN011 Upper 3 bits of gain = 011 (0.75x) 0 GAIN100 Upper 3 bits of gain = 100 (1.00x) 1 SCHED0 Scheduling 0x054 read-write 0x00000000 0x000003FF PRESCALE Prescale 0 10 read-write CFG1 Configration 0x058 read-write 0x00002060 0x30E770FF ADCMODE ADC Mode 0 2 read-write NORMAL High speed mode with a maximum CLK_ADC of 10 MHz. 0 OSRHS High Speed OSR 2 3 read-write HISPD2 High speed over sampling of 2x. 0 HISPD4 High speed over sampling of 4x. 1 HISPD8 High speed over sampling of 8x. 2 HISPD16 High speed over sampling of 16x. 3 HISPD32 HIgh speed over sampling of 32x. 4 HISPD64 High speed over sampling of 64x. 5 ANALOGGAIN Analog Gain 12 3 read-write ANAGAIN0P5 Analog gain of 0.5x. 1 ANAGAIN1 Analog gain of 1x. 2 ANAGAIN2 Analog gain of 2x. 3 ANAGAIN3 Analog gain of 3x. 4 ANAGAIN4 Analog gain of 4x. 5 REFSEL Reference Select 16 3 read-write VBGR Internal 1.21 V reference. 0 VREF External Reference. (Calibrated for 1.25V nominal.) 1 VDDX AVDD (unbuffered) 3 VDDX0P8BUF AVDD (buffered) * 0.8 4 DIGAVG Digital Averaging 21 3 read-write AVG1 Collect one output word (no digital averaging). 0 AVG2 Collect and average 2 digital output words. 1 AVG4 Collect and average 4 digital output words. 2 AVG8 Collect and average 8 digital output words. 3 AVG16 Collect and average 16 digital output words. 4 TWOSCOMPL Two's Complement 28 2 read-write AUTO Automatic: Single ended measurements are reported as unipolar and differential measurements are reported as bipolar. 0 FORCEUNIPOLAR Force all measurements to result in unipolar output. Negative differential numbers will saturate to 0. 1 FORCEBIPOLAR Force all measurements to result in bipolar output. Single ended measurements are half the range, but allow for small negative measurements. 2 SCALE1 Scale 0x060 read-write 0x8002C000 0xFFFFFFFF OFFSET Offset 0 18 read-write GAIN13LSB Gain 13 LSBs 18 13 read-write GAIN3MSB Gain 3 MSBs 31 1 read-write GAIN011 Upper 3 bits of gain = 011 (0.75x) 0 GAIN100 Upper 3 bits of gain = 100 (1.00x) 1 SCHED1 Scheduling 0x064 read-write 0x00000000 0x000003FF PRESCALE Prescale 0 10 read-write SINGLEFIFOCFG Single FIFO Configuration 0x070 read-write 0x00000030 0x0000013F ALIGNMENT Alignment 0 3 read-write RIGHT12 ID[7:0], SIGN_EXT, DATA[11:0] 0 RIGHT16 ID[7:0], SIGN_EXT, DATA[15:0] 1 RIGHT20 ID[7:0], SIGN_EXT, DATA[19:0] 2 LEFT12 DATA[11:0], 000000000000, ID[7:0] 3 LEFT16 DATA[15:0], 00000000, ID[7:0] 4 LEFT20 DATA[19:0], 0000, ID[7:0] 5 SHOWID Show ID 3 1 read-write DVL Data Valid Level 4 2 read-write VALID1 When 1 entry in the single FIFO is valid, set the SINGLEFIFODVL interrupt and request DMA. 0 VALID2 When 2 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 1 VALID3 When 3 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 2 VALID4 When 4 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 3 DMAWUFIFOSINGLE Single FIFO DMA wakeup. 8 1 read-write DISABLED While in EM2 or EM3, the DMA controller will not be requested. 0 ENABLED While in EM2 or EM3, the DMA controller will be requested when the single FIFO reaches its Data Valid Level. [DVL must be set to 0 (VALID1).] 1 SINGLEFIFODATA Read the oldest valid data from the single FIFO and pop the FIFO 0x074 read-only 0x00000000 0xFFFFFFFF DATA Single FIFO Read Data 0 32 read-only SINGLEFIFOSTAT Single FIFO status 0x078 read-only 0x00000000 0x00000007 FIFOREADCNT FIFO Read Count 0 3 read-only SINGLEDATA latest single queue conversion data 0x07C read-only 0x00000000 0xFFFFFFFF DATA Data 0 32 read-only SCANFIFOCFG Scan FIFO Configuration 0x080 read-write 0x00000030 0x0000013F ALIGNMENT Alignment 0 3 read-write RIGHT12 ID[7:0], SIGN_EXT, DATA[11:0] 0 RIGHT16 ID[7:0], SIGN_EXT, DATA[15:0] 1 RIGHT20 ID[7:0], SIGN_EXT, DATA[19:0] 2 LEFT12 DATA[11:0], 000000000000, ID[7:0] 3 LEFT16 DATA[15:0], 00000000, ID[7:0] 4 LEFT20 DATA[19:0], 0000, ID[7:0] 5 SHOWID Show ID 3 1 read-write DVL Data Valid Level 4 2 read-write VALID1 When 1 entry in the scan FIFO is valid, set the SCANFIFODVL interrupt and request DMA. 0 VALID2 When 2 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA. 1 VALID3 When 3 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA. 2 VALID4 When 4 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA. 3 DMAWUFIFOSCAN Scan FIFO DMA Wakeup 8 1 read-write DISABLED While in EM2 or EM3, the DMA controller will not be requested. 0 ENABLED While in EM2 or EM3, the DMA controller will be requested when the scan FIFO reaches its Data Valid Level. [DVL must be set to 0 (VALID1).] 1 SCANFIFODATA Read the oldest valid data from the scan FIFO and pop the FIFO 0x084 read-only 0x00000000 0xFFFFFFFF DATA Data 0 32 read-only SCANFIFOSTAT Scan FIFO status 0x088 read-only 0x00000000 0x00000007 FIFOREADCNT FIFO Read Count 0 3 read-only SCANDATA Most recent data data from scan queue conversion 0x08C read-only 0x00000000 0xFFFFFFFF DATA Data 0 32 read-only SINGLE No Description 0x098 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN0 No Description 0x0A0 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN1 No Description 0x0A4 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN2 No Description 0x0A8 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN3 No Description 0x0AC read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN4 No Description 0x0B0 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN5 No Description 0x0B4 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN6 No Description 0x0B8 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN7 No Description 0x0BC read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN8 No Description 0x0C0 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN9 No Description 0x0C4 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN10 No Description 0x0C8 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN11 No Description 0x0CC read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN12 No Description 0x0D0 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN13 No Description 0x0D4 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN14 No Description 0x0D8 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN15 No Description 0x0DC read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write I2C0_S 0 I2C0_S Registers 0x4A010000 0x00000000 0x00001000 registers I2C0 27 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN module enable 0 1 read-write DISABLE Disable Peripheral Clock 0 ENABLE Enable Peripheral Clock 1 CTRL No Description 0x008 read-write 0x00000000 0x0037B3FF CORERST Soft Reset the internal state registers 0 1 read-write DISABLE No change to internal state registers 0 ENABLE Reset the internal state registers 1 SLAVE Addressable as Follower 1 1 read-write DISABLE All addresses will be responded to with a NACK 0 ENABLE Addresses matching the programmed follower address or the general call address (if enabled) require a response from software. Other addresses are automatically responded to with a NACK. 1 AUTOACK Automatic Acknowledge 2 1 read-write DISABLE Software must give one ACK command for each ACK transmitted on the I2C bus. 0 ENABLE Addresses that are not automatically NACK'ed, and all data is automatically acknowledged. 1 AUTOSE Automatic STOP when Empty 3 1 read-write DISABLE A stop must be sent manually when no more data is to be transmitted. 0 ENABLE The leader automatically sends a STOP when no more data is available for transmission. 1 AUTOSN Automatic STOP on NACK 4 1 read-write DISABLE Stop is not automatically sent if a NACK is received from a follower. 0 ENABLE The leader automatically sends a STOP if a NACK is received from a follower. 1 ARBDIS Arbitration Disable 5 1 read-write DISABLE When a device loses arbitration, the ARBIF interrupt flag is set and the bus is released. 0 ENABLE When a device loses arbitration, the ARBIF interrupt flag is set, but communication proceeds. 1 GCAMEN General Call Address Match Enable 6 1 read-write DISABLE General call address will be NACK'ed if it is not included by the follower address and address mask. 0 ENABLE When a general call address is received, a software response is required 1 TXBIL TX Buffer Interrupt Level 7 1 read-write EMPTY TXBL status and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALF_FULL TXBL status and the TXBL interrupt flag are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full 1 CLHR Clock Low High Ratio 8 2 read-write STANDARD Nlow=4 and Nhigh=4, and the Nlow:Nhigh ratio is 4:4 0 ASYMMETRIC Nlow=6 and Nhigh=3, and the Nlow:Nhigh ratio is 6:3 1 FAST Nlow=11 and Nhigh=6, and the Nlow:Nhigh ratio is 11:6 2 BITO Bus Idle Timeout 12 2 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 GIBITO Go Idle on Bus Idle Timeout 15 1 read-write DISABLE A bus idle timeout has no effect on the bus state. 0 ENABLE A bus idle timeout tells the I2C module that the bus is idle, allowing new transfers to be initiated. 1 CLTO Clock Low Timeout 16 3 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 I2C320PCC Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout. 4 I2C1024PCC Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout. 5 SCLMONEN SCL Monitor Enable 20 1 read-write DISABLE Disable SCL monitor 0 ENABLE Enable SCL monitor 1 SDAMONEN SDA Monitor Enable 21 1 read-write DISABLE Disable SDA Monitor 0 ENABLE Enable SDA Monitor 1 CMD No Description 0x00C write-only 0x00000000 0x000000FF START Send start condition 0 1 write-only STOP Send stop condition 1 1 write-only ACK Send ACK 2 1 write-only NACK Send NACK 3 1 write-only CONT Continue transmission 4 1 write-only ABORT Abort transmission 5 1 write-only CLEARTX Clear TX 6 1 write-only CLEARPC Clear Pending Commands 7 1 write-only STATE No Description 0x010 read-only 0x00000001 0x000000FF BUSY Bus Busy 0 1 read-only MASTER Leader 1 1 read-only TRANSMITTER Transmitter 2 1 read-only NACKED Nack Received 3 1 read-only BUSHOLD Bus Held 4 1 read-only STATE Transmission State 5 3 read-only IDLE No transmission is being performed. 0 WAIT Waiting for idle. Will send a start condition as soon as the bus is idle. 1 START Start transmit phase 2 ADDR Address transmit or receive phase 3 ADDRACK Address ack/nack transmit or receive phase 4 DATA Data transmit or receive phase 5 DATAACK Data ack/nack transmit or receive phase 6 STATUS No Description 0x014 read-only 0x00000080 0x00000FFF PSTART Pending START 0 1 read-only PSTOP Pending STOP 1 1 read-only PACK Pending ACK 2 1 read-only PNACK Pending NACK 3 1 read-only PCONT Pending continue 4 1 read-only PABORT Pending abort 5 1 read-only TXC TX Complete 6 1 read-only TXBL TX Buffer Level 7 1 read-only RXDATAV RX Data Valid 8 1 read-only RXFULL RX FIFO Full 9 1 read-only TXBUFCNT TX Buffer Count 10 2 read-only CLKDIV No Description 0x018 read-write 0x00000000 0x000001FF DIV Clock Divider 0 9 read-write SADDR No Description 0x01C read-write 0x00000000 0x000000FE ADDR Follower address 1 7 read-write SADDRMASK No Description 0x020 read-write 0x00000000 0x000000FE SADDRMASK Follower Address Mask 1 7 read-write RXDATA No Description 0x024 read-only 0x00000000 0x000000FF RXDATA RX Data 0 8 read-only RXDOUBLE No Description 0x028 read-only 0x00000000 0x0000FFFF RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDATAP No Description 0x02C read-only 0x00000000 0x000000FF RXDATAP RX Data Peek 0 8 read-only RXDOUBLEP No Description 0x030 read-only 0x00000000 0x0000FFFF RXDATAP0 RX Data 0 Peek 0 8 read-only RXDATAP1 RX Data 1 Peek 8 8 read-only TXDATA No Description 0x034 write-only 0x00000000 0x000000FF TXDATA TX Data 0 8 write-only TXDOUBLE No Description 0x038 write-only 0x00000000 0x0000FFFF TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only IF No Description 0x03C read-write 0x00000000 0x001FFFFF START START condition Interrupt Flag 0 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write ADDR Address Interrupt Flag 2 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write ACK Acknowledge Received Interrupt Flag 6 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write MSTOP Leader STOP Condition Interrupt Flag 8 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write SSTOP Follower STOP condition Interrupt Flag 16 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write IEN No Description 0x040 read-write 0x00000000 0x001FFFFF START START condition Interrupt Flag 0 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write ADDR Address Interrupt Flag 2 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write ACK Acknowledge Received Interrupt Flag 6 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write MSTOP Leader STOP Condition Interrupt Flag 8 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write SSTOP Follower STOP condition Interrupt Flag 16 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write WDOG0_S 0 WDOG0_S Registers 0x4A018000 0x00000000 0x00001000 registers WDOG0 43 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Module Enable 0 1 read-write CFG No Description 0x008 read-write 0x000F0000 0x730F071F CLRSRC WDOG Clear Source 0 1 read-write SW A write to the clear bit will clear the WDOG counter 0 PRSSRC0 A rising edge on the PRS Source 0 will clear the WDOG counter 1 EM2RUN EM2 Run 1 1 read-write DISABLE WDOG timer is frozen in EM2. 0 ENABLE WDOG timer is running in EM2. 1 EM3RUN EM3 Run 2 1 read-write DISABLE WDOG timer is frozen in EM3. 0 ENABLE WDOG timer is running in EM3. 1 EM4BLOCK EM4 Block 3 1 read-write DISABLE EM4 can be entered by software. See EMU for detailed description. 0 ENABLE EM4 cannot be entered by software. 1 DEBUGRUN Debug Mode Run 4 1 read-write DISABLE WDOG timer is frozen in debug mode 0 ENABLE WDOG timer is running in debug mode 1 WDOGRSTDIS WDOG Reset Disable 8 1 read-write EN A timeout will cause a WDOG reset 0 DIS A timeout will not cause a WDOG reset 1 PRS0MISSRSTEN PRS Src0 Missing Event WDOG Reset 9 1 read-write PRS1MISSRSTEN PRS Src1 Missing Event WDOG Reset 10 1 read-write PERSEL WDOG Timeout Period Select 16 4 read-write SEL0 Timeout period of 9 wdog cycles 0 SEL1 Timeout period of 17 wdog cycles 1 SEL2 Timeout period of 33 wdog cycles 2 SEL3 Timeout period of 65 wdog cycles 3 SEL4 Timeout period of 129 wdog cycles 4 SEL5 Timeout period of 257 wdog cycles 5 SEL6 Timeout period of 513 wdog cycles 6 SEL7 Timeout period of 1k wdog cycles 7 SEL8 Timeout period of 2k wdog cycles 8 SEL9 Timeout period of 4k wdog cycles 9 SEL10 Timeout period of 8k wdog cycles 10 SEL11 Timeout period of 16k wdog cycles 11 SEL12 Timeout period of 32k wdog cycles 12 SEL13 Timeout period of 64k wdog cycles 13 SEL14 Timeout period of 128k wdog cycles 14 SEL15 Timeout period of 256k wdog cycles 15 WARNSEL WDOG Warning Period Select 24 2 read-write DIS Disable 0 SEL1 Warning timeout is 25% of the Timeout. 1 SEL2 Warning timeout is 50% of the Timeout. 2 SEL3 Warning timeout is 75% of the Timeout. 3 WINSEL WDOG Illegal Window Select 28 3 read-write DIS Disabled. 0 SEL1 Window timeout is 12.5% of the Timeout. 1 SEL2 Window timeout is 25% of the Timeout. 2 SEL3 Window timeout is 37.5% of the Timeout. 3 SEL4 Window timeout is 50% of the Timeout. 4 SEL5 Window timeout is 62.5% of the Timeout. 5 SEL6 Window timeout is 75.5% of the Timeout. 6 SEL7 Window timeout is 87.5% of the Timeout. 7 CMD No Description 0x00C write-only 0x00000000 0x00000001 CLEAR WDOG Timer Clear 0 1 write-only UNCHANGED WDOG timer is unchanged. 0 CLEARED WDOG timer is cleared to 0. 1 STATUS No Description 0x014 read-only 0x00000000 0x80000000 LOCK WDOG Configuration Lock Status 31 1 read-only UNLOCKED All WDOG lockable registers are unlocked. 0 LOCKED All WDOG lockable registers are locked. 1 IF No Description 0x018 read-write 0x00000000 0x0000001F TOUT WDOG Timeout Interrupt Flag 0 1 read-write WARN WDOG Warning Timeout Interrupt Flag 1 1 read-write WIN WDOG Window Interrupt Flag 2 1 read-write PEM0 PRS Src0 Event Missing Interrupt Flag 3 1 read-write PEM1 PRS Src1 Event Missing Interrupt Flag 4 1 read-write IEN No Description 0x01C read-write 0x00000000 0x0000001F TOUT WDOG Timeout Interrupt Enable 0 1 read-write WARN WDOG Warning Timeout Interrupt Enable 1 1 read-write WIN WDOG Window Interrupt Enable 2 1 read-write PEM0 PRS Src0 Event Missing Interrupt Enable 3 1 read-write PEM1 PRS Src1 Event Missing Interrupt Enable 4 1 read-write LOCK No Description 0x020 write-only 0x0000ABE8 0x0000FFFF LOCKKEY WDOG Configuration Lock 0 16 write-only LOCK Lock WDOG lockable registers 0 UNLOCK Unlock WDOG lockable registers 44008 SYNCBUSY No Description 0x024 read-only 0x00000000 0x00000001 CMD Sync Busy for Cmd Register 0 1 read-only AMUXCP0_S 1 AMUXCP0_S Registers 0x4A020000 0x00000000 0x00001000 registers IPVERSION IPVERSION 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IPVERSION 0 32 read-only CTRL Control 0x008 read-write 0x00000000 0x00000033 FORCEHP Force High Power 0 1 read-write FORCELP Force Low Power 1 1 read-write FORCERUN Force run 4 1 read-write FORCESTOP Force stop 5 1 read-write STATUS Status 0x00C read-only 0x00000000 0x00000003 RUN running 0 1 read-only HICAP high cap 1 1 read-only TEST Test 0x010 read-write 0x00000000 0x80003313 SYNCCLK Sync Clock 0 1 read-write SYNCMODE Sync Mode 1 1 read-write FORCEREQUEST Force Request 4 1 read-write FORCEHICAP Force high capacitance driver 8 1 read-write FORCELOCAP Force low capacitance driver 9 1 read-write FORCEBOOSTON Force Boost On 12 1 read-write FORCEBOOSTOFF Force Boost Off 13 1 read-write STATUSEN Enable write to status bits 31 1 read-write TRIM Trim 0x014 read-write 0x77E44AA1 0x77FFEFFF WARMUPTIME Warm up time 0 2 read-write WUCYCLES72 Warm up cycle = 72; 3.6us @20 MHz 0 WUCYCLES96 Warm up cycle = 96; 4.8us @ 20 MHz 1 WUCYCLES128 Warm up cycle = 128; 6.4us @ 20 MHz 2 WUCYCLES160 Warm up cycle = 160; 8.0us @ 20 MHz 3 FLOATVDDCPLO Float VDDCP Low Power 2 1 read-write FLOATVDDCPHI Float VDDCP High Power 3 1 read-write BYPASSDIV2LO Bypass Div2 Low Power 4 1 read-write BYPASSDIV2HI Bypass Div2 High Power 5 1 read-write BUMP0P5XLO Bump 0.5X Low Power 6 1 read-write BUMP0P5XHI Bump 0.5X High Power 7 1 read-write BIAS2XLO Bias 2x Low Power 8 1 read-write BIAS2XHI Bias 2x High Power 9 1 read-write VOLTAGECTRLLO Charge Pump Voltage Control Low Power 10 2 read-write VOLTAGECTRLHI Charge Pump Voltage Control High Power 13 2 read-write BIASCTRLLO Bias Control Low Power 15 3 read-write BIASCTRLLOCONT Bias Control Low Power Continuous 18 3 read-write BIASCTRLHI Bias Control High Power 21 3 read-write PUMPCAPLO Pump Cap Low Power 24 3 read-write PUMPCAPHI Pump Cap High Power 28 3 read-write EUART0_S 0 EUART0_S Registers 0x4A030000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Module enable 0 1 read-write CFG0 No Description 0x008 read-write 0x00000000 0xC1D264FE LOOPBK Loopback Enable 1 1 read-write DISABLE The receiver is connected to and receives data from UARTn_RX 0 ENABLE The receiver is connected to and receives data from UARTn_TX 1 CCEN Collision Check Enable 2 1 read-write DISABLE Collision check is disabled 0 ENABLE Collision check is enabled. The receiver must be enabled for the check to be performed 1 MPM Multi-Processor Mode 3 1 read-write DISABLE The 9th bit of incoming frames has no special function 0 ENABLE An incoming frame with the 9th bit equal to MPAB will be loaded into the RX FIFO regardless of RXBLOCK and will result in the MPAB interrupt flag being set 1 MPAB Multi-Processor Address-Bit 4 1 read-write OVS Oversampling 5 3 read-write X16 16X oversampling 0 X8 8X oversampling 1 X6 6X oversampling 2 X4 4X oversampling 3 DISABLE Disable oversampling (for LF operation) 4 MSBF Most Significant Bit First 10 1 read-write DISABLE Data is sent with the least significant bit first 0 ENABLE Data is sent with the most significant bit first 1 RXINV Receiver Input Invert 13 1 read-write DISABLE Input is passed directly to the receiver 0 ENABLE Input is inverted before it is passed to the receiver 1 TXINV Transmitter output Invert 14 1 read-write DISABLE Output from the transmitter is passed unchanged to UARTn_TX 0 ENABLE Output from the transmitter is inverted before it is passed to UARTn_TX 1 AUTOTRI Automatic TX Tristate 17 1 read-write DISABLE The output on UARTn_TX when the transmitter is idle is defined by TXINV 0 ENABLE UARTn_TX is tristated whenever the transmitter is idle 1 SKIPPERRF Skip Parity Error Frames 20 1 read-write ERRSDMA Halt DMA Read On Error 22 1 read-write DISABLE Framing and parity errors have no effect on DMA requests from the UART 0 ENABLE DMA requests from the UART are blocked while the PERR or FERR interrupt flags are set 1 ERRSRX Disable RX On Error 23 1 read-write DISABLE Framing and parity errors have no effect on receiver 0 ENABLE Framing and parity errors disable the receiver 1 ERRSTX Disable TX On Error 24 1 read-write DISABLE Received framing and parity errors have no effect on transmitter 0 ENABLE Received framing and parity errors disable the transmitter 1 MVDIS Majority Vote Disable 30 1 read-write AUTOBAUDEN AUTOBAUD detection enable 31 1 read-write CFG1 No Description 0x00C read-write 0x00000000 0x00DB8E0F DBGHALT Debug halt 0 1 read-write DISABLE Continue normal UART operation even if core is halted 0 ENABLE If core is halted, receive one frame and then halt reception by deactivating RTS. Next frame reception happens when the core is unhalted during single stepping. 1 CTSINV Clear-to-send Invert Enable 1 1 read-write DISABLE The CTS pin is active low 0 ENABLE The CTS pin is active high 1 CTSEN Clear-to-send Enable 2 1 read-write DISABLE Ignore CTS 0 ENABLE Stop transmitting when CTS is inactive 1 RTSINV Request-to-send Invert Enable 3 1 read-write DISABLE The RTS pin is active low 0 ENABLE The RTS pin is active high 1 TXDMAWU Transmitter DMA Wakeup 9 1 read-write RXDMAWU Receiver DMA Wakeup 10 1 read-write SFUBRX Start Frame Unblock Receiver 11 1 read-write RXPRSEN PRS RX Enable 15 1 read-write TXFIW TX FIFO Interrupt Watermark 16 2 read-write ONEFRAME TXFL status flag and IF are set when the TX FIFO has space for at least one more frame. 0 TWOFRAMES TXFL status flag and IF are set when the TX FIFO has space for at least two more frames. 1 THREEFRAMES TXFL status flag and IF are set when the TX FIFO has space for at least three more frames. 2 FOURFRAMES TXFL status flag and IF are set when the TX FIFO has space for at least four more frames. 3 RXFIW RX FIFO Interrupt Watermark 19 2 read-write ONEFRAME RXFL status flag and IF are set when the RX FIFO has at least one frame in it. 0 TWOFRAMES RXFL status flag and IF are set when the RX FIFO has at least two frames in it. 1 THREEFRAMES RXFL status flag and IF are set when the RX FIFO has at least three frames in it. 2 FOURFRAMES RXFL status flag and IF are set when the RX FIFO has four frames in it. 3 RTSRXFW Request-to-send RX FIFO Watermark 22 2 read-write ONEFRAME RTS is set if there is space for at least one more frame in the RX FIFO. 0 TWOFRAMES RTS is set if there is space for at least two more frames in the RX FIFO. 1 THREEFRAMES RTS is set if there is space for at least three more frames in the RX FIFO. 2 FOURFRAMES RTS is set if there is space for four more frames in the RX FIFO. 3 FRAMECFG No Description 0x010 read-write 0x00001002 0x00003303 DATABITS Data-Bit Mode 0 2 read-write SEVEN Each frame contains 7 data bits 1 EIGHT Each frame contains 8 data bits 2 NINE Each frame contains 9 data bits 3 PARITY Parity-Bit Mode 8 2 read-write NONE Parity bits are not used 0 EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. 2 ODD Odd parity is used. Parity bits are automatically generated and checked by hardware. 3 STOPBITS Stop-Bit Mode 12 2 read-write HALF The transmitter generates a half stop bit. Stop-bits are not verified by receiver 0 ONE One stop bit is generated and verified 1 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies the first stop bit 2 TWO The transmitter generates two stop bits. The receiver checks the first stop-bit only 3 IRHFCFG No Description 0x014 read-write 0x00000000 0x0000000F IRHFEN Enable IrDA Module 0 1 read-write IRHFPW IrDA TX Pulse Width 1 2 read-write ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 0 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 2 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 3 IRHFFILT IrDA RX Filter 3 1 read-write DISABLE No filter enabled 0 ENABLE Filter enabled. IrDA pulse must be high for at least 4 consecutive clock cycles to be detected 1 IRLFCFG No Description 0x018 read-write 0x00000000 0x00000001 IRLFEN Pulse Generator/Extender Enable 0 1 read-write TIMINGCFG No Description 0x01C read-write 0x00000000 0x00000003 TXDELAY TX Delay Transmission 0 2 read-write NONE Frames are transmitted immediately. 0 SINGLE Transmission of new frames is delayed by a single bit period. 1 DOUBLE Transmission of new frames is delayed by a two bit periods. 2 TRIPPLE Transmission of new frames is delayed by a three bit periods. 3 STARTFRAMECFG No Description 0x020 read-write 0x00000000 0x000001FF STARTFRAME Start Frame 0 9 read-write SIGFRAMECFG No Description 0x024 read-write 0x00000000 0x000001FF SIGFRAME Signal Frame Value 0 9 read-write CLKDIV No Description 0x028 read-write 0x00000000 0x007FFFF8 DIV Fractional Clock Divider 3 20 read-write TRIGCTRL No Description 0x02C read-write 0x00000000 0x00000003 RXTEN Receive Trigger Enable 0 1 read-write TXTEN Transmit Trigger Enable 1 1 read-write CMD No Description 0x030 write-only 0x00000000 0x000001FF RXEN Receiver Enable 0 1 write-only RXDIS Receiver Disable 1 1 write-only TXEN Transmitter Enable 2 1 write-only TXDIS Transmitter Disable 3 1 write-only RXBLOCKEN Receiver Block Enable 4 1 write-only RXBLOCKDIS Receiver Block Disable 5 1 write-only TXTRIEN Transmitter Tristate Enable 6 1 write-only TXTRIDIS Transmitter Tristate Disable 7 1 write-only CLEARTX Clear TX FIFO 8 1 write-only RXDATA No Description 0x034 read-only 0x00000000 0x000007FF RXDATA RX Data 0 9 read-only PERR Parity Error 9 1 read-only FERR Framing Error 10 1 read-only RXDATAP No Description 0x038 read-only 0x00000000 0x000007FF RXDATAP RX Data Peek 0 9 read-only PERRP Parity Error Peek 9 1 read-only FERRP Framing Error Peek 10 1 read-only TXDATA No Description 0x03C write-only 0x00000000 0x00003FFF TXDATA TX Data 0 9 write-only UBRXAT Unblock RX After Transmission 9 1 write-only TXTRIAT Set TXTRI After Transmisssion 10 1 write-only TXBREAK Transit Data as Break 11 1 write-only TXDISAT Clear TXEN After Transmission 12 1 write-only RXENAT Enable RXEN After Transmission 13 1 write-only STATUS No Description 0x040 read-only 0x00003040 0x010F31FB RXENS Receiver Enable Status 0 1 read-only TXENS Transmitter Enable Status 1 1 read-only RXBLOCK Block Incoming Data 3 1 read-only TXTRI Transmitter Tristated 4 1 read-only TXC TX Complete 5 1 read-only TXFL TX FIFO Level 6 1 read-only RXFL RX FIFO Level 7 1 read-only RXFULL RX FIFO Full 8 1 read-only RXIDLE RX Idle 12 1 read-only TXIDLE TX Idle 13 1 read-only TXFCNT Valid entries in TX FIFO 16 3 read-only CLEARTXBUSY TX FIFO Clear Busy 19 1 read-only AUTOBAUDDONE Auto Baud Rate Detection Completed 24 1 read-only IF No Description 0x044 read-write 0x00000000 0x010C377F TXC TX Complete Interrupt Flag 0 1 read-write TXFL TX FIFO Level Interrupt Flag 1 1 read-write RXFL RX FIFO Level Interrupt Flag 2 1 read-write RXFULL RX FIFO Full Interrupt Flag 3 1 read-write RXOF RX FIFO Overflow Interrupt Flag 4 1 read-write RXUF RX FIFO Underflow Interrupt Flag 5 1 read-write TXOF TX FIFO Overflow Interrupt Flag 6 1 read-write PERR Parity Error Interrupt Flag 8 1 read-write FERR Framing Error Interrupt Flag 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write CCF Collision Check Fail Interrupt Flag 12 1 read-write TXIDLE TX Idle Interrupt Flag 13 1 read-write STARTF Start Frame Interrupt Flag 18 1 read-write SIGF Signal Frame Interrupt Flag 19 1 read-write AUTOBAUDDONE Auto Baud Complete Interrupt Flag 24 1 read-write IEN No Description 0x048 read-write 0x00000000 0x010C377F TXC TX Complete IEN 0 1 read-write TXFL TX FIFO Level IEN 1 1 read-write RXFL RX FIFO Level IEN 2 1 read-write RXFULL RX FIFO Full IEN 3 1 read-write RXOF RX FIFO Overflow IEN 4 1 read-write RXUF RX FIFO Underflow IEN 5 1 read-write TXOF TX FIFO Overflow IEN 6 1 read-write PERR Parity Error IEN 8 1 read-write FERR Framing Error IEN 9 1 read-write MPAF Multi-Processor Addr Frame IEN 10 1 read-write CCF Collision Check Fail IEN 12 1 read-write TXIDLE TX IDLE IEN 13 1 read-write STARTF Start Frame IEN 18 1 read-write SIGF Signal Frame IEN 19 1 read-write AUTOBAUDDONE Auto Baud Complete IEN 24 1 read-write SYNCBUSY No Description 0x04C read-only 0x00000000 0x000007FF DIV SYNCBUSY for DIV in CLKDIV 0 1 read-only RXTEN SYNCBUSY for RXTEN in TRIGCTRL 1 1 read-only TXTEN SYNCBUSY for TXTEN in TRIGCTRL 2 1 read-only RXEN SYNCBUSY for RXEN in CMD 3 1 read-only RXDIS SYNCBUSY for RXDIS in CMD 4 1 read-only TXEN SYNCBUSY for TXEN in CMD 5 1 read-only TXDIS SYNCBUSY for TXDIS in CMD 6 1 read-only RXBLOCKEN SYNCBUSY for RXBLOCKEN in CMD 7 1 read-only RXBLOCKDIS SYNCBUSY for RXBLOCKDIS in CMD 8 1 read-only TXTRIEN SYNCBUSY for TXTRIEN in CMD 9 1 read-only TXTRIDIS SYNCBUSY in TXTRIDIS in CMD 10 1 read-only CRYPTOACC_S 1 CRYPTOACC_S Registers 0x4C020000 0x00000000 0x00001000 registers CRYPTOACC 0 TRNG 1 PKE 2 FETCHADDR Fetcher: Start address of data block. In direct mode, this register is written by the software. In scatter-gather mode, this register is updated after each processed descriptor. 0x000 read-write 0x00000000 0xFFFFFFFF ADDR Start address of data block 0 32 read-write FETCHLEN Fetcher: Length of data block. In direct mode, this register is written by the software. In scatter-gather mode, this register is not used. 0x008 read-write 0x00000000 0x3FFFFFFF LENGTH Length of data block 0 28 read-write CONSTADDR Constant address 28 1 read-write REALIGN Realign length 29 1 read-write FETCHTAG Fetcher: User tag. In direct mode, this register is written by the software. In scatter-gather mode, this register is not used. 0x00C read-write 0x00000000 0xFFFFFFFF TAG User tag 0 32 read-write PUSHADDR Pusher: Start address of data block (LSB). In direct mode, this register is written by the software. In scatter-gather mode, this register is updated after each processed descriptor. 0x010 read-write 0x00000000 0xFFFFFFFF ADDR Start address of data block 0 32 read-write PUSHLEN Pusher: Length of data block. In direct mode, this register is written by the software. In scatter-gather mode, this register is not used. 0x018 read-write 0x00000000 0x7FFFFFFF LENGTH Start address of data block 0 28 read-write CONSTADDR Constant address 28 1 read-write REALIGN Realign length 29 1 read-write DISCARD Discard data 30 1 read-write IEN Interrupt enable 0x01C read-write 0x00000000 0x0000003F FETCHERENDOFBLOCK End of block interrupt enable 0 1 read-write FETCHERSTOPPED Stopped interrupt enable 1 1 read-write FETCHERERROR Error interrupt enable 2 1 read-write PUSHERENDOFBLOCK End of block interrupt enable 3 1 read-write PUSHERSTOPPED Stopped interrupt enable 4 1 read-write PUSHERERROR Error interrupt enable 5 1 read-write IF Interrupt flag register 0x028 read-only 0x00000000 0x0000003F FETCHERENDOFBLOCK End of block interrupt flag 0 1 read-only FETCHERSTOPPED Stopped interrupt flag 1 1 read-only FETCHERERROR Error interrupt flag 2 1 read-only PUSHERENDOFBLOCK End of block interrupt flag 3 1 read-only PUSHERSTOPPED Stopped interrupt flag 4 1 read-only PUSHERERROR Error interrupt flag 5 1 read-only IF_CLR Writing a '1' clears the interrupt status. Writing a '0' has no effect. 0x030 write-only 0x00000000 0x0000003F FETCHERENDOFBLOCK End of block interrupt flag clear 0 1 write-only FETCHERSTOPPED Stopped interrupt flag clear 1 1 write-only FETCHERERROR Error interrupt flag clear 2 1 write-only PUSHERENDOFBLOCK End of block interrupt flag clear 3 1 write-only PUSHERSTOPPED Stopped interrupt flag clear 4 1 write-only PUSHERERROR Error interrupt flag clear 5 1 write-only CTRL Control register, called CONFIG in Barco datasheet. 0x034 read-write 0x00000000 0x0000001F FETCHERSCATTERGATHER Fetcher scatter/gather 0 1 read-write PUSHERSCATTERGATHER Pusher scatter/gather 1 1 read-write STOPFETCHER Stop fetcher 2 1 read-write STOPPUSHER Stop pusher 3 1 read-write SWRESET Software reset 4 1 read-write CMD Command register for starting the fetcher and pusher 0x038 write-only 0x00000000 0x00000003 STARTFETCHER Start fetch 0 1 write-only STARTPUSHER Start push 1 1 write-only STATUS Status register 0x03C read-only 0x00000000 0xFFFF0073 FETCHERBSY Fetcher busy 0 1 read-only PUSHERBSY Pusher busy 1 1 read-only NOTEMPTY Not empty flag from input FIFO (fetcher) 4 1 read-only WAITING Pusher waiting for FIFO 5 1 read-only SOFTRSTBSY Software reset busy 6 1 read-only FIFODATANUM Number of data in output FIFO 16 16 read-only INCL_IPS_HW_CFG No Description 0x400 read-only 0x00000611 0x000007FF g_IncludeAES Generic g_IncludeAES value 0 1 read-only g_IncludeAESGCM Generic g_IncludeAESGCM value 1 1 read-only g_IncludeAESXTS Generic g_IncludeAESXTS value 2 1 read-only g_IncludeDES Generic g_IncludeDES value 3 1 read-only g_IncludeHASH Generic g_IncludeHASH value 4 1 read-only g_IncludeChachaPoly Generic g_IncludeChachaPoly value 5 1 read-only g_IncludeSHA3 Generic g_IncludeSHA3 value 6 1 read-only g_IncludeZUC Generic g_IncludeZUC value 7 1 read-only g_IncludeSM4 Generic g_IncludeSM4 value 8 1 read-only g_IncludePKE Generic g_IncludePKE value 9 1 read-only g_IncludeNDRNG Generic g_IncludeNDRNG value 10 1 read-only BA411E_HW_CFG_1 No Description 0x404 read-only 0x0700017F 0x070301FF g_AesModesPoss AES Modes Supported 0 9 read-only g_CS Generic g_CS value 16 1 read-only g_UseMasking Generic g_UseMasking value 17 1 read-only g_Keysize Generic g_Keysize value 24 3 read-only BA411E_HW_CFG_2 No Description 0x408 read-only 0x00000080 0x0000FFFF g_CtrSize Generic g_CtrSize value 0 16 read-only BA413_HW_CFG No Description 0x40C read-only 0x0003007F 0x0007007F g_HashMaskFunc Generic g_HashMaskFunc value 0 7 read-only g_HashPadding Generic g_HashPadding value 16 1 read-only g_HMAC_enabled Generic g_HMAC_enabled value 17 1 read-only g_HashVerifyDigest Generic g_HashVerifyDigest value 18 1 read-only BA418_HW_CFG No Description 0x410 read-only 0x00000001 0x00000001 g_Sha3CtxtEn Generic g_Sha3CtxtEn value 0 1 read-only BA419_HW_CFG No Description 0x414 read-only 0x0000005F 0x0000007F g_SM4ModesPoss Generic g_SM4ModesPoss value 0 7 read-only CRYPTOACC_S_RNGCTRL 1 CRYPTOACC_S_RNGCTRL Registers 0x4C021000 0x00000000 0x00001000 registers CRYPTOACC 0 TRNG 1 PKE 2 RNGCTRL No Description 0x000 read-write 0x00040000 0x001FFFFF ENABLE TRNG Module Enable 0 1 read-write DISABLED Module disabled 0 ENABLED Module enabled 1 TESTEN Test Enable 2 1 read-write NOISE Non-determinsitc random number generation 0 TESTDATA Pseudo-random number generation 1 CONDBYPASS Conditioning Bypass 3 1 read-write NORMAL The conditionig function is used 0 BYPASS The conditioning function is bypassed 1 REPCOUNTIEN IRQ enable for Repetition Count Test 4 1 read-write APT64IEN IRQ enable for APT64IF 5 1 read-write APT4096IEN IRQ enable for APT4096IF 6 1 read-write FULLIEN IRQ enable for FIFO full 7 1 read-write SOFTRESET Software Reset 8 1 read-write NORMAL Module not in reset 0 RESET The continuous test, the conditioning function and the FIFO are reset 1 PREIEN IRQ enable for AIS31 prelim. noise alarm 9 1 read-write ALMIEN IRQ enable for AIS31 noise alarm 10 1 read-write FORCERUN Oscillator Force Run 11 1 read-write NORMAL Oscillators will shut down when FIFO is full 0 RUN Oscillators will continue to run even after FIFO is full 1 BYPNIST NIST Start-up Test Bypass. 12 1 read-write NORMAL NIST-800-90B startup test is applied. No data will be written to the FIFO until the test passes. 0 BYPASS NIST-800-90B startup test is bypassed. 1 BYPAIS31 AIS31 Start-up Test Bypass. 13 1 read-write NORMAL AIS31 startup test is applied. No data will be written to the FIFO until the test passes. 0 BYPASS AIS31 startup test is bypassed. 1 HEALTHTESTSEL Health test input select 14 1 read-write BEFORE Before conditioning 0 AFTER After conditioning 1 AIS31TESTSEL AIS31 test input select 15 1 read-write BEFORE Before conditioning 0 AFTER After conditioning 1 NB128BITBLOCKS Number of 128b blocks in AES-CBCMAC 16 4 read-write FIFOWRSTARTUP Fifo Write Start Up 20 1 read-write FIFOLEVEL Number of 32 bits words of random available in the FIFO. Writing to this register clears the FIFO full interrupt 0x004 read-only 0x00000000 0xFFFFFFFF FIFOLEVEL FIFO Level 0 32 read-only FIFOTHRESH FIFO level at which the rings are restarted when in the FIFOFull_Off state, expressed in number of 128bit blocks 0x008 read-only 0x0000003F 0xFFFFFFFF FIFOTHRESH FIFO threshold level 0 32 read-only FIFODEPTH Maximum number of 32 bits words that can be stored in the FIFO: 2^g_fifodepth 0x00C read-only 0x00000040 0xFFFFFFFF FIFODEPTH FIFO Depth. 0 32 read-only KEY0 This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011... 0x010 read-write 0x00000000 0xFFFFFFFF KEY Key 0 32 read-write KEY1 This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011... 0x014 read-write 0x00000000 0xFFFFFFFF KEY Key 0 32 read-write KEY2 This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011... 0x018 read-write 0x00000000 0xFFFFFFFF KEY Key 0 32 read-write KEY3 This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011... 0x01C read-write 0x00000000 0xFFFFFFFF KEY Key 0 32 read-write TESTDATA This register is used to feed known data to the conditioning function or to the continuous tests. See manual 0x020 write-only 0x00000000 0xFFFFFFFF VALUE Test data input to conditioning tests 0 32 write-only RNGSTATUS No Description 0x030 read-write 0x00000000 0x000007FF TESTDATABUSY Test Data Busy 0 1 read-only IDLE TESTDATA write is finished processing or no test in progress. 0 BUSY TESTDATA write is still being processed. 1 STATE State of the control FSM 1 3 read-only RESET RESET State 0 STARTUP STARTUP State 1 FIFOFULLON FIFOFULLON State 2 FIFOFULLOFF FIFOFULLOFF State 3 RUNNING RUNNING State 4 ERROR ERROR State 5 UNUSED_6 UNUSED 6 UNUSED_7 UNUSED 7 REPCOUNTIF Repetition Count Test interrupt status 4 1 read-only APT64IF 64-sample window Adaptive Proportion IF 5 1 read-only APT4096IF 4096-sample window Adaptive Prop. IF 6 1 read-only FULLIF FIFO full interrupt status 7 1 read-only PREIF AIS31 Preliminary Noise Alarm IF 8 1 read-write ALMIF AIS31 Noise Alarm interrupt status 9 1 read-only INITWAITVAL No Description 0x034 read-write 0x0000FFFF 0x0000FFFF INITWAITVAL Wait counter value 0 16 read-write SWOFFTMRVAL Number of clk cycles to wait before stopping the rings after the FIFO is full 0x040 read-write 0x0000FFFF 0x0000FFFF SWOFFTMRVAL Switch Off Timer Value 0 16 read-write CLKDIV Sample clock divider. The frequency at which the outputs of the rings are sampled is given by Fs = Fpclk/(ClkDiv + 1) 0x044 read-write 0x00000000 0x000000FF VALUE Sample clock divider 0 8 read-write AIS31CONF0 No Description 0x048 read-write 0x43401040 0x7FFF7FFF STARTUPTHRES Start-up Threshold 0 15 read-write ONLINETHRESH Online Threshold 16 15 read-write AIS31CONF1 No Description 0x04C read-write 0x03C00680 0x7FFF7FFF HEXPECTEDVALUE Expected History Value 0 15 read-write ONLINEREPTHRESH Online Repeat Threshold 16 15 read-write AIS31CONF2 No Description 0x050 read-write 0x04400340 0x7FFF7FFF HMIN Minimum Allowed History Value 0 15 read-write HMAX Maximum Allowed History Value 16 15 read-write AIS31STATUS This register is used to obtain diagnostic information about the AIS31 start-up and online tests when g_AIS31=True. Writing to this register clears all fields 0x054 read-write 0x00000000 0x0003FFFF NUMPRELIMALARMS Number of preliminary alarms 0 16 read-write PRELIMNOISEALARMRNG Preliminary noise alarm RNG 16 1 read-write PRELIMNOISEALARMREP Preliminary noise alarm Rep 17 1 read-write CRYPTOACC_S_PKCTRL 1 CRYPTOACC_S_PKCTRL Registers 0x4C022000 0x00000000 0x00001000 registers CRYPTOACC 0 TRNG 1 PKE 2 POINTER No Description 0x000 read-write 0x00000000 0x0F0F0F0F OPPTRA OpPtrA 0 4 read-write OPPTRB OpPtrB 8 4 read-write OPPTRC OpPtrC 16 4 read-write OPPTRN OpPtrN 24 4 read-write COMMAND No Description 0x004 read-write 0x00000000 0xFC77FFFF OPERATION Type of Operation 0 7 read-write FIELD Field 7 1 read-write GFP Field is GF(p) 0 GF2M Field is GF(2^m) 1 SIZE Size of Operands in data memory 8 11 read-write SELCURVE Select Curve 20 3 read-write NONE No acceleration 0 P256 P256 1 P192 P192 4 EDWARDS Edwards Curve Enable 26 1 read-write BUFSEL Buffer Select 27 1 read-write MEM0 use data in data memory 0 0 SWAPBYTES Swap bytes 28 1 read-write NATIVE Native format (little endian) 0 SWAPPED Byte swapped (big endian) 1 FLAGA Flag A 29 1 read-write FLAGB Flag B 30 1 read-write CALCR2 Calculate R2 31 1 read-write FALSE don't recalculate R² mod N 0 TRUE re-calculate R² mod N 1 PKCTRL No Description 0x008 write-only 0x00000000 0x00000003 PKSTART PK Start 0 1 write-only IFC ClearIRQ 1 1 write-only PKSTATUS No Description 0x00C read-only 0x00000000 0x00033FFF FAILADDR Fail Address 0 4 read-only NOTONCURVE Point Px not on curve 4 1 read-only ATINFINITY Point Px at infinity 5 1 read-only COUPLENOTVALID Couple not valid 6 1 read-only PARAMNNOTVALID Param n not valid 7 1 read-only NOTIMPLEMENTED Not implemented 8 1 read-only SIGNOTVALID Signature not valid 9 1 read-only PARAMABNOTVALID Param AB not valid 10 1 read-only NOTINVERTIBLE Not invertible 11 1 read-only COMPOSITE Composite 12 1 read-only FALSE random number under test is probably prime 0 TRUE random number under test is composite 1 NOTQUAD Not quadratic residue 13 1 read-only PKBUSY PK busy 16 1 read-only PKIF Interrupt status 17 1 read-only VERSION No Description 0x010 read-only 0x00000000 0x0000FFFF SW Software version number 0 8 read-only HW Hardware version number 8 8 read-only TIMER No Description 0x014 read-only 0x00000000 0xFFFFFFFF TIMER Timer 0 32 read-only EMU_NS 1 EMU_NS Registers 0x50004000 0x00000000 0x00001000 registers EMU 6 EMUDG 29 EMUSE 30 DECBOD No Description 0x010 read-write 0x00000022 0x00000033 DECBODEN DECBOD enable 0 1 read-write DECBODMASK DECBOD Mask 1 1 read-write DECOVMBODEN Over Voltage Monitor enable 4 1 read-write DECOVMBODMASK Over Voltage Monitor Mask 5 1 read-write BOD3SENSE No Description 0x020 read-write 0x00000000 0x00000077 AVDDBODEN AVDD BOD enable 0 1 read-write VDDIO0BODEN VDDIO0 BOD enable 1 1 read-write VDDIO1BODEN VDDIO1 BOD enable 2 1 read-write VREGVDDCMPCTRL No Description 0x03C read-write 0x00000006 0x00000007 VREGINCMPEN VREGVDD comparator enable 0 1 read-write THRESSEL VREGVDD comparator threshold programming 1 2 read-write PD1PARETCTRL No Description 0x040 read-write 0x00000000 0x0000FFFF PD1PARETDIS Disable PD1 Partial Retention 0 16 read-write RETAIN Retain associated registers when in EM2/3 0 NORETAIN Do not retain associcated registers when in EM2/3 1 LOCK No Description 0x060 write-only 0x0000ADE8 0x0000FFFF LOCKKEY Lock Key 0 16 write-only UNLOCK Unlock EMU register 44520 IF No Description 0x064 read-write 0x00000000 0xEB070000 AVDDBOD AVDD BOD Interrupt flag 16 1 read-write IOVDD0BOD VDDIO0 BOD Interrupt flag 17 1 read-write EM23WAKEUP EM23 Wake up Interrupt flag 24 1 read-write VSCALEDONE Vscale done Interrupt flag 25 1 read-write TEMPAVG Temperature Average Interrupt flag 27 1 read-write TEMP Temperature Interrupt flag 29 1 read-write TEMPLOW Temperature low Interrupt flag 30 1 read-write TEMPHIGH Temperature high Interrupt flag 31 1 read-write IEN No Description 0x068 read-write 0x00000000 0xEB070000 AVDDBOD AVDD BOD Interrupt enable 16 1 read-write IOVDD0BOD VDDIO0 BOD Interrupt enable 17 1 read-write EM23WAKEUP EM23 Wake up Interrupt enable 24 1 read-write VSCALEDONE Vscale done Interrupt enable 25 1 read-write TEMPAVG Temperature Interrupt enable 27 1 read-write TEMP Temperature Interrupt enable 29 1 read-write TEMPLOW Temperature low Interrupt enable 30 1 read-write TEMPHIGH Temperature high Interrupt enable 31 1 read-write EM4CTRL No Description 0x06C read-write 0x00000000 0x00000133 EM4ENTRY EM4 entry request 0 2 read-write EM4IORETMODE EM4 IO retention mode 4 2 read-write DISABLE No Retention: Pads enter reset state when entering EM4 0 EM4EXIT Retention through EM4: Pads enter reset state when exiting EM4 1 SWUNLATCH Retention through EM4 and Wakeup: software writes UNLATCH register to remove retention 2 BOD3SENSEEM4WU Set BOD3SENSE as EM4 wakeup 8 1 read-write CMD No Description 0x070 write-only 0x00000000 0x00020E12 EM4UNLATCH EM4 unlatch 1 1 write-only TEMPAVGREQ Temperature Average Request 4 1 write-only EM01VSCALE1 Scale voltage to Vscale1 10 1 write-only EM01VSCALE2 Scale voltage to Vscale2 11 1 write-only RSTCAUSECLR Reset Cause Clear 17 1 write-only CTRL No Description 0x074 read-write 0x00000200 0xE0010309 EM2DBGEN Enable debugging in EM2 0 1 read-write TEMPAVGNUM Averaged Temperature samples num 3 1 read-write N16 16 measurements 0 N64 64 measurements 1 EM23VSCALE EM2/EM3 Vscale 8 2 read-write VSCALE0 VSCALE0. 0.9v 0 VSCALE1 VSCALE1. 1.0v 1 VSCALE2 VSCALE2. 1.1v 2 FLASHPWRUPONDEMAND Enable flash on demand wakeup 16 1 read-write EFPDIRECTMODEEN EFP Direct Mode Enable 29 1 read-write EFPDRVDECOUPLE EFP drives DECOUPLE 30 1 read-write EFPDRVDVDD EFP drives DVDD 31 1 read-write TEMPLIMITS No Description 0x078 read-write 0x01FF0000 0x01FF01FF TEMPLOW Temp Low limit 0 9 read-write TEMPHIGH Temp High limit 16 9 read-write STATUS No Description 0x084 read-only 0x00000080 0xFF0054FF LOCK Lock status 0 1 read-only UNLOCKED All EMU lockable registers are unlocked. 0 LOCKED All EMU lockable registers are locked. 1 FIRSTTEMPDONE First Temp done 1 1 read-only TEMPACTIVE Temp active 2 1 read-only TEMPAVGACTIVE Temp Average active 3 1 read-only VSCALEBUSY Vscale busy 4 1 read-only VSCALEFAILED Vscale failed 5 1 read-only VSCALE Vscale status 6 2 read-only VSCALE0 Voltage scaling set to 0.9v 0 VSCALE1 Voltage scaling set to 1.0v 1 VSCALE2 Voltage scaling set to 1.1v 2 RACACTIVE RAC active 10 1 read-only EM4IORET EM4 IO retention status 12 1 read-only EM2ENTERED EM2 entered 14 1 read-only TEMP No Description 0x088 read-only 0x00000000 0x07FF07FF TEMPLSB Temperature measured decimal part 0 2 read-only TEMP Temperature measured 2 9 read-only TEMPAVG Averaged Temperature 16 11 read-only RSTCTRL No Description 0x090 read-write 0x40010407 0xC001C5CF WDOG0RMODE Enable WDOG0 reset 0 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset except some EMU registers 1 SYSRMODE Enable M33 System reset 2 1 read-write DISABLED Reset request is blocked 0 ENABLED Device is reset except some EMU registers 1 LOCKUPRMODE Enable M33 Lockup reset 3 1 read-write DISABLED Reset Request is Block 0 ENABLED The entire device is reset except some EMU registers 1 AVDDBODRMODE Enable AVDD BOD reset 6 1 read-write DISABLED Reset Request is block 0 ENABLED The entire device is reset except some EMU registers 1 IOVDD0BODRMODE Enable VDDIO0 BOD reset 7 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset except some EMU registers 1 DECBODRMODE Enable DECBOD reset 10 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset 1 DCIRMODE DCI System reset 16 1 read-write DISABLED Reset request blocked 0 ENABLED The entire device is reset except some EMU registers 1 RSTCAUSE No Description 0x094 read-only 0x00000000 0x8001FFFF POR Power On Reset 0 1 read-only PIN Pin Reset 1 1 read-only EM4 EM4 Wakeup Reset 2 1 read-only WDOG0 Watchdog 0 Reset 3 1 read-only LOCKUP M33 Core Lockup Reset 5 1 read-only SYSREQ M33 Core Sys Reset 6 1 read-only DVDDBOD HVBOD Reset 7 1 read-only DVDDLEBOD LEBOD Reset 8 1 read-only DECBOD LVBOD Reset 9 1 read-only AVDDBOD LEBOD1 Reset 10 1 read-only IOVDD0BOD LEBOD2 Reset 11 1 read-only DCI DCI reset 16 1 read-only VREGIN DCDC VREGIN comparator 31 1 read-only DGIF No Description 0x0A0 read-write 0x00000000 0xE1000000 EM23WAKEUPDGIF EM23 Wake up Interrupt flag 24 1 read-write TEMPDGIF Temperature Interrupt flag 29 1 read-write TEMPLOWDGIF Temperature low Interrupt flag 30 1 read-write TEMPHIGHDGIF Temperature high Interrupt flag 31 1 read-write DGIEN No Description 0x0A4 read-write 0x00000000 0xE1000000 EM23WAKEUPDGIEN EM23 Wake up Interrupt enable 24 1 read-write TEMPDGIEN Temperature Interrupt enable 29 1 read-write TEMPLOWDGIEN Temperature low Interrupt enable 30 1 read-write TEMPHIGHDGIEN Temperature high Interrupt enable 31 1 read-write EFPIF No Description 0x100 read-write 0x00000000 0x00000001 EFPIF EFP Interrupt Flag 0 1 read-write EFPIEN No Description 0x104 read-write 0x00000000 0x00000001 EFPIEN EFP Interrupt enable 0 1 read-write CMU_NS 1 CMU_NS Registers 0x50008000 0x00000000 0x00001000 registers CMU 46 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only STATUS No Description 0x008 read-only 0x00000000 0xC0030001 CALRDY Calibration Ready 0 1 read-only WDOGLOCK Configuration Lock Status for WDOG 30 1 read-only UNLOCKED WDOG configuration lock is unlocked 0 LOCKED WDOG configuration lock is locked 1 LOCK Configuration Lock Status 31 1 read-only UNLOCKED Configuration lock is unlocked 0 LOCKED Configuration lock is locked 1 LOCK No Description 0x010 write-only 0x000093F7 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write this value to unlock 37879 WDOGLOCK No Description 0x014 write-only 0x00005257 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write this value to unlock 37879 IF No Description 0x020 read-write 0x00000000 0x00000003 CALRDY Calibration Ready Interrupt Flag 0 1 read-write CALOF Calibration Overflow Interrupt Flag 1 1 read-write IEN No Description 0x024 read-write 0x00000000 0x00000003 CALRDY Calibration Ready Interrupt Enable 0 1 read-write CALOF Calibration Overflow Interrupt Enable 1 1 read-write CALCMD No Description 0x050 write-only 0x00000000 0x00000003 CALSTART Calibration Start 0 1 write-only CALSTOP Calibration Stop 1 1 write-only CALCTRL No Description 0x054 read-write 0x00000000 0xFF8FFFFF CALTOP Calibration Counter Top Value 0 20 read-write CONT Continuous Calibration 23 1 read-write UPSEL Calibration Up-counter Select 24 4 read-write DISABLED Up-counter is not clocked 0 PRS PRS CMU_CALUP consumer is clocking up-counter 1 HFXO HFXO is clocking up-counter 2 LFXO LFXO is clocking up-counter 3 HFRCODPLL HFRCODPLL is clocking up-counter 4 FSRCO FSRCO is clocking up-counter 8 LFRCO LFRCO is clocking up-counter 9 ULFRCO ULFRCO is clocking up-counter 10 DOWNSEL Calibration Down-counter Select 28 4 read-write DISABLED Down-counter is not clocked 0 HCLK HCLK is clocking down-counter 1 PRS PRS CMU_CALDN consumer is clocking down-counter 2 HFXO HFXO is clocking down-counter 3 LFXO LFXO is clocking down-counter 4 HFRCODPLL HFRCODPLL is clocking down-counter 5 FSRCO FSRCO is clocking down-counter 9 LFRCO LFRCO is clocking down-counter 10 ULFRCO ULFRCO is clocking down-counter 11 CALCNT No Description 0x058 read-only 0x00000000 0x000FFFFF CALCNT Calibration Result Counter Value 0 20 read-only CLKEN0 No Description 0x064 read-write 0x00000000 0xFFFFFFFF LDMA Enable Bus Clock 0 1 read-write LDMAXBAR Enable Bus Clock 1 1 read-write RADIOAES Enable Bus Clock 2 1 read-write GPCRC Enable Bus Clock 3 1 read-write TIMER0 Enable Bus Clock 4 1 read-write TIMER1 Enable Bus Clock 5 1 read-write TIMER2 Enable Bus Clock 6 1 read-write TIMER3 Enable Bus Clock 7 1 read-write USART0 Enable Bus Clock 8 1 read-write USART1 Enable Bus Clock 9 1 read-write IADC0 Enable Bus Clock 10 1 read-write AMUXCP0 Enable Bus Clock 11 1 read-write LETIMER0 Enable Bus Clock 12 1 read-write WDOG0 Enable Bus Clock 13 1 read-write I2C0 Enable Bus Clock 14 1 read-write I2C1 Enable Bus Clock 15 1 read-write SYSCFG Enable Bus Clock 16 1 read-write DPLL0 Enable Bus Clock 17 1 read-write HFRCO0 Enable Bus Clock 18 1 read-write HFXO0 Enable Bus Clock 19 1 read-write FSRCO Enable Bus Clock 20 1 read-write LFRCO Enable Bus Clock 21 1 read-write LFXO Enable Bus Clock 22 1 read-write ULFRCO Enable Bus Clock 23 1 read-write EUART0 Enable Bus Clock 24 1 read-write PDM Enable Bus Clock 25 1 read-write GPIO Enable Bus Clock 26 1 read-write PRS Enable Bus Clock 27 1 read-write BURAM Enable Bus Clock 28 1 read-write BURTC Enable Bus Clock 29 1 read-write RTCC Enable Bus Clock 30 1 read-write DCDC Enable Bus Clock 31 1 read-write CLKEN1 No Description 0x068 read-write 0x00000000 0x0007FFFF AGC Enable Bus Clock 0 1 read-write MODEM Enable Bus Clock 1 1 read-write RFCRC Enable Bus Clock 2 1 read-write FRC Enable Bus Clock 3 1 read-write PROTIMER Enable Bus Clock 4 1 read-write RAC Enable Bus Clock 5 1 read-write SYNTH Enable Bus Clock 6 1 read-write RDSCRATCHPAD Enable Bus Clock 7 1 read-write RDMAILBOX0 Enable Bus Clock 8 1 read-write RDMAILBOX1 Enable Bus Clock 9 1 read-write PRORTC Enable Bus Clock 10 1 read-write BUFC Enable Bus Clock 11 1 read-write IFADCDEBUG Enable Bus Clock 12 1 read-write CRYPTOACC Enable Bus Clock 13 1 read-write RFSENSE Enable Bus Clock 14 1 read-write SMU Enable Bus Clock 15 1 read-write ICACHE0 Enable Bus Clock 16 1 read-write MSC Enable Bus Clock 17 1 read-write TIMER4 Enable Bus Clock 18 1 read-write SYSCLKCTRL No Description 0x070 read-write 0x00000001 0x0001F507 CLKSEL Clock Select 0 3 read-write FSRCO FSRCO is clocking SYSCLK 1 HFRCODPLL HFRCODPLL is clocking SYSCLK 2 HFXO HFXO is clocking SYSCLK 3 CLKIN0 CLKIN0 is clocking SYSCLK 4 PCLKPRESC PCLK Prescaler 10 1 read-write DIV1 PCLK is HCLK divided by 1 0 DIV2 PCLK is HCLK divided by 2 1 HCLKPRESC HCLK Prescaler 12 4 read-write DIV1 HCLK is SYSCLK divided by 1 0 DIV2 HCLK is SYSCLK divided by 2 1 DIV4 HCLK is SYSCLK divided by 4 3 DIV8 HCLK is SYSCLK divided by 8 7 DIV16 HCLK is SYSCLK divided by 16 15 RHCLKPRESC Radio HCLK Prescaler 16 1 read-write DIV1 Radio HCLK is SYSCLK divided by 1 0 DIV2 Radio HCLK is SYSCLK divided by 2 1 TRACECLKCTRL No Description 0x080 read-write 0x00000000 0x00000030 PRESC TRACECLK Prescaler 4 2 read-write DIV1 TRACECLK is SYSCLK divided by 1 0 DIV2 TRACECLK is SYSCLK divided by 2 1 DIV4 TRACECLK is SYSCLK divided by 4 3 EXPORTCLKCTRL No Description 0x090 read-write 0x00000000 0x1F0F0F0F CLKOUTSEL0 Clock Output Select 0 0 4 read-write DISABLED CLKOUT0 is not clocked 0 HCLK HCLK is clocking CLKOUT0 1 HFEXPCLK EXPORTCLK is clocking CLKOUT0 2 ULFRCO ULFRCO is clocking CLKOUT0 3 LFRCO LFRCO is clocking CLKOUT0 4 LFXO LFXO is clocking CLKOUT0 5 HFRCODPLL HFRCODPLL is clocking CLKOUT0 6 HFXO HFXO is clocking CLKOUT0 7 FSRCO FSRCO is clocking CLKOUT0 8 CLKOUTSEL1 Clock Output Select 1 8 4 read-write DISABLED CLKOUT1 is not clocked 0 HCLK HCLK is clocking CLKOUT1 1 HFEXPCLK EXPORTCLK is clocking CLKOUT1 2 ULFRCO ULFRCO is clocking CLKOUT1 3 LFRCO LFRCO is clocking CLKOUT1 4 LFXO LFXO is clocking CLKOUT1 5 HFRCODPLL HFRCODPLL is clocking CLKOUT1 6 HFXO HFXO is clocking CLKOUT1 7 FSRCO FSRCO is clocking CLKOUT1 8 CLKOUTSEL2 Clock Output Select 2 16 4 read-write DISABLED CLKOUT2 is not clocked 0 HCLK HCLK is clocking CLKOUT2 1 HFEXPCLK EXPORTCLK is clocking CLKOUT2 2 ULFRCO ULFRCO is clocking CLKOUT2 3 LFRCO LFRCO is clocking CLKOUT2 4 LFXO LFXO is clocking CLKOUT2 5 HFRCODPLL HFRCODPLL is clocking CLKOUT2 6 HFXO HFXO is clocking CLKOUT2 7 FSRCO FSRCO is clocking CLKOUT2 8 PRESC EXPORTCLK Prescaler 24 5 read-write DPLLREFCLKCTRL No Description 0x100 read-write 0x00000000 0x00000003 CLKSEL Clock Select 0 2 read-write DISABLED DPLLREFCLK is not clocked 0 HFXO HFXO is clocking DPLLREFCLK 1 LFXO LFXO is clocking DPLLREFCLK 2 CLKIN0 CLKIN0 is clocking DPLLREFCLK 3 EM01GRPACLKCTRL No Description 0x120 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write HFRCODPLL HFRCODPLL is clocking EM01GRPACLK 1 HFXO HFXO is clocking EM01GRPACLK 2 FSRCO FSRCO is clocking EM01GRPACLK 3 EM01GRPBCLKCTRL No Description 0x124 read-write 0x00000001 0x00000007 CLKSEL Clock Select 0 3 read-write HFRCODPLL HFRCODPLL is clocking EM01GRPBCLK 1 HFXO HFXO is clocking EM01GRPBCLK 2 FSRCO FSRCO is clocking EM01GRPBCLK 3 CLKIN0 CLKIN0 is clocking EM01GRPBCLK 4 HFRCODPLLRT HFRCODPLL (re-timed) is clocking EM01GRPBCLK 5 HFXORT HFXO (re-timed) is clocking EM01GRPBCLK 6 EM23GRPACLKCTRL No Description 0x140 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking EM23GRPACLK 1 LFXO LFXO is clocking EM23GRPACLK 2 ULFRCO ULFRCO is clocking EM23GRPACLK 3 EM4GRPACLKCTRL No Description 0x160 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking EM4GRPACLK 1 LFXO LFXO is clocking EM4GRPACLK 2 ULFRCO ULFRCO is clocking EM4GRPACLK 3 IADCCLKCTRL No Description 0x180 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write EM01GRPACLK EM01GRPACLK is clocking IADCCLK 1 FSRCO FSRCO is clocking IADCCLK 2 WDOG0CLKCTRL No Description 0x200 read-write 0x00000001 0x00000007 CLKSEL Clock Select 0 3 read-write LFRCO LFRCO is clocking WDOG0CLK 1 LFXO LFXO is clocking WDOG0CLK 2 ULFRCO ULFRCO is clocking WDOG0CLK 3 HCLKDIV1024 HCLKDIV1024 is clocking WDOG0CLK 4 EUART0CLKCTRL No Description 0x220 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write DISABLED UART is not clocked 0 EM01GRPACLK EM01GRPACLK is clocking UART 1 EM23GRPACLK EM23GRPACLK is clocking UART 2 RTCCCLKCTRL No Description 0x240 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking RTCCCLK 1 LFXO LFXO is clocking RTCCCLK 2 ULFRCO ULFRCO is clocking RTCCCLK 3 PRORTCCLKCTRL No Description 0x248 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking PRORTCCLK 1 LFXO LFXO is clocking PRORTCCLK 2 ULFRCO ULFRCO is clocking PRORTCCLK 3 CRYPTOACCCLKCTRL No Description 0x260 read-write 0x00000000 0x00000003 PKEN PK Enable 0 1 read-write AESEN AES Enable 1 1 read-write RADIOCLKCTRL No Description 0x280 read-write 0x00000000 0x80000001 EN Enable 0 1 read-write DBGCLK Enable Clock for Debugger 31 1 read-write HFXO0_NS 2 HFXO0_NS Registers 0x5000C000 0x00000000 0x00001000 registers HFXO0 44 IPVERSION No Description 0x000 read-only 0x00000002 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only XTALCFG No Description 0x010 read-write 0x044334CB 0x0FFFFFFF COREBIASSTARTUPI Intermediate Startup Core Bias Current 0 6 read-write COREBIASSTARTUP Startup Core Bias Current 6 6 read-write CTUNEXISTARTUP Startup Tuning Capacitance on XI 12 4 read-write CTUNEXOSTARTUP Startup Tuning Capacitance on XO 16 4 read-write TIMEOUTSTEADY Steady State Timeout 20 4 read-write T16US The steady state timeout is set to 16 us minimum. The maximum can be +40%. 0 T41US The steady state timeout is set to 41 us minimum. The maximum can be +40%. 1 T83US The steady state timeout is set to 83 us minimum. The maximum can be +40%. 2 T125US The steady state timeout is set to 125 us minimum. The maximum can be +40%. 3 T166US The steady state timeout is set to 166 us minimum. The maximum can be +40%. 4 T208US The steady state timeout is set to 208 us minimum. The maximum can be +40%. 5 T250US The steady state timeout is set to 250 us minimum. The maximum can be +40%. 6 T333US The steady state timeout is set to 333 us minimum. The maximum can be +40%. 7 T416US The steady state timeout is set to 416 us minimum. The maximum can be +40%. 8 T500US The steady state timeout is set to 500 us minimum. The maximum can be +40%. 9 T666US The steady state timeout is set to 666 us minimum. The maximum can be +40%. 10 T833US The steady state timeout is set to 833 us minimum. The maximum can be +40%. 11 T1666US The steady state timeout is set to 1666 us minimum. The maximum can be +40%. 12 T2500US The steady state timeout is set to 2500 us minimum. The maximum can be +40%. 13 T4166US The steady state timeout is set to 4166 us minimum. The maximum can be +40%. 14 T7500US The steady state timeout is set to 7500 us minimum. The maximum can be +40%. 15 TIMEOUTCBLSB Core Bias LSB Change Timeout 24 4 read-write T8US The core bias LSB change timeout is set to 8 us minimum. The maximum can be +40%. 0 T20US The core bias LSB change timeout is set to 20 us minimum. The maximum can be +40%. 1 T41US The core bias LSB change timeout is set to 41 us minimum. The maximum can be +40%. 2 T62US The core bias LSB change timeout is set to 62 us minimum. The maximum can be +40%. 3 T83US The core bias LSB change timeout is set to 83 us minimum. The maximum can be +40%. 4 T104US The core bias LSB change timeout is set to 104 us minimum. The maximum can be +40%. 5 T125US The core bias LSB change timeout is set to 125 us minimum. The maximum can be +40%. 6 T166US The core bias LSB change timeout is set to 166 us minimum. The maximum can be +40%. 7 T208US The core bias LSB change timeout is set to 208 us minimum. The maximum can be +40%. 8 T250US The core bias LSB change timeout is set to 250 us minimum. The maximum can be +40%. 9 T333US The core bias LSB change timeout is set to 333 us minimum. The maximum can be +40%. 10 T416US The core bias LSB change timeout is set to 416 us minimum. The maximum can be +40%. 11 T833US The core bias LSB change timeout is set to 833 us minimum. The maximum can be +40%. 12 T1250US The core bias LSB change timeout is set to 1250 us minimum. The maximum can be +40%. 13 T2083US The core bias LSB change timeout is set to 2083 us minimum. The maximum can be +40%. 14 T3750US The core bias LSB change timeout is set to 3750 us minimum. The maximum can be +40%. 15 XTALCTRL No Description 0x018 read-write 0x0F8C8C10 0x8FFFFFFF COREBIASANA Core Bias Current 0 8 read-write CTUNEXIANA Tuning Capacitance on XI 8 8 read-write CTUNEXOANA Tuning Capacitance on XO 16 8 read-write CTUNEFIXANA Fixed Tuning Capacitance 24 2 read-write NONE Remove fixed capacitance on XI and XO nodes 0 XI Adds fixed capacitance on XI node 1 XO Adds fixed capacitance on XO node 2 BOTH Adds fixed capacitance on both XI and XO nodes 3 COREDGENANA Core Degeneration 26 2 read-write NONE Do not apply core degeneration resistence 0 DGEN33 Apply 33 ohm core degeneration resistence 1 DGEN50 Apply 50 ohm core degeneration resistence 2 DGEN100 Apply 100 ohm core degeneration resistence 3 SKIPCOREBIASOPT Skip Core Bias Optimization 31 1 read-write CFG No Description 0x020 read-write 0x10000000 0xF000000D MODE Crystal Oscillator Mode 0 1 read-write XTAL crystal oscillator 0 EXTCLK external sinusoidal clock can be supplied on XI pin. 1 ENXIDCBIASANA Enable XI Internal DC Bias 2 1 read-write SQBUFSCHTRGANA Squaring Buffer Schmitt Trigger 3 1 read-write DISABLE Squaring buffer schmitt trigger is disabled 0 ENABLE Squaring buffer schmitt trigger is enabled 1 CTRL No Description 0x028 read-write 0x00000002 0x80000037 FORCEEN Force Enable 0 1 read-write DISONDEMAND Disable On-demand Mode 1 1 read-write KEEPWARM Keep Warm 2 1 read-write FORCEXI2GNDANA Force XI Pin to Ground 4 1 read-write DISABLE Disabled (not pulled) 0 ENABLE Enabled (pulled) 1 FORCEXO2GNDANA Force XO Pin to Ground 5 1 read-write DISABLE Disabled (not pulled) 0 ENABLE Enabled (pulled) 1 CMD No Description 0x050 write-only 0x00000000 0x00000003 COREBIASOPT Core Bias Optimizaton 0 1 write-only MANUALOVERRIDE Manual Override 1 1 write-only STATUS No Description 0x058 read-only 0x00000000 0xC00F0003 RDY Ready Status 0 1 read-only COREBIASOPTRDY Core Bias Optimization Ready 1 1 read-only ENS Enabled Status 16 1 read-only HWREQ Oscillator Requested by Hardware 17 1 read-only ISWARM Oscillator Is Kept Warm 19 1 read-only FSMLOCK FSM Lock Status 30 1 read-only UNLOCKED FSM lock is unlocked 0 LOCKED FSM lock is locked 1 LOCK Configuration Lock Status 31 1 read-only UNLOCKED Configuration lock is unlocked 0 LOCKED Configuration lock is locked 1 IF No Description 0x070 read-write 0x00000000 0xE0000003 RDY Ready Interrupt 0 1 read-write COREBIASOPTRDY Core Bias Optimization Ready Interrupt 1 1 read-write DNSERR Did Not Start Error Interrupt 29 1 read-write COREBIASOPTERR Core Bias Optimization Error Interrupt 31 1 read-write IEN No Description 0x074 read-write 0x00000000 0xE0000003 RDY Ready Interrupt 0 1 read-write COREBIASOPTRDY Core Bias Optimization Ready Interrupt 1 1 read-write DNSERR Did Not Start Error Interrupt 29 1 read-write COREBIASOPTERR Core Bias Optimization Error Interrupt 31 1 read-write LOCK No Description 0x080 write-only 0x0000580E 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write this value to unlock 22542 HFRCO0_NS 1 HFRCO0_NS Registers 0x50010000 0x00000000 0x00001000 registers HFRCO0 45 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only CTRL No Description 0x004 read-write 0x00000000 0x00000003 FORCEEN Force Enable 0 1 read-write DISONDEMAND Disable On-demand 1 1 read-write CAL No Description 0x008 read-write 0xA8689F7F 0xFFFFBF7F TUNING Tuning Value 0 7 read-write FINETUNING Fine Tuning Value 8 6 read-write LDOHP LDO High Power Mode 15 1 read-write FREQRANGE Frequency Range 16 5 read-write CMPBIAS Comparator Bias Current 21 3 read-write CLKDIV Locally Divide HFRCO Clock Output 24 2 read-write DIV1 Divide by 1. 0 DIV2 Divide by 2. 1 DIV4 Divide by 4. 2 CMPSEL Comparator Load Select 26 2 read-write IREFTC Tempco Trim on Comparator Current 28 4 read-write STATUS No Description 0x00C read-only 0x00000000 0x80010007 RDY Ready 0 1 read-only FREQBSY Frequency Updating Busy 1 1 read-only SYNCBUSY Synchronization Busy 2 1 read-only ENS Enable Status 16 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED HFRCO is unlocked 0 LOCKED HFRCO is locked 1 IF No Description 0x010 read-write 0x00000000 0x00000001 RDY Ready Interrupt Flag 0 1 read-write IEN No Description 0x014 read-write 0x00000000 0x00000001 RDY RDY Interrupt Enable 0 1 read-write LOCK No Description 0x01C write-only 0x00008195 0x0000FFFF LOCKKEY Lock Key 0 16 write-only UNLOCK Unlock code 33173 FSRCO_NS 0 FSRCO_NS Registers 0x50018000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version 0 32 read-only DPLL0_NS 0 DPLL0_NS Registers 0x5001C000 0x00000000 0x00001000 registers DPLL0 50 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Module Enable 0 1 read-write CFG No Description 0x008 read-write 0x00000000 0x00000047 MODE Operating Mode Control 0 1 read-write FLL Frequency Lock Mode 0 PLL Phase Lock Mode 1 EDGESEL Reference Edge Select 1 1 read-write AUTORECOVER Automatic Recovery Control 2 1 read-write DITHEN Dither Enable Control 6 1 read-write CFG1 No Description 0x00C read-write 0x00000000 0x0FFF0FFF M Factor M 0 12 read-write N Factor N 16 12 read-write IF No Description 0x010 read-write 0x00000000 0x00000007 LOCK Lock Interrupt Flag 0 1 read-write LOCKFAILLOW Lock Failure Low Interrupt Flag 1 1 read-write LOCKFAILHIGH Lock Failure High Interrupt Flag 2 1 read-write IEN No Description 0x014 read-write 0x00000000 0x00000007 LOCK LOCK interrupt Enable 0 1 read-write LOCKFAILLOW LOCKFAILLOW Interrupe Enable 1 1 read-write LOCKFAILHIGH LOCKFAILHIGH Interrupt Enable 2 1 read-write STATUS No Description 0x018 read-only 0x00000000 0x80000003 RDY Ready Status 0 1 read-only ENS Enable Status 1 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED 0 LOCKED 1 LOCK No Description 0x024 write-only 0x00007102 0x0000FFFF LOCKKEY Lock Key 0 16 write-only UNLOCK 28930 LFXO_NS 0 LFXO_NS Registers 0x50020000 0x00000000 0x00001000 registers LFXO 22 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CTRL No Description 0x004 read-write 0x00000002 0x00000033 FORCEEN LFXO Force Enable 0 1 read-write DISONDEMAND LFXO Disable On-demand requests 1 1 read-write FAILDETEN LFXO Failure Detection Enable 4 1 read-write FAILDETEM4WUEN LFXO Failure Detection EM4WU Enable 5 1 read-write CFG Do not write to this register unless the oscillator is forced off. The oscillator is forced off if DISONDEMAND is set and FORCEEN is cleared. 0x008 read-write 0x00000701 0x00000733 AGC LFXO AGC Enable 0 1 read-write HIGHAMPL LFXO High Amplitude Enable 1 1 read-write MODE LFXO Mode 4 2 read-write XTAL A 32768Hz crystal should be connected to the LF crystal pads. Voltage must not exceed VDDIO. 0 BUFEXTCLK An external sine source with minimum amplitude 100mv (zero-to-peak) and maximum amplitude 500mV (zero-to-peak) should be connected in series with LFXTAL_I pin. Minimum voltage should be larger than ground and maximum voltage smaller than VDDIO. The sine source does not need to be ac coupled externally as it is ac couples inside LFXO. LFXTAL_O is free to be used as a general purpose GPIO. 1 DIGEXTCLK An external 32KHz CMOS clock should be provided on LFXTAL_I. LFXTAL_O is free to be used as a general purpose GPIO. 2 TIMEOUT LFXO Start-up Delay 8 3 read-write CYCLES2 Timeout period of 2 cycles 0 CYCLES256 Timeout period of 256 cycles 1 CYCLES1K Timeout period of 1024 cycles 2 CYCLES2K Timeout period of 2048 cycles 3 CYCLES4K Timeout period of 4096 cycles 4 CYCLES8K Timeout period of 8192 cycles 5 CYCLES16K Timeout period of 16384 cycles 6 CYCLES32K Timeout period of 32768 cycles 7 STATUS No Description 0x010 read-only 0x00000000 0x80010001 RDY LFXO Ready Status 0 1 read-only ENS LFXO Enable Status 16 1 read-only LOCK LFXO Locked Status 31 1 read-only UNLOCKED LFXO lockable registers are not locked 0 LOCKED LFXO lockable registers are locked 1 CAL Do not write to this register unless CALBSY in SYNCBUSY register is low. 0x014 read-write 0x00000200 0x0000037F CAPTUNE Internal Capacitance Tuning 0 7 read-write GAIN LFXO Startup Gain 8 2 read-write IF No Description 0x018 read-write 0x00000000 0x0000000F RDY LFXO Ready Interrupt Flag 0 1 read-write POSEDGE Rising Edge Interrupt Flag 1 1 read-write NEGEDGE Falling Edge Interrupt Flag 2 1 read-write FAIL LFXO Failure Interrupt Flag 3 1 read-write IEN No Description 0x01C read-write 0x00000000 0x0000000F RDY LFXO Ready Interrupt Enable 0 1 read-write POSEDGE Rising Edge Interrupt Enable 1 1 read-write NEGEDGE Falling Edge Interrupt Enable 2 1 read-write FAIL LFXO Failure Interrupt Enable 3 1 read-write SYNCBUSY No Description 0x020 read-only 0x00000000 0x00000001 CAL LFXO Synchronization status 0 1 read-only LOCK No Description 0x024 write-only 0x00001A20 0x0000FFFF LOCKKEY Lock Key 0 16 write-only UNLOCK Unlock LFXO lockable registers 6688 LFRCO_NS 1 LFRCO_NS Registers 0x50024000 0x00000000 0x00001000 registers LFRCO 23 IPVERSION Contains the LFRCO ip version 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only CTRL Control register 0x004 read-write 0x00000000 0x00000003 FORCEEN Force Enable 0 1 read-write DISONDEMAND Disable On-Demand 1 1 read-write STATUS Status register 0x008 read-only 0x00000000 0x80010001 RDY Ready Status 0 1 read-only ENS Enabled Status 16 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED Access to configuration registers not locked 0 LOCKED Access to configuration registers locked 1 IF Interrupt flag register 0x014 read-write 0x00000000 0x00070707 RDY Ready Flag 0 1 read-write POSEDGE Rising Edge Flag 1 1 read-write NEGEDGE Falling Edge Flag 2 1 read-write TCDONE Temperature Check Done Flag 8 1 read-write CALDONE Calibration Done Flag 9 1 read-write TEMPCHANGE Temperature Change Flag 10 1 read-write SCHEDERR Scheduling Error Flag 16 1 read-write TCOOR Temperature Check Out Of Range Flag 17 1 read-write CALOOR Calibration Out Of Range Flag 18 1 read-write IEN Interrupt enable register 0x018 read-write 0x00000000 0x00070707 RDY Ready Enable 0 1 read-write POSEDGE Rising Edge Enable 1 1 read-write NEGEDGE Falling Edge Enable 2 1 read-write TCDONE Temperature Check Done Enable 8 1 read-write CALDONE Calibration Done Enable 9 1 read-write TEMPCHANGE Temperature Change Enable 10 1 read-write SCHEDERR Scheduling Error Enable 16 1 read-write TCOOR Temperature Check Out Of Range Enable 17 1 read-write CALOOR Calibration Out Of Range Enable 18 1 read-write LOCK Configuration lock register. Locks and unlocks access to configuration registers. 0x020 write-only 0x00000000 0x0000FFFF LOCKKEY Lock Key 0 16 write-only LOCK Lock Configuration Registers 0 UNLOCK Unlock Configuration Registers 3987 CFG Configuration register 0x024 read-write 0x00000000 0x00000001 HIGHPRECEN High Precision Enable 0 1 read-write NOMCAL Nominal calibration register 0x02C read-write 0x0005B8D8 0x001FFFFF NOMCALCNT Nominal Calibration Count 0 21 read-write NOMCALINV Nominal calibration inverted register 0x030 read-write 0x0000597A 0x0001FFFF NOMCALCNTINV Nominal Calibration Count Inverted 0 17 read-write CMD Command register 0x034 write-only 0x00000000 0x00000001 REDUCETCINT Reduce Temperature Check Interval 0 1 write-only ULFRCO_NS 0 ULFRCO_NS Registers 0x50028000 0x00000000 0x00001000 registers ULFRCO 24 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION ULFRCO IP version 0 32 read-only STATUS No Description 0x008 read-only 0x00000000 0x00010001 RDY Ready Status 0 1 read-only ENS Enable Status 16 1 read-only IF No Description 0x014 read-write 0x00000000 0x00000007 RDY Ready Interrupt Flag 0 1 read-write POSEDGE Positive Edge Interrupt Flag 1 1 read-write NEGEDGE Negative Edge Interrupt Flag 2 1 read-write IEN No Description 0x018 read-write 0x00000000 0x00000007 RDY Enable Ready Interrupt 0 1 read-write POSEDGE Enable Positive Edge Interrupt 1 1 read-write NEGEDGE Enable Negative Edge Interrupt 2 1 read-write MSC_NS 1 MSC_NS Registers 0x50030000 0x00000000 0x00001000 registers MSC 49 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only READCTRL No Description 0x008 read-write 0x00200000 0x00301002 DOUTBUFEN Flash dout pipeline buffer enable 12 1 read-write MODE Read Mode 20 2 read-write WS0 Zero wait-states inserted in fetch or read transfers 0 WS1 One wait-state inserted for each fetch or read transfer 1 WS2 Two wait-states inserted for eatch fetch or read transfer 2 WS3 Three wait-states inserted for eatch fetch or read transfer 3 WRITECTRL No Description 0x00C read-write 0x00000000 0x0000000B WREN Enable Write/Erase Controller 0 1 read-write IRQERASEABORT Abort Page Erase on Interrupt 1 1 read-write LPWRITE Low-Power Erase 3 1 read-write WRITECMD No Description 0x010 write-only 0x00000000 0x00001126 ERASEPAGE Erase Page 1 1 write-only WRITEEND End Write Mode 2 1 write-only ERASEABORT Abort erase sequence 5 1 write-only ERASEMAIN0 Mass erase region 0 8 1 write-only CLEARWDATA Clear WDATA state 12 1 write-only ADDRB No Description 0x014 read-write 0x00000000 0xFFFFFFFF ADDRB Page Erase or Write Address Buffer 0 32 read-write WDATA No Description 0x018 read-write 0x00000000 0xFFFFFFFF DATAW Write Data 0 32 read-write STATUS No Description 0x01C read-only 0x08000008 0xF901007F BUSY Erase/Write Busy 0 1 read-only LOCKED Access Locked 1 1 read-only INVADDR Invalid Write Address or Erase Page 2 1 read-only WDATAREADY WDATA Write Ready 3 1 read-only ERASEABORTED Erase Operation Aborted 4 1 read-only PENDING Write Command In Queue 5 1 read-only TIMEOUT Write Command Timeout 6 1 read-only REGLOCK Register Lock Status 16 1 read-only UNLOCKED Register lock is unlocked 0 LOCKED Register lock is locked. 1 PWRON Flash Power On Status 24 1 read-only WREADY Flash Write Ready 27 1 read-only PWRUPCKBDFAILCOUNT Flash power up checkerboard pattern chec 28 4 read-only IF No Description 0x020 read-write 0x00000000 0x00000307 ERASE Host Erase Done Interrupt Read Flag 0 1 read-write WRITE Host Write Done Interrupt Read Flag 1 1 read-write WDATAOV Host write buffer overflow 2 1 read-write PWRUPF Flash Power Up Sequence Complete Flag 8 1 read-write PWROFF Flash Power Off Sequence Complete Flag 9 1 read-write IEN No Description 0x024 read-write 0x00000000 0x00000307 ERASE Erase Done Interrupt enable 0 1 read-write WRITE Write Done Interrupt enable 1 1 read-write WDATAOV write data buffer overflow irq enable 2 1 read-write PWRUPF Flash Power Up Seq done irq enable 8 1 read-write PWROFF Flash Power Off Seq done irq enable 9 1 read-write USERDATASIZE No Description 0x034 read-only 0x00000004 0x0000003F USERDATASIZE User Data Size 0 6 read-only CMD No Description 0x038 write-only 0x00000000 0x00000011 PWRUP Flash Power Up Command 0 1 write-only PWROFF Flash power off/sleep command 4 1 write-only LOCK No Description 0x03C write-only 0x00000000 0x0000FFFF LOCKKEY Configuration Lock 0 16 write-only LOCK Key to lock the register lock 0 UNLOCK Key to unlock the register lock. 7025 MISCLOCKWORD No Description 0x040 read-write 0x00000011 0x00000011 MELOCKBIT Mass Erase Lock 0 1 read-write UDLOCKBIT User Data Lock 4 1 read-write PWRCTRL No Description 0x050 read-write 0x00100002 0x00FF0013 PWROFFONEM1ENTRY Power down Flash macro when enter EM1 0 1 read-write PWROFFONEM1PENTRY Power down Flash macro when enter EM1P 1 1 read-write PWROFFENTRYAGAIN POWER down flash again in EM1/EM1p 4 1 read-write PWROFFDLY Power down delay 16 8 read-write PAGELOCK0 No Description 0x120 read-write 0x00000000 0xFFFFFFFF LOCKBIT page lock bit 0 32 read-write PAGELOCK1 No Description 0x124 read-write 0x00000000 0xFFFFFFFF LOCKBIT page lock bit 0 32 read-write ICACHE0_NS 0 ICACHE0_NS Registers 0x50034000 0x00000000 0x00001000 registers ICACHE0 17 IPVERSION The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION. 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only CTRL No Description 0x004 read-write 0x00000000 0x00000007 CACHEDIS Cache Disable 0 1 read-write USEMPU Use MPU 1 1 read-write AUTOFLUSHDIS Automatic Flushing Disable 2 1 read-write PCHITS No Description 0x008 read-only 0x00000000 0xFFFFFFFF PCHITS Performance Counter Hits 0 32 read-only PCMISSES No Description 0x00C read-only 0x00000000 0xFFFFFFFF PCMISSES Performance Counter Misses 0 32 read-only PCAHITS No Description 0x010 read-only 0x00000000 0xFFFFFFFF PCAHITS Performance Counter Advanced Hits 0 32 read-only STATUS No Description 0x014 read-only 0x00000000 0x00000001 PCRUNNING PC Running 0 1 read-only CMD No Description 0x018 write-only 0x00000000 0x00000007 FLUSH Flush 0 1 write-only STARTPC Start Performance Counters 1 1 write-only STOPPC Stop Performance Counters 2 1 write-only LPMODE No Description 0x01C read-write 0x00000023 0x000000F3 LPLEVEL Low Power Level 0 2 read-write BASIC Base instruction cache functionality 0 ADVANCED Advanced buffering mode, where the cache uses the fetch pattern to predict highly accessed data and store it in low-energy memory 1 MINACTIVITY Minimum activity mode, which allows the cache to minimize activity in logic that it predicts has a low probability being used. This mode can introduce wait-states into the instruction fetch stream when the cache exits one of its low-activity states. The number of wait-states introduced is small, but users running with 0-wait-state memory and wishing to reduce the variability that the cache might introduce with additional wait-states may wish to lower the cache low-power level. Note, this mode includes the advanced buffering mode functionality. 3 NESTFACTOR Low Power Nest Factor 4 4 read-write IF No Description 0x020 read-write 0x00000000 0x00000107 HITOF Hit Overflow Interrupt Flag 0 1 read-write MISSOF Miss Overflow Interrupt Flag 1 1 read-write AHITOF Advanced Hit Overflow Interrupt Flag 2 1 read-write RAMERROR RAM error Interrupt Flag 8 1 read-write IEN No Description 0x024 read-write 0x00000000 0x00000107 HITOF Hit Overflow Interrupt Enable 0 1 read-write MISSOF Miss Overflow Interrupt Enable 1 1 read-write AHITOF Advanced Hit Overflow Interrupt Enable 2 1 read-write RAMERROR RAM error Interrupt Enable 8 1 read-write PRS_NS 1 PRS_NS Registers 0x50038000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only ASYNC_SWPULSE No Description 0x008 write-only 0x00000000 0x00000FFF CH0PULSE Channel pulse 0 1 write-only CH1PULSE Channel pulse 1 1 write-only CH2PULSE Channel pulse 2 1 write-only CH3PULSE Channel pulse 3 1 write-only CH4PULSE Channel pulse 4 1 write-only CH5PULSE Channel pulse 5 1 write-only CH6PULSE Channel pulse 6 1 write-only CH7PULSE Channel pulse 7 1 write-only CH8PULSE Channel pulse 8 1 write-only CH9PULSE Channel pulse 9 1 write-only CH10PULSE Channel pulse 10 1 write-only CH11PULSE Channel pulse 11 1 write-only ASYNC_SWLEVEL No Description 0x00C read-write 0x00000000 0x00000FFF CH0LEVEL Channel Level 0 1 read-write CH1LEVEL Channel Level 1 1 read-write CH2LEVEL Channel Level 2 1 read-write CH3LEVEL Channel Level 3 1 read-write CH4LEVEL Channel Level 4 1 read-write CH5LEVEL Channel Level 5 1 read-write CH6LEVEL Channel Level 6 1 read-write CH7LEVEL Channel Level 7 1 read-write CH8LEVEL Channel Level 8 1 read-write CH9LEVEL Channel Level 9 1 read-write CH10LEVEL Channel Level 10 1 read-write CH11LEVEL Channel Level 11 1 read-write ASYNC_PEEK No Description 0x010 read-only 0x00000000 0x00000FFF CH0VAL Channel 0 Current Value 0 1 read-only CH1VAL Channel 1 Current Value 1 1 read-only CH2VAL Channel 2 Current Value 2 1 read-only CH3VAL Channel 3 Current Value 3 1 read-only CH4VAL Channel 4 Current Value 4 1 read-only CH5VAL Channel 5 Current Value 5 1 read-only CH6VAL Channel 6 Current Value 6 1 read-only CH7VAL Channel 7 Current Value 7 1 read-only CH8VAL Channel 8 Current Value 8 1 read-only CH9VAL Channel 9 Current Value 9 1 read-only CH10VAL Channel 10 Current Value 10 1 read-only CH11VAL Channel 11 Current Value 11 1 read-only SYNC_PEEK No Description 0x014 read-only 0x00000000 0x0000000F CH0VAL Channel Value 0 1 read-only CH1VAL Channel Value 1 1 read-only CH2VAL Channel Value 2 1 read-only CH3VAL Channel Value 3 1 read-only ASYNC_CH0_CTRL No Description 0x018 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH1_CTRL No Description 0x01C read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH2_CTRL No Description 0x020 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH3_CTRL No Description 0x024 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH4_CTRL No Description 0x028 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH5_CTRL No Description 0x02C read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH6_CTRL No Description 0x030 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH7_CTRL No Description 0x034 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH8_CTRL No Description 0x038 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH9_CTRL No Description 0x03C read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH10_CTRL No Description 0x040 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH11_CTRL No Description 0x044 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write SYNC_CH0_CTRL No Description 0x048 read-write 0x00000000 0x00007F07 SIGSEL Signal Select 0 3 read-write SOURCESEL Source Select 8 7 read-write SYNC_CH1_CTRL No Description 0x04C read-write 0x00000000 0x00007F07 SIGSEL Signal Select 0 3 read-write SOURCESEL Source Select 8 7 read-write SYNC_CH2_CTRL No Description 0x050 read-write 0x00000000 0x00007F07 SIGSEL Signal Select 0 3 read-write SOURCESEL Source Select 8 7 read-write SYNC_CH3_CTRL No Description 0x054 read-write 0x00000000 0x00007F07 SIGSEL Signal Select 0 3 read-write SOURCESEL Source Select 8 7 read-write CONSUMER_CMU_CALDN CALDN Consumer Register 0x058 read-write 0x00000000 0x0000000F PRSSEL CALDN async channel select 0 4 read-write CONSUMER_CMU_CALUP CALUP Consumer Register 0x05C read-write 0x00000000 0x0000000F PRSSEL CALUP async channel select 0 4 read-write CONSUMER_IADC0_SCANTRIGGER SCAN Consumer Register 0x064 read-write 0x00000000 0x0000030F PRSSEL SCAN async channel select 0 4 read-write SPRSSEL SCAN sync channel select 8 2 read-write CONSUMER_IADC0_SINGLETRIGGER SINGLE Consumer Register 0x068 read-write 0x00000000 0x0000030F PRSSEL SINGLE async channel select 0 4 read-write SPRSSEL SINGLE sync channel select 8 2 read-write CONSUMER_LDMAXBAR_DMAREQ0 DMAREQ0 Consumer Register 0x06C read-write 0x00000000 0x0000000F PRSSEL DMAREQ0 async channel select 0 4 read-write CONSUMER_LDMAXBAR_DMAREQ1 DMAREQ1 Consumer Register 0x070 read-write 0x00000000 0x0000000F PRSSEL DMAREQ1 async channel select 0 4 read-write CONSUMER_LETIMER0_CLEAR CLEAR Consumer Register 0x074 read-write 0x00000000 0x0000000F PRSSEL CLEAR async channel select 0 4 read-write CONSUMER_LETIMER0_START START Consumer Register 0x078 read-write 0x00000000 0x0000000F PRSSEL START async channel select 0 4 read-write CONSUMER_LETIMER0_STOP STOP Consumer Register 0x07C read-write 0x00000000 0x0000000F PRSSEL STOP async channel select 0 4 read-write CONSUMER_EUART0_RX RX Consumer Register 0x080 read-write 0x00000000 0x0000000F PRSSEL RX async channel select 0 4 read-write CONSUMER_EUART0_TRIGGER TRIGGER Consumer Register 0x084 read-write 0x00000000 0x0000000F PRSSEL TRIGGER async channel select 0 4 read-write CONSUMER_MODEM_DIN DIN Consumer Register 0x088 read-write 0x00000000 0x0000000F PRSSEL DIN async channel select 0 4 read-write CONSUMER_RAC_CLR CLR Consumer Register 0x0C0 read-write 0x00000000 0x0000000F PRSSEL CLR async channel select 0 4 read-write CONSUMER_RAC_CTIIN0 CTI Consumer Register 0x0C4 read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_RAC_CTIIN1 CTI Consumer Register 0x0C8 read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_RAC_CTIIN2 CTI Consumer Register 0x0CC read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_RAC_CTIIN3 CTI Consumer Register 0x0D0 read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_RAC_FORCETX FORCETX Consumer Register 0x0D4 read-write 0x00000000 0x0000000F PRSSEL FORCETX async channel select 0 4 read-write CONSUMER_RAC_RXDIS RXDIS Consumer Register 0x0D8 read-write 0x00000000 0x0000000F PRSSEL RXDIS async channel select 0 4 read-write CONSUMER_RAC_RXEN RXEN Consumer Register 0x0DC read-write 0x00000000 0x0000000F PRSSEL RXEN async channel select 0 4 read-write CONSUMER_RAC_SEQ SEQ Consumer Register 0x0E0 read-write 0x00000000 0x0000000F PRSSEL SEQ async channel select 0 4 read-write CONSUMER_RAC_TXEN TXEN Consumer Register 0x0E4 read-write 0x00000000 0x0000000F PRSSEL TXEN async channel select 0 4 read-write CONSUMER_RTCC_CC0 CC0 Consumer Register 0x0E8 read-write 0x00000000 0x0000000F PRSSEL CC0 async channel select 0 4 read-write CONSUMER_RTCC_CC1 CC1 Consumer Register 0x0EC read-write 0x00000000 0x0000000F PRSSEL CC1 async channel select 0 4 read-write CONSUMER_RTCC_CC2 CC2 Consumer Register 0x0F0 read-write 0x00000000 0x0000000F PRSSEL CC2 async channel select 0 4 read-write CONSUMER_CORE_CTIIN0 CTI Consumer Register 0x0F8 read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_CORE_CTIIN1 CTI Consumer Register 0x0FC read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_CORE_CTIIN2 CTI Consumer Register 0x100 read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_CORE_CTIIN3 CTI Consumer Register 0x104 read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_CORE_M33RXEV M33 Consumer Register 0x108 read-write 0x00000000 0x0000000F PRSSEL M33 async channel select 0 4 read-write CONSUMER_TIMER0_CC0 CC0 Consumer Register 0x10C read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER0_CC1 CC1 Consumer Register 0x110 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER0_CC2 CC2 Consumer Register 0x114 read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER0_DTI DTI Consumer Register 0x118 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER0_DTIFS1 DTI Consumer Register 0x11C read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER0_DTIFS2 DTI Consumer Register 0x120 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER1_CC0 CC0 Consumer Register 0x124 read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER1_CC1 CC1 Consumer Register 0x128 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER1_CC2 CC2 Consumer Register 0x12C read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER1_DTI DTI Consumer Register 0x130 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER1_DTIFS1 DTI Consumer Register 0x134 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER1_DTIFS2 DTI Consumer Register 0x138 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER2_CC0 CC0 Consumer Register 0x13C read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER2_CC1 CC1 Consumer Register 0x140 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER2_CC2 CC2 Consumer Register 0x144 read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER2_DTI DTI Consumer Register 0x148 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER2_DTIFS1 DTI Consumer Register 0x14C read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER2_DTIFS2 DTI Consumer Register 0x150 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER3_CC0 CC0 Consumer Register 0x154 read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER3_CC1 CC1 Consumer Register 0x158 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER3_CC2 CC2 Consumer Register 0x15C read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER3_DTI DTI Consumer Register 0x160 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER3_DTIFS1 DTI Consumer Register 0x164 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER3_DTIFS2 DTI Consumer Register 0x168 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER4_CC0 CC0 Consumer Register 0x16C read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER4_CC1 CC1 Consumer Register 0x170 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER4_CC2 CC2 Consumer Register 0x174 read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER4_DTI DTI Consumer Register 0x178 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER4_DTIFS1 DTI Consumer Register 0x17C read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER4_DTIFS2 DTI Consumer Register 0x180 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_USART0_CLK CLK Consumer Register 0x184 read-write 0x00000000 0x0000000F PRSSEL CLK async channel select 0 4 read-write CONSUMER_USART0_IR IR Consumer Register 0x188 read-write 0x00000000 0x0000000F PRSSEL IR async channel select 0 4 read-write CONSUMER_USART0_RX RX Consumer Register 0x18C read-write 0x00000000 0x0000000F PRSSEL RX async channel select 0 4 read-write CONSUMER_USART0_TRIGGER TRIGGER Consumer Register 0x190 read-write 0x00000000 0x0000000F PRSSEL TRIGGER async channel select 0 4 read-write CONSUMER_USART1_CLK CLK Consumer Register 0x194 read-write 0x00000000 0x0000000F PRSSEL CLK async channel select 0 4 read-write CONSUMER_USART1_IR IR Consumer Register 0x198 read-write 0x00000000 0x0000000F PRSSEL IR async channel select 0 4 read-write CONSUMER_USART1_RX RX Consumer Register 0x19C read-write 0x00000000 0x0000000F PRSSEL RX async channel select 0 4 read-write CONSUMER_USART1_TRIGGER TRIGGER Consumer Register 0x1A0 read-write 0x00000000 0x0000000F PRSSEL TRIGGER async channel select 0 4 read-write CONSUMER_WDOG0_SRC0 SRC0 Consumer Register 0x1A4 read-write 0x00000000 0x0000000F PRSSEL SRC0 async channel select 0 4 read-write CONSUMER_WDOG0_SRC1 SRC1 Consumer Register 0x1A8 read-write 0x00000000 0x0000000F PRSSEL SRC1 async channel select 0 4 read-write GPIO_NS 1 GPIO_NS Registers 0x5003C000 0x00000000 0x00001000 registers GPIO_ODD 25 GPIO_EVEN 26 PORTA_CTRL Port control 0x000 read-write 0x00400040 0x10701070 SLEWRATE Slew Rate 4 3 read-write DINDIS Data In Disable 12 1 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write DINDISALT Data In Disable Alt 28 1 read-write PORTA_MODEL mode low 0x004 read-write 0x00000000 0xFFFFFFFF MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE4 MODE n 16 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE5 MODE n 20 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE6 MODE n 24 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE7 MODE n 28 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTA_MODEH mode high 0x00C read-write 0x00000000 0x0000000F MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTA_DOUT data out 0x010 read-write 0x00000000 0x000001FF DOUT Data output 0 9 read-write PORTA_DIN data in 0x014 read-only 0x00000000 0x000001FF DIN Data input 0 9 read-only PORTB_CTRL Port control 0x030 read-write 0x00400040 0x10701070 SLEWRATE Slew Rate 4 3 read-write DINDIS Data In Disable 12 1 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write DINDISALT Data In Disable Alt 28 1 read-write PORTB_MODEL mode low 0x034 read-write 0x00000000 0x000FFFFF MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE4 MODE n 16 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTB_DOUT data out 0x040 read-write 0x00000000 0x0000001F DOUT Data output 0 5 read-write PORTB_DIN data in 0x044 read-only 0x00000000 0x0000001F DIN Data input 0 5 read-only PORTC_CTRL Port control 0x060 read-write 0x00400040 0x10701070 SLEWRATE Slew Rate 4 3 read-write DINDIS Data In Disable 12 1 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write DINDISALT Data In Disable Alt 28 1 read-write PORTC_MODEL mode low 0x064 read-write 0x00000000 0xFFFFFFFF MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE4 MODE n 16 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE5 MODE n 20 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE6 MODE n 24 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE7 MODE n 28 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTC_DOUT data out 0x070 read-write 0x00000000 0x000000FF DOUT Data output 0 8 read-write PORTC_DIN data in 0x074 read-only 0x00000000 0x000000FF DIN Data input 0 8 read-only PORTD_CTRL Port control 0x090 read-write 0x00400040 0x10701070 SLEWRATE Slew Rate 4 3 read-write DINDIS Data In Disable 12 1 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write DINDISALT Data In Disable Alt 28 1 read-write PORTD_MODEL mode low 0x094 read-write 0x00000000 0x0000FFFF MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTD_DOUT data out 0x0A0 read-write 0x00000000 0x0000000F DOUT Data output 0 4 read-write PORTD_DIN data in 0x0A4 read-only 0x00000000 0x0000000F DIN Data input 0 4 read-only LOCK No Description 0x300 write-only 0x0000A534 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Unlock code 42292 GPIOLOCKSTATUS No Description 0x310 read-only 0x00000000 0x00000001 LOCK GPIO LOCK status 0 1 read-only UNLOCKED Registers are unlocked 0 LOCKED Registers are locked 1 ABUSALLOC A Bus allocation 0x320 read-write 0x00000000 0x0F0F0F0F AEVEN0 A Bus Even 0 0 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 AEVEN1 A Bus Even 1 8 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 AODD0 A Bus Odd 0 16 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 AODD1 A Bus Odd 1 24 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 BBUSALLOC B Bus allocation 0x324 read-write 0x00000000 0x0F0F0F0F BEVEN0 B Bus Even 0 0 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 BEVEN1 B Bus Even 1 8 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 BODD0 B Bus Odd 0 16 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 BODD1 B Bus Odd 1 24 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 CDBUSALLOC CD Bus allocation 0x328 read-write 0x00000000 0x0F0F0F0F CDEVEN0 CD Bus Even 0 0 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 CDEVEN1 CD Bus Even 1 8 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 CDODD0 CD Bus Odd 0 16 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 CDODD1 CD Bus Odd 1 24 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 EXTIPSELL External Interrupt Port Select Low 0x400 read-write 0x00000000 0x33333333 EXTIPSEL0 External Interrupt Port Select 0 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL1 External Interrupt Port Select 4 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL2 External Interrupt Port Select 8 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL3 External Interrupt Port Select 12 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL4 External Interrupt Port Select 16 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL5 External Interrupt Port Select 20 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL6 External Interrupt Port Select 24 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL7 External Interrupt Port Select 28 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSELH External interrupt Port Select High 0x404 read-write 0x00000000 0x00003333 EXTIPSEL0 External Interrupt Port Select 0 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL1 External Interrupt Port Select 4 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL2 External Interrupt Port Select 8 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL3 External Interrupt Port Select 12 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPINSELL External Interrupt Pin Select Low 0x408 read-write 0x00000000 0x33333333 EXTIPINSEL0 External Interrupt Pin select 0 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL1 External Interrupt Pin select 4 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL2 External Interrupt Pin select 8 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL3 External Interrupt Pin select 12 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL4 External Interrupt Pin select 16 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL5 External Interrupt Pin select 20 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL6 External Interrupt Pin select 24 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL7 External Interrupt Pin select 28 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSELH External Interrupt Pin Select High 0x40C read-write 0x00000000 0x00003333 EXTIPINSEL0 External Interrupt Pin select 0 2 read-write OFFSET8 OFFSET=8 0 OFFSET9 OFFSET=9 1 OFFSET10 OFFSET=10 2 OFFSET11 OFFSET=11 3 EXTIPINSEL1 External Interrupt Pin select 4 2 read-write OFFSET8 OFFSET=8 0 OFFSET9 OFFSET=9 1 OFFSET10 OFFSET=10 2 OFFSET11 OFFSET=11 3 EXTIPINSEL2 External Interrupt Pin select 8 2 read-write OFFSET8 OFFSET=8 0 OFFSET9 OFFSET=9 1 OFFSET10 OFFSET=10 2 OFFSET11 OFFSET=11 3 EXTIPINSEL3 External Interrupt Pin select 12 2 read-write OFFSET8 OFFSET=8 0 OFFSET9 OFFSET=9 1 OFFSET10 OFFSET=10 2 OFFSET11 OFFSET=11 3 EXTIRISE External Interrupt Rising Edge Trigger 0x410 read-write 0x00000000 0x00000FFF EXTIRISE EXT Int Rise 0 12 read-write EXTIFALL External Interrupt Falling Edge Trigger 0x414 read-write 0x00000000 0x00000FFF EXTIFALL EXT Int FALL 0 12 read-write IF Interrupt Flag 0x420 read-write 0x00000000 0x0FFF0FFF EXTIF0 External Pin Flag 0 1 read-write EXTIF1 External Pin Flag 1 1 read-write EXTIF2 External Pin Flag 2 1 read-write EXTIF3 External Pin Flag 3 1 read-write EXTIF4 External Pin Flag 4 1 read-write EXTIF5 External Pin Flag 5 1 read-write EXTIF6 External Pin Flag 6 1 read-write EXTIF7 External Pin Flag 7 1 read-write EXTIF8 External Pin Flag 8 1 read-write EXTIF9 External Pin Flag 9 1 read-write EXTIF10 External Pin Flag 10 1 read-write EXTIF11 External Pin Flag 11 1 read-write EM4WU EM4 wake up 16 12 read-write IEN Interrupt Enable 0x424 read-write 0x00000000 0x0FFF0FFF EXTIEN0 External Pin Enable 0 1 read-write EXTIEN1 External Pin Enable 1 1 read-write EXTIEN2 External Pin Enable 2 1 read-write EXTIEN3 External Pin Enable 3 1 read-write EXTIEN4 External Pin Enable 4 1 read-write EXTIEN5 External Pin Enable 5 1 read-write EXTIEN6 External Pin Enable 6 1 read-write EXTIEN7 External Pin Enable 7 1 read-write EXTIEN8 External Pin Enable 8 1 read-write EXTIEN9 External Pin Enable 9 1 read-write EXTIEN10 External Pin Enable 10 1 read-write EXTIEN11 External Pin Enable 11 1 read-write EM4WUIEN0 EM4 Wake Up Interrupt En 16 1 read-write EM4WUIEN1 EM4 Wake Up Interrupt En 17 1 read-write EM4WUIEN2 EM4 Wake Up Interrupt En 18 1 read-write EM4WUIEN3 EM4 Wake Up Interrupt En 19 1 read-write EM4WUIEN4 EM4 Wake Up Interrupt En 20 1 read-write EM4WUIEN5 EM4 Wake Up Interrupt En 21 1 read-write EM4WUIEN6 EM4 Wake Up Interrupt En 22 1 read-write EM4WUIEN7 EM4 Wake Up Interrupt En 23 1 read-write EM4WUIEN8 EM4 Wake Up Interrupt En 24 1 read-write EM4WUIEN9 EM4 Wake Up Interrupt En 25 1 read-write EM4WUIEN10 EM4 Wake Up Interrupt En 26 1 read-write EM4WUIEN11 EM4 Wake Up Interrupt En 27 1 read-write EM4WUEN No Description 0x42C read-write 0x00000000 0x0FFF0000 EM4WUEN EM4 wake up enable 16 12 read-write EM4WUPOL No Description 0x430 read-write 0x00000000 0x0FFF0000 EM4WUPOL EM4 Wake-Up Polarity 16 12 read-write DBGROUTEPEN No Description 0x440 read-write 0x0000000F 0x0000000F SWCLKTCKPEN Route Pin Enable 0 1 read-write SWDIOTMSPEN Route Location 0 1 1 read-write TDOPEN JTAG Test Debug Output Pin Enable 2 1 read-write TDIPEN JTAG Test Debug Input Pin Enable 3 1 read-write TRACEROUTEPEN No Description 0x444 read-write 0x00000000 0x00000007 SWVPEN Serial Wire Viewer Output Pin Enable 0 1 read-write TRACECLKPEN Trace Clk Pin Enable 1 1 read-write TRACEDATA0PEN Trace Data0 Pin Enable 2 1 read-write CMU_ROUTEEN CMU pin enable 0x450 read-write 0x00000000 0x0000000F CLKOUT0PEN CLKOUT0 pin enable control bit 0 1 read-write CLKOUT1PEN CLKOUT1 pin enable control bit 1 1 read-write CLKOUT2PEN CLKOUT2 pin enable control bit 2 1 read-write CMU_CLKIN0ROUTE CLKIN0 port/pin select 0x454 read-write 0x00000000 0x000F0003 PORT CLKIN0 port select register 0 2 read-write PIN CLKIN0 pin select register 16 4 read-write CMU_CLKOUT0ROUTE CLKOUT0 port/pin select 0x458 read-write 0x00000000 0x000F0003 PORT CLKOUT0 port select register 0 2 read-write PIN CLKOUT0 pin select register 16 4 read-write CMU_CLKOUT1ROUTE CLKOUT1 port/pin select 0x45C read-write 0x00000000 0x000F0003 PORT CLKOUT1 port select register 0 2 read-write PIN CLKOUT1 pin select register 16 4 read-write CMU_CLKOUT2ROUTE CLKOUT2 port/pin select 0x460 read-write 0x00000000 0x000F0003 PORT CLKOUT2 port select register 0 2 read-write PIN CLKOUT2 pin select register 16 4 read-write DCDC_ROUTEEN DCDC pin enable 0x46C read-write 0x00000000 0x00000003 DCDCCOREHIDDENPEN DCDCCOREHIDDEN pin enable control bit 0 1 read-write FRC_ROUTEEN FRC pin enable 0x47C read-write 0x00000000 0x00000007 DCLKPEN DCLK pin enable control bit 0 1 read-write DFRAMEPEN DFRAME pin enable control bit 1 1 read-write DOUTPEN DOUT pin enable control bit 2 1 read-write FRC_DCLKROUTE DCLK port/pin select 0x480 read-write 0x00000000 0x000F0003 PORT DCLK port select register 0 2 read-write PIN DCLK pin select register 16 4 read-write FRC_DFRAMEROUTE DFRAME port/pin select 0x484 read-write 0x00000000 0x000F0003 PORT DFRAME port select register 0 2 read-write PIN DFRAME pin select register 16 4 read-write FRC_DOUTROUTE DOUT port/pin select 0x488 read-write 0x00000000 0x000F0003 PORT DOUT port select register 0 2 read-write PIN DOUT pin select register 16 4 read-write I2C0_ROUTEEN I2C0 pin enable 0x490 read-write 0x00000000 0x00000003 SCLPEN SCL pin enable control bit 0 1 read-write SDAPEN SDA pin enable control bit 1 1 read-write I2C0_SCLROUTE SCL port/pin select 0x494 read-write 0x00000000 0x000F0003 PORT SCL port select register 0 2 read-write PIN SCL pin select register 16 4 read-write I2C0_SDAROUTE SDA port/pin select 0x498 read-write 0x00000000 0x000F0003 PORT SDA port select register 0 2 read-write PIN SDA pin select register 16 4 read-write I2C1_ROUTEEN I2C1 pin enable 0x4A0 read-write 0x00000000 0x00000003 SCLPEN SCL pin enable control bit 0 1 read-write SDAPEN SDA pin enable control bit 1 1 read-write I2C1_SCLROUTE SCL port/pin select 0x4A4 read-write 0x00000000 0x000F0003 PORT SCL port select register 0 2 read-write PIN SCL pin select register 16 4 read-write I2C1_SDAROUTE SDA port/pin select 0x4A8 read-write 0x00000000 0x000F0003 PORT SDA port select register 0 2 read-write PIN SDA pin select register 16 4 read-write LETIMER0_ROUTEEN LETIMER pin enable 0x4B0 read-write 0x00000000 0x00000003 OUT0PEN OUT0 pin enable control bit 0 1 read-write OUT1PEN OUT1 pin enable control bit 1 1 read-write LETIMER0_OUT0ROUTE OUT0 port/pin select 0x4B4 read-write 0x00000000 0x000F0003 PORT OUT0 port select register 0 2 read-write PIN OUT0 pin select register 16 4 read-write LETIMER0_OUT1ROUTE OUT1 port/pin select 0x4B8 read-write 0x00000000 0x000F0003 PORT OUT1 port select register 0 2 read-write PIN OUT1 pin select register 16 4 read-write EUART0_ROUTEEN EUART pin enable 0x4C0 read-write 0x00000000 0x00000003 RTSPEN RTS pin enable control bit 0 1 read-write TXPEN TX pin enable control bit 1 1 read-write EUART0_CTSROUTE CTS port/pin select 0x4C4 read-write 0x00000000 0x000F0003 PORT CTS port select register 0 2 read-write PIN CTS pin select register 16 4 read-write EUART0_RTSROUTE RTS port/pin select 0x4C8 read-write 0x00000000 0x000F0003 PORT RTS port select register 0 2 read-write PIN RTS pin select register 16 4 read-write EUART0_RXROUTE RX port/pin select 0x4CC read-write 0x00000000 0x000F0003 PORT RX port select register 0 2 read-write PIN RX pin select register 16 4 read-write EUART0_TXROUTE TX port/pin select 0x4D0 read-write 0x00000000 0x000F0003 PORT TX port select register 0 2 read-write PIN TX pin select register 16 4 read-write MODEM_ROUTEEN MODEM pin enable 0x4D8 read-write 0x00000000 0x00007FFF ANT0PEN ANT0 pin enable control bit 0 1 read-write ANT1PEN ANT1 pin enable control bit 1 1 read-write ANTROLLOVERPEN ANTROLLOVER pin enable control bit 2 1 read-write ANTRR0PEN ANTRR0 pin enable control bit 3 1 read-write ANTRR1PEN ANTRR1 pin enable control bit 4 1 read-write ANTRR2PEN ANTRR2 pin enable control bit 5 1 read-write ANTRR3PEN ANTRR3 pin enable control bit 6 1 read-write ANTRR4PEN ANTRR4 pin enable control bit 7 1 read-write ANTRR5PEN ANTRR5 pin enable control bit 8 1 read-write ANTSWENPEN ANTSWEN pin enable control bit 9 1 read-write ANTSWUSPEN ANTSWUS pin enable control bit 10 1 read-write ANTTRIGPEN ANTTRIG pin enable control bit 11 1 read-write ANTTRIGSTOPPEN ANTTRIGSTOP pin enable control bit 12 1 read-write DCLKPEN DCLK pin enable control bit 13 1 read-write DOUTPEN DOUT pin enable control bit 14 1 read-write MODEM_ANT0ROUTE ANT0 port/pin select 0x4DC read-write 0x00000000 0x000F0003 PORT ANT0 port select register 0 2 read-write PIN ANT0 pin select register 16 4 read-write MODEM_ANT1ROUTE ANT1 port/pin select 0x4E0 read-write 0x00000000 0x000F0003 PORT ANT1 port select register 0 2 read-write PIN ANT1 pin select register 16 4 read-write MODEM_ANTROLLOVERROUTE ANTROLLOVER port/pin select 0x4E4 read-write 0x00000000 0x000F0003 PORT ANTROLLOVER port select register 0 2 read-write PIN ANTROLLOVER pin select register 16 4 read-write MODEM_ANTRR0ROUTE ANTRR0 port/pin select 0x4E8 read-write 0x00000000 0x000F0003 PORT ANTRR0 port select register 0 2 read-write PIN ANTRR0 pin select register 16 4 read-write MODEM_ANTRR1ROUTE ANTRR1 port/pin select 0x4EC read-write 0x00000000 0x000F0003 PORT ANTRR1 port select register 0 2 read-write PIN ANTRR1 pin select register 16 4 read-write MODEM_ANTRR2ROUTE ANTRR2 port/pin select 0x4F0 read-write 0x00000000 0x000F0003 PORT ANTRR2 port select register 0 2 read-write PIN ANTRR2 pin select register 16 4 read-write MODEM_ANTRR3ROUTE ANTRR3 port/pin select 0x4F4 read-write 0x00000000 0x000F0003 PORT ANTRR3 port select register 0 2 read-write PIN ANTRR3 pin select register 16 4 read-write MODEM_ANTRR4ROUTE ANTRR4 port/pin select 0x4F8 read-write 0x00000000 0x000F0003 PORT ANTRR4 port select register 0 2 read-write PIN ANTRR4 pin select register 16 4 read-write MODEM_ANTRR5ROUTE ANTRR5 port/pin select 0x4FC read-write 0x00000000 0x000F0003 PORT ANTRR5 port select register 0 2 read-write PIN ANTRR5 pin select register 16 4 read-write MODEM_ANTSWENROUTE ANTSWEN port/pin select 0x500 read-write 0x00000000 0x000F0003 PORT ANTSWEN port select register 0 2 read-write PIN ANTSWEN pin select register 16 4 read-write MODEM_ANTSWUSROUTE ANTSWUS port/pin select 0x504 read-write 0x00000000 0x000F0003 PORT ANTSWUS port select register 0 2 read-write PIN ANTSWUS pin select register 16 4 read-write MODEM_ANTTRIGROUTE ANTTRIG port/pin select 0x508 read-write 0x00000000 0x000F0003 PORT ANTTRIG port select register 0 2 read-write PIN ANTTRIG pin select register 16 4 read-write MODEM_ANTTRIGSTOPROUTE ANTTRIGSTOP port/pin select 0x50C read-write 0x00000000 0x000F0003 PORT ANTTRIGSTOP port select register 0 2 read-write PIN ANTTRIGSTOP pin select register 16 4 read-write MODEM_DCLKROUTE DCLK port/pin select 0x510 read-write 0x00000000 0x000F0003 PORT DCLK port select register 0 2 read-write PIN DCLK pin select register 16 4 read-write MODEM_DINROUTE DIN port/pin select 0x514 read-write 0x00000000 0x000F0003 PORT DIN port select register 0 2 read-write PIN DIN pin select register 16 4 read-write MODEM_DOUTROUTE DOUT port/pin select 0x518 read-write 0x00000000 0x000F0003 PORT DOUT port select register 0 2 read-write PIN DOUT pin select register 16 4 read-write PDM_ROUTEEN PDM pin enable 0x520 read-write 0x00000000 0x00000001 CLKPEN CLK pin enable control bit 0 1 read-write PDM_CLKROUTE CLK port/pin select 0x524 read-write 0x00000000 0x000F0003 PORT CLK port select register 0 2 read-write PIN CLK pin select register 16 4 read-write PDM_DAT0ROUTE DAT0 port/pin select 0x528 read-write 0x00000000 0x000F0003 PORT DAT0 port select register 0 2 read-write PIN DAT0 pin select register 16 4 read-write PDM_DAT1ROUTE DAT1 port/pin select 0x52C read-write 0x00000000 0x000F0003 PORT DAT1 port select register 0 2 read-write PIN DAT1 pin select register 16 4 read-write PRS0_ROUTEEN PRS0 pin enable 0x534 read-write 0x00000000 0x0000FFFF ASYNCH0PEN ASYNCH0 pin enable control bit 0 1 read-write ASYNCH1PEN ASYNCH1 pin enable control bit 1 1 read-write ASYNCH2PEN ASYNCH2 pin enable control bit 2 1 read-write ASYNCH3PEN ASYNCH3 pin enable control bit 3 1 read-write ASYNCH4PEN ASYNCH4 pin enable control bit 4 1 read-write ASYNCH5PEN ASYNCH5 pin enable control bit 5 1 read-write ASYNCH6PEN ASYNCH6 pin enable control bit 6 1 read-write ASYNCH7PEN ASYNCH7 pin enable control bit 7 1 read-write ASYNCH8PEN ASYNCH8 pin enable control bit 8 1 read-write ASYNCH9PEN ASYNCH9 pin enable control bit 9 1 read-write ASYNCH10PEN ASYNCH10 pin enable control bit 10 1 read-write ASYNCH11PEN ASYNCH11 pin enable control bit 11 1 read-write SYNCH0PEN SYNCH0 pin enable control bit 12 1 read-write SYNCH1PEN SYNCH1 pin enable control bit 13 1 read-write SYNCH2PEN SYNCH2 pin enable control bit 14 1 read-write SYNCH3PEN SYNCH3 pin enable control bit 15 1 read-write PRS0_ASYNCH0ROUTE ASYNCH0 port/pin select 0x538 read-write 0x00000000 0x000F0003 PORT ASYNCH0 port select register 0 2 read-write PIN ASYNCH0 pin select register 16 4 read-write PRS0_ASYNCH1ROUTE ASYNCH1 port/pin select 0x53C read-write 0x00000000 0x000F0003 PORT ASYNCH1 port select register 0 2 read-write PIN ASYNCH1 pin select register 16 4 read-write PRS0_ASYNCH2ROUTE ASYNCH2 port/pin select 0x540 read-write 0x00000000 0x000F0003 PORT ASYNCH2 port select register 0 2 read-write PIN ASYNCH2 pin select register 16 4 read-write PRS0_ASYNCH3ROUTE ASYNCH3 port/pin select 0x544 read-write 0x00000000 0x000F0003 PORT ASYNCH3 port select register 0 2 read-write PIN ASYNCH3 pin select register 16 4 read-write PRS0_ASYNCH4ROUTE ASYNCH4 port/pin select 0x548 read-write 0x00000000 0x000F0003 PORT ASYNCH4 port select register 0 2 read-write PIN ASYNCH4 pin select register 16 4 read-write PRS0_ASYNCH5ROUTE ASYNCH5 port/pin select 0x54C read-write 0x00000000 0x000F0003 PORT ASYNCH5 port select register 0 2 read-write PIN ASYNCH5 pin select register 16 4 read-write PRS0_ASYNCH6ROUTE ASYNCH6 port/pin select 0x550 read-write 0x00000000 0x000F0003 PORT ASYNCH6 port select register 0 2 read-write PIN ASYNCH6 pin select register 16 4 read-write PRS0_ASYNCH7ROUTE ASYNCH7 port/pin select 0x554 read-write 0x00000000 0x000F0003 PORT ASYNCH7 port select register 0 2 read-write PIN ASYNCH7 pin select register 16 4 read-write PRS0_ASYNCH8ROUTE ASYNCH8 port/pin select 0x558 read-write 0x00000000 0x000F0003 PORT ASYNCH8 port select register 0 2 read-write PIN ASYNCH8 pin select register 16 4 read-write PRS0_ASYNCH9ROUTE ASYNCH9 port/pin select 0x55C read-write 0x00000000 0x000F0003 PORT ASYNCH9 port select register 0 2 read-write PIN ASYNCH9 pin select register 16 4 read-write PRS0_ASYNCH10ROUTE ASYNCH10 port/pin select 0x560 read-write 0x00000000 0x000F0003 PORT ASYNCH10 port select register 0 2 read-write PIN ASYNCH10 pin select register 16 4 read-write PRS0_ASYNCH11ROUTE ASYNCH11 port/pin select 0x564 read-write 0x00000000 0x000F0003 PORT ASYNCH11 port select register 0 2 read-write PIN ASYNCH11 pin select register 16 4 read-write PRS0_SYNCH0ROUTE SYNCH0 port/pin select 0x568 read-write 0x00000000 0x000F0003 PORT SYNCH0 port select register 0 2 read-write PIN SYNCH0 pin select register 16 4 read-write PRS0_SYNCH1ROUTE SYNCH1 port/pin select 0x56C read-write 0x00000000 0x000F0003 PORT SYNCH1 port select register 0 2 read-write PIN SYNCH1 pin select register 16 4 read-write PRS0_SYNCH2ROUTE SYNCH2 port/pin select 0x570 read-write 0x00000000 0x000F0003 PORT SYNCH2 port select register 0 2 read-write PIN SYNCH2 pin select register 16 4 read-write PRS0_SYNCH3ROUTE SYNCH3 port/pin select 0x574 read-write 0x00000000 0x000F0003 PORT SYNCH3 port select register 0 2 read-write PIN SYNCH3 pin select register 16 4 read-write TIMER0_ROUTEEN TIMER0 pin enable 0x57C read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER0_CC0ROUTE CC0 port/pin select 0x580 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER0_CC1ROUTE CC1 port/pin select 0x584 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER0_CC2ROUTE CC2 port/pin select 0x588 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER0_CDTI0ROUTE CDTI0 port/pin select 0x58C read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER0_CDTI1ROUTE CDTI1 port/pin select 0x590 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER0_CDTI2ROUTE CDTI2 port/pin select 0x594 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write TIMER1_ROUTEEN TIMER1 pin enable 0x59C read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER1_CC0ROUTE CC0 port/pin select 0x5A0 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER1_CC1ROUTE CC1 port/pin select 0x5A4 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER1_CC2ROUTE CC2 port/pin select 0x5A8 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER1_CDTI0ROUTE CDTI0 port/pin select 0x5AC read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER1_CDTI1ROUTE CDTI1 port/pin select 0x5B0 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER1_CDTI2ROUTE CDTI2 port/pin select 0x5B4 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write TIMER2_ROUTEEN TIMER2 pin enable 0x5BC read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER2_CC0ROUTE CC0 port/pin select 0x5C0 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER2_CC1ROUTE CC1 port/pin select 0x5C4 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER2_CC2ROUTE CC2 port/pin select 0x5C8 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER2_CDTI0ROUTE CDTI0 port/pin select 0x5CC read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER2_CDTI1ROUTE CDTI1 port/pin select 0x5D0 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER2_CDTI2ROUTE CDTI2 port/pin select 0x5D4 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write TIMER3_ROUTEEN TIMER3 pin enable 0x5DC read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER3_CC0ROUTE CC0 port/pin select 0x5E0 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER3_CC1ROUTE CC1 port/pin select 0x5E4 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER3_CC2ROUTE CC2 port/pin select 0x5E8 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER3_CDTI0ROUTE CDTI0 port/pin select 0x5EC read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER3_CDTI1ROUTE CDTI1 port/pin select 0x5F0 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER3_CDTI2ROUTE CDTI2 port/pin select 0x5F4 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write TIMER4_ROUTEEN TIMER4 pin enable 0x5FC read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER4_CC0ROUTE CC0 port/pin select 0x600 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER4_CC1ROUTE CC1 port/pin select 0x604 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER4_CC2ROUTE CC2 port/pin select 0x608 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER4_CDTI0ROUTE CDTI0 port/pin select 0x60C read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER4_CDTI1ROUTE CDTI1 port/pin select 0x610 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER4_CDTI2ROUTE CDTI2 port/pin select 0x614 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write USART0_ROUTEEN USART0 pin enable 0x61C read-write 0x00000000 0x0000001F CSPEN CS pin enable control bit 0 1 read-write RTSPEN RTS pin enable control bit 1 1 read-write RXPEN RX pin enable control bit 2 1 read-write CLKPEN SCLK pin enable control bit 3 1 read-write TXPEN TX pin enable control bit 4 1 read-write USART0_CSROUTE CS port/pin select 0x620 read-write 0x00000000 0x000F0003 PORT CS port select register 0 2 read-write PIN CS pin select register 16 4 read-write USART0_CTSROUTE CTS port/pin select 0x624 read-write 0x00000000 0x000F0003 PORT CTS port select register 0 2 read-write PIN CTS pin select register 16 4 read-write USART0_RTSROUTE RTS port/pin select 0x628 read-write 0x00000000 0x000F0003 PORT RTS port select register 0 2 read-write PIN RTS pin select register 16 4 read-write USART0_RXROUTE RX port/pin select 0x62C read-write 0x00000000 0x000F0003 PORT RX port select register 0 2 read-write PIN RX pin select register 16 4 read-write USART0_CLKROUTE SCLK port/pin select 0x630 read-write 0x00000000 0x000F0003 PORT SCLK port select register 0 2 read-write PIN SCLK pin select register 16 4 read-write USART0_TXROUTE TX port/pin select 0x634 read-write 0x00000000 0x000F0003 PORT TX port select register 0 2 read-write PIN TX pin select register 16 4 read-write USART1_ROUTEEN USART1 pin enable 0x63C read-write 0x00000000 0x0000001F CSPEN CS pin enable control bit 0 1 read-write RTSPEN RTS pin enable control bit 1 1 read-write RXPEN RX pin enable control bit 2 1 read-write CLKPEN SCLK pin enable control bit 3 1 read-write TXPEN TX pin enable control bit 4 1 read-write USART1_CSROUTE CS port/pin select 0x640 read-write 0x00000000 0x000F0003 PORT CS port select register 0 2 read-write PIN CS pin select register 16 4 read-write USART1_CTSROUTE CTS port/pin select 0x644 read-write 0x00000000 0x000F0003 PORT CTS port select register 0 2 read-write PIN CTS pin select register 16 4 read-write USART1_RTSROUTE RTS port/pin select 0x648 read-write 0x00000000 0x000F0003 PORT RTS port select register 0 2 read-write PIN RTS pin select register 16 4 read-write USART1_RXROUTE RX port/pin select 0x64C read-write 0x00000000 0x000F0003 PORT RX port select register 0 2 read-write PIN RX pin select register 16 4 read-write USART1_CLKROUTE SCLK port/pin select 0x650 read-write 0x00000000 0x000F0003 PORT SCLK port select register 0 2 read-write PIN SCLK pin select register 16 4 read-write USART1_TXROUTE TX port/pin select 0x654 read-write 0x00000000 0x000F0003 PORT TX port select register 0 2 read-write PIN TX pin select register 16 4 read-write LDMA_NS 0 LDMA_NS Registers 0x50040000 0x00000000 0x00001000 registers LDMA 21 IPVERSION No Description 0x000 read-only 0x00000000 0x000000FF IPVERSION IPVERSION 0 8 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN LDMA module enable and disable register 0 1 read-write CTRL No Description 0x008 read-write 0x1E000000 0x9F000000 NUMFIXED Number of Fixed Priority Channels 24 5 read-write CORERST Reset DMA controller 31 1 read-write STATUS No Description 0x00C read-only 0x1F100000 0x1F1F1FFB ANYBUSY Any DMA Channel Busy 0 1 read-only ANYREQ Any DMA Channel Request Pending 1 1 read-only CHGRANT Granted Channel Number 3 5 read-only CHERROR Errant Channel Number 8 5 read-only FIFOLEVEL FIFO Level 16 5 read-only CHNUM Number of Channels 24 5 read-only SYNCSWSET No Description 0x010 write-only 0x00000000 0x000000FF SYNCSWSET DMA SYNC Software Trigger Set 0 8 write-only SYNCSWCLR No Description 0x014 write-only 0x00000000 0x000000FF SYNCSWCLR DMA SYNC Software Trigger Clear 0 8 write-only SYNCHWEN No Description 0x018 read-write 0x00000000 0x00FF00FF SYNCSETEN Hardware Sync Trigger Set Enable 0 8 read-write SYNCCLREN Hardware Sync Trigger Clear Enable 16 8 read-write SYNCHWSEL No Description 0x01C read-write 0x00000000 0x00FF00FF SYNCSETEDGE Hardware Sync Trigger Set Edge Select 0 8 read-write RISE Use rising edge detection 0 FALL Use falling edge detection 1 SYNCCLREDGE Hardware Sync Trigger Clear Edge Select 16 8 read-write RISE Use rising edge detection 0 FALL Use falling edge detection 1 SYNCSTATUS No Description 0x020 read-only 0x00000000 0x000000FF SYNCTRIG sync trig status 0 8 read-only CHEN No Description 0x024 write-only 0x00000000 0x000000FF CHEN Channel Enables 0 8 write-only CHDIS No Description 0x028 write-only 0x00000000 0x000000FF CHDIS DMA Channel disable 0 8 write-only CHSTATUS No Description 0x02C read-only 0x00000000 0x000000FF CHSTATUS DMA Channel Status 0 8 read-only CHBUSY No Description 0x030 read-only 0x00000000 0x000000FF BUSY Channels Busy 0 8 read-only CHDONE No Description 0x034 read-write 0x00000000 0x000000FF CHDONE0 DMA Channel Link done intr flag 0 1 read-write CHDONE1 DMA Channel Link done intr flag 1 1 read-write CHDONE2 DMA Channel Link done intr flag 2 1 read-write CHDONE3 DMA Channel Link done intr flag 3 1 read-write CHDONE4 DMA Channel Link done intr flag 4 1 read-write CHDONE5 DMA Channel Link done intr flag 5 1 read-write CHDONE6 DMA Channel Link done intr flag 6 1 read-write CHDONE7 DMA Channel Link done intr flag 7 1 read-write DBGHALT No Description 0x038 read-write 0x00000000 0x000000FF DBGHALT DMA Debug Halt 0 8 read-write SWREQ No Description 0x03C write-only 0x00000000 0x000000FF SWREQ Software Transfer Requests 0 8 write-only REQDIS No Description 0x040 read-write 0x00000000 0x000000FF REQDIS DMA Request Disables 0 8 read-write REQPEND No Description 0x044 read-only 0x00000000 0x000000FF REQPEND DMA Requests Pending 0 8 read-only LINKLOAD No Description 0x048 write-only 0x00000000 0x000000FF LINKLOAD DMA Link Loads 0 8 write-only REQCLEAR No Description 0x04C write-only 0x00000000 0x000000FF REQCLEAR DMA Request Clear 0 8 write-only IF No Description 0x050 read-write 0x00000000 0x800000FF DONE0 DMA Structure Operation Done 0 1 read-write DONE1 DMA Structure Operation Done 1 1 read-write DONE2 DMA Structure Operation Done 2 1 read-write DONE3 DMA Structure Operation Done 3 1 read-write DONE4 DMA Structure Operation Done 4 1 read-write DONE5 DMA Structure Operation Done 5 1 read-write DONE6 DMA Structure Operation Done 6 1 read-write DONE7 DMA Structure Operation Done 7 1 read-write ERROR Error Flag 31 1 read-write IEN No Description 0x054 read-write 0x00000000 0x800000FF CHDONE Enable or disable the done interrupt 0 8 read-write ERROR Enable or disable the error interrupt 31 1 read-write CH0_CFG No Description 0x05C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH0_LOOP No Description 0x060 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH0_CTRL No Description 0x064 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH0_SRC No Description 0x068 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH0_DST No Description 0x06C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH0_LINK No Description 0x070 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH1_CFG No Description 0x08C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH1_LOOP No Description 0x090 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH1_CTRL No Description 0x094 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH1_SRC No Description 0x098 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH1_DST No Description 0x09C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH1_LINK No Description 0x0A0 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH2_CFG No Description 0x0BC read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH2_LOOP No Description 0x0C0 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH2_CTRL No Description 0x0C4 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH2_SRC No Description 0x0C8 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH2_DST No Description 0x0CC read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH2_LINK No Description 0x0D0 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH3_CFG No Description 0x0EC read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH3_LOOP No Description 0x0F0 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH3_CTRL No Description 0x0F4 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH3_SRC No Description 0x0F8 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH3_DST No Description 0x0FC read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH3_LINK No Description 0x100 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH4_CFG No Description 0x11C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH4_LOOP No Description 0x120 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH4_CTRL No Description 0x124 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH4_SRC No Description 0x128 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH4_DST No Description 0x12C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH4_LINK No Description 0x130 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH5_CFG No Description 0x14C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH5_LOOP No Description 0x150 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH5_CTRL No Description 0x154 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH5_SRC No Description 0x158 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH5_DST No Description 0x15C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH5_LINK No Description 0x160 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH6_CFG No Description 0x17C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH6_LOOP No Description 0x180 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH6_CTRL No Description 0x184 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH6_SRC No Description 0x188 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH6_DST No Description 0x18C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH6_LINK No Description 0x190 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH7_CFG No Description 0x1AC read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH7_LOOP No Description 0x1B0 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH7_CTRL No Description 0x1B4 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH7_SRC No Description 0x1B8 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH7_DST No Description 0x1BC read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH7_LINK No Description 0x1C0 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LDMAXBAR_NS 1 LDMAXBAR_NS Registers 0x50044000 0x00000000 0x00001000 registers CH0_REQSEL No Description 0x000 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH1_REQSEL No Description 0x004 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH2_REQSEL No Description 0x008 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH3_REQSEL No Description 0x00C read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH4_REQSEL No Description 0x010 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH5_REQSEL No Description 0x014 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH6_REQSEL No Description 0x018 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH7_REQSEL No Description 0x01C read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write TIMER0_NS 0 TIMER0_NS Registers 0x50048000 0x00000000 0x00001000 registers TIMER0 7 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 RETIMESEL PWM output retime select 12 1 read-write ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0xFFFFFFFF TOP Counter Top Value 0 32 read-write TOPB No Description 0x020 read-write 0x00000000 0xFFFFFFFF TOPB Counter Top Buffer Register 0 32 read-write CNT No Description 0x024 read-write 0x00000000 0xFFFFFFFF CNT Counter Value 0 32 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0xFFFFFFFF OCB Output Compare Value Buffer 0 32 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0xFFFFFFFF ICF Input Capture FIFO 0 32 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0xFFFFFFFF ICOF Input Capture FIFO Overflow 0 32 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0xFFFFFFFF OCB Output Compare Value Buffer 0 32 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0xFFFFFFFF ICF Input Capture FIFO 0 32 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0xFFFFFFFF ICOF Input Capture FIFO Overflow 0 32 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0xFFFFFFFF OCB Output Compare Value Buffer 0 32 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0xFFFFFFFF ICF Input Capture FIFO 0 32 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0xFFFFFFFF ICOF Input Capture FIFO Overflow 0 32 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 TIMER1_NS 0 TIMER1_NS Registers 0x5004C000 0x00000000 0x00001000 registers TIMER1 8 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 RETIMESEL PWM output retime select 12 1 read-write ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0x0000FFFF TOP Counter Top Value 0 16 read-write TOPB No Description 0x020 read-write 0x00000000 0x0000FFFF TOPB Counter Top Buffer Register 0 16 read-write CNT No Description 0x024 read-write 0x00000000 0x0000FFFF CNT Counter Value 0 16 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 TIMER2_NS 0 TIMER2_NS Registers 0x50050000 0x00000000 0x00001000 registers TIMER2 9 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 RETIMESEL PWM output retime select 12 1 read-write ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0x0000FFFF TOP Counter Top Value 0 16 read-write TOPB No Description 0x020 read-write 0x00000000 0x0000FFFF TOPB Counter Top Buffer Register 0 16 read-write CNT No Description 0x024 read-write 0x00000000 0x0000FFFF CNT Counter Value 0 16 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 TIMER3_NS 0 TIMER3_NS Registers 0x50054000 0x00000000 0x00001000 registers TIMER3 10 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 RETIMESEL PWM output retime select 12 1 read-write ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0x0000FFFF TOP Counter Top Value 0 16 read-write TOPB No Description 0x020 read-write 0x00000000 0x0000FFFF TOPB Counter Top Buffer Register 0 16 read-write CNT No Description 0x024 read-write 0x00000000 0x0000FFFF CNT Counter Value 0 16 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 TIMER4_NS 0 TIMER4_NS Registers 0x50058000 0x00000000 0x00001000 registers TIMER4 11 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 RETIMESEL PWM output retime select 12 1 read-write ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0x0000FFFF TOP Counter Top Value 0 16 read-write TOPB No Description 0x020 read-write 0x00000000 0x0000FFFF TOPB Counter Top Buffer Register 0 16 read-write CNT No Description 0x024 read-write 0x00000000 0x0000FFFF CNT Counter Value 0 16 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 USART0_NS 0 USART0_NS Registers 0x5005C000 0x00000000 0x00001000 registers USART0_RX 13 USART0_TX 14 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IPVERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN USART Enable 0 1 read-write CTRL No Description 0x008 read-write 0x00000000 0xF3FFFF7F SYNC USART Synchronous Mode 0 1 read-write DISABLE The USART operates in asynchronous mode 0 ENABLE The USART operates in synchronous mode 1 LOOPBK Loopback Enable 1 1 read-write DISABLE The receiver is connected to and receives data from U(S)n_RX 0 ENABLE The receiver is connected to and receives data from U(S)n_TX 1 CCEN Collision Check Enable 2 1 read-write DISABLE Collision check is disabled 0 ENABLE Collision check is enabled. The receiver must be enabled for the check to be performed 1 MPM Multi-Processor Mode 3 1 read-write DISABLE The 9th bit of incoming frames has no special function 0 ENABLE An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set 1 MPAB Multi-Processor Address-Bit 4 1 read-write OVS Oversampling 5 2 read-write X16 Regular UART mode with 16X oversampling in asynchronous mode 0 X8 Double speed with 8X oversampling in asynchronous mode 1 X6 6X oversampling in asynchronous mode 2 X4 Quadruple speed with 4X oversampling in asynchronous mode 3 CLKPOL Clock Polarity 8 1 read-write IDLELOW The bus clock used in synchronous mode has a low base value 0 IDLEHIGH The bus clock used in synchronous mode has a high base value 1 CLKPHA Clock Edge For Setup/Sample 9 1 read-write SAMPLELEADING Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode 0 SAMPLETRAILING Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode 1 MSBF Most Significant Bit First 10 1 read-write DISABLE Data is sent with the least significant bit first 0 ENABLE Data is sent with the most significant bit first 1 CSMA Action On Chip Select In Main Mode 11 1 read-write NOACTION No action taken 0 GOTOSLAVEMODE Go to secondary mode 1 TXBIL TX Buffer Interrupt Level 12 1 read-write EMPTY TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALFFULL TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full. 1 RXINV Receiver Input Invert 13 1 read-write DISABLE Input is passed directly to the receiver 0 ENABLE Input is inverted before it is passed to the receiver 1 TXINV Transmitter output Invert 14 1 read-write DISABLE Output from the transmitter is passed unchanged to U(S)n_TX 0 ENABLE Output from the transmitter is inverted before it is passed to U(S)n_TX 1 CSINV Chip Select Invert 15 1 read-write DISABLE Chip select is active low 0 ENABLE Chip select is active high 1 AUTOCS Automatic Chip Select 16 1 read-write AUTOTRI Automatic TX Tristate 17 1 read-write DISABLE The output on U(S)n_TX when the transmitter is idle is defined by TXINV 0 ENABLE U(S)n_TX is tristated whenever the transmitter is idle 1 SCMODE SmartCard Mode 18 1 read-write SCRETRANS SmartCard Retransmit 19 1 read-write SKIPPERRF Skip Parity Error Frames 20 1 read-write BIT8DV Bit 8 Default Value 21 1 read-write ERRSDMA Halt DMA On Error 22 1 read-write DISABLE Framing and parity errors have no effect on DMA requests from the USART 0 ENABLE DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set 1 ERRSRX Disable RX On Error 23 1 read-write DISABLE Framing and parity errors have no effect on receiver 0 ENABLE Framing and parity errors disable the receiver 1 ERRSTX Disable TX On Error 24 1 read-write DISABLE Received framing and parity errors have no effect on transmitter 0 ENABLE Received framing and parity errors disable the transmitter 1 SSSEARLY Synchronous Secondary Setup Early 25 1 read-write BYTESWAP Byteswap In Double Accesses 28 1 read-write DISABLE Normal byte order 0 ENABLE Byte order swapped 1 AUTOTX Always Transmit When RX Not Full 29 1 read-write MVDIS Majority Vote Disable 30 1 read-write SMSDELAY Synchronous Main Sample Delay 31 1 read-write FRAME No Description 0x00C read-write 0x00001005 0x0000330F DATABITS Data-Bit Mode 0 4 read-write FOUR Each frame contains 4 data bits 1 FIVE Each frame contains 5 data bits 2 SIX Each frame contains 6 data bits 3 SEVEN Each frame contains 7 data bits 4 EIGHT Each frame contains 8 data bits 5 NINE Each frame contains 9 data bits 6 TEN Each frame contains 10 data bits 7 ELEVEN Each frame contains 11 data bits 8 TWELVE Each frame contains 12 data bits 9 THIRTEEN Each frame contains 13 data bits 10 FOURTEEN Each frame contains 14 data bits 11 FIFTEEN Each frame contains 15 data bits 12 SIXTEEN Each frame contains 16 data bits 13 PARITY Parity-Bit Mode 8 2 read-write NONE Parity bits are not used 0 EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. 2 ODD Odd parity is used. Parity bits are automatically generated and checked by hardware. 3 STOPBITS Stop-Bit Mode 12 2 read-write HALF The transmitter generates a half stop bit. Stop-bits are not verified by receiver 0 ONE One stop bit is generated and verified 1 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies the first stop bit 2 TWO The transmitter generates two stop bits. The receiver checks the first stop-bit only 3 TRIGCTRL No Description 0x010 read-write 0x00000000 0x00001FF0 RXTEN Receive Trigger Enable 4 1 read-write TXTEN Transmit Trigger Enable 5 1 read-write AUTOTXTEN AUTOTX Trigger Enable 6 1 read-write TXARX0EN Enable Transmit Trigger after RX End of 7 1 read-write TXARX1EN Enable Transmit Trigger after RX End of 8 1 read-write TXARX2EN Enable Transmit Trigger after RX End of 9 1 read-write RXATX0EN Enable Receive Trigger after TX end of f 10 1 read-write RXATX1EN Enable Receive Trigger after TX end of f 11 1 read-write RXATX2EN Enable Receive Trigger after TX end of f 12 1 read-write CMD No Description 0x014 write-only 0x00000000 0x00000FFF RXEN Receiver Enable 0 1 write-only RXDIS Receiver Disable 1 1 write-only TXEN Transmitter Enable 2 1 write-only TXDIS Transmitter Disable 3 1 write-only MASTEREN Main Mode Enable 4 1 write-only MASTERDIS Main Mode Disable 5 1 write-only RXBLOCKEN Receiver Block Enable 6 1 write-only RXBLOCKDIS Receiver Block Disable 7 1 write-only TXTRIEN Transmitter Tristate Enable 8 1 write-only TXTRIDIS Transmitter Tristate Disable 9 1 write-only CLEARTX Clear TX 10 1 write-only CLEARRX Clear RX 11 1 write-only STATUS No Description 0x018 read-only 0x00002040 0x00037FFF RXENS Receiver Enable Status 0 1 read-only TXENS Transmitter Enable Status 1 1 read-only MASTER SPI Main Mode 2 1 read-only RXBLOCK Block Incoming Data 3 1 read-only TXTRI Transmitter Tristated 4 1 read-only TXC TX Complete 5 1 read-only TXBL TX Buffer Level 6 1 read-only RXDATAV RX Data Valid 7 1 read-only RXFULL RX FIFO Full 8 1 read-only TXBDRIGHT TX Buffer Expects Double Right Data 9 1 read-only TXBSRIGHT TX Buffer Expects Single Right Data 10 1 read-only RXDATAVRIGHT RX Data Right 11 1 read-only RXFULLRIGHT RX Full of Right Data 12 1 read-only TXIDLE TX Idle 13 1 read-only TIMERRESTARTED The USART Timer restarted itself 14 1 read-only TXBUFCNT TX Buffer Count 16 2 read-only CLKDIV No Description 0x01C read-write 0x00000000 0x807FFFF8 DIV Fractional Clock Divider 3 20 read-write AUTOBAUDEN AUTOBAUD detection enable 31 1 read-write RXDATAX No Description 0x020 read-only 0x00000000 0x0000C1FF RXDATA RX Data 0 9 read-only PERR Data Parity Error 14 1 read-only FERR Data Framing Error 15 1 read-only RXDATA No Description 0x024 read-only 0x00000000 0x000000FF RXDATA RX Data 0 8 read-only RXDOUBLEX No Description 0x028 read-only 0x00000000 0xC1FFC1FF RXDATA0 RX Data 0 0 9 read-only PERR0 Data Parity Error 0 14 1 read-only FERR0 Data Framing Error 0 15 1 read-only RXDATA1 RX Data 1 16 9 read-only PERR1 Data Parity Error 1 30 1 read-only FERR1 Data Framing Error 1 31 1 read-only RXDOUBLE No Description 0x02C read-only 0x00000000 0x0000FFFF RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDATAXP No Description 0x030 read-only 0x00000000 0x0000C1FF RXDATAP RX Data Peek 0 9 read-only PERRP Data Parity Error Peek 14 1 read-only FERRP Data Framing Error Peek 15 1 read-only RXDOUBLEXP No Description 0x034 read-only 0x00000000 0xC1FFC1FF RXDATAP0 RX Data 0 Peek 0 9 read-only PERRP0 Data Parity Error 0 Peek 14 1 read-only FERRP0 Data Framing Error 0 Peek 15 1 read-only RXDATAP1 RX Data 1 Peek 16 9 read-only PERRP1 Data Parity Error 1 Peek 30 1 read-only FERRP1 Data Framing Error 1 Peek 31 1 read-only TXDATAX No Description 0x038 write-only 0x00000000 0x0000F9FF TXDATAX TX Data 0 9 write-only UBRXAT Unblock RX After Transmission 11 1 write-only TXTRIAT Set TXTRI After Transmission 12 1 write-only TXBREAK Transmit Data As Break 13 1 write-only TXDISAT Clear TXEN After Transmission 14 1 write-only RXENAT Enable RX After Transmission 15 1 write-only TXDATA No Description 0x03C write-only 0x00000000 0x000000FF TXDATA TX Data 0 8 write-only TXDOUBLEX No Description 0x040 write-only 0x00000000 0xF9FFF9FF TXDATA0 TX Data 0 9 write-only UBRXAT0 Unblock RX After Transmission 11 1 write-only TXTRIAT0 Set TXTRI After Transmission 12 1 write-only TXBREAK0 Transmit Data As Break 13 1 write-only TXDISAT0 Clear TXEN After Transmission 14 1 write-only RXENAT0 Enable RX After Transmission 15 1 write-only TXDATA1 TX Data 16 9 write-only UBRXAT1 Unblock RX After Transmission 27 1 write-only TXTRIAT1 Set TXTRI After Transmission 28 1 write-only TXBREAK1 Transmit Data As Break 29 1 write-only TXDISAT1 Clear TXEN After Transmission 30 1 write-only RXENAT1 Enable RX After Transmission 31 1 write-only TXDOUBLE No Description 0x044 write-only 0x00000000 0x0000FFFF TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only IF No Description 0x048 read-write 0x00000002 0x0001FFFF TXC TX Complete Interrupt Flag 0 1 read-write TXBL TX Buffer Level Interrupt Flag 1 1 read-write RXDATAV RX Data Valid Interrupt Flag 2 1 read-write RXFULL RX Buffer Full Interrupt Flag 3 1 read-write RXOF RX Overflow Interrupt Flag 4 1 read-write RXUF RX Underflow Interrupt Flag 5 1 read-write TXOF TX Overflow Interrupt Flag 6 1 read-write TXUF TX Underflow Interrupt Flag 7 1 read-write PERR Parity Error Interrupt Flag 8 1 read-write FERR Framing Error Interrupt Flag 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write SSM Chip-Select In Main Mode Interrupt Flag 11 1 read-write CCF Collision Check Fail Interrupt Flag 12 1 read-write TXIDLE TX Idle Interrupt Flag 13 1 read-write TCMP0 Timer comparator 0 Interrupt Flag 14 1 read-write TCMP1 Timer comparator 1 Interrupt Flag 15 1 read-write TCMP2 Timer comparator 2 Interrupt Flag 16 1 read-write IEN No Description 0x04C read-write 0x00000000 0x0001FFFF TXC TX Complete Interrupt Enable 0 1 read-write TXBL TX Buffer Level Interrupt Enable 1 1 read-write RXDATAV RX Data Valid Interrupt Enable 2 1 read-write RXFULL RX Buffer Full Interrupt Enable 3 1 read-write RXOF RX Overflow Interrupt Enable 4 1 read-write RXUF RX Underflow Interrupt Enable 5 1 read-write TXOF TX Overflow Interrupt Enable 6 1 read-write TXUF TX Underflow Interrupt Enable 7 1 read-write PERR Parity Error Interrupt Enable 8 1 read-write FERR Framing Error Interrupt Enable 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write SSM Chip-Select In Main Mode Interrupt Flag 11 1 read-write CCF Collision Check Fail Interrupt Enable 12 1 read-write TXIDLE TX Idle Interrupt Enable 13 1 read-write TCMP0 Timer comparator 0 Interrupt Enable 14 1 read-write TCMP1 Timer comparator 1 Interrupt Enable 15 1 read-write TCMP2 Timer comparator 2 Interrupt Enable 16 1 read-write IRCTRL No Description 0x050 read-write 0x00000000 0x0000008F IREN Enable IrDA Module 0 1 read-write IRPW IrDA TX Pulse Width 1 2 read-write ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 0 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 2 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 3 IRFILT IrDA RX Filter 3 1 read-write DISABLE No filter enabled 0 ENABLE Filter enabled. IrDA pulse must be high for at least 5 consecutive clock cycles to be detected 1 I2SCTRL No Description 0x054 read-write 0x00000000 0x0000071F EN Enable I2S Mode 0 1 read-write MONO Stero or Mono 1 1 read-write JUSTIFY Justification of I2S Data 2 1 read-write LEFT Data is left-justified 0 RIGHT Data is right-justified 1 DMASPLIT Separate DMA Request For Left/Right Data 3 1 read-write DELAY Delay on I2S data 4 1 read-write FORMAT I2S Word Format 8 3 read-write W32D32 32-bit word, 32-bit data 0 W32D24M 32-bit word, 32-bit data with 8 lsb masked 1 W32D24 32-bit word, 24-bit data 2 W32D16 32-bit word, 16-bit data 3 W32D8 32-bit word, 8-bit data 4 W16D16 16-bit word, 16-bit data 5 W16D8 16-bit word, 8-bit data 6 W8D8 8-bit word, 8-bit data 7 TIMING No Description 0x058 read-write 0x00000000 0x77770000 TXDELAY TX frame start delay 16 3 read-write DISABLE Disable - TXDELAY in USARTn_CTRL can be used for legacy 0 ONE Start of transmission is delayed for 1 baud-times 1 TWO Start of transmission is delayed for 2 baud-times 2 THREE Start of transmission is delayed for 3 baud-times 3 SEVEN Start of transmission is delayed for 7 baud-times 4 TCMP0 Start of transmission is delayed for TCMPVAL0 baud-times 5 TCMP1 Start of transmission is delayed for TCMPVAL1 baud-times 6 TCMP2 Start of transmission is delayed for TCMPVAL2 baud-times 7 CSSETUP Chip Select Setup 20 3 read-write ZERO CS is not asserted before start of transmission 0 ONE CS is asserted for 1 baud-times before start of transmission 1 TWO CS is asserted for 2 baud-times before start of transmission 2 THREE CS is asserted for 3 baud-times before start of transmission 3 SEVEN CS is asserted for 7 baud-times before start of transmission 4 TCMP0 CS is asserted before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted before the start of transmission for TCMPVAL2 baud-times 7 ICS Inter-character spacing 24 3 read-write ZERO There is no space between charcters 0 ONE Create a space of 1 baud-times before start of transmission 1 TWO Create a space of 2 baud-times before start of transmission 2 THREE Create a space of 3 baud-times before start of transmission 3 SEVEN Create a space of 7 baud-times before start of transmission 4 TCMP0 Create a space of before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 Create a space of before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 Create a space of before the start of transmission for TCMPVAL2 baud-times 7 CSHOLD Chip Select Hold 28 3 read-write ZERO Disable CS being asserted after the end of transmission 0 ONE CS is asserted for 1 baud-times after the end of transmission 1 TWO CS is asserted for 2 baud-times after the end of transmission 2 THREE CS is asserted for 3 baud-times after the end of transmission 3 SEVEN CS is asserted for 7 baud-times after the end of transmission 4 TCMP0 CS is asserted after the end of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted after the end of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted after the end of transmission for TCMPVAL2 baud-times 7 CTRLX No Description 0x05C read-write 0x00000000 0x8000808F DBGHALT Debug halt 0 1 read-write DISABLE Continue to transmit until TX buffer is empty 0 ENABLE Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock; otherwise, each single step could transmit multiple frames instead of just transmitting one frame. 1 CTSINV CTS Pin Inversion 1 1 read-write DISABLE The USn_CTS pin is low true 0 ENABLE The USn_CTS pin is high true 1 CTSEN CTS Function enabled 2 1 read-write DISABLE Ingore CTS 0 ENABLE Stop transmitting when CTS is negated 1 RTSINV RTS Pin Inversion 3 1 read-write DISABLE The USn_RTS pin is low true 0 ENABLE The USn_RTS pin is high true 1 RXPRSEN PRS RX Enable 7 1 read-write CLKPRSEN PRS CLK Enable 15 1 read-write TIMECMP0 No Description 0x060 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 0. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 0 is disabled 0 TXEOF Comparator 0 and timer are started at TX end of frame 1 TXC Comparator 0 and timer are started at TX Complete 2 RXACT Comparator 0 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 0 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 0 20 3 read-write TCMP0 Comparator 0 is disabled when the counter equals TCMPVAL and triggers a TCMP0 event 0 TXST Comparator 0 is disabled at TX start TX Engine 1 RXACT Comparator 0 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 0 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP0 24 1 read-write DISABLE Disable the timer restarting on TCMP0 0 ENABLE Enable the timer restarting on TCMP0 1 TIMECMP1 No Description 0x064 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 1. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 1 is disabled 0 TXEOF Comparator 1 and timer are started at TX end of frame 1 TXC Comparator 1 and timer are started at TX Complete 2 RXACT Comparator 1 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 1 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 1 20 3 read-write TCMP1 Comparator 1 is disabled when the counter equals TCMPVAL and triggers a TCMP1 event 0 TXST Comparator 1 is disabled at TX start TX Engine 1 RXACT Comparator 1 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 1 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP1 24 1 read-write DISABLE Disable the timer restarting on TCMP1 0 ENABLE Enable the timer restarting on TCMP1 1 TIMECMP2 No Description 0x068 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 2. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 2 is disabled 0 TXEOF Comparator 2 and timer are started at TX end of frame 1 TXC Comparator 2 and timer are started at TX Complete 2 RXACT Comparator 2 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 2 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 2 20 3 read-write TCMP2 Comparator 2 is disabled when the counter equals TCMPVAL and triggers a TCMP2 event 0 TXST Comparator 2 is disabled at TX start TX Engine 1 RXACT Comparator 2 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 2 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP2 24 1 read-write DISABLE Disable the timer restarting on TCMP2 0 ENABLE Enable the timer restarting on TCMP2 1 USART1_NS 0 USART1_NS Registers 0x50060000 0x00000000 0x00001000 registers USART1_RX 15 USART1_TX 16 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IPVERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN USART Enable 0 1 read-write CTRL No Description 0x008 read-write 0x00000000 0xF3FFFF7F SYNC USART Synchronous Mode 0 1 read-write DISABLE The USART operates in asynchronous mode 0 ENABLE The USART operates in synchronous mode 1 LOOPBK Loopback Enable 1 1 read-write DISABLE The receiver is connected to and receives data from U(S)n_RX 0 ENABLE The receiver is connected to and receives data from U(S)n_TX 1 CCEN Collision Check Enable 2 1 read-write DISABLE Collision check is disabled 0 ENABLE Collision check is enabled. The receiver must be enabled for the check to be performed 1 MPM Multi-Processor Mode 3 1 read-write DISABLE The 9th bit of incoming frames has no special function 0 ENABLE An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set 1 MPAB Multi-Processor Address-Bit 4 1 read-write OVS Oversampling 5 2 read-write X16 Regular UART mode with 16X oversampling in asynchronous mode 0 X8 Double speed with 8X oversampling in asynchronous mode 1 X6 6X oversampling in asynchronous mode 2 X4 Quadruple speed with 4X oversampling in asynchronous mode 3 CLKPOL Clock Polarity 8 1 read-write IDLELOW The bus clock used in synchronous mode has a low base value 0 IDLEHIGH The bus clock used in synchronous mode has a high base value 1 CLKPHA Clock Edge For Setup/Sample 9 1 read-write SAMPLELEADING Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode 0 SAMPLETRAILING Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode 1 MSBF Most Significant Bit First 10 1 read-write DISABLE Data is sent with the least significant bit first 0 ENABLE Data is sent with the most significant bit first 1 CSMA Action On Chip Select In Main Mode 11 1 read-write NOACTION No action taken 0 GOTOSLAVEMODE Go to secondary mode 1 TXBIL TX Buffer Interrupt Level 12 1 read-write EMPTY TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALFFULL TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full. 1 RXINV Receiver Input Invert 13 1 read-write DISABLE Input is passed directly to the receiver 0 ENABLE Input is inverted before it is passed to the receiver 1 TXINV Transmitter output Invert 14 1 read-write DISABLE Output from the transmitter is passed unchanged to U(S)n_TX 0 ENABLE Output from the transmitter is inverted before it is passed to U(S)n_TX 1 CSINV Chip Select Invert 15 1 read-write DISABLE Chip select is active low 0 ENABLE Chip select is active high 1 AUTOCS Automatic Chip Select 16 1 read-write AUTOTRI Automatic TX Tristate 17 1 read-write DISABLE The output on U(S)n_TX when the transmitter is idle is defined by TXINV 0 ENABLE U(S)n_TX is tristated whenever the transmitter is idle 1 SCMODE SmartCard Mode 18 1 read-write SCRETRANS SmartCard Retransmit 19 1 read-write SKIPPERRF Skip Parity Error Frames 20 1 read-write BIT8DV Bit 8 Default Value 21 1 read-write ERRSDMA Halt DMA On Error 22 1 read-write DISABLE Framing and parity errors have no effect on DMA requests from the USART 0 ENABLE DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set 1 ERRSRX Disable RX On Error 23 1 read-write DISABLE Framing and parity errors have no effect on receiver 0 ENABLE Framing and parity errors disable the receiver 1 ERRSTX Disable TX On Error 24 1 read-write DISABLE Received framing and parity errors have no effect on transmitter 0 ENABLE Received framing and parity errors disable the transmitter 1 SSSEARLY Synchronous Secondary Setup Early 25 1 read-write BYTESWAP Byteswap In Double Accesses 28 1 read-write DISABLE Normal byte order 0 ENABLE Byte order swapped 1 AUTOTX Always Transmit When RX Not Full 29 1 read-write MVDIS Majority Vote Disable 30 1 read-write SMSDELAY Synchronous Main Sample Delay 31 1 read-write FRAME No Description 0x00C read-write 0x00001005 0x0000330F DATABITS Data-Bit Mode 0 4 read-write FOUR Each frame contains 4 data bits 1 FIVE Each frame contains 5 data bits 2 SIX Each frame contains 6 data bits 3 SEVEN Each frame contains 7 data bits 4 EIGHT Each frame contains 8 data bits 5 NINE Each frame contains 9 data bits 6 TEN Each frame contains 10 data bits 7 ELEVEN Each frame contains 11 data bits 8 TWELVE Each frame contains 12 data bits 9 THIRTEEN Each frame contains 13 data bits 10 FOURTEEN Each frame contains 14 data bits 11 FIFTEEN Each frame contains 15 data bits 12 SIXTEEN Each frame contains 16 data bits 13 PARITY Parity-Bit Mode 8 2 read-write NONE Parity bits are not used 0 EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. 2 ODD Odd parity is used. Parity bits are automatically generated and checked by hardware. 3 STOPBITS Stop-Bit Mode 12 2 read-write HALF The transmitter generates a half stop bit. Stop-bits are not verified by receiver 0 ONE One stop bit is generated and verified 1 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies the first stop bit 2 TWO The transmitter generates two stop bits. The receiver checks the first stop-bit only 3 TRIGCTRL No Description 0x010 read-write 0x00000000 0x00001FF0 RXTEN Receive Trigger Enable 4 1 read-write TXTEN Transmit Trigger Enable 5 1 read-write AUTOTXTEN AUTOTX Trigger Enable 6 1 read-write TXARX0EN Enable Transmit Trigger after RX End of 7 1 read-write TXARX1EN Enable Transmit Trigger after RX End of 8 1 read-write TXARX2EN Enable Transmit Trigger after RX End of 9 1 read-write RXATX0EN Enable Receive Trigger after TX end of f 10 1 read-write RXATX1EN Enable Receive Trigger after TX end of f 11 1 read-write RXATX2EN Enable Receive Trigger after TX end of f 12 1 read-write CMD No Description 0x014 write-only 0x00000000 0x00000FFF RXEN Receiver Enable 0 1 write-only RXDIS Receiver Disable 1 1 write-only TXEN Transmitter Enable 2 1 write-only TXDIS Transmitter Disable 3 1 write-only MASTEREN Main Mode Enable 4 1 write-only MASTERDIS Main Mode Disable 5 1 write-only RXBLOCKEN Receiver Block Enable 6 1 write-only RXBLOCKDIS Receiver Block Disable 7 1 write-only TXTRIEN Transmitter Tristate Enable 8 1 write-only TXTRIDIS Transmitter Tristate Disable 9 1 write-only CLEARTX Clear TX 10 1 write-only CLEARRX Clear RX 11 1 write-only STATUS No Description 0x018 read-only 0x00002040 0x00037FFF RXENS Receiver Enable Status 0 1 read-only TXENS Transmitter Enable Status 1 1 read-only MASTER SPI Main Mode 2 1 read-only RXBLOCK Block Incoming Data 3 1 read-only TXTRI Transmitter Tristated 4 1 read-only TXC TX Complete 5 1 read-only TXBL TX Buffer Level 6 1 read-only RXDATAV RX Data Valid 7 1 read-only RXFULL RX FIFO Full 8 1 read-only TXBDRIGHT TX Buffer Expects Double Right Data 9 1 read-only TXBSRIGHT TX Buffer Expects Single Right Data 10 1 read-only RXDATAVRIGHT RX Data Right 11 1 read-only RXFULLRIGHT RX Full of Right Data 12 1 read-only TXIDLE TX Idle 13 1 read-only TIMERRESTARTED The USART Timer restarted itself 14 1 read-only TXBUFCNT TX Buffer Count 16 2 read-only CLKDIV No Description 0x01C read-write 0x00000000 0x807FFFF8 DIV Fractional Clock Divider 3 20 read-write AUTOBAUDEN AUTOBAUD detection enable 31 1 read-write RXDATAX No Description 0x020 read-only 0x00000000 0x0000C1FF RXDATA RX Data 0 9 read-only PERR Data Parity Error 14 1 read-only FERR Data Framing Error 15 1 read-only RXDATA No Description 0x024 read-only 0x00000000 0x000000FF RXDATA RX Data 0 8 read-only RXDOUBLEX No Description 0x028 read-only 0x00000000 0xC1FFC1FF RXDATA0 RX Data 0 0 9 read-only PERR0 Data Parity Error 0 14 1 read-only FERR0 Data Framing Error 0 15 1 read-only RXDATA1 RX Data 1 16 9 read-only PERR1 Data Parity Error 1 30 1 read-only FERR1 Data Framing Error 1 31 1 read-only RXDOUBLE No Description 0x02C read-only 0x00000000 0x0000FFFF RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDATAXP No Description 0x030 read-only 0x00000000 0x0000C1FF RXDATAP RX Data Peek 0 9 read-only PERRP Data Parity Error Peek 14 1 read-only FERRP Data Framing Error Peek 15 1 read-only RXDOUBLEXP No Description 0x034 read-only 0x00000000 0xC1FFC1FF RXDATAP0 RX Data 0 Peek 0 9 read-only PERRP0 Data Parity Error 0 Peek 14 1 read-only FERRP0 Data Framing Error 0 Peek 15 1 read-only RXDATAP1 RX Data 1 Peek 16 9 read-only PERRP1 Data Parity Error 1 Peek 30 1 read-only FERRP1 Data Framing Error 1 Peek 31 1 read-only TXDATAX No Description 0x038 write-only 0x00000000 0x0000F9FF TXDATAX TX Data 0 9 write-only UBRXAT Unblock RX After Transmission 11 1 write-only TXTRIAT Set TXTRI After Transmission 12 1 write-only TXBREAK Transmit Data As Break 13 1 write-only TXDISAT Clear TXEN After Transmission 14 1 write-only RXENAT Enable RX After Transmission 15 1 write-only TXDATA No Description 0x03C write-only 0x00000000 0x000000FF TXDATA TX Data 0 8 write-only TXDOUBLEX No Description 0x040 write-only 0x00000000 0xF9FFF9FF TXDATA0 TX Data 0 9 write-only UBRXAT0 Unblock RX After Transmission 11 1 write-only TXTRIAT0 Set TXTRI After Transmission 12 1 write-only TXBREAK0 Transmit Data As Break 13 1 write-only TXDISAT0 Clear TXEN After Transmission 14 1 write-only RXENAT0 Enable RX After Transmission 15 1 write-only TXDATA1 TX Data 16 9 write-only UBRXAT1 Unblock RX After Transmission 27 1 write-only TXTRIAT1 Set TXTRI After Transmission 28 1 write-only TXBREAK1 Transmit Data As Break 29 1 write-only TXDISAT1 Clear TXEN After Transmission 30 1 write-only RXENAT1 Enable RX After Transmission 31 1 write-only TXDOUBLE No Description 0x044 write-only 0x00000000 0x0000FFFF TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only IF No Description 0x048 read-write 0x00000002 0x0001FFFF TXC TX Complete Interrupt Flag 0 1 read-write TXBL TX Buffer Level Interrupt Flag 1 1 read-write RXDATAV RX Data Valid Interrupt Flag 2 1 read-write RXFULL RX Buffer Full Interrupt Flag 3 1 read-write RXOF RX Overflow Interrupt Flag 4 1 read-write RXUF RX Underflow Interrupt Flag 5 1 read-write TXOF TX Overflow Interrupt Flag 6 1 read-write TXUF TX Underflow Interrupt Flag 7 1 read-write PERR Parity Error Interrupt Flag 8 1 read-write FERR Framing Error Interrupt Flag 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write SSM Chip-Select In Main Mode Interrupt Flag 11 1 read-write CCF Collision Check Fail Interrupt Flag 12 1 read-write TXIDLE TX Idle Interrupt Flag 13 1 read-write TCMP0 Timer comparator 0 Interrupt Flag 14 1 read-write TCMP1 Timer comparator 1 Interrupt Flag 15 1 read-write TCMP2 Timer comparator 2 Interrupt Flag 16 1 read-write IEN No Description 0x04C read-write 0x00000000 0x0001FFFF TXC TX Complete Interrupt Enable 0 1 read-write TXBL TX Buffer Level Interrupt Enable 1 1 read-write RXDATAV RX Data Valid Interrupt Enable 2 1 read-write RXFULL RX Buffer Full Interrupt Enable 3 1 read-write RXOF RX Overflow Interrupt Enable 4 1 read-write RXUF RX Underflow Interrupt Enable 5 1 read-write TXOF TX Overflow Interrupt Enable 6 1 read-write TXUF TX Underflow Interrupt Enable 7 1 read-write PERR Parity Error Interrupt Enable 8 1 read-write FERR Framing Error Interrupt Enable 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write SSM Chip-Select In Main Mode Interrupt Flag 11 1 read-write CCF Collision Check Fail Interrupt Enable 12 1 read-write TXIDLE TX Idle Interrupt Enable 13 1 read-write TCMP0 Timer comparator 0 Interrupt Enable 14 1 read-write TCMP1 Timer comparator 1 Interrupt Enable 15 1 read-write TCMP2 Timer comparator 2 Interrupt Enable 16 1 read-write IRCTRL No Description 0x050 read-write 0x00000000 0x0000008F IREN Enable IrDA Module 0 1 read-write IRPW IrDA TX Pulse Width 1 2 read-write ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 0 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 2 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 3 IRFILT IrDA RX Filter 3 1 read-write DISABLE No filter enabled 0 ENABLE Filter enabled. IrDA pulse must be high for at least 5 consecutive clock cycles to be detected 1 I2SCTRL No Description 0x054 read-write 0x00000000 0x0000071F EN Enable I2S Mode 0 1 read-write MONO Stero or Mono 1 1 read-write JUSTIFY Justification of I2S Data 2 1 read-write LEFT Data is left-justified 0 RIGHT Data is right-justified 1 DMASPLIT Separate DMA Request For Left/Right Data 3 1 read-write DELAY Delay on I2S data 4 1 read-write FORMAT I2S Word Format 8 3 read-write W32D32 32-bit word, 32-bit data 0 W32D24M 32-bit word, 32-bit data with 8 lsb masked 1 W32D24 32-bit word, 24-bit data 2 W32D16 32-bit word, 16-bit data 3 W32D8 32-bit word, 8-bit data 4 W16D16 16-bit word, 16-bit data 5 W16D8 16-bit word, 8-bit data 6 W8D8 8-bit word, 8-bit data 7 TIMING No Description 0x058 read-write 0x00000000 0x77770000 TXDELAY TX frame start delay 16 3 read-write DISABLE Disable - TXDELAY in USARTn_CTRL can be used for legacy 0 ONE Start of transmission is delayed for 1 baud-times 1 TWO Start of transmission is delayed for 2 baud-times 2 THREE Start of transmission is delayed for 3 baud-times 3 SEVEN Start of transmission is delayed for 7 baud-times 4 TCMP0 Start of transmission is delayed for TCMPVAL0 baud-times 5 TCMP1 Start of transmission is delayed for TCMPVAL1 baud-times 6 TCMP2 Start of transmission is delayed for TCMPVAL2 baud-times 7 CSSETUP Chip Select Setup 20 3 read-write ZERO CS is not asserted before start of transmission 0 ONE CS is asserted for 1 baud-times before start of transmission 1 TWO CS is asserted for 2 baud-times before start of transmission 2 THREE CS is asserted for 3 baud-times before start of transmission 3 SEVEN CS is asserted for 7 baud-times before start of transmission 4 TCMP0 CS is asserted before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted before the start of transmission for TCMPVAL2 baud-times 7 ICS Inter-character spacing 24 3 read-write ZERO There is no space between charcters 0 ONE Create a space of 1 baud-times before start of transmission 1 TWO Create a space of 2 baud-times before start of transmission 2 THREE Create a space of 3 baud-times before start of transmission 3 SEVEN Create a space of 7 baud-times before start of transmission 4 TCMP0 Create a space of before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 Create a space of before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 Create a space of before the start of transmission for TCMPVAL2 baud-times 7 CSHOLD Chip Select Hold 28 3 read-write ZERO Disable CS being asserted after the end of transmission 0 ONE CS is asserted for 1 baud-times after the end of transmission 1 TWO CS is asserted for 2 baud-times after the end of transmission 2 THREE CS is asserted for 3 baud-times after the end of transmission 3 SEVEN CS is asserted for 7 baud-times after the end of transmission 4 TCMP0 CS is asserted after the end of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted after the end of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted after the end of transmission for TCMPVAL2 baud-times 7 CTRLX No Description 0x05C read-write 0x00000000 0x8000808F DBGHALT Debug halt 0 1 read-write DISABLE Continue to transmit until TX buffer is empty 0 ENABLE Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock; otherwise, each single step could transmit multiple frames instead of just transmitting one frame. 1 CTSINV CTS Pin Inversion 1 1 read-write DISABLE The USn_CTS pin is low true 0 ENABLE The USn_CTS pin is high true 1 CTSEN CTS Function enabled 2 1 read-write DISABLE Ingore CTS 0 ENABLE Stop transmitting when CTS is negated 1 RTSINV RTS Pin Inversion 3 1 read-write DISABLE The USn_RTS pin is low true 0 ENABLE The USn_RTS pin is high true 1 RXPRSEN PRS RX Enable 7 1 read-write CLKPRSEN PRS CLK Enable 15 1 read-write TIMECMP0 No Description 0x060 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 0. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 0 is disabled 0 TXEOF Comparator 0 and timer are started at TX end of frame 1 TXC Comparator 0 and timer are started at TX Complete 2 RXACT Comparator 0 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 0 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 0 20 3 read-write TCMP0 Comparator 0 is disabled when the counter equals TCMPVAL and triggers a TCMP0 event 0 TXST Comparator 0 is disabled at TX start TX Engine 1 RXACT Comparator 0 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 0 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP0 24 1 read-write DISABLE Disable the timer restarting on TCMP0 0 ENABLE Enable the timer restarting on TCMP0 1 TIMECMP1 No Description 0x064 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 1. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 1 is disabled 0 TXEOF Comparator 1 and timer are started at TX end of frame 1 TXC Comparator 1 and timer are started at TX Complete 2 RXACT Comparator 1 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 1 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 1 20 3 read-write TCMP1 Comparator 1 is disabled when the counter equals TCMPVAL and triggers a TCMP1 event 0 TXST Comparator 1 is disabled at TX start TX Engine 1 RXACT Comparator 1 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 1 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP1 24 1 read-write DISABLE Disable the timer restarting on TCMP1 0 ENABLE Enable the timer restarting on TCMP1 1 TIMECMP2 No Description 0x068 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 2. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 2 is disabled 0 TXEOF Comparator 2 and timer are started at TX end of frame 1 TXC Comparator 2 and timer are started at TX Complete 2 RXACT Comparator 2 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 2 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 2 20 3 read-write TCMP2 Comparator 2 is disabled when the counter equals TCMPVAL and triggers a TCMP2 event 0 TXST Comparator 2 is disabled at TX start TX Engine 1 RXACT Comparator 2 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 2 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP2 24 1 read-write DISABLE Disable the timer restarting on TCMP2 0 ENABLE Enable the timer restarting on TCMP2 1 BURTC_NS 0 BURTC_NS Registers 0x50064000 0x00000000 0x00001000 registers BURTC 18 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN BURTC Enable 0 1 read-write CFG No Description 0x008 read-write 0x00000000 0x000000F3 DEBUGRUN Debug Mode Run Enable 0 1 read-write DISABLE BURTC is frozen in debug mode 0 ENABLE BURTC is running in debug mode 1 COMPTOP Compare Channel is Top Value 1 1 read-write DISABLE The top value of the BURTC is 4294967295 (0xFFFFFFFF) 0 ENABLE The top value of the BURTC is given by COMP 1 CNTPRESC Counter prescaler value. 4 4 read-write DIV1 CLK_CNT = (BURTC LF CLK)/1 0 DIV2 CLK_CNT = (BURTC LF CLK)/2 1 DIV4 CLK_CNT = (BURTC LF CLK)/4 2 DIV8 CLK_CNT = (BURTC LF CLK)/8 3 DIV16 CLK_CNT = (BURTC LF CLK)/16 4 DIV32 CLK_CNT = (BURTC LF CLK)/32 5 DIV64 CLK_CNT = (BURTC LF CLK)/64 6 DIV128 CLK_CNT = (BURTC LF CLK)/128 7 DIV256 CLK_CNT = (BURTC LF CLK)/256 8 DIV512 CLK_CNT = (BURTC LF CLK)/512 9 DIV1024 CLK_CNT = (BURTC LF CLK)/1024 10 DIV2048 CLK_CNT = (BURTC LF CLK)/2048 11 DIV4096 CLK_CNT = (BURTC LF CLK)/4096 12 DIV8192 CLK_CNT = (BURTC LF CLK)/8192 13 DIV16384 CLK_CNT = (BURTC LF CLK)/16384 14 DIV32768 CLK_CNT = (BURTC LF CLK)/32768 15 CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start BURTC counter 0 1 write-only STOP Stop BURTC counter 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x00000003 RUNNING BURTC running status 0 1 read-only LOCK Configuration Lock Status 1 1 read-only UNLOCKED All BURTC lockable registers are unlocked. 0 LOCKED All BURTC lockable registers are locked. 1 IF No Description 0x014 read-write 0x00000000 0x00000003 OF Overflow Interrupt Flag 0 1 read-write COMP Compare Match Interrupt Flag 1 1 read-write IEN No Description 0x018 read-write 0x00000000 0x00000003 OF Overflow Interrupt Flag 0 1 read-write COMP Compare Match Interrupt Flag 1 1 read-write PRECNT No Description 0x01C read-write 0x00000000 0x00007FFF PRECNT Pre-Counter Value 0 15 read-write CNT No Description 0x020 read-write 0x00000000 0xFFFFFFFF CNT Counter Value 0 32 read-write EM4WUEN No Description 0x024 read-write 0x00000000 0x00000003 OFEM4WUEN Overflow EM4 Wakeup Enable 0 1 read-write COMPEM4WUEN Compare Match EM4 Wakeup Enable 1 1 read-write SYNCBUSY No Description 0x028 read-only 0x00000000 0x0000003F START Sync busy for START 0 1 read-only STOP Sync busy for STOP 1 1 read-only PRECNT Sync busy for PRECNT 2 1 read-only CNT Sync busy for CNT 3 1 read-only COMP Sync busy for COMP 4 1 read-only EN Sync busy for EN 5 1 read-only LOCK No Description 0x02C write-only 0x0000AEE8 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write to unlock all BURTC lockable registers 44776 COMP No Description 0x030 read-write 0x00000000 0xFFFFFFFF COMP Compare Value 0 32 read-write I2C1_NS 0 I2C1_NS Registers 0x50068000 0x00000000 0x00001000 registers I2C1 28 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN module enable 0 1 read-write DISABLE Disable Peripheral Clock 0 ENABLE Enable Peripheral Clock 1 CTRL No Description 0x008 read-write 0x00000000 0x0037B3FF CORERST Soft Reset the internal state registers 0 1 read-write DISABLE No change to internal state registers 0 ENABLE Reset the internal state registers 1 SLAVE Addressable as Follower 1 1 read-write DISABLE All addresses will be responded to with a NACK 0 ENABLE Addresses matching the programmed follower address or the general call address (if enabled) require a response from software. Other addresses are automatically responded to with a NACK. 1 AUTOACK Automatic Acknowledge 2 1 read-write DISABLE Software must give one ACK command for each ACK transmitted on the I2C bus. 0 ENABLE Addresses that are not automatically NACK'ed, and all data is automatically acknowledged. 1 AUTOSE Automatic STOP when Empty 3 1 read-write DISABLE A stop must be sent manually when no more data is to be transmitted. 0 ENABLE The leader automatically sends a STOP when no more data is available for transmission. 1 AUTOSN Automatic STOP on NACK 4 1 read-write DISABLE Stop is not automatically sent if a NACK is received from a follower. 0 ENABLE The leader automatically sends a STOP if a NACK is received from a follower. 1 ARBDIS Arbitration Disable 5 1 read-write DISABLE When a device loses arbitration, the ARBIF interrupt flag is set and the bus is released. 0 ENABLE When a device loses arbitration, the ARBIF interrupt flag is set, but communication proceeds. 1 GCAMEN General Call Address Match Enable 6 1 read-write DISABLE General call address will be NACK'ed if it is not included by the follower address and address mask. 0 ENABLE When a general call address is received, a software response is required 1 TXBIL TX Buffer Interrupt Level 7 1 read-write EMPTY TXBL status and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALF_FULL TXBL status and the TXBL interrupt flag are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full 1 CLHR Clock Low High Ratio 8 2 read-write STANDARD Nlow=4 and Nhigh=4, and the Nlow:Nhigh ratio is 4:4 0 ASYMMETRIC Nlow=6 and Nhigh=3, and the Nlow:Nhigh ratio is 6:3 1 FAST Nlow=11 and Nhigh=6, and the Nlow:Nhigh ratio is 11:6 2 BITO Bus Idle Timeout 12 2 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 GIBITO Go Idle on Bus Idle Timeout 15 1 read-write DISABLE A bus idle timeout has no effect on the bus state. 0 ENABLE A bus idle timeout tells the I2C module that the bus is idle, allowing new transfers to be initiated. 1 CLTO Clock Low Timeout 16 3 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 I2C320PCC Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout. 4 I2C1024PCC Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout. 5 SCLMONEN SCL Monitor Enable 20 1 read-write DISABLE Disable SCL monitor 0 ENABLE Enable SCL monitor 1 SDAMONEN SDA Monitor Enable 21 1 read-write DISABLE Disable SDA Monitor 0 ENABLE Enable SDA Monitor 1 CMD No Description 0x00C write-only 0x00000000 0x000000FF START Send start condition 0 1 write-only STOP Send stop condition 1 1 write-only ACK Send ACK 2 1 write-only NACK Send NACK 3 1 write-only CONT Continue transmission 4 1 write-only ABORT Abort transmission 5 1 write-only CLEARTX Clear TX 6 1 write-only CLEARPC Clear Pending Commands 7 1 write-only STATE No Description 0x010 read-only 0x00000001 0x000000FF BUSY Bus Busy 0 1 read-only MASTER Leader 1 1 read-only TRANSMITTER Transmitter 2 1 read-only NACKED Nack Received 3 1 read-only BUSHOLD Bus Held 4 1 read-only STATE Transmission State 5 3 read-only IDLE No transmission is being performed. 0 WAIT Waiting for idle. Will send a start condition as soon as the bus is idle. 1 START Start transmit phase 2 ADDR Address transmit or receive phase 3 ADDRACK Address ack/nack transmit or receive phase 4 DATA Data transmit or receive phase 5 DATAACK Data ack/nack transmit or receive phase 6 STATUS No Description 0x014 read-only 0x00000080 0x00000FFF PSTART Pending START 0 1 read-only PSTOP Pending STOP 1 1 read-only PACK Pending ACK 2 1 read-only PNACK Pending NACK 3 1 read-only PCONT Pending continue 4 1 read-only PABORT Pending abort 5 1 read-only TXC TX Complete 6 1 read-only TXBL TX Buffer Level 7 1 read-only RXDATAV RX Data Valid 8 1 read-only RXFULL RX FIFO Full 9 1 read-only TXBUFCNT TX Buffer Count 10 2 read-only CLKDIV No Description 0x018 read-write 0x00000000 0x000001FF DIV Clock Divider 0 9 read-write SADDR No Description 0x01C read-write 0x00000000 0x000000FE ADDR Follower address 1 7 read-write SADDRMASK No Description 0x020 read-write 0x00000000 0x000000FE SADDRMASK Follower Address Mask 1 7 read-write RXDATA No Description 0x024 read-only 0x00000000 0x000000FF RXDATA RX Data 0 8 read-only RXDOUBLE No Description 0x028 read-only 0x00000000 0x0000FFFF RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDATAP No Description 0x02C read-only 0x00000000 0x000000FF RXDATAP RX Data Peek 0 8 read-only RXDOUBLEP No Description 0x030 read-only 0x00000000 0x0000FFFF RXDATAP0 RX Data 0 Peek 0 8 read-only RXDATAP1 RX Data 1 Peek 8 8 read-only TXDATA No Description 0x034 write-only 0x00000000 0x000000FF TXDATA TX Data 0 8 write-only TXDOUBLE No Description 0x038 write-only 0x00000000 0x0000FFFF TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only IF No Description 0x03C read-write 0x00000000 0x001FFFFF START START condition Interrupt Flag 0 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write ADDR Address Interrupt Flag 2 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write ACK Acknowledge Received Interrupt Flag 6 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write MSTOP Leader STOP Condition Interrupt Flag 8 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write SSTOP Follower STOP condition Interrupt Flag 16 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write IEN No Description 0x040 read-write 0x00000000 0x001FFFFF START START condition Interrupt Flag 0 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write ADDR Address Interrupt Flag 2 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write ACK Acknowledge Received Interrupt Flag 6 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write MSTOP Leader STOP Condition Interrupt Flag 8 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write SSTOP Follower STOP condition Interrupt Flag 16 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write SYSCFG_NS_CFGNS 1 SYSCFG_NS_CFGNS Registers 0x50078000 0x00000000 0x00001000 registers SYSCFG 20 SW0 52 SW1 53 SW2 54 SW3 55 CFGNSTCALIB Configure to define the system tick for the M33. 0x01C read-write 0x01004A37 0x03FFFFFF TENMS Ten Milliseconds 0 24 read-write SKEW Skew 24 1 read-write NOREF No Reference 25 1 read-write REF Reference clock is implemented 0 NOREF Reference clock is not implemented 1 ROOTNSDATA0 Generic data space for user to pass to root, e.g., address of struct in mem 0x600 read-write 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write ROOTNSDATA1 Generic data space for user to pass to root, e.g., address of struct in mem 0x604 read-write 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write SYSCFG_NS 1 SYSCFG_NS Registers 0x5007C000 0x00000000 0x00001000 registers SYSCFG 20 SW0 52 SW1 53 SW2 54 SW3 55 IF Read to get system status. 0x000 read-write 0x00000000 0x3303000F SW0 Software Interrupt 0 0 1 read-write SW1 Software Interrupt 1 1 1 read-write SW2 Software Interrupt 2 2 1 read-write SW3 Software Interrupt 3 3 1 read-write RAMERR1B RAM 1-Bit Error Interrupt Flag 16 1 read-write RAMERR2B RAM 2-Bit Error Interrupt Flag 17 1 read-write SEQRAMERR1B SEQRAM 1-Bit Error Interrupt Flag 24 1 read-write SEQRAMERR2B SEQRAM 2-Bit Error Interrupt Flag 25 1 read-write FRCRAMERR1B FRCRAM 1-Bit Error Interrupt Flag 28 1 read-write FRCRAMERR2B FRCRAM 2-Bit Error Interrupt Flag 29 1 read-write IEN Write to enable interrupts. 0x004 read-write 0x00000000 0x3303000F SW0 Software interrupt 0 0 1 read-write SW1 Software interrupt 1 1 1 read-write SW2 Software interrupt 2 2 1 read-write SW3 Software interrupt 3 3 1 read-write RAMERR1B RAM 1-bit Error Interrupt Enable 16 1 read-write RAMERR2B RAM 2-bit Error Interrupt Enable 17 1 read-write SEQRAMERR1B SEQRAM 1-bit Error Interrupt Enable 24 1 read-write SEQRAMERR2B SEQRAM 2-bit Error Interrupt Enable 25 1 read-write FRCRAMERR1B FRCRAM 1-bit Error Interrupt Enable 28 1 read-write FRCRAMERR2B FRCRAM 2-bit Error Interrupt Enable 29 1 read-write CHIPREVHW Read to get the hard-wired chip revision. 0x010 read-write 0x00000C01 0xFF0FFFFF MAJOR Hardwired Chip Revision Major value 0 6 read-write FAMILY Hardwired Chip Family value 6 6 read-write MINOR Hardwired Chip Revision Minor value 12 8 read-write CHIPREV Read to get the chip revision programmed by feature configuration. 0x014 read-write 0x00000000 0x000FFFFF MAJOR Chip Revision Major value 0 6 read-write FAMILY Chip Family value 6 6 read-write MINOR Chip Revision Minor value 12 8 read-write CFGSYSTIC Configure the source of the system tick for the M33. 0x020 read-write 0x00000000 0x00000001 SYSTICEXTCLKEN SysTick External Clock Enable 0 1 read-write CTRL Configure to provide general RAM configuration. 0x200 read-write 0x00000021 0x00000021 ADDRFAULTEN Invalid Address Bus Fault Response Enable 0 1 read-write RAMECCERRFAULTEN Two bit ECC Error Bus Fault Response Enable 5 1 read-write DMEM0RETNCTRL Configure to provide general RAM retention configuration. 0x208 read-write 0x00000000 0x00000003 RAMRETNCTRL DMEM0 blockset retention control 0 2 read-write ALLON None of the RAM blocks powered down 0 BLK0 Power down RAM block 0 1 BLK1 Power down RAM block 1 2 DMEM0ECCADDR Read to get status of the DMEM0 ECC error address. 0x210 read-only 0x00000000 0xFFFFFFFF DMEM0ECCADDR DMEM0 RAM ECC Error Address 0 32 read-only DMEM0ECCCTRL Configure to set RAM ECC control. 0x214 read-write 0x00000000 0x00000003 RAMECCEN RAM ECC Enable 0 1 read-write RAMECCEWEN RAM ECC Error Writeback Enable 1 1 read-write RADIORAMRETNCTRL Configure SEQRAM Retention controls. 0x400 read-write 0x00000000 0x00000103 SEQRAMRETNCTRL SEQRAM Retention Control 0 2 read-write ALLON SEQRAM not powered down 0 BLK0 Power down SEQRAM block 0 1 BLK1 Power down SEQRAM block 1 2 ALLOFF Power down all SEQRAM blocks 3 FRCRAMRETNCTRL FRCRAM Retention Control 8 1 read-write ALLON FRCRAM not powered down 0 ALLOFF Power down FRCRAM 1 RADIOECCCTRL Configure to set RAM ECC control. 0x408 read-write 0x00000000 0x00000303 SEQRAMECCEN SEQRAM ECC Enable 0 1 read-write SEQRAMECCEWEN SEQRAM ECC Error Writeback Enable 1 1 read-write FRCRAMECCEN FRCRAM ECC Enable 8 1 read-write FRCRAMECCEWEN FRCRAM ECC Error Writeback Enable 9 1 read-write SEQRAMECCADDR Read to get status of the SEQRAM ECC error address. 0x410 read-only 0x00000000 0xFFFFFFFF SEQRAMECCADDR SEQRAM ECC Address 0 32 read-only FRCRAMECCADDR Read to get status of the FRCRAM ECC error address. 0x414 read-only 0x00000000 0xFFFFFFFF FRCRAMECCADDR FRCRAM ECC Error Address 0 32 read-only ROOTDATA0 Data in this register is passed to the trusted root firmware upon reset. 0x600 read-write 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write ROOTDATA1 Data in this register is passed to the trusted root firmware upon reset. 0x604 read-write 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write ROOTLOCKSTATUS This register returns the status of the SE managed locks. 0x608 read-only 0x011F0107 0x011F0117 BUSLOCK Bus Lock 0 1 read-only REGLOCK Register Lock 1 1 read-only MFRLOCK Manufacture Lock 2 1 read-only ROOTMODELOCK Root Mode Lock 4 1 read-only ROOTDBGLOCK Root Debug Lock 8 1 read-only USERDBGLOCK User Invasive Debug Lock 16 1 read-only USERNIDLOCK User Non-invasive Debug Lock 17 1 read-only USERSPIDLOCK User Secure Invasive Debug Lock 18 1 read-only USERSPNIDLOCK User Secure Non-invasive Debug Lock 19 1 read-only USERDBGAPLOCK User Debug Access Port Lock 20 1 read-only RADIODBGLOCK Radio Debug Lock 24 1 read-only BURAM_NS 0 BURAM_NS Registers 0x50080000 0x00000000 0x00001000 registers RET0_REG No Description 0x000 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET1_REG No Description 0x004 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET2_REG No Description 0x008 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET3_REG No Description 0x00C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET4_REG No Description 0x010 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET5_REG No Description 0x014 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET6_REG No Description 0x018 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET7_REG No Description 0x01C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET8_REG No Description 0x020 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET9_REG No Description 0x024 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET10_REG No Description 0x028 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET11_REG No Description 0x02C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET12_REG No Description 0x030 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET13_REG No Description 0x034 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET14_REG No Description 0x038 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET15_REG No Description 0x03C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET16_REG No Description 0x040 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET17_REG No Description 0x044 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET18_REG No Description 0x048 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET19_REG No Description 0x04C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET20_REG No Description 0x050 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET21_REG No Description 0x054 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET22_REG No Description 0x058 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET23_REG No Description 0x05C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET24_REG No Description 0x060 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET25_REG No Description 0x064 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET26_REG No Description 0x068 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET27_REG No Description 0x06C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET28_REG No Description 0x070 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET29_REG No Description 0x074 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET30_REG No Description 0x078 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET31_REG No Description 0x07C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write GPCRC_NS 0 GPCRC_NS Registers 0x50088000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN CRC Enable 0 1 read-write DISABLE Disable CRC function. Reordering functions are still available. Only BITREVERSE and BYTEREVERSE bits are configurable in this mode. 0 ENABLE Writes to INPUTDATA registers will result in CRC operations. 1 CTRL No Description 0x008 read-write 0x00000000 0x00002710 POLYSEL Polynomial Select 4 1 read-write CRC32 CRC-32 (0x04C11DB7) polynomial selected 0 CRC16 16-bit CRC programmable polynomial selected 1 BYTEMODE Byte Mode Enable 8 1 read-write BITREVERSE Byte-level Bit Reverse Enable 9 1 read-write NORMAL No reverse 0 REVERSED Reverse bit order in each byte 1 BYTEREVERSE Byte Reverse Mode 10 1 read-write NORMAL No reverse: B3, B2, B1, B0 0 REVERSED Reverse byte order. For 32-bit: B0, B1, B2, B3; For 16-bit: 0, 0, B0, B1 1 AUTOINIT Auto Init Enable 13 1 read-write CMD No Description 0x00C write-only 0x00000000 0x80000001 INIT Initialization Enable 0 1 write-only INIT No Description 0x010 read-write 0x00000000 0xFFFFFFFF INIT CRC Initialization Value 0 32 read-write POLY No Description 0x014 read-write 0x00000000 0x0000FFFF POLY CRC Polynomial Value 0 16 read-write INPUTDATA No Description 0x018 write-only 0x00000000 0xFFFFFFFF INPUTDATA Input Data for 32-bit 0 32 write-only INPUTDATAHWORD No Description 0x01C write-only 0x00000000 0x0000FFFF INPUTDATAHWORD Input Data for 16-bit 0 16 write-only INPUTDATABYTE No Description 0x020 write-only 0x00000000 0x000000FF INPUTDATABYTE Input Data for 8-bit 0 8 write-only DATA No Description 0x024 read-only 0x00000000 0xFFFFFFFF DATA CRC Data Register 0 32 read-only DATAREV No Description 0x028 read-only 0x00000000 0xFFFFFFFF DATAREV Data Reverse Value 0 32 read-only DATABYTEREV No Description 0x02C read-only 0x00000000 0xFFFFFFFF DATABYTEREV Data Byte Reverse Value 0 32 read-only DCDC_NS 0 DCDC_NS Registers 0x50094000 0x00000000 0x00001000 registers IPVERSION IPVERSION 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IPVERSION 0 32 read-only EN Enable 0x004 read-write 0x00000000 0x00000001 EN Enable 0 1 read-write DISABLE Disable 0 ENABLE Enable 1 CTRL Control 0x008 read-write 0x00000044 0x00000077 MODE DCDC/Bypass Mode Control 0 1 read-write BYPASS DCDC is OFF, bypass switch is enabled 0 DCDCREGULATION Request DCDC regulation, bypass switch disabled 1 DCMONLYEN DCDC DCM Only Enable 2 1 read-write DUALMODE Support higher load current at lower battery voltage by working in CCM mode 0 DCMONLYEN DCM only mode for normal operation, this is the default setting 1 IPKTMAXCTRL Peak Current Timeout Control 4 3 read-write OFF Ton_max disabled 0 TMAX_0P35us 0.35us 1 TMAX_0P63us 0.63us 2 TMAX_0P91us 0.91us 3 TMAX_1P19us 1.19us 4 TMAX_1P47us 1.47us 5 TMAX_1P75us 1.75us 6 TMAX_2P03us 2.03us 7 EM01CTRL0 EM01 Configurations 0x010 read-write 0x00000109 0x0000030F IPKVAL EM01 Peak Current Setting 0 4 read-write Load36mA Ipeak = 90mA, IL = 36mA 3 Load40mA Ipeak = 100mA, IL = 40mA 4 Load44mA Ipeak = 110mA, IL = 44mA 5 Load48mA Ipeak = 120mA, IL = 48mA 6 Load52mA Ipeak = 130mA, IL = 52mA 7 Load56mA Ipeak = 140mA, IL = 56mA 8 Load60mA Ipeak = 150mA, IL = 60mA 9 DRVSPEED EM01 Drive Speed Setting 8 2 read-write BEST_EMI Lowest Efficiency, Lowest EMI.. Small decrease in efficiency from default setting 0 DEFAULT_SETTING Default Efficiency, Acceptable EMI level 1 INTERMEDIATE Small increase in efficiency from the default setting 2 BEST_EFFICIENCY Highest Efficiency, Highest EMI.. Small increase in efficiency from INTERMEDIATE setting 3 EM23CTRL0 EM23 Configurations 0x014 read-write 0x00000103 0x0000030F IPKVAL EM23 Peak Current Setting 0 4 read-write LOAD5MA Ipeak = 90mA, IL = 5 mA 3 LOAD10MA Ipeak = 150mA, IL = 10 mA 9 DRVSPEED EM23 Drive Speed Setting 8 2 read-write BEST_EMI Lowest Efficiency, Lowest EMI.. Small decrease in efficiency from default setting 0 DEFAULT_SETTING Default Efficiency, Acceptable EMI level 1 INTERMEDIATE Small increase in efficiency from the default setting 2 BEST_EFFICIENCY Highest Efficiency, Highest EMI.. Small increase in efficiency from INTERMEDIATE setting 3 IF Interrupt Flags 0x024 read-write 0x00000000 0x000000FF BYPSW Bypass Switch Enabled 0 1 read-write WARM DCDC Warmup Time Done 1 1 read-write RUNNING DCDC Running 2 1 read-write VREGINLOW VREGVDD below threshold 3 1 read-write VREGINHIGH VREGVDD above threshold 4 1 read-write REGULATION DCDC in regulation 5 1 read-write TMAX Ton_max Timeout Reached 6 1 read-write EM4ERR EM4 Entry Request Error 7 1 read-write IEN Interrupt Enable 0x028 read-write 0x00000000 0x000000FF BYPSW Bypass Switch Enabled Interrupt Enable 0 1 read-write WARM DCDC Warmup Time Done Interrupt Enable 1 1 read-write RUNNING DCDC Running Interrupt Enable 2 1 read-write VREGINLOW VREGVDD below threshold Interrupt Enable 3 1 read-write VREGINHIGH VREGVDD above threshold Interrupt Enable 4 1 read-write REGULATION DCDC in Regulation Interrupt Enable 5 1 read-write TMAX Ton_max Timeout Interrupt Enable 6 1 read-write EM4ERR EM4 Entry Req Interrupt Enable 7 1 read-write STATUS DCDC Status Register 0x02C read-only 0x00000000 0x0000001F BYPSW Bypass Switch is currently enabled 0 1 read-only WARM DCDC Warmup Done 1 1 read-only RUNNING DCDC is running 2 1 read-only VREGIN VREGVDD comparator status 3 1 read-only BYPCMPOUT Bypass Comparator Output 4 1 read-only LOCK No Description 0x040 write-only 0x00000000 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCKKEY Value to write to unlock 43981 LOCKSTATUS No Description 0x044 read-only 0x00000000 0x00000001 LOCK Lock Status 0 1 read-only UNLOCKED Unlocked State 0 LOCKED LOCKED STATE 1 PDM_NS 0 PDM_NS Registers 0x50098000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP VERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN PDM enable 0 1 read-write DISABLE Disable module 0 ENABLE Enable module 1 CTRL No Description 0x008 read-write 0x00000000 0x000FFF1F GAIN Selects Gain factor of DCF 0 5 read-write DSR Down sampling rate of Decimation filter 8 12 read-write CMD No Description 0x00C write-only 0x00000000 0x00010111 START Start DCF 0 1 write-only STOP Stop DCF 4 1 write-only CLEAR Clear DCF 8 1 write-only FIFOFL FIFO Flush 16 1 write-only STATUS No Description 0x010 read-only 0x00000020 0x00000731 ACT PDM is active 0 1 read-only FULL FIFO FULL Status 4 1 read-only EMPTY FIFO EMPTY Status 5 1 read-only FIFOCNT FIFO CNT 8 3 read-only CFG0 No Description 0x014 read-write 0x00000000 0x03013713 FORDER Filter order 0 2 read-write SECOND Second order filter. 0 THIRD Third order filter. 1 FOURTH Fourth order filter. 2 FIFTH Fifth order filter. 3 NUMCH Number of Channels 4 1 read-write ONE One channel. 0 TWO Two channels. 1 DATAFORMAT Filter output format 8 3 read-write RIGHT16 Right aligned 16-bit, left bits are sign extended. 0 DOUBLE16 Pack two 16-bit samples into one 32-bit word. 1 RIGHT24 Right aligned 24bit, left bits are sign extended. 2 FULL32BIT 32 bit data. 3 LEFT16 Left aligned 16-bit, right bits are zeros. 4 LEFT24 Left aligned 24-bit, right bits are zeros. 5 RAW32BIT RAW 32 bit data from Integrator. 6 FIFODVL Data Valid level in FIFO 12 2 read-write ONE Atleast one word. 0 TWO Two words. 1 THREE Three words. 2 FOUR Four words. 3 STEREOMODECH01 Stereo mode CH01 16 1 read-write DISABLE No Stereo mode. 0 CH01ENABLE CH0 and CH1 in Stereo mode. 1 CH0CLKPOL CH0 CLK Polarity 24 1 read-write NORMAL Input data clocked on rising clock edge. 0 INVERT Input data clocked on falling clock edge. 1 CH1CLKPOL CH1 CLK Polarity 25 1 read-write NORMAL Input data clocked on rising clock edge. 0 INVERT Input data clocked on falling clock edge. 1 CFG1 No Description 0x018 read-write 0x00000000 0x030003FF PRESC Prescalar Setting for PDM sample 0 10 read-write DLYMUXSEL Data delay buffer mux selection 24 2 read-write RXDATA No Description 0x020 read-only 0x00000000 0xFFFFFFFF RXDATA PDM received data 0 32 read-only IF No Description 0x040 read-write 0x00000000 0x0000000F DV Data Valid Interrupt Flag 0 1 read-write DVL Data Valid Level Interrupt Flag 1 1 read-write OF FIFO Overflow Interrupt Flag 2 1 read-write UF FIFO Undeflow Interrupt Flag 3 1 read-write IEN No Description 0x044 read-write 0x00000000 0x0000000F DV Data Valid Interrupt Enable 0 1 read-write DVL Data Valid Level Interrupt Enable 1 1 read-write OF FIFO Overflow Interrupt Enable 2 1 read-write UF FIFO Undeflow Interrupt Enable 3 1 read-write SYNCBUSY No Description 0x060 read-only 0x00000000 0x00000009 SYNCBUSY sync busy 0 1 read-only FIFOFLBUSY FIFO Flush Sync busy 3 1 read-only RFSENSE_NS 0 RFSENSE_NS Registers 0x5009C000 0x00000000 0x00001000 registers EN Block enables 0x000 read-write 0x00000000 0x00000001 EN RFSENSE Enable 0 1 read-write EM4WUEN No Description 0x004 read-write 0x00000000 0x00000001 EM4WUEN EM4 WakeUp Enable 0 1 read-write CFG Configures RFSENSE digital logic behavior 0x008 read-write 0x03800000 0x0780000D PREAMBLELEN Number of Preamble bits 0 1 read-write SYNCWORDLEN Synword Length 2 2 read-write ENERGYDUR RFSENSE Energy Duration 23 3 read-write dur1ms 1ms duration 0 dur2ms 2ms duration 1 dur4ms 4ms duration 2 dur8ms 8ms duration 3 dur16ms 16ms duration 4 dur32ms 32ms duration 5 dur64ms 64ms duration 6 dur128ms 128ms duration 7 LEGACYMODE RFSENSE Legacy Mode 26 1 read-write SYNCWORD No Description 0x00C read-write 0x00000000 0xFFFFFFFF SYNCWORD Sync Word 0 32 read-write THDSEL No Description 0x010 read-write 0x00000080 0x000000FF THDSEL Threshold Select 0 8 read-write IF No Description 0x020 read-write 0x00000000 0x00000003 RFSENSE RFSENSE Interrupt Flag 0 1 read-write SEQ Sequencer Interrupt Flag 1 1 read-write IEN No Description 0x024 read-write 0x00000000 0x00000003 RFSENSE RFSENSE Interrrupt Enable 0 1 read-write SEQ Sequencer Interrupt Enable 1 1 read-write CALCFG No Description 0x028 read-write 0x01050010 0x130F70FF CALPERIOD Calibration Period 0 8 read-write DISCMCAL Disable Common Mode Calibration 12 1 read-write DISPTATCAL Disable PTAT Calibration 13 1 read-write ENCALPUP Enable Calibration at Power Up 14 1 read-write PTATCALSTEPS PTAT Calibration Steps 16 2 read-write STEPS2 0 STEPS4 1 STEPS6 2 STEPS8 3 CMCALSTEPS CM Calibration Steps 18 2 read-write STEPS2 0 STEPS4 1 STEPS6 2 STEPS8 3 CALSTEPCLKS Clocks per calibration step settling 24 2 read-write PTATCALMODE PTAT Calibration mode 28 1 read-write RFEN No Description 0x02C read-write 0x00000060 0x0000007F ENBG Enable Bandgap 0 1 read-write BGSTART Bandgap Startup Signal 1 1 read-write PTATISO Isolate PTAT core 2 1 read-write PTATSTART PTAT Startup signal 3 1 read-write SUPFLTN Disable supply filtering 4 1 read-write DCEN DC Bias Enable 5 1 read-write RESETN Reset RFSENSE data flop 6 1 read-write MODESEL No Description 0x030 read-write 0x00000000 0x00000007 MODESEL Mode Select 0 3 read-write NORMAL_OP Normal operation 0 CM_CAL Common-mode calibration 1 REF_CAL Bandgap Reference calibration 2 NORMAL_OP2 Normal operation mode-2 3 DM_A_CAL Differntial A calibration 4 DM_B_CAL Differential B calibration 5 DM_A_CAL2 Differential A mode-2 calibration 6 DM_B_CAL2 Differential B mode-2 calibration 7 CMPCONF No Description 0x034 read-write 0x00000000 0x00000007 CHP Invert Comparator IO 0 1 read-write HYS Enable Hysteresis 1 1 read-write PLSN Disable Comparator reset pulse 2 1 read-write TRIMPTAT IPTAT Calbiration trim values 0x038 read-write 0x00000420 0x0000073F TRIMRES PTAT reference resistor trim 0 6 read-write TRIMCURR PTAT current trim 8 3 read-write m80pct Reduce PTAT current by 80% 0 m60pct Reduce PTAT current by 60% 1 m40pct Reduce PTAT current by 40% 2 m20pct Reduce PTAT current by 20% 3 default Default PTAT current 4 p20pct Increase PTAT current by 20% 5 p40pct Increase PTAT current by 40% 6 p60pct Increase PTAT current by 60% 7 TRIMBG BandGap Calibration trim values 0x03C read-write 0x00000088 0x000000FF TRIMREF Reference Trim 0 4 read-write TRIMTC TempCo Trim 4 4 read-write TRIMDAC RFSENSE DAC trim values 0x040 read-write 0x00007F7F 0x03FFFFFF TRIMCM Trim Common Mode 0 8 read-write CMPOSCAL Comparator Offset Calibration value 8 8 read-write TRIMDM Trim Differential Mode 16 9 read-write INVDM Invert Differential offset polarity 25 1 read-write SPARE No Description 0x044 read-write 0x00000000 0x000000F1 SPARE Spare register 0 1 read-write DIGSPARE Digital Spare registers 4 4 read-write SWCTRL Enable Software Control of the FSM signals 0x060 read-write 0x00000010 0x0000001F SWCTRL New BitField 0 4 read-write ANACLKINV Invert Analog clock 4 1 read-write DIAGCTRL No Description 0x064 read-write 0x00000000 0x00000003 DIAGABYPN Diag buffer bypass 0 1 read-write ENBYPASS Enable DIAGA buffer bypass 0 DISBYPASS Disable DIAGA buffer bypass 1 DIAGACHP Diag buffer chop 1 1 read-write DISABLE Disable DIAGA buffer chop 0 ENABLE Enable DIAGA buffer chop 1 STATUS No Description 0x068 read-only 0x00000000 0x0FF73F1F RFSENSEDATA RFSENSE data input from analog 0 1 read-only FIRSTTRIPDONE First RFSENSE trip done 1 1 read-only PREAMBLEDET Preamble Detected 2 1 read-only SYNCDET Syncword Detected 3 1 read-only CALRUNNING Calibration Running 4 1 read-only CALTRIMRES Calibration Resistor Trim value 8 6 read-only CALTRIMCURR Calibration Current Trim value 16 3 read-only CALTRIMCM Calibration Common mode Trim value 20 8 read-only RADIOAES_NS 1 RADIOAES_NS Registers 0x54000000 0x00000000 0x00001000 registers AES 47 FETCHADDR Fetcher: Start address of data block. In direct mode, this register is written by the software. In scatter-gather mode, this register is updated after each processed descriptor. 0x000 read-write 0x00000000 0xFFFFFFFF ADDR Start address of data block 0 32 read-write FETCHLEN Fetcher: Length of data block. In direct mode, this register is written by the software. In scatter-gather mode, this register is not used. 0x008 read-write 0x00000000 0x3FFFFFFF LENGTH Length of data block 0 28 read-write CONSTADDR Constant address 28 1 read-write REALIGN Realign lengh 29 1 read-write FETCHTAG Fetcher: User tag. In direct mode, this register is written by the software. In scatter-gather mode, this register is not used. 0x00C read-write 0x00000000 0xFFFFFFFF TAG User tag 0 32 read-write PUSHADDR Pusher: Start address of data block (LSB). In direct mode, this register is written by the software. In scatter-gather mode, this register is updated after each processed descriptor. 0x010 read-write 0x00000000 0xFFFFFFFF ADDR Start address of data block 0 32 read-write PUSHLEN Pusher: Length of data block. In direct mode, this register is written by the software. In scatter-gather mode, this register is not used. 0x018 read-write 0x00000000 0x7FFFFFFF LENGTH Start address of data block 0 28 read-write CONSTADDR Constant address 28 1 read-write REALIGN Realign length 29 1 read-write DISCARD Discard data 30 1 read-write IEN Interrupt enable 0x01C read-write 0x00000000 0x0000003F FETCHERENDOFBLOCK End of block interrupt enable 0 1 read-write FETCHERSTOPPED Stopped interrupt enable 1 1 read-write FETCHERERROR Error interrupt enable 2 1 read-write PUSHERENDOFBLOCK End of block interrupt enable 3 1 read-write PUSHERSTOPPED Stopped interrupt enable 4 1 read-write PUSHERERROR Error interrupt enable 5 1 read-write IF Interrupt flag register 0x028 read-only 0x00000000 0x0000003F FETCHERENDOFBLOCK End of block interrupt flag 0 1 read-only FETCHERSTOPPED Stopped interrupt flag 1 1 read-only FETCHERERROR Error interrupt flag 2 1 read-only PUSHERENDOFBLOCK End of block interrupt flag 3 1 read-only PUSHERSTOPPED Stopped interrupt flag 4 1 read-only PUSHERERROR Error interrupt flag 5 1 read-only IF_CLR Writing a '1' clears the interrupt status. Writing a '0' has no effect. 0x030 write-only 0x00000000 0x0000003F FETCHERENDOFBLOCK End of block interrupt flag clear 0 1 write-only FETCHERSTOPPED Stopped interrupt flag clear 1 1 write-only FETCHERERROR Error interrupt flag clear 2 1 write-only PUSHERENDOFBLOCK FETCHERENDOFBLOCKIFC 3 1 write-only PUSHERSTOPPED FETCHERSTOPPEDIFC 4 1 write-only PUSHERERROR FETCHERERRORIFC 5 1 write-only CTRL Control register, called CONFIG in Barco datasheet. 0x034 read-write 0x00000000 0x0000001F FETCHERSCATTERGATHER Fetcher scatter/gather 0 1 read-write PUSHERSCATTERGATHER Pusher scatter/gather 1 1 read-write STOPFETCHER Stop fetcher 2 1 read-write STOPPUSHER Stop pusher 3 1 read-write SWRESET Software reset 4 1 read-write CMD Command register for starting the fetcher and pusher 0x038 write-only 0x00000000 0x00000003 STARTFETCHER Start fetch 0 1 write-only STARTPUSHER Start push 1 1 write-only STATUS Status register 0x03C read-only 0x00000000 0xFFFF0073 FETCHERBSY Fetcher busy 0 1 read-only PUSHERBSY Pusher busy 1 1 read-only NOTEMPTY Not empty flag from input FIFO (fetcher) 4 1 read-only WAITING Pusher waiting for FIFO 5 1 read-only SOFTRSTBSY Software reset busy 6 1 read-only FIFODATANUM Number of data in output FIFO 16 16 read-only INCL_IPS_HW_CFG No Description 0x400 read-only 0x00000001 0x000007FF g_IncludeAES Generic g_IncludeAES value 0 1 read-only g_IncludeAESGCM Generic g_IncludeAESGCM value 1 1 read-only g_IncludeAESXTS Generic g_IncludeAESXTS value 2 1 read-only g_IncludeDES Generic g_IncludeDES value 3 1 read-only g_IncludeHASH Generic g_IncludeHASH value 4 1 read-only g_IncludeChachaPoly Generic g_IncludeChachaPoly value 5 1 read-only g_IncludeSHA3 Generic g_IncludeSHA3 value 6 1 read-only g_IncludeZUC Generic g_IncludeZUC value 7 1 read-only g_IncludeSM4 Generic g_IncludeSM4 value 8 1 read-only g_IncludePKE Generic g_IncludePKE value 9 1 read-only g_IncludeNDRNG Generic g_IncludeNDRNG value 10 1 read-only BA411E_HW_CFG_1 No Description 0x404 read-only 0x05010127 0x070301FF g_AesModesPoss AES Modes Supported 0 9 read-only g_CS Generic g_CS value 16 1 read-only g_UseMasking Generic g_UseMasking value 17 1 read-only g_Keysize Generic g_Keysize value 24 3 read-only BA411E_HW_CFG_2 No Description 0x408 read-only 0x00000080 0x0000FFFF g_CtrSize Generic g_CtrSize value 0 16 read-only BA413_HW_CFG No Description 0x40C read-only 0x00000000 0x0007007F g_HashMaskFunc Generic g_HashMaskFunc value 0 7 read-only g_HashPadding Generic g_HashPadding value 16 1 read-only g_HMAC_enabled Generic g_HMAC_enabled value 17 1 read-only g_HashVerifyDigest Generic g_HashVerifyDigest value 18 1 read-only BA418_HW_CFG No Description 0x410 read-only 0x00000001 0x00000001 g_Sha3CtxtEn Generic g_Sha3CtxtEn value 0 1 read-only BA419_HW_CFG No Description 0x414 read-only 0x00000000 0x0000007F g_SM4ModesPoss Generic g_SM4ModesPoss value 0 7 read-only SMU_NS 1 SMU_NS Registers 0x54008000 0x00000000 0x00001000 registers SMU_SECURE 3 SMU_PRIVILEGED 4 IPVERSION The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION. 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only STATUS Read to get SMU status. 0x004 read-only 0x00000000 0x00000003 SMULOCK SMU Lock 0 1 read-only UNLOCKED SMULOCK is Unlocked 0 LOCKED SMULOCK is Locked 1 SMUPRGERR SMU Programming Error 1 1 read-only LOCK Access to Lock/unlock the SMU Configuration. 0x008 write-only 0x00000000 0x00FFFFFF SMULOCKKEY SMU Lock/Key 0 24 write-only UNLOCK Unlocks Registers 11325013 IF Read to get status of SMU interrupts. 0x00C read-write 0x00000000 0x00030005 PPUPRIV PPU Privilege Interrupt Flag 0 1 read-write PPUINST PPU Instruction Interrupt Flag 2 1 read-write PPUSEC PPU Security Interrupt Flag 16 1 read-write BMPUSEC BMPU Security Interrupt Flag 17 1 read-write IEN Write to Enable/Disable SMU interrupts. 0x010 read-write 0x00000000 0x00030005 PPUPRIV PPU Privilege Interrupt Enable 0 1 read-write PPUINST PPU Instruction Interrupt Enable 2 1 read-write PPUSEC PPU Security Interrupt Enable 16 1 read-write BMPUSEC BMPU Security Interrupt Enable 17 1 read-write M33CTRL Holds the M33 control settings. 0x020 read-write 0x00000000 0x0000001F LOCKSVTAIRCR LOCKSVTAIRCR control of M33 CPU 0 1 read-write LOCKNSVTOR LOCKNSVTOR control of M33 CPU 1 1 read-write LOCKSMPU LOCKSMPU control of M33 CPU 2 1 read-write LOCKNSMPU LOCKNSMPU control of M33 CPU 3 1 read-write LOCKSAU LOCKSAU control of M33 CPU 4 1 read-write PPUPATD0 Set peripheral bits to 1 to mark as privileged access only. 0x040 read-write 0xFFFFFFFF 0xFFFFFFFF EMU EMU Privileged Access 1 1 read-write CMU CMU Privileged Access 2 1 read-write HFXO0 HFXO0 Privileged Access 3 1 read-write HFRCO0 HFRCO0 Privileged Access 4 1 read-write FSRCO FSRCO Privileged Access 5 1 read-write DPLL0 DPLL0 Privileged Access 6 1 read-write LFXO LFXO Privileged Access 7 1 read-write LFRCO LFRCO Privileged Access 8 1 read-write ULFRCO ULFRCO Privileged Access 9 1 read-write MSC MSC Privileged Access 10 1 read-write ICACHE0 ICACHE0 Privileged Access 11 1 read-write PRS PRS Privileged Access 12 1 read-write GPIO GPIO Privileged Access 13 1 read-write LDMA LDMA Privileged Access 14 1 read-write LDMAXBAR LDMAXBAR Privileged Access 15 1 read-write TIMER0 TIMER0 Privileged Access 16 1 read-write TIMER1 TIMER1 Privileged Access 17 1 read-write TIMER2 TIMER2 Privileged Access 18 1 read-write TIMER3 TIMER3 Privileged Access 19 1 read-write TIMER4 TIMER4 Privileged Access 20 1 read-write USART0 USART0 Privileged Access 21 1 read-write USART1 USART1 Privileged Access 22 1 read-write BURTC BURTC Privileged Access 23 1 read-write I2C1 I2C1 Privileged Access 24 1 read-write CHIPTESTCTRL CHIPTESTCTRL Privileged Access 25 1 read-write SYSCFGCFGNS SYSCFGCFGNS Privileged Access 26 1 read-write SYSCFG SYSCFG Privileged Access 27 1 read-write BURAM BURAM Privileged Access 28 1 read-write IFADCDEBUG IFADCDEBUG Privileged Access 29 1 read-write GPCRC GPCRC Privileged Access 30 1 read-write DCI DCI Privileged Access 31 1 read-write PPUPATD1 Set peripheral bits to 1 to mark as privileged access only. 0x044 read-write 0x0000FFFF 0x0000FFFF DCDC DCDC Privileged Access 1 1 read-write PDM PDM Privileged Access 2 1 read-write RFSENSE RFSENSE Privileged Access 3 1 read-write RADIOAES RADIOAES Privileged Access 4 1 read-write SMU SMU Privileged Access 5 1 read-write SMUCFGNS SMUCFGNS Privileged Access 6 1 read-write RTCC RTCC Privileged Access 7 1 read-write LETIMER0 LETIMER0 Privileged Access 8 1 read-write IADC0 IADC0 Privileged Access 9 1 read-write I2C0 I2C0 Privileged Access 10 1 read-write WDOG0 WDOG0 Privileged Access 11 1 read-write AMUXCP0 AMUXCP0 Privileged Access 12 1 read-write EUART0 EUART0 Privileged Access 13 1 read-write CRYPTOACC CRYPTOACC Privileged Access 14 1 read-write AHBRADIO AHBRADIO Privileged Access 15 1 read-write PPUSATD0 Set peripheral bits to 1 to mark as secure access only. 0x060 read-write 0xFFFFFFFF 0xFFFFFFFF EMU EMU Secure Access 1 1 read-write CMU CMU Secure Access 2 1 read-write HFXO0 HFXO0 Secure Access 3 1 read-write HFRCO0 HFRCO0 Secure Access 4 1 read-write FSRCO FSRCO Secure Access 5 1 read-write DPLL0 DPLL0 Secure Access 6 1 read-write LFXO LFXO Secure Access 7 1 read-write LFRCO LFRCO Secure Access 8 1 read-write ULFRCO ULFRCO Secure Access 9 1 read-write MSC MSC Secure Access 10 1 read-write ICACHE0 ICACHE0 Secure Access 11 1 read-write PRS PRS Secure Access 12 1 read-write GPIO GPIO Secure Access 13 1 read-write LDMA LDMA Secure Access 14 1 read-write LDMAXBAR LDMAXBAR Secure Access 15 1 read-write TIMER0 TIMER0 Secure Access 16 1 read-write TIMER1 TIMER1 Secure Access 17 1 read-write TIMER2 TIMER2 Secure Access 18 1 read-write TIMER3 TIMER3 Secure Access 19 1 read-write TIMER4 TIMER4 Secure Access 20 1 read-write USART0 USART0 Secure Access 21 1 read-write USART1 USART1 Secure Access 22 1 read-write BURTC BURTC Secure Access 23 1 read-write I2C1 I2C1 Secure Access 24 1 read-write CHIPTESTCTRL CHIPTESTCTRL Secure Access 25 1 read-write SYSCFGCFGNS SYSCFGCFGNS Secure Access 26 1 read-write SYSCFG SYSCFG Secure Access 27 1 read-write BURAM BURAM Secure Access 28 1 read-write IFADCDEBUG IFADCDEBUG Secure Access 29 1 read-write GPCRC GPCRC Secure Access 30 1 read-write DCI DCI Secure Access 31 1 read-write PPUSATD1 Set peripheral bits to 1 to mark as secure access only. 0x064 read-write 0x0000FFFF 0x0000FFFF DCDC DCDC Secure Access 1 1 read-write PDM PDM Secure Access 2 1 read-write RFSENSE RFSENSE Secure Access 3 1 read-write RADIOAES RADIOAES Secure Access 4 1 read-write SMU SMU Secure Access 5 1 read-write SMUCFGNS SMUCFGNS Secure Access 6 1 read-write RTCC RTCC Secure Access 7 1 read-write LETIMER0 LETIMER0 Secure Access 8 1 read-write IADC0 IADC0 Secure Access 9 1 read-write I2C0 I2C0 Secure Access 10 1 read-write WDOG0 WDOG0 Secure Access 11 1 read-write AMUXCP0 AMUXCP0 Secure Access 12 1 read-write EUART0 EUART0 Secure Access 13 1 read-write CRYPTOACC CRYPTOACC Secure Access 14 1 read-write AHBRADIO AHBRADIO Secure Access 15 1 read-write PPUFS Read to get fault status of SMU. 0x140 read-only 0x00000000 0x000000FF PPUFSPERIPHID Peripheral ID 0 8 read-only BMPUPATD0 Set master bits to 1 to mark as a privileged master. 0x150 read-write 0x0000001F 0x0000001F RADIOAES RADIO AES DMA privileged mode 0 1 read-write CRYPTOACC CRYPTOACC DMA privileged mode 1 1 read-write RADIOSUBSYSTEM RADIO subsystem masters privileged mode 2 1 read-write RADIOIFADCDEBUG RADIO IFADC debug privileged mode 3 1 read-write LDMA MCU LDMA privileged mode 4 1 read-write BMPUSATD0 Set master bits to 1 to mark as a secure master. 0x170 read-write 0x0000001F 0x0000001F RADIOAES RADIOAES DMA secure mode 0 1 read-write CRYPTOACC CRYPTOACC DMA secure mode 1 1 read-write RADIOSUBSYSTEM RADIO subsystem masters secure mode 2 1 read-write RADIOIFADCDEBUG RADIO IFADC debug secure mode 3 1 read-write LDMA MCU LDMA secure mode 4 1 read-write BMPUFS Read to get status about the master that triggered a fault. 0x250 read-only 0x00000000 0x000000FF BMPUFSMASTERID Master ID 0 8 read-only BMPUFSADDR Read to get the access address that triggered a fault. 0x254 read-only 0x00000000 0xFFFFFFFF BMPUFSADDR Fault Address 0 32 read-only ESAURTYPES0 Write to specify if a region is secure or non-secure. 0x260 read-write 0x00000000 0x00001000 ESAUR3NS Region 3 Non-Secure Type 12 1 read-write ESAURTYPES1 Write to specify if a region is secure or non-secure. 0x264 read-write 0x00000000 0x00001000 ESAUR11NS Region 11 Non-Secure Type 12 1 read-write ESAUMRB01 Specify the boundary between regions 0 and 1. 0x270 read-write 0x02000000 0x0FFFF000 ESAUMRB01 Moveable Region Boundary 0-1 12 16 read-write ESAUMRB12 Specify the boundary between regions 1 and 2. 0x274 read-write 0x04000000 0x0FFFF000 ESAUMRB12 Moveable Region Boundary 1-2 12 16 read-write ESAUMRB45 Specify the boundary between regions 4 and 5. 0x280 read-write 0x02000000 0x0FFFF000 ESAUMRB45 Moveable Region Boundary 4-5 12 16 read-write ESAUMRB56 Specify the boundary between regions 5 and 6. 0x284 read-write 0x04000000 0x0FFFF000 ESAUMRB56 Moveable Region Boundary 5-6 12 16 read-write SMU_NS_CFGNS 1 SMU_NS_CFGNS Registers 0x5400C000 0x00000000 0x00001000 registers SMU_SECURE 3 SMU_PRIVILEGED 4 NSSTATUS Register for status flags. 0x004 read-only 0x00000000 0x00000001 SMUNSLOCK SMUNS Lock Status 0 1 read-only UNLOCKED SMUNSLOCK Unlocked 0 LOCKED SMUNSLOCK Locked 1 NSLOCK Register used to lock/unlock access to the register file. 0x008 write-only 0x00000000 0x00FFFFFF SMUNSLOCKKEY SMU Non-Secure Lock/Key 0 24 write-only UNLOCK Unlocks Registers 11325013 NSIF Register for interrupt status flags. 0x00C read-write 0x00000000 0x00000005 PPUNSPRIVIF PPUNS Privilege Interrupt Flag 0 1 read-write PPUNSINSTIF PPUNS Instruction Interrupt Flag 2 1 read-write NSIEN Register used for enabling/disabling interrupts. 0x010 read-write 0x00000000 0x00000005 PPUNSPRIVIEN PPUNS Privilege Interrupt Enable 0 1 read-write PPUNSINSTIEN PPUNS Instruction Interrupt Enable 2 1 read-write PPUNSPATD0 Set peripheral bits to 1 to mark as privileged access only. 0x040 read-write 0x00000000 0xFFFFFFFF EMU EMU Privileged Access 1 1 read-write CMU CMU Privileged Access 2 1 read-write HFXO0 HFXO0 Privileged Access 3 1 read-write HFRCO0 HFRCO0 Privileged Access 4 1 read-write FSRCO FSRCO Privileged Access 5 1 read-write DPLL0 DPLL0 Privileged Access 6 1 read-write LFXO LFXO Privileged Access 7 1 read-write LFRCO LFRCO Privileged Access 8 1 read-write ULFRCO ULFRCO Privileged Access 9 1 read-write MSC MSC Privileged Access 10 1 read-write ICACHE0 ICACHE0 Privileged Access 11 1 read-write PRS PRS Privileged Access 12 1 read-write GPIO GPIO Privileged Access 13 1 read-write LDMA LDMA Privileged Access 14 1 read-write LDMAXBAR LDMAXBAR Privileged Access 15 1 read-write TIMER0 TIMER0 Privileged Access 16 1 read-write TIMER1 TIMER1 Privileged Access 17 1 read-write TIMER2 TIMER2 Privileged Access 18 1 read-write TIMER3 TIMER3 Privileged Access 19 1 read-write TIMER4 TIMER4 Privileged Access 20 1 read-write USART0 USART0 Privileged Access 21 1 read-write USART1 USART1 Privileged Access 22 1 read-write BURTC BURTC Privileged Access 23 1 read-write I2C1 I2C1 Privileged Access 24 1 read-write CHIPTESTCTRL CHIPTESTCTRL Privileged Access 25 1 read-write SYSCFGCFGNS SYSCFGCFGNS Privileged Access 26 1 read-write SYSCFG SYSCFG Privileged Access 27 1 read-write BURAM BURAM Privileged Access 28 1 read-write IFADCDEBUG IFADCDEBUG Privileged Access 29 1 read-write GPCRC GPCRC Privileged Access 30 1 read-write DCI DCI Privileged Access 31 1 read-write PPUNSPATD1 Set peripheral bits to 1 to mark as privileged access only. 0x044 read-write 0x00000000 0x0000FFFF DCDC DCDC Privileged Access 1 1 read-write PDM PDM Privileged Access 2 1 read-write RFSENSE RFSENSE Privileged Access 3 1 read-write RADIOAES RADIOAES Privileged Access 4 1 read-write SMU SMU Privileged Access 5 1 read-write SMUCFGNS SMUCFGNS Privileged Access 6 1 read-write RTCC RTCC Privileged Access 7 1 read-write LETIMER0 LETIMER0 Privileged Access 8 1 read-write IADC0 IADC0 Privileged Access 9 1 read-write I2C0 I2C0 Privileged Access 10 1 read-write WDOG0 WDOG0 Privileged Access 11 1 read-write AMUXCP0 AMUXCP0 Privileged Access 12 1 read-write EUART0 EUART0 Privileged Access 13 1 read-write CRYPTOACC CRYPTOACC Privileged Access 14 1 read-write AHBRADIO AHBRADIO Privileged Access 15 1 read-write PPUNSFS Read this register to query the fault status. 0x140 read-only 0x00000000 0x000000FF PPUFSPERIPHID Peripheral ID 0 8 read-only BMPUNSPATD0 Write to set BMPU priveledged attributes. 0x150 read-write 0x00000000 0x0000001F RADIOAES RADIO AES DMA privileged mode 0 1 read-write CRYPTOACC CRYPTOACC DMA privileged mode 1 1 read-write RADIOSUBSYSTEM RADIO subsystem masters privileged mode 2 1 read-write RADIOIFADCDEBUG RADIO IFADC debug privileged mode 3 1 read-write LDMA MCU LDMA privileged mode 4 1 read-write RTCC_NS 1 RTCC_NS Registers 0x58000000 0x00000000 0x00001000 registers RTCC 12 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP VERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN RTCC Enable 0 1 read-write CFG No Description 0x008 read-write 0x00000000 0x000000FF DEBUGRUN Debug Mode Run Enable 0 1 read-write X0 RTCC is frozen in debug mode 0 X1 RTCC is running in debug mode 1 PRECNTCCV0TOP Pre-counter CCV0 top value enable. 1 1 read-write CNTCCV1TOP CCV1 top value enable 2 1 read-write CNTTICK Counter prescaler mode. 3 1 read-write PRESC CNT register ticks according to configuration in CNTPRESC. 0 CCV0MATCH CNT register ticks when PRECNT matches RTCC_CC0_OC[14:0] 1 CNTPRESC Counter prescaler value. 4 4 read-write DIV1 CLK_CNT = (RTCC LF CLK)/1 0 DIV2 CLK_CNT = (RTCC LF CLK)/2 1 DIV4 CLK_CNT = (RTCC LF CLK)/4 2 DIV8 CLK_CNT = (RTCC LF CLK)/8 3 DIV16 CLK_CNT = (RTCC LF CLK)/16 4 DIV32 CLK_CNT = (RTCC LF CLK)/32 5 DIV64 CLK_CNT = (RTCC LF CLK)/64 6 DIV128 CLK_CNT = (RTCC LF CLK)/128 7 DIV256 CLK_CNT = (RTCC LF CLK)/256 8 DIV512 CLK_CNT = (RTCC LF CLK)/512 9 DIV1024 CLK_CNT = (RTCC LF CLK)/1024 10 DIV2048 CLK_CNT = (RTCC LF CLK)/2048 11 DIV4096 CLK_CNT = (RTCC LF CLK)/4096 12 DIV8192 CLK_CNT = (RTCC LF CLK)/8192 13 DIV16384 CLK_CNT = (RTCC LF CLK)/16384 14 DIV32768 CLK_CNT = (RTCC LF CLK)/32768 15 CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start RTCC main counter 0 1 write-only STOP Stop RTCC main counter 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x00000003 RUNNING RTCC running status 0 1 read-only RTCCLOCKSTATUS Lock Status 1 1 read-only UNLOCKED RTCC registers are unlocked 0 LOCKED RTCC registers are locked 1 IF No Description 0x014 read-write 0x00000000 0x000003FF OF Overflow Interrupt Flag 0 1 read-write CNTTICK Main counter tick 1 1 read-write CC0 CC Channel n Interrupt Flag 4 1 read-write CC1 CC Channel n Interrupt Flag 6 1 read-write CC2 CC Channel n Interrupt Flag 8 1 read-write IEN No Description 0x018 read-write 0x00000000 0x000003FF OF OF Interrupt Enable 0 1 read-write CNTTICK CNTTICK Interrupt Enable 1 1 read-write CC0 CC Channel n Interrupt Enable 4 1 read-write CC1 CC Channel n Interrupt Enable 6 1 read-write CC2 CC Channel n Interrupt Enable 8 1 read-write PRECNT No Description 0x01C read-write 0x00000000 0x00007FFF PRECNT Pre-Counter Value 0 15 read-write CNT No Description 0x020 read-write 0x00000000 0xFFFFFFFF CNT Counter Value 0 32 read-write COMBCNT No Description 0x024 read-only 0x00000000 0xFFFFFFFF PRECNT Pre-Counter Value 0 15 read-only CNTLSB Counter Value 15 17 read-only SYNCBUSY No Description 0x028 read-only 0x00000000 0x0000000F START Sync busy for START 0 1 read-only STOP Sync busy for STOP 1 1 read-only PRECNT Sync busy for PRECNT 2 1 read-only CNT Sync busy for CNT 3 1 read-only LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write to unlock RTCC lockable registers 44776 CC0_CTRL No Description 0x030 read-write 0x00000000 0x000000FF MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 CC0_OCVALUE No Description 0x034 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC0_ICVALUE No Description 0x038 read-only 0x00000000 0xFFFFFFFF IC Input Capture Value 0 32 read-only CC1_CTRL No Description 0x03C read-write 0x00000000 0x000000FF MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 CC1_OCVALUE No Description 0x040 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC1_ICVALUE No Description 0x044 read-only 0x00000000 0xFFFFFFFF IC Input Capture Value 0 32 read-only CC2_CTRL No Description 0x048 read-write 0x00000000 0x000000FF MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 CC2_OCVALUE No Description 0x04C read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC2_ICVALUE No Description 0x050 read-only 0x00000000 0xFFFFFFFF IC Input Capture Value 0 32 read-only LETIMER0_NS 0 LETIMER0_NS Registers 0x5A000000 0x00000000 0x00001000 registers LETIMER0 19 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN module en 0 1 read-write CTRL No Description 0x008 read-write 0x00000000 0x000F13FF REPMODE Repeat Mode 0 2 read-write FREE When started, the LETIMER counts down until it is stopped by software 0 ONESHOT The counter counts REP0 times. When REP0 reaches zero, the counter stops 1 BUFFERED The counter counts REP0 times. If REP1 has been written, it is loaded into REP0 when REP0 reaches zero, otherwise the counter stops 2 DOUBLE Both REP0 and REP1 are decremented when the LETIMER wraps around. The LETIMER counts until both REP0 and REP1 are zero 3 UFOA0 Underflow Output Action 0 2 2 read-write NONE LETIMERn_OUT0 is held at its idle value as defined by OPOL0 0 TOGGLE LETIMERn_OUT0 is toggled on CNT underflow 1 PULSE LETIMERn_OUT0 is held active for one LETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL0 2 PWM LETIMERn_OUT0 is set idle on CNT underflow, and active on compare match with COMP1 3 UFOA1 Underflow Output Action 1 4 2 read-write NONE LETIMERn_OUT1 is held at its idle value as defined by OPOL1 0 TOGGLE LETIMERn_OUT1 is toggled on CNT underflow 1 PULSE LETIMERn_OUT1 is held active for one LETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL1 2 PWM LETIMERn_OUT1 is set idle on CNT underflow, and active on compare match with COMP1 3 OPOL0 Output 0 Polarity 6 1 read-write OPOL1 Output 1 Polarity 7 1 read-write BUFTOP Buffered Top 8 1 read-write DISABLE TOP is only written by software 0 ENABLE TOP is set to TOPBUFF value when REP0 reaches 0 1 CNTTOPEN Compare Value 0 Is Top Value 9 1 read-write DISABLE The top value of the LETIMER is 16777215 (0xFFFFFF) 0 ENABLE The top value of the LETIMER is given by TOP 1 DEBUGRUN Debug Mode Run Enable 12 1 read-write DISABLE LETIMER is frozen in debug mode 0 ENABLE LETIMER is running in debug mode 1 CNTPRESC Counter prescaler value 16 4 read-write DIV1 CLK_CNT = (LETIMER LF CLK)/1 0 DIV2 CLK_CNT = (LETIMER LF CLK)/2 1 DIV4 CLK_CNT = (LETIMER LF CLK)/4 2 DIV8 CLK_CNT = (LETIMER LF CLK)/8 3 DIV16 CLK_CNT = (LETIMER LF CLK)/16 4 DIV32 CLK_CNT = (LETIMER LF CLK)/32 5 DIV64 CLK_CNT = (LETIMER LF CLK)/64 6 DIV128 CLK_CNT = (LETIMER LF CLK)/128 7 DIV256 CLK_CNT = (LETIMER LF CLK)/256 8 CMD No Description 0x00C write-only 0x00000000 0x0000001F START Start LETIMER 0 1 write-only STOP Stop LETIMER 1 1 write-only CLEAR Clear LETIMER 2 1 write-only CTO0 Clear Toggle Output 0 3 1 write-only CTO1 Clear Toggle Output 1 4 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x00000001 RUNNING LETIMER Running 0 1 read-only CNT No Description 0x018 read-write 0x00000000 0x00FFFFFF CNT Counter Value 0 24 read-write COMP0 No Description 0x01C read-write 0x00000000 0x00FFFFFF COMP0 Compare Value 0 0 24 read-write COMP1 No Description 0x020 read-write 0x00000000 0x00FFFFFF COMP1 Compare Value 1 0 24 read-write TOP No Description 0x024 read-write 0x00000000 0x00FFFFFF TOP Counter TOP Value 0 24 read-write TOPBUFF No Description 0x028 read-write 0x00000000 0x00FFFFFF TOPBUFF Buffered Counter TOP Value 0 24 read-write REP0 No Description 0x02C read-write 0x00000000 0x000000FF REP0 Repeat Counter 0 0 8 read-write REP1 No Description 0x030 read-write 0x00000000 0x000000FF REP1 Repeat Counter 1 0 8 read-write IF No Description 0x034 read-write 0x00000000 0x0000001F COMP0 Compare Match 0 Interrupt Flag 0 1 read-write COMP1 Compare Match 1 Interrupt Flag 1 1 read-write UF Underflow Interrupt Flag 2 1 read-write REP0 Repeat Counter 0 Interrupt Flag 3 1 read-write REP1 Repeat Counter 1 Interrupt Flag 4 1 read-write IEN No Description 0x038 read-write 0x00000000 0x0000001F COMP0 Compare Match 0 Interrupt Enable 0 1 read-write COMP1 Compare Match 1 Interrupt Enable 1 1 read-write UF Underflow Interrupt Enable 2 1 read-write REP0 Repeat Counter 0 Interrupt Enable 3 1 read-write REP1 Repeat Counter 1 Interrupt Enable 4 1 read-write SYNCBUSY No Description 0x040 read-only 0x00000000 0x000003FD CNT Sync busy for CNT 0 1 read-only TOP Sync busy for TOP 2 1 read-only REP0 Sync busy for REP0 3 1 read-only REP1 Sync busy for REP1 4 1 read-only START Sync busy for START 5 1 read-only STOP Sync busy for STOP 6 1 read-only CLEAR Sync busy for CLEAR 7 1 read-only CTO0 Sync busy for CTO0 8 1 read-only CTO1 Sync busy for CTO1 9 1 read-only PRSMODE No Description 0x050 read-write 0x00000000 0x0CCC0000 PRSSTARTMODE PRS Start Mode 18 2 read-write NONE PRS cannot start the LETIMER 0 RISING Rising edge of selected PRS input can start the LETIMER 1 FALLING Falling edge of selected PRS input can start the LETIMER 2 BOTH Both the rising or falling edge of the selected PRS input can start the LETIMER 3 PRSSTOPMODE PRS Stop Mode 22 2 read-write NONE PRS cannot stop the LETIMER 0 RISING Rising edge of selected PRS input can stop the LETIMER 1 FALLING Falling edge of selected PRS input can stop the LETIMER 2 BOTH Both the rising or falling edge of the selected PRS input can stop the LETIMER 3 PRSCLEARMODE PRS Clear Mode 26 2 read-write NONE PRS cannot clear the LETIMER 0 RISING Rising edge of selected PRS input can clear the LETIMER 1 FALLING Falling edge of selected PRS input can clear the LETIMER 2 BOTH Both the rising or falling edge of the selected PRS input can clear the LETIMER 3 IADC0_NS 1 IADC0_NS Registers 0x5A004000 0x00000000 0x00001000 registers IADC 48 IPVERSION IPVERSION 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only EN Enable 0x004 read-write 0x00000000 0x00000001 EN Enable IADC Module 0 1 read-write DISABLE Disable 0 ENABLE Enable 1 CTRL Control 0x008 read-write 0x00000000 0x707F003F EM23WUCONVERT EM23 Wakeup on Conversion 0 1 read-write WUDVL When using suspend mode, conversions performed in EM2 or EM3 should not wake up the DMA until the FIFO's DVL setting is reached. This saves more power for large OSR settings or infrequent sampling. 0 WUCONVERT When using suspend mode, conversions performed in EM2 or EM3 will wake up the DMA and keep it awake until the conversions are done, regardless of the DVL setting. This mode burns more power, but it is useful when the conversion rate is faster than the time for the DMA to cycle through wake up and going back to sleep as it converts more than 4 scan table entries. Without using the wake up on conversion mode, the FIFO may overflow while the DMA is going in and out of sleep. 1 ADCCLKSUSPEND0 ADC_CLK Suspend - PRS0 1 1 read-write PRSWUDIS Normal mode which does not disable the ADC_CLK. 0 PRSWUEN ADCCLKWUEN will gate off ADC_CLK until the trigger is detected provided the internal timer is not selected as the trigger. Once the trigger is detected the ADC_CLK will be started, the band gap will be started, the ADC will be warmed up, and the SCAN Table and the Single entry will be converted. Once the conversions are done, the ADC_CLK will be gated off. 1 ADCCLKSUSPEND1 ADC_CLK Suspend - PRS1 2 1 read-write PRSWUDIS Normal mode which does not disable the ADC_CLK. 0 PRSWUEN ADCCLKWUEN will gate off ADC_CLK until the trigger is detected provided the internal timer is not selected as the trigger. Once the trigger is detected the ADC_CLK will be started, the band gap will be started, the ADC will be warmed up, and the SCAN Table and the Single entry will be converted. Once the conversions are done, the ADC_CLK will be gated off. 1 DBGHALT Debug Halt 3 1 read-write NORMAL Continue operation as normal during debug mode 0 HALT Complete the current conversion and then halt during debug mode 1 WARMUPMODE Warmup Mode 4 2 read-write NORMAL Shut down the IADC after conversions have completed. 0 KEEPINSTANDBY Switch to standby mode after conversions have completed. The next warmup time will require 1us. 1 KEEPWARM Keep IADC fully powered after conversions have completed. 2 TIMEBASE Time Base 16 7 read-write HSCLKRATE High Speed Clock Rate 28 3 read-write DIV1 Use CMU_CLK_ADC directly. The source clock must be 40 MHz or less. 0 DIV2 Divide CMU_CLK_ADC by 2 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 1 DIV3 Divide CMU_CLK_ADC by 3 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 2 DIV4 Divide CMU_CLK_ADC by 4 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 3 CMD Command 0x00C write-only 0x00000000 0x0303001B SINGLESTART Single Queue Start 0 1 write-only SINGLESTOP Single Queue Stop 1 1 write-only SCANSTART Scan Queue Start 3 1 write-only SCANSTOP Scan Queue Stop 4 1 write-only TIMEREN Timer Enable 16 1 write-only TIMERDIS Timer Disable 17 1 write-only SINGLEFIFOFLUSH Flush the Single FIFO 24 1 write-only SCANFIFOFLUSH Flush the Scan FIFO 25 1 write-only TIMER Timer 0x010 read-write 0x00000000 0x0000FFFF TIMER Timer Period 0 16 read-write STATUS Status 0x014 read-only 0x00000000 0x4131CF5B SINGLEQEN Single Queue Enabled 0 1 read-only SINGLEQUEUEPENDING Single Queue Pending 1 1 read-only SCANQEN Scan Queued Enabled 3 1 read-only SCANQUEUEPENDING Scan Queue Pending 4 1 read-only CONVERTING Converting 6 1 read-only SINGLEFIFODV SINGLEFIFO Data Valid 8 1 read-only SCANFIFODV SCANFIFO Data Valid 9 1 read-only SINGLEFIFOFLUSHING The Single FIFO is flushing 14 1 read-only SCANFIFOFLUSHING The Scan FIFO is flushing 15 1 read-only TIMERACTIVE Timer Active 16 1 read-only SINGLEWRITEPENDING SINGLE write pending 20 1 read-only MASKREQWRITEPENDING MASKREQ write pending 21 1 read-only SYNCBUSY SYNCBUSY 24 1 read-only ADCWARM ADCWARM 30 1 read-only MASKREQ Mask Request 0x018 read-write 0x00000000 0x0000FFFF MASKREQ Scan Queue Mask Request 0 16 read-write STMASK Scan Table Mask 0x01C read-only 0x00000000 0x0000FFFF STMASK Scan Table Mask 0 16 read-only CMPTHR Comparator Threshold 0x020 read-write 0x00000000 0xFFFFFFFF ADLT ADC Less Than or Equal to Threshold 0 16 read-write ADGT ADC Greater Than or Equal to Threshold 16 16 read-write IF Interrupt Flag 0x024 read-write 0x00000000 0x800F338F SINGLEFIFODVL Single FIFO Data Valid Level 0 1 read-write SCANFIFODVL Scan FIFO Data Valid Level 1 1 read-write SINGLECMP Single Result Window Compare 2 1 read-write SCANCMP Scan Result Window Compare 3 1 read-write SCANENTRYDONE Scan Entry Done 7 1 read-write SCANTABLEDONE Scan Table Done 8 1 read-write SINGLEDONE Single Conversion Done 9 1 read-write POLARITYERR Polarity Error 12 1 read-write PORTALLOCERR Port Allocation Error 13 1 read-write SINGLEFIFOOF Single FIFO Overflow 16 1 read-write SCANFIFOOF Scan FIFO Overflow 17 1 read-write SINGLEFIFOUF Single FIFO Underflow 18 1 read-write SCANFIFOUF Scan FIFO Underflow 19 1 read-write EM23ABORTERROR EM2/3 Abort Error 31 1 read-write IEN Interrupt Enable 0x028 read-write 0x00000000 0x800F338F SINGLEFIFODVL Single FIFO Data Valid Level Enable 0 1 read-write SCANFIFODVL Scan FIFO Data Valid Level Enable 1 1 read-write SINGLECMP Single Result Window Compare Enable 2 1 read-write SCANCMP Scan Result Window Compare Enable 3 1 read-write SCANENTRYDONE Scan Entry Done Enable 7 1 read-write SCANTABLEDONE Scan Table Done Enable 8 1 read-write SINGLEDONE Single Conversion Done Enable 9 1 read-write POLARITYERR Polarity Error Enable 12 1 read-write PORTALLOCERR Port Allocation Error Enable 13 1 read-write SINGLEFIFOOF Single FIFO Overflow Enable 16 1 read-write SCANFIFOOF Scan FIFO Overflow Enable 17 1 read-write SINGLEFIFOUF Single FIFO Underflow Enable 18 1 read-write SCANFIFOUF Scan FIFO Underflow Enable 19 1 read-write EM23ABORTERROR EM2/3 Abort Error Enable 31 1 read-write TRIGGER Trigger 0x02C read-write 0x00000000 0x00011717 SCANTRIGSEL Scan Trigger Select 0 3 read-write IMMEDIATE Immediate triggering. The scan queue will be disabled once all conversions in the scan table are complete, unless TRIGGERACTION is set to continuous. 0 TIMER Triggers when the local timer count reaches zero. 1 PRSCLKGRP Triggers on PRS0 from a timer module that is using the same clock group as the ADC and has been programmed to use the same clock source as the ADC. The prescale may be different between the ADC and the timer module. 2 PRSPOS Triggers on asynchronous PRS0 positive edge. Requires PRS0 to go low for 3 ADC_CLKs before another positive edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. 3 PRSNEG Triggers on asynchronous PRS0 negative edge. Requires PRS0 to go high for 3 ADC_CLKs before another negative edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. PRSNEG should only be used when the trigger source is from a module that remains powered during EM23. For modules (ie: TIMER) that power down during EM23, PRSPOS should be used for an asynchronous trigger, and PRSCLKGRP should be used for a synchronous trigger. 4 SCANTRIGACTION Scan Trigger Action 4 1 read-write ONCE For TRIGSEL=IMMEDIATE, goes through the scan table once and disables queue. For TRIGSEL = TIMER, PRSCLKGRP, PRSPOS, PRSNEG, goes through the scan table once per trigger. 0 CONTINUOUS Goes through the scan table, converts each entry with a mask bit set, and puts it back into the scan queue to repeat again continuously. The queues are first come first serve. If both queues are triggered, the single queue will get to convert after each scan table completes. The scan queue will get to convert after each single conversion completes. 1 SINGLETRIGSEL Single Trigger Select 8 3 read-write IMMEDIATE Immediate triggering. The single queue will be disabled once the conversion is complete, unless TRIGGERACTION is set to continuous. 0 TIMER Triggers when the local timer count reaches zero. 1 PRSCLKGRP Triggers on PRS1 from a timer module that is using the same clock group as the ADC and has been programmed to use the same clock source as the ADC. The prescale may be different between the ADC and the timer module. 2 PRSPOS Triggers on asynchronous PRS1 positive edge. Requires PRS1 to go low for 3 ADC_CLKs before another positive edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. 3 PRSNEG Triggers on asynchronous PRS1 negative edge. Requires PRS1 to go high for 3 ADC_CLKs before another negative edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. PRSNEG should only be used when the trigger source is from a module that remains powered during EM23. For modules (ie: TIMER) that power down during EM23, PRSPOS should be used for an asynchronous trigger, and PRSCLKGRP should be used for a synchronous trigger. 4 SINGLETRIGACTION Single Trigger Action 12 1 read-write ONCE For TRIGSEL=IMMEDIATE, converts the single queue once and disables queue. For TRIGSEL = TIMER, PRSCLKGRP, PRSPOS, PRSNEG, converts the single queue once per trigger.ask. 0 CONTINUOUS Converts the single queue, then checks for a pending scan queue before converting the single queue again continuously. The queues are first come first serve. If both queues are continuous, the IADC alternates between them. 1 SINGLETAILGATE Single Tailgate Enable 16 1 read-write TAILGATEOFF The single queue is ready to start warming up and converting once the trigger had been detected. 0 TAILGATEON After the single queue's trigger is detected, it must wait until the end of a scan operation before the Single queue can be converted. 1 CFG0 Configration 0x048 read-write 0x00002060 0x30E770FF ADCMODE ADC Mode 0 2 read-write NORMAL High speed mode with a maximum CLK_ADC of 10 MHz. 0 OSRHS High Speed OSR 2 3 read-write HISPD2 High speed over sampling of 2x. 0 HISPD4 High speed over sampling of 4x. 1 HISPD8 High speed over sampling of 8x. 2 HISPD16 High speed over sampling of 16x. 3 HISPD32 HIgh speed over sampling of 32x. 4 HISPD64 High speed over sampling of 64x. 5 ANALOGGAIN Analog Gain 12 3 read-write ANAGAIN0P5 Analog gain of 0.5x. 1 ANAGAIN1 Analog gain of 1x. 2 ANAGAIN2 Analog gain of 2x. 3 ANAGAIN3 Analog gain of 3x. 4 ANAGAIN4 Analog gain of 4x. 5 REFSEL Reference Select 16 3 read-write VBGR Internal 1.21 V reference. 0 VREF External Reference. (Calibrated for 1.25V nominal.) 1 VDDX AVDD (unbuffered) 3 VDDX0P8BUF AVDD (buffered) * 0.8 4 DIGAVG Digital Averaging 21 3 read-write AVG1 Collect one output word (no digital averaging). 0 AVG2 Collect and average 2 digital output words. 1 AVG4 Collect and average 4 digital output words. 2 AVG8 Collect and average 8 digital output words. 3 AVG16 Collect and average 16 digital output words. 4 TWOSCOMPL Two's Complement 28 2 read-write AUTO Automatic: Single ended measurements are reported as unipolar and differential measurements are reported as bipolar. 0 FORCEUNIPOLAR Force all measurements to result in unipolar output. Negative differential numbers will saturate to 0. 1 FORCEBIPOLAR Force all measurements to result in bipolar output. Single ended measurements are half the range, but allow for small negative measurements. 2 SCALE0 Scale 0x050 read-write 0x8002C000 0xFFFFFFFF OFFSET Offset 0 18 read-write GAIN13LSB Gain 13 LSBs 18 13 read-write GAIN3MSB Gain 3 MSBs 31 1 read-write GAIN011 Upper 3 bits of gain = 011 (0.75x) 0 GAIN100 Upper 3 bits of gain = 100 (1.00x) 1 SCHED0 Scheduling 0x054 read-write 0x00000000 0x000003FF PRESCALE Prescale 0 10 read-write CFG1 Configration 0x058 read-write 0x00002060 0x30E770FF ADCMODE ADC Mode 0 2 read-write NORMAL High speed mode with a maximum CLK_ADC of 10 MHz. 0 OSRHS High Speed OSR 2 3 read-write HISPD2 High speed over sampling of 2x. 0 HISPD4 High speed over sampling of 4x. 1 HISPD8 High speed over sampling of 8x. 2 HISPD16 High speed over sampling of 16x. 3 HISPD32 HIgh speed over sampling of 32x. 4 HISPD64 High speed over sampling of 64x. 5 ANALOGGAIN Analog Gain 12 3 read-write ANAGAIN0P5 Analog gain of 0.5x. 1 ANAGAIN1 Analog gain of 1x. 2 ANAGAIN2 Analog gain of 2x. 3 ANAGAIN3 Analog gain of 3x. 4 ANAGAIN4 Analog gain of 4x. 5 REFSEL Reference Select 16 3 read-write VBGR Internal 1.21 V reference. 0 VREF External Reference. (Calibrated for 1.25V nominal.) 1 VDDX AVDD (unbuffered) 3 VDDX0P8BUF AVDD (buffered) * 0.8 4 DIGAVG Digital Averaging 21 3 read-write AVG1 Collect one output word (no digital averaging). 0 AVG2 Collect and average 2 digital output words. 1 AVG4 Collect and average 4 digital output words. 2 AVG8 Collect and average 8 digital output words. 3 AVG16 Collect and average 16 digital output words. 4 TWOSCOMPL Two's Complement 28 2 read-write AUTO Automatic: Single ended measurements are reported as unipolar and differential measurements are reported as bipolar. 0 FORCEUNIPOLAR Force all measurements to result in unipolar output. Negative differential numbers will saturate to 0. 1 FORCEBIPOLAR Force all measurements to result in bipolar output. Single ended measurements are half the range, but allow for small negative measurements. 2 SCALE1 Scale 0x060 read-write 0x8002C000 0xFFFFFFFF OFFSET Offset 0 18 read-write GAIN13LSB Gain 13 LSBs 18 13 read-write GAIN3MSB Gain 3 MSBs 31 1 read-write GAIN011 Upper 3 bits of gain = 011 (0.75x) 0 GAIN100 Upper 3 bits of gain = 100 (1.00x) 1 SCHED1 Scheduling 0x064 read-write 0x00000000 0x000003FF PRESCALE Prescale 0 10 read-write SINGLEFIFOCFG Single FIFO Configuration 0x070 read-write 0x00000030 0x0000013F ALIGNMENT Alignment 0 3 read-write RIGHT12 ID[7:0], SIGN_EXT, DATA[11:0] 0 RIGHT16 ID[7:0], SIGN_EXT, DATA[15:0] 1 RIGHT20 ID[7:0], SIGN_EXT, DATA[19:0] 2 LEFT12 DATA[11:0], 000000000000, ID[7:0] 3 LEFT16 DATA[15:0], 00000000, ID[7:0] 4 LEFT20 DATA[19:0], 0000, ID[7:0] 5 SHOWID Show ID 3 1 read-write DVL Data Valid Level 4 2 read-write VALID1 When 1 entry in the single FIFO is valid, set the SINGLEFIFODVL interrupt and request DMA. 0 VALID2 When 2 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 1 VALID3 When 3 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 2 VALID4 When 4 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 3 DMAWUFIFOSINGLE Single FIFO DMA wakeup. 8 1 read-write DISABLED While in EM2 or EM3, the DMA controller will not be requested. 0 ENABLED While in EM2 or EM3, the DMA controller will be requested when the single FIFO reaches its Data Valid Level. [DVL must be set to 0 (VALID1).] 1 SINGLEFIFODATA Read the oldest valid data from the single FIFO and pop the FIFO 0x074 read-only 0x00000000 0xFFFFFFFF DATA Single FIFO Read Data 0 32 read-only SINGLEFIFOSTAT Single FIFO status 0x078 read-only 0x00000000 0x00000007 FIFOREADCNT FIFO Read Count 0 3 read-only SINGLEDATA latest single queue conversion data 0x07C read-only 0x00000000 0xFFFFFFFF DATA Data 0 32 read-only SCANFIFOCFG Scan FIFO Configuration 0x080 read-write 0x00000030 0x0000013F ALIGNMENT Alignment 0 3 read-write RIGHT12 ID[7:0], SIGN_EXT, DATA[11:0] 0 RIGHT16 ID[7:0], SIGN_EXT, DATA[15:0] 1 RIGHT20 ID[7:0], SIGN_EXT, DATA[19:0] 2 LEFT12 DATA[11:0], 000000000000, ID[7:0] 3 LEFT16 DATA[15:0], 00000000, ID[7:0] 4 LEFT20 DATA[19:0], 0000, ID[7:0] 5 SHOWID Show ID 3 1 read-write DVL Data Valid Level 4 2 read-write VALID1 When 1 entry in the scan FIFO is valid, set the SCANFIFODVL interrupt and request DMA. 0 VALID2 When 2 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA. 1 VALID3 When 3 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA. 2 VALID4 When 4 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA. 3 DMAWUFIFOSCAN Scan FIFO DMA Wakeup 8 1 read-write DISABLED While in EM2 or EM3, the DMA controller will not be requested. 0 ENABLED While in EM2 or EM3, the DMA controller will be requested when the scan FIFO reaches its Data Valid Level. [DVL must be set to 0 (VALID1).] 1 SCANFIFODATA Read the oldest valid data from the scan FIFO and pop the FIFO 0x084 read-only 0x00000000 0xFFFFFFFF DATA Data 0 32 read-only SCANFIFOSTAT Scan FIFO status 0x088 read-only 0x00000000 0x00000007 FIFOREADCNT FIFO Read Count 0 3 read-only SCANDATA Most recent data data from scan queue conversion 0x08C read-only 0x00000000 0xFFFFFFFF DATA Data 0 32 read-only SINGLE No Description 0x098 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN0 No Description 0x0A0 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN1 No Description 0x0A4 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN2 No Description 0x0A8 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN3 No Description 0x0AC read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN4 No Description 0x0B0 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN5 No Description 0x0B4 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN6 No Description 0x0B8 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN7 No Description 0x0BC read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN8 No Description 0x0C0 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN9 No Description 0x0C4 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN10 No Description 0x0C8 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN11 No Description 0x0CC read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN12 No Description 0x0D0 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN13 No Description 0x0D4 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN14 No Description 0x0D8 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN15 No Description 0x0DC read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write I2C0_NS 0 I2C0_NS Registers 0x5A010000 0x00000000 0x00001000 registers I2C0 27 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN module enable 0 1 read-write DISABLE Disable Peripheral Clock 0 ENABLE Enable Peripheral Clock 1 CTRL No Description 0x008 read-write 0x00000000 0x0037B3FF CORERST Soft Reset the internal state registers 0 1 read-write DISABLE No change to internal state registers 0 ENABLE Reset the internal state registers 1 SLAVE Addressable as Follower 1 1 read-write DISABLE All addresses will be responded to with a NACK 0 ENABLE Addresses matching the programmed follower address or the general call address (if enabled) require a response from software. Other addresses are automatically responded to with a NACK. 1 AUTOACK Automatic Acknowledge 2 1 read-write DISABLE Software must give one ACK command for each ACK transmitted on the I2C bus. 0 ENABLE Addresses that are not automatically NACK'ed, and all data is automatically acknowledged. 1 AUTOSE Automatic STOP when Empty 3 1 read-write DISABLE A stop must be sent manually when no more data is to be transmitted. 0 ENABLE The leader automatically sends a STOP when no more data is available for transmission. 1 AUTOSN Automatic STOP on NACK 4 1 read-write DISABLE Stop is not automatically sent if a NACK is received from a follower. 0 ENABLE The leader automatically sends a STOP if a NACK is received from a follower. 1 ARBDIS Arbitration Disable 5 1 read-write DISABLE When a device loses arbitration, the ARBIF interrupt flag is set and the bus is released. 0 ENABLE When a device loses arbitration, the ARBIF interrupt flag is set, but communication proceeds. 1 GCAMEN General Call Address Match Enable 6 1 read-write DISABLE General call address will be NACK'ed if it is not included by the follower address and address mask. 0 ENABLE When a general call address is received, a software response is required 1 TXBIL TX Buffer Interrupt Level 7 1 read-write EMPTY TXBL status and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALF_FULL TXBL status and the TXBL interrupt flag are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full 1 CLHR Clock Low High Ratio 8 2 read-write STANDARD Nlow=4 and Nhigh=4, and the Nlow:Nhigh ratio is 4:4 0 ASYMMETRIC Nlow=6 and Nhigh=3, and the Nlow:Nhigh ratio is 6:3 1 FAST Nlow=11 and Nhigh=6, and the Nlow:Nhigh ratio is 11:6 2 BITO Bus Idle Timeout 12 2 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 GIBITO Go Idle on Bus Idle Timeout 15 1 read-write DISABLE A bus idle timeout has no effect on the bus state. 0 ENABLE A bus idle timeout tells the I2C module that the bus is idle, allowing new transfers to be initiated. 1 CLTO Clock Low Timeout 16 3 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 I2C320PCC Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout. 4 I2C1024PCC Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout. 5 SCLMONEN SCL Monitor Enable 20 1 read-write DISABLE Disable SCL monitor 0 ENABLE Enable SCL monitor 1 SDAMONEN SDA Monitor Enable 21 1 read-write DISABLE Disable SDA Monitor 0 ENABLE Enable SDA Monitor 1 CMD No Description 0x00C write-only 0x00000000 0x000000FF START Send start condition 0 1 write-only STOP Send stop condition 1 1 write-only ACK Send ACK 2 1 write-only NACK Send NACK 3 1 write-only CONT Continue transmission 4 1 write-only ABORT Abort transmission 5 1 write-only CLEARTX Clear TX 6 1 write-only CLEARPC Clear Pending Commands 7 1 write-only STATE No Description 0x010 read-only 0x00000001 0x000000FF BUSY Bus Busy 0 1 read-only MASTER Leader 1 1 read-only TRANSMITTER Transmitter 2 1 read-only NACKED Nack Received 3 1 read-only BUSHOLD Bus Held 4 1 read-only STATE Transmission State 5 3 read-only IDLE No transmission is being performed. 0 WAIT Waiting for idle. Will send a start condition as soon as the bus is idle. 1 START Start transmit phase 2 ADDR Address transmit or receive phase 3 ADDRACK Address ack/nack transmit or receive phase 4 DATA Data transmit or receive phase 5 DATAACK Data ack/nack transmit or receive phase 6 STATUS No Description 0x014 read-only 0x00000080 0x00000FFF PSTART Pending START 0 1 read-only PSTOP Pending STOP 1 1 read-only PACK Pending ACK 2 1 read-only PNACK Pending NACK 3 1 read-only PCONT Pending continue 4 1 read-only PABORT Pending abort 5 1 read-only TXC TX Complete 6 1 read-only TXBL TX Buffer Level 7 1 read-only RXDATAV RX Data Valid 8 1 read-only RXFULL RX FIFO Full 9 1 read-only TXBUFCNT TX Buffer Count 10 2 read-only CLKDIV No Description 0x018 read-write 0x00000000 0x000001FF DIV Clock Divider 0 9 read-write SADDR No Description 0x01C read-write 0x00000000 0x000000FE ADDR Follower address 1 7 read-write SADDRMASK No Description 0x020 read-write 0x00000000 0x000000FE SADDRMASK Follower Address Mask 1 7 read-write RXDATA No Description 0x024 read-only 0x00000000 0x000000FF RXDATA RX Data 0 8 read-only RXDOUBLE No Description 0x028 read-only 0x00000000 0x0000FFFF RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDATAP No Description 0x02C read-only 0x00000000 0x000000FF RXDATAP RX Data Peek 0 8 read-only RXDOUBLEP No Description 0x030 read-only 0x00000000 0x0000FFFF RXDATAP0 RX Data 0 Peek 0 8 read-only RXDATAP1 RX Data 1 Peek 8 8 read-only TXDATA No Description 0x034 write-only 0x00000000 0x000000FF TXDATA TX Data 0 8 write-only TXDOUBLE No Description 0x038 write-only 0x00000000 0x0000FFFF TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only IF No Description 0x03C read-write 0x00000000 0x001FFFFF START START condition Interrupt Flag 0 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write ADDR Address Interrupt Flag 2 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write ACK Acknowledge Received Interrupt Flag 6 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write MSTOP Leader STOP Condition Interrupt Flag 8 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write SSTOP Follower STOP condition Interrupt Flag 16 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write IEN No Description 0x040 read-write 0x00000000 0x001FFFFF START START condition Interrupt Flag 0 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write ADDR Address Interrupt Flag 2 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write ACK Acknowledge Received Interrupt Flag 6 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write MSTOP Leader STOP Condition Interrupt Flag 8 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write SSTOP Follower STOP condition Interrupt Flag 16 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write WDOG0_NS 0 WDOG0_NS Registers 0x5A018000 0x00000000 0x00001000 registers WDOG0 43 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Module Enable 0 1 read-write CFG No Description 0x008 read-write 0x000F0000 0x730F071F CLRSRC WDOG Clear Source 0 1 read-write SW A write to the clear bit will clear the WDOG counter 0 PRSSRC0 A rising edge on the PRS Source 0 will clear the WDOG counter 1 EM2RUN EM2 Run 1 1 read-write DISABLE WDOG timer is frozen in EM2. 0 ENABLE WDOG timer is running in EM2. 1 EM3RUN EM3 Run 2 1 read-write DISABLE WDOG timer is frozen in EM3. 0 ENABLE WDOG timer is running in EM3. 1 EM4BLOCK EM4 Block 3 1 read-write DISABLE EM4 can be entered by software. See EMU for detailed description. 0 ENABLE EM4 cannot be entered by software. 1 DEBUGRUN Debug Mode Run 4 1 read-write DISABLE WDOG timer is frozen in debug mode 0 ENABLE WDOG timer is running in debug mode 1 WDOGRSTDIS WDOG Reset Disable 8 1 read-write EN A timeout will cause a WDOG reset 0 DIS A timeout will not cause a WDOG reset 1 PRS0MISSRSTEN PRS Src0 Missing Event WDOG Reset 9 1 read-write PRS1MISSRSTEN PRS Src1 Missing Event WDOG Reset 10 1 read-write PERSEL WDOG Timeout Period Select 16 4 read-write SEL0 Timeout period of 9 wdog cycles 0 SEL1 Timeout period of 17 wdog cycles 1 SEL2 Timeout period of 33 wdog cycles 2 SEL3 Timeout period of 65 wdog cycles 3 SEL4 Timeout period of 129 wdog cycles 4 SEL5 Timeout period of 257 wdog cycles 5 SEL6 Timeout period of 513 wdog cycles 6 SEL7 Timeout period of 1k wdog cycles 7 SEL8 Timeout period of 2k wdog cycles 8 SEL9 Timeout period of 4k wdog cycles 9 SEL10 Timeout period of 8k wdog cycles 10 SEL11 Timeout period of 16k wdog cycles 11 SEL12 Timeout period of 32k wdog cycles 12 SEL13 Timeout period of 64k wdog cycles 13 SEL14 Timeout period of 128k wdog cycles 14 SEL15 Timeout period of 256k wdog cycles 15 WARNSEL WDOG Warning Period Select 24 2 read-write DIS Disable 0 SEL1 Warning timeout is 25% of the Timeout. 1 SEL2 Warning timeout is 50% of the Timeout. 2 SEL3 Warning timeout is 75% of the Timeout. 3 WINSEL WDOG Illegal Window Select 28 3 read-write DIS Disabled. 0 SEL1 Window timeout is 12.5% of the Timeout. 1 SEL2 Window timeout is 25% of the Timeout. 2 SEL3 Window timeout is 37.5% of the Timeout. 3 SEL4 Window timeout is 50% of the Timeout. 4 SEL5 Window timeout is 62.5% of the Timeout. 5 SEL6 Window timeout is 75.5% of the Timeout. 6 SEL7 Window timeout is 87.5% of the Timeout. 7 CMD No Description 0x00C write-only 0x00000000 0x00000001 CLEAR WDOG Timer Clear 0 1 write-only UNCHANGED WDOG timer is unchanged. 0 CLEARED WDOG timer is cleared to 0. 1 STATUS No Description 0x014 read-only 0x00000000 0x80000000 LOCK WDOG Configuration Lock Status 31 1 read-only UNLOCKED All WDOG lockable registers are unlocked. 0 LOCKED All WDOG lockable registers are locked. 1 IF No Description 0x018 read-write 0x00000000 0x0000001F TOUT WDOG Timeout Interrupt Flag 0 1 read-write WARN WDOG Warning Timeout Interrupt Flag 1 1 read-write WIN WDOG Window Interrupt Flag 2 1 read-write PEM0 PRS Src0 Event Missing Interrupt Flag 3 1 read-write PEM1 PRS Src1 Event Missing Interrupt Flag 4 1 read-write IEN No Description 0x01C read-write 0x00000000 0x0000001F TOUT WDOG Timeout Interrupt Enable 0 1 read-write WARN WDOG Warning Timeout Interrupt Enable 1 1 read-write WIN WDOG Window Interrupt Enable 2 1 read-write PEM0 PRS Src0 Event Missing Interrupt Enable 3 1 read-write PEM1 PRS Src1 Event Missing Interrupt Enable 4 1 read-write LOCK No Description 0x020 write-only 0x0000ABE8 0x0000FFFF LOCKKEY WDOG Configuration Lock 0 16 write-only LOCK Lock WDOG lockable registers 0 UNLOCK Unlock WDOG lockable registers 44008 SYNCBUSY No Description 0x024 read-only 0x00000000 0x00000001 CMD Sync Busy for Cmd Register 0 1 read-only AMUXCP0_NS 1 AMUXCP0_NS Registers 0x5A020000 0x00000000 0x00001000 registers IPVERSION IPVERSION 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IPVERSION 0 32 read-only CTRL Control 0x008 read-write 0x00000000 0x00000033 FORCEHP Force High Power 0 1 read-write FORCELP Force Low Power 1 1 read-write FORCERUN Force run 4 1 read-write FORCESTOP Force stop 5 1 read-write STATUS Status 0x00C read-only 0x00000000 0x00000003 RUN running 0 1 read-only HICAP high cap 1 1 read-only TEST Test 0x010 read-write 0x00000000 0x80003313 SYNCCLK Sync Clock 0 1 read-write SYNCMODE Sync Mode 1 1 read-write FORCEREQUEST Force Request 4 1 read-write FORCEHICAP Force high capacitance driver 8 1 read-write FORCELOCAP Force low capacitance driver 9 1 read-write FORCEBOOSTON Force Boost On 12 1 read-write FORCEBOOSTOFF Force Boost Off 13 1 read-write STATUSEN Enable write to status bits 31 1 read-write TRIM Trim 0x014 read-write 0x77E44AA1 0x77FFEFFF WARMUPTIME Warm up time 0 2 read-write WUCYCLES72 Warm up cycle = 72; 3.6us @20 MHz 0 WUCYCLES96 Warm up cycle = 96; 4.8us @ 20 MHz 1 WUCYCLES128 Warm up cycle = 128; 6.4us @ 20 MHz 2 WUCYCLES160 Warm up cycle = 160; 8.0us @ 20 MHz 3 FLOATVDDCPLO Float VDDCP Low Power 2 1 read-write FLOATVDDCPHI Float VDDCP High Power 3 1 read-write BYPASSDIV2LO Bypass Div2 Low Power 4 1 read-write BYPASSDIV2HI Bypass Div2 High Power 5 1 read-write BUMP0P5XLO Bump 0.5X Low Power 6 1 read-write BUMP0P5XHI Bump 0.5X High Power 7 1 read-write BIAS2XLO Bias 2x Low Power 8 1 read-write BIAS2XHI Bias 2x High Power 9 1 read-write VOLTAGECTRLLO Charge Pump Voltage Control Low Power 10 2 read-write VOLTAGECTRLHI Charge Pump Voltage Control High Power 13 2 read-write BIASCTRLLO Bias Control Low Power 15 3 read-write BIASCTRLLOCONT Bias Control Low Power Continuous 18 3 read-write BIASCTRLHI Bias Control High Power 21 3 read-write PUMPCAPLO Pump Cap Low Power 24 3 read-write PUMPCAPHI Pump Cap High Power 28 3 read-write EUART0_NS 0 EUART0_NS Registers 0x5A030000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Module enable 0 1 read-write CFG0 No Description 0x008 read-write 0x00000000 0xC1D264FE LOOPBK Loopback Enable 1 1 read-write DISABLE The receiver is connected to and receives data from UARTn_RX 0 ENABLE The receiver is connected to and receives data from UARTn_TX 1 CCEN Collision Check Enable 2 1 read-write DISABLE Collision check is disabled 0 ENABLE Collision check is enabled. The receiver must be enabled for the check to be performed 1 MPM Multi-Processor Mode 3 1 read-write DISABLE The 9th bit of incoming frames has no special function 0 ENABLE An incoming frame with the 9th bit equal to MPAB will be loaded into the RX FIFO regardless of RXBLOCK and will result in the MPAB interrupt flag being set 1 MPAB Multi-Processor Address-Bit 4 1 read-write OVS Oversampling 5 3 read-write X16 16X oversampling 0 X8 8X oversampling 1 X6 6X oversampling 2 X4 4X oversampling 3 DISABLE Disable oversampling (for LF operation) 4 MSBF Most Significant Bit First 10 1 read-write DISABLE Data is sent with the least significant bit first 0 ENABLE Data is sent with the most significant bit first 1 RXINV Receiver Input Invert 13 1 read-write DISABLE Input is passed directly to the receiver 0 ENABLE Input is inverted before it is passed to the receiver 1 TXINV Transmitter output Invert 14 1 read-write DISABLE Output from the transmitter is passed unchanged to UARTn_TX 0 ENABLE Output from the transmitter is inverted before it is passed to UARTn_TX 1 AUTOTRI Automatic TX Tristate 17 1 read-write DISABLE The output on UARTn_TX when the transmitter is idle is defined by TXINV 0 ENABLE UARTn_TX is tristated whenever the transmitter is idle 1 SKIPPERRF Skip Parity Error Frames 20 1 read-write ERRSDMA Halt DMA Read On Error 22 1 read-write DISABLE Framing and parity errors have no effect on DMA requests from the UART 0 ENABLE DMA requests from the UART are blocked while the PERR or FERR interrupt flags are set 1 ERRSRX Disable RX On Error 23 1 read-write DISABLE Framing and parity errors have no effect on receiver 0 ENABLE Framing and parity errors disable the receiver 1 ERRSTX Disable TX On Error 24 1 read-write DISABLE Received framing and parity errors have no effect on transmitter 0 ENABLE Received framing and parity errors disable the transmitter 1 MVDIS Majority Vote Disable 30 1 read-write AUTOBAUDEN AUTOBAUD detection enable 31 1 read-write CFG1 No Description 0x00C read-write 0x00000000 0x00DB8E0F DBGHALT Debug halt 0 1 read-write DISABLE Continue normal UART operation even if core is halted 0 ENABLE If core is halted, receive one frame and then halt reception by deactivating RTS. Next frame reception happens when the core is unhalted during single stepping. 1 CTSINV Clear-to-send Invert Enable 1 1 read-write DISABLE The CTS pin is active low 0 ENABLE The CTS pin is active high 1 CTSEN Clear-to-send Enable 2 1 read-write DISABLE Ignore CTS 0 ENABLE Stop transmitting when CTS is inactive 1 RTSINV Request-to-send Invert Enable 3 1 read-write DISABLE The RTS pin is active low 0 ENABLE The RTS pin is active high 1 TXDMAWU Transmitter DMA Wakeup 9 1 read-write RXDMAWU Receiver DMA Wakeup 10 1 read-write SFUBRX Start Frame Unblock Receiver 11 1 read-write RXPRSEN PRS RX Enable 15 1 read-write TXFIW TX FIFO Interrupt Watermark 16 2 read-write ONEFRAME TXFL status flag and IF are set when the TX FIFO has space for at least one more frame. 0 TWOFRAMES TXFL status flag and IF are set when the TX FIFO has space for at least two more frames. 1 THREEFRAMES TXFL status flag and IF are set when the TX FIFO has space for at least three more frames. 2 FOURFRAMES TXFL status flag and IF are set when the TX FIFO has space for at least four more frames. 3 RXFIW RX FIFO Interrupt Watermark 19 2 read-write ONEFRAME RXFL status flag and IF are set when the RX FIFO has at least one frame in it. 0 TWOFRAMES RXFL status flag and IF are set when the RX FIFO has at least two frames in it. 1 THREEFRAMES RXFL status flag and IF are set when the RX FIFO has at least three frames in it. 2 FOURFRAMES RXFL status flag and IF are set when the RX FIFO has four frames in it. 3 RTSRXFW Request-to-send RX FIFO Watermark 22 2 read-write ONEFRAME RTS is set if there is space for at least one more frame in the RX FIFO. 0 TWOFRAMES RTS is set if there is space for at least two more frames in the RX FIFO. 1 THREEFRAMES RTS is set if there is space for at least three more frames in the RX FIFO. 2 FOURFRAMES RTS is set if there is space for four more frames in the RX FIFO. 3 FRAMECFG No Description 0x010 read-write 0x00001002 0x00003303 DATABITS Data-Bit Mode 0 2 read-write SEVEN Each frame contains 7 data bits 1 EIGHT Each frame contains 8 data bits 2 NINE Each frame contains 9 data bits 3 PARITY Parity-Bit Mode 8 2 read-write NONE Parity bits are not used 0 EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. 2 ODD Odd parity is used. Parity bits are automatically generated and checked by hardware. 3 STOPBITS Stop-Bit Mode 12 2 read-write HALF The transmitter generates a half stop bit. Stop-bits are not verified by receiver 0 ONE One stop bit is generated and verified 1 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies the first stop bit 2 TWO The transmitter generates two stop bits. The receiver checks the first stop-bit only 3 IRHFCFG No Description 0x014 read-write 0x00000000 0x0000000F IRHFEN Enable IrDA Module 0 1 read-write IRHFPW IrDA TX Pulse Width 1 2 read-write ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 0 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 2 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 3 IRHFFILT IrDA RX Filter 3 1 read-write DISABLE No filter enabled 0 ENABLE Filter enabled. IrDA pulse must be high for at least 4 consecutive clock cycles to be detected 1 IRLFCFG No Description 0x018 read-write 0x00000000 0x00000001 IRLFEN Pulse Generator/Extender Enable 0 1 read-write TIMINGCFG No Description 0x01C read-write 0x00000000 0x00000003 TXDELAY TX Delay Transmission 0 2 read-write NONE Frames are transmitted immediately. 0 SINGLE Transmission of new frames is delayed by a single bit period. 1 DOUBLE Transmission of new frames is delayed by a two bit periods. 2 TRIPPLE Transmission of new frames is delayed by a three bit periods. 3 STARTFRAMECFG No Description 0x020 read-write 0x00000000 0x000001FF STARTFRAME Start Frame 0 9 read-write SIGFRAMECFG No Description 0x024 read-write 0x00000000 0x000001FF SIGFRAME Signal Frame Value 0 9 read-write CLKDIV No Description 0x028 read-write 0x00000000 0x007FFFF8 DIV Fractional Clock Divider 3 20 read-write TRIGCTRL No Description 0x02C read-write 0x00000000 0x00000003 RXTEN Receive Trigger Enable 0 1 read-write TXTEN Transmit Trigger Enable 1 1 read-write CMD No Description 0x030 write-only 0x00000000 0x000001FF RXEN Receiver Enable 0 1 write-only RXDIS Receiver Disable 1 1 write-only TXEN Transmitter Enable 2 1 write-only TXDIS Transmitter Disable 3 1 write-only RXBLOCKEN Receiver Block Enable 4 1 write-only RXBLOCKDIS Receiver Block Disable 5 1 write-only TXTRIEN Transmitter Tristate Enable 6 1 write-only TXTRIDIS Transmitter Tristate Disable 7 1 write-only CLEARTX Clear TX FIFO 8 1 write-only RXDATA No Description 0x034 read-only 0x00000000 0x000007FF RXDATA RX Data 0 9 read-only PERR Parity Error 9 1 read-only FERR Framing Error 10 1 read-only RXDATAP No Description 0x038 read-only 0x00000000 0x000007FF RXDATAP RX Data Peek 0 9 read-only PERRP Parity Error Peek 9 1 read-only FERRP Framing Error Peek 10 1 read-only TXDATA No Description 0x03C write-only 0x00000000 0x00003FFF TXDATA TX Data 0 9 write-only UBRXAT Unblock RX After Transmission 9 1 write-only TXTRIAT Set TXTRI After Transmisssion 10 1 write-only TXBREAK Transit Data as Break 11 1 write-only TXDISAT Clear TXEN After Transmission 12 1 write-only RXENAT Enable RXEN After Transmission 13 1 write-only STATUS No Description 0x040 read-only 0x00003040 0x010F31FB RXENS Receiver Enable Status 0 1 read-only TXENS Transmitter Enable Status 1 1 read-only RXBLOCK Block Incoming Data 3 1 read-only TXTRI Transmitter Tristated 4 1 read-only TXC TX Complete 5 1 read-only TXFL TX FIFO Level 6 1 read-only RXFL RX FIFO Level 7 1 read-only RXFULL RX FIFO Full 8 1 read-only RXIDLE RX Idle 12 1 read-only TXIDLE TX Idle 13 1 read-only TXFCNT Valid entries in TX FIFO 16 3 read-only CLEARTXBUSY TX FIFO Clear Busy 19 1 read-only AUTOBAUDDONE Auto Baud Rate Detection Completed 24 1 read-only IF No Description 0x044 read-write 0x00000000 0x010C377F TXC TX Complete Interrupt Flag 0 1 read-write TXFL TX FIFO Level Interrupt Flag 1 1 read-write RXFL RX FIFO Level Interrupt Flag 2 1 read-write RXFULL RX FIFO Full Interrupt Flag 3 1 read-write RXOF RX FIFO Overflow Interrupt Flag 4 1 read-write RXUF RX FIFO Underflow Interrupt Flag 5 1 read-write TXOF TX FIFO Overflow Interrupt Flag 6 1 read-write PERR Parity Error Interrupt Flag 8 1 read-write FERR Framing Error Interrupt Flag 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write CCF Collision Check Fail Interrupt Flag 12 1 read-write TXIDLE TX Idle Interrupt Flag 13 1 read-write STARTF Start Frame Interrupt Flag 18 1 read-write SIGF Signal Frame Interrupt Flag 19 1 read-write AUTOBAUDDONE Auto Baud Complete Interrupt Flag 24 1 read-write IEN No Description 0x048 read-write 0x00000000 0x010C377F TXC TX Complete IEN 0 1 read-write TXFL TX FIFO Level IEN 1 1 read-write RXFL RX FIFO Level IEN 2 1 read-write RXFULL RX FIFO Full IEN 3 1 read-write RXOF RX FIFO Overflow IEN 4 1 read-write RXUF RX FIFO Underflow IEN 5 1 read-write TXOF TX FIFO Overflow IEN 6 1 read-write PERR Parity Error IEN 8 1 read-write FERR Framing Error IEN 9 1 read-write MPAF Multi-Processor Addr Frame IEN 10 1 read-write CCF Collision Check Fail IEN 12 1 read-write TXIDLE TX IDLE IEN 13 1 read-write STARTF Start Frame IEN 18 1 read-write SIGF Signal Frame IEN 19 1 read-write AUTOBAUDDONE Auto Baud Complete IEN 24 1 read-write SYNCBUSY No Description 0x04C read-only 0x00000000 0x000007FF DIV SYNCBUSY for DIV in CLKDIV 0 1 read-only RXTEN SYNCBUSY for RXTEN in TRIGCTRL 1 1 read-only TXTEN SYNCBUSY for TXTEN in TRIGCTRL 2 1 read-only RXEN SYNCBUSY for RXEN in CMD 3 1 read-only RXDIS SYNCBUSY for RXDIS in CMD 4 1 read-only TXEN SYNCBUSY for TXEN in CMD 5 1 read-only TXDIS SYNCBUSY for TXDIS in CMD 6 1 read-only RXBLOCKEN SYNCBUSY for RXBLOCKEN in CMD 7 1 read-only RXBLOCKDIS SYNCBUSY for RXBLOCKDIS in CMD 8 1 read-only TXTRIEN SYNCBUSY for TXTRIEN in CMD 9 1 read-only TXTRIDIS SYNCBUSY in TXTRIDIS in CMD 10 1 read-only CRYPTOACC_NS 1 CRYPTOACC_NS Registers 0x5C020000 0x00000000 0x00001000 registers CRYPTOACC 0 TRNG 1 PKE 2 FETCHADDR Fetcher: Start address of data block. In direct mode, this register is written by the software. In scatter-gather mode, this register is updated after each processed descriptor. 0x000 read-write 0x00000000 0xFFFFFFFF ADDR Start address of data block 0 32 read-write FETCHLEN Fetcher: Length of data block. In direct mode, this register is written by the software. In scatter-gather mode, this register is not used. 0x008 read-write 0x00000000 0x3FFFFFFF LENGTH Length of data block 0 28 read-write CONSTADDR Constant address 28 1 read-write REALIGN Realign length 29 1 read-write FETCHTAG Fetcher: User tag. In direct mode, this register is written by the software. In scatter-gather mode, this register is not used. 0x00C read-write 0x00000000 0xFFFFFFFF TAG User tag 0 32 read-write PUSHADDR Pusher: Start address of data block (LSB). In direct mode, this register is written by the software. In scatter-gather mode, this register is updated after each processed descriptor. 0x010 read-write 0x00000000 0xFFFFFFFF ADDR Start address of data block 0 32 read-write PUSHLEN Pusher: Length of data block. In direct mode, this register is written by the software. In scatter-gather mode, this register is not used. 0x018 read-write 0x00000000 0x7FFFFFFF LENGTH Start address of data block 0 28 read-write CONSTADDR Constant address 28 1 read-write REALIGN Realign length 29 1 read-write DISCARD Discard data 30 1 read-write IEN Interrupt enable 0x01C read-write 0x00000000 0x0000003F FETCHERENDOFBLOCK End of block interrupt enable 0 1 read-write FETCHERSTOPPED Stopped interrupt enable 1 1 read-write FETCHERERROR Error interrupt enable 2 1 read-write PUSHERENDOFBLOCK End of block interrupt enable 3 1 read-write PUSHERSTOPPED Stopped interrupt enable 4 1 read-write PUSHERERROR Error interrupt enable 5 1 read-write IF Interrupt flag register 0x028 read-only 0x00000000 0x0000003F FETCHERENDOFBLOCK End of block interrupt flag 0 1 read-only FETCHERSTOPPED Stopped interrupt flag 1 1 read-only FETCHERERROR Error interrupt flag 2 1 read-only PUSHERENDOFBLOCK End of block interrupt flag 3 1 read-only PUSHERSTOPPED Stopped interrupt flag 4 1 read-only PUSHERERROR Error interrupt flag 5 1 read-only IF_CLR Writing a '1' clears the interrupt status. Writing a '0' has no effect. 0x030 write-only 0x00000000 0x0000003F FETCHERENDOFBLOCK End of block interrupt flag clear 0 1 write-only FETCHERSTOPPED Stopped interrupt flag clear 1 1 write-only FETCHERERROR Error interrupt flag clear 2 1 write-only PUSHERENDOFBLOCK End of block interrupt flag clear 3 1 write-only PUSHERSTOPPED Stopped interrupt flag clear 4 1 write-only PUSHERERROR Error interrupt flag clear 5 1 write-only CTRL Control register, called CONFIG in Barco datasheet. 0x034 read-write 0x00000000 0x0000001F FETCHERSCATTERGATHER Fetcher scatter/gather 0 1 read-write PUSHERSCATTERGATHER Pusher scatter/gather 1 1 read-write STOPFETCHER Stop fetcher 2 1 read-write STOPPUSHER Stop pusher 3 1 read-write SWRESET Software reset 4 1 read-write CMD Command register for starting the fetcher and pusher 0x038 write-only 0x00000000 0x00000003 STARTFETCHER Start fetch 0 1 write-only STARTPUSHER Start push 1 1 write-only STATUS Status register 0x03C read-only 0x00000000 0xFFFF0073 FETCHERBSY Fetcher busy 0 1 read-only PUSHERBSY Pusher busy 1 1 read-only NOTEMPTY Not empty flag from input FIFO (fetcher) 4 1 read-only WAITING Pusher waiting for FIFO 5 1 read-only SOFTRSTBSY Software reset busy 6 1 read-only FIFODATANUM Number of data in output FIFO 16 16 read-only INCL_IPS_HW_CFG No Description 0x400 read-only 0x00000611 0x000007FF g_IncludeAES Generic g_IncludeAES value 0 1 read-only g_IncludeAESGCM Generic g_IncludeAESGCM value 1 1 read-only g_IncludeAESXTS Generic g_IncludeAESXTS value 2 1 read-only g_IncludeDES Generic g_IncludeDES value 3 1 read-only g_IncludeHASH Generic g_IncludeHASH value 4 1 read-only g_IncludeChachaPoly Generic g_IncludeChachaPoly value 5 1 read-only g_IncludeSHA3 Generic g_IncludeSHA3 value 6 1 read-only g_IncludeZUC Generic g_IncludeZUC value 7 1 read-only g_IncludeSM4 Generic g_IncludeSM4 value 8 1 read-only g_IncludePKE Generic g_IncludePKE value 9 1 read-only g_IncludeNDRNG Generic g_IncludeNDRNG value 10 1 read-only BA411E_HW_CFG_1 No Description 0x404 read-only 0x0700017F 0x070301FF g_AesModesPoss AES Modes Supported 0 9 read-only g_CS Generic g_CS value 16 1 read-only g_UseMasking Generic g_UseMasking value 17 1 read-only g_Keysize Generic g_Keysize value 24 3 read-only BA411E_HW_CFG_2 No Description 0x408 read-only 0x00000080 0x0000FFFF g_CtrSize Generic g_CtrSize value 0 16 read-only BA413_HW_CFG No Description 0x40C read-only 0x0003007F 0x0007007F g_HashMaskFunc Generic g_HashMaskFunc value 0 7 read-only g_HashPadding Generic g_HashPadding value 16 1 read-only g_HMAC_enabled Generic g_HMAC_enabled value 17 1 read-only g_HashVerifyDigest Generic g_HashVerifyDigest value 18 1 read-only BA418_HW_CFG No Description 0x410 read-only 0x00000001 0x00000001 g_Sha3CtxtEn Generic g_Sha3CtxtEn value 0 1 read-only BA419_HW_CFG No Description 0x414 read-only 0x0000005F 0x0000007F g_SM4ModesPoss Generic g_SM4ModesPoss value 0 7 read-only CRYPTOACC_NS_RNGCTRL 1 CRYPTOACC_NS_RNGCTRL Registers 0x5C021000 0x00000000 0x00001000 registers CRYPTOACC 0 TRNG 1 PKE 2 RNGCTRL No Description 0x000 read-write 0x00040000 0x001FFFFF ENABLE TRNG Module Enable 0 1 read-write DISABLED Module disabled 0 ENABLED Module enabled 1 TESTEN Test Enable 2 1 read-write NOISE Non-determinsitc random number generation 0 TESTDATA Pseudo-random number generation 1 CONDBYPASS Conditioning Bypass 3 1 read-write NORMAL The conditionig function is used 0 BYPASS The conditioning function is bypassed 1 REPCOUNTIEN IRQ enable for Repetition Count Test 4 1 read-write APT64IEN IRQ enable for APT64IF 5 1 read-write APT4096IEN IRQ enable for APT4096IF 6 1 read-write FULLIEN IRQ enable for FIFO full 7 1 read-write SOFTRESET Software Reset 8 1 read-write NORMAL Module not in reset 0 RESET The continuous test, the conditioning function and the FIFO are reset 1 PREIEN IRQ enable for AIS31 prelim. noise alarm 9 1 read-write ALMIEN IRQ enable for AIS31 noise alarm 10 1 read-write FORCERUN Oscillator Force Run 11 1 read-write NORMAL Oscillators will shut down when FIFO is full 0 RUN Oscillators will continue to run even after FIFO is full 1 BYPNIST NIST Start-up Test Bypass. 12 1 read-write NORMAL NIST-800-90B startup test is applied. No data will be written to the FIFO until the test passes. 0 BYPASS NIST-800-90B startup test is bypassed. 1 BYPAIS31 AIS31 Start-up Test Bypass. 13 1 read-write NORMAL AIS31 startup test is applied. No data will be written to the FIFO until the test passes. 0 BYPASS AIS31 startup test is bypassed. 1 HEALTHTESTSEL Health test input select 14 1 read-write BEFORE Before conditioning 0 AFTER After conditioning 1 AIS31TESTSEL AIS31 test input select 15 1 read-write BEFORE Before conditioning 0 AFTER After conditioning 1 NB128BITBLOCKS Number of 128b blocks in AES-CBCMAC 16 4 read-write FIFOWRSTARTUP Fifo Write Start Up 20 1 read-write FIFOLEVEL Number of 32 bits words of random available in the FIFO. Writing to this register clears the FIFO full interrupt 0x004 read-only 0x00000000 0xFFFFFFFF FIFOLEVEL FIFO Level 0 32 read-only FIFOTHRESH FIFO level at which the rings are restarted when in the FIFOFull_Off state, expressed in number of 128bit blocks 0x008 read-only 0x0000003F 0xFFFFFFFF FIFOTHRESH FIFO threshold level 0 32 read-only FIFODEPTH Maximum number of 32 bits words that can be stored in the FIFO: 2^g_fifodepth 0x00C read-only 0x00000040 0xFFFFFFFF FIFODEPTH FIFO Depth. 0 32 read-only KEY0 This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011... 0x010 read-write 0x00000000 0xFFFFFFFF KEY Key 0 32 read-write KEY1 This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011... 0x014 read-write 0x00000000 0xFFFFFFFF KEY Key 0 32 read-write KEY2 This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011... 0x018 read-write 0x00000000 0xFFFFFFFF KEY Key 0 32 read-write KEY3 This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011... 0x01C read-write 0x00000000 0xFFFFFFFF KEY Key 0 32 read-write TESTDATA This register is used to feed known data to the conditioning function or to the continuous tests. See manual 0x020 write-only 0x00000000 0xFFFFFFFF VALUE Test data input to conditioning tests 0 32 write-only RNGSTATUS No Description 0x030 read-write 0x00000000 0x000007FF TESTDATABUSY Test Data Busy 0 1 read-only IDLE TESTDATA write is finished processing or no test in progress. 0 BUSY TESTDATA write is still being processed. 1 STATE State of the control FSM 1 3 read-only RESET RESET State 0 STARTUP STARTUP State 1 FIFOFULLON FIFOFULLON State 2 FIFOFULLOFF FIFOFULLOFF State 3 RUNNING RUNNING State 4 ERROR ERROR State 5 UNUSED_6 UNUSED 6 UNUSED_7 UNUSED 7 REPCOUNTIF Repetition Count Test interrupt status 4 1 read-only APT64IF 64-sample window Adaptive Proportion IF 5 1 read-only APT4096IF 4096-sample window Adaptive Prop. IF 6 1 read-only FULLIF FIFO full interrupt status 7 1 read-only PREIF AIS31 Preliminary Noise Alarm IF 8 1 read-write ALMIF AIS31 Noise Alarm interrupt status 9 1 read-only INITWAITVAL No Description 0x034 read-write 0x0000FFFF 0x0000FFFF INITWAITVAL Wait counter value 0 16 read-write SWOFFTMRVAL Number of clk cycles to wait before stopping the rings after the FIFO is full 0x040 read-write 0x0000FFFF 0x0000FFFF SWOFFTMRVAL Switch Off Timer Value 0 16 read-write CLKDIV Sample clock divider. The frequency at which the outputs of the rings are sampled is given by Fs = Fpclk/(ClkDiv + 1) 0x044 read-write 0x00000000 0x000000FF VALUE Sample clock divider 0 8 read-write AIS31CONF0 No Description 0x048 read-write 0x43401040 0x7FFF7FFF STARTUPTHRES Start-up Threshold 0 15 read-write ONLINETHRESH Online Threshold 16 15 read-write AIS31CONF1 No Description 0x04C read-write 0x03C00680 0x7FFF7FFF HEXPECTEDVALUE Expected History Value 0 15 read-write ONLINEREPTHRESH Online Repeat Threshold 16 15 read-write AIS31CONF2 No Description 0x050 read-write 0x04400340 0x7FFF7FFF HMIN Minimum Allowed History Value 0 15 read-write HMAX Maximum Allowed History Value 16 15 read-write AIS31STATUS This register is used to obtain diagnostic information about the AIS31 start-up and online tests when g_AIS31=True. Writing to this register clears all fields 0x054 read-write 0x00000000 0x0003FFFF NUMPRELIMALARMS Number of preliminary alarms 0 16 read-write PRELIMNOISEALARMRNG Preliminary noise alarm RNG 16 1 read-write PRELIMNOISEALARMREP Preliminary noise alarm Rep 17 1 read-write CRYPTOACC_NS_PKCTRL 1 CRYPTOACC_NS_PKCTRL Registers 0x5C022000 0x00000000 0x00001000 registers CRYPTOACC 0 TRNG 1 PKE 2 POINTER No Description 0x000 read-write 0x00000000 0x0F0F0F0F OPPTRA OpPtrA 0 4 read-write OPPTRB OpPtrB 8 4 read-write OPPTRC OpPtrC 16 4 read-write OPPTRN OpPtrN 24 4 read-write COMMAND No Description 0x004 read-write 0x00000000 0xFC77FFFF OPERATION Type of Operation 0 7 read-write FIELD Field 7 1 read-write GFP Field is GF(p) 0 GF2M Field is GF(2^m) 1 SIZE Size of Operands in data memory 8 11 read-write SELCURVE Select Curve 20 3 read-write NONE No acceleration 0 P256 P256 1 P192 P192 4 EDWARDS Edwards Curve Enable 26 1 read-write BUFSEL Buffer Select 27 1 read-write MEM0 use data in data memory 0 0 SWAPBYTES Swap bytes 28 1 read-write NATIVE Native format (little endian) 0 SWAPPED Byte swapped (big endian) 1 FLAGA Flag A 29 1 read-write FLAGB Flag B 30 1 read-write CALCR2 Calculate R2 31 1 read-write FALSE don't recalculate R² mod N 0 TRUE re-calculate R² mod N 1 PKCTRL No Description 0x008 write-only 0x00000000 0x00000003 PKSTART PK Start 0 1 write-only IFC ClearIRQ 1 1 write-only PKSTATUS No Description 0x00C read-only 0x00000000 0x00033FFF FAILADDR Fail Address 0 4 read-only NOTONCURVE Point Px not on curve 4 1 read-only ATINFINITY Point Px at infinity 5 1 read-only COUPLENOTVALID Couple not valid 6 1 read-only PARAMNNOTVALID Param n not valid 7 1 read-only NOTIMPLEMENTED Not implemented 8 1 read-only SIGNOTVALID Signature not valid 9 1 read-only PARAMABNOTVALID Param AB not valid 10 1 read-only NOTINVERTIBLE Not invertible 11 1 read-only COMPOSITE Composite 12 1 read-only FALSE random number under test is probably prime 0 TRUE random number under test is composite 1 NOTQUAD Not quadratic residue 13 1 read-only PKBUSY PK busy 16 1 read-only PKIF Interrupt status 17 1 read-only VERSION No Description 0x010 read-only 0x00000000 0x0000FFFF SW Software version number 0 8 read-only HW Hardware version number 8 8 read-only TIMER No Description 0x014 read-only 0x00000000 0xFFFFFFFF TIMER Timer 0 32 read-only PRORTC_S 1 PRORTC_S Registers 0xA8000000 0x00000000 0x00001000 registers PRORTC 41 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP VERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN RTCC Enable 0 1 read-write CFG No Description 0x008 read-write 0x00000000 0x000000FF DEBUGRUN Debug Mode Run Enable 0 1 read-write X0 RTCC is frozen in debug mode 0 X1 RTCC is running in debug mode 1 PRECNTCCV0TOP Pre-counter CCV0 top value enable. 1 1 read-write CNTCCV1TOP CCV1 top value enable 2 1 read-write CNTTICK Counter prescaler mode. 3 1 read-write PRESC CNT register ticks according to configuration in CNTPRESC. 0 CCV0MATCH CNT register ticks when PRECNT matches RTCC_CC0_OC[14:0] 1 CNTPRESC Counter prescaler value. 4 4 read-write DIV1 CLK_CNT = (RTCC LF CLK)/1 0 DIV2 CLK_CNT = (RTCC LF CLK)/2 1 DIV4 CLK_CNT = (RTCC LF CLK)/4 2 DIV8 CLK_CNT = (RTCC LF CLK)/8 3 DIV16 CLK_CNT = (RTCC LF CLK)/16 4 DIV32 CLK_CNT = (RTCC LF CLK)/32 5 DIV64 CLK_CNT = (RTCC LF CLK)/64 6 DIV128 CLK_CNT = (RTCC LF CLK)/128 7 DIV256 CLK_CNT = (RTCC LF CLK)/256 8 DIV512 CLK_CNT = (RTCC LF CLK)/512 9 DIV1024 CLK_CNT = (RTCC LF CLK)/1024 10 DIV2048 CLK_CNT = (RTCC LF CLK)/2048 11 DIV4096 CLK_CNT = (RTCC LF CLK)/4096 12 DIV8192 CLK_CNT = (RTCC LF CLK)/8192 13 DIV16384 CLK_CNT = (RTCC LF CLK)/16384 14 DIV32768 CLK_CNT = (RTCC LF CLK)/32768 15 CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start RTCC main counter 0 1 write-only STOP Stop RTCC main counter 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x00000003 RUNNING RTCC running status 0 1 read-only RTCCLOCKSTATUS Lock Status 1 1 read-only UNLOCKED RTCC registers are unlocked 0 LOCKED RTCC registers are locked 1 IF No Description 0x014 read-write 0x00000000 0x000000FF OF Overflow Interrupt Flag 0 1 read-write CNTTICK Main counter tick 1 1 read-write CC0 CC Channel n Interrupt Flag 4 1 read-write CC1 CC Channel n Interrupt Flag 6 1 read-write IEN No Description 0x018 read-write 0x00000000 0x000000FF OF OF Interrupt Enable 0 1 read-write CNTTICK CNTTICK Interrupt Enable 1 1 read-write CC0 CC Channel n Interrupt Enable 4 1 read-write CC1 CC Channel n Interrupt Enable 6 1 read-write PRECNT No Description 0x01C read-write 0x00000000 0x00007FFF PRECNT Pre-Counter Value 0 15 read-write CNT No Description 0x020 read-write 0x00000000 0xFFFFFFFF CNT Counter Value 0 32 read-write COMBCNT No Description 0x024 read-only 0x00000000 0xFFFFFFFF PRECNT Pre-Counter Value 0 15 read-only CNTLSB Counter Value 15 17 read-only SYNCBUSY No Description 0x028 read-only 0x00000000 0x0000000F START Sync busy for START 0 1 read-only STOP Sync busy for STOP 1 1 read-only PRECNT Sync busy for PRECNT 2 1 read-only CNT Sync busy for CNT 3 1 read-only LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write to unlock RTCC lockable registers 44776 CC0_CTRL No Description 0x030 read-write 0x00000000 0x000000FF MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 CC0_OCVALUE No Description 0x034 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC0_ICVALUE No Description 0x038 read-only 0x00000000 0xFFFFFFFF IC Input Capture Value 0 32 read-only CC1_CTRL No Description 0x03C read-write 0x00000000 0x000000FF MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 CC1_OCVALUE No Description 0x040 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC1_ICVALUE No Description 0x044 read-only 0x00000000 0xFFFFFFFF IC Input Capture Value 0 32 read-only FRC_S 1 FRC_S Registers 0xA8004000 0x00000000 0x00001000 registers FRC_PRI 33 FRC 34 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Enable peripheral clock to this module 0 1 read-write STATUS No Description 0x008 read-only 0x00000000 0x01FFFFFF SNIFFDCOUNT Sniffer data count 0 5 read-only ACTIVETXFCD Active Transmit Frame Descriptor 5 1 read-only FCD0 FCD0 is active 0 FCD1 FCD1 is active 1 ACTIVERXFCD Active Receive Frame Descriptor 6 1 read-only FCD2 FCD2 is active 0 FCD3 FCD3 is active 1 SNIFFDFRAME Sniffer data frame active status 7 1 read-only RXRAWBLOCKED Receiver raw trigger block is active 8 1 read-only FRAMEOK Frame valid 9 1 read-only RXABORTINPROGRESS Receive aborted in progress status flag 10 1 read-only TXWORD Transmit Word Flag 11 1 read-only RXWORD Receive Word Flag 12 1 read-only CONVPAUSED Convolutional coder pause event active 13 1 read-only TXSUBFRAMEPAUSED Transmit subframe pause event active 14 1 read-only INTERLEAVEREADPAUSED Interleaver read pause event active 15 1 read-only INTERLEAVEWRITEPAUSED Interleaver write pause event active 16 1 read-only FRAMEDETPAUSED Frame detected pause event active 17 1 read-only FRAMELENGTHERROR Frame Length Error for RX and TX 18 1 read-only DEMODERROR Demod Error in RX 19 1 read-only FSMSTATE FSM state status for srw_frc_interface 20 5 read-only IDLE 0 RX_INIT 1 RX_DATA 2 RX_CRC 3 RX_FCD_UPDATE 4 RX_DISCARD 5 RX_TRAIL 6 RX_DONE 7 RX_PAUSE_INIT 8 RX_PAUSED 9 UNDEFINED1 10 UNDEFINED2 11 RX_CRC_ZEROCHECK 12 RX_SUP 13 RX_WAITEOF 14 UNDEFINED3 15 TX_INIT 16 TX_DATA 17 TX_CRC 18 TX_FCD_UPDATE 19 TX_TRAIL 20 TX_FLUSH 21 TX_DONE 22 TX_DONE_WAIT 23 TX_RAW 24 TX_PAUSEFLUSH 25 DFLCTRL No Description 0x00C read-write 0x00000000 0x01FFFF7F DFLMODE Dynamic Frame Length Mode 0 3 read-write DISABLE Dynamic Frame Length support is disabled, and the frame length is controlled by writing directly to the FRAMELENGTH field 0 SINGLEBYTE Dynamic Frame Length is enabled and located in a single byte over air. This byte is loaded into the least significant byte of the extracted length field 1 SINGLEBYTEMSB Dynamic Frame Length is enabled and located in a single byte over air. This byte is loaded into the most significant byte of the extracted length field 2 DUALBYTELSBFIRST Dynamic Frame Length is enabled and located in two bytes over air, of which the least significant byte is transferred first 3 DUALBYTEMSBFIRST Dynamic Frame Length is enabled and located in two bytes over air, of which the most significant byte is transferred first 4 INFINITE Dynamic Frame Length support is disabled, and infinite frame lengths are transmitted and received. RXABORT may be used to abort active receive operations, while the TXDIS command (available in the RAC) may be used to abort active transmit operations. 5 BLOCKERROR In transmit mode, the frame length must be written directly to the FRAMELENGTH field. In receive mode, data will be received until a block decoding error is found. 6 DFLBITORDER Dynamic Frame Length Bit order 3 1 read-write NORMAL Bit ordering is defined by the BITORDER field 0 REVERSE Bit ordering is reversed, compared to what is defined by the BITORDER field 1 DFLSHIFT Dynamic Frame Length bitshift 4 3 read-write DFLOFFSET Length Field Offset Value 8 4 read-write DFLBITS Length field number of bits 12 4 read-write MINLENGTH Minimum decoded length 16 4 read-write DFLINCLUDECRC Length field includes CRC values or not 20 1 read-write X0 The CRC values are not included in the frame length 0 X1 The CRC values are included in the frame length 1 DFLBOIOFFSET Length Field Offset Value 21 4 read-write MAXLENGTH No Description 0x010 read-write 0x00004FFF 0x0000FFFF MAXLENGTH Max Frame Length Value 0 12 read-write INILENGTH Initial Frame Length Value 12 4 read-write ADDRFILTCTRL No Description 0x014 read-write 0x00000000 0x0000FF07 EN Address Filter Enable 0 1 read-write BRDCST00EN Broadcast Address 0x00 Enable 1 1 read-write BRDCSTFFEN Broadcast Address 0xFF Enable 2 1 read-write ADDRESS Address 8 8 read-write DATABUFFER No Description 0x018 read-write 0x00000000 0x000000FF DATABUFFER Frame Controller data buffer 0 8 read-write WCNT No Description 0x01C read-only 0x00000000 0x00000FFF WCNT Word Counter Value 0 12 read-only WCNTCMP0 No Description 0x020 read-write 0x00000000 0x00000FFF FRAMELENGTH Word Counter Frame Length Value 0 12 read-write WCNTCMP1 No Description 0x024 read-write 0x00000000 0x00000FFF LENGTHFIELDLOC Length field location 0 12 read-write WCNTCMP2 No Description 0x028 read-write 0x00000000 0x00000FFF ADDRFIELDLOC Address field location 0 12 read-write CMD No Description 0x02C write-only 0x00000000 0x00001FFF RXABORT RX Abort 0 1 write-only FRAMEDETRESUME FRAMEDET resume 1 1 write-only INTERLEAVEWRITERESUME Interleaver write resume 2 1 write-only INTERLEAVEREADRESUME Interleaver read resume 3 1 write-only CONVRESUME Convolutional coder resume 4 1 write-only CONVTERMINATE Convolutional coder termination 5 1 write-only TXSUBFRAMERESUME TX subframe resume 6 1 write-only INTERLEAVEINIT Interleaver initialization 7 1 write-only INTERLEAVECNTCLEAR Interleaver counter clear 8 1 write-only CONVINIT Convolutional coder initialize 9 1 write-only BLOCKINIT Block coder initialize 10 1 write-only STATEINIT FRC State initialize 11 1 write-only RXRAWUNBLOCK Clear RXRAWBLOCKED status flag 12 1 write-only WHITECTRL No Description 0x030 read-write 0x00000000 0x00001F7F FEEDBACKSEL LFSR Feedback selector 0 5 read-write BIT0 Select bit 0 as feedback 0 BIT1 Select bit 1 as feedback 1 BIT2 Select bit 2 as feedback 2 BIT3 Select bit 3 as feedback 3 BIT4 Select bit 4 as feedback 4 BIT5 Select bit 5 as feedback 5 BIT6 Select bit 6 as feedback 6 BIT7 Select bit 7 as feedback 7 BIT8 Select bit 8 as feedback 8 BIT9 Select bit 9 as feedback 9 BIT10 Select bit 10 as feedback 10 BIT11 Select bit 11 as feedback 11 BIT12 Select bit 12 as feedback 12 BIT13 Select bit 13 as feedback 13 BIT14 Select bit 14 as feedback 14 BIT15 Select bit 15 as feedback 15 INPUT Select data input as feedback 16 ZERO Select zero as feedback 17 ONE Select one as feedback 18 TXLASTWORD In transmit mode, the feedback is one during the last transmit word and zero otherwise. In receive mode, the feedback is always zero. 19 XORFEEDBACK LFSR Feedback XOR setting 5 2 read-write DIRECT The signal defined by FEEDBACKSEL is used directly as Feedback. 0 XOR The signal defined by FEEDBACKSEL is XOR'ed with bit 15, and the result is used as Feedback 1 ZERO Feedback is set to 0 2 SHROUTPUTSEL Shift Register Output Selector 8 4 read-write BLOCKERRORCORRECT Block Errors Correction enable 12 1 read-write X0 Block decoding errors are not corrected, only the BLOCKERR interrupt is set on detection. 0 X1 Block decoding errors are attempted corrected by memory lookup tables. The BLOCKERR interrupt is also set on error detection. 1 WHITEPOLY No Description 0x034 read-write 0x00000000 0x0000FFFF POLY Whitener Polynomial 0 16 read-write WHITEINIT No Description 0x038 read-write 0x00000000 0x0000FFFF WHITEINIT Whitener Initial Value 0 16 read-write FECCTRL No Description 0x03C read-write 0x00000000 0x003FFFF7 BLOCKWHITEMODE Block Coder Whitener Mode 0 3 read-write DIRECT The input data is passed directly to the output without any other operations. 0 WHITE Data is whitened in TX and de-whitened in RX with the whitener feedback register updated every bit period. 1 BYTEWHITE Data is whitened in TX and de-whitened in RX with the whitener feedback register updated every byte period, recommended only for compatibility purposes. 2 INTERLEAVEDWHITE0 Data is whitened in TX after symbol interleaving and de-whitened in RX before symbol de-interleaving. 3 INTERLEAVEDWHITE1 Data is whitened in TX after symbol interleaving and de-whitened in RX before symbol de-interleaving. The first 16 (if INTERLEAVEWIDTH is 0) or 32 (if INTERLEAVEWIDTH is 1) RF symbols are not whitened or de-whitened. 4 BLOCKCODEINSERT Parity bits are added in TX and checked and removed in RX to perform block coding forward error correction (FEC). In transmit mode, the block encoder will insert parity bits between the bit stream provided from the transmit buffer. In receive mode, the block decoder will remove parity bits and they will not further be provided to the receive buffer. 5 BLOCKCODEREPLACE Parity bits are added in TX and checked and removed in RX to perform block coding forward error correction (FEC). In transmit mode, the block encoder will replace bits provided by the transmit buffer with parity bits. In receive mode, the block decoder will output both data bits and parity bits to the receive buffer. 6 BLOCKLOOKUP A lookup table is used to implement table lookup block coding in TX, and table lookup block decoding in RX. 7 CONVMODE Convolutional Encoder / Decoder mode. 4 2 read-write DISABLE Convolutional encoding / decoding is disabled 0 CONVOLUTIONAL Normal convolutional encoding / decoding is enabled 1 REPEAT Repeat-mode convolutional encoding / decoding is enabled 2 CONVDECODEMODE Convolutional decoding mode setting. 6 1 read-write SOFT Use soft decision convolutional decoding, recommended in most cases. 0 HARD Use hard decision convolutional decoding. 1 CONVTRACEBACKDISABLE Convolutional traceback disabling 7 1 read-write X0 Traceback history is enabled, and convolutional decoding will use RAM to store state information. In receive mode, output from convolutional decoding will be generated after the traceback history has reached a certain level. 0 X1 Traceback history is disabled, and convolutional decoding will not use RAM to store state information. No trellis termination sequence will be automatically appended to the transmit data. In receive mode, output from convolutional decoding will be generated after every state transition. This will not provide any convolutional decoding gain, but can be used to decode very simple codes without using any RAM memory. 1 CONVINV Convolutional code symbol inversion 8 2 read-write INTERLEAVEMODE Interleaver mode. 10 2 read-write DISABLE Interleaving is disabled 0 ENABLE Interleaving is enabled 1 RXBUFFER No symbol interleaving is performed, but the interleaver data storage is used as a data buffer in receive mode. This may, for instance, be used for receiver pause functionality. 2 RXTXBUFFER No symbol interleaving is performed, but the interleaver data storage is used as a data buffer in receive and transmit mode. This may, for instance, be used for receiver and transmitter pause functionality. 3 INTERLEAVEFIRSTINDEX 4-bit index of the first interleaver 12 4 read-write INTERLEAVEWIDTH Interleave symbol width. 16 1 read-write ONE Each interleaver element consists of one RF symbol 0 TWO Each interleaver element consists of two RF symbols 1 CONVBUSLOCK Convolutional decoding bus lock 17 1 read-write CONVSUBFRAMETERMINATE Enable trellis termination for subframes 18 1 read-write X0 Trellis termination is applied at the end of the frame. 0 X1 Trellis termination is applied at the end of each subframe and at the end of the frame. 1 SINGLEBLOCK Single block code per frame 19 1 read-write FORCE2FSK Force use of 2-FSK 20 1 read-write CONVHARDERROR Enable convolutional decoding hard error 21 1 read-write X0 Convolutional hard error decoding is disabled. 0 X1 Convolutional hard error decoding is enabled. 1 BLOCKRAMADDR No Description 0x040 read-write 0x00004000 0xFFFFFFFC BLOCKRAMADDR Block decoding RAM address 2 30 read-write CONVRAMADDR No Description 0x044 read-write 0x00004000 0xFFFFFFFC CONVRAMADDR Convolutional decoding RAM address 2 30 read-write CTRL No Description 0x048 read-write 0x00000700 0x001F3FF7 RANDOMTX Random TX Mode 0 1 read-write UARTMODE Data Uart Mode 1 1 read-write BITORDER Data Bit Order. 2 1 read-write LSBFIRST Least Significant bit in each word is sent/received first. 0 MSBFIRST Most Significant bit in each word is sent/received first. 1 TXFCDMODE TX Frame Control Descriptor Mode 4 2 read-write FCDMODE0 FCD0 is reloaded when SCNT reaches 0 0 FCDMODE1 Use FCD0 for the first sub-frame, then switching between FCD0 and FCD1 for following sub-frames 1 FCDMODE2 Use FCD0 for the first sub-frame, then FCD1 is used for all following sub-frames 2 FCDMODE3 Use alternating FCD0 / FCD1 for each complete frame 3 RXFCDMODE RX Frame Control Descriptor Mode 6 2 read-write FCDMODE0 FCD2 is reloaded when SCNT reaches 0 0 FCDMODE1 Use FCD2 for the first sub-frame, then switching between FCD2 and FCD3 for following sub-frames 1 FCDMODE2 Use FCD2 for the first sub-frame, then FCD3 is used for all following sub-frames 2 FCDMODE3 Use alternating FCD2 / FCD3 for each complete frame 3 BITSPERWORD Bits Per Word, for first word in a frame 8 3 read-write RATESELECT MODEM rate select 11 2 read-write TXPREFETCH Transmit prefetch data 13 1 read-write X0 The frame controller will start preparing transmit data when entering the TX state. This setting may be used in most cases. 0 X1 The frame controller will start preparing transmit data already in the TXWARM, RX2TX or TX2TX state. This setting must be used to avoid transmit underflow in the cases where no preamble or frame synchronization is inserted by the modulator (i.e. typically when the MODEM control fields TXBASES is zero and SYNCDATA is set). 1 SEQHANDSHAKE Sequencer data handshake 16 1 read-write X0 The sequencer may read transmit or read data through the FRCRD command, but it will not wait for the sequencer to do so before proceeding to parse transmit or receive data. 0 X1 The frame controller will require that the sequencer program uses the FRCRD command to read both transmit and receive data which the frame controller stores in the DATABUFFER register. If data is not read with this field set, the overflow (RXOF) or underflow (TXUF) will be set. 1 PRBSTEST Pseudo-Random Bit Sequence Testmode 17 1 read-write LPMODEDIS Disable FRC low power 18 1 read-write WAITEOFEN Enable STATE_TX_WAITEOF 19 1 read-write RXABORTIGNOREDIS Disable ignoring CMD_RXABORT 20 1 read-write RXCTRL No Description 0x04C read-write 0x00000000 0x000007FF STORECRC Store CRC value. 0 1 read-write ACCEPTCRCERRORS Accept CRC Errors. 1 1 read-write REJECT Frames with one or more detected CRC errors will be cleared from the receiver buffer. 0 ACCEPT Frames will always be written to the receive buffer, regardless of CRC errors. 1 ACCEPTBLOCKERRORS Accept Block Decoding Errors. 2 1 read-write REJECT Frame reception will be stopped when a block decoding error is found. 0 ACCEPT Frame reception will continue even in the case of a block decoding error. 1 TRACKABFRAME Track Aborted RX Frame 3 1 read-write X0 When a frame abort is triggered, the frame reception is immediately aborted, the RXABORTED interrupt flag is set, and the receiver may start searching for a new frame. 0 X1 When a frame abort is triggered, the receiver is still enabled for the duration of the frame (as defined by the frame length), but no data output is generated. Only when the complete frame is received, the RXABORTED interrupt flag is set and a new frame reception may begin. This mode may, for instance, be used to avoid finding a new FRAMEDET event inside the payload data of a discarded frame. 1 BUFCLEAR Buffer Clear 4 1 read-write BUFRESTOREFRAMEERROR Buffer restore on frame error 5 1 read-write BUFRESTORERXABORTED Buffer restore on RXABORTED 6 1 read-write RXFRAMEENDAHEADBYTES RX frame almost end of packet timing 7 4 read-write TRAILTXDATACTRL No Description 0x050 read-write 0x00000000 0x007FFFFF TRAILTXDATA Trailing Data value 0 8 read-write TRAILTXDATACNT Trailing data bit count 8 3 read-write TRAILTXDATAFORCE Force trailing TX data insertion 11 1 read-write X0 Trailing data in transmit is only applied in order to fill up an integer number of block coding and interleaver buffers. If block coding and interleaving is not used, no trailing data is transmitted. 0 X1 The number of bits defined by TRAILTXDATACNT is always appended to the transmit data, in addition to the necessary bits to fill up an integer number of block coding and interleaver buffers. 1 TRAILTXREPLEN Trailing Data Repeat Length 12 10 read-write TXSUPPLENOVERIDE TX Sup Len Override 22 1 read-write TRAILRXDATA No Description 0x054 read-write 0x00000000 0x0000003F RSSI Append RSSI 0 1 read-write CRCOK Append CRC OK Indicator 1 1 read-write PROTIMERCC0BASE PROTIMER Capture Compare channel 0 Base 2 1 read-write PROTIMERCC0WRAPL PROTIMER Capture Compare channel 0 WrapL 3 1 read-write PROTIMERCC0WRAPH PROTIMER Capture Compare channel 0 WrapH 4 1 read-write RTCSTAMP RTCC Time Stamp 5 1 read-write SCNT No Description 0x058 read-only 0x00000000 0x000000FF SCNT Sub-Frame Counter Value 0 8 read-only CONVGENERATOR No Description 0x05C read-write 0x00000000 0x00037F7F GENERATOR0 Output 0 Generator Polynomial 0 7 read-write GENERATOR1 Output 1 Generator Polynomial 8 7 read-write RECURSIVE Convolutional encoding 16 1 read-write X0 Non-recursive convolutional coding is used 0 X1 Recursive convolutional coding is used 1 NONSYSTEMATIC Non systematic recursive code 17 1 read-write X0 The recursive code is systematic 0 X1 The recursive code is not systematic 1 PUNCTCTRL No Description 0x060 read-write 0x00000101 0x00007F7F PUNCT0 Puncturing Matrix Row for Output 0 0 7 read-write PUNCT1 Puncturing Matrix Row for Output 1 8 7 read-write PAUSECTRL No Description 0x064 read-write 0x00000000 0x001FFFFF FRAMEDETPAUSEEN Frame detect pause enable 0 1 read-write TXINTERLEAVEWRITEPAUSEEN Transmit interleaver write pause enable 1 1 read-write RXINTERLEAVEWRITEPAUSEEN Receive interleaver write pause enable 2 1 read-write INTERLEAVEREADPAUSEEN Interleaver read pause enable 3 1 read-write TXSUBFRAMEPAUSEEN Transmit subframe pause enable 4 1 read-write CONVPAUSECNT Convolutional decoder pause setting 5 6 read-write INTERLEAVEWRITEPAUSECNT Interleaver write pause count 11 5 read-write INTERLEAVEREADPAUSECNT Interleaver read pause count 16 5 read-write IF No Description 0x068 read-write 0x00000000 0x7F7FFFFF TXDONE TX Done Interrupt Flag 0 1 read-write TXAFTERFRAMEDONE TX after frame Done Interrupt Flag 1 1 read-write TXABORTED Transmit Aborted Interrupt Flag 2 1 read-write TXUF Transmit Underflow Interrupt Flag 3 1 read-write RXDONE RX Done Interrupt Flag 4 1 read-write RXABORTED RX Aborted Interrupt Flag 5 1 read-write FRAMEERROR Frame Error Interrupt Flag 6 1 read-write BLOCKERROR Block Error Interrupt Flag 7 1 read-write RXOF Receive Overflow Interrupt Flag 8 1 read-write WCNTCMP0 Word Counter Compare 0 Event 9 1 read-write WCNTCMP1 Word Counter Compare 1 Event 10 1 read-write WCNTCMP2 Word Counter Compare 2 Event 11 1 read-write ADDRERROR Receive address error event 12 1 read-write BUSERROR A bus error event occurred 13 1 read-write RXRAWEVENT Receiver raw data event 14 1 read-write TXRAWEVENT Transmit raw data event 15 1 read-write SNIFFOF Data sniffer overflow 16 1 read-write WCNTCMP3 Word Counter Compare 3 Event 17 1 read-write WCNTCMP4 Word Counter Compare 4 Event 18 1 read-write BOISET BOI SET 19 1 read-write PKTBUFSTART Packet Buffer Start 20 1 read-write PKTBUFTHRESHOLD Packet Buffer Threshold 21 1 read-write RXRAWOF RX raw FIFO overflow 22 1 read-write FRAMEDETPAUSED Frame detected pause event active 24 1 read-write INTERLEAVEWRITEPAUSED Interleaver write pause event active 25 1 read-write INTERLEAVEREADPAUSED Interleaver read pause event active 26 1 read-write TXSUBFRAMEPAUSED Transmit subframe pause event active 27 1 read-write CONVPAUSED Convolutional coder pause event active 28 1 read-write RXWORD Receive Word Interrupt Flag 29 1 read-write TXWORD Transmit Word Interrupt Flag 30 1 read-write IEN No Description 0x06C read-write 0x00000000 0x7F7FFFFF TXDONE TX Done Interrupt Enable 0 1 read-write TXAFTERFRAMEDONE TX after frame Done Interrupt Enable 1 1 read-write TXABORTED Transmit Aborted Interrupt Enable 2 1 read-write TXUF Transmit Underflow Interrupt Enable 3 1 read-write RXDONE RX Done Interrupt Enable 4 1 read-write RXABORTED RX Aborted Interrupt Enable 5 1 read-write FRAMEERROR Frame Error Interrupt Enable 6 1 read-write BLOCKERROR Block Error Interrupt Enable 7 1 read-write RXOF Receive Overflow Interrupt Enable 8 1 read-write WCNTCMP0 Word Counter Compare 0 Enable 9 1 read-write WCNTCMP1 Word Counter Compare 1 Enable 10 1 read-write WCNTCMP2 Word Counter Compare 2 Enable 11 1 read-write ADDRERROR Receive address error enable 12 1 read-write BUSERROR Bus error enable 13 1 read-write RXRAWEVENT Receiver raw data enable 14 1 read-write TXRAWEVENT Transmit raw data enable 15 1 read-write SNIFFOF Data sniffer overflow enable 16 1 read-write WCNTCMP3 Word Counter Compare 3 Enable 17 1 read-write WCNTCMP4 Word Counter Compare 4 Enable 18 1 read-write BOISET BOISET 19 1 read-write PKTBUFSTART PKTBUFSTART Enable 20 1 read-write PKTBUFTHRESHOLD PKTBUFTHRESHOLD Enable 21 1 read-write RXRAWOF RXRAWOF Enable 22 1 read-write FRAMEDETPAUSED Frame detected pause event enable 24 1 read-write INTERLEAVEWRITEPAUSED Interleaver write pause event enable 25 1 read-write INTERLEAVEREADPAUSED Interleaver read pause event enable 26 1 read-write TXSUBFRAMEPAUSED Transmit subframe pause event enable 27 1 read-write CONVPAUSED Convolutional coder pause event enable 28 1 read-write RXWORD Receive Word Interrupt Enable 29 1 read-write TXWORD Transmit Word Interrupt Enable 30 1 read-write OTACNT No Description 0x070 read-only 0x00000000 0xFFFFFFFF OTARXCNT OTA RX bit counter 0 16 read-only OTATXCNT OTA TX bit counter 16 16 read-only BUFFERMODE No Description 0x078 read-write 0x00000000 0x0000000F TXBUFFERMODE Transmit Buffer Mode 0 1 read-write BUFC The Frame Controller fetches data from the Buffer Controller (BUFC) in transmit mode. 0 REGISTER The Frame Controller does not fetch data from the Buffer Controller in transmit mode. Instead, data must be written to the DATABUFFER register when the TXWORD interrupt flag is set. 1 RXBUFFERMODE Receive Buffer Mode 1 2 read-write BUFC The Frame Controller write data to the Buffer Controller (BUFC) in receive mode. 0 REGISTER The Frame Controller does not write data to the Buffer Controller in receive mode. Instead, data must be read from the DATABUFFER register when the RXWORD interrupt flag is set. 1 DISABLE The Frame Controller will not output demodulated data. This mode can, for instance, be used together with storing RAW frame data. 2 RXFRCBUFMUX RX FRC Buffer Mux 3 1 read-write SNIFFCTRL No Description 0x084 read-write 0x000007FC 0x0003FFFF SNIFFMODE Data Sniff Mode 0 2 read-write OFF FRC Packet Sniffer mode is disabled 0 UART UART encoded data is transmitted on the DOUT pin. 1 SPI SPI data is transmitted on the DOUT pin and a data clock is output to the DCLK pin. 2 SNIFFBITS Data sniff data bits 2 1 read-write EIGHT Each sniffer output word contains 8 data bits 0 NINE Each sniffer output word contains 9 data bits 1 SNIFFRXDATA Enable sniffing of received data. 3 1 read-write SNIFFTXDATA Enable sniffing of transmitted data. 4 1 read-write SNIFFRSSI Enable sniffing of RSSI 5 1 read-write SNIFFSTATE Enable sniffing of state information 6 1 read-write SNIFFAUXDATA Enable sniffing of auxiliary data 7 1 read-write SNIFFBR Sniffer baudrate setting 8 8 read-write SNIFFSYNCWORD Sniffer baudrate setting 17 1 read-write AUXDATA No Description 0x088 write-only 0x00000000 0x000001FF AUXDATA Auxiliary sniffer data output 0 9 write-only RAWCTRL No Description 0x08C read-write 0x00000000 0x000021BF TXRAWMODE Transmitter raw data mode 0 2 read-write DISABLE RAW transmit mode is disabled 0 SINGLEBUFFER RAW transmit mode is enabled, transmitting the configured raw data (fetched from RAM) once before transmit is completed. 1 REPEATBUFFER RAW transmit mode is enabled, transmitting the configured raw data (fetched from RAM) repeatedly until the transmitter is disabled. 2 RXRAWMODE Receiver raw data mode 2 3 read-write DISABLE RAW receive mode is disabled 0 SINGLEITEM RAW receive mode is enabled, fetching a single item which is stored in the RXRAWDATA register. A new item is fetched when the RXRAWBLOCKED flag is cleared. In this mode, the flag is cleared automatically when RXRAWDATA is read. 1 SINGLEBUFFER RAW receive mode is enabled, fetching multiple items which are stored to RAM. The RXRAWBLOCKED flag must be cleared in order to start raw data reception. 2 SINGLEBUFFERFRAME This mode is identical to the SINGLEBUFFER mode, except that the FRC will treat the end of the filled buffer as the end of a frame reception (i.e. also trigger the RXDONE interrupt and signal to the RAC that frame reception is complete.) 3 REPEATBUFFER RAW receive mode is enabled, fetching multiple items which are stored to RAM. The RXRAWBLOCKED flag must be cleared in order to start raw data reception. 4 RXRAWRANDOM Receive raw data random number generator 5 1 read-write RXRAWTRIGGER Receiver raw data trigger setting 7 2 read-write IMMEDIATE RAW data storage is triggered immediately when demodulator is enabled. 0 PRS RAW data storage is triggered by the selected RXRAWPRSSEL PRS channel. 1 INTERNALSIG RAW data storage is triggered by an internal signal 2 DEMODRAWDATAMUX Raw data mux control 13 1 read-write DEMODRAWDATASEL RAW data is selected using modem register DEMODRAWDATASEL. 0 DEMODRAWDATASEL2 RAW data is selected using modem register DEMODRAWDATASEL2. 1 RXRAWDATA No Description 0x090 read-only 0x00000000 0xFFFFFFFF RXRAWDATA Receiver RAW data register 0 32 read-only PAUSEDATA No Description 0x094 read-only 0x00000000 0xFFFFFFFF PAUSEDATA Receiver pause data register 0 32 read-only LIKELYCONVSTATE No Description 0x098 read-only 0x00000000 0x0000003F LIKELYCONVSTATE Most likely convolutional decoder state 0 6 read-only INTELEMENTNEXT No Description 0x09C read-only 0x00000000 0x000000FF INTELEMENTNEXT Interleaver element value 0 8 read-only INTWRITEPOINT No Description 0x0A0 read-write 0x00000000 0x0000001F INTWRITEPOINT Interleaver buffer write pointer 0 5 read-write INTREADPOINT No Description 0x0A4 read-write 0x00000000 0x0000001F INTREADPOINT Interleaver buffer read pointer 0 5 read-write AUTOCG No Description 0x0A8 read-write 0x00000000 0x0000FFFF AUTOCGEN Automatic clock gate enable 0 16 read-write CGCLKSTOP No Description 0x0AC read-write 0x00000000 0x0000FFFF FORCEOFF Force off 0 16 read-write SEQIF No Description 0x0B4 read-write 0x00000000 0x7F7FFFFF TXDONE TX Done Interrupt Flag 0 1 read-write TXAFTERFRAMEDONE TX after frame Done Interrupt Flag 1 1 read-write TXABORTED Transmit Aborted Interrupt Flag 2 1 read-write TXUF Transmit Underflow Interrupt Flag 3 1 read-write RXDONE RX Done Interrupt Flag 4 1 read-write RXABORTED RX Aborted Interrupt Flag 5 1 read-write FRAMEERROR Frame Error Interrupt Flag 6 1 read-write BLOCKERROR Block Error Interrupt Flag 7 1 read-write RXOF Receive Overflow Interrupt Flag 8 1 read-write WCNTCMP0 Word Counter Compare 0 Event 9 1 read-write WCNTCMP1 Word Counter Compare 1 Event 10 1 read-write WCNTCMP2 Word Counter Compare 2 Event 11 1 read-write ADDRERROR Receive address error event 12 1 read-write BUSERROR A bus error event occurred 13 1 read-write RXRAWEVENT Receiver raw data event 14 1 read-write TXRAWEVENT Transmit raw data event 15 1 read-write SNIFFOF Data sniffer overflow 16 1 read-write WCNTCMP3 Word Counter Compare 3 Event 17 1 read-write WCNTCMP4 Word Counter Compare 4 Event 18 1 read-write BOISET BOISET Event 19 1 read-write PKTBUFSTART Packet Buffer Start 20 1 read-write PKTBUFTHRESHOLD Packet Buffer Threshold 21 1 read-write RXRAWOF RX raw FIFO overflow 22 1 read-write FRAMEDETPAUSED Frame detected pause event active 24 1 read-write INTERLEAVEWRITEPAUSED Interleaver write pause event active 25 1 read-write INTERLEAVEREADPAUSED Interleaver read pause event active 26 1 read-write TXSUBFRAMEPAUSED Transmit subframe pause event active 27 1 read-write CONVPAUSED Convolutional coder pause event active 28 1 read-write RXWORD Receive Word Interrupt Flag 29 1 read-write TXWORD Transmit Word Interrupt Flag 30 1 read-write SEQIEN No Description 0x0B8 read-write 0x00000000 0x7F7FFFFF TXDONE TX Done Interrupt Enable 0 1 read-write TXAFTERFRAMEDONE TX after frame Done Interrupt Enable 1 1 read-write TXABORTED Transmit Aborted Interrupt Enable 2 1 read-write TXUF Transmit Underflow Interrupt Enable 3 1 read-write RXDONE RX Done Interrupt Enable 4 1 read-write RXABORTED RX Aborted Interrupt Enable 5 1 read-write FRAMEERROR Frame Error Interrupt Enable 6 1 read-write BLOCKERROR Block Error Interrupt Enable 7 1 read-write RXOF Receive Overflow Interrupt Enable 8 1 read-write WCNTCMP0 Word Counter Compare 0 Enable 9 1 read-write WCNTCMP1 Word Counter Compare 1 Enable 10 1 read-write WCNTCMP2 Word Counter Compare 2 Enable 11 1 read-write ADDRERROR Receive address error enable 12 1 read-write BUSERROR Bus error enable 13 1 read-write RXRAWEVENT Receiver raw data enable 14 1 read-write TXRAWEVENT Transmit raw data enable 15 1 read-write SNIFFOF Data sniffer overflow enable 16 1 read-write WCNTCMP3 Word Counter Compare 2 Enable 17 1 read-write WCNTCMP4 Word Counter Compare 2 Enable 18 1 read-write BOISET Word Counter Compare 2 Enable 19 1 read-write PKTBUFSTART PKTBUFSTART Enable 20 1 read-write PKTBUFTHRESHOLD PKTBUFTHRESHOLD Enable 21 1 read-write RXRAWOF RXRAWOF Enable 22 1 read-write FRAMEDETPAUSED Frame detected pause event enable 24 1 read-write INTERLEAVEWRITEPAUSED Interleaver write pause event enable 25 1 read-write INTERLEAVEREADPAUSED Interleaver read pause event enable 26 1 read-write TXSUBFRAMEPAUSED Transmit subframe pause event enable 27 1 read-write CONVPAUSED Convolutional coder pause event enable 28 1 read-write RXWORD Receive Word Interrupt Enable 29 1 read-write TXWORD Transmit Word Interrupt Enable 30 1 read-write WCNTCMP3 No Description 0x0BC read-write 0x00000000 0x00000FFF SUPPLENFIELDLOC Sup Length field location 0 12 read-write BOICTRL No Description 0x0C0 read-write 0x00000000 0x0001FFFF BOIEN BOI EN 0 1 read-write BOIFIELDLOC BOI field location 1 12 read-write BOIBITPOS BOI bit position 13 3 read-write BOIMATCHVAL BOI match value 16 1 read-write DSLCTRL No Description 0x0C4 read-write 0x00000000 0x7FFFFF7F DSLMODE Dynamic Frame Length Mode 0 3 read-write DISABLE Dynamic Frame Length support is disabled, and the frame length is controlled by writing directly to the FRAMELENGTH field 0 SINGLEBYTE Dynamic Frame Length is enabled and located in a single byte over air. This byte is loaded into the least significant byte of the extracted length field 1 SINGLEBYTEMSB Dynamic Frame Length is enabled and located in a single byte over air. This byte is loaded into the most significant byte of the extracted length field 2 DUALBYTELSBFIRST Dynamic Frame Length is enabled and located in two bytes over air, of which the least significant byte is transferred first 3 DUALBYTEMSBFIRST Dynamic Frame Length is enabled and located in two bytes over air, of which the most significant byte is transferred first 4 INFINITE Dynamic Frame Length support is disabled, and infinite frame lengths are transmitted and received. RXABORT may be used to abort active receive operations, while the TXDIS command (available in the RAC) may be used to abort active transmit operations. 5 BLOCKERROR In transmit mode, the frame length must be written directly to the FRAMELENGTH field. In receive mode, data will be received until a block decoding error is found. 6 DSLBITORDER Dynamic Frame Length Bit order 3 1 read-write NORMAL Bit ordering is defined by the BITORDER field 0 REVERSE Bit ordering is reversed, compared to what is defined by the BITORDER field 1 DSLSHIFT Dynamic Frame Length bitshift 4 3 read-write DSLOFFSET Length Field Offset Value 8 8 read-write DSLBITS Length field number of bits 16 4 read-write DSLMINLENGTH Minimum decoded length 20 4 read-write RXSUPRECEPMODE RX Supplement Reception Mode 24 3 read-write NOSUP Do not receive SUP 0 BOIDSLBASED Receive SUP based on BOI and fetch SUPLEN from DSL setting 1 BOIFIXEDSLBASED Receive SUP based on BOI and fetch SUPLEN from WCNTCMP4 2 DSLBASED Receive SUP based irrespective of BOI and fetch SUPLEN from DSL setting 3 FIXEDSLBASED Receive SUP based irrespective of BOI and fetch SUPLEN from WCNTCMP4 setting 4 STORESUP Store SUPP in BUFC 27 1 read-write SUPSHFFACTOR Supp Shift factor 28 3 read-write WCNTCMP4 No Description 0x0C8 read-write 0x00000000 0x00000FFF SUPPLENGTH Supp Length Value 0 12 read-write PKTBUFCTRL No Description 0x0CC read-write 0x00000000 0x0103FFFF PKTBUFSTARTLOC Packet Buffer Start Address 0 12 read-write PKTBUFTHRESHOLD Packet Buffer Threshold 12 6 read-write PKTBUFTHRESHOLDEN Packet Buffer Threshold Enable 24 1 read-write PKTBUFSTATUS No Description 0x0D0 read-only 0x00000000 0x0000003F PKTBUFCOUNT Packet Buffer Count 0 6 read-only PKTBUF0 No Description 0x0D4 read-only 0x00000000 0xFFFFFFFF PKTBUF0 Packet Capture Buffer 0 8 read-only PKTBUF1 Packet Capture Buffer 8 8 read-only PKTBUF2 Packet Capture Buffer 16 8 read-only PKTBUF3 Packet Capture Buffer 24 8 read-only PKTBUF1 No Description 0x0D8 read-only 0x00000000 0xFFFFFFFF PKTBUF4 Packet Capture Buffer 0 8 read-only PKTBUF5 Packet Capture Buffer 8 8 read-only PKTBUF6 Packet Capture Buffer 16 8 read-only PKTBUF7 Packet Capture Buffer 24 8 read-only PKTBUF2 No Description 0x0DC read-only 0x00000000 0xFFFFFFFF PKTBUF8 Packet Capture Buffer 0 8 read-only PKTBUF9 Packet Capture Buffer 8 8 read-only PKTBUF10 Packet Capture Buffer 16 8 read-only PKTBUF11 Packet Capture Buffer 24 8 read-only PKTBUF3 No Description 0x0E0 read-only 0x00000000 0xFFFFFFFF PKTBUF12 Packet Capture Buffer 0 8 read-only PKTBUF13 Packet Capture Buffer 8 8 read-only PKTBUF14 Packet Capture Buffer 16 8 read-only PKTBUF15 Packet Capture Buffer 24 8 read-only PKTBUF4 No Description 0x0E4 read-only 0x00000000 0xFFFFFFFF PKTBUF16 Packet Capture Buffer 0 8 read-only PKTBUF17 Packet Capture Buffer 8 8 read-only PKTBUF18 Packet Capture Buffer 16 8 read-only PKTBUF19 Packet Capture Buffer 24 8 read-only PKTBUF5 No Description 0x0E8 read-only 0x00000000 0xFFFFFFFF PKTBUF20 Packet Capture Buffer 0 8 read-only PKTBUF21 Packet Capture Buffer 8 8 read-only PKTBUF22 Packet Capture Buffer 16 8 read-only PKTBUF23 Packet Capture Buffer 24 8 read-only PKTBUF6 No Description 0x0EC read-only 0x00000000 0xFFFFFFFF PKTBUF24 Packet Capture Buffer 0 8 read-only PKTBUF25 Packet Capture Buffer 8 8 read-only PKTBUF26 Packet Capture Buffer 16 8 read-only PKTBUF27 Packet Capture Buffer 24 8 read-only PKTBUF7 No Description 0x0F0 read-only 0x00000000 0xFFFFFFFF PKTBUF28 Packet Capture Buffer 0 8 read-only PKTBUF29 Packet Capture Buffer 8 8 read-only PKTBUF30 Packet Capture Buffer 16 8 read-only PKTBUF31 Packet Capture Buffer 24 8 read-only PKTBUF8 No Description 0x0F4 read-only 0x00000000 0xFFFFFFFF PKTBUF32 Packet Capture Buffer 0 8 read-only PKTBUF33 Packet Capture Buffer 8 8 read-only PKTBUF34 Packet Capture Buffer 16 8 read-only PKTBUF35 Packet Capture Buffer 24 8 read-only PKTBUF9 No Description 0x0F8 read-only 0x00000000 0xFFFFFFFF PKTBUF36 Packet Capture Buffer 0 8 read-only PKTBUF37 Packet Capture Buffer 8 8 read-only PKTBUF38 Packet Capture Buffer 16 8 read-only PKTBUF39 Packet Capture Buffer 24 8 read-only PKTBUF10 No Description 0x0FC read-only 0x00000000 0xFFFFFFFF PKTBUF40 Packet Capture Buffer 0 8 read-only PKTBUF41 Packet Capture Buffer 8 8 read-only PKTBUF42 Packet Capture Buffer 16 8 read-only PKTBUF43 Packet Capture Buffer 24 8 read-only PKTBUF11 No Description 0x100 read-only 0x00000000 0xFFFFFFFF PKTBUF44 Packet Capture Buffer 0 8 read-only PKTBUF45 Packet Capture Buffer 8 8 read-only PKTBUF46 Packet Capture Buffer 16 8 read-only PKTBUF47 Packet Capture Buffer 24 8 read-only FCD0 No Description 0x104 read-write 0x000000FF 0x0001FFFF WORDS No of Words in sub-frame 0 8 read-write BUFFER Buffer to Access 8 2 read-write INCLUDECRC Include CRC 10 1 read-write CALCCRC Calculate CRC 11 1 read-write SKIPCRC Skip First Words in CRC Calculation 12 2 read-write SKIPWHITE Skip data whitening in this subframe 14 1 read-write ADDTRAILTXDATA Add trailing TX data in this subframe 15 1 read-write EXCLUDESUBFRAMEWCNT Exclude subframe from WCNT 16 1 read-write FCD1 No Description 0x108 read-write 0x000000FF 0x0001FFFF WORDS No of Words in sub-frame 0 8 read-write BUFFER Buffer to Access 8 2 read-write INCLUDECRC Include CRC 10 1 read-write CALCCRC Calculate CRC 11 1 read-write SKIPCRC Skip First Words in CRC Calculation 12 2 read-write SKIPWHITE Skip data whitening in this subframe 14 1 read-write ADDTRAILTXDATA Add trailing TX data in this subframe 15 1 read-write EXCLUDESUBFRAMEWCNT Exclude subframe from WCNT 16 1 read-write FCD2 No Description 0x10C read-write 0x000000FF 0x0001FFFF WORDS No of Words in sub-frame 0 8 read-write BUFFER Buffer to Access 8 2 read-write INCLUDECRC Include CRC 10 1 read-write CALCCRC Calculate CRC 11 1 read-write SKIPCRC Skip First Words in CRC Calculation 12 2 read-write SKIPWHITE Skip data whitening in this subframe 14 1 read-write ADDTRAILTXDATA Add trailing TX data in this subframe 15 1 read-write EXCLUDESUBFRAMEWCNT Exclude subframe from WCNT 16 1 read-write FCD3 No Description 0x110 read-write 0x000000FF 0x0001FFFF WORDS No of Words in sub-frame 0 8 read-write BUFFER Buffer to Access 8 2 read-write INCLUDECRC Include CRC 10 1 read-write CALCCRC Calculate CRC 11 1 read-write SKIPCRC Skip First Words in CRC Calculation 12 2 read-write SKIPWHITE Skip data whitening in this subframe 14 1 read-write ADDTRAILTXDATA Add trailing TX data in this subframe 15 1 read-write EXCLUDESUBFRAMEWCNT Exclude subframe from WCNT 16 1 read-write INTELEMENT0 No Description 0x120 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT1 No Description 0x124 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT2 No Description 0x128 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT3 No Description 0x12C read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT4 No Description 0x130 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT5 No Description 0x134 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT6 No Description 0x138 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT7 No Description 0x13C read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT8 No Description 0x140 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT9 No Description 0x144 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT10 No Description 0x148 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT11 No Description 0x14C read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT12 No Description 0x150 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT13 No Description 0x154 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT14 No Description 0x158 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT15 No Description 0x15C read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only AGC_S 1 AGC_S Registers 0xA800C000 0x00000000 0x00001000 registers AGC 31 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Enable peripheral clock to this module 0 1 read-write STATUS0 No Description 0x008 read-only 0x00000000 0x03FFFFFF GAININDEX Gain Table Index 0 6 read-only RFPKDLAT RFPKD Latch 6 1 read-only IFPKDLOLAT IFPKD Lo threshold pass Latch 7 1 read-only IFPKDHILAT IFPKD Hi threshold pass Latch 8 1 read-only CCA Clear Channel Assessment 9 1 read-only GAINOK Gain OK 10 1 read-only PGAINDEX PGA GAIN INDEX 11 4 read-only LNAINDEX LNA GAIN INDEX 15 4 read-only PNINDEX PN GAIN INDEX 19 5 read-only ADCINDEX ADC Attenuator INDEX 24 2 read-only STATUS2 No Description 0x010 read-only 0x00000000 0xFFFF4FFF RFPKTLATCNT RF PKD Latch CNT 0 12 read-only PNDWNUP Allow PN GAIN UP 14 1 read-only RFPKDPRDCNT RF PKD PERIOD CNT 16 16 read-only RSSI No Description 0x018 read-only 0x00008000 0x0000FFC0 RSSIFRAC RSSI fractional part 6 2 read-only RSSIINT RSSI integer part 8 8 read-only FRAMERSSI No Description 0x01C read-only 0x00008000 0x0000FFC0 FRAMERSSIFRAC FRAMERSSI fractional part 6 2 read-only FRAMERSSIINT FRAMERSSI integer part 8 8 read-only CTRL0 No Description 0x020 read-write 0x2002727F 0xFECFFFFF PWRTARGET Power Target 0 8 read-write MODE Mode 8 3 read-write CONT AGC loop is adjusting gain continuously. 0 LOCKPREDET Gain is locked once a preamble is detected. 1 LOCKFRAMEDET Gain is locked once a sync word is detected. 2 LOCKDSA Gain is locked once DSA is detected. 3 RSSISHIFT RSSI Shift 11 8 read-write DISCFLOOPADJ Disable gain adjustment by CFLOOP 19 1 read-write DISRESETCHPWR Disable Reset of CHPWR 22 1 read-write ADCATTENMODE ADC Attenuator mode 23 1 read-write DISABLE ADC attenuator back-off will not be done by AGC 0 NOTMAXGAIN ADC attenuator is backed-off if rxgain is NOT MAXGAIN 1 ADCATTENCODE ADC Attenuator code 25 2 read-write ENRSSIRESET Enables reset of RSSI and CCA 27 1 read-write DSADISCFLOOP Disable channel filter loop 28 1 read-write DISPNGAINUP Disable PN gain increase 29 1 read-write DISPNDWNCOMP Disable PN gain decrease compensation 30 1 read-write AGCRST AGC reset 31 1 read-write CTRL1 No Description 0x024 read-write 0x00001300 0xFFFFFFFF CCATHRSH Clear Channel Assessment (CCA) Threshold 0 8 read-write RSSIPERIOD RSSI measure period 8 4 read-write PWRPERIOD AGC measure period 12 3 read-write SUBPERIOD Subperiod 15 1 read-write SUBNUM Subperiod numerator 16 5 read-write SUBDEN Subperiod denominator 21 5 read-write SUBINT Subperiod integer 26 6 read-write CTRL2 No Description 0x028 read-write 0x0000610A 0xE3FFFFFF DMASEL DMA select 0 1 read-write RSSI RSSI 0 GAIN Gain 1 SAFEMODE AGC safe mode 1 1 read-write SAFEMODETHD Enter threshold 2 3 read-write REHICNTTHD Exit threshold based on HICNT 5 8 read-write RELOTHD Exit threshold based on Release Counter 13 3 read-write RELBYCHPWR Safe mode release mode 16 2 read-write LO_CNT Increment counter if IFPKD_LO_LAT signal is not set. 0 PWR Increment counter if channel power is below RELTARGETPWR. 1 LO_CNT_PWR Increment if either LO_CNT or PWR. 2 LO_CNT_AND_PWR Increment if both LO_CNT and PWR. 3 RELTARGETPWR Safe Mode Release Power Target 18 8 read-write DEBCNTRST Debonce CNT Reset MODE 29 1 read-write PRSDEBUGEN PRS Debug Enable 30 1 read-write DISRFPKD Disable RF PEAKDET 31 1 read-write CTRL3 No Description 0x02C read-write 0x5140A800 0xFFFFFFFF IFPKDDEB IF PEAKDET debounce mode enable 0 1 read-write IFPKDDEBTHD IF PEAKDET debance thrshold 1 2 read-write IFPKDDEBPRD IF PEAKDET debance period 3 6 read-write IFPKDDEBRST IF PEAKDET debounce period 9 4 read-write RFPKDDEB RF PEAKDET debounce mode enable 13 1 read-write RFPKDDEBTHD RF PEAKDET debance thrshold 14 5 read-write RFPKDDEBPRD RF PEAKDET debance period 19 8 read-write RFPKDDEBRST RFPKD_LAT debounce reset delay 27 5 read-write CTRL4 No Description 0x030 read-write 0x0000000E 0xFE00FFFF PERIODRFPKD RFPKD trigger measure period 0 16 read-write RFPKDPRDGEAR RFPKD Period Gear 25 3 read-write RFPKDSYNCSEL SYNC RF PKD OUTPUT SELECT 28 1 read-write RFPKDSEL RF PKD OUTPUT SELECT 29 1 read-write FRZPKDEN PKD Freeze Enable 30 1 read-write RFPKDCNTEN Counter-based RFPKD Enable 31 1 read-write CTRL5 No Description 0x034 read-write 0x00000000 0x00FFFFFF PNUPDISTHD Disable PN GAIN increase THD 0 12 read-write PNUPRELTHD Enable PN GAIN increase THD 12 12 read-write CTRL6 No Description 0x038 read-write 0x00000000 0xC0000000 SEQPNUPALLOW SEQ Set PN GAIN UP ALLOW 30 1 read-write SEQRFPKDEN SEQ-based RFPKD Enable 31 1 read-write RSSISTEPTHR No Description 0x03C read-write 0x00000000 0x3FFFFFFF POSSTEPTHR Positive Step Threshold 0 8 read-write NEGSTEPTHR Negative Step Threshold 8 8 read-write STEPPER Step Period 16 1 read-write DEMODRESTARTPER Demodulator Restart Period 17 4 read-write DEMODRESTARTTHR Demodulator Restart Threshold 21 8 read-write RSSIFAST RSSI fast startup 29 1 read-write IF No Description 0x044 read-write 0x00000000 0x0000037D RSSIVALID RSSI Value is Valid 0 1 read-write CCA Clear Channel Assessment 2 1 read-write RSSIPOSSTEP Positive RSSI Step Detected 3 1 read-write RSSINEGSTEP Negative RSSI Step Detected 4 1 read-write SHORTRSSIPOSSTEP Short-term Positive RSSI Step Detected 6 1 read-write RFPKDPRDDONE RF PKD PERIOD CNT TOMEOUT 8 1 read-write RFPKDCNTDONE RF PKD pulse CNT TOMEOUT 9 1 read-write IEN No Description 0x048 read-write 0x00000000 0x0000037D RSSIVALID RSSIVALID Interrupt Enable 0 1 read-write CCA CCA Interrupt Enable 2 1 read-write RSSIPOSSTEP RSSIPOSSTEP Interrupt Enable 3 1 read-write RSSINEGSTEP RSSINEGSTEP Interrupt Enable 4 1 read-write SHORTRSSIPOSSTEP SHORTRSSIPOSSTEP Interrupt Enable 6 1 read-write RFPKDPRDDONE RF PKD PERIOD CNT Interrupt Enable 8 1 read-write RFPKDCNTDONE RF PKD pulse CNT Interrupt Enable 9 1 read-write GAINRANGE No Description 0x050 read-write 0x08813187 0x0FFFFFFF LNAINDEXBORDER LNA gain border 0 4 read-write PGAINDEXBORDER PGA gain border 4 4 read-write GAININCSTEP AGC gain increase step size 8 4 read-write PNGAINSTEP PN Gain Step size 12 4 read-write LATCHEDHISTEP Ltached Hi step size 16 4 read-write HIPWRTHD High power detect thrshold 20 6 read-write BOOSTLNA LNA GAIN BOOST mode 26 1 read-write LNABWADJ LNA BW ADJUST 27 1 read-write AGCPERIOD No Description 0x054 read-write 0xD607370E 0xFFFFFFFF PERIODHI AGC measure period hi 0 8 read-write PERIODLO AGC measure period low 8 8 read-write MAXHICNTTHD max hi-countrer threshold 16 8 read-write SETTLETIMEIF IF peak Detector settling time 24 4 read-write SETTLETIMERF RF peak Detector settling time 28 4 read-write HICNTREGION No Description 0x058 read-write 0x08060543 0xFFFFFFFF HICNTREGION0 AGC HICNT to step size map region 0 0 4 read-write HICNTREGION1 AGC HICNT to step size map region 1 4 4 read-write HICNTREGION2 AGC HICNT to step size map region 2 8 8 read-write HICNTREGION3 AGC HICNT to step size map region 3 16 8 read-write HICNTREGION4 AGC HICNT to step size map region 4 24 8 read-write STEPDWN No Description 0x05C read-write 0x00036D11 0x0003FFFF STEPDWN0 AGC gain step size 0 0 3 read-write STEPDWN1 AGC gain step size 1 3 3 read-write STEPDWN2 AGC gain step size 2 6 3 read-write STEPDWN3 AGC gain step size 3 9 3 read-write STEPDWN4 AGC gain step size 4 12 3 read-write STEPDWN5 AGC gain step size 5 15 3 read-write GAINSTEPLIM No Description 0x064 read-write 0x22003144 0x3FFFFFFF CFLOOPSTEPMAX Maximum step in slow loop 0 5 read-write CFLOOPDEL Channel Filter Loop Delay 5 7 read-write HYST Hysteresis 12 4 read-write MAXPWRVAR Maximum Power Variation 16 8 read-write TRANRSTAGC power transient detector Reset AGC 24 1 read-write PNINDEXMAX MAX PN INDEX 25 5 read-write PNRFATT0 No Description 0x068 read-write 0x07142040 0x3FFFFFFF LNAMIXRFATT1 PN RF attenuation code for index 1 0 6 read-write LNAMIXRFATT2 PN RF attenuation code for index 2 6 6 read-write LNAMIXRFATT3 PN RF attenuation code for index 3 12 6 read-write LNAMIXRFATT4 PN RF attenuation code for index 4 18 6 read-write LNAMIXRFATT5 PN RF attenuation code for index 5 24 6 read-write PNRFATT1 No Description 0x06C read-write 0x1F5D038A 0x3FFFFFFF LNAMIXRFATT6 PN RF attenuation code for index 6 0 6 read-write LNAMIXRFATT7 PN RF attenuation code for index 7 6 6 read-write LNAMIXRFATT8 PN RF attenuation code for index 8 12 6 read-write LNAMIXRFATT9 PN RF attenuation code for index 9 18 6 read-write LNAMIXRFATT10 PN RF attenuation code for index 10 24 6 read-write PNRFATT2 No Description 0x070 read-write 0x01A3BAE0 0x03FFFFFF LNAMIXRFATT11 PN RF attenuation code for index 11 0 6 read-write LNAMIXRFATT12 PN RF attenuation code for index 12 6 6 read-write LNAMIXRFATT13 PN RF attenuation code for index 13 12 6 read-write LNAMIXRFATT14 PN RF attenuation code for index 14 18 8 read-write PNRFATT3 No Description 0x074 read-write 0x03E8F67F 0x07FFFFFF LNAMIXRFATT15 PN RF attenuation code for index 15 0 8 read-write LNAMIXRFATT16 PN RF attenuation code for index 16 8 9 read-write LNAMIXRFATT17 PN RF attenuation code for index 17 17 10 read-write LNAMIXCODE0 No Description 0x078 read-write 0x15724BBD 0x3FFFFFFF LNAMIXSLICE1 LNA/MIX slice code for index 1 0 6 read-write LNAMIXSLICE2 LNA/MIX slice code for index 2 6 6 read-write LNAMIXSLICE3 LNA/MIX slice code for index 3 12 6 read-write LNAMIXSLICE4 LNA/MIX slice code for index 4 18 6 read-write LNAMIXSLICE5 LNA/MIX slice code for index 5 24 6 read-write LNAMIXCODE1 No Description 0x07C read-write 0x0518A311 0x3FFFFFFF LNAMIXSLICE6 LNA/MIX slice code for index 6 0 6 read-write LNAMIXSLICE7 LNA/MIX slice code for index 7 6 6 read-write LNAMIXSLICE8 LNA/MIX slice code for index 8 12 6 read-write LNAMIXSLICE9 LNA/MIX slice code for index 9 18 6 read-write LNAMIXSLICE10 LNA/MIX slice code for index 10 24 6 read-write PGACODE0 No Description 0x080 read-write 0x76543210 0xFFFFFFFF PGAGAIN1 PGA GAIN code for index 1 0 4 read-write PGAGAIN2 PGA GAIN code for index 2 4 4 read-write PGAGAIN3 PGA GAIN code for index 3 8 4 read-write PGAGAIN4 PGA GAIN code for index 4 12 4 read-write PGAGAIN5 PGA GAIN code for index 5 16 4 read-write PGAGAIN6 PGA GAIN code for index 6 20 4 read-write PGAGAIN7 PGA GAIN code for index 7 24 4 read-write PGAGAIN8 PGA GAIN code for index 8 28 4 read-write PGACODE1 No Description 0x084 read-write 0x00000A98 0x00000FFF PGAGAIN9 PGA GAIN code for index 9 0 4 read-write PGAGAIN10 PGA GAIN code for index 10 4 4 read-write PGAGAIN11 PGA GAIN code for index 11 8 4 read-write LBT No Description 0x088 read-write 0x00000000 0x0000007F CCARSSIPERIOD RSSI Period during CCA measurements 0 4 read-write ENCCARSSIPERIOD RSSI PERIOD during CCA measurements 4 1 read-write ENCCAGAINREDUCED CCA gain reduced 5 1 read-write ENCCARSSIMAX Use RSSIMAX to indicate CCA 6 1 read-write MIRRORIF No Description 0x08C read-write 0x00000000 0x0000000F RSSIPOSSTEPM Positive RSSI Step Detected 0 1 read-only RSSINEGSTEPM Negative RSSI Step Detected 1 1 read-only SHORTRSSIPOSSTEPM Short-term Positive RSSI Step Detected 2 1 read-only IFMIRRORCLEAR Clear bit for the AGC IF MIRROR Register 3 1 read-write SEQIF No Description 0x090 read-write 0x00000000 0x0000037D RSSIVALID RSSI Value is Valid 0 1 read-write CCA Clear Channel Assessment 2 1 read-write RSSIPOSSTEP Positive RSSI Step Detected 3 1 read-write RSSINEGSTEP Negative RSSI Step Detected 4 1 read-write SHORTRSSIPOSSTEP Short-term Positive RSSI Step Detected 6 1 read-write RFPKDPRDDONE RF PKD PERIOD CNT TOMEOUT 8 1 read-write RFPKDCNTDONE RF PKD pulse CNT TOMEOUT 9 1 read-write SEQIEN No Description 0x094 read-write 0x00000000 0x0000037D RSSIVALID RSSIVALID Interrupt Enable 0 1 read-write CCA CCA Interrupt Enable 2 1 read-write RSSIPOSSTEP RSSIPOSSTEP Interrupt Enable 3 1 read-write RSSINEGSTEP RSSINEGSTEP Interrupt Enable 4 1 read-write SHORTRSSIPOSSTEP SHORTRSSIPOSSTEP Interrupt Enable 6 1 read-write RFPKDPRDDONE RF PKD PERIOD CNT Interrupt Enable 8 1 read-write RFPKDCNTDONE RF PKD pulse CNT Interrupt Enable 9 1 read-write RFCRC_S 0 RFCRC_S Registers 0xA8010000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Enable peripheral clock to this module 0 1 read-write CTRL No Description 0x008 read-write 0x00000704 0x00001FEF INPUTINV Input Invert 0 1 read-write OUTPUTINV Output Invert 1 1 read-write CRCWIDTH 2 2 read-write CRCWIDTH8 8 bit (1 Byte) CRC code 0 CRCWIDTH16 16 bit (2 Bytes) CRC code 1 CRCWIDTH24 24 bit (3 Bytes) CRC code 2 CRCWIDTH32 32 bit (4 Bytes) CRC code 3 INPUTBITORDER CRC input bit ordering setting 5 1 read-write LSBFIRST The least significant data bit is first input to the CRC generator. 0 MSBFIRST The most significant data bit is first input to the CRC generator. 1 BYTEREVERSE Reverse CRC byte ordering over air 6 1 read-write NORMAL The least significant byte of the CRC register is transferred first over air via the Frame Controller. 0 REVERSED The most significant byte of the CRC register is transferred first over air via the Frame Controller. 1 BITREVERSE Reverse CRC bit ordering over air 7 1 read-write NORMAL The bit ordering of CRC data is the same as defined by the BITORDER field in the Frame Controller. 0 REVERSED The bit ordering of CRC data is the opposite as defined by the BITORDER field in the Frame Controller. 1 BITSPERWORD Number of bits per input word 8 4 read-write PADCRCINPUT Pad CRC input data 12 1 read-write X0 No zero-padding of CRC input data is applied 0 X1 CRC input data is zero-padded, such that the number of bytes over which the CRC value is calculated at least equals the length of the calculated CRC value. 1 STATUS No Description 0x00C read-only 0x00000000 0x00000001 BUSY CRC Running 0 1 read-only CMD No Description 0x010 write-only 0x00000000 0x00000001 INITIALIZE Initialize CRC 0 1 write-only INPUTDATA No Description 0x014 write-only 0x00000000 0x0000FFFF INPUTDATA Input Data 0 16 write-only INIT No Description 0x018 read-write 0x00000000 0xFFFFFFFF INIT CRC Initialization Value 0 32 read-write DATA No Description 0x01C read-only 0x00000000 0xFFFFFFFF DATA CRC Data Register 0 32 read-only POLY No Description 0x020 read-write 0x00000000 0xFFFFFFFF POLY CRC Polynomial Value 0 32 read-write MODEM_S 1 MODEM_S Registers 0xA8014000 0x00000000 0x00001000 registers MODEM 35 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Enable peripheral clock to this module 0 1 read-write STATUS No Description 0x008 read-only 0x00000000 0xFFFF7FF7 DEMODSTATE DEMOD state 0 3 read-only OFF Off state 0 TIMINGSEARCH Timing search 1 PRESEARCH Preamble search 2 FRAMESEARCH Frame search 3 RXFRAME Payload Detection 4 FRAMEDETMODE0 Timing search with sliding window (FDM0) 5 FRAMEDETID Frame Detected ID 4 1 read-only FRAMEDET0 Last frame was detected with sync word defined in SYNC0. 0 FRAMEDET1 Last frame was detected with sync word defined in SYNC1. 1 ANTSEL Selected Antenna 5 1 read-only ANTENNA0 Antenna 0 is selected (ANT0 = 1 and ANT1 = 0). 0 ANTENNA1 Antenna 1 is selected (ANT0 = 0 and ANT1 = 1). 1 TIMSEQINV Timing Sequence Inverted 6 1 read-only TIMLOSTCAUSE Timing Lost Cause 7 1 read-only LOWCORR Timing lost during Preamble Search or due to low correlation value during Frame Search. 0 TIMEOUT Timing lost due to incorrect symbols detected during Frame Search. 1 DSADETECTED DSA detected 8 1 read-only DSAFREQESTDONE DSA frequency estimation complete 9 1 read-only VITERBIDEMODTIMDET Viterbi Demod timing detected 10 1 read-only VITERBIDEMODFRAMEDET Viterbi Demod frame detected 11 1 read-only STAMPSTATE BLE Viterbi Demod Timing Stamp 12 3 read-only CORR Correlation 16 8 read-only WEAKSYMBOLS Weak symbols 24 8 read-only TIMDETSTATUS No Description 0x00C read-only 0x00000000 0x1F0FFFFF TIMDETCORR Correlation value 0 8 read-only TIMDETFREQOFFEST Frequency offset estimate 8 8 read-only TIMDETPREERRORS Preamble errors 16 4 read-only TIMDETPASS Timing detection pass 24 1 read-only TIMDETINDEX Timing detection index 25 4 read-only FREQOFFEST No Description 0x010 read-only 0x00000000 0xFFFF1FFF FREQOFFEST Frequency offset estimate 0 13 read-only CORRVAL Correlation value 16 8 read-only SOFTVAL Soft detection value 24 8 read-only AFCADJRX No Description 0x014 read-only 0x00000000 0x0007FFFF AFCADJRX AFC adjustment for RX 0 19 read-only AFCADJTX No Description 0x018 read-only 0x00000000 0x0007FFFF AFCADJTX AFC adjustment for TX 0 19 read-only MIXCTRL No Description 0x01C read-write 0x00000000 0x0000001F ANAMIXMODE Analog receiver mixer mode of operation 0 4 read-write NORMAL The analog mixer operates in its normal mode 0 IPQPIQSWAP I path is positive, Q path is positive, I and Q are swapped 1 IPQN I path is positive, Q path is negative 2 IPQNIQSWAP I path is positive, Q path is negative, I and Q are swapped 3 INQP I path is negative, Q path is positive 4 INQPIQSWAP I path is negative, Q path is positive, I and Q are swapped 5 INQN I path is negative, Q path is negative 6 INQNIQSWAP I path is negative, Q path is negative, I and Q are swapped 7 UPCONVERT Control the analog receiver mixer such that the analog mixer performs a digital up-conversion on the mixer output, with the frequency set by the DEC0 and CFOSR settings. This mode may be used to perform RF loopback using the normal synthesizer both for transmit and receive, and still get a positive IF frequency on the IF receive signal. 8 DOWNCONVERT Control the analog receiver mixer such that the analog mixer performs a digital down-conversion on the mixer output, with the frequency set by the DEC0 and CFOSR settings. 9 DIGIQSWAPEN Digital I/Q swap enable 4 1 read-write CTRL0 No Description 0x020 read-write 0x00000000 0xFFFFFFFF FDM0DIFFDIS Frame Detection Mode 0 disable 0 1 read-write MAPFSK Mapping of FSK symbols 1 3 read-write MAP0 4FSK: Symbol 11, 10, 00, 01 for decreasing frequency. 2FSK/MSK/ASK/OOK: Symbol 1 is high/positive frequency or high amplitude, symbol 0 is low/negative frequency or low amplitude. 0 MAP1 4FSK: Symbol 01, 00, 10, 11 for decreasing frequency. 2FSK/MSK/ASK/OOK: Symbol 0 is high/negative frequency or high amplitude, symbol 1 is low/negative frequency or low amplitude. 1 MAP2 4FSK: Symbol 10, 11, 01, 00 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 2 MAP3 4FSK: Symbol 00, 01, 11, 10 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 3 MAP4 4FSK: Symbol 11, 01, 00, 10 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 4 MAP5 4FSK: Symbol 10, 00, 01, 11 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 5 MAP6 4FSK: Symbol 01, 11, 10, 00 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 6 MAP7 4FSK: Symbol 00, 10, 11, 01 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 7 CODING Symbol coding 4 2 read-write NRZ Non Return to Zero 0 MANCHESTER Manchester Coding 1 DSSS Direct Sequence Spread Spectrum 2 LINECODE Line code. Maps 0 to 0011 symbol and 1 to 1100 symbols 3 MODFORMAT Modulation format 6 3 read-write FSK2 Frequency Shift Keying with 2 symbols 0 FSK4 Frequency Shift Keying with 4 symbols 1 BPSK Binary Phase Shift Keying 2 DBPSK Differentially encoded Binary Phase Shift Keying 3 OQPSK Half Sine Shaped Offset Quadrature Phase Shift Keying 4 MSK Minimum Shift Keying 5 OOKASK On Off Keying and Amplitude Shift Keying 6 DUALCORROPTDIS Dual Correlation Optimization Disable 9 1 read-write OOKASYNCPIN OOK asynchronous pin mode 10 1 read-write DSSSLEN DSSS length 11 5 read-write DSSSSHIFTS DSSS shifts 16 3 read-write NOSHIFT No symbols are defined by shifting. 0 SHIFT1 Next symbol generated by 1 cyclic shift. 1 SHIFT2 Next symbol generated by 2 cyclic shifts. 2 SHIFT4 Next symbol generated by 4 cyclic shifts. 3 SHIFT8 Next symbol generated by 8 cyclic shifts. 4 SHIFT16 Next symbol generated by 16 cyclic shifts. 5 DSSSDOUBLE DSSS double 19 2 read-write DIS Doubling is disabled. 0 INV Doubling is enabled by using inverted symbols. 1 CONJ Doubling is enabled by using complex conjugated symbols. 2 DETDIS Detection disable 21 1 read-write DIFFENCMODE Differential encoding mode 22 3 read-write DIS Differential Encoding is disabled. 0 RR0 Transmit the XOR-ed value of the Raw symbol and the last Raw symbol. Initial Raw symbol is 0. 1 RE0 Transmit the XOR-ed value of the Raw symbol and the last Encoded symbol. Initial Encoded symbol is 0. 2 RR1 Transmit the XOR-ed value of the Raw symbol and the last Raw symbol. Initial Raw symbol is 1. 3 RE1 Transmit the XOR-ed value of the Raw symbol and the last Encoded symbol. Initial Encoded symbol is 1. 4 SHAPING Shaping filter 25 2 read-write DISABLED Filter disabled. 0 ODDLENGTH Filter has odd length. Filter uses coefficients 0,1,2,3,4,5,6,7,8,7,6,5,4,3,2,1,0. 1 EVENLENGTH Filter has even length. Filter uses coefficients 0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0. 2 ASYMMETRIC Filter has asymmetrical coefficients. Filter uses coefficients 0,1,2,3,4,5,6,7. 3 DEMODRAWDATASEL Demod raw data select 27 3 read-write DIS Disabled. 0 ENTROPY 1-bit entropy source extracted from the RF receive chain, to be used for random number generation. 1 ADC 2 * 3-bit I and Q ADC data. 2 FILTLSB 2 * 16-bit I and Q channel filtered data downmixed to zero-IF. The receive signal chain has 19 bits dynamic range at this point, and the FILTLSB setting outputs the 16 least significant bits (with saturation). 3 FILTMSB 2 * 16-bit I and Q channel filtered data downmixed to zero-IF. The receive signal chain has 19 bits dynamic range at this point, and the FILTMSB setting outputs the 16 most significant bits (with truncation). 4 FILTFULL 2 * 19-bit I and Q channel filtered data downmixed to zero-IF. The FILTFULL option will output all 19 bits of dynamic range, sign extended to 32 bits. 5 FREQ 8-bit received frequency data (or logarithmic amplitude for ASK/OOK). 6 DEMOD 8-bit demodulated data (freq/amp/phase). When coherent detection is enabled, only the in-phase component is selected. 7 FRAMEDETDEL FRAMEDET delay 30 2 read-write DEL0 No delay 0 DEL8 8 baud delay 1 DEL16 16 baud delay 2 DEL32 32 baud delay 3 CTRL1 No Description 0x024 read-write 0x00000000 0xFFFFDFFF SYNCBITS Number of sync-word bits 0 5 read-write SYNCERRORS Maximum number of sync errors 5 4 read-write DUALSYNC Dual sync words. 9 1 read-write DISABLED Demodulator only searches for SYNC0. 0 ENABLED Demodulator searches for SYNC0 and SYNC1 in parallel. 1 TXSYNC Transmit sync word. 10 1 read-write SYNC0 Modulator transmits SYNC0. 0 SYNC1 Modulator transmits SYNC1. 1 SYNCDATA Sync data. 11 1 read-write DISABLED SYNC is not part of transmit payload. Modulator adds SYNC in transmit. 0 ENABLED SYNC is part of transmit payload. Modulator does not add SYNC in transmit. 1 SYNC1INV SYNC1 invert. 12 1 read-write COMPMODE Compensation mode 14 2 read-write DIS Compensation is disabled. 0 PRELOCK Compensation locks when preamble is detected. 1 FRAMELOCK Compensation locks when frame is detected. 2 NOLOCK Compensation is always running 3 RESYNCPER Resync period 16 4 read-write PHASEDEMOD Phase demodulation 20 2 read-write BDD Bit Differential Detection. 0 MBDD Multibit Differential Detection. 1 FREQOFFESTPER Frequency offset estimation period 22 3 read-write FREQOFFESTLIM Frequency offset limit 25 7 read-write CTRL2 No Description 0x028 read-write 0x00001000 0xFFFFFFFF SQITHRESH Signal Quality Indicator threshold 0 8 read-write RXFRCDIS Receive FRC disable 8 1 read-write RXPINMODE Receive pin mode 9 1 read-write SYNCHRONOUS Detected payload bits are clocked out on DOUT. Only setups with 1 bit per symbol are supported. 0 ASYNCHRONOUS DOUT is continuously providing the sign of the detected frequency deviation before offset compensation. Only 2/4-FSK is supported. 1 TXPINMODE Transmit pin mode 10 2 read-write OFF Pinmode is turned off. Data is gathered from FRC. DOUT/DCLK clocks out transmitted data. 0 UNUSED Unused mode 1 ASYNCHRONOUS DIN/PRS controls transmitted baud directly. DCLK is set to 0. No support for frame handling nor coding. Only 2-FSK and OOK/ASK can be used. 2 SYNCHRONOUS DIN/PRS is sampled on the rising edge of DCLK and used as payload. Frame handling and coding is supported. Only setups with 1 bit per symbol is supported. 3 DATAFILTER Datafilter 12 3 read-write DISABLED Datafilter disabled 0 SHORT Short datafilter enabled. 2*RXBRFRAC should be more than 3. 1 MEDIUM Medium datafilter enabled. 2*RXBRFRAC should be more than 4. 2 LONG Long datafilter enabled. 2*RXBRFRAC should be more than 5. 3 LEN6 Datafilter with length 6 enabled. 2*RXBRFRAC should be more than 6. 4 LEN7 Datafilter with length 7 enabled. 2*RXBRFRAC should be more than 7. 5 LEN8 Datafilter with length 8 enabled. 2*RXBRFRAC should be more than 8. 6 LEN9 Datafilter with length 9 enabled. 2*RXBRFRAC should be more than 9. 7 BRDIVA Baudrate division factor A 15 4 read-write BRDIVB Baudrate division factor B 19 4 read-write DEVMULA Deviation multiplication factor A 23 2 read-write DEVMULB Deviation multiplication factor B 25 2 read-write RATESELMODE Rate select mode 27 2 read-write NOCHANGE No rate change. BRDIVA/DEVMULA is used for entire frame. 0 PAYLOAD Change rate for payload. BRDIVA/DEVMULA is used for header and BRDIVB/DEVMULB is used for payload. 1 FRC FRC selects between BRDIVA/DEVMULA and BRDIVB/DEVMULB for each symbol in the payload. Header uses BRDIVA/DEVMULA. 2 SYNC The configured/detected syncword decides the settings used for the payload. SYNC0 uses BRDIVA/DEVMULA and SYNC1 uses BRDIVB/DEVMULB. Header uses BRDIVA/DEVMULA. 3 DEVWEIGHTDIS Deviation weighting disable. 29 1 read-write DMASEL DMA select. 30 2 read-write SOFT SOFTVAL field 0 CORR CORRVAL field 1 FREQOFFEST FREQOFFEST field 2 POE POE field 3 CTRL3 No Description 0x02C read-write 0x00008000 0xFFFFFF81 PRSDINEN DIN PRS enable 0 1 read-write ANTDIVMODE Antenna Diversity mode 8 3 read-write ANTENNA0 Antenna 0 (ANT0=1, ANT1=0) is used 0 ANTENNA1 Antenna 1 (ANT0=0, ANT1=1) is used 1 ANTSELFIRST Select-First algorithm. 2 ANTSELCORR Select-Best algorithm based on correlation value. 3 ANTSELRSSI Select-Best algorithm based on RSSI value. 4 ANTDIVREPEATDIS Antenna diversity repeat disable 11 1 read-write TSAMPMODE Timing Search Amplitude Mode 12 2 read-write OFF Amplitude is not used during timing search. 0 ON Timing detection is disabled for windows where at least one sample is below limit set by TSAMPLIM. 1 DIFF Timing detection is disabled for windows where the difference between samples is higher than the limit set by TSAMPLIM. 2 TSAMPDEL Timing Search Amplitude delay 14 2 read-write TSAMPLIM Timing Search Amplitude limit 16 16 read-write CTRL4 No Description 0x030 read-write 0x03000000 0xBFFFFFFF ISICOMP Inter Symbol Interference compensation 0 4 read-write DEVOFFCOMP Deviation offset compensation 4 1 read-write PREDISTGAIN Predistortion gain 5 5 read-write PREDISTDEB Predistortion debounce 10 3 read-write PREDISTAVG Predistortion Average 13 1 read-write AVG8 Average over 8 samples. 0 AVG16 Average over 16 samples. 1 PREDISTRST Predistortion Reset 14 1 read-write PHASECLICKFILT Phase click filter 15 7 read-write SOFTDSSSMODE Soft DSSS mode 22 1 read-write CORR0INV Soft value is inverted value of symbol-0 correlation value. 0 CORRDIFF Soft value is difference between correlation values for symbol-0 and symbol-1. 1 ADCSATLEVEL ADC Saturation Level setting 23 3 read-write CONS1 AGC enters fast loop after first saturation sample. 0 CONS2 2 saturation samples required before AGC enters fast loop. 1 CONS4 4 saturation samples required before AGC enters fast loop. 2 CONS8 8 saturation samples required before AGC enters fast loop. 3 CONS16 16 saturation samples required before AGC enters fast loop. 4 CONS32 32 saturation samples required before AGC enters fast loop. 5 CONS64 64 saturation samples required before AGC enters fast loop. 6 ADCSATDENS ADC Saturation Density setting 26 2 read-write OFFSETPHASEMASKING Offset phase masking 28 1 read-write OFFSETPHASESCALING Offset phase scaling 29 1 read-write CTRL5 No Description 0x034 read-write 0x00000000 0x607007FE BRCALEN Baudrate calibration enable 1 1 read-write BRCALMODE Baudrate calibration mode 2 2 read-write PEAK Measure period between peaks in demodulated signal. This mode can give false peaks for high oversampling ratios without sufficient datafiltering. 0 ZERO Measure period between zero-crossings in demodulated signal. This mode can miss zero-crossings for high frequency offsets. 1 PEAKZERO Combine peak-period and zero-crossing periods. This mode gives best accuracy, but includes weaknesses from both PEAK and ZERO modes. 2 BRCALAVG Baudrate calibration averaging 4 2 read-write DETDEL Detection delay 6 3 read-write TDEDGE Timing detection edge mode 9 1 read-write TREDGE Timing resynchronization edge mode 10 1 read-write DEMODRAWDATASEL2 Demod raw data select 2 20 3 read-write DIS Disabled. 0 CORR 4-bit max_corr_index and 17-bit max_corr . 2 CHPW 8-bit channel power and 4-bit BBSSMUX 3 BBPF 11-bit pre-filter correlation output for BLR and 11-bit pre-filter correlation output for COH demod 4 FSM 5-bit Narrow-band BLE FSM state, 5-bit Long-range BLE FSM state, 3-bit DSA FSM state, 7-bit Detection FSM State. Captured each time state changes 5 RESYNCBAUDTRANS Resynchronization Baud Transitions 29 1 read-write RESYNCLIMIT Resynchronization Limit 30 1 read-write HALF Adjust timing if accumulated timing is higher/lower than RESYNCPER/2. 0 ALWAYS Adjust timing if accumulated timing is non-zero. 1 CTRL6 No Description 0x038 read-write 0x00000000 0xF6000000 CODINGB Coding format 25 2 read-write NRZ Non Return to Zero 0 MANCHESTER Manchester Coding 1 DSSS Direct Sequence Spread Spectrum 2 LINECODE Line code. Maps 0 to 0011 symbol and 1 to 1100 symbols 3 RXBRCALCDIS RX Baudrate Calculation Disable 30 1 read-write TXBR No Description 0x058 read-write 0x00000000 0x00FFFFFF TXBRNUM Transmit baudrate numerator 0 16 read-write TXBRDEN Transmit baudrate denominator 16 8 read-write RXBR No Description 0x05C read-write 0x00000000 0x00001FFF RXBRNUM Receive baudrate numerator 0 5 read-write RXBRDEN Receive baudrate denominator 5 5 read-write RXBRINT Receive baudrate integer 10 3 read-write CF No Description 0x060 read-write 0x00000000 0xCFFFFFFF DEC0 First decimation 0 3 read-write DF3 Decimation Factor 0 = 3. Cutoff 0.050 * f<subscript>HFXO</subscript>. 0 DF4WIDE Decimation Factor 0 = 4. Cutoff 0.069 * f<subscript>HFXO</subscript>. 1 DF4NARROW Decimation Factor 0 = 4. Cutoff 0.037 * f<subscript>HFXO</subscript>. 2 DF8WIDE Decimation Factor 0 = 8. Cutoff 0.012 * f<subscript>HFXO</subscript>. 3 DF8NARROW Decimation Factor 0 = 8. Cutoff 0.005 * f<subscript>HFXO</subscript>. 4 DEC1 Second decimation 3 14 read-write DEC2 Third decimation 17 6 read-write CFOSR Center Frequency Oversampling Ratio 23 3 read-write CF7 Oversampling ratio = 7 0 CF8 Oversampling ratio = 8 1 CF12 Oversampling ratio = 12 2 CF16 Oversampling ratio = 16 3 CF32 Oversampling ratio = 32 4 CF0 Center frequency set to 0 5 DEC1GAIN Second decimation filter gain 26 2 read-write ADD0 No additional gain. Suggested setting for BW higher than 1kHz 0 ADD6 6 dB additional gain. Suggested setting for BW between 250 Hz and 1 kHz 1 ADD12 12 dB additional gain. Suggested setting for BW less than 250 Hz 2 PRE No Description 0x064 read-write 0x00000000 0xFFFF1FFF BASE Preamble base 0 4 read-write BASEBITS BASE bits 4 2 read-write PRESYMB4FSK Preamble symbols 4-FSK 6 1 read-write OUTER Symbols corresponding to +/- 3dev. 0 INNER Symbols corresponding to +/- dev. 1 PREERRORS Preamble errors 7 4 read-write DSSSPRE DSSS preamble 11 1 read-write SYNCSYMB4FSK Sync symbols 4FSK 12 1 read-write FSK2 The syncword is 2FSK modulated. Each bit in SYNCn is encoded as a positive or negative deviation. The deviation is controlled by PRESYMB4FSK. 0 FSK4 The syncword is 4FSK modulated. Every two bits in SYNCn are encoded as a 4FSK symbol. 1 TXBASES TX bases 16 16 read-write SYNC0 No Description 0x068 read-write 0x00000000 0xFFFFFFFF SYNC0 Sync-word 0 0 32 read-write SYNC1 No Description 0x06C read-write 0x00000000 0xFFFFFFFF SYNC1 Sync word 1 0 32 read-write TIMING No Description 0x080 read-write 0x00000000 0xFFFFFFFF TIMTHRESH Timing threshold 0 8 read-write TIMINGBASES Timing bases 8 4 read-write ADDTIMSEQ Additional timing sequences 12 4 read-write TIMSEQINVEN Timing sequence inversion enable 16 1 read-write TIMSEQSYNC Timing sequence part of sync-word 17 1 read-write FDM0THRESH Frame Detection Mode 0 threshold 18 3 read-write OFFSUBNUM Offset subperiod numerator 21 4 read-write OFFSUBDEN Offset subperiod denominator 25 4 read-write TSAGCDEL Timing Search AGC delay 29 1 read-write FASTRESYNC Fast timing resynchronization 30 2 read-write DIS Disabled. 0 PREDET Allow fast resynchronization until preamble is detected. 1 FRAMEDET Allow fast resynchronization until frame is detected. 2 DSSS0 No Description 0x084 read-write 0x00000000 0xFFFFFFFF DSSS0 DSSS symbol 0 0 32 read-write MODINDEX No Description 0x088 read-write 0x00000000 0x003F03FF MODINDEXM Modulation index mantissa. 0 5 read-write MODINDEXE Modulation index exponent. 5 5 read-write FREQGAINE Frequency demodulation gain - exponent 16 3 read-write FREQGAINM Frequency demodulation gain - mantissa 19 3 read-write AFC No Description 0x08C read-write 0x00000000 0x1FFFFDFF AFCSCALEM AFC scaling mantissa 0 5 read-write AFCSCALEE AFC scaling exponent 5 4 read-write AFCRXMODE AFC RX mode 10 3 read-write DIS Disabled. 0 FREE Free running. AFCADJRX constantly updated. 1 FREEPRESTART Free running. AFCADJRX not updated before preamble is detected. 2 TIMLOCK AFCADJRX locked when timing is detected. 3 PRELOCK AFCADJRX locked when preamble is detected. 4 FRAMELOCK AFCADJRX locked when frame is detected. 5 FRAMELOCKPRESTART AFCADJRX not updated before preamble is detected and locked when frame is detected. 6 AFCTXMODE AFC TX mode 13 2 read-write DIS Disabled. 0 PRELOCK AFCADJTX loaded from AFCADJRX when preamble is detected. 1 FRAMELOCK AFCADJTX loaded from AFCADJRX when frame is detected. 2 AFCRXCLR AFCRX clear mode 15 1 read-write AFCDEL AFC delay 16 5 read-write AFCAVGPER AFC average period 21 3 read-write AFCLIMRESET Reset AFCADJRX value 24 1 read-write AFCONESHOT AFC One-Shot feature 25 1 read-write AFCENINTCOMP Internal frequency offset compensation 26 1 read-write AFCDSAFREQOFFEST Consider frequency offset estimation 27 1 read-write AFCDELDET Delay Detection state machine 28 1 read-write AFCADJLIM No Description 0x090 read-write 0x00000000 0x0003FFFF AFCADJLIM AFC adjustment limit 0 18 read-write SHAPING0 No Description 0x094 read-write 0x22130A04 0xFFFFFFFF COEFF0 Shaping Coefficient 0 0 8 read-write COEFF1 Shaping Coefficient 1 8 8 read-write COEFF2 Shaping Coefficient 2 16 8 read-write COEFF3 Shaping Coefficient 3 24 8 read-write SHAPING1 No Description 0x098 read-write 0x4F4A4132 0xFFFFFFFF COEFF4 Shaping Coefficient 4 0 8 read-write COEFF5 Shaping Coefficient 5 8 8 read-write COEFF6 Shaping Coefficient 6 16 8 read-write COEFF7 Shaping Coefficient 7 24 8 read-write SHAPING2 No Description 0x09C read-write 0x00000000 0xFFFFFFFF COEFF8 Shaping Coefficient 8 0 8 read-write COEFF9 Shaping Coefficient 9 8 8 read-write COEFF10 Shaping Coefficient 10 16 8 read-write COEFF11 Shaping Coefficient 11 24 8 read-write SHAPING3 No Description 0x0A0 read-write 0x00000000 0xFFFFFFFF COEFF12 Shaping Coefficient 12 0 8 read-write COEFF13 Shaping Coefficient 13 8 8 read-write COEFF14 Shaping Coefficient 14 16 8 read-write COEFF15 Shaping Coefficient 15 24 8 read-write SHAPING4 No Description 0x0A4 read-write 0x00000000 0xFFFFFFFF COEFF16 Shaping Coefficient 16 0 8 read-write COEFF17 Shaping Coefficient 17 8 8 read-write COEFF18 Shaping Coefficient 18 16 8 read-write COEFF19 Shaping Coefficient 19 24 8 read-write SHAPING5 No Description 0x0A8 read-write 0x00000000 0xFFFFFFFF COEFF20 Shaping Coefficient 20 0 8 read-write COEFF21 Shaping Coefficient 21 8 8 read-write COEFF22 Shaping Coefficient 22 16 8 read-write COEFF23 Shaping Coefficient 23 24 8 read-write SHAPING6 No Description 0x0AC read-write 0x00000000 0xFFFFFFFF COEFF24 Shaping Coefficient 24 0 8 read-write COEFF25 Shaping Coefficient 25 8 8 read-write COEFF26 Shaping Coefficient 26 16 8 read-write COEFF27 Shaping Coefficient 27 24 8 read-write SHAPING7 No Description 0x0B0 read-write 0x00000000 0xFFFFFFFF COEFF28 Shaping Coefficient 28 0 8 read-write COEFF29 Shaping Coefficient 29 8 8 read-write COEFF30 Shaping Coefficient 30 16 8 read-write COEFF31 Shaping Coefficient 31 24 8 read-write SHAPING8 No Description 0x0B4 read-write 0x00000000 0xFFFFFFFF COEFF32 Shaping Coefficient 32 0 8 read-write COEFF33 Shaping Coefficient 33 8 8 read-write COEFF34 Shaping Coefficient 34 16 8 read-write COEFF35 Shaping Coefficient 35 24 8 read-write SHAPING9 No Description 0x0B8 read-write 0x00000000 0xFFFFFFFF COEFF36 Shaping Coefficient 36 0 8 read-write COEFF37 Shaping Coefficient 37 8 8 read-write COEFF38 Shaping Coefficient 38 16 8 read-write COEFF39 Shaping Coefficient 39 24 8 read-write SHAPING10 No Description 0x0BC read-write 0x00000000 0xFFFFFFFF COEFF40 Shaping Coefficient 40 0 8 read-write COEFF41 Shaping Coefficient 41 8 8 read-write COEFF42 Shaping Coefficient 42 16 8 read-write COEFF43 Shaping Coefficient 43 24 8 read-write SHAPING11 No Description 0x0C0 read-write 0x00000000 0xFFFFFFFF COEFF44 Shaping Coefficient 44 0 8 read-write COEFF45 Shaping Coefficient 45 8 8 read-write COEFF46 Shaping Coefficient 46 16 8 read-write COEFF47 Shaping Coefficient 47 24 8 read-write RAMPCTRL No Description 0x0C4 read-write 0x00000555 0xFF800FFF RAMPRATE0 Ramp rate 0 0 4 read-write RAMPRATE1 Ramp rate 1 4 4 read-write RAMPRATE2 Ramp rate 2 8 4 read-write RAMPLEV No Description 0x0CC read-write 0x009F9F9F 0x00FFFFFF RAMPLEV0 Ramp level 0 0 8 read-write RAMPLEV1 Ramp level 1 8 8 read-write RAMPLEV2 Ramp level 2 16 8 read-write DCCOMP No Description 0x0E0 read-write 0x00000030 0x000001FF DCESTIEN DC Offset Estimation Enable 0 1 read-write DCCOMPEN DC Offset Compensation Enable 1 1 read-write DCRSTEN DC Compensation Filter Reset Enable 2 1 read-write DCCOMPFREEZE DC Offset Compensation Filter Freeze 3 1 read-write DCCOMPGEAR DC Offset Compensation Filter Gear 4 3 read-write DCLIMIT DC offset limit 7 2 read-write FULLSCALE 1000 mV 0 FULLSCALEBY4 250 mV 1 FULLSCALEBY8 125 mV 2 FULLSCALEBY16 62 mV 3 DCCOMPFILTINIT No Description 0x0E4 read-write 0x00000000 0x7FFFFFFF DCCOMPINITVALI I-channel initialization value 0 15 read-write DCCOMPINITVALQ Q-channel initialization value 15 15 read-write DCCOMPINIT Initialize filter state 30 1 read-write DCESTI No Description 0x0E8 read-only 0x00000000 0x3FFFFFFF DCCOMPESTIVALI I-channel DC-Offset Estimated value 0 15 read-only DCCOMPESTIVALQ Q-channel DC-Offset Estimated value 15 15 read-only SRCCHF No Description 0x0EC read-write 0x00000000 0xEFFFF8FF SRCRATIO1 I-channel SRC ratio 0 8 read-write SRCENABLE1 SRC1 enable 11 1 read-write SRCRATIO2 Q-channel SRC ratio 12 15 read-write SRCENABLE2 SRC2 enable 27 1 read-write BWSEL Channel filter bandwidth 29 2 read-write X0 wide bandwidth selected ; BW = 0.263*Fxtal/dec0-factor/dec1-factor 0 X1 wide bandwidth selected ; BW = 0.263*Fxtal/dec0-factor/dec1-factor 1 X2 narrow bandwidth selected ; BW = 0.196*Fxtal/dec0-factor/dec1-factor 2 X3 narrow bandwidth selected ; BW = 0.196*Fxtal/dec0-factor/dec1-factor 3 INTOSR Forcing Integer OSR 31 1 read-write DSATHD0 No Description 0x0F4 read-write 0x07830464 0xFFFFFFFF SPIKETHD Spike threshold 0 8 read-write UNMODTHD Unmodulated carrier detector threshold 8 6 read-write FDEVMINTHD Frequency deviation minimum threshold 14 6 read-write FDEVMAXTHD Frequency deviation maximum threshold 20 12 read-write DSATHD1 No Description 0x0F8 read-write 0x3AC81388 0x7FFFFFFF POWABSTHD Power absolute threshold 0 16 read-write POWRELTHD Relative power detector threshold 16 2 read-write DISABLED Threshold is 6dB. The relative power detector will trigger when the current RSSI is 6dB stronger than the previously detected RSSI. 0 MODE1 Threshold is 9dB. The relative power detector will trigger when the current RSSI is 9dB stronger than the previously detected RSSI. 1 MODE2 Threshold is 12dB. The relative power detector will trigger when the current RSSI is 12dB stronger than the previously detected RSSI. 2 MODE3 Threshold is 15dB. The relative power detector will trigger when the current RSSI is 15dB stronger than the previously detected RSSI. 3 DSARSTCNT DSA reset counter 18 3 read-write RSSIJMPTHD RSSI jump detector threshold 21 4 read-write FREQLATDLY Frequency late delay 25 2 read-write PWRFLTBYP Power filter bypass 27 1 read-write AMPFLTBYP Amplitude filter bypass 28 1 read-write PWRDETDIS Power detection disabled 29 1 read-write FREQSCALE Frequency scale factor 30 1 read-write DSACTRL No Description 0x0FC read-write 0x000A2090 0xFFEFFFFF DSAMODE Mode of Digital Signal Arrival detector 0 2 read-write DISABLED DSA is disabled 0 ENABLED DSA is enabled by the relative/absolute RSSI detector and is reset by using detectors for spike content and frequency deviation. The RSSI jump detector is used to recover from false detects. 1 ARRTHD Signal arrival valid counter threshold 2 4 read-write ARRTOLERTHD0 Arrival tolerance threshold 0 6 5 read-write ARRTOLERTHD1 Arrival tolerance threshold 1 11 5 read-write SCHPRD Search period window length 16 1 read-write TS2 The search period is 2 symbol periods. 0 TS4 The search period is 4 symbol periods. 1 FREQAVGSYM DSA frequency estimation averaging 17 1 read-write AVG2TS Frequency estimation over 2 symbol periods. 0 AVG4TS Frequency estimation over 4 symbol periods. 1 TRANRSTDSA power transient detector Reset DSA 18 1 read-write DSARSTON DSA detection reset 19 1 read-write GAINREDUCDLY Detection Delay of AGC gain reduction 21 2 read-write LOWDUTY Low duty cycle delay 23 3 read-write RESTORE Power detector reset of DSA 26 1 read-write AGCBAUDEN Consider Baud_en from AGC 27 1 read-write AMPJUPTHD Amplitude jump detection thrshold 28 4 read-write VITERBIDEMOD No Description 0x100 read-write 0x00206100 0xFFFFFFFF VTDEMODEN Viterbi demodulator enable 0 1 read-write HARDDECISION Hard decision 1 1 read-write VITERBIKSI1 VITERBI KSI1 2 7 read-write VITERBIKSI2 VITERBI KSI2 9 7 read-write VITERBIKSI3 VITERBI KSI3 16 6 read-write SYNTHAFC Synthesizer AFC in Viterbi demod 22 1 read-write CORRCYCLE Correction cycles 23 4 read-write CORRSTPSIZE Correction step size 27 4 read-write DISDEMODOF Disable Demod Over Flow Detection 31 1 read-write VTCORRCFG0 No Description 0x104 read-write 0x123556B7 0xFFFFFFFF EXPECTPATT Expected pattern 0 32 read-write DIGMIXCTRL No Description 0x10C read-write 0x00000000 0x007FFFFF DIGMIXFREQ Digital mixer frequency control word 0 20 read-write DIGMIXMODE Digital mixer frequency control 20 1 read-write CFOSR Mixer frequency specified by CFOSR. 0 DIGMIXFREQ Mixer frequency specified by DIGMIXFREQ. 1 MIXERCONJ Digital mixer input conjugate 21 1 read-write DIGMIXFB Digital mixer Frequency Correction 22 1 read-write VTCORRCFG1 No Description 0x110 read-write 0x29043020 0x7FFFFFFF CORRSHFTLEN Correlator shift length 0 6 read-write VTFRQLIM Viterbi frequency limiter 6 9 read-write EXPSYNCLEN Expected sync length 15 8 read-write BUFFHEAD Buffer header 23 4 read-write EXPECTHT Expected patterns head and tail 27 4 read-write VTTRACK No Description 0x114 read-write 0x4D80BB88 0xFFFFFFFF FREQTRACKMODE Frequency tracking mode 0 2 read-write DISABLED Frequency tracking disabled. Only a one-time frequency offset compensation applied through DSA. 0 MODE1 Frequency tracking enabled with one correction, when needed, every 16 symbol periods. 1 MODE2 Frequency tracking enabled with one correction, when needed, every 32 symbol periods. 2 MODE3 Frequency tracking enabled with one correction, when needed, every 48 symbol periods. 3 TIMTRACKTHD Timing tracking threshold 2 4 read-write TIMEACQUTHD Time acquisition threshold 6 8 read-write TIMCHK Time check 14 1 read-write TIMEOUTMODE Timeout mode 15 1 read-write TIMGEAR Timing Gear 16 2 read-write GEAR0 Execute timing tracking regardless of difference between Early/Late and Current correlation values. Referred to as fast gear. Same as GEAR3 0 GEAR1 Execute timing tracking only when correlation value of Early/Late is 75% or less of the Current correlation value. Referred to as medium gear. 1 GEAR2 Execute timing tracking only when correlation value of Early/Late is 50% or less of the Current correlation value. Referred to as slow gear. 2 FREQBIAS Frequency estimation bias 18 4 read-write HIPWRTHD High Power detection threshold 22 8 read-write SYNCTIMEOUTSEL SYNC-WORD DET TIMEOUT 30 2 read-write BREST No Description 0x118 read-only 0x00000000 0x000007FF BRESTINT Integer part of estimated baudrate 0 6 read-only BRESTNUM Fractional part of estimated baudrate 6 5 read-only AUTOCG No Description 0x124 read-write 0x00000000 0x0000FFFF AUTOCGEN Enable automatic clock gating 0 16 read-write CGCLKSTOP No Description 0x128 read-write 0x00000000 0x0000FFFF FORCEOFF Manual control clocks 0 16 read-write DSATHD2 No Description 0x130 read-write 0x0C660664 0x7FFFFEFF POWABSTHDLOG Power threshold in logarithm-scale 0 8 read-write JUMPDETEN Power jump detection enable 9 1 read-write FDADJTHD Frequency deviation ripple threshold 10 6 read-write PMDETPASSTHD DSA Preamble detection counter threshold 16 4 read-write FREQESTTHD Frequency Estimation Timeout Threshold 20 5 read-write INTERFERDET Interference detection threshold 25 5 read-write PMDETFORCE Force DSA preamble detector 30 1 read-write DIRECTMODE No Description 0x134 read-write 0x0000010C 0x00001F0F DMENABLE Enable Direct Mode 0 1 read-write SYNCASYNC Choose Synchronous or Asynchronous mode 1 1 read-write SYNCPREAM Synchronous mode preamble 2 2 read-write ADD0 No preamble bits appended 0 ADD8 8 preamble bits appended 1 ADD16 16 preamble bits appended 2 ADD32 32 preamble bits appended 3 CLKWIDTH Synchronous mode clock pulse width 8 5 read-write LONGRANGE No Description 0x138 read-write 0x00FA53E8 0x7FFFFFFF LRCORRTHD Correlator threshold 0 11 read-write LRCORRSCHWIN Window size 11 4 read-write LRBLE Enable 15 1 read-write LRTIMCORRTHD Correlator threshold 16 11 read-write LRBLEDSA DSA enable 27 1 read-write LRDEC DEC value 28 3 read-write LONGRANGE1 No Description 0x13C read-write 0x00000000 0x3FFF7FFF LRSS Long Range Signal Selection 0 4 read-write LRTIMEOUTTHD Long Range Time Out Threshold 4 11 read-write CHPWRACCUDEL Channel Power Accumulated Delay 16 2 read-write DEL0 Use accumulated channel power value 0 DEL32 Delayed by 32 chips 1 DEL64 Delayed by 64 chips 2 HYSVAL Hysteresis Value for BBSS 18 3 read-write AVGWIN Average window 21 3 read-write LRSPIKETHADD Long Range DSA spike threshold addition 24 4 read-write LOGICBASEDPUGATE Logic Based Phase Unwrap Gating 28 1 read-write LOGICBASEDLRDEMODGATE Logic Based Long Range Demod Gating 29 1 read-write LONGRANGE2 No Description 0x140 read-write 0x00000000 0xFFFFFFFF LRCHPWRTH1 Long Range channel power threshold 0 8 read-write LRCHPWRTH2 Long Range channel power threshold 8 8 read-write LRCHPWRTH3 Long Range channel power threshold 16 8 read-write LRCHPWRTH4 Long Range channel power threshold 24 8 read-write LONGRANGE3 No Description 0x144 read-write 0x00000000 0xFFFFFFFF LRCHPWRTH5 Long Range channel power threshold 0 8 read-write LRCHPWRTH6 Long Range channel power threshold 8 8 read-write LRCHPWRTH7 Long Range channel power threshold 16 8 read-write LRCHPWRTH8 Long Range channel power threshold 24 8 read-write LONGRANGE4 No Description 0x148 read-write 0x00000000 0xFFFFFFFF LRCHPWRTH9 Long Range channel power threshold 0 8 read-write LRCHPWRTH10 Long Range channel power threshold 8 8 read-write LRCHPWRSH1 Long Range channel power shift 16 4 read-write LRCHPWRSH2 Long Range channel power shift 20 4 read-write LRCHPWRSH3 Long Range channel power shift 24 4 read-write LRCHPWRSH4 Long Range channel power shift 28 4 read-write LONGRANGE5 No Description 0x14C read-write 0x00000000 0x0FFFFFFF LRCHPWRSH5 Long Range channel power shift 0 4 read-write LRCHPWRSH6 Long Range channel power shift 4 4 read-write LRCHPWRSH7 Long Range channel power shift 8 4 read-write LRCHPWRSH8 Long Range channel power shift 12 4 read-write LRCHPWRSH9 Long Range channel power shift 16 4 read-write LRCHPWRSH10 Long Range channel power shift 20 4 read-write LRCHPWRSH11 Long Range channel power shift 24 4 read-write LONGRANGE6 No Description 0x150 read-write 0x00000000 0xFFF7FFFF LRCHPWRSPIKETH Long Range channel power spike threshold 0 8 read-write LRSPIKETHD Long Range spike threshold 8 11 read-write LRCHPWRTH11 Long Range channel power threshold 20 8 read-write LRCHPWRSH12 Long Range channel power shift 28 4 read-write LRFRC No Description 0x154 read-write 0x00000101 0x000001FF CI500 Long Range CI mapping for 500kbps 0 2 read-write FRCACKTIMETHD FRC acknowledge timeout threshold 2 6 read-write LRCORRMODE LR Correlator operation Mode 8 1 read-write DSATHD3 No Description 0x168 read-write 0x07830464 0xFFFFFFFF SPIKETHDLO Spike threshold 0 8 read-write UNMODTHDLO Unmodulated carrier detector threshold 8 6 read-write FDEVMINTHDLO Frequency deviation minimum threshold 14 6 read-write FDEVMAXTHDLO Frequency deviation maximum threshold 20 12 read-write DSATHD4 No Description 0x16C read-write 0x00821388 0x07FFFFFF POWABSTHDLO Power absolute threshold for low power 0 16 read-write ARRTOLERTHD0LO Arrival tolerance threshold 0 16 5 read-write ARRTOLERTHD1LO Arrival tolerance threshold 1 21 5 read-write SWTHD Enable switch threshold for low power 26 1 read-write VTBLETIMING No Description 0x170 read-write 0x00000000 0x0000FFF3 VTBLETIMINGSEL Viterbi BLE timing stamp selection 0 2 read-write FRAMEDET_DELAY Delayed frame detection will be used as Timing stamp. This mode should be selected for legacy demod and Long Range BLE demod. 0 END_FRAME_PULSE The end of frame detection from Narrow Viterbi demod will be used as Timing stamp. This signal is a narrow pulse signal and pulse width is one xo clock cycle. 1 END_FRAME The end of frame detection from Narrow Viterbi demod will be used as Timing stamp. This signal is a wdie pulse signal 2 INV_END_FRAME For testing only. 3 TIMINGDELAY Viterbi BLE Delay timer 4 8 read-write FLENOFF Timing Stamp Frame Length Offset 12 4 read-write IF No Description 0x208 read-write 0x00000000 0x0007FFFF TXFRAMESENT Frame sent 0 1 read-write TXSYNCSENT Sync word sent 1 1 read-write TXPRESENT Preamble sent 2 1 read-write TXRAMPDONE Mod ramper idle 3 1 read-write LDTNOARR No signal Detected in LDT 4 1 read-write PHDSADET PHASE DSA DETECT 5 1 read-write PHYUNCODEDET CONCURRENT UNCODED PHY DET 6 1 read-write PHYCODEDET CONCURRENT CODED PHY DET 7 1 read-write RXTIMDET Timing detected 8 1 read-write RXPREDET Preamble detected 9 1 read-write RXFRAMEDET0 Frame with sync-word 0 detected 10 1 read-write RXFRAMEDET1 Frame with sync-word 1 detected 11 1 read-write RXTIMLOST Timing lost 12 1 read-write RXPRELOST Preamble lost 13 1 read-write RXFRAMEDETOF Frame detection overflow 14 1 read-write RXTIMNF Timing not found 15 1 read-write FRCTIMOUT DEMOD-FRC req/ack timeout 16 1 read-write ETS Early Time Stamp detect 17 1 read-write CFGANTPATTRD cfg 18 1 read-write IEN No Description 0x20C read-write 0x00000000 0x0007FFFF TXFRAMESENT Frame sent 0 1 read-write TXSYNCSENT Sync word sent 1 1 read-write TXPRESENT Preamble sent 2 1 read-write TXRAMPDONE Mod ramper idle 3 1 read-write LDTNOARR No signal Detected in LDT 4 1 read-write PHDSADET PHASE DSA DETECT 5 1 read-write PHYUNCODEDET CONCURRENT UNCODED PHY DET 6 1 read-write PHYCODEDET CONCURRENT CODED PHY DET 7 1 read-write RXTIMDET Timing detected 8 1 read-write RXPREDET Preamble detected 9 1 read-write RXFRAMEDET0 Frame with sync-word 0 detected 10 1 read-write RXFRAMEDET1 Frame with sync-word 1 detected 11 1 read-write RXTIMLOST Timing lost 12 1 read-write RXPRELOST Preamble lost 13 1 read-write RXFRAMEDETOF Frame detection overflow 14 1 read-write RXTIMNF Timing not found 15 1 read-write FRCTIMOUT DEMOD-FRC req/ack timeout 16 1 read-write ETS Early Time Stamp detect 17 1 read-write CFGANTPATTRD CFGANTPATTRD 18 1 read-write CMD No Description 0x218 write-only 0x00000000 0x00000039 PRESTOP Preamble stop 0 1 write-only AFCTXLOCK Lock AFC TX compensation 3 1 write-only AFCTXCLEAR Clear AFC TX compensation. 4 1 write-only AFCRXCLEAR Clear AFC RX compensation. 5 1 write-only FSMSTATUS No Description 0x21C read-only 0x00000000 0x00FFFFFF DETSTATE Detection FSM state 0 7 read-only OFF Off state 0 TIMINGSEARCH Timing search 10 PRESEARCH Preamble search 20 FRAMESEARCH Frame search 30 RXFRAME Payload Detection 40 FRAMEDETMODE0 Timing search with sliding window (FDM0) 50 DSASTATE Demodulator DSA FSM state 7 3 read-only IDLE IDLE state 0 ARRIVALCHK Arrival Check 1 STATUSCHK Status Check 2 SAMPPW SAMP_PW 3 WAITPWRUP WAIT_PWRUP 4 WAITDSALO WAIT_DSALO 5 WAITABORT WAIT_ABORT 6 STOP STOP 7 LRBLESTATE Demodulator long-range BLE FSM state 10 5 read-only IDLE IDLE state 0 CLEANUP CLEANUP 1 CORRCOE CORRCOE 2 WAITLRDSA WAIT_LR_DSA 3 MAXCORR MAXCORR 4 WAITRDY WAIT_RDY 5 FEC1DATA FEC1_DATA 6 FEC1ACK FEC1_ACK 7 PAUSE PAUSE 8 FEC2DATA FEC2_DATA 9 FEC2ACK FEC2_ACK 10 TRACKCUR TRACK_CUR 11 TRACKEAR TRACK_EAR 12 TRACKLAT TRACK_LAT 13 TRACKDONE TRACK_DONE 14 TDECISION T_DECISION 15 STOP STOP 16 NBBLESTATE Demodulator Narrow-band BLE FSM state 15 5 read-only IDLE IDLE state 0 VTINITI VTINITI 1 ADDRNXT ADDR_NXT 2 INICOST INI_COST 3 CALCCOST CALC_COST 4 INITALACQU INITAL_ACQU 5 INITALCOSTCALC INITAL_COST_CALC 6 MINCOSTCALC MIN_COST_CALC 7 FREQACQU FREQ_ACQU 8 FREQACQUDONE FREQ_ACQU_DONE 9 TIMINGACQUEARLY TIMING_ACQU_EARLY 10 TIMINGACQUCURR TIMING_ACQU_CURR 11 TIMINGACQULATE TIMING_ACQU_LATE 12 TIMINGACQUDONE TIMING_ACQU_DONE 13 VIRTBIINIT0 VIRTBI_INIT0 14 VIRTBIINIT1 VIRTBI_INIT1 15 VIRTBIRXSYNC VIRTBI_RXSYNC 16 VIRTBIRXPAYLOAD VIRTBI_RXPAYLOAD 17 HARDRXSYNC HARD_RXSYNC 18 HARDXPAYLOAD HARD_RXPAYLOAD 19 TRACKFREQ TRACK_FREQ 20 TRACKTIMEARLY TRACK_TIM_EARLY 21 TRACKTIMCURR TRACK_TIM_CURR 22 TRACKTIMLATE TRACK_TIM_LATE 23 TRACKDONE TRACK_DONE 24 TRACKDECISION TRACK_DECISION 25 STOP STOP 26 WAITACK WAIT_ACK 27 DEBUG DEBUG 28 ANTDIVSTATE Antenna diversity control state 20 4 read-only IDLE Idle state 0 FIRST_ANT0 First ANT0 selection 1 FIRST_ANT1 First ANT1 selection 2 TIMSEARCH_ANT0 Timing search on ANT0 3 TIMSEARCH_ANT1 Timing search on ANT1 4 TIMDET_ANT0 Check ANT1 after timing detecton ANT0 5 TIMDET_ANT1 Check ANT0 after timing detecton ANT1 6 EVALUATE Evaluate and select better antenna 7 TIMSEARCH_SELECTED Searching on better antenna 8 TIMDET_SELECTED Selected better antenna 9 REPEAT_ANT0 Repeat ANT0 10 REPEAT_ANT1 Repeat ANT1 11 MANUAL Manual mode 15 STATUS2 No Description 0x220 read-only 0x00000000 0xFFFCFFFF CHPWRACCUMUX Channel power 0 8 read-only BBSSMUX Actual Baseband Signal Selection 8 4 read-only LRBLECI RXed packet's LR BLE coding indicator 12 2 read-only LR125k FEC block 2 coded using C=8, 125kbps 0 LR500k FEC block 2 coded using C=2, 500kbps 1 UNCODEDPHY UNCODED PHY DET 14 1 read-only CODEDPHY CODED PHY DET 15 1 read-only RTVTCORR VT demod Correlation 18 14 read-only STATUS3 No Description 0x224 read-only 0x00000000 0x057FFFFF BBPFOUTABS1 Pre-filter Correlation Output 0 11 read-only BBPFOUTABS Pre-filter Correlation Output for BLR 11 11 read-only LRDSALIVE BLRDSA Prefilter above LRSPIKETHD 22 1 read-only LRDSADET DSA prefilter above LRSPIKETHD 24 1 read-only SYNCSECPEAKABTH SYNC second peak above threshold 26 1 read-only IRCAL No Description 0x228 read-write 0x00000000 0x0000FFBF IRCALEN IRCAL enable bit 0 1 read-write MURSHF MUR shift value 1 5 read-write MUISHF MUI shift value 7 6 read-write IRCORREN IR Correction enable bit 13 1 read-write IRCALCOEFRSTCMD IRCAL coef reset cmd 14 1 write-only IRCALIFADCDBG IRCAL IFADC DBG 15 1 read-write IRCALCOEF No Description 0x22C read-only 0x00000000 0x7FFF7FFF CRV CRV coefficient 0 15 read-only CIV CIV coefficient 16 15 read-only BLEIQDSA No Description 0x230 read-write 0x00000000 0xFFFFFFFF BLEIQDSAEN BLEIQDSA Enable 0 1 read-write BLEIQDSATH BLEIQDSA Threshold 1 14 read-write BLEIQDSAIIRCOEFPWR BLEIQDSA IIRCOEFPWR 15 3 read-write BLEIQDSADIFFTH1 BLEIQDSA BLEIQDSADIFFTH1 18 14 read-write BLEIQDSAEXT1 No Description 0x234 read-write 0x0E000000 0x3FFFFFFF FREQSCALEIQDSA I/Q DSA Frequency scale 0 2 read-write CHPWRFIRAVGEN Channel Power FIR Avg Enable 2 1 read-write CHPWRFIRAVGVAL Channel Power FIR Avg Value 3 2 read-write AVG0 No Avg 0 AVG2 2 sample avg 1 AVG4 4 sample avg 2 AVG8 8 sample avg 3 CORRIIRAVGMULFACT Corr IIR Avg Multiplication Factor 5 2 read-write BLEIQDSAADDRBIAS BLEIQDSA ADDRBIAS 7 4 read-write BLEIQDSATHCOMB Threshold when i and q are added 11 14 read-write MAXCORRCNTIQDSA Max Corr Cnt IQDSA 25 4 read-write IIRRST IIR Reset 29 1 read-write SYNCPROPERTIES No Description 0x238 read-write 0x00000000 0x000000FF SYNCCORRCLR Sync auto corr clear bit 0 1 read-write SYNCSECPEAKTH SYNC auto corr second peak threshold 1 7 read-write DIGIGAINCTRL No Description 0x23C read-write 0x00000000 0x000001FF DIGIGAINEN Digital Gain Enable 0 1 read-write DIGIGAINSEL Digital Gain Select 1 5 read-write GAINM3 GAINM3 0 GAINM2P75 GAINM2P75 1 GAINM2P5 GAINM2P5 2 GAINM2P25 GAINM2P25 3 GAINM2 GAINM2 4 GAINM1P75 GAINM1P75 5 GAINM1P5 GAINM1P5 6 GAINM1P25 GAINM1P25 7 GAINM1 GAINM1 8 GAINM0P75 GAINM0P75 9 GAINM0P5 GAINM0P5 10 GAINM0P25 GAINM0P25 11 GAINM0 GAINM0 12 GAINP0P25 GAINP0P25 13 GAINP0P5 GAINP0P5 14 GAINP0P75 GAINP0P75 15 GAINP1 GAINP1 16 GAINP1P25 GAINP1P25 17 GAINP1P5 GAINP1P5 18 GAINP1P75 GAINP1P75 19 GAINP2 GAINP2 20 GAINP2P25 GAINP2P25 21 GAINP2P5 GAINP2P5 22 GAINP2P75 GAINP2P75 23 GAINP3 GAINP3 24 DIGIGAINDOUBLE Digital Gain Doubled 6 1 read-write DIGIGAINHALF Digital Gain Halved 7 1 read-write DEC0GAIN DEC0 Gain Select 8 1 read-write PRSCTRL No Description 0x240 read-write 0x00000000 0x0003FFFF POSTPONESEL 0 2 read-write ADVANCESEL 2 2 read-write NEWWNDSEL 4 2 read-write WEAKSEL 6 2 read-write SYNCSENTSEL 8 2 read-write PRESENTSEL 10 2 read-write LOWCORRSEL 12 2 read-write ANT0SEL 14 2 read-write ANT1SEL 16 2 read-write REALTIMCFE No Description 0x248 read-write 0x001F81F4 0xE01FFFFF MINCOSTTHD Min. Cost thrshold 0 10 read-write RTSCHWIN Real time CFE searching window 10 4 read-write RTSCHMODE Real Time CFE searching mode 14 1 read-write TRACKINGWIN Correlator size for Tracking 15 3 read-write SYNCACQWIN SYNC Correlator Size 18 3 read-write SINEWEN Enable SINE WEIGHT 29 1 read-write VTAFCFRAME Viterbi AFC FRAME Mode 30 1 read-write RTCFEEN Trecs Enable 31 1 read-write SEQIF No Description 0x24C read-write 0x00000000 0x0007FFFF TXFRAMESENT Frame sent 0 1 read-write TXSYNCSENT Sync word sent 1 1 read-write TXPRESENT Preamble sent 2 1 read-write TXRAMPDONE Mod ramper idle 3 1 read-write LDTNOARR No signal Detected in LDT 4 1 read-write PHDSADET PHASE DSA DETECT 5 1 read-write PHYUNCODEDET CONCURRENT UNCODED PHY DET 6 1 read-write PHYCODEDET CONCURRENT CODED PHY DET 7 1 read-write RXTIMDET Timing detected 8 1 read-write RXPREDET Preamble detected 9 1 read-write RXFRAMEDET0 Frame with sync-word 0 detected 10 1 read-write RXFRAMEDET1 Frame with sync-word 1 detected 11 1 read-write RXTIMLOST Timing lost 12 1 read-write RXPRELOST Preamble lost 13 1 read-write RXFRAMEDETOF Frame detection overflow 14 1 read-write RXTIMNF Timing not found 15 1 read-write FRCTIMOUT DEMOD-FRC req/ack timeout 16 1 read-write ETS Early timestamp 17 1 read-write CFGANTPATTRD CFGANTPATTRD 18 1 read-write SEQIEN No Description 0x250 read-write 0x00000000 0x0007FFFF TXFRAMESENT Frame sent 0 1 read-write TXSYNCSENT Sync word sent 1 1 read-write TXPRESENT Preamble sent 2 1 read-write TXRAMPDONE Mod ramper idle 3 1 read-write LDTNOARR No signal Detected in LDT 4 1 read-write PHDSADET PHASE DSA DETECT 5 1 read-write PHYUNCODEDET CONCURRENT UNCODED PHY DET 6 1 read-write PHYCODEDET CONCURRENT CODED PHY DET 7 1 read-write RXTIMDET Timing detected 8 1 read-write RXPREDET Preamble detected 9 1 read-write RXFRAMEDET0 Frame with sync-word 0 detected 10 1 read-write RXFRAMEDET1 Frame with sync-word 1 detected 11 1 read-write RXTIMLOST Timing lost 12 1 read-write RXPRELOST Preamble lost 13 1 read-write RXFRAMEDETOF Frame detection overflow 14 1 read-write RXTIMNF Timing not found 15 1 read-write FRCTIMOUT DEMOD-FRC req/ack timeout 16 1 read-write ETS Early time stamp 17 1 read-write CFGANTPATTRD CFGANTPATTRD 18 1 read-write ETSCTRL No Description 0x254 read-write 0x00000000 0x3FFFF7FF ETSLOC Early Time Stamp Location 0 10 read-write CAPSIGONPRS Capture Signal On PRS 10 1 read-write CAPTRIG Trigger to capture 12 18 read-write ANTSWCTRL No Description 0x258 read-write 0x003C0000 0x01FFFFFF ANTDFLTSEL Ant Default Select 0 6 read-write ANTCOUNT Total Ant count 6 6 read-write ANTSWTYPE Ant Switch Type 12 2 read-write US_2 2us ant switching 0 US_4 4us ant switching 1 US_6 6us ant switching 2 US_8 8us ant switching 3 ANTSWRST Ant SW rst pulse 14 1 write-only CFGANTPATTEN Configure Ant Pattern Enable 15 1 read-write ANTSWENABLE Ant sw enable 16 1 read-write EXTDSTOPPULSECNT Extend Stop Pulse Counter 17 8 read-write ANTSWSTART No Description 0x25C read-write 0x00000000 0x0003FFFF ANTSWSTARTTIM Ant switch start time 0 18 read-write ANTSWEND No Description 0x260 read-write 0x00000000 0x0003FFFF ANTSWENDTIM Ant switch start time 0 18 read-write TRECPMPATT No Description 0x264 read-write 0x55555555 0xFFFFFFFF PMEXPECTPATT Expected PM pattern 0 32 read-write TRECPMDET No Description 0x268 read-write 0x00000017 0xBFFFC3FF PMACQUINGWIN PM Correlator Size 0 3 read-write PMCOSTVALTHD Min COST Validation for AFC 3 3 read-write PMTIMEOUTSEL PM searching timeout Threshold 6 2 read-write PHSCALE PHASE Scaler 8 2 read-write PMMINCOSTTHD Min. Cost thrshold for Trecs PM 14 9 read-write VTPMDETSEL Trecs PM Detection Thrshold 23 2 read-write COSTHYST PM Seaching COST HYST 25 5 read-write PREAMSCH PM detection enable in Trecs 31 1 read-write CFGANTPATT No Description 0x26C read-write 0x00000000 0x3FFFFFFF CFGANTPATTVAL CFGANTPATTVAL 0 30 read-write ETSTIM No Description 0x270 read-write 0x00000000 0x0003FFFF ETSTIMVAL ETSTIMVAL 0 17 read-write ETSCOUNTEREN ETSCOUNTEREN 17 1 read-write ANTSWCTRL1 No Description 0x274 read-write 0x0006AAAA 0x00FFFFFF TIMEPERIOD Time Period of xtal 0 24 read-write COCURRMODE No Description 0x278 read-write 0x00000000 0x80000000 CONCURRENT CONCURRENT MODE Enable 31 1 read-write ANTDIVCTRL No Description 0x27C read-write 0x00000000 0x000001FF ADPRETHRESH Preamble threshold 0 8 read-write ENADPRETHRESH Enable Preamble threshold 8 1 read-write DISABLE Disable use of Preamble threshold after timing detection 0 ENABLE Enable use of Preamble threshold after timing detection 1 BLEIQDSAEXT2 No Description 0x280 read-write 0x00000000 0x000007FF DISMAXPEAKTRACKMODE Disable Max Peak Track Mode 0 1 read-write BBSSDEBOUNCETIM BBSS Debounce Time 1 8 read-write BBSSDIFFCHVAL BBSS Diff Change Val 9 2 read-write GT0 Greater than 0 0 GT1 Greater than 1 1 GT2 Greater than 2 2 GT3 Greater than 3 3 SPARE No Description 0x284 read-write 0x00000000 0x000000FF SPARE Spare register 0 8 read-write IRCALCOEFWR0 No Description 0x288 read-write 0x00000000 0xFFFFFFFF CRVWD CRV coefficient 0 15 read-write CRVWEN CIV Coefficient Write Enable 15 1 read-write CIVWD CIV coefficient 16 15 read-write CIVWEN CIV Coefficient Write Enable 31 1 read-write IRCALCOEFWR1 No Description 0x28C read-write 0x00000000 0xFFFFFFFF CRVWD CRV coefficient 0 15 read-write CRVWEN CIV Coefficient Write Enable 15 1 read-write CIVWD CIV coefficient 16 15 read-write CIVWEN CIV Coefficient Write Enable 31 1 read-write SYNTH_S 1 SYNTH_S Registers 0xA8018000 0x00000000 0x00001000 registers SYNTH 42 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Enable peripheral clock to this module 0 1 read-write STATUS No Description 0x008 read-only 0x00000000 0x04014707 INLOCK RF Synthesizer in Lock 0 1 read-only IFFREQEN Synthesizer IF frequency enable status 1 1 read-only CMD No Description 0x00C write-only 0x00000000 0x0000061F SYNTHSTART Starts the RF synthesizer 0 1 write-only SYNTHSTOP Stops the RF synthesizer 1 1 write-only ENABLEIF Enable the synthesizer IF frequency 2 1 write-only DISABLEIF Disable the synthesizer IF frequency 3 1 write-only CAPCALSTART Start VCO capacitor array calibration 4 1 write-only CTRL No Description 0x010 read-write 0x00000003 0xD9770007 LOCKTHRESHOLD Frequency synthesizer lock threshold 0 3 read-write PRSMUX0 PRS output mux 0 selector 16 3 read-write DISABLED PRS output 0 is disabled 0 INLOCK Synthesizer is in lock 1 LOCK_WINDOW PLL Lock Window, sampled by PFD 2 FPLL Divided PLL clock 3 VCCMP_HI VCO voltage high detected 4 VCO_AMPLITUDE_OK Obsolete. Read returns 1. 5 VCO_DET_OUT_D Obsolete. Read returns 0. 6 PRSMUX1 PRS output mux 1 selector 20 3 read-write DISABLED PRS output 1 is disabled 0 AUXINLOCK Obsolete. read returns 0. 1 REF_IS_LEADING Disabled. Read returns 0. 2 FPLL Divided PLL clock 3 VCCMP_LOW VCO voltage low detected 4 MMD_PRESCALER_RESET_N MMD prescaler reset, active low 5 CLK_SYNTH_DIV2 MMD next denom output, corresponding to the delta-sigma clock, divided by 2. 6 INVCLKSYNTH Invert clk_synth 24 1 read-write NO Do not invert clk_synth 0 YES Invert clk_synth 1 MMDRSTNOVERRIDEEN Enable MMD reset override 30 1 read-write DISABLE Disable MMD reset override 0 ENABLE Enable MMD reset override 1 MMDMANRSTN Manual MMD reset 31 1 read-write RESET Reset MMD and DSM logic 0 NORESET Allow MMD and DSM to run 1 VCDACCTRL No Description 0x02C read-write 0x00000020 0x000001FF VCDACVAL Control voltage to VCO 0 6 read-write VCDACEN Enable VCDAC 6 1 read-write DISABLE VC DAC disabled 0 ENABLE VC DAC enabled 1 LPFEN LPF Enable Control 7 1 read-write DISABLE Disable LPF 0 ENABLE Enable LPF 1 LPFQSEN LPF Quickstart Control 8 1 read-write DISABLE Disable LPF 0 ENABLE Enable LPF 1 FREQ No Description 0x034 read-write 0x00000000 0x0FFFFFFF FREQ RF Carrier Frequency. 0 28 read-write IFFREQ No Description 0x038 read-write 0x00000000 0x001FFFFF IFFREQ IF used in receive mode 0 20 read-write LOSIDE Configure LO in receive 20 1 read-write LOW The local oscillator (LO) is lower in frequency than the receive RF channel. In MODEM_MIXCTRL the ANAMIXMODE field must be set to NORMAL and DIGIQSWAPEN must be cleared. 0 HIGH The local oscillator (LO) is higher in frequency than the receive RF channel. In MODEM_MIXCTRL the ANAMIXMODE field must be set to CONJUGATE and DIGIQSWAPEN must be set. 1 DIVCTRL No Description 0x03C read-write 0x00000001 0x000001FF LODIVFREQCTRL Frequency division 0 9 read-write LODIV1 Divide LO frequency by 1. 1 LODIV2 Divide LO frequency by 2. 2 LODIV3 Divide LO frequency by 3. 3 LODIV4 Divide LO frequency by 4. 4 LODIV5 Divide LO frequency by 5. 5 LODIV7 Divide LO frequency by 7. 7 LODIV6 Divide LO frequency by 6. 19 LODIV8 Divide LO frequency by 8. 20 LODIV10 Divide LO frequency by 10. 21 LODIV14 Divide LO frequency by 14. 23 LODIV9 Divide LO frequency by 9. 27 LODIV12 Divide LO frequency by 12. 28 LODIV15 Divide LO frequency by 15. 29 LODIV16 Divide LO frequency by 16. 36 LODIV20 Divide LO frequency by 20. 37 LODIV18 Divide LO frequency by 18. 155 LODIV24 Divide LO frequency by 24. 156 CHCTRL No Description 0x040 read-write 0x00000000 0x0000003F CHNO Channel number 0 6 read-write CHSP No Description 0x044 read-write 0x00000000 0x0003FFFF CHSP Channel spacing 0 18 read-write CALOFFSET No Description 0x048 read-write 0x00000000 0x00007FFF CALOFFSET Carrier calibration offset 0 15 read-write VCOTUNING No Description 0x04C read-write 0x00008400 0x0000FFFF VCOTUNING VCO capacitor array calibration value. 0 11 read-write VCAPSEL VCO varactor cap select 11 5 read-write VCOGAIN No Description 0x058 read-write 0x00000077 0x000000FF VCOKVCOARSE VCO varactor coarse gain setting 0 4 read-write VCOKVFINE VCO varactor fine gain setting 4 4 read-write IF No Description 0x078 read-write 0x00000000 0x00000237 LOCKED Synthesizer locked Interrupt Flag 0 1 read-write UNLOCKED Synthesizer unlocked Interrupt Flag 1 1 read-write SYRDY Synthesizer ready Interrupt Flag 2 1 read-write VCOHIGH VCO high voltage Interrupt Flag 4 1 read-write VCOLOW VCO low voltage Interrupt Flag 5 1 read-write LOCNTDONE LOCNT measurement done Interrupt Flag 9 1 read-write IEN No Description 0x084 read-write 0x00000000 0x00000237 LOCKED LOCKED Interrupt Enable 0 1 read-write UNLOCKED UNLOCKED Interrupt Enable 1 1 read-write SYRDY CAPCALDONE Interrupt Enable 2 1 read-write VCOHIGH VCOHIGH Interrupt Enable 4 1 read-write VCOLOW VCOLOW Interrupt Enable 5 1 read-write LOCNTDONE LOCNTDONE Interrupt Enable 9 1 read-write LOCNTCTRL No Description 0x088 read-write 0x00000000 0x00000FFF ENABLE Enable LO Counter 0 1 read-write OFF LO counter is disabled 0 ON LO counter is enabled 1 CLEAR Clear LO Counter 1 1 write-only OFF Do not clear LO counter 0 ON Clear LO counter 1 RUN Run LO Counter 2 1 write-only OFF Do not run LO counter 0 ON Run LO counter 1 READ Read LO Counter 3 1 read-write OFF LOCOUNT register read returns all 0's 0 ON LOCOUNT register read returns count value 1 NUMCYCLE Number of Clock Cycles to Run LO Counter 4 4 read-write CNT_2 Set count length to 2 XO clock cycles 0 CNT_4 Set count length to 4 XO clock cycles 1 CNT_8 Set count length to 8 XO clock cycles 2 CNT_16 Set count length to 16 XO clock cycles 3 CNT_32 Set count length to 32 XO clock cycles 4 CNT_64 Set count length to 64 XO clock cycles 5 CNT_128 Set count length to 128 XO clock cycles 6 CNT_256 Set count length to 256 XO clock cycles 7 CNT_512 Set count length to 512 XO clock cycles 8 CNT_1024 Set count length to 1024 XO clock cycles 9 CNT_2048 Set count length to 2048 XO clock cycles 10 CNT_4096 Set count length to 4096 XO clock cycles 11 CNT_8192 Set count length to 8192 XO clock cycles 12 LOCNTOVERRIDEEN Enable manual override of CLEAR and RUN 8 1 read-write DISABLE Disable manual override 0 ENABLE Enable manual override 1 LOCNTMANCLEAR Manual Control of LO counter CLEAR 9 1 read-write NOCLEAR Don't clear LO counter 0 CLEAR Clear LO counter 1 LOCNTMANRUN Manual Control of the LO counter RUN 10 1 read-write NORUN Don't initiate start/stop LO counter 0 RUN Initiate start/stop of LO counter 1 FCALRUNCLKEN Enable FCAL run pulse counter clock 11 1 read-write DISABLE Don't enable clock 0 ENABLE Enable clock 1 LOCNTSTATUS No Description 0x08C read-only 0x00000000 0x000FFFFF LOCOUNT LO Counter Value 0 19 read-only BUSY LO Counter is Busy 19 1 read-only LOCNTTARGET No Description 0x090 read-only 0x00000000 0x0007FFFF TARGET LO Counter Measurement Target 0 19 read-only MMDDENOMINIT No Description 0x094 read-write 0x00000000 0x07FFFFFF DENOMINIT0 New BitField 0 9 read-write DENOMINIT1 New BitField 9 9 read-write DENOMINIT2 New BitField 18 9 read-write CHPDACINIT No Description 0x098 read-write 0x00000000 0x00000FFF DACINIT Initial CHP DAC Value 0 12 read-write LPFCTRL1CAL No Description 0x09C read-write 0x00000000 0x0003FFFF OP1BWCAL LPF Op1 BW Control in Cal Mode 0 4 read-write OP1COMPCAL LPF Op1 Comp Control in Cal Mode 4 4 read-write RFBVALCAL LPF Rfb Value Select in Cal Mode 8 3 read-write RPVALCAL LPF Rp Value Select in Cal Mode 11 3 read-write RZVALCAL LPF Rz Value Select in Cal Mode 14 4 read-write LPFCTRL1RX No Description 0x0A0 read-write 0x00000000 0x0003FFFF OP1BWRX LPF Op1 BW Control in RX Mode 0 4 read-write OP1COMPRX LPF Op1 Comp Control in RX Mode 4 4 read-write RFBVALRX LPF Rfb Value Select in RX Mode 8 3 read-write RPVALRX LPF Rp Value Select in RX Mode 11 3 read-write RZVALRX LPF Rz Value Select in RX Mode 14 4 read-write LPFCTRL1TX No Description 0x0A4 read-write 0x00000000 0x0003FFFF OP1BWTX LPF Op1 BW Control in TX Mode 0 4 read-write OP1COMPTX LPF Op1 Comp Control in TX Mode 4 4 read-write RFBVALTX LPF Rfb Value Select in TX Mode 8 3 read-write RPVALTX LPF Rp Value Select in TX Mode 11 3 read-write RZVALTX LPF Rz Value Select in TX Mode 14 4 read-write LPFCTRL2RX No Description 0x0A8 read-write 0x00000000 0x1FFFFFFF LPFSWENRX LPF Switching Enable in RX Mode 0 1 read-write DISABLE Disable switching 0 ENABLE Enable switching 1 LPFINCAPRX LPF Input Cap Select in RX Mode 1 2 read-write LPFGNDSWENRX LPF Gnd Switch Enable in RX Mode 3 1 read-write DISABLE Disable GND switching 0 ENABLE Enable GND switching 1 CALCRX LPF Cap Cal Select in RX Mode 4 5 read-write CASELRX LPF Ca Select in RX Mode 9 1 read-write DISABLE Disable Ca 0 ENABLE Enable Ca 1 CAVALRX LPF Ca Value Select in RX Mode 10 5 read-write CFBSELRX LPF Cfb Select in RX Mode 15 1 read-write DISABLE Disable Cfb 0 ENABLE Enable Cfb 1 CZSELRX LPF Cz Select in RX Mode 16 1 read-write DISABLE Disable Cz 0 ENABLE Enable Cz 1 CZVALRX LPF Cz Value Select in RX Mode 17 8 read-write MODESELRX LPF Filter Mode Select in RX Mode 25 1 read-write ONEOP Sets 1 opamp configuration 0 TWOOP Sets 2 opamp configuration 1 VCMLVLRX LPF Vcm Level Select in RX Mode 26 3 read-write LPFCTRL2TX No Description 0x0AC read-write 0x00000000 0x1FFFFFFF LPFSWENTX LPF Switching Enable in TX Mode 0 1 read-write DISABLE Disable switching 0 ENABLE Enable switching 1 LPFINCAPTX LPF Input Cap Select in TX Mode 1 2 read-write LPFGNDSWENTX LPF Gnd Switch Enable in TX Mode 3 1 read-write DISABLE Disable GND switching 0 ENABLE Enable GND switching 1 CALCTX LPF Cap Cal Select in TX Mode 4 5 read-write CASELTX LPF Ca Select in TX Mode 9 1 read-write DISABLE Disable Ca 0 ENABLE Enable Ca 1 CAVALTX LPF Ca Value Select in TX Mode 10 5 read-write CFBSELTX LPF Cfb Select in TX Mode 15 1 read-write DISABLE Disable Cfb 0 ENABLE Enable Cfb 1 CZSELTX LPF Cz Select in TX Mode 16 1 read-write DISABLE Disable Cz 0 ENABLE Enable Cz 1 CZVALTX LPF Cz Value Select in TX Mode 17 8 read-write MODESELTX LPF Filter Mode Select in TX Mode 25 1 read-write ONEOP 1 opamp configuration 0 TWOOP 2 opamp configuration 1 VCMLVLTX LPF Vcm Level Select in TX Mode 26 3 read-write DSMCTRLRX No Description 0x0B0 read-write 0x00000013 0x070003FF DITHERDSMINPUTRX Dithering of DSM input for RX mode 0 1 read-write DITHERDSMOUTPUTRX Dithering of DSM output for RX mode 1 3 read-write DITHERDACRX Dithering of charge pump DAC for RX mode 4 4 read-write DSMMODERX Delta-sigma topology for RX mode 8 1 read-write FEEDFORWARD Feed forward architecture 0 MASH MASH architecture. Note that the delta-sigma output dithering (DITHERDSMOUTPUT) is not available in this mode. 1 LSBFORCERX Delta-sigma input force LSB for RX mode 9 1 read-write DEMMODERX DEM Mode for RX mode 24 1 read-write DISABLED DEM is disabled 0 ENABLED DEM is enabled 1 MASHORDERRX MASH order for RX mode 25 1 read-write SECOND 2nd Order Mash 0 THIRD 3rd Order Mash 1 REQORDERRX ReQuant order for RX mode 26 1 read-write FIRST 1st Order DAC 0 SECOND 2rd Order DAC 1 DSMCTRLTX No Description 0x0B4 read-write 0x00000013 0x070003FF DITHERDSMINPUTTX Dithering of DSM input for TX mode 0 1 read-write DITHERDSMOUTPUTTX Dithering of DSM output for TX mode 1 3 read-write DITHERDACTX Dithering of charge pump DAC for TX mode 4 4 read-write DSMMODETX Delta-sigma topology for TX mode 8 1 read-write FEEDFORWARD Feed forward architecture 0 MASH MASH architecture. Note that the delta-sigma output dithering (DITHERDSMOUTPUT) is not available in this mode. 1 LSBFORCETX Delta-sigma input force LSB for TX mode 9 1 read-write DEMMODETX DEM Mode for TX mode 24 1 read-write DISABLED DEM is disabled 0 ENABLED DEM is enabled 1 MASHORDERTX MASH order for TX mode 25 1 read-write SECOND 2nd Order Mash 0 THIRD 3rd Order Mash 1 REQORDERTX ReQuant order for TX mode 26 1 read-write FIRST 1st Order DAC 0 SECOND 2rd Order DAC 1 SEQIF No Description 0x0B8 read-write 0x00000000 0x00000237 LOCKED Synthesizer locked Interrupt Flag 0 1 read-write UNLOCKED Synthesizer unlocked Interrupt Flag 1 1 read-write SYRDY Synthesizer ready Interrupt Flag 2 1 read-write VCOHIGH VCO high voltage Interrupt Flag 4 1 read-write VCOLOW VCO low voltage Interrupt Flag 5 1 read-write LOCNTDONE LOCNT measurement done Interrupt Flag 9 1 read-write SEQIEN No Description 0x0BC read-write 0x00000000 0x00000237 LOCKED LOCKED Interrupt Enable 0 1 read-write UNLOCKED UNLOCKED Interrupt Enable 1 1 read-write SYRDY CAPCALDONE Interrupt Enable 2 1 read-write VCOHIGH VCOHIGH Interrupt Enable 4 1 read-write VCOLOW VCOLOW Interrupt Enable 5 1 read-write LOCNTDONE LOCNTDONE Interrupt Enable 9 1 read-write PROTIMER_S 1 PROTIMER_S Registers 0xA801C000 0x00000000 0x00001000 registers PROTIMER 36 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IPVERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN EN 0 1 read-write CTRL No Description 0x008 read-write 0x00000000 0x3FF33336 DEBUGRUN Debug Mode Run Enable 1 1 read-write X0 PROTIMER is frozen in debug mode 0 X1 PROTIMER is running in debug mode 1 DMACLRACT DMA Request Clear on Active 2 1 read-write OSMEN One-Shot Mode Enable 4 1 read-write X0 Protimer continues to count when WRAP counter overflows. 0 X1 Protimer stops counting when WRAP counter overflows. 1 ZEROSTARTEN Start from zero enable 5 1 read-write X0 Protimer starts from the previous count value 0 X1 Protimer starts counting from zero 1 PRECNTSRC Selects clock to Pre-counter 8 2 read-write DISABLED Disable Pre-counter 0 CLOCK Module clock 1 UNUSED0 Do not use 2 UNUSED1 Do not use 3 BASECNTSRC Selects clock to Base counter 12 2 read-write DISABLED Disable base counter 0 PRECNTOF Pre-counter overflow events 1 UNUSED0 Do not use 2 UNUSED1 Do not use 3 WRAPCNTSRC Selects clock to Wrap counter 16 2 read-write DISABLED Disable Wrap counter 0 PRECNTOF Pre-counter overflow events 1 BASECNTOF Base counter overflow events 2 UNUSED Do not use 3 TOUT0SRC Selects clock to timeout counter 0 20 2 read-write DISABLED No counting 0 PRECNTOF Pre-counter overflow events 1 BASECNTOF Base counter overflow events 2 WRAPCNTOF Wrap counter overflow events 3 TOUT0SYNCSRC Select timeout counter 0 event 22 2 read-write DISABLED No synchronization 0 PRECNTOF Pre-counter overflow event 1 BASECNTOF Base counter overflow event 2 WRAPCNTOF Wrap counter overflow event 3 TOUT1SRC Selects clock to timeout counter 1 24 2 read-write DISABLED No counting 0 PRECNTOF Pre-counter overflow events 1 BASECNTOF Base counter overflow events 2 WRAPCNTOF Wrap counter overflow events 3 TOUT1SYNCSRC Select timeout counter 1 event 26 2 read-write DISABLED No synchronization 0 PRECNTOF Pre-counter overflow event 1 BASECNTOF Base counter overflow event 2 WRAPCNTOF Wrap counter overflow event 3 TOUT0MODE Repeat Mode 28 1 read-write FREE When started, the TOUT0 counts down until it is stopped by software 0 ONESHOT TOUT0 is stopped after it reaches zero 1 TOUT1MODE Repeat Mode 29 1 read-write FREE When started, the TOUT1 counts down until it is stopped by software 0 ONESHOT TOUT1 is stopped after it reaches zero 1 CMD No Description 0x00C write-only 0x00000000 0x000707F7 START Start PROTIMER 0 1 write-only RTCSYNCSTART Start PROTIMER Synchronized with RTCC 1 1 write-only STOP Stop PROTIMER 2 1 write-only TOUT0START Start Timeout counter 0 4 1 write-only TOUT0STOP Stop Timeout counter 0 5 1 write-only TOUT1START Start Timeout counter 1 6 1 write-only TOUT1STOP Stop Timeout counter 0 7 1 write-only FORCETXIDLE Force to Idle state of tx_state 8 1 write-only FORCERXIDLE Force to Idle state of rx_state 9 1 write-only FORCERXRX Force to Rx state of rx_state 10 1 write-only LBTSTART LBT sequence start 16 1 write-only LBTPAUSE Pause LBT sequence 17 1 write-only LBTSTOP LBT sequence stop 18 1 write-only PRSCTRL No Description 0x010 read-write 0x00000000 0x000E0E0E STARTPRSEN Enable Protimer start commands from PRS. 1 1 read-write STARTEDGE Start Command Edge Select 2 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 STOPPRSEN Enable Protimer stop commands from PRS. 9 1 read-write STOPEDGE Stop Command Edge Select 10 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 RTCCTRIGGERPRSEN Enable RTCC Trigger from PRS. 17 1 read-write RTCCTRIGGEREDGE RTCC Trigger Edge Select 18 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 STATUS No Description 0x014 read-only 0x00000000 0x0000FFFF RUNNING Running 0 1 read-only LBTSYNC LBT Synchronizing 1 1 read-only LBTRUNNING LBT Running 2 1 read-only LBTPAUSED LBT has been paused. 3 1 read-only TOUT0RUNNING Timeout Counter 0 Running 4 1 read-only TOUT0SYNC Timeout Counter 0 Synchronizing 5 1 read-only TOUT1RUNNING Timeout Counter 1 Running 6 1 read-only TOUT1SYNC Timeout Counter 1 Synchronizing 7 1 read-only ICV0 CC0 Capture Valid 8 1 read-only X0 PROTIMER_CC0_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC0_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV1 CC1 Capture Valid 9 1 read-only X0 PROTIMER_CC1_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC1_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV2 CC2 Capture Valid 10 1 read-only X0 PROTIMER_CC2_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC2_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV3 CC3 Capture Valid 11 1 read-only X0 PROTIMER_CC3_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC3_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV4 CC4 Capture Valid 12 1 read-only X0 PROTIMER_CC4_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC4_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV5 CC5 Capture Valid 13 1 read-only ICV6 CC6 Capture Valid 14 1 read-only ICV7 CC7 Capture Valid 15 1 read-only PRECNT No Description 0x018 read-write 0x00000000 0x0000FFFF PRECNT Pre Counter Value 0 16 read-write BASECNT No Description 0x01C read-write 0x00000000 0x0000FFFF BASECNT Base Counter Value 0 16 read-write WRAPCNT No Description 0x020 read-write 0x00000000 0xFFFFFFFF WRAPCNT Wrap Counter Value 0 32 read-write BASEPRE No Description 0x024 read-only 0x00000000 0xFFFFFFFF PRECNTV Pre counter value 0 16 read-only BASECNTV Base counter value 16 16 read-only LWRAPCNT No Description 0x028 read-only 0x00000000 0xFFFFFFFF LWRAPCNT Latched Wrap Counter Value 0 32 read-only PRECNTTOPADJ No Description 0x02C read-write 0x00000000 0x0000FFFF PRECNTTOPADJ PRECNT Top Adjust Value 0 16 read-write PRECNTTOP No Description 0x030 read-write 0x00FFFF00 0x00FFFFFF PRECNTTOPFRAC PRECNT Top Fractional Value 0 8 read-write PRECNTTOP PRECNT Top Value 8 16 read-write BASECNTTOP No Description 0x034 read-write 0x0000FFFF 0x0000FFFF BASECNTTOP BASECNT Top Value 0 16 read-write WRAPCNTTOP No Description 0x038 read-write 0xFFFFFFFF 0xFFFFFFFF WRAPCNTTOP WRAPCNT Top Value 0 32 read-write TOUT0CNT No Description 0x03C read-write 0x00000000 0xFFFFFFFF TOUT0PCNT TOUT0PCNT Value 0 16 read-write TOUT0CNT TOUT0CNT Value 16 16 read-write TOUT0CNTTOP No Description 0x040 read-write 0x00FF00FF 0xFFFFFFFF TOUT0PCNTTOP TOUT0PCNTTOP Value 0 16 read-write TOUT0CNTTOP TOUT0CNTTOP Value 16 16 read-write TOUT0COMP No Description 0x044 read-write 0x00000000 0xFFFFFFFF TOUT0PCNTCOMP TOUT0PCNTCOMP 0 16 read-write TOUT0CNTCOMP TOUT0CNTCOMP Value 16 16 read-write TOUT1CNT No Description 0x048 read-write 0x00000000 0xFFFFFFFF TOUT1PCNT TOUT1PCNT Value 0 16 read-write TOUT1CNT TOUT1CNT Value 16 16 read-write TOUT1CNTTOP No Description 0x04C read-write 0x00FF00FF 0xFFFFFFFF TOUT1PCNTTOP TOUT1PCNTTOP Value 0 16 read-write TOUT1CNTTOP TOUT1CNTTOP Value 16 16 read-write TOUT1COMP No Description 0x050 read-write 0x00000000 0xFFFFFFFF TOUT1PCNTCOMP TOUT1PCNTCOMP 0 16 read-write TOUT1CNTCOMP TOUT1CNTCOMP Value 16 16 read-write LBTCTRL No Description 0x054 read-write 0x00000000 0x0F1F1FFF STARTEXP Start Exponent 0 4 read-write EXP0 STARTEXP value = 0 (used for Fast TX) 0 EXP1 STARTEXP value = 1 1 EXP2 STARTEXP value = 2 2 EXP3 STARTEXP value = 3 3 EXP4 STARTEXP value = 4 4 EXP5 STARTEXP value = 5 5 EXP6 STARTEXP value = 6 6 EXP7 STARTEXP value = 7 7 EXP8 STARTEXP value = 8 8 MAXEXP Maximum Exponent 4 4 read-write EXP0 MAXEXP value = 0 0 EXP1 MAXEXP value = 1 1 EXP2 MAXEXP value = 2 2 EXP3 MAXEXP value = 3 3 EXP4 MAXEXP value = 4 4 EXP5 MAXEXP value = 5 5 EXP6 MAXEXP value = 6 6 EXP7 MAXEXP value = 7 7 EXP8 MAXEXP value = 8 8 CCADELAY Clear Channel Assessment Delay 8 5 read-write CCAREPEAT Clear Channel Assessment Repeat 16 4 read-write FIXEDBACKOFF Fixed backoff 20 1 read-write RETRYLIMIT Retry Limit 24 4 read-write LBTPRSCTRL No Description 0x058 read-write 0x00000000 0x01010100 LBTSTARTPRSEN Enable LBT start commands from PRS. 8 1 read-write LBTPAUSEPRSEN Enable LBT pause commands from PRS. 16 1 read-write LBTSTOPPRSEN Enable LBT stop commands from PRS. 24 1 read-write LBTSTATE No Description 0x05C read-write 0x00000000 0xFFFFFFFF TOUT0PCNT TOUT0PCNT value to be saved 0 16 read-write TOUT0CNT TOUT0CNT value to be saved 16 16 read-write RANDOM No Description 0x060 read-write 0x00000000 0x0000FFFF RANDOM Pseudo Random Value 0 16 read-write IF No Description 0x064 read-write 0x00000000 0x3FFFFFF7 PRECNTOF PRECNT Overflow Interrupt Flag 0 1 read-write BASECNTOF BASECNT Overflow Interrupt Flag 1 1 read-write WRAPCNTOF WRAPCNT Overflow Interrupt Flag 2 1 read-write TOUT0 TOUT0 underflow interrupt flag 4 1 read-write TOUT1 TOUT1 underflow interrupt flag 5 1 read-write TOUT0MATCH TOUT0 compare match interrupt flag 6 1 read-write TOUT1MATCH TOUT1 compare match interrupt flag 7 1 read-write CC0 CC Channel 0 Interrupt Flag 8 1 read-write CC1 CC Channel 1 Interrupt Flag 9 1 read-write CC2 CC Channel 2 Interrupt Flag 10 1 read-write CC3 CC Channel 3 Interrupt Flag 11 1 read-write CC4 CC Channel 4 Interrupt Flag 12 1 read-write CC5 CC Channel 5 Interrupt Flag 13 1 read-write CC6 CC Channel 6 Interrupt Flag 14 1 read-write CC7 CC Channel 7 Interrupt Flag 15 1 read-write COF0 CC Channel 0 Overflow Interrupt Flag 16 1 read-write COF1 CC Channel 1 Overflow Interrupt Flag 17 1 read-write COF2 CC Channel 2 Overflow Interrupt Flag 18 1 read-write COF3 CC Channel 3 Overflow Interrupt Flag 19 1 read-write COF4 CC Channel 4 Overflow Interrupt Flag 20 1 read-write COF5 CC Channel 5 Overflow Interrupt Flag 21 1 read-write COF6 CC Channel 6 Overflow Interrupt Flag 22 1 read-write COF7 CC Channel 7 Overflow Interrupt Flag 23 1 read-write LBTSUCCESS Listen Before Talk Success 24 1 read-write LBTFAILURE Listen Before Talk Failure 25 1 read-write LBTPAUSED Listen Before Talk Paused 26 1 read-write LBTRETRY Listen Before Talk Retry 27 1 read-write RTCCSYNCHED PROTIMER synchronized with the RTCC 28 1 read-write TOUT0MATCHLBT TOUT0 compare match interrupt flag 29 1 read-write IEN No Description 0x070 read-write 0x00000000 0x3FFFFFF7 PRECNTOF PRECNTOF Interrupt Enable 0 1 read-write BASECNTOF BASECNTOF Interrupt Enable 1 1 read-write WRAPCNTOF WRAPCNTOF Interrupt Enable 2 1 read-write TOUT0 TOUT0 Interrupt Enable 4 1 read-write TOUT1 TOUT1 Interrupt Enable 5 1 read-write TOUT0MATCH TOUT0MATCH Interrupt Enable 6 1 read-write TOUT1MATCH TOUT1MATCH Interrupt Enable 7 1 read-write CC0 CC0 Interrupt Enable 8 1 read-write CC1 CC1 Interrupt Enable 9 1 read-write CC2 CC2 Interrupt Enable 10 1 read-write CC3 CC3 Interrupt Enable 11 1 read-write CC4 CC4 Interrupt Enable 12 1 read-write CC5 CC5 Interrupt Enable 13 1 read-write CC6 CC6 Interrupt Enable 14 1 read-write CC7 CC7 Interrupt Enable 15 1 read-write COF0 COF0 Interrupt Enable 16 1 read-write COF1 COF1 Interrupt Enable 17 1 read-write COF2 COF2 Interrupt Enable 18 1 read-write COF3 COF3 Interrupt Enable 19 1 read-write COF4 COF4 Interrupt Enable 20 1 read-write COF5 COF5 Interrupt Enable 21 1 read-write COF6 COF6 Interrupt Enable 22 1 read-write COF7 COF7 Interrupt Enable 23 1 read-write LBTSUCCESS LBTSUCCESS Interrupt Enable 24 1 read-write LBTFAILURE LBTFAILURE Interrupt Enable 25 1 read-write LBTPAUSED LBTPAUSED Interrupt Enable 26 1 read-write LBTRETRY LBTRETRY Interrupt Enable 27 1 read-write RTCCSYNCHED RTCCSYNCHED Interrupt Enable 28 1 read-write TOUT0MATCHLBT TOUT0MATCHLBT Interrupt Enable 29 1 read-write RXCTRL No Description 0x074 read-write 0x00000000 0x1F1F1F1F RXSETEVENT1 First event that sets RX req signal 0 5 read-write DISABLED Request is never set 0 ALWAYS Does not wait for any particular event 1 PRECNTOF Pre counter overflow 2 BASECNTOF Base counter overflow 3 WRAPCNTOF Wrap counter overflow 4 TOUT0UF Timeout counter 0 underflow 5 TOUT1UF Timeout counter 1 underflow 6 TOUT0MATCH Timeout counter 0 match 7 TOUT1MATCH Timeout counter 1 match 8 CC0 Channel 0 Capture/Compare event 9 CC1 Channel 1 Capture/Compare event 10 CC2 Channel 2 Capture/Compare event 11 CC3 Channel 3 Capture/Compare event 12 CC4 Channel 4 Capture/Compare event 13 TXDONE MOD indicated that TX completed 14 RXDONE FRC indicated that RX completed 15 TXORRXDONE MOD/FRC indicated that TX or RX completed 16 FDET0 DEMOD indicated that syncword 0 was detected 17 FDET1 DEMOD indicated that syncword 1 was detected 18 FDET0OR1 DEMOD indicated that syncword 0 or 1 was detected 19 LBTSUCCESS LBT completed successfully 20 LBTRETRY LBT detected occupied channel and will try again 21 LBTFAILURE LBT could not start transmission 22 ANYLBT Any LBT event 23 CCAACK A CCA measurement completed 24 CCA A CCA measurement completed, and channel was clear 25 NOTCCA A CCA measurement completed, and channel was busy 26 TOUT0MATCHLBT Timeout counter 0 match occurred during LBT operation 27 RXSETEVENT2 Second event that sets RX req signal 8 5 read-write RXCLREVENT1 First event that clears RX req signal 16 5 read-write RXCLREVENT2 Second event that clears RX req signal 24 5 read-write TXCTRL No Description 0x078 read-write 0x00000000 0x00001F1F TXSETEVENT1 First event that sets TX req signal 0 5 read-write DISABLED Request is never set 0 ALWAYS Does not wait for any particular event 1 PRECNTOF Pre counter overflow 2 BASECNTOF Base counter overflow 3 WRAPCNTOF Wrap counter overflow 4 TOUT0UF Timeout counter 0 underflow 5 TOUT1UF Timeout counter 1 underflow 6 TOUT0MATCH Timeout counter 0 match 7 TOUT1MATCH Timeout counter 1 match 8 CC0 Channel 0 Capture/Compare event 9 CC1 Channel 1 Capture/Compare event 10 CC2 Channel 2 Capture/Compare event 11 CC3 Channel 3 Capture/Compare event 12 CC4 Channel 4 Capture/Compare event 13 TXDONE MOD indicated that TX completed 14 RXDONE FRC indicated that RX completed 15 TXORRXDONE MOD/FRC indicated that TX or RX completed 16 FDET0 DEMOD indicated that syncword 0 was detected 17 FDET1 DEMOD indicated that syncword 1 was detected 18 FDET0OR1 DEMOD indicated that syncword 0 or 1 was detected 19 LBTSUCCESS LBT completed successfully 20 LBTRETRY LBT detected occupied channel and will try again 21 LBTFAILURE LBT could not start transmission 22 ANYLBT Any LBT event 23 CCAACK A CCA measurement completed 24 CCA A CCA measurement completed, and channel was clear 25 NOTCCA A CCA measurement completed, and channel was busy 26 TOUT0MATCHLBT Timeout counter 0 match occurred during LBT operation 27 TXSETEVENT2 Second event that sets TX req signal 8 5 read-write ETSI No Description 0x07C read-write 0x00000000 0x03FFFFFF ETSIEN ETSI LBT enabling 0 1 read-write GRANULARLESSTHANRXWARM Granular less than RXWARM 1 1 read-write RXWARMTHLD Minimum backoff period for RXWARM 2 8 read-write CCAFIXED Fixed listening time 10 16 read-write LBTSTATE1 No Description 0x080 read-write 0x00000000 0x00000FFF CCACNT Current CCA counter value 0 4 read-write EXP LBT Exponent 4 4 read-write RETRYCNT LBT Retry counter 8 4 read-write RANDOMFW0 No Description 0x084 read-write 0x00000000 0x07FFFFFF RANDOM0 Linear random backoff period from FW 0 9 read-write RANDOM1 Linear random backoff period from FW 9 9 read-write RANDOM2 Linear random backoff period from FW 18 9 read-write RANDOMFW1 No Description 0x088 read-write 0x00000000 0x07FFFFFF RANDOM3 Linear random backoff period from FW 0 9 read-write RANDOM4 Linear random backoff period from FW 9 9 read-write RANDOM5 Linear random backoff period from FW 18 9 read-write RANDOMFW2 No Description 0x08C read-write 0x00000000 0x0003FFFF RANDOM6 Linear random backoff period from FW 0 9 read-write RANDOM7 Linear random backoff period from FW 9 9 read-write SEQIF No Description 0x090 read-write 0x00000000 0x3FFFFFF7 PRECNTOF PRECNT Overflow Interrupt Flag 0 1 read-write BASECNTOF BASECNT Overflow Interrupt Flag 1 1 read-write WRAPCNTOF WRAPCNT Overflow Interrupt Flag 2 1 read-write TOUT0 TOUT0 underflow interrupt flag 4 1 read-write TOUT1 TOUT1 underflow interrupt flag 5 1 read-write TOUT0MATCH TOUT0 compare match interrupt flag 6 1 read-write TOUT1MATCH TOUT1 compare match interrupt flag 7 1 read-write CC0 CC Channel 0 Interrupt Flag 8 1 read-write CC1 CC Channel 1 Interrupt Flag 9 1 read-write CC2 CC Channel 2 Interrupt Flag 10 1 read-write CC3 CC Channel 3 Interrupt Flag 11 1 read-write CC4 CC Channel 4 Interrupt Flag 12 1 read-write CC5 CC Channel 5 Interrupt Flag 13 1 read-write CC6 CC Channel 6 Interrupt Flag 14 1 read-write CC7 CC Channel 7 Interrupt Flag 15 1 read-write COF0 CC Channel 0 Overflow Interrupt Flag 16 1 read-write COF1 CC Channel 1 Overflow Interrupt Flag 17 1 read-write COF2 CC Channel 2 Overflow Interrupt Flag 18 1 read-write COF3 CC Channel 3 Overflow Interrupt Flag 19 1 read-write COF4 CC Channel 4 Overflow Interrupt Flag 20 1 read-write COF5 CC Channel 5 Overflow Interrupt Flag 21 1 read-write COF6 CC Channel 6 Overflow Interrupt Flag 22 1 read-write COF7 CC Channel 7 Overflow Interrupt Flag 23 1 read-write LBTSUCCESS Listen Before Talk Success 24 1 read-write LBTFAILURE Listen Before Talk Failure 25 1 read-write LBTPAUSED Listen Before Talk Paused 26 1 read-write LBTRETRY Listen Before Talk Retry 27 1 read-write RTCCSYNCHED PROTIMER synchronized with the RTCC 28 1 read-write TOUT0MATCHLBT TOUT0 compare match interrupt flag 29 1 read-write SEQIEN No Description 0x094 read-write 0x00000000 0x3FFFFFF7 PRECNTOF PRECNTOF Interrupt Enable 0 1 read-write BASECNTOF BASECNTOF Interrupt Enable 1 1 read-write WRAPCNTOF WRAPCNTOF Interrupt Enable 2 1 read-write TOUT0 TOUT0 Interrupt Enable 4 1 read-write TOUT1 TOUT1 Interrupt Enable 5 1 read-write TOUT0MATCH TOUT0MATCH Interrupt Enable 6 1 read-write TOUT1MATCH TOUT1MATCH Interrupt Enable 7 1 read-write CC0 CC0 Interrupt Enable 8 1 read-write CC1 CC1 Interrupt Enable 9 1 read-write CC2 CC2 Interrupt Enable 10 1 read-write CC3 CC3 Interrupt Enable 11 1 read-write CC4 CC4 Interrupt Enable 12 1 read-write CC5 CC5 Interrupt Enable 13 1 read-write CC6 CC6 Interrupt Enable 14 1 read-write CC7 CC7 Interrupt Enable 15 1 read-write COF0 COF0 Interrupt Enable 16 1 read-write COF1 COF1 Interrupt Enable 17 1 read-write COF2 COF2 Interrupt Enable 18 1 read-write COF3 COF3 Interrupt Enable 19 1 read-write COF4 COF4 Interrupt Enable 20 1 read-write COF5 COF5 Interrupt Enable 21 1 read-write COF6 COF6 Interrupt Enable 22 1 read-write COF7 COF7 Interrupt Enable 23 1 read-write LBTSUCCESS LBTSUCCESS Interrupt Enable 24 1 read-write LBTFAILURE LBTFAILURE Interrupt Enable 25 1 read-write LBTPAUSED LBTPAUSED Interrupt Enable 26 1 read-write LBTRETRY LBTRETRY Interrupt Enable 27 1 read-write RTCCSYNCHED RTCCSYNCHED Interrupt Enable 28 1 read-write TOUT0MATCHLBT TOUT0MATCHLBT Interrupt Enable 29 1 read-write CC0_CTRL No Description 0x100 read-write 0x00000000 0x07E07F7F ENABLE Channel Enable 0 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 PREMATCHEN Enable PRECNT matching 2 1 read-write BASEMATCHEN Enable BASECNT matching 3 1 read-write WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 PRORTC1 PRORTC capture/compare 1 10 ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 CC0_PRE No Description 0x104 read-write 0x00000000 0x0000FFFF PRE CC Channel PRE Value 0 16 read-write CC0_BASE No Description 0x108 read-write 0x00000000 0x0000FFFF BASE CC Channel BASE Value 0 16 read-write CC0_WRAP No Description 0x10C read-write 0x00000000 0xFFFFFFFF WRAP CC Channel WRAP Value 0 32 read-write CC1_CTRL No Description 0x110 read-write 0x00000000 0x07E07F7F ENABLE Channel Enable 0 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 PREMATCHEN Enable PRECNT matching 2 1 read-write BASEMATCHEN Enable BASECNT matching 3 1 read-write WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 PRORTC1 PRORTC capture/compare 1 10 ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 CC1_PRE No Description 0x114 read-write 0x00000000 0x0000FFFF PRE CC Channel PRE Value 0 16 read-write CC1_BASE No Description 0x118 read-write 0x00000000 0x0000FFFF BASE CC Channel BASE Value 0 16 read-write CC1_WRAP No Description 0x11C read-write 0x00000000 0xFFFFFFFF WRAP CC Channel WRAP Value 0 32 read-write CC2_CTRL No Description 0x120 read-write 0x00000000 0x07E07F7F ENABLE Channel Enable 0 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 PREMATCHEN Enable PRECNT matching 2 1 read-write BASEMATCHEN Enable BASECNT matching 3 1 read-write WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 PRORTC1 PRORTC capture/compare 1 10 ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 CC2_PRE No Description 0x124 read-write 0x00000000 0x0000FFFF PRE CC Channel PRE Value 0 16 read-write CC2_BASE No Description 0x128 read-write 0x00000000 0x0000FFFF BASE CC Channel BASE Value 0 16 read-write CC2_WRAP No Description 0x12C read-write 0x00000000 0xFFFFFFFF WRAP CC Channel WRAP Value 0 32 read-write CC3_CTRL No Description 0x130 read-write 0x00000000 0x07E07F7F ENABLE Channel Enable 0 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 PREMATCHEN Enable PRECNT matching 2 1 read-write BASEMATCHEN Enable BASECNT matching 3 1 read-write WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 PRORTC1 PRORTC capture/compare 1 10 ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 CC3_PRE No Description 0x134 read-write 0x00000000 0x0000FFFF PRE CC Channel PRE Value 0 16 read-write CC3_BASE No Description 0x138 read-write 0x00000000 0x0000FFFF BASE CC Channel BASE Value 0 16 read-write CC3_WRAP No Description 0x13C read-write 0x00000000 0xFFFFFFFF WRAP CC Channel WRAP Value 0 32 read-write CC4_CTRL No Description 0x140 read-write 0x00000000 0x07E07F7F ENABLE Channel Enable 0 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 PREMATCHEN Enable PRECNT matching 2 1 read-write BASEMATCHEN Enable BASECNT matching 3 1 read-write WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 PRORTC1 PRORTC capture/compare 1 10 ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 CC4_PRE No Description 0x144 read-write 0x00000000 0x0000FFFF PRE CC Channel PRE Value 0 16 read-write CC4_BASE No Description 0x148 read-write 0x00000000 0x0000FFFF BASE CC Channel BASE Value 0 16 read-write CC4_WRAP No Description 0x14C read-write 0x00000000 0xFFFFFFFF WRAP CC Channel WRAP Value 0 32 read-write CC5_CTRL No Description 0x150 read-write 0x00000000 0x07E07F7F ENABLE Channel Enable 0 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 PREMATCHEN Enable PRECNT matching 2 1 read-write BASEMATCHEN Enable BASECNT matching 3 1 read-write WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 PRORTC1 PRORTC capture/compare 1 10 ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 CC5_PRE No Description 0x154 read-write 0x00000000 0x0000FFFF PRE CC Channel PRE Value 0 16 read-write CC5_BASE No Description 0x158 read-write 0x00000000 0x0000FFFF BASE CC Channel BASE Value 0 16 read-write CC5_WRAP No Description 0x15C read-write 0x00000000 0xFFFFFFFF WRAP CC Channel WRAP Value 0 32 read-write CC6_CTRL No Description 0x160 read-write 0x00000000 0x07E07F7F ENABLE Channel Enable 0 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 PREMATCHEN Enable PRECNT matching 2 1 read-write BASEMATCHEN Enable BASECNT matching 3 1 read-write WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 PRORTC1 PRORTC capture/compare 1 10 ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 CC6_PRE No Description 0x164 read-write 0x00000000 0x0000FFFF PRE CC Channel PRE Value 0 16 read-write CC6_BASE No Description 0x168 read-write 0x00000000 0x0000FFFF BASE CC Channel BASE Value 0 16 read-write CC6_WRAP No Description 0x16C read-write 0x00000000 0xFFFFFFFF WRAP CC Channel WRAP Value 0 32 read-write CC7_CTRL No Description 0x170 read-write 0x00000000 0x07E07F7F ENABLE Channel Enable 0 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 PREMATCHEN Enable PRECNT matching 2 1 read-write BASEMATCHEN Enable BASECNT matching 3 1 read-write WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 PRORTC1 PRORTC capture/compare 1 10 ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 CC7_PRE No Description 0x174 read-write 0x00000000 0x0000FFFF PRE CC Channel PRE Value 0 16 read-write CC7_BASE No Description 0x178 read-write 0x00000000 0x0000FFFF BASE CC Channel BASE Value 0 16 read-write CC7_WRAP No Description 0x17C read-write 0x00000000 0xFFFFFFFF WRAP CC Channel WRAP Value 0 32 read-write RAC_S 1 RAC_S Registers 0xA8020000 0x00000000 0x00001000 registers RAC_RSM 37 RAC_SEQ 38 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Enable peripheral clock to this module 0 1 read-write RXENSRCEN No Description 0x008 read-write 0x00000000 0x00003FFF SWRXEN SW RX Enable 0 8 read-write CHANNELBUSYEN Channel Busy Enable 8 1 read-write TIMDETEN Timing Detected Enable 9 1 read-write PREDETEN Preamble Detected Enable 10 1 read-write FRAMEDETEN Frame Detected Enable 11 1 read-write DEMODRXREQEN DEMOD RX Request Enable 12 1 read-write PRSRXEN PRS RX Enable 13 1 read-write STATUS No Description 0x00C read-only 0x00000000 0xFFF8FFFF RXMASK Receive Enable Mask 0 16 read-only FORCESTATEACTIVE FSM state force active 19 1 read-only X0 No special state transition is currently in progress 0 X1 A forced state transition is currently in progress 1 TXAFTERFRAMEPEND TX After Frame Pending 20 1 read-only X0 A transmit after frame operation is currently not pending. 0 X1 A transmit after frame operation is currently pending. 1 TXAFTERFRAMEACTIVE TX After Frame Active 21 1 read-only X0 The currently ongoing TX was not initiated by a TXAFTERFRAME command. 0 X1 The currently ongoing TX was initiated by a TXAFTERFRAME command. 1 SEQSLEEPING SEQ in sleeping 22 1 read-only SEQSLEEPDEEP SEQ in deep sleep 23 1 read-only STATE Radio State 24 4 read-only OFF Radio is off 0 RXWARM Radio is enabling receiver 1 RXSEARCH Radio is listening for incoming frames 2 RXFRAME Radio is receiving a frame 3 RXPD Radio is powering down receiver and going to OFF state 4 RX2RX Radio remains in receive mode after frame reception is completed 5 RXOVERFLOW Received data was lost due to full receive buffer 6 RX2TX Radio is disabling receiver and enabling transmitter 7 TXWARM Radio is enabling transmitter 8 TX Radio is transmitting data 9 TXPD Radio is powering down transmitter and going to OFF state 10 TX2RX Radio is disabling transmitter and enabling reception 11 TX2TX Radio is preparing for a transmission after the previous transmission was ended 12 SHUTDOWN Radio is powering down receiver and going to OFF state 13 POR Radio power-on-reset state 14 SEQACTIVE SEQ active 28 1 read-only TXENS TXEN Status 30 1 read-only X0 TXEN is not set. 0 X1 TXEN is set. 1 RXENS RXEN Status 31 1 read-only X0 RXEN is not set. 0 X1 RXEN is set. 1 CMD No Description 0x010 write-only 0x00000000 0xC000FDFF TXEN Transmitter Enable 0 1 write-only FORCETX Force TX Command 1 1 write-only TXONCCA Transmit On CCA 2 1 write-only CLEARTXEN Clear TX Enable 3 1 write-only TXAFTERFRAME TX After Frame 4 1 write-only TXDIS TX Disable 5 1 write-only CLEARRXOVERFLOW Clear RX Overflow 6 1 write-only RXCAL Start an RX Calibration 7 1 write-only RXDIS RX Disable 8 1 write-only FRCWR FRC write cmd 10 1 write-only FRCRD FRC read cmd 11 1 write-only PAENSET PAEN Set 12 1 write-only PAENCLEAR PAEN Clear 13 1 write-only LNAENSET LNAEN Set 14 1 write-only LNAENCLEAR LNAEN Clear 15 1 write-only CTRL No Description 0x014 read-write 0x00000000 0x1F0107EF FORCEDISABLE Force Radio Disable 0 1 read-write PRSTXEN PRS TX Enable 1 1 read-write TXAFTERRX TX After RX 2 1 read-write X0 TX will not be started automatically. 0 X1 A transition to TX is automatically started when a received frame is accepted by the FRC. 1 PRSMODE PRS RXEN Mode 3 1 read-write DIRECT The PRS signal is used directly 0 PULSE The PRS signal is used as an RX enable pulse 1 PRSCLR PRS RXEN Clear 5 1 read-write RXSEARCH The PRS RXEN signal is cleared when the RSM state enters RXSEARCH 0 PRSCH The Selected PRS channel in PRSCLRSEL is used as a disable pulse 1 TXPOSTPONE TX Postpone 6 1 read-write X0 In the TX state transmit data is output. 0 X1 In the TX state an unmodulated carrier is output until this bit is cleared. 1 ACTIVEPOL ACTIVE signal polarity 7 1 read-write X0 Active low 0 X1 Active high 1 PAENPOL PAEN signal polarity 8 1 read-write X0 Active low 0 X1 Active high 1 LNAENPOL LNAEN signal polarity 9 1 read-write X0 Active low 0 X1 Active high 1 PRSRXDIS PRS RX Disable 10 1 read-write X0 PRS will not disable RX 0 X1 The channel selected by PRSRXDISSEL will generate a disable RX pulse 1 PRSFORCETX PRS Force RX 16 1 read-write X0 PRS will not force TX 0 X1 The channel selected by PRSFORCETXSEL will generate a force TX pulse 1 SEQRESET SEQ reset 24 1 write-only EXITSHUTDOWNDIS Exit SHUTDOWN state Disable 25 1 read-write CPUWAITDIS SEQ CPU Wait Disable 26 1 read-write SEQCLKDIS SEQ Clk Disable 27 1 read-write RXOFDIS Switch to RXOVERFLOW Disable 28 1 read-write FORCESTATE No Description 0x018 read-write 0x00000000 0x0000000F FORCESTATE Force RAC state transition 0 4 read-write IF No Description 0x01C read-write 0x00000000 0x00FF000F STATECHANGE Radio State Change 0 1 read-write STIMCMPEV STIMER Compare Event 1 1 read-write SEQLOCKUP SEQ locked up 2 1 read-write SEQRESETREQ SEQ reset request 3 1 read-write SEQ Sequencer Interrupt Flags 16 8 read-write IEN No Description 0x020 read-write 0x00000000 0x00FF000F STATECHANGE Radio State Change Interrupt Enable 0 1 read-write STIMCMPEV STIMER Compare Event Interrupt Enable 1 1 read-write SEQLOCKUP SEQ locked up Interrupt Enable 2 1 read-write SEQRESETREQ SEQ reset request Interrupt Enable 3 1 read-write SEQ Sequencer Flags Interrupt Enable 16 8 read-write TESTCTRL No Description 0x024 read-write 0x00000000 0x00000003 MODEN Modulator enable 0 1 read-write DEMODEN Demodulator enable 1 1 read-write SEQIF No Description 0x028 read-write 0x00000000 0x3FFF000F STATECHANGESEQ Radio State Change 0 1 read-write STIMCMPEVSEQ STIMER Compare Event 1 1 read-write DEMODRXREQCLRSEQ Demod RX request clear 2 1 read-write PRSEVENTSEQ SEQ PRS Event 3 1 read-write STATEOFF entering STATE_OFF 16 1 read-write STATERXWARM entering STATE_RXWARM 17 1 read-write STATERXSEARCH entering STATE_RXSEARCH 18 1 read-write STATERXFRAME entering STATE_RXFRAME 19 1 read-write STATERXPD entering STATE_RXPD 20 1 read-write STATERX2RX entering STATE_RX2RX 21 1 read-write STATERXOVERFLOW entering STATE_RXOVERFLOW 22 1 read-write STATERX2TX entering STATE_RX2TX 23 1 read-write STATETXWARM entering STATE_TXWARM 24 1 read-write STATETX entering STATE_TX 25 1 read-write STATETXPD entering STATE_TXPD 26 1 read-write STATETX2RX entering STATE_TX2RX 27 1 read-write STATETX2TX entering STATE_TX2TX 28 1 read-write STATESHUTDOWN entering STATE_SHUTDOWN 29 1 read-write SEQIEN No Description 0x02C read-write 0x00000000 0x3FFF000F STATECHANGESEQ Radio State Change Interrupt Enable 0 1 read-write STIMCMPEVSEQ STIMER Compare Event Interrupt Enable 1 1 read-write DEMODRXREQCLRSEQ Demod RX req clr Interrupt Enable 2 1 read-write PRSEVENTSEQ PRS SEQ EVENT Interrupt Enable 3 1 read-write STATEOFF STATE_OFF Interrupt Enable 16 1 read-write STATERXWARM STATE_RXWARM Interrupt Enable 17 1 read-write STATERXSEARCH STATE_RXSEARC Interrupt Enable 18 1 read-write STATERXFRAME STATE_RXFRAME Interrupt Enable 19 1 read-write STATERXPD STATE_RXPD Interrupt Enable 20 1 read-write STATERX2RX STATE_RX2RX Interrupt Enable 21 1 read-write STATERXOVERFLOW STATE_RXOVERFLOW Interrupt Enable 22 1 read-write STATERX2TX STATE_RX2TX Interrupt Enable 23 1 read-write STATETXWARM STATE_TXWARM Interrupt Enable 24 1 read-write STATETX STATE_TX Interrupt Enable 25 1 read-write STATETXPD STATE_TXPD Interrupt Enable 26 1 read-write STATETX2RX STATE_TX2RX Interrupt Enable 27 1 read-write STATETX2TX STATE_TX2TX Interrupt Enable 28 1 read-write STATESHUTDOWN STATE_SHUTDOWN Interrupt Enable 29 1 read-write STIMER No Description 0x030 read-only 0x00000000 0x0000FFFF STIMER STIMER Register 0 16 read-only STIMERCOMP No Description 0x034 read-write 0x00000000 0x0000FFFF STIMERCOMP STIMER Compare Register 0 16 read-write SEQCTRL No Description 0x038 read-write 0x00000000 0x1F00007F COMPACT STIMER Compare Action 0 1 read-write WRAP STIMER wraps when reaching STIMERCOMP 0 CONTINUE STIMER continues when reaching STIMERCOMP 1 COMPINVALMODE STIMER Comp Invalid Mode 1 2 read-write NEVER STIMERCOMP is always valid 0 STATECHANGE STIMERCOMP is invalidated when the RSM changes state 1 COMPEVENT STIMERCOMP is invalidated when an STIMER compare event occurs 2 STATECOMP STIMERCOMP is invalidated both when the RSM changes state and when a compare event occurs 3 RELATIVE STIMER Compare value relative 3 1 read-write Absolute The compare value set for stimer is an absolute value. 0 Relative The compare value set for stimer is a relative value. It takes the amount of time you set to make compare event happens. 1 STIMERALWAYSRUN STIMER always Run 4 1 read-write STIMERDEBUGRUN STIMER Debug Run 5 1 read-write X0 STIMER is not running when the Sequencer is halted. 0 X1 STIMER is running when the Sequencer is halted. 1 STATEDEBUGRUN FSM state Debug Run 6 1 read-write X0 FSM keeps unchanged when the Sequencer is halted 0 X1 FSM keeps going when the Sequencer is halted 1 SWIRQ SW spare IRQ 24 5 read-write PRESC No Description 0x03C read-write 0x00000007 0x0000007F STIMER STIMER Prescaler 0 7 read-write SR0 No Description 0x040 read-write 0x00000000 0xFFFFFFFF SR0 Sequencer Storage Register 0 0 32 read-write SR1 No Description 0x044 read-write 0x00000000 0xFFFFFFFF SR1 Sequencer Storage Register 1 0 32 read-write SR2 No Description 0x048 read-write 0x00000000 0xFFFFFFFF SR2 Sequencer Storage Register 2 0 32 read-write SR3 No Description 0x04C read-write 0x00000000 0xFFFFFFFF SR3 Sequencer Storage Register 3 0 32 read-write STCTRL No Description 0x050 read-write 0x00000000 0x01FFFFFF STCAL Systick timer freq cal 0 24 read-write STSKEW Systick timer skew 24 1 read-write FRCTXWORD No Description 0x054 read-write 0x00000000 0x000000FF WDATA FRC write data 0 8 read-write FRCRXWORD No Description 0x058 read-only 0x00000000 0x000000FF RDATA FRC read data 0 8 read-only EM1PCSR No Description 0x05C read-write 0x00000000 0x00070033 RADIOEM1PMODE 0 1 read-write HWCTRL Hardware Controls EM1P Request Signal 0 SWCTRL Software Controls EM1P Request Signal 1 RADIOEM1PDISSWREQ 1 1 read-write MCUEM1PMODE 4 1 read-write HWCTRL Hardware Controls EM1P Request Signal. 0 SWCTRL Software Controls EM1P Request Signal 1 MCUEM1PDISSWREQ 5 1 read-write RADIOEM1PREQ 16 1 read-only RADIOEM1PACK 17 1 read-only RADIOEM1PHWREQ 18 1 read-only SYNTHENCTRL No Description 0x094 read-write 0x00000000 0x00100282 VCOSTARTUP SYVCOFASTSTARTUP 1 1 read-write fast_start_up_0 0 fast_start_up_1 1 VCBUFEN SYLPFVCBUFEN 7 1 read-write Disabled 0 Enabled 1 LPFBWSEL LPF bandwidth register selection 20 1 read-write LPFBWRX Select LPFBWRX 0 LPFBWTX Select LPFBWTX 1 SYNTHREGCTRL No Description 0x098 read-write 0x04000000 0x07001C00 MMDLDOVREFTRIM SYTRIMMMDREGVREF 10 3 read-write vref0p6000 0 vref0p6125 1 vref0p6250 2 vref0p6375 3 vref0p6500 4 vref0p6625 5 vref0p6750 6 vref0p6875 7 CHPLDOVREFTRIM SYTRIMCHPREGVREF 24 3 read-write vref0p6000 0 vref0p6125 1 vref0p6250 2 vref0p6375 3 vref0p6500 4 vref0p6625 5 vref0p6750 6 vref0p6875 7 VCOCTRL No Description 0x09C read-write 0x0000004C 0x000000FF VCOAMPLITUDE SYVCOAMPLOPEN 0 4 read-write VCODETAMPLITUDE SYVCOAMPLPKD 4 4 read-write SYNTHCTRL No Description 0x0A4 read-write 0x00000000 0x00000400 MMDPOWERBALANCEDISABLE SYMMDPOWERBALANCEENB 10 1 read-write EnablePowerbleed 0 DisablePowerBleed 1 STATUS2 No Description 0x0AC read-only 0x00000000 0x0000FFFF PREVSTATE1 Previous Radio State 0 4 read-only OFF Radio is off 0 RXWARM Radio is enabling receiver 1 RXSEARCH Radio is listening for incoming frames 2 RXFRAME Radio is receiving a frame 3 RXPD Radio is powering down receiver and going to OFF state 4 RX2RX Radio remains in receive mode after frame reception is completed 5 RXOVERFLOW Received data was lost due to full receive buffer 6 RX2TX Radio is disabling receiver and enabling transmitter 7 TXWARM Radio is enabling transmitter 8 TX Radio is transmitting data 9 TXPD Radio is powering down transmitter and going to OFF state 10 TX2RX Radio is disabling transmitter and enabling reception 11 TX2TX Radio is preparing for a transmission after the previous transmission was ended 12 SHUTDOWN Radio is powering down receiver and going to OFF state 13 POR Radio power-on-reset state 14 PREVSTATE2 Previous Radio State 2 4 4 read-only OFF Radio is off 0 RXWARM Radio is enabling receiver 1 RXSEARCH Radio is listening for incoming frames 2 RXFRAME Radio is receiving a frame 3 RXPD Radio is powering down receiver and going to OFF state 4 RX2RX Radio remains in receive mode after frame reception is completed 5 RXOVERFLOW Received data was lost due to full receive buffer 6 RX2TX Radio is disabling receiver and enabling transmitter 7 TXWARM Radio is enabling transmitter 8 TX Radio is transmitting data 9 TXPD Radio is powering down transmitter and going to OFF state 10 TX2RX Radio is disabling transmitter and enabling reception 11 TX2TX Radio is preparing for a transmission after the previous transmission was ended 12 SHUTDOWN Radio is powering down receiver and going to OFF state 13 POR Radio power-on-reset state 14 PREVSTATE3 Previous Radio State 3 8 4 read-only OFF Radio is off 0 RXWARM Radio is enabling receiver 1 RXSEARCH Radio is listening for incoming frames 2 RXFRAME Radio is receiving a frame 3 RXPD Radio is powering down receiver and going to OFF state 4 RX2RX Radio remains in receive mode after frame reception is completed 5 RXOVERFLOW Received data was lost due to full receive buffer 6 RX2TX Radio is disabling receiver and enabling transmitter 7 TXWARM Radio is enabling transmitter 8 TX Radio is transmitting data 9 TXPD Radio is powering down transmitter and going to OFF state 10 TX2RX Radio is disabling transmitter and enabling reception 11 TX2TX Radio is preparing for a transmission after the previous transmission was ended 12 SHUTDOWN Radio is powering down receiver and going to OFF state 13 POR Radio power-on-reset state 14 CURRSTATE Current Radio State 12 4 read-only OFF Radio is off 0 RXWARM Radio is enabling receiver 1 RXSEARCH Radio is listening for incoming frames 2 RXFRAME Radio is receiving a frame 3 RXPD Radio is powering down receiver and going to OFF state 4 RX2RX Radio remains in receive mode after frame reception is completed 5 RXOVERFLOW Received data was lost due to full receive buffer 6 RX2TX Radio is disabling receiver and enabling transmitter 7 TXWARM Radio is enabling transmitter 8 TX Radio is transmitting data 9 TXPD Radio is powering down transmitter and going to OFF state 10 TX2RX Radio is disabling transmitter and enabling reception 11 TX2TX Radio is preparing for a transmission after the previous transmission was ended 12 SHUTDOWN Radio is powering down receiver and going to OFF state 13 POR Radio power-on-reset state 14 IFPGACTRL No Description 0x0B0 read-write 0x00000000 0x0FF80000 DCCALON Enable/Disable DCCAL in DEMOD 19 1 read-write DISABLE DC ESTI DISABLED 0 ENABLE DC ESTI ENABLED 1 DCRSTEN DC Compensation Filter Reset Enable 20 1 read-write DISABLE DC Comp out of Reset 0 ENABLE DC Comp in Reset 1 DCESTIEN DCESTIEN Override for RAC 21 1 read-write DISABLE DCESTI Disabled in MODEM 0 ENABLE DCESTI Enabled in MODEM 1 DCCALDEC0 DEC0 Value for DCCAL 22 3 read-write DF3 Decimation Factor 0 = 3. Cutoff 0.050 * f<subscript>HFXO</subscript>. 0 DF4WIDE Decimation Factor 0 = 4. Cutoff 0.069 * f<subscript>HFXO</subscript>. 1 DF4NARROW Decimation Factor 0 = 4. Cutoff 0.037 * f<subscript>HFXO</subscript>. 2 DF8WIDE Decimation Factor 0 = 8. Cutoff 0.012 * f<subscript>HFXO</subscript>. 3 DF8NARROW Decimation Factor 0 = 8. Cutoff 0.005 * f<subscript>HFXO</subscript>. 4 DCCALDCGEAR DC COMP GEAR Value for DCCAL 25 3 read-write PAENCTRL No Description 0x0B4 read-write 0x00000000 0x10010100 PARAMP PA output level ramping 8 1 read-write INVRAMPCLK Invert PA ramping clock 16 1 read-write PARAMPMODE PA ramp mode 28 1 read-write LINEAR PA ramps in normal linear mode, ramp offset doesn't apply 0 OFFSET PA ramps with an pre-determined offset that is different between different PAs 1 APC No Description 0x0B8 read-write 0xFF000000 0xFF000004 ENAPCSW software control bit for apc 2 1 read-write DISABLE 0 ENABLE 1 AMPCONTROLLIMITSW software amp_control top limit 24 8 read-write AUXADCTRIM 0x0BC read-write 0x06D55502 0x1FFFFFFF AUXADCCLKINVERT AUXADCCLKINVERT 0 1 read-write Disable_Invert 0 Enable_Invert 1 AUXADCLDOVREFTRIM AUXADCLDOVREFTRIM 1 2 read-write TRIM1p27 0 TRIM1p3 1 TRIM1p35 2 TRIM1p4 3 AUXADCOUTPUTINVERT AUXADCOUTPUTINVERT 3 1 read-write Disabled 0 Enabled 1 AUXADCRCTUNE AUXADCRCTUNE 4 5 read-write AUXADCTRIMADCINPUTRES AUXADCTRIMADCINPUTRES 9 2 read-write RES200k 0 RES250k 1 RES300k 2 RES350k 3 AUXADCTRIMCURRINPUTBUF AUXADCTRIMCURRINPUTBUF 11 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURROPA1 AUXADCTRIMCURROPA1 13 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURROPA2 AUXADCTRIMCURROPA2 15 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURRREFBUF AUXADCTRIMCURRREFBUF 17 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURRTSENSE AUXADCTRIMCURRTSENSE 19 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURRVCMBUF AUXADCTRIMCURRVCMBUF 21 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMLDOHIGHCURRENT AUXADCTRIMLDOHIGHCURRENT 23 1 read-write LowCurrentMode 0 HighCurrentMode 1 AUXADCTRIMREFP AUXADCTRIMREFP 24 2 read-write REF1p05 0 REF1p16 1 REF1p2 2 REF1p25 3 AUXADCTRIMVREFVCM AUXADCTRIMVREFVCM 26 2 read-write Trim0p6 0 Trim0p65 1 Trim0p7 2 Trim0p75 3 AUXADCTSENSETRIMVBE2 AUXADCTSENSETRIMVBE2 28 1 read-write VBE_16uA 0 VBE_32uA 1 AUXADCEN 0x0C0 read-write 0x00000000 0x000003FF AUXADCENAUXADC AUXADCENAUXADC 0 1 read-write Disabled 0 Enabled 1 AUXADCENINPUTBUFFER AUXADCENINPUTBUFFER 1 1 read-write Disabled 0 Enabled 1 AUXADCENLDO AUXADCENLDO 2 1 read-write Disabled 0 Enabled 1 AUXADCENOUTPUTDRV AUXADCENOUTPUTDRV 3 1 read-write Disabled 0 Enabled 1 AUXADCENPMON AUXADCENPMON 4 1 read-write Disabled 0 Enabled 1 AUXADCENRESONDIAGA AUXADCENRESONDIAGA 5 1 read-write Disabled 0 Enabled 1 AUXADCENTSENSE AUXADCENTSENSE 6 1 read-write Disabled 0 Enabled 1 AUXADCENTSENSECAL AUXADCENTSENSECAL 7 1 read-write Disabled 0 Enabled 1 AUXADCINPUTBUFFERBYPASS AUXADCINPUTBUFFERBYPASS 8 1 read-write Not_Bypassed 0 Bypassed 1 AUXADCENMEASTHERMISTOR AUXADCENMEASTHERMISTOR 9 1 read-write Disabled 0 Enabled 1 AUXADCCTRL0 No Description 0x0C4 read-write 0x00000100 0x00003FFF CYCLES Cycle number to run 0 10 read-write MUXSEL Select accumulator 10 2 read-write CLRCOUNTER Clear counter 12 1 read-write CLRFILTER Clear accumulators 13 1 read-write AUXADCCTRL1 0x0C8 read-write 0x00000000 0xF31F0FFF AUXADCINPUTRESSEL AUXADCINPUTRESSEL 0 4 read-write RES640kOhm 0 RES320kOhm 1 RES160kOhm 2 RES80kOhm 3 RES40kOhm 4 RES20kOhm 5 RES10kOhm 6 RES5kOhm 7 RES2p5kOhm 8 RES1p25kOhm 9 RES0p6kOhm 10 RES_switch 11 AUXADCINPUTSELECT AUXADCINPUTSELECT 4 4 read-write SEL0 0 SEL1 1 SEL2 2 SEL3 3 SEL4 4 SEL5 5 SEL6 6 SEL7 7 SEL8 8 SEL9 9 AUXADCPMONSELECT AUXADCPMONSELECT 8 4 read-write AUXADCTSENSESELCURR AUXADCTSENSESELCURR 16 5 read-write AUXADCRESET AUXADCRESET 24 1 read-write Reset_Enabled 0 Reset_Disabled 1 AUXADCTSENSESELVBE AUXADCTSENSESELVBE 25 1 read-write VBE1 0 VBE2 1 AUXADCTHERMISTORFREQSEL AUXADCTHERMISTORFREQSEL 28 4 read-write DIV1 0 DIV2 1 DIV4 2 DIV8 3 DIV16 4 DIV32 5 DIV64 6 DIV128 7 DIV256 8 DIV512 9 DIV1024 10 AUXADCOUT No Description 0x0CC read-only 0x00000000 0x0FFFFFFF AUXADCOUT AUXADC output 0 28 read-only CLKMULTEN0 0x0D0 read-write 0xAA400005 0xFFDFFFFF CLKMULTBWCAL CLKMULTBWCAL 0 2 read-write bw_1lsb 0 bw_2lsb 1 bw_3lsb 2 bw_4lsb 3 CLKMULTDISICO CLKMULTDISICO 2 1 read-write enable 0 disable 1 CLKMULTENBBDET CLKMULTENBBDET 3 1 read-write disable 0 enable 1 CLKMULTENBBXLDET CLKMULTENBBXLDET 4 1 read-write disable 0 enable 1 CLKMULTENBBXMDET CLKMULTENBBXMDET 5 1 read-write disable 0 enable 1 CLKMULTENCFDET CLKMULTENCFDET 6 1 read-write disable 0 enable 1 CLKMULTENDITHER CLKMULTENDITHER 7 1 read-write disable 0 enable 1 CLKMULTENDRVADC CLKMULTENDRVADC 8 1 read-write disable 0 enable 1 CLKMULTENDRVN CLKMULTENDRVN 9 1 read-write disable 0 enable 1 CLKMULTENDRVP CLKMULTENDRVP 10 1 read-write disable 0 enable 1 CLKMULTENDRVRX2P4G CLKMULTENDRVRX2P4G 11 1 read-write disable 0 enable 1 CLKMULTENFBDIV CLKMULTENFBDIV 14 1 read-write disable 0 enable 1 CLKMULTENREFDIV CLKMULTENREFDIV 15 1 read-write disable 0 enable 1 CLKMULTENREG1 CLKMULTENREG1 16 1 read-write disable 0 enable 1 CLKMULTENREG2 CLKMULTENREG2 17 1 read-write disable 0 enable 1 CLKMULTENREG3 CLKMULTENREG3 18 1 read-write disable 0 enable 1 CLKMULTENROTDET CLKMULTENROTDET 19 1 read-write disable 0 enable 1 CLKMULTENBYPASS40MHZ CLKMULTENBYPASS40MHZ 20 1 read-write disable 0 enable 1 CLKMULTFREQCAL CLKMULTFREQCAL 22 2 read-write pedes_14uA 0 pedes_22uA 1 pedes_30uA 2 pedes_38uA 3 CLKMULTREG2ADJI CLKMULTREG2ADJI 24 2 read-write I_80uA 0 I_100uA 1 I_120uA 2 I_140uA 3 CLKMULTREG1ADJV CLKMULTREG1ADJV 26 2 read-write v1p28 0 v1p32 1 v1p33 2 v1p38 3 CLKMULTREG2ADJV CLKMULTREG2ADJV 28 2 read-write v1p03 0 v1p09 1 v1p10 2 v1p16 3 CLKMULTREG3ADJV CLKMULTREG3ADJV 30 2 read-write v1p03 0 v1p06 1 v1p07 2 v1p09 3 CLKMULTEN1 0x0D4 read-write 0x00000188 0x0001FDEF CLKMULTINNIBBLE CLKMULTINNIBBLE 0 4 read-write CLKMULTLDFNIB CLKMULTLDFNIB 5 1 read-write disable 0 enable 1 CLKMULTLDMNIB CLKMULTLDMNIB 6 1 read-write disable 0 enable 1 CLKMULTRDNIBBLE CLKMULTRDNIBBLE 7 2 read-write quarter_nibble 0 fine_nibble 1 moderate_nibble 2 coarse_nibble 3 CLKMULTLDCNIB CLKMULTLDCNIB 10 1 read-write disable 0 enable 1 CLKMULTDRVAMPSEL CLKMULTDRVAMPSEL 11 6 read-write off 0 slide_x1 1 slide_x2 3 slide_x3 7 slide_x4 15 slide_x5 31 slide_x6 63 CLKMULTCTRL 0x0D8 read-write 0x000000C0 0x00007FFF CLKMULTDIVN CLKMULTDIVN 0 7 read-write CLKMULTDIVR CLKMULTDIVR 7 3 read-write CLKMULTDIVX CLKMULTDIVX 10 3 read-write div_1 0 div_2 1 div_4 2 div_6 3 div_8 4 div10 5 div12 6 div14 7 CLKMULTENRESYNC CLKMULTENRESYNC 13 1 read-write disable_sync 0 enable_sync 1 CLKMULTVALID CLKMULTVALID 14 1 read-write invalid 0 valid 1 CLKMULTSTATUS 0x0DC read-only 0x00000000 0x0000001F CLKMULTOUTNIBBLE CLKMULTOUTNIBBLE 0 4 read-only CLKMULTACKVALID CLKMULTACKVALID 4 1 read-only invalid 0 valid 1 IFADCTRIM0 0x0E4 read-write 0x11512C6C 0x3FFFFFFF IFADCCLKSEL IFADCCLKSEL 0 1 read-write clk_2p4g 0 clk_subg 1 IFADCENHALFMODE IFADCENHALFMODE 1 1 read-write full_speed_mode 0 half_speed_mode 1 IFADCLDOSERIESAMPLVL IFADCLDOSERIESAMPLVL 2 3 read-write v1p225 0 v1p250 1 v1p275 2 v1p300 3 v1p325 4 v1p350 5 v1p375 6 v1p400 7 IFADCLDOSHUNTAMPLVL1 IFADCLDOSHUNTAMPLVL1 5 3 read-write v1p125 0 v1p150 1 v1p175 2 v1p200 3 v1p225 4 v1p250 5 v1p275 6 v1p300 7 IFADCLDOSHUNTAMPLVL2 IFADCLDOSHUNTAMPLVL2 8 1 read-write disable 0 enable 1 IFADCLDOSHUNTCURLVL1 IFADCLDOSHUNTCURLVL1 9 3 read-write i55u 0 i65u 1 i70u 2 i85u 3 i85u2 4 i95u 5 i100u 6 i110u 7 IFADCLDOSHUNTCURLVL2 IFADCLDOSHUNTCURLVL2 12 3 read-write i4u 0 i4p5u 1 i5u 2 i5p5u 3 i5u2 4 i5p5u2 5 i6u 6 i6p5u 7 IFADCOTACURRENT IFADCOTACURRENT 15 3 read-write i3u 0 i3p5u 1 i4u 2 i4p5u 3 i4u2 4 i4p5u2 5 i5u 6 i5p5u 7 IFADCREFBUFAMPLVL IFADCREFBUFAMPLVL 18 3 read-write v0p88 0 v0p91 1 v0p94 2 v0p97 3 v1p00 4 v1p03 5 v1p06 6 v1p09 7 IFADCREFBUFCURLVL IFADCREFBUFCURLVL 21 3 read-write i4u 0 i4p5u 1 i5u 2 i5p5u 3 i5u2 4 i5p5u2 5 i6u 6 i6p5u 7 IFADCSIDETONEAMP IFADCSIDETONEAMP 24 3 read-write diff_5p68mV 0 diff_29p1mV 1 diff_9p73mV 2 diff_76p9mV 3 diff_9p68_mV 4 diff_51_mV 5 diff_17p2_mV 6 disable 7 IFADCSIDETONEFREQ IFADCSIDETONEFREQ 27 3 read-write na0 0 div_128 1 div_64 2 div_32 3 div_16 4 div_8 5 div_4 6 na7 7 IFADCTRIM1 0x0E8 read-write 0x00000123 0x000001FF IFADCVCMLVL IFADCVCMLVL 0 3 read-write vcm_475mV 0 vcm_500mV 1 vcm_525mV 2 vcm_550mV 3 vcm_575mV 4 vcm_600mV 5 vcm_625mV 6 cm_650mV 7 IFADCENNEGRES IFADCENNEGRES 3 1 read-write disable 0 enable 1 IFADCNEGRESCURRENT IFADCNEGRESCURRENT 4 3 read-write i1p0u 0 i1p5u 1 i2p0u 2 i2p5u 3 i2p0u2 4 i2p5u2 5 i3p0u 6 i3p5u 7 IFADCNEGRESVCM IFADCNEGRESVCM 7 2 read-write r210k_x_1uA 0 r210k_x_1uA2 1 r100k_x_2uA 2 r50k_x_3uA 3 IFADCCAL 0x0EC read-write 0x00000C00 0x00FF1F03 IFADCENRCCAL IFADCENRCCAL 0 1 read-write rccal_disable 0 rccal_enable 1 IFADCTUNERCCALMODE IFADCTUNERCCALMODE 1 1 read-write SYmode 0 ADCmode 1 IFADCTUNERC IFADCTUNERC 8 5 read-write IFADCRCCALCOUNTERSTARTVAL IFADCRCCALCOUNTERSTARTVAL 16 8 read-write IFADCSTATUS 0x0F0 read-only 0x00000000 0x00000001 IFADCRCCALOUT IFADCRCCALOUT 0 1 read-only lo 0 hi 1 LNAMIXTRIM0 0x0F8 read-write 0x1108233D 0x1FFFFFFF LNAMIXCURCTRL LNAMIXCURCTRL 0 6 read-write LNAMIXHIGHCUR LNAMIXHIGHCUR 6 2 read-write current_470uA 0 current_530uA 1 unused 2 current_590uA 3 LNAMIXLOWCUR LNAMIXLOWCUR 8 4 read-write LNAMIXRFPKDBWSEL LNAMIXRFPKDBWSEL 12 2 read-write LNAMIXRFPKDCALCM LNAMIXRFPKDCALCM 14 6 read-write LNAMIXRFPKDCALDM LNAMIXRFPKDCALDM 20 5 read-write LNAMIXTRIMVREG LNAMIXTRIMVREG 25 4 read-write LNAMIXTRIM1 0x0FC read-write 0x00045408 0x0007FFFF LNAMIXIBIASADJ LNAMIXIBIASADJ 0 6 read-write LNAMIXLNACAPSEL LNAMIXLNACAPSEL 6 3 read-write LNAMIXMXRBIAS LNAMIXMXRBIAS 9 2 read-write bias_1V 0 unused 1 bias_900m 2 bias_800m 3 LNAMIXNCASADJ LNAMIXNCASADJ 11 2 read-write ncas_1V 0 unused 1 ncas_950m 2 ncas_900m 3 LNAMIXPCASADJ LNAMIXPCASADJ 13 2 read-write pcas_250m 0 unused 1 pcas_300m 2 pcas_350m 3 LNAMIXVOUTADJ LNAMIXVOUTADJ 15 4 read-write LNAMIXCAL 0x104 read-write 0x00000070 0x00000077 LNAMIXCALEN LNAMIXCALEN 0 1 read-write cal_disable 0 cal_enable 1 LNAMIXCALVMODE LNAMIXCALVMODE 1 1 read-write current_mode 0 voltage_mode 1 LNAMIXENIRCAL LNAMIXENIRCAL 2 1 read-write disable 0 enable 1 LNAMIXIRCALAMP LNAMIXIRCALAMP 4 3 read-write LNAMIXEN 0x108 read-write 0x00000000 0x00000001 LNAMIXENLDO LNAMIXENLDO 0 1 read-write disable 0 enable 1 PRECTRL 0x10C read-write 0x00000026 0x0000003F PREBYPFORCE PREBYPFORCE 0 1 read-write not_forced 0 forced 1 PREREGTRIM PREREGTRIM 1 3 read-write v1p61 0 v1p68 1 v1p74 2 v1p80 3 v1p86 4 v1p91 5 v1p96 6 v2p00 7 PREVREFTRIM PREVREFTRIM 4 2 read-write v0p675 0 v0p688 1 v0p700 2 v0p713 3 PATRIM0 0x110 read-write 0x00000077 0x00003FFF TX0DBMTRIMBIASN TX0DBMTRIMBIASN 0 4 read-write v_378m 0 v_392m 1 v_405m 2 v_418p5m 3 v_431m 4 v_444m 5 v_457m 6 v_470m 7 v_483m 8 v_496m 9 v_509m 10 v_522m 11 v_535m 12 v_548m 13 v_561m 14 v_574m 15 TX0DBMTRIMBIASP TX0DBMTRIMBIASP 4 4 read-write v_378m 0 v_392m 1 v_405m 2 v_418p5m 3 v_431m 4 v_444m 5 v_457m 6 v_470m 7 v_483m 8 v_496m 9 v_509m 10 v_522m 11 v_535m 12 v_548m 13 v_561m 14 v_574m 15 TX0DBMTRIMDUTYCYN TX0DBMTRIMDUTYCYN 8 3 read-write up_0pct 0 up_1pct 1 up_2pct 2 up_3pct 3 up_4pct 4 up_5pct 5 up_6pct 6 na 7 TX0DBMTRIMDUTYCYP TX0DBMTRIMDUTYCYP 11 3 read-write dn_0pct 0 dn_1pct 1 dn_2pct 2 dn_3pct 3 dn_4pct 4 dn_5pct 5 dn_6pct 6 na 7 PATRIM1 0x114 read-write 0x0003AB97 0x0007FFFF TX0DBMTRIMPREDRVREGIBCORE TX0DBMTRIMPREDRVREGIBCORE 0 2 read-write i_4u 0 i_5u 1 i_6u 2 i_7u 3 TX0DBMTRIMPREDRVREGIBNDIO TX0DBMTRIMPREDRVREGIBNDIO 2 4 read-write vreg_1p127 0 vreg_1p171 1 vreg_1p209 2 vreg_1p244 3 vreg_1p275 4 vreg_1p305 5 vreg_1p335 6 vreg_1p363 7 vreg_1p388 8 vreg_1p414 9 vreg_1p439 10 vreg_1p464 11 vreg_1p486 12 vreg_1p506 13 vreg_1p525 14 vreg_1p545 15 TX0DBMTRIMPREDRVREGPSR TX0DBMTRIMPREDRVREGPSR 6 1 read-write disable 0 enable 1 TX0DBMTRIMPREDRVSLOPE TX0DBMTRIMPREDRVSLOPE 7 2 read-write slope_0 0 slope_1 1 slope_2 2 slope_max 3 TX0DBMTRIMREGFB TX0DBMTRIMREGFB 9 4 read-write vo_vi_0p475 0 vo_vi_0p500 1 vo_vi_0p525 2 vo_vi_0p550 3 vo_vi_0p575 4 vo_vi_0p600 5 vo_vi_0p625 6 vo_vi_0p650 7 vo_vi_0p675 8 vo_vi_0p700 9 vo_vi_0p725 10 vo_vi_0p750 11 vo_vi_0p775 12 vo_vi_0p800 13 vo_vi_0p825 14 vo_vi_0p850 15 TX0DBMTRIMREGVREF TX0DBMTRIMREGVREF 13 3 read-write v_900m 0 v_912p5m 1 v_925m 2 v_937p5m 3 v_950m 4 v_962p5m 5 v_975m 6 v_987p5m 7 TX0DBMTRIMTAPCAP TX0DBMTRIMTAPCAP 16 3 read-write cap_0F 0 cap_0p35pF 1 cap_0p7pF 2 cap_1p05pF 3 cap_1p4pF 4 cap_1p75pF 5 cap_2p1pF 6 cap_2p45pF 7 PATRIM2 0x118 read-write 0x00000088 0x00003FFF TX6DBMTRIMBIASN TX6DBMTRIMBIASN 0 4 read-write vnbias_dn104mV 0 vnbias_dn91mV 1 vnbias_dn78mV 2 vnbias_dn65mV 3 vnbias_dn52mV 4 vnbias_dn39mV 5 vnbias_dn26mV 6 vnbias_dn13mV 7 vnbias_default_613mV 8 vnbias_up13mV 9 vnbias_up26mV 10 vnbias_up39mV 11 vnbias_up52mV 12 vnbias_up65mV 13 vnbias_up78mV 14 vnbias_up91mV 15 TX6DBMTRIMBIASP TX6DBMTRIMBIASP 4 4 read-write vpbias_dn104mV 0 vpbias_dn91mV 1 vpbias_dn78mV 2 vpbias_dn65mV 3 vpbias_dn52mV 4 vpbias_dn39mV 5 vpbias_dn26mV 6 vpbias_dn13mV 7 vpbias_default_949mV 8 vpbias_up13mV 9 vpbias_up26mV 10 vpbias_up39mV 11 vpbias_up52mV 12 vpbias_up65mV 13 vpbias_up78mV 14 vpbias_up91mV 15 TX6DBMTRIMDUTYCYN TX6DBMTRIMDUTYCYN 8 3 read-write up_0pct 0 up_1pct 1 up_2pct 2 up_3pct 3 up_4pct 4 up_5pct 5 up_6pct 6 na 7 TX6DBMTRIMDUTYCYP TX6DBMTRIMDUTYCYP 11 3 read-write dn_0pct 0 dn_1pct 1 dn_2pct 2 dn_3pct 3 dn_4pct 4 dn_5pct 5 dn_6pct 6 na 7 PATRIM3 No Description 0x11C read-write 0x002E2B2A 0x007E7FFF TX6DBMTRIMIBIASMASTER TX6DBMTRIMIBIASMASTER 0 2 read-write ibias_45u 0 ibias_47p5u 1 ibias_50u 2 ibias_52p5u 3 TX6DBMTRIMPREDRVREGFB TX6DBMTRIMPREDRVREGFB 2 2 read-write Acl_1p63 0 Acl_1p71 1 Acl_1p80 2 Acl_1p92 3 TX6DBMTRIMPREDRVREGFBKATT TX6DBMTRIMPREDRVREGFBKATT 4 1 read-write reduce_BW 0 increase_BW 1 TX6DBMTRIMPREDRVREGPSR TX6DBMTRIMPREDRVREGPSR 5 1 read-write low_psr 0 high_psr 1 TX6DBMTRIMPREDRVREGSLICE TX6DBMTRIMPREDRVREGSLICE 6 2 read-write iload_3mA 0 iload_6mA 1 iload_9mA 2 iload_12mA 3 TX6DBMTRIMPREDRVREGVREF TX6DBMTRIMPREDRVREGVREF 8 3 read-write vref_0p675 0 vref_0p700 1 vref_0p725 2 vref_0p750 3 vref_0p775 4 vref_0p800 5 vref_0p825 6 vref_0p850 7 TX6DBMTRIMREGBLEEDAUTO TX6DBMTRIMREGBLEEDAUTO 11 1 read-write not_automatic 0 automatic 1 TX6DBMTRIMREGFB TX6DBMTRIMREGFB 12 2 read-write Acl_2p0x 0 Acl_2p1x 1 Acl_2p3125x 2 Acl_2p5x 3 TX6DBMTRIMREGPSR TX6DBMTRIMREGPSR 14 1 read-write low_PSR 0 high_PSR 1 TX6DBMTRIMREGVREF TX6DBMTRIMREGVREF 17 4 read-write vref_0p6000 0 vref_0p6125 1 vref_0p6250 2 vref_0p6375 3 vref_0p6500 4 vref_0p6625 5 vref_0p6750 6 vref_0p6875 7 vref_0p7000 8 vref_0p7125 9 vref_0p7250 10 vref_0p7375 11 vref_0p7500 12 vref_0p7625 13 vref_0p7750 14 vref_0p7875 15 TX6DBMTRIMRXMODEVREF TX6DBMTRIMRXMODEVREF 21 2 read-write vddreg_1p05 0 vddreg_1p14 1 vddreg_1p20 2 vddreg_1p23 3 PACTRL 0x120 read-write 0x00000010 0x1FFF033F TX0DBMPOWER TX0DBMPOWER 0 4 read-write on_stripe_0 0 on_stripe_12 12 TX0DBMSELSLICE TX0DBMSELSLICE 4 2 read-write on_0_slice 0 on_1_slices 1 on_2_slices 2 NA 3 TX0DBMSLICERESET TX0DBMSLICERESET 8 1 read-write active 0 reset 1 TX0DBMLATCHBYPASS TX0DBMLATCHBYPASS 9 1 read-write disable 0 enable 1 TX6DBMPOWER TX6DBMPOWER 16 5 read-write TX6DBMSELSLICE TX6DBMSELSLICE 21 3 read-write n_slice_on_0 0 n_slice_on_1 1 n_slice_on_2 2 n_slice_on_3 3 n_slice_on_4 4 tbd_5 5 tbd_6 6 tbd_7 7 TX6DBMSLICERESET TX6DBMSLICERESET 24 1 read-write disable_reset 0 enable_reset 1 TX6DBMLATCHBYPASS TX6DBMLATCHBYPASS 25 1 read-write not_bypass 0 bypass_latch 1 TX6DBMPREDRVREGBYPASS TX6DBMREGBYPASSPDRVLDo 26 1 read-write not_bypass 0 bypass 1 TX6DBMPULLDOWNREG TX6DBMPULLDOWNREG 27 1 read-write not_pull_down 0 pull_down 1 TX6DBMREGBYPASS TX6DBMREGBYPASS 28 1 read-write not_bypass 0 bypass 1 PGATRIM 0x128 read-write 0x00000547 0x000007FF PGACTUNE PGACTUNE 0 4 read-write cfb_0p7 0 cfb_nominal 7 cfb_1p32 15 PGADISANTILOCK PGADISANTILOCK 4 1 read-write antilock_enable 0 antilock_disable 1 PGAVCMOUTTRIM PGAVCMOUTTRIM 5 3 read-write vcm_out_0p4 0 vcm_out_0p45 1 vcm_out_0p5 2 vcm_out_0p55 3 vcm_out_0p6 4 vcm_out_0p65 5 vcm_out_0p7 6 vcm_out_0p75 7 PGAVLDOTRIM PGAVLDOTRIM 8 3 read-write vdda_1p15 0 vdda_1p2 1 vdda_1p25 2 vdda_1p3 3 vdda_1p35 4 vdda_1p4 5 vdda_1p5 6 vdda_1p55 7 PGACAL 0x12C read-write 0x20202020 0x3F3F3F3F PGAOFFNCALI PGAOFFNCALI 0 6 read-write offset_m_300mv 0 offset_p_300mv 63 PGAOFFNCALQ PGAOFFNCALQ 8 6 read-write offset_m_300mv 0 offset_p_300mv 63 PGAOFFPCALI PGAOFFPCALI 16 6 read-write offset_m_300mv 0 offset_p_300mv 63 PGAOFFPCALQ PGAOFFPCALQ 24 6 read-write offset_m_300mv 0 offset_p_300mv 63 PGACTRL 0x130 read-write 0x04000000 0x07FFFEEF PGABWMODE PGABWMODE 0 2 read-write bw_5MHz 0 bw_2p5MHz 1 bw_1p67MHz 2 bw_1p25MHz 3 PGAENBIAS PGAENBIAS 2 1 read-write bias_disable 0 bias_enable 1 PGAENGHZ PGAENGHZ 3 1 read-write ghz_disable 0 ghz_enable 1 PGAENLATCHI PGAENLATCHI 5 1 read-write pkd_latch_i_disable 0 pkd_latch_i_enable 1 PGAENLATCHQ PGAENLATCHQ 6 1 read-write pkd_latch_q_disable 0 pkd_latch_q_enable 1 PGAENLDOLOAD PGAENLDOLOAD 7 1 read-write disable_ldo_load 0 enable_ldo_load 1 PGAENPGAI PGAENPGAI 9 1 read-write pgai_disable 0 pgai_enable 1 PGAENPGAQ PGAENPGAQ 10 1 read-write pgaq_disable 0 pgaq_enable 1 PGAENPKD PGAENPKD 11 1 read-write pkd_disable 0 pkd_enable 1 PGAENRCMOUT PGAENRCMOUT 12 1 read-write rcm_out_disable 0 rcm_out_enable 1 PGAPOWERMODE PGAPOWERMODE 14 2 read-write pm_typ 0 pm_0p9 1 pm_1p2 2 pm_0p8 3 PGATHRPKDLOSEL PGATHRPKDLOSEL 16 4 read-write vref50mv 0 vref75mv 1 vref100mv 2 vref125mv 3 vref150mv 4 vref175mv 5 vref200mv 6 vref225mv 7 vref250mv 8 vref275mv 9 vref300mv 10 PGATHRPKDHISEL PGATHRPKDHISEL 20 4 read-write vref50mv 0 vref75mv 1 vref100mv 2 vref125mv 3 verf150mv 4 vref175mv 5 vref200mv 6 vref225mv 7 vref250mv 8 vref275mv 9 vref300mv 10 LNAMIXRFPKDTHRESHSEL LNAMIXRFPKDTHRESHSEL 24 3 read-write RFBIASCAL 0x134 read-write 0x30203020 0x3F3F3F3F RFBIASCALBIAS RFBIASCALBIAS 0 6 read-write RFBIASCALTC RFBIASCALTC 8 6 read-write RFBIASCALVREF RFBIASCALVREF 16 6 read-write RFBIASCALVREFSTARTUP RFBIASCALVREFSTARTUP 24 6 read-write RFBIASCTRL 0x138 read-write 0x00040000 0x000F001F RFBIASDISABLEBOOTSTRAP RFBIASDISABLEBOOTSTRAP 0 1 read-write enable_startup 0 disable_startup 1 RFBIASLDOHIGHCURRENT RFBIASLDOHIGHCURRENT 1 1 read-write low_current 0 high_current 1 RFBIASNONFLASHMODE RFBIASNONFLASHMODE 2 1 read-write flash_process 0 non_flash_process 1 RFBIASSTARTUPCORE RFBIASSTARTUPCORE 3 1 read-write default 0 force_start 1 RFBIASSTARTUPSUPPLY RFBIASSTARTUPSUPPLY 4 1 read-write default 0 forc_start 1 RFBIASLDOVREFTRIM RFBIASLDOVREFTRIM 16 4 read-write vref_v0p800 0 vref_v0p813 1 vref_v0p825 2 vref_v0p837 3 vref_v0p850 4 vref_v0p863 5 vref_v0p875 6 vref_v0p887 7 vref_v0p900 8 vref_v0p913 9 vref_v0p925 10 vref_v0p938 11 vref_v0p950 12 vref_v0p963 13 vref_v0p975 14 vref_v0p988 15 RADIOEN 0x13C read-write 0x00000000 0x00000007 PREEN PREEN 0 1 read-write powered_off 0 powered_on 1 PRESTB100UDIS PRESTB100UDIS 1 1 read-write i100ua_enabled 0 i100ua_disabled 1 RFBIASEN RFBIASEN 2 1 read-write disable_rfis_vtr 0 enable_rfis_vtr 1 RFPATHEN No Description 0x140 read-write 0x00000004 0x0000001E LNAMIXEN LNAMIXEN 1 1 read-write disable 0 enable 1 LNAMIXRFATTDCEN LNAMIXRFATTDCEN 2 1 read-write disable_dc 0 enable_dc 1 LNAMIXRFPKDENRF LNAMIXRFPKDENRF 3 1 read-write disable 0 enable_path 1 LNAMIXTRSW LNAMIXTRSW 4 1 read-write disabled 0 enabled 1 RX 0x144 read-write 0x00000010 0x00000FFF IFADCCAPRESET IFADCCAPRESET 0 1 read-write cap_reset_disable 0 cap_reset_enable 1 IFADCENLDOSERIES IFADCENLDOSERIES 1 1 read-write series_ldo_disable 0 series_ldo_enable 1 IFADCENLDOSHUNT IFADCENLDOSHUNT 2 1 read-write shunt_ldo_disable 0 shunt_ldo_enable 1 LNAMIXENRFPKD LNAMIXENRFPKD 3 1 read-write disable 0 enable 1 LNAMIXLDOLOWCUR LNAMIXLDOLOWCUR 4 1 read-write regular_mode 0 low_current_mode 1 LNAMIXREGLOADEN LNAMIXREGLOADEN 5 1 read-write disable_resistor 0 enable_resistor 1 PGAENLDO PGAENLDO 6 1 read-write disable_ldo 0 enable_ldo 1 SYCHPBIASTRIMBUF SYCHPBIASTRIMBUF 7 1 read-write i_tail_10u 0 i_tail_20u 1 SYCHPQNC3EN SYCHPQNC3EN 8 1 read-write qnc_2 0 qnc_3 1 SYPFDCHPLPEN SYPFDCHPLPEN 9 1 read-write disable 0 enable 1 SYPFDFPWEN SYPFDFPWEN 10 1 read-write disable 0 enable 1 TX6DBMENRXMODEBIAS TX6DBMENRXMODEBIAS 11 1 read-write Disable 0 Enable 1 TX 0x148 read-write 0x00000000 0xE3CB00FF TX0DBMENBLEEDPREDRVREG TX0DBMENBLEEDPREDRVREG 0 1 read-write disable 0 enable 1 TX0DBMENBLEEDREG TX0DBMENBLEEDREG 1 1 read-write disable 0 enable 1 TX0DBMENPREDRV TX0DBMENPREDRV 2 1 read-write disable 0 enable 1 TX0DBMENPREDRVREG TX0DBMENPREDRVREG 3 1 read-write disable 0 enable 1 TX0DBMENPREDRVREGBIAS TX0DBMENPREDRVREGBIAS 4 1 read-write disable 0 enable 1 TX0DBMENBIAS TX0DBMENBIAS 5 1 read-write disable 0 enable 1 TX0DBMENRAMPCLK TX0DBMENRAMPCLK 6 1 read-write disable 0 enable 1 TX0DBMENREG TX0DBMENREG 7 1 read-write disable 0 enable 1 TX6DBMENBLEEDPREDRVREG TX6DBMENBLEEDPREDRVREG 16 1 read-write disable 0 enable 1 TX6DBMENBLEEDREG TX6DBMENBLEEDREG 17 1 read-write disable 0 enable 1 TX6DBMENPREDRVREG TX6DBMENPREDRVREG 19 1 read-write disable 0 enable 1 TX6DBMENRAMPCLK TX6DBMENRAMPCLK 22 1 read-write disable_clock 0 enable_clock 1 TX6DBMENREG TX6DBMENREG 23 1 read-write disable 0 enable 1 TX6DBMENPACORE TX6DBMENPACORE 24 1 read-write disable 0 enable 1 TX6DBMENPAOUT TX6DBMENPAOUT 25 1 read-write disable 0 enable 1 ENXOSQBUFFILT Override 29 1 read-write ENPAPOWER Override 30 1 read-write ENPASELSLICE Override 31 1 read-write SYTRIM0 0x150 read-write 0x00062E29 0x003FEFFF SYCHPBIAS SYCHPBIAS 0 3 read-write bias_0 0 bias_1 1 bias_2 3 bias_3 7 SYCHPCURR SYCHPCURR 3 3 read-write curr_1p5uA 0 curr_2p0uA 1 curr_2p5uA 2 curr_3p0uA 3 curr_3p5uA 4 curr_4p0uA 5 curr_4p5uA 6 curr_5p0uA 7 SYCHPLEVNSRC SYCHPLEVNSRC 6 3 read-write SYCHPLEVPSRC SYCHPLEVPSRC 9 3 read-write vsrcp_n105m 0 vsrcp_n90m 1 vsrcp_n75m 2 vsrcp_n60m 3 vsrcp_n45m 4 vsrcp_n30m 5 vsrcp_n15m 6 vsrcp_n0m 7 SYCHPSRCEN SYCHPSRCEN 13 1 read-write disable 0 enable 1 SYCHPREPLICACURRADJ SYCHPREPLICACURRADJ 14 3 read-write load_8ua 0 load_16ua 1 load_20ua 2 load_28ua 3 load_24ua 4 load_32ua 5 load_36ua 6 load_44ua 7 SYTRIMCHPREGAMPBIAS SYTRIMCHPREGAMPBIAS 17 3 read-write bias_14uA 0 bias_20uA 1 bias_26uA 2 bias_32uA 3 bias_38uA 4 bias_44uA 5 bias_50uA 6 bias_56uA 7 SYTRIMCHPREGAMPBW SYTRIMCHPREGAMPBW 20 2 read-write C_000f 0 C_300f 1 C_600f 2 C_900f 3 SYTRIM1 0x154 read-write 0x00003FC4 0xE003FFFF SYLODIVLDOTRIMCORE SYLODIVLDOTRIMCORE 0 2 read-write RXLO 0 TXLO 3 SYLODIVLDOTRIMNDIO SYLODIVLDOTRIMNDIO 2 4 read-write vreg_1p08 0 vreg_1p11 1 vreg_1p15 2 vreg_1p18 3 vreg_1p21 4 vreg_1p24 5 vreg_1p27 6 vreg_1p29 7 vreg_1p32 8 vreg_1p34 9 SYMMDREPLICA1CURRADJ SYMMDREPLICA1CURRADJ 6 3 read-write load_8ua 0 load_16u 1 load_20ua 2 load_28ua 3 load_24ua 4 load_32ua 5 load_36ua 6 load_44ua 7 SYMMDREPLICA2CURRADJ SYMMDREPLICA2CURRADJ 9 3 read-write load_32u 0 load_64u 1 load_96u 2 load_128u 3 load_160u 4 load_192u 5 load_224u 6 load_256u 7 SYTRIMMMDREGAMPBIAS SYTRIMMMDREGAMPBIAS 12 3 read-write bias_14uA 0 bias_20uA 1 bias_26uA 2 bias_32uA 3 bias_38uA 4 bias_44uA 5 bias_50uA 6 bias_56uA 7 SYTRIMMMDREGAMPBW SYTRIMMMDREGAMPBW 15 2 read-write C_000f 0 C_300f 1 C_600f 2 C_900f 3 SYLODIVRLOADCCLKSEL SYLODIVRLOADCCLKSEL 17 1 read-write adc_clk_div8 0 adc_clk_div16 1 SYLODIVSGTESTDIV SYLODIVSGTESTDIV 29 3 read-write div2 0 div3 1 div4 2 div6 3 div8 4 div12 5 div16 6 div12x 7 SYCAL 0x158 read-write 0x01008100 0x03018700 SYVCOMODEPKD SYVCOMODEPKD 8 1 read-write t_openloop_0 0 t_pkdetect_1 1 SYVCOMORECURRENT SYVCOMORECURRENT 9 1 read-write more_current_0 0 more_current_1 1 SYVCOSLOWNOISEFILTER SYVCOSLOWNOISEFILTER 10 1 read-write slow_noise_filter_0 0 slow_noise_filter_1 1 SYVCOVCAPVCM SYVCOVCAPVCM 15 2 read-write SYHILOADCHPREG SYHILOADCHPREG 24 2 read-write i_350uA 0 i_500uA 1 i_550uA 2 i_700uA 3 SYEN 0x15C read-write 0x00000000 0x00007FFF SYCHPEN SYCHPEN 0 1 read-write disable 0 enable 1 SYCHPLPEN SYCHPLPEN 1 1 read-write disable 0 enable 1 SYENCHPREG SYENCHPREG 2 1 read-write Disable 0 Enable 1 SYENCHPREPLICA SYENCHPREPLICA 3 1 read-write disable 0 enable 1 SYENMMDREG SYENMMDREG 4 1 read-write Disable 0 Enable 1 SYENMMDREPLICA1 SYENMMDREPLICA1 5 1 read-write disable 0 enable 1 SYENMMDREPLICA2 SYENMMDREPLICA2 6 1 read-write Disable 0 Enable 1 SYENVCOBIAS SYENVCOBIAS 7 1 read-write en_vco_bias_0 0 en_vco_bias_1 1 SYENVCOPFET SYENVCOPFET 8 1 read-write en_vco_pfet_0 0 en_vco_pfet_1 1 SYENVCOREG SYENVCOREG 9 1 read-write en_vco_reg_0 0 en_vco_reg_1 1 SYLODIVEN SYLODIVEN 10 1 read-write disable 0 enable 1 SYLODIVLDOBIASEN SYLODIVLDOBIASEN 11 1 read-write disable 0 enable 1 SYLODIVLDOEN SYLODIVLDOEN 12 1 read-write disable 0 enable 1 SYSTARTCHPREG SYSTARTCHPREG 13 1 read-write no_fast_startup 0 fast_startup 1 SYSTARTMMDREG SYSTARTMMDREG 14 1 read-write no_fast_startup 0 fast_startup 1 SYLOEN 0x160 read-write 0x00000000 0x80000663 SYLODIVRLOADCCLK2G4EN SYLODIVRLOADCCLK2G4EN 0 1 read-write disable 0 enable 1 SYLODIVRLO2G4EN SYLODIVRLO2G4EN 1 1 read-write disable 0 enable 1 SYLODIVTLO0DBM2G4AUXEN SYLODIVTLO0DBM2G4AUXEN 5 1 read-write disable 0 enable 1 SYLODIVTLO0DBM2G4EN SYLODIVTLO0DBM2G4EN 6 1 read-write disable 0 enable 1 SYLODIVTLO6DBM2G4AUXEN SYLODIVTLO6DBM2G4AUXEN 9 1 read-write disable 0 enable 1 SYLODIVTLO6DBM2G4EN SYLODIVTLO6DBM2G4EN 10 1 read-write disable 0 enable 1 SYLODIVSGTESTDIVEN SYLODIVSGTESTDIVEN 31 1 read-write disable 0 enable 1 SYMMDCTRL 0x168 read-write 0x00000400 0x00000E07 SYMMDENRSDIG SYMMDENRSDIG 0 1 read-write disable 0 enable 1 SYMMDDIVRSDIG SYMMDDIVRSDIG 1 2 read-write Divideby1 0 Divideby2 1 Divideby4 2 Divideby8 3 SYMMDMODE SYMMDMODE 9 3 read-write rx_w_swctrl 0 rx_wo_swctrl 1 qnc_dsm2 2 qnc_dsm3 3 rxlp_wo_swctrl 4 notuse_5 5 notuse_6 6 notuse_7 7 DIGCLKRETIMECTRL No Description 0x16C read-write 0x00000000 0x00000777 DIGCLKRETIMEENRETIME DIGCLKRETIMEENRETIME 0 1 read-write disable 0 enable 1 DIGCLKRETIMEDISRETIME DIGCLKRETIMEDISRETIME 1 1 read-write enable_retime 0 disable_retime 1 DIGCLKRETIMERESETN DIGCLKRETIMERESETN 2 1 read-write reset 0 operate 1 DIGCLKRETIMELIMITH DIGCLKRETIMELIMITH 4 3 read-write DIGCLKRETIMELIMITL DIGCLKRETIMELIMITL 8 3 read-write DIGCLKRETIMESTATUS No Description 0x170 read-only 0x00000000 0x00000003 DIGCLKRETIMECLKSEL DIGCLKRETIMECLKSEL 0 1 read-only use_raw_clk 0 use_retimed_clk 1 DIGCLKRETIMERESETNLO DIGCLKRETIMERESETNLO 1 1 read-only lo 0 hi 1 XORETIMECTRL No Description 0x174 read-write 0x00000000 0x00000777 XORETIMEENRETIME XORETIMEENRETIME 0 1 read-write disable 0 enable 1 XORETIMEDISRETIME XORETIMEDISRETIME 1 1 read-write enable_retime 0 disable_retime 1 XORETIMERESETN XORETIMERESETN 2 1 read-write operate 0 reset 1 XORETIMELIMITH XORETIMELIMITH 4 3 read-write XORETIMELIMITL XORETIMELIMITL 8 3 read-write XORETIMESTATUS No Description 0x178 read-only 0x00000000 0x00000003 XORETIMECLKSEL XORETIMECLKSEL 0 1 read-only use_raw_clk 0 use_retimed_clk 1 XORETIMERESETNLO XORETIMERESETNLO 1 1 read-only lo 0 hi 1 XOSQBUFFILT 0x17C read-write 0x00000000 0x00000003 XOSQBUFFILT XOSQBUFFILT 0 2 read-write bypass 0 filter_1 1 filter_2 2 filter_3 3 AGCOVERWRITE No Description 0x188 read-write 0x00000000 0x03F0FFFF ENMANLNAMIXRFATT Enable RAC Overwite PN 0 1 read-write ENMANLNAMIXSLICE Enable RAC Overwite LNA 1 1 read-write ENMANPGAGAIN Enable RAC Overwite PGA 2 1 read-write ENMANIFADCSCALE Enable RAC Overwite PN 3 1 read-write MANLNAMIXRFATT RAC Overwite PN 4 6 read-write MANLNAMIXSLICE RAC Overwite LNA 10 6 read-write MANPGAGAIN RAC Overwite PGA 20 4 read-write MANIFADCSCALE RAC Overwite PGA 24 2 read-write SCRATCH0 No Description 0x3E0 read-write 0x00000000 0xFFFFFFFF SCRATCH0 SCRATCH0 0 32 read-write SCRATCH1 No Description 0x3E4 read-write 0x00000000 0xFFFFFFFF SCRATCH1 SCRATCH1 0 32 read-write SCRATCH2 No Description 0x3E8 read-write 0x00000000 0xFFFFFFFF SCRATCH2 SCRATCH2 0 32 read-write SCRATCH3 No Description 0x3EC read-write 0x00000000 0xFFFFFFFF SCRATCH3 SCRATCH3 0 32 read-write SCRATCH4 No Description 0x3F0 read-write 0x00000000 0xFFFFFFFF SCRATCH4 SCRATCH4 0 32 read-write SCRATCH5 No Description 0x3F4 read-write 0x00000000 0xFFFFFFFF SCRATCH5 SCRATCH5 0 32 read-write SCRATCH6 No Description 0x3F8 read-write 0x00000000 0xFFFFFFFF SCRATCH6 SCRATCH6 0 32 read-write SCRATCH7 No Description 0x3FC read-write 0x00000000 0xFFFFFFFF SCRATCH7 SCRATCH7 0 32 read-write THMSW No Description 0x7E8 read-write 0x00000000 0x00000003 EN Enable Switch 0 1 read-write Disabled 0 Enabled 1 HALFSWITCH Halfswitch Mode enable 1 1 read-write Disabled 0 Enabled 1 RDMAILBOX0_S 0 RDMAILBOX0_S Registers 0xA8028000 0x00000000 0x00001000 registers MSGPTR0 No Description 0x000 read-write 0x00000000 0xFFFFFFFF PTR Pointer 0 32 read-write MSGPTR1 No Description 0x004 read-write 0x00000000 0xFFFFFFFF PTR Pointer 0 32 read-write MSGPTR2 No Description 0x008 read-write 0x00000000 0xFFFFFFFF PTR Pointer 0 32 read-write MSGPTR3 No Description 0x00C read-write 0x00000000 0xFFFFFFFF PTR Pointer 0 32 read-write IF No Description 0x040 read-write 0x00000000 0x0000000F MBOXIF0 Mailbox Interupt Flag 0 1 read-write MBOXIF1 Mailbox Interupt Flag 1 1 read-write MBOXIF2 Mailbox Interupt Flag 2 1 read-write MBOXIF3 Mailbox Interupt Flag 3 1 read-write IEN No Description 0x044 read-write 0x00000000 0x0000000F MBOXIEN0 Mailbox Interrupt Enable 0 1 read-write MBOXIEN1 Mailbox Interrupt Enable 1 1 read-write MBOXIEN2 Mailbox Interrupt Enable 2 1 read-write MBOXIEN3 Mailbox Interrupt Enable 3 1 read-write RDMAILBOX1_S 0 RDMAILBOX1_S Registers 0xA802C000 0x00000000 0x00001000 registers MSGPTR0 No Description 0x000 read-write 0x00000000 0xFFFFFFFF PTR Pointer 0 32 read-write MSGPTR1 No Description 0x004 read-write 0x00000000 0xFFFFFFFF PTR Pointer 0 32 read-write MSGPTR2 No Description 0x008 read-write 0x00000000 0xFFFFFFFF PTR Pointer 0 32 read-write MSGPTR3 No Description 0x00C read-write 0x00000000 0xFFFFFFFF PTR Pointer 0 32 read-write IF No Description 0x040 read-write 0x00000000 0x0000000F MBOXIF0 Mailbox Interupt Flag 0 1 read-write MBOXIF1 Mailbox Interupt Flag 1 1 read-write MBOXIF2 Mailbox Interupt Flag 2 1 read-write MBOXIF3 Mailbox Interupt Flag 3 1 read-write IEN No Description 0x044 read-write 0x00000000 0x0000000F MBOXIEN0 Mailbox Interrupt Enable 0 1 read-write MBOXIEN1 Mailbox Interrupt Enable 1 1 read-write MBOXIEN2 Mailbox Interrupt Enable 2 1 read-write MBOXIEN3 Mailbox Interrupt Enable 3 1 read-write BUFC_S 1 BUFC_S Registers 0xAA000000 0x00000000 0x00001000 registers BUFC 32 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Enable peripheral clock to this module 0 1 read-write LPMODE No Description 0x008 read-write 0x00000000 0x00000003 LPENBYSEQ Low power mode enable from M0p sequencer 0 1 read-write LPENBYM33 Low power mode enable from M33 1 1 read-write BUF0_CTRL No Description 0x00C read-write 0x00000000 0x00000007 SIZE Buffer Size 0 3 read-write SIZE64 Sets Buffer size to 64 bytes 0 SIZE128 Sets Buffer size to 128 bytes 1 SIZE256 Sets Buffer size to 256 bytes 2 SIZE512 Sets Buffer size to 512 bytes 3 SIZE1024 Sets Buffer size to 1024 bytes 4 SIZE2048 Sets Buffer size to 2048 bytes 5 SIZE4096 Sets Buffer size to 4096 bytes 6 BUF0_ADDR No Description 0x010 read-write 0x20000000 0xFFFFFFFC ADDR Buffer Address 2 30 read-write BUF0_WRITEOFFSET No Description 0x014 read-write 0x00000000 0x00001FFF WRITEOFFSET Write Offset 0 13 read-write BUF0_READOFFSET No Description 0x018 read-write 0x00000000 0x00001FFF READOFFSET Read Offset 0 13 read-write BUF0_READDATA No Description 0x020 read-only 0x00000000 0x000000FF READDATA Buffer Read Data 0 8 read-only BUF0_WRITEDATA No Description 0x024 write-only 0x00000000 0x000000FF WRITEDATA Buffer Write Data 0 8 write-only BUF0_XWRITE No Description 0x028 write-only 0x00000000 0x000000FF XORWRITEDATA Buffer XOR Write Data 0 8 write-only BUF0_STATUS No Description 0x02C read-only 0x00000000 0x01111FFF BYTES Number of Bytes in the Buffer 0 13 read-only THRESHOLDFLAG Buffer Threshold Flag 20 1 read-only BUF0_THRESHOLDCTRL No Description 0x030 read-write 0x00000000 0x00002FFF THRESHOLD Buffer Threshold Value 0 12 read-write THRESHOLDMODE Buffer Threshold Mode 13 1 read-write LARGER THRESHOLDIF will be set if BYTES is larger than THRESHOLD 0 LESSOREQUAL THRESHOLDIF will be set if BYTES is less than or equal to THRESHOLD 1 BUF0_CMD No Description 0x034 write-only 0x00000000 0x0000000F CLEAR Buffer Clear 0 1 write-only PREFETCH Prefetch 1 1 write-only BUF0_FIFOASYNC No Description 0x038 write-only 0x00000000 0x00000001 RST Reset ASYNC 0 1 write-only BUF0_READDATA32 No Description 0x03C read-only 0x00000000 0xFFFFFFFF READDATA32 Buffer Read Data 0 32 read-only BUF0_WRITEDATA32 No Description 0x040 write-only 0x00000000 0xFFFFFFFF WRITEDATA32 Buffer Write Data 0 32 write-only BUF0_XWRITE32 No Description 0x044 write-only 0x00000000 0xFFFFFFFF XORWRITEDATA32 Buffer XOR Write Data 0 32 write-only BUF1_CTRL No Description 0x04C read-write 0x00000000 0x00000007 SIZE Buffer Size 0 3 read-write SIZE64 Sets Buffer size to 64 bytes 0 SIZE128 Sets Buffer size to 128 bytes 1 SIZE256 Sets Buffer size to 256 bytes 2 SIZE512 Sets Buffer size to 512 bytes 3 SIZE1024 Sets Buffer size to 1024 bytes 4 SIZE2048 Sets Buffer size to 2048 bytes 5 SIZE4096 Sets Buffer size to 4096 bytes 6 BUF1_ADDR No Description 0x050 read-write 0x20000000 0xFFFFFFFC ADDR Buffer Address 2 30 read-write BUF1_WRITEOFFSET No Description 0x054 read-write 0x00000000 0x00001FFF WRITEOFFSET Write Offset 0 13 read-write BUF1_READOFFSET No Description 0x058 read-write 0x00000000 0x00001FFF READOFFSET Read Offset 0 13 read-write BUF1_READDATA No Description 0x060 read-only 0x00000000 0x000000FF READDATA Buffer Read Data 0 8 read-only BUF1_WRITEDATA No Description 0x064 write-only 0x00000000 0x000000FF WRITEDATA Buffer Write Data 0 8 write-only BUF1_XWRITE No Description 0x068 write-only 0x00000000 0x000000FF XORWRITEDATA Buffer XOR Write Data 0 8 write-only BUF1_STATUS No Description 0x06C read-only 0x00000000 0x01111FFF BYTES Number of Bytes in the Buffer 0 13 read-only THRESHOLDFLAG Buffer Threshold Flag 20 1 read-only BUF1_THRESHOLDCTRL No Description 0x070 read-write 0x00000000 0x00002FFF THRESHOLD Buffer Threshold Value 0 12 read-write THRESHOLDMODE Buffer Threshold Mode 13 1 read-write LARGER THRESHOLDIF will be set if BYTES is larger than THRESHOLD 0 LESSOREQUAL THRESHOLDIF will be set if BYTES is less than or equal to THRESHOLD 1 BUF1_CMD No Description 0x074 write-only 0x00000000 0x0000000F CLEAR Buffer Clear 0 1 write-only PREFETCH Prefetch 1 1 write-only BUF1_FIFOASYNC No Description 0x078 write-only 0x00000000 0x00000001 RST Reset ASYNC 0 1 write-only BUF1_READDATA32 No Description 0x07C read-only 0x00000000 0xFFFFFFFF READDATA32 Buffer Read Data 0 32 read-only BUF1_WRITEDATA32 No Description 0x080 write-only 0x00000000 0xFFFFFFFF WRITEDATA32 Buffer Write Data 0 32 write-only BUF1_XWRITE32 No Description 0x084 write-only 0x00000000 0xFFFFFFFF XORWRITEDATA32 Buffer XOR Write Data 0 32 write-only BUF2_CTRL No Description 0x08C read-write 0x00000000 0x00000007 SIZE Buffer Size 0 3 read-write SIZE64 Sets Buffer size to 64 bytes 0 SIZE128 Sets Buffer size to 128 bytes 1 SIZE256 Sets Buffer size to 256 bytes 2 SIZE512 Sets Buffer size to 512 bytes 3 SIZE1024 Sets Buffer size to 1024 bytes 4 SIZE2048 Sets Buffer size to 2048 bytes 5 SIZE4096 Sets Buffer size to 4096 bytes 6 BUF2_ADDR No Description 0x090 read-write 0x20000000 0xFFFFFFFC ADDR Buffer Address 2 30 read-write BUF2_WRITEOFFSET No Description 0x094 read-write 0x00000000 0x00001FFF WRITEOFFSET Write Offset 0 13 read-write BUF2_READOFFSET No Description 0x098 read-write 0x00000000 0x00001FFF READOFFSET Read Offset 0 13 read-write BUF2_READDATA No Description 0x0A0 read-only 0x00000000 0x000000FF READDATA Buffer Read Data 0 8 read-only BUF2_WRITEDATA No Description 0x0A4 write-only 0x00000000 0x000000FF WRITEDATA Buffer Write Data 0 8 write-only BUF2_XWRITE No Description 0x0A8 write-only 0x00000000 0x000000FF XORWRITEDATA Buffer XOR Write Data 0 8 write-only BUF2_STATUS No Description 0x0AC read-only 0x00000000 0x01111FFF BYTES Number of Bytes in the Buffer 0 13 read-only THRESHOLDFLAG Buffer Threshold Flag 20 1 read-only BUF2_THRESHOLDCTRL No Description 0x0B0 read-write 0x00000000 0x00002FFF THRESHOLD Buffer Threshold Value 0 12 read-write THRESHOLDMODE Buffer Threshold Mode 13 1 read-write LARGER THRESHOLDIF will be set if BYTES is larger than THRESHOLD 0 LESSOREQUAL THRESHOLDIF will be set if BYTES is less than or equal to THRESHOLD 1 BUF2_CMD No Description 0x0B4 write-only 0x00000000 0x0000000F CLEAR Buffer Clear 0 1 write-only PREFETCH Prefetch 1 1 write-only BUF2_FIFOASYNC No Description 0x0B8 write-only 0x00000000 0x00000001 RST Reset ASYNC 0 1 write-only BUF2_READDATA32 No Description 0x0BC read-only 0x00000000 0xFFFFFFFF READDATA32 Buffer Read Data 0 32 read-only BUF2_WRITEDATA32 No Description 0x0C0 write-only 0x00000000 0xFFFFFFFF WRITEDATA32 Buffer Write Data 0 32 write-only BUF2_XWRITE32 No Description 0x0C4 write-only 0x00000000 0xFFFFFFFF XORWRITEDATA32 Buffer XOR Write Data 0 32 write-only BUF3_CTRL No Description 0x0CC read-write 0x00000000 0x00000007 SIZE Buffer Size 0 3 read-write SIZE64 Sets Buffer size to 64 bytes 0 SIZE128 Sets Buffer size to 128 bytes 1 SIZE256 Sets Buffer size to 256 bytes 2 SIZE512 Sets Buffer size to 512 bytes 3 SIZE1024 Sets Buffer size to 1024 bytes 4 SIZE2048 Sets Buffer size to 2048 bytes 5 SIZE4096 Sets Buffer size to 4096 bytes 6 BUF3_ADDR No Description 0x0D0 read-write 0x20000000 0xFFFFFFFC ADDR Buffer Address 2 30 read-write BUF3_WRITEOFFSET No Description 0x0D4 read-write 0x00000000 0x00001FFF WRITEOFFSET Write Offset 0 13 read-write BUF3_READOFFSET No Description 0x0D8 read-write 0x00000000 0x00001FFF READOFFSET Read Offset 0 13 read-write BUF3_READDATA No Description 0x0E0 read-only 0x00000000 0x000000FF READDATA Buffer Read Data 0 8 read-only BUF3_WRITEDATA No Description 0x0E4 write-only 0x00000000 0x000000FF WRITEDATA Buffer Write Data 0 8 write-only BUF3_XWRITE No Description 0x0E8 write-only 0x00000000 0x000000FF XORWRITEDATA Buffer XOR Write Data 0 8 write-only BUF3_STATUS No Description 0x0EC read-only 0x00000000 0x01111FFF BYTES Number of Bytes in the Buffer 0 13 read-only THRESHOLDFLAG Buffer Threshold Flag 20 1 read-only BUF3_THRESHOLDCTRL No Description 0x0F0 read-write 0x00000000 0x00002FFF THRESHOLD Buffer Threshold Value 0 12 read-write THRESHOLDMODE Buffer Threshold Mode 13 1 read-write LARGER THRESHOLDIF will be set if BYTES is larger than THRESHOLD 0 LESSOREQUAL THRESHOLDIF will be set if BYTES is less than or equal to THRESHOLD 1 BUF3_CMD No Description 0x0F4 write-only 0x00000000 0x0000000F CLEAR Buffer Clear 0 1 write-only PREFETCH Prefetch 1 1 write-only BUF3_FIFOASYNC No Description 0x0F8 write-only 0x00000000 0x00000001 RST Reset ASYNC 0 1 write-only BUF3_READDATA32 No Description 0x0FC read-only 0x00000000 0xFFFFFFFF READDATA32 Buffer Read Data 0 32 read-only BUF3_WRITEDATA32 No Description 0x100 write-only 0x00000000 0xFFFFFFFF WRITEDATA32 Buffer Write Data 0 32 write-only BUF3_XWRITE32 No Description 0x104 write-only 0x00000000 0xFFFFFFFF XORWRITEDATA32 Buffer XOR Write Data 0 32 write-only IF No Description 0x114 read-write 0x00000000 0x9F1F1F1F BUF0OF Buffer 0 Overflow 0 1 read-write BUF0UF Buffer 0 Underflow 1 1 read-write BUF0THR Buffer 0 Threshold Event 2 1 read-write BUF0CORR Buffer 0 Corrupt 3 1 read-write BUF0NWA Buffer 0 Not Word-Aligned 4 1 read-write BUF1OF Buffer 1 Overflow 8 1 read-write BUF1UF Buffer 1 Underflow 9 1 read-write BUF1THR Buffer 1 Threshold Event 10 1 read-write BUF1CORR Buffer 1 Corrupt 11 1 read-write BUF1NWA Buffer 1 Not Word-Aligned 12 1 read-write BUF2OF Buffer 2 Overflow 16 1 read-write BUF2UF Buffer 2 Underflow 17 1 read-write BUF2THR Buffer 2 Threshold Event 18 1 read-write BUF2CORR Buffer 2 Corrupt 19 1 read-write BUF2NWA Buffer 2 Not Word-Aligned 20 1 read-write BUF3OF Buffer 3 Overflow 24 1 read-write BUF3UF Buffer 3 Underflow 25 1 read-write BUF3THR Buffer 3 Threshold Event 26 1 read-write BUF3CORR Buffer 3 Corrupt 27 1 read-write BUF3NWA Buffer 3 Not Word-Aligned 28 1 read-write BUSERROR Bus Error 31 1 read-write IEN No Description 0x118 read-write 0x00000000 0x9F1F1F1F BUF0OF BUF0OF Interrupt Enable 0 1 read-write BUF0UF BUF0UF Interrupt Enable 1 1 read-write BUF0THR BUF0THR Interrupt Enable 2 1 read-write BUF0CORR BUF0CORR Interrupt Enable 3 1 read-write BUF0NWA BUF0NWA Interrupt Enable 4 1 read-write BUF1OF BUF1OF Interrupt Enable 8 1 read-write BUF1UF BUF1UF Interrupt Enable 9 1 read-write BUF1THR BUF1THR Interrupt Enable 10 1 read-write BUF1CORR BUF1CORR Interrupt Enable 11 1 read-write BUF1NWA BUF1NWA Interrupt Enable 12 1 read-write BUF2OF BUF2OF Interrupt Enable 16 1 read-write BUF2UF BUF2UF Interrupt Enable 17 1 read-write BUF2THR BUF2THR Interrupt Enable 18 1 read-write BUF2CORR BUF2CORR Interrupt Enable 19 1 read-write BUF2NWA BUF2NWA Interrupt Enable 20 1 read-write BUF3OF BUF3OF Interrupt Enable 24 1 read-write BUF3UF BUF3UF Interrupt Enable 25 1 read-write BUF3THR BUF3THR Interrupt Enable 26 1 read-write BUF3CORR BUF3CORR Interrupt Enable 27 1 read-write BUF3NWA BUF3NWA Interrupt Enable 28 1 read-write BUSERROR BUSERROR Interrupt Enable 31 1 read-write SEQIF No Description 0x11C read-write 0x00000000 0x9F1F1F1F BUF0OF Buffer 0 Overflow 0 1 read-write BUF0UF Buffer 0 Underflow 1 1 read-write BUF0THR Buffer 0 Threshold Event 2 1 read-write BUF0CORR Buffer 0 Corrupt 3 1 read-write BUF0NWA Buffer 0 Not Word-Aligned 4 1 read-write BUF1OF Buffer 1 Overflow 8 1 read-write BUF1UF Buffer 1 Underflow 9 1 read-write BUF1THR Buffer 1 Threshold Event 10 1 read-write BUF1CORR Buffer 1 Corrupt 11 1 read-write BUF1NWA Buffer 1 Not Word-Aligned 12 1 read-write BUF2OF Buffer 2 Overflow 16 1 read-write BUF2UF Buffer 2 Underflow 17 1 read-write BUF2THR Buffer 2 Threshold Event 18 1 read-write BUF2CORR Buffer 2 Corrupt 19 1 read-write BUF2NWA Buffer 2 Not Word-Aligned 20 1 read-write BUF3OF Buffer 3 Overflow 24 1 read-write BUF3UF Buffer 3 Underflow 25 1 read-write BUF3THR Buffer 3 Threshold Event 26 1 read-write BUF3CORR Buffer 3 Corrupt 27 1 read-write BUF3NWA Buffer 3 Not Word-Aligned 28 1 read-write BUSERROR Bus Error 31 1 read-write SEQIEN No Description 0x120 read-write 0x00000000 0x9F1F1F1F BUF0OF BUF0OF Interrupt Enable 0 1 read-write BUF0UF BUF0UF Interrupt Enable 1 1 read-write BUF0THR BUF0THR Interrupt Enable 2 1 read-write BUF0CORR BUF0CORR Interrupt Enable 3 1 read-write BUF0NWA BUF0NWA Interrupt Enable 4 1 read-write BUF1OF BUF1OF Interrupt Enable 8 1 read-write BUF1UF BUF1UF Interrupt Enable 9 1 read-write BUF1THR BUF1THR Interrupt Enable 10 1 read-write BUF1CORR BUF1CORR Interrupt Enable 11 1 read-write BUF1NWA BUF1NWA Interrupt Enable 12 1 read-write BUF2OF BUF2OF Interrupt Enable 16 1 read-write BUF2UF BUF2UF Interrupt Enable 17 1 read-write BUF2THR BUF2THR Interrupt Enable 18 1 read-write BUF2CORR BUF2CORR Interrupt Enable 19 1 read-write BUF2NWA BUF2NWA Interrupt Enable 20 1 read-write BUF3OF BUF3OF Interrupt Enable 24 1 read-write BUF3UF BUF3UF Interrupt Enable 25 1 read-write BUF3THR BUF3THR Interrupt Enable 26 1 read-write BUF3CORR BUF3CORR Interrupt Enable 27 1 read-write BUF3NWA BUF3NWA Interrupt Enable 28 1 read-write BUSERROR BUSERROR Interrupt Enable 31 1 read-write PRORTC_NS 1 PRORTC_NS Registers 0xB8000000 0x00000000 0x00001000 registers PRORTC 41 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP VERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN RTCC Enable 0 1 read-write CFG No Description 0x008 read-write 0x00000000 0x000000FF DEBUGRUN Debug Mode Run Enable 0 1 read-write X0 RTCC is frozen in debug mode 0 X1 RTCC is running in debug mode 1 PRECNTCCV0TOP Pre-counter CCV0 top value enable. 1 1 read-write CNTCCV1TOP CCV1 top value enable 2 1 read-write CNTTICK Counter prescaler mode. 3 1 read-write PRESC CNT register ticks according to configuration in CNTPRESC. 0 CCV0MATCH CNT register ticks when PRECNT matches RTCC_CC0_OC[14:0] 1 CNTPRESC Counter prescaler value. 4 4 read-write DIV1 CLK_CNT = (RTCC LF CLK)/1 0 DIV2 CLK_CNT = (RTCC LF CLK)/2 1 DIV4 CLK_CNT = (RTCC LF CLK)/4 2 DIV8 CLK_CNT = (RTCC LF CLK)/8 3 DIV16 CLK_CNT = (RTCC LF CLK)/16 4 DIV32 CLK_CNT = (RTCC LF CLK)/32 5 DIV64 CLK_CNT = (RTCC LF CLK)/64 6 DIV128 CLK_CNT = (RTCC LF CLK)/128 7 DIV256 CLK_CNT = (RTCC LF CLK)/256 8 DIV512 CLK_CNT = (RTCC LF CLK)/512 9 DIV1024 CLK_CNT = (RTCC LF CLK)/1024 10 DIV2048 CLK_CNT = (RTCC LF CLK)/2048 11 DIV4096 CLK_CNT = (RTCC LF CLK)/4096 12 DIV8192 CLK_CNT = (RTCC LF CLK)/8192 13 DIV16384 CLK_CNT = (RTCC LF CLK)/16384 14 DIV32768 CLK_CNT = (RTCC LF CLK)/32768 15 CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start RTCC main counter 0 1 write-only STOP Stop RTCC main counter 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x00000003 RUNNING RTCC running status 0 1 read-only RTCCLOCKSTATUS Lock Status 1 1 read-only UNLOCKED RTCC registers are unlocked 0 LOCKED RTCC registers are locked 1 IF No Description 0x014 read-write 0x00000000 0x000000FF OF Overflow Interrupt Flag 0 1 read-write CNTTICK Main counter tick 1 1 read-write CC0 CC Channel n Interrupt Flag 4 1 read-write CC1 CC Channel n Interrupt Flag 6 1 read-write IEN No Description 0x018 read-write 0x00000000 0x000000FF OF OF Interrupt Enable 0 1 read-write CNTTICK CNTTICK Interrupt Enable 1 1 read-write CC0 CC Channel n Interrupt Enable 4 1 read-write CC1 CC Channel n Interrupt Enable 6 1 read-write PRECNT No Description 0x01C read-write 0x00000000 0x00007FFF PRECNT Pre-Counter Value 0 15 read-write CNT No Description 0x020 read-write 0x00000000 0xFFFFFFFF CNT Counter Value 0 32 read-write COMBCNT No Description 0x024 read-only 0x00000000 0xFFFFFFFF PRECNT Pre-Counter Value 0 15 read-only CNTLSB Counter Value 15 17 read-only SYNCBUSY No Description 0x028 read-only 0x00000000 0x0000000F START Sync busy for START 0 1 read-only STOP Sync busy for STOP 1 1 read-only PRECNT Sync busy for PRECNT 2 1 read-only CNT Sync busy for CNT 3 1 read-only LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write to unlock RTCC lockable registers 44776 CC0_CTRL No Description 0x030 read-write 0x00000000 0x000000FF MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 CC0_OCVALUE No Description 0x034 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC0_ICVALUE No Description 0x038 read-only 0x00000000 0xFFFFFFFF IC Input Capture Value 0 32 read-only CC1_CTRL No Description 0x03C read-write 0x00000000 0x000000FF MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 CC1_OCVALUE No Description 0x040 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC1_ICVALUE No Description 0x044 read-only 0x00000000 0xFFFFFFFF IC Input Capture Value 0 32 read-only FRC_NS 1 FRC_NS Registers 0xB8004000 0x00000000 0x00001000 registers FRC_PRI 33 FRC 34 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Enable peripheral clock to this module 0 1 read-write STATUS No Description 0x008 read-only 0x00000000 0x01FFFFFF SNIFFDCOUNT Sniffer data count 0 5 read-only ACTIVETXFCD Active Transmit Frame Descriptor 5 1 read-only FCD0 FCD0 is active 0 FCD1 FCD1 is active 1 ACTIVERXFCD Active Receive Frame Descriptor 6 1 read-only FCD2 FCD2 is active 0 FCD3 FCD3 is active 1 SNIFFDFRAME Sniffer data frame active status 7 1 read-only RXRAWBLOCKED Receiver raw trigger block is active 8 1 read-only FRAMEOK Frame valid 9 1 read-only RXABORTINPROGRESS Receive aborted in progress status flag 10 1 read-only TXWORD Transmit Word Flag 11 1 read-only RXWORD Receive Word Flag 12 1 read-only CONVPAUSED Convolutional coder pause event active 13 1 read-only TXSUBFRAMEPAUSED Transmit subframe pause event active 14 1 read-only INTERLEAVEREADPAUSED Interleaver read pause event active 15 1 read-only INTERLEAVEWRITEPAUSED Interleaver write pause event active 16 1 read-only FRAMEDETPAUSED Frame detected pause event active 17 1 read-only FRAMELENGTHERROR Frame Length Error for RX and TX 18 1 read-only DEMODERROR Demod Error in RX 19 1 read-only FSMSTATE FSM state status for srw_frc_interface 20 5 read-only IDLE 0 RX_INIT 1 RX_DATA 2 RX_CRC 3 RX_FCD_UPDATE 4 RX_DISCARD 5 RX_TRAIL 6 RX_DONE 7 RX_PAUSE_INIT 8 RX_PAUSED 9 UNDEFINED1 10 UNDEFINED2 11 RX_CRC_ZEROCHECK 12 RX_SUP 13 RX_WAITEOF 14 UNDEFINED3 15 TX_INIT 16 TX_DATA 17 TX_CRC 18 TX_FCD_UPDATE 19 TX_TRAIL 20 TX_FLUSH 21 TX_DONE 22 TX_DONE_WAIT 23 TX_RAW 24 TX_PAUSEFLUSH 25 DFLCTRL No Description 0x00C read-write 0x00000000 0x01FFFF7F DFLMODE Dynamic Frame Length Mode 0 3 read-write DISABLE Dynamic Frame Length support is disabled, and the frame length is controlled by writing directly to the FRAMELENGTH field 0 SINGLEBYTE Dynamic Frame Length is enabled and located in a single byte over air. This byte is loaded into the least significant byte of the extracted length field 1 SINGLEBYTEMSB Dynamic Frame Length is enabled and located in a single byte over air. This byte is loaded into the most significant byte of the extracted length field 2 DUALBYTELSBFIRST Dynamic Frame Length is enabled and located in two bytes over air, of which the least significant byte is transferred first 3 DUALBYTEMSBFIRST Dynamic Frame Length is enabled and located in two bytes over air, of which the most significant byte is transferred first 4 INFINITE Dynamic Frame Length support is disabled, and infinite frame lengths are transmitted and received. RXABORT may be used to abort active receive operations, while the TXDIS command (available in the RAC) may be used to abort active transmit operations. 5 BLOCKERROR In transmit mode, the frame length must be written directly to the FRAMELENGTH field. In receive mode, data will be received until a block decoding error is found. 6 DFLBITORDER Dynamic Frame Length Bit order 3 1 read-write NORMAL Bit ordering is defined by the BITORDER field 0 REVERSE Bit ordering is reversed, compared to what is defined by the BITORDER field 1 DFLSHIFT Dynamic Frame Length bitshift 4 3 read-write DFLOFFSET Length Field Offset Value 8 4 read-write DFLBITS Length field number of bits 12 4 read-write MINLENGTH Minimum decoded length 16 4 read-write DFLINCLUDECRC Length field includes CRC values or not 20 1 read-write X0 The CRC values are not included in the frame length 0 X1 The CRC values are included in the frame length 1 DFLBOIOFFSET Length Field Offset Value 21 4 read-write MAXLENGTH No Description 0x010 read-write 0x00004FFF 0x0000FFFF MAXLENGTH Max Frame Length Value 0 12 read-write INILENGTH Initial Frame Length Value 12 4 read-write ADDRFILTCTRL No Description 0x014 read-write 0x00000000 0x0000FF07 EN Address Filter Enable 0 1 read-write BRDCST00EN Broadcast Address 0x00 Enable 1 1 read-write BRDCSTFFEN Broadcast Address 0xFF Enable 2 1 read-write ADDRESS Address 8 8 read-write DATABUFFER No Description 0x018 read-write 0x00000000 0x000000FF DATABUFFER Frame Controller data buffer 0 8 read-write WCNT No Description 0x01C read-only 0x00000000 0x00000FFF WCNT Word Counter Value 0 12 read-only WCNTCMP0 No Description 0x020 read-write 0x00000000 0x00000FFF FRAMELENGTH Word Counter Frame Length Value 0 12 read-write WCNTCMP1 No Description 0x024 read-write 0x00000000 0x00000FFF LENGTHFIELDLOC Length field location 0 12 read-write WCNTCMP2 No Description 0x028 read-write 0x00000000 0x00000FFF ADDRFIELDLOC Address field location 0 12 read-write CMD No Description 0x02C write-only 0x00000000 0x00001FFF RXABORT RX Abort 0 1 write-only FRAMEDETRESUME FRAMEDET resume 1 1 write-only INTERLEAVEWRITERESUME Interleaver write resume 2 1 write-only INTERLEAVEREADRESUME Interleaver read resume 3 1 write-only CONVRESUME Convolutional coder resume 4 1 write-only CONVTERMINATE Convolutional coder termination 5 1 write-only TXSUBFRAMERESUME TX subframe resume 6 1 write-only INTERLEAVEINIT Interleaver initialization 7 1 write-only INTERLEAVECNTCLEAR Interleaver counter clear 8 1 write-only CONVINIT Convolutional coder initialize 9 1 write-only BLOCKINIT Block coder initialize 10 1 write-only STATEINIT FRC State initialize 11 1 write-only RXRAWUNBLOCK Clear RXRAWBLOCKED status flag 12 1 write-only WHITECTRL No Description 0x030 read-write 0x00000000 0x00001F7F FEEDBACKSEL LFSR Feedback selector 0 5 read-write BIT0 Select bit 0 as feedback 0 BIT1 Select bit 1 as feedback 1 BIT2 Select bit 2 as feedback 2 BIT3 Select bit 3 as feedback 3 BIT4 Select bit 4 as feedback 4 BIT5 Select bit 5 as feedback 5 BIT6 Select bit 6 as feedback 6 BIT7 Select bit 7 as feedback 7 BIT8 Select bit 8 as feedback 8 BIT9 Select bit 9 as feedback 9 BIT10 Select bit 10 as feedback 10 BIT11 Select bit 11 as feedback 11 BIT12 Select bit 12 as feedback 12 BIT13 Select bit 13 as feedback 13 BIT14 Select bit 14 as feedback 14 BIT15 Select bit 15 as feedback 15 INPUT Select data input as feedback 16 ZERO Select zero as feedback 17 ONE Select one as feedback 18 TXLASTWORD In transmit mode, the feedback is one during the last transmit word and zero otherwise. In receive mode, the feedback is always zero. 19 XORFEEDBACK LFSR Feedback XOR setting 5 2 read-write DIRECT The signal defined by FEEDBACKSEL is used directly as Feedback. 0 XOR The signal defined by FEEDBACKSEL is XOR'ed with bit 15, and the result is used as Feedback 1 ZERO Feedback is set to 0 2 SHROUTPUTSEL Shift Register Output Selector 8 4 read-write BLOCKERRORCORRECT Block Errors Correction enable 12 1 read-write X0 Block decoding errors are not corrected, only the BLOCKERR interrupt is set on detection. 0 X1 Block decoding errors are attempted corrected by memory lookup tables. The BLOCKERR interrupt is also set on error detection. 1 WHITEPOLY No Description 0x034 read-write 0x00000000 0x0000FFFF POLY Whitener Polynomial 0 16 read-write WHITEINIT No Description 0x038 read-write 0x00000000 0x0000FFFF WHITEINIT Whitener Initial Value 0 16 read-write FECCTRL No Description 0x03C read-write 0x00000000 0x003FFFF7 BLOCKWHITEMODE Block Coder Whitener Mode 0 3 read-write DIRECT The input data is passed directly to the output without any other operations. 0 WHITE Data is whitened in TX and de-whitened in RX with the whitener feedback register updated every bit period. 1 BYTEWHITE Data is whitened in TX and de-whitened in RX with the whitener feedback register updated every byte period, recommended only for compatibility purposes. 2 INTERLEAVEDWHITE0 Data is whitened in TX after symbol interleaving and de-whitened in RX before symbol de-interleaving. 3 INTERLEAVEDWHITE1 Data is whitened in TX after symbol interleaving and de-whitened in RX before symbol de-interleaving. The first 16 (if INTERLEAVEWIDTH is 0) or 32 (if INTERLEAVEWIDTH is 1) RF symbols are not whitened or de-whitened. 4 BLOCKCODEINSERT Parity bits are added in TX and checked and removed in RX to perform block coding forward error correction (FEC). In transmit mode, the block encoder will insert parity bits between the bit stream provided from the transmit buffer. In receive mode, the block decoder will remove parity bits and they will not further be provided to the receive buffer. 5 BLOCKCODEREPLACE Parity bits are added in TX and checked and removed in RX to perform block coding forward error correction (FEC). In transmit mode, the block encoder will replace bits provided by the transmit buffer with parity bits. In receive mode, the block decoder will output both data bits and parity bits to the receive buffer. 6 BLOCKLOOKUP A lookup table is used to implement table lookup block coding in TX, and table lookup block decoding in RX. 7 CONVMODE Convolutional Encoder / Decoder mode. 4 2 read-write DISABLE Convolutional encoding / decoding is disabled 0 CONVOLUTIONAL Normal convolutional encoding / decoding is enabled 1 REPEAT Repeat-mode convolutional encoding / decoding is enabled 2 CONVDECODEMODE Convolutional decoding mode setting. 6 1 read-write SOFT Use soft decision convolutional decoding, recommended in most cases. 0 HARD Use hard decision convolutional decoding. 1 CONVTRACEBACKDISABLE Convolutional traceback disabling 7 1 read-write X0 Traceback history is enabled, and convolutional decoding will use RAM to store state information. In receive mode, output from convolutional decoding will be generated after the traceback history has reached a certain level. 0 X1 Traceback history is disabled, and convolutional decoding will not use RAM to store state information. No trellis termination sequence will be automatically appended to the transmit data. In receive mode, output from convolutional decoding will be generated after every state transition. This will not provide any convolutional decoding gain, but can be used to decode very simple codes without using any RAM memory. 1 CONVINV Convolutional code symbol inversion 8 2 read-write INTERLEAVEMODE Interleaver mode. 10 2 read-write DISABLE Interleaving is disabled 0 ENABLE Interleaving is enabled 1 RXBUFFER No symbol interleaving is performed, but the interleaver data storage is used as a data buffer in receive mode. This may, for instance, be used for receiver pause functionality. 2 RXTXBUFFER No symbol interleaving is performed, but the interleaver data storage is used as a data buffer in receive and transmit mode. This may, for instance, be used for receiver and transmitter pause functionality. 3 INTERLEAVEFIRSTINDEX 4-bit index of the first interleaver 12 4 read-write INTERLEAVEWIDTH Interleave symbol width. 16 1 read-write ONE Each interleaver element consists of one RF symbol 0 TWO Each interleaver element consists of two RF symbols 1 CONVBUSLOCK Convolutional decoding bus lock 17 1 read-write CONVSUBFRAMETERMINATE Enable trellis termination for subframes 18 1 read-write X0 Trellis termination is applied at the end of the frame. 0 X1 Trellis termination is applied at the end of each subframe and at the end of the frame. 1 SINGLEBLOCK Single block code per frame 19 1 read-write FORCE2FSK Force use of 2-FSK 20 1 read-write CONVHARDERROR Enable convolutional decoding hard error 21 1 read-write X0 Convolutional hard error decoding is disabled. 0 X1 Convolutional hard error decoding is enabled. 1 BLOCKRAMADDR No Description 0x040 read-write 0x00004000 0xFFFFFFFC BLOCKRAMADDR Block decoding RAM address 2 30 read-write CONVRAMADDR No Description 0x044 read-write 0x00004000 0xFFFFFFFC CONVRAMADDR Convolutional decoding RAM address 2 30 read-write CTRL No Description 0x048 read-write 0x00000700 0x001F3FF7 RANDOMTX Random TX Mode 0 1 read-write UARTMODE Data Uart Mode 1 1 read-write BITORDER Data Bit Order. 2 1 read-write LSBFIRST Least Significant bit in each word is sent/received first. 0 MSBFIRST Most Significant bit in each word is sent/received first. 1 TXFCDMODE TX Frame Control Descriptor Mode 4 2 read-write FCDMODE0 FCD0 is reloaded when SCNT reaches 0 0 FCDMODE1 Use FCD0 for the first sub-frame, then switching between FCD0 and FCD1 for following sub-frames 1 FCDMODE2 Use FCD0 for the first sub-frame, then FCD1 is used for all following sub-frames 2 FCDMODE3 Use alternating FCD0 / FCD1 for each complete frame 3 RXFCDMODE RX Frame Control Descriptor Mode 6 2 read-write FCDMODE0 FCD2 is reloaded when SCNT reaches 0 0 FCDMODE1 Use FCD2 for the first sub-frame, then switching between FCD2 and FCD3 for following sub-frames 1 FCDMODE2 Use FCD2 for the first sub-frame, then FCD3 is used for all following sub-frames 2 FCDMODE3 Use alternating FCD2 / FCD3 for each complete frame 3 BITSPERWORD Bits Per Word, for first word in a frame 8 3 read-write RATESELECT MODEM rate select 11 2 read-write TXPREFETCH Transmit prefetch data 13 1 read-write X0 The frame controller will start preparing transmit data when entering the TX state. This setting may be used in most cases. 0 X1 The frame controller will start preparing transmit data already in the TXWARM, RX2TX or TX2TX state. This setting must be used to avoid transmit underflow in the cases where no preamble or frame synchronization is inserted by the modulator (i.e. typically when the MODEM control fields TXBASES is zero and SYNCDATA is set). 1 SEQHANDSHAKE Sequencer data handshake 16 1 read-write X0 The sequencer may read transmit or read data through the FRCRD command, but it will not wait for the sequencer to do so before proceeding to parse transmit or receive data. 0 X1 The frame controller will require that the sequencer program uses the FRCRD command to read both transmit and receive data which the frame controller stores in the DATABUFFER register. If data is not read with this field set, the overflow (RXOF) or underflow (TXUF) will be set. 1 PRBSTEST Pseudo-Random Bit Sequence Testmode 17 1 read-write LPMODEDIS Disable FRC low power 18 1 read-write WAITEOFEN Enable STATE_TX_WAITEOF 19 1 read-write RXABORTIGNOREDIS Disable ignoring CMD_RXABORT 20 1 read-write RXCTRL No Description 0x04C read-write 0x00000000 0x000007FF STORECRC Store CRC value. 0 1 read-write ACCEPTCRCERRORS Accept CRC Errors. 1 1 read-write REJECT Frames with one or more detected CRC errors will be cleared from the receiver buffer. 0 ACCEPT Frames will always be written to the receive buffer, regardless of CRC errors. 1 ACCEPTBLOCKERRORS Accept Block Decoding Errors. 2 1 read-write REJECT Frame reception will be stopped when a block decoding error is found. 0 ACCEPT Frame reception will continue even in the case of a block decoding error. 1 TRACKABFRAME Track Aborted RX Frame 3 1 read-write X0 When a frame abort is triggered, the frame reception is immediately aborted, the RXABORTED interrupt flag is set, and the receiver may start searching for a new frame. 0 X1 When a frame abort is triggered, the receiver is still enabled for the duration of the frame (as defined by the frame length), but no data output is generated. Only when the complete frame is received, the RXABORTED interrupt flag is set and a new frame reception may begin. This mode may, for instance, be used to avoid finding a new FRAMEDET event inside the payload data of a discarded frame. 1 BUFCLEAR Buffer Clear 4 1 read-write BUFRESTOREFRAMEERROR Buffer restore on frame error 5 1 read-write BUFRESTORERXABORTED Buffer restore on RXABORTED 6 1 read-write RXFRAMEENDAHEADBYTES RX frame almost end of packet timing 7 4 read-write TRAILTXDATACTRL No Description 0x050 read-write 0x00000000 0x007FFFFF TRAILTXDATA Trailing Data value 0 8 read-write TRAILTXDATACNT Trailing data bit count 8 3 read-write TRAILTXDATAFORCE Force trailing TX data insertion 11 1 read-write X0 Trailing data in transmit is only applied in order to fill up an integer number of block coding and interleaver buffers. If block coding and interleaving is not used, no trailing data is transmitted. 0 X1 The number of bits defined by TRAILTXDATACNT is always appended to the transmit data, in addition to the necessary bits to fill up an integer number of block coding and interleaver buffers. 1 TRAILTXREPLEN Trailing Data Repeat Length 12 10 read-write TXSUPPLENOVERIDE TX Sup Len Override 22 1 read-write TRAILRXDATA No Description 0x054 read-write 0x00000000 0x0000003F RSSI Append RSSI 0 1 read-write CRCOK Append CRC OK Indicator 1 1 read-write PROTIMERCC0BASE PROTIMER Capture Compare channel 0 Base 2 1 read-write PROTIMERCC0WRAPL PROTIMER Capture Compare channel 0 WrapL 3 1 read-write PROTIMERCC0WRAPH PROTIMER Capture Compare channel 0 WrapH 4 1 read-write RTCSTAMP RTCC Time Stamp 5 1 read-write SCNT No Description 0x058 read-only 0x00000000 0x000000FF SCNT Sub-Frame Counter Value 0 8 read-only CONVGENERATOR No Description 0x05C read-write 0x00000000 0x00037F7F GENERATOR0 Output 0 Generator Polynomial 0 7 read-write GENERATOR1 Output 1 Generator Polynomial 8 7 read-write RECURSIVE Convolutional encoding 16 1 read-write X0 Non-recursive convolutional coding is used 0 X1 Recursive convolutional coding is used 1 NONSYSTEMATIC Non systematic recursive code 17 1 read-write X0 The recursive code is systematic 0 X1 The recursive code is not systematic 1 PUNCTCTRL No Description 0x060 read-write 0x00000101 0x00007F7F PUNCT0 Puncturing Matrix Row for Output 0 0 7 read-write PUNCT1 Puncturing Matrix Row for Output 1 8 7 read-write PAUSECTRL No Description 0x064 read-write 0x00000000 0x001FFFFF FRAMEDETPAUSEEN Frame detect pause enable 0 1 read-write TXINTERLEAVEWRITEPAUSEEN Transmit interleaver write pause enable 1 1 read-write RXINTERLEAVEWRITEPAUSEEN Receive interleaver write pause enable 2 1 read-write INTERLEAVEREADPAUSEEN Interleaver read pause enable 3 1 read-write TXSUBFRAMEPAUSEEN Transmit subframe pause enable 4 1 read-write CONVPAUSECNT Convolutional decoder pause setting 5 6 read-write INTERLEAVEWRITEPAUSECNT Interleaver write pause count 11 5 read-write INTERLEAVEREADPAUSECNT Interleaver read pause count 16 5 read-write IF No Description 0x068 read-write 0x00000000 0x7F7FFFFF TXDONE TX Done Interrupt Flag 0 1 read-write TXAFTERFRAMEDONE TX after frame Done Interrupt Flag 1 1 read-write TXABORTED Transmit Aborted Interrupt Flag 2 1 read-write TXUF Transmit Underflow Interrupt Flag 3 1 read-write RXDONE RX Done Interrupt Flag 4 1 read-write RXABORTED RX Aborted Interrupt Flag 5 1 read-write FRAMEERROR Frame Error Interrupt Flag 6 1 read-write BLOCKERROR Block Error Interrupt Flag 7 1 read-write RXOF Receive Overflow Interrupt Flag 8 1 read-write WCNTCMP0 Word Counter Compare 0 Event 9 1 read-write WCNTCMP1 Word Counter Compare 1 Event 10 1 read-write WCNTCMP2 Word Counter Compare 2 Event 11 1 read-write ADDRERROR Receive address error event 12 1 read-write BUSERROR A bus error event occurred 13 1 read-write RXRAWEVENT Receiver raw data event 14 1 read-write TXRAWEVENT Transmit raw data event 15 1 read-write SNIFFOF Data sniffer overflow 16 1 read-write WCNTCMP3 Word Counter Compare 3 Event 17 1 read-write WCNTCMP4 Word Counter Compare 4 Event 18 1 read-write BOISET BOI SET 19 1 read-write PKTBUFSTART Packet Buffer Start 20 1 read-write PKTBUFTHRESHOLD Packet Buffer Threshold 21 1 read-write RXRAWOF RX raw FIFO overflow 22 1 read-write FRAMEDETPAUSED Frame detected pause event active 24 1 read-write INTERLEAVEWRITEPAUSED Interleaver write pause event active 25 1 read-write INTERLEAVEREADPAUSED Interleaver read pause event active 26 1 read-write TXSUBFRAMEPAUSED Transmit subframe pause event active 27 1 read-write CONVPAUSED Convolutional coder pause event active 28 1 read-write RXWORD Receive Word Interrupt Flag 29 1 read-write TXWORD Transmit Word Interrupt Flag 30 1 read-write IEN No Description 0x06C read-write 0x00000000 0x7F7FFFFF TXDONE TX Done Interrupt Enable 0 1 read-write TXAFTERFRAMEDONE TX after frame Done Interrupt Enable 1 1 read-write TXABORTED Transmit Aborted Interrupt Enable 2 1 read-write TXUF Transmit Underflow Interrupt Enable 3 1 read-write RXDONE RX Done Interrupt Enable 4 1 read-write RXABORTED RX Aborted Interrupt Enable 5 1 read-write FRAMEERROR Frame Error Interrupt Enable 6 1 read-write BLOCKERROR Block Error Interrupt Enable 7 1 read-write RXOF Receive Overflow Interrupt Enable 8 1 read-write WCNTCMP0 Word Counter Compare 0 Enable 9 1 read-write WCNTCMP1 Word Counter Compare 1 Enable 10 1 read-write WCNTCMP2 Word Counter Compare 2 Enable 11 1 read-write ADDRERROR Receive address error enable 12 1 read-write BUSERROR Bus error enable 13 1 read-write RXRAWEVENT Receiver raw data enable 14 1 read-write TXRAWEVENT Transmit raw data enable 15 1 read-write SNIFFOF Data sniffer overflow enable 16 1 read-write WCNTCMP3 Word Counter Compare 3 Enable 17 1 read-write WCNTCMP4 Word Counter Compare 4 Enable 18 1 read-write BOISET BOISET 19 1 read-write PKTBUFSTART PKTBUFSTART Enable 20 1 read-write PKTBUFTHRESHOLD PKTBUFTHRESHOLD Enable 21 1 read-write RXRAWOF RXRAWOF Enable 22 1 read-write FRAMEDETPAUSED Frame detected pause event enable 24 1 read-write INTERLEAVEWRITEPAUSED Interleaver write pause event enable 25 1 read-write INTERLEAVEREADPAUSED Interleaver read pause event enable 26 1 read-write TXSUBFRAMEPAUSED Transmit subframe pause event enable 27 1 read-write CONVPAUSED Convolutional coder pause event enable 28 1 read-write RXWORD Receive Word Interrupt Enable 29 1 read-write TXWORD Transmit Word Interrupt Enable 30 1 read-write OTACNT No Description 0x070 read-only 0x00000000 0xFFFFFFFF OTARXCNT OTA RX bit counter 0 16 read-only OTATXCNT OTA TX bit counter 16 16 read-only BUFFERMODE No Description 0x078 read-write 0x00000000 0x0000000F TXBUFFERMODE Transmit Buffer Mode 0 1 read-write BUFC The Frame Controller fetches data from the Buffer Controller (BUFC) in transmit mode. 0 REGISTER The Frame Controller does not fetch data from the Buffer Controller in transmit mode. Instead, data must be written to the DATABUFFER register when the TXWORD interrupt flag is set. 1 RXBUFFERMODE Receive Buffer Mode 1 2 read-write BUFC The Frame Controller write data to the Buffer Controller (BUFC) in receive mode. 0 REGISTER The Frame Controller does not write data to the Buffer Controller in receive mode. Instead, data must be read from the DATABUFFER register when the RXWORD interrupt flag is set. 1 DISABLE The Frame Controller will not output demodulated data. This mode can, for instance, be used together with storing RAW frame data. 2 RXFRCBUFMUX RX FRC Buffer Mux 3 1 read-write SNIFFCTRL No Description 0x084 read-write 0x000007FC 0x0003FFFF SNIFFMODE Data Sniff Mode 0 2 read-write OFF FRC Packet Sniffer mode is disabled 0 UART UART encoded data is transmitted on the DOUT pin. 1 SPI SPI data is transmitted on the DOUT pin and a data clock is output to the DCLK pin. 2 SNIFFBITS Data sniff data bits 2 1 read-write EIGHT Each sniffer output word contains 8 data bits 0 NINE Each sniffer output word contains 9 data bits 1 SNIFFRXDATA Enable sniffing of received data. 3 1 read-write SNIFFTXDATA Enable sniffing of transmitted data. 4 1 read-write SNIFFRSSI Enable sniffing of RSSI 5 1 read-write SNIFFSTATE Enable sniffing of state information 6 1 read-write SNIFFAUXDATA Enable sniffing of auxiliary data 7 1 read-write SNIFFBR Sniffer baudrate setting 8 8 read-write SNIFFSYNCWORD Sniffer baudrate setting 17 1 read-write AUXDATA No Description 0x088 write-only 0x00000000 0x000001FF AUXDATA Auxiliary sniffer data output 0 9 write-only RAWCTRL No Description 0x08C read-write 0x00000000 0x000021BF TXRAWMODE Transmitter raw data mode 0 2 read-write DISABLE RAW transmit mode is disabled 0 SINGLEBUFFER RAW transmit mode is enabled, transmitting the configured raw data (fetched from RAM) once before transmit is completed. 1 REPEATBUFFER RAW transmit mode is enabled, transmitting the configured raw data (fetched from RAM) repeatedly until the transmitter is disabled. 2 RXRAWMODE Receiver raw data mode 2 3 read-write DISABLE RAW receive mode is disabled 0 SINGLEITEM RAW receive mode is enabled, fetching a single item which is stored in the RXRAWDATA register. A new item is fetched when the RXRAWBLOCKED flag is cleared. In this mode, the flag is cleared automatically when RXRAWDATA is read. 1 SINGLEBUFFER RAW receive mode is enabled, fetching multiple items which are stored to RAM. The RXRAWBLOCKED flag must be cleared in order to start raw data reception. 2 SINGLEBUFFERFRAME This mode is identical to the SINGLEBUFFER mode, except that the FRC will treat the end of the filled buffer as the end of a frame reception (i.e. also trigger the RXDONE interrupt and signal to the RAC that frame reception is complete.) 3 REPEATBUFFER RAW receive mode is enabled, fetching multiple items which are stored to RAM. The RXRAWBLOCKED flag must be cleared in order to start raw data reception. 4 RXRAWRANDOM Receive raw data random number generator 5 1 read-write RXRAWTRIGGER Receiver raw data trigger setting 7 2 read-write IMMEDIATE RAW data storage is triggered immediately when demodulator is enabled. 0 PRS RAW data storage is triggered by the selected RXRAWPRSSEL PRS channel. 1 INTERNALSIG RAW data storage is triggered by an internal signal 2 DEMODRAWDATAMUX Raw data mux control 13 1 read-write DEMODRAWDATASEL RAW data is selected using modem register DEMODRAWDATASEL. 0 DEMODRAWDATASEL2 RAW data is selected using modem register DEMODRAWDATASEL2. 1 RXRAWDATA No Description 0x090 read-only 0x00000000 0xFFFFFFFF RXRAWDATA Receiver RAW data register 0 32 read-only PAUSEDATA No Description 0x094 read-only 0x00000000 0xFFFFFFFF PAUSEDATA Receiver pause data register 0 32 read-only LIKELYCONVSTATE No Description 0x098 read-only 0x00000000 0x0000003F LIKELYCONVSTATE Most likely convolutional decoder state 0 6 read-only INTELEMENTNEXT No Description 0x09C read-only 0x00000000 0x000000FF INTELEMENTNEXT Interleaver element value 0 8 read-only INTWRITEPOINT No Description 0x0A0 read-write 0x00000000 0x0000001F INTWRITEPOINT Interleaver buffer write pointer 0 5 read-write INTREADPOINT No Description 0x0A4 read-write 0x00000000 0x0000001F INTREADPOINT Interleaver buffer read pointer 0 5 read-write AUTOCG No Description 0x0A8 read-write 0x00000000 0x0000FFFF AUTOCGEN Automatic clock gate enable 0 16 read-write CGCLKSTOP No Description 0x0AC read-write 0x00000000 0x0000FFFF FORCEOFF Force off 0 16 read-write SEQIF No Description 0x0B4 read-write 0x00000000 0x7F7FFFFF TXDONE TX Done Interrupt Flag 0 1 read-write TXAFTERFRAMEDONE TX after frame Done Interrupt Flag 1 1 read-write TXABORTED Transmit Aborted Interrupt Flag 2 1 read-write TXUF Transmit Underflow Interrupt Flag 3 1 read-write RXDONE RX Done Interrupt Flag 4 1 read-write RXABORTED RX Aborted Interrupt Flag 5 1 read-write FRAMEERROR Frame Error Interrupt Flag 6 1 read-write BLOCKERROR Block Error Interrupt Flag 7 1 read-write RXOF Receive Overflow Interrupt Flag 8 1 read-write WCNTCMP0 Word Counter Compare 0 Event 9 1 read-write WCNTCMP1 Word Counter Compare 1 Event 10 1 read-write WCNTCMP2 Word Counter Compare 2 Event 11 1 read-write ADDRERROR Receive address error event 12 1 read-write BUSERROR A bus error event occurred 13 1 read-write RXRAWEVENT Receiver raw data event 14 1 read-write TXRAWEVENT Transmit raw data event 15 1 read-write SNIFFOF Data sniffer overflow 16 1 read-write WCNTCMP3 Word Counter Compare 3 Event 17 1 read-write WCNTCMP4 Word Counter Compare 4 Event 18 1 read-write BOISET BOISET Event 19 1 read-write PKTBUFSTART Packet Buffer Start 20 1 read-write PKTBUFTHRESHOLD Packet Buffer Threshold 21 1 read-write RXRAWOF RX raw FIFO overflow 22 1 read-write FRAMEDETPAUSED Frame detected pause event active 24 1 read-write INTERLEAVEWRITEPAUSED Interleaver write pause event active 25 1 read-write INTERLEAVEREADPAUSED Interleaver read pause event active 26 1 read-write TXSUBFRAMEPAUSED Transmit subframe pause event active 27 1 read-write CONVPAUSED Convolutional coder pause event active 28 1 read-write RXWORD Receive Word Interrupt Flag 29 1 read-write TXWORD Transmit Word Interrupt Flag 30 1 read-write SEQIEN No Description 0x0B8 read-write 0x00000000 0x7F7FFFFF TXDONE TX Done Interrupt Enable 0 1 read-write TXAFTERFRAMEDONE TX after frame Done Interrupt Enable 1 1 read-write TXABORTED Transmit Aborted Interrupt Enable 2 1 read-write TXUF Transmit Underflow Interrupt Enable 3 1 read-write RXDONE RX Done Interrupt Enable 4 1 read-write RXABORTED RX Aborted Interrupt Enable 5 1 read-write FRAMEERROR Frame Error Interrupt Enable 6 1 read-write BLOCKERROR Block Error Interrupt Enable 7 1 read-write RXOF Receive Overflow Interrupt Enable 8 1 read-write WCNTCMP0 Word Counter Compare 0 Enable 9 1 read-write WCNTCMP1 Word Counter Compare 1 Enable 10 1 read-write WCNTCMP2 Word Counter Compare 2 Enable 11 1 read-write ADDRERROR Receive address error enable 12 1 read-write BUSERROR Bus error enable 13 1 read-write RXRAWEVENT Receiver raw data enable 14 1 read-write TXRAWEVENT Transmit raw data enable 15 1 read-write SNIFFOF Data sniffer overflow enable 16 1 read-write WCNTCMP3 Word Counter Compare 2 Enable 17 1 read-write WCNTCMP4 Word Counter Compare 2 Enable 18 1 read-write BOISET Word Counter Compare 2 Enable 19 1 read-write PKTBUFSTART PKTBUFSTART Enable 20 1 read-write PKTBUFTHRESHOLD PKTBUFTHRESHOLD Enable 21 1 read-write RXRAWOF RXRAWOF Enable 22 1 read-write FRAMEDETPAUSED Frame detected pause event enable 24 1 read-write INTERLEAVEWRITEPAUSED Interleaver write pause event enable 25 1 read-write INTERLEAVEREADPAUSED Interleaver read pause event enable 26 1 read-write TXSUBFRAMEPAUSED Transmit subframe pause event enable 27 1 read-write CONVPAUSED Convolutional coder pause event enable 28 1 read-write RXWORD Receive Word Interrupt Enable 29 1 read-write TXWORD Transmit Word Interrupt Enable 30 1 read-write WCNTCMP3 No Description 0x0BC read-write 0x00000000 0x00000FFF SUPPLENFIELDLOC Sup Length field location 0 12 read-write BOICTRL No Description 0x0C0 read-write 0x00000000 0x0001FFFF BOIEN BOI EN 0 1 read-write BOIFIELDLOC BOI field location 1 12 read-write BOIBITPOS BOI bit position 13 3 read-write BOIMATCHVAL BOI match value 16 1 read-write DSLCTRL No Description 0x0C4 read-write 0x00000000 0x7FFFFF7F DSLMODE Dynamic Frame Length Mode 0 3 read-write DISABLE Dynamic Frame Length support is disabled, and the frame length is controlled by writing directly to the FRAMELENGTH field 0 SINGLEBYTE Dynamic Frame Length is enabled and located in a single byte over air. This byte is loaded into the least significant byte of the extracted length field 1 SINGLEBYTEMSB Dynamic Frame Length is enabled and located in a single byte over air. This byte is loaded into the most significant byte of the extracted length field 2 DUALBYTELSBFIRST Dynamic Frame Length is enabled and located in two bytes over air, of which the least significant byte is transferred first 3 DUALBYTEMSBFIRST Dynamic Frame Length is enabled and located in two bytes over air, of which the most significant byte is transferred first 4 INFINITE Dynamic Frame Length support is disabled, and infinite frame lengths are transmitted and received. RXABORT may be used to abort active receive operations, while the TXDIS command (available in the RAC) may be used to abort active transmit operations. 5 BLOCKERROR In transmit mode, the frame length must be written directly to the FRAMELENGTH field. In receive mode, data will be received until a block decoding error is found. 6 DSLBITORDER Dynamic Frame Length Bit order 3 1 read-write NORMAL Bit ordering is defined by the BITORDER field 0 REVERSE Bit ordering is reversed, compared to what is defined by the BITORDER field 1 DSLSHIFT Dynamic Frame Length bitshift 4 3 read-write DSLOFFSET Length Field Offset Value 8 8 read-write DSLBITS Length field number of bits 16 4 read-write DSLMINLENGTH Minimum decoded length 20 4 read-write RXSUPRECEPMODE RX Supplement Reception Mode 24 3 read-write NOSUP Do not receive SUP 0 BOIDSLBASED Receive SUP based on BOI and fetch SUPLEN from DSL setting 1 BOIFIXEDSLBASED Receive SUP based on BOI and fetch SUPLEN from WCNTCMP4 2 DSLBASED Receive SUP based irrespective of BOI and fetch SUPLEN from DSL setting 3 FIXEDSLBASED Receive SUP based irrespective of BOI and fetch SUPLEN from WCNTCMP4 setting 4 STORESUP Store SUPP in BUFC 27 1 read-write SUPSHFFACTOR Supp Shift factor 28 3 read-write WCNTCMP4 No Description 0x0C8 read-write 0x00000000 0x00000FFF SUPPLENGTH Supp Length Value 0 12 read-write PKTBUFCTRL No Description 0x0CC read-write 0x00000000 0x0103FFFF PKTBUFSTARTLOC Packet Buffer Start Address 0 12 read-write PKTBUFTHRESHOLD Packet Buffer Threshold 12 6 read-write PKTBUFTHRESHOLDEN Packet Buffer Threshold Enable 24 1 read-write PKTBUFSTATUS No Description 0x0D0 read-only 0x00000000 0x0000003F PKTBUFCOUNT Packet Buffer Count 0 6 read-only PKTBUF0 No Description 0x0D4 read-only 0x00000000 0xFFFFFFFF PKTBUF0 Packet Capture Buffer 0 8 read-only PKTBUF1 Packet Capture Buffer 8 8 read-only PKTBUF2 Packet Capture Buffer 16 8 read-only PKTBUF3 Packet Capture Buffer 24 8 read-only PKTBUF1 No Description 0x0D8 read-only 0x00000000 0xFFFFFFFF PKTBUF4 Packet Capture Buffer 0 8 read-only PKTBUF5 Packet Capture Buffer 8 8 read-only PKTBUF6 Packet Capture Buffer 16 8 read-only PKTBUF7 Packet Capture Buffer 24 8 read-only PKTBUF2 No Description 0x0DC read-only 0x00000000 0xFFFFFFFF PKTBUF8 Packet Capture Buffer 0 8 read-only PKTBUF9 Packet Capture Buffer 8 8 read-only PKTBUF10 Packet Capture Buffer 16 8 read-only PKTBUF11 Packet Capture Buffer 24 8 read-only PKTBUF3 No Description 0x0E0 read-only 0x00000000 0xFFFFFFFF PKTBUF12 Packet Capture Buffer 0 8 read-only PKTBUF13 Packet Capture Buffer 8 8 read-only PKTBUF14 Packet Capture Buffer 16 8 read-only PKTBUF15 Packet Capture Buffer 24 8 read-only PKTBUF4 No Description 0x0E4 read-only 0x00000000 0xFFFFFFFF PKTBUF16 Packet Capture Buffer 0 8 read-only PKTBUF17 Packet Capture Buffer 8 8 read-only PKTBUF18 Packet Capture Buffer 16 8 read-only PKTBUF19 Packet Capture Buffer 24 8 read-only PKTBUF5 No Description 0x0E8 read-only 0x00000000 0xFFFFFFFF PKTBUF20 Packet Capture Buffer 0 8 read-only PKTBUF21 Packet Capture Buffer 8 8 read-only PKTBUF22 Packet Capture Buffer 16 8 read-only PKTBUF23 Packet Capture Buffer 24 8 read-only PKTBUF6 No Description 0x0EC read-only 0x00000000 0xFFFFFFFF PKTBUF24 Packet Capture Buffer 0 8 read-only PKTBUF25 Packet Capture Buffer 8 8 read-only PKTBUF26 Packet Capture Buffer 16 8 read-only PKTBUF27 Packet Capture Buffer 24 8 read-only PKTBUF7 No Description 0x0F0 read-only 0x00000000 0xFFFFFFFF PKTBUF28 Packet Capture Buffer 0 8 read-only PKTBUF29 Packet Capture Buffer 8 8 read-only PKTBUF30 Packet Capture Buffer 16 8 read-only PKTBUF31 Packet Capture Buffer 24 8 read-only PKTBUF8 No Description 0x0F4 read-only 0x00000000 0xFFFFFFFF PKTBUF32 Packet Capture Buffer 0 8 read-only PKTBUF33 Packet Capture Buffer 8 8 read-only PKTBUF34 Packet Capture Buffer 16 8 read-only PKTBUF35 Packet Capture Buffer 24 8 read-only PKTBUF9 No Description 0x0F8 read-only 0x00000000 0xFFFFFFFF PKTBUF36 Packet Capture Buffer 0 8 read-only PKTBUF37 Packet Capture Buffer 8 8 read-only PKTBUF38 Packet Capture Buffer 16 8 read-only PKTBUF39 Packet Capture Buffer 24 8 read-only PKTBUF10 No Description 0x0FC read-only 0x00000000 0xFFFFFFFF PKTBUF40 Packet Capture Buffer 0 8 read-only PKTBUF41 Packet Capture Buffer 8 8 read-only PKTBUF42 Packet Capture Buffer 16 8 read-only PKTBUF43 Packet Capture Buffer 24 8 read-only PKTBUF11 No Description 0x100 read-only 0x00000000 0xFFFFFFFF PKTBUF44 Packet Capture Buffer 0 8 read-only PKTBUF45 Packet Capture Buffer 8 8 read-only PKTBUF46 Packet Capture Buffer 16 8 read-only PKTBUF47 Packet Capture Buffer 24 8 read-only FCD0 No Description 0x104 read-write 0x000000FF 0x0001FFFF WORDS No of Words in sub-frame 0 8 read-write BUFFER Buffer to Access 8 2 read-write INCLUDECRC Include CRC 10 1 read-write CALCCRC Calculate CRC 11 1 read-write SKIPCRC Skip First Words in CRC Calculation 12 2 read-write SKIPWHITE Skip data whitening in this subframe 14 1 read-write ADDTRAILTXDATA Add trailing TX data in this subframe 15 1 read-write EXCLUDESUBFRAMEWCNT Exclude subframe from WCNT 16 1 read-write FCD1 No Description 0x108 read-write 0x000000FF 0x0001FFFF WORDS No of Words in sub-frame 0 8 read-write BUFFER Buffer to Access 8 2 read-write INCLUDECRC Include CRC 10 1 read-write CALCCRC Calculate CRC 11 1 read-write SKIPCRC Skip First Words in CRC Calculation 12 2 read-write SKIPWHITE Skip data whitening in this subframe 14 1 read-write ADDTRAILTXDATA Add trailing TX data in this subframe 15 1 read-write EXCLUDESUBFRAMEWCNT Exclude subframe from WCNT 16 1 read-write FCD2 No Description 0x10C read-write 0x000000FF 0x0001FFFF WORDS No of Words in sub-frame 0 8 read-write BUFFER Buffer to Access 8 2 read-write INCLUDECRC Include CRC 10 1 read-write CALCCRC Calculate CRC 11 1 read-write SKIPCRC Skip First Words in CRC Calculation 12 2 read-write SKIPWHITE Skip data whitening in this subframe 14 1 read-write ADDTRAILTXDATA Add trailing TX data in this subframe 15 1 read-write EXCLUDESUBFRAMEWCNT Exclude subframe from WCNT 16 1 read-write FCD3 No Description 0x110 read-write 0x000000FF 0x0001FFFF WORDS No of Words in sub-frame 0 8 read-write BUFFER Buffer to Access 8 2 read-write INCLUDECRC Include CRC 10 1 read-write CALCCRC Calculate CRC 11 1 read-write SKIPCRC Skip First Words in CRC Calculation 12 2 read-write SKIPWHITE Skip data whitening in this subframe 14 1 read-write ADDTRAILTXDATA Add trailing TX data in this subframe 15 1 read-write EXCLUDESUBFRAMEWCNT Exclude subframe from WCNT 16 1 read-write INTELEMENT0 No Description 0x120 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT1 No Description 0x124 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT2 No Description 0x128 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT3 No Description 0x12C read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT4 No Description 0x130 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT5 No Description 0x134 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT6 No Description 0x138 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT7 No Description 0x13C read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT8 No Description 0x140 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT9 No Description 0x144 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT10 No Description 0x148 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT11 No Description 0x14C read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT12 No Description 0x150 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT13 No Description 0x154 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT14 No Description 0x158 read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only INTELEMENT15 No Description 0x15C read-only 0x00000000 0x000000FF INTELEMENT Interleaver element data 0 8 read-only AGC_NS 1 AGC_NS Registers 0xB800C000 0x00000000 0x00001000 registers AGC 31 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Enable peripheral clock to this module 0 1 read-write STATUS0 No Description 0x008 read-only 0x00000000 0x03FFFFFF GAININDEX Gain Table Index 0 6 read-only RFPKDLAT RFPKD Latch 6 1 read-only IFPKDLOLAT IFPKD Lo threshold pass Latch 7 1 read-only IFPKDHILAT IFPKD Hi threshold pass Latch 8 1 read-only CCA Clear Channel Assessment 9 1 read-only GAINOK Gain OK 10 1 read-only PGAINDEX PGA GAIN INDEX 11 4 read-only LNAINDEX LNA GAIN INDEX 15 4 read-only PNINDEX PN GAIN INDEX 19 5 read-only ADCINDEX ADC Attenuator INDEX 24 2 read-only STATUS2 No Description 0x010 read-only 0x00000000 0xFFFF4FFF RFPKTLATCNT RF PKD Latch CNT 0 12 read-only PNDWNUP Allow PN GAIN UP 14 1 read-only RFPKDPRDCNT RF PKD PERIOD CNT 16 16 read-only RSSI No Description 0x018 read-only 0x00008000 0x0000FFC0 RSSIFRAC RSSI fractional part 6 2 read-only RSSIINT RSSI integer part 8 8 read-only FRAMERSSI No Description 0x01C read-only 0x00008000 0x0000FFC0 FRAMERSSIFRAC FRAMERSSI fractional part 6 2 read-only FRAMERSSIINT FRAMERSSI integer part 8 8 read-only CTRL0 No Description 0x020 read-write 0x2002727F 0xFECFFFFF PWRTARGET Power Target 0 8 read-write MODE Mode 8 3 read-write CONT AGC loop is adjusting gain continuously. 0 LOCKPREDET Gain is locked once a preamble is detected. 1 LOCKFRAMEDET Gain is locked once a sync word is detected. 2 LOCKDSA Gain is locked once DSA is detected. 3 RSSISHIFT RSSI Shift 11 8 read-write DISCFLOOPADJ Disable gain adjustment by CFLOOP 19 1 read-write DISRESETCHPWR Disable Reset of CHPWR 22 1 read-write ADCATTENMODE ADC Attenuator mode 23 1 read-write DISABLE ADC attenuator back-off will not be done by AGC 0 NOTMAXGAIN ADC attenuator is backed-off if rxgain is NOT MAXGAIN 1 ADCATTENCODE ADC Attenuator code 25 2 read-write ENRSSIRESET Enables reset of RSSI and CCA 27 1 read-write DSADISCFLOOP Disable channel filter loop 28 1 read-write DISPNGAINUP Disable PN gain increase 29 1 read-write DISPNDWNCOMP Disable PN gain decrease compensation 30 1 read-write AGCRST AGC reset 31 1 read-write CTRL1 No Description 0x024 read-write 0x00001300 0xFFFFFFFF CCATHRSH Clear Channel Assessment (CCA) Threshold 0 8 read-write RSSIPERIOD RSSI measure period 8 4 read-write PWRPERIOD AGC measure period 12 3 read-write SUBPERIOD Subperiod 15 1 read-write SUBNUM Subperiod numerator 16 5 read-write SUBDEN Subperiod denominator 21 5 read-write SUBINT Subperiod integer 26 6 read-write CTRL2 No Description 0x028 read-write 0x0000610A 0xE3FFFFFF DMASEL DMA select 0 1 read-write RSSI RSSI 0 GAIN Gain 1 SAFEMODE AGC safe mode 1 1 read-write SAFEMODETHD Enter threshold 2 3 read-write REHICNTTHD Exit threshold based on HICNT 5 8 read-write RELOTHD Exit threshold based on Release Counter 13 3 read-write RELBYCHPWR Safe mode release mode 16 2 read-write LO_CNT Increment counter if IFPKD_LO_LAT signal is not set. 0 PWR Increment counter if channel power is below RELTARGETPWR. 1 LO_CNT_PWR Increment if either LO_CNT or PWR. 2 LO_CNT_AND_PWR Increment if both LO_CNT and PWR. 3 RELTARGETPWR Safe Mode Release Power Target 18 8 read-write DEBCNTRST Debonce CNT Reset MODE 29 1 read-write PRSDEBUGEN PRS Debug Enable 30 1 read-write DISRFPKD Disable RF PEAKDET 31 1 read-write CTRL3 No Description 0x02C read-write 0x5140A800 0xFFFFFFFF IFPKDDEB IF PEAKDET debounce mode enable 0 1 read-write IFPKDDEBTHD IF PEAKDET debance thrshold 1 2 read-write IFPKDDEBPRD IF PEAKDET debance period 3 6 read-write IFPKDDEBRST IF PEAKDET debounce period 9 4 read-write RFPKDDEB RF PEAKDET debounce mode enable 13 1 read-write RFPKDDEBTHD RF PEAKDET debance thrshold 14 5 read-write RFPKDDEBPRD RF PEAKDET debance period 19 8 read-write RFPKDDEBRST RFPKD_LAT debounce reset delay 27 5 read-write CTRL4 No Description 0x030 read-write 0x0000000E 0xFE00FFFF PERIODRFPKD RFPKD trigger measure period 0 16 read-write RFPKDPRDGEAR RFPKD Period Gear 25 3 read-write RFPKDSYNCSEL SYNC RF PKD OUTPUT SELECT 28 1 read-write RFPKDSEL RF PKD OUTPUT SELECT 29 1 read-write FRZPKDEN PKD Freeze Enable 30 1 read-write RFPKDCNTEN Counter-based RFPKD Enable 31 1 read-write CTRL5 No Description 0x034 read-write 0x00000000 0x00FFFFFF PNUPDISTHD Disable PN GAIN increase THD 0 12 read-write PNUPRELTHD Enable PN GAIN increase THD 12 12 read-write CTRL6 No Description 0x038 read-write 0x00000000 0xC0000000 SEQPNUPALLOW SEQ Set PN GAIN UP ALLOW 30 1 read-write SEQRFPKDEN SEQ-based RFPKD Enable 31 1 read-write RSSISTEPTHR No Description 0x03C read-write 0x00000000 0x3FFFFFFF POSSTEPTHR Positive Step Threshold 0 8 read-write NEGSTEPTHR Negative Step Threshold 8 8 read-write STEPPER Step Period 16 1 read-write DEMODRESTARTPER Demodulator Restart Period 17 4 read-write DEMODRESTARTTHR Demodulator Restart Threshold 21 8 read-write RSSIFAST RSSI fast startup 29 1 read-write IF No Description 0x044 read-write 0x00000000 0x0000037D RSSIVALID RSSI Value is Valid 0 1 read-write CCA Clear Channel Assessment 2 1 read-write RSSIPOSSTEP Positive RSSI Step Detected 3 1 read-write RSSINEGSTEP Negative RSSI Step Detected 4 1 read-write SHORTRSSIPOSSTEP Short-term Positive RSSI Step Detected 6 1 read-write RFPKDPRDDONE RF PKD PERIOD CNT TOMEOUT 8 1 read-write RFPKDCNTDONE RF PKD pulse CNT TOMEOUT 9 1 read-write IEN No Description 0x048 read-write 0x00000000 0x0000037D RSSIVALID RSSIVALID Interrupt Enable 0 1 read-write CCA CCA Interrupt Enable 2 1 read-write RSSIPOSSTEP RSSIPOSSTEP Interrupt Enable 3 1 read-write RSSINEGSTEP RSSINEGSTEP Interrupt Enable 4 1 read-write SHORTRSSIPOSSTEP SHORTRSSIPOSSTEP Interrupt Enable 6 1 read-write RFPKDPRDDONE RF PKD PERIOD CNT Interrupt Enable 8 1 read-write RFPKDCNTDONE RF PKD pulse CNT Interrupt Enable 9 1 read-write GAINRANGE No Description 0x050 read-write 0x08813187 0x0FFFFFFF LNAINDEXBORDER LNA gain border 0 4 read-write PGAINDEXBORDER PGA gain border 4 4 read-write GAININCSTEP AGC gain increase step size 8 4 read-write PNGAINSTEP PN Gain Step size 12 4 read-write LATCHEDHISTEP Ltached Hi step size 16 4 read-write HIPWRTHD High power detect thrshold 20 6 read-write BOOSTLNA LNA GAIN BOOST mode 26 1 read-write LNABWADJ LNA BW ADJUST 27 1 read-write AGCPERIOD No Description 0x054 read-write 0xD607370E 0xFFFFFFFF PERIODHI AGC measure period hi 0 8 read-write PERIODLO AGC measure period low 8 8 read-write MAXHICNTTHD max hi-countrer threshold 16 8 read-write SETTLETIMEIF IF peak Detector settling time 24 4 read-write SETTLETIMERF RF peak Detector settling time 28 4 read-write HICNTREGION No Description 0x058 read-write 0x08060543 0xFFFFFFFF HICNTREGION0 AGC HICNT to step size map region 0 0 4 read-write HICNTREGION1 AGC HICNT to step size map region 1 4 4 read-write HICNTREGION2 AGC HICNT to step size map region 2 8 8 read-write HICNTREGION3 AGC HICNT to step size map region 3 16 8 read-write HICNTREGION4 AGC HICNT to step size map region 4 24 8 read-write STEPDWN No Description 0x05C read-write 0x00036D11 0x0003FFFF STEPDWN0 AGC gain step size 0 0 3 read-write STEPDWN1 AGC gain step size 1 3 3 read-write STEPDWN2 AGC gain step size 2 6 3 read-write STEPDWN3 AGC gain step size 3 9 3 read-write STEPDWN4 AGC gain step size 4 12 3 read-write STEPDWN5 AGC gain step size 5 15 3 read-write GAINSTEPLIM No Description 0x064 read-write 0x22003144 0x3FFFFFFF CFLOOPSTEPMAX Maximum step in slow loop 0 5 read-write CFLOOPDEL Channel Filter Loop Delay 5 7 read-write HYST Hysteresis 12 4 read-write MAXPWRVAR Maximum Power Variation 16 8 read-write TRANRSTAGC power transient detector Reset AGC 24 1 read-write PNINDEXMAX MAX PN INDEX 25 5 read-write PNRFATT0 No Description 0x068 read-write 0x07142040 0x3FFFFFFF LNAMIXRFATT1 PN RF attenuation code for index 1 0 6 read-write LNAMIXRFATT2 PN RF attenuation code for index 2 6 6 read-write LNAMIXRFATT3 PN RF attenuation code for index 3 12 6 read-write LNAMIXRFATT4 PN RF attenuation code for index 4 18 6 read-write LNAMIXRFATT5 PN RF attenuation code for index 5 24 6 read-write PNRFATT1 No Description 0x06C read-write 0x1F5D038A 0x3FFFFFFF LNAMIXRFATT6 PN RF attenuation code for index 6 0 6 read-write LNAMIXRFATT7 PN RF attenuation code for index 7 6 6 read-write LNAMIXRFATT8 PN RF attenuation code for index 8 12 6 read-write LNAMIXRFATT9 PN RF attenuation code for index 9 18 6 read-write LNAMIXRFATT10 PN RF attenuation code for index 10 24 6 read-write PNRFATT2 No Description 0x070 read-write 0x01A3BAE0 0x03FFFFFF LNAMIXRFATT11 PN RF attenuation code for index 11 0 6 read-write LNAMIXRFATT12 PN RF attenuation code for index 12 6 6 read-write LNAMIXRFATT13 PN RF attenuation code for index 13 12 6 read-write LNAMIXRFATT14 PN RF attenuation code for index 14 18 8 read-write PNRFATT3 No Description 0x074 read-write 0x03E8F67F 0x07FFFFFF LNAMIXRFATT15 PN RF attenuation code for index 15 0 8 read-write LNAMIXRFATT16 PN RF attenuation code for index 16 8 9 read-write LNAMIXRFATT17 PN RF attenuation code for index 17 17 10 read-write LNAMIXCODE0 No Description 0x078 read-write 0x15724BBD 0x3FFFFFFF LNAMIXSLICE1 LNA/MIX slice code for index 1 0 6 read-write LNAMIXSLICE2 LNA/MIX slice code for index 2 6 6 read-write LNAMIXSLICE3 LNA/MIX slice code for index 3 12 6 read-write LNAMIXSLICE4 LNA/MIX slice code for index 4 18 6 read-write LNAMIXSLICE5 LNA/MIX slice code for index 5 24 6 read-write LNAMIXCODE1 No Description 0x07C read-write 0x0518A311 0x3FFFFFFF LNAMIXSLICE6 LNA/MIX slice code for index 6 0 6 read-write LNAMIXSLICE7 LNA/MIX slice code for index 7 6 6 read-write LNAMIXSLICE8 LNA/MIX slice code for index 8 12 6 read-write LNAMIXSLICE9 LNA/MIX slice code for index 9 18 6 read-write LNAMIXSLICE10 LNA/MIX slice code for index 10 24 6 read-write PGACODE0 No Description 0x080 read-write 0x76543210 0xFFFFFFFF PGAGAIN1 PGA GAIN code for index 1 0 4 read-write PGAGAIN2 PGA GAIN code for index 2 4 4 read-write PGAGAIN3 PGA GAIN code for index 3 8 4 read-write PGAGAIN4 PGA GAIN code for index 4 12 4 read-write PGAGAIN5 PGA GAIN code for index 5 16 4 read-write PGAGAIN6 PGA GAIN code for index 6 20 4 read-write PGAGAIN7 PGA GAIN code for index 7 24 4 read-write PGAGAIN8 PGA GAIN code for index 8 28 4 read-write PGACODE1 No Description 0x084 read-write 0x00000A98 0x00000FFF PGAGAIN9 PGA GAIN code for index 9 0 4 read-write PGAGAIN10 PGA GAIN code for index 10 4 4 read-write PGAGAIN11 PGA GAIN code for index 11 8 4 read-write LBT No Description 0x088 read-write 0x00000000 0x0000007F CCARSSIPERIOD RSSI Period during CCA measurements 0 4 read-write ENCCARSSIPERIOD RSSI PERIOD during CCA measurements 4 1 read-write ENCCAGAINREDUCED CCA gain reduced 5 1 read-write ENCCARSSIMAX Use RSSIMAX to indicate CCA 6 1 read-write MIRRORIF No Description 0x08C read-write 0x00000000 0x0000000F RSSIPOSSTEPM Positive RSSI Step Detected 0 1 read-only RSSINEGSTEPM Negative RSSI Step Detected 1 1 read-only SHORTRSSIPOSSTEPM Short-term Positive RSSI Step Detected 2 1 read-only IFMIRRORCLEAR Clear bit for the AGC IF MIRROR Register 3 1 read-write SEQIF No Description 0x090 read-write 0x00000000 0x0000037D RSSIVALID RSSI Value is Valid 0 1 read-write CCA Clear Channel Assessment 2 1 read-write RSSIPOSSTEP Positive RSSI Step Detected 3 1 read-write RSSINEGSTEP Negative RSSI Step Detected 4 1 read-write SHORTRSSIPOSSTEP Short-term Positive RSSI Step Detected 6 1 read-write RFPKDPRDDONE RF PKD PERIOD CNT TOMEOUT 8 1 read-write RFPKDCNTDONE RF PKD pulse CNT TOMEOUT 9 1 read-write SEQIEN No Description 0x094 read-write 0x00000000 0x0000037D RSSIVALID RSSIVALID Interrupt Enable 0 1 read-write CCA CCA Interrupt Enable 2 1 read-write RSSIPOSSTEP RSSIPOSSTEP Interrupt Enable 3 1 read-write RSSINEGSTEP RSSINEGSTEP Interrupt Enable 4 1 read-write SHORTRSSIPOSSTEP SHORTRSSIPOSSTEP Interrupt Enable 6 1 read-write RFPKDPRDDONE RF PKD PERIOD CNT Interrupt Enable 8 1 read-write RFPKDCNTDONE RF PKD pulse CNT Interrupt Enable 9 1 read-write RFCRC_NS 0 RFCRC_NS Registers 0xB8010000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Enable peripheral clock to this module 0 1 read-write CTRL No Description 0x008 read-write 0x00000704 0x00001FEF INPUTINV Input Invert 0 1 read-write OUTPUTINV Output Invert 1 1 read-write CRCWIDTH 2 2 read-write CRCWIDTH8 8 bit (1 Byte) CRC code 0 CRCWIDTH16 16 bit (2 Bytes) CRC code 1 CRCWIDTH24 24 bit (3 Bytes) CRC code 2 CRCWIDTH32 32 bit (4 Bytes) CRC code 3 INPUTBITORDER CRC input bit ordering setting 5 1 read-write LSBFIRST The least significant data bit is first input to the CRC generator. 0 MSBFIRST The most significant data bit is first input to the CRC generator. 1 BYTEREVERSE Reverse CRC byte ordering over air 6 1 read-write NORMAL The least significant byte of the CRC register is transferred first over air via the Frame Controller. 0 REVERSED The most significant byte of the CRC register is transferred first over air via the Frame Controller. 1 BITREVERSE Reverse CRC bit ordering over air 7 1 read-write NORMAL The bit ordering of CRC data is the same as defined by the BITORDER field in the Frame Controller. 0 REVERSED The bit ordering of CRC data is the opposite as defined by the BITORDER field in the Frame Controller. 1 BITSPERWORD Number of bits per input word 8 4 read-write PADCRCINPUT Pad CRC input data 12 1 read-write X0 No zero-padding of CRC input data is applied 0 X1 CRC input data is zero-padded, such that the number of bytes over which the CRC value is calculated at least equals the length of the calculated CRC value. 1 STATUS No Description 0x00C read-only 0x00000000 0x00000001 BUSY CRC Running 0 1 read-only CMD No Description 0x010 write-only 0x00000000 0x00000001 INITIALIZE Initialize CRC 0 1 write-only INPUTDATA No Description 0x014 write-only 0x00000000 0x0000FFFF INPUTDATA Input Data 0 16 write-only INIT No Description 0x018 read-write 0x00000000 0xFFFFFFFF INIT CRC Initialization Value 0 32 read-write DATA No Description 0x01C read-only 0x00000000 0xFFFFFFFF DATA CRC Data Register 0 32 read-only POLY No Description 0x020 read-write 0x00000000 0xFFFFFFFF POLY CRC Polynomial Value 0 32 read-write MODEM_NS 1 MODEM_NS Registers 0xB8014000 0x00000000 0x00001000 registers MODEM 35 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Enable peripheral clock to this module 0 1 read-write STATUS No Description 0x008 read-only 0x00000000 0xFFFF7FF7 DEMODSTATE DEMOD state 0 3 read-only OFF Off state 0 TIMINGSEARCH Timing search 1 PRESEARCH Preamble search 2 FRAMESEARCH Frame search 3 RXFRAME Payload Detection 4 FRAMEDETMODE0 Timing search with sliding window (FDM0) 5 FRAMEDETID Frame Detected ID 4 1 read-only FRAMEDET0 Last frame was detected with sync word defined in SYNC0. 0 FRAMEDET1 Last frame was detected with sync word defined in SYNC1. 1 ANTSEL Selected Antenna 5 1 read-only ANTENNA0 Antenna 0 is selected (ANT0 = 1 and ANT1 = 0). 0 ANTENNA1 Antenna 1 is selected (ANT0 = 0 and ANT1 = 1). 1 TIMSEQINV Timing Sequence Inverted 6 1 read-only TIMLOSTCAUSE Timing Lost Cause 7 1 read-only LOWCORR Timing lost during Preamble Search or due to low correlation value during Frame Search. 0 TIMEOUT Timing lost due to incorrect symbols detected during Frame Search. 1 DSADETECTED DSA detected 8 1 read-only DSAFREQESTDONE DSA frequency estimation complete 9 1 read-only VITERBIDEMODTIMDET Viterbi Demod timing detected 10 1 read-only VITERBIDEMODFRAMEDET Viterbi Demod frame detected 11 1 read-only STAMPSTATE BLE Viterbi Demod Timing Stamp 12 3 read-only CORR Correlation 16 8 read-only WEAKSYMBOLS Weak symbols 24 8 read-only TIMDETSTATUS No Description 0x00C read-only 0x00000000 0x1F0FFFFF TIMDETCORR Correlation value 0 8 read-only TIMDETFREQOFFEST Frequency offset estimate 8 8 read-only TIMDETPREERRORS Preamble errors 16 4 read-only TIMDETPASS Timing detection pass 24 1 read-only TIMDETINDEX Timing detection index 25 4 read-only FREQOFFEST No Description 0x010 read-only 0x00000000 0xFFFF1FFF FREQOFFEST Frequency offset estimate 0 13 read-only CORRVAL Correlation value 16 8 read-only SOFTVAL Soft detection value 24 8 read-only AFCADJRX No Description 0x014 read-only 0x00000000 0x0007FFFF AFCADJRX AFC adjustment for RX 0 19 read-only AFCADJTX No Description 0x018 read-only 0x00000000 0x0007FFFF AFCADJTX AFC adjustment for TX 0 19 read-only MIXCTRL No Description 0x01C read-write 0x00000000 0x0000001F ANAMIXMODE Analog receiver mixer mode of operation 0 4 read-write NORMAL The analog mixer operates in its normal mode 0 IPQPIQSWAP I path is positive, Q path is positive, I and Q are swapped 1 IPQN I path is positive, Q path is negative 2 IPQNIQSWAP I path is positive, Q path is negative, I and Q are swapped 3 INQP I path is negative, Q path is positive 4 INQPIQSWAP I path is negative, Q path is positive, I and Q are swapped 5 INQN I path is negative, Q path is negative 6 INQNIQSWAP I path is negative, Q path is negative, I and Q are swapped 7 UPCONVERT Control the analog receiver mixer such that the analog mixer performs a digital up-conversion on the mixer output, with the frequency set by the DEC0 and CFOSR settings. This mode may be used to perform RF loopback using the normal synthesizer both for transmit and receive, and still get a positive IF frequency on the IF receive signal. 8 DOWNCONVERT Control the analog receiver mixer such that the analog mixer performs a digital down-conversion on the mixer output, with the frequency set by the DEC0 and CFOSR settings. 9 DIGIQSWAPEN Digital I/Q swap enable 4 1 read-write CTRL0 No Description 0x020 read-write 0x00000000 0xFFFFFFFF FDM0DIFFDIS Frame Detection Mode 0 disable 0 1 read-write MAPFSK Mapping of FSK symbols 1 3 read-write MAP0 4FSK: Symbol 11, 10, 00, 01 for decreasing frequency. 2FSK/MSK/ASK/OOK: Symbol 1 is high/positive frequency or high amplitude, symbol 0 is low/negative frequency or low amplitude. 0 MAP1 4FSK: Symbol 01, 00, 10, 11 for decreasing frequency. 2FSK/MSK/ASK/OOK: Symbol 0 is high/negative frequency or high amplitude, symbol 1 is low/negative frequency or low amplitude. 1 MAP2 4FSK: Symbol 10, 11, 01, 00 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 2 MAP3 4FSK: Symbol 00, 01, 11, 10 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 3 MAP4 4FSK: Symbol 11, 01, 00, 10 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 4 MAP5 4FSK: Symbol 10, 00, 01, 11 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 5 MAP6 4FSK: Symbol 01, 11, 10, 00 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 6 MAP7 4FSK: Symbol 00, 10, 11, 01 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 7 CODING Symbol coding 4 2 read-write NRZ Non Return to Zero 0 MANCHESTER Manchester Coding 1 DSSS Direct Sequence Spread Spectrum 2 LINECODE Line code. Maps 0 to 0011 symbol and 1 to 1100 symbols 3 MODFORMAT Modulation format 6 3 read-write FSK2 Frequency Shift Keying with 2 symbols 0 FSK4 Frequency Shift Keying with 4 symbols 1 BPSK Binary Phase Shift Keying 2 DBPSK Differentially encoded Binary Phase Shift Keying 3 OQPSK Half Sine Shaped Offset Quadrature Phase Shift Keying 4 MSK Minimum Shift Keying 5 OOKASK On Off Keying and Amplitude Shift Keying 6 DUALCORROPTDIS Dual Correlation Optimization Disable 9 1 read-write OOKASYNCPIN OOK asynchronous pin mode 10 1 read-write DSSSLEN DSSS length 11 5 read-write DSSSSHIFTS DSSS shifts 16 3 read-write NOSHIFT No symbols are defined by shifting. 0 SHIFT1 Next symbol generated by 1 cyclic shift. 1 SHIFT2 Next symbol generated by 2 cyclic shifts. 2 SHIFT4 Next symbol generated by 4 cyclic shifts. 3 SHIFT8 Next symbol generated by 8 cyclic shifts. 4 SHIFT16 Next symbol generated by 16 cyclic shifts. 5 DSSSDOUBLE DSSS double 19 2 read-write DIS Doubling is disabled. 0 INV Doubling is enabled by using inverted symbols. 1 CONJ Doubling is enabled by using complex conjugated symbols. 2 DETDIS Detection disable 21 1 read-write DIFFENCMODE Differential encoding mode 22 3 read-write DIS Differential Encoding is disabled. 0 RR0 Transmit the XOR-ed value of the Raw symbol and the last Raw symbol. Initial Raw symbol is 0. 1 RE0 Transmit the XOR-ed value of the Raw symbol and the last Encoded symbol. Initial Encoded symbol is 0. 2 RR1 Transmit the XOR-ed value of the Raw symbol and the last Raw symbol. Initial Raw symbol is 1. 3 RE1 Transmit the XOR-ed value of the Raw symbol and the last Encoded symbol. Initial Encoded symbol is 1. 4 SHAPING Shaping filter 25 2 read-write DISABLED Filter disabled. 0 ODDLENGTH Filter has odd length. Filter uses coefficients 0,1,2,3,4,5,6,7,8,7,6,5,4,3,2,1,0. 1 EVENLENGTH Filter has even length. Filter uses coefficients 0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0. 2 ASYMMETRIC Filter has asymmetrical coefficients. Filter uses coefficients 0,1,2,3,4,5,6,7. 3 DEMODRAWDATASEL Demod raw data select 27 3 read-write DIS Disabled. 0 ENTROPY 1-bit entropy source extracted from the RF receive chain, to be used for random number generation. 1 ADC 2 * 3-bit I and Q ADC data. 2 FILTLSB 2 * 16-bit I and Q channel filtered data downmixed to zero-IF. The receive signal chain has 19 bits dynamic range at this point, and the FILTLSB setting outputs the 16 least significant bits (with saturation). 3 FILTMSB 2 * 16-bit I and Q channel filtered data downmixed to zero-IF. The receive signal chain has 19 bits dynamic range at this point, and the FILTMSB setting outputs the 16 most significant bits (with truncation). 4 FILTFULL 2 * 19-bit I and Q channel filtered data downmixed to zero-IF. The FILTFULL option will output all 19 bits of dynamic range, sign extended to 32 bits. 5 FREQ 8-bit received frequency data (or logarithmic amplitude for ASK/OOK). 6 DEMOD 8-bit demodulated data (freq/amp/phase). When coherent detection is enabled, only the in-phase component is selected. 7 FRAMEDETDEL FRAMEDET delay 30 2 read-write DEL0 No delay 0 DEL8 8 baud delay 1 DEL16 16 baud delay 2 DEL32 32 baud delay 3 CTRL1 No Description 0x024 read-write 0x00000000 0xFFFFDFFF SYNCBITS Number of sync-word bits 0 5 read-write SYNCERRORS Maximum number of sync errors 5 4 read-write DUALSYNC Dual sync words. 9 1 read-write DISABLED Demodulator only searches for SYNC0. 0 ENABLED Demodulator searches for SYNC0 and SYNC1 in parallel. 1 TXSYNC Transmit sync word. 10 1 read-write SYNC0 Modulator transmits SYNC0. 0 SYNC1 Modulator transmits SYNC1. 1 SYNCDATA Sync data. 11 1 read-write DISABLED SYNC is not part of transmit payload. Modulator adds SYNC in transmit. 0 ENABLED SYNC is part of transmit payload. Modulator does not add SYNC in transmit. 1 SYNC1INV SYNC1 invert. 12 1 read-write COMPMODE Compensation mode 14 2 read-write DIS Compensation is disabled. 0 PRELOCK Compensation locks when preamble is detected. 1 FRAMELOCK Compensation locks when frame is detected. 2 NOLOCK Compensation is always running 3 RESYNCPER Resync period 16 4 read-write PHASEDEMOD Phase demodulation 20 2 read-write BDD Bit Differential Detection. 0 MBDD Multibit Differential Detection. 1 FREQOFFESTPER Frequency offset estimation period 22 3 read-write FREQOFFESTLIM Frequency offset limit 25 7 read-write CTRL2 No Description 0x028 read-write 0x00001000 0xFFFFFFFF SQITHRESH Signal Quality Indicator threshold 0 8 read-write RXFRCDIS Receive FRC disable 8 1 read-write RXPINMODE Receive pin mode 9 1 read-write SYNCHRONOUS Detected payload bits are clocked out on DOUT. Only setups with 1 bit per symbol are supported. 0 ASYNCHRONOUS DOUT is continuously providing the sign of the detected frequency deviation before offset compensation. Only 2/4-FSK is supported. 1 TXPINMODE Transmit pin mode 10 2 read-write OFF Pinmode is turned off. Data is gathered from FRC. DOUT/DCLK clocks out transmitted data. 0 UNUSED Unused mode 1 ASYNCHRONOUS DIN/PRS controls transmitted baud directly. DCLK is set to 0. No support for frame handling nor coding. Only 2-FSK and OOK/ASK can be used. 2 SYNCHRONOUS DIN/PRS is sampled on the rising edge of DCLK and used as payload. Frame handling and coding is supported. Only setups with 1 bit per symbol is supported. 3 DATAFILTER Datafilter 12 3 read-write DISABLED Datafilter disabled 0 SHORT Short datafilter enabled. 2*RXBRFRAC should be more than 3. 1 MEDIUM Medium datafilter enabled. 2*RXBRFRAC should be more than 4. 2 LONG Long datafilter enabled. 2*RXBRFRAC should be more than 5. 3 LEN6 Datafilter with length 6 enabled. 2*RXBRFRAC should be more than 6. 4 LEN7 Datafilter with length 7 enabled. 2*RXBRFRAC should be more than 7. 5 LEN8 Datafilter with length 8 enabled. 2*RXBRFRAC should be more than 8. 6 LEN9 Datafilter with length 9 enabled. 2*RXBRFRAC should be more than 9. 7 BRDIVA Baudrate division factor A 15 4 read-write BRDIVB Baudrate division factor B 19 4 read-write DEVMULA Deviation multiplication factor A 23 2 read-write DEVMULB Deviation multiplication factor B 25 2 read-write RATESELMODE Rate select mode 27 2 read-write NOCHANGE No rate change. BRDIVA/DEVMULA is used for entire frame. 0 PAYLOAD Change rate for payload. BRDIVA/DEVMULA is used for header and BRDIVB/DEVMULB is used for payload. 1 FRC FRC selects between BRDIVA/DEVMULA and BRDIVB/DEVMULB for each symbol in the payload. Header uses BRDIVA/DEVMULA. 2 SYNC The configured/detected syncword decides the settings used for the payload. SYNC0 uses BRDIVA/DEVMULA and SYNC1 uses BRDIVB/DEVMULB. Header uses BRDIVA/DEVMULA. 3 DEVWEIGHTDIS Deviation weighting disable. 29 1 read-write DMASEL DMA select. 30 2 read-write SOFT SOFTVAL field 0 CORR CORRVAL field 1 FREQOFFEST FREQOFFEST field 2 POE POE field 3 CTRL3 No Description 0x02C read-write 0x00008000 0xFFFFFF81 PRSDINEN DIN PRS enable 0 1 read-write ANTDIVMODE Antenna Diversity mode 8 3 read-write ANTENNA0 Antenna 0 (ANT0=1, ANT1=0) is used 0 ANTENNA1 Antenna 1 (ANT0=0, ANT1=1) is used 1 ANTSELFIRST Select-First algorithm. 2 ANTSELCORR Select-Best algorithm based on correlation value. 3 ANTSELRSSI Select-Best algorithm based on RSSI value. 4 ANTDIVREPEATDIS Antenna diversity repeat disable 11 1 read-write TSAMPMODE Timing Search Amplitude Mode 12 2 read-write OFF Amplitude is not used during timing search. 0 ON Timing detection is disabled for windows where at least one sample is below limit set by TSAMPLIM. 1 DIFF Timing detection is disabled for windows where the difference between samples is higher than the limit set by TSAMPLIM. 2 TSAMPDEL Timing Search Amplitude delay 14 2 read-write TSAMPLIM Timing Search Amplitude limit 16 16 read-write CTRL4 No Description 0x030 read-write 0x03000000 0xBFFFFFFF ISICOMP Inter Symbol Interference compensation 0 4 read-write DEVOFFCOMP Deviation offset compensation 4 1 read-write PREDISTGAIN Predistortion gain 5 5 read-write PREDISTDEB Predistortion debounce 10 3 read-write PREDISTAVG Predistortion Average 13 1 read-write AVG8 Average over 8 samples. 0 AVG16 Average over 16 samples. 1 PREDISTRST Predistortion Reset 14 1 read-write PHASECLICKFILT Phase click filter 15 7 read-write SOFTDSSSMODE Soft DSSS mode 22 1 read-write CORR0INV Soft value is inverted value of symbol-0 correlation value. 0 CORRDIFF Soft value is difference between correlation values for symbol-0 and symbol-1. 1 ADCSATLEVEL ADC Saturation Level setting 23 3 read-write CONS1 AGC enters fast loop after first saturation sample. 0 CONS2 2 saturation samples required before AGC enters fast loop. 1 CONS4 4 saturation samples required before AGC enters fast loop. 2 CONS8 8 saturation samples required before AGC enters fast loop. 3 CONS16 16 saturation samples required before AGC enters fast loop. 4 CONS32 32 saturation samples required before AGC enters fast loop. 5 CONS64 64 saturation samples required before AGC enters fast loop. 6 ADCSATDENS ADC Saturation Density setting 26 2 read-write OFFSETPHASEMASKING Offset phase masking 28 1 read-write OFFSETPHASESCALING Offset phase scaling 29 1 read-write CTRL5 No Description 0x034 read-write 0x00000000 0x607007FE BRCALEN Baudrate calibration enable 1 1 read-write BRCALMODE Baudrate calibration mode 2 2 read-write PEAK Measure period between peaks in demodulated signal. This mode can give false peaks for high oversampling ratios without sufficient datafiltering. 0 ZERO Measure period between zero-crossings in demodulated signal. This mode can miss zero-crossings for high frequency offsets. 1 PEAKZERO Combine peak-period and zero-crossing periods. This mode gives best accuracy, but includes weaknesses from both PEAK and ZERO modes. 2 BRCALAVG Baudrate calibration averaging 4 2 read-write DETDEL Detection delay 6 3 read-write TDEDGE Timing detection edge mode 9 1 read-write TREDGE Timing resynchronization edge mode 10 1 read-write DEMODRAWDATASEL2 Demod raw data select 2 20 3 read-write DIS Disabled. 0 CORR 4-bit max_corr_index and 17-bit max_corr . 2 CHPW 8-bit channel power and 4-bit BBSSMUX 3 BBPF 11-bit pre-filter correlation output for BLR and 11-bit pre-filter correlation output for COH demod 4 FSM 5-bit Narrow-band BLE FSM state, 5-bit Long-range BLE FSM state, 3-bit DSA FSM state, 7-bit Detection FSM State. Captured each time state changes 5 RESYNCBAUDTRANS Resynchronization Baud Transitions 29 1 read-write RESYNCLIMIT Resynchronization Limit 30 1 read-write HALF Adjust timing if accumulated timing is higher/lower than RESYNCPER/2. 0 ALWAYS Adjust timing if accumulated timing is non-zero. 1 CTRL6 No Description 0x038 read-write 0x00000000 0xF6000000 CODINGB Coding format 25 2 read-write NRZ Non Return to Zero 0 MANCHESTER Manchester Coding 1 DSSS Direct Sequence Spread Spectrum 2 LINECODE Line code. Maps 0 to 0011 symbol and 1 to 1100 symbols 3 RXBRCALCDIS RX Baudrate Calculation Disable 30 1 read-write TXBR No Description 0x058 read-write 0x00000000 0x00FFFFFF TXBRNUM Transmit baudrate numerator 0 16 read-write TXBRDEN Transmit baudrate denominator 16 8 read-write RXBR No Description 0x05C read-write 0x00000000 0x00001FFF RXBRNUM Receive baudrate numerator 0 5 read-write RXBRDEN Receive baudrate denominator 5 5 read-write RXBRINT Receive baudrate integer 10 3 read-write CF No Description 0x060 read-write 0x00000000 0xCFFFFFFF DEC0 First decimation 0 3 read-write DF3 Decimation Factor 0 = 3. Cutoff 0.050 * f<subscript>HFXO</subscript>. 0 DF4WIDE Decimation Factor 0 = 4. Cutoff 0.069 * f<subscript>HFXO</subscript>. 1 DF4NARROW Decimation Factor 0 = 4. Cutoff 0.037 * f<subscript>HFXO</subscript>. 2 DF8WIDE Decimation Factor 0 = 8. Cutoff 0.012 * f<subscript>HFXO</subscript>. 3 DF8NARROW Decimation Factor 0 = 8. Cutoff 0.005 * f<subscript>HFXO</subscript>. 4 DEC1 Second decimation 3 14 read-write DEC2 Third decimation 17 6 read-write CFOSR Center Frequency Oversampling Ratio 23 3 read-write CF7 Oversampling ratio = 7 0 CF8 Oversampling ratio = 8 1 CF12 Oversampling ratio = 12 2 CF16 Oversampling ratio = 16 3 CF32 Oversampling ratio = 32 4 CF0 Center frequency set to 0 5 DEC1GAIN Second decimation filter gain 26 2 read-write ADD0 No additional gain. Suggested setting for BW higher than 1kHz 0 ADD6 6 dB additional gain. Suggested setting for BW between 250 Hz and 1 kHz 1 ADD12 12 dB additional gain. Suggested setting for BW less than 250 Hz 2 PRE No Description 0x064 read-write 0x00000000 0xFFFF1FFF BASE Preamble base 0 4 read-write BASEBITS BASE bits 4 2 read-write PRESYMB4FSK Preamble symbols 4-FSK 6 1 read-write OUTER Symbols corresponding to +/- 3dev. 0 INNER Symbols corresponding to +/- dev. 1 PREERRORS Preamble errors 7 4 read-write DSSSPRE DSSS preamble 11 1 read-write SYNCSYMB4FSK Sync symbols 4FSK 12 1 read-write FSK2 The syncword is 2FSK modulated. Each bit in SYNCn is encoded as a positive or negative deviation. The deviation is controlled by PRESYMB4FSK. 0 FSK4 The syncword is 4FSK modulated. Every two bits in SYNCn are encoded as a 4FSK symbol. 1 TXBASES TX bases 16 16 read-write SYNC0 No Description 0x068 read-write 0x00000000 0xFFFFFFFF SYNC0 Sync-word 0 0 32 read-write SYNC1 No Description 0x06C read-write 0x00000000 0xFFFFFFFF SYNC1 Sync word 1 0 32 read-write TIMING No Description 0x080 read-write 0x00000000 0xFFFFFFFF TIMTHRESH Timing threshold 0 8 read-write TIMINGBASES Timing bases 8 4 read-write ADDTIMSEQ Additional timing sequences 12 4 read-write TIMSEQINVEN Timing sequence inversion enable 16 1 read-write TIMSEQSYNC Timing sequence part of sync-word 17 1 read-write FDM0THRESH Frame Detection Mode 0 threshold 18 3 read-write OFFSUBNUM Offset subperiod numerator 21 4 read-write OFFSUBDEN Offset subperiod denominator 25 4 read-write TSAGCDEL Timing Search AGC delay 29 1 read-write FASTRESYNC Fast timing resynchronization 30 2 read-write DIS Disabled. 0 PREDET Allow fast resynchronization until preamble is detected. 1 FRAMEDET Allow fast resynchronization until frame is detected. 2 DSSS0 No Description 0x084 read-write 0x00000000 0xFFFFFFFF DSSS0 DSSS symbol 0 0 32 read-write MODINDEX No Description 0x088 read-write 0x00000000 0x003F03FF MODINDEXM Modulation index mantissa. 0 5 read-write MODINDEXE Modulation index exponent. 5 5 read-write FREQGAINE Frequency demodulation gain - exponent 16 3 read-write FREQGAINM Frequency demodulation gain - mantissa 19 3 read-write AFC No Description 0x08C read-write 0x00000000 0x1FFFFDFF AFCSCALEM AFC scaling mantissa 0 5 read-write AFCSCALEE AFC scaling exponent 5 4 read-write AFCRXMODE AFC RX mode 10 3 read-write DIS Disabled. 0 FREE Free running. AFCADJRX constantly updated. 1 FREEPRESTART Free running. AFCADJRX not updated before preamble is detected. 2 TIMLOCK AFCADJRX locked when timing is detected. 3 PRELOCK AFCADJRX locked when preamble is detected. 4 FRAMELOCK AFCADJRX locked when frame is detected. 5 FRAMELOCKPRESTART AFCADJRX not updated before preamble is detected and locked when frame is detected. 6 AFCTXMODE AFC TX mode 13 2 read-write DIS Disabled. 0 PRELOCK AFCADJTX loaded from AFCADJRX when preamble is detected. 1 FRAMELOCK AFCADJTX loaded from AFCADJRX when frame is detected. 2 AFCRXCLR AFCRX clear mode 15 1 read-write AFCDEL AFC delay 16 5 read-write AFCAVGPER AFC average period 21 3 read-write AFCLIMRESET Reset AFCADJRX value 24 1 read-write AFCONESHOT AFC One-Shot feature 25 1 read-write AFCENINTCOMP Internal frequency offset compensation 26 1 read-write AFCDSAFREQOFFEST Consider frequency offset estimation 27 1 read-write AFCDELDET Delay Detection state machine 28 1 read-write AFCADJLIM No Description 0x090 read-write 0x00000000 0x0003FFFF AFCADJLIM AFC adjustment limit 0 18 read-write SHAPING0 No Description 0x094 read-write 0x22130A04 0xFFFFFFFF COEFF0 Shaping Coefficient 0 0 8 read-write COEFF1 Shaping Coefficient 1 8 8 read-write COEFF2 Shaping Coefficient 2 16 8 read-write COEFF3 Shaping Coefficient 3 24 8 read-write SHAPING1 No Description 0x098 read-write 0x4F4A4132 0xFFFFFFFF COEFF4 Shaping Coefficient 4 0 8 read-write COEFF5 Shaping Coefficient 5 8 8 read-write COEFF6 Shaping Coefficient 6 16 8 read-write COEFF7 Shaping Coefficient 7 24 8 read-write SHAPING2 No Description 0x09C read-write 0x00000000 0xFFFFFFFF COEFF8 Shaping Coefficient 8 0 8 read-write COEFF9 Shaping Coefficient 9 8 8 read-write COEFF10 Shaping Coefficient 10 16 8 read-write COEFF11 Shaping Coefficient 11 24 8 read-write SHAPING3 No Description 0x0A0 read-write 0x00000000 0xFFFFFFFF COEFF12 Shaping Coefficient 12 0 8 read-write COEFF13 Shaping Coefficient 13 8 8 read-write COEFF14 Shaping Coefficient 14 16 8 read-write COEFF15 Shaping Coefficient 15 24 8 read-write SHAPING4 No Description 0x0A4 read-write 0x00000000 0xFFFFFFFF COEFF16 Shaping Coefficient 16 0 8 read-write COEFF17 Shaping Coefficient 17 8 8 read-write COEFF18 Shaping Coefficient 18 16 8 read-write COEFF19 Shaping Coefficient 19 24 8 read-write SHAPING5 No Description 0x0A8 read-write 0x00000000 0xFFFFFFFF COEFF20 Shaping Coefficient 20 0 8 read-write COEFF21 Shaping Coefficient 21 8 8 read-write COEFF22 Shaping Coefficient 22 16 8 read-write COEFF23 Shaping Coefficient 23 24 8 read-write SHAPING6 No Description 0x0AC read-write 0x00000000 0xFFFFFFFF COEFF24 Shaping Coefficient 24 0 8 read-write COEFF25 Shaping Coefficient 25 8 8 read-write COEFF26 Shaping Coefficient 26 16 8 read-write COEFF27 Shaping Coefficient 27 24 8 read-write SHAPING7 No Description 0x0B0 read-write 0x00000000 0xFFFFFFFF COEFF28 Shaping Coefficient 28 0 8 read-write COEFF29 Shaping Coefficient 29 8 8 read-write COEFF30 Shaping Coefficient 30 16 8 read-write COEFF31 Shaping Coefficient 31 24 8 read-write SHAPING8 No Description 0x0B4 read-write 0x00000000 0xFFFFFFFF COEFF32 Shaping Coefficient 32 0 8 read-write COEFF33 Shaping Coefficient 33 8 8 read-write COEFF34 Shaping Coefficient 34 16 8 read-write COEFF35 Shaping Coefficient 35 24 8 read-write SHAPING9 No Description 0x0B8 read-write 0x00000000 0xFFFFFFFF COEFF36 Shaping Coefficient 36 0 8 read-write COEFF37 Shaping Coefficient 37 8 8 read-write COEFF38 Shaping Coefficient 38 16 8 read-write COEFF39 Shaping Coefficient 39 24 8 read-write SHAPING10 No Description 0x0BC read-write 0x00000000 0xFFFFFFFF COEFF40 Shaping Coefficient 40 0 8 read-write COEFF41 Shaping Coefficient 41 8 8 read-write COEFF42 Shaping Coefficient 42 16 8 read-write COEFF43 Shaping Coefficient 43 24 8 read-write SHAPING11 No Description 0x0C0 read-write 0x00000000 0xFFFFFFFF COEFF44 Shaping Coefficient 44 0 8 read-write COEFF45 Shaping Coefficient 45 8 8 read-write COEFF46 Shaping Coefficient 46 16 8 read-write COEFF47 Shaping Coefficient 47 24 8 read-write RAMPCTRL No Description 0x0C4 read-write 0x00000555 0xFF800FFF RAMPRATE0 Ramp rate 0 0 4 read-write RAMPRATE1 Ramp rate 1 4 4 read-write RAMPRATE2 Ramp rate 2 8 4 read-write RAMPLEV No Description 0x0CC read-write 0x009F9F9F 0x00FFFFFF RAMPLEV0 Ramp level 0 0 8 read-write RAMPLEV1 Ramp level 1 8 8 read-write RAMPLEV2 Ramp level 2 16 8 read-write DCCOMP No Description 0x0E0 read-write 0x00000030 0x000001FF DCESTIEN DC Offset Estimation Enable 0 1 read-write DCCOMPEN DC Offset Compensation Enable 1 1 read-write DCRSTEN DC Compensation Filter Reset Enable 2 1 read-write DCCOMPFREEZE DC Offset Compensation Filter Freeze 3 1 read-write DCCOMPGEAR DC Offset Compensation Filter Gear 4 3 read-write DCLIMIT DC offset limit 7 2 read-write FULLSCALE 1000 mV 0 FULLSCALEBY4 250 mV 1 FULLSCALEBY8 125 mV 2 FULLSCALEBY16 62 mV 3 DCCOMPFILTINIT No Description 0x0E4 read-write 0x00000000 0x7FFFFFFF DCCOMPINITVALI I-channel initialization value 0 15 read-write DCCOMPINITVALQ Q-channel initialization value 15 15 read-write DCCOMPINIT Initialize filter state 30 1 read-write DCESTI No Description 0x0E8 read-only 0x00000000 0x3FFFFFFF DCCOMPESTIVALI I-channel DC-Offset Estimated value 0 15 read-only DCCOMPESTIVALQ Q-channel DC-Offset Estimated value 15 15 read-only SRCCHF No Description 0x0EC read-write 0x00000000 0xEFFFF8FF SRCRATIO1 I-channel SRC ratio 0 8 read-write SRCENABLE1 SRC1 enable 11 1 read-write SRCRATIO2 Q-channel SRC ratio 12 15 read-write SRCENABLE2 SRC2 enable 27 1 read-write BWSEL Channel filter bandwidth 29 2 read-write X0 wide bandwidth selected ; BW = 0.263*Fxtal/dec0-factor/dec1-factor 0 X1 wide bandwidth selected ; BW = 0.263*Fxtal/dec0-factor/dec1-factor 1 X2 narrow bandwidth selected ; BW = 0.196*Fxtal/dec0-factor/dec1-factor 2 X3 narrow bandwidth selected ; BW = 0.196*Fxtal/dec0-factor/dec1-factor 3 INTOSR Forcing Integer OSR 31 1 read-write DSATHD0 No Description 0x0F4 read-write 0x07830464 0xFFFFFFFF SPIKETHD Spike threshold 0 8 read-write UNMODTHD Unmodulated carrier detector threshold 8 6 read-write FDEVMINTHD Frequency deviation minimum threshold 14 6 read-write FDEVMAXTHD Frequency deviation maximum threshold 20 12 read-write DSATHD1 No Description 0x0F8 read-write 0x3AC81388 0x7FFFFFFF POWABSTHD Power absolute threshold 0 16 read-write POWRELTHD Relative power detector threshold 16 2 read-write DISABLED Threshold is 6dB. The relative power detector will trigger when the current RSSI is 6dB stronger than the previously detected RSSI. 0 MODE1 Threshold is 9dB. The relative power detector will trigger when the current RSSI is 9dB stronger than the previously detected RSSI. 1 MODE2 Threshold is 12dB. The relative power detector will trigger when the current RSSI is 12dB stronger than the previously detected RSSI. 2 MODE3 Threshold is 15dB. The relative power detector will trigger when the current RSSI is 15dB stronger than the previously detected RSSI. 3 DSARSTCNT DSA reset counter 18 3 read-write RSSIJMPTHD RSSI jump detector threshold 21 4 read-write FREQLATDLY Frequency late delay 25 2 read-write PWRFLTBYP Power filter bypass 27 1 read-write AMPFLTBYP Amplitude filter bypass 28 1 read-write PWRDETDIS Power detection disabled 29 1 read-write FREQSCALE Frequency scale factor 30 1 read-write DSACTRL No Description 0x0FC read-write 0x000A2090 0xFFEFFFFF DSAMODE Mode of Digital Signal Arrival detector 0 2 read-write DISABLED DSA is disabled 0 ENABLED DSA is enabled by the relative/absolute RSSI detector and is reset by using detectors for spike content and frequency deviation. The RSSI jump detector is used to recover from false detects. 1 ARRTHD Signal arrival valid counter threshold 2 4 read-write ARRTOLERTHD0 Arrival tolerance threshold 0 6 5 read-write ARRTOLERTHD1 Arrival tolerance threshold 1 11 5 read-write SCHPRD Search period window length 16 1 read-write TS2 The search period is 2 symbol periods. 0 TS4 The search period is 4 symbol periods. 1 FREQAVGSYM DSA frequency estimation averaging 17 1 read-write AVG2TS Frequency estimation over 2 symbol periods. 0 AVG4TS Frequency estimation over 4 symbol periods. 1 TRANRSTDSA power transient detector Reset DSA 18 1 read-write DSARSTON DSA detection reset 19 1 read-write GAINREDUCDLY Detection Delay of AGC gain reduction 21 2 read-write LOWDUTY Low duty cycle delay 23 3 read-write RESTORE Power detector reset of DSA 26 1 read-write AGCBAUDEN Consider Baud_en from AGC 27 1 read-write AMPJUPTHD Amplitude jump detection thrshold 28 4 read-write VITERBIDEMOD No Description 0x100 read-write 0x00206100 0xFFFFFFFF VTDEMODEN Viterbi demodulator enable 0 1 read-write HARDDECISION Hard decision 1 1 read-write VITERBIKSI1 VITERBI KSI1 2 7 read-write VITERBIKSI2 VITERBI KSI2 9 7 read-write VITERBIKSI3 VITERBI KSI3 16 6 read-write SYNTHAFC Synthesizer AFC in Viterbi demod 22 1 read-write CORRCYCLE Correction cycles 23 4 read-write CORRSTPSIZE Correction step size 27 4 read-write DISDEMODOF Disable Demod Over Flow Detection 31 1 read-write VTCORRCFG0 No Description 0x104 read-write 0x123556B7 0xFFFFFFFF EXPECTPATT Expected pattern 0 32 read-write DIGMIXCTRL No Description 0x10C read-write 0x00000000 0x007FFFFF DIGMIXFREQ Digital mixer frequency control word 0 20 read-write DIGMIXMODE Digital mixer frequency control 20 1 read-write CFOSR Mixer frequency specified by CFOSR. 0 DIGMIXFREQ Mixer frequency specified by DIGMIXFREQ. 1 MIXERCONJ Digital mixer input conjugate 21 1 read-write DIGMIXFB Digital mixer Frequency Correction 22 1 read-write VTCORRCFG1 No Description 0x110 read-write 0x29043020 0x7FFFFFFF CORRSHFTLEN Correlator shift length 0 6 read-write VTFRQLIM Viterbi frequency limiter 6 9 read-write EXPSYNCLEN Expected sync length 15 8 read-write BUFFHEAD Buffer header 23 4 read-write EXPECTHT Expected patterns head and tail 27 4 read-write VTTRACK No Description 0x114 read-write 0x4D80BB88 0xFFFFFFFF FREQTRACKMODE Frequency tracking mode 0 2 read-write DISABLED Frequency tracking disabled. Only a one-time frequency offset compensation applied through DSA. 0 MODE1 Frequency tracking enabled with one correction, when needed, every 16 symbol periods. 1 MODE2 Frequency tracking enabled with one correction, when needed, every 32 symbol periods. 2 MODE3 Frequency tracking enabled with one correction, when needed, every 48 symbol periods. 3 TIMTRACKTHD Timing tracking threshold 2 4 read-write TIMEACQUTHD Time acquisition threshold 6 8 read-write TIMCHK Time check 14 1 read-write TIMEOUTMODE Timeout mode 15 1 read-write TIMGEAR Timing Gear 16 2 read-write GEAR0 Execute timing tracking regardless of difference between Early/Late and Current correlation values. Referred to as fast gear. Same as GEAR3 0 GEAR1 Execute timing tracking only when correlation value of Early/Late is 75% or less of the Current correlation value. Referred to as medium gear. 1 GEAR2 Execute timing tracking only when correlation value of Early/Late is 50% or less of the Current correlation value. Referred to as slow gear. 2 FREQBIAS Frequency estimation bias 18 4 read-write HIPWRTHD High Power detection threshold 22 8 read-write SYNCTIMEOUTSEL SYNC-WORD DET TIMEOUT 30 2 read-write BREST No Description 0x118 read-only 0x00000000 0x000007FF BRESTINT Integer part of estimated baudrate 0 6 read-only BRESTNUM Fractional part of estimated baudrate 6 5 read-only AUTOCG No Description 0x124 read-write 0x00000000 0x0000FFFF AUTOCGEN Enable automatic clock gating 0 16 read-write CGCLKSTOP No Description 0x128 read-write 0x00000000 0x0000FFFF FORCEOFF Manual control clocks 0 16 read-write DSATHD2 No Description 0x130 read-write 0x0C660664 0x7FFFFEFF POWABSTHDLOG Power threshold in logarithm-scale 0 8 read-write JUMPDETEN Power jump detection enable 9 1 read-write FDADJTHD Frequency deviation ripple threshold 10 6 read-write PMDETPASSTHD DSA Preamble detection counter threshold 16 4 read-write FREQESTTHD Frequency Estimation Timeout Threshold 20 5 read-write INTERFERDET Interference detection threshold 25 5 read-write PMDETFORCE Force DSA preamble detector 30 1 read-write DIRECTMODE No Description 0x134 read-write 0x0000010C 0x00001F0F DMENABLE Enable Direct Mode 0 1 read-write SYNCASYNC Choose Synchronous or Asynchronous mode 1 1 read-write SYNCPREAM Synchronous mode preamble 2 2 read-write ADD0 No preamble bits appended 0 ADD8 8 preamble bits appended 1 ADD16 16 preamble bits appended 2 ADD32 32 preamble bits appended 3 CLKWIDTH Synchronous mode clock pulse width 8 5 read-write LONGRANGE No Description 0x138 read-write 0x00FA53E8 0x7FFFFFFF LRCORRTHD Correlator threshold 0 11 read-write LRCORRSCHWIN Window size 11 4 read-write LRBLE Enable 15 1 read-write LRTIMCORRTHD Correlator threshold 16 11 read-write LRBLEDSA DSA enable 27 1 read-write LRDEC DEC value 28 3 read-write LONGRANGE1 No Description 0x13C read-write 0x00000000 0x3FFF7FFF LRSS Long Range Signal Selection 0 4 read-write LRTIMEOUTTHD Long Range Time Out Threshold 4 11 read-write CHPWRACCUDEL Channel Power Accumulated Delay 16 2 read-write DEL0 Use accumulated channel power value 0 DEL32 Delayed by 32 chips 1 DEL64 Delayed by 64 chips 2 HYSVAL Hysteresis Value for BBSS 18 3 read-write AVGWIN Average window 21 3 read-write LRSPIKETHADD Long Range DSA spike threshold addition 24 4 read-write LOGICBASEDPUGATE Logic Based Phase Unwrap Gating 28 1 read-write LOGICBASEDLRDEMODGATE Logic Based Long Range Demod Gating 29 1 read-write LONGRANGE2 No Description 0x140 read-write 0x00000000 0xFFFFFFFF LRCHPWRTH1 Long Range channel power threshold 0 8 read-write LRCHPWRTH2 Long Range channel power threshold 8 8 read-write LRCHPWRTH3 Long Range channel power threshold 16 8 read-write LRCHPWRTH4 Long Range channel power threshold 24 8 read-write LONGRANGE3 No Description 0x144 read-write 0x00000000 0xFFFFFFFF LRCHPWRTH5 Long Range channel power threshold 0 8 read-write LRCHPWRTH6 Long Range channel power threshold 8 8 read-write LRCHPWRTH7 Long Range channel power threshold 16 8 read-write LRCHPWRTH8 Long Range channel power threshold 24 8 read-write LONGRANGE4 No Description 0x148 read-write 0x00000000 0xFFFFFFFF LRCHPWRTH9 Long Range channel power threshold 0 8 read-write LRCHPWRTH10 Long Range channel power threshold 8 8 read-write LRCHPWRSH1 Long Range channel power shift 16 4 read-write LRCHPWRSH2 Long Range channel power shift 20 4 read-write LRCHPWRSH3 Long Range channel power shift 24 4 read-write LRCHPWRSH4 Long Range channel power shift 28 4 read-write LONGRANGE5 No Description 0x14C read-write 0x00000000 0x0FFFFFFF LRCHPWRSH5 Long Range channel power shift 0 4 read-write LRCHPWRSH6 Long Range channel power shift 4 4 read-write LRCHPWRSH7 Long Range channel power shift 8 4 read-write LRCHPWRSH8 Long Range channel power shift 12 4 read-write LRCHPWRSH9 Long Range channel power shift 16 4 read-write LRCHPWRSH10 Long Range channel power shift 20 4 read-write LRCHPWRSH11 Long Range channel power shift 24 4 read-write LONGRANGE6 No Description 0x150 read-write 0x00000000 0xFFF7FFFF LRCHPWRSPIKETH Long Range channel power spike threshold 0 8 read-write LRSPIKETHD Long Range spike threshold 8 11 read-write LRCHPWRTH11 Long Range channel power threshold 20 8 read-write LRCHPWRSH12 Long Range channel power shift 28 4 read-write LRFRC No Description 0x154 read-write 0x00000101 0x000001FF CI500 Long Range CI mapping for 500kbps 0 2 read-write FRCACKTIMETHD FRC acknowledge timeout threshold 2 6 read-write LRCORRMODE LR Correlator operation Mode 8 1 read-write DSATHD3 No Description 0x168 read-write 0x07830464 0xFFFFFFFF SPIKETHDLO Spike threshold 0 8 read-write UNMODTHDLO Unmodulated carrier detector threshold 8 6 read-write FDEVMINTHDLO Frequency deviation minimum threshold 14 6 read-write FDEVMAXTHDLO Frequency deviation maximum threshold 20 12 read-write DSATHD4 No Description 0x16C read-write 0x00821388 0x07FFFFFF POWABSTHDLO Power absolute threshold for low power 0 16 read-write ARRTOLERTHD0LO Arrival tolerance threshold 0 16 5 read-write ARRTOLERTHD1LO Arrival tolerance threshold 1 21 5 read-write SWTHD Enable switch threshold for low power 26 1 read-write VTBLETIMING No Description 0x170 read-write 0x00000000 0x0000FFF3 VTBLETIMINGSEL Viterbi BLE timing stamp selection 0 2 read-write FRAMEDET_DELAY Delayed frame detection will be used as Timing stamp. This mode should be selected for legacy demod and Long Range BLE demod. 0 END_FRAME_PULSE The end of frame detection from Narrow Viterbi demod will be used as Timing stamp. This signal is a narrow pulse signal and pulse width is one xo clock cycle. 1 END_FRAME The end of frame detection from Narrow Viterbi demod will be used as Timing stamp. This signal is a wdie pulse signal 2 INV_END_FRAME For testing only. 3 TIMINGDELAY Viterbi BLE Delay timer 4 8 read-write FLENOFF Timing Stamp Frame Length Offset 12 4 read-write IF No Description 0x208 read-write 0x00000000 0x0007FFFF TXFRAMESENT Frame sent 0 1 read-write TXSYNCSENT Sync word sent 1 1 read-write TXPRESENT Preamble sent 2 1 read-write TXRAMPDONE Mod ramper idle 3 1 read-write LDTNOARR No signal Detected in LDT 4 1 read-write PHDSADET PHASE DSA DETECT 5 1 read-write PHYUNCODEDET CONCURRENT UNCODED PHY DET 6 1 read-write PHYCODEDET CONCURRENT CODED PHY DET 7 1 read-write RXTIMDET Timing detected 8 1 read-write RXPREDET Preamble detected 9 1 read-write RXFRAMEDET0 Frame with sync-word 0 detected 10 1 read-write RXFRAMEDET1 Frame with sync-word 1 detected 11 1 read-write RXTIMLOST Timing lost 12 1 read-write RXPRELOST Preamble lost 13 1 read-write RXFRAMEDETOF Frame detection overflow 14 1 read-write RXTIMNF Timing not found 15 1 read-write FRCTIMOUT DEMOD-FRC req/ack timeout 16 1 read-write ETS Early Time Stamp detect 17 1 read-write CFGANTPATTRD cfg 18 1 read-write IEN No Description 0x20C read-write 0x00000000 0x0007FFFF TXFRAMESENT Frame sent 0 1 read-write TXSYNCSENT Sync word sent 1 1 read-write TXPRESENT Preamble sent 2 1 read-write TXRAMPDONE Mod ramper idle 3 1 read-write LDTNOARR No signal Detected in LDT 4 1 read-write PHDSADET PHASE DSA DETECT 5 1 read-write PHYUNCODEDET CONCURRENT UNCODED PHY DET 6 1 read-write PHYCODEDET CONCURRENT CODED PHY DET 7 1 read-write RXTIMDET Timing detected 8 1 read-write RXPREDET Preamble detected 9 1 read-write RXFRAMEDET0 Frame with sync-word 0 detected 10 1 read-write RXFRAMEDET1 Frame with sync-word 1 detected 11 1 read-write RXTIMLOST Timing lost 12 1 read-write RXPRELOST Preamble lost 13 1 read-write RXFRAMEDETOF Frame detection overflow 14 1 read-write RXTIMNF Timing not found 15 1 read-write FRCTIMOUT DEMOD-FRC req/ack timeout 16 1 read-write ETS Early Time Stamp detect 17 1 read-write CFGANTPATTRD CFGANTPATTRD 18 1 read-write CMD No Description 0x218 write-only 0x00000000 0x00000039 PRESTOP Preamble stop 0 1 write-only AFCTXLOCK Lock AFC TX compensation 3 1 write-only AFCTXCLEAR Clear AFC TX compensation. 4 1 write-only AFCRXCLEAR Clear AFC RX compensation. 5 1 write-only FSMSTATUS No Description 0x21C read-only 0x00000000 0x00FFFFFF DETSTATE Detection FSM state 0 7 read-only OFF Off state 0 TIMINGSEARCH Timing search 10 PRESEARCH Preamble search 20 FRAMESEARCH Frame search 30 RXFRAME Payload Detection 40 FRAMEDETMODE0 Timing search with sliding window (FDM0) 50 DSASTATE Demodulator DSA FSM state 7 3 read-only IDLE IDLE state 0 ARRIVALCHK Arrival Check 1 STATUSCHK Status Check 2 SAMPPW SAMP_PW 3 WAITPWRUP WAIT_PWRUP 4 WAITDSALO WAIT_DSALO 5 WAITABORT WAIT_ABORT 6 STOP STOP 7 LRBLESTATE Demodulator long-range BLE FSM state 10 5 read-only IDLE IDLE state 0 CLEANUP CLEANUP 1 CORRCOE CORRCOE 2 WAITLRDSA WAIT_LR_DSA 3 MAXCORR MAXCORR 4 WAITRDY WAIT_RDY 5 FEC1DATA FEC1_DATA 6 FEC1ACK FEC1_ACK 7 PAUSE PAUSE 8 FEC2DATA FEC2_DATA 9 FEC2ACK FEC2_ACK 10 TRACKCUR TRACK_CUR 11 TRACKEAR TRACK_EAR 12 TRACKLAT TRACK_LAT 13 TRACKDONE TRACK_DONE 14 TDECISION T_DECISION 15 STOP STOP 16 NBBLESTATE Demodulator Narrow-band BLE FSM state 15 5 read-only IDLE IDLE state 0 VTINITI VTINITI 1 ADDRNXT ADDR_NXT 2 INICOST INI_COST 3 CALCCOST CALC_COST 4 INITALACQU INITAL_ACQU 5 INITALCOSTCALC INITAL_COST_CALC 6 MINCOSTCALC MIN_COST_CALC 7 FREQACQU FREQ_ACQU 8 FREQACQUDONE FREQ_ACQU_DONE 9 TIMINGACQUEARLY TIMING_ACQU_EARLY 10 TIMINGACQUCURR TIMING_ACQU_CURR 11 TIMINGACQULATE TIMING_ACQU_LATE 12 TIMINGACQUDONE TIMING_ACQU_DONE 13 VIRTBIINIT0 VIRTBI_INIT0 14 VIRTBIINIT1 VIRTBI_INIT1 15 VIRTBIRXSYNC VIRTBI_RXSYNC 16 VIRTBIRXPAYLOAD VIRTBI_RXPAYLOAD 17 HARDRXSYNC HARD_RXSYNC 18 HARDXPAYLOAD HARD_RXPAYLOAD 19 TRACKFREQ TRACK_FREQ 20 TRACKTIMEARLY TRACK_TIM_EARLY 21 TRACKTIMCURR TRACK_TIM_CURR 22 TRACKTIMLATE TRACK_TIM_LATE 23 TRACKDONE TRACK_DONE 24 TRACKDECISION TRACK_DECISION 25 STOP STOP 26 WAITACK WAIT_ACK 27 DEBUG DEBUG 28 ANTDIVSTATE Antenna diversity control state 20 4 read-only IDLE Idle state 0 FIRST_ANT0 First ANT0 selection 1 FIRST_ANT1 First ANT1 selection 2 TIMSEARCH_ANT0 Timing search on ANT0 3 TIMSEARCH_ANT1 Timing search on ANT1 4 TIMDET_ANT0 Check ANT1 after timing detecton ANT0 5 TIMDET_ANT1 Check ANT0 after timing detecton ANT1 6 EVALUATE Evaluate and select better antenna 7 TIMSEARCH_SELECTED Searching on better antenna 8 TIMDET_SELECTED Selected better antenna 9 REPEAT_ANT0 Repeat ANT0 10 REPEAT_ANT1 Repeat ANT1 11 MANUAL Manual mode 15 STATUS2 No Description 0x220 read-only 0x00000000 0xFFFCFFFF CHPWRACCUMUX Channel power 0 8 read-only BBSSMUX Actual Baseband Signal Selection 8 4 read-only LRBLECI RXed packet's LR BLE coding indicator 12 2 read-only LR125k FEC block 2 coded using C=8, 125kbps 0 LR500k FEC block 2 coded using C=2, 500kbps 1 UNCODEDPHY UNCODED PHY DET 14 1 read-only CODEDPHY CODED PHY DET 15 1 read-only RTVTCORR VT demod Correlation 18 14 read-only STATUS3 No Description 0x224 read-only 0x00000000 0x057FFFFF BBPFOUTABS1 Pre-filter Correlation Output 0 11 read-only BBPFOUTABS Pre-filter Correlation Output for BLR 11 11 read-only LRDSALIVE BLRDSA Prefilter above LRSPIKETHD 22 1 read-only LRDSADET DSA prefilter above LRSPIKETHD 24 1 read-only SYNCSECPEAKABTH SYNC second peak above threshold 26 1 read-only IRCAL No Description 0x228 read-write 0x00000000 0x0000FFBF IRCALEN IRCAL enable bit 0 1 read-write MURSHF MUR shift value 1 5 read-write MUISHF MUI shift value 7 6 read-write IRCORREN IR Correction enable bit 13 1 read-write IRCALCOEFRSTCMD IRCAL coef reset cmd 14 1 write-only IRCALIFADCDBG IRCAL IFADC DBG 15 1 read-write IRCALCOEF No Description 0x22C read-only 0x00000000 0x7FFF7FFF CRV CRV coefficient 0 15 read-only CIV CIV coefficient 16 15 read-only BLEIQDSA No Description 0x230 read-write 0x00000000 0xFFFFFFFF BLEIQDSAEN BLEIQDSA Enable 0 1 read-write BLEIQDSATH BLEIQDSA Threshold 1 14 read-write BLEIQDSAIIRCOEFPWR BLEIQDSA IIRCOEFPWR 15 3 read-write BLEIQDSADIFFTH1 BLEIQDSA BLEIQDSADIFFTH1 18 14 read-write BLEIQDSAEXT1 No Description 0x234 read-write 0x0E000000 0x3FFFFFFF FREQSCALEIQDSA I/Q DSA Frequency scale 0 2 read-write CHPWRFIRAVGEN Channel Power FIR Avg Enable 2 1 read-write CHPWRFIRAVGVAL Channel Power FIR Avg Value 3 2 read-write AVG0 No Avg 0 AVG2 2 sample avg 1 AVG4 4 sample avg 2 AVG8 8 sample avg 3 CORRIIRAVGMULFACT Corr IIR Avg Multiplication Factor 5 2 read-write BLEIQDSAADDRBIAS BLEIQDSA ADDRBIAS 7 4 read-write BLEIQDSATHCOMB Threshold when i and q are added 11 14 read-write MAXCORRCNTIQDSA Max Corr Cnt IQDSA 25 4 read-write IIRRST IIR Reset 29 1 read-write SYNCPROPERTIES No Description 0x238 read-write 0x00000000 0x000000FF SYNCCORRCLR Sync auto corr clear bit 0 1 read-write SYNCSECPEAKTH SYNC auto corr second peak threshold 1 7 read-write DIGIGAINCTRL No Description 0x23C read-write 0x00000000 0x000001FF DIGIGAINEN Digital Gain Enable 0 1 read-write DIGIGAINSEL Digital Gain Select 1 5 read-write GAINM3 GAINM3 0 GAINM2P75 GAINM2P75 1 GAINM2P5 GAINM2P5 2 GAINM2P25 GAINM2P25 3 GAINM2 GAINM2 4 GAINM1P75 GAINM1P75 5 GAINM1P5 GAINM1P5 6 GAINM1P25 GAINM1P25 7 GAINM1 GAINM1 8 GAINM0P75 GAINM0P75 9 GAINM0P5 GAINM0P5 10 GAINM0P25 GAINM0P25 11 GAINM0 GAINM0 12 GAINP0P25 GAINP0P25 13 GAINP0P5 GAINP0P5 14 GAINP0P75 GAINP0P75 15 GAINP1 GAINP1 16 GAINP1P25 GAINP1P25 17 GAINP1P5 GAINP1P5 18 GAINP1P75 GAINP1P75 19 GAINP2 GAINP2 20 GAINP2P25 GAINP2P25 21 GAINP2P5 GAINP2P5 22 GAINP2P75 GAINP2P75 23 GAINP3 GAINP3 24 DIGIGAINDOUBLE Digital Gain Doubled 6 1 read-write DIGIGAINHALF Digital Gain Halved 7 1 read-write DEC0GAIN DEC0 Gain Select 8 1 read-write PRSCTRL No Description 0x240 read-write 0x00000000 0x0003FFFF POSTPONESEL 0 2 read-write ADVANCESEL 2 2 read-write NEWWNDSEL 4 2 read-write WEAKSEL 6 2 read-write SYNCSENTSEL 8 2 read-write PRESENTSEL 10 2 read-write LOWCORRSEL 12 2 read-write ANT0SEL 14 2 read-write ANT1SEL 16 2 read-write REALTIMCFE No Description 0x248 read-write 0x001F81F4 0xE01FFFFF MINCOSTTHD Min. Cost thrshold 0 10 read-write RTSCHWIN Real time CFE searching window 10 4 read-write RTSCHMODE Real Time CFE searching mode 14 1 read-write TRACKINGWIN Correlator size for Tracking 15 3 read-write SYNCACQWIN SYNC Correlator Size 18 3 read-write SINEWEN Enable SINE WEIGHT 29 1 read-write VTAFCFRAME Viterbi AFC FRAME Mode 30 1 read-write RTCFEEN Trecs Enable 31 1 read-write SEQIF No Description 0x24C read-write 0x00000000 0x0007FFFF TXFRAMESENT Frame sent 0 1 read-write TXSYNCSENT Sync word sent 1 1 read-write TXPRESENT Preamble sent 2 1 read-write TXRAMPDONE Mod ramper idle 3 1 read-write LDTNOARR No signal Detected in LDT 4 1 read-write PHDSADET PHASE DSA DETECT 5 1 read-write PHYUNCODEDET CONCURRENT UNCODED PHY DET 6 1 read-write PHYCODEDET CONCURRENT CODED PHY DET 7 1 read-write RXTIMDET Timing detected 8 1 read-write RXPREDET Preamble detected 9 1 read-write RXFRAMEDET0 Frame with sync-word 0 detected 10 1 read-write RXFRAMEDET1 Frame with sync-word 1 detected 11 1 read-write RXTIMLOST Timing lost 12 1 read-write RXPRELOST Preamble lost 13 1 read-write RXFRAMEDETOF Frame detection overflow 14 1 read-write RXTIMNF Timing not found 15 1 read-write FRCTIMOUT DEMOD-FRC req/ack timeout 16 1 read-write ETS Early timestamp 17 1 read-write CFGANTPATTRD CFGANTPATTRD 18 1 read-write SEQIEN No Description 0x250 read-write 0x00000000 0x0007FFFF TXFRAMESENT Frame sent 0 1 read-write TXSYNCSENT Sync word sent 1 1 read-write TXPRESENT Preamble sent 2 1 read-write TXRAMPDONE Mod ramper idle 3 1 read-write LDTNOARR No signal Detected in LDT 4 1 read-write PHDSADET PHASE DSA DETECT 5 1 read-write PHYUNCODEDET CONCURRENT UNCODED PHY DET 6 1 read-write PHYCODEDET CONCURRENT CODED PHY DET 7 1 read-write RXTIMDET Timing detected 8 1 read-write RXPREDET Preamble detected 9 1 read-write RXFRAMEDET0 Frame with sync-word 0 detected 10 1 read-write RXFRAMEDET1 Frame with sync-word 1 detected 11 1 read-write RXTIMLOST Timing lost 12 1 read-write RXPRELOST Preamble lost 13 1 read-write RXFRAMEDETOF Frame detection overflow 14 1 read-write RXTIMNF Timing not found 15 1 read-write FRCTIMOUT DEMOD-FRC req/ack timeout 16 1 read-write ETS Early time stamp 17 1 read-write CFGANTPATTRD CFGANTPATTRD 18 1 read-write ETSCTRL No Description 0x254 read-write 0x00000000 0x3FFFF7FF ETSLOC Early Time Stamp Location 0 10 read-write CAPSIGONPRS Capture Signal On PRS 10 1 read-write CAPTRIG Trigger to capture 12 18 read-write ANTSWCTRL No Description 0x258 read-write 0x003C0000 0x01FFFFFF ANTDFLTSEL Ant Default Select 0 6 read-write ANTCOUNT Total Ant count 6 6 read-write ANTSWTYPE Ant Switch Type 12 2 read-write US_2 2us ant switching 0 US_4 4us ant switching 1 US_6 6us ant switching 2 US_8 8us ant switching 3 ANTSWRST Ant SW rst pulse 14 1 write-only CFGANTPATTEN Configure Ant Pattern Enable 15 1 read-write ANTSWENABLE Ant sw enable 16 1 read-write EXTDSTOPPULSECNT Extend Stop Pulse Counter 17 8 read-write ANTSWSTART No Description 0x25C read-write 0x00000000 0x0003FFFF ANTSWSTARTTIM Ant switch start time 0 18 read-write ANTSWEND No Description 0x260 read-write 0x00000000 0x0003FFFF ANTSWENDTIM Ant switch start time 0 18 read-write TRECPMPATT No Description 0x264 read-write 0x55555555 0xFFFFFFFF PMEXPECTPATT Expected PM pattern 0 32 read-write TRECPMDET No Description 0x268 read-write 0x00000017 0xBFFFC3FF PMACQUINGWIN PM Correlator Size 0 3 read-write PMCOSTVALTHD Min COST Validation for AFC 3 3 read-write PMTIMEOUTSEL PM searching timeout Threshold 6 2 read-write PHSCALE PHASE Scaler 8 2 read-write PMMINCOSTTHD Min. Cost thrshold for Trecs PM 14 9 read-write VTPMDETSEL Trecs PM Detection Thrshold 23 2 read-write COSTHYST PM Seaching COST HYST 25 5 read-write PREAMSCH PM detection enable in Trecs 31 1 read-write CFGANTPATT No Description 0x26C read-write 0x00000000 0x3FFFFFFF CFGANTPATTVAL CFGANTPATTVAL 0 30 read-write ETSTIM No Description 0x270 read-write 0x00000000 0x0003FFFF ETSTIMVAL ETSTIMVAL 0 17 read-write ETSCOUNTEREN ETSCOUNTEREN 17 1 read-write ANTSWCTRL1 No Description 0x274 read-write 0x0006AAAA 0x00FFFFFF TIMEPERIOD Time Period of xtal 0 24 read-write COCURRMODE No Description 0x278 read-write 0x00000000 0x80000000 CONCURRENT CONCURRENT MODE Enable 31 1 read-write ANTDIVCTRL No Description 0x27C read-write 0x00000000 0x000001FF ADPRETHRESH Preamble threshold 0 8 read-write ENADPRETHRESH Enable Preamble threshold 8 1 read-write DISABLE Disable use of Preamble threshold after timing detection 0 ENABLE Enable use of Preamble threshold after timing detection 1 BLEIQDSAEXT2 No Description 0x280 read-write 0x00000000 0x000007FF DISMAXPEAKTRACKMODE Disable Max Peak Track Mode 0 1 read-write BBSSDEBOUNCETIM BBSS Debounce Time 1 8 read-write BBSSDIFFCHVAL BBSS Diff Change Val 9 2 read-write GT0 Greater than 0 0 GT1 Greater than 1 1 GT2 Greater than 2 2 GT3 Greater than 3 3 SPARE No Description 0x284 read-write 0x00000000 0x000000FF SPARE Spare register 0 8 read-write IRCALCOEFWR0 No Description 0x288 read-write 0x00000000 0xFFFFFFFF CRVWD CRV coefficient 0 15 read-write CRVWEN CIV Coefficient Write Enable 15 1 read-write CIVWD CIV coefficient 16 15 read-write CIVWEN CIV Coefficient Write Enable 31 1 read-write IRCALCOEFWR1 No Description 0x28C read-write 0x00000000 0xFFFFFFFF CRVWD CRV coefficient 0 15 read-write CRVWEN CIV Coefficient Write Enable 15 1 read-write CIVWD CIV coefficient 16 15 read-write CIVWEN CIV Coefficient Write Enable 31 1 read-write SYNTH_NS 1 SYNTH_NS Registers 0xB8018000 0x00000000 0x00001000 registers SYNTH 42 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Enable peripheral clock to this module 0 1 read-write STATUS No Description 0x008 read-only 0x00000000 0x04014707 INLOCK RF Synthesizer in Lock 0 1 read-only IFFREQEN Synthesizer IF frequency enable status 1 1 read-only CMD No Description 0x00C write-only 0x00000000 0x0000061F SYNTHSTART Starts the RF synthesizer 0 1 write-only SYNTHSTOP Stops the RF synthesizer 1 1 write-only ENABLEIF Enable the synthesizer IF frequency 2 1 write-only DISABLEIF Disable the synthesizer IF frequency 3 1 write-only CAPCALSTART Start VCO capacitor array calibration 4 1 write-only CTRL No Description 0x010 read-write 0x00000003 0xD9770007 LOCKTHRESHOLD Frequency synthesizer lock threshold 0 3 read-write PRSMUX0 PRS output mux 0 selector 16 3 read-write DISABLED PRS output 0 is disabled 0 INLOCK Synthesizer is in lock 1 LOCK_WINDOW PLL Lock Window, sampled by PFD 2 FPLL Divided PLL clock 3 VCCMP_HI VCO voltage high detected 4 VCO_AMPLITUDE_OK Obsolete. Read returns 1. 5 VCO_DET_OUT_D Obsolete. Read returns 0. 6 PRSMUX1 PRS output mux 1 selector 20 3 read-write DISABLED PRS output 1 is disabled 0 AUXINLOCK Obsolete. read returns 0. 1 REF_IS_LEADING Disabled. Read returns 0. 2 FPLL Divided PLL clock 3 VCCMP_LOW VCO voltage low detected 4 MMD_PRESCALER_RESET_N MMD prescaler reset, active low 5 CLK_SYNTH_DIV2 MMD next denom output, corresponding to the delta-sigma clock, divided by 2. 6 INVCLKSYNTH Invert clk_synth 24 1 read-write NO Do not invert clk_synth 0 YES Invert clk_synth 1 MMDRSTNOVERRIDEEN Enable MMD reset override 30 1 read-write DISABLE Disable MMD reset override 0 ENABLE Enable MMD reset override 1 MMDMANRSTN Manual MMD reset 31 1 read-write RESET Reset MMD and DSM logic 0 NORESET Allow MMD and DSM to run 1 VCDACCTRL No Description 0x02C read-write 0x00000020 0x000001FF VCDACVAL Control voltage to VCO 0 6 read-write VCDACEN Enable VCDAC 6 1 read-write DISABLE VC DAC disabled 0 ENABLE VC DAC enabled 1 LPFEN LPF Enable Control 7 1 read-write DISABLE Disable LPF 0 ENABLE Enable LPF 1 LPFQSEN LPF Quickstart Control 8 1 read-write DISABLE Disable LPF 0 ENABLE Enable LPF 1 FREQ No Description 0x034 read-write 0x00000000 0x0FFFFFFF FREQ RF Carrier Frequency. 0 28 read-write IFFREQ No Description 0x038 read-write 0x00000000 0x001FFFFF IFFREQ IF used in receive mode 0 20 read-write LOSIDE Configure LO in receive 20 1 read-write LOW The local oscillator (LO) is lower in frequency than the receive RF channel. In MODEM_MIXCTRL the ANAMIXMODE field must be set to NORMAL and DIGIQSWAPEN must be cleared. 0 HIGH The local oscillator (LO) is higher in frequency than the receive RF channel. In MODEM_MIXCTRL the ANAMIXMODE field must be set to CONJUGATE and DIGIQSWAPEN must be set. 1 DIVCTRL No Description 0x03C read-write 0x00000001 0x000001FF LODIVFREQCTRL Frequency division 0 9 read-write LODIV1 Divide LO frequency by 1. 1 LODIV2 Divide LO frequency by 2. 2 LODIV3 Divide LO frequency by 3. 3 LODIV4 Divide LO frequency by 4. 4 LODIV5 Divide LO frequency by 5. 5 LODIV7 Divide LO frequency by 7. 7 LODIV6 Divide LO frequency by 6. 19 LODIV8 Divide LO frequency by 8. 20 LODIV10 Divide LO frequency by 10. 21 LODIV14 Divide LO frequency by 14. 23 LODIV9 Divide LO frequency by 9. 27 LODIV12 Divide LO frequency by 12. 28 LODIV15 Divide LO frequency by 15. 29 LODIV16 Divide LO frequency by 16. 36 LODIV20 Divide LO frequency by 20. 37 LODIV18 Divide LO frequency by 18. 155 LODIV24 Divide LO frequency by 24. 156 CHCTRL No Description 0x040 read-write 0x00000000 0x0000003F CHNO Channel number 0 6 read-write CHSP No Description 0x044 read-write 0x00000000 0x0003FFFF CHSP Channel spacing 0 18 read-write CALOFFSET No Description 0x048 read-write 0x00000000 0x00007FFF CALOFFSET Carrier calibration offset 0 15 read-write VCOTUNING No Description 0x04C read-write 0x00008400 0x0000FFFF VCOTUNING VCO capacitor array calibration value. 0 11 read-write VCAPSEL VCO varactor cap select 11 5 read-write VCOGAIN No Description 0x058 read-write 0x00000077 0x000000FF VCOKVCOARSE VCO varactor coarse gain setting 0 4 read-write VCOKVFINE VCO varactor fine gain setting 4 4 read-write IF No Description 0x078 read-write 0x00000000 0x00000237 LOCKED Synthesizer locked Interrupt Flag 0 1 read-write UNLOCKED Synthesizer unlocked Interrupt Flag 1 1 read-write SYRDY Synthesizer ready Interrupt Flag 2 1 read-write VCOHIGH VCO high voltage Interrupt Flag 4 1 read-write VCOLOW VCO low voltage Interrupt Flag 5 1 read-write LOCNTDONE LOCNT measurement done Interrupt Flag 9 1 read-write IEN No Description 0x084 read-write 0x00000000 0x00000237 LOCKED LOCKED Interrupt Enable 0 1 read-write UNLOCKED UNLOCKED Interrupt Enable 1 1 read-write SYRDY CAPCALDONE Interrupt Enable 2 1 read-write VCOHIGH VCOHIGH Interrupt Enable 4 1 read-write VCOLOW VCOLOW Interrupt Enable 5 1 read-write LOCNTDONE LOCNTDONE Interrupt Enable 9 1 read-write LOCNTCTRL No Description 0x088 read-write 0x00000000 0x00000FFF ENABLE Enable LO Counter 0 1 read-write OFF LO counter is disabled 0 ON LO counter is enabled 1 CLEAR Clear LO Counter 1 1 write-only OFF Do not clear LO counter 0 ON Clear LO counter 1 RUN Run LO Counter 2 1 write-only OFF Do not run LO counter 0 ON Run LO counter 1 READ Read LO Counter 3 1 read-write OFF LOCOUNT register read returns all 0's 0 ON LOCOUNT register read returns count value 1 NUMCYCLE Number of Clock Cycles to Run LO Counter 4 4 read-write CNT_2 Set count length to 2 XO clock cycles 0 CNT_4 Set count length to 4 XO clock cycles 1 CNT_8 Set count length to 8 XO clock cycles 2 CNT_16 Set count length to 16 XO clock cycles 3 CNT_32 Set count length to 32 XO clock cycles 4 CNT_64 Set count length to 64 XO clock cycles 5 CNT_128 Set count length to 128 XO clock cycles 6 CNT_256 Set count length to 256 XO clock cycles 7 CNT_512 Set count length to 512 XO clock cycles 8 CNT_1024 Set count length to 1024 XO clock cycles 9 CNT_2048 Set count length to 2048 XO clock cycles 10 CNT_4096 Set count length to 4096 XO clock cycles 11 CNT_8192 Set count length to 8192 XO clock cycles 12 LOCNTOVERRIDEEN Enable manual override of CLEAR and RUN 8 1 read-write DISABLE Disable manual override 0 ENABLE Enable manual override 1 LOCNTMANCLEAR Manual Control of LO counter CLEAR 9 1 read-write NOCLEAR Don't clear LO counter 0 CLEAR Clear LO counter 1 LOCNTMANRUN Manual Control of the LO counter RUN 10 1 read-write NORUN Don't initiate start/stop LO counter 0 RUN Initiate start/stop of LO counter 1 FCALRUNCLKEN Enable FCAL run pulse counter clock 11 1 read-write DISABLE Don't enable clock 0 ENABLE Enable clock 1 LOCNTSTATUS No Description 0x08C read-only 0x00000000 0x000FFFFF LOCOUNT LO Counter Value 0 19 read-only BUSY LO Counter is Busy 19 1 read-only LOCNTTARGET No Description 0x090 read-only 0x00000000 0x0007FFFF TARGET LO Counter Measurement Target 0 19 read-only MMDDENOMINIT No Description 0x094 read-write 0x00000000 0x07FFFFFF DENOMINIT0 New BitField 0 9 read-write DENOMINIT1 New BitField 9 9 read-write DENOMINIT2 New BitField 18 9 read-write CHPDACINIT No Description 0x098 read-write 0x00000000 0x00000FFF DACINIT Initial CHP DAC Value 0 12 read-write LPFCTRL1CAL No Description 0x09C read-write 0x00000000 0x0003FFFF OP1BWCAL LPF Op1 BW Control in Cal Mode 0 4 read-write OP1COMPCAL LPF Op1 Comp Control in Cal Mode 4 4 read-write RFBVALCAL LPF Rfb Value Select in Cal Mode 8 3 read-write RPVALCAL LPF Rp Value Select in Cal Mode 11 3 read-write RZVALCAL LPF Rz Value Select in Cal Mode 14 4 read-write LPFCTRL1RX No Description 0x0A0 read-write 0x00000000 0x0003FFFF OP1BWRX LPF Op1 BW Control in RX Mode 0 4 read-write OP1COMPRX LPF Op1 Comp Control in RX Mode 4 4 read-write RFBVALRX LPF Rfb Value Select in RX Mode 8 3 read-write RPVALRX LPF Rp Value Select in RX Mode 11 3 read-write RZVALRX LPF Rz Value Select in RX Mode 14 4 read-write LPFCTRL1TX No Description 0x0A4 read-write 0x00000000 0x0003FFFF OP1BWTX LPF Op1 BW Control in TX Mode 0 4 read-write OP1COMPTX LPF Op1 Comp Control in TX Mode 4 4 read-write RFBVALTX LPF Rfb Value Select in TX Mode 8 3 read-write RPVALTX LPF Rp Value Select in TX Mode 11 3 read-write RZVALTX LPF Rz Value Select in TX Mode 14 4 read-write LPFCTRL2RX No Description 0x0A8 read-write 0x00000000 0x1FFFFFFF LPFSWENRX LPF Switching Enable in RX Mode 0 1 read-write DISABLE Disable switching 0 ENABLE Enable switching 1 LPFINCAPRX LPF Input Cap Select in RX Mode 1 2 read-write LPFGNDSWENRX LPF Gnd Switch Enable in RX Mode 3 1 read-write DISABLE Disable GND switching 0 ENABLE Enable GND switching 1 CALCRX LPF Cap Cal Select in RX Mode 4 5 read-write CASELRX LPF Ca Select in RX Mode 9 1 read-write DISABLE Disable Ca 0 ENABLE Enable Ca 1 CAVALRX LPF Ca Value Select in RX Mode 10 5 read-write CFBSELRX LPF Cfb Select in RX Mode 15 1 read-write DISABLE Disable Cfb 0 ENABLE Enable Cfb 1 CZSELRX LPF Cz Select in RX Mode 16 1 read-write DISABLE Disable Cz 0 ENABLE Enable Cz 1 CZVALRX LPF Cz Value Select in RX Mode 17 8 read-write MODESELRX LPF Filter Mode Select in RX Mode 25 1 read-write ONEOP Sets 1 opamp configuration 0 TWOOP Sets 2 opamp configuration 1 VCMLVLRX LPF Vcm Level Select in RX Mode 26 3 read-write LPFCTRL2TX No Description 0x0AC read-write 0x00000000 0x1FFFFFFF LPFSWENTX LPF Switching Enable in TX Mode 0 1 read-write DISABLE Disable switching 0 ENABLE Enable switching 1 LPFINCAPTX LPF Input Cap Select in TX Mode 1 2 read-write LPFGNDSWENTX LPF Gnd Switch Enable in TX Mode 3 1 read-write DISABLE Disable GND switching 0 ENABLE Enable GND switching 1 CALCTX LPF Cap Cal Select in TX Mode 4 5 read-write CASELTX LPF Ca Select in TX Mode 9 1 read-write DISABLE Disable Ca 0 ENABLE Enable Ca 1 CAVALTX LPF Ca Value Select in TX Mode 10 5 read-write CFBSELTX LPF Cfb Select in TX Mode 15 1 read-write DISABLE Disable Cfb 0 ENABLE Enable Cfb 1 CZSELTX LPF Cz Select in TX Mode 16 1 read-write DISABLE Disable Cz 0 ENABLE Enable Cz 1 CZVALTX LPF Cz Value Select in TX Mode 17 8 read-write MODESELTX LPF Filter Mode Select in TX Mode 25 1 read-write ONEOP 1 opamp configuration 0 TWOOP 2 opamp configuration 1 VCMLVLTX LPF Vcm Level Select in TX Mode 26 3 read-write DSMCTRLRX No Description 0x0B0 read-write 0x00000013 0x070003FF DITHERDSMINPUTRX Dithering of DSM input for RX mode 0 1 read-write DITHERDSMOUTPUTRX Dithering of DSM output for RX mode 1 3 read-write DITHERDACRX Dithering of charge pump DAC for RX mode 4 4 read-write DSMMODERX Delta-sigma topology for RX mode 8 1 read-write FEEDFORWARD Feed forward architecture 0 MASH MASH architecture. Note that the delta-sigma output dithering (DITHERDSMOUTPUT) is not available in this mode. 1 LSBFORCERX Delta-sigma input force LSB for RX mode 9 1 read-write DEMMODERX DEM Mode for RX mode 24 1 read-write DISABLED DEM is disabled 0 ENABLED DEM is enabled 1 MASHORDERRX MASH order for RX mode 25 1 read-write SECOND 2nd Order Mash 0 THIRD 3rd Order Mash 1 REQORDERRX ReQuant order for RX mode 26 1 read-write FIRST 1st Order DAC 0 SECOND 2rd Order DAC 1 DSMCTRLTX No Description 0x0B4 read-write 0x00000013 0x070003FF DITHERDSMINPUTTX Dithering of DSM input for TX mode 0 1 read-write DITHERDSMOUTPUTTX Dithering of DSM output for TX mode 1 3 read-write DITHERDACTX Dithering of charge pump DAC for TX mode 4 4 read-write DSMMODETX Delta-sigma topology for TX mode 8 1 read-write FEEDFORWARD Feed forward architecture 0 MASH MASH architecture. Note that the delta-sigma output dithering (DITHERDSMOUTPUT) is not available in this mode. 1 LSBFORCETX Delta-sigma input force LSB for TX mode 9 1 read-write DEMMODETX DEM Mode for TX mode 24 1 read-write DISABLED DEM is disabled 0 ENABLED DEM is enabled 1 MASHORDERTX MASH order for TX mode 25 1 read-write SECOND 2nd Order Mash 0 THIRD 3rd Order Mash 1 REQORDERTX ReQuant order for TX mode 26 1 read-write FIRST 1st Order DAC 0 SECOND 2rd Order DAC 1 SEQIF No Description 0x0B8 read-write 0x00000000 0x00000237 LOCKED Synthesizer locked Interrupt Flag 0 1 read-write UNLOCKED Synthesizer unlocked Interrupt Flag 1 1 read-write SYRDY Synthesizer ready Interrupt Flag 2 1 read-write VCOHIGH VCO high voltage Interrupt Flag 4 1 read-write VCOLOW VCO low voltage Interrupt Flag 5 1 read-write LOCNTDONE LOCNT measurement done Interrupt Flag 9 1 read-write SEQIEN No Description 0x0BC read-write 0x00000000 0x00000237 LOCKED LOCKED Interrupt Enable 0 1 read-write UNLOCKED UNLOCKED Interrupt Enable 1 1 read-write SYRDY CAPCALDONE Interrupt Enable 2 1 read-write VCOHIGH VCOHIGH Interrupt Enable 4 1 read-write VCOLOW VCOLOW Interrupt Enable 5 1 read-write LOCNTDONE LOCNTDONE Interrupt Enable 9 1 read-write PROTIMER_NS 1 PROTIMER_NS Registers 0xB801C000 0x00000000 0x00001000 registers PROTIMER 36 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IPVERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN EN 0 1 read-write CTRL No Description 0x008 read-write 0x00000000 0x3FF33336 DEBUGRUN Debug Mode Run Enable 1 1 read-write X0 PROTIMER is frozen in debug mode 0 X1 PROTIMER is running in debug mode 1 DMACLRACT DMA Request Clear on Active 2 1 read-write OSMEN One-Shot Mode Enable 4 1 read-write X0 Protimer continues to count when WRAP counter overflows. 0 X1 Protimer stops counting when WRAP counter overflows. 1 ZEROSTARTEN Start from zero enable 5 1 read-write X0 Protimer starts from the previous count value 0 X1 Protimer starts counting from zero 1 PRECNTSRC Selects clock to Pre-counter 8 2 read-write DISABLED Disable Pre-counter 0 CLOCK Module clock 1 UNUSED0 Do not use 2 UNUSED1 Do not use 3 BASECNTSRC Selects clock to Base counter 12 2 read-write DISABLED Disable base counter 0 PRECNTOF Pre-counter overflow events 1 UNUSED0 Do not use 2 UNUSED1 Do not use 3 WRAPCNTSRC Selects clock to Wrap counter 16 2 read-write DISABLED Disable Wrap counter 0 PRECNTOF Pre-counter overflow events 1 BASECNTOF Base counter overflow events 2 UNUSED Do not use 3 TOUT0SRC Selects clock to timeout counter 0 20 2 read-write DISABLED No counting 0 PRECNTOF Pre-counter overflow events 1 BASECNTOF Base counter overflow events 2 WRAPCNTOF Wrap counter overflow events 3 TOUT0SYNCSRC Select timeout counter 0 event 22 2 read-write DISABLED No synchronization 0 PRECNTOF Pre-counter overflow event 1 BASECNTOF Base counter overflow event 2 WRAPCNTOF Wrap counter overflow event 3 TOUT1SRC Selects clock to timeout counter 1 24 2 read-write DISABLED No counting 0 PRECNTOF Pre-counter overflow events 1 BASECNTOF Base counter overflow events 2 WRAPCNTOF Wrap counter overflow events 3 TOUT1SYNCSRC Select timeout counter 1 event 26 2 read-write DISABLED No synchronization 0 PRECNTOF Pre-counter overflow event 1 BASECNTOF Base counter overflow event 2 WRAPCNTOF Wrap counter overflow event 3 TOUT0MODE Repeat Mode 28 1 read-write FREE When started, the TOUT0 counts down until it is stopped by software 0 ONESHOT TOUT0 is stopped after it reaches zero 1 TOUT1MODE Repeat Mode 29 1 read-write FREE When started, the TOUT1 counts down until it is stopped by software 0 ONESHOT TOUT1 is stopped after it reaches zero 1 CMD No Description 0x00C write-only 0x00000000 0x000707F7 START Start PROTIMER 0 1 write-only RTCSYNCSTART Start PROTIMER Synchronized with RTCC 1 1 write-only STOP Stop PROTIMER 2 1 write-only TOUT0START Start Timeout counter 0 4 1 write-only TOUT0STOP Stop Timeout counter 0 5 1 write-only TOUT1START Start Timeout counter 1 6 1 write-only TOUT1STOP Stop Timeout counter 0 7 1 write-only FORCETXIDLE Force to Idle state of tx_state 8 1 write-only FORCERXIDLE Force to Idle state of rx_state 9 1 write-only FORCERXRX Force to Rx state of rx_state 10 1 write-only LBTSTART LBT sequence start 16 1 write-only LBTPAUSE Pause LBT sequence 17 1 write-only LBTSTOP LBT sequence stop 18 1 write-only PRSCTRL No Description 0x010 read-write 0x00000000 0x000E0E0E STARTPRSEN Enable Protimer start commands from PRS. 1 1 read-write STARTEDGE Start Command Edge Select 2 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 STOPPRSEN Enable Protimer stop commands from PRS. 9 1 read-write STOPEDGE Stop Command Edge Select 10 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 RTCCTRIGGERPRSEN Enable RTCC Trigger from PRS. 17 1 read-write RTCCTRIGGEREDGE RTCC Trigger Edge Select 18 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 STATUS No Description 0x014 read-only 0x00000000 0x0000FFFF RUNNING Running 0 1 read-only LBTSYNC LBT Synchronizing 1 1 read-only LBTRUNNING LBT Running 2 1 read-only LBTPAUSED LBT has been paused. 3 1 read-only TOUT0RUNNING Timeout Counter 0 Running 4 1 read-only TOUT0SYNC Timeout Counter 0 Synchronizing 5 1 read-only TOUT1RUNNING Timeout Counter 1 Running 6 1 read-only TOUT1SYNC Timeout Counter 1 Synchronizing 7 1 read-only ICV0 CC0 Capture Valid 8 1 read-only X0 PROTIMER_CC0_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC0_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV1 CC1 Capture Valid 9 1 read-only X0 PROTIMER_CC1_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC1_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV2 CC2 Capture Valid 10 1 read-only X0 PROTIMER_CC2_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC2_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV3 CC3 Capture Valid 11 1 read-only X0 PROTIMER_CC3_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC3_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV4 CC4 Capture Valid 12 1 read-only X0 PROTIMER_CC4_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC4_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV5 CC5 Capture Valid 13 1 read-only ICV6 CC6 Capture Valid 14 1 read-only ICV7 CC7 Capture Valid 15 1 read-only PRECNT No Description 0x018 read-write 0x00000000 0x0000FFFF PRECNT Pre Counter Value 0 16 read-write BASECNT No Description 0x01C read-write 0x00000000 0x0000FFFF BASECNT Base Counter Value 0 16 read-write WRAPCNT No Description 0x020 read-write 0x00000000 0xFFFFFFFF WRAPCNT Wrap Counter Value 0 32 read-write BASEPRE No Description 0x024 read-only 0x00000000 0xFFFFFFFF PRECNTV Pre counter value 0 16 read-only BASECNTV Base counter value 16 16 read-only LWRAPCNT No Description 0x028 read-only 0x00000000 0xFFFFFFFF LWRAPCNT Latched Wrap Counter Value 0 32 read-only PRECNTTOPADJ No Description 0x02C read-write 0x00000000 0x0000FFFF PRECNTTOPADJ PRECNT Top Adjust Value 0 16 read-write PRECNTTOP No Description 0x030 read-write 0x00FFFF00 0x00FFFFFF PRECNTTOPFRAC PRECNT Top Fractional Value 0 8 read-write PRECNTTOP PRECNT Top Value 8 16 read-write BASECNTTOP No Description 0x034 read-write 0x0000FFFF 0x0000FFFF BASECNTTOP BASECNT Top Value 0 16 read-write WRAPCNTTOP No Description 0x038 read-write 0xFFFFFFFF 0xFFFFFFFF WRAPCNTTOP WRAPCNT Top Value 0 32 read-write TOUT0CNT No Description 0x03C read-write 0x00000000 0xFFFFFFFF TOUT0PCNT TOUT0PCNT Value 0 16 read-write TOUT0CNT TOUT0CNT Value 16 16 read-write TOUT0CNTTOP No Description 0x040 read-write 0x00FF00FF 0xFFFFFFFF TOUT0PCNTTOP TOUT0PCNTTOP Value 0 16 read-write TOUT0CNTTOP TOUT0CNTTOP Value 16 16 read-write TOUT0COMP No Description 0x044 read-write 0x00000000 0xFFFFFFFF TOUT0PCNTCOMP TOUT0PCNTCOMP 0 16 read-write TOUT0CNTCOMP TOUT0CNTCOMP Value 16 16 read-write TOUT1CNT No Description 0x048 read-write 0x00000000 0xFFFFFFFF TOUT1PCNT TOUT1PCNT Value 0 16 read-write TOUT1CNT TOUT1CNT Value 16 16 read-write TOUT1CNTTOP No Description 0x04C read-write 0x00FF00FF 0xFFFFFFFF TOUT1PCNTTOP TOUT1PCNTTOP Value 0 16 read-write TOUT1CNTTOP TOUT1CNTTOP Value 16 16 read-write TOUT1COMP No Description 0x050 read-write 0x00000000 0xFFFFFFFF TOUT1PCNTCOMP TOUT1PCNTCOMP 0 16 read-write TOUT1CNTCOMP TOUT1CNTCOMP Value 16 16 read-write LBTCTRL No Description 0x054 read-write 0x00000000 0x0F1F1FFF STARTEXP Start Exponent 0 4 read-write EXP0 STARTEXP value = 0 (used for Fast TX) 0 EXP1 STARTEXP value = 1 1 EXP2 STARTEXP value = 2 2 EXP3 STARTEXP value = 3 3 EXP4 STARTEXP value = 4 4 EXP5 STARTEXP value = 5 5 EXP6 STARTEXP value = 6 6 EXP7 STARTEXP value = 7 7 EXP8 STARTEXP value = 8 8 MAXEXP Maximum Exponent 4 4 read-write EXP0 MAXEXP value = 0 0 EXP1 MAXEXP value = 1 1 EXP2 MAXEXP value = 2 2 EXP3 MAXEXP value = 3 3 EXP4 MAXEXP value = 4 4 EXP5 MAXEXP value = 5 5 EXP6 MAXEXP value = 6 6 EXP7 MAXEXP value = 7 7 EXP8 MAXEXP value = 8 8 CCADELAY Clear Channel Assessment Delay 8 5 read-write CCAREPEAT Clear Channel Assessment Repeat 16 4 read-write FIXEDBACKOFF Fixed backoff 20 1 read-write RETRYLIMIT Retry Limit 24 4 read-write LBTPRSCTRL No Description 0x058 read-write 0x00000000 0x01010100 LBTSTARTPRSEN Enable LBT start commands from PRS. 8 1 read-write LBTPAUSEPRSEN Enable LBT pause commands from PRS. 16 1 read-write LBTSTOPPRSEN Enable LBT stop commands from PRS. 24 1 read-write LBTSTATE No Description 0x05C read-write 0x00000000 0xFFFFFFFF TOUT0PCNT TOUT0PCNT value to be saved 0 16 read-write TOUT0CNT TOUT0CNT value to be saved 16 16 read-write RANDOM No Description 0x060 read-write 0x00000000 0x0000FFFF RANDOM Pseudo Random Value 0 16 read-write IF No Description 0x064 read-write 0x00000000 0x3FFFFFF7 PRECNTOF PRECNT Overflow Interrupt Flag 0 1 read-write BASECNTOF BASECNT Overflow Interrupt Flag 1 1 read-write WRAPCNTOF WRAPCNT Overflow Interrupt Flag 2 1 read-write TOUT0 TOUT0 underflow interrupt flag 4 1 read-write TOUT1 TOUT1 underflow interrupt flag 5 1 read-write TOUT0MATCH TOUT0 compare match interrupt flag 6 1 read-write TOUT1MATCH TOUT1 compare match interrupt flag 7 1 read-write CC0 CC Channel 0 Interrupt Flag 8 1 read-write CC1 CC Channel 1 Interrupt Flag 9 1 read-write CC2 CC Channel 2 Interrupt Flag 10 1 read-write CC3 CC Channel 3 Interrupt Flag 11 1 read-write CC4 CC Channel 4 Interrupt Flag 12 1 read-write CC5 CC Channel 5 Interrupt Flag 13 1 read-write CC6 CC Channel 6 Interrupt Flag 14 1 read-write CC7 CC Channel 7 Interrupt Flag 15 1 read-write COF0 CC Channel 0 Overflow Interrupt Flag 16 1 read-write COF1 CC Channel 1 Overflow Interrupt Flag 17 1 read-write COF2 CC Channel 2 Overflow Interrupt Flag 18 1 read-write COF3 CC Channel 3 Overflow Interrupt Flag 19 1 read-write COF4 CC Channel 4 Overflow Interrupt Flag 20 1 read-write COF5 CC Channel 5 Overflow Interrupt Flag 21 1 read-write COF6 CC Channel 6 Overflow Interrupt Flag 22 1 read-write COF7 CC Channel 7 Overflow Interrupt Flag 23 1 read-write LBTSUCCESS Listen Before Talk Success 24 1 read-write LBTFAILURE Listen Before Talk Failure 25 1 read-write LBTPAUSED Listen Before Talk Paused 26 1 read-write LBTRETRY Listen Before Talk Retry 27 1 read-write RTCCSYNCHED PROTIMER synchronized with the RTCC 28 1 read-write TOUT0MATCHLBT TOUT0 compare match interrupt flag 29 1 read-write IEN No Description 0x070 read-write 0x00000000 0x3FFFFFF7 PRECNTOF PRECNTOF Interrupt Enable 0 1 read-write BASECNTOF BASECNTOF Interrupt Enable 1 1 read-write WRAPCNTOF WRAPCNTOF Interrupt Enable 2 1 read-write TOUT0 TOUT0 Interrupt Enable 4 1 read-write TOUT1 TOUT1 Interrupt Enable 5 1 read-write TOUT0MATCH TOUT0MATCH Interrupt Enable 6 1 read-write TOUT1MATCH TOUT1MATCH Interrupt Enable 7 1 read-write CC0 CC0 Interrupt Enable 8 1 read-write CC1 CC1 Interrupt Enable 9 1 read-write CC2 CC2 Interrupt Enable 10 1 read-write CC3 CC3 Interrupt Enable 11 1 read-write CC4 CC4 Interrupt Enable 12 1 read-write CC5 CC5 Interrupt Enable 13 1 read-write CC6 CC6 Interrupt Enable 14 1 read-write CC7 CC7 Interrupt Enable 15 1 read-write COF0 COF0 Interrupt Enable 16 1 read-write COF1 COF1 Interrupt Enable 17 1 read-write COF2 COF2 Interrupt Enable 18 1 read-write COF3 COF3 Interrupt Enable 19 1 read-write COF4 COF4 Interrupt Enable 20 1 read-write COF5 COF5 Interrupt Enable 21 1 read-write COF6 COF6 Interrupt Enable 22 1 read-write COF7 COF7 Interrupt Enable 23 1 read-write LBTSUCCESS LBTSUCCESS Interrupt Enable 24 1 read-write LBTFAILURE LBTFAILURE Interrupt Enable 25 1 read-write LBTPAUSED LBTPAUSED Interrupt Enable 26 1 read-write LBTRETRY LBTRETRY Interrupt Enable 27 1 read-write RTCCSYNCHED RTCCSYNCHED Interrupt Enable 28 1 read-write TOUT0MATCHLBT TOUT0MATCHLBT Interrupt Enable 29 1 read-write RXCTRL No Description 0x074 read-write 0x00000000 0x1F1F1F1F RXSETEVENT1 First event that sets RX req signal 0 5 read-write DISABLED Request is never set 0 ALWAYS Does not wait for any particular event 1 PRECNTOF Pre counter overflow 2 BASECNTOF Base counter overflow 3 WRAPCNTOF Wrap counter overflow 4 TOUT0UF Timeout counter 0 underflow 5 TOUT1UF Timeout counter 1 underflow 6 TOUT0MATCH Timeout counter 0 match 7 TOUT1MATCH Timeout counter 1 match 8 CC0 Channel 0 Capture/Compare event 9 CC1 Channel 1 Capture/Compare event 10 CC2 Channel 2 Capture/Compare event 11 CC3 Channel 3 Capture/Compare event 12 CC4 Channel 4 Capture/Compare event 13 TXDONE MOD indicated that TX completed 14 RXDONE FRC indicated that RX completed 15 TXORRXDONE MOD/FRC indicated that TX or RX completed 16 FDET0 DEMOD indicated that syncword 0 was detected 17 FDET1 DEMOD indicated that syncword 1 was detected 18 FDET0OR1 DEMOD indicated that syncword 0 or 1 was detected 19 LBTSUCCESS LBT completed successfully 20 LBTRETRY LBT detected occupied channel and will try again 21 LBTFAILURE LBT could not start transmission 22 ANYLBT Any LBT event 23 CCAACK A CCA measurement completed 24 CCA A CCA measurement completed, and channel was clear 25 NOTCCA A CCA measurement completed, and channel was busy 26 TOUT0MATCHLBT Timeout counter 0 match occurred during LBT operation 27 RXSETEVENT2 Second event that sets RX req signal 8 5 read-write RXCLREVENT1 First event that clears RX req signal 16 5 read-write RXCLREVENT2 Second event that clears RX req signal 24 5 read-write TXCTRL No Description 0x078 read-write 0x00000000 0x00001F1F TXSETEVENT1 First event that sets TX req signal 0 5 read-write DISABLED Request is never set 0 ALWAYS Does not wait for any particular event 1 PRECNTOF Pre counter overflow 2 BASECNTOF Base counter overflow 3 WRAPCNTOF Wrap counter overflow 4 TOUT0UF Timeout counter 0 underflow 5 TOUT1UF Timeout counter 1 underflow 6 TOUT0MATCH Timeout counter 0 match 7 TOUT1MATCH Timeout counter 1 match 8 CC0 Channel 0 Capture/Compare event 9 CC1 Channel 1 Capture/Compare event 10 CC2 Channel 2 Capture/Compare event 11 CC3 Channel 3 Capture/Compare event 12 CC4 Channel 4 Capture/Compare event 13 TXDONE MOD indicated that TX completed 14 RXDONE FRC indicated that RX completed 15 TXORRXDONE MOD/FRC indicated that TX or RX completed 16 FDET0 DEMOD indicated that syncword 0 was detected 17 FDET1 DEMOD indicated that syncword 1 was detected 18 FDET0OR1 DEMOD indicated that syncword 0 or 1 was detected 19 LBTSUCCESS LBT completed successfully 20 LBTRETRY LBT detected occupied channel and will try again 21 LBTFAILURE LBT could not start transmission 22 ANYLBT Any LBT event 23 CCAACK A CCA measurement completed 24 CCA A CCA measurement completed, and channel was clear 25 NOTCCA A CCA measurement completed, and channel was busy 26 TOUT0MATCHLBT Timeout counter 0 match occurred during LBT operation 27 TXSETEVENT2 Second event that sets TX req signal 8 5 read-write ETSI No Description 0x07C read-write 0x00000000 0x03FFFFFF ETSIEN ETSI LBT enabling 0 1 read-write GRANULARLESSTHANRXWARM Granular less than RXWARM 1 1 read-write RXWARMTHLD Minimum backoff period for RXWARM 2 8 read-write CCAFIXED Fixed listening time 10 16 read-write LBTSTATE1 No Description 0x080 read-write 0x00000000 0x00000FFF CCACNT Current CCA counter value 0 4 read-write EXP LBT Exponent 4 4 read-write RETRYCNT LBT Retry counter 8 4 read-write RANDOMFW0 No Description 0x084 read-write 0x00000000 0x07FFFFFF RANDOM0 Linear random backoff period from FW 0 9 read-write RANDOM1 Linear random backoff period from FW 9 9 read-write RANDOM2 Linear random backoff period from FW 18 9 read-write RANDOMFW1 No Description 0x088 read-write 0x00000000 0x07FFFFFF RANDOM3 Linear random backoff period from FW 0 9 read-write RANDOM4 Linear random backoff period from FW 9 9 read-write RANDOM5 Linear random backoff period from FW 18 9 read-write RANDOMFW2 No Description 0x08C read-write 0x00000000 0x0003FFFF RANDOM6 Linear random backoff period from FW 0 9 read-write RANDOM7 Linear random backoff period from FW 9 9 read-write SEQIF No Description 0x090 read-write 0x00000000 0x3FFFFFF7 PRECNTOF PRECNT Overflow Interrupt Flag 0 1 read-write BASECNTOF BASECNT Overflow Interrupt Flag 1 1 read-write WRAPCNTOF WRAPCNT Overflow Interrupt Flag 2 1 read-write TOUT0 TOUT0 underflow interrupt flag 4 1 read-write TOUT1 TOUT1 underflow interrupt flag 5 1 read-write TOUT0MATCH TOUT0 compare match interrupt flag 6 1 read-write TOUT1MATCH TOUT1 compare match interrupt flag 7 1 read-write CC0 CC Channel 0 Interrupt Flag 8 1 read-write CC1 CC Channel 1 Interrupt Flag 9 1 read-write CC2 CC Channel 2 Interrupt Flag 10 1 read-write CC3 CC Channel 3 Interrupt Flag 11 1 read-write CC4 CC Channel 4 Interrupt Flag 12 1 read-write CC5 CC Channel 5 Interrupt Flag 13 1 read-write CC6 CC Channel 6 Interrupt Flag 14 1 read-write CC7 CC Channel 7 Interrupt Flag 15 1 read-write COF0 CC Channel 0 Overflow Interrupt Flag 16 1 read-write COF1 CC Channel 1 Overflow Interrupt Flag 17 1 read-write COF2 CC Channel 2 Overflow Interrupt Flag 18 1 read-write COF3 CC Channel 3 Overflow Interrupt Flag 19 1 read-write COF4 CC Channel 4 Overflow Interrupt Flag 20 1 read-write COF5 CC Channel 5 Overflow Interrupt Flag 21 1 read-write COF6 CC Channel 6 Overflow Interrupt Flag 22 1 read-write COF7 CC Channel 7 Overflow Interrupt Flag 23 1 read-write LBTSUCCESS Listen Before Talk Success 24 1 read-write LBTFAILURE Listen Before Talk Failure 25 1 read-write LBTPAUSED Listen Before Talk Paused 26 1 read-write LBTRETRY Listen Before Talk Retry 27 1 read-write RTCCSYNCHED PROTIMER synchronized with the RTCC 28 1 read-write TOUT0MATCHLBT TOUT0 compare match interrupt flag 29 1 read-write SEQIEN No Description 0x094 read-write 0x00000000 0x3FFFFFF7 PRECNTOF PRECNTOF Interrupt Enable 0 1 read-write BASECNTOF BASECNTOF Interrupt Enable 1 1 read-write WRAPCNTOF WRAPCNTOF Interrupt Enable 2 1 read-write TOUT0 TOUT0 Interrupt Enable 4 1 read-write TOUT1 TOUT1 Interrupt Enable 5 1 read-write TOUT0MATCH TOUT0MATCH Interrupt Enable 6 1 read-write TOUT1MATCH TOUT1MATCH Interrupt Enable 7 1 read-write CC0 CC0 Interrupt Enable 8 1 read-write CC1 CC1 Interrupt Enable 9 1 read-write CC2 CC2 Interrupt Enable 10 1 read-write CC3 CC3 Interrupt Enable 11 1 read-write CC4 CC4 Interrupt Enable 12 1 read-write CC5 CC5 Interrupt Enable 13 1 read-write CC6 CC6 Interrupt Enable 14 1 read-write CC7 CC7 Interrupt Enable 15 1 read-write COF0 COF0 Interrupt Enable 16 1 read-write COF1 COF1 Interrupt Enable 17 1 read-write COF2 COF2 Interrupt Enable 18 1 read-write COF3 COF3 Interrupt Enable 19 1 read-write COF4 COF4 Interrupt Enable 20 1 read-write COF5 COF5 Interrupt Enable 21 1 read-write COF6 COF6 Interrupt Enable 22 1 read-write COF7 COF7 Interrupt Enable 23 1 read-write LBTSUCCESS LBTSUCCESS Interrupt Enable 24 1 read-write LBTFAILURE LBTFAILURE Interrupt Enable 25 1 read-write LBTPAUSED LBTPAUSED Interrupt Enable 26 1 read-write LBTRETRY LBTRETRY Interrupt Enable 27 1 read-write RTCCSYNCHED RTCCSYNCHED Interrupt Enable 28 1 read-write TOUT0MATCHLBT TOUT0MATCHLBT Interrupt Enable 29 1 read-write CC0_CTRL No Description 0x100 read-write 0x00000000 0x07E07F7F ENABLE Channel Enable 0 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 PREMATCHEN Enable PRECNT matching 2 1 read-write BASEMATCHEN Enable BASECNT matching 3 1 read-write WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 PRORTC1 PRORTC capture/compare 1 10 ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 CC0_PRE No Description 0x104 read-write 0x00000000 0x0000FFFF PRE CC Channel PRE Value 0 16 read-write CC0_BASE No Description 0x108 read-write 0x00000000 0x0000FFFF BASE CC Channel BASE Value 0 16 read-write CC0_WRAP No Description 0x10C read-write 0x00000000 0xFFFFFFFF WRAP CC Channel WRAP Value 0 32 read-write CC1_CTRL No Description 0x110 read-write 0x00000000 0x07E07F7F ENABLE Channel Enable 0 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 PREMATCHEN Enable PRECNT matching 2 1 read-write BASEMATCHEN Enable BASECNT matching 3 1 read-write WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 PRORTC1 PRORTC capture/compare 1 10 ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 CC1_PRE No Description 0x114 read-write 0x00000000 0x0000FFFF PRE CC Channel PRE Value 0 16 read-write CC1_BASE No Description 0x118 read-write 0x00000000 0x0000FFFF BASE CC Channel BASE Value 0 16 read-write CC1_WRAP No Description 0x11C read-write 0x00000000 0xFFFFFFFF WRAP CC Channel WRAP Value 0 32 read-write CC2_CTRL No Description 0x120 read-write 0x00000000 0x07E07F7F ENABLE Channel Enable 0 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 PREMATCHEN Enable PRECNT matching 2 1 read-write BASEMATCHEN Enable BASECNT matching 3 1 read-write WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 PRORTC1 PRORTC capture/compare 1 10 ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 CC2_PRE No Description 0x124 read-write 0x00000000 0x0000FFFF PRE CC Channel PRE Value 0 16 read-write CC2_BASE No Description 0x128 read-write 0x00000000 0x0000FFFF BASE CC Channel BASE Value 0 16 read-write CC2_WRAP No Description 0x12C read-write 0x00000000 0xFFFFFFFF WRAP CC Channel WRAP Value 0 32 read-write CC3_CTRL No Description 0x130 read-write 0x00000000 0x07E07F7F ENABLE Channel Enable 0 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 PREMATCHEN Enable PRECNT matching 2 1 read-write BASEMATCHEN Enable BASECNT matching 3 1 read-write WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 PRORTC1 PRORTC capture/compare 1 10 ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 CC3_PRE No Description 0x134 read-write 0x00000000 0x0000FFFF PRE CC Channel PRE Value 0 16 read-write CC3_BASE No Description 0x138 read-write 0x00000000 0x0000FFFF BASE CC Channel BASE Value 0 16 read-write CC3_WRAP No Description 0x13C read-write 0x00000000 0xFFFFFFFF WRAP CC Channel WRAP Value 0 32 read-write CC4_CTRL No Description 0x140 read-write 0x00000000 0x07E07F7F ENABLE Channel Enable 0 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 PREMATCHEN Enable PRECNT matching 2 1 read-write BASEMATCHEN Enable BASECNT matching 3 1 read-write WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 PRORTC1 PRORTC capture/compare 1 10 ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 CC4_PRE No Description 0x144 read-write 0x00000000 0x0000FFFF PRE CC Channel PRE Value 0 16 read-write CC4_BASE No Description 0x148 read-write 0x00000000 0x0000FFFF BASE CC Channel BASE Value 0 16 read-write CC4_WRAP No Description 0x14C read-write 0x00000000 0xFFFFFFFF WRAP CC Channel WRAP Value 0 32 read-write CC5_CTRL No Description 0x150 read-write 0x00000000 0x07E07F7F ENABLE Channel Enable 0 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 PREMATCHEN Enable PRECNT matching 2 1 read-write BASEMATCHEN Enable BASECNT matching 3 1 read-write WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 PRORTC1 PRORTC capture/compare 1 10 ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 CC5_PRE No Description 0x154 read-write 0x00000000 0x0000FFFF PRE CC Channel PRE Value 0 16 read-write CC5_BASE No Description 0x158 read-write 0x00000000 0x0000FFFF BASE CC Channel BASE Value 0 16 read-write CC5_WRAP No Description 0x15C read-write 0x00000000 0xFFFFFFFF WRAP CC Channel WRAP Value 0 32 read-write CC6_CTRL No Description 0x160 read-write 0x00000000 0x07E07F7F ENABLE Channel Enable 0 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 PREMATCHEN Enable PRECNT matching 2 1 read-write BASEMATCHEN Enable BASECNT matching 3 1 read-write WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 PRORTC1 PRORTC capture/compare 1 10 ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 CC6_PRE No Description 0x164 read-write 0x00000000 0x0000FFFF PRE CC Channel PRE Value 0 16 read-write CC6_BASE No Description 0x168 read-write 0x00000000 0x0000FFFF BASE CC Channel BASE Value 0 16 read-write CC6_WRAP No Description 0x16C read-write 0x00000000 0xFFFFFFFF WRAP CC Channel WRAP Value 0 32 read-write CC7_CTRL No Description 0x170 read-write 0x00000000 0x07E07F7F ENABLE Channel Enable 0 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 PREMATCHEN Enable PRECNT matching 2 1 read-write BASEMATCHEN Enable BASECNT matching 3 1 read-write WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 PRORTC1 PRORTC capture/compare 1 10 ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 CC7_PRE No Description 0x174 read-write 0x00000000 0x0000FFFF PRE CC Channel PRE Value 0 16 read-write CC7_BASE No Description 0x178 read-write 0x00000000 0x0000FFFF BASE CC Channel BASE Value 0 16 read-write CC7_WRAP No Description 0x17C read-write 0x00000000 0xFFFFFFFF WRAP CC Channel WRAP Value 0 32 read-write RAC_NS 1 RAC_NS Registers 0xB8020000 0x00000000 0x00001000 registers RAC_RSM 37 RAC_SEQ 38 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Enable peripheral clock to this module 0 1 read-write RXENSRCEN No Description 0x008 read-write 0x00000000 0x00003FFF SWRXEN SW RX Enable 0 8 read-write CHANNELBUSYEN Channel Busy Enable 8 1 read-write TIMDETEN Timing Detected Enable 9 1 read-write PREDETEN Preamble Detected Enable 10 1 read-write FRAMEDETEN Frame Detected Enable 11 1 read-write DEMODRXREQEN DEMOD RX Request Enable 12 1 read-write PRSRXEN PRS RX Enable 13 1 read-write STATUS No Description 0x00C read-only 0x00000000 0xFFF8FFFF RXMASK Receive Enable Mask 0 16 read-only FORCESTATEACTIVE FSM state force active 19 1 read-only X0 No special state transition is currently in progress 0 X1 A forced state transition is currently in progress 1 TXAFTERFRAMEPEND TX After Frame Pending 20 1 read-only X0 A transmit after frame operation is currently not pending. 0 X1 A transmit after frame operation is currently pending. 1 TXAFTERFRAMEACTIVE TX After Frame Active 21 1 read-only X0 The currently ongoing TX was not initiated by a TXAFTERFRAME command. 0 X1 The currently ongoing TX was initiated by a TXAFTERFRAME command. 1 SEQSLEEPING SEQ in sleeping 22 1 read-only SEQSLEEPDEEP SEQ in deep sleep 23 1 read-only STATE Radio State 24 4 read-only OFF Radio is off 0 RXWARM Radio is enabling receiver 1 RXSEARCH Radio is listening for incoming frames 2 RXFRAME Radio is receiving a frame 3 RXPD Radio is powering down receiver and going to OFF state 4 RX2RX Radio remains in receive mode after frame reception is completed 5 RXOVERFLOW Received data was lost due to full receive buffer 6 RX2TX Radio is disabling receiver and enabling transmitter 7 TXWARM Radio is enabling transmitter 8 TX Radio is transmitting data 9 TXPD Radio is powering down transmitter and going to OFF state 10 TX2RX Radio is disabling transmitter and enabling reception 11 TX2TX Radio is preparing for a transmission after the previous transmission was ended 12 SHUTDOWN Radio is powering down receiver and going to OFF state 13 POR Radio power-on-reset state 14 SEQACTIVE SEQ active 28 1 read-only TXENS TXEN Status 30 1 read-only X0 TXEN is not set. 0 X1 TXEN is set. 1 RXENS RXEN Status 31 1 read-only X0 RXEN is not set. 0 X1 RXEN is set. 1 CMD No Description 0x010 write-only 0x00000000 0xC000FDFF TXEN Transmitter Enable 0 1 write-only FORCETX Force TX Command 1 1 write-only TXONCCA Transmit On CCA 2 1 write-only CLEARTXEN Clear TX Enable 3 1 write-only TXAFTERFRAME TX After Frame 4 1 write-only TXDIS TX Disable 5 1 write-only CLEARRXOVERFLOW Clear RX Overflow 6 1 write-only RXCAL Start an RX Calibration 7 1 write-only RXDIS RX Disable 8 1 write-only FRCWR FRC write cmd 10 1 write-only FRCRD FRC read cmd 11 1 write-only PAENSET PAEN Set 12 1 write-only PAENCLEAR PAEN Clear 13 1 write-only LNAENSET LNAEN Set 14 1 write-only LNAENCLEAR LNAEN Clear 15 1 write-only CTRL No Description 0x014 read-write 0x00000000 0x1F0107EF FORCEDISABLE Force Radio Disable 0 1 read-write PRSTXEN PRS TX Enable 1 1 read-write TXAFTERRX TX After RX 2 1 read-write X0 TX will not be started automatically. 0 X1 A transition to TX is automatically started when a received frame is accepted by the FRC. 1 PRSMODE PRS RXEN Mode 3 1 read-write DIRECT The PRS signal is used directly 0 PULSE The PRS signal is used as an RX enable pulse 1 PRSCLR PRS RXEN Clear 5 1 read-write RXSEARCH The PRS RXEN signal is cleared when the RSM state enters RXSEARCH 0 PRSCH The Selected PRS channel in PRSCLRSEL is used as a disable pulse 1 TXPOSTPONE TX Postpone 6 1 read-write X0 In the TX state transmit data is output. 0 X1 In the TX state an unmodulated carrier is output until this bit is cleared. 1 ACTIVEPOL ACTIVE signal polarity 7 1 read-write X0 Active low 0 X1 Active high 1 PAENPOL PAEN signal polarity 8 1 read-write X0 Active low 0 X1 Active high 1 LNAENPOL LNAEN signal polarity 9 1 read-write X0 Active low 0 X1 Active high 1 PRSRXDIS PRS RX Disable 10 1 read-write X0 PRS will not disable RX 0 X1 The channel selected by PRSRXDISSEL will generate a disable RX pulse 1 PRSFORCETX PRS Force RX 16 1 read-write X0 PRS will not force TX 0 X1 The channel selected by PRSFORCETXSEL will generate a force TX pulse 1 SEQRESET SEQ reset 24 1 write-only EXITSHUTDOWNDIS Exit SHUTDOWN state Disable 25 1 read-write CPUWAITDIS SEQ CPU Wait Disable 26 1 read-write SEQCLKDIS SEQ Clk Disable 27 1 read-write RXOFDIS Switch to RXOVERFLOW Disable 28 1 read-write FORCESTATE No Description 0x018 read-write 0x00000000 0x0000000F FORCESTATE Force RAC state transition 0 4 read-write IF No Description 0x01C read-write 0x00000000 0x00FF000F STATECHANGE Radio State Change 0 1 read-write STIMCMPEV STIMER Compare Event 1 1 read-write SEQLOCKUP SEQ locked up 2 1 read-write SEQRESETREQ SEQ reset request 3 1 read-write SEQ Sequencer Interrupt Flags 16 8 read-write IEN No Description 0x020 read-write 0x00000000 0x00FF000F STATECHANGE Radio State Change Interrupt Enable 0 1 read-write STIMCMPEV STIMER Compare Event Interrupt Enable 1 1 read-write SEQLOCKUP SEQ locked up Interrupt Enable 2 1 read-write SEQRESETREQ SEQ reset request Interrupt Enable 3 1 read-write SEQ Sequencer Flags Interrupt Enable 16 8 read-write TESTCTRL No Description 0x024 read-write 0x00000000 0x00000003 MODEN Modulator enable 0 1 read-write DEMODEN Demodulator enable 1 1 read-write SEQIF No Description 0x028 read-write 0x00000000 0x3FFF000F STATECHANGESEQ Radio State Change 0 1 read-write STIMCMPEVSEQ STIMER Compare Event 1 1 read-write DEMODRXREQCLRSEQ Demod RX request clear 2 1 read-write PRSEVENTSEQ SEQ PRS Event 3 1 read-write STATEOFF entering STATE_OFF 16 1 read-write STATERXWARM entering STATE_RXWARM 17 1 read-write STATERXSEARCH entering STATE_RXSEARCH 18 1 read-write STATERXFRAME entering STATE_RXFRAME 19 1 read-write STATERXPD entering STATE_RXPD 20 1 read-write STATERX2RX entering STATE_RX2RX 21 1 read-write STATERXOVERFLOW entering STATE_RXOVERFLOW 22 1 read-write STATERX2TX entering STATE_RX2TX 23 1 read-write STATETXWARM entering STATE_TXWARM 24 1 read-write STATETX entering STATE_TX 25 1 read-write STATETXPD entering STATE_TXPD 26 1 read-write STATETX2RX entering STATE_TX2RX 27 1 read-write STATETX2TX entering STATE_TX2TX 28 1 read-write STATESHUTDOWN entering STATE_SHUTDOWN 29 1 read-write SEQIEN No Description 0x02C read-write 0x00000000 0x3FFF000F STATECHANGESEQ Radio State Change Interrupt Enable 0 1 read-write STIMCMPEVSEQ STIMER Compare Event Interrupt Enable 1 1 read-write DEMODRXREQCLRSEQ Demod RX req clr Interrupt Enable 2 1 read-write PRSEVENTSEQ PRS SEQ EVENT Interrupt Enable 3 1 read-write STATEOFF STATE_OFF Interrupt Enable 16 1 read-write STATERXWARM STATE_RXWARM Interrupt Enable 17 1 read-write STATERXSEARCH STATE_RXSEARC Interrupt Enable 18 1 read-write STATERXFRAME STATE_RXFRAME Interrupt Enable 19 1 read-write STATERXPD STATE_RXPD Interrupt Enable 20 1 read-write STATERX2RX STATE_RX2RX Interrupt Enable 21 1 read-write STATERXOVERFLOW STATE_RXOVERFLOW Interrupt Enable 22 1 read-write STATERX2TX STATE_RX2TX Interrupt Enable 23 1 read-write STATETXWARM STATE_TXWARM Interrupt Enable 24 1 read-write STATETX STATE_TX Interrupt Enable 25 1 read-write STATETXPD STATE_TXPD Interrupt Enable 26 1 read-write STATETX2RX STATE_TX2RX Interrupt Enable 27 1 read-write STATETX2TX STATE_TX2TX Interrupt Enable 28 1 read-write STATESHUTDOWN STATE_SHUTDOWN Interrupt Enable 29 1 read-write STIMER No Description 0x030 read-only 0x00000000 0x0000FFFF STIMER STIMER Register 0 16 read-only STIMERCOMP No Description 0x034 read-write 0x00000000 0x0000FFFF STIMERCOMP STIMER Compare Register 0 16 read-write SEQCTRL No Description 0x038 read-write 0x00000000 0x1F00007F COMPACT STIMER Compare Action 0 1 read-write WRAP STIMER wraps when reaching STIMERCOMP 0 CONTINUE STIMER continues when reaching STIMERCOMP 1 COMPINVALMODE STIMER Comp Invalid Mode 1 2 read-write NEVER STIMERCOMP is always valid 0 STATECHANGE STIMERCOMP is invalidated when the RSM changes state 1 COMPEVENT STIMERCOMP is invalidated when an STIMER compare event occurs 2 STATECOMP STIMERCOMP is invalidated both when the RSM changes state and when a compare event occurs 3 RELATIVE STIMER Compare value relative 3 1 read-write Absolute The compare value set for stimer is an absolute value. 0 Relative The compare value set for stimer is a relative value. It takes the amount of time you set to make compare event happens. 1 STIMERALWAYSRUN STIMER always Run 4 1 read-write STIMERDEBUGRUN STIMER Debug Run 5 1 read-write X0 STIMER is not running when the Sequencer is halted. 0 X1 STIMER is running when the Sequencer is halted. 1 STATEDEBUGRUN FSM state Debug Run 6 1 read-write X0 FSM keeps unchanged when the Sequencer is halted 0 X1 FSM keeps going when the Sequencer is halted 1 SWIRQ SW spare IRQ 24 5 read-write PRESC No Description 0x03C read-write 0x00000007 0x0000007F STIMER STIMER Prescaler 0 7 read-write SR0 No Description 0x040 read-write 0x00000000 0xFFFFFFFF SR0 Sequencer Storage Register 0 0 32 read-write SR1 No Description 0x044 read-write 0x00000000 0xFFFFFFFF SR1 Sequencer Storage Register 1 0 32 read-write SR2 No Description 0x048 read-write 0x00000000 0xFFFFFFFF SR2 Sequencer Storage Register 2 0 32 read-write SR3 No Description 0x04C read-write 0x00000000 0xFFFFFFFF SR3 Sequencer Storage Register 3 0 32 read-write STCTRL No Description 0x050 read-write 0x00000000 0x01FFFFFF STCAL Systick timer freq cal 0 24 read-write STSKEW Systick timer skew 24 1 read-write FRCTXWORD No Description 0x054 read-write 0x00000000 0x000000FF WDATA FRC write data 0 8 read-write FRCRXWORD No Description 0x058 read-only 0x00000000 0x000000FF RDATA FRC read data 0 8 read-only EM1PCSR No Description 0x05C read-write 0x00000000 0x00070033 RADIOEM1PMODE 0 1 read-write HWCTRL Hardware Controls EM1P Request Signal 0 SWCTRL Software Controls EM1P Request Signal 1 RADIOEM1PDISSWREQ 1 1 read-write MCUEM1PMODE 4 1 read-write HWCTRL Hardware Controls EM1P Request Signal. 0 SWCTRL Software Controls EM1P Request Signal 1 MCUEM1PDISSWREQ 5 1 read-write RADIOEM1PREQ 16 1 read-only RADIOEM1PACK 17 1 read-only RADIOEM1PHWREQ 18 1 read-only SYNTHENCTRL No Description 0x094 read-write 0x00000000 0x00100282 VCOSTARTUP SYVCOFASTSTARTUP 1 1 read-write fast_start_up_0 0 fast_start_up_1 1 VCBUFEN SYLPFVCBUFEN 7 1 read-write Disabled 0 Enabled 1 LPFBWSEL LPF bandwidth register selection 20 1 read-write LPFBWRX Select LPFBWRX 0 LPFBWTX Select LPFBWTX 1 SYNTHREGCTRL No Description 0x098 read-write 0x04000000 0x07001C00 MMDLDOVREFTRIM SYTRIMMMDREGVREF 10 3 read-write vref0p6000 0 vref0p6125 1 vref0p6250 2 vref0p6375 3 vref0p6500 4 vref0p6625 5 vref0p6750 6 vref0p6875 7 CHPLDOVREFTRIM SYTRIMCHPREGVREF 24 3 read-write vref0p6000 0 vref0p6125 1 vref0p6250 2 vref0p6375 3 vref0p6500 4 vref0p6625 5 vref0p6750 6 vref0p6875 7 VCOCTRL No Description 0x09C read-write 0x0000004C 0x000000FF VCOAMPLITUDE SYVCOAMPLOPEN 0 4 read-write VCODETAMPLITUDE SYVCOAMPLPKD 4 4 read-write SYNTHCTRL No Description 0x0A4 read-write 0x00000000 0x00000400 MMDPOWERBALANCEDISABLE SYMMDPOWERBALANCEENB 10 1 read-write EnablePowerbleed 0 DisablePowerBleed 1 STATUS2 No Description 0x0AC read-only 0x00000000 0x0000FFFF PREVSTATE1 Previous Radio State 0 4 read-only OFF Radio is off 0 RXWARM Radio is enabling receiver 1 RXSEARCH Radio is listening for incoming frames 2 RXFRAME Radio is receiving a frame 3 RXPD Radio is powering down receiver and going to OFF state 4 RX2RX Radio remains in receive mode after frame reception is completed 5 RXOVERFLOW Received data was lost due to full receive buffer 6 RX2TX Radio is disabling receiver and enabling transmitter 7 TXWARM Radio is enabling transmitter 8 TX Radio is transmitting data 9 TXPD Radio is powering down transmitter and going to OFF state 10 TX2RX Radio is disabling transmitter and enabling reception 11 TX2TX Radio is preparing for a transmission after the previous transmission was ended 12 SHUTDOWN Radio is powering down receiver and going to OFF state 13 POR Radio power-on-reset state 14 PREVSTATE2 Previous Radio State 2 4 4 read-only OFF Radio is off 0 RXWARM Radio is enabling receiver 1 RXSEARCH Radio is listening for incoming frames 2 RXFRAME Radio is receiving a frame 3 RXPD Radio is powering down receiver and going to OFF state 4 RX2RX Radio remains in receive mode after frame reception is completed 5 RXOVERFLOW Received data was lost due to full receive buffer 6 RX2TX Radio is disabling receiver and enabling transmitter 7 TXWARM Radio is enabling transmitter 8 TX Radio is transmitting data 9 TXPD Radio is powering down transmitter and going to OFF state 10 TX2RX Radio is disabling transmitter and enabling reception 11 TX2TX Radio is preparing for a transmission after the previous transmission was ended 12 SHUTDOWN Radio is powering down receiver and going to OFF state 13 POR Radio power-on-reset state 14 PREVSTATE3 Previous Radio State 3 8 4 read-only OFF Radio is off 0 RXWARM Radio is enabling receiver 1 RXSEARCH Radio is listening for incoming frames 2 RXFRAME Radio is receiving a frame 3 RXPD Radio is powering down receiver and going to OFF state 4 RX2RX Radio remains in receive mode after frame reception is completed 5 RXOVERFLOW Received data was lost due to full receive buffer 6 RX2TX Radio is disabling receiver and enabling transmitter 7 TXWARM Radio is enabling transmitter 8 TX Radio is transmitting data 9 TXPD Radio is powering down transmitter and going to OFF state 10 TX2RX Radio is disabling transmitter and enabling reception 11 TX2TX Radio is preparing for a transmission after the previous transmission was ended 12 SHUTDOWN Radio is powering down receiver and going to OFF state 13 POR Radio power-on-reset state 14 CURRSTATE Current Radio State 12 4 read-only OFF Radio is off 0 RXWARM Radio is enabling receiver 1 RXSEARCH Radio is listening for incoming frames 2 RXFRAME Radio is receiving a frame 3 RXPD Radio is powering down receiver and going to OFF state 4 RX2RX Radio remains in receive mode after frame reception is completed 5 RXOVERFLOW Received data was lost due to full receive buffer 6 RX2TX Radio is disabling receiver and enabling transmitter 7 TXWARM Radio is enabling transmitter 8 TX Radio is transmitting data 9 TXPD Radio is powering down transmitter and going to OFF state 10 TX2RX Radio is disabling transmitter and enabling reception 11 TX2TX Radio is preparing for a transmission after the previous transmission was ended 12 SHUTDOWN Radio is powering down receiver and going to OFF state 13 POR Radio power-on-reset state 14 IFPGACTRL No Description 0x0B0 read-write 0x00000000 0x0FF80000 DCCALON Enable/Disable DCCAL in DEMOD 19 1 read-write DISABLE DC ESTI DISABLED 0 ENABLE DC ESTI ENABLED 1 DCRSTEN DC Compensation Filter Reset Enable 20 1 read-write DISABLE DC Comp out of Reset 0 ENABLE DC Comp in Reset 1 DCESTIEN DCESTIEN Override for RAC 21 1 read-write DISABLE DCESTI Disabled in MODEM 0 ENABLE DCESTI Enabled in MODEM 1 DCCALDEC0 DEC0 Value for DCCAL 22 3 read-write DF3 Decimation Factor 0 = 3. Cutoff 0.050 * f<subscript>HFXO</subscript>. 0 DF4WIDE Decimation Factor 0 = 4. Cutoff 0.069 * f<subscript>HFXO</subscript>. 1 DF4NARROW Decimation Factor 0 = 4. Cutoff 0.037 * f<subscript>HFXO</subscript>. 2 DF8WIDE Decimation Factor 0 = 8. Cutoff 0.012 * f<subscript>HFXO</subscript>. 3 DF8NARROW Decimation Factor 0 = 8. Cutoff 0.005 * f<subscript>HFXO</subscript>. 4 DCCALDCGEAR DC COMP GEAR Value for DCCAL 25 3 read-write PAENCTRL No Description 0x0B4 read-write 0x00000000 0x10010100 PARAMP PA output level ramping 8 1 read-write INVRAMPCLK Invert PA ramping clock 16 1 read-write PARAMPMODE PA ramp mode 28 1 read-write LINEAR PA ramps in normal linear mode, ramp offset doesn't apply 0 OFFSET PA ramps with an pre-determined offset that is different between different PAs 1 APC No Description 0x0B8 read-write 0xFF000000 0xFF000004 ENAPCSW software control bit for apc 2 1 read-write DISABLE 0 ENABLE 1 AMPCONTROLLIMITSW software amp_control top limit 24 8 read-write AUXADCTRIM 0x0BC read-write 0x06D55502 0x1FFFFFFF AUXADCCLKINVERT AUXADCCLKINVERT 0 1 read-write Disable_Invert 0 Enable_Invert 1 AUXADCLDOVREFTRIM AUXADCLDOVREFTRIM 1 2 read-write TRIM1p27 0 TRIM1p3 1 TRIM1p35 2 TRIM1p4 3 AUXADCOUTPUTINVERT AUXADCOUTPUTINVERT 3 1 read-write Disabled 0 Enabled 1 AUXADCRCTUNE AUXADCRCTUNE 4 5 read-write AUXADCTRIMADCINPUTRES AUXADCTRIMADCINPUTRES 9 2 read-write RES200k 0 RES250k 1 RES300k 2 RES350k 3 AUXADCTRIMCURRINPUTBUF AUXADCTRIMCURRINPUTBUF 11 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURROPA1 AUXADCTRIMCURROPA1 13 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURROPA2 AUXADCTRIMCURROPA2 15 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURRREFBUF AUXADCTRIMCURRREFBUF 17 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURRTSENSE AUXADCTRIMCURRTSENSE 19 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURRVCMBUF AUXADCTRIMCURRVCMBUF 21 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMLDOHIGHCURRENT AUXADCTRIMLDOHIGHCURRENT 23 1 read-write LowCurrentMode 0 HighCurrentMode 1 AUXADCTRIMREFP AUXADCTRIMREFP 24 2 read-write REF1p05 0 REF1p16 1 REF1p2 2 REF1p25 3 AUXADCTRIMVREFVCM AUXADCTRIMVREFVCM 26 2 read-write Trim0p6 0 Trim0p65 1 Trim0p7 2 Trim0p75 3 AUXADCTSENSETRIMVBE2 AUXADCTSENSETRIMVBE2 28 1 read-write VBE_16uA 0 VBE_32uA 1 AUXADCEN 0x0C0 read-write 0x00000000 0x000003FF AUXADCENAUXADC AUXADCENAUXADC 0 1 read-write Disabled 0 Enabled 1 AUXADCENINPUTBUFFER AUXADCENINPUTBUFFER 1 1 read-write Disabled 0 Enabled 1 AUXADCENLDO AUXADCENLDO 2 1 read-write Disabled 0 Enabled 1 AUXADCENOUTPUTDRV AUXADCENOUTPUTDRV 3 1 read-write Disabled 0 Enabled 1 AUXADCENPMON AUXADCENPMON 4 1 read-write Disabled 0 Enabled 1 AUXADCENRESONDIAGA AUXADCENRESONDIAGA 5 1 read-write Disabled 0 Enabled 1 AUXADCENTSENSE AUXADCENTSENSE 6 1 read-write Disabled 0 Enabled 1 AUXADCENTSENSECAL AUXADCENTSENSECAL 7 1 read-write Disabled 0 Enabled 1 AUXADCINPUTBUFFERBYPASS AUXADCINPUTBUFFERBYPASS 8 1 read-write Not_Bypassed 0 Bypassed 1 AUXADCENMEASTHERMISTOR AUXADCENMEASTHERMISTOR 9 1 read-write Disabled 0 Enabled 1 AUXADCCTRL0 No Description 0x0C4 read-write 0x00000100 0x00003FFF CYCLES Cycle number to run 0 10 read-write MUXSEL Select accumulator 10 2 read-write CLRCOUNTER Clear counter 12 1 read-write CLRFILTER Clear accumulators 13 1 read-write AUXADCCTRL1 0x0C8 read-write 0x00000000 0xF31F0FFF AUXADCINPUTRESSEL AUXADCINPUTRESSEL 0 4 read-write RES640kOhm 0 RES320kOhm 1 RES160kOhm 2 RES80kOhm 3 RES40kOhm 4 RES20kOhm 5 RES10kOhm 6 RES5kOhm 7 RES2p5kOhm 8 RES1p25kOhm 9 RES0p6kOhm 10 RES_switch 11 AUXADCINPUTSELECT AUXADCINPUTSELECT 4 4 read-write SEL0 0 SEL1 1 SEL2 2 SEL3 3 SEL4 4 SEL5 5 SEL6 6 SEL7 7 SEL8 8 SEL9 9 AUXADCPMONSELECT AUXADCPMONSELECT 8 4 read-write AUXADCTSENSESELCURR AUXADCTSENSESELCURR 16 5 read-write AUXADCRESET AUXADCRESET 24 1 read-write Reset_Enabled 0 Reset_Disabled 1 AUXADCTSENSESELVBE AUXADCTSENSESELVBE 25 1 read-write VBE1 0 VBE2 1 AUXADCTHERMISTORFREQSEL AUXADCTHERMISTORFREQSEL 28 4 read-write DIV1 0 DIV2 1 DIV4 2 DIV8 3 DIV16 4 DIV32 5 DIV64 6 DIV128 7 DIV256 8 DIV512 9 DIV1024 10 AUXADCOUT No Description 0x0CC read-only 0x00000000 0x0FFFFFFF AUXADCOUT AUXADC output 0 28 read-only CLKMULTEN0 0x0D0 read-write 0xAA400005 0xFFDFFFFF CLKMULTBWCAL CLKMULTBWCAL 0 2 read-write bw_1lsb 0 bw_2lsb 1 bw_3lsb 2 bw_4lsb 3 CLKMULTDISICO CLKMULTDISICO 2 1 read-write enable 0 disable 1 CLKMULTENBBDET CLKMULTENBBDET 3 1 read-write disable 0 enable 1 CLKMULTENBBXLDET CLKMULTENBBXLDET 4 1 read-write disable 0 enable 1 CLKMULTENBBXMDET CLKMULTENBBXMDET 5 1 read-write disable 0 enable 1 CLKMULTENCFDET CLKMULTENCFDET 6 1 read-write disable 0 enable 1 CLKMULTENDITHER CLKMULTENDITHER 7 1 read-write disable 0 enable 1 CLKMULTENDRVADC CLKMULTENDRVADC 8 1 read-write disable 0 enable 1 CLKMULTENDRVN CLKMULTENDRVN 9 1 read-write disable 0 enable 1 CLKMULTENDRVP CLKMULTENDRVP 10 1 read-write disable 0 enable 1 CLKMULTENDRVRX2P4G CLKMULTENDRVRX2P4G 11 1 read-write disable 0 enable 1 CLKMULTENFBDIV CLKMULTENFBDIV 14 1 read-write disable 0 enable 1 CLKMULTENREFDIV CLKMULTENREFDIV 15 1 read-write disable 0 enable 1 CLKMULTENREG1 CLKMULTENREG1 16 1 read-write disable 0 enable 1 CLKMULTENREG2 CLKMULTENREG2 17 1 read-write disable 0 enable 1 CLKMULTENREG3 CLKMULTENREG3 18 1 read-write disable 0 enable 1 CLKMULTENROTDET CLKMULTENROTDET 19 1 read-write disable 0 enable 1 CLKMULTENBYPASS40MHZ CLKMULTENBYPASS40MHZ 20 1 read-write disable 0 enable 1 CLKMULTFREQCAL CLKMULTFREQCAL 22 2 read-write pedes_14uA 0 pedes_22uA 1 pedes_30uA 2 pedes_38uA 3 CLKMULTREG2ADJI CLKMULTREG2ADJI 24 2 read-write I_80uA 0 I_100uA 1 I_120uA 2 I_140uA 3 CLKMULTREG1ADJV CLKMULTREG1ADJV 26 2 read-write v1p28 0 v1p32 1 v1p33 2 v1p38 3 CLKMULTREG2ADJV CLKMULTREG2ADJV 28 2 read-write v1p03 0 v1p09 1 v1p10 2 v1p16 3 CLKMULTREG3ADJV CLKMULTREG3ADJV 30 2 read-write v1p03 0 v1p06 1 v1p07 2 v1p09 3 CLKMULTEN1 0x0D4 read-write 0x00000188 0x0001FDEF CLKMULTINNIBBLE CLKMULTINNIBBLE 0 4 read-write CLKMULTLDFNIB CLKMULTLDFNIB 5 1 read-write disable 0 enable 1 CLKMULTLDMNIB CLKMULTLDMNIB 6 1 read-write disable 0 enable 1 CLKMULTRDNIBBLE CLKMULTRDNIBBLE 7 2 read-write quarter_nibble 0 fine_nibble 1 moderate_nibble 2 coarse_nibble 3 CLKMULTLDCNIB CLKMULTLDCNIB 10 1 read-write disable 0 enable 1 CLKMULTDRVAMPSEL CLKMULTDRVAMPSEL 11 6 read-write off 0 slide_x1 1 slide_x2 3 slide_x3 7 slide_x4 15 slide_x5 31 slide_x6 63 CLKMULTCTRL 0x0D8 read-write 0x000000C0 0x00007FFF CLKMULTDIVN CLKMULTDIVN 0 7 read-write CLKMULTDIVR CLKMULTDIVR 7 3 read-write CLKMULTDIVX CLKMULTDIVX 10 3 read-write div_1 0 div_2 1 div_4 2 div_6 3 div_8 4 div10 5 div12 6 div14 7 CLKMULTENRESYNC CLKMULTENRESYNC 13 1 read-write disable_sync 0 enable_sync 1 CLKMULTVALID CLKMULTVALID 14 1 read-write invalid 0 valid 1 CLKMULTSTATUS 0x0DC read-only 0x00000000 0x0000001F CLKMULTOUTNIBBLE CLKMULTOUTNIBBLE 0 4 read-only CLKMULTACKVALID CLKMULTACKVALID 4 1 read-only invalid 0 valid 1 IFADCTRIM0 0x0E4 read-write 0x11512C6C 0x3FFFFFFF IFADCCLKSEL IFADCCLKSEL 0 1 read-write clk_2p4g 0 clk_subg 1 IFADCENHALFMODE IFADCENHALFMODE 1 1 read-write full_speed_mode 0 half_speed_mode 1 IFADCLDOSERIESAMPLVL IFADCLDOSERIESAMPLVL 2 3 read-write v1p225 0 v1p250 1 v1p275 2 v1p300 3 v1p325 4 v1p350 5 v1p375 6 v1p400 7 IFADCLDOSHUNTAMPLVL1 IFADCLDOSHUNTAMPLVL1 5 3 read-write v1p125 0 v1p150 1 v1p175 2 v1p200 3 v1p225 4 v1p250 5 v1p275 6 v1p300 7 IFADCLDOSHUNTAMPLVL2 IFADCLDOSHUNTAMPLVL2 8 1 read-write disable 0 enable 1 IFADCLDOSHUNTCURLVL1 IFADCLDOSHUNTCURLVL1 9 3 read-write i55u 0 i65u 1 i70u 2 i85u 3 i85u2 4 i95u 5 i100u 6 i110u 7 IFADCLDOSHUNTCURLVL2 IFADCLDOSHUNTCURLVL2 12 3 read-write i4u 0 i4p5u 1 i5u 2 i5p5u 3 i5u2 4 i5p5u2 5 i6u 6 i6p5u 7 IFADCOTACURRENT IFADCOTACURRENT 15 3 read-write i3u 0 i3p5u 1 i4u 2 i4p5u 3 i4u2 4 i4p5u2 5 i5u 6 i5p5u 7 IFADCREFBUFAMPLVL IFADCREFBUFAMPLVL 18 3 read-write v0p88 0 v0p91 1 v0p94 2 v0p97 3 v1p00 4 v1p03 5 v1p06 6 v1p09 7 IFADCREFBUFCURLVL IFADCREFBUFCURLVL 21 3 read-write i4u 0 i4p5u 1 i5u 2 i5p5u 3 i5u2 4 i5p5u2 5 i6u 6 i6p5u 7 IFADCSIDETONEAMP IFADCSIDETONEAMP 24 3 read-write diff_5p68mV 0 diff_29p1mV 1 diff_9p73mV 2 diff_76p9mV 3 diff_9p68_mV 4 diff_51_mV 5 diff_17p2_mV 6 disable 7 IFADCSIDETONEFREQ IFADCSIDETONEFREQ 27 3 read-write na0 0 div_128 1 div_64 2 div_32 3 div_16 4 div_8 5 div_4 6 na7 7 IFADCTRIM1 0x0E8 read-write 0x00000123 0x000001FF IFADCVCMLVL IFADCVCMLVL 0 3 read-write vcm_475mV 0 vcm_500mV 1 vcm_525mV 2 vcm_550mV 3 vcm_575mV 4 vcm_600mV 5 vcm_625mV 6 cm_650mV 7 IFADCENNEGRES IFADCENNEGRES 3 1 read-write disable 0 enable 1 IFADCNEGRESCURRENT IFADCNEGRESCURRENT 4 3 read-write i1p0u 0 i1p5u 1 i2p0u 2 i2p5u 3 i2p0u2 4 i2p5u2 5 i3p0u 6 i3p5u 7 IFADCNEGRESVCM IFADCNEGRESVCM 7 2 read-write r210k_x_1uA 0 r210k_x_1uA2 1 r100k_x_2uA 2 r50k_x_3uA 3 IFADCCAL 0x0EC read-write 0x00000C00 0x00FF1F03 IFADCENRCCAL IFADCENRCCAL 0 1 read-write rccal_disable 0 rccal_enable 1 IFADCTUNERCCALMODE IFADCTUNERCCALMODE 1 1 read-write SYmode 0 ADCmode 1 IFADCTUNERC IFADCTUNERC 8 5 read-write IFADCRCCALCOUNTERSTARTVAL IFADCRCCALCOUNTERSTARTVAL 16 8 read-write IFADCSTATUS 0x0F0 read-only 0x00000000 0x00000001 IFADCRCCALOUT IFADCRCCALOUT 0 1 read-only lo 0 hi 1 LNAMIXTRIM0 0x0F8 read-write 0x1108233D 0x1FFFFFFF LNAMIXCURCTRL LNAMIXCURCTRL 0 6 read-write LNAMIXHIGHCUR LNAMIXHIGHCUR 6 2 read-write current_470uA 0 current_530uA 1 unused 2 current_590uA 3 LNAMIXLOWCUR LNAMIXLOWCUR 8 4 read-write LNAMIXRFPKDBWSEL LNAMIXRFPKDBWSEL 12 2 read-write LNAMIXRFPKDCALCM LNAMIXRFPKDCALCM 14 6 read-write LNAMIXRFPKDCALDM LNAMIXRFPKDCALDM 20 5 read-write LNAMIXTRIMVREG LNAMIXTRIMVREG 25 4 read-write LNAMIXTRIM1 0x0FC read-write 0x00045408 0x0007FFFF LNAMIXIBIASADJ LNAMIXIBIASADJ 0 6 read-write LNAMIXLNACAPSEL LNAMIXLNACAPSEL 6 3 read-write LNAMIXMXRBIAS LNAMIXMXRBIAS 9 2 read-write bias_1V 0 unused 1 bias_900m 2 bias_800m 3 LNAMIXNCASADJ LNAMIXNCASADJ 11 2 read-write ncas_1V 0 unused 1 ncas_950m 2 ncas_900m 3 LNAMIXPCASADJ LNAMIXPCASADJ 13 2 read-write pcas_250m 0 unused 1 pcas_300m 2 pcas_350m 3 LNAMIXVOUTADJ LNAMIXVOUTADJ 15 4 read-write LNAMIXCAL 0x104 read-write 0x00000070 0x00000077 LNAMIXCALEN LNAMIXCALEN 0 1 read-write cal_disable 0 cal_enable 1 LNAMIXCALVMODE LNAMIXCALVMODE 1 1 read-write current_mode 0 voltage_mode 1 LNAMIXENIRCAL LNAMIXENIRCAL 2 1 read-write disable 0 enable 1 LNAMIXIRCALAMP LNAMIXIRCALAMP 4 3 read-write LNAMIXEN 0x108 read-write 0x00000000 0x00000001 LNAMIXENLDO LNAMIXENLDO 0 1 read-write disable 0 enable 1 PRECTRL 0x10C read-write 0x00000026 0x0000003F PREBYPFORCE PREBYPFORCE 0 1 read-write not_forced 0 forced 1 PREREGTRIM PREREGTRIM 1 3 read-write v1p61 0 v1p68 1 v1p74 2 v1p80 3 v1p86 4 v1p91 5 v1p96 6 v2p00 7 PREVREFTRIM PREVREFTRIM 4 2 read-write v0p675 0 v0p688 1 v0p700 2 v0p713 3 PATRIM0 0x110 read-write 0x00000077 0x00003FFF TX0DBMTRIMBIASN TX0DBMTRIMBIASN 0 4 read-write v_378m 0 v_392m 1 v_405m 2 v_418p5m 3 v_431m 4 v_444m 5 v_457m 6 v_470m 7 v_483m 8 v_496m 9 v_509m 10 v_522m 11 v_535m 12 v_548m 13 v_561m 14 v_574m 15 TX0DBMTRIMBIASP TX0DBMTRIMBIASP 4 4 read-write v_378m 0 v_392m 1 v_405m 2 v_418p5m 3 v_431m 4 v_444m 5 v_457m 6 v_470m 7 v_483m 8 v_496m 9 v_509m 10 v_522m 11 v_535m 12 v_548m 13 v_561m 14 v_574m 15 TX0DBMTRIMDUTYCYN TX0DBMTRIMDUTYCYN 8 3 read-write up_0pct 0 up_1pct 1 up_2pct 2 up_3pct 3 up_4pct 4 up_5pct 5 up_6pct 6 na 7 TX0DBMTRIMDUTYCYP TX0DBMTRIMDUTYCYP 11 3 read-write dn_0pct 0 dn_1pct 1 dn_2pct 2 dn_3pct 3 dn_4pct 4 dn_5pct 5 dn_6pct 6 na 7 PATRIM1 0x114 read-write 0x0003AB97 0x0007FFFF TX0DBMTRIMPREDRVREGIBCORE TX0DBMTRIMPREDRVREGIBCORE 0 2 read-write i_4u 0 i_5u 1 i_6u 2 i_7u 3 TX0DBMTRIMPREDRVREGIBNDIO TX0DBMTRIMPREDRVREGIBNDIO 2 4 read-write vreg_1p127 0 vreg_1p171 1 vreg_1p209 2 vreg_1p244 3 vreg_1p275 4 vreg_1p305 5 vreg_1p335 6 vreg_1p363 7 vreg_1p388 8 vreg_1p414 9 vreg_1p439 10 vreg_1p464 11 vreg_1p486 12 vreg_1p506 13 vreg_1p525 14 vreg_1p545 15 TX0DBMTRIMPREDRVREGPSR TX0DBMTRIMPREDRVREGPSR 6 1 read-write disable 0 enable 1 TX0DBMTRIMPREDRVSLOPE TX0DBMTRIMPREDRVSLOPE 7 2 read-write slope_0 0 slope_1 1 slope_2 2 slope_max 3 TX0DBMTRIMREGFB TX0DBMTRIMREGFB 9 4 read-write vo_vi_0p475 0 vo_vi_0p500 1 vo_vi_0p525 2 vo_vi_0p550 3 vo_vi_0p575 4 vo_vi_0p600 5 vo_vi_0p625 6 vo_vi_0p650 7 vo_vi_0p675 8 vo_vi_0p700 9 vo_vi_0p725 10 vo_vi_0p750 11 vo_vi_0p775 12 vo_vi_0p800 13 vo_vi_0p825 14 vo_vi_0p850 15 TX0DBMTRIMREGVREF TX0DBMTRIMREGVREF 13 3 read-write v_900m 0 v_912p5m 1 v_925m 2 v_937p5m 3 v_950m 4 v_962p5m 5 v_975m 6 v_987p5m 7 TX0DBMTRIMTAPCAP TX0DBMTRIMTAPCAP 16 3 read-write cap_0F 0 cap_0p35pF 1 cap_0p7pF 2 cap_1p05pF 3 cap_1p4pF 4 cap_1p75pF 5 cap_2p1pF 6 cap_2p45pF 7 PATRIM2 0x118 read-write 0x00000088 0x00003FFF TX6DBMTRIMBIASN TX6DBMTRIMBIASN 0 4 read-write vnbias_dn104mV 0 vnbias_dn91mV 1 vnbias_dn78mV 2 vnbias_dn65mV 3 vnbias_dn52mV 4 vnbias_dn39mV 5 vnbias_dn26mV 6 vnbias_dn13mV 7 vnbias_default_613mV 8 vnbias_up13mV 9 vnbias_up26mV 10 vnbias_up39mV 11 vnbias_up52mV 12 vnbias_up65mV 13 vnbias_up78mV 14 vnbias_up91mV 15 TX6DBMTRIMBIASP TX6DBMTRIMBIASP 4 4 read-write vpbias_dn104mV 0 vpbias_dn91mV 1 vpbias_dn78mV 2 vpbias_dn65mV 3 vpbias_dn52mV 4 vpbias_dn39mV 5 vpbias_dn26mV 6 vpbias_dn13mV 7 vpbias_default_949mV 8 vpbias_up13mV 9 vpbias_up26mV 10 vpbias_up39mV 11 vpbias_up52mV 12 vpbias_up65mV 13 vpbias_up78mV 14 vpbias_up91mV 15 TX6DBMTRIMDUTYCYN TX6DBMTRIMDUTYCYN 8 3 read-write up_0pct 0 up_1pct 1 up_2pct 2 up_3pct 3 up_4pct 4 up_5pct 5 up_6pct 6 na 7 TX6DBMTRIMDUTYCYP TX6DBMTRIMDUTYCYP 11 3 read-write dn_0pct 0 dn_1pct 1 dn_2pct 2 dn_3pct 3 dn_4pct 4 dn_5pct 5 dn_6pct 6 na 7 PATRIM3 No Description 0x11C read-write 0x002E2B2A 0x007E7FFF TX6DBMTRIMIBIASMASTER TX6DBMTRIMIBIASMASTER 0 2 read-write ibias_45u 0 ibias_47p5u 1 ibias_50u 2 ibias_52p5u 3 TX6DBMTRIMPREDRVREGFB TX6DBMTRIMPREDRVREGFB 2 2 read-write Acl_1p63 0 Acl_1p71 1 Acl_1p80 2 Acl_1p92 3 TX6DBMTRIMPREDRVREGFBKATT TX6DBMTRIMPREDRVREGFBKATT 4 1 read-write reduce_BW 0 increase_BW 1 TX6DBMTRIMPREDRVREGPSR TX6DBMTRIMPREDRVREGPSR 5 1 read-write low_psr 0 high_psr 1 TX6DBMTRIMPREDRVREGSLICE TX6DBMTRIMPREDRVREGSLICE 6 2 read-write iload_3mA 0 iload_6mA 1 iload_9mA 2 iload_12mA 3 TX6DBMTRIMPREDRVREGVREF TX6DBMTRIMPREDRVREGVREF 8 3 read-write vref_0p675 0 vref_0p700 1 vref_0p725 2 vref_0p750 3 vref_0p775 4 vref_0p800 5 vref_0p825 6 vref_0p850 7 TX6DBMTRIMREGBLEEDAUTO TX6DBMTRIMREGBLEEDAUTO 11 1 read-write not_automatic 0 automatic 1 TX6DBMTRIMREGFB TX6DBMTRIMREGFB 12 2 read-write Acl_2p0x 0 Acl_2p1x 1 Acl_2p3125x 2 Acl_2p5x 3 TX6DBMTRIMREGPSR TX6DBMTRIMREGPSR 14 1 read-write low_PSR 0 high_PSR 1 TX6DBMTRIMREGVREF TX6DBMTRIMREGVREF 17 4 read-write vref_0p6000 0 vref_0p6125 1 vref_0p6250 2 vref_0p6375 3 vref_0p6500 4 vref_0p6625 5 vref_0p6750 6 vref_0p6875 7 vref_0p7000 8 vref_0p7125 9 vref_0p7250 10 vref_0p7375 11 vref_0p7500 12 vref_0p7625 13 vref_0p7750 14 vref_0p7875 15 TX6DBMTRIMRXMODEVREF TX6DBMTRIMRXMODEVREF 21 2 read-write vddreg_1p05 0 vddreg_1p14 1 vddreg_1p20 2 vddreg_1p23 3 PACTRL 0x120 read-write 0x00000010 0x1FFF033F TX0DBMPOWER TX0DBMPOWER 0 4 read-write on_stripe_0 0 on_stripe_12 12 TX0DBMSELSLICE TX0DBMSELSLICE 4 2 read-write on_0_slice 0 on_1_slices 1 on_2_slices 2 NA 3 TX0DBMSLICERESET TX0DBMSLICERESET 8 1 read-write active 0 reset 1 TX0DBMLATCHBYPASS TX0DBMLATCHBYPASS 9 1 read-write disable 0 enable 1 TX6DBMPOWER TX6DBMPOWER 16 5 read-write TX6DBMSELSLICE TX6DBMSELSLICE 21 3 read-write n_slice_on_0 0 n_slice_on_1 1 n_slice_on_2 2 n_slice_on_3 3 n_slice_on_4 4 tbd_5 5 tbd_6 6 tbd_7 7 TX6DBMSLICERESET TX6DBMSLICERESET 24 1 read-write disable_reset 0 enable_reset 1 TX6DBMLATCHBYPASS TX6DBMLATCHBYPASS 25 1 read-write not_bypass 0 bypass_latch 1 TX6DBMPREDRVREGBYPASS TX6DBMREGBYPASSPDRVLDo 26 1 read-write not_bypass 0 bypass 1 TX6DBMPULLDOWNREG TX6DBMPULLDOWNREG 27 1 read-write not_pull_down 0 pull_down 1 TX6DBMREGBYPASS TX6DBMREGBYPASS 28 1 read-write not_bypass 0 bypass 1 PGATRIM 0x128 read-write 0x00000547 0x000007FF PGACTUNE PGACTUNE 0 4 read-write cfb_0p7 0 cfb_nominal 7 cfb_1p32 15 PGADISANTILOCK PGADISANTILOCK 4 1 read-write antilock_enable 0 antilock_disable 1 PGAVCMOUTTRIM PGAVCMOUTTRIM 5 3 read-write vcm_out_0p4 0 vcm_out_0p45 1 vcm_out_0p5 2 vcm_out_0p55 3 vcm_out_0p6 4 vcm_out_0p65 5 vcm_out_0p7 6 vcm_out_0p75 7 PGAVLDOTRIM PGAVLDOTRIM 8 3 read-write vdda_1p15 0 vdda_1p2 1 vdda_1p25 2 vdda_1p3 3 vdda_1p35 4 vdda_1p4 5 vdda_1p5 6 vdda_1p55 7 PGACAL 0x12C read-write 0x20202020 0x3F3F3F3F PGAOFFNCALI PGAOFFNCALI 0 6 read-write offset_m_300mv 0 offset_p_300mv 63 PGAOFFNCALQ PGAOFFNCALQ 8 6 read-write offset_m_300mv 0 offset_p_300mv 63 PGAOFFPCALI PGAOFFPCALI 16 6 read-write offset_m_300mv 0 offset_p_300mv 63 PGAOFFPCALQ PGAOFFPCALQ 24 6 read-write offset_m_300mv 0 offset_p_300mv 63 PGACTRL 0x130 read-write 0x04000000 0x07FFFEEF PGABWMODE PGABWMODE 0 2 read-write bw_5MHz 0 bw_2p5MHz 1 bw_1p67MHz 2 bw_1p25MHz 3 PGAENBIAS PGAENBIAS 2 1 read-write bias_disable 0 bias_enable 1 PGAENGHZ PGAENGHZ 3 1 read-write ghz_disable 0 ghz_enable 1 PGAENLATCHI PGAENLATCHI 5 1 read-write pkd_latch_i_disable 0 pkd_latch_i_enable 1 PGAENLATCHQ PGAENLATCHQ 6 1 read-write pkd_latch_q_disable 0 pkd_latch_q_enable 1 PGAENLDOLOAD PGAENLDOLOAD 7 1 read-write disable_ldo_load 0 enable_ldo_load 1 PGAENPGAI PGAENPGAI 9 1 read-write pgai_disable 0 pgai_enable 1 PGAENPGAQ PGAENPGAQ 10 1 read-write pgaq_disable 0 pgaq_enable 1 PGAENPKD PGAENPKD 11 1 read-write pkd_disable 0 pkd_enable 1 PGAENRCMOUT PGAENRCMOUT 12 1 read-write rcm_out_disable 0 rcm_out_enable 1 PGAPOWERMODE PGAPOWERMODE 14 2 read-write pm_typ 0 pm_0p9 1 pm_1p2 2 pm_0p8 3 PGATHRPKDLOSEL PGATHRPKDLOSEL 16 4 read-write vref50mv 0 vref75mv 1 vref100mv 2 vref125mv 3 vref150mv 4 vref175mv 5 vref200mv 6 vref225mv 7 vref250mv 8 vref275mv 9 vref300mv 10 PGATHRPKDHISEL PGATHRPKDHISEL 20 4 read-write vref50mv 0 vref75mv 1 vref100mv 2 vref125mv 3 verf150mv 4 vref175mv 5 vref200mv 6 vref225mv 7 vref250mv 8 vref275mv 9 vref300mv 10 LNAMIXRFPKDTHRESHSEL LNAMIXRFPKDTHRESHSEL 24 3 read-write RFBIASCAL 0x134 read-write 0x30203020 0x3F3F3F3F RFBIASCALBIAS RFBIASCALBIAS 0 6 read-write RFBIASCALTC RFBIASCALTC 8 6 read-write RFBIASCALVREF RFBIASCALVREF 16 6 read-write RFBIASCALVREFSTARTUP RFBIASCALVREFSTARTUP 24 6 read-write RFBIASCTRL 0x138 read-write 0x00040000 0x000F001F RFBIASDISABLEBOOTSTRAP RFBIASDISABLEBOOTSTRAP 0 1 read-write enable_startup 0 disable_startup 1 RFBIASLDOHIGHCURRENT RFBIASLDOHIGHCURRENT 1 1 read-write low_current 0 high_current 1 RFBIASNONFLASHMODE RFBIASNONFLASHMODE 2 1 read-write flash_process 0 non_flash_process 1 RFBIASSTARTUPCORE RFBIASSTARTUPCORE 3 1 read-write default 0 force_start 1 RFBIASSTARTUPSUPPLY RFBIASSTARTUPSUPPLY 4 1 read-write default 0 forc_start 1 RFBIASLDOVREFTRIM RFBIASLDOVREFTRIM 16 4 read-write vref_v0p800 0 vref_v0p813 1 vref_v0p825 2 vref_v0p837 3 vref_v0p850 4 vref_v0p863 5 vref_v0p875 6 vref_v0p887 7 vref_v0p900 8 vref_v0p913 9 vref_v0p925 10 vref_v0p938 11 vref_v0p950 12 vref_v0p963 13 vref_v0p975 14 vref_v0p988 15 RADIOEN 0x13C read-write 0x00000000 0x00000007 PREEN PREEN 0 1 read-write powered_off 0 powered_on 1 PRESTB100UDIS PRESTB100UDIS 1 1 read-write i100ua_enabled 0 i100ua_disabled 1 RFBIASEN RFBIASEN 2 1 read-write disable_rfis_vtr 0 enable_rfis_vtr 1 RFPATHEN No Description 0x140 read-write 0x00000004 0x0000001E LNAMIXEN LNAMIXEN 1 1 read-write disable 0 enable 1 LNAMIXRFATTDCEN LNAMIXRFATTDCEN 2 1 read-write disable_dc 0 enable_dc 1 LNAMIXRFPKDENRF LNAMIXRFPKDENRF 3 1 read-write disable 0 enable_path 1 LNAMIXTRSW LNAMIXTRSW 4 1 read-write disabled 0 enabled 1 RX 0x144 read-write 0x00000010 0x00000FFF IFADCCAPRESET IFADCCAPRESET 0 1 read-write cap_reset_disable 0 cap_reset_enable 1 IFADCENLDOSERIES IFADCENLDOSERIES 1 1 read-write series_ldo_disable 0 series_ldo_enable 1 IFADCENLDOSHUNT IFADCENLDOSHUNT 2 1 read-write shunt_ldo_disable 0 shunt_ldo_enable 1 LNAMIXENRFPKD LNAMIXENRFPKD 3 1 read-write disable 0 enable 1 LNAMIXLDOLOWCUR LNAMIXLDOLOWCUR 4 1 read-write regular_mode 0 low_current_mode 1 LNAMIXREGLOADEN LNAMIXREGLOADEN 5 1 read-write disable_resistor 0 enable_resistor 1 PGAENLDO PGAENLDO 6 1 read-write disable_ldo 0 enable_ldo 1 SYCHPBIASTRIMBUF SYCHPBIASTRIMBUF 7 1 read-write i_tail_10u 0 i_tail_20u 1 SYCHPQNC3EN SYCHPQNC3EN 8 1 read-write qnc_2 0 qnc_3 1 SYPFDCHPLPEN SYPFDCHPLPEN 9 1 read-write disable 0 enable 1 SYPFDFPWEN SYPFDFPWEN 10 1 read-write disable 0 enable 1 TX6DBMENRXMODEBIAS TX6DBMENRXMODEBIAS 11 1 read-write Disable 0 Enable 1 TX 0x148 read-write 0x00000000 0xE3CB00FF TX0DBMENBLEEDPREDRVREG TX0DBMENBLEEDPREDRVREG 0 1 read-write disable 0 enable 1 TX0DBMENBLEEDREG TX0DBMENBLEEDREG 1 1 read-write disable 0 enable 1 TX0DBMENPREDRV TX0DBMENPREDRV 2 1 read-write disable 0 enable 1 TX0DBMENPREDRVREG TX0DBMENPREDRVREG 3 1 read-write disable 0 enable 1 TX0DBMENPREDRVREGBIAS TX0DBMENPREDRVREGBIAS 4 1 read-write disable 0 enable 1 TX0DBMENBIAS TX0DBMENBIAS 5 1 read-write disable 0 enable 1 TX0DBMENRAMPCLK TX0DBMENRAMPCLK 6 1 read-write disable 0 enable 1 TX0DBMENREG TX0DBMENREG 7 1 read-write disable 0 enable 1 TX6DBMENBLEEDPREDRVREG TX6DBMENBLEEDPREDRVREG 16 1 read-write disable 0 enable 1 TX6DBMENBLEEDREG TX6DBMENBLEEDREG 17 1 read-write disable 0 enable 1 TX6DBMENPREDRVREG TX6DBMENPREDRVREG 19 1 read-write disable 0 enable 1 TX6DBMENRAMPCLK TX6DBMENRAMPCLK 22 1 read-write disable_clock 0 enable_clock 1 TX6DBMENREG TX6DBMENREG 23 1 read-write disable 0 enable 1 TX6DBMENPACORE TX6DBMENPACORE 24 1 read-write disable 0 enable 1 TX6DBMENPAOUT TX6DBMENPAOUT 25 1 read-write disable 0 enable 1 ENXOSQBUFFILT Override 29 1 read-write ENPAPOWER Override 30 1 read-write ENPASELSLICE Override 31 1 read-write SYTRIM0 0x150 read-write 0x00062E29 0x003FEFFF SYCHPBIAS SYCHPBIAS 0 3 read-write bias_0 0 bias_1 1 bias_2 3 bias_3 7 SYCHPCURR SYCHPCURR 3 3 read-write curr_1p5uA 0 curr_2p0uA 1 curr_2p5uA 2 curr_3p0uA 3 curr_3p5uA 4 curr_4p0uA 5 curr_4p5uA 6 curr_5p0uA 7 SYCHPLEVNSRC SYCHPLEVNSRC 6 3 read-write SYCHPLEVPSRC SYCHPLEVPSRC 9 3 read-write vsrcp_n105m 0 vsrcp_n90m 1 vsrcp_n75m 2 vsrcp_n60m 3 vsrcp_n45m 4 vsrcp_n30m 5 vsrcp_n15m 6 vsrcp_n0m 7 SYCHPSRCEN SYCHPSRCEN 13 1 read-write disable 0 enable 1 SYCHPREPLICACURRADJ SYCHPREPLICACURRADJ 14 3 read-write load_8ua 0 load_16ua 1 load_20ua 2 load_28ua 3 load_24ua 4 load_32ua 5 load_36ua 6 load_44ua 7 SYTRIMCHPREGAMPBIAS SYTRIMCHPREGAMPBIAS 17 3 read-write bias_14uA 0 bias_20uA 1 bias_26uA 2 bias_32uA 3 bias_38uA 4 bias_44uA 5 bias_50uA 6 bias_56uA 7 SYTRIMCHPREGAMPBW SYTRIMCHPREGAMPBW 20 2 read-write C_000f 0 C_300f 1 C_600f 2 C_900f 3 SYTRIM1 0x154 read-write 0x00003FC4 0xE003FFFF SYLODIVLDOTRIMCORE SYLODIVLDOTRIMCORE 0 2 read-write RXLO 0 TXLO 3 SYLODIVLDOTRIMNDIO SYLODIVLDOTRIMNDIO 2 4 read-write vreg_1p08 0 vreg_1p11 1 vreg_1p15 2 vreg_1p18 3 vreg_1p21 4 vreg_1p24 5 vreg_1p27 6 vreg_1p29 7 vreg_1p32 8 vreg_1p34 9 SYMMDREPLICA1CURRADJ SYMMDREPLICA1CURRADJ 6 3 read-write load_8ua 0 load_16u 1 load_20ua 2 load_28ua 3 load_24ua 4 load_32ua 5 load_36ua 6 load_44ua 7 SYMMDREPLICA2CURRADJ SYMMDREPLICA2CURRADJ 9 3 read-write load_32u 0 load_64u 1 load_96u 2 load_128u 3 load_160u 4 load_192u 5 load_224u 6 load_256u 7 SYTRIMMMDREGAMPBIAS SYTRIMMMDREGAMPBIAS 12 3 read-write bias_14uA 0 bias_20uA 1 bias_26uA 2 bias_32uA 3 bias_38uA 4 bias_44uA 5 bias_50uA 6 bias_56uA 7 SYTRIMMMDREGAMPBW SYTRIMMMDREGAMPBW 15 2 read-write C_000f 0 C_300f 1 C_600f 2 C_900f 3 SYLODIVRLOADCCLKSEL SYLODIVRLOADCCLKSEL 17 1 read-write adc_clk_div8 0 adc_clk_div16 1 SYLODIVSGTESTDIV SYLODIVSGTESTDIV 29 3 read-write div2 0 div3 1 div4 2 div6 3 div8 4 div12 5 div16 6 div12x 7 SYCAL 0x158 read-write 0x01008100 0x03018700 SYVCOMODEPKD SYVCOMODEPKD 8 1 read-write t_openloop_0 0 t_pkdetect_1 1 SYVCOMORECURRENT SYVCOMORECURRENT 9 1 read-write more_current_0 0 more_current_1 1 SYVCOSLOWNOISEFILTER SYVCOSLOWNOISEFILTER 10 1 read-write slow_noise_filter_0 0 slow_noise_filter_1 1 SYVCOVCAPVCM SYVCOVCAPVCM 15 2 read-write SYHILOADCHPREG SYHILOADCHPREG 24 2 read-write i_350uA 0 i_500uA 1 i_550uA 2 i_700uA 3 SYEN 0x15C read-write 0x00000000 0x00007FFF SYCHPEN SYCHPEN 0 1 read-write disable 0 enable 1 SYCHPLPEN SYCHPLPEN 1 1 read-write disable 0 enable 1 SYENCHPREG SYENCHPREG 2 1 read-write Disable 0 Enable 1 SYENCHPREPLICA SYENCHPREPLICA 3 1 read-write disable 0 enable 1 SYENMMDREG SYENMMDREG 4 1 read-write Disable 0 Enable 1 SYENMMDREPLICA1 SYENMMDREPLICA1 5 1 read-write disable 0 enable 1 SYENMMDREPLICA2 SYENMMDREPLICA2 6 1 read-write Disable 0 Enable 1 SYENVCOBIAS SYENVCOBIAS 7 1 read-write en_vco_bias_0 0 en_vco_bias_1 1 SYENVCOPFET SYENVCOPFET 8 1 read-write en_vco_pfet_0 0 en_vco_pfet_1 1 SYENVCOREG SYENVCOREG 9 1 read-write en_vco_reg_0 0 en_vco_reg_1 1 SYLODIVEN SYLODIVEN 10 1 read-write disable 0 enable 1 SYLODIVLDOBIASEN SYLODIVLDOBIASEN 11 1 read-write disable 0 enable 1 SYLODIVLDOEN SYLODIVLDOEN 12 1 read-write disable 0 enable 1 SYSTARTCHPREG SYSTARTCHPREG 13 1 read-write no_fast_startup 0 fast_startup 1 SYSTARTMMDREG SYSTARTMMDREG 14 1 read-write no_fast_startup 0 fast_startup 1 SYLOEN 0x160 read-write 0x00000000 0x80000663 SYLODIVRLOADCCLK2G4EN SYLODIVRLOADCCLK2G4EN 0 1 read-write disable 0 enable 1 SYLODIVRLO2G4EN SYLODIVRLO2G4EN 1 1 read-write disable 0 enable 1 SYLODIVTLO0DBM2G4AUXEN SYLODIVTLO0DBM2G4AUXEN 5 1 read-write disable 0 enable 1 SYLODIVTLO0DBM2G4EN SYLODIVTLO0DBM2G4EN 6 1 read-write disable 0 enable 1 SYLODIVTLO6DBM2G4AUXEN SYLODIVTLO6DBM2G4AUXEN 9 1 read-write disable 0 enable 1 SYLODIVTLO6DBM2G4EN SYLODIVTLO6DBM2G4EN 10 1 read-write disable 0 enable 1 SYLODIVSGTESTDIVEN SYLODIVSGTESTDIVEN 31 1 read-write disable 0 enable 1 SYMMDCTRL 0x168 read-write 0x00000400 0x00000E07 SYMMDENRSDIG SYMMDENRSDIG 0 1 read-write disable 0 enable 1 SYMMDDIVRSDIG SYMMDDIVRSDIG 1 2 read-write Divideby1 0 Divideby2 1 Divideby4 2 Divideby8 3 SYMMDMODE SYMMDMODE 9 3 read-write rx_w_swctrl 0 rx_wo_swctrl 1 qnc_dsm2 2 qnc_dsm3 3 rxlp_wo_swctrl 4 notuse_5 5 notuse_6 6 notuse_7 7 DIGCLKRETIMECTRL No Description 0x16C read-write 0x00000000 0x00000777 DIGCLKRETIMEENRETIME DIGCLKRETIMEENRETIME 0 1 read-write disable 0 enable 1 DIGCLKRETIMEDISRETIME DIGCLKRETIMEDISRETIME 1 1 read-write enable_retime 0 disable_retime 1 DIGCLKRETIMERESETN DIGCLKRETIMERESETN 2 1 read-write reset 0 operate 1 DIGCLKRETIMELIMITH DIGCLKRETIMELIMITH 4 3 read-write DIGCLKRETIMELIMITL DIGCLKRETIMELIMITL 8 3 read-write DIGCLKRETIMESTATUS No Description 0x170 read-only 0x00000000 0x00000003 DIGCLKRETIMECLKSEL DIGCLKRETIMECLKSEL 0 1 read-only use_raw_clk 0 use_retimed_clk 1 DIGCLKRETIMERESETNLO DIGCLKRETIMERESETNLO 1 1 read-only lo 0 hi 1 XORETIMECTRL No Description 0x174 read-write 0x00000000 0x00000777 XORETIMEENRETIME XORETIMEENRETIME 0 1 read-write disable 0 enable 1 XORETIMEDISRETIME XORETIMEDISRETIME 1 1 read-write enable_retime 0 disable_retime 1 XORETIMERESETN XORETIMERESETN 2 1 read-write operate 0 reset 1 XORETIMELIMITH XORETIMELIMITH 4 3 read-write XORETIMELIMITL XORETIMELIMITL 8 3 read-write XORETIMESTATUS No Description 0x178 read-only 0x00000000 0x00000003 XORETIMECLKSEL XORETIMECLKSEL 0 1 read-only use_raw_clk 0 use_retimed_clk 1 XORETIMERESETNLO XORETIMERESETNLO 1 1 read-only lo 0 hi 1 XOSQBUFFILT 0x17C read-write 0x00000000 0x00000003 XOSQBUFFILT XOSQBUFFILT 0 2 read-write bypass 0 filter_1 1 filter_2 2 filter_3 3 AGCOVERWRITE No Description 0x188 read-write 0x00000000 0x03F0FFFF ENMANLNAMIXRFATT Enable RAC Overwite PN 0 1 read-write ENMANLNAMIXSLICE Enable RAC Overwite LNA 1 1 read-write ENMANPGAGAIN Enable RAC Overwite PGA 2 1 read-write ENMANIFADCSCALE Enable RAC Overwite PN 3 1 read-write MANLNAMIXRFATT RAC Overwite PN 4 6 read-write MANLNAMIXSLICE RAC Overwite LNA 10 6 read-write MANPGAGAIN RAC Overwite PGA 20 4 read-write MANIFADCSCALE RAC Overwite PGA 24 2 read-write SCRATCH0 No Description 0x3E0 read-write 0x00000000 0xFFFFFFFF SCRATCH0 SCRATCH0 0 32 read-write SCRATCH1 No Description 0x3E4 read-write 0x00000000 0xFFFFFFFF SCRATCH1 SCRATCH1 0 32 read-write SCRATCH2 No Description 0x3E8 read-write 0x00000000 0xFFFFFFFF SCRATCH2 SCRATCH2 0 32 read-write SCRATCH3 No Description 0x3EC read-write 0x00000000 0xFFFFFFFF SCRATCH3 SCRATCH3 0 32 read-write SCRATCH4 No Description 0x3F0 read-write 0x00000000 0xFFFFFFFF SCRATCH4 SCRATCH4 0 32 read-write SCRATCH5 No Description 0x3F4 read-write 0x00000000 0xFFFFFFFF SCRATCH5 SCRATCH5 0 32 read-write SCRATCH6 No Description 0x3F8 read-write 0x00000000 0xFFFFFFFF SCRATCH6 SCRATCH6 0 32 read-write SCRATCH7 No Description 0x3FC read-write 0x00000000 0xFFFFFFFF SCRATCH7 SCRATCH7 0 32 read-write THMSW No Description 0x7E8 read-write 0x00000000 0x00000003 EN Enable Switch 0 1 read-write Disabled 0 Enabled 1 HALFSWITCH Halfswitch Mode enable 1 1 read-write Disabled 0 Enabled 1 RDMAILBOX0_NS 0 RDMAILBOX0_NS Registers 0xB8028000 0x00000000 0x00001000 registers MSGPTR0 No Description 0x000 read-write 0x00000000 0xFFFFFFFF PTR Pointer 0 32 read-write MSGPTR1 No Description 0x004 read-write 0x00000000 0xFFFFFFFF PTR Pointer 0 32 read-write MSGPTR2 No Description 0x008 read-write 0x00000000 0xFFFFFFFF PTR Pointer 0 32 read-write MSGPTR3 No Description 0x00C read-write 0x00000000 0xFFFFFFFF PTR Pointer 0 32 read-write IF No Description 0x040 read-write 0x00000000 0x0000000F MBOXIF0 Mailbox Interupt Flag 0 1 read-write MBOXIF1 Mailbox Interupt Flag 1 1 read-write MBOXIF2 Mailbox Interupt Flag 2 1 read-write MBOXIF3 Mailbox Interupt Flag 3 1 read-write IEN No Description 0x044 read-write 0x00000000 0x0000000F MBOXIEN0 Mailbox Interrupt Enable 0 1 read-write MBOXIEN1 Mailbox Interrupt Enable 1 1 read-write MBOXIEN2 Mailbox Interrupt Enable 2 1 read-write MBOXIEN3 Mailbox Interrupt Enable 3 1 read-write RDMAILBOX1_NS 0 RDMAILBOX1_NS Registers 0xB802C000 0x00000000 0x00001000 registers MSGPTR0 No Description 0x000 read-write 0x00000000 0xFFFFFFFF PTR Pointer 0 32 read-write MSGPTR1 No Description 0x004 read-write 0x00000000 0xFFFFFFFF PTR Pointer 0 32 read-write MSGPTR2 No Description 0x008 read-write 0x00000000 0xFFFFFFFF PTR Pointer 0 32 read-write MSGPTR3 No Description 0x00C read-write 0x00000000 0xFFFFFFFF PTR Pointer 0 32 read-write IF No Description 0x040 read-write 0x00000000 0x0000000F MBOXIF0 Mailbox Interupt Flag 0 1 read-write MBOXIF1 Mailbox Interupt Flag 1 1 read-write MBOXIF2 Mailbox Interupt Flag 2 1 read-write MBOXIF3 Mailbox Interupt Flag 3 1 read-write IEN No Description 0x044 read-write 0x00000000 0x0000000F MBOXIEN0 Mailbox Interrupt Enable 0 1 read-write MBOXIEN1 Mailbox Interrupt Enable 1 1 read-write MBOXIEN2 Mailbox Interrupt Enable 2 1 read-write MBOXIEN3 Mailbox Interrupt Enable 3 1 read-write BUFC_NS 1 BUFC_NS Registers 0xBA000000 0x00000000 0x00001000 registers BUFC 32 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Enable peripheral clock to this module 0 1 read-write LPMODE No Description 0x008 read-write 0x00000000 0x00000003 LPENBYSEQ Low power mode enable from M0p sequencer 0 1 read-write LPENBYM33 Low power mode enable from M33 1 1 read-write BUF0_CTRL No Description 0x00C read-write 0x00000000 0x00000007 SIZE Buffer Size 0 3 read-write SIZE64 Sets Buffer size to 64 bytes 0 SIZE128 Sets Buffer size to 128 bytes 1 SIZE256 Sets Buffer size to 256 bytes 2 SIZE512 Sets Buffer size to 512 bytes 3 SIZE1024 Sets Buffer size to 1024 bytes 4 SIZE2048 Sets Buffer size to 2048 bytes 5 SIZE4096 Sets Buffer size to 4096 bytes 6 BUF0_ADDR No Description 0x010 read-write 0x20000000 0xFFFFFFFC ADDR Buffer Address 2 30 read-write BUF0_WRITEOFFSET No Description 0x014 read-write 0x00000000 0x00001FFF WRITEOFFSET Write Offset 0 13 read-write BUF0_READOFFSET No Description 0x018 read-write 0x00000000 0x00001FFF READOFFSET Read Offset 0 13 read-write BUF0_READDATA No Description 0x020 read-only 0x00000000 0x000000FF READDATA Buffer Read Data 0 8 read-only BUF0_WRITEDATA No Description 0x024 write-only 0x00000000 0x000000FF WRITEDATA Buffer Write Data 0 8 write-only BUF0_XWRITE No Description 0x028 write-only 0x00000000 0x000000FF XORWRITEDATA Buffer XOR Write Data 0 8 write-only BUF0_STATUS No Description 0x02C read-only 0x00000000 0x01111FFF BYTES Number of Bytes in the Buffer 0 13 read-only THRESHOLDFLAG Buffer Threshold Flag 20 1 read-only BUF0_THRESHOLDCTRL No Description 0x030 read-write 0x00000000 0x00002FFF THRESHOLD Buffer Threshold Value 0 12 read-write THRESHOLDMODE Buffer Threshold Mode 13 1 read-write LARGER THRESHOLDIF will be set if BYTES is larger than THRESHOLD 0 LESSOREQUAL THRESHOLDIF will be set if BYTES is less than or equal to THRESHOLD 1 BUF0_CMD No Description 0x034 write-only 0x00000000 0x0000000F CLEAR Buffer Clear 0 1 write-only PREFETCH Prefetch 1 1 write-only BUF0_FIFOASYNC No Description 0x038 write-only 0x00000000 0x00000001 RST Reset ASYNC 0 1 write-only BUF0_READDATA32 No Description 0x03C read-only 0x00000000 0xFFFFFFFF READDATA32 Buffer Read Data 0 32 read-only BUF0_WRITEDATA32 No Description 0x040 write-only 0x00000000 0xFFFFFFFF WRITEDATA32 Buffer Write Data 0 32 write-only BUF0_XWRITE32 No Description 0x044 write-only 0x00000000 0xFFFFFFFF XORWRITEDATA32 Buffer XOR Write Data 0 32 write-only BUF1_CTRL No Description 0x04C read-write 0x00000000 0x00000007 SIZE Buffer Size 0 3 read-write SIZE64 Sets Buffer size to 64 bytes 0 SIZE128 Sets Buffer size to 128 bytes 1 SIZE256 Sets Buffer size to 256 bytes 2 SIZE512 Sets Buffer size to 512 bytes 3 SIZE1024 Sets Buffer size to 1024 bytes 4 SIZE2048 Sets Buffer size to 2048 bytes 5 SIZE4096 Sets Buffer size to 4096 bytes 6 BUF1_ADDR No Description 0x050 read-write 0x20000000 0xFFFFFFFC ADDR Buffer Address 2 30 read-write BUF1_WRITEOFFSET No Description 0x054 read-write 0x00000000 0x00001FFF WRITEOFFSET Write Offset 0 13 read-write BUF1_READOFFSET No Description 0x058 read-write 0x00000000 0x00001FFF READOFFSET Read Offset 0 13 read-write BUF1_READDATA No Description 0x060 read-only 0x00000000 0x000000FF READDATA Buffer Read Data 0 8 read-only BUF1_WRITEDATA No Description 0x064 write-only 0x00000000 0x000000FF WRITEDATA Buffer Write Data 0 8 write-only BUF1_XWRITE No Description 0x068 write-only 0x00000000 0x000000FF XORWRITEDATA Buffer XOR Write Data 0 8 write-only BUF1_STATUS No Description 0x06C read-only 0x00000000 0x01111FFF BYTES Number of Bytes in the Buffer 0 13 read-only THRESHOLDFLAG Buffer Threshold Flag 20 1 read-only BUF1_THRESHOLDCTRL No Description 0x070 read-write 0x00000000 0x00002FFF THRESHOLD Buffer Threshold Value 0 12 read-write THRESHOLDMODE Buffer Threshold Mode 13 1 read-write LARGER THRESHOLDIF will be set if BYTES is larger than THRESHOLD 0 LESSOREQUAL THRESHOLDIF will be set if BYTES is less than or equal to THRESHOLD 1 BUF1_CMD No Description 0x074 write-only 0x00000000 0x0000000F CLEAR Buffer Clear 0 1 write-only PREFETCH Prefetch 1 1 write-only BUF1_FIFOASYNC No Description 0x078 write-only 0x00000000 0x00000001 RST Reset ASYNC 0 1 write-only BUF1_READDATA32 No Description 0x07C read-only 0x00000000 0xFFFFFFFF READDATA32 Buffer Read Data 0 32 read-only BUF1_WRITEDATA32 No Description 0x080 write-only 0x00000000 0xFFFFFFFF WRITEDATA32 Buffer Write Data 0 32 write-only BUF1_XWRITE32 No Description 0x084 write-only 0x00000000 0xFFFFFFFF XORWRITEDATA32 Buffer XOR Write Data 0 32 write-only BUF2_CTRL No Description 0x08C read-write 0x00000000 0x00000007 SIZE Buffer Size 0 3 read-write SIZE64 Sets Buffer size to 64 bytes 0 SIZE128 Sets Buffer size to 128 bytes 1 SIZE256 Sets Buffer size to 256 bytes 2 SIZE512 Sets Buffer size to 512 bytes 3 SIZE1024 Sets Buffer size to 1024 bytes 4 SIZE2048 Sets Buffer size to 2048 bytes 5 SIZE4096 Sets Buffer size to 4096 bytes 6 BUF2_ADDR No Description 0x090 read-write 0x20000000 0xFFFFFFFC ADDR Buffer Address 2 30 read-write BUF2_WRITEOFFSET No Description 0x094 read-write 0x00000000 0x00001FFF WRITEOFFSET Write Offset 0 13 read-write BUF2_READOFFSET No Description 0x098 read-write 0x00000000 0x00001FFF READOFFSET Read Offset 0 13 read-write BUF2_READDATA No Description 0x0A0 read-only 0x00000000 0x000000FF READDATA Buffer Read Data 0 8 read-only BUF2_WRITEDATA No Description 0x0A4 write-only 0x00000000 0x000000FF WRITEDATA Buffer Write Data 0 8 write-only BUF2_XWRITE No Description 0x0A8 write-only 0x00000000 0x000000FF XORWRITEDATA Buffer XOR Write Data 0 8 write-only BUF2_STATUS No Description 0x0AC read-only 0x00000000 0x01111FFF BYTES Number of Bytes in the Buffer 0 13 read-only THRESHOLDFLAG Buffer Threshold Flag 20 1 read-only BUF2_THRESHOLDCTRL No Description 0x0B0 read-write 0x00000000 0x00002FFF THRESHOLD Buffer Threshold Value 0 12 read-write THRESHOLDMODE Buffer Threshold Mode 13 1 read-write LARGER THRESHOLDIF will be set if BYTES is larger than THRESHOLD 0 LESSOREQUAL THRESHOLDIF will be set if BYTES is less than or equal to THRESHOLD 1 BUF2_CMD No Description 0x0B4 write-only 0x00000000 0x0000000F CLEAR Buffer Clear 0 1 write-only PREFETCH Prefetch 1 1 write-only BUF2_FIFOASYNC No Description 0x0B8 write-only 0x00000000 0x00000001 RST Reset ASYNC 0 1 write-only BUF2_READDATA32 No Description 0x0BC read-only 0x00000000 0xFFFFFFFF READDATA32 Buffer Read Data 0 32 read-only BUF2_WRITEDATA32 No Description 0x0C0 write-only 0x00000000 0xFFFFFFFF WRITEDATA32 Buffer Write Data 0 32 write-only BUF2_XWRITE32 No Description 0x0C4 write-only 0x00000000 0xFFFFFFFF XORWRITEDATA32 Buffer XOR Write Data 0 32 write-only BUF3_CTRL No Description 0x0CC read-write 0x00000000 0x00000007 SIZE Buffer Size 0 3 read-write SIZE64 Sets Buffer size to 64 bytes 0 SIZE128 Sets Buffer size to 128 bytes 1 SIZE256 Sets Buffer size to 256 bytes 2 SIZE512 Sets Buffer size to 512 bytes 3 SIZE1024 Sets Buffer size to 1024 bytes 4 SIZE2048 Sets Buffer size to 2048 bytes 5 SIZE4096 Sets Buffer size to 4096 bytes 6 BUF3_ADDR No Description 0x0D0 read-write 0x20000000 0xFFFFFFFC ADDR Buffer Address 2 30 read-write BUF3_WRITEOFFSET No Description 0x0D4 read-write 0x00000000 0x00001FFF WRITEOFFSET Write Offset 0 13 read-write BUF3_READOFFSET No Description 0x0D8 read-write 0x00000000 0x00001FFF READOFFSET Read Offset 0 13 read-write BUF3_READDATA No Description 0x0E0 read-only 0x00000000 0x000000FF READDATA Buffer Read Data 0 8 read-only BUF3_WRITEDATA No Description 0x0E4 write-only 0x00000000 0x000000FF WRITEDATA Buffer Write Data 0 8 write-only BUF3_XWRITE No Description 0x0E8 write-only 0x00000000 0x000000FF XORWRITEDATA Buffer XOR Write Data 0 8 write-only BUF3_STATUS No Description 0x0EC read-only 0x00000000 0x01111FFF BYTES Number of Bytes in the Buffer 0 13 read-only THRESHOLDFLAG Buffer Threshold Flag 20 1 read-only BUF3_THRESHOLDCTRL No Description 0x0F0 read-write 0x00000000 0x00002FFF THRESHOLD Buffer Threshold Value 0 12 read-write THRESHOLDMODE Buffer Threshold Mode 13 1 read-write LARGER THRESHOLDIF will be set if BYTES is larger than THRESHOLD 0 LESSOREQUAL THRESHOLDIF will be set if BYTES is less than or equal to THRESHOLD 1 BUF3_CMD No Description 0x0F4 write-only 0x00000000 0x0000000F CLEAR Buffer Clear 0 1 write-only PREFETCH Prefetch 1 1 write-only BUF3_FIFOASYNC No Description 0x0F8 write-only 0x00000000 0x00000001 RST Reset ASYNC 0 1 write-only BUF3_READDATA32 No Description 0x0FC read-only 0x00000000 0xFFFFFFFF READDATA32 Buffer Read Data 0 32 read-only BUF3_WRITEDATA32 No Description 0x100 write-only 0x00000000 0xFFFFFFFF WRITEDATA32 Buffer Write Data 0 32 write-only BUF3_XWRITE32 No Description 0x104 write-only 0x00000000 0xFFFFFFFF XORWRITEDATA32 Buffer XOR Write Data 0 32 write-only IF No Description 0x114 read-write 0x00000000 0x9F1F1F1F BUF0OF Buffer 0 Overflow 0 1 read-write BUF0UF Buffer 0 Underflow 1 1 read-write BUF0THR Buffer 0 Threshold Event 2 1 read-write BUF0CORR Buffer 0 Corrupt 3 1 read-write BUF0NWA Buffer 0 Not Word-Aligned 4 1 read-write BUF1OF Buffer 1 Overflow 8 1 read-write BUF1UF Buffer 1 Underflow 9 1 read-write BUF1THR Buffer 1 Threshold Event 10 1 read-write BUF1CORR Buffer 1 Corrupt 11 1 read-write BUF1NWA Buffer 1 Not Word-Aligned 12 1 read-write BUF2OF Buffer 2 Overflow 16 1 read-write BUF2UF Buffer 2 Underflow 17 1 read-write BUF2THR Buffer 2 Threshold Event 18 1 read-write BUF2CORR Buffer 2 Corrupt 19 1 read-write BUF2NWA Buffer 2 Not Word-Aligned 20 1 read-write BUF3OF Buffer 3 Overflow 24 1 read-write BUF3UF Buffer 3 Underflow 25 1 read-write BUF3THR Buffer 3 Threshold Event 26 1 read-write BUF3CORR Buffer 3 Corrupt 27 1 read-write BUF3NWA Buffer 3 Not Word-Aligned 28 1 read-write BUSERROR Bus Error 31 1 read-write IEN No Description 0x118 read-write 0x00000000 0x9F1F1F1F BUF0OF BUF0OF Interrupt Enable 0 1 read-write BUF0UF BUF0UF Interrupt Enable 1 1 read-write BUF0THR BUF0THR Interrupt Enable 2 1 read-write BUF0CORR BUF0CORR Interrupt Enable 3 1 read-write BUF0NWA BUF0NWA Interrupt Enable 4 1 read-write BUF1OF BUF1OF Interrupt Enable 8 1 read-write BUF1UF BUF1UF Interrupt Enable 9 1 read-write BUF1THR BUF1THR Interrupt Enable 10 1 read-write BUF1CORR BUF1CORR Interrupt Enable 11 1 read-write BUF1NWA BUF1NWA Interrupt Enable 12 1 read-write BUF2OF BUF2OF Interrupt Enable 16 1 read-write BUF2UF BUF2UF Interrupt Enable 17 1 read-write BUF2THR BUF2THR Interrupt Enable 18 1 read-write BUF2CORR BUF2CORR Interrupt Enable 19 1 read-write BUF2NWA BUF2NWA Interrupt Enable 20 1 read-write BUF3OF BUF3OF Interrupt Enable 24 1 read-write BUF3UF BUF3UF Interrupt Enable 25 1 read-write BUF3THR BUF3THR Interrupt Enable 26 1 read-write BUF3CORR BUF3CORR Interrupt Enable 27 1 read-write BUF3NWA BUF3NWA Interrupt Enable 28 1 read-write BUSERROR BUSERROR Interrupt Enable 31 1 read-write SEQIF No Description 0x11C read-write 0x00000000 0x9F1F1F1F BUF0OF Buffer 0 Overflow 0 1 read-write BUF0UF Buffer 0 Underflow 1 1 read-write BUF0THR Buffer 0 Threshold Event 2 1 read-write BUF0CORR Buffer 0 Corrupt 3 1 read-write BUF0NWA Buffer 0 Not Word-Aligned 4 1 read-write BUF1OF Buffer 1 Overflow 8 1 read-write BUF1UF Buffer 1 Underflow 9 1 read-write BUF1THR Buffer 1 Threshold Event 10 1 read-write BUF1CORR Buffer 1 Corrupt 11 1 read-write BUF1NWA Buffer 1 Not Word-Aligned 12 1 read-write BUF2OF Buffer 2 Overflow 16 1 read-write BUF2UF Buffer 2 Underflow 17 1 read-write BUF2THR Buffer 2 Threshold Event 18 1 read-write BUF2CORR Buffer 2 Corrupt 19 1 read-write BUF2NWA Buffer 2 Not Word-Aligned 20 1 read-write BUF3OF Buffer 3 Overflow 24 1 read-write BUF3UF Buffer 3 Underflow 25 1 read-write BUF3THR Buffer 3 Threshold Event 26 1 read-write BUF3CORR Buffer 3 Corrupt 27 1 read-write BUF3NWA Buffer 3 Not Word-Aligned 28 1 read-write BUSERROR Bus Error 31 1 read-write SEQIEN No Description 0x120 read-write 0x00000000 0x9F1F1F1F BUF0OF BUF0OF Interrupt Enable 0 1 read-write BUF0UF BUF0UF Interrupt Enable 1 1 read-write BUF0THR BUF0THR Interrupt Enable 2 1 read-write BUF0CORR BUF0CORR Interrupt Enable 3 1 read-write BUF0NWA BUF0NWA Interrupt Enable 4 1 read-write BUF1OF BUF1OF Interrupt Enable 8 1 read-write BUF1UF BUF1UF Interrupt Enable 9 1 read-write BUF1THR BUF1THR Interrupt Enable 10 1 read-write BUF1CORR BUF1CORR Interrupt Enable 11 1 read-write BUF1NWA BUF1NWA Interrupt Enable 12 1 read-write BUF2OF BUF2OF Interrupt Enable 16 1 read-write BUF2UF BUF2UF Interrupt Enable 17 1 read-write BUF2THR BUF2THR Interrupt Enable 18 1 read-write BUF2CORR BUF2CORR Interrupt Enable 19 1 read-write BUF2NWA BUF2NWA Interrupt Enable 20 1 read-write BUF3OF BUF3OF Interrupt Enable 24 1 read-write BUF3UF BUF3UF Interrupt Enable 25 1 read-write BUF3THR BUF3THR Interrupt Enable 26 1 read-write BUF3CORR BUF3CORR Interrupt Enable 27 1 read-write BUF3NWA BUF3NWA Interrupt Enable 28 1 read-write BUSERROR BUSERROR Interrupt Enable 31 1 read-write DEVINFO 1 DEVINFO Registers 0x0FE08000 0x00000000 0x00001000 registers INFO Version of the device info structure being used 0x000 read-only 0x07000000 0xFFFFFFFF CRC CRC 0 16 read-only PRODREV Production Revision 16 8 read-only DEVINFOREV DI Page Version 24 8 read-only PART Part description 0x004 read-only 0x00000000 0x3F3FFFFF DEVICENUM Device Number 0 16 read-only FAMILYNUM Device Family 16 6 read-only FAMILY Device Family 24 6 read-only FG Flex Gecko 0 MG Mighty Gecko 1 BG Blue Gecko 2 PG Pearl Gecko 5 MEMINFO Flash page size and misc. chip information 0x008 read-only 0x00000000 0xFFFFFFFF FLASHPAGESIZE Flash Page Size 0 8 read-only UDPAGESIZE User Data Page Size 8 8 read-only DILEN Length of DI Page 16 16 read-only MSIZE Flash and SRAM Memory size in kB 0x00C read-only 0x00000000 0x07FFFFFF FLASH Flash Size 0 16 read-only SRAM Sram Size 16 11 read-only PKGINFO Miscellaneous device information 0x010 read-only 0x00000000 0x00FFFFFF TEMPGRADE Temperature Grade 0 8 read-only N40TO85 -40 to 85 degC 0 N40TO125 -40 to 125 degC 1 N40TO105 -40 to 105 degC 2 N0TO70 0 to 70 degC 3 PKGTYPE Package Type 8 8 read-only WLCSP WLCSP package 74 BGA BGA package 76 QFN QFN package 77 QFP QFP package 81 PINCOUNT Pin Count 16 8 read-only CUSTOMINFO Custom information 0x014 read-only 0x00000000 0xFFFF0000 PARTNO Part Number 16 16 read-only SWFIX Used to track s/w workaround info 0x018 read-only 0xFFFFFFFF 0xFFFFFFFF RSV Reserved 0 32 read-only SWCAPA0 Software Capability Vector 0 0x01C read-only 0x00000000 0x00333333 ZIGBEE Zigbee Capability 0 2 read-only LEVEL0 Zigbee stack capability not available 0 LEVEL1 Green Power only 1 LEVEL2 Zigbee and Green Power 2 LEVEL3 Zigbee Only 3 THREAD Thread Capability 4 2 read-only LEVEL0 Thread stack capability not available 0 LEVEL1 Thread stack enabled 1 LEVEL2 N/A 2 LEVEL3 N/A 3 RF4CE RF4CE Capability 8 2 read-only LEVEL0 RF4CE stack capability not available 0 LEVEL1 RF4CE stack enabled 1 LEVEL2 N/A 2 LEVEL3 N/A 3 BTSMART Bluetooth Smart Capability 12 2 read-only LEVEL0 Bluetooth SMART stack capability not available 0 LEVEL1 Bluetooth SMART enabled 1 LEVEL2 N/A 2 LEVEL3 N/A 3 CONNECT Connect Capability 16 2 read-only LEVEL0 Connect stack capability not available 0 LEVEL1 Connect enabled 1 LEVEL2 N/A 2 LEVEL3 N/A 3 SRI RAIL Capability 20 2 read-only LEVEL0 RAIL capability not available 0 LEVEL1 RAIL enabled 1 LEVEL2 N/A 2 LEVEL3 N/A 3 SWCAPA1 Software Capability Vector 1 0x020 read-only 0x00000000 0x00000007 RFMCUEN RF-MCU 0 1 read-only NCPEN NCP 1 1 read-only GWEN Gateway 2 1 read-only EXTINFO External component description 0x028 read-only 0x00000000 0x00FFFFFF TYPE Type 0 8 read-only NONE 255 CONNECTION Connection 8 8 read-only SPI SPI control interface 0 NONE No interface 255 REV Revision 16 8 read-only EUI48L MA-L compliant EUI48 OUI (low bits) and Unique Identifier (24-bit) 0x040 read-only 0x00000000 0xFFFFFFFF UNIQUEID Unique ID 0 24 read-only OUI48L OUI48L 24 8 read-only EUI48H MA-L compliant EUI48 OUI (high bits) 0x044 read-only 0xFFFF0000 0xFFFFFFFF OUI48H OUI48H 0 16 read-only RESERVED RESERVED 16 16 read-only EUI64L MA-L compliant EUI64 Unique Identifier (low bits) 0x048 read-only 0x00000000 0xFFFFFFFF UNIQUEL UNIQUEL 0 32 read-only EUI64H MA-L compliant EUI64 OUI and Unique Identifier (high bits) 0x04C read-only 0x00000000 0xFFFFFFFF UNIQUEH UNIQUEH 0 8 read-only OUI64 OUI64 8 24 read-only CALTEMP Calibration Temperature Information 0x050 read-only 0x00000000 0x000000FF TEMP Cal Temp 0 8 read-only EMUTEMP EMU Temperature Sensor Calibration 0x054 read-only 0x00000000 0x1FFF07FC EMUTEMPROOM Emu Room Temperature 2 9 read-only HFRCODPLLCAL0 HFRCODPLL Calibration 0x058 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL1 HFRCODPLL Calibration 0x05C read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL2 HFRCODPLL Calibration 0x060 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL3 HFRCODPLL Calibration 0x064 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL4 HFRCODPLL Calibration 0x068 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL5 HFRCODPLL Calibration 0x06C read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL6 HFRCODPLL Calibration 0x070 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL7 HFRCODPLL Calibration 0x074 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL8 HFRCODPLL Calibration 0x078 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL9 HFRCODPLL Calibration 0x07C read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL10 HFRCODPLL Calibration 0x080 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL11 HFRCODPLL Calibration 0x084 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL12 HFRCODPLL Calibration 0x088 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL13 HFRCODPLL Calibration 0x08C read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL14 HFRCODPLL Calibration 0x090 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL15 HFRCODPLL Calibration 0x094 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL16 HFRCODPLL Calibration 0x098 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL17 HFRCODPLL Calibration 0x09C read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only MODULENAME0 Characters 1-4 of Module Name stored as a null terminated string 0x130 read-only 0xFFFFFFFF 0xFFFFFFFF MODCHAR1 0 8 read-only MODCHAR2 8 8 read-only MODCHAR3 16 8 read-only MODCHAR4 24 8 read-only MODULENAME1 Characters 5-8 of Module Name stored as a null terminated string 0x134 read-only 0xFFFFFFFF 0xFFFFFFFF MODCHAR5 0 8 read-only MODCHAR6 8 8 read-only MODCHAR7 16 8 read-only MODCHAR8 24 8 read-only MODULENAME2 Characters 9-12 of Module Name stored as a null terminated string 0x138 read-only 0xFFFFFFFF 0xFFFFFFFF MODCHAR9 0 8 read-only MODCHAR10 8 8 read-only MODCHAR11 16 8 read-only MODCHAR12 24 8 read-only MODULENAME3 Characters 13-16 of Module Name stored as a null terminated string 0x13C read-only 0xFFFFFFFF 0xFFFFFFFF MODCHAR13 0 8 read-only MODCHAR14 8 8 read-only MODCHAR15 16 8 read-only MODCHAR16 24 8 read-only MODULENAME4 Characters 17-20 of Module Name stored as a null terminated string 0x140 read-only 0xFFFFFFFF 0xFFFFFFFF MODCHAR17 0 8 read-only MODCHAR18 8 8 read-only MODCHAR19 16 8 read-only MODCHAR20 24 8 read-only MODULENAME5 Characters 21-24 of Module Name stored as a null terminated string 0x144 read-only 0xFFFFFFFF 0xFFFFFFFF MODCHAR21 0 8 read-only MODCHAR22 8 8 read-only MODCHAR23 16 8 read-only MODCHAR24 24 8 read-only MODULENAME6 Characters 25-26 of Module Name stored as a null terminated string 0x148 read-only 0xFFFFFFFF 0xFFFFFFFF MODCHAR25 0 8 read-only MODCHAR26 8 8 read-only RSV 16 16 read-only MODULEINFO Module Information 0x14C read-only 0xFFFFFFFF 0xFFFFFFFF HWREV 0 5 read-only ANTENNA 5 3 read-only BUILTIN Built-in Antenna 0 CONNECTOR RF Connector 1 RFPAD RF Pad 2 INVERTEDF F-invert PCB 3 MODNUMBER 8 7 read-only TYPE 15 1 read-only PCB PCB 0 SIP SIP 1 LFXO 16 1 read-only NONE LFXO is not installed 0 PRESENT LFXO is installed 1 EXPRESS 17 1 read-only SUPPORTED Blue Gecko Express is supported 0 NONE Blue Gecko Express is not supported 1 LFXOCALVAL 18 1 read-only VALID LFXO Tuning in MODXOCAL is valid 0 NOTVALID LFXO Tuning value in MODXOCAL is not valid 1 HFXOCALVAL 19 1 read-only VALID HFXO calibration in MODXOCAL is valid 0 NOTVALID HFXO calibration in MODXOCAL is not valid 1 MODNUMBERMSB 20 9 read-only PADCDC 29 1 read-only VDCDC PAVDD connected to Vdcdc 0 OTHER PAVDD connected to Vdd or other 1 PHYLIMITED 30 1 read-only LIMITED 0 UNLIMITED 1 EXTVALID 31 1 read-only EXTUSED EXT used 0 EXTUNUSED EXT not used 1 MODXOCAL Module Crystal Oscillator Calibration 0x150 read-only 0x007FFFFF 0x007FFFFF HFXOCTUNEXIANA 0 8 read-only HFXOCTUNEXOANA 8 8 read-only LFXOCAPTUNE 16 7 read-only IADC0GAIN0 IADC0 Gain Calibration Info 0x180 read-only 0x00000000 0xFFFFFFFF GAINCANA1 0 16 read-only GAINCANA2 16 16 read-only IADC0GAIN1 IADC0 Gain Calibration Info 0x184 read-only 0x00000000 0xFFFFFFFF GAINCANA3 0 16 read-only GAINCANA4 16 16 read-only IADC0OFFSETCAL0 IADC0 Offset Calibration Info 0x188 read-only 0x00000000 0xFFFFFFFF OFFSETANABASE 0 16 read-only OFFSETANA1HIACC 16 16 read-only IADC0NORMALOFFSETCAL0 IADC0 Normal Offset Calibration Info 0x18C read-only 0x00000000 0xFFFFFFFF OFFSETANA1NORM 0 16 read-only OFFSETANA2NORM 16 16 read-only IADC0NORMALOFFSETCAL1 IADC0 Normal Offset Calibration Info 0x190 read-only 0x00000000 0x0000FFFF OFFSETANA3NORM 0 16 read-only IADC0HISPDOFFSETCAL0 IADC High Speed Offset Calibration Info 0x194 read-only 0x00000000 0xFFFFFFFF OFFSETANA1HISPD 0 16 read-only OFFSETANA2HISPD 16 16 read-only IADC0HISPDOFFSETCAL1 IADC High Speed Offset Calibration Info 0x198 read-only 0x00000000 0x0000FFFF OFFSETANA3HISPD 0 16 read-only LEGACY This is the legacy device detection information for tools compatability 0x1FC read-only 0x00800000 0x00FF0000 DEVICEFAMILY Device Family 16 8 read-only EFR32MG1P EFR32 Mighty Gecko Family Series 1 Device Config 1 16 EFR32MG1B EFR32 Mighty Gecko Family Series 1 Device Config 1 17 EFR32MG1V EFR32 Mighty Gecko Family Series 1 Device Config 1 18 EFR32BG1P EFR32 Blue Gecko Family Series 1 Device Config 1 19 EFR32BG1B EFR32 Blue Gecko Family Series 1 Device Config 1 20 EFR32BG1V EFR32 Blue Gecko Family Series 1 Device Config 1 21 EFR32FG1P EFR32 Flex Gecko Family Series 1 Device Config 1 25 EFR32FG1B EFR32 Flex Gecko Family Series 1 Device Config 1 26 EFR32FG1V EFR32 Flex Gecko Family Series 1 Device Config 1 27 EFR32MG12P EFR32 Mighty Gecko Family Series 1 Device Config 2 28 EFR32MG12B EFR32 Mighty Gecko Family Series 1 Device Config 2 29 EFR32MG12V EFR32 Mighty Gecko Family Series 1 Device Config 2 30 EFR32BG12P EFR32 Blue Gecko Family Series 1 Device Config 2 31 EFR32BG12B EFR32 Blue Gecko Family Series 1 Device Config 2 32 EFR32BG12V EFR32 Blue Gecko Family Series 1 Device Config 2 33 EFR32FG12P EFR32 Flex Gecko Family Series 1 Device Config 2 37 EFR32FG12B EFR32 Flex Gecko Family Series 1 Device Config 2 38 EFR32FG12V EFR32 Flex Gecko Family Series 1 Device Config 2 39 EFR32MG13P EFR32 Mighty Gecko Family Series 13 Device Config 3 40 EFR32MG13B EFR32 Mighty Gecko Family Series 13 Device Config 3 41 EFR32MG13V EFR32 Mighty Gecko Family Series 1 Device Config 3 42 EFR32BG13P EFR32 Blue Gecko Family Series 1 Device Config 3 43 EFR32BG13B EFR32 Blue Gecko Family Series 1 Device Config 3 44 EFR32BG13V EFR32 Blue Gecko Family Series 1 Device Config 3 45 EFR32FG13P EFR32 Flex Gecko Family Series 1 Device Config 3 49 EFR32FG13B EFR32 Flex Gecko Family Series 1 Device Config 3 50 EFR32FG13V EFR32 Flex Gecko Family Series 1 Device Config 3 51 EFR32MG14P EFR32 Mighty Gecko Family Series 1 Device Config 4 52 EFR32MG14B EFR32 Mighty Gecko Family Series 1 Device Config 4 53 EFR32MG14V EFR32 Mighty Gecko Family Series 1 Device Config 4 54 EFR32BG14P EFR32 Blue Gecko Family Series 1 Device Config 4 55 EFR32BG14B EFR32 Blue Gecko Family Series 1 Device Config 4 56 EFR32BG14V EFR32 Blue Gecko Family Series 1 Device Config 4 57 EFR32FG14P EFR32 Flex Gecko Family Series 1 Device Config 4 61 EFR32FG14B EFR32 Flex Gecko Family Series 1 Device Config 4 62 EFR32FG14V EFR32 Flex Gecko Family Series 1 Device Config 4 63 EFM32G EFM32 Gecko Device Family 71 EFM32GG EFM32 Giant Gecko Device Family 72 EFM32TG EFM32 Tiny Gecko Device Family 73 EFM32LG EFM32 Leopard Gecko Device Family 74 EFM32WG EFM32 Wonder Gecko Device Family 75 EFM32ZG EFM32 Zero Gecko Device Family 76 EFM32HG EFM32 Happy Gecko Device Family 77 EFM32PG1B EFM32 Pearl Gecko Device Family Series 1 Device Config 1 81 EFM32JG1B EFM32 Jade Gecko Device Family Series 1 Device Config 1 83 EFM32PG12B EFM32 Pearl Gecko Device Family Series 1 Device Config 2 85 EFM32JG12B EFM32 Jade Gecko Device Family Series 1 Device Config 2 87 EFM32PG13B EFM32 Pearl Gecko Device Family Series 1 Device Config 3 89 EFM32JG13B EFM32 Jade Gecko Device Family Series 1 Device Config 3 91 EFM32GG11B EFM32 Giant Gecko Device Family Series 1 Device Config 1 100 EFM32TG11B EFM32 Giant Gecko Device Family Series 1 Device Config 1 103 EZR32LG EZR32 Leopard Gecko Device Family 120 EZR32WG EZR32 Wonder Gecko Device Family 121 EZR32HG EZR32 Happy Gecko Device Family 122 SERIES2V0 DI page is encoded with the series 2 layout. Check alternate location. 128 RTHERM Thermistor Calibrated Internal Resistance 0x25C read-only 0x00000000 0x0000FFFF RTHERM 0 16 read-only Copyright 2018 Silicon Laboratories, Inc. 0x00000000 0x00080000 rx 0x0FE00000 0x00000400 rx 0x0FE08000 0x00000400 rx 0x0FE0E000 0x00000600 rx 0x20000000 0x00008000 rwx 0x4C024000 0x00004000 rwx 0x4C028000 0x00001000 rwx 0x5C024000 0x00004000 rwx 0x5C028000 0x00001000 rwx 0xA0000000 0x00004000 rwx 0xA0004000 0x00001000 rwx 0xB0000000 0x00004000 rwx 0xB0004000 0x00001000 rwx