STM32L15xC 1.0 STM32L15xC 8 32 0x20 0x0 0xFFFFFFFF C_ADC Common ADC registers ADC 0x40012700 0x0 0x400 registers CSR CSR ADC Common status register 0x0 0x20 read-only 0x00000000 ADONS1 ADON Status of ADC 6 1 OVR1 Overrun flag of ADC 1 5 1 STRT1 Regular channel Start flag of ADC 1 4 1 JSTRT1 Injected channel Start flag of ADC 1 3 1 JEOC1 Injected channel end of conversion of ADC 1 2 1 EOC1 End of conversion of ADC 1 1 1 AWD1 Analog watchdog flag of ADC 1 0 1 CCR CCR ADC common control register 0x4 0x20 read-write 0x00000000 TSVREFE Temperature sensor and VREFINT enable 23 1 ADCPRE ADC prescaler 16 2 COMP Comparators COMP 0x40007C00 0x0 0x400 registers COMP_CA Comparator wakeup through EXTI line (21 and 22) interrupt/Channel acquisition interrupt 22 COMP_ACQ Comparator Channel Acquisition 53 CSR CSR comparator control and status register 0x0 0x20 0x00000000 TSUSP Suspend Timer Mode 31 1 read-write CAIF Channel acquisition interrupt flag 30 1 read-only CAIE Channel Acquisition Interrupt Enable / Clear 29 1 read-write RCH13 Select GPIO port PC3 as re-routed ADC input channel CH13. 28 1 read-write FCH8 Select GPIO port PB0 as fast ADC input channel CH8. 27 1 read-write FCH3 Select GPIO port PA3 as fast ADC input channel CH3. 26 1 read-write OUTSEL Comparator 2 output selection 21 3 read-write INSEL Inverted input selection 18 3 read-write WNDWE Window mode enable 17 1 read-write VREFOUTEN VREFINT output enable 16 1 read-write CMP2OUT Comparator 2 output 13 1 read-only SPEED Comparator 2 speed mode 12 1 read-write CMP1OUT Comparator 1 output 7 1 read-only SW1 SW1 analog switch enable 5 1 read-write CMP1EN Comparator 1 enable 4 1 read-write PD400K 400 kO pull-down resistor 3 1 read-write PD10K 10 kO pull-down resistor 2 1 read-write PU400K 400 kO pull-up resistor 1 1 read-write PU10K 10 kO pull-up resistor 0 1 read-write CRC CRC calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF Data_register Data Register 0 32 IDR IDR Independent data register 0x4 0x20 read-write 0x00000000 Independent_data_register Independent data register 0 7 CR CR Control register 0x8 0x20 write-only 0x00000000 RESET RESET 0 1 DAC Digital-to-analog converter DAC 0x40007400 0x0 0x400 registers DAC DAC interrupt 21 CR CR control register 0x0 0x20 read-write 0x00000000 DMAUDRIE2 DAC channel2 DMA underrun interrupt enable 29 1 DMAEN2 DAC channel2 DMA enable 28 1 MAMP2 DAC channel2 mask/amplitude selector 24 4 WAVE2 DAC channel2 noise/triangle wave generation enable 22 2 TSEL2 DAC channel2 trigger selection 19 3 TEN2 DAC channel2 trigger enable 18 1 BOFF2 DAC channel2 output buffer disable 17 1 EN2 DAC channel2 enable 16 1 DMAUDRIE1 DAC channel1 DMA Underrun Interrupt enable 13 1 DMAEN1 DAC channel1 DMA enable 12 1 MAMP1 DAC channel1 mask/amplitude selector 8 4 WAVE1 DAC channel1 noise/triangle wave generation enable 6 2 TSEL1 DAC channel1 trigger selection 3 3 TEN1 DAC channel1 trigger enable 2 1 BOFF1 DAC channel1 output buffer disable 1 1 EN1 DAC channel1 enable 0 1 SWTRIGR SWTRIGR software trigger register 0x4 0x20 write-only 0x00000000 SWTRIG2 DAC channel2 software trigger 1 1 SWTRIG1 DAC channel1 software trigger 0 1 DHR12R1 DHR12R1 channel1 12-bit right-aligned data holding register 0x8 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit right-aligned data 0 12 DHR12L1 DHR12L1 channel1 12-bit left aligned data holding register 0xC 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit left-aligned data 4 12 DHR8R1 DHR8R1 channel1 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 DACC1DHR DAC channel1 8-bit right-aligned data 0 8 DHR12R2 DHR12R2 channel2 12-bit right aligned data holding register 0x14 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit right-aligned data 0 12 DHR12L2 DHR12L2 channel2 12-bit left aligned data holding register 0x18 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit left-aligned data 4 12 DHR8R2 DHR8R2 channel2 8-bit right-aligned data holding register 0x1C 0x20 read-write 0x00000000 DACC2DHR DAC channel2 8-bit right-aligned data 0 8 DHR12RD DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit right-aligned data 16 12 DACC1DHR DAC channel1 12-bit right-aligned data 0 12 DHR12LD DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit left-aligned data 20 12 DACC1DHR DAC channel1 12-bit left-aligned data 4 12 DHR8RD DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 DACC2DHR DAC channel2 8-bit right-aligned data 8 8 DACC1DHR DAC channel1 8-bit right-aligned data 0 8 DOR1 DOR1 channel1 data output register 0x2C 0x20 read-only 0x00000000 DACC1DOR DAC channel1 data output 0 12 DOR2 DOR2 channel2 data output register 0x30 0x20 read-only 0x00000000 DACC2DOR DAC channel2 data output 0 12 SR SR status register 0x34 0x20 read-write 0x00000000 DMAUDR2 DAC channel2 DMA underrun flag 29 1 DMAUDR1 DAC channel1 DMA underrun flag 13 1 DMA1 Direct memory access controller DMA 0x40026000 0x0 0x400 registers DMA1_Channel1 DMA1 Channel1 global interrupt 11 DMA1_Channel2 DMA1 Channel2 global interrupt 12 DMA1_Channel3 DMA1 Channel3 global interrupt 13 DMA1_Channel4 DMA1 Channel4 global interrupt 14 DMA1_Channel5 DMA1 Channel5 global interrupt 15 DMA1_Channel6 DMA1 Channel6 global interrupt 16 DMA1_Channel7 DMA1 Channel7 global interrupt 17 ISR ISR interrupt status register 0x0 0x20 read-only 0x00000000 TEIF7 Channel x transfer error flag (x = 1 ..7) 27 1 HTIF7 Channel x half transfer flag (x = 1 ..7) 26 1 TCIF7 Channel x transfer complete flag (x = 1 ..7) 25 1 GIF7 Channel x global interrupt flag (x = 1 ..7) 24 1 TEIF6 Channel x transfer error flag (x = 1 ..7) 23 1 HTIF6 Channel x half transfer flag (x = 1 ..7) 22 1 TCIF6 Channel x transfer complete flag (x = 1 ..7) 21 1 GIF6 Channel x global interrupt flag (x = 1 ..7) 20 1 TEIF5 Channel x transfer error flag (x = 1 ..7) 19 1 HTIF5 Channel x half transfer flag (x = 1 ..7) 18 1 TCIF5 Channel x transfer complete flag (x = 1 ..7) 17 1 GIF5 Channel x global interrupt flag (x = 1 ..7) 16 1 TEIF4 Channel x transfer error flag (x = 1 ..7) 15 1 HTIF4 Channel x half transfer flag (x = 1 ..7) 14 1 TCIF4 Channel x transfer complete flag (x = 1 ..7) 13 1 GIF4 Channel x global interrupt flag (x = 1 ..7) 12 1 TEIF3 Channel x transfer error flag (x = 1 ..7) 11 1 HTIF3 Channel x half transfer flag (x = 1 ..7) 10 1 TCIF3 Channel x transfer complete flag (x = 1 ..7) 9 1 GIF3 Channel x global interrupt flag (x = 1 ..7) 8 1 TEIF2 Channel x transfer error flag (x = 1 ..7) 7 1 HTIF2 Channel x half transfer flag (x = 1 ..7) 6 1 TCIF2 Channel x transfer complete flag (x = 1 ..7) 5 1 GIF2 Channel x global interrupt flag (x = 1 ..7) 4 1 TEIF1 Channel x transfer error flag (x = 1 ..7) 3 1 HTIF1 Channel x half transfer flag (x = 1 ..7) 2 1 TCIF1 Channel x transfer complete flag (x = 1 ..7) 1 1 GIF1 Channel x global interrupt flag (x = 1 ..7) 0 1 IFCR IFCR interrupt flag clear register 0x4 0x20 write-only 0x00000000 CTEIF7 Channel x transfer error clear (x = 1 ..7) 27 1 CHTIF7 Channel x half transfer clear (x = 1 ..7) 26 1 CTCIF7 Channel x transfer complete clear (x = 1 ..7) 25 1 CGIF7 Channel x global interrupt clear (x = 1 ..7) 24 1 CTEIF6 Channel x transfer error clear (x = 1 ..7) 23 1 CHTIF6 Channel x half transfer clear (x = 1 ..7) 22 1 CTCIF6 Channel x transfer complete clear (x = 1 ..7) 21 1 CGIF6 Channel x global interrupt clear (x = 1 ..7) 20 1 CTEIF5 Channel x transfer error clear (x = 1 ..7) 19 1 CHTIF5 Channel x half transfer clear (x = 1 ..7) 18 1 CTCIF5 Channel x transfer complete clear (x = 1 ..7) 17 1 CGIF5 Channel x global interrupt clear (x = 1 ..7) 16 1 CTEIF4 Channel x transfer error clear (x = 1 ..7) 15 1 CHTIF4 Channel x half transfer clear (x = 1 ..7) 14 1 CTCIF4 Channel x transfer complete clear (x = 1 ..7) 13 1 CGIF4 Channel x global interrupt clear (x = 1 ..7) 12 1 CTEIF3 Channel x transfer error clear (x = 1 ..7) 11 1 CHTIF3 Channel x half transfer clear (x = 1 ..7) 10 1 CTCIF3 Channel x transfer complete clear (x = 1 ..7) 9 1 CGIF3 Channel x global interrupt clear (x = 1 ..7) 8 1 CTEIF2 Channel x transfer error clear (x = 1 ..7) 7 1 CHTIF2 Channel x half transfer clear (x = 1 ..7) 6 1 CTCIF2 Channel x transfer complete clear (x = 1 ..7) 5 1 CGIF2 Channel x global interrupt clear (x = 1 ..7) 4 1 CTEIF1 Channel x transfer error clear (x = 1 ..7) 3 1 CHTIF1 Channel x half transfer clear (x = 1 ..7) 2 1 CTCIF1 Channel x transfer complete clear (x = 1 ..7) 1 1 CGIF1 Channel x global interrupt clear (x = 1 ..7) 0 1 CCR1 CCR1 channel x configuration register 0x8 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 CNDTR1 CNDTR1 channel x number of data register 0xC 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR1 CPAR1 channel x peripheral address register 0x10 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR1 CMAR1 channel x memory address register 0x14 0x20 read-write 0x00000000 MA Memory address 0 32 CCR2 CCR2 channel x configuration register 0x1C 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 CNDTR2 CNDTR2 channel x number of data register 0x20 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR2 CPAR2 channel x peripheral address register 0x24 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR2 CMAR2 channel x memory address register 0x28 0x20 read-write 0x00000000 MA Memory address 0 32 CCR3 CCR3 channel x configuration register 0x30 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 CNDTR3 CNDTR3 channel x number of data register 0x34 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR3 CPAR3 channel x peripheral address register 0x38 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR3 CMAR3 channel x memory address register 0x3C 0x20 read-write 0x00000000 MA Memory address 0 32 CCR4 CCR4 channel x configuration register 0x44 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 CNDTR4 CNDTR4 channel x number of data register 0x48 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR4 CPAR4 channel x peripheral address register 0x4C 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR4 CMAR4 channel x memory address register 0x50 0x20 read-write 0x00000000 MA Memory address 0 32 CCR5 CCR5 channel x configuration register 0x58 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 CNDTR5 CNDTR5 channel x number of data register 0x5C 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR5 CPAR5 channel x peripheral address register 0x60 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR5 CMAR5 channel x memory address register 0x64 0x20 read-write 0x00000000 MA Memory address 0 32 CCR6 CCR6 channel x configuration register 0x6C 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 CNDTR6 CNDTR6 channel x number of data register 0x70 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR6 CPAR6 channel x peripheral address register 0x74 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR6 CMAR6 channel x memory address register 0x78 0x20 read-write 0x00000000 MA Memory address 0 32 CCR7 CCR7 channel x configuration register 0x80 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 CNDTR7 CNDTR7 channel x number of data register 0x84 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR7 CPAR7 channel x peripheral address register 0x88 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR7 CMAR7 channel x memory address register 0x8C 0x20 read-write 0x00000000 MA Memory address 0 32 DMA2 0x40026400 DMA2_CH1 DMA2 Channel 1 interrupt 47 DMA2_CH2 DMA2 Channel 2 interrupt 48 DMA2_CH3 DMA2 Channel 3 interrupt 49 DMA2_CH4 DMA2 Channel 4 interrupt 50 DMA2_CH5 DMA2 Channel 5 interrupt 51 EXTI External interrupt/event controller EXTI 0x40010400 0x0 0x400 registers TAMPER_STAMP Tamper and TimeStamp through EXTI line interrupts 2 EXTI0 EXTI Line0 interrupt 6 EXTI1 EXTI Line1 interrupt 7 EXTI2 EXTI Line2 interrupt 8 EXTI3 EXTI Line3 interrupt 9 EXTI4 EXTI Line4 interrupt 10 EXTI9_5 EXTI Line[9:5] interrupts 23 EXTI15_10 EXTI Line[15:10] interrupts 40 IMR IMR IMR 0x0 0x20 read-write 0x00000000 MR Interrupt mask on line x 0 23 EMR EMR EMR 0x4 0x20 read-write 0x00000000 MR Event mask on line x 0 23 RTSR RTSR RTSR 0x8 0x20 read-write 0x00000000 TR Rising edge trigger event configuration bit of line x 0 23 FTSR FTSR FTSR 0xC 0x20 read-write 0x00000000 TR Falling edge trigger event configuration bit of line x 0 23 SWIER SWIER SWIER 0x10 0x20 read-write 0x00000000 SWIER Software interrupt on line x 0 23 PR PR PR 0x14 0x20 read-write 0x00000000 PR Pending bit 0 23 Flash Flash Flash 0x40023C00 0x0 0x400 registers FLASH Flash global interrupt 4 ACR ACR Access control register 0x0 0x20 read-write 0x00000000 LATENCY Latency 0 1 PRFTEN Prefetch enable 1 1 ACC64 64-bit access 2 1 SLEEP_PD Flash mode during Sleep 3 1 RUN_PD Flash mode during Run 4 1 PECR PECR Program/erase control register 0x4 0x20 read-write 0x00000007 PELOCK FLASH_PECR and data EEPROM lock 0 1 PRGLOCK Program memory lock 1 1 OPTLOCK Option bytes block lock 2 1 PROG Program memory selection 3 1 DATA Data EEPROM selection 4 1 FTDW Fixed time data write for Byte, Half Word and Word programming 8 1 ERASE Page or Double Word erase mode 9 1 FPRG Half Page/Double Word programming mode 10 1 PARALLELBANK Parallel bank mode 15 1 EOPIE End of programming interrupt enable 16 1 ERRIE Error interrupt enable 17 1 OBL_LAUNCH Launch the option byte loading 18 1 PDKEYR PDKEYR Power down key register 0x8 0x20 write-only 0x00000000 PDKEYR RUN_PD in FLASH_ACR key 0 32 PEKEYR PEKEYR Program/erase key register 0xC 0x20 write-only 0x00000000 PEKEYR FLASH_PEC and data EEPROM key 0 32 PRGKEYR PRGKEYR Program memory key register 0x10 0x20 write-only 0x00000000 PRGKEYR Program memory key 0 32 OPTKEYR OPTKEYR Option byte key register 0x14 0x20 write-only 0x00000000 OPTKEYR Option byte key 0 32 SR SR Status register 0x18 0x20 0x00000004 BSY Write/erase operations in progress 0 1 read-only EOP End of operation 1 1 read-only ENDHV End of high voltage 2 1 read-only READY Flash memory module ready after low power mode 3 1 read-only WRPERR Write protected error 8 1 read-write PGAERR Programming alignment error 9 1 read-write SIZERR Size error 10 1 read-write OPTVERR Option validity error 11 1 read-write OPTVERRUSR Option UserValidity Error 12 1 read-write OBR OBR Option byte register 0x1C 0x20 read-only 0x00F80000 RDPRT Read protection 0 8 BOR_LEV BOR_LEV 16 4 IWDG_SW IWDG_SW 20 1 nRTS_STOP nRTS_STOP 21 1 nRST_STDBY nRST_STDBY 22 1 BFB2 Boot From Bank 2 23 1 WRPR1 WRPR1 Write protection register 0x20 0x20 read-write 0x00000000 WRP1 Write protection 0 32 WRPR2 WRPR2 Write protection register 0x80 0x20 read-write 0x00000000 WRP2 WRP2 0 32 WRPR3 WRPR3 Write protection register 0x84 0x20 read-write 0x00000000 WRP3 WRP3 0 32 GPIOA General-purpose I/Os GPIO 0x40020000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xA8000000 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDER OSPEEDER GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR15 OSPEEDR15 30 2 OSPEEDR14 OSPEEDR14 28 2 OSPEEDR13 OSPEEDR13 26 2 OSPEEDR12 OSPEEDR12 24 2 OSPEEDR11 OSPEEDR11 22 2 OSPEEDR10 OSPEEDR10 20 2 OSPEEDR9 OSPEEDR9 18 2 OSPEEDR8 OSPEEDR8 16 2 OSPEEDR7 OSPEEDR7 14 2 OSPEEDR6 OSPEEDR6 12 2 OSPEEDR5 OSPEEDR5 10 2 OSPEEDR4 OSPEEDR4 8 2 OSPEEDR3 OSPEEDR3 6 2 OSPEEDR2 OSPEEDR2 4 2 OSPEEDR1 OSPEEDR1 2 2 OSPEEDR0 OSPEEDR0 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x64000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL AFRL 0x20 0x20 read-write 0x00000000 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 GPIOB General-purpose I/Os GPIO 0x40020400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00000280 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDER OSPEEDER GPIO port output speed register 0x8 0x20 read-write 0x000000C0 OSPEEDR15 OSPEEDR15 30 2 OSPEEDR14 OSPEEDR14 28 2 OSPEEDR13 OSPEEDR13 26 2 OSPEEDR12 OSPEEDR12 24 2 OSPEEDR11 OSPEEDR11 22 2 OSPEEDR10 OSPEEDR10 20 2 OSPEEDR9 OSPEEDR9 18 2 OSPEEDR8 OSPEEDR8 16 2 OSPEEDR7 OSPEEDR7 14 2 OSPEEDR6 OSPEEDR6 12 2 OSPEEDR5 OSPEEDR5 10 2 OSPEEDR4 OSPEEDR4 8 2 OSPEEDR3 OSPEEDR3 6 2 OSPEEDR2 OSPEEDR2 4 2 OSPEEDR1 OSPEEDR1 2 2 OSPEEDR0 OSPEEDR0 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000100 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL AFRL 0x20 0x20 read-write 0x00000000 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 GPIOC General-purpose I/Os GPIO 0x40020800 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00000000 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDER OSPEEDER GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR15 OSPEEDR15 30 2 OSPEEDR14 OSPEEDR14 28 2 OSPEEDR13 OSPEEDR13 26 2 OSPEEDR12 OSPEEDR12 24 2 OSPEEDR11 OSPEEDR11 22 2 OSPEEDR10 OSPEEDR10 20 2 OSPEEDR9 OSPEEDR9 18 2 OSPEEDR8 OSPEEDR8 16 2 OSPEEDR7 OSPEEDR7 14 2 OSPEEDR6 OSPEEDR6 12 2 OSPEEDR5 OSPEEDR5 10 2 OSPEEDR4 OSPEEDR4 8 2 OSPEEDR3 OSPEEDR3 6 2 OSPEEDR2 OSPEEDR2 4 2 OSPEEDR1 OSPEEDR1 2 2 OSPEEDR0 OSPEEDR0 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL AFRL 0x20 0x20 read-write 0x00000000 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 GPIOD 0x40020C00 GPIOE 0x40021000 GPIOF 0x40021800 GPIOG 0x40021C00 GPIOH 0x40021400 I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 31 I2C1_ER I2C1 error interrupt 32 CR1 CR1 CR1 0x0 0x20 read-write 0x0000 SWRST Software reset 15 1 ALERT SMBus alert 13 1 PEC Packet error checking 12 1 POS Acknowledge/PEC Position (for data reception) 11 1 ACK Acknowledge enable 10 1 STOP Stop generation 9 1 START Start generation 8 1 NOSTRETCH Clock stretching disable (Slave mode) 7 1 ENGC General call enable 6 1 ENPEC PEC enable 5 1 ENARP ARP enable 4 1 SMBTYPE SMBus type 3 1 SMBUS SMBus mode 1 1 PE Peripheral enable 0 1 CR2 CR2 CR2 0x4 0x20 read-write 0x0000 LAST DMA last transfer 12 1 DMAEN DMA requests enable 11 1 ITBUFEN Buffer interrupt enable 10 1 ITEVTEN Event interrupt enable 9 1 ITERREN Error interrupt enable 8 1 FREQ Peripheral clock frequency 0 6 OAR1 OAR1 OAR1 0x8 0x20 read-write 0x0000 ADDMODE ADDMODE 15 1 ADD_8_9 Interface address 8 2 ADD_1_7 Interface address 1 7 ADD_0 Interface address 0 1 OAR2 OAR2 OAR2 0xC 0x20 read-write 0x0000 ADD2 Interface address 1 7 ENDUAL Dual addressing mode enable 0 1 DR DR DR 0x10 0x20 read-write 0x0000 DR -bit data register 0 8 SR1 SR1 SR1 0x14 0x20 0x0000 SMBALERT SMBus alert 15 1 read-write TIMEOUT Timeout or Tlow error 14 1 read-write PECERR PEC Error in reception 12 1 read-write OVR Overrun/Underrun 11 1 read-write AF Acknowledge failure 10 1 read-write ARLO Arbitration lost (master mode) 9 1 read-write BERR Bus error 8 1 read-write TxE Data register empty (transmitters) 7 1 read-only RxNE Data register not empty (receivers) 6 1 read-only STOPF Stop detection (slave mode) 4 1 read-only ADD10 10-bit header sent (Master mode) 3 1 read-only BTF Byte transfer finished 2 1 read-only ADDR Address sent (master mode)/matched (slave mode) 1 1 read-only SB Start bit (Master mode) 0 1 read-only SR2 SR2 SR2 0x18 0x20 read-only 0x0000 PEC acket error checking register 8 8 DUALF Dual flag (Slave mode) 7 1 SMBHOST SMBus host header (Slave mode) 6 1 SMBDEFAULT SMBus device default address (Slave mode) 5 1 GENCALL General call address (Slave mode) 4 1 TRA Transmitter/receiver 2 1 BUSY Bus busy 1 1 MSL Master/slave 0 1 CCR CCR CCR 0x1C 0x20 read-write 0x0000 F_S I2C master mode selection 15 1 DUTY Fast mode duty cycle 14 1 CCR Clock control register in Fast/Standard mode (Master mode) 0 12 TRISE TRISE TRISE 0x20 0x20 read-write 0x0002 TRISE Maximum rise time in Fast/Standard mode (Master mode) 0 6 I2C2 0x40005800 I2C2_EV I2C2 event interrupt 33 I2C2_ER I2C2 error interrupt 34 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register 0x0 0x20 write-only 0x00000000 KEY Key value (write only, read 0000h) 0 16 PR PR Prescaler register 0x4 0x20 read-write 0x00000000 PR Prescaler divider 0 3 RLR RLR Reload register 0x8 0x20 read-write 0x00000FFF RL Watchdog counter reload value 0 12 SR SR Status register 0xC 0x20 read-only 0x00000000 RVU Watchdog counter reload value update 1 1 PVU Watchdog prescaler value update 0 1 LCD Liquid crystal display controller LCD 0x40002400 0x0 0x400 registers LCD LCD global interrupt 24 CR CR control register 0x0 0x20 read-write 0x00000000 MUX_SEG Mux segment enable 7 1 BIAS Bias selector 5 2 DUTY Duty selection 2 3 VSEL Voltage source selection 1 1 LCDEN LCD controller enable 0 1 FCR FCR frame control register 0x4 0x20 read-write 0x00000000 PS PS 16-bit prescaler 22 4 DIV DIV clock divider 18 4 BLINK Blink mode selection 16 2 BLINKF Blink frequency selection 13 3 CC Contrast control 10 3 DEAD Dead time duration 7 3 PON Pulse ON duration 4 3 UDDIE Update display done interrupt enable 3 1 SOFIE Start of frame interrupt enable 1 1 HD High drive enable 0 1 SR SR status register 0x8 0x20 0x00000020 FCRSF LCD Frame Control Register Synchronization flag 5 1 read-only RDY Ready flag 4 1 read-only UDD Update Display Done 3 1 read-only UDR Update display request 2 1 read-write SOF Start of frame flag 1 1 read-only ENS LCD enabled status 0 1 read-only CLR CLR clear register 0xC 0x20 write-only 0x00000000 UDDC Update display done clear 3 1 SOFC Start of frame flag clear 1 1 RAM_COM0 RAM_COM0 display memory 0x14 0x20 read-write 0x00000000 S31 S31 31 1 S30 S30 30 1 S29 S29 29 1 S28 S28 28 1 S27 S27 27 1 S26 S26 26 1 S25 S25 25 1 S24 S24 24 1 S23 S23 23 1 S22 S22 22 1 S21 S21 21 1 S20 S20 20 1 S19 S19 19 1 S18 S18 18 1 S17 S17 17 1 S16 S16 16 1 S15 S15 15 1 S14 S14 14 1 S13 S13 13 1 S12 S12 12 1 S11 S11 11 1 S10 S10 10 1 S09 S09 9 1 S08 S08 8 1 S07 S07 7 1 S06 S06 6 1 S05 S05 5 1 S04 S04 4 1 S03 S03 3 1 S02 S02 2 1 S01 S01 1 1 S00 S00 0 1 RAM_COM1 RAM_COM1 display memory 0x1C 0x20 read-write 0x00000000 S31 S31 31 1 S30 S30 30 1 S29 S29 29 1 S28 S28 28 1 S27 S27 27 1 S26 S26 26 1 S25 S25 25 1 S24 S24 24 1 S23 S23 23 1 S22 S22 22 1 S21 S21 21 1 S20 S20 20 1 S19 S19 19 1 S18 S18 18 1 S17 S17 17 1 S16 S16 16 1 S15 S15 15 1 S14 S14 14 1 S13 S13 13 1 S12 S12 12 1 S11 S11 11 1 S10 S10 10 1 S09 S09 9 1 S08 S08 8 1 S07 S07 7 1 S06 S06 6 1 S05 S05 5 1 S04 S04 4 1 S03 S03 3 1 S02 S02 2 1 S01 S01 1 1 S00 S00 0 1 RAM_COM2 RAM_COM2 display memory 0x24 0x20 read-write 0x00000000 S31 S31 31 1 S30 S30 30 1 S29 S29 29 1 S28 S28 28 1 S27 S27 27 1 S26 S26 26 1 S25 S25 25 1 S24 S24 24 1 S23 S23 23 1 S22 S22 22 1 S21 S21 21 1 S20 S20 20 1 S19 S19 19 1 S18 S18 18 1 S17 S17 17 1 S16 S16 16 1 S15 S15 15 1 S14 S14 14 1 S13 S13 13 1 S12 S12 12 1 S11 S11 11 1 S10 S10 10 1 S09 S09 9 1 S08 S08 8 1 S07 S07 7 1 S06 S06 6 1 S05 S05 5 1 S04 S04 4 1 S03 S03 3 1 S02 S02 2 1 S01 S01 1 1 S00 S00 0 1 RAM_COM3 RAM_COM3 display memory 0x2C 0x20 read-write 0x00000000 S31 S31 31 1 S30 S30 30 1 S29 S29 29 1 S28 S28 28 1 S27 S27 27 1 S26 S26 26 1 S25 S25 25 1 S24 S24 24 1 S23 S23 23 1 S22 S22 22 1 S21 S21 21 1 S20 S20 20 1 S19 S19 19 1 S18 S18 18 1 S17 S17 17 1 S16 S16 16 1 S15 S15 15 1 S14 S14 14 1 S13 S13 13 1 S12 S12 12 1 S11 S11 11 1 S10 S10 10 1 S09 S09 9 1 S08 S08 8 1 S07 S07 7 1 S06 S06 6 1 S05 S05 5 1 S04 S04 4 1 S03 S03 3 1 S02 S02 2 1 S01 S01 1 1 S00 S00 0 1 RAM_COM4 RAM_COM4 display memory 0x34 0x20 read-write 0x00000000 S31 S31 31 1 S30 S30 30 1 S29 S29 29 1 S28 S28 28 1 S27 S27 27 1 S26 S26 26 1 S25 S25 25 1 S24 S24 24 1 S23 S23 23 1 S22 S22 22 1 S21 S21 21 1 S20 S20 20 1 S19 S19 19 1 S18 S18 18 1 S17 S17 17 1 S16 S16 16 1 S15 S15 15 1 S14 S14 14 1 S13 S13 13 1 S12 S12 12 1 S11 S11 11 1 S10 S10 10 1 S09 S09 9 1 S08 S08 8 1 S07 S07 7 1 S06 S06 6 1 S05 S05 5 1 S04 S04 4 1 S03 S03 3 1 S02 S02 2 1 S01 S01 1 1 S00 S00 0 1 RAM_COM5 RAM_COM5 display memory 0x3C 0x20 read-write 0x00000000 S31 S31 31 1 S30 S30 30 1 S29 S29 29 1 S28 S28 28 1 S27 S27 27 1 S26 S26 26 1 S25 S25 25 1 S24 S24 24 1 S23 S23 23 1 S22 S22 22 1 S21 S21 21 1 S20 S20 20 1 S19 S19 19 1 S18 S18 18 1 S17 S17 17 1 S16 S16 16 1 S15 S15 15 1 S14 S14 14 1 S13 S13 13 1 S12 S12 12 1 S11 S11 11 1 S10 S10 10 1 S09 S09 9 1 S08 S08 8 1 S07 S07 7 1 S06 S06 6 1 S05 S05 5 1 S04 S04 4 1 S03 S03 3 1 S02 S02 2 1 S01 S01 1 1 S00 S00 0 1 RAM_COM6 RAM_COM6 display memory 0x44 0x20 read-write 0x00000000 S31 S31 31 1 S30 S30 30 1 S29 S29 29 1 S28 S28 28 1 S27 S27 27 1 S26 S26 26 1 S25 S25 25 1 S24 S24 24 1 S23 S23 23 1 S22 S22 22 1 S21 S21 21 1 S20 S20 20 1 S19 S19 19 1 S18 S18 18 1 S17 S17 17 1 S16 S16 16 1 S15 S15 15 1 S14 S14 14 1 S13 S13 13 1 S12 S12 12 1 S11 S11 11 1 S10 S10 10 1 S09 S09 9 1 S08 S08 8 1 S07 S07 7 1 S06 S06 6 1 S05 S05 5 1 S04 S04 4 1 S03 S03 3 1 S02 S02 2 1 S01 S01 1 1 S00 S00 0 1 RAM_COM7 RAM_COM7 display memory 0x4C 0x20 read-write 0x00000000 S31 S31 31 1 S30 S30 30 1 S29 S29 29 1 S28 S28 28 1 S27 S27 27 1 S26 S26 26 1 S25 S25 25 1 S24 S24 24 1 S23 S23 23 1 S22 S22 22 1 S21 S21 21 1 S20 S20 20 1 S19 S19 19 1 S18 S18 18 1 S17 S17 17 1 S16 S16 16 1 S15 S15 15 1 S14 S14 14 1 S13 S13 13 1 S12 S12 12 1 S11 S11 11 1 S10 S10 10 1 S09 S09 9 1 S08 S08 8 1 S07 S07 7 1 S06 S06 6 1 S05 S05 5 1 S04 S04 4 1 S03 S03 3 1 S02 S02 2 1 S01 S01 1 1 S00 S00 0 1 OPAMP Operational amplifiers OPAMP 0x40007C5C 0x0 0x400 registers CSR CSR control/status register 0x0 0x20 read-write 0x00010101 OPA3CALOUT OPAMP3 calibration output 31 1 OPA2CALOUT OPAMP2 calibration output 30 1 OPA1CALOUT OPAMP1 calibration output 29 1 AOP_RANGE Power range selection 28 1 S7SEL2 Switch 7 for OPAMP2 enable 27 1 ANAWSEL3 Switch SanA enable for OPAMP3 26 1 ANAWSEL2 Switch SanA enable for OPAMP2 25 1 ANAWSEL1 Switch SanA enable for OPAMP1 24 1 OPA3LPM OPAMP3 low power mode 23 1 OPA3CAL_H OPAMP3 offset calibration for N differential pair 22 1 OPA3CAL_L OPAMP3 offset Calibration for P differential pair 21 1 S6SEL3 Switch 6 for OPAMP3 enable 20 1 S5SEL3 Switch 5 for OPAMP3 enable 19 1 S4SEL3 Switch 4 for OPAMP3 enable 18 1 S3SEL3 Switch 3 for OPAMP3 Enable 17 1 OPA3PD OPAMP3 power down 16 1 OPA2LPM OPAMP2 low power mode 15 1 OPA2CAL_H OPAMP2 offset calibration for N differential pair 14 1 OPA2CAL_L OPAMP2 offset Calibration for P differential pair 13 1 S6SEL2 Switch 6 for OPAMP2 enable 12 1 S5SEL2 Switch 5 for OPAMP2 enable 11 1 S4SEL2 Switch 4 for OPAMP2 enable 10 1 S3SEL2 Switch 3 for OPAMP2 enable 9 1 OPA2PD OPAMP2 power down 8 1 OPA1LPM OPAMP1 low power mode 7 1 OPA1CAL_H OPAMP1 offset calibration for N differential pair 6 1 OPA1CAL_L OPAMP1 offset calibration for P differential pair 5 1 S6SEL1 Switch 6 for OPAMP1 enable 4 1 S5SEL1 Switch 5 for OPAMP1 enable 3 1 S4SEL1 Switch 4 for OPAMP1 enable 2 1 S3SEL1 Switch 3 for OPAMP1 enable 1 1 OPA1PD OPAMP1 power down 0 1 OTR OTR offset trimming register for normal mode 0x4 0x20 read-write 0x00000000 OT_USER Select user or factory trimming value 31 1 AO3_OPT_OFFSET_TRIM OPAMP3, 10-bit offset trim value for normal mode 20 10 AO2_OPT_OFFSET_TRIM OPAMP2, 10-bit offset trim value for normal mode 10 10 AO1_OPT_OFFSET_TRIM OPAMP1, 10-bit offset trim value for normal mode 0 10 LPOTR LPOTR OPAMP offset trimming register for low power mode 0x8 0x20 read-write 0x00000000 AO3_OPT_OFFSET_TRIM_LP OPAMP3, 10-bit offset trim value for low power mode 20 10 AO2_OPT_OFFSET_TRIM_LP OPAMP2, 10-bit offset trim value for low power mode 10 10 AO1_OPT_OFFSET_TRIM_LP OPAMP1, 10-bit offset trim value for low power mode 0 10 PWR Power control PWR 0x40007000 0x0 0x400 registers PVD PVD through EXTI Line detection interrupt 1 CR CR power control register 0x0 0x20 read-write 0x00001000 LPRUN Low power run mode 14 1 VOS Voltage scaling range selection 11 2 FWU Fast wakeup 10 1 ULP Ultralow power mode 9 1 DBP Disable backup domain write protection 8 1 PLS PVD level selection 5 3 PVDE Power voltage detector enable 4 1 CSBF Clear standby flag 3 1 CWUF Clear wakeup flag 2 1 PDDS Power down deepsleep 1 1 LPSDSR Low-power deep sleep 0 1 CSR CSR power control/status register 0x4 0x20 0x00000008 EWUP3 Enable WKUP pin 3 10 1 read-write EWUP2 Enable WKUP pin 2 9 1 read-write EWUP1 Enable WKUP pin 1 8 1 read-write REGLPF Regulator LP flag 5 1 read-only VOSF Voltage Scaling select flag 4 1 read-only VREFINTRDYF Internal voltage reference (VREFINT) ready flag 3 1 read-only PVDO PVD output 2 1 read-only SBF Standby flag 1 1 read-only WUF Wakeup flag 0 1 read-only RCC Reset and clock control RCC 0x40023800 0x0 0x400 registers RCC RCC global interrupt 5 CR CR Clock control register 0x0 0x20 0x00000300 RTCPRE1 TC/LCD prescaler 30 1 read-write RTCPRE0 RTCPRE0 29 1 read-write CSSON Clock security system enable 28 1 read-write PLLRDY PLL clock ready flag 25 1 read-only PLLON PLL enable 24 1 read-write HSEBYP HSE clock bypass 18 1 read-write HSERDY HSE clock ready flag 17 1 read-only HSEON HSE clock enable 16 1 read-write MSIRDY MSI clock ready flag 9 1 read-only MSION MSI clock enable 8 1 read-write HSIRDY Internal high-speed clock ready flag 1 1 read-only HSION Internal high-speed clock enable 0 1 read-write ICSCR ICSCR Internal clock sources calibration register 0x4 0x20 0x0000B000 MSITRIM MSI clock trimming 24 8 read-write MSICAL MSI clock calibration 16 8 read-only MSIRANGE MSI clock ranges 13 3 read-write HSITRIM High speed internal clock trimming 8 5 read-write HSICAL nternal high speed clock calibration 0 8 read-only CFGR CFGR Clock configuration register 0x8 0x20 0x00000000 MCOPRE Microcontroller clock output prescaler 28 3 read-write MCOSEL Microcontroller clock output selection 24 3 read-write PLLDIV PLL output division 22 2 read-write PLLMUL PLL multiplication factor 18 4 read-write PLLSRC PLL entry clock source 16 1 read-write PPRE2 APB high-speed prescaler (APB2) 11 3 read-write PPRE1 APB low-speed prescaler (APB1) 8 3 read-write HPRE AHB prescaler 4 4 read-write SWS System clock switch status 2 2 read-only SW System clock switch 0 2 read-write CIR CIR Clock interrupt register 0xC 0x20 0x00000000 CSSC Clock security system interrupt clear 23 1 write-only LSECSSC LSE CSS interrupt clear 22 1 write-only MSIRDYC MSI ready interrupt clear 21 1 write-only PLLRDYC PLL ready interrupt clear 20 1 write-only HSERDYC HSE ready interrupt clear 19 1 write-only HSIRDYC HSI ready interrupt clear 18 1 write-only LSERDYC LSE ready interrupt clear 17 1 write-only LSIRDYC LSI ready interrupt clear 16 1 write-only LSECSSIE LSE CSS interrupt enable 14 1 read-write MSIRDYIE MSI ready interrupt enable 13 1 read-write PLLRDYIE PLL ready interrupt enable 12 1 read-write HSERDYIE HSE ready interrupt enable 11 1 read-write HSIRDYIE HSI ready interrupt enable 10 1 read-write LSERDYIE LSE ready interrupt enable 9 1 read-write LSIRDYIE LSI ready interrupt enable 8 1 read-write CSSF Clock security system interrupt flag 7 1 read-only LSECSSF LSE CSS Interrupt flag 6 1 read-only MSIRDYF MSI ready interrupt flag 5 1 read-only PLLRDYF PLL ready interrupt flag 4 1 read-only HSERDYF HSE ready interrupt flag 3 1 read-only HSIRDYF HSI ready interrupt flag 2 1 read-only LSERDYF LSE ready interrupt flag 1 1 read-only LSIRDYF LSI ready interrupt flag 0 1 read-only AHBRSTR AHBRSTR AHB peripheral reset register 0x10 0x20 read-write 0x00000000 DMA2RST DMA2 reset 25 1 DMA1RST DMA1 reset 24 1 FLITFRST FLITF reset 15 1 CRCRST CRC reset 12 1 GPIOGRST IO port G reset 7 1 GPIOFRST IO port F reset 6 1 GPIOHRST IO port H reset 5 1 GPIOERST IO port E reset 4 1 GPIODRST IO port D reset 3 1 GPIOCRST IO port C reset 2 1 GPIOBRST IO port B reset 1 1 GPIOARST IO port A reset 0 1 APB2RSTR APB2RSTR APB2 peripheral reset register 0x14 0x20 read-write 0x00000000 USART1RST USART1RST 14 1 SPI1RST SPI1RST 12 1 ADC1RST ADC1RST 9 1 TM11RST TM11RST 4 1 TM10RST TM10RST 3 1 TIM9RST TIM9RST 2 1 SYSCFGRST SYSCFGRST 0 1 APB1RSTR APB1RSTR APB1 peripheral reset register 0x18 0x20 read-write 0x00000000 COMPRST COMP interface reset 31 1 DACRST DAC interface reset 29 1 PWRRST Power interface reset 28 1 USBRST USB reset 23 1 I2C2RST I2C 2 reset 22 1 I2C1RST I2C 1 reset 21 1 USART3RST USART 3 reset 18 1 USART2RST USART 2 reset 17 1 SPI3RST SPI 3 reset 15 1 SPI2RST SPI 2 reset 14 1 WWDRST Window watchdog reset 11 1 LCDRST LCD reset 9 1 TIM7RST Timer 7 reset 5 1 TIM6RST Timer 6reset 4 1 TIM5RST Timer 5 reset 3 1 TIM4RST Timer 4 reset 2 1 TIM3RST Timer 3 reset 1 1 TIM2RST Timer 2 reset 0 1 AHBENR AHBENR AHB peripheral clock enable register 0x1C 0x20 read-write 0x00008000 DMA2EN DMA2 clock enable 25 1 DMA1EN DMA1 clock enable 24 1 FLITFEN FLITF clock enable 15 1 CRCEN CRC clock enable 12 1 GPIOPGEN IO port G clock enable 7 1 GPIOPFEN IO port F clock enable 6 1 GPIOPHEN IO port H clock enable 5 1 GPIOPEEN IO port E clock enable 4 1 GPIOPDEN IO port D clock enable 3 1 GPIOPCEN IO port C clock enable 2 1 GPIOPBEN IO port B clock enable 1 1 GPIOPAEN IO port A clock enable 0 1 APB2ENR APB2ENR APB2 peripheral clock enable register 0x20 0x20 read-write 0x00000000 USART1EN USART1 clock enable 14 1 SPI1EN SPI 1 clock enable 12 1 ADC1EN ADC1 interface clock enable 9 1 TIM11EN TIM11 timer clock enable 4 1 TIM10EN TIM10 timer clock enable 3 1 TIM9EN TIM9 timer clock enable 2 1 SYSCFGEN System configuration controller clock enable 0 1 APB1ENR APB1ENR APB1 peripheral clock enable register 0x24 0x20 read-write 0x00000000 COMPEN COMP interface clock enable 31 1 DACEN DAC interface clock enable 29 1 PWREN Power interface clock enable 28 1 USBEN USB clock enable 23 1 I2C2EN I2C 2 clock enable 22 1 I2C1EN I2C 1 clock enable 21 1 USART3EN USART 3 clock enable 18 1 USART2EN USART 2 clock enable 17 1 SPI3EN SPI 3 clock enable 15 1 SPI2EN SPI 2 clock enable 14 1 WWDGEN Window watchdog clock enable 11 1 LCDEN LCD clock enable 9 1 TIM7EN Timer 7 clock enable 5 1 TIM6EN Timer 6 clock enable 4 1 TIM5EN Timer 5 clock enable 3 1 TIM4EN Timer 4 clock enable 2 1 TIM3EN Timer 3 clock enable 1 1 TIM2EN Timer 2 clock enable 0 1 AHBLPENR AHBLPENR AHB peripheral clock enable in low power mode register 0x28 0x20 read-write 0x0101903F DMA2LPEN DMA2 clock enable during Sleep mode 25 1 DMA1LPEN DMA1 clock enable during Sleep mode 24 1 SRAMLPEN SRAM clock enable during Sleep mode 16 1 FLITFLPEN FLITF clock enable during Sleep mode 15 1 CRCLPEN CRC clock enable during Sleep mode 12 1 GPIOGLPEN IO port G clock enable during Sleep mode 7 1 GPIOFLPEN IO port F clock enable during Sleep mode 6 1 GPIOHLPEN IO port H clock enable during Sleep mode 5 1 GPIOELPEN IO port E clock enable during Sleep mode 4 1 GPIODLPEN IO port D clock enable during Sleep mode 3 1 GPIOCLPEN IO port C clock enable during Sleep mode 2 1 GPIOBLPEN IO port B clock enable during Sleep mode 1 1 GPIOALPEN IO port A clock enable during Sleep mode 0 1 APB2LPENR APB2LPENR APB2 peripheral clock enable in low power mode register 0x2C 0x20 read-write 0x00000000 USART1LPEN USART1 clock enable during Sleep mode 14 1 SPI1LPEN SPI 1 clock enable during Sleep mode 12 1 ADC1LPEN ADC1 interface clock enable during Sleep mode 9 1 TIM11LPEN TIM11 timer clock enable during Sleep mode 4 1 TIM10LPEN TIM10 timer clock enable during Sleep mode 3 1 TIM9LPEN TIM9 timer clock enable during Sleep mode 2 1 SYSCFGLPEN System configuration controller clock enable during Sleep mode 0 1 APB1LPENR APB1LPENR APB1 peripheral clock enable in low power mode register 0x30 0x20 read-write 0x00000000 COMPLPEN COMP interface clock enable during Sleep mode 31 1 DACLPEN DAC interface clock enable during Sleep mode 29 1 PWRLPEN Power interface clock enable during Sleep mode 28 1 USBLPEN USB clock enable during Sleep mode 23 1 I2C2LPEN I2C 2 clock enable during Sleep mode 22 1 I2C1LPEN I2C 1 clock enable during Sleep mode 21 1 USART3LPEN USART 3 clock enable during Sleep mode 18 1 USART2LPEN USART 2 clock enable during Sleep mode 17 1 SPI2LPEN SPI 2 clock enable during Sleep mode 14 1 WWDGLPEN Window watchdog clock enable during Sleep mode 11 1 LCDLPEN LCD clock enable during Sleep mode 9 1 TIM7LPEN Timer 7 clock enable during Sleep mode 5 1 TIM6LPEN Timer 6 clock enable during Sleep mode 4 1 TIM4LPEN Timer 4 clock enable during Sleep mode 2 1 TIM3LPEN Timer 3 clock enable during Sleep mode 1 1 TIM2LPEN Timer 2 clock enable during Sleep mode 0 1 CSR CSR Control/status register 0x34 0x20 0x00000000 LPWRSTF Low-power reset flag 31 1 read-write WWDGRSTF Window watchdog reset flag 30 1 read-write IWDGRSTF Independent watchdog reset flag 29 1 read-write SFTRSTF Software reset flag 28 1 read-write PORRSTF POR/PDR reset flag 27 1 read-write PINRSTF PIN reset flag 26 1 read-write OBLRSTF Options bytes loading reset flag 25 1 read-write RMVF Remove reset flag 24 1 read-write RTCRST RTC software reset 23 1 read-write RTCEN RTC clock enable 22 1 read-write RTCSEL RTC and LCD clock source selection 16 2 read-write LSECSSD CSS on LSE failure Detection 12 1 read-only LSECSSON CSS on LSE enable 11 1 read-write LSEBYP External low-speed oscillator bypass 10 1 read-write LSERDY External low-speed oscillator ready 9 1 read-only LSEON External low-speed oscillator enable 8 1 read-write LSIRDY Internal low-speed oscillator ready 1 1 read-only LSION Internal low-speed oscillator enable 0 1 read-write RI Routing interface RI 0x40007C04 0x0 0x400 registers ICR ICR RI input capture register 0x0 0x20 read-write 0x00000000 IC4 IC4 21 1 IC3 IC3 20 1 IC2 IC2 19 1 IC1 IC1 18 1 TIM Timer select bits 16 2 IC4IOS Input capture 4 select bits 12 4 IC3IOS Input capture 3 select bits 8 4 IC2IOS Input capture 2 select bits 4 4 IC1IOS Input capture 1 select bits 0 4 ASCR1 ASCR1 RI analog switches control register 1 0x4 0x20 read-write 0x00000000 SCM Switch control mode 31 1 CH30GR11_4 Analog switch control 30 1 CH29GR11_3 Analog switch control 29 1 CH28GR11_2 Analog switch control 28 1 CH27GR11_1 Analog switch control 27 1 VCOMP ADC analog switch selection for internal node to comparator 1 26 1 CH25 Analog I/O switch control of channel CH25 25 1 CH24 Analog I/O switch control of channel CH24 24 1 CH23 Analog I/O switch control of channel CH23 23 1 CH22 Analog I/O switch control of channel CH22 22 1 CH21GR7_4 Analog switch control 21 1 CH20GR7_3 Analog switch control 20 1 CH19GR7_2 Analog switch control 19 1 CH18GR7_1 Analog switch control 18 1 CH31GR7_1 Analog switch control 16 1 CH15GR9_2 Analog switch control 15 1 CH14GR9_1 Analog switch control 14 1 CH13GR8_4 Analog switch control 13 1 CH12GR8_3 Analog switch control 12 1 CH11GR8_2 Analog switch control 11 1 CH10GR8_1 Analog switch control 10 1 CH9GR3_2 Analog switch control 9 1 CH8GR3_1 Analog switch control 8 1 CH7GR2_2 Analog switch control 7 1 CH6GR2_1 Analog switch control 6 1 COMP1_SW1 Comparator 1 analog switch 5 1 CH31GR11_5 Analog switch control 4 1 CH3GR1_4 Analog switch control 3 1 CH2GR1_3 Analog switch control 2 1 CH1GR1_2 Analog switch control 1 1 CH0GR1_1 Analog switch control 0 1 ASCR2 ASCR2 RI analog switches control register 2 0x8 0x20 read-write 0x00000000 GR5_4 GR5_4 analog switch control 29 1 GR6_4 GR6_4 analog switch control 28 1 GR6_3 GR6_3 analog switch control 27 1 GR7_7 GR7_7 analog switch control 26 1 GR7_6 GR7_6 analog switch control 25 1 GR7_5 GR7_5 analog switch control 24 1 GR2_5 GR2_5 analog switch control 23 1 GR2_4 GR2_4 analog switch control 22 1 GR2_3 GR2_3 analog switch control 21 1 GR9_4 GR9_4 analog switch control 20 1 GR9_3 GR9_3 analog switch control 19 1 GR3_5 GR3_5 analog switch control 18 1 GR3_4 GR3_4 analog switch control 17 1 GR3_3 GR3_3 analog switch control 16 1 GR4_3 GR4_3 analog switch control 11 1 GR4_2 GR4_2 analog switch control 10 1 GR4_1 GR4_1 analog switch control 9 1 GR5_3 GR5_3 analog switch control 8 1 GR5_2 GR5_2 analog switch control 7 1 GR5_1 GR5_1 analog switch control 6 1 GR6_2 GR6_2 analog switch control 5 1 GR6_1 GR6_1 analog switch control 4 1 GR10_4 GR10_4 analog switch control 3 1 GR10_3 GR10_3 analog switch control 2 1 GR10_2 GR10_2 analog switch control 1 1 GR10_1 GR10_1 analog switch control 0 1 HYSCR1 HYSCR1 RI hysteresis control register 1 0xC 0x20 read-write 0x00000000 PB Port B hysteresis control on/off 16 16 PA Port A hysteresis control on/off 0 16 HYSCR2 HYSCR2 RI hysteresis control register 2 0x10 0x20 read-write 0x00000000 PD Port D hysteresis control on/off 16 16 PC Port C hysteresis control on/off 0 16 HYSCR3 HYSCR3 RI hysteresis control register 3 0x14 0x20 read-write 0x00000000 PF Port F hysteresis control on/off 16 16 PE Port E hysteresis control on/off 0 16 HYSCR4 HYSCR4 Hysteresis control register 0x18 0x20 read-write 0x00000000 PG Port G hysteresis control on/off 0 16 ASMR1 ASMR1 Analog switch mode register 0x1C 0x20 read-write 0x00000000 PA Port A analog switch mode selection 0 16 CMR1 CMR1 Channel mask register 0x20 0x20 read-write 0x00000000 PA Port A channel masking 0 16 CICR1 CICR1 Channel identification for capture register 0x24 0x20 read-write 0x00000000 PA Port A channel identification for capture 0 16 ASMR2 ASMR2 Analog switch mode register 0x28 0x20 read-write 0x00000000 PB Port B analog switch mode selection 0 16 CMR2 CMR2 Channel mask register 0x2C 0x20 read-write 0x00000000 PB Port B channel masking 0 16 CICR2 CICR2 Channel identification for capture register 0x30 0x20 read-write 0x00000000 PB Port B channel identification for capture 0 16 ASMR3 ASMR3 Analog switch mode register 0x34 0x20 read-write 0x00000000 PC Port C analog switch mode selection 0 16 CMR3 CMR3 Channel mask register 0x38 0x20 read-write 0x00000000 PC Port C channel masking 0 16 CICR3 CICR3 Channel identification for capture register 0x3C 0x20 read-write 0x00000000 PC Port C channel identification for capture 0 16 ASMR4 ASMR4 Analog switch mode register 0x40 0x20 read-write 0x00000000 PF Port F analog switch mode selection 0 16 CMR4 CMR4 Channel mask register 0x44 0x20 read-write 0x00000000 PF Port F channel masking 0 16 CICR4 CICR4 Channel identification for capture register 0x48 0x20 read-write 0x00000000 PF Port F channel identification for capture 0 16 ASMR5 ASMR5 Analog switch mode register 0x4C 0x20 read-write 0x00000000 PG Port G analog switch mode selection 0 16 CMR5 CMR5 Channel mask register 0x50 0x20 read-write 0x00000000 PG Port G channel masking 0 16 CICR5 CICR5 Channel identification for capture register 0x54 0x20 read-write 0x00000000 PG Port G channel identification for capture 0 16 RTC Real-time clock RTC 0x40002800 0x0 0x400 registers RTC_WKUP RTC Wakeup through EXTI line interrupt 3 RTC_Alarm RTC Alarms (A and B) through EXTI line interrupt 41 TR TR time register 0x0 0x20 read-write 0x00000000 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 DR DR date register 0x4 0x20 read-write 0x00002101 YT Year tens in BCD format 20 4 YU Year units in BCD format 16 4 WDU Week day units 13 3 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 CR CR control register 0x8 0x20 read-write 0x00000000 COE Calibration output enable 23 1 OSEL Output selection 21 2 POL Output polarity 20 1 COSEL Calibration output selection 19 1 BKP Backup 18 1 SUB1H Subtract 1 hour 17 1 ADD1H Add 1 hour 16 1 TSIE Time-stamp interrupt enable 15 1 WUTIE Wakeup timer interrupt enable 14 1 ALRBIE Alarm B interrupt enable 13 1 ALRAIE Alarm A interrupt enable 12 1 TSE Time stamp enable 11 1 WUTE Wakeup timer enable 10 1 ALRBE Alarm B enable 9 1 ALRAE Alarm A enable 8 1 DCE Coarse digital calibration enable 7 1 FMT Hour format 6 1 BYPSHAD Bypass the shadow registers 5 1 REFCKON Reference clock detection enable 4 1 TSEDGE Time-stamp event active edge 3 1 WCKSEL WCKSEL 0 3 ISR ISR initialization and status register 0xC 0x20 0x00000007 RECALPF Recalibration pending Flag 16 1 read-only TAMP3F TAMPER3 detection flag 15 1 read-write TAMP2F TAMPER2 detection flag 14 1 read-write TAMP1F Tamper detection flag 13 1 read-write TSOVF Timestamp overflow flag 12 1 read-write TSF Timestamp flag 11 1 read-write WUTF Wakeup timer flag 10 1 read-write ALRBF Alarm B flag 9 1 read-write ALRAF Alarm A flag 8 1 read-write INIT Initialization mode 7 1 read-write INITF Initialization flag 6 1 read-write RSF Registers synchronization flag 5 1 read-write INITS Initialization status flag 4 1 read-only SHPF Shift operation pending 3 1 read-write WUTWF Wakeup timer write flag 2 1 read-only ALRBWF Alarm B write flag 1 1 read-only ALRAWF Alarm A write flag 0 1 read-only PRER PRER prescaler register 0x10 0x20 read-write 0x007F00FF PREDIV_A Asynchronous prescaler factor 16 7 PREDIV_S Synchronous prescaler factor 0 15 WUTR WUTR wakeup timer register 0x14 0x20 read-write 0x0000FFFF WUT Wakeup auto-reload value bits 0 16 CALIBR CALIBR calibration register 0x18 0x20 read-write 0x00000000 DCS Digital calibration sign 7 1 DC Digital calibration 0 5 ALRMAR ALRMAR alarm A register 0x1C 0x20 read-write 0x00000000 MSK4 Alarm A date mask 31 1 WDSEL Week day selection 30 1 DT Date tens in BCD format. 28 2 DU Date units or day in BCD format. 24 4 MSK3 Alarm A hours mask 23 1 PM AM/PM notation 22 1 HT Hour tens in BCD format. 20 2 HU Hour units in BCD format. 16 4 MSK2 Alarm A minutes mask 15 1 MNT Minute tens in BCD format. 12 3 MNU Minute units in BCD format. 8 4 MSK1 Alarm A seconds mask 7 1 ST Second tens in BCD format. 4 3 SU Second units in BCD format. 0 4 ALRMBR ALRMBR alarm B register 0x20 0x20 read-write 0x00000000 MSK4 Alarm B date mask 31 1 WDSEL Week day selection 30 1 DT Date tens in BCD format 28 2 DU Date units or day in BCD format 24 4 MSK3 Alarm B hours mask 23 1 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MSK2 Alarm B minutes mask 15 1 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 MSK1 Alarm B seconds mask 7 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 WPR WPR write protection register 0x24 0x20 write-only 0x00000000 KEY Write protection key 0 8 SSR SSR sub second register 0x28 0x20 read-only 0x00000000 SS Sub second value 0 16 SHIFTR SHIFTR shift control register 0x2C 0x20 write-only 0x00000000 ADD1S ADD1S 31 1 SUBFS Subtract a fraction of a second 0 15 TSTR TSTR TSTR 0x30 0x20 read-only 0x00000000 PM AM/PM notation 22 1 HT Hour tens in BCD format. 20 2 HU Hour units in BCD format. 16 4 MNT Minute tens in BCD format. 12 3 MNU Minute units in BCD format. 8 4 ST Second tens in BCD format. 4 3 SU Second units in BCD format. 0 4 TSDR TSDR time stamp date register 0x34 0x20 read-only 0x00000000 WDU Week day units 13 3 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 TSSSR TSSSR timestamp sub second register 0x38 0x20 read-only 0x00000000 SS Sub second value 0 16 CALR CALR calibration register 0x3C 0x20 read-write 0x00000000 CALP Use an 8-second calibration cycle period 15 1 CALW8 Use a 16-second calibration cycle period 14 1 CALW16 CALW16 13 1 CALM Calibration minus 0 9 TAFCR TAFCR tamper and alternate function configuration register 0x40 0x20 read-write 0x00000000 ALARMOUTTYPE AFO_ALARM output type 18 1 TAMPPUDIS TAMPER pull-up disable 15 1 TAMPPRCH Tamper precharge duration 13 2 TAMPFLT Tamper filter count 11 2 TAMPFREQ Tamper sampling frequency 8 3 TAMPTS Activate timestamp on tamper detection event 7 1 TAMP3TRG TAMPER1 mapping 6 1 TAMP3E TIMESTAMP mapping 5 1 TAMP2TRG Active level for tamper 2 4 1 TAMP2E Tamper 2 detection enable 3 1 TAMPIE Tamper interrupt enable 2 1 TAMP1ETRG Active level for tamper 1 1 1 TAMP1E Tamper 1 detection enable 0 1 ALRMASSR ALRMASSR alarm A sub second register 0x44 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 ALRMBSSR ALRMBSSR alarm B sub second register 0x48 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 BKP0R BKP0R backup register 0x50 0x20 read-write 0x00000000 BKP BKP 0 32 BKP1R BKP1R backup register 0x54 0x20 read-write 0x00000000 BKP BKP 0 32 BKP2R BKP2R backup register 0x58 0x20 read-write 0x00000000 BKP BKP 0 32 BKP3R BKP3R backup register 0x5C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP4R BKP4R backup register 0x60 0x20 read-write 0x00000000 BKP BKP 0 32 BKP5R BKP5R backup register 0x64 0x20 read-write 0x00000000 BKP BKP 0 32 BKP6R BKP6R backup register 0x68 0x20 read-write 0x00000000 BKP BKP 0 32 BKP7R BKP7R backup register 0x6C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP8R BKP8R backup register 0x70 0x20 read-write 0x00000000 BKP BKP 0 32 BKP9R BKP9R backup register 0x74 0x20 read-write 0x00000000 BKP BKP 0 32 BKP10R BKP10R backup register 0x78 0x20 read-write 0x00000000 BKP BKP 0 32 BKP11R BKP11R backup register 0x7C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP12R BKP12R backup register 0x80 0x20 read-write 0x00000000 BKP BKP 0 32 BKP13R BKP13R backup register 0x84 0x20 read-write 0x00000000 BKP BKP 0 32 BKP14R BKP14R backup register 0x88 0x20 read-write 0x00000000 BKP BKP 0 32 BKP15R BKP15R backup register 0x8C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP16R BKP16R backup register 0x90 0x20 read-write 0x00000000 BKP BKP 0 32 BKP17R BKP17R backup register 0x94 0x20 read-write 0x00000000 BKP BKP 0 32 BKP18R BKP18R backup register 0x98 0x20 read-write 0x00000000 BKP BKP 0 32 BKP19R BKP19R backup register 0x9C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP20R BKP20R backup register 0xA0 0x20 read-write 0x00000000 BKP BKP 0 32 BKP21R BKP21R backup register 0xA4 0x20 read-write 0x00000000 BKP BKP 0 32 BKP22R BKP22R backup register 0xA8 0x20 read-write 0x00000000 BKP BKP 0 32 BKP23R BKP23R backup register 0xAC 0x20 read-write 0x00000000 BKP BKP 0 32 BKP24R BKP24R backup register 0xB0 0x20 read-write 0x00000000 BKP BKP 0 32 BKP25R BKP25R backup register 0xB4 0x20 read-write 0x00000000 BKP BKP 0 32 BKP26R BKP26R backup register 0xB8 0x20 read-write 0x00000000 BKP BKP 0 32 BKP27R BKP27R backup register 0xBC 0x20 read-write 0x00000000 BKP BKP 0 32 BKP28R BKP28R backup register 0xC0 0x20 read-write 0x00000000 BKP BKP 0 32 BKP29R BKP29R backup register 0xC4 0x20 read-write 0x00000000 BKP BKP 0 32 BKP30R BKP30R backup register 0xC8 0x20 read-write 0x00000000 BKP BKP 0 32 BKP31R BKP31R backup register 0xCC 0x20 read-write 0x00000000 BKP BKP 0 32 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 35 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 RXONLY Receive only 10 1 SSM Software slave management 9 1 SSI Internal slave select 8 1 LSBFIRST Frame format 7 1 SPE SPI enable 6 1 BR Baud rate control 3 3 MSTR Master selection 2 1 CPOL Clock polarity 1 1 CPHA Clock phase 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 TXEIE Tx buffer empty interrupt enable 7 1 RXNEIE RX buffer not empty interrupt enable 6 1 ERRIE Error interrupt enable 5 1 FRF Frame format 4 1 SSOE SS output enable 2 1 TXDMAEN Tx buffer DMA enable 1 1 RXDMAEN Rx buffer DMA enable 0 1 SR SR status register 0x8 0x20 0x0002 TIFRFE TI frame format error 8 1 read-only BSY Busy flag 7 1 read-only OVR Overrun flag 6 1 read-only MODF Mode fault 5 1 read-only CRCERR CRC error flag 4 1 read-write UDR Underrun flag 3 1 read-only CHSIDE Channel side 2 1 read-only TXE Transmit buffer empty 1 1 read-only RXNE Receive buffer not empty 0 1 read-only DR DR data register 0xC 0x20 read-write 0x0000 DR Data register 0 16 CRCPR CRCPR CRC polynomial register 0x10 0x20 read-write 0x0007 CRCPOLY CRC polynomial register 0 16 RXCRCR RXCRCR RX CRC register 0x14 0x20 read-only 0x0000 RxCRC Rx CRC register 0 16 TXCRCR TXCRCR TX CRC register 0x18 0x20 read-only 0x0000 TxCRC Tx CRC register 0 16 I2SCFGR I2SCFGR I2S configuration register 0x1C 0x20 read-write 0x0000 I2SMOD I2S mode selection 11 1 I2SE I2S Enable 10 1 I2SCFG I2S configuration mode 8 2 PCMSYNC PCM frame synchronization 7 1 I2SSTD I2S standard selection 4 2 CKPOL Steady state clock polarity 3 1 DATLEN Data length to be transferred 1 2 CHLEN Channel length (number of bits per audio channel) 0 1 I2SPR I2SPR I2S prescaler register 0x20 0x20 read-write 0x00000002 MCKOE Master clock output enable 9 1 ODD Odd factor for the prescaler 8 1 I2SDIV I2S Linear prescaler 0 8 SPI2 0x40003800 SPI2 SPI2 global interrupt 36 SPI3 0x40003C00 SPI3 SPI3 global interrupt 46 SYSCFG System configuration controller SYSCFG 0x40010000 0x0 0x400 registers MEMRMP MEMRMP memory remap register 0x0 0x20 0x00000000 MEM_MODE MEM_MODE 0 2 read-write BOOT_MODE BOOT_MODE 8 2 read-only PMC PMC peripheral mode configuration register 0x4 0x20 read-write 0x00000000 USB_PU USB pull-up 0 1 EXTICR1 EXTICR1 external interrupt configuration register 1 0x8 0x20 read-write 0x0000 EXTI3 EXTI x configuration (x = 0 to 3) 12 4 EXTI2 EXTI x configuration (x = 0 to 3) 8 4 EXTI1 EXTI x configuration (x = 0 to 3) 4 4 EXTI0 EXTI x configuration (x = 0 to 3) 0 4 EXTICR2 EXTICR2 external interrupt configuration register 2 0xC 0x20 read-write 0x0000 EXTI7 EXTI x configuration (x = 4 to 7) 12 4 EXTI6 EXTI x configuration (x = 4 to 7) 8 4 EXTI5 EXTI x configuration (x = 4 to 7) 4 4 EXTI4 EXTI x configuration (x = 4 to 7) 0 4 EXTICR3 EXTICR3 external interrupt configuration register 3 0x10 0x20 read-write 0x0000 EXTI11 EXTI x configuration (x = 8 to 11) 12 4 EXTI10 EXTI10 8 4 EXTI9 EXTI x configuration (x = 8 to 11) 4 4 EXTI8 EXTI x configuration (x = 8 to 11) 0 4 EXTICR4 EXTICR4 external interrupt configuration register 4 0x14 0x20 read-write 0x0000 EXTI15 EXTI x configuration (x = 12 to 15) 12 4 EXTI14 EXTI14 8 4 EXTI13 EXTI13 4 4 EXTI12 EXTI12 0 4 TIM10 General-purpose timers TIM 0x40010C00 0x0 0x400 registers TIM10 TIM10 global interrupt 26 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 DIER DIER Interrupt enable register 0xC 0x20 write-only 0x0000 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC1OF Capture/compare 1 overcapture flag 9 1 CC1IF Capture/Compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 read-write 0x0000 CC1G Capture/Compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 0x18 0x20 read-write 0x0000 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC1FE Output compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC1F Input capture 1 filter 4 4 ICPCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1NP Capture/Compare 1 complementary output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT TIM10 counter 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC TIM9 prescaler 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 OR OR option register 0x50 0x20 read-write 0x0000 TI1_RMP TIM11 Input 1 remapping capability 0 2 TIM11 0x40011000 TIM11 TIM11 global interrupt 27 TIM2 General-purpose timers TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 28 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 DIER DIER Interrupt enable register 0xC 0x20 write-only 0x0000 TDE Trigger DMA request enable 14 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/compare 1 overcapture flag 12 1 CC3OF Capture/compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/compare 1 overcapture flag 9 1 TIF Trigger interrupt flag 6 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/Compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 read-write 0x0000 TG Trigger generation 6 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 0x18 0x20 read-write 0x0000 OC2CE Output compare 2 clear enable 15 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 OC2FE Output compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 1 OC1CE Output compare 1 clear enable 7 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC1FE Output compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 ICPCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 0x1C 0x20 read-write 0x0000 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 1 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 4 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 complementary output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x0000 CNT TIM2 counter 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC TIM2 prescaler 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000 ARR Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x0000 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 1 0x38 0x20 read-write 0x0000 CCR2 Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 1 0x3C 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 CCR4 CCR4 capture/compare register 1 0x40 0x20 read-write 0x00000000 CCR4 Capture/Compare 4 value 0 16 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 TIM3 0x40000400 TIM3 TIM3 global interrupt 29 TIM4 0x40000800 TIM4 TIM4 global interrupt 30 TIM5 0x40000C00 TIM5 TIM5 global interrupt 45 TIM6 Basic timers TIM 0x40001000 0x0 0x400 registers TIM6 TIM6 global interrupt 43 CR1 CR1 TIM6 control register 1 0x0 0x20 read-write 0x0000 ARPE Auto-reload preload enable 7 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 TIM6 control register 2 0x4 0x20 read-write 0x0000 MMS Master mode selection 4 3 DIER DIER TIM6 DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 SR SR TIM6 status register 0x10 0x20 read-write 0x0000 UIF Update interrupt flag 0 1 EGR EGR TIM6 event generation register 0x14 0x20 write-only 0x0000 UG Update generation 0 1 CNT CNT TIM6 counter 0x24 0x20 read-write 0x0000 CNT CNT 0 16 PSC PSC TIM6 prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler valueThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). 0 16 ARR ARR TIM6 auto-reload register 0x2C 0x20 read-write 0x0000 ARR Prescaler value 0 16 TIM7 0x40001400 TIM7 TIM7 global interrupt 44 TIM9 General-purpose timers TIM 0x40010800 0x0 0x400 registers TIM9 TIM9 global interrupt 25 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 OMP One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 MMS Master mode selection 4 3 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DIER DIER Interrupt enable register 0xC 0x20 write-only 0x0000 TIE Trigger interrupt enable 6 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/compare 1 overcapture flag 9 1 TIF Trigger interrupt flag 6 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/Compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 read-write 0x0000 TG Trigger generation 6 1 CC2G Capture/Compare 2 generation 2 1 CC1G Capture/Compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 0x18 0x20 read-write 0x0000 OC2CE Output compare 2 clear enable 15 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 OC2FE Output compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 1 OC1CE Output compare 1 clear enable 7 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC1FE Output compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 ICPCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT TIM9 counter 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC TIM9 prescaler 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 2 value 0 16 OR OR option register 0x50 0x20 read-write 0x0000 TI1_RMP TIM9 Input 1 remapping capability 0 2 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 37 SR SR Status register 0x0 0x20 0x00C00000 CTS CTS flag 9 1 read-write LBD LIN break detection flag 8 1 read-write TXE Transmit data register empty 7 1 read-only TC Transmission complete 6 1 read-write RXNE Read data register not empty 5 1 read-write IDLE IDLE line detected 4 1 read-only ORE Overrun error 3 1 read-only NF Noise detected flag 2 1 read-only FE Framing error 1 1 read-only PE Parity error 0 1 read-only DR DR Data register 0x4 0x20 read-write 0x00000000 DR Data value 0 9 BRR BRR Baud rate register 0x8 0x20 read-write 0x00000000 DIV_Mantissa mantissa of USARTDIV 4 12 DIV_Fraction fraction of USARTDIV 0 4 CR1 CR1 Control register 1 0xC 0x20 read-write 0x00000000 OVER8 Oversampling mode 15 1 UE USART enable 13 1 M Word length 12 1 WAKE Wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE TXE interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXNE interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 RWU Receiver wakeup 1 1 SBK Send break 0 1 CR2 CR2 Control register 2 0x10 0x20 read-write 0x00000000 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CLKEN Clock enable 11 1 CPOL Clock polarity 10 1 CPHA Clock phase 9 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL lin break detection length 5 1 ADD Address of the USART node 0 4 CR3 CR3 Control register 3 0x14 0x20 read-write 0x00000000 ONEBIT One sample bit method enable 11 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 SCEN Smartcard mode enable 5 1 NACK Smartcard NACK enable 4 1 HDSEL Half-duplex selection 3 1 IRLP IrDA low-power 2 1 IREN IrDA mode enable 1 1 EIE Error interrupt enable 0 1 GTPR GTPR Guard time and prescaler register 0x18 0x20 read-write 0x00000000 GT Guard time value 8 8 PSC Prescaler value 0 8 USART2 0x40004400 USART2 USART2 global interrupt 38 USART3 0x40004800 USART3 USART3 global interrupt 39 USB Universal serial bus full-speed device interface USB 0x40005C00 0x0 0x400 registers USB_HP USB High priority interrupt 19 USB_LP USB Low priority interrupt 20 USB_FS_WKUP USB Device FS Wakeup through 42 USB_EP0R USB_EP0R endpoint 0 register 0x0 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 USB_EP1R USB_EP1R endpoint 1 register 0x4 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 USB_EP2R USB_EP2R endpoint 2 register 0x8 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 USB_EP3R USB_EP3R endpoint 3 register 0xC 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 USB_EP4R USB_EP4R endpoint 4 register 0x10 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 USB_EP5R USB_EP5R endpoint 5 register 0x14 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 USB_EP6R USB_EP6R endpoint 6 register 0x18 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 USB_EP7R USB_EP7R endpoint 7 register 0x1C 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 USB_CNTR USB_CNTR control register 0x40 0x20 read-write 0x00000003 FRES Force USB Reset 0 1 PDWN Power down 1 1 LPMODE Low-power mode 2 1 FSUSP Force suspend 3 1 RESUME Resume request 4 1 ESOFM Expected start of frame interrupt mask 8 1 SOFM Start of frame interrupt mask 9 1 RESETM USB reset interrupt mask 10 1 SUSPM Suspend mode interrupt mask 11 1 WKUPM Wakeup interrupt mask 12 1 ERRM Error interrupt mask 13 1 PMAOVRM Packet memory area over / underrun interrupt mask 14 1 CTRM Correct transfer interrupt mask 15 1 ISTR ISTR interrupt status register 0x44 0x20 read-write 0x00000000 EP_ID Endpoint Identifier 0 4 DIR Direction of transaction 4 1 ESOF Expected start frame 8 1 SOF start of frame 9 1 RESET reset request 10 1 SUSP Suspend mode request 11 1 WKUP Wakeup 12 1 ERR Error 13 1 PMAOVR Packet memory area over / underrun 14 1 CTR Correct transfer 15 1 FNR FNR frame number register 0x48 0x20 read-only 0x0000 FN Frame number 0 11 LSOF Lost SOF 11 2 LCK Locked 13 1 RXDM Receive data - line status 14 1 RXDP Receive data + line status 15 1 DADDR DADDR device address 0x4C 0x20 read-write 0x0000 ADD Device address 0 7 EF Enable function 7 1 BTABLE BTABLE Buffer table address 0x50 0x20 read-write 0x0000 BTABLE Buffer table 3 13 USB_SRAM 0x40006000 WWDG Window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window Watchdog interrupt 0 CR CR Control register 0x0 0x20 0x0000007F WDGA Activation bit 7 1 write-only T 7-bit counter (MSB to LSB) 0 7 read-write CFR CFR Configuration register 0x4 0x20 0x0000007F EWI Early wakeup interrupt 9 1 write-only WDGTB1 Timer base 8 1 read-write WDGTB0 WDGTB0 7 1 read-write W 7-bit window value 0 7 read-write SR SR SR 0x8 0x20 read-write 0x00000000 EWIF EWIF 0 1 ADC Analog-to-digital converter ADC 0x40012400 0x0 0x400 registers ADC1 ADC1 global interrupt 18 SR SR status register 0x0 0x20 0x00000000 JCNR Injected channel not ready 9 1 read-only RCNR Regular channel not ready 8 1 read-only ADONS ADC ON status 6 1 read-only OVR Overrun 5 1 read-write STRT Regular channel start flag 4 1 read-write JSTRT Injected channel start flag 3 1 read-write JEOC Injected channel end of conversion 2 1 read-write EOC Regular channel end of conversion 1 1 read-write AWD Analog watchdog flag 0 1 read-write CR1 CR1 control register 1 0x4 0x20 read-write 0x00000000 OVRIE Overrun interrupt enable 26 1 RES Resolution 24 2 AWDEN Analog watchdog enable on regular channels 23 1 JAWDEN Analog watchdog enable on injected channels 22 1 PDI Power down during the idle phase 17 1 PDD Power down during the delay phase 16 1 DISCNUM Discontinuous mode channel count 13 3 JDISCEN Discontinuous mode on injected channels 12 1 DISCEN Discontinuous mode on regular channels 11 1 JAUTO Automatic injected group conversion 10 1 AWDSGL Enable the watchdog on a single channel in scan mode 9 1 SCAN Scan mode 8 1 JEOCIE Interrupt enable for injected channels 7 1 AWDIE Analog watchdog interrupt enable 6 1 EOCIE Interrupt enable for EOC 5 1 AWDCH Analog watchdog channel select bits 0 5 CR2 CR2 control register 2 0x8 0x20 read-write 0x00000000 SWSTART Start conversion of regular channels 30 1 EXTEN External trigger enable for regular channels 28 2 EXTSEL External event select for regular group 24 4 JSWSTART Start conversion of injected channels 22 1 JEXTEN External trigger enable for injected channels 20 2 JEXTSEL External event select for injected group 16 4 ALIGN Data alignment 11 1 EOCS End of conversion selection 10 1 DDS DMA disable selection 9 1 DMA Direct memory access mode 8 1 DELS Delay selection 4 3 ADC_CFG ADC configuration 2 1 CONT Continuous conversion 1 1 ADON A/D Converter ON / OFF 0 1 SMPR1 SMPR1 sample time register 1 0xC 0x20 read-write 0x00000000 SampletimebitsSMPx_x Reserved 0 32 SMPR2 SMPR2 sample time register 2 0x10 0x20 read-write 0x00000000 SampletimebitsSMPx_x Reserved 0 32 SMPR3 SMPR3 sample time register 3 0x14 0x20 read-write 0x00000000 SampletimebitsSMPx_x Reserved 0 32 JOFR1 JOFR1 injected channel data offset register x 0x18 0x20 read-write 0x00000000 JOFFSET1 Data offset for injected channel x 0 12 JOFR2 JOFR2 injected channel data offset register x 0x1C 0x20 read-write 0x00000000 JOFFSET2 Data offset for injected channel x 0 12 JOFR3 JOFR3 injected channel data offset register x 0x20 0x20 read-write 0x00000000 JOFFSET3 Data offset for injected channel x 0 12 JOFR4 JOFR4 injected channel data offset register x 0x24 0x20 read-write 0x00000000 JOFFSET4 Data offset for injected channel x 0 12 HTR HTR watchdog higher threshold register 0x28 0x20 read-write 0x00000FFF HT Analog watchdog higher threshold 0 12 LTR LTR watchdog lower threshold register 0x2C 0x20 read-write 0x00000000 LT Analog watchdog lower threshold 0 12 SQR1 SQR1 regular sequence register 1 0x30 0x20 read-write 0x00000000 L Regular channel sequence length 20 4 SQ28 28th conversion in regular sequence 15 5 SQ27 27th conversion in regular sequence 10 5 SQ26 26th conversion in regular sequence 5 5 SQ25 25th conversion in regular sequence 0 5 SQR2 SQR2 regular sequence register 2 0x34 0x20 read-write 0x00000000 SQ24 24th conversion in regular sequence 25 5 SQ23 23rd conversion in regular sequence 20 5 SQ22 22nd conversion in regular sequence 15 5 SQ21 21st conversion in regular sequence 10 5 SQ20 20th conversion in regular sequence 5 5 SQ19 19th conversion in regular sequence 0 5 SQR3 SQR3 regular sequence register 3 0x38 0x20 read-write 0x00000000 SQ18 18th conversion in regular sequence 25 5 SQ17 17th conversion in regular sequence 20 5 SQ16 16th conversion in regular sequence 15 5 SQ15 15th conversion in regular sequence 10 5 SQ14 14th conversion in regular sequence 5 5 SQ13 13th conversion in regular sequence 0 5 SQR4 SQR4 regular sequence register 4 0x3C 0x20 read-write 0x00000000 SQ12 12th conversion in regular sequence 25 5 SQ11 11th conversion in regular sequence 20 5 SQ10 10th conversion in regular sequence 15 5 SQ9 9th conversion in regular sequence 10 5 SQ8 8th conversion in regular sequence 5 5 SQ7 7th conversion in regular sequence 0 5 SQR5 SQR5 regular sequence register 5 0x40 0x20 read-write 0x00000000 SQ6 6th conversion in regular sequence 25 5 SQ5 5th conversion in regular sequence 20 5 SQ4 4th conversion in regular sequence 15 5 SQ3 3rd conversion in regular sequence 10 5 SQ2 2nd conversion in regular sequence 5 5 SQ1 1st conversion in regular sequence 0 5 JSQR JSQR injected sequence register 0x44 0x20 read-write 0x00000000 JL Injected sequence length 20 2 JSQ4 4th conversion in injected sequence 15 5 JSQ3 3rd conversion in injected sequence 10 5 JSQ2 2nd conversion in injected sequence 5 5 JSQ1 1st conversion in injected sequence 0 5 JDR1 JDR1 injected data register x 0x48 0x20 read-only 0x00000000 JDATA Injected data 0 16 JDR2 JDR2 injected data register x 0x4C 0x20 read-only 0x00000000 JDATA Injected data 0 16 JDR3 JDR3 injected data register x 0x50 0x20 read-only 0x00000000 JDATA Injected data 0 16 JDR4 JDR4 injected data register x 0x54 0x20 read-only 0x00000000 JDATA Injected data 0 16 DR DR regular data register 0x58 0x20 read-only 0x00000000 RegularDATA Regular data 0 16 SMPR0 SMPR0 sample time register 0 0x5C 0x20 read-write 0x00000000 SampletimebitsSMPx_x Reserved 0 32 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E000 0x0 0x1001 registers ICTR ICTR Interrupt Controller Type Register 0x4 0x20 read-only 0x00000000 INTLINESNUM Total number of interrupt lines in groups 0 4 STIR STIR Software Triggered Interrupt Register 0xF00 0x20 write-only 0x00000000 INTID interrupt to be triggered 0 9 ISER0 ISER0 Interrupt Set-Enable Register 0x100 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER1 ISER1 Interrupt Set-Enable Register 0x104 0x20 read-write 0x00000000 SETENA SETENA 0 32 ICER0 ICER0 Interrupt Clear-Enable Register 0x180 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER1 ICER1 Interrupt Clear-Enable Register 0x184 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ISPR0 ISPR0 Interrupt Set-Pending Register 0x200 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR1 ISPR1 Interrupt Set-Pending Register 0x204 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ICPR0 ICPR0 Interrupt Clear-Pending Register 0x280 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR1 ICPR1 Interrupt Clear-Pending Register 0x284 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 IABR0 IABR0 Interrupt Active Bit Register 0x300 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR1 IABR1 Interrupt Active Bit Register 0x304 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IPR0 IPR0 Interrupt Priority Register 0x400 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR1 IPR1 Interrupt Priority Register 0x404 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR2 IPR2 Interrupt Priority Register 0x408 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR3 IPR3 Interrupt Priority Register 0x40C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR4 IPR4 Interrupt Priority Register 0x410 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR5 IPR5 Interrupt Priority Register 0x414 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR6 IPR6 Interrupt Priority Register 0x418 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR7 IPR7 Interrupt Priority Register 0x41C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR8 IPR8 Interrupt Priority Register 0x420 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR9 IPR9 Interrupt Priority Register 0x424 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR10 IPR10 Interrupt Priority Register 0x428 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR11 IPR11 Interrupt Priority Register 0x42C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR12 IPR12 Interrupt Priority Register 0x430 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR13 IPR13 Interrupt Priority Register 0x434 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 DBG Debug support DBG 0xE0042000 0x0 0x400 registers DBGMCU_IDCODE DBGMCU_IDCODE IDCODE 0x0 0x20 read-only 0x10006411 DEV_ID DEV_ID 0 12 REV_ID REV_ID 16 16 DBGMCU_CR DBGMCU_CR Control Register 0x4 0x20 read-write 0x00000000 DBG_SLEEP DBG_SLEEP 0 1 DBG_STOP DBG_STOP 1 1 DBG_STANDBY DBG_STANDBY 2 1 TRACE_IOEN TRACE_IOEN 5 1 TRACE_MODE TRACE_MODE 6 2 DBG_I2C2_SMBUS_TIMEOUT DBG_I2C2_SMBUS_TIMEOUT 16 1 DBG_TIM8_STOP DBG_TIM8_STOP 17 1 DBG_TIM5_STOP DBG_TIM5_STOP 18 1 DBG_TIM6_STOP DBG_TIM6_STOP 19 1 DBG_TIM7_STOP DBG_TIM7_STOP 20 1 DBGMCU_APB1_FZ DBGMCU_APB1_FZ Debug MCU APB1 Freeze registe 0x8 0x20 read-write 0x00000000 DBG_TIM2_STOP DBG_TIM2_STOP 0 1 DBG_TIM3_STOP DBG_TIM3 _STOP 1 1 DBG_TIM4_STOP DBG_TIM4_STOP 2 1 DBG_TIM5_STOP DBG_TIM5_STOP 3 1 DBG_TIM6_STOP DBG_TIM6_STOP 4 1 DBG_TIM7_STOP DBG_TIM7_STOP 5 1 DBG_TIM12_STOP DBG_TIM12_STOP 6 1 DBG_TIM13_STOP DBG_TIM13_STOP 7 1 DBG_TIM14_STOP DBG_TIM14_STOP 8 1 DBG_WWDG_STOP DBG_WWDG_STOP 11 1 DBG_IWDEG_STOP DBG_IWDEG_STOP 12 1 DBG_J2C1_SMBUS_TIMEOUT DBG_J2C1_SMBUS_TIMEOUT 21 1 DBG_J2C2_SMBUS_TIMEOUT DBG_J2C2_SMBUS_TIMEOUT 22 1 DBG_J2C3SMBUS_TIMEOUT DBG_J2C3SMBUS_TIMEOUT 23 1 DBG_CAN1_STOP DBG_CAN1_STOP 25 1 DBG_CAN2_STOP DBG_CAN2_STOP 26 1 DBGMCU_APB2_FZ DBGMCU_APB2_FZ Debug MCU APB2 Freeze registe 0xC 0x20 read-write 0x00000000 DBG_TIM1_STOP TIM1 counter stopped when core is halted 0 1 DBG_TIM8_STOP TIM8 counter stopped when core is halted 1 1 DBG_TIM9_STOP TIM9 counter stopped when core is halted 16 1 DBG_TIM10_STOP TIM10 counter stopped when core is halted 17 1 DBG_TIM11_STOP TIM11 counter stopped when core is halted 18 1