STM32G050 1.0 STM32G050 CM0 r0p1 little true false 4 false 8 32 0x20 0x0 0xFFFFFFFF ADC Analog to Digital ConverteR ADC 0x40012400 0x0 0x400 registers ADC ADC interrupt (ADC combined with EXTI 17 and 18) 12 ADC_ISR ADC_ISR ADC interrupt and status register 0x0 0x20 0x00000000 0xFFFFFFFF ADRDY ADC ready This bit is set by hardware after the ADC has been enabled (ADEN=1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it. 0 1 read-write B_0x0 ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software) 0x0 B_0x1 ADC is ready to start conversion 0x1 EOSMP End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to '1’. 1 1 read-write B_0x0 Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software) 0x0 B_0x1 End of sampling phase reached 0x1 EOC End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register. 2 1 read-write B_0x0 Channel conversion not complete (or the flag event was already acknowledged and cleared by software) 0x0 B_0x1 Channel conversion complete 0x1 EOS End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it. 3 1 read-write B_0x0 Conversion sequence not complete (or the flag event was already acknowledged and cleared by software) 0x0 B_0x1 Conversion sequence complete 0x1 OVR ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it. 4 1 read-write B_0x0 No overrun occurred (or the flag event was already acknowledged and cleared by software) 0x0 B_0x1 Overrun has occurred 0x1 AWD1 Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1. 7 1 read-write B_0x0 No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) 0x0 B_0x1 Analog watchdog event occurred 0x1 AWD2 Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it. 8 1 read-write B_0x0 No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) 0x0 B_0x1 Analog watchdog event occurred 0x1 AWD3 Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1. 9 1 read-write B_0x0 No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) 0x0 B_0x1 Analog watchdog event occurred 0x1 EOCAL End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it. 11 1 read-write B_0x0 Calibration is not complete 0x0 B_0x1 Calibration is complete 0x1 CCRDY Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration. 13 1 read-write B_0x0 Channel configuration update not applied. 0x0 B_0x1 Channel configuration update is applied. 0x1 ADC_IER ADC_IER ADC interrupt enable register 0x4 0x20 0x00000000 0xFFFFFFFF ADRDYIE ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 0 1 read-write B_0x0 ADRDY interrupt disabled. 0x0 B_0x1 ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set. 0x1 EOSMPIE End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 1 1 read-write B_0x0 EOSMP interrupt disabled. 0x0 B_0x1 EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set. 0x1 EOCIE End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 2 1 read-write B_0x0 EOC interrupt disabled 0x0 B_0x1 EOC interrupt enabled. An interrupt is generated when the EOC bit is set. 0x1 EOSIE End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 3 1 read-write B_0x0 EOS interrupt disabled 0x0 B_0x1 EOS interrupt enabled. An interrupt is generated when the EOS bit is set. 0x1 OVRIE Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 4 1 read-write B_0x0 Overrun interrupt disabled 0x0 B_0x1 Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. 0x1 AWD1IE Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 7 1 read-write B_0x0 Analog watchdog interrupt disabled 0x0 B_0x1 Analog watchdog interrupt enabled 0x1 AWD2IE Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 8 1 read-write B_0x0 Analog watchdog interrupt disabled 0x0 B_0x1 Analog watchdog interrupt enabled 0x1 AWD3IE Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 9 1 read-write B_0x0 Analog watchdog interrupt disabled 0x0 B_0x1 Analog watchdog interrupt enabled 0x1 EOCALIE End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 11 1 read-write B_0x0 End of calibration interrupt disabled 0x0 B_0x1 End of calibration interrupt enabled 0x1 CCRDYIE Channel Configuration Ready Interrupt enable This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 13 1 read-write B_0x0 Channel configuration ready interrupt disabled 0x0 B_0x1 Channel configuration ready interrupt enabled 0x1 ADC_CR ADC_CR ADC control register 0x8 0x20 0x00000000 0xFFFFFFFF ADEN ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0) 0 1 read-write B_0x0 ADC is disabled (OFF state) 0x0 B_0x1 Write 1 to enable the ADC. 0x1 ADDIS ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1’ is only effective when ADEN=1 and ADSTART=0 (which ensures that no conversion is ongoing) 1 1 read-write B_0x0 No ADDIS command ongoing 0x0 B_0x1 Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress. 0x1 ADSTART ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT=0, DISCEN=0), when software trigger is selected (EXTEN=00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored. 2 1 read-write B_0x0 No ADC conversion is ongoing. 0x0 B_0x1 Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting. 0x1 ADSTP ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1’ is only effective when ADSTART=1 and ADDIS=0 (ADC is enabled and may be converting and there is no pending request to disable the ADC) 4 1 read-write B_0x0 No ADC stop conversion command ongoing 0x0 B_0x1 Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress. 0x1 ADVREGEN ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). 28 1 read-write B_0x0 ADC voltage regulator disabled 0x0 B_0x1 ADC voltage regulator enabled 0x1 ADCAL ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 (ADC enabled and no conversion is ongoing). 31 1 read-write B_0x0 Calibration complete 0x0 B_0x1 Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress. 0x1 ADC_CFGR1 ADC_CFGR1 ADC configuration register 1 0xc 0x20 0x00000000 0xFFFFFFFF DMAEN Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to . Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 0 1 read-write B_0x0 DMA disabled 0x0 B_0x1 DMA enabled 0x1 DMACFG Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN=1. For more details, refer to page351 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 1 1 read-write B_0x0 DMA one shot mode selected 0x0 B_0x1 DMA circular mode selected 0x1 SCANDIR Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared to 0. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 2 1 read-write B_0x0 Upward scan (from CHSEL0 to CHSEL18) 0x0 B_0x1 Backward scan (from CHSEL18 to CHSEL0) 0x1 RES Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADEN=0. 3 2 read-write B_0x0 12 bits 0x0 B_0x1 10 bits 0x1 B_0x2 8 bits 0x2 B_0x3 6 bits 0x3 ALIGN Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Data alignment and resolution (oversampling disabled: OVSE = 0) on page349 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 5 1 read-write B_0x0 Right alignment 0x0 B_0x1 Left alignment 0x1 EXTSEL External trigger selection These bits select the external event used to trigger the start of conversion (refer to External triggers for details): Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 6 3 read-write B_0x0 TRG0 0x0 B_0x1 TRG1 0x1 B_0x2 TRG2 0x2 B_0x3 TRG3 0x3 B_0x4 TRG4 0x4 B_0x5 TRG5 0x5 B_0x6 TRG6 0x6 B_0x7 TRG7 0x7 EXTEN External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 10 2 read-write B_0x0 Hardware trigger detection disabled (conversions can be started by software) 0x0 B_0x1 Hardware trigger detection on the rising edge 0x1 B_0x2 Hardware trigger detection on the falling edge 0x2 B_0x3 Hardware trigger detection on both the rising and falling edges 0x3 OVRMOD Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 12 1 read-write B_0x0 ADC_DR register is preserved with the old data when an overrun is detected. 0x0 B_0x1 ADC_DR register is overwritten with the last conversion result when an overrun is detected. 0x1 CONT Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN=1 and CONT=1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 13 1 read-write B_0x0 Single conversion mode 0x0 B_0x1 Continuous conversion mode 0x1 WAIT Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 14 1 read-write B_0x0 Wait conversion mode off 0x0 B_0x1 Wait conversion mode on 0x1 AUTOFF Auto-off mode This bit is set and cleared by software to enable/disable auto-off mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 15 1 read-write B_0x0 Auto-off mode disabled 0x0 B_0x1 Auto-off mode enabled 0x1 DISCEN Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN=1 and CONT=1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 16 1 read-write B_0x0 Discontinuous mode disabled 0x0 B_0x1 Discontinuous mode enabled 0x1 CHSELRMOD Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 21 1 read-write B_0x0 Each bit of the ADC_CHSELR register enables an input 0x0 B_0x1 ADC_CHSELR register is able to sequence up to 8 channels 0x1 AWD1SGL Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 22 1 read-write B_0x0 Analog watchdog 1 enabled on all channels 0x0 B_0x1 Analog watchdog 1 enabled on a single channel 0x1 AWD1EN Analog watchdog enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 23 1 read-write B_0x0 Analog watchdog 1 disabled 0x0 B_0x1 Analog watchdog 1 enabled 0x1 AWD1CH Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 26 5 read-write B_0x0 ADC analog input Channel 0 monitored by AWD 0x0 B_0x1 ADC analog input Channel 1 monitored by AWD 0x1 B_0x11 ADC analog input Channel 17 monitored by AWD 0x11 B_0x12 ADC analog input Channel 18 monitored by AWD 0x12 ADC_CFGR2 ADC_CFGR2 ADC configuration register 2 0x10 0x20 0x00000000 0xFFFFFFFF OVSE Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 1 read-write B_0x0 Oversampler disabled 0x0 B_0x1 Oversampler enabled 0x1 OVSR Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 2 3 read-write B_0x0 2x 0x0 B_0x1 4x 0x1 B_0x2 8x 0x2 B_0x3 16x 0x3 B_0x4 32x 0x4 B_0x5 64x 0x5 B_0x6 128x 0x6 B_0x7 256x 0x7 OVSS Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 5 4 read-write B_0x0 No shift 0x0 B_0x1 Shift 1-bit 0x1 B_0x2 Shift 2-bits 0x2 B_0x3 Shift 3-bits 0x3 B_0x4 Shift 4-bits 0x4 B_0x5 Shift 5-bits 0x5 B_0x6 Shift 6-bits 0x6 B_0x7 Shift 7-bits 0x7 B_0x8 Shift 8-bits 0x8 TOVS Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 9 1 read-write B_0x0 All oversampled conversions for a channel are done consecutively after a trigger 0x0 B_0x1 Each oversampled conversion for a channel needs a trigger 0x1 LFTRIG Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 29 1 read-write B_0x0 Low Frequency Trigger Mode disabled 0x0 B_0x1 Low Frequency Trigger Mode enabled 0x1 CKMODE ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). 30 2 read-write B_0x0 ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section) 0x0 B_0x1 PCLK/2 (Synchronous clock mode) 0x1 B_0x2 PCLK/4 (Synchronous clock mode) 0x2 B_0x3 PCLK (Synchronous clock mode). This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle) 0x3 ADC_SMPR ADC_SMPR ADC sampling time register 0x14 0x20 0x00000000 0xFFFFFFFF SMP1 Sampling time selection 1 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 3 read-write B_0x0 1.5 ADC clock cycles 0x0 B_0x1 3.5 ADC clock cycles 0x1 B_0x2 7.5 ADC clock cycles 0x2 B_0x3 12.5 ADC clock cycles 0x3 B_0x4 19.5 ADC clock cycles 0x4 B_0x5 39.5 ADC clock cycles 0x5 B_0x6 79.5 ADC clock cycles 0x6 B_0x7 160.5 ADC clock cycles 0x7 SMP2 Sampling time selection 2 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 4 3 read-write B_0x0 1.5 ADC clock cycles 0x0 B_0x1 3.5 ADC clock cycles 0x1 B_0x2 7.5 ADC clock cycles 0x2 B_0x3 12.5 ADC clock cycles 0x3 B_0x4 19.5 ADC clock cycles 0x4 B_0x5 39.5 ADC clock cycles 0x5 B_0x6 79.5 ADC clock cycles 0x6 B_0x7 160.5 ADC clock cycles 0x7 SMPSEL0 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 8 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL1 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 9 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL2 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 10 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL3 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 11 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL4 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 12 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL5 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 13 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL6 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 14 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL7 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 15 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL8 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 16 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL9 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 17 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL10 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 18 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL11 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 19 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL12 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 20 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL13 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 21 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL14 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 22 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL15 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 23 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL16 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 24 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL17 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 25 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 SMPSEL18 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 26 1 read-write B_0x0 Sampling time of CHANNELx use the setting of SMP1[2:0] register. 0x0 B_0x1 Sampling time of CHANNELx use the setting of SMP2[2:0] register. 0x1 ADC_AWD1TR ADC_AWD1TR ADC watchdog threshold register 0x20 0x20 0x0FFF0000 0xFFFFFFFF LT1 Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page355. 0 12 read-write HT1 Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page355. 16 12 read-write ADC_AWD2TR ADC_AWD2TR ADC watchdog threshold register 0x24 0x20 0x0FFF0000 0xFFFFFFFF LT2 Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page355. 0 12 read-write HT2 Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page355. 16 12 read-write ADC_CHSELR_0 ADC_CHSELR_0 ADC channel selection register [alternate] 0x28 0x20 0x00000000 0xFFFFFFFF CHSEL0 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 0 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL1 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 1 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL2 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 2 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL3 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 3 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL4 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 4 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL5 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 5 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL6 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 6 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL7 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 7 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL8 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 8 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL9 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 9 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL10 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 10 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL11 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 11 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL12 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 12 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL13 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 13 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL14 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 14 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL15 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 15 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL16 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 16 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL17 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 17 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 CHSEL18 Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 18 1 read-write B_0x0 Input Channel-x is not selected for conversion 0x0 B_0x1 Input Channel-x is selected for conversion 0x1 ADC_CHSELR_1 ADC_CHSELR_1 channel selection register CHSELRMOD = 1 in ADC_CFGR1 ADC_CHSELR_0 0x28 0x20 read-write 0x00000000 SQ1 1st conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 4 read-write SQ2 2nd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 4 4 read-write SQ3 3rd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 8 4 read-write SQ4 4th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 12 4 read-write SQ5 5th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 16 4 read-write SQ6 6th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 20 4 read-write SQ7 7th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 24 4 read-write SQ8 8th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. ... Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 28 4 read-write B_0x0 CH0 0x0 B_0x1 CH1 0x1 B_0xC CH12 0xC B_0xD CH13 0xD B_0xE CH14 0xE B_0xF No channel selected (End of sequence) 0xF ADC_AWD3TR ADC_AWD3TR ADC watchdog threshold register 0x2c 0x20 0x0FFF0000 0xFFFFFFFF LT3 Analog watchdog 3lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page355. 0 12 read-write HT3 Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page355. 16 12 read-write ADC_DR ADC_DR ADC data register 0x40 0x20 0x00000000 0xFFFFFFFF DATA Converted data These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in OVSE = 0) on page349. Just after a calibration is complete, DATA[6:0] contains the calibration factor. 0 16 read-only ADC_AWD2CR ADC_AWD2CR ADC Analog Watchdog 2 Configuration register 0xa0 0x20 0x00000000 0xFFFFFFFF AWD2CH0 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH1 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 1 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH2 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 2 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH3 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 3 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH4 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 4 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH5 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 5 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH6 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 6 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH7 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 7 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH8 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 8 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH9 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 9 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH10 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 10 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH11 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 11 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH12 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 12 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH13 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 13 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH14 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 14 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH15 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 15 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH16 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 16 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH17 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 17 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 AWD2CH18 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 18 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD2 0x0 B_0x1 ADC analog channel-x is monitored by AWD2 0x1 ADC_AWD3CR ADC_AWD3CR ADC Analog Watchdog 3 Configuration register 0xa4 0x20 0x00000000 0xFFFFFFFF AWD3CH0 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH1 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 1 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH2 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 2 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH3 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 3 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH4 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 4 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH5 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 5 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH6 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 6 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH7 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 7 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH8 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 8 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH9 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 9 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH10 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 10 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH11 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 11 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH12 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 12 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH13 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 13 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH14 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 14 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH15 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 15 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH16 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 16 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH17 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 17 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 AWD3CH18 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 18 1 read-write B_0x0 ADC analog channel-x is not monitored by AWD3 0x0 B_0x1 ADC analog channel-x is monitored by AWD3 0x1 ADC_CALFACT ADC_CALFACT ADC Calibration factor 0xb4 0x20 0x00000000 0xFFFFFFFF CALFACT Calibration factor These bits are written by hardware or by software. Once a calibration is complete,they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new calibration is launched. Just after a calibration is complete, DATA[6:0] contains the calibration factor. Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). Refer to SQ8[3:0] for a definition of channel selection. 0 7 read-write ADC_CCR ADC_CCR ADC common configuration register 0x308 0x20 0x00000000 0xFFFFFFFF PRESC ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). 18 4 read-write B_0x0 input ADC clock not divided 0x0 B_0x1 input ADC clock divided by 2 0x1 B_0x2 input ADC clock divided by 4 0x2 B_0x3 input ADC clock divided by 6 0x3 B_0x4 input ADC clock divided by 8 0x4 B_0x5 input ADC clock divided by 10 0x5 B_0x6 input ADC clock divided by 12 0x6 B_0x7 input ADC clock divided by 16 0x7 B_0x8 input ADC clock divided by 32 0x8 B_0x9 input ADC clock divided by 64 0x9 B_0xA input ADC clock divided by 128 0xA B_0xB input ADC clock divided by 256 0xB VREFEN VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 22 1 read-write B_0x0 VREFINT disabled 0x0 B_0x1 VREFINT enabled 0x1 TSEN Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 23 1 read-write B_0x0 Temperature sensor disabled 0x0 B_0x1 Temperature sensor enabled 0x1 VBATEN VBAT enable This bit is set and cleared by software to enable/disable the VBAT channel. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing) 24 1 read-write B_0x0 VBAT channel disabled 0x0 B_0x1 VBAT channel enabled 0x1 CRC Cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers CRC_DR CRC_DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data register bits 0 32 CRC_IDR CRC_IDR Independent data register 0x4 0x20 read-write 0x00000000 IDR General-purpose 32-bit data register bits 0 32 CRC_CR CRC_CR Control register 0x8 0x20 0x00000000 REV_OUT Reverse output data This bit controls the reversal of the bit order of the output data. 7 1 read-write B_0x0 Bit order not affected 0x0 B_0x1 Bit-reversed output format 0x1 REV_IN Reverse input data These bits control the reversal of the bit order of the input data 5 2 read-write B_0x0 Bit order not affected 0x0 B_0x1 Bit reversal done by byte 0x1 B_0x2 Bit reversal done by half-word 0x2 B_0x3 Bit reversal done by word 0x3 POLYSIZE Polynomial size These bits control the size of the polynomial. 3 2 read-write B_0x0 32 bit polynomial 0x0 B_0x1 16 bit polynomial 0x1 B_0x2 8 bit polynomial 0x2 B_0x3 7 bit polynomial 0x3 RESET RESET bit 0 1 write-only CRC_INIT CRC_INIT Initial CRC value 0x10 0x20 read-write 0xFFFFFFFF CRC_INIT Programmable initial CRC value 0 32 CRC_POL CRC_POL polynomial 0x14 0x20 read-write 0x04C11DB7 POL Programmable polynomial 0 32 DBG Debug support DBG 0x40015800 0x0 0x400 registers IDCODE IDCODE MCU Device ID Code Register 0x0 0x20 read-only 0x0 DEV_ID Device Identifier 0 12 REV_ID Revision Identifier 16 16 DBG_CR DBG_CR DBG configuration register 0x4 0x20 read-write 0x00000000 DBG_STOP Debug Stop mode Debug options in Stop mode. Upon Stop mode exit, the software must re-establish the desired clock configuration. 1 1 read-write B_0x0 All clocks disabled, including FCLK and HCLK. Upon Stop mode exit, the CPU is clocked by the HSI internal RC oscillator. 0x0 B_0x1 FCLK and HCLK running, derived from the internal RC oscillator remaining active. If Systick is enabled, it may generate periodic interrupt and wake up events. 0x1 DBG_STANDBY Debug Standby and Shutdown modes Debug options in Standby or Shutdown mode. 2 1 read-write B_0x0 Digital part powered. From software point of view, exiting Standby and Shutdown modes is identical as fetching reset vector (except for status bits indicating that the MCU exits Standby) 0x0 B_0x1 Digital part powered and FCLK and HCLK running, derived from the internal RC oscillator remaining active. The MCU generates a system reset so that exiting Standby and Shutdown has the same effect as starting from reset. 0x1 DBG_APB_FZ1 DBG_APB_FZ1 DBG APB freeze register 1 0x8 0x20 read-write 0x00000000 DBG_TIM3_STOP Clocking of TIM3 counter when the core is halted This bit enables/disables the clock to the counter of TIM3 when the core is halted: 1 1 read-write B_0x0 Enable 0x0 B_0x1 Disable 0x1 DBG_TIM6_STOP Clocking of TIM6 counter when the core is halted This bit enables/disables the clock to the counter of TIM6 when the core is halted: 4 1 read-write B_0x0 Enable 0x0 B_0x1 Disable 0x1 DBG_TIM7_STOP Clocking of TIM7 counter when the core is halted. This bit enables/disables the clock to the counter of ITIM7 when the core is halted: 5 1 read-write B_0x0 Enable 0x0 B_0x1 Disable 0x1 DBG_RTC_STOP Clocking of RTC counter when the core is halted This bit enables/disables the clock to the counter of RTC when the core is halted: 10 1 read-write B_0x0 Enable 0x0 B_0x1 Disable 0x1 DBG_WWDG_STOP Clocking of WWDG counter when the core is halted This bit enables/disables the clock to the counter of WWDG when the core is halted: 11 1 read-write B_0x0 Enable 0x0 B_0x1 Disable 0x1 DBG_IWDG_STOP Clocking of IWDG counter when the core is halted This bit enables/disables the clock to the counter of IWDG when the core is halted: 12 1 read-write B_0x0 Enable 0x0 B_0x1 Disable 0x1 DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout when core is halted 21 1 read-write B_0x0 Same behavior as in normal mode 0x0 B_0x1 The SMBUS timeout is frozen 0x1 DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout when core is halted 22 1 read-write DBG_APB_FZ2 DBG_APB_FZ2 DBG APB freeze register 2 0xc 0x20 read-write 0x00000000 DBG_TIM1_STOP Clocking of TIM1 counter when the core is halted This bit enables/disables the clock to the counter of TIM1 when the core is halted: 11 1 read-write B_0x0 Enable 0x0 B_0x1 Disable 0x1 DBG_TIM14_STOP Clocking of TIM14 counter when the core is halted This bit enables/disables the clock to the counter of TIM14 when the core is halted: 15 1 read-write B_0x0 Enable 0x0 B_0x1 Disable 0x1 DBG_TIM15_STOP Clocking of TIM15 counter when the core is halted This bit enables/disables the clock to the counter of TIM15 when the core is halted: Only available on STM32G071xx and STM32G081xx, reserved on STM32G031xx and STM32G041xx. 16 1 read-write B_0x0 Enable 0x0 B_0x1 Disable 0x1 DBG_TIM16_STOP Clocking of TIM16 counter when the core is halted This bit enables/disables the clock to the counter of TIM16 when the core is halted: 17 1 read-write B_0x0 Enable 0x0 B_0x1 Disable 0x1 DBG_TIM17_STOP Clocking of TIM17 counter when the core is halted This bit enables/disables the clock to the counter of TIM17 when the core is halted: 18 1 read-write B_0x0 Enable 0x0 B_0x1 Disable 0x1 DMA DMA controller DMA 0x40020000 0x0 0x400 registers DMA_Channel1 DMA channel 1 interrupt 9 DMA_Channel2_3 DMA channel 2 and 3 interrupts 10 DMA_ISR DMA_ISR DMA interrupt status register 0x0 0x20 0x00000000 0xFFFFFFFF GIF1 global interrupt flag for channel 1 0 1 read-only B_0x0 no TE, HT or TC event 0x0 B_0x1 a TE, HT or TC event occurred 0x1 TCIF1 transfer complete (TC) flag for channel 1 1 1 read-only B_0x0 no TC event 0x0 B_0x1 a TC event occurred 0x1 HTIF1 half transfer (HT) flag for channel 1 2 1 read-only B_0x0 no HT event 0x0 B_0x1 a HT event occurred 0x1 TEIF1 transfer error (TE) flag for channel 1 3 1 read-only B_0x0 no TE event 0x0 B_0x1 a TE event occurred 0x1 GIF2 global interrupt flag for channel 2 4 1 read-only B_0x0 no TE, HT or TC event 0x0 B_0x1 a TE, HT or TC event occurred 0x1 TCIF2 transfer complete (TC) flag for channel 2 5 1 read-only B_0x0 no TC event 0x0 B_0x1 a TC event occurred 0x1 HTIF2 half transfer (HT) flag for channel 2 6 1 read-only B_0x0 no HT event 0x0 B_0x1 a HT event occurred 0x1 TEIF2 transfer error (TE) flag for channel 2 7 1 read-only B_0x0 no TE event 0x0 B_0x1 a TE event occurred 0x1 GIF3 global interrupt flag for channel 3 8 1 read-only B_0x0 no TE, HT or TC event 0x0 B_0x1 a TE, HT or TC event occurred 0x1 TCIF3 transfer complete (TC) flag for channel 3 9 1 read-only B_0x0 no TC event 0x0 B_0x1 a TC event occurred 0x1 HTIF3 half transfer (HT) flag for channel 3 10 1 read-only B_0x0 no HT event 0x0 B_0x1 a HT event occurred 0x1 TEIF3 transfer error (TE) flag for channel 3 11 1 read-only B_0x0 no TE event 0x0 B_0x1 a TE event occurred 0x1 GIF4 global interrupt flag for channel 4 12 1 read-only B_0x0 no TE, HT or TC event 0x0 B_0x1 a TE, HT or TC event occurred 0x1 TCIF4 transfer complete (TC) flag for channel 4 13 1 read-only B_0x0 no TC event 0x0 B_0x1 a TC event occurred 0x1 HTIF4 half transfer (HT) flag for channel 4 14 1 read-only B_0x0 no HT event 0x0 B_0x1 a HT event occurred 0x1 TEIF4 transfer error (TE) flag for channel 4 15 1 read-only B_0x0 no TE event 0x0 B_0x1 a TE event occurred 0x1 GIF5 global interrupt flag for channel 5 16 1 read-only B_0x0 no TE, HT or TC event 0x0 B_0x1 a TE, HT or TC event occurred 0x1 TCIF5 transfer complete (TC) flag for channel 5 17 1 read-only B_0x0 no TC event 0x0 B_0x1 a TC event occurred 0x1 HTIF5 half transfer (HT) flag for channel 5 18 1 read-only B_0x0 no HT event 0x0 B_0x1 a HT event occurred 0x1 TEIF5 transfer error (TE) flag for channel 5 19 1 read-only B_0x0 no TE event 0x0 B_0x1 a TE event occurred 0x1 GIF6 global interrupt flag for channel 6 20 1 read-only B_0x0 no TE, HT or TC event 0x0 B_0x1 a TE, HT or TC event occurred 0x1 TCIF6 transfer complete (TC) flag for channel 6 21 1 read-only B_0x0 no TC event 0x0 B_0x1 a TC event occurred 0x1 HTIF6 half transfer (HT) flag for channel 6 22 1 read-only B_0x0 no HT event 0x0 B_0x1 a HT event occurred 0x1 TEIF6 transfer error (TE) flag for channel 6 23 1 read-only B_0x0 no TE event 0x0 B_0x1 a TE event occurred 0x1 GIF7 global interrupt flag for channel 7 24 1 read-only B_0x0 no TE, HT or TC event 0x0 B_0x1 a TE, HT or TC event occurred 0x1 TCIF7 transfer complete (TC) flag for channel 7 25 1 read-only B_0x0 no TC event 0x0 B_0x1 a TC event occurred 0x1 HTIF7 half transfer (HT) flag for channel 7 26 1 read-only B_0x0 no HT event 0x0 B_0x1 a HT event occurred 0x1 TEIF7 transfer error (TE) flag for channel 7 27 1 read-only B_0x0 no TE event 0x0 B_0x1 a TE event occurred 0x1 DMA_IFCR DMA_IFCR DMA interrupt flag clear register 0x4 0x20 0x00000000 0xFFFFFFFF CGIF1 global interrupt flag clear for channel 1 0 1 write-only CTCIF1 transfer complete flag clear for channel 1 1 1 write-only CHTIF1 half transfer flag clear for channel 1 2 1 write-only CTEIF1 transfer error flag clear for channel 1 3 1 write-only CGIF2 global interrupt flag clear for channel 2 4 1 write-only CTCIF2 transfer complete flag clear for channel 2 5 1 write-only CHTIF2 half transfer flag clear for channel 2 6 1 write-only CTEIF2 transfer error flag clear for channel 2 7 1 write-only CGIF3 global interrupt flag clear for channel 3 8 1 write-only CTCIF3 transfer complete flag clear for channel 3 9 1 write-only CHTIF3 half transfer flag clear for channel 3 10 1 write-only CTEIF3 transfer error flag clear for channel 3 11 1 write-only CGIF4 global interrupt flag clear for channel 4 12 1 write-only CTCIF4 transfer complete flag clear for channel 4 13 1 write-only CHTIF4 half transfer flag clear for channel 4 14 1 write-only CTEIF4 transfer error flag clear for channel 4 15 1 write-only CGIF5 global interrupt flag clear for channel 5 16 1 write-only CTCIF5 transfer complete flag clear for channel 5 17 1 write-only CHTIF5 half transfer flag clear for channel 5 18 1 write-only CTEIF5 transfer error flag clear for channel 5 19 1 write-only CGIF6 global interrupt flag clear for channel 6 20 1 write-only CTCIF6 transfer complete flag clear for channel 6 21 1 write-only CHTIF6 half transfer flag clear for channel 6 22 1 write-only CTEIF6 transfer error flag clear for channel 6 23 1 write-only CGIF7 global interrupt flag clear for channel 7 24 1 write-only CTCIF7 transfer complete flag clear for channel 7 25 1 write-only CHTIF7 half transfer flag clear for channel 7 26 1 write-only CTEIF7 transfer error flag clear for channel 7 27 1 write-only DMA_CCR1 DMA_CCR1 DMA channel 1 configuration register 0x8 0x20 0x00000000 0xFFFFFFFF EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software. 0 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TCIE transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 1 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 HTIE half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 2 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TEIE transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 3 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 4 1 read-write B_0x0 read from peripheral 0x0 B_0x1 read from memory 0x1 CIRC circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 5 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 6 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 7 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 8 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 10 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 PL priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 12 2 read-write B_0x0 low 0x0 B_0x1 medium 0x1 B_0x2 high 0x2 B_0x3 very high 0x3 MEM2MEM memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 14 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DMA_CNDTR1 DMA_CNDTR1 DMA channel x number of data register 0xc 0x20 0x00000000 0xFFFFFFFF NDT number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write’ transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 0 16 read-write DMA_CPAR1 DMA_CPAR1 DMA channel x peripheral address register 0x10 0x20 0x00000000 0xFFFFFFFF PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CMAR1 DMA_CMAR1 DMA channel x memory address register 0x14 0x20 0x00000000 0xFFFFFFFF MA peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CCR2 DMA_CCR2 DMA channel 2 configuration register 0x1c 0x20 0x00000000 0xFFFFFFFF EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software. 0 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TCIE transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 1 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 HTIE half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 2 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TEIE transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 3 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 4 1 read-write B_0x0 read from peripheral 0x0 B_0x1 read from memory 0x1 CIRC circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 5 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 6 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 7 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 8 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 10 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 PL priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 12 2 read-write B_0x0 low 0x0 B_0x1 medium 0x1 B_0x2 high 0x2 B_0x3 very high 0x3 MEM2MEM memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 14 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DMA_CNDTR2 DMA_CNDTR2 DMA channel x number of data register 0x20 0x20 0x00000000 0xFFFFFFFF NDT number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write’ transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 0 16 read-write DMA_CPAR2 DMA_CPAR2 DMA channel x peripheral address register 0x24 0x20 0x00000000 0xFFFFFFFF PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CMAR2 DMA_CMAR2 DMA channel x memory address register 0x28 0x20 0x00000000 0xFFFFFFFF MA peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CCR3 DMA_CCR3 DMA channel 3 configuration register 0x30 0x20 0x00000000 0xFFFFFFFF EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software. 0 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TCIE transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 1 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 HTIE half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 2 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TEIE transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 3 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 4 1 read-write B_0x0 read from peripheral 0x0 B_0x1 read from memory 0x1 CIRC circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 5 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 6 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 7 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 8 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 10 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 PL priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 12 2 read-write B_0x0 low 0x0 B_0x1 medium 0x1 B_0x2 high 0x2 B_0x3 very high 0x3 MEM2MEM memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 14 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DMA_CNDTR3 DMA_CNDTR3 DMA channel x configuration register 0x34 0x20 0x00000000 0xFFFFFFFF NDT number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write’ transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 0 16 read-write DMA_CPAR3 DMA_CPAR3 DMA channel x peripheral address register 0x38 0x20 0x00000000 0xFFFFFFFF PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CMAR3 DMA_CMAR3 DMA channel x memory address register 0x3c 0x20 0x00000000 0xFFFFFFFF MA peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CCR4 DMA_CCR4 DMA channel 4 configuration register 0x44 0x20 0x00000000 0xFFFFFFFF EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software. 0 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TCIE transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 1 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 HTIE half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 2 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TEIE transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 3 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 4 1 read-write B_0x0 read from peripheral 0x0 B_0x1 read from memory 0x1 CIRC circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 5 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 6 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 7 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 8 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 10 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 PL priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 12 2 read-write B_0x0 low 0x0 B_0x1 medium 0x1 B_0x2 high 0x2 B_0x3 very high 0x3 MEM2MEM memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 14 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DMA_CNDTR4 DMA_CNDTR4 DMA channel x configuration register 0x48 0x20 0x00000000 0xFFFFFFFF NDT number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write’ transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 0 16 read-write DMA_CPAR4 DMA_CPAR4 DMA channel x peripheral address register 0x4c 0x20 0x00000000 0xFFFFFFFF PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CMAR4 DMA_CMAR4 DMA channel x memory address register 0x50 0x20 0x00000000 0xFFFFFFFF MA peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CCR5 DMA_CCR5 DMA channel 5 configuration register 0x58 0x20 0x00000000 0xFFFFFFFF EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software. 0 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TCIE transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 1 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 HTIE half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 2 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TEIE transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 3 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 4 1 read-write B_0x0 read from peripheral 0x0 B_0x1 read from memory 0x1 CIRC circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 5 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 6 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 7 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 8 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 10 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 PL priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 12 2 read-write B_0x0 low 0x0 B_0x1 medium 0x1 B_0x2 high 0x2 B_0x3 very high 0x3 MEM2MEM memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 14 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DMA_CNDTR5 DMA_CNDTR5 DMA channel x configuration register 0x5c 0x20 0x00000000 0xFFFFFFFF NDT number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write’ transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 0 16 read-write DMA_CPAR5 DMA_CPAR5 DMA channel x peripheral address register 0x60 0x20 0x00000000 0xFFFFFFFF PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CMAR5 DMA_CMAR5 DMA channel x memory address register 0x64 0x20 0x00000000 0xFFFFFFFF MA peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CCR6 DMA_CCR6 DMA channel 6 configuration register 0x6c 0x20 0x00000000 0xFFFFFFFF EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software. 0 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TCIE transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 1 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 HTIE half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 2 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TEIE transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 3 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 4 1 read-write B_0x0 read from peripheral 0x0 B_0x1 read from memory 0x1 CIRC circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 5 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 6 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 7 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 8 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 10 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 PL priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 12 2 read-write B_0x0 low 0x0 B_0x1 medium 0x1 B_0x2 high 0x2 B_0x3 very high 0x3 MEM2MEM memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 14 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DMA_CNDTR6 DMA_CNDTR6 DMA channel x configuration register 0x70 0x20 0x00000000 0xFFFFFFFF NDT number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write’ transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 0 16 read-write DMA_CPAR6 DMA_CPAR6 DMA channel x peripheral address register 0x74 0x20 0x00000000 0xFFFFFFFF PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CMAR6 DMA_CMAR6 DMA channel x memory address register 0x78 0x20 0x00000000 0xFFFFFFFF MA peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CCR7 DMA_CCR7 DMA channel 7 configuration register 0x80 0x20 0x00000000 0xFFFFFFFF EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software. 0 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TCIE transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 1 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 HTIE half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 2 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 TEIE transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 3 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 4 1 read-write B_0x0 read from peripheral 0x0 B_0x1 read from memory 0x1 CIRC circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 5 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 6 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 7 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 8 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 10 2 read-write B_0x0 8 bits 0x0 B_0x1 16 bits 0x1 B_0x2 32 bits 0x2 PL priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 12 2 read-write B_0x0 low 0x0 B_0x1 medium 0x1 B_0x2 high 0x2 B_0x3 very high 0x3 MEM2MEM memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 14 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 DMA_CNDTR7 DMA_CNDTR7 DMA channel x configuration register 0x84 0x20 0x00000000 0xFFFFFFFF NDT number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write’ transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1). 0 16 read-write DMA_CPAR7 DMA_CPAR7 DMA channel x peripheral address register 0x88 0x20 0x00000000 0xFFFFFFFF PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMA_CMAR7 DMA_CMAR7 DMA channel x memory address register 0x8c 0x20 0x00000000 0xFFFFFFFF MA peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1). 0 32 read-write DMAMUX DMAMUX DMAMUX 0x40020800 0x0 0x800 registers DMA1_Channel4_5_6_7_DMAMUX_DMA2_Channel1_2_3_4_5 DMA1 channel 4, 5, 6, 7, DMAMUX,DMA2 channel 1, 2, 3, 4, 5 interrupts 11 DMAMUX_C0CR DMAMUX_C0CR DMAMUX request line multiplexer channel x configuration register 0x0 0x20 read-write 0x00000000 DMAREQ_ID DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. 0 6 read-write SOIE Synchronization overrun interrupt enable 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 EGE Event generation enable 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 SE Synchronization enable 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SPOL Synchronization polarity Defines the edge polarity of the selected synchronization input: 17 2 read-write B_0x0 no event, i.e. no synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 NBREQ Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low. 19 5 read-write SYNC_ID Synchronization identification Selects the synchronization input (see inputs to resources STM32G0). 24 5 read-write DMAMUX_C1CR DMAMUX_C1CR DMAMUX request line multiplexer channel x configuration register 0x4 0x20 read-write 0x00000000 DMAREQ_ID DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. 0 6 read-write SOIE Synchronization overrun interrupt enable 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 EGE Event generation enable 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 SE Synchronization enable 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SPOL Synchronization polarity Defines the edge polarity of the selected synchronization input: 17 2 read-write B_0x0 no event, i.e. no synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 NBREQ Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low. 19 5 read-write SYNC_ID Synchronization identification Selects the synchronization input (see inputs to resources STM32G0). 24 5 read-write DMAMUX_C2CR DMAMUX_C2CR DMAMUX request line multiplexer channel x configuration register 0x8 0x20 read-write 0x00000000 DMAREQ_ID DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. 0 6 read-write SOIE Synchronization overrun interrupt enable 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 EGE Event generation enable 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 SE Synchronization enable 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SPOL Synchronization polarity Defines the edge polarity of the selected synchronization input: 17 2 read-write B_0x0 no event, i.e. no synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 NBREQ Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low. 19 5 read-write SYNC_ID Synchronization identification Selects the synchronization input (see inputs to resources STM32G0). 24 5 read-write DMAMUX_C3CR DMAMUX_C3CR DMAMUX request line multiplexer channel x configuration register 0xC 0x20 read-write 0x00000000 DMAREQ_ID DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. 0 6 read-write SOIE Synchronization overrun interrupt enable 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 EGE Event generation enable 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 SE Synchronization enable 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SPOL Synchronization polarity Defines the edge polarity of the selected synchronization input: 17 2 read-write B_0x0 no event, i.e. no synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 NBREQ Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low. 19 5 read-write SYNC_ID Synchronization identification Selects the synchronization input (see inputs to resources STM32G0). 24 5 read-write DMAMUX_C4CR DMAMUX_C4CR DMAMUX request line multiplexer channel x configuration register 0x10 0x20 read-write 0x00000000 DMAREQ_ID DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. 0 6 read-write SOIE Synchronization overrun interrupt enable 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 EGE Event generation enable 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 SE Synchronization enable 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SPOL Synchronization polarity Defines the edge polarity of the selected synchronization input: 17 2 read-write B_0x0 no event, i.e. no synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 NBREQ Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low. 19 5 read-write SYNC_ID Synchronization identification Selects the synchronization input (see inputs to resources STM32G0). 24 5 read-write DMAMUX_C5CR DMAMUX_C5CR DMAMUX request line multiplexer channel x configuration register 0x14 0x20 read-write 0x00000000 DMAREQ_ID DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. 0 6 read-write SOIE Synchronization overrun interrupt enable 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 EGE Event generation enable 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 SE Synchronization enable 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SPOL Synchronization polarity Defines the edge polarity of the selected synchronization input: 17 2 read-write B_0x0 no event, i.e. no synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 NBREQ Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low. 19 5 read-write SYNC_ID Synchronization identification Selects the synchronization input (see inputs to resources STM32G0). 24 5 read-write DMAMUX_C6CR DMAMUX_C6CR DMAMUX request line multiplexer channel x configuration register 0x18 0x20 read-write 0x00000000 DMAREQ_ID DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. 0 6 read-write SOIE Synchronization overrun interrupt enable 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 EGE Event generation enable 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 SE Synchronization enable 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SPOL Synchronization polarity Defines the edge polarity of the selected synchronization input: 17 2 read-write B_0x0 no event, i.e. no synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 NBREQ Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low. 19 5 read-write SYNC_ID Synchronization identification Selects the synchronization input (see inputs to resources STM32G0). 24 5 read-write DMAMUX_C7CR DMAMUX_C7CR DMAMUX request line multiplexer channel x configuration register 0x1C 0x20 read-write 0x00000000 DMAREQ_ID DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. 0 6 read-write SOIE Synchronization overrun interrupt enable 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 EGE Event generation enable 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 SE Synchronization enable 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SPOL Synchronization polarity Defines the edge polarity of the selected synchronization input: 17 2 read-write B_0x0 no event, i.e. no synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 NBREQ Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low. 19 5 read-write SYNC_ID Synchronization identification Selects the synchronization input (see inputs to resources STM32G0). 24 5 read-write DMAMUX_C8CR DMAMUX_C8CR DMAMUX request line multiplexer channel x configuration register 0x20 0x20 read-write 0x00000000 DMAREQ_ID DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. 0 6 read-write SOIE Synchronization overrun interrupt enable 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 EGE Event generation enable 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 SE Synchronization enable 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SPOL Synchronization polarity Defines the edge polarity of the selected synchronization input: 17 2 read-write B_0x0 no event, i.e. no synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 NBREQ Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low. 19 5 read-write SYNC_ID Synchronization identification Selects the synchronization input (see inputs to resources STM32G0). 24 5 read-write DMAMUX_C9CR DMAMUX_C9CR DMAMUX request line multiplexer channel x configuration register 0x24 0x20 read-write 0x00000000 DMAREQ_ID DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. 0 6 read-write SOIE Synchronization overrun interrupt enable 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 EGE Event generation enable 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 SE Synchronization enable 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SPOL Synchronization polarity Defines the edge polarity of the selected synchronization input: 17 2 read-write B_0x0 no event, i.e. no synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 NBREQ Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low. 19 5 read-write SYNC_ID Synchronization identification Selects the synchronization input (see inputs to resources STM32G0). 24 5 read-write DMAMUX_C10CR DMAMUX_C10CR DMAMUX request line multiplexer channel x configuration register 0x28 0x20 read-write 0x00000000 DMAREQ_ID DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. 0 6 read-write SOIE Synchronization overrun interrupt enable 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 EGE Event generation enable 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 SE Synchronization enable 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SPOL Synchronization polarity Defines the edge polarity of the selected synchronization input: 17 2 read-write B_0x0 no event, i.e. no synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 NBREQ Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low. 19 5 read-write SYNC_ID Synchronization identification Selects the synchronization input (see inputs to resources STM32G0). 24 5 read-write DMAMUX_C11CR DMAMUX_C11CR DMAMUX request line multiplexer channel x configuration register 0x2C 0x20 read-write 0x00000000 DMAREQ_ID DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. 0 6 read-write SOIE Synchronization overrun interrupt enable 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 EGE Event generation enable 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 SE Synchronization enable 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SPOL Synchronization polarity Defines the edge polarity of the selected synchronization input: 17 2 read-write B_0x0 no event, i.e. no synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 NBREQ Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low. 19 5 read-write SYNC_ID Synchronization identification Selects the synchronization input (see inputs to resources STM32G0). 24 5 read-write DMAMUX_CSR DMAMUX_CSR DMAMUX request line multiplexer interrupt channel status register 0x80 0x20 read-only 0x00000000 SOF0 Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. 0 1 read-only SOF1 Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. 1 1 read-only SOF2 Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. 2 1 read-only SOF3 Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. 3 1 read-only SOF4 Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. 4 1 read-only SOF5 Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. 5 1 read-only SOF6 Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. 6 1 read-only SOF7 Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. 7 1 read-only SOF8 Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. 8 1 read-only SOF9 Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. 9 1 read-only SOF10 Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. 10 1 read-only SOF11 Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. 11 1 read-only DMAMUX_CFR DMAMUX_CFR DMAMUX request line multiplexer interrupt clear flag register 0x84 0x20 write-only 0x00000000 CSOF0 Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. 0 1 write-only CSOF1 Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. 1 1 write-only CSOF2 Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. 2 1 write-only CSOF3 Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. 3 1 write-only CSOF4 Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. 4 1 write-only CSOF5 Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. 5 1 write-only CSOF6 Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. 6 1 write-only CSOF7 Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. 7 1 read-only CSOF8 Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. 8 1 read-only CSOF9 Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. 9 1 read-only CSOF10 Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. 10 1 read-only CSOF11 Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. 11 1 read-only DMAMUX_RG0CR DMAMUX_RG0CR DMAMUX request generator channel x configuration register 0x100 0x20 read-write 0x00000000 SIG_ID Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator 0 5 read-write OIE Trigger overrun interrupt enable 8 1 read-write B_0x0 interrupt on a trigger overrun event occurrence is disabled 0x0 B_0x1 interrupt on a trigger overrun event occurrence is enabled 0x1 GE DMA request generator channel x enable 16 1 read-write B_0x0 DMA request generator channel x disabled 0x0 B_0x1 DMA request generator channel x enabled 0x1 GPOL DMA request generator trigger polarity Defines the edge polarity of the selected trigger input 17 2 read-write B_0x0 no event. I.e. none trigger detection nor generation. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 GNBREQ Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled. 19 5 read-write DMAMUX_RG1CR DMAMUX_RG1CR DMAMUX request generator channel x configuration register 0x104 0x20 read-write 0x00000000 SIG_ID Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator 0 5 read-write OIE Trigger overrun interrupt enable 8 1 read-write B_0x0 interrupt on a trigger overrun event occurrence is disabled 0x0 B_0x1 interrupt on a trigger overrun event occurrence is enabled 0x1 GE DMA request generator channel x enable 16 1 read-write B_0x0 DMA request generator channel x disabled 0x0 B_0x1 DMA request generator channel x enabled 0x1 GPOL DMA request generator trigger polarity Defines the edge polarity of the selected trigger input 17 2 read-write B_0x0 no event. I.e. none trigger detection nor generation. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 GNBREQ Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled. 19 5 read-write DMAMUX_RG2CR DMAMUX_RG2CR DMAMUX request generator channel x configuration register 0x108 0x20 read-write 0x00000000 SIG_ID Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator 0 5 read-write OIE Trigger overrun interrupt enable 8 1 read-write B_0x0 interrupt on a trigger overrun event occurrence is disabled 0x0 B_0x1 interrupt on a trigger overrun event occurrence is enabled 0x1 GE DMA request generator channel x enable 16 1 read-write B_0x0 DMA request generator channel x disabled 0x0 B_0x1 DMA request generator channel x enabled 0x1 GPOL DMA request generator trigger polarity Defines the edge polarity of the selected trigger input 17 2 read-write B_0x0 no event. I.e. none trigger detection nor generation. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 GNBREQ Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled. 19 5 read-write DMAMUX_RG3CR DMAMUX_RG3CR DMAMUX request generator channel x configuration register 0x10C 0x20 read-write 0x00000000 SIG_ID Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator 0 5 read-write OIE Trigger overrun interrupt enable 8 1 read-write B_0x0 interrupt on a trigger overrun event occurrence is disabled 0x0 B_0x1 interrupt on a trigger overrun event occurrence is enabled 0x1 GE DMA request generator channel x enable 16 1 read-write B_0x0 DMA request generator channel x disabled 0x0 B_0x1 DMA request generator channel x enabled 0x1 GPOL DMA request generator trigger polarity Defines the edge polarity of the selected trigger input 17 2 read-write B_0x0 no event. I.e. none trigger detection nor generation. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 GNBREQ Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled. 19 5 read-write DMAMUX_RGSR DMAMUX_RGSR DMAMUX request generator interrupt status register 0x140 0x20 read-only 0x00000000 OF0 Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. 0 1 read-only OF1 Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. 1 1 read-only OF2 Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. 2 1 read-only OF3 Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. 3 1 read-only DMAMUX_RGCFR DMAMUX_RGCFR DMAMUX request generator interrupt clear flag register 0x144 0x20 write-only 0x00000000 COF0 Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. 0 1 write-only COF1 Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. 1 1 write-only COF2 Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. 2 1 write-only COF3 Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. 3 1 write-only EXTI External interrupt/event controller EXTI 0x40021800 0x0 0x400 registers EXTI0_1 EXTI line 0 and 1 interrupt 5 EXTI2_3 EXTI line 2 and 3 interrupt 6 EXTI4_15 EXTI line 4 to 15 interrupt 7 RTSR1 RTSR1 EXTI rising trigger selection register 0x0 0x20 read-write 0x00000000 RT0 Rising trigger event configuration bit of Configurable Event line 0 1 RT1 Rising trigger event configuration bit of Configurable Event line 1 1 RT2 Rising trigger event configuration bit of Configurable Event line 2 1 RT3 Rising trigger event configuration bit of Configurable Event line 3 1 RT4 Rising trigger event configuration bit of Configurable Event line 4 1 RT5 Rising trigger event configuration bit of Configurable Event line 5 1 RT6 Rising trigger event configuration bit of Configurable Event line 6 1 RT7 Rising trigger event configuration bit of Configurable Event line 7 1 RT8 Rising trigger event configuration bit of Configurable Event line 8 1 RT9 Rising trigger event configuration bit of Configurable Event line 9 1 RT10 Rising trigger event configuration bit of Configurable Event line 10 1 RT11 Rising trigger event configuration bit of Configurable Event line 11 1 RT12 Rising trigger event configuration bit of Configurable Event line 12 1 RT13 Rising trigger event configuration bit of Configurable Event line 13 1 RT14 Rising trigger event configuration bit of Configurable Event line 14 1 RT15 Rising trigger event configuration bit of Configurable Event line 15 1 FTSR1 FTSR1 EXTI falling trigger selection register 0x4 0x20 read-write 0x00000000 FT0 Falling trigger event configuration bit of configurable line 0 1 FT1 Falling trigger event configuration bit of configurable line 1 1 FT2 Falling trigger event configuration bit of configurable line 2 1 FT3 Falling trigger event configuration bit of configurable line 3 1 FT4 Falling trigger event configuration bit of configurable line 4 1 FT5 Falling trigger event configuration bit of configurable line 5 1 FT6 Falling trigger event configuration bit of configurable line 6 1 FT7 Falling trigger event configuration bit of configurable line 7 1 FT8 Falling trigger event configuration bit of configurable line 8 1 FT9 Falling trigger event configuration bit of configurable line 9 1 FT10 Falling trigger event configuration bit of configurable line 10 1 FT11 Falling trigger event configuration bit of configurable line 11 1 FT12 Falling trigger event configuration bit of configurable line 12 1 FT13 Falling trigger event configuration bit of configurable line 13 1 FT14 Falling trigger event configuration bit of configurable line 14 1 FT15 Falling trigger event configuration bit of configurable line 15 1 SWIER1 SWIER1 EXTI software interrupt event register 0x8 0x20 read-write 0x00000000 SWI0 Software rising edge event trigger on line 0 1 SWI1 Software rising edge event trigger on line 1 1 SWI2 Software rising edge event trigger on line 2 1 SWI3 Software rising edge event trigger on line 3 1 SWI4 Software rising edge event trigger on line 4 1 SWI5 Software rising edge event trigger on line 5 1 SWI6 Software rising edge event trigger on line 6 1 SWI7 Software rising edge event trigger on line 7 1 SWI8 Software rising edge event trigger on line 8 1 SWI9 Software rising edge event trigger on line 9 1 SWI10 Software rising edge event trigger on line 10 1 SWI11 Software rising edge event trigger on line 11 1 SWI12 Software rising edge event trigger on line 12 1 SWI13 Software rising edge event trigger on line 13 1 SWI14 Software rising edge event trigger on line 14 1 SWI15 Software rising edge event trigger on line 15 1 RPR1 RPR1 EXTI rising edge pending register 0xC 0x20 read-write 0x00000000 RPIF0 Rising edge event pending for configurable line 0 1 RPIF1 Rising edge event pending for configurable line 1 1 RPIF2 Rising edge event pending for configurable line 2 1 RPIF3 Rising edge event pending for configurable line 3 1 RPIF4 Rising edge event pending for configurable line 4 1 RPIF5 configurable event inputs x rising edge Pending bit 5 1 RPIF6 Rising edge event pending for configurable line 6 1 RPIF7 Rising edge event pending for configurable line 7 1 RPIF8 Rising edge event pending for configurable line 8 1 RPIF9 Rising edge event pending for configurable line 9 1 RPIF10 Rising edge event pending for configurable line 10 1 RPIF11 Rising edge event pending for configurable line 11 1 RPIF12 Rising edge event pending for configurable line 12 1 RPIF13 Rising edge event pending for configurable line 13 1 RPIF14 Rising edge event pending for configurable line 14 1 RPIF15 Rising edge event pending for configurable line 15 1 FPR1 FPR1 EXTI falling edge pending register 0x10 0x20 read-write 0x00000000 FPIF0 Falling edge event pending for configurable line 0 1 FPIF1 Falling edge event pending for configurable line 1 1 FPIF2 Falling edge event pending for configurable line 2 1 FPIF3 Falling edge event pending for configurable line 3 1 FPIF4 Falling edge event pending for configurable line 4 1 FPIF5 Falling edge event pending for configurable line 5 1 FPIF6 Falling edge event pending for configurable line 6 1 FPIF7 Falling edge event pending for configurable line 7 1 FPIF8 Falling edge event pending for configurable line 8 1 FPIF9 Falling edge event pending for configurable line 9 1 FPIF10 Falling edge event pending for configurable line 10 1 FPIF11 Falling edge event pending for configurable line 11 1 FPIF12 Falling edge event pending for configurable line 12 1 FPIF13 Falling edge event pending for configurable line 13 1 FPIF14 Falling edge event pending for configurable line 14 1 FPIF15 Falling edge event pending for configurable line 15 1 EXTICR1 EXTICR1 EXTI external interrupt selection register 0x60 0x20 read-write 0x00000000 EXTI0_7 GPIO port selection 0 8 EXTI8_15 GPIO port selection 8 8 EXTI16_23 GPIO port selection 16 8 EXTI24_31 GPIO port selection 24 8 EXTICR2 EXTICR2 EXTI external interrupt selection register 0x64 0x20 read-write 0x00000000 EXTI0_7 GPIO port selection 0 8 EXTI8_15 GPIO port selection 8 8 EXTI16_23 GPIO port selection 16 8 EXTI24_31 GPIO port selection 24 8 EXTICR3 EXTICR3 EXTI external interrupt selection register 0x68 0x20 read-write 0x00000000 EXTI0_7 GPIO port selection 0 8 EXTI8_15 GPIO port selection 8 8 EXTI16_23 GPIO port selection 16 8 EXTI24_31 GPIO port selection 24 8 EXTICR4 EXTICR4 EXTI external interrupt selection register 0x6C 0x20 read-write 0x00000000 EXTI0_7 GPIO port selection 0 8 EXTI8_15 GPIO port selection 8 8 EXTI16_23 GPIO port selection 16 8 EXTI24_31 GPIO port selection 24 8 IMR1 IMR1 EXTI CPU wakeup with interrupt mask register 0x80 0x20 read-write 0xFFF80000 IM0 CPU wakeup with interrupt mask on event input 0 1 IM1 CPU wakeup with interrupt mask on event input 1 1 IM2 CPU wakeup with interrupt mask on event input 2 1 IM3 CPU wakeup with interrupt mask on event input 3 1 IM4 CPU wakeup with interrupt mask on event input 4 1 IM5 CPU wakeup with interrupt mask on event input 5 1 IM6 CPU wakeup with interrupt mask on event input 6 1 IM7 CPU wakeup with interrupt mask on event input 7 1 IM8 CPU wakeup with interrupt mask on event input 8 1 IM9 CPU wakeup with interrupt mask on event input 9 1 IM10 CPU wakeup with interrupt mask on event input 10 1 IM11 CPU wakeup with interrupt mask on event input 11 1 IM12 CPU wakeup with interrupt mask on event input 12 1 IM13 CPU wakeup with interrupt mask on event input 13 1 IM14 CPU wakeup with interrupt mask on event input 14 1 IM15 CPU wakeup with interrupt mask on event input 15 1 IM19 CPU wakeup with interrupt mask on event input 19 1 IM21 CPU wakeup with interrupt mask on event input 21 1 IM22 CPU wakeup with interrupt mask on event input 22 1 IM23 CPU wakeup with interrupt mask on event input 23 1 IM24 CPU wakeup with interrupt mask on event input 24 1 IM25 CPU wakeup with interrupt mask on event input 25 1 IM26 CPU wakeup with interrupt mask on event input 26 1 IM31 CPU wakeup with interrupt mask on event input 31 1 EMR1 EMR1 EXTI CPU wakeup with event mask register IMR1 0x84 0x20 read-write 0x00000000 EM0 CPU wakeup with event mask on event input 0 1 EM1 CPU wakeup with event mask on event input 1 1 EM2 CPU wakeup with event mask on event input 2 1 EM3 CPU wakeup with event mask on event input 3 1 EM4 CPU wakeup with event mask on event input 4 1 EM5 CPU wakeup with event mask on event input 5 1 EM6 CPU wakeup with event mask on event input 6 1 EM7 CPU wakeup with event mask on event input 7 1 EM8 CPU wakeup with event mask on event input 8 1 EM9 CPU wakeup with event mask on event input 9 1 EM10 CPU wakeup with event mask on event input 10 1 EM11 CPU wakeup with event mask on event input 11 1 EM12 CPU wakeup with event mask on event input 12 1 EM13 CPU wakeup with event mask on event input 13 1 EM14 CPU wakeup with event mask on event input 14 1 EM15 CPU wakeup with event mask on event input 15 1 EM19 CPU wakeup with event mask on event input 19 1 EM21 CPU wakeup with event mask on event input 21 1 EM23 CPU wakeup with event mask on event input 23 1 EM25 CPU wakeup with event mask on event input 25 1 EM26 CPU wakeup with event mask on event input 26 1 EM31 CPU wakeup with event mask on event input 31 1 FLASH Flash Flash 0x40022000 0x0 0x400 registers FLASH Flash global interrupt 3 ACR ACR Access control register 0x0 0x20 read-write 0x00000600 LATENCY Latency 0 3 PRFTEN Prefetch enable 8 1 ICEN Instruction cache enable 9 1 ICRST Instruction cache reset 11 1 EMPTY Flash User area empty 16 1 KEYR KEYR Flash key register 0x8 0x20 write-only 0x00000000 KEYR KEYR 0 32 OPTKEYR OPTKEYR Option byte key register 0xC 0x20 write-only 0x00000000 OPTKEYR Option byte key 0 32 SR SR Status register 0x10 0x20 read-write 0x00000000 EOP End of operation 0 1 OPERR Operation error 1 1 PROGERR Programming error 3 1 WRPERR Write protected error 4 1 PGAERR Programming alignment error 5 1 SIZERR Size error 6 1 PGSERR Programming sequence error 7 1 MISERR Fast programming data miss error 8 1 FASTERR Fast programming error 9 1 OPTVERR Option and Engineering bits loading validity error 15 1 BSY1 BSY1 16 1 BSY2 BSY2 17 1 CFGBSY Programming or erase configuration busy. 18 1 CR CR Flash control register 0x14 0x20 read-write 0xC0000000 PG Programming 0 1 PER Page erase 1 1 MER1 Mass erase 2 1 PNB Page number 3 10 BKER BKER 13 1 MER2 MER2 15 1 STRT Start 16 1 OPTSTRT Options modification start 17 1 FSTPG Fast programming 18 1 EOPIE End of operation interrupt enable 24 1 ERRIE Error interrupt enable 25 1 OBL_LAUNCH Force the option byte loading 27 1 OPTLOCK Options Lock 30 1 LOCK FLASH_CR Lock 31 1 ECCR ECCR Flash ECC register 0x18 0x20 0x00000000 ADDR_ECC ECC fail address 0 14 read-only SYSF_ECC ECC fail for Corrected ECC Error or Double ECC Error in info block 20 1 read-only ECCIE ECC correction interrupt enable 24 1 read-write ECCC ECC correction 30 1 read-write ECCD ECC detection 31 1 read-write OPTR OPTR Flash option register 0x20 0x20 read-write 0xF0000000 RDP Read protection level 0 8 nRST_STOP nRST_STOP 13 1 nRST_STDBY nRST_STDBY 14 1 IDWG_SW Independent watchdog selection 16 1 IWDG_STOP Independent watchdog counter freeze in Stop mode 17 1 IWDG_STDBY Independent watchdog counter freeze in Standby mode 18 1 WWDG_SW Window watchdog selection 19 1 nSWAP_BANK nSWAP_BANK 20 1 DUAL_BANK DUAL_BANK 21 1 RAM_PARITY_CHECK SRAM parity check control 22 1 nBOOT_SEL nBOOT_SEL 24 1 nBOOT1 Boot configuration 25 1 nBOOT0 nBOOT0 option bit 26 1 WRP1AR WRP1AR Flash WRP area A address register 0x2C 0x20 read-only 0xF0000000 WRP1A_STRT WRP area A start offset 0 7 WRP1A_END WRP area A end offset 16 7 WRP1BR WRP1BR Flash WRP area B address register 0x30 0x20 read-only 0xF0000000 WRP1B_STRT WRP area B start offset 0 7 WRP1B_END WRP area B end offset 16 7 WRP2AR WRP2AR FLASH WRP2 area A address register 0x4C 0x20 read-write 0x00000000 WRP2A_STRT WRP2A_STRT 0 7 WRP2A_END WRP2A_END 16 7 WRP2BR WRP2BR FLASH WRP2 area B address register 0x50 0x20 read-write 0x00000000 WRP2B_STRT WRP2B_STRT 0 7 WRP2B_END WRP2B_END 16 7 GPIOA General-purpose I/Os GPIO 0x50000000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xEBFFFFFF MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x0C000000 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x24000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFSEL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFSEL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFSEL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFSEL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFSEL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFSEL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFSEL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFSEL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFSEL15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFSEL14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFSEL13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFSEL12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFSEL11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFSEL10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFSEL9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFSEL8 Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR port bit reset register 0x28 0x20 write-only 0x00000000 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 GPIOB General-purpose I/Os GPIO 0x50000400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFSEL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFSEL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFSEL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFSEL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFSEL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFSEL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFSEL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFSEL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFSEL15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFSEL14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFSEL13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFSEL12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFSEL11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFSEL10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFSEL9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFSEL8 Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR port bit reset register 0x28 0x20 write-only 0x00000000 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 GPIOC 0x50000800 GPIOD 0x50000C00 GPIOE 0x50001000 GPIOF 0x50001400 I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1 I2C1 global interrupt 23 I2C_CR1 I2C_CR1 Control register 1 0x0 0x20 read-write 0x00000000 PE Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles. 0 1 read-write B_0x0 Peripheral disable 0x0 B_0x1 Peripheral enable 0x1 TXIE TX Interrupt enable 1 1 read-write B_0x0 Transmit (TXIS) interrupt disabled 0x0 B_0x1 Transmit (TXIS) interrupt enabled 0x1 RXIE RX Interrupt enable 2 1 read-write B_0x0 Receive (RXNE) interrupt disabled 0x0 B_0x1 Receive (RXNE) interrupt enabled 0x1 ADDRIE Address match Interrupt enable (slave only) 3 1 read-write B_0x0 Address match (ADDR) interrupts disabled 0x0 B_0x1 Address match (ADDR) interrupts enabled 0x1 NACKIE Not acknowledge received Interrupt enable 4 1 read-write B_0x0 Not acknowledge (NACKF) received interrupts disabled 0x0 B_0x1 Not acknowledge (NACKF) received interrupts enabled 0x1 STOPIE Stop detection Interrupt enable 5 1 read-write B_0x0 Stop detection (STOPF) interrupt disabled 0x0 B_0x1 Stop detection (STOPF) interrupt enabled 0x1 TCIE Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR) 6 1 read-write B_0x0 Transfer Complete interrupt disabled 0x0 B_0x1 Transfer Complete interrupt enabled 0x1 ERRIE Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT) 7 1 read-write B_0x0 Error detection interrupts disabled 0x0 B_0x1 Error detection interrupts enabled 0x1 DNF Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0). 8 4 read-write B_0x0 Digital filter disabled 0x0 B_0x1 Digital filter enabled and filtering capability up to 1 tI2CCLK 0x1 B_0xF digital filter enabled and filtering capability up to15 tI2CCLK 0xF ANFOFF Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0). 12 1 read-write B_0x0 Analog noise filter enabled 0x0 B_0x1 Analog noise filter disabled 0x1 TXDMAEN DMA transmission requests enable 14 1 read-write B_0x0 DMA mode disabled for transmission 0x0 B_0x1 DMA mode enabled for transmission 0x1 RXDMAEN DMA reception requests enable 15 1 read-write B_0x0 DMA mode disabled for reception 0x0 B_0x1 DMA mode enabled for reception 0x1 SBC Slave byte control This bit is used to enable hardware byte control in slave mode. 16 1 read-write B_0x0 Slave byte control disabled 0x0 B_0x1 Slave byte control enabled 0x1 NOSTRETCH Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0). 17 1 read-write B_0x0 Clock stretching enabled 0x0 B_0x1 Clock stretching disabled 0x1 WUPEN Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to . Note: WUPEN can be set only when DNF = '0000’ 18 1 read-write B_0x0 Wakeup from Stop mode disable. 0x0 B_0x1 Wakeup from Stop mode enable. 0x1 GCEN General call enable 19 1 read-write B_0x0 General call disabled. Address 0b00000000 is NACKed. 0x0 B_0x1 General call enabled. Address 0b00000000 is ACKed. 0x1 SMBHEN SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to . 20 1 read-write B_0x0 Host Address disabled. Address 0b0001000x is NACKed. 0x0 B_0x1 Host Address enabled. Address 0b0001000x is ACKed. 0x1 SMBDEN SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to . 21 1 read-write B_0x0 Device Default Address disabled. Address 0b1100001x is NACKed. 0x0 B_0x1 Device Default Address enabled. Address 0b1100001x is ACKed. 0x1 ALERTEN SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to . 22 1 read-write B_0x0 The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK). 0x0 B_0x1 The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK). 0x1 PECEN PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to . 23 1 read-write B_0x0 PEC calculation disabled 0x0 B_0x1 PEC calculation enabled 0x1 I2C_CR2 I2C_CR2 Control register 2 0x4 0x20 read-write 0x00000000 SADD Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed. 0 10 read-write RD_WRN Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed. 10 1 read-write B_0x0 Master requests a write transfer. 0x0 B_0x1 Master requests a read transfer. 0x1 ADD10 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed. 11 1 read-write B_0x0 The master operates in 7-bit addressing mode, 0x0 B_0x1 The master operates in 10-bit addressing mode 0x1 HEAD10R 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed. 12 1 read-write B_0x0 The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction. 0x0 B_0x1 The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction. 0x1 START Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1’ to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0’ to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set. 13 1 read-write B_0x0 No Start generation. 0x0 B_0x1 Restart/Start generation: 0x1 STOP Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0’ to this bit has no effect. 14 1 read-write B_0x0 No Stop generation. 0x0 B_0x1 Stop generation after current byte transfer. 0x1 NACK NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0’ to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value. 15 1 read-write B_0x0 an ACK is sent after current received byte. 0x0 B_0x1 a NACK is sent after current received byte. 0x1 NBYTES Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don’t care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed. 16 8 read-write RELOAD NBYTES reload mode This bit is set and cleared by software. 24 1 read-write B_0x0 The transfer is completed after the NBYTES data transfer (STOP or RESTART follows). 0x0 B_0x1 The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low. 0x1 AUTOEND Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set. 25 1 read-write B_0x0 software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. 0x0 B_0x1 Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. 0x1 PECBYTE Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0’ to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to . 26 1 read-write B_0x0 No PEC transfer. 0x0 B_0x1 PEC transmission/reception is requested 0x1 I2C_OAR1 I2C_OAR1 Own address register 1 0x8 0x20 read-write 0x00000000 OA1 Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0. 0 10 read-write OA1MODE Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0. 10 1 read-write B_0x0 Own address 1 is a 7-bit address. 0x0 B_0x1 Own address 1 is a 10-bit address. 0x1 OA1EN Own Address 1 enable 15 1 read-write B_0x0 Own address 1 disabled. The received slave address OA1 is NACKed. 0x0 B_0x1 Own address 1 enabled. The received slave address OA1 is ACKed. 0x1 I2C_OAR2 I2C_OAR2 Own address register 2 0xC 0x20 read-write 0x00000000 OA2 Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0. 1 7 read-write OA2MSK Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. 8 3 read-write B_0x0 No mask 0x0 B_0x1 OA2[1] is masked and don’t care. Only OA2[7:2] are compared. 0x1 B_0x2 OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared. 0x2 B_0x3 OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared. 0x3 B_0x4 OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared. 0x4 B_0x5 OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared. 0x5 B_0x6 OA2[6:1] are masked and don’t care. Only OA2[7] is compared. 0x6 B_0x7 OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged. 0x7 OA2EN Own Address 2 enable 15 1 read-write B_0x0 Own address 2 disabled. The received slave address OA2 is NACKed. 0x0 B_0x1 Own address 2 enabled. The received slave address OA2 is ACKed. 0x1 I2C_TIMINGR I2C_TIMINGR Timing register 0x10 0x20 read-write 0x00000000 SCLL SCL low period (master mode) 0 8 SCLH SCL high period (master mode) 8 8 SDADEL Data hold time 16 4 SCLDEL Data setup time 20 4 PRESC Timing prescaler 28 4 I2C_TIMEOUTR I2C_TIMEOUTR Status register 1 0x14 0x20 read-write 0x00000000 TIMEOUTA Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0. 0 12 read-write TIDLE Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0. 12 1 read-write B_0x0 TIMEOUTA is used to detect SCL low timeout 0x0 B_0x1 TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) 0x1 TIMOUTEN Clock timeout enable 15 1 read-write B_0x0 SCL timeout detection is disabled 0x0 B_0x1 SCL timeout detection is enabled: when SCL is low for more than tTIMEOUT (TIDLE=0) or high for more than tIDLE (TIDLE=1), a timeout error is detected (TIMEOUT=1). 0x1 TIMEOUTB Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0. 16 12 read-write TEXTEN Extended clock timeout enable 31 1 read-write B_0x0 Extended clock timeout detection is disabled 0x0 B_0x1 Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than tLOW:EXT is done by the I2C interface, a timeout error is detected (TIMEOUT=1). 0x1 I2C_ISR I2C_ISR Interrupt and Status register 0x18 0x20 0x00000001 ADDCODE Address match code (Slave mode) 17 7 read-only DIR Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1). 16 1 read-only B_0x0 Write transfer, slave enters receiver mode. 0x0 B_0x1 Read transfer, slave enters transmitter mode. 0x1 BUSY Bus busy 15 1 read-only ALERT SMBus alert 13 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only PECERR PEC Error in reception 11 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only TCR Transfer Complete Reload 7 1 read-only TC Transfer Complete (master mode) 6 1 read-only STOPF Stop detection flag 5 1 read-only NACKF Not acknowledge received flag 4 1 read-only ADDR Address matched (slave mode) 3 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only TXIS Transmit interrupt status (transmitters) 1 1 read-write TXE Transmit data register empty (transmitters) 0 1 read-write I2C_ICR I2C_ICR Interrupt clear register 0x1C 0x20 write-only 0x00000000 ALERTCF Alert flag clear 13 1 TIMOUTCF Timeout detection flag clear 12 1 PECCF PEC Error flag clear 11 1 OVRCF Overrun/Underrun flag clear 10 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 STOPCF Stop detection flag clear 5 1 NACKCF Not Acknowledge flag clear 4 1 ADDRCF Address Matched flag clear 3 1 I2C_PECR I2C_PECR PEC register 0x20 0x20 read-only 0x00000000 PEC Packet error checking register 0 8 I2C_RXDR I2C_RXDR Receive data register 0x24 0x20 read-only 0x00000000 RXDATA 8-bit receive data 0 8 I2C_TXDR I2C_TXDR Transmit data register 0x28 0x20 read-write 0x00000000 TXDATA 8-bit transmit data 0 8 I2C2 0x40005800 I2C2 I2C2 global interrupt 24 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers IWDG_KR IWDG_KR Key register 0x0 0x20 write-only 0x00000000 KEY Key value (write only, read 0x0000) 0 16 IWDG_PR IWDG_PR Prescaler register 0x4 0x20 read-write 0x00000000 PR Prescaler divider These bits are write access protected see . They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the status register (IWDG_SR) is reset. 0 3 read-write B_0x0 divider /4 0x0 B_0x1 divider /8 0x1 B_0x2 divider /16 0x2 B_0x3 divider /32 0x3 B_0x4 divider /64 0x4 B_0x5 divider /128 0x5 B_0x6 divider /256 0x6 B_0x7 divider /256 0x7 IWDG_RLR IWDG_RLR Reload register 0x8 0x20 read-write 0x00000FFF RL Watchdog counter reload value 0 12 IWDG_SR IWDG_SR Status register 0xC 0x20 read-only 0x00000000 PVU Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Prescaler value can be updated only when PVU bit is reset. 0 1 read-only RVU Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Reload value can be updated only when RVU bit is reset. 1 1 read-only WVU Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Window value can be updated only when WVU bit is reset. 2 1 read-only IWDG_WINR IWDG_WINR Window register 0x10 0x20 read-write 0x00000FFF WIN Watchdog counter window value 0 12 PWR Power control PWR 0x40007000 0x0 0x400 registers CR1 CR1 Power control register 1 0x0 0x20 read-write 0x00000208 LPR Low-power run 14 1 VOS Voltage scaling range selection 9 2 DBP Disable backup domain write protection 8 1 FPD_LPSLP Flash memory powered down during Low-power sleep mode 5 1 FPD_LPRUN Flash memory powered down during Low-power run mode 4 1 FPD_STOP Flash memory powered down during Stop mode 3 1 LPMS Low-power mode selection 0 3 CR2 CR2 Power control register 2 0x4 0x20 read-write 0x00000000 USV USV 10 1 CR3 CR3 Power control register 3 0x8 0x20 read-write 0X00008000 EWUP1 Enable Wakeup pin WKUP1 0 1 EWUP2 Enable Wakeup pin WKUP2 1 1 EWUP3 Enable Wakeup pin WKUP3 2 1 EWUP4 Enable Wakeup pin WKUP4 3 1 EWUP5 Enable WKUP5 wakeup pin 4 1 EWUP6 Enable WKUP6 wakeup pin 5 1 APC Apply pull-up and pull-down configuration 10 1 EIWUL Enable internal wakeup line 15 1 CR4 CR4 Power control register 4 0xC 0x20 read-write 0x00000000 WP1 Wakeup pin WKUP1 polarity 0 1 WP2 Wakeup pin WKUP2 polarity 1 1 WP3 Wakeup pin WKUP3 polarity 2 1 WP4 Wakeup pin WKUP4 polarity 3 1 WP5 Wakeup pin WKUP5 polarity 4 1 WP6 WKUP6 wakeup pin polarity 5 1 VBE VBAT battery charging enable 8 1 VBRS VBAT battery charging resistor selection 9 1 SR1 SR1 Power status register 1 0x10 0x20 read-only 0x00000000 WUF1 Wakeup flag 1 0 1 WUF2 Wakeup flag 2 1 1 WUF3 Wakeup flag 3 2 1 WUF4 Wakeup flag 4 3 1 WUF5 Wakeup flag 5 4 1 WUF6 Wakeup flag 6 5 1 SBF Standby flag 8 1 WUFI Wakeup flag internal 15 1 SR2 SR2 Power status register 2 0x14 0x20 read-only 0x00000000 VOSF Voltage scaling flag 10 1 REGLPF Low-power regulator flag 9 1 REGLPS Low-power regulator started 8 1 FLASH_RDY Flash ready flag 7 1 SCR SCR Power status clear register 0x18 0x20 write-only 0x00000000 CSBF Clear standby flag 8 1 CWUF6 Clear wakeup flag 6 5 1 CWUF5 Clear wakeup flag 5 4 1 CWUF4 Clear wakeup flag 4 3 1 CWUF3 Clear wakeup flag 3 2 1 CWUF2 Clear wakeup flag 2 1 1 CWUF1 Clear wakeup flag 1 0 1 PUCRA PUCRA Power Port A pull-up control register 0x20 0x20 read-write 0x00000000 PU15 Port A pull-up bit y (y=0..15) 15 1 PU14 Port A pull-up bit y (y=0..15) 14 1 PU13 Port A pull-up bit y (y=0..15) 13 1 PU12 Port A pull-up bit y (y=0..15) 12 1 PU11 Port A pull-up bit y (y=0..15) 11 1 PU10 Port A pull-up bit y (y=0..15) 10 1 PU9 Port A pull-up bit y (y=0..15) 9 1 PU8 Port A pull-up bit y (y=0..15) 8 1 PU7 Port A pull-up bit y (y=0..15) 7 1 PU6 Port A pull-up bit y (y=0..15) 6 1 PU5 Port A pull-up bit y (y=0..15) 5 1 PU4 Port A pull-up bit y (y=0..15) 4 1 PU3 Port A pull-up bit y (y=0..15) 3 1 PU2 Port A pull-up bit y (y=0..15) 2 1 PU1 Port A pull-up bit y (y=0..15) 1 1 PU0 Port A pull-up bit y (y=0..15) 0 1 PDCRA PDCRA Power Port A pull-down control register 0x24 0x20 read-write 0x00000000 PD15 Port A pull-down bit y (y=0..15) 15 1 PD14 Port A pull-down bit y (y=0..15) 14 1 PD13 Port A pull-down bit y (y=0..15) 13 1 PD12 Port A pull-down bit y (y=0..15) 12 1 PD11 Port A pull-down bit y (y=0..15) 11 1 PD10 Port A pull-down bit y (y=0..15) 10 1 PD9 Port A pull-down bit y (y=0..15) 9 1 PD8 Port A pull-down bit y (y=0..15) 8 1 PD7 Port A pull-down bit y (y=0..15) 7 1 PD6 Port A pull-down bit y (y=0..15) 6 1 PD5 Port A pull-down bit y (y=0..15) 5 1 PD4 Port A pull-down bit y (y=0..15) 4 1 PD3 Port A pull-down bit y (y=0..15) 3 1 PD2 Port A pull-down bit y (y=0..15) 2 1 PD1 Port A pull-down bit y (y=0..15) 1 1 PD0 Port A pull-down bit y (y=0..15) 0 1 PUCRB PUCRB Power Port B pull-up control register 0x28 0x20 read-write 0x00000000 PU15 Port B pull-up bit y (y=0..15) 15 1 PU14 Port B pull-up bit y (y=0..15) 14 1 PU13 Port B pull-up bit y (y=0..15) 13 1 PU12 Port B pull-up bit y (y=0..15) 12 1 PU11 Port B pull-up bit y (y=0..15) 11 1 PU10 Port B pull-up bit y (y=0..15) 10 1 PU9 Port B pull-up bit y (y=0..15) 9 1 PU8 Port B pull-up bit y (y=0..15) 8 1 PU7 Port B pull-up bit y (y=0..15) 7 1 PU6 Port B pull-up bit y (y=0..15) 6 1 PU5 Port B pull-up bit y (y=0..15) 5 1 PU4 Port B pull-up bit y (y=0..15) 4 1 PU3 Port B pull-up bit y (y=0..15) 3 1 PU2 Port B pull-up bit y (y=0..15) 2 1 PU1 Port B pull-up bit y (y=0..15) 1 1 PU0 Port B pull-up bit y (y=0..15) 0 1 PDCRB PDCRB Power Port B pull-down control register 0x2C 0x20 read-write 0x00000000 PD15 Port B pull-down bit y (y=0..15) 15 1 PD14 Port B pull-down bit y (y=0..15) 14 1 PD13 Port B pull-down bit y (y=0..15) 13 1 PD12 Port B pull-down bit y (y=0..15) 12 1 PD11 Port B pull-down bit y (y=0..15) 11 1 PD10 Port B pull-down bit y (y=0..15) 10 1 PD9 Port B pull-down bit y (y=0..15) 9 1 PD8 Port B pull-down bit y (y=0..15) 8 1 PD7 Port B pull-down bit y (y=0..15) 7 1 PD6 Port B pull-down bit y (y=0..15) 6 1 PD5 Port B pull-down bit y (y=0..15) 5 1 PD4 Port B pull-down bit y (y=0..15) 4 1 PD3 Port B pull-down bit y (y=0..15) 3 1 PD2 Port B pull-down bit y (y=0..15) 2 1 PD1 Port B pull-down bit y (y=0..15) 1 1 PD0 Port B pull-down bit y (y=0..15) 0 1 PUCRC PUCRC Power Port C pull-up control register 0x30 0x20 read-write 0x00000000 PU15 Port C pull-up bit y (y=0..15) 15 1 PU14 Port C pull-up bit y (y=0..15) 14 1 PU13 Port C pull-up bit y (y=0..15) 13 1 PU12 Port C pull-up bit y (y=0..15) 12 1 PU11 Port C pull-up bit y (y=0..15) 11 1 PU10 Port C pull-up bit y (y=0..15) 10 1 PU9 Port C pull-up bit y (y=0..15) 9 1 PU8 Port C pull-up bit y (y=0..15) 8 1 PU7 Port C pull-up bit y (y=0..15) 7 1 PU6 Port C pull-up bit y (y=0..15) 6 1 PU5 Port C pull-up bit y (y=0..15) 5 1 PU4 Port C pull-up bit y (y=0..15) 4 1 PU3 Port C pull-up bit y (y=0..15) 3 1 PU2 Port C pull-up bit y (y=0..15) 2 1 PU1 Port C pull-up bit y (y=0..15) 1 1 PU0 Port C pull-up bit y (y=0..15) 0 1 PDCRC PDCRC Power Port C pull-down control register 0x34 0x20 read-write 0x00000000 PD15 Port C pull-down bit y (y=0..15) 15 1 PD14 Port C pull-down bit y (y=0..15) 14 1 PD13 Port C pull-down bit y (y=0..15) 13 1 PD12 Port C pull-down bit y (y=0..15) 12 1 PD11 Port C pull-down bit y (y=0..15) 11 1 PD10 Port C pull-down bit y (y=0..15) 10 1 PD9 Port C pull-down bit y (y=0..15) 9 1 PD8 Port C pull-down bit y (y=0..15) 8 1 PD7 Port C pull-down bit y (y=0..15) 7 1 PD6 Port C pull-down bit y (y=0..15) 6 1 PD5 Port C pull-down bit y (y=0..15) 5 1 PD4 Port C pull-down bit y (y=0..15) 4 1 PD3 Port C pull-down bit y (y=0..15) 3 1 PD2 Port C pull-down bit y (y=0..15) 2 1 PD1 Port C pull-down bit y (y=0..15) 1 1 PD0 Port C pull-down bit y (y=0..15) 0 1 PUCRD PUCRD Power Port D pull-up control register 0x38 0x20 read-write 0x00000000 PU15 Port D pull-up bit y (y=0..15) 15 1 PU14 Port D pull-up bit y (y=0..15) 14 1 PU13 Port D pull-up bit y (y=0..15) 13 1 PU12 Port D pull-up bit y (y=0..15) 12 1 PU11 Port D pull-up bit y (y=0..15) 11 1 PU10 Port D pull-up bit y (y=0..15) 10 1 PU9 Port D pull-up bit y (y=0..15) 9 1 PU8 Port D pull-up bit y (y=0..15) 8 1 PU7 Port D pull-up bit y (y=0..15) 7 1 PU6 Port D pull-up bit y (y=0..15) 6 1 PU5 Port D pull-up bit y (y=0..15) 5 1 PU4 Port D pull-up bit y (y=0..15) 4 1 PU3 Port D pull-up bit y (y=0..15) 3 1 PU2 Port D pull-up bit y (y=0..15) 2 1 PU1 Port D pull-up bit y (y=0..15) 1 1 PU0 Port D pull-up bit y (y=0..15) 0 1 PDCRD PDCRD Power Port D pull-down control register 0x3C 0x20 read-write 0x00000000 PD15 Port D pull-down bit y (y=0..15) 15 1 PD14 Port D pull-down bit y (y=0..15) 14 1 PD13 Port D pull-down bit y (y=0..15) 13 1 PD12 Port D pull-down bit y (y=0..15) 12 1 PD11 Port D pull-down bit y (y=0..15) 11 1 PD10 Port D pull-down bit y (y=0..15) 10 1 PD9 Port D pull-down bit y (y=0..15) 9 1 PD8 Port D pull-down bit y (y=0..15) 8 1 PD7 Port D pull-down bit y (y=0..15) 7 1 PD6 Port D pull-down bit y (y=0..15) 6 1 PD5 Port D pull-down bit y (y=0..15) 5 1 PD4 Port D pull-down bit y (y=0..15) 4 1 PD3 Port D pull-down bit y (y=0..15) 3 1 PD2 Port D pull-down bit y (y=0..15) 2 1 PD1 Port D pull-down bit y (y=0..15) 1 1 PD0 Port D pull-down bit y (y=0..15) 0 1 PUCRE PUCRE Power Port E pull-UP control register 0x40 0x20 read-write 0x00000000 PU15 Port E pull-up bit y (y=0..15) 15 1 PU14 Port E pull-up bit y (y=0..15) 14 1 PU13 Port E pull-up bit y (y=0..15) 13 1 PU12 Port E pull-up bit y (y=0..15) 12 1 PU11 Port E pull-up bit y (y=0..15) 11 1 PU10 Port E pull-up bit y (y=0..15) 10 1 PU9 Port E pull-up bit y (y=0..15) 9 1 PU8 Port E pull-up bit y (y=0..15) 8 1 PU7 Port E pull-up bit y (y=0..15) 7 1 PU6 Port E pull-up bit y (y=0..15) 6 1 PU5 Port E pull-up bit y (y=0..15) 5 1 PU4 Port E pull-up bit y (y=0..15) 4 1 PU3 Port E pull-up bit y (y=0..15) 3 1 PU2 Port E pull-up bit y (y=0..15) 2 1 PU1 Port E pull-up bit y (y=0..15) 1 1 PU0 Port E pull-up bit y (y=0..15) 0 1 PDCRE PDCRE Power Port E pull-down control register 0x44 0x20 read-write 0x00000000 PD15 Port E pull-down bit y (y=0..15) 15 1 PD14 Port E pull-down bit y (y=0..15) 14 1 PD13 Port E pull-down bit y (y=0..15) 13 1 PD12 Port E pull-down bit y (y=0..15) 12 1 PD11 Port E pull-down bit y (y=0..15) 11 1 PD10 Port E pull-down bit y (y=0..15) 10 1 PD9 Port E pull-down bit y (y=0..15) 9 1 PD8 Port E pull-down bit y (y=0..15) 8 1 PD7 Port E pull-down bit y (y=0..15) 7 1 PD6 Port E pull-down bit y (y=0..15) 6 1 PD5 Port E pull-down bit y (y=0..15) 5 1 PD4 Port E pull-down bit y (y=0..15) 4 1 PD3 Port E pull-down bit y (y=0..15) 3 1 PD2 Port E pull-down bit y (y=0..15) 2 1 PD1 Port E pull-down bit y (y=0..15) 1 1 PD0 Port E pull-down bit y (y=0..15) 0 1 PUCRF PUCRF Power Port F pull-up control register 0x48 0x20 read-write 0x00000000 PU13 Port F pull-up bit y (y=0..15) 13 1 PU12 Port F pull-up bit y (y=0..15) 12 1 PU11 Port F pull-up bit y (y=0..15) 11 1 PU10 Port F pull-up bit y (y=0..15) 10 1 PU9 Port F pull-up bit y (y=0..15) 9 1 PU8 Port F pull-up bit y (y=0..15) 8 1 PU7 Port F pull-up bit y (y=0..15) 7 1 PU6 Port F pull-up bit y (y=0..15) 6 1 PU5 Port F pull-up bit y (y=0..15) 5 1 PU4 Port F pull-up bit y (y=0..15) 4 1 PU3 Port F pull-up bit y (y=0..15) 3 1 PU2 Port F pull-up bit y (y=0..15) 2 1 PU1 Port F pull-up bit y (y=0..15) 1 1 PU0 Port F pull-up bit y (y=0..15) 0 1 PDCRF PDCRF Power Port F pull-down control register 0x4C 0x20 read-write 0x00000000 PD13 Port F pull-down bit y (y=0..15) 13 1 PD12 Port F pull-down bit y (y=0..15) 12 1 PD11 Port F pull-down bit y (y=0..15) 11 1 PD10 Port F pull-down bit y (y=0..15) 10 1 PD9 Port F pull-down bit y (y=0..15) 9 1 PD8 Port F pull-down bit y (y=0..15) 8 1 PD7 Port F pull-down bit y (y=0..15) 7 1 PD6 Port F pull-down bit y (y=0..15) 6 1 PD5 Port F pull-down bit y (y=0..15) 5 1 PD4 Port F pull-down bit y (y=0..15) 4 1 PD3 Port F pull-down bit y (y=0..15) 3 1 PD2 Port F pull-down bit y (y=0..15) 2 1 PD1 Port F pull-down bit y (y=0..15) 1 1 PD0 Port F pull-down bit y (y=0..15) 0 1 RCC Reset and clock control RCC 0x40021000 0x0 0x400 registers RCC RCC global interrupt 4 CR CR Clock control register 0x0 0x20 read-write 0x00000063 HSION HSI16 clock enable 8 1 HSIKERON HSI16 always enable for peripheral kernels 9 1 HSIRDY HSI16 clock ready flag 10 1 HSIDIV HSI16 clock division factor 11 3 HSEON HSE clock enable 16 1 HSERDY HSE clock ready flag 17 1 HSEBYP HSE crystal oscillator bypass 18 1 CSSON Clock security system enable 19 1 PLLON PLL enable 24 1 PLLRDY PLL clock ready flag 25 1 ICSCR ICSCR Internal clock sources calibration register 0x4 0x20 0x10000000 HSICAL HSI16 clock calibration 0 8 read-only HSITRIM HSI16 clock trimming 8 7 read-write CFGR CFGR Clock configuration register 0x8 0x20 0x00000000 MCOPRE Microcontroller clock output prescaler 28 4 read-only MCOSEL Microcontroller clock output 24 4 read-write MCO2PRE MCO2PRE 20 4 read-write MCO2SEL MCO2SEL 16 4 read-write PPRE APB prescaler 12 3 read-write HPRE AHB prescaler 8 4 read-write SWS System clock switch status 3 3 read-only SW System clock switch 0 3 read-write PLLSYSCFGR PLLSYSCFGR PLL configuration register 0xC 0x20 read-write 0x00001000 PLLSRC PLL input clock source 0 2 PLLM Division factor M of the PLL input clock divider 4 3 PLLN PLL frequency multiplication factor N 8 8 PLLPEN PLLPCLK clock output enable 16 1 PLLP PLL VCO division factor P for PLLPCLK clock output 17 5 PLLQEN PLLQCLK clock output enable 24 1 PLLQ PLL VCO division factor Q for PLLQCLK clock output 25 3 PLLREN PLLRCLK clock output enable 28 1 PLLR PLL VCO division factor R for PLLRCLK clock output 29 3 CIER CIER Clock interrupt enable register 0x18 0x20 read-write 0x00000000 LSIRDYIE LSI ready interrupt enable 0 1 LSERDYIE LSE ready interrupt enable 1 1 HSIRDYIE HSI ready interrupt enable 3 1 HSERDYIE HSE ready interrupt enable 4 1 PLLSYSRDYIE PLL ready interrupt enable 5 1 CIFR CIFR Clock interrupt flag register 0x1C 0x20 read-only 0x00000000 LSIRDYF LSI ready interrupt flag 0 1 LSERDYF LSE ready interrupt flag 1 1 HSIRDYF HSI ready interrupt flag 3 1 HSERDYF HSE ready interrupt flag 4 1 PLLSYSRDYF PLL ready interrupt flag 5 1 CSSF Clock security system interrupt flag 8 1 LSECSSF LSE Clock security system interrupt flag 9 1 CICR CICR Clock interrupt clear register 0x20 0x20 write-only 0x00000000 LSIRDYC LSI ready interrupt clear 0 1 LSERDYC LSE ready interrupt clear 1 1 HSIRDYC HSI ready interrupt clear 3 1 HSERDYC HSE ready interrupt clear 4 1 PLLSYSRDYC PLL ready interrupt clear 5 1 CSSC Clock security system interrupt clear 8 1 LSECSSC LSE Clock security system interrupt clear 9 1 IOPRSTR IOPRSTR I/O port reset register 0x24 0x20 read-write 0x00000000 GPIOARST GPIOARST 0 1 GPIOBRST GPIOBRST 1 1 GPIOCRST GPIOCRST 2 1 GPIODRST GPIODRST 3 1 GPIOERST GPIOERST 4 1 GPIOFRST GPIOFRST 5 1 AHBRSTR AHBRSTR AHB peripheral reset register 0x28 0x20 read-write 0x00000000 DMA1RST DMA1 reset 0 1 DMA2RST DMA1 reset 1 1 FLASHRST FLITF reset 8 1 CRCRST CRC reset 12 1 APBRSTR1 APBRSTR1 APB peripheral reset register 1 0x2C 0x20 read-write 0x00000000 TIM3RST TIM3 timer reset 1 1 TIM4RST TIM4 timer reset 2 1 TIM6RST TIM6 timer reset 4 1 TIM7RST TIM7 timer reset 5 1 USART5RST USART5RST 8 1 USART6RST USART6RST 9 1 USBRST USBRST 13 1 SPI2RST SPI2 reset 14 1 SPI3RST SPI3 reset 15 1 USART2RST USART2 reset 17 1 USART3RST USART3 reset 18 1 USART4RST USART4 reset 19 1 I2C1RST I2C1 reset 21 1 I2C2RST I2C2 reset 22 1 I2C3RST I2C3RST reset 23 1 DBGRST Debug support reset 27 1 PWRRST Power interface reset 28 1 APBRSTR2 APBRSTR2 APB peripheral reset register 2 0x30 0x20 read-write 0x00000000 SYSCFGRST SYSCFG, COMP and VREFBUF reset 0 1 TIM1RST TIM1 timer reset 11 1 SPI1RST SPI1 reset 12 1 USART1RST USART1 reset 14 1 TIM14RST TIM14 timer reset 15 1 TIM15RST TIM15 timer reset 16 1 TIM16RST TIM16 timer reset 17 1 TIM17RST TIM17 timer reset 18 1 ADCRST ADC reset 20 1 IOPENR IOPENR GPIO clock enable register 0x34 0x20 read-write 0x00000000 GPIOAEN I/O port A clock enable during Sleep mode 0 1 GPIOBEN I/O port B clock enable during Sleep mode 1 1 GPIOCEN I/O port C clock enable during Sleep mode 2 1 GPIODEN I/O port D clock enable during Sleep mode 3 1 GPIOEEN I/O port E clock enable during Sleep mode 4 1 GPIOFEN I/O port F clock enable during Sleep mode 5 1 AHBENR AHBENR AHB peripheral clock enable register 0x38 0x20 read-write 0x00000100 DMA1EN DMA1 clock enable 0 1 DMA2EN DMA2 clock enable 1 1 FLASHEN Flash memory interface clock enable 8 1 CRCEN CRC clock enable 12 1 APBENR1 APBENR1 APB peripheral clock enable register 1 0x3C 0x20 read-write 0x00000000 TIM3EN TIM3 timer clock enable 1 1 TIM4EN TIM4 timer clock enable 2 1 TIM6EN TIM6 timer clock enable 4 1 TIM7EN TIM7 timer clock enable 5 1 USART5EN USART5EN 8 1 USART6EN USART6EN 9 1 RTCAPBEN RTC APB clock enable 10 1 WWDGEN WWDG clock enable 11 1 USBEN USBEN 13 1 SPI2EN SPI2 clock enable 14 1 SPI3EN SPI3 clock enable 15 1 USART2EN USART2 clock enable 17 1 USART3EN USART3 clock enable 18 1 USART4EN USART4 clock enable 19 1 I2C1EN I2C1 clock enable 21 1 I2C2EN I2C2 clock enable 22 1 I2C3EN I2C3 clock enable 23 1 DBGEN Debug support clock enable 27 1 PWREN Power interface clock enable 28 1 APBENR2 APBENR2 APB peripheral clock enable register 2 0x40 0x20 read-write 0x00000000 SYSCFGEN SYSCFG, COMP and VREFBUF clock enable 0 1 TIM1EN TIM1 timer clock enable 11 1 SPI1EN SPI1 clock enable 12 1 USART1EN USART1 clock enable 14 1 TIM14EN TIM14 timer clock enable 15 1 TIM15EN TIM15 timer clock enable 16 1 TIM16EN TIM16 timer clock enable 17 1 TIM17EN TIM16 timer clock enable 18 1 ADCEN ADC clock enable 20 1 IOPSMENR IOPSMENR GPIO in Sleep mode clock enable register 0x44 0x20 read-write 0x0000003F GPIOASMEN I/O port A clock enable during Sleep mode 0 1 GPIOBSMEN I/O port B clock enable during Sleep mode 1 1 GPIOCSMEN I/O port C clock enable during Sleep mode 2 1 GPIODSMEN I/O port D clock enable during Sleep mode 3 1 GPIOESMEN I/O port E clock enable during Sleep mode 4 1 GPIOFSMEN I/O port F clock enable during Sleep mode 5 1 AHBSMENR AHBSMENR AHB peripheral clock enable in Sleep mode register 0x48 0x20 read-write 0x00051303 DMA1SMEN DMA1 clock enable during Sleep mode 0 1 DMA2SMEN DMA2 clock enable during Sleep mode 1 1 FLASHSMEN Flash memory interface clock enable during Sleep mode 8 1 SRAMSMEN SRAM clock enable during Sleep mode 9 1 CRCSMEN CRC clock enable during Sleep mode 12 1 APBSMENR1 APBSMENR1 APB peripheral clock enable in Sleep mode register 1 0x4C 0x20 read-write 0xFFFFFFB7 TIM3SMEN TIM3 timer clock enable during Sleep mode 1 1 TIM4SMEN TIM4 timer clock enable during Sleep mode 2 1 TIM6SMEN TIM6 timer clock enable during Sleep mode 4 1 TIM7SMEN TIM7 timer clock enable during Sleep mode 5 1 USART5SMEN USART5 clock enable 8 1 USART6SMEN USART6 clock enable 9 1 RTCAPBSMEN RTC APB clock enable during Sleep mode 10 1 WWDGSMEN WWDG clock enable during Sleep mode 11 1 USBSMEN USB clock enable during Sleep mode 13 1 SPI2SMEN SPI2 clock enable during Sleep mode 14 1 SPI3SMEN SPI3 clock enable during Sleep mode 15 1 USART2SMEN USART2 clock enable during Sleep mode 17 1 USART3SMEN USART3 clock enable during Sleep mode 18 1 USART4SMEN USART4 clock enable during Sleep mode 19 1 I2C1SMEN I2C1 clock enable during Sleep mode 21 1 I2C2SMEN I2C2 clock enable during Sleep mode 22 1 I2C3SMEN I2C3 clock enable during Sleep mode 23 1 DBGSMEN Debug support clock enable during Sleep mode 27 1 PWRSMEN Power interface clock enable during Sleep mode 28 1 APBSMENR2 APBSMENR2 APB peripheral clock enable in Sleep mode register 2 0x50 0x20 read-write 0x0017D801 SYSCFGSMEN SYSCFG, COMP and VREFBUF clock enable during Sleep mode 0 1 TIM1SMEN TIM1 timer clock enable during Sleep mode 11 1 SPI1SMEN SPI1 clock enable during Sleep mode 12 1 USART1SMEN USART1 clock enable during Sleep mode 14 1 TIM14SMEN TIM14 timer clock enable during Sleep mode 15 1 TIM15SMEN TIM15 timer clock enable during Sleep mode 16 1 TIM16SMEN TIM16 timer clock enable during Sleep mode 17 1 TIM17SMEN TIM16 timer clock enable during Sleep mode 18 1 ADCSMEN ADC clock enable during Sleep mode 20 1 CCIPR CCIPR Peripherals independent clock configuration register 0x54 0x20 read-write 0x00000000 USART1SEL USART1 clock source selection 0 2 USART2SEL USART2 clock source selection 2 2 USART3SEL USART3 clock source selection 4 2 I2C1SEL I2C1 clock source selection 12 2 I2S2SEL I2S1 clock source selection 14 2 TIM1SEL TIM1 clock source selection 22 1 TIM15SEL TIM15 clock source selection 24 1 ADCSEL ADCs clock source selection 30 2 CCIPR2 CCIPR2 Peripherals independent clock configuration register 2 0x58 0x20 read-write 0x00000000 I2S1SEL 2S1SEL 0 2 I2S2SEL I2S2SEL 2 2 USBSEL USBSEL 12 2 BDCR BDCR RTC domain control register 0x5C 0x20 read-write 0x00000000 LSEON LSE oscillator enable 0 1 LSERDY LSE oscillator ready 1 1 read-only LSEBYP LSE oscillator bypass 2 1 LSEDRV LSE oscillator drive capability 3 2 LSECSSON CSS on LSE enable 5 1 LSECSSD CSS on LSE failure Detection 6 1 read-only RTCSEL RTC clock source selection 8 2 RTCEN RTC clock enable 15 1 BDRST RTC domain software reset 16 1 LSCOEN Low-speed clock output (LSCO) enable 24 1 LSCOSEL Low-speed clock output selection 25 1 CSR CSR Control/status register 0x60 0x20 read-write 0x00000000 LSION LSI oscillator enable 0 1 LSIRDY LSI oscillator ready 1 1 read-only RMVF Remove reset flags 23 1 OBLRSTF Option byte loader reset flag 25 1 read-only PINRSTF Pin reset flag 26 1 read-only PWRRSTF BOR or POR/PDR flag 27 1 read-only SFTRSTF Software reset flag 28 1 read-only IWDGRSTF Independent window watchdog reset flag 29 1 read-only WWDGRSTF Window watchdog reset flag 30 1 read-only LPWRRSTF Low-power reset flag 31 1 read-only RTC Real-time clock RTC 0x40002800 0x0 0x400 registers RTC_STAMP RTC and TAMP interrupts 2 RTC_TR RTC_TR RTC time register 0x0 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format 0 4 read-write ST Second tens in BCD format 4 3 read-write MNU Minute units in BCD format 8 4 read-write MNT Minute tens in BCD format 12 3 read-write HU Hour units in BCD format 16 4 read-write HT Hour tens in BCD format 20 2 read-write PM AM/PM notation 22 1 read-write B_0x0 AM or 24-hour format 0x0 B_0x1 PM 0x1 RTC_DR RTC_DR RTC date register 0x4 0x20 0x00002101 0xFFFFFFFF DU Date units in BCD format 0 4 read-write DT Date tens in BCD format 4 2 read-write MU Month units in BCD format 8 4 read-write MT Month tens in BCD format 12 1 read-write WDU Week day units ... 13 3 read-write B_0x0 forbidden 0x0 B_0x1 Monday 0x1 B_0x7 Sunday 0x7 YU Year units in BCD format 16 4 read-write YT Year tens in BCD format 20 4 read-write RTC_SSR RTC_SSR RTC sub second register 0x8 0x20 0x00000000 0xFFFFFFFF SS Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR. 0 16 read-only RTC_ICSR RTC_ICSR RTC initialization control and status register 0xc 0x20 0x00000007 0xFFFFFFFF ALRAWF Alarm A write flag This bit is set by hardware when alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0 1 read-only B_0x0 Alarm A update not allowed 0x0 B_0x1 Alarm A update allowed 0x1 ALRBWF Alarm B write flag This bit is set by hardware when alarm B values can be changed, after the ALRBE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 1 1 read-only B_0x0 Alarm B update not allowed 0x0 B_0x1 Alarm B update allowed 0x1 WUTWF Wakeup timer write flag This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 2 1 read-only B_0x0 Wakeup timer configuration update not allowed except in initialization mode 0x0 B_0x1 Wakeup timer configuration update allowed 0x1 SHPF Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. 3 1 read-only B_0x0 No shift operation is pending 0x0 B_0x1 A shift operation is pending 0x1 INITS Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state). 4 1 read-only B_0x0 Calendar has not been initialized 0x0 B_0x1 Calendar has been initialized 0x1 RSF Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 5 1 read-write B_0x0 Calendar shadow registers not yet synchronized 0x0 B_0x1 Calendar shadow registers synchronized 0x1 INITF Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. 6 1 read-only B_0x0 Calendar registers update is not allowed 0x0 B_0x1 Calendar registers update is allowed 0x1 INIT Initialization mode 7 1 read-write B_0x0 Free running mode 0x0 B_0x1 Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 0x1 RECALPF Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to . 16 1 read-only RTC_PRER RTC_PRER RTC prescaler register 0x10 0x20 0x007F00FF 0xFFFFFFFF PREDIV_S Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1) 0 15 read-write PREDIV_A Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) 16 7 read-write RTC_WUTR RTC_WUTR RTC wakeup timer register 0x14 0x20 0x0000FFFF 0xFFFFFFFF WUT Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0]+1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register. When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs between WUT and (WUT + 1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden. 0 16 read-write RTC_CR RTC_CR control register 0x18 0x20 0x00000000 0xFFFFFFFF WUCKSEL ck_wut wakeup clock selection 10x: ck_spre (usually 1Hz) clock is selected 11x: ck_spre (usually 1Hz) clock is selected and 216is added to the WUT counter value 0 3 read-write B_0x0 RTC/16 clock is selected 0x0 B_0x1 RTC/8 clock is selected 0x1 B_0x2 RTC/4 clock is selected 0x2 B_0x3 RTC/2 clock is selected 0x3 TSEDGE Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting. 3 1 read-write B_0x0 RTC_TS input rising edge generates a timestamp event 0x0 B_0x1 RTC_TS input falling edge generates a timestamp event 0x1 REFCKON RTC_REFIN reference clock detection enable (50 or 60Hz) Note: PREDIV_S must be 0x00FF. 4 1 read-write B_0x0 RTC_REFIN detection disabled 0x0 B_0x1 RTC_REFIN detection enabled 0x1 BYPSHAD Bypass the shadow registers Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1. 5 1 read-write B_0x0 Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. 0x0 B_0x1 Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. 0x1 FMT Hour format 6 1 read-write B_0x0 24 hour/day format 0x0 B_0x1 AM/PM hour format 0x1 ALRAE Alarm A enable 8 1 read-write B_0x0 Alarm A disabled 0x0 B_0x1 Alarm A enabled 0x1 ALRBE Alarm B enable 9 1 read-write B_0x0 Alarm B disabled 0x0 B_0x1 Alarm B enabled 0x1 WUTE Wakeup timer enable Note: When the wakeup timer is disabled, wait for WUTWF=1 before enabling it again. 10 1 read-write B_0x0 Wakeup timer disabled 0x0 B_0x1 Wakeup timer enabled 0x1 TSE timestamp enable 11 1 read-write B_0x0 timestamp disable 0x0 B_0x1 timestamp enable 0x1 ALRAIE Alarm A interrupt enable 12 1 read-write B_0x0 Alarm A interrupt disabled 0x0 B_0x1 Alarm A interrupt enabled 0x1 ALRBIE Alarm B interrupt enable 13 1 read-write B_0x0 Alarm B interrupt disable 0x0 B_0x1 Alarm B interrupt enable 0x1 WUTIE Wakeup timer interrupt enable 14 1 read-write B_0x0 Wakeup timer interrupt disabled 0x0 B_0x1 Wakeup timer interrupt enabled 0x1 TSIE Timestamp interrupt enable 15 1 read-write B_0x0 Timestamp interrupt disable 0x0 B_0x1 Timestamp interrupt enable 0x1 ADD1H Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 16 1 write-only B_0x0 No effect 0x0 B_0x1 Adds 1 hour to the current time. This can be used for summer time change 0x1 SUB1H Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0. 17 1 write-only B_0x0 No effect 0x0 B_0x1 Subtracts 1 hour to the current time. This can be used for winter time change. 0x1 BKP Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. 18 1 read-write COSEL Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to . 19 1 read-write B_0x0 Calibration output is 512Hz 0x0 B_0x1 Calibration output is 1Hz 0x1 POL Output polarity This bit is used to configure the polarity of TAMPALRM output. 20 1 read-write B_0x0 The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1). 0x0 B_0x1 The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1). 0x1 OSEL Output selection These bits are used to select the flag to be routed to TAMPALRM output. 21 2 read-write B_0x0 Output disabled 0x0 B_0x1 Alarm A output enabled 0x1 B_0x2 Alarm B output enabled 0x2 B_0x3 Wakeup output enabled 0x3 COE Calibration output enable This bit enables the CALIB output 23 1 read-write B_0x0 Calibration output disabled 0x0 B_0x1 Calibration output enabled 0x1 ITSE timestamp on internal event enable 24 1 read-write B_0x0 internal event timestamp disabled 0x0 B_0x1 internal event timestamp enabled 0x1 TAMPTS Activate timestamp on tamper detection event TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set after the tamper flags, therefore if TAMPTS and TSIE are set, it is recommended to disable the tamper interrupts in order to avoid servicing 2 interrupts. 25 1 read-write B_0x0 Tamper detection event does not cause a RTC timestamp to be saved 0x0 B_0x1 Save RTC timestamp on tamper detection event 0x1 TAMPOE Tamper detection output enable on TAMPALRM 26 1 read-write B_0x0 The tamper flag is not routed on TAMPALRM 0x0 B_0x1 The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL. 0x1 TAMPALRM_PU TAMPALRM pull-up enable 29 1 read-write B_0x0 No pull-up is applied on TAMPALRM output 0x0 B_0x1 A pull-up is applied on TAMPALRM output 0x1 TAMPALRM_TYPE TAMPALRM output type 30 1 read-write B_0x0 TAMPALRM is push-pull output 0x0 B_0x1 TAMPALRM is open-drain output 0x1 OUT2EN RTC_OUT2 output enable Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL ≠ 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL ≠ 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2 If (OSEL≠ 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1. 31 1 read-write RTC_WPR RTC_WPR write protection register 0x24 0x20 0x00000000 0xFFFFFFFF KEY Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to for a description of how to unlock RTC register write protection. 0 8 write-only RTC_CALR RTC_CALR RTC calibration register 0x28 0x20 0x00000000 0xFFFFFFFF CALM Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768Hz). This decreases the frequency of the calendar with a resolution of 0.9537ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See . 0 9 read-write CALW16 Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to calibration. 13 1 read-write CALW8 Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to digital calibration. 14 1 read-write CALP Increase frequency of RTC by 488.5ppm This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 × CALP) - CALM. Refer to . 15 1 read-write B_0x0 No RTCCLK pulses are added. 0x0 B_0x1 One RTCCLK pulse is effectively inserted every 211 pulses (frequency increased by 488.5ppm). 0x1 RTC_SHIFTR RTC_SHIFTR RTC shift control register 0x2c 0x20 0x00000000 0xFFFFFFFF SUBFS Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time. 0 15 write-only ADD1S Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. 31 1 write-only B_0x0 No effect 0x0 B_0x1 Add one second to the clock/calendar 0x1 RTC_TSTR RTC_TSTR RTC timestamp time register 0x30 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format. 0 4 read-only ST Second tens in BCD format. 4 3 read-only MNU Minute units in BCD format. 8 4 read-only MNT Minute tens in BCD format. 12 3 read-only HU Hour units in BCD format. 16 4 read-only HT Hour tens in BCD format. 20 2 read-only PM AM/PM notation 22 1 read-only B_0x0 AM or 24-hour format 0x0 B_0x1 PM 0x1 RTC_TSDR RTC_TSDR RTC timestamp date register 0x34 0x20 0x00000000 0xFFFFFFFF DU Date units in BCD format 0 4 read-only DT Date tens in BCD format 4 2 read-only MU Month units in BCD format 8 4 read-only MT Month tens in BCD format 12 1 read-only WDU Week day units 13 3 read-only RTC_TSSSR RTC_TSSSR RTC timestamp sub second register 0x38 0x20 0x00000000 0xFFFFFFFF SS Sub second value SS[15:0] is the value of the synchronous prescaler counter when the timestamp event occurred. 0 16 read-only RTC_ALRMAR RTC_ALRMAR RTC alarm A register 0x40 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format. 0 4 read-write ST Second tens in BCD format. 4 3 read-write MSK1 Alarm A seconds mask 7 1 read-write B_0x0 Alarm A set if the seconds match 0x0 B_0x1 Seconds don't care in alarm A comparison 0x1 MNU Minute units in BCD format 8 4 read-write MNT Minute tens in BCD format 12 3 read-write MSK2 Alarm A minutes mask 15 1 read-write B_0x0 Alarm A set if the minutes match 0x0 B_0x1 Minutes don't care in alarm A comparison 0x1 HU Hour units in BCD format 16 4 read-write HT Hour tens in BCD format 20 2 read-write PM AM/PM notation 22 1 read-write B_0x0 AM or 24-hour format 0x0 B_0x1 PM 0x1 MSK3 Alarm A hours mask 23 1 read-write B_0x0 Alarm A set if the hours match 0x0 B_0x1 Hours don't care in alarm A comparison 0x1 DU Date units or day in BCD format 24 4 read-write DT Date tens in BCD format 28 2 read-write WDSEL Week day selection 30 1 read-write B_0x0 DU[3:0] represents the date units 0x0 B_0x1 DU[3:0] represents the week day. DT[1:0] is don't care. 0x1 MSK4 Alarm A date mask 31 1 read-write B_0x0 Alarm A set if the date/day match 0x0 B_0x1 Date/day don't care in alarm A comparison 0x1 RTC_ALRMASSR RTC_ALRMASSR RTC alarm A sub second register 0x44 0x20 0x00000000 0xFFFFFFFF SS Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. 0 15 read-write MASKSS Mask the most-significant bits starting at this bit 2: SS[14:2] are don't care in alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are don't care in alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are don't care in alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are don't care in alarm A comparison. SS[12:0] are compared. 14: SS[14] is don't care in alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. 24 4 read-write B_0x0 No comparison on sub seconds for alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). 0x0 B_0x1 SS[14:1] are don't care in alarm A comparison. Only SS[0] is compared. 0x1 RTC_ALRMBR RTC_ALRMBR RTC alarm B register 0x48 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format 0 4 read-write ST Second tens in BCD format 4 3 read-write MSK1 Alarm B seconds mask 7 1 read-write B_0x0 Alarm B set if the seconds match 0x0 B_0x1 Seconds don't care in alarm B comparison 0x1 MNU Minute units in BCD format 8 4 read-write MNT Minute tens in BCD format 12 3 read-write MSK2 Alarm B minutes mask 15 1 read-write B_0x0 Alarm B set if the minutes match 0x0 B_0x1 Minutes don't care in alarm B comparison 0x1 HU Hour units in BCD format 16 4 read-write HT Hour tens in BCD format 20 2 read-write PM AM/PM notation 22 1 read-write B_0x0 AM or 24-hour format 0x0 B_0x1 PM 0x1 MSK3 Alarm B hours mask 23 1 read-write B_0x0 Alarm B set if the hours match 0x0 B_0x1 Hours don't care in alarm B comparison 0x1 DU Date units or day in BCD format 24 4 read-write DT Date tens in BCD format 28 2 read-write WDSEL Week day selection 30 1 read-write B_0x0 DU[3:0] represents the date units 0x0 B_0x1 DU[3:0] represents the week day. DT[1:0] is don't care. 0x1 MSK4 Alarm B date mask 31 1 read-write B_0x0 Alarm B set if the date and day match 0x0 B_0x1 Date and day don't care in alarm B comparison 0x1 RTC_ALRMBSSR RTC_ALRMBSSR RTC alarm B sub second register 0x4c 0x20 0x00000000 0xFFFFFFFF SS Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared. 0 15 read-write MASKSS Mask the most-significant bits starting at this bit ... The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. 24 4 read-write B_0x0 No comparison on sub seconds for alarm B. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). 0x0 B_0x1 SS[14:1] are don't care in alarm B comparison. Only SS[0] is compared. 0x1 B_0x2 SS[14:2] are don't care in alarm B comparison. Only SS[1:0] are compared. 0x2 B_0x3 SS[14:3] are don't care in alarm B comparison. Only SS[2:0] are compared. 0x3 B_0xC SS[14:12] are don't care in alarm B comparison. SS[11:0] are compared. 0xC B_0xD SS[14:13] are don't care in alarm B comparison. SS[12:0] are compared. 0xD B_0xE SS[14] is don't care in alarm B comparison. SS[13:0] are compared. 0xE B_0xF All 15 SS bits are compared and must match to activate alarm. 0xF RTC_SR RTC_SR RTC status register 0x50 0x20 0x00000000 0xFFFFFFFF ALRAF Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm A register (RTC_ALRMAR). 0 1 read-only ALRBF Alarm B flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm B register (RTC_ALRMBR). 1 1 read-only WUTF Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. 2 1 read-only TSF Timestamp flag This flag is set by hardware when a timestamp event occurs. If ITSF flag is set, TSF must be cleared together with ITSF. 3 1 read-only TSOVF Timestamp overflow flag This flag is set by hardware when a timestamp event occurs while TSF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 read-only ITSF Internal timestamp flag This flag is set by hardware when a timestamp on the internal event occurs. 5 1 read-only RTC_MISR RTC_MISR RTC masked interrupt status register 0x54 0x20 0x00000000 0xFFFFFFFF ALRAMF Alarm A masked flag This flag is set by hardware when the alarm A interrupt occurs. 0 1 read-only ALRBMF Alarm B masked flag This flag is set by hardware when the alarm B interrupt occurs. 1 1 read-only WUTMF Wakeup timer masked flag This flag is set by hardware when the wakeup timer interrupt occurs. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. 2 1 read-only TSMF Timestamp masked flag This flag is set by hardware when a timestamp interrupt occurs. If ITSF flag is set, TSF must be cleared together with ITSF. 3 1 read-only TSOVMF Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 read-only ITSMF Internal timestamp masked flag This flag is set by hardware when a timestamp on the internal event occurs and timestampinterrupt is raised. 5 1 read-only RTC_SCR RTC_SCR RTC status clear register 0x5c 0x20 0x00000000 0xFFFFFFFF CALRAF Clear alarm A flag Writing 1 in this bit clears the ALRAF bit in the RTC_SR register. 0 1 write-only CALRBF Clear alarm B flag Writing 1 in this bit clears the ALRBF bit in the RTC_SR register. 1 1 write-only CWUTF Clear wakeup timer flag Writing 1 in this bit clears the WUTF bit in the RTC_SR register. 2 1 write-only CTSF Clear timestamp flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. If ITSF flag is set, TSF must be cleared together with ITSF by setting CRSF and CITSF. 3 1 write-only CTSOVF Clear timestamp overflow flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 write-only CITSF Clear internal timestamp flag Writing 1 in this bit clears the ITSF bit in the RTC_SR register. 5 1 write-only SPI1 Serial peripheral interface/Inter-IC sound SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 25 SPI_CR1 SPI_CR1 0x0 16 0x00000000 0x0000FFFF CPHA Clock phase Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode. 0 1 read-write B_0x0 The first clock transition is the first data capture edge 0x0 B_0x1 The second clock transition is the first data capture edge 0x1 CPOL Clock polarity Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode. 1 1 read-write B_0x0 CK to 0 when idle 0x0 B_0x1 CK to 1 when idle 0x1 MSTR Master selection Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode. 2 1 read-write B_0x0 Slave configuration 0x0 B_0x1 Master configuration 0x1 BR Baud rate control Note: These bits should not be changed when communication is ongoing. These bits are not used in I2S mode. 3 3 read-write B_0x0 fPCLK/2 0x0 B_0x1 fPCLK/4 0x1 B_0x2 fPCLK/8 0x2 B_0x3 fPCLK/16 0x3 B_0x4 fPCLK/32 0x4 B_0x5 fPCLK/64 0x5 B_0x6 fPCLK/128 0x6 B_0x7 fPCLK/256 0x7 SPE SPI enable Note: When disabling the SPI, follow the procedure described in SPI on page1020. This bit is not used in I2S mode. 6 1 read-write B_0x0 Peripheral disabled 0x0 B_0x1 Peripheral enabled 0x1 LSBFIRST Frame format Note: 1. This bit should not be changed when communication is ongoing. 2. This bit is not used in I2S mode and SPI TI mode. 7 1 read-write B_0x0 data is transmitted / received with the MSB first 0x0 B_0x1 data is transmitted / received with the LSB first 0x1 SSI Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. Note: This bit is not used in I2S mode and SPI TI mode. 8 1 read-write SSM Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. Note: This bit is not used in I2S mode and SPI TI mode. 9 1 read-write B_0x0 Software slave management disabled 0x0 B_0x1 Software slave management enabled 0x1 RXONLY Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I2S mode. 10 1 read-write B_0x0 Full-duplex (Transmit and receive) 0x0 B_0x1 Output disabled (Receive-only mode) 0x1 CRCL CRC length This bit is set and cleared by software to select the CRC length. Note: This bit should be written only when SPI is disabled (SPE = '0’) for correct operation. This bit is not used in I2S mode. 11 1 read-write B_0x0 8-bit CRC length 0x0 B_0x1 16-bit CRC length 0x1 CRCNEXT Transmit CRC next Note: This bit has to be written as soon as the last data is written in the SPIx_DR register. This bit is not used in I2S mode. 12 1 read-write B_0x0 Next transmit value is from Tx buffer. 0x0 B_0x1 Next transmit value is from Tx CRC register. 0x1 CRCEN Hardware CRC calculation enable Note: This bit should be written only when SPI is disabled (SPE = '0’) for correct operation. This bit is not used in I2S mode. 13 1 read-write B_0x0 CRC calculation disabled 0x0 B_0x1 CRC calculation enabled 0x1 BIDIOE Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. This bit is not used in I2S mode. 14 1 read-write B_0x0 Output disabled (receive-only mode) 0x0 B_0x1 Output enabled (transmit-only mode) 0x1 BIDIMODE Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I2S mode. 15 1 read-write B_0x0 2-line unidirectional data mode selected 0x0 B_0x1 1-line bidirectional data mode selected 0x1 SPI_CR2 SPI_CR2 0x4 16 0x00000700 0x0000FFFF RXDMAEN Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set. 0 1 read-write B_0x0 Rx buffer DMA disabled 0x0 B_0x1 Rx buffer DMA enabled 0x1 TXDMAEN Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set. 1 1 read-write B_0x0 Tx buffer DMA disabled 0x0 B_0x1 Tx buffer DMA enabled 0x1 SSOE SS output enable Note: This bit is not used in I2S mode and SPI TI mode. 2 1 read-write B_0x0 SS output is disabled in master mode and the SPI interface can work in multimaster configuration 0x0 B_0x1 SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. 0x1 NSSP NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = ’1’, or FRF = ’1’. Note: 1. This bit must be written only when the SPI is disabled (SPE=0). 2. This bit is not used in I2S mode and SPI TI mode. 3 1 read-write B_0x0 No NSS pulse 0x0 B_0x1 NSS pulse generated 0x1 FRF Frame format 1 SPI TI mode Note: This bit must be written only when the SPI is disabled (SPE=0). This bit is not used in I2S mode. 4 1 read-write B_0x0 SPI Motorola mode 0x0 ERRIE Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode). 5 1 read-write B_0x0 Error interrupt is masked 0x0 B_0x1 Error interrupt is enabled 0x1 RXNEIE RX buffer not empty interrupt enable 6 1 read-write B_0x0 RXNE interrupt masked 0x0 B_0x1 RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. 0x1 TXEIE Tx buffer empty interrupt enable 7 1 read-write B_0x0 TXE interrupt masked 0x0 B_0x1 TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. 0x1 DS Data size These bits configure the data length for SPI transfers. If software attempts to write one of the “Not used” values, they are forced to the value “0111” (8-bit) Note: These bits are not used in I2S mode. 8 4 read-write B_0x0 Not used 0x0 B_0x1 Not used 0x1 B_0x2 Not used 0x2 B_0x3 4-bit 0x3 B_0x4 5-bit 0x4 B_0x5 6-bit 0x5 B_0x6 7-bit 0x6 B_0x7 8-bit 0x7 B_0x8 9-bit 0x8 B_0x9 10-bit 0x9 B_0xA 11-bit 0xA B_0xB 12-bit 0xB B_0xC 13-bit 0xC B_0xD 14-bit 0xD B_0xE 15-bit 0xE B_0xF 16-bit 0xF FRXTH FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event Note: This bit is not used in I2S mode. 12 1 read-write B_0x0 RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) 0x0 B_0x1 RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) 0x1 LDMA_RX Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). Note: Refer to if the CRCEN bit is set. This bit is not used in I²S mode. 13 1 read-write B_0x0 Number of data to transfer is even 0x0 B_0x1 Number of data to transfer is odd 0x1 LDMA_TX Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). Note: Refer to if the CRCEN bit is set. This bit is not used in I²S mode. 14 1 read-write B_0x0 Number of data to transfer is even 0x0 B_0x1 Number of data to transfer is odd 0x1 SPI_SR SPI_SR 0x8 16 0x00000002 0x0000FFFF RXNE Receive buffer not empty 0 1 read-only B_0x0 Rx buffer empty 0x0 B_0x1 Rx buffer not empty 0x1 TXE Transmit buffer empty 1 1 read-only B_0x0 Tx buffer not empty 0x0 B_0x1 Tx buffer empty 0x1 CHSIDE Channel side Note: This bit is not used in SPI mode. It has no significance in PCM mode. 2 1 read-only B_0x0 Channel Left has to be transmitted or has been received 0x0 B_0x1 Channel Right has to be transmitted or has been received 0x1 UDR Underrun flag This flag is set by hardware and reset by a software sequence. Refer to page1056 for the software sequence. Note: This bit is not used in SPI mode. 3 1 read-only B_0x0 No underrun occurred 0x0 B_0x1 Underrun occurred 0x1 CRCERR CRC error flag Note: This flag is set by hardware and cleared by software writing 0. This bit is not used in I2S mode. 4 1 read-write B_0x0 CRC value received matches the SPIx_RXCRCR value 0x0 B_0x1 CRC value received does not match the SPIx_RXCRCR value 0x1 MODF Mode fault This flag is set by hardware and reset by a software sequence. Refer to (MODF) on page1030 for the software sequence. Note: This bit is not used in I2S mode. 5 1 read-only B_0x0 No mode fault occurred 0x0 B_0x1 Mode fault occurred 0x1 OVR Overrun flag This flag is set by hardware and reset by a software sequence. Refer to page1056 for the software sequence. 6 1 read-only B_0x0 No overrun occurred 0x0 B_0x1 Overrun occurred 0x1 BSY Busy flag This flag is set and cleared by hardware. Note: The BSY flag must be used with caution: refer to and . 7 1 read-only B_0x0 SPI (or I2S) not busy 0x0 B_0x1 SPI (or I2S) is busy in communication or Tx buffer is not empty 0x1 FRE Frame format error This flag is used for SPI in TI slave mode and I2S slave mode. Refer to error flags and . This flag is set by hardware and reset when SPIx_SR is read by software. 8 1 read-only B_0x0 No frame format error 0x0 B_0x1 A frame format error occurred 0x1 FRLVL FIFO reception level These bits are set and cleared by hardware. Note: These bits are not used in I²S mode and in SPI receive-only mode while CRC calculation is enabled. 9 2 read-only B_0x0 FIFO empty 0x0 B_0x1 1/4 FIFO 0x1 B_0x2 1/2 FIFO 0x2 B_0x3 FIFO full 0x3 FTLVL FIFO transmission level These bits are set and cleared by hardware. Note: This bit is not used in I2S mode. 11 2 read-only B_0x0 FIFO empty 0x0 B_0x1 1/4 FIFO 0x1 B_0x2 1/2 FIFO 0x2 B_0x3 FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) 0x3 SPI_DR SPI_DR 0xc 16 0x00000000 0x0000FFFF DR Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See ). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. 0 16 read-write SPI_CRCPR SPI_CRCPR 0x10 16 0x00000007 0x0000FFFF CRCPOLY CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required. 0 16 read-write SPI_RXCRCR SPI_RXCRCR 0x14 16 0x00000000 0x0000FFFF RXCRC Rx CRC register When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY Flag is set could return an incorrect value. These bits are not used in I2S mode. 0 16 read-only SPI_TXCRCR SPI_TXCRCR 0x18 16 0x00000000 0x0000FFFF TXCRC Tx CRC register When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode. 0 16 read-only SPI_I2SCFGR SPI_I2SCFGR 0x1c 16 0x00000000 0x0000FFFF CHLEN Channel length (number of bits per audio channel) The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode. 0 1 read-write B_0x0 16-bit wide 0x0 B_0x1 32-bit wide 0x1 DATLEN Data length to be transferred Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode. 1 2 read-write B_0x0 16-bit data length 0x0 B_0x1 24-bit data length 0x1 B_0x2 32-bit data length 0x2 B_0x3 Not allowed 0x3 CKPOL Inactive state clock polarity Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode. The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals. 3 1 read-write B_0x0 I2S clock inactive state is low level 0x0 B_0x1 I2S clock inactive state is high level 0x1 I2SSTD I2S standard selection For more details on I2S standards, refer to Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode. 4 2 read-write B_0x0 I2S Philips standard 0x0 B_0x1 MSB justified standard (left justified) 0x1 B_0x2 LSB justified standard (right justified) 0x2 B_0x3 PCM standard 0x3 PCMSYNC PCM frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode. 7 1 read-write B_0x0 Short frame synchronization 0x0 B_0x1 Long frame synchronization 0x1 I2SCFG I2S configuration mode Note: These bits should be configured when the I2S is disabled. They are not used in SPI mode. 8 2 read-write B_0x0 Slave - transmit 0x0 B_0x1 Slave - receive 0x1 B_0x2 Master - transmit 0x2 B_0x3 Master - receive 0x3 I2SE I2S enable Note: This bit is not used in SPI mode. 10 1 read-write B_0x0 I2S peripheral is disabled 0x0 B_0x1 I2S peripheral is enabled 0x1 I2SMOD I2S mode selection Note: This bit should be configured when the SPI is disabled. 11 1 read-write B_0x0 SPI mode is selected 0x0 B_0x1 I2S mode is selected 0x1 ASTRTEN Asynchronous start enable. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. The appropriate level is a low level on WS signal when I2S Philips Standard is used, or a high level for other standards. Please refer to for additional information. 12 1 read-write B_0x0 The Asynchronous start is disabled. 0x0 B_0x1 The Asynchronous start is enabled. 0x1 SPI_I2SPR SPI_I2SPR 0x20 16 0x00000002 0x0000FFFF I2SDIV I2S linear prescaler I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. Refer to . Note: These bits should be configured when the I2S is disabled. They are used only when the I2S is in master mode. They are not used in SPI mode. 0 8 read-write ODD Odd factor for the prescaler Refer to . Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. It is not used in SPI mode. 8 1 read-write B_0x0 Real divider value is = I2SDIV *2 0x0 B_0x1 Real divider value is = (I2SDIV * 2)+1 0x1 MCKOE Master clock output enable Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. It is not used in SPI mode. 9 1 read-write B_0x0 Master clock output is disabled 0x0 B_0x1 Master clock output is enabled 0x1 SPI2 0x40003800 SPI2_SPI3 SPI2/SPI3 global interrupt 26 SYSCFG System configuration controller SYSCFG 0x40010000 0x0 0x100 registers CFGR1 CFGR1 SYSCFG configuration register 1 0x0 0x20 read-write 0x00000000 I2C3_FMP I2C3_FMP 24 1 I2C_PA10_FMP Fast Mode Plus (FM+) driving capability activation bits 23 1 I2C_PA9_FMP Fast Mode Plus (FM+) driving capability activation bits 22 1 I2C2_FMP FM+ driving capability activation for I2C2 21 1 I2C1_FMP FM+ driving capability activation for I2C1 20 1 I2C_PB9_FMP I2C_PB9_FMP 19 4 I2C_PB8_FMP I2C_PB8_FMP 18 4 I2C_PB7_FMP I2C_PB7_FMP 17 4 I2C_PBx_FMP Fast Mode Plus (FM+) driving capability activation bits 16 4 UCPD2_STROBE Strobe signal bit for UCPD2 10 1 UCPD1_STROBE Strobe signal bit for UCPD1 9 1 BOOSTEN I/O analog switch voltage booster enable 8 1 IR_MOD IR Modulation Envelope signal selection. 6 2 IR_POL IR output polarity selection 5 1 PA12_RMP PA11 and PA12 remapping bit. 4 1 PA11_RMP PA11_RMP 3 1 MEM_MODE Memory mapping selection bits 0 2 CFGR2 CFGR2 SYSCFG configuration register 1 0x18 0x20 read-write 0x00000000 LOCKUP_LOCK Cortex-M0+ LOCKUP bit enable bit 0 1 SRAM_PARITY_LOCK SRAM parity lock bit 1 1 ECC_LOCK ECC error lock bit 3 1 SRAM_PEF SRAM parity error flag 8 1 ITLINE0 ITLINE0 interrupt line 0 status register 0x80 0x20 read-only 0x00000000 WWDG Window watchdog interrupt pending flag 0 1 ITLINE2 ITLINE2 interrupt line 2 status register 0x88 0x20 read-only 0x00000000 TAMP TAMP 0 1 RTC RTC 1 1 ITLINE3 ITLINE3 interrupt line 3 status register 0x8C 0x20 read-only 0x00000000 FLASH_ITF FLASH_ITF 0 1 FLASH_ECC FLASH_ECC 1 1 ITLINE4 ITLINE4 interrupt line 4 status register 0x90 0x20 read-only 0x00000000 RCC RCC 0 1 ITLINE5 ITLINE5 interrupt line 5 status register 0x94 0x20 read-only 0x00000000 EXTI0 EXTI0 0 1 EXTI1 EXTI1 1 1 ITLINE6 ITLINE6 interrupt line 6 status register 0x98 0x20 read-only 0x00000000 EXTI2 EXTI2 0 1 EXTI3 EXTI3 1 1 ITLINE7 ITLINE7 interrupt line 7 status register 0x9C 0x20 read-only 0x00000000 EXTI4 EXTI4 0 1 EXTI5 EXTI5 1 1 EXTI6 EXTI6 2 1 EXTI7 EXTI7 3 1 EXTI8 EXTI8 4 1 EXTI9 EXTI9 5 1 EXTI10 EXTI10 6 1 EXTI11 EXTI11 7 1 EXTI12 EXTI12 8 1 EXTI13 EXTI13 9 1 EXTI14 EXTI14 10 1 EXTI15 EXTI15 11 1 ITLINE8 ITLINE8 interrupt line 8 status register 0xA0 0x20 read-only 0x00000000 USB USB 2 1 ITLINE9 ITLINE9 interrupt line 9 status register 0xA4 0x20 read-only 0x00000000 DMA1_CH1 DMA1_CH1 0 1 ITLINE10 ITLINE10 interrupt line 10 status register 0xA8 0x20 read-only 0x00000000 DMA1_CH2 DMA1_CH1 0 1 DMA1_CH3 DMA1_CH3 1 1 ITLINE11 ITLINE11 interrupt line 11 status register 0xAC 0x20 read-only 0x00000000 DMAMUX DMAMUX 0 1 DMA1_CH4 DMA1_CH4 1 1 DMA1_CH5 DMA1_CH5 2 1 DMA1_CH6 DMA1_CH6 3 1 DMA1_CH7 DMA1_CH7 4 1 DMA2_CH1 DMA2_CH1 5 1 DMA2_CH2 DMA2_CH2 6 1 DMA2_CH3 DMA2_CH3 7 1 DMA2_CH4 DMA2_CH4 8 1 DMA2_CH5 DMA2_CH5 9 1 ITLINE12 ITLINE12 interrupt line 12 status register 0xB0 0x20 read-only 0x00000000 ADC ADC 0 1 ITLINE13 ITLINE13 interrupt line 13 status register 0xB4 0x20 read-only 0x00000000 TIM1_CCU TIM1_CCU 0 1 TIM1_TRG TIM1_TRG 1 1 TIM1_UPD TIM1_UPD 2 1 TIM1_BRK TIM1_BRK 3 1 ITLINE14 ITLINE14 interrupt line 14 status register 0xB8 0x20 read-only 0x00000000 TIM1_CC TIM1_CC 0 1 ITLINE16 ITLINE16 interrupt line 16 status register 0xC0 0x20 read-only 0x00000000 TIM3 TIM3 0 1 TIM4 TIM4 1 1 ITLINE17 ITLINE17 interrupt line 17 status register 0xC4 0x20 read-only 0x00000000 TIM6 TIM6 0 1 ITLINE18 ITLINE18 interrupt line 18 status register 0xC8 0x20 read-only 0x00000000 TIM7 TIM7 0 1 ITLINE19 ITLINE19 interrupt line 19 status register 0xCC 0x20 read-only 0x00000000 TIM14 TIM14 0 1 ITLINE20 ITLINE20 interrupt line 20 status register 0xD0 0x20 read-only 0x00000000 TIM15 TIM15 0 1 ITLINE21 ITLINE21 interrupt line 21 status register 0xD4 0x20 read-only 0x00000000 TIM16 TIM16 0 1 ITLINE22 ITLINE22 interrupt line 22 status register 0xD8 0x20 read-only 0x00000000 TIM17 TIM17 0 1 ITLINE23 ITLINE23 interrupt line 23 status register 0xDC 0x20 read-only 0x00000000 I2C1 I2C1 0 1 ITLINE24 ITLINE24 interrupt line 24 status register 0xE0 0x20 read-only 0x00000000 I2C2 I2C2 0 1 I2C3 I2C3 1 1 ITLINE25 ITLINE25 interrupt line 25 status register 0xE4 0x20 read-only 0x00000000 SPI1 SPI1 0 1 ITLINE26 ITLINE26 interrupt line 26 status register 0xE8 0x20 read-only 0x00000000 SPI2 SPI2 0 1 SPI3 SPI3 14 1 ITLINE27 ITLINE27 interrupt line 27 status register 0xEC 0x20 read-only 0x00000000 USART1 USART1 0 1 ITLINE28 ITLINE28 interrupt line 28 status register 0xF0 0x20 read-only 0x00000000 USART2 USART2 0 1 ITLINE29 ITLINE29 interrupt line 29 status register 0xF4 0x20 read-only 0x00000000 USART3 USART3 0 1 USART4 USART4 1 1 USART5 USART5 3 1 USART6 USART6 4 1 TAMP Tamper and backup registers TAMP 0x4000B000 0x0 0x400 registers TAMP_CR1 TAMP_CR1 TAMP control register 1 0x0 0x20 0xFFFF0000 0xFFFFFFFF TAMP1E Tamper detection on TAMP_IN1 enable 0 1 read-write B_0x0 Tamper detection on TAMP_IN1 is disabled. 0x0 B_0x1 Tamper detection on TAMP_IN1 is enabled. 0x1 TAMP2E Tamper detection on TAMP_IN2 enable 1 1 read-write B_0x0 Tamper detection on TAMP_IN2 is disabled. 0x0 B_0x1 Tamper detection on TAMP_IN2 is enabled. 0x1 TAMP3E Tamper detection on TAMP_IN3 enable 2 1 read-write B_0x0 Tamper detection on TAMP_IN3 is disabled. 0x0 B_0x1 Tamper detection on TAMP_IN3 is enabled. 0x1 ITAMP3E Internal tamper 3 enable: LSE monitoring 18 1 read-write B_0x0 Internal tamper 3 disabled. 0x0 B_0x1 Internal tamper 3 enabled: a tamper is generated when the LSE frequency is below or above thresholds. 0x1 ITAMP4E Internal tamper 4 enable: HSE monitoring 19 1 read-write B_0x0 Internal tamper 4 disabled. 0x0 B_0x1 Internal tamper 4 enabled. a tamper is generated when the HSE frequency is below or above thresholds. 0x1 ITAMP5E Internal tamper 5 enable: RTC calendar overflow 20 1 read-write B_0x0 Internal tamper 5 disabled. 0x0 B_0x1 Internal tamper 5 enabled: a tamper is generated when the RTC calendar reaches its maximum value, on the 31st of December 99, at 23:59:59. The calendar is then frozen and cannot overflow. 0x1 ITAMP6E Internal tamper 6 enable: ST manufacturer readout 21 1 read-write B_0x0 Internal tamper 6 disabled. 0x0 B_0x1 Internal tamper 6 enabled: a tamper is generated in case of ST manufacturer readout. 0x1 TAMP_CR2 TAMP_CR2 TAMP control register 2 0x4 0x20 0x00000000 0xFFFFFFFF TAMP1NOER Tamper 1 no erase 0 1 read-write B_0x0 Tamper 1 event erases the backup registers. 0x0 B_0x1 Tamper 1 event does not erase the backup registers. 0x1 TAMP2NOER Tamper 2 no erase 1 1 read-write B_0x0 Tamper 2 event erases the backup registers. 0x0 B_0x1 Tamper 2 event does not erase the backup registers. 0x1 TAMP3NOER Tamper 3 no erase 2 1 read-write B_0x0 Tamper 3 event erases the backup registers. 0x0 B_0x1 Tamper 3 event does not erase the backup registers. 0x1 TAMP1MSK Tamper 1 mask The tamper 1 interrupt must not be enabled when TAMP1MSK is set. 16 1 read-write B_0x0 Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection. 0x0 B_0x1 Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers are not erased. 0x1 TAMP2MSK Tamper 2 mask The tamper 2 interrupt must not be enabled when TAMP2MSK is set. 17 1 read-write B_0x0 Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to allow next tamper event detection. 0x0 B_0x1 Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. 0x1 TAMP3MSK Tamper 3 mask The tamper 3 interrupt must not be enabled when TAMP3MSK is set. 18 1 read-write B_0x0 Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to allow next tamper event detection. 0x0 B_0x1 Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased. 0x1 TAMP1TRG Active level for tamper 1 input (active mode disabled) If TAMPFLT = 00 Tamper 1 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 1 input falling edge and low level triggers a tamper detection event. 24 1 read-write B_0x0 If TAMPFLT ≠ 00 Tamper 1 input staying low triggers a tamper detection event. 0x0 B_0x1 If TAMPFLT ≠ 00 Tamper 1 input staying high triggers a tamper detection event. 0x1 TAMP2TRG Active level for tamper 2 input (active mode disabled) If TAMPFLT = 00 Tamper 2 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 2 input falling edge and low level triggers a tamper detection event. 25 1 read-write B_0x0 If TAMPFLT ≠ 00 Tamper 2 input staying low triggers a tamper detection event. 0x0 B_0x1 If TAMPFLT ≠ 00 Tamper 2 input staying high triggers a tamper detection event. 0x1 TAMP3TRG Active level for tamper 3 input (active mode disabled) If TAMPFLT = 00 Tamper 3 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 3 input falling edge and low level triggers a tamper detection event. 26 1 read-write B_0x0 If TAMPFLT ≠ 00 Tamper 3 input staying low triggers a tamper detection event. 0x0 B_0x1 If TAMPFLT ≠ 00 Tamper 3 input staying high triggers a tamper detection event. 0x1 TAMP_FLTCR TAMP_FLTCR TAMP filter control register 0xc 0x20 0x00000000 0xFFFFFFFF TAMPFREQ Tamper sampling frequency Determines the frequency at which each of the TAMP_INx inputs are sampled. 0 3 read-write B_0x0 RTCCLK / 32768 (1Hz when RTCCLK = 32768Hz) 0x0 B_0x1 RTCCLK / 16384 (2Hz when RTCCLK = 32768Hz) 0x1 B_0x2 RTCCLK / 8192 (4Hz when RTCCLK = 32768Hz) 0x2 B_0x3 RTCCLK / 4096 (8Hz when RTCCLK = 32768Hz) 0x3 B_0x4 RTCCLK / 2048 (16Hz when RTCCLK = 32768Hz) 0x4 B_0x5 RTCCLK / 1024 (32Hz when RTCCLK = 32768Hz) 0x5 B_0x6 RTCCLK / 512 (64Hz when RTCCLK = 32768Hz) 0x6 B_0x7 RTCCLK / 256 (128Hz when RTCCLK = 32768Hz) 0x7 TAMPFLT TAMP_INx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the TAMP_INx inputs. 3 2 read-write B_0x0 Tamper event is activated on edge of TAMP_INx input transitions to the active level (no internal pull-up on TAMP_INx input). 0x0 B_0x1 Tamper event is activated after 2 consecutive samples at the active level. 0x1 B_0x2 Tamper event is activated after 4 consecutive samples at the active level. 0x2 B_0x3 Tamper event is activated after 8 consecutive samples at the active level. 0x3 TAMPPRCH TAMP_INx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the TAMP_INx inputs. 5 2 read-write B_0x0 1 RTCCLK cycle 0x0 B_0x1 2 RTCCLK cycles 0x1 B_0x2 4 RTCCLK cycles 0x2 B_0x3 8 RTCCLK cycles 0x3 TAMPPUDIS TAMP_INx pull-up disable This bit determines if each of the TAMPx pins are precharged before each sample. 7 1 read-write B_0x0 Precharge TAMP_INx pins before sampling (enable internal pull-up) 0x0 B_0x1 Disable precharge of TAMP_INx pins. 0x1 TAMP_IER TAMP_IER TAMP interrupt enable register 0x2c 0x20 0x00000000 0xFFFFFFFF TAMP1IE Tamper 1 interrupt enable 0 1 read-write B_0x0 Tamper 1 interrupt disabled. 0x0 B_0x1 Tamper 1 interrupt enabled. 0x1 TAMP2IE Tamper 2 interrupt enable 1 1 read-write B_0x0 Tamper 2 interrupt disabled. 0x0 B_0x1 Tamper 2 interrupt enabled. 0x1 TAMP3IE Tamper 3 interrupt enable 2 1 read-write B_0x0 Tamper 3 interrupt disabled. 0x0 B_0x1 Tamper 3 interrupt enabled.. 0x1 ITAMP3IE Internal tamper 3 interrupt enable: LSE monitoring 18 1 read-write B_0x0 Internal tamper 3 interrupt disabled. 0x0 B_0x1 Internal tamper 3 interrupt enabled. 0x1 ITAMP4IE Internal tamper 4 interrupt enable: HSE monitoring 19 1 read-write B_0x0 Internal tamper 4 interrupt disabled. 0x0 B_0x1 Internal tamper 4 interrupt enabled. 0x1 ITAMP5IE Internal tamper 5 interrupt enable: RTC calendar overflow 20 1 read-write B_0x0 Internal tamper 5 interrupt disabled. 0x0 B_0x1 Internal tamper 5 interrupt enabled. 0x1 ITAMP6IE Internal tamper 6 interrupt enable: ST manufacturer readout 21 1 read-write B_0x0 Internal tamper 6 interrupt disabled. 0x0 B_0x1 Internal tamper 6 interrupt enabled. 0x1 TAMP_SR TAMP_SR TAMP status register 0x30 0x20 0x00000000 0xFFFFFFFF TAMP1F TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP1 input. 0 1 read-only TAMP2F TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP2 input. 1 1 read-only TAMP3F TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP3 input. 2 1 read-only ITAMP3F LSE monitoring tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 3. 18 1 read-only ITAMP4F HSE monitoring tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 4. 19 1 read-only ITAMP5F RTC calendar overflow tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 5. 20 1 read-only ITAMP6F ST manufacturer readout tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 6. 21 1 read-only TAMP_MISR TAMP_MISR TAMP masked interrupt status register 0x34 0x20 0x00000000 0xFFFFFFFF TAMP1MF TAMP1 interrupt masked flag This flag is set by hardware when the tamper 1 interrupt is raised. 0 1 read-only TAMP2MF TAMP2 interrupt masked flag This flag is set by hardware when the tamper 2 interrupt is raised. 1 1 read-only TAMP3MF TAMP3 interrupt masked flag This flag is set by hardware when the tamper 3 interrupt is raised. 2 1 read-only ITAMP3MF LSE monitoring tamper interrupt masked flag This flag is set by hardware when the internal tamper 3 interrupt is raised. 18 1 read-only ITAMP4MF HSE monitoring tamper interrupt masked flag This flag is set by hardware when the internal tamper 4 interrupt is raised. 19 1 read-only ITAMP5MF RTC calendar overflow tamper interrupt masked flag This flag is set by hardware when the internal tamper 5 interrupt is raised. 20 1 read-only ITAMP6MF ST manufacturer readout tamper interrupt masked flag This flag is set by hardware when the internal tamper 6 interrupt is raised. 21 1 read-only TAMP_SCR TAMP_SCR TAMP status clear register 0x3c 0x20 0x00000000 0xFFFFFFFF CTAMP1F Clear TAMP1 detection flag Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register. 0 1 write-only CTAMP2F Clear TAMP2 detection flag Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register. 1 1 write-only CTAMP3F Clear TAMP3 detection flag Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register. 2 1 write-only CITAMP3F Clear ITAMP3 detection flag Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register. 18 1 write-only CITAMP4F Clear ITAMP4 detection flag Writing 1 in this bit clears the ITAMP4F bit in the TAMP_SR register. 19 1 write-only CITAMP5F Clear ITAMP5 detection flag Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register. 20 1 write-only CITAMP6F Clear ITAMP6 detection flag Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register. 21 1 write-only TAMP_BKP0R TAMP_BKP0R TAMP backup 0 register 0x100 0x20 0x00000000 0xFFFFFFFF BKP The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. 0 32 read-write TAMP_BKP1R TAMP_BKP1R TAMP backup 1 register 0x104 0x20 0x00000000 0xFFFFFFFF BKP The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. 0 32 read-write TAMP_BKP2R TAMP_BKP2R TAMP backup 2 register 0x108 0x20 0x00000000 0xFFFFFFFF BKP The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. 0 32 read-write TAMP_BKP3R TAMP_BKP3R TAMP backup 3 register 0x10c 0x20 0x00000000 0xFFFFFFFF BKP The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. 0 32 read-write TAMP_BKP4R TAMP_BKP4R TAMP backup 4 register 0x110 0x20 0x00000000 0xFFFFFFFF BKP The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. 0 32 read-write TIM1 Advanced-timers TIM 0x40012C00 0x0 0x400 registers TIM1_BRK_UP_TRG_COM TIM1 break, update, trigger and commutation interrupts 13 TIM1_CC TIM1 Capture Compare interrupt 14 TIM1_CR1 TIM1_CR1 control register 1 0x0 0x20 read-write 0x00000000 CEN Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write B_0x0 Counter disabled 0x0 B_0x1 Counter enabled 0x1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write B_0x0 UEV enabled. The Update (UEV) event is generated by one of the following events: 0x0 B_0x1 UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. 0x1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write B_0x0 Any of the following events generate an update interrupt or DMA request if enabled. These events can be: 0x0 B_0x1 Only counter overflow/underflow generates an update interrupt or DMA request if enabled. 0x1 OPM One pulse mode 3 1 read-write B_0x0 Counter is not stopped at update event 0x0 B_0x1 Counter stops counting at the next update event (clearing the bit CEN) 0x1 DIR Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. 4 1 read-write B_0x0 Counter used as upcounter 0x0 B_0x1 Counter used as downcounter 0x1 CMS Center-aligned mode selection Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed 5 2 read-write B_0x0 Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 0x0 B_0x1 Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 0x1 B_0x2 Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 0x2 B_0x3 Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. 0x3 ARPE Auto-reload preload enable 7 1 read-write B_0x0 TIMx_ARR register is not buffered 0x0 B_0x1 TIMx_ARR register is buffered 0x1 CKD Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx): Note: tDTS = 1/fDTS, tCK_INT = 1/fCK_INT. 8 2 read-write B_0x0 tDTS=tCK_INT 0x0 B_0x1 tDTS=2*tCK_INT 0x1 B_0x2 tDTS=4*tCK_INT 0x2 B_0x3 Reserved, do not program this value 0x3 UIFREMAP UIF status bit remapping 11 1 read-write B_0x0 No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 0x0 B_0x1 Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. 0x1 TIM1_CR2 TIM1_CR2 control register 2 0x4 0x20 read-write 0x00000000 CCPC Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 1 read-write B_0x0 CCxE, CCxNE and OCxM bits are not preloaded 0x0 B_0x1 CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). 0x1 CCUS Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 2 1 read-write B_0x0 When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0x0 B_0x1 When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 0x1 CCDS Capture/compare DMA selection 3 1 read-write B_0x0 CCx DMA request sent when CCx event occurs 0x0 B_0x1 CCx DMA requests sent when update event occurs 0x1 MMS Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 4 3 read-write B_0x0 Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 0x0 B_0x1 Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 0x1 B_0x2 Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 0x2 B_0x3 Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). 0x3 B_0x4 Compare - OC1REFC signal is used as trigger output (TRGO) 0x4 B_0x5 Compare - OC2REFC signal is used as trigger output (TRGO) 0x5 B_0x6 Compare - OC3REFC signal is used as trigger output (TRGO) 0x6 B_0x7 Compare - OC4REFC signal is used as trigger output (TRGO) 0x7 TI1S TI1 selection 7 1 read-write B_0x0 The TIMx_CH1 pin is connected to TI1 input 0x0 B_0x1 The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) 0x1 OIS1 Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 8 1 read-write B_0x0 OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 0x0 B_0x1 OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 0x1 OIS1N Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write B_0x0 OC1N=0 after a dead-time when MOE=0 0x0 B_0x1 OC1N=1 after a dead-time when MOE=0 0x1 OIS2 Output Idle state 2 (OC2 output) Refer to OIS1 bit 10 1 read-write OIS2N Output Idle state 2 (OC2N output) Refer to OIS1N bit 11 1 read-write OIS3 Output Idle state 3 (OC3 output) Refer to OIS1 bit 12 1 read-write OIS3N Output Idle state 3 (OC3N output) Refer to OIS1N bit 13 1 read-write OIS4 Output Idle state 4 (OC4 output) Refer to OIS1 bit 14 1 read-write OIS5 Output Idle state 5 (OC5 output) Refer to OIS1 bit 16 1 read-write OIS6 Output Idle state 6 (OC6 output) Refer to OIS1 bit 18 1 read-write MMS2 Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 20 4 read-write B_0x0 Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset. 0x0 B_0x1 Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register). 0x1 B_0x2 Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer. 0x2 B_0x3 Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2). 0x3 B_0x4 Compare - OC1REFC signal is used as trigger output (TRGO2) 0x4 B_0x5 Compare - OC2REFC signal is used as trigger output (TRGO2) 0x5 B_0x6 Compare - OC3REFC signal is used as trigger output (TRGO2) 0x6 B_0x7 Compare - OC4REFC signal is used as trigger output (TRGO2) 0x7 B_0x8 Compare - OC5REFC signal is used as trigger output (TRGO2) 0x8 B_0x9 Compare - OC6REFC signal is used as trigger output (TRGO2) 0x9 B_0xA Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2 0xA B_0xB Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2 0xB B_0xC Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2 0xC B_0xD Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2 0xD B_0xE Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2 0xE B_0xF Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2 0xF TIM1_SMCR TIM1_SMCR slave mode control register 0x8 0x20 read-write 0x00000000 SMS1 Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write B_0x0 Slave mode disabled - if CEN = '1’ then the prescaler is clocked directly by the internal clock. 0x0 B_0x1 Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 0x1 B_0x2 Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 0x2 B_0x3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 0x3 B_0x4 Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0x4 B_0x5 Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0x5 B_0x6 Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0x6 B_0x7 External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 0x7 B_0x8 Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter.Codes above 1000: Reserved. 0x8 OCCS OCREF clear selection This bit is used to select the OCREF clear source. 3 1 read-write B_0x0 OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIM1_OR1.OCREF_CLR 0x0 B_0x1 OCREF_CLR_INT is connected to ETRF 0x1 TS1 Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write B_0x0 Internal Trigger 0 (ITR0) 0x0 B_0x1 Internal Trigger 1 (ITR1) 0x1 B_0x2 Internal Trigger 2 (ITR2) 0x2 B_0x3 Internal Trigger 3 (ITR3) 0x3 B_0x4 TI1 Edge Detector (TI1F_ED) 0x4 B_0x5 Filtered Timer Input 1 (TI1FP1) 0x5 B_0x6 Filtered Timer Input 2 (TI2FP2) 0x6 B_0x7 External Trigger input (ETRF) 0x7 MSM Master/slave mode 7 1 read-write B_0x0 No action 0x0 B_0x1 The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 0x1 ETF External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 8 4 read-write B_0x0 No filter, sampling is done at fDTS 0x0 B_0x1 fSAMPLING=fCK_INT, N=2 0x1 B_0x2 fSAMPLING=fCK_INT, N=4 0x2 B_0x3 fSAMPLING=fCK_INT, N=8 0x3 B_0x4 fSAMPLING=fDTS/2, N=6 0x4 B_0x5 fSAMPLING=fDTS/2, N=8 0x5 B_0x6 fSAMPLING=fDTS/4, N=6 0x6 B_0x7 fSAMPLING=fDTS/4, N=8 0x7 B_0x8 fSAMPLING=fDTS/8, N=6 0x8 B_0x9 fSAMPLING=fDTS/8, N=8 0x9 B_0xA fSAMPLING=fDTS/16, N=5 0xA B_0xB fSAMPLING=fDTS/16, N=6 0xB B_0xC fSAMPLING=fDTS/16, N=8 0xC B_0xD fSAMPLING=fDTS/32, N=5 0xD B_0xE fSAMPLING=fDTS/32, N=6 0xE B_0xF fSAMPLING=fDTS/32, N=8 0xF ETPS External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 12 2 read-write B_0x0 Prescaler OFF 0x0 B_0x1 ETRP frequency divided by 2 0x1 B_0x2 ETRP frequency divided by 4 0x2 B_0x3 ETRP frequency divided by 8 0x3 ECE External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. 14 1 read-write B_0x0 External clock mode 2 disabled 0x0 B_0x1 External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 0x1 ETP External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 15 1 read-write B_0x0 ETR is non-inverted, active at high level or rising edge. 0x0 B_0x1 ETR is inverted, active at low level or falling edge. 0x1 SMS2 Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 16 1 read-write B_0x0 Slave mode disabled - if CEN = '1’ then the prescaler is clocked directly by the internal clock. 0x0 B_0x1 Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 0x1 B_0x2 Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 0x2 B_0x3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 0x3 B_0x4 Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0x4 B_0x5 Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0x5 B_0x6 Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0x6 B_0x7 External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 0x7 B_0x8 Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter.Codes above 1000: Reserved. 0x8 TS2 Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 20 2 read-write B_0x0 Internal Trigger 0 (ITR0) 0x0 B_0x1 Internal Trigger 1 (ITR1) 0x1 B_0x2 Internal Trigger 2 (ITR2) 0x2 B_0x3 Internal Trigger 3 (ITR3) 0x3 B_0x4 TI1 Edge Detector (TI1F_ED) 0x4 B_0x5 Filtered Timer Input 1 (TI1FP1) 0x5 B_0x6 Filtered Timer Input 2 (TI2FP2) 0x6 B_0x7 External Trigger input (ETRF) 0x7 TIM1_DIER TIM1_DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 UIE Update interrupt enable 0 1 read-write B_0x0 Update interrupt disabled 0x0 B_0x1 Update interrupt enabled 0x1 CC1IE Capture/Compare 1 interrupt enable 1 1 read-write B_0x0 CC1 interrupt disabled 0x0 B_0x1 CC1 interrupt enabled 0x1 CC2IE Capture/Compare 2 interrupt enable 2 1 read-write B_0x0 CC2 interrupt disabled 0x0 B_0x1 CC2 interrupt enabled 0x1 CC3IE Capture/Compare 3 interrupt enable 3 1 read-write B_0x0 CC3 interrupt disabled 0x0 B_0x1 CC3 interrupt enabled 0x1 CC4IE Capture/Compare 4 interrupt enable 4 1 read-write B_0x0 CC4 interrupt disabled 0x0 B_0x1 CC4 interrupt enabled 0x1 COMIE COM interrupt enable 5 1 read-write B_0x0 COM interrupt disabled 0x0 B_0x1 COM interrupt enabled 0x1 TIE Trigger interrupt enable 6 1 read-write B_0x0 Trigger interrupt disabled 0x0 B_0x1 Trigger interrupt enabled 0x1 BIE Break interrupt enable 7 1 read-write B_0x0 Break interrupt disabled 0x0 B_0x1 Break interrupt enabled 0x1 UDE Update DMA request enable 8 1 read-write B_0x0 Update DMA request disabled 0x0 B_0x1 Update DMA request enabled 0x1 CC1DE Capture/Compare 1 DMA request enable 9 1 read-write B_0x0 CC1 DMA request disabled 0x0 B_0x1 CC1 DMA request enabled 0x1 CC2DE Capture/Compare 2 DMA request enable 10 1 read-write B_0x0 CC2 DMA request disabled 0x0 B_0x1 CC2 DMA request enabled 0x1 CC3DE Capture/Compare 3 DMA request enable 11 1 read-write B_0x0 CC3 DMA request disabled 0x0 B_0x1 CC3 DMA request enabled 0x1 CC4DE Capture/Compare 4 DMA request enable 12 1 read-write B_0x0 CC4 DMA request disabled 0x0 B_0x1 CC4 DMA request enabled 0x1 COMDE COM DMA request enable 13 1 read-write B_0x0 COM DMA request disabled 0x0 B_0x1 COM DMA request enabled 0x1 TDE Trigger DMA request enable 14 1 read-write B_0x0 Trigger DMA request disabled 0x0 B_0x1 Trigger DMA request enabled 0x1 TIM1_SR TIM1_SR status register 0x10 0x20 read-write 0x0000 UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write B_0x0 No update occurred. 0x0 B_0x1 Update interrupt pending. This bit is set by hardware when the registers are updated: 0x1 CC1IF Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). 1 1 read-write B_0x0 No compare match / No input capture occurred 0x0 B_0x1 A compare match or an input capture occurred. 0x1 CC2IF Capture/Compare 2 interrupt flag Refer to CC1IF description 2 1 read-write CC3IF Capture/Compare 3 interrupt flag Refer to CC1IF description 3 1 read-write CC4IF Capture/Compare 4 interrupt flag Refer to CC1IF description 4 1 read-write COMIF COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. 5 1 read-write B_0x0 No COM event occurred. 0x0 B_0x1 COM interrupt pending. 0x1 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write B_0x0 No trigger event occurred. 0x0 B_0x1 Trigger interrupt pending. 0x1 BIF Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 7 1 read-write B_0x0 No break event occurred. 0x0 B_0x1 An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. 0x1 B2IF Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. 8 1 read-write B_0x0 No break event occurred. 0x0 B_0x1 An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register. 0x1 CC1OF Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’. 9 1 read-write B_0x0 No overcapture has been detected. 0x0 B_0x1 The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set 0x1 CC2OF Capture/Compare 2 overcapture flag Refer to CC1OF description 10 1 read-write CC3OF Capture/Compare 3 overcapture flag Refer to CC1OF description 11 1 read-write CC4OF Capture/Compare 4 overcapture flag Refer to CC1OF description 12 1 read-write SBIF System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation. 13 1 read-write B_0x0 No break event occurred. 0x0 B_0x1 An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. 0x1 CC5IF Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output) 16 1 read-write CC6IF Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output) 17 1 read-write TIM1_EGR TIM1_EGR event generation register 0x14 0x20 write-only 0x0000 UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only B_0x0 No action 0x0 B_0x1 Reinitialize the counter and generates an update of the registers. The prescaler internal counter is also cleared (the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). 0x1 CC1G Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. 1 1 write-only B_0x0 No action 0x0 B_0x1 A capture/compare event is generated on channel 1: 0x1 CC2G Capture/Compare 2 generation Refer to CC1G description 2 1 write-only CC3G Capture/Compare 3 generation Refer to CC1G description 3 1 write-only CC4G Capture/Compare 4 generation Refer to CC1G description 4 1 write-only COMG Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output. 5 1 write-only B_0x0 No action 0x0 B_0x1 When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated. 0x1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only B_0x0 No action 0x0 B_0x1 The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 0x1 BG Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 7 1 write-only B_0x0 No action 0x0 B_0x1 A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. 0x1 B2G Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 8 1 write-only B_0x0 No action 0x0 B_0x1 A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled. 0x1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER). 0 2 read-write B_0x0 CC1 channel is configured as output 0x0 B_0x1 CC1 channel is configured as input, IC1 is mapped on TI1 0x1 B_0x2 CC1 channel is configured as input, IC1 is mapped on TI2 0x2 B_0x3 CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 OC1FE Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. 2 1 read-write B_0x0 CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 0x0 B_0x1 An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. 0x1 OC1PE Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. 3 1 read-write B_0x0 Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 0x0 B_0x1 Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. 0x1 OC1M1 Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. Note: The OC1M[3] bit is not contiguous, located in bit 16. 4 3 read-write B_0x0 Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). 0x0 B_0x1 Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x1 B_0x2 Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x2 B_0x3 Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0x3 B_0x4 Force inactive level - OC1REF is forced low. 0x4 B_0x5 Force active level - OC1REF is forced high. 0x5 B_0x6 PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF='0’) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’). 0x6 B_0x7 PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. 0x7 B_0x8 Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 0x8 B_0x9 Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 0x9 B_0xC Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 0xC B_0xD Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 0xD B_0xE Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 0xE B_0xF Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 0xF OC1CE Output Compare 1 clear enable 7 1 read-write B_0x0 OC1Ref is not affected by the ocref_clr_int signal 0x0 B_0x1 OC1Ref is cleared as soon as a High level is detected on ocref_clr_int signal (OCREF_CLR input or ETRF input) 0x1 CC2S Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER). 8 2 read-write B_0x0 CC2 channel is configured as output 0x0 B_0x1 CC2 channel is configured as input, IC2 is mapped on TI2 0x1 B_0x2 CC2 channel is configured as input, IC2 is mapped on TI1 0x2 B_0x3 CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) 0x3 OC2FE Output Compare 2 fast enable Refer to OC1FE description. 10 1 read-write OC2PE Output Compare 2 preload enable Refer to OC1PE description. 11 1 read-write OC2M1 Output Compare 2 mode Refer to OC1M[3:0] description. 12 3 read-write OC2CE Output Compare 2 clear enable Refer to OC1CE description. 15 1 read-write OC1M2 Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. Note: The OC1M[3] bit is not contiguous, located in bit 16. 16 1 read-write B_0x0 Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). 0x0 B_0x1 Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x1 B_0x2 Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x2 B_0x3 Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0x3 B_0x4 Force inactive level - OC1REF is forced low. 0x4 B_0x5 Force active level - OC1REF is forced high. 0x5 B_0x6 PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF='0’) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’). 0x6 B_0x7 PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. 0x7 B_0x8 Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 0x8 B_0x9 Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 0x9 B_0xC Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 0xC B_0xD Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 0xD B_0xE Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 0xE B_0xF Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 0xF OC2M2 Output Compare 2 mode Refer to OC1M[3:0] description. 24 1 read-write CCMR1_Input CCMR1_Input capture/compare mode register 1 (output mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 CC1S Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER). 0 2 read-write B_0x0 CC1 channel is configured as output 0x0 B_0x1 CC1 channel is configured as input, IC1 is mapped on TI1 0x1 B_0x2 CC1 channel is configured as input, IC1 is mapped on TI2 0x2 B_0x3 CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 IC1PSC Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 2 2 read-write B_0x0 no prescaler, capture is done each time an edge is detected on the capture input 0x0 B_0x1 capture is done once every 2 events 0x1 B_0x2 capture is done once every 4 events 0x2 B_0x3 capture is done once every 8 events 0x3 IC1F Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 4 4 read-write B_0x0 No filter, sampling is done at fDTS 0x0 B_0x1 fSAMPLING=fCK_INT, N=2 0x1 B_0x2 fSAMPLING=fCK_INT, N=4 0x2 B_0x3 fSAMPLING=fCK_INT, N=8 0x3 B_0x4 fSAMPLING=fDTS/2, N=6 0x4 B_0x5 fSAMPLING=fDTS/2, N=8 0x5 B_0x6 fSAMPLING=fDTS/4, N=6 0x6 B_0x7 fSAMPLING=fDTS/4, N=8 0x7 B_0x8 fSAMPLING=fDTS/8, N=6 0x8 B_0x9 fSAMPLING=fDTS/8, N=8 0x9 B_0xA fSAMPLING=fDTS/16, N=5 0xA B_0xB fSAMPLING=fDTS/16, N=6 0xB B_0xC fSAMPLING=fDTS/16, N=8 0xC B_0xD fSAMPLING=fDTS/32, N=5 0xD B_0xE fSAMPLING=fDTS/32, N=6 0xE B_0xF fSAMPLING=fDTS/32, N=8 0xF CC2S Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER). 8 2 read-write B_0x0 CC2 channel is configured as output 0x0 B_0x1 CC2 channel is configured as input, IC2 is mapped on TI2 0x1 B_0x2 CC2 channel is configured as input, IC2 is mapped on TI1 0x2 B_0x3 CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 IC2PSC Input capture 2 prescaler Refer to IC1PSC[1:0] description. 10 2 read-write IC2F Input capture 2 filter Refer to IC1F[3:0] description. 12 4 read-write CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 CC3S Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = '0’ in TIMx_CCER). 0 2 read-write B_0x0 CC3 channel is configured as output 0x0 B_0x1 CC3 channel is configured as input, IC3 is mapped on TI3 0x1 B_0x2 CC3 channel is configured as input, IC3 is mapped on TI4 0x2 B_0x3 CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 OC3FE Output compare 3 fast enable Refer to OC1FE description. 2 1 read-write OC3PE Output compare 3 preload enable Refer to OC1PE description. 3 1 read-write OC3M1 Output compare 3 mode Refer to OC1M[3:0] description. 4 3 read-write OC3CE Output compare 3 clear enable Refer to OC1CE description. 7 1 read-write CC4S Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = '0’ in TIMx_CCER). 8 2 read-write B_0x0 CC4 channel is configured as output 0x0 B_0x1 CC4 channel is configured as input, IC4 is mapped on TI4 0x1 B_0x2 CC4 channel is configured as input, IC4 is mapped on TI3 0x2 B_0x3 CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 OC4FE Output compare 4 fast enable Refer to OC1FE description. 10 1 read-write OC4PE Output compare 4 preload enable Refer to OC1PE description. 11 1 read-write OC4M1 Output compare 4 mode Refer to OC3M[3:0] description. 12 3 read-write OC4CE Output compare 4 clear enable Refer to OC1CE description. 15 1 read-write OC3M2 Output compare 3 mode Refer to OC1M[3:0] description. 16 1 read-write OC4M2 Output compare 4 mode Refer to OC3M[3:0] description. 24 1 read-write CCMR2_Input CCMR2_Input capture/compare mode register 2 (output mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 CC3S Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = '0’ in TIMx_CCER). 0 2 read-write B_0x0 CC3 channel is configured as output 0x0 B_0x1 CC3 channel is configured as input, IC3 is mapped on TI3 0x1 B_0x2 CC3 channel is configured as input, IC3 is mapped on TI4 0x2 B_0x3 CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 IC3PSC Input capture 3 prescaler Refer to IC1PSC[1:0] description. 2 2 read-write IC3F Input capture 3 filter Refer to IC1F[3:0] description. 4 4 read-write CC4S Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = '0’ in TIMx_CCER). 8 2 read-write B_0x0 CC4 channel is configured as output 0x0 B_0x1 CC4 channel is configured as input, IC4 is mapped on TI4 0x1 B_0x2 CC4 channel is configured as input, IC4 is mapped on TI3 0x2 B_0x3 CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 IC4PSC Input capture 4 prescaler Refer to IC1PSC[1:0] description. 10 2 read-write IC4F Input capture 4 filter Refer to IC1F[3:0] description. 12 4 read-write TIM1_CCER TIM1_CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1E Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details. Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated. 0 1 read-write B_0x0 Capture mode disabled / OC1 is not active (see below) 0x0 B_0x1 Capture mode enabled / OC1 signal is output on the corresponding output pin 0x1 CC1P Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: The configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. 1 1 read-write B_0x0 OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) 0x0 B_0x1 OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) 0x1 CC1NE Capture/Compare 1 complementary output enable On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated. 2 1 read-write B_0x0 Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 0x0 B_0x1 On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 0x1 CC1NP Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (channel configured as output). On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated. 3 1 read-write B_0x0 OC1N active high. 0x0 B_0x1 OC1N active low. 0x1 CC2E Capture/Compare 2 output enable Refer to CC1E description 4 1 read-write CC2P Capture/Compare 2 output polarity Refer to CC1P description 5 1 read-write CC2NE Capture/Compare 2 complementary output enable Refer to CC1NE description 6 1 read-write CC2NP Capture/Compare 2 complementary output polarity Refer to CC1NP description 7 1 read-write CC3E Capture/Compare 3 output enable Refer to CC1E description 8 1 read-write CC3P Capture/Compare 3 output polarity Refer to CC1P description 9 1 read-write CC3NE Capture/Compare 3 complementary output enable Refer to CC1NE description 10 1 read-write CC3NP Capture/Compare 3 complementary output polarity Refer to CC1NP description 11 1 read-write CC4E Capture/Compare 4 output enable Refer to CC1E description 12 1 read-write CC4P Capture/Compare 4 output polarity Refer to CC1P description 13 1 read-write CC4NP Capture/Compare 4 complementary output polarity Refer to CC1NP description 15 1 read-write CC5E Capture/Compare 5 output enable Refer to CC1E description 16 1 read-write CC5P Capture/Compare 5 output polarity Refer to CC1P description 17 1 read-write CC6E Capture/Compare 6 output enable Refer to CC1E description 20 1 read-write CC6P Capture/Compare 6 output polarity Refer to CC1P description 21 1 read-write TIM1_CNT TIM1_CNT counter 0x24 0x20 0x00000000 CNT Counter value 0 16 read-write UIFCPY UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0. 31 1 read-only TIM1_PSC TIM1_PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). 0 16 read-write TIM1_ARR TIM1_ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 0 16 read-write TIM1_RCR TIM1_RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 16 TIM1_CCR1 TIM1_CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 TIM1_CCR2 TIM1_CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 2 value 0 16 TIM1_CCR3 TIM1_CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3 Capture/Compare value 0 16 TIM1_CCR4 TIM1_CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4 Capture/Compare value 0 16 TIM1_BDTR TIM1_BDTR break and dead-time register 0x44 0x20 read-write 0x0000 DTG Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tDTG with tDTG=tDTS. DTG[7:5]=10x => DT=(64+DTG[5:0])xtDTG with tDTG=2xtDTS. DTG[7:5]=110 => DT=(32+DTG[4:0])xtDTG with tDTG=8xtDTS. DTG[7:5]=111 => DT=(32+DTG[4:0])xtDTG with tDTG=16xtDTS. Example if tDTS=125 ns (8 MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 μs to 31750 ns  by 250 ns steps, 32 μs to 63 μs by 1 μs steps, 64 μs to 126 μs by 2 μs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 8 read-write LOCK Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 8 2 read-write B_0x0 LOCK OFF - No bit is write protected. 0x0 B_0x1 LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits in TIMx_BDTR register can no longer be written. 0x1 B_0x2 LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 0x2 B_0x3 LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. 0x3 OSSI Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write B_0x0 When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state). 0x0 B_0x1 When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output. 0x1 OSSR Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write B_0x0 When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state). 0x0 B_0x1 When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). 0x1 BKE Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per ). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 12 1 read-write B_0x0 Break function disabled 0x0 B_0x1 Break function enabled 0x1 BKP Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 13 1 read-write B_0x0 Break input BRK is active low 0x0 B_0x1 Break input BRK is active high 0x1 AOE Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 1 read-write B_0x0 MOE can be set only by software 0x0 B_0x1 MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 0x1 MOE Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). 15 1 read-write B_0x0 In response to a break 2 event. OC and OCN outputs are disabled 0x0 B_0x1 OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register). 0x1 BKF Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 4 read-write B_0x0 No filter, BRK acts asynchronously 0x0 B_0x1 fSAMPLING=fCK_INT, N=2 0x1 B_0x2 fSAMPLING=fCK_INT, N=4 0x2 B_0x3 fSAMPLING=fCK_INT, N=8 0x3 B_0x4 fSAMPLING=fDTS/2, N=6 0x4 B_0x5 fSAMPLING=fDTS/2, N=8 0x5 B_0x6 fSAMPLING=fDTS/4, N=6 0x6 B_0x7 fSAMPLING=fDTS/4, N=8 0x7 B_0x8 fSAMPLING=fDTS/8, N=6 0x8 B_0x9 fSAMPLING=fDTS/8, N=8 0x9 B_0xA fSAMPLING=fDTS/16, N=5 0xA B_0xB fSAMPLING=fDTS/16, N=6 0xB B_0xC fSAMPLING=fDTS/16, N=8 0xC B_0xD fSAMPLING=fDTS/32, N=5 0xD B_0xE fSAMPLING=fDTS/32, N=6 0xE B_0xF fSAMPLING=fDTS/32, N=8 0xF BK2F Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 20 4 read-write B_0x0 No filter, BRK2 acts asynchronously 0x0 B_0x1 fSAMPLING=fCK_INT, N=2 0x1 B_0x2 fSAMPLING=fCK_INT, N=4 0x2 B_0x3 fSAMPLING=fCK_INT, N=8 0x3 B_0x4 fSAMPLING=fDTS/2, N=6 0x4 B_0x5 fSAMPLING=fDTS/2, N=8 0x5 B_0x6 fSAMPLING=fDTS/4, N=6 0x6 B_0x7 fSAMPLING=fDTS/4, N=8 0x7 B_0x8 fSAMPLING=fDTS/8, N=6 0x8 B_0x9 fSAMPLING=fDTS/8, N=8 0x9 B_0xA fSAMPLING=fDTS/16, N=5 0xA B_0xB fSAMPLING=fDTS/16, N=6 0xB B_0xC fSAMPLING=fDTS/16, N=8 0xC B_0xD fSAMPLING=fDTS/32, N=5 0xD B_0xE fSAMPLING=fDTS/32, N=6 0xE B_0xF fSAMPLING=fDTS/32, N=8 0xF BK2E Break 2 enable Note: The BRK2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 24 1 read-write B_0x0 Break input BRK2 disabled 0x0 B_0x1 Break input BRK2 enabled 0x1 BK2P Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 25 1 read-write B_0x0 Break input BRK2 is active low 0x0 B_0x1 Break input BRK2 is active high 0x1 BKDSRM Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 26 1 read-write B_0x0 Break input BRK is armed 0x0 B_0x1 Break input BRK is disarmed 0x1 BK2DSRM Break2 Disarm Refer to BKDSRM description 27 1 read-write BKBID Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 28 1 read-write B_0x0 Break input BRK in input mode 0x0 B_0x1 Break input BRK in bidirectional mode 0x1 BK2BID Break2 bidirectional Refer to BKBID description 29 1 read-write TIM1_DCR TIM1_DCR DMA control register 0x48 0x20 read-write 0x0000 DBA DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... 0 5 read-write B_0x0 TIMx_CR1, 0x0 B_0x1 TIMx_CR2, 0x1 B_0x2 TIMx_SMCR, 0x2 DBL DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA. 8 5 read-write B_0x0 1 transfer 0x0 B_0x1 2 transfers 0x1 B_0x2 3 transfers 0x2 B_0x11 18 transfers 0x11 TIM1_DMAR TIM1_DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 32 read-write CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x54 0x20 read-write 0x00000000 OC6M_bit3 Output Compare 6 mode bit 3 24 1 OC5M_bit3 Output Compare 5 mode bit 3 16 1 OC6CE Output compare 6 clear enable 15 1 OC6M Output compare 6 mode 12 3 OC6PE Output compare 6 preload enable 11 1 OC6FE Output compare 6 fast enable 10 1 OC5CE Output compare 5 clear enable 7 1 OC5M Output compare 5 mode 4 3 OC5PE Output compare 5 preload enable 3 1 OC5FE Output compare 5 fast enable 2 1 TIM1_CCR5 TIM1_CCR5 capture/compare register 4 0x58 0x20 read-write 0x00000000 CCR5 Capture/Compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC5 output. 0 16 read-write GC5C1 Group Channel 5 and Channel 1 Distortion on Channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. 29 1 read-write B_0x0 No effect of OC5REF on OC1REFC5 0x0 B_0x1 OC1REFC is the logical AND of OC1REFC and OC5REF 0x1 GC5C2 Group Channel 5 and Channel 2 Distortion on Channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. 30 1 read-write B_0x0 No effect of OC5REF on OC2REFC 0x0 B_0x1 OC2REFC is the logical AND of OC2REFC and OC5REF 0x1 GC5C3 Group Channel 5 and Channel 3 Distortion on Channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals. 31 1 read-write B_0x0 No effect of OC5REF on OC3REFC 0x0 B_0x1 OC3REFC is the logical AND of OC3REFC and OC5REF 0x1 TIM1_CCR6 TIM1_CCR6 capture/compare register 6 0x5C 0x20 read-write 0x00000000 CCR6 Capture/Compare value 0 16 TIM1_AF1 TIM1_AF1 TIM1 alternate function option register 1 0x60 0x20 read-write 0x00000001 BKINE BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write B_0x0 BKIN input disabled 0x0 B_0x1 BKIN input enabled 0x1 BKINP BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write B_0x0 BKIN input polarity is not inverted (active low if BKP=0, active high if BKP=1) 0x0 B_0x1 BKIN input polarity is inverted (active high if BKP=0, active low if BKP=1) 0x1 ETRSEL ETR source selection These bits select the ETR input source. Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 4 read-write B_0x0 ETR legacy mode 0x0 B_0x1 COMP1 output 0x1 B_0x2 COMP2 output 0x2 B_0x3 ADC1 AWD1 0x3 B_0x4 ADC1 AWD2 0x4 B_0x5 ADC1 AWD3 0x5 TIM1_AF2 TIM1_AF2 TIM1 alternate function option register 2 0x64 0x20 read-write 0x00000001 BK2INE BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timer’s BRK2 input. BKIN2 input is 'ORed’ with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write B_0x0 BKIN2 input disabled 0x0 B_0x1 BKIN2 input enabled 0x1 BK2INP BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write B_0x0 BKIN2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1) 0x0 B_0x1 BKIN2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1) 0x1 TIM1_TISEL TIM1_TISEL TIM1 timer input selection register 0x68 0x20 read-write 0x00000000 TI1SEL selects TI1[0] to TI1[15] input Others: Reserved 0 4 read-write B_0x0 TIM1_CH1 input 0x0 B_0x1 COMP1 output 0x1 TI2SEL selects TI2[0] to TI2[15] input Others: Reserved 8 4 read-write B_0x0 TIM1_CH2 input 0x0 B_0x1 COMP2 output 0x1 TI3SEL selects TI3[0] to TI3[15] input Others: Reserved 16 4 read-write B_0x0 TIM1_CH3 input 0x0 TI4SEL selects TI4[0] to TI4[15] input Others: Reserved 24 4 read-write B_0x0 TIM1_CH4 input 0x0 TIM3 General-purpose-timers TIM 0x40000400 0x0 0x400 registers TIM3 TIM3 global interrupt 16 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CEN Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 read-write B_0x0 Counter disabled 0x0 B_0x1 Counter enabled 0x1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write B_0x0 UEV enabled. The Update (UEV) event is generated by one of the following events: 0x0 B_0x1 UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. 0x1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write B_0x0 Any of the following events generate an update interrupt or DMA request if enabled. These events can be: 0x0 B_0x1 Only counter overflow/underflow generates an update interrupt or DMA request if enabled. 0x1 OPM One-pulse mode 3 1 read-write B_0x0 Counter is not stopped at update event 0x0 B_0x1 Counter stops counting at the next update event (clearing the bit CEN) 0x1 DIR Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. 4 1 read-write B_0x0 Counter used as upcounter 0x0 B_0x1 Counter used as downcounter 0x1 CMS Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) 5 2 read-write B_0x0 Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 0x0 B_0x1 Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 0x1 B_0x2 Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 0x2 B_0x3 Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. 0x3 ARPE Auto-reload preload enable 7 1 read-write B_0x0 TIMx_ARR register is not buffered 0x0 B_0x1 TIMx_ARR register is buffered 0x1 CKD Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx), 8 2 read-write B_0x0 tDTS = tCK_INT 0x0 B_0x1 tDTS = 2 × tCK_INT 0x1 B_0x2 tDTS = 4 × tCK_INT 0x2 UIFREMAP UIF status bit remapping 11 1 read-write B_0x0 No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 0x0 B_0x1 Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. 0x1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 CCDS Capture/compare DMA selection 3 1 read-write B_0x0 CCx DMA request sent when CCx event occurs 0x0 B_0x1 CCx DMA requests sent when update event occurs 0x1 MMS Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 4 3 read-write B_0x0 Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 0x0 B_0x1 Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. 0x1 B_0x2 Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 0x2 B_0x3 Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO) 0x3 B_0x4 Compare - OC1REFC signal is used as trigger output (TRGO) 0x4 B_0x5 Compare - OC2REFC signal is used as trigger output (TRGO) 0x5 B_0x6 Compare - OC3REFC signal is used as trigger output (TRGO) 0x6 B_0x7 Compare - OC4REFC signal is used as trigger output (TRGO) 0x7 TI1S TI1 selection 7 1 read-write B_0x0 The TIMx_CH1 pin is connected to TI1 input 0x0 B_0x1 The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also 0x1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 SMS1 Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write B_0x0 Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock. 0x0 B_0x1 Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 0x1 B_0x2 Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 0x2 B_0x3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 0x3 B_0x4 Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0x4 B_0x5 Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0x5 B_0x6 Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0x6 B_0x7 External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 0x7 B_0x8 Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) 0x8 OCCS OCREF clear selection This bit is used to select the OCREF clear source 3 1 read-write B_0x0 OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIMx_OR1.OCREF_CLR 0x0 B_0x1 OCREF_CLR_INT is connected to ETRF 0x1 TS1 Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write B_0x0 Internal Trigger 0 (ITR0) 0x0 B_0x1 Internal Trigger 1 (ITR1) 0x1 B_0x2 Internal Trigger 2 (ITR2) 0x2 B_0x3 Internal Trigger 3 (ITR3) 0x3 B_0x4 TI1 Edge Detector (TI1F_ED) 0x4 B_0x5 Filtered Timer Input 1 (TI1FP1) 0x5 B_0x6 Filtered Timer Input 2 (TI2FP2) 0x6 B_0x7 External Trigger input (ETRF) 0x7 B_0x8 Internal Trigger 4 (ITR4) 0x8 B_0x9 Internal Trigger 5 (ITR5) 0x9 B_0xA Internal Trigger 6 (ITR6) 0xA B_0xB Internal Trigger 7 (ITR7) 0xB B_0xC Internal Trigger 8 (ITR8) 0xC MSM Master/Slave mode 7 1 read-write B_0x0 No action 0x0 B_0x1 The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 0x1 ETF External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 8 4 read-write B_0x0 No filter, sampling is done at fDTS 0x0 B_0x1 fSAMPLING=fCK_INT, N=2 0x1 B_0x2 fSAMPLING=fCK_INT, N=4 0x2 B_0x3 fSAMPLING=fCK_INT, N=8 0x3 B_0x4 fSAMPLING=fDTS/2, N=6 0x4 B_0x5 fSAMPLING=fDTS/2, N=8 0x5 B_0x6 fSAMPLING=fDTS/4, N=6 0x6 B_0x7 fSAMPLING=fDTS/4, N=8 0x7 B_0x8 fSAMPLING=fDTS/8, N=6 0x8 B_0x9 fSAMPLING=fDTS/8, N=8 0x9 B_0xA fSAMPLING=fDTS/16, N=5 0xA B_0xB fSAMPLING=fDTS/16, N=6 0xB B_0xC fSAMPLING=fDTS/16, N=8 0xC B_0xD fSAMPLING=fDTS/32, N=5 0xD B_0xE fSAMPLING=fDTS/32, N=6 0xE B_0xF fSAMPLING=fDTS/32, N=8 0xF ETPS External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 12 2 read-write B_0x0 Prescaler OFF 0x0 B_0x1 ETRP frequency divided by 2 0x1 B_0x2 ETRP frequency divided by 4 0x2 B_0x3 ETRP frequency divided by 8 0x3 ECE External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. 14 1 read-write B_0x0 External clock mode 2 disabled 0x0 B_0x1 External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 0x1 ETP External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 15 1 read-write B_0x0 ETR is non-inverted, active at high level or rising edge 0x0 B_0x1 ETR is inverted, active at low level or falling edge 0x1 SMS2 Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 16 1 read-write B_0x0 Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock. 0x0 B_0x1 Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 0x1 B_0x2 Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 0x2 B_0x3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 0x3 B_0x4 Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0x4 B_0x5 Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0x5 B_0x6 Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0x6 B_0x7 External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 0x7 B_0x8 Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) 0x8 TS2 Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 20 2 read-write B_0x0 Internal Trigger 0 (ITR0) 0x0 B_0x1 Internal Trigger 1 (ITR1) 0x1 B_0x2 Internal Trigger 2 (ITR2) 0x2 B_0x3 Internal Trigger 3 (ITR3) 0x3 B_0x4 TI1 Edge Detector (TI1F_ED) 0x4 B_0x5 Filtered Timer Input 1 (TI1FP1) 0x5 B_0x6 Filtered Timer Input 2 (TI2FP2) 0x6 B_0x7 External Trigger input (ETRF) 0x7 B_0x8 Internal Trigger 4 (ITR4) 0x8 B_0x9 Internal Trigger 5 (ITR5) 0x9 B_0xA Internal Trigger 6 (ITR6) 0xA B_0xB Internal Trigger 7 (ITR7) 0xB B_0xC Internal Trigger 8 (ITR8) 0xC DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 UIE Update interrupt enable 0 1 read-write B_0x0 Update interrupt disabled. 0x0 B_0x1 Update interrupt enabled. 0x1 CC1IE Capture/Compare 1 interrupt enable 1 1 read-write B_0x0 CC1 interrupt disabled. 0x0 B_0x1 CC1 interrupt enabled. 0x1 CC2IE Capture/Compare 2 interrupt enable 2 1 read-write B_0x0 CC2 interrupt disabled. 0x0 B_0x1 CC2 interrupt enabled. 0x1 CC3IE Capture/Compare 3 interrupt enable 3 1 read-write B_0x0 CC3 interrupt disabled. 0x0 B_0x1 CC3 interrupt enabled. 0x1 CC4IE Capture/Compare 4 interrupt enable 4 1 read-write B_0x0 CC4 interrupt disabled. 0x0 B_0x1 CC4 interrupt enabled. 0x1 TIE Trigger interrupt enable 6 1 read-write B_0x0 Trigger interrupt disabled. 0x0 B_0x1 Trigger interrupt enabled. 0x1 UDE Update DMA request enable 8 1 read-write B_0x0 Update DMA request disabled. 0x0 B_0x1 Update DMA request enabled. 0x1 CC1DE Capture/Compare 1 DMA request enable 9 1 read-write B_0x0 CC1 DMA request disabled. 0x0 B_0x1 CC1 DMA request enabled. 0x1 CC2DE Capture/Compare 2 DMA request enable 10 1 read-write B_0x0 CC2 DMA request disabled. 0x0 B_0x1 CC2 DMA request enabled. 0x1 CC3DE Capture/Compare 3 DMA request enable 11 1 read-write B_0x0 CC3 DMA request disabled. 0x0 B_0x1 CC3 DMA request enabled. 0x1 CC4DE Capture/Compare 4 DMA request enable 12 1 read-write B_0x0 CC4 DMA request disabled. 0x0 B_0x1 CC4 DMA request enabled. 0x1 TDE Trigger DMA request enable 14 1 read-write B_0x0 Trigger DMA request disabled. 0x0 B_0x1 Trigger DMA request enabled. 0x1 SR SR status register 0x10 0x20 read-write 0x0000 UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write B_0x0 No update occurred 0x0 B_0x1 Update interrupt pending. This bit is set by hardware when the registers are updated: 0x1 CC1IF Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). 1 1 read-write B_0x0 No compare match / No input capture occurred 0x0 B_0x1 A compare match or an input capture occurred 0x1 CC2IF Capture/Compare 2 interrupt flag Refer to CC1IF description 2 1 read-write CC3IF Capture/Compare 3 interrupt flag Refer to CC1IF description 3 1 read-write CC4IF Capture/Compare 4 interrupt flag Refer to CC1IF description 4 1 read-write TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write B_0x0 No trigger event occurred. 0x0 B_0x1 Trigger interrupt pending. 0x1 CC1OF Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’. 9 1 read-write B_0x0 No overcapture has been detected. 0x0 B_0x1 The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set 0x1 CC2OF Capture/compare 2 overcapture flag refer to CC1OF description 10 1 read-write CC3OF Capture/Compare 3 overcapture flag refer to CC1OF description 11 1 read-write CC4OF Capture/Compare 4 overcapture flag refer to CC1OF description 12 1 read-write EGR EGR event generation register 0x14 0x20 write-only 0x0000 UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only B_0x0 No action 0x0 B_0x1 Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). 0x1 CC1G Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. 1 1 write-only B_0x0 No action 0x0 B_0x1 A capture/compare event is generated on channel 1: 0x1 CC2G Capture/compare 2 generation Refer to CC1G description 2 1 write-only CC3G Capture/compare 3 generation Refer to CC1G description 3 1 write-only CC4G Capture/compare 4 generation Refer to CC1G description 4 1 write-only TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only B_0x0 No action 0x0 B_0x1 The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 0x1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC2CE Output compare 2 clear enable 15 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 OC2FE Output compare 2 fast enable 10 1 CC2S Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). 8 2 read-write B_0x0 CC2 channel is configured as output. 0x0 B_0x1 CC2 channel is configured as input, IC2 is mapped on TI2. 0x1 B_0x2 CC2 channel is configured as input, IC2 is mapped on TI1. 0x2 B_0x3 CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 OC1CE Output compare 1 clear enable 7 1 read-write B_0x0 OC1Ref is not affected by the ETRF input 0x0 B_0x1 OC1Ref is cleared as soon as a High level is detected on ETRF input 0x1 OC1M1 Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Note: The OC1M[3] bit is not contiguous, located in bit 16. 4 3 read-write B_0x0 Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). 0x0 B_0x1 Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x1 B_0x2 Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x2 B_0x3 Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0x3 B_0x4 Force inactive level - OC1REF is forced low. 0x4 B_0x5 Force active level - OC1REF is forced high. 0x5 B_0x6 PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF='0) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=1). 0x6 B_0x7 PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. 0x7 B_0x8 Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 0x8 B_0x9 Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 0x9 B_0xC Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 0xC B_0xD Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 0xD B_0xE Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 0xE B_0xF Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 0xF OC1PE Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. 3 1 read-write B_0x0 Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 0x0 B_0x1 Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. 0x1 OC1FE Output compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write B_0x0 CC1 channel is configured as output 0x0 B_0x1 CC1 channel is configured as input, IC1 is mapped on TI1 0x1 B_0x2 CC1 channel is configured as input, IC1 is mapped on TI2 0x2 B_0x3 CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). 8 2 read-write B_0x0 CC4 channel is configured as output 0x0 B_0x1 CC4 channel is configured as input, IC4 is mapped on TI4 0x1 B_0x2 CC4 channel is configured as input, IC4 is mapped on TI3 0x2 B_0x3 CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 0 2 read-write B_0x0 CC3 channel is configured as output 0x0 B_0x1 CC3 channel is configured as input, IC3 is mapped on TI3 0x1 B_0x2 CC3 channel is configured as input, IC3 is mapped on TI4 0x2 B_0x3 CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1E Capture/Compare 1 output enable. 0 1 read-write B_0x0 Capture mode disabled / OC1 is not active 0x0 B_0x1 Capture mode enabled / OC1 signal is output on the corresponding output pin 0x1 CC1P Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used. 1 1 read-write B_0x0 OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) 0x0 B_0x1 OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) 0x1 CC1NP Capture/Compare 1 output Polarity. CC1 channel configured as output: CC1NP must be kept cleared in this case. CC1 channel configured as input: This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description. 3 1 read-write CC2E Capture/Compare 2 output enable. Refer to CC1E description 4 1 read-write CC2P Capture/Compare 2 output Polarity. refer to CC1P description 5 1 read-write CC2NP Capture/Compare 2 output Polarity. Refer to CC1NP description 7 1 read-write CC3E Capture/Compare 3 output enable. Refer to CC1E description 8 1 read-write CC3P Capture/Compare 3 output Polarity. Refer to CC1P description 9 1 read-write CC3NP Capture/Compare 3 output Polarity. Refer to CC1NP description 11 1 read-write CC4E Capture/Compare 4 output enable. refer to CC1E description 12 1 read-write CC4P Capture/Compare 4 output Polarity. Refer to CC1P description 13 1 read-write CC4NP Capture/Compare 4 output Polarity. Refer to CC1NP description 15 1 read-write CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT_H High counter value (TIM2 only) 16 16 CNT_L Low counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0xFFFFFFFF ARR High auto-reload value (TIM2) nullLow Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 0 32 read-write CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 High Capture/Compare 1 value (TIM2) nullLow Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed. 0 32 read-write CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 High Capture/Compare 2 value (TIM2) nullLow Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed. 0 32 read-write CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3 High Capture/Compare 3 value (TIM2) nullLow Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed. 0 32 read-write CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4 High Capture/Compare 4 value (TIM2) nullLow Capture/Compare value if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed. 0 32 read-write DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBA DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 0 5 read-write B_0x0 TIMx_CR1 0x0 B_0x1 TIMx_CR2 0x1 B_0x2 TIMx_SMCR 0x2 DBL DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ... 8 5 read-write B_0x0 1 transfer, 0x0 B_0x1 2 transfers, 0x1 B_0x2 3 transfers, 0x2 B_0x11 18 transfers. 0x11 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 AF1 AF1 TIM alternate function option register 1 0x60 0x20 read-write 0x0000 ETRSEL ETR source selection These bits select the ETR input source. Others: Reserved 14 4 read-write B_0x0 ETR legacy mode 0x0 B_0x1 COMP1 0x1 B_0x2 COMP2 0x2 B_0x3 LSE 0x3 TISEL TISEL TIM alternate function option register 1 0x68 0x20 read-write 0x0000 TI1SEL TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved 0 4 read-write B_0x0 TIM2_CH1 input 0x0 B_0x1 COMP1 output 0x1 TI2SEL TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved 8 4 read-write B_0x0 TIM2_CH2 input 0x0 B_0x1 COMP2 output 0x1 TI3SEL TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. Others: Reserved 16 4 read-write B_0x0 TIM2_CH3 input 0x0 B_0x1 COMP3 output 0x1 TIM6 Basic timers TIM 0x40001000 0x0 0x400 registers TIM6 TIM6 global interrupt 17 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CEN Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 read-write B_0x0 Counter disabled 0x0 B_0x1 Counter enabled 0x1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write B_0x0 UEV enabled. The Update (UEV) event is generated by one of the following events: 0x0 B_0x1 UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. 0x1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write B_0x0 Any of the following events generates an update interrupt or DMA request if enabled. These events can be: 0x0 B_0x1 Only counter overflow/underflow generates an update interrupt or DMA request if enabled. 0x1 OPM One-pulse mode 3 1 read-write B_0x0 Counter is not stopped at update event 0x0 B_0x1 Counter stops counting at the next update event (clearing the CEN bit). 0x1 ARPE Auto-reload preload enable 7 1 read-write B_0x0 TIMx_ARR register is not buffered. 0x0 B_0x1 TIMx_ARR register is buffered. 0x1 UIFREMAP UIF status bit remapping 11 1 read-write B_0x0 No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 0x0 B_0x1 Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. 0x1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 MMS Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 4 3 read-write B_0x0 Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 0x0 B_0x1 Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. 0x1 B_0x2 Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 0x2 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 UIE Update interrupt enable 0 1 read-write B_0x0 Update interrupt disabled. 0x0 B_0x1 Update interrupt enabled. 0x1 UDE Update DMA request enable 8 1 read-write B_0x0 Update DMA request disabled. 0x0 B_0x1 Update DMA request enabled. 0x1 SR SR status register 0x10 0x20 read-write 0x0000 UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register. 0 1 read-write B_0x0 No update occurred. 0x0 B_0x1 Update interrupt pending. This bit is set by hardware when the registers are updated: 0x1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only B_0x0 No action. 0x0 B_0x1 Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected). 0x1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT Counter value 0 16 read-write UIFCPY UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR Prescaler value 0 16 TIM7 0x40001400 TIM7 TIM7 global interrupt 18 TIM14 General purpose timers TIM 0x40002000 0x0 0x400 registers TIM14 TIM14 global interrupt 19 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CEN Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write B_0x0 Counter disabled 0x0 B_0x1 Counter enabled 0x1 UDIS Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. Counter overflow Setting the UG bit. Buffered registers are then loaded with their preload values. 1 1 read-write B_0x0 UEV enabled. An UEV is generated by one of the following events: 0x0 B_0x1 UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set. 0x1 URS Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. Counter overflow Setting the UG bit 2 1 read-write B_0x0 Any of the following events generate an UEV if enabled: 0x0 B_0x1 Only counter overflow generates an UEV if enabled. 0x1 OPM One-pulse mode 3 1 read-write B_0x0 Counter is not stopped on the update event 0x0 B_0x1 Counter stops counting on the next update event (clearing the CEN bit). 0x1 ARPE Auto-reload preload enable 7 1 read-write B_0x0 TIMx_ARR register is not buffered 0x0 B_0x1 TIMx_ARR register is buffered 0x1 CKD Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx), 8 2 read-write B_0x0 tDTS = tCK_INT 0x0 B_0x1 tDTS = 2 × tCK_INT 0x1 B_0x2 tDTS = 4 × tCK_INT 0x2 UIFREMAP UIF status bit remapping 11 1 read-write B_0x0 No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 0x0 B_0x1 Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. 0x1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 UIE Update interrupt enable 0 1 read-write B_0x0 Update interrupt disabled 0x0 B_0x1 Update interrupt enabled 0x1 CC1IE Capture/Compare 1 interrupt enable 1 1 read-write B_0x0 CC1 interrupt disabled 0x0 B_0x1 CC1 interrupt enabled 0x1 SR SR status register 0x10 0x20 read-write 0x0000 UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=’0’ in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register. 0 1 read-write B_0x0 No update occurred. 0x0 B_0x1 Update interrupt pending. This bit is set by hardware when the registers are updated: 0x1 CC1IF Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). 1 1 read-write B_0x0 No compare match / No input capture occurred 0x0 B_0x1 A compare match or an input capture occurred. 0x1 CC1OF Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’. 9 1 read-write B_0x0 No overcapture has been detected. 0x0 B_0x1 The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set 0x1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only B_0x0 No action 0x0 B_0x1 Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared. 0x1 CC1G Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. 1 1 write-only B_0x0 No action 0x0 B_0x1 A capture/compare event is generated on channel 1: 0x1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write B_0x0 CC1 channel is configured as output. 0x0 B_0x1 CC1 channel is configured as input, IC1 is mapped on TI1. 0x1 OC1FE Output compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. 2 1 read-write B_0x0 CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 0x0 B_0x1 An active edge on the trigger input acts like a compare match on CC1 output. OC is then set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode. 0x1 OC1PE Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. 3 1 read-write B_0x0 Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 0x0 B_0x1 Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. 0x1 OC1M1 Output compare 1 mode (refer to bit 16 for OC1M[3]) These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. Others: Reserved Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16. 4 3 read-write B_0x0 Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 0x0 B_0x1 Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x1 B_0x2 Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x2 B_0x3 Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1. 0x3 B_0x4 Force inactive level - OC1REF is forced low. 0x4 B_0x5 Force active level - OC1REF is forced high. 0x5 B_0x6 PWM mode 1 - Channel 1 is active as long as TIMx_CNT < TIMx_CCR1 else inactive. 0x6 B_0x7 PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT < TIMx_CCR1 else active 0x7 OC1M2 Output compare 1 mode (refer to bit 16 for OC1M[3]) These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. Others: Reserved Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16. 16 1 read-write B_0x0 Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 0x0 B_0x1 Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x1 B_0x2 Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x2 B_0x3 Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1. 0x3 B_0x4 Force inactive level - OC1REF is forced low. 0x4 B_0x5 Force active level - OC1REF is forced high. 0x5 B_0x6 PWM mode 1 - Channel 1 is active as long as TIMx_CNT < TIMx_CCR1 else inactive. 0x6 B_0x7 PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT < TIMx_CCR1 else active 0x7 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write B_0x0 CC1 channel is configured as output 0x0 B_0x1 CC1 channel is configured as input, IC1 is mapped on TI1 0x1 IC1PSC Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 2 2 read-write B_0x0 no prescaler, capture is done each time an edge is detected on the capture input 0x0 B_0x1 capture is done once every 2 events 0x1 B_0x2 capture is done once every 4 events 0x2 B_0x3 capture is done once every 8 events 0x3 IC1F Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 4 4 read-write B_0x0 No filter, sampling is done at fDTS 0x0 B_0x1 fSAMPLING=fCK_INT, N=2 0x1 B_0x2 fSAMPLING=fCK_INT, N=4 0x2 B_0x3 fSAMPLING=fCK_INT, N=8 0x3 B_0x4 fSAMPLING=fDTS/2, N=6 0x4 B_0x5 fSAMPLING=fDTS/2, N=8 0x5 B_0x6 fSAMPLING=fDTS/4, N=6 0x6 B_0x7 fSAMPLING=fDTS/4, N=8 0x7 B_0x8 fSAMPLING=fDTS/8, N=6 0x8 B_0x9 fSAMPLING=fDTS/8, N=8 0x9 B_0xA fSAMPLING=fDTS/16, N=5 0xA B_0xB fSAMPLING=fDTS/16, N=6 0xB B_0xC fSAMPLING=fDTS/16, N=8 0xC B_0xD fSAMPLING=fDTS/32, N=5 0xD B_0xE fSAMPLING=fDTS/32, N=6 0xE B_0xF fSAMPLING=fDTS/32, N=8 0xF CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1E Capture/Compare 1 output enable. 0 1 read-write B_0x0 Capture mode disabled / OC1 is not active 0x0 B_0x1 Capture mode enabled / OC1 signal is output on the corresponding output pin 0x1 CC1P Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used. 1 1 read-write B_0x0 OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) 0x0 B_0x1 OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) 0x1 CC1NP Capture/Compare 1 complementary output Polarity. CC1 channel configured as output: CC1NP must be kept cleared. CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define TI1FP1 polarity (refer to CC1P description). 3 1 read-write CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT low counter value 0 16 UIFCPY UIF Copy 31 1 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Low Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Low Capture/Compare 1 value 0 16 TISEL TISEL TIM timer input selection register 0x68 0x20 read-write 0x0000 TI1SEL selects TI1[0] to TI1[15] input Others: Reserved 0 4 read-write B_0x0 TIM14_CH1 input 0x0 B_0x1 RTC CLK 0x1 B_0x2 HSE/32 0x2 B_0x3 MCO 0x3 TIM15 General purpose timers TIM 0x40014000 0x0 0x400 registers TIM15 TIM 15 global interrupt 20 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CEN Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write B_0x0 Counter disabled 0x0 B_0x1 Counter enabled 0x1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write B_0x0 UEV enabled. The Update (UEV) event is generated by one of the following events: 0x0 B_0x1 UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. 0x1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write B_0x0 Any of the following events generate an update interrupt if enabled. These events can be: 0x0 B_0x1 Only counter overflow/underflow generates an update interrupt if enabled 0x1 OPM One-pulse mode 3 1 read-write B_0x0 Counter is not stopped at update event 0x0 B_0x1 Counter stops counting at the next update event (clearing the bit CEN) 0x1 ARPE Auto-reload preload enable 7 1 read-write B_0x0 TIMx_ARR register is not buffered 0x0 B_0x1 TIMx_ARR register is buffered 0x1 CKD Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx) 8 2 read-write B_0x0 tDTS = tCK_INT 0x0 B_0x1 tDTS = 2*tCK_INT 0x1 B_0x2 tDTS = 4*tCK_INT 0x2 B_0x3 Reserved, do not program this value 0x3 UIFREMAP UIF status bit remapping 11 1 read-write B_0x0 No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 0x0 B_0x1 Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. 0x1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 CCPC Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 1 read-write B_0x0 CCxE, CCxNE and OCxM bits are not preloaded 0x0 B_0x1 CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). 0x1 CCUS Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 2 1 read-write B_0x0 When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. 0x0 B_0x1 When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. 0x1 CCDS Capture/compare DMA selection 3 1 read-write B_0x0 CCx DMA request sent when CCx event occurs 0x0 B_0x1 CCx DMA requests sent when update event occurs 0x1 MMS Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 4 3 read-write B_0x0 Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 0x0 B_0x1 Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 0x1 B_0x2 Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 0x2 B_0x3 Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). 0x3 B_0x4 Compare - OC1REFC signal is used as trigger output (TRGO). 0x4 B_0x5 Compare - OC2REFC signal is used as trigger output (TRGO). 0x5 TI1S TI1 selection 7 1 read-write B_0x0 The TIMx_CH1 pin is connected to TI1 input 0x0 B_0x1 The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination) 0x1 OIS1 Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register). 8 1 read-write B_0x0 OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 0x0 B_0x1 OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 0x1 OIS1N Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register). 9 1 read-write B_0x0 OC1N=0 after a dead-time when MOE=0 0x0 B_0x1 OC1N=1 after a dead-time when MOE=0 0x1 OIS2 Output idle state 2 (OC2 output) Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIM15_BDTR register). 10 1 read-write B_0x0 OC2=0 when MOE=0 0x0 B_0x1 OC2=1 when MOE=0 0x1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 SMS1 Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write B_0x0 Slave mode disabled - if CEN = '1’ then the prescaler is clocked directly by the internal clock. 0x0 B_0x4 Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0x4 B_0x5 Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0x5 B_0x6 Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0x6 B_0x7 External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 0x7 B_0x8 Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 0x8 TS1 Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write B_0x0 Internal Trigger 0 (ITR0) 0x0 B_0x1 Internal Trigger 1 (ITR1) 0x1 B_0x2 Internal Trigger 2 (ITR2) 0x2 B_0x3 Internal Trigger 3 (ITR3) 0x3 B_0x4 TI1 Edge Detector (TI1F_ED) 0x4 B_0x5 Filtered Timer Input 1 (TI1FP1) 0x5 B_0x6 Filtered Timer Input 2 (TI2FP2) 0x6 MSM Master/slave mode 7 1 read-write B_0x0 No action 0x0 B_0x1 The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 0x1 SMS2 Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 16 1 read-write B_0x0 Slave mode disabled - if CEN = '1’ then the prescaler is clocked directly by the internal clock. 0x0 B_0x4 Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0x4 B_0x5 Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0x5 B_0x6 Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0x6 B_0x7 External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 0x7 B_0x8 Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 0x8 TS2 Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 20 2 read-write B_0x0 Internal Trigger 0 (ITR0) 0x0 B_0x1 Internal Trigger 1 (ITR1) 0x1 B_0x2 Internal Trigger 2 (ITR2) 0x2 B_0x3 Internal Trigger 3 (ITR3) 0x3 B_0x4 TI1 Edge Detector (TI1F_ED) 0x4 B_0x5 Filtered Timer Input 1 (TI1FP1) 0x5 B_0x6 Filtered Timer Input 2 (TI2FP2) 0x6 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 UIE Update interrupt enable 0 1 read-write B_0x0 Update interrupt disabled 0x0 B_0x1 Update interrupt enabled 0x1 CC1IE Capture/Compare 1 interrupt enable 1 1 read-write B_0x0 CC1 interrupt disabled 0x0 B_0x1 CC1 interrupt enabled 0x1 CC2IE Capture/Compare 2 interrupt enable 2 1 read-write B_0x0 CC2 interrupt disabled 0x0 B_0x1 CC2 interrupt enabled 0x1 COMIE COM interrupt enable 5 1 read-write B_0x0 COM interrupt disabled 0x0 B_0x1 COM interrupt enabled 0x1 TIE Trigger interrupt enable 6 1 read-write B_0x0 Trigger interrupt disabled 0x0 B_0x1 Trigger interrupt enabled 0x1 BIE Break interrupt enable 7 1 read-write B_0x0 Break interrupt disabled 0x0 B_0x1 Break interrupt enabled 0x1 UDE Update DMA request enable 8 1 read-write B_0x0 Update DMA request disabled 0x0 B_0x1 Update DMA request enabled 0x1 CC1DE Capture/Compare 1 DMA request enable 9 1 read-write B_0x0 CC1 DMA request disabled 0x0 B_0x1 CC1 DMA request enabled 0x1 CC2DE Capture/Compare 2 DMA request enable 10 1 read-write B_0x0 CC2 DMA request disabled 0x0 B_0x1 CC2 DMA request enabled 0x1 COMDE COM DMA request enable 13 1 read-write B_0x0 COM DMA request disabled 0x0 B_0x1 COM DMA request enabled 0x1 TDE Trigger DMA request enable 14 1 read-write B_0x0 Trigger DMA request disabled 0x0 B_0x1 Trigger DMA request enabled 0x1 SR SR status register 0x10 0x20 read-write 0x0000 UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write B_0x0 No update occurred. 0x0 B_0x1 Update interrupt pending. This bit is set by hardware when the registers are updated: 0x1 CC1IF Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). 1 1 read-write B_0x0 No compare match / No input capture occurred 0x0 B_0x1 A compare match or an input capture occurred 0x1 CC2IF Capture/Compare 2 interrupt flag refer to CC1IF description 2 1 read-write COMIF COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software. 5 1 read-write B_0x0 No COM event occurred 0x0 B_0x1 COM interrupt pending 0x1 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write B_0x0 No trigger event occurred 0x0 B_0x1 Trigger interrupt pending 0x1 BIF Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 7 1 read-write B_0x0 No break event occurred 0x0 B_0x1 An active level has been detected on the break input 0x1 CC1OF Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’. 9 1 read-write B_0x0 No overcapture has been detected 0x0 B_0x1 The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set 0x1 CC2OF Capture/Compare 2 overcapture flag Refer to CC1OF description 10 1 read-write EGR EGR event generation register 0x14 0x20 write-only 0x0000 UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only B_0x0 No action 0x0 B_0x1 Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). 0x1 CC1G Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. 1 1 write-only B_0x0 No action 0x0 B_0x1 A capture/compare event is generated on channel 1: 0x1 CC2G Capture/Compare 2 generation Refer to CC1G description 2 1 write-only COMG Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output. 5 1 read-write B_0x0 No action 0x0 B_0x1 When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits 0x1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only B_0x0 No action 0x0 B_0x1 The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled 0x1 BG Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 7 1 write-only B_0x0 No action 0x0 B_0x1 A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. 0x1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER). 0 2 read-write B_0x0 CC1 channel is configured as output. 0x0 B_0x1 CC1 channel is configured as input, IC1 is mapped on TI1. 0x1 B_0x2 CC1 channel is configured as input, IC1 is mapped on TI2. 0x2 B_0x3 CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 OC1FE Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. 2 1 read-write B_0x0 CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 0x0 B_0x1 An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. 0x1 OC1PE Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. 3 1 read-write B_0x0 Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 0x0 B_0x1 Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. 0x1 OC1M1 Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16. 4 3 read-write B_0x0 Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 0x0 B_0x1 Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x1 B_0x2 Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x2 B_0x3 Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0x3 B_0x4 Force inactive level - OC1REF is forced low. 0x4 B_0x5 Force active level - OC1REF is forced high. 0x5 B_0x6 PWM mode 1 - Channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. 0x6 B_0x7 PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. 0x7 B_0x8 Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 0x8 B_0x9 Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 0x9 B_0xC Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 0xC B_0xD Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 0xD CC2S Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER). 8 2 read-write B_0x0 CC2 channel is configured as output. 0x0 B_0x1 CC2 channel is configured as input, IC2 is mapped on TI2. 0x1 B_0x2 CC2 channel is configured as input, IC2 is mapped on TI1. 0x2 B_0x3 CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) 0x3 OC2FE Output Compare 2 fast enable 10 1 read-write OC2PE Output Compare 2 preload enable 11 1 read-write OC2M1 Output Compare 2 mode 12 3 read-write OC1M2 Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16. 16 1 read-write B_0x0 Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 0x0 B_0x1 Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x1 B_0x2 Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x2 B_0x3 Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0x3 B_0x4 Force inactive level - OC1REF is forced low. 0x4 B_0x5 Force active level - OC1REF is forced high. 0x5 B_0x6 PWM mode 1 - Channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. 0x6 B_0x7 PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. 0x7 B_0x8 Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 0x8 B_0x9 Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 0x9 B_0xC Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 0xC B_0xD Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 0xD OC2M2 Output Compare 2 mode 24 1 read-write CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 CC1S Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER). 0 2 read-write B_0x0 CC1 channel is configured as output 0x0 B_0x1 CC1 channel is configured as input, IC1 is mapped on TI1 0x1 B_0x2 CC1 channel is configured as input, IC1 is mapped on TI2 0x2 B_0x3 CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 IC1PSC Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 2 2 read-write B_0x0 no prescaler, capture is done each time an edge is detected on the capture input 0x0 B_0x1 capture is done once every 2 events 0x1 B_0x2 capture is done once every 4 events 0x2 B_0x3 capture is done once every 8 events 0x3 IC1F Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 4 4 read-write B_0x0 No filter, sampling is done at fDTS 0x0 B_0x1 fSAMPLING=fCK_INT, N=2 0x1 B_0x2 fSAMPLING=fCK_INT, N=4 0x2 B_0x3 fSAMPLING=fCK_INT, N=8 0x3 B_0x4 fSAMPLING=fDTS/2, N=6 0x4 B_0x5 fSAMPLING=fDTS/2, N=8 0x5 B_0x6 fSAMPLING=fDTS/4, N=6 0x6 B_0x7 fSAMPLING=fDTS/4, N=8 0x7 B_0x8 fSAMPLING=fDTS/8, N=6 0x8 B_0x9 fSAMPLING=fDTS/8, N=8 0x9 B_0xA fSAMPLING=fDTS/16, N=5 0xA B_0xB fSAMPLING=fDTS/16, N=6 0xB B_0xC fSAMPLING=fDTS/16, N=8 0xC B_0xD fSAMPLING=fDTS/32, N=5 0xD B_0xE fSAMPLING=fDTS/32, N=6 0xE B_0xF fSAMPLING=fDTS/32, N=8 0xF CC2S Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER). 8 2 read-write B_0x0 CC2 channel is configured as output 0x0 B_0x1 CC2 channel is configured as input, IC2 is mapped on TI2 0x1 B_0x2 CC2 channel is configured as input, IC2 is mapped on TI1 0x2 B_0x3 CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 IC2PSC Input capture 2 prescaler 10 2 read-write IC2F Input capture 2 filter 12 4 read-write CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1E Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details. 0 1 read-write B_0x0 Capture mode disabled / OC1 is not active (see below) 0x0 B_0x1 Capture mode enabled / OC1 signal is output on the corresponding output pin 0x1 CC1P Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. 1 1 read-write B_0x0 OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) 0x0 B_0x1 OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) 0x1 CC1NE Capture/Compare 1 complementary output enable 2 1 read-write B_0x0 Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 0x0 B_0x1 On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 0x1 CC1NP Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated. 3 1 read-write B_0x0 OC1N active high 0x0 B_0x1 OC1N active low 0x1 CC2E Capture/Compare 2 output enable Refer to CC1E description 4 1 read-write CC2P Capture/Compare 2 output polarity Refer to CC1P description 5 1 read-write CC2NP Capture/Compare 2 complementary output polarity Refer to CC1NP description 7 1 read-write CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 2 value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 DTG Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 8 read-write LOCK Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 8 2 read-write B_0x0 LOCK OFF - No bit is write protected 0x0 B_0x1 LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written 0x1 B_0x2 LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 0x2 B_0x3 LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. 0x3 OSSI Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write B_0x0 When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) 0x0 B_0x1 When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1) 0x1 OSSR Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write B_0x0 When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state) 0x0 B_0x1 When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). 0x1 BKE Break enable 1; Break inputs (BRK and CCS clock failure event) enabled This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 12 1 read-write B_0x0 Break inputs (BRK and CCS clock failure event) disabled 0x0 BKP Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 13 1 read-write B_0x0 Break input BRK is active low 0x0 B_0x1 Break input BRK is active high 0x1 AOE Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 1 read-write B_0x0 MOE can be set only by software 0x0 B_0x1 MOE can be set by software or automatically at the next update event (if the break input is not be active) 0x1 MOE Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). 15 1 read-write B_0x0 OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. 0x0 B_0x1 OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register) 0x1 BKF Break filter This bit-field defines the frequency used to sample the BRK input signal and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 4 read-write B_0x0 No filter, BRK acts asynchronously 0x0 B_0x1 fSAMPLING=fCK_INT, N=2 0x1 B_0x2 fSAMPLING=fCK_INT, N=4 0x2 B_0x3 fSAMPLING=fCK_INT, N=8 0x3 B_0x4 fSAMPLING=fDTS/2, N=6 0x4 B_0x5 fSAMPLING=fDTS/2, N=8 0x5 B_0x6 fSAMPLING=fDTS/4, N=6 0x6 B_0x7 fSAMPLING=fDTS/4, N=8 0x7 B_0x8 fSAMPLING=fDTS/8, N=6 0x8 B_0x9 fSAMPLING=fDTS/8, N=8 0x9 B_0xA fSAMPLING=fDTS/16, N=5 0xA B_0xB fSAMPLING=fDTS/16, N=6 0xB B_0xC fSAMPLING=fDTS/16, N=8 0xC B_0xD fSAMPLING=fDTS/32, N=5 0xD B_0xE fSAMPLING=fDTS/32, N=6 0xE B_0xF fSAMPLING=fDTS/32, N=8 0xF BKDSRM Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 26 1 read-write B_0x0 Break input BRK is armed 0x0 B_0x1 Break input BRK is disarmed 0x1 BKBID Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 28 1 read-write B_0x0 Break input BRK in input mode 0x0 B_0x1 Break input BRK in bidirectional mode 0x1 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBA DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... 0 5 read-write B_0x0 TIMx_CR1, 0x0 B_0x1 TIMx_CR2, 0x1 B_0x2 TIMx_SMCR, 0x2 DBL DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ... 8 5 read-write B_0x0 1 transfer, 0x0 B_0x1 2 transfers, 0x1 B_0x2 3 transfers, 0x2 B_0x11 18 transfers. 0x11 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 AF1 AF1 TIM15 alternate register 1 0x60 0x20 read-write 0x00000001 BKINE BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write B_0x0 BKIN input disabled 0x0 B_0x1 BKIN input enabled 0x1 BKINP BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write B_0x0 BKIN input is active low 0x0 B_0x1 BKIN input is active high 0x1 TISEL TISEL input selection register 0x68 0x20 read-write 0x0000 TI1SEL selects TI1[0] to TI1[15] input Others: Reserved 0 4 read-write B_0x0 TIM15_CH1 input 0x0 B_0x1 TIM2_IC1 0x1 B_0x2 TIM3_IC1 0x2 TI2SEL selects TI2[0] to TI2[15] input Others: Reserved 8 4 read-write B_0x0 TIM15_CH2 input 0x0 B_0x1 TIM2_IC2 0x1 B_0x2 TIM3_IC2 0x2 TIM16 General purpose timers TIM 0x40014400 0x0 0x400 registers TIM16 TIM16 global interrupt 21 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CEN Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write B_0x0 Counter disabled 0x0 B_0x1 Counter enabled 0x1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write B_0x0 UEV enabled. The Update (UEV) event is generated by one of the following events: 0x0 B_0x1 UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. 0x1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write B_0x0 Any of the following events generate an update interrupt or DMA request if enabled. These events can be: 0x0 B_0x1 Only counter overflow/underflow generates an update interrupt or DMA request if enabled. 0x1 OPM One pulse mode 3 1 read-write B_0x0 Counter is not stopped at update event 0x0 B_0x1 Counter stops counting at the next update event (clearing the bit CEN) 0x1 ARPE Auto-reload preload enable 7 1 read-write B_0x0 TIMx_ARR register is not buffered 0x0 B_0x1 TIMx_ARR register is buffered 0x1 CKD Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx), 8 2 read-write B_0x0 tDTS=tCK_INT 0x0 B_0x1 tDTS=2*tCK_INT 0x1 B_0x2 tDTS=4*tCK_INT 0x2 B_0x3 Reserved, do not program this value 0x3 UIFREMAP UIF status bit remapping 11 1 read-write B_0x0 No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 0x0 B_0x1 Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. 0x1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 CCPC Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 1 read-write B_0x0 CCxE, CCxNE and OCxM bits are not preloaded 0x0 B_0x1 CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. 0x1 CCUS Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 2 1 read-write B_0x0 When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. 0x0 B_0x1 When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. 0x1 CCDS Capture/compare DMA selection 3 1 read-write B_0x0 CCx DMA request sent when CCx event occurs 0x0 B_0x1 CCx DMA requests sent when update event occurs 0x1 OIS1 Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 8 1 read-write B_0x0 OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 0x0 B_0x1 OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 0x1 OIS1N Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write B_0x0 OC1N=0 after a dead-time when MOE=0 0x0 B_0x1 OC1N=1 after a dead-time when MOE=0 0x1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 UIE Update interrupt enable 0 1 read-write B_0x0 Update interrupt disabled 0x0 B_0x1 Update interrupt enabled 0x1 CC1IE Capture/Compare 1 interrupt enable 1 1 read-write B_0x0 CC1 interrupt disabled 0x0 B_0x1 CC1 interrupt enabled 0x1 COMIE COM interrupt enable 5 1 read-write B_0x0 COM interrupt disabled 0x0 B_0x1 COM interrupt enabled 0x1 BIE Break interrupt enable 7 1 read-write B_0x0 Break interrupt disabled 0x0 B_0x1 Break interrupt enabled 0x1 UDE Update DMA request enable 8 1 read-write B_0x0 Update DMA request disabled 0x0 B_0x1 Update DMA request enabled 0x1 CC1DE Capture/Compare 1 DMA request enable 9 1 read-write B_0x0 CC1 DMA request disabled 0x0 B_0x1 CC1 DMA request enabled 0x1 SR SR status register 0x10 0x20 read-write 0x0000 UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write B_0x0 No update occurred. 0x0 B_0x1 Update interrupt pending. This bit is set by hardware when the registers are updated: 0x1 CC1IF Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). 1 1 read-write B_0x0 No compare match / No input capture occurred 0x0 B_0x1 A compare match or an input capture occurred 0x1 COMIF COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software. 5 1 read-write B_0x0 No COM event occurred 0x0 B_0x1 COM interrupt pending 0x1 BIF Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 7 1 read-write B_0x0 No break event occurred 0x0 B_0x1 An active level has been detected on the break input 0x1 CC1OF Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’. 9 1 read-write B_0x0 No overcapture has been detected 0x0 B_0x1 The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set 0x1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only B_0x0 No action. 0x0 B_0x1 Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). 0x1 CC1G Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. 1 1 write-only B_0x0 No action. 0x0 B_0x1 A capture/compare event is generated on channel 1: 0x1 COMG Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output. 5 1 write-only B_0x0 No action 0x0 B_0x1 When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits 0x1 BG Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 7 1 write-only B_0x0 No action. 0x0 B_0x1 A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. 0x1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER). 0 2 read-write B_0x0 CC1 channel is configured as output 0x0 B_0x1 CC1 channel is configured as input, IC1 is mapped on TI1 0x1 OC1FE Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. 2 1 read-write B_0x0 CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 0x0 B_0x1 An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode. 0x1 OC1PE Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. 3 1 read-write B_0x0 Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 0x0 B_0x1 Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. 0x1 OC1M1 Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. The OC1M[3] bit is not contiguous, located in bit 16. 4 3 read-write B_0x0 Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 0x0 B_0x1 Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x1 B_0x2 Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x2 B_0x3 Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0x3 B_0x4 Force inactive level - OC1REF is forced low. 0x4 B_0x5 Force active level - OC1REF is forced high. 0x5 B_0x6 PWM mode 1 - Channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. 0x6 B_0x7 PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. 0x7 OC1M2 Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. The OC1M[3] bit is not contiguous, located in bit 16. 16 1 read-write B_0x0 Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 0x0 B_0x1 Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x1 B_0x2 Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x2 B_0x3 Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0x3 B_0x4 Force inactive level - OC1REF is forced low. 0x4 B_0x5 Force active level - OC1REF is forced high. 0x5 B_0x6 PWM mode 1 - Channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. 0x6 B_0x7 PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. 0x7 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 CC1S Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER). 0 2 read-write B_0x0 CC1 channel is configured as output 0x0 B_0x1 CC1 channel is configured as input, IC1 is mapped on TI1 0x1 IC1PSC Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 2 2 read-write B_0x0 no prescaler, capture is done each time an edge is detected on the capture input. 0x0 B_0x1 capture is done once every 2 events 0x1 B_0x2 capture is done once every 4 events 0x2 B_0x3 capture is done once every 8 events 0x3 IC1F Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 4 4 read-write B_0x0 No filter, sampling is done at fDTS 0x0 B_0x1 fSAMPLING=fCK_INT, N=2 0x1 B_0x2 fSAMPLING=fCK_INT, N=4 0x2 B_0x3 fSAMPLING=fCK_INT, N=8 0x3 B_0x4 fSAMPLING=fDTS/2, N= 0x4 B_0x5 fSAMPLING=fDTS/2, N=8 0x5 B_0x6 fSAMPLING=fDTS/4, N=6 0x6 B_0x7 fSAMPLING=fDTS/4, N=8 0x7 B_0x8 fSAMPLING=fDTS/8, N=6 0x8 B_0x9 fSAMPLING=fDTS/8, N=8 0x9 B_0xA fSAMPLING=fDTS/16, N=5 0xA B_0xB fSAMPLING=fDTS/16, N=6 0xB B_0xC fSAMPLING=fDTS/16, N=8 0xC B_0xD fSAMPLING=fDTS/32, N=5 0xD B_0xE fSAMPLING=fDTS/32, N=6 0xE B_0xF fSAMPLING=fDTS/32, N=8 0xF CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1E Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details. 0 1 read-write B_0x0 Capture mode disabled / OC1 is not active (see below) 0x0 B_0x1 Capture mode enabled / OC1 signal is output on the corresponding output pin 0x1 CC1P Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. 1 1 read-write B_0x0 OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) 0x0 B_0x1 OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) 0x1 CC1NE Capture/Compare 1 complementary output enable 2 1 read-write B_0x0 Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 0x0 B_0x1 On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 0x1 CC1NP Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to the description of CC1P. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated. 3 1 read-write B_0x0 OC1N active high 0x0 B_0x1 OC1N active low 0x1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 DTG Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 8 read-write LOCK Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 8 2 read-write B_0x0 LOCK OFF - No bit is write protected 0x0 B_0x1 LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. 0x1 B_0x2 LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 0x2 B_0x3 LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. 0x3 OSSI Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write B_0x0 When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) 0x0 B_0x1 When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1) 0x1 OSSR Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write B_0x0 When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state) 0x0 B_0x1 When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). 0x1 BKE Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 12 1 read-write B_0x0 Break inputs (BRK and CCS clock failure event) disabled 0x0 BKP Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 13 1 read-write B_0x0 Break input BRK is active low 0x0 B_0x1 Break input BRK is active high 0x1 AOE Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 1 read-write B_0x0 MOE can be set only by software 0x0 B_0x1 MOE can be set by software or automatically at the next update event (if the break input is not be active) 0x1 MOE Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). 15 1 read-write B_0x0 OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. 0x0 B_0x1 OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)See OC/OCN enable description for more details ( 0x1 BKF Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 4 read-write B_0x0 No filter, BRK acts asynchronously 0x0 B_0x1 fSAMPLING=fCK_INT, N=2 0x1 B_0x2 fSAMPLING=fCK_INT, N=4 0x2 B_0x3 fSAMPLING=fCK_INT, N=8 0x3 B_0x4 fSAMPLING=fDTS/2, N=6 0x4 B_0x5 fSAMPLING=fDTS/2, N=8 0x5 B_0x6 fSAMPLING=fDTS/4, N=6 0x6 B_0x7 fSAMPLING=fDTS/4, N=8 0x7 B_0x8 fSAMPLING=fDTS/8, N=6 0x8 B_0x9 fSAMPLING=fDTS/8, N=8 0x9 B_0xA fSAMPLING=fDTS/16, N=5 0xA B_0xB fSAMPLING=fDTS/16, N=6 0xB B_0xC fSAMPLING=fDTS/16, N=8 0xC B_0xD fSAMPLING=fDTS/32, N=5 0xD B_0xE fSAMPLING=fDTS/32, N=6 0xE B_0xF fSAMPLING=fDTS/32, N=8 0xF BKDSRM Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 26 1 read-write B_0x0 Break input BRK is armed 0x0 B_0x1 Break input BRK is disarmed 0x1 BKBID Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 28 1 read-write B_0x0 Break input BRK in input mode 0x0 B_0x1 Break input BRK in bidirectional mode 0x1 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBA DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 0 5 read-write B_0x0 TIMx_CR1, 0x0 B_0x1 TIMx_CR2, 0x1 B_0x2 TIMx_SMCR, 0x2 DBL DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... 8 5 read-write B_0x0 1 transfer, 0x0 B_0x1 2 transfers, 0x1 B_0x2 3 transfers, 0x2 B_0x11 18 transfers. 0x11 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 AF1 AF1 TIM17 option register 1 0x60 0x20 read-write 0x00000001 BKINE BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write B_0x0 BKIN input disabled 0x0 B_0x1 BKIN input enabled 0x1 BKINP BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write B_0x0 BKIN input is active low 0x0 B_0x1 BKIN input is active high 0x1 TISEL TISEL input selection register 0x68 0x20 read-write 0x0000 TI1SEL selects TI1[0] to TI1[15] input Others: Reserved 0 4 read-write B_0x0 TIM16_CH1 input 0x0 B_0x1 LSI 0x1 B_0x2 LSE 0x2 B_0x3 RTC wakeup 0x3 TIM17 0x40014800 TIM17 TIM17 global interrupt 22 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 27 CR1_FIFO_ENABLED CR1_FIFO_ENABLED Control register 1 0x0 0x20 read-write 0x0000 UE USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value. 0 1 read-write B_0x0 USART prescaler and outputs disabled, low-power mode 0x0 B_0x1 USART enabled 0x1 UESM USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to . 1 1 read-write B_0x0 USART not able to wake up the MCU from low-power mode. 0x0 B_0x1 USART able to wake up the MCU from low-power mode. 0x1 RE Receiver enable This bit enables the receiver. It is set and cleared by software. 2 1 read-write B_0x0 Receiver is disabled 0x0 B_0x1 Receiver is enabled and begins searching for a start bit 0x1 TE Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. 3 1 read-write B_0x0 Transmitter is disabled 0x0 B_0x1 Transmitter is enabled 0x1 IDLEIE IDLE interrupt enable This bit is set and cleared by software. 4 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated whenever IDLE = 1 in the USART_ISR register 0x1 RXFNEIE RXFIFO not empty interrupt enable This bit is set and cleared by software. 5 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated whenever ORE = 1 or RXFNE = 1 in the USART_ISR register 0x1 TCIE Transmission complete interrupt enable This bit is set and cleared by software. 6 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated whenever TC = 1 in the USART_ISR register 0x1 TXFNFIE TXFIFO not full interrupt enable This bit is set and cleared by software. 7 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated whenever TXFNF =1 in the USART_ISR register 0x1 PEIE PE interrupt enable This bit is set and cleared by software. 8 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated whenever PE = 1 in the USART_ISR register 0x1 PS Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0). 9 1 read-write B_0x0 Even parity 0x0 B_0x1 Odd parity 0x1 PCE Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0). 10 1 read-write B_0x0 Parity control disabled 0x0 B_0x1 Parity control enabled 0x1 WAKE Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). 11 1 read-write B_0x0 Idle line 0x0 B_0x1 Address mark 0x1 M0 Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0). 12 1 read-write MME Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. 13 1 read-write B_0x0 Receiver in active mode permanently 0x0 B_0x1 Receiver can switch between Mute mode and active mode. 0x1 CMIE Character match interrupt enable This bit is set and cleared by software. 14 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated when the CMF bit is set in the USART_ISR register. 0x1 OVER8 Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. 15 1 read-write B_0x0 Oversampling by 16 0x0 B_0x1 Oversampling by 8 0x1 DEDT Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 16 5 read-write DEAT Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 21 5 read-write RTOIE Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. . 26 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated when the RTOF bit is set in the USART_ISR register. 0x1 EOBIE End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to . 27 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated when the EOBF flag is set in the USART_ISR register 0x1 M1 Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported. 28 1 read-write FIFOEN FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. 29 1 read-write B_0x0 FIFO mode is disabled. 0x0 B_0x1 FIFO mode is enabled. 0x1 TXFEIE TXFIFO empty interrupt enable This bit is set and cleared by software. 30 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated when TXFE = 1 in the USART_ISR register 0x1 RXFFIE RXFIFO Full interrupt enable This bit is set and cleared by software. 31 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated when RXFF = 1 in the USART_ISR register 0x1 CR1_FIFO_DISABLED CR1_FIFO_DISABLED Control register 1 CR1_FIFO_ENABLED 0x0 0x20 read-write 0x0000 UE USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value. 0 1 read-write B_0x0 USART prescaler and outputs disabled, low-power mode 0x0 B_0x1 USART enabled 0x1 UESM USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to . 1 1 read-write B_0x0 USART not able to wake up the MCU from low-power mode. 0x0 B_0x1 USART able to wake up the MCU from low-power mode. 0x1 RE Receiver enable This bit enables the receiver. It is set and cleared by software. 2 1 read-write B_0x0 Receiver is disabled 0x0 B_0x1 Receiver is enabled and begins searching for a start bit 0x1 TE Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. 3 1 read-write B_0x0 Transmitter is disabled 0x0 B_0x1 Transmitter is enabled 0x1 IDLEIE IDLE interrupt enable This bit is set and cleared by software. 4 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated whenever IDLE = 1 in the USART_ISR register 0x1 RXNEIE Receive data register not empty This bit is set and cleared by software. 5 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated whenever ORE = 1 or RXNE = 1 in the USART_ISR register 0x1 TCIE Transmission complete interrupt enable This bit is set and cleared by software. 6 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated whenever TC = 1 in the USART_ISR register 0x1 TXEIE Transmit data register empty This bit is set and cleared by software. 7 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated whenever TXE =1 in the USART_ISR register 0x1 PEIE PE interrupt enable This bit is set and cleared by software. 8 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated whenever PE = 1 in the USART_ISR register 0x1 PS Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0). 9 1 read-write B_0x0 Even parity 0x0 B_0x1 Odd parity 0x1 PCE Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0). 10 1 read-write B_0x0 Parity control disabled 0x0 B_0x1 Parity control enabled 0x1 WAKE Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). 11 1 read-write B_0x0 Idle line 0x0 B_0x1 Address mark 0x1 M0 Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0). 12 1 read-write MME Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. 13 1 read-write B_0x0 Receiver in active mode permanently 0x0 B_0x1 Receiver can switch between Mute mode and active mode. 0x1 CMIE Character match interrupt enable This bit is set and cleared by software. 14 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated when the CMF bit is set in the USART_ISR register. 0x1 OVER8 Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. 15 1 read-write B_0x0 Oversampling by 16 0x0 B_0x1 Oversampling by 8 0x1 DEDT Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 16 5 read-write DEAT Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 21 5 read-write RTOIE Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. . 26 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated when the RTOF bit is set in the USART_ISR register. 0x1 EOBIE End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to . 27 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated when the EOBF flag is set in the USART_ISR register 0x1 M1 Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported. 28 1 read-write FIFOEN FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. 29 1 read-write B_0x0 FIFO mode is disabled. 0x0 B_0x1 FIFO mode is enabled. 0x1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x0000 SLVEN Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 0 1 read-write B_0x0 Slave mode disabled. 0x0 B_0x1 Slave mode enabled. 0x1 DIS_NSS When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 3 1 read-write B_0x0 SPI slave selection depends on NSS input pin. 0x0 B_0x1 SPI slave is always selected and NSS input pin is ignored. 0x1 ADDM7 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. 4 1 read-write B_0x0 4-bit address detection 0x0 B_0x1 7-bit address detection (in 8-bit data mode) 0x1 LBDL LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 5 1 read-write B_0x0 10-bit break detection 0x0 B_0x1 11-bit break detection 0x1 LBDIE LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 6 1 read-write B_0x0 Interrupt is inhibited 0x0 B_0x1 An interrupt is generated whenever LBDF = 1 in the USART_ISR register 0x1 LBCL Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 8 1 read-write B_0x0 The clock pulse of the last data bit is not output to the SCLK pin 0x0 B_0x1 The clock pulse of the last data bit is output to the SCLK pin 0x1 CPHA Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 9 1 read-write B_0x0 The first clock transition is the first data capture edge 0x0 B_0x1 The second clock transition is the first data capture edge 0x1 CPOL Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 10 1 read-write B_0x0 Steady low value on SCLK pin outside transmission window 0x0 B_0x1 Steady high value on SCLK pin outside transmission window 0x1 CLKEN Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1 11 1 read-write B_0x0 SCLK pin disabled 0x0 B_0x1 SCLK pin enabled 0x1 STOP stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0). 12 2 read-write B_0x0 1 stop bit 0x0 B_0x1 0.5 stop bit. 0x1 B_0x2 2 stop bits 0x2 B_0x3 1.5 stop bits 0x3 LINEN LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to . 14 1 read-write B_0x0 LIN mode disabled 0x0 B_0x1 LIN mode enabled 0x1 SWAP Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). 15 1 read-write B_0x0 TX/RX pins are used as defined in standard pinout 0x0 B_0x1 The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART. 0x1 RXINV RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0). 16 1 read-write B_0x0 RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark) 0x0 B_0x1 RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle). 0x1 TXINV TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0). 17 1 read-write B_0x0 TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark) 0x0 B_0x1 TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle). 0x1 DATAINV Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). 18 1 read-write B_0x0 Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L) 0x0 B_0x1 Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted. 0x1 MSBFIRST Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). 19 1 read-write B_0x0 data is transmitted/received with data bit 0 first, following the start bit. 0x0 B_0x1 data is transmitted/received with the MSB (bit 7/8) first, following the start bit. 0x1 ABREN Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to . 20 1 read-write B_0x0 Auto baud rate detection is disabled. 0x0 B_0x1 Auto baud rate detection is enabled. 0x1 ABRMOD Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to . 21 2 read-write B_0x0 Measurement of the start bit is used to detect the baud rate. 0x0 B_0x1 Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx) 0x1 B_0x2 0x7F frame detection. 0x2 B_0x3 0x55 frame detection 0x3 RTOEN Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to . 23 1 read-write B_0x0 Receiver timeout feature disabled. 0x0 B_0x1 Receiver timeout feature enabled. 0x1 ADD Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UE = 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UE = 0). 24 8 read-write CR3 CR3 Control register 3 0x8 0x20 read-write 0x0000 EIE Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register). 0 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register. 0x1 IREN IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 1 1 read-write B_0x0 IrDA disabled 0x0 B_0x1 IrDA enabled 0x1 IRLP IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 2 1 read-write B_0x0 Normal mode 0x0 B_0x1 Low-power mode 0x1 HDSEL Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0). 3 1 read-write B_0x0 Half duplex mode is not selected 0x0 B_0x1 Half duplex mode is selected 0x1 NACK Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to . 4 1 read-write B_0x0 NACK transmission in case of parity error is disabled 0x0 B_0x1 NACK transmission during parity error is enabled 0x1 SCEN Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to . 5 1 read-write B_0x0 Smartcard Mode disabled 0x0 B_0x1 Smartcard Mode enabled 0x1 DMAR DMA enable receiver This bit is set/reset by software 6 1 read-write B_0x1 DMA mode is enabled for reception 0x1 B_0x0 DMA mode is disabled for reception 0x0 DMAT DMA enable transmitter This bit is set/reset by software 7 1 read-write B_0x1 DMA mode is enabled for transmission 0x1 B_0x0 DMA mode is disabled for transmission 0x0 RTSE RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 8 1 read-write B_0x0 RTS hardware flow control disabled 0x0 B_0x1 RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received. 0x1 CTSE CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 9 1 read-write B_0x0 CTS hardware flow control disabled 0x0 B_0x1 CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted. 0x1 CTSIE CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 10 1 read-write B_0x0 Interrupt is inhibited 0x0 B_0x1 An interrupt is generated whenever CTSIF = 1 in the USART_ISR register 0x1 ONEBIT One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0). 11 1 read-write B_0x0 Three sample bit method 0x0 B_0x1 One sample bit method 0x1 OVRDIS Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data 12 1 read-write B_0x0 Overrun Error Flag, ORE, is set when received data is not read before receiving new data. 0x0 B_0x1 Overrun functionality is disabled. If new data is received while the RXNE flag is still set 0x1 DDRE DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error. 13 1 read-write B_0x0 DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode). 0x0 B_0x1 DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag. 0x1 DEM Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. . 14 1 read-write B_0x0 DE function is disabled. 0x0 B_0x1 DE function is enabled. The DE signal is output on the RTS pin. 0x1 DEP Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 15 1 read-write B_0x0 DE signal is active high. 0x0 B_0x1 DE signal is active low. 0x1 SCARCNT Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 17 3 read-write B_0x0 retransmission disabled - No automatic retransmission in transmit mode. 0x0 B_0x1 number of automatic retransmission attempts (before signaling error) 0x1 B_0x2 number of automatic retransmission attempts (before signaling error) 0x2 B_0x3 number of automatic retransmission attempts (before signaling error) 0x3 B_0x4 number of automatic retransmission attempts (before signaling error) 0x4 B_0x5 number of automatic retransmission attempts (before signaling error) 0x5 B_0x6 number of automatic retransmission attempts (before signaling error) 0x6 B_0x7 number of automatic retransmission attempts (before signaling error) 0x7 WUS Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835. 20 2 read-write B_0x0 WUF active on address match (as defined by ADD[7:0] and ADDM7) 0x0 B_0x2 WUF active on start bit detection 0x2 B_0x3 WUF active on RXNE/RXFNE. 0x3 WUFIE Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835. 22 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated whenever WUF = 1 in the USART_ISR register 0x1 TXFTIE TXFIFO threshold interrupt enable This bit is set and cleared by software. 23 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG. 0x1 TCBGTIE Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to . 24 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated whenever TCBGT=1 in the USART_ISR register 0x1 RXFTCFG Receive FIFO threshold configuration Remaining combinations: Reserved 25 3 read-write B_0x0 Receive FIFO reaches 1/8 of its depth 0x0 B_0x1 Receive FIFO reaches 1/4 of its depth 0x1 B_0x2 Receive FIFO reaches 1/2 of its depth 0x2 B_0x3 Receive FIFO reaches 3/4 of its depth 0x3 B_0x4 Receive FIFO reaches 7/8 of its depth 0x4 B_0x5 Receive FIFO becomes full 0x5 RXFTIE RXFIFO threshold interrupt enable This bit is set and cleared by software. 28 1 read-write B_0x0 Interrupt inhibited 0x0 B_0x1 USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG. 0x1 TXFTCFG TXFIFO threshold configuration Remaining combinations: Reserved 29 3 read-write B_0x0 TXFIFO reaches 1/8 of its depth 0x0 B_0x1 TXFIFO reaches 1/4 of its depth 0x1 B_0x2 TXFIFO reaches 1/2 of its depth 0x2 B_0x3 TXFIFO reaches 3/4 of its depth 0x3 B_0x4 TXFIFO reaches 7/8 of its depth 0x4 B_0x5 TXFIFO becomes empty 0x5 BRR BRR Baud rate register 0xC 0x20 read-write 0x0000 BRR USART baud rate 0 16 read-write GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x0000 PSC Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010 0000: Divides the source clock by 32 (IrDA mode) ... 1111 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0’ when the Smartcard and IrDA modes are not supported. Refer to . 0 8 read-write B_0x0 Reserved - do not program this value 0x0 B_0x1 Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode) 0x1 B_0x2 Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode) 0x2 B_0x3 Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode) 0x3 B_0x1F Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode) 0x1F GT Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 8 8 read-write RTOR RTOR Receiver timeout register 0x14 0x20 read-write 0x0000 RTO Receiver timeout value 0 24 BLEN Block Length 24 8 RQR RQR Request register 0x18 0x20 write-only 0x0000 ABRRQ Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to . 0 1 write-only SBKRQ Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. 1 1 write-only MMRQ Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag. 2 1 write-only RXFRQ Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition. 3 1 write-only TXFRQ Transmit data flush request When FIFO mode is disabled, writing '1’ to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. 4 1 write-only ISR_FIFO_ENABLED ISR_FIFO_ENABLED Interrupt & status register 0x1C 0x20 read-only 0x008000C0 PE Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR. 0 1 read-only B_0x0 No parity error 0x0 B_0x1 Parity error 0x1 FE Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR. 1 1 read-only B_0x0 No Framing error is detected 0x0 B_0x1 Framing error or break character is detected 0x1 NE Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR. 2 1 read-only B_0x0 No noise is detected 0x0 B_0x1 Noise is detected 0x1 ORE Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE = 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. 3 1 read-only B_0x0 No overrun error 0x0 B_0x1 Overrun error is detected 0x1 IDLE Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set. 4 1 read-only B_0x0 No Idle line is detected 0x0 B_0x1 Idle line is detected 0x1 RXFNE RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register. 5 1 read-only B_0x0 Data is not received 0x0 B_0x1 Received data is ready to be read. 0x1 TC Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set. 6 1 read-only B_0x0 Transmission is not complete 0x0 B_0x1 Transmission is complete 0x1 TXFNF TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission. 7 1 read-only B_0x0 Transmit FIFO is full 0x0 B_0x1 Transmit FIFO is not full 0x1 LBDF LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to . 8 1 read-only B_0x0 LIN Break not detected 0x0 B_0x1 LIN break detected 0x1 CTSIF CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 9 1 read-only B_0x0 No change occurred on the nCTS status line 0x0 B_0x1 A change occurred on the nCTS status line 0x1 CTS CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 10 1 read-only B_0x0 nCTS line set 0x0 B_0x1 nCTS line reset 0x1 RTOF Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. 11 1 read-only B_0x0 Timeout value not reached 0x0 B_0x1 Timeout value reached without any data reception 0x1 EOBF End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to . 12 1 read-only B_0x0 End of Block not reached 0x0 B_0x1 End of Block (number of characters) reached 0x1 UDR SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to . 13 1 read-only B_0x0 No underrun error 0x0 B_0x1 underrun error 0x1 ABRE Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. 14 1 read-only ABRF Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. 15 1 read-only BUSY Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). 16 1 read-only B_0x0 USART is idle (no reception) 0x0 B_0x1 Reception on going 0x1 CMF Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register. 17 1 read-only B_0x0 No Character match detected 0x0 B_0x1 Character Match detected 0x1 SBKF Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. 18 1 read-only B_0x0 Break character transmitted 0x0 B_0x1 Break character requested by setting SBKRQ bit in USART_RQR register 0x1 RWU Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to . 19 1 read-only B_0x0 Receiver in active mode 0x0 B_0x1 Receiver in Mute mode 0x1 WUF Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to . 20 1 read-only TEACK Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period. 21 1 read-only REACK Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to . 22 1 read-only TXFE TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register. 23 1 read-only B_0x0 TXFIFO not empty. 0x0 B_0x1 TXFIFO empty. 0x1 RXFF RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register. 24 1 read-only B_0x0 RXFIFO not full. 0x0 B_0x1 RXFIFO Full. 0x1 TCBGT Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835. 25 1 read-only B_0x0 Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) 0x0 B_0x1 Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). 0x1 RXFT RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101’, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data. 26 1 read-only B_0x0 Receive FIFO does not reach the programmed threshold. 0x0 B_0x1 Receive FIFO reached the programmed threshold. 0x1 TXFT TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register. 27 1 read-only B_0x0 TXFIFO does not reach the programmed threshold. 0x0 B_0x1 TXFIFO reached the programmed threshold. 0x1 ISR_FIFO_DISABLED ISR_FIFO_DISABLED Interrupt & status register ISR_FIFO_ENABLED 0x1C 0x20 read-only 0x000000C0 PE Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. 0 1 read-only B_0x0 No parity error 0x0 B_0x1 Parity error 0x1 FE Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. 1 1 read-only B_0x0 No Framing error is detected 0x0 B_0x1 Framing error or break character is detected 0x1 NE Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). 2 1 read-only B_0x0 No noise is detected 0x0 B_0x1 Noise is detected 0x1 ORE Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNE = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIE = 1 or EIE  =  1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. 3 1 read-only B_0x0 No overrun error 0x0 B_0x1 Overrun error is detected 0x1 IDLE Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set. 4 1 read-only B_0x0 No Idle line is detected 0x0 B_0x1 Idle line is detected 0x1 RXNE Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE = 1 in the USART_CR1 register. 5 1 read-only B_0x0 Data is not received 0x0 B_0x1 Received data is ready to be read. 0x1 TC Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately. 6 1 read-only B_0x0 Transmission is not complete 0x0 B_0x1 Transmission is complete 0x1 TXE Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register. 7 1 read-only B_0x0 Data register full 0x0 B_0x1 Data register not full 0x1 LBDF LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to . 8 1 read-only B_0x0 LIN Break not detected 0x0 B_0x1 LIN break detected 0x1 CTSIF CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 9 1 read-only B_0x0 No change occurred on the nCTS status line 0x0 B_0x1 A change occurred on the nCTS status line 0x1 CTS CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 10 1 read-only B_0x0 nCTS line set 0x0 B_0x1 nCTS line reset 0x1 RTOF Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. 11 1 read-only B_0x0 Timeout value not reached 0x0 B_0x1 Timeout value reached without any data reception 0x1 EOBF End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to . 12 1 read-only B_0x0 End of Block not reached 0x0 B_0x1 End of Block (number of characters) reached 0x1 UDR SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to . 13 1 read-only B_0x0 No underrun error 0x0 B_0x1 underrun error 0x1 ABRE Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. 14 1 read-only ABRF Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. 15 1 read-only BUSY Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). 16 1 read-only B_0x0 USART is idle (no reception) 0x0 B_0x1 Reception on going 0x1 CMF Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register. 17 1 read-only B_0x0 No Character match detected 0x0 B_0x1 Character Match detected 0x1 SBKF Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. 18 1 read-only B_0x0 Break character transmitted 0x0 B_0x1 Break character requested by setting SBKRQ bit in USART_RQR register 0x1 RWU Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to . 19 1 read-only B_0x0 Receiver in active mode 0x0 B_0x1 Receiver in Mute mode 0x1 WUF Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to . 20 1 read-only TEACK Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period. 21 1 read-only REACK Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to . 22 1 read-only TCBGT Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835. 25 1 read-only B_0x0 Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) 0x0 B_0x1 Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). 0x1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x0000 PECF Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register. 0 1 write-only FECF Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register. 1 1 write-only NECF Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register. 2 1 write-only ORECF Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register. 3 1 write-only IDLECF Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register. 4 1 write-only TXFECF TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register. 5 1 write-only TCCF Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register. 6 1 write-only TCBGTCF Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. 7 1 write-only LBDCF LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 8 1 write-only CTSCF CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 9 1 write-only RTOCF Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835. 11 1 write-only EOBCF End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to . 12 1 write-only UDRCF SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to 13 1 write-only CMCF Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register. 17 1 write-only WUCF Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835. 20 1 write-only RDR RDR Receive data register 0x24 0x20 read-only 0x0000 RDR Receive data value 0 9 TDR TDR Transmit data register 0x28 0x20 read-write 0x0000 TDR Transmit data value 0 9 PRESC PRESC Prescaler register 0x2C 0x20 read-write 0x0000 PRESCALER Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256. 0 4 read-write B_0x0 input clock not divided 0x0 B_0x1 input clock divided by 2 0x1 B_0x2 input clock divided by 4 0x2 B_0x3 input clock divided by 6 0x3 B_0x4 input clock divided by 8 0x4 B_0x5 input clock divided by 10 0x5 B_0x6 input clock divided by 12 0x6 B_0x7 input clock divided by 16 0x7 B_0x8 input clock divided by 32 0x8 B_0x9 input clock divided by 64 0x9 B_0xA input clock divided by 128 0xA B_0xB input clock divided by 256 0xB USART2 0x40004400 USART2 USART2 global interrupt 28 WWDG System window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window watchdog interrupt 0 WWDG_CR WWDG_CR Control register 0x0 0x20 read-write 0x0000007F T 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared). 0 7 read-write WDGA Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 7 1 read-write B_0x0 Watchdog disabled 0x0 B_0x1 Watchdog enabled 0x1 WWDG_CFR WWDG_CFR Configuration register 0x4 0x20 read-write 0x0000007F W 7-bit window value These bits contain the window value to be compared with the down-counter. 0 7 read-write EWI Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset. 9 1 read-write WDGTB Timer base The timebase of the prescaler can be modified as follows: 11 3 read-write B_0x0 CK Counter Clock (PCLK div 4096) div 1 0x0 B_0x1 CK Counter Clock (PCLK div 4096) div 2 0x1 B_0x2 CK Counter Clock (PCLK div 4096) div 4 0x2 B_0x3 CK Counter Clock (PCLK div 4096) div 8 0x3 B_0x4 CK Counter Clock (PCLK div 4096) div 16 0x4 B_0x5 CK Counter Clock (PCLK div 4096) div 32 0x5 B_0x6 CK Counter Clock (PCLK div 4096) div 64 0x6 B_0x7 CK Counter Clock (PCLK div 4096) div 128 0x7 WWDG_SR WWDG_SR Status register 0x8 0x20 read-write 0x00000000 EWIF Early wakeup interrupt flag 0 1