Renesas Electronics Corporation Renesas R7FA6T2BD RA6 1.30.01 Arm Cortex-M33 based Microcontroller RA6T2 group This software is supplied by Renesas Electronics Corporation and is only intended for \n use with Renesas products. No other uses are authorized. This software is owned by \n Renesas Electronics Corporation and is protected under all applicable laws, including \n copyright laws. \n \n THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING \n THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO \n WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. \n ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. 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By using this software, you agree to \n the additional terms and conditions found by accessing the following link: \n http://www.renesas.com/disclaimer \n \n CM33 r0p4 little true true true 4 false 96 system_RA6 8 32 32 read-write 0 0xffffffff RMPU Renesas Memory Protection Unit 0x40000000 0x00 2 registers 0x04 2 registers 0x100 2 registers 0x104 2 registers 0x108 2 registers 0x10C 2 registers 0x200 136 registers MMPUOAD MMPU Operation After Detection Register 0x0000 16 read-write 0x0000 0xffff OAD Operation after detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 KEY This bit enables or disables writes to the OAD bit. 8 15 write-only MMPUOADPT MMPU Operation After Detection Protect Register 0x0004 16 read-write 0x0000 0xffff PROTECT Protection of register 0 0 read-write 0 MMPUOAD register writes are possible. #0 1 MMPUOAD register writes are protected. Read is possible. #1 KEY Key code 8 15 write-only MMPUENDMAC MMPU Enable Register for DMAC 0x0100 16 read-write 0x0000 0xffff ENABLE Bus Master MPU of DMAC enable 0 0 read-write 0 Bus Master MPU of DMAC is disabled. #0 1 Bus Master MPU of DMAC is enabled. #1 KEY These bits enable or disable writes to the ENABLE bit. 8 15 write-only MMPUENPTDMAC MMPU Enable Protect Register for DMAC 0x0104 16 read-write 0x0000 0xffff PROTECT Protection of register 0 0 read-write 0 MMPUENDMAC register writes are possible. #0 1 MMPUENDMAC register writes are protected. Read is possible. #1 KEY These bits enable or disable writes to the PROTECT bit. 8 15 write-only MMPURPTDMAC MMPU Regions Protect Register for DMAC 0x0108 16 read-write 0x0000 0xffff PROTECT Protection of register 0 0 read-write 0 Bus Master MPU register for DMAC writing is possible. #0 1 Bus Master MPU register for DMAC writing is protected. Read is possible. #1 KEY These bits enable or disable writes to the PROTECT bit. 8 15 write-only MMPURPTDMAC_SEC MMPU Regions Protect register for DMAC Secure 0x010C 16 read-write 0x0000 0xffff PROTECT Protection of register 0 0 read-write 0 Bus master MPU register for DMAC secure writes are possible. #0 1 Bus master MPU register for DMAC secure writes are protected. Read is possible. #1 KEY These bits enable or disable writes to the PROTECT bit. 8 15 write-only 8 0x010 0-7 MMPUACDMAC%s MMPU Access Control Register for DMAC 0x0200 16 read-write 0x0000 0xffff ENABLE Region enable 0 0 read-write 0 DMAC Region n unit is disabled #0 1 DMAC Region n unit is enabled #1 RP Read protection 1 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 2 read-write 0 Write permission #0 1 Write protection #1 8 0x010 0-7 MMPUSDMAC%s MMPU Start Address Register for DMAC 0x0204 32 read-write 0x00000000 0x0000001f MMPUS Region start address register 5 31 read-write 8 0x010 0-7 MMPUEDMAC%s MMPU End Address Register for DMAC 0x0208 32 read-write 0x0000001f 0x0000001f MMPUE Region end address register 5 31 read-write TZF TrustZone Filter 0x40000E00 0x00 2 registers 0x04 2 registers TZFOAD TrustZone Filter Operation After Detection Register 0x00 16 read-write 0x0000 0xffff OAD Operation after detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 KEY KeyCode 8 15 write-only TZFPT TrustZone Filter Protect Register 0x04 16 read-write 0x0000 0xffff PROTECT Protection of register 0 0 read-write 0 All Bus TrustZone Filter register writing is protected. Read is possible. #0 1 All Bus TrustZone Filter register writing is possible. #1 KEY KeyCode 8 15 write-only SRAM SRAM Control 0x40002000 0x00 1 registers 0x04 1 registers 0xC0 5 registers 0xD0 1 registers 0xD4 1 registers 0xD8 1 registers PARIOAD SRAM Parity Error Operation After Detection Register 0x00 8 read-write 0x00 0xff OAD Operation After Detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 SRAMPRCR SRAM Protection Register 0x04 8 read-write 0x00 0xff SRAMPRCR Register Write Control 0 0 read-write 0 Disable writes to protected registers #0 1 Enable writes to protected registers #1 KW Write Key Code 1 7 write-only ECCMODE ECC Operating Mode Control Register 0xC0 8 read-write 0x00 0xff ECCMOD ECC Operating Mode Select 0 1 read-write 00 Disable ECC function #00 01 Setting prohibited #01 10 Enable ECC function without error checking #10 11 Enable ECC function with error checking #11 ECC2STS ECC 2-Bit Error Status Register 0xC1 8 read-write 0x00 0xff ECC2ERR ECC 2-Bit Error Status 0 0 read-write 0 No 2-bit ECC error occurred #0 1 2-bit ECC error occurred #1 ECC1STSEN ECC 1-Bit Error Information Update Enable Register 0xC2 8 read-write 0x00 0xff E1STSEN ECC 1-Bit Error Information Update Enable 0 0 read-write 0 Disable updating of 1-bit ECC error information #0 1 Enable updating of 1-bit ECC error information #1 ECC1STS ECC 1-Bit Error Status Register 0xC3 8 read-write 0x00 0xff ECC1ERR ECC 1-Bit Error Status 0 0 read-write 0 No 1-bit ECC error occurred #0 1 1-bit ECC error occurred #1 ECCPRCR ECC Protection Register 0xC4 8 read-write 0x00 0xff ECCPRCR Register Write Control 0 0 read-write 0 Disable writes to the protected registers #0 1 Enable writes to the protected registers #1 KW Write Key Code 1 7 write-only 0x78 Enable write to the ECCPRCR bit 0x78 Others Disable write to the ECCPRCR bit true ECCPRCR2 ECC Protection Register 2 0xD0 8 read-write 0x00 0xff ECCPRCR2 Register Write Control 0 0 read-write 0 Disable writes to the protected registers #0 1 Enable writes to the protected registers #1 KW2 Write Key Code 1 7 write-only 0x78 Enable write to the ECCPRCR2 bit 0x78 Others Disable write to the ECCPRCR2 bit true ECCETST ECC Test Control Register 0xD4 8 read-write 0x00 0xff TSTBYP ECC Bypass Select 0 0 read-write 0 Disable ECC bypass #0 1 Enable ECC bypass #1 ECCOAD SRAM ECC Error Operation After Detection Register 0xD8 8 read-write 0x00 0xff OAD Operation After Detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 BUS BUS Control 0x40003000 0x1100 2 registers 0x1104 2 registers 0x1110 2 registers 0x1120 2 registers 0x1130 2 registers 0x1134 2 registers 0x1800 52 registers 0x1900 52 registers 0x1A00 56 registers BUSSCNTFHBIU Slave Bus Control Register 0x1100 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 1 read-write 00 DMAC/DTC > CPU #00 01 DMAC/DTC ↔ CPU #01 10 Setting prohibited #10 11 Setting prohibited #11 BUSSCNTFLBIU Slave Bus Control Register 0x1104 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 1 read-write 00 DMAC/DTC > CPU #00 01 DMAC/DTC ↔ CPU #01 10 Setting prohibited #10 11 Setting prohibited #11 BUSSCNTS0BIU Slave Bus Control Register 0x1110 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 1 read-write 00 DMAC/DTC > CPU #00 01 DMAC/DTC ↔ CPU #01 10 Setting prohibited #10 11 Setting prohibited #11 BUSSCNTPSBIU Slave Bus Control Register 0x1120 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 0 read-write 0 DMAC/DTC > CPU #0 1 DMAC/DTC ↔ CPU #1 BUSSCNTPLBIU Slave Bus Control Register 0x1130 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 0 read-write 0 DMAC/DTC > CPU #0 1 DMAC/DTC ↔ CPU #1 BUSSCNTPHBIU Slave Bus Control Register 0x1134 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 0 read-write 0 DMAC/DTC > CPU #0 1 DMAC/DTC ↔ CPU #1 3 0x10 1-3 BUS%sERRADD BUS Error Address Register 0x1800 32 read-only 0x00000000 0xffffffff BERAD Bus Error Address 0 31 read-only 3 0x10 1-3 BUS%sERRRW BUS Error Read Write Register 0x1804 8 read-write 0x00 0xff RWSTAT Error Access Read/Write Status 0 0 read-only 0 Read access #0 1 Write access #1 3 0x10 1-3 BTZF%sERRADD BUS TZF Error Address Register 0x1900 32 read-only 0x00000000 0xffffffff BTZFERAD Bus TrustZone Filter Error Address 0 31 read-only 3 0x10 1-3 BTZF%sERRRW BUS TZF Error Read Write Register 0x1904 8 read-write 0x00 0xff TRWSTAT TrustZone filter error access Read/Write Status 0 0 read-only 0 Read access #0 1 Write access #1 3 0x10 1-3 BUS%sERRSTAT BUS Error Status Register %s 0x1A00 8 read-only 0x00 0xff SLERRSTAT Slave bus Error Status 0 0 read-only 0 No error occurred #0 1 Error occurred #1 STERRSTAT Slave TrustZone filter Error Status 1 1 read-only 0 No error occurred #0 1 Error occurred #1 MMERRSTAT Master MPU Error Status 3 3 read-only 0 No error occurred #0 1 Error occurred #1 ILERRSTAT Illegal address access Error Status 4 4 read-only 0 No error occurred #0 1 Error occurred #1 3 0x10 1-3 BUS%sERRCLR BUS Error Clear Register %s 0x1A08 8 read-write 0x00 0xff SLERRCLR Slave bus Error Clear 0 0 read-write STERRCLR Slave TrustZone filter Error Clear 1 1 read-write MMERRCLR Master MPU Error Clear 3 3 read-write ILERRCLR Illegal Address Access Error Clear 4 4 read-write DMACDTCERRSTAT DMAC/DTC Error Status Register 0x1A24 8 read-only 0x00 0xff MTERRSTAT Master TrustZone Filter Error Status 0 0 read-only 0 No error occurred #0 1 Error occurred #1 DMACDTCERRCLR DMAC/DTC Error Clear Register 0x1A2C 8 read-write 0x00 0xff MTERRCLR Master TrustZone filter Error Clear 0 0 read-write DMAC0 Direct memory access controller 0 0x40005000 0x00 18 registers 0x13 3 registers 0x18 7 registers 0x20 16 registers DMSAR DMA Source Address Register 0x00 32 read-write 0x00000000 0xffffffff DMDAR DMA Destination Address Register 0x04 32 read-write 0x00000000 0xffffffff DMCRA DMA Transfer Count Register 0x08 32 read-write 0x00000000 0xffffffff DMCRAL Lower bits of transfer count 0 15 read-write DMCRAH Upper bits of transfer count 16 25 read-write DMCRB DMA Block Transfer Count Register 0x0C 32 read-write 0x00000000 0xffffffff DMCRBL Functions as a number of block, repeat or repeat-block transfer counter. 0 15 read-write DMCRBH Specifies the number of block, repeat or repeat-block transfer operations. 16 31 read-write DMTMD DMA Transfer Mode Register 0x10 16 read-write 0x0000 0xffff DCTG Transfer Request Source Select 0 1 read-write 00 Software request #00 01 Hardware request #01 10 Setting prohibited #10 11 Setting prohibited #11 SZ Transfer Data Size Select 8 9 read-write 00 8 bits #00 01 16 bits #01 10 32 bits #10 11 Setting prohibited #11 TKP Transfer Keeping 10 10 read-write 0 Transfer is stopped by completion of specified total number of transfer operations. #0 1 Transfer is not stopped by completion of specified total number of transfer operations (free-running). #1 DTS Repeat Area Select 12 13 read-write 00 The destination is specified as the repeat area or block area. #00 01 The source is specified as the repeat area or block area. #01 10 The repeat area or block area is not specified. #10 11 Setting prohibited. #11 MD Transfer Mode Select 14 15 read-write 00 Normal transfer #00 01 Repeat transfer #01 10 Block transfer #10 11 Repeat-block transfer #11 DMINT DMA Interrupt Setting Register 0x13 8 read-write 0x00 0xff DARIE Destination Address Extended Repeat Area Overflow Interrupt Enable 0 0 read-write 0 Disables an interrupt request for an extended repeat area overflow on the destination address. #0 1 Enables an interrupt request for an extended repeat area overflow on the destination address. #1 SARIE Source Address Extended Repeat Area Overflow Interrupt Enable 1 1 read-write 0 Disables an interrupt request for an extended repeat area overflow on the source address. #0 1 Enables an interrupt request for an extended repeat area overflow on the source address. #1 RPTIE Repeat Size End Interrupt Enable 2 2 read-write 0 Disables the repeat size end interrupt request. #0 1 Enables the repeat size end interrupt request. #1 ESIE Transfer Escape End Interrupt Enable 3 3 read-write 0 Disables the transfer escape end interrupt request. #0 1 Enables the transfer escape end interrupt request. #1 DTIE Transfer End Interrupt Enable 4 4 read-write 0 Disables the transfer end interrupt request. #0 1 Enables the transfer end interrupt request. #1 DMAMD DMA Address Mode Register 0x14 16 read-write 0x0000 0xffff DARA Destination Address Extended Repeat Area 0 4 read-write DADR Destination Address Update Select After Reload 5 5 read-write 0 Only reloading. #0 1 Add index after reloading. #1 DM Destination Address Update Mode 6 7 read-write 00 Destination address is fixed. #00 01 Offset addition. #01 10 Destination address is incremented. #10 11 Destination address is decremented. #11 SARA Source Address Extended Repeat Area 8 12 read-write SADR Source Address Update Select After Reload 13 13 read-write 0 Only reloading. #0 1 Add index after reloading. #1 SM Source Address Update Mode 14 15 read-write 00 Source address is fixed. #00 01 Offset addition. #01 10 Source address is incremented. #10 11 Source address is decremented. #11 DMOFR DMA Offset Register 0x18 32 read-write 0x00000000 0xffffffff DMCNT DMA Transfer Enable Register 0x1C 8 read-write 0x00 0xff DTE DMA Transfer Enable 0 0 read-write 0 Disables DMA transfer. #0 1 Enables DMA transfer. #1 DMREQ DMA Software Start Register 0x1D 8 read-write 0x00 0xff SWREQ DMA Software Start 0 0 read-write 0 DMA transfer is not requested. #0 1 DMA transfer is requested. #1 CLRS DMA Software Start Bit Auto Clear Select 4 4 read-write 0 SWREQ bit is cleared after DMA transfer is started by software. #0 1 SWREQ bit is not cleared after DMA transfer is started by software. #1 DMSTS DMA Status Register 0x1E 8 read-write 0x00 0xff ESIF Transfer Escape End Interrupt Flag 0 0 read-write 0 A transfer escape end interrupt has not been generated. #0 1 A transfer escape end interrupt has been generated. #1 DTIF Transfer End Interrupt Flag 4 4 read-write 0 A transfer end interrupt has not been generated. #0 1 A transfer end interrupt has been generated. #1 ACT DMAC Active Flag 7 7 read-only 0 DMAC is in the idle state. #0 1 DMAC is operating. #1 DMSRR DMA Source Reload Address Register 0x20 32 read-write 0x00000000 0xffffffff DMDRR DMA Destination Reload Address Register 0x24 32 read-write 0x00000000 0xffffffff DMSBS DMA Source Buffer Size Register 0x28 32 read-write 0x00000000 0xffffffff DMSBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMSBSH Specifies the repeat-area size in repeat-block transfer mode 16 31 read-write DMDBS DMA Destination Buffer Size Register 0x2C 32 read-write 0x00000000 0xffffffff DMDBSL Functions as data transfer counter in repeat-block transfer mode. 0 15 read-write DMDBSH Specifies the repeat-area size in repeat-block transfer mode. 16 31 read-write DMAC1 Direct memory access controller 1 0x40005040 DMAC2 Direct memory access controller 2 0x40005080 DMAC3 Direct memory access controller 3 0x400050C0 DMAC4 Direct memory access controller 4 0x40005100 DMAC5 Direct memory access controller 5 0x40005140 DMAC6 Direct memory access controller 6 0x40005180 DMAC7 Direct memory access controller 7 0x400051C0 DMA DMAC Module Activation 0x40005200 0x00 1 registers 0x40 4 registers DMAST DMA Module Activation Register 0x00 8 read-write 0x00 0xff DMST DMAC Operation Enable 0 0 read-write 0 DMAC activation is disabled. #0 1 DMAC activation is enabled. #1 DMECHR DMAC Error Channel Register 0x40 32 read-write 0x00000000 0xffffffff DMECH DMAC Error channel 0 2 read-only DMECHSAM DMAC Error channel Security Attribution Monitor 8 8 read-only 0 secure channel #0 1 non-secure channel #1 DMESTA DMAC Error Status 16 16 read-write 0 No DMA transfer error occurred #0 1 DMA transfer error occurred #1 DTC Data Transfer Controller 0x40005400 0x00 1 registers 0x04 4 registers 0x0C 1 registers 0x0E 3 registers 0x14 4 registers 0x20 4 registers DTCCR DTC Control Register 0x00 8 read-write 0x08 0xff RRS DTC Transfer Information Read Skip Enable 4 4 read-write 0 Transfer information read is not skipped #0 1 Transfer information read is skipped when vector numbers match #1 DTCVBR DTC Vector Base Register 0x04 32 read-write 0x00000000 0xffffffff DTCST DTC Module Start Register 0x0C 8 read-write 0x00 0xff DTCST DTC Module Start 0 0 read-write 0 DTC module stopped. #0 1 DTC module started. #1 DTCSTS DTC Status Register 0x0E 16 read-only 0x0000 0xffff VECN DTC-Activating Vector Number Monitoring 0 7 read-only ACT DTC Active Flag 15 15 read-only 0 DTC transfer operation is not in progress. #0 1 DTC transfer operation is in progress. #1 DTCCR_SEC DTC Control Register for secure Region 0x10 8 read-write 0x08 0xff RRS DTC Transfer Information Read Skip Enable for Secure 4 4 read-write 0 Transfer information read is not skipped. #0 1 Transfer information read is skipped when vector numbers match. #1 DTCVBR_SEC DTC Vector Base Register for secure Region 0x14 32 read-write 0x00000000 0xffffffff DTEVR DTC Error Vector Register 0x20 32 read-write 0x00000000 0xffffffff DTEV DTC Error Vector Number 0 7 read-only DTEVSAM DTC Error Vector Number SA Monitor 8 8 read-only 0 Secure vector number #0 1 Non-Secure vector number #1 DTESTA DTC Error Status Flag 16 16 read-write 0 No DTC transfer error occurred #0 1 DTC transfer error occurred #1 ICU Interrupt Controller 0x40006000 0x00 16 registers 0x100 1 registers 0x120 2 registers 0x130 2 registers 0x140 2 registers 0x1A0 4 registers 0x200 2 registers 0x280 32 registers 0x300 384 registers IEL0 ICU Interrupt 0 0 IEL1 ICU Interrupt 1 1 IEL2 ICU Interrupt 2 2 IEL3 ICU Interrupt 3 3 IEL4 ICU Interrupt 4 4 IEL5 ICU Interrupt 5 5 IEL6 ICU Interrupt 6 6 IEL7 ICU Interrupt 7 7 IEL8 ICU Interrupt 8 8 IEL9 ICU Interrupt 9 9 IEL10 ICU Interrupt 10 10 IEL11 ICU Interrupt 11 11 IEL12 ICU Interrupt 12 12 IEL13 ICU Interrupt 13 13 IEL14 ICU Interrupt 14 14 IEL15 ICU Interrupt 15 15 IEL16 ICU Interrupt 16 16 IEL17 ICU Interrupt 17 17 IEL18 ICU Interrupt 18 18 IEL19 ICU Interrupt 19 19 IEL20 ICU Interrupt 20 20 IEL21 ICU Interrupt 21 21 IEL22 ICU Interrupt 22 22 IEL23 ICU Interrupt 23 23 IEL24 ICU Interrupt 24 24 IEL25 ICU Interrupt 25 25 IEL26 ICU Interrupt 26 26 IEL27 ICU Interrupt 27 27 IEL28 ICU Interrupt 28 28 IEL29 ICU Interrupt 29 29 IEL30 ICU Interrupt 30 30 IEL31 ICU Interrupt 31 31 IEL32 ICU Interrupt 32 32 IEL33 ICU Interrupt 33 33 IEL34 ICU Interrupt 34 34 IEL35 ICU Interrupt 35 35 IEL36 ICU Interrupt 36 36 IEL37 ICU Interrupt 37 37 IEL38 ICU Interrupt 38 38 IEL39 ICU Interrupt 39 39 IEL40 ICU Interrupt 40 40 IEL41 ICU Interrupt 41 41 IEL42 ICU Interrupt 42 42 IEL43 ICU Interrupt 43 43 IEL44 ICU Interrupt 44 44 IEL45 ICU Interrupt 45 45 IEL46 ICU Interrupt 46 46 IEL47 ICU Interrupt 47 47 IEL48 ICU Interrupt 48 48 IEL49 ICU Interrupt 49 49 IEL50 ICU Interrupt 50 50 IEL51 ICU Interrupt 51 51 IEL52 ICU Interrupt 52 52 IEL53 ICU Interrupt 53 53 IEL54 ICU Interrupt 54 54 IEL55 ICU Interrupt 55 55 IEL56 ICU Interrupt 56 56 IEL57 ICU Interrupt 57 57 IEL58 ICU Interrupt 58 58 IEL59 ICU Interrupt 59 59 IEL60 ICU Interrupt 60 60 IEL61 ICU Interrupt 61 61 IEL62 ICU Interrupt 62 62 IEL63 ICU Interrupt 63 63 IEL64 ICU Interrupt 64 64 IEL65 ICU Interrupt 65 65 IEL66 ICU Interrupt 66 66 IEL67 ICU Interrupt 67 67 IEL68 ICU Interrupt 68 68 IEL69 ICU Interrupt 69 69 IEL70 ICU Interrupt 70 70 IEL71 ICU Interrupt 71 71 IEL72 ICU Interrupt 72 72 IEL73 ICU Interrupt 73 73 IEL74 ICU Interrupt 74 74 IEL75 ICU Interrupt 75 75 IEL76 ICU Interrupt 76 76 IEL77 ICU Interrupt 77 77 IEL78 ICU Interrupt 78 78 IEL79 ICU Interrupt 79 79 IEL80 ICU Interrupt 80 80 IEL81 ICU Interrupt 81 81 IEL82 ICU Interrupt 82 82 IEL83 ICU Interrupt 83 83 IEL84 ICU Interrupt 84 84 IEL85 ICU Interrupt 85 85 IEL86 ICU Interrupt 86 86 IEL87 ICU Interrupt 87 87 IEL88 ICU Interrupt 88 88 IEL89 ICU Interrupt 89 89 IEL90 ICU Interrupt 90 90 IEL91 ICU Interrupt 91 91 IEL92 ICU Interrupt 92 92 IEL93 ICU Interrupt 93 93 IEL94 ICU Interrupt 94 94 IEL95 ICU Interrupt 95 95 16 0x1 0-15 IRQCR%s IRQ Control Register %s 0x000 8 read-write 0x00 0xff IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 5 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQi Digital Filter Enable 7 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 NMICR NMI Pin Interrupt Control Register 0x100 8 read-write 0x00 0xff NMIMD NMI Detection Set 0 0 read-write 0 Falling edge #0 1 Rising edge #1 NFCLKSEL NMI Digital Filter Sampling Clock Select 4 5 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 NFLTEN NMI Digital Filter Enable 7 7 read-write 0 Disabled. #0 1 Enabled. #1 NMIER Non-Maskable Interrupt Enable Register 0x120 16 read-write 0x0000 0xffff IWDTEN IWDT Underflow/Refresh Error Interrupt Enable 0 0 read-write 0 Disabled #0 1 Enabled. #1 WDTEN WDT Underflow/Refresh Error Interrupt Enable 1 1 read-write 0 Disabled #0 1 Enabled #1 LVD1EN Voltage monitor 1 Interrupt Enable 2 2 read-write 0 Disabled #0 1 Enabled #1 LVD2EN Voltage monitor 2 Interrupt Enable 3 3 read-write 0 Disabled #0 1 Enabled #1 OSTEN Oscillation Stop Detection Interrupt Enable 6 6 read-write 0 Disabled #0 1 Enabled #1 NMIEN NMI Pin Interrupt Enable 7 7 read-write 0 Disabled #0 1 Enabled #1 RPEEN SRAM Parity Error Interrupt Enable 8 8 read-write 0 Disabled #0 1 Enabled #1 RECCEN SRAM ECC Error Interrupt Enable 9 9 read-write 0 Disabled #0 1 Enabled #1 BUSMEN Bus Master MPU Error Interrupt Enable 11 11 read-write 0 Disabled #0 1 Enabled #1 TZFEN 13 13 read-write 0 Disabled #0 1 Enabled #1 CPEEN 15 15 read-write 0 Disabled #0 1 Enabled #1 NMICLR Non-Maskable Interrupt Status Clear Register 0x130 16 read-write 0x0000 0xffff IWDTCLR IWDT Underflow/Refresh Error Interrupt Status Flag Clear 0 0 read-write 0 No effect #0 1 Clear the NMISR.IWDTST flag #1 WDTCLR WDT Underflow/Refresh Error Interrupt Status Flag Clear 1 1 read-write 0 No effect #0 1 Clear the NMISR.WDTST flag #1 LVD1CLR Voltage Monitor 1 Interrupt Status Flag Clear 2 2 read-write 0 No effect #0 1 Clear the NMISR.LVD1ST flag #1 LVD2CLR Voltage Monitor 2 Interrupt Status Flag Clear 3 3 read-write 0 No effect #0 1 Clear the NMISR.LVD2ST flag. #1 OSTCLR Oscillation Stop Detection Interrupt Status Flag Clear 6 6 read-write 0 No effect #0 1 Clear the NMISR.OSTST flag #1 NMICLR NMI Pin Interrupt Status Flag Clear 7 7 read-write 0 No effect #0 1 Clear the NMISR.NMIST flag #1 RPECLR SRAM Parity Error Interrupt Status Flag Clear 8 8 read-write 0 No effect #0 1 Clear the NMISR.RPEST flag #1 RECCCLR SRAM ECC Error Interrupt Status Flag Clear 9 9 read-write 0 No effect #0 1 Clear the NMISR.RECCST flag #1 BUSMCLR Bus Master MPU Error Interrupt Status Flag Clear 11 11 read-write 0 No effect #0 1 Clear the NMISR.BUSMST flag #1 TZFCLR 13 13 read-write 0 No effect #0 1 Clear the NMISR.TZFCLR flag #1 CPECLR 15 15 read-write 0 No effect #0 1 Clear the NMISR.CPECLR flag #1 NMISR Non-Maskable Interrupt Status Register 0x140 16 read-only 0x0000 0xffff IWDTST IWDT Underflow/Refresh Error Interrupt Status Flag 0 0 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 WDTST WDT Underflow/Refresh Error Interrupt Status Flag 1 1 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 LVD1ST Voltage Monitor 1 Interrupt Status Flag 2 2 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 LVD2ST Voltage Monitor 2 Interrupt Status Flag 3 3 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 OSTST Oscillation Stop Detection Interrupt Status Flag 6 6 read-only 0 Interrupt not requested for main oscillation stop #0 1 Interrupt requested for main oscillation stop #1 NMIST NMI Pin Interrupt Status Flag 7 7 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 RPEST SRAM Parity Error Interrupt Status Flag 8 8 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 RECCST SRAM ECC Error Interrupt Status Flag 9 9 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 BUSMST Bus Master MPU Error Interrupt Status Flag 11 11 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 TZFST 13 13 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 CPEST 15 15 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 WUPEN0 Wake Up Interrupt Enable Register 0 0x1A0 32 read-write 0x00000000 0xffffffff IRQWUPEN IRQn Interrupt Software Standby/Snooze Mode Returns Enable bit (n = 0 to 15) 0 15 read-write 0 Software Standby/Snooze Mode returns by IRQn interrupt is disabled #0 1 Software Standby/Snooze Mode returns by IRQn interrupt is enabled #1 IWDTWUPEN IWDT Interrupt Software Standby/Snooze Mode Returns Enable bit 16 16 read-write 0 Software Standby/Snooze Mode returns by IWDT interrupt is disabled #0 1 Software Standby/Snooze Mode returns by IWDT interrupt is enabled #1 KEYWUPEN Key interrupt S/W standby returns enable bit 17 17 read-write 0 S/W standby returns by KEY interrupt is disabled #0 1 S/W standby returns by KEY interrupt is enabled #1 LVD1WUPEN LVD1 Interrupt Software Standby/Snooze Mode Returns Enable bit 18 18 read-write 0 Software Standby/Snooze Mode returns by LVD1 interrupt is disabled #0 1 Software Standby/Snooze Mode returns by LVD1 interrupt is enabled #1 LVD2WUPEN LVD2 Interrupt Software Standby/Snooze Mode Returns Enable bit 19 19 read-write 0 Software Standby/Snooze Mode returns by LVD2 interrupt is disabled #0 1 Software Standby/Snooze Mode returns by LVD2 interrupt is enabled #1 AGT1UDWUPEN AGT1 Underflow Interrupt Software Standby/Snooze Mode Returns Enable bit 28 28 read-write 0 Software Standby/Snooze Mode returns by AGT1 underflow interrupt is disabled #0 1 Software Standby/Snooze Mode returns by AGT1 underflow interrupt is enabled #1 AGT1CAWUPEN AGT1 Compare Match A Interrupt Software Standby/Snooze Mode Returns Enable bit 29 29 read-write 0 Software Standby/Snooze Mode returns by AGT1 compare match A interrupt is disabled #0 1 Software Standby/Snooze Mode returns by AGT1 compare match A interrupt is enabled #1 AGT1CBWUPEN AGT1 Compare Match B Interrupt Software Standby/Snooze Mode Returns Enable bit 30 30 read-write 0 Software Standby/Snooze Mode returns by AGT1 compare match B interrupt is disabled #0 1 Software Standby/Snooze Mode returns by AGT1 compare match B interrupt is enabled #1 IIC0WUPEN IIC0 Address Match Interrupt Software Standby/Snooze Mode Returns Enable bit 31 31 read-write 0 Software Standby/Snooze Mode returns by IIC0 address match interrupt is disabled #0 1 Software Standby/Snooze Mode returns by IIC0 address match interrupt is enabled #1 SELSR0 SYS Event Link Setting Register 0x200 16 read-write 0x0000 0xffff 8 0x4 0-7 DELSR%s DMAC Event Link Setting Register %s 0x280 32 read-write 0x00000000 0xffffffff DELS DMAC Event Link Select 0 8 read-write 0x00 Disable interrupts to the associated DMAC module. 0x00 Others Event signal number to be linked. For details, see . true IR DMAC Activation Request Status Flag 16 16 read-write 0 No DMAC activation request occurred. #0 1 DMAC activation request occurred. #1 96 0x4 0-95 IELSR%s ICU Event Link Setting Register %s 0x300 32 read-write 0x00000000 0xffffffff CACHE CACHE 0x40007000 0x00 12 registers 0x40 12 registers 0x200 8 registers CCACTL C-Cache Control Register 0x000 32 read-write 0x00000000 0xffffffff ENC C-Cache Enable 0 0 read-write 0 Disable C-cache #0 1 Enable C-cache #1 CCAFCT C-Cache Flush Control Register 0x004 32 read-write 0x00000000 0xffffffff FC C-Cache Flush 0 0 read-write 0 No action #0 1 C-cache line flush (all lines invalidated) #1 CCALCF C-Cache Line Configuration Register 0x008 32 read-write 0x00000001 0xffffffff CC C-Cache Line Size 0 1 read-write 00 Prohibited #00 01 Cache line size 32 bytes #01 10 Cache line size 64 bytes #10 11 Prohibited #11 SCACTL S-Cache Control Register 0x040 32 read-write 0x00000000 0xffffffff ENS S-Cache Enable 0 0 read-write 0 Disable S-cache #0 1 Enable S-cache #1 SCAFCT S-Cache Flush Control Register 0x044 32 read-write 0x00000000 0xffffffff FS S-Cache Flush 0 0 read-write 0 No action #0 1 S-cache line flush (all lines invalidated) #1 SCALCF S-Cache Line Configuration Register 0x048 32 read-write 0x00000001 0xffffffff CS S-Cache Line Size 0 1 read-write 00 Prohibited #00 01 Cache line size 32 bytes #01 10 Cache line size 64 bytes #10 11 Prohibited #11 CAPOAD Cache Parity Error Operation After Detection Register 0x200 32 read-write 0x00000000 0xffffffff OAD Operation after Detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 CAPRCR Cache Protection Register 0x204 32 read-write 0x00000000 0xffffffff PRCR Register Write Control 0 0 read-write 0 Disable writes to protected registers #0 1 Enable writes to protected registers #1 KW Write key code 1 7 read-write CPSCU CPU System Security Control Unit 0x40008000 0x00 4 registers 0x10 8 registers 0x30 8 registers 0x40 20 registers 0x70 12 registers 0x100 8 registers 0x130 8 registers 0x180 4 registers 0x1B0 4 registers CSAR Cache Security Attribution Register 0x000 32 read-write 0xffffffff 0xffffffff CACHESA Security Attributes of Registers for Cache Control 0 0 read-write 0 Secure #0 1 Non-secure #1 CACHELSA Security Attributes of Registers for Cache Line Configuration 1 1 read-write 0 Secure #0 1 Non-secure #1 CACHEESA Security Attributes of Registers for Cache Error 2 2 read-write 0 Secure #0 1 Non-secure #1 SRAMSAR SRAM Security Attribution Register 0x10 32 read-write 0xffffffff 0xffffffff SRAMSA0 Security attributes of registers for SRAM Protection 0 0 read-write 0 Secure #0 1 Non-Secure #1 SRAMSA2 Security attributes of registers for ECC Relation 2 2 read-write 0 Secure #0 1 Non-Secure #1 STBRAMSAR Standby RAM memory Security Attribution Register 0x014 32 read-write 0xfffffff0 0xffffffff NSBSTBR Security attributes of each region for Standby RAM 0 3 read-write 0x0 Region7-0 are all Secure. 0x0 0x1 Region7 is Non-secure. Region6-0 are Secure 0x1 0x2 Region7-6 are Non-secure. Region5-0 are Secure. 0x2 0x3 Region7-5 are Non-secure. Region4-0 are Secure. 0x3 0x4 Region7-4 are Non-secure. Region 3-0 are Secure. 0x4 0x5 Region7-3 are Non-secure. Region 2-0 are Secure. 0x5 0x6 Region7-2 are Non-secure. Region 1-0 are Secure. 0x6 0x7 Region7-1 are Non-Secure. Region0 is Secure. 0x7 Others Region7-0 are all Non-Secure. true DTCSAR DTC Controller Security Attribution Register 0x30 32 read-write 0xffffffff 0xffffffff DTCSTSA DTC Security Attribution 0 0 read-write 0 Secure. #0 1 Non-Secure. #1 DMACSAR DMAC Controller Security Attribution Register 0x34 32 read-write 0xffffffff 0xffffffff DMASTSA DMAST Security Attribution 0 0 read-write 0 Secure #0 1 Non-secure #1 ICUSARA Interrupt Controller Unit Security Attribution Register A 0x40 32 read-write 0xffffffff 0xffffffff SAIRQCR00 Security attributes of registers for the IRQCRn register 0 0 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR01 Security attributes of registers for the IRQCRn register 1 1 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR02 Security attributes of registers for the IRQCRn register 2 2 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR03 Security attributes of registers for the IRQCRn register 3 3 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR04 Security attributes of registers for the IRQCRn register 4 4 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR05 Security attributes of registers for the IRQCRn register 5 5 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR06 Security attributes of registers for the IRQCRn register 6 6 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR07 Security attributes of registers for the IRQCRn register 7 7 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR08 Security attributes of registers for the IRQCRn register 8 8 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR09 Security attributes of registers for the IRQCRn register 9 9 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR10 Security attributes of registers for the IRQCRn register 10 10 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR11 Security attributes of registers for the IRQCRn register 11 11 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR12 Security attributes of registers for the IRQCRn register 12 12 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR13 Security attributes of registers for the IRQCRn register 13 13 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR14 Security attributes of registers for the IRQCRn register 14 14 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR15 Security attributes of registers for the IRQCRn register 15 15 read-write 0 Secure #0 1 Non-secure #1 ICUSARB Interrupt Controller Unit Security Attribution Register B 0x44 32 read-write 0xffffffff 0xffffffff SANMI Security attributes of registers for nonmaskable interrupt 0 0 read-write 0 Secure #0 1 Non-secure #1 ICUSARC Interrupt Controller Unit Security Attribution Register C 0x48 32 read-write 0xffffffff 0xffffffff SADMAC0 Security attributes of registers for DMAC channel 0 0 read-write 0 Secure #0 1 Non-secure #1 SADMAC1 Security attributes of registers for DMAC channel 1 1 read-write 0 Secure #0 1 Non-secure #1 SADMAC2 Security attributes of registers for DMAC channel 2 2 read-write 0 Secure #0 1 Non-secure #1 SADMAC3 Security attributes of registers for DMAC channel 3 3 read-write 0 Secure #0 1 Non-secure #1 SADMAC4 Security attributes of registers for DMAC channel 4 4 read-write 0 Secure #0 1 Non-secure #1 SADMAC5 Security attributes of registers for DMAC channel 5 5 read-write 0 Secure #0 1 Non-secure #1 SADMAC6 Security attributes of registers for DMAC channel 6 6 read-write 0 Secure #0 1 Non-secure #1 SADMAC7 Security attributes of registers for DMAC channel 7 7 read-write 0 Secure #0 1 Non-secure #1 ICUSARD Interrupt Controller Unit Security Attribution Register D 0x4C 32 read-write 0xffffffff 0xffffffff SASELSR0 Security attributes of registers for SELSR0 0 0 read-write 0 Secure #0 1 Non-secure #1 ICUSARE Interrupt Controller Unit Security Attribution Register E 0x50 32 read-write 0xffffffff 0xffffffff SAIWDTWUP Security attributes of registers for WUPEN0.b16 16 16 read-write 0 Secure #0 1 Non-secure #1 SAKEYWUP Security attributes of registers for WUPEN0.b17 17 17 read-write 0 Secure #0 1 Non-secure #1 SALVD1WUP Security attributes of registers for WUPEN0.b18 18 18 read-write 0 Secure #0 1 Non-secure #1 SALVD2WUP Security attributes of registers for WUPEN0.b19 19 19 read-write 0 Secure #0 1 Non-secure #1 SAAGT1UDWUP Security attributes of registers for WUPEN0.b28 28 28 read-write 0 Secure #0 1 Non-secure #1 SAAGT1CAWUP Security attributes of registers for WUPEN0.b29 29 29 read-write 0 Secure #0 1 Non-secure #1 SAAGT1CBWUP Security attributes of registers for WUPEN0.b30 30 30 read-write 0 Secure #0 1 Non-secure #1 SAIIC0WUP Security attributes of registers for WUPEN0.b31 31 31 read-write 0 Secure #0 1 Non-secure #1 ICUSARG Interrupt Controller Unit Security Attribution Register G 0x70 32 read-write 0xffffffff 0xffffffff SAIELSR00 Security attributes of registers for IELSR31 to IELSR0 0 0 read-write 0 Secure #0 1 Non-secure #1 SAIELSR01 Security attributes of registers for IELSR31 to IELSR0 1 1 read-write 0 Secure #0 1 Non-secure #1 SAIELSR02 Security attributes of registers for IELSR31 to IELSR0 2 2 read-write 0 Secure #0 1 Non-secure #1 SAIELSR03 Security attributes of registers for IELSR31 to IELSR0 3 3 read-write 0 Secure #0 1 Non-secure #1 SAIELSR04 Security attributes of registers for IELSR31 to IELSR0 4 4 read-write 0 Secure #0 1 Non-secure #1 SAIELSR05 Security attributes of registers for IELSR31 to IELSR0 5 5 read-write 0 Secure #0 1 Non-secure #1 SAIELSR06 Security attributes of registers for IELSR31 to IELSR0 6 6 read-write 0 Secure #0 1 Non-secure #1 SAIELSR07 Security attributes of registers for IELSR31 to IELSR0 7 7 read-write 0 Secure #0 1 Non-secure #1 SAIELSR08 Security attributes of registers for IELSR31 to IELSR0 8 8 read-write 0 Secure #0 1 Non-secure #1 SAIELSR09 Security attributes of registers for IELSR31 to IELSR0 9 9 read-write 0 Secure #0 1 Non-secure #1 SAIELSR10 Security attributes of registers for IELSR31 to IELSR0 10 10 read-write 0 Secure #0 1 Non-secure #1 SAIELSR11 Security attributes of registers for IELSR31 to IELSR0 11 11 read-write 0 Secure #0 1 Non-secure #1 SAIELSR12 Security attributes of registers for IELSR31 to IELSR0 12 12 read-write 0 Secure #0 1 Non-secure #1 SAIELSR13 Security attributes of registers for IELSR31 to IELSR0 13 13 read-write 0 Secure #0 1 Non-secure #1 SAIELSR14 Security attributes of registers for IELSR31 to IELSR0 14 14 read-write 0 Secure #0 1 Non-secure #1 SAIELSR15 Security attributes of registers for IELSR31 to IELSR0 15 15 read-write 0 Secure #0 1 Non-secure #1 SAIELSR16 Security attributes of registers for IELSR31 to IELSR0 16 16 read-write 0 Secure #0 1 Non-secure #1 SAIELSR17 Security attributes of registers for IELSR31 to IELSR0 17 17 read-write 0 Secure #0 1 Non-secure #1 SAIELSR18 Security attributes of registers for IELSR31 to IELSR0 18 18 read-write 0 Secure #0 1 Non-secure #1 SAIELSR19 Security attributes of registers for IELSR31 to IELSR0 19 19 read-write 0 Secure #0 1 Non-secure #1 SAIELSR20 Security attributes of registers for IELSR31 to IELSR0 20 20 read-write 0 Secure #0 1 Non-secure #1 SAIELSR21 Security attributes of registers for IELSR31 to IELSR0 21 21 read-write 0 Secure #0 1 Non-secure #1 SAIELSR22 Security attributes of registers for IELSR31 to IELSR0 22 22 read-write 0 Secure #0 1 Non-secure #1 SAIELSR23 Security attributes of registers for IELSR31 to IELSR0 23 23 read-write 0 Secure #0 1 Non-secure #1 SAIELSR24 Security attributes of registers for IELSR31 to IELSR0 24 24 read-write 0 Secure #0 1 Non-secure #1 SAIELSR25 Security attributes of registers for IELSR31 to IELSR0 25 25 read-write 0 Secure #0 1 Non-secure #1 SAIELSR26 Security attributes of registers for IELSR31 to IELSR0 26 26 read-write 0 Secure #0 1 Non-secure #1 SAIELSR27 Security attributes of registers for IELSR31 to IELSR0 27 27 read-write 0 Secure #0 1 Non-secure #1 SAIELSR28 Security attributes of registers for IELSR31 to IELSR0 28 28 read-write 0 Secure #0 1 Non-secure #1 SAIELSR29 Security attributes of registers for IELSR31 to IELSR0 29 29 read-write 0 Secure #0 1 Non-secure #1 SAIELSR30 Security attributes of registers for IELSR31 to IELSR0 30 30 read-write 0 Secure #0 1 Non-secure #1 SAIELSR31 Security attributes of registers for IELSR31 to IELSR0 31 31 read-write 0 Secure #0 1 Non-secure #1 ICUSARH Interrupt Controller Unit Security Attribution Register H 0x74 32 read-write 0xffffffff 0xffffffff SAIELSR32 Security attributes of registers for IELSR63 to IELSR32 0 0 read-write 0 Secure #0 1 Non-secure #1 SAIELSR33 Security attributes of registers for IELSR63 to IELSR32 1 1 read-write 0 Secure #0 1 Non-secure #1 SAIELSR34 Security attributes of registers for IELSR63 to IELSR32 2 2 read-write 0 Secure #0 1 Non-secure #1 SAIELSR35 Security attributes of registers for IELSR63 to IELSR32 3 3 read-write 0 Secure #0 1 Non-secure #1 SAIELSR36 Security attributes of registers for IELSR63 to IELSR32 4 4 read-write 0 Secure #0 1 Non-secure #1 SAIELSR37 Security attributes of registers for IELSR63 to IELSR32 5 5 read-write 0 Secure #0 1 Non-secure #1 SAIELSR38 Security attributes of registers for IELSR63 to IELSR32 6 6 read-write 0 Secure #0 1 Non-secure #1 SAIELSR39 Security attributes of registers for IELSR63 to IELSR32 7 7 read-write 0 Secure #0 1 Non-secure #1 SAIELSR40 Security attributes of registers for IELSR63 to IELSR32 8 8 read-write 0 Secure #0 1 Non-secure #1 SAIELSR41 Security attributes of registers for IELSR63 to IELSR32 9 9 read-write 0 Secure #0 1 Non-secure #1 SAIELSR42 Security attributes of registers for IELSR63 to IELSR32 10 10 read-write 0 Secure #0 1 Non-secure #1 SAIELSR43 Security attributes of registers for IELSR63 to IELSR32 11 11 read-write 0 Secure #0 1 Non-secure #1 SAIELSR44 Security attributes of registers for IELSR63 to IELSR32 12 12 read-write 0 Secure #0 1 Non-secure #1 SAIELSR45 Security attributes of registers for IELSR63 to IELSR32 13 13 read-write 0 Secure #0 1 Non-secure #1 SAIELSR46 Security attributes of registers for IELSR63 to IELSR32 14 14 read-write 0 Secure #0 1 Non-secure #1 SAIELSR47 Security attributes of registers for IELSR63 to IELSR32 15 15 read-write 0 Secure #0 1 Non-secure #1 SAIELSR48 Security attributes of registers for IELSR63 to IELSR32 16 16 read-write 0 Secure #0 1 Non-secure #1 SAIELSR49 Security attributes of registers for IELSR63 to IELSR32 17 17 read-write 0 Secure #0 1 Non-secure #1 SAIELSR50 Security attributes of registers for IELSR63 to IELSR32 18 18 read-write 0 Secure #0 1 Non-secure #1 SAIELSR51 Security attributes of registers for IELSR63 to IELSR32 19 19 read-write 0 Secure #0 1 Non-secure #1 SAIELSR52 Security attributes of registers for IELSR63 to IELSR32 20 20 read-write 0 Secure #0 1 Non-secure #1 SAIELSR53 Security attributes of registers for IELSR63 to IELSR32 21 21 read-write 0 Secure #0 1 Non-secure #1 SAIELSR54 Security attributes of registers for IELSR63 to IELSR32 22 22 read-write 0 Secure #0 1 Non-secure #1 SAIELSR55 Security attributes of registers for IELSR63 to IELSR32 23 23 read-write 0 Secure #0 1 Non-secure #1 SAIELSR56 Security attributes of registers for IELSR63 to IELSR32 24 24 read-write 0 Secure #0 1 Non-secure #1 SAIELSR57 Security attributes of registers for IELSR63 to IELSR32 25 25 read-write 0 Secure #0 1 Non-secure #1 SAIELSR58 Security attributes of registers for IELSR63 to IELSR32 26 26 read-write 0 Secure #0 1 Non-secure #1 SAIELSR59 Security attributes of registers for IELSR63 to IELSR32 27 27 read-write 0 Secure #0 1 Non-secure #1 SAIELSR60 Security attributes of registers for IELSR63 to IELSR32 28 28 read-write 0 Secure #0 1 Non-secure #1 SAIELSR61 Security attributes of registers for IELSR63 to IELSR32 29 29 read-write 0 Secure #0 1 Non-secure #1 SAIELSR62 Security attributes of registers for IELSR63 to IELSR32 30 30 read-write 0 Secure #0 1 Non-secure #1 SAIELSR63 Security attributes of registers for IELSR63 to IELSR32 31 31 read-write 0 Secure #0 1 Non-secure #1 ICUSARI Interrupt Controller Unit Security Attribution Register I 0x78 32 read-write 0xffffffff 0xffffffff SAIELSR64 Security attributes of registers for IELSR95 to IELSR64 0 0 read-write 0 Secure #0 1 Non-secure #1 SAIELSR65 Security attributes of registers for IELSR95 to IELSR64 1 1 read-write 0 Secure #0 1 Non-secure #1 SAIELSR66 Security attributes of registers for IELSR95 to IELSR64 2 2 read-write 0 Secure #0 1 Non-secure #1 SAIELSR67 Security attributes of registers for IELSR95 to IELSR64 3 3 read-write 0 Secure #0 1 Non-secure #1 SAIELSR68 Security attributes of registers for IELSR95 to IELSR64 4 4 read-write 0 Secure #0 1 Non-secure #1 SAIELSR69 Security attributes of registers for IELSR95 to IELSR64 5 5 read-write 0 Secure #0 1 Non-secure #1 SAIELSR70 Security attributes of registers for IELSR95 to IELSR64 6 6 read-write 0 Secure #0 1 Non-secure #1 SAIELSR71 Security attributes of registers for IELSR95 to IELSR64 7 7 read-write 0 Secure #0 1 Non-secure #1 SAIELSR72 Security attributes of registers for IELSR95 to IELSR64 8 8 read-write 0 Secure #0 1 Non-secure #1 SAIELSR73 Security attributes of registers for IELSR95 to IELSR64 9 9 read-write 0 Secure #0 1 Non-secure #1 SAIELSR74 Security attributes of registers for IELSR95 to IELSR64 10 10 read-write 0 Secure #0 1 Non-secure #1 SAIELSR75 Security attributes of registers for IELSR95 to IELSR64 11 11 read-write 0 Secure #0 1 Non-secure #1 SAIELSR76 Security attributes of registers for IELSR95 to IELSR64 12 12 read-write 0 Secure #0 1 Non-secure #1 SAIELSR77 Security attributes of registers for IELSR95 to IELSR64 13 13 read-write 0 Secure #0 1 Non-secure #1 SAIELSR78 Security attributes of registers for IELSR95 to IELSR64 14 14 read-write 0 Secure #0 1 Non-secure #1 SAIELSR79 Security attributes of registers for IELSR95 to IELSR64 15 15 read-write 0 Secure #0 1 Non-secure #1 SAIELSR80 Security attributes of registers for IELSR95 to IELSR64 16 16 read-write 0 Secure #0 1 Non-secure #1 SAIELSR81 Security attributes of registers for IELSR95 to IELSR64 17 17 read-write 0 Secure #0 1 Non-secure #1 SAIELSR82 Security attributes of registers for IELSR95 to IELSR64 18 18 read-write 0 Secure #0 1 Non-secure #1 SAIELSR83 Security attributes of registers for IELSR95 to IELSR64 19 19 read-write 0 Secure #0 1 Non-secure #1 SAIELSR84 Security attributes of registers for IELSR95 to IELSR64 20 20 read-write 0 Secure #0 1 Non-secure #1 SAIELSR85 Security attributes of registers for IELSR95 to IELSR64 21 21 read-write 0 Secure #0 1 Non-secure #1 SAIELSR86 Security attributes of registers for IELSR95 to IELSR64 22 22 read-write 0 Secure #0 1 Non-secure #1 SAIELSR87 Security attributes of registers for IELSR95 to IELSR64 23 23 read-write 0 Secure #0 1 Non-secure #1 SAIELSR88 Security attributes of registers for IELSR95 to IELSR64 24 24 read-write 0 Secure #0 1 Non-secure #1 SAIELSR89 Security attributes of registers for IELSR95 to IELSR64 25 25 read-write 0 Secure #0 1 Non-secure #1 SAIELSR90 Security attributes of registers for IELSR95 to IELSR64 26 26 read-write 0 Secure #0 1 Non-secure #1 SAIELSR91 Security attributes of registers for IELSR95 to IELSR64 27 27 read-write 0 Secure #0 1 Non-secure #1 SAIELSR92 Security attributes of registers for IELSR95 to IELSR64 28 28 read-write 0 Secure #0 1 Non-secure #1 SAIELSR93 Security attributes of registers for IELSR95 to IELSR64 29 29 read-write 0 Secure #0 1 Non-secure #1 SAIELSR94 Security attributes of registers for IELSR95 to IELSR64 30 30 read-write 0 Secure #0 1 Non-secure #1 SAIELSR95 Security attributes of registers for IELSR95 to IELSR64 31 31 read-write 0 Secure #0 1 Non-secure #1 BUSSARA BUS Security Attribution Register A 0x0100 32 read-write 0xffffffff 0xffffffff BUSSA0 BUS Security Attribution A0 0 0 read-write 0 Secure #0 1 Non-Secure #1 BUSSARB BUS Security Attribution Register B 0x0104 32 read-write 0xffffffff 0xffffffff BUSSB0 BUS Security Attribution B0 0 0 read-write 0 Secure #0 1 Non-Secure #1 MMPUSARA Master Memory Protection Unit Security Attribution Register A 0x130 32 read-write 0xffffffff 0xffffffff MMPUASAn MMPUA Security Attribution (n = 0 to 7) 0 7 read-write 0 Secure #0 1 Non-Secure #1 MMPUSARB Master Memory Protection Unit Security Attribution Register B 0x134 32 read-write 0xffffffff 0xffffffff MMPUBSA0 MMPUB Security Attribution 0 0 read-write 0 Secure #0 1 Non-Secure #1 TZFSAR TrustZone Filter Security Attribution Register 0x180 32 read-write 0xfffffffe 0xffffffff TZFSA0 Security attributes of registers for TrustZone Filter 0 0 read-write 0 Secure #0 1 Non-secure #1 CPUDSAR CPU Debug Security Attribution Register 0x1B0 32 read-write 0xfffffffe 0xffffffff CPUDSA0 CPU Debug Security Attribution 0 0 0 read-write 0 Secure #0 1 Non-secure #1 DBG Debug Function 0x4001B000 0x00 4 registers 0x10 4 registers DBGSTR Debug Status Register 0x00 32 read-only 0x00000000 0xffffffff CDBGPWRUPREQ Debug power-up request 28 28 read-only 0 OCD is not requesting debug power up #0 1 OCD is requesting debug power up #1 CDBGPWRUPACK Debug power-up acknowledge 29 29 read-only 0 Debug power-up request is not acknowledged #0 1 Debug power-up request is acknowledged #1 DBGSTOPCR Debug Stop Control Register 0x10 32 read-write 0x00000003 0xffffffff DBGSTOP_IWDT Mask bit for IWDT reset/interrupt in the OCD run mode 0 0 read-write 0 Enable IWDT reset/interrupt #0 1 Mask IWDT reset/interrupt and stop IWDT counter #1 DBGSTOP_WDT Mask bit for WDT reset/interrupt in the OCD run mode 1 1 read-write 0 Enable WDT reset/interrupt #0 1 Mask WDT reset/interrupt and stop WDT counter #1 DBGSTOP_LVD0 Mask bit for LVD0 reset 16 16 read-write 0 Enable LVD0 reset #0 1 Mask LVD0 reset #1 DBGSTOP_LVD1 Mask bit for LVD1 reset/interrupt 17 17 read-write 0 Enable LVD1 reset/interrupt #0 1 Mask LVD1 reset/interrupt #1 DBGSTOP_LVD2 Mask bit for LVD2 reset/interrupt 18 18 read-write 0 Enable LVD2 reset/interrupt #0 1 Mask LVD2 reset/interrupt #1 DBGSTOP_RPER Mask bit for SRAM parity error reset/interrupt 24 24 read-write 0 Enable SRAM parity error reset/interrupt #0 1 Mask SRAM parity error reset/interrupt #1 DBGSTOP_RECCR Mask bit for SRAM ECC error reset/interrupt 25 25 read-write 0 Enable SRAM ECC error reset/interrupt #0 1 Mask SRAM ECC error reset/interrupt #1 DBGSTOP_CPER Mask bit for Cache SRAM parity error reset/interrupt 31 31 read-write 0 Enable Cache SRAM parity error reset/interrupt #0 1 Mask Cache SRAM parity error reset/interrupt #1 FCACHE Flash Cache 0x4001C100 0x00 2 registers 0x04 2 registers 0x1C 1 registers 0x40 2 registers FCACHEE Flash Cache Enable Register 0x000 16 read-write 0x0000 0xffff FCACHEEN Flash Cache Enable 0 0 read-write 0 FCACHE is disabled #0 1 FCACHE is enabled #1 FCACHEIV Flash Cache Invalidate Register 0x004 16 read-write 0x0000 0xffff FCACHEIV Flash Cache Invalidate 0 0 read-write 0 Read: Do not invalidate. Write: The setting is ignored. #0 1 Invalidate FCACHE is invalidated. #1 FLWT Flash Wait Cycle Register 0x01C 8 read-write 0x00 0xff FLWT Flash Wait Cycle 0 2 read-write FSAR Flash Security Attribution Register 0x040 16 read-write 0xffff 0xffff FLWTSA FLWT Security Attribution 0 0 read-write 0 Secure #0 1 Non-Secure #1 FCKMHZSA FCKMHZ Security Attribution 8 8 read-write 0 Secure #0 1 Non-Secure #1 SYSC System Control 0x4001E000 0x0C 2 registers 0x20 4 registers 0x26 1 registers 0x28 3 registers 0x32 1 registers 0x36 1 registers 0x38 1 registers 0x3C 1 registers 0x3E 4 registers 0x48 3 registers 0x61 2 registers 0x6D 4 registers 0x75 4 registers 0x92 1 registers 0x94 1 registers 0x98 4 registers 0xA0 1 registers 0xA2 1 registers 0xC0 2 registers 0xE0 4 registers 0x3C0 16 registers 0x3E0 4 registers 0x3FE 7 registers 0x406 3 registers 0x40A 3 registers 0x40E 1 registers 0x410 2 registers 0x413 1 registers 0x416 3 registers 0x41A 2 registers 0x490 1 registers 0x492 1 registers SBYCR Standby Control Register 0x00C 16 read-write 0x4000 0xffff SSBY Software Standby Mode Select 15 15 read-write 0 Sleep mode #0 1 Software Standby mode. #1 SCKDIVCR System Clock Division Control Register 0x020 32 read-write 0x22022222 0xffffffff PCKD Peripheral Module Clock D (PCLKD) Select 0 2 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Setting prohibited. true PCKC Peripheral Module Clock C (PCLKC) Select 4 6 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Setting prohibited. true PCKB Peripheral Module Clock B (PCLKB) Select 8 10 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Setting prohibited. true PCKA Peripheral Module Clock A (PCLKA) Select 12 14 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Setting prohibited. true RSV Reserved. Set these bits to the same value as PCKB[2:0]. 16 18 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Settings prohibited true ICK System Clock (ICLK) Select 24 26 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Setting prohibited. true FCK FlashIF Clock (FCLK) Select 28 30 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Setting prohibited. true SCKSCR System Clock Source Control Register 0x026 8 read-write 0x01 0xff CKSEL Clock Source Select 0 2 read-write 000 HOCO #000 001 MOCO #001 010 LOCO #010 011 Main clock oscillator (MOSC) #011 100 Setting prohibited #100 101 PLL #101 110 Setting prohibited #110 111 Setting prohibited #111 PLLCCR PLL Clock Control Register 0x028 16 read-write 0x1300 0xffff PLIDIV PLL Input Frequency Division Ratio Select 0 1 read-write 00 /1 #00 01 /2 #01 10 /3 #10 Others Setting prohibited. true PLSRCSEL PLL Clock Source Select 4 4 read-write 0 Main clock oscillator #0 1 HOCO #1 PLLMUL PLL Frequency Multiplication Factor Select 8 13 read-write 0x13 0x3B PLLCR PLL Control Register 0x02A 8 read-write 0x01 0xff PLLSTP PLL Stop Control 0 0 read-write 0 PLL is operating #0 1 PLL is stopped. #1 MOSCCR Main Clock Oscillator Control Register 0x032 8 read-write 0x01 0xff MOSTP Main Clock Oscillator Stop 0 0 read-write 0 Operate the main clock oscillator #0 1 Stop the main clock oscillator #1 HOCOCR High-Speed On-Chip Oscillator Control Register 0x036 8 read-write 0x00 0xfe HCSTP HOCO Stop 0 0 read-write 0 Operate the HOCO clock #0 1 Stop the HOCO clock #1 MOCOCR Middle-Speed On-Chip Oscillator Control Register 0x038 8 read-write 0x00 0xff MCSTP MOCO Stop 0 0 read-write 0 MOCO clock is operating #0 1 MOCO clock is stopped #1 OSCSF Oscillation Stabilization Flag Register 0x03C 8 read-only 0x00 0xfe HOCOSF HOCO Clock Oscillation Stabilization Flag 0 0 read-only 0 The HOCO clock is stopped or is not yet stable #0 1 The HOCO clock is stable, so is available for use as the system clock #1 MOSCSF Main Clock Oscillation Stabilization Flag 3 3 read-only 0 The main clock oscillator is stopped (MOSTP = 1) or is not yet stable #0 1 The main clock oscillator is stable, so is available for use as the system clock #1 PLLSF PLL Clock Oscillation Stabilization Flag 5 5 read-only 0 The PLL clock is stopped, or oscillation of the PLL clock is not stable yet #0 1 The PLL clock is stable, so is available for use as the system clock #1 PLL2SF PLL2 Clock Oscillation Stabilization Flag 6 6 read-only 0 The PLL2 clock is stopped, or oscillation of the PLL2 clock is not stable yet #0 1 The PLL2 clock is stable #1 CKOCR Clock Out Control Register 0x03E 8 read-write 0x00 0xff CKOSEL Clock Out Source Select 0 2 read-write 000 HOCO (value after reset) #000 001 MOCO #001 010 LOCO #010 011 MOSC #011 100 Setting prohibited #100 101 Setting prohibited #101 Others Setting prohibited true CKODIV Clock Output Frequency Division Ratio 4 6 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 111 x 1/128 #111 CKOEN Clock Out Enable 7 7 read-write 0 Disable clock out #0 1 Enable clock out #1 TRCKCR Trace Clock Control Register 0x03F 8 read-write 0x01 0xff TRCK Trace Clock operating frequency select 0 3 read-write 0x0 /1 0x0 0x1 /2 (value after reset) 0x1 0x2 /4 0x2 Others Setting prohibited true TRCKEN Trace Clock operating Enable 7 7 read-write 0 Stop #0 1 Operation enable #1 OSTDCR Oscillation Stop Detection Control Register 0x040 8 read-write 0x00 0xff OSTDIE Oscillation Stop Detection Interrupt Enable 0 0 read-write 0 Disable oscillation stop detection interrupt (do not notify the POEG) #0 1 Enable oscillation stop detection interrupt (notify the POEG) #1 OSTDE Oscillation Stop Detection Function Enable 7 7 read-write 0 Disable oscillation stop detection function #0 1 Enable oscillation stop detection function #1 OSTDSR Oscillation Stop Detection Status Register 0x041 8 read-write 0x00 0xff OSTDF Oscillation Stop Detection Flag 0 0 read-write 0 Main clock oscillation stop not detected #0 1 Main clock oscillation stop detected #1 PLL2CCR PLL2 Clock Control Register 0x048 16 read-write 0x1300 0xffff PL2IDIV PLL2 Input Frequency Division Ratio Select 0 1 read-write 00 ∕ 1 (value after reset) #00 01 ∕ 2 #01 10 ∕ 3 #10 Others Setting prohibited. true PL2SRCSEL PLL2 Clock Source Select 4 4 read-write 0 Main clock oscillator #0 1 HOCO #1 PLL2MUL PLL2 Frequency Multiplication Factor Select 8 13 read-write PLL2CR PLL2 Control Register 0x04A 8 read-write 0x01 0xff PLL2STP PLL2 Stop Control 0 0 read-write 0 PLL2 is operating #0 1 PLL2 is stopped. #1 MOCOUTCR MOCO User Trimming Control Register 0x061 8 read-write 0x00 0xff MOCOUTRM MOCO User Trimming 0 7 read-write HOCOUTCR HOCO User Trimming Control Register 0x062 8 read-write 0x00 0xff HOCOUTRM HOCO User Trimming 0 7 read-write SCISPICKDIVCR SCI SPI Clock Division Control Register 0x06D 8 read-write 0x00 0xff SCISPICKDIV SCI SPI Clock (SCISPICLK) Division Select 0 2 read-write 000 ∕ 1 (value after reset) #000 001 ∕ 2 #001 010 ∕ 4 #010 011 ∕ 6 #011 100 ∕ 8 #100 Others Setting prohibited. true CANFDCKDIVCR CANFD Clock Division Control Register 0x06E 8 read-write 0x00 0xff CANFDCKDIV CANFD clock (CANFDCLK) Division Select 0 2 read-write 000 /1 (value after reset) #000 001 /2 #001 010 /4 #010 011 /6 #011 100 /8 #100 Others Setting prohibited true GPTCKDIVCR GPT Clock Division Control Register 0x06F 8 read-write 0x00 0xff GPTCKDIV GPT clock (GPTCLK) Division Select 0 2 read-write 000 /1 (value after reset) #000 001 /2 #001 010 /4 #010 011 /6 #011 100 /8 #100 Others Setting prohibited true IICCKDIVCR IIC Clock Division Control Register 0x070 8 read-write 0x01 0xff IICCKDIV IIC clock (IICCLK) Division Select 0 2 read-write 000 /1 (value after reset) #000 001 /2 #001 010 /4 #010 011 /6 #011 100 /8 #100 Others Setting prohibited true SCISPICKCR SCI SPI Clock Control Register 0x075 8 read-write 0x01 0xff SCISPICKSEL SCI SPI Clock (SCISPICLK) Source Select 0 2 read-write 000 HOCO #000 001 MOCO (value after reset) #001 010 LOCO #010 011 Main clock oscillator #011 101 PLL #101 110 PLL2 #110 Others Setting prohibited. true SCISPICKSREQ SCI SPI Clock (SCISPICLK) Switching Request 6 6 read-write 0 No request #0 1 Request switching. #1 SCISPICKSRDY SCI SPI Clock (SCISPICLK) Switching Ready state flag 7 7 read-only 0 Switching not possible #0 1 Switching possible. #1 CANFDCKCR CANFD Clock Control Register 0x076 8 read-write 0x01 0xff CANFDCKSEL CANFD clock (CANFDCLK) Source Select 0 2 read-write 101 PLL #101 110 PLL2 #110 Others Setting prohibited true CANFDCKSREQ CANFD clock (CANFDCLK) Switching Request 6 6 read-write 0 No request #0 1 Request switching #1 CANFDCKSRDY CANFD clock (CANFDCLK) Switching Ready state flag 7 7 read-only 0 Impossible to Switch #0 1 Possible to Switch #1 GPTCKCR GPT Clock Control Register 0x077 8 read-write 0x01 0xff GPTCKSEL GPT clock (GPTCLK) Source Select 0 2 read-write 000 HOCO #000 001 MOCO (value after reset) #001 010 LOCO #010 011 Main clock oscillator #011 101 PLL #101 110 PLL2 #110 Others Setting prohibited true GPTCKSREQ GPT clock (GPTCLK) Switching Request 6 6 read-write 0 No request #0 1 Request switching #1 GPTCKSRDY GPT clock (GPTCLK) Switching Ready state flag 7 7 read-only 0 Impossible to Switch #0 1 Possible to Switch #1 IICCKCR IIC Clock Control Register 0x078 8 read-write 0x01 0xff IICCKSEL IIC clock (IICCLK) Source Select 0 2 read-write 000 HOCO #000 001 MOCO (value after reset) #001 010 LOCO #010 011 Main clock oscillator #011 101 PLL #101 110 PLL2 #110 Others Setting prohibited true IICCKSREQ IIC clock (IICCLK) Switching Request 6 6 read-write 0 No request #0 1 Request switching #1 IICCKSRDY IIC clock (IICCLK) Switching Ready state flag 7 7 read-only 0 Impossible to Switch #0 1 Possible to Switch #1 SNZCR Snooze Control Register 0x092 8 read-write 0x00 0xff RXDREQEN RXD0 Snooze Request Enable 0 0 read-write 0 Ignore RXD0 falling edge in Software Standby mode #0 1 Detect RXD0 falling edge in Software Standby mode #1 SNZDTCEN DTC Enable in Snooze mode 1 1 read-write 0 Disable DTC operation #0 1 Enable DTC operation #1 SNZE Snooze mode Enable 7 7 read-write 0 Disable Snooze mode #0 1 Enable Snooze mode #1 SNZEDCR0 Snooze End Control Register 0 0x094 8 read-write 0x00 0xff AGTUNFED AGT1 Underflow Snooze End Enable 0 0 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 DTCZRED Last DTC Transmission Completion Snooze End Enable 1 1 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 DTCNZRED Not Last DTC Transmission Completion Snooze End Enable 2 2 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 SCI0UMTED SCI0 Address Mismatch Snooze End Enable 7 7 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 SNZREQCR0 Snooze Request Control Register 0 0x098 32 read-write 0x00000000 0xffffffff SNZREQEN0 Enable IRQ0 pin snooze request 0 0 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN1 Enable IRQ1 pin snooze request 1 1 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN2 Enable IRQ2 pin snooze request 2 2 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN3 Enable IRQ3 pin snooze request 3 3 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN4 Enable IRQ4 pin snooze request 4 4 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN5 Enable IRQ5 pin snooze request 5 5 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN6 Enable IRQ6 pin snooze request 6 6 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN7 Enable IRQ7 pin snooze request 7 7 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN8 Enable IRQ8 pin snooze request 8 8 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN9 Enable IRQ9 pin snooze request 9 9 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN10 Enable IRQ10 pin snooze request 10 10 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN11 Enable IRQ11 pin snooze request 11 11 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN12 Enable IRQ12 pin snooze request 12 12 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN13 Enable IRQ13 pin snooze request 13 13 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN14 Enable IRQ14 pin snooze request 14 14 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN15 Enable IRQ15 pin snooze request 15 15 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN17 Enable Key Interrupt snooze request 17 17 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN28 Enable AGT1 underflow snooze request 28 28 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN29 Enable AGT1 compare match A snooze request 29 29 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN30 Enable AGT1 compare match B snooze request 30 30 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 OPCCR Operating Power Control Register 0x0A0 8 read-write 0x00 0xff OPCM Operating Power Control Mode Select 0 1 read-write 00 High-speed mode #00 01 Setting prohibited #01 10 Setting prohibited #10 11 Low-speed mode #11 OPCMTSF Operating Power Control Mode Transition Status Flag 4 4 read-only 0 Transition completed #0 1 During transition #1 MOSCWTCR Main Clock Oscillator Wait Control Register 0x0A2 8 read-write 0x05 0xff MSTS Main Clock Oscillator Wait Time Setting 0 3 read-write 0x0 Wait time = 3 cycles (11.4 us) 0x0 0x1 Wait time = 35 cycles (133.5 us) 0x1 0x2 Wait time = 67 cycles (255.6 us) 0x2 0x3 Wait time = 131 cycles (499.7 us) 0x3 0x4 Wait time = 259 cycles (988.0 us) 0x4 0x5 Wait time = 547 cycles (2086.6 us) 0x5 0x6 Wait time = 1059 cycles (4039.8 us) 0x6 0x7 Wait time = 2147 cycles (8190.2 us) 0x7 0x8 Wait time = 4291 cycles (16368.9 us) 0x8 0x9 Wait time = 8163 cycles (31139.4 us) 0x9 Others Setting prohibited true RSTSR1 Reset Status Register 1 0x0C0 16 read-write 0x0000 0x54f8 IWDTRF Independent Watchdog Timer Reset Detect Flag 0 0 read-write 0 Independent watchdog timer reset not detected #0 1 Independent watchdog timer reset detected #1 WDTRF Watchdog Timer Reset Detect Flag 1 1 read-write 0 Watchdog timer reset not detected #0 1 Watchdog timer reset detected #1 SWRF Software Reset Detect Flag 2 2 read-write 0 Software reset not detected #0 1 Software reset detected #1 RPERF SRAM Parity Error Reset Detect Flag 8 8 read-write 0 SRAM parity error reset not detected #0 1 SRAM parity error reset detected #1 REERF SRAM ECC Error Reset Detect Flag 9 9 read-write 0 SRAM ECC error reset not detected #0 1 SRAM ECC error reset detected #1 BUSMRF Bus Master MPU Error Reset Detect Flag 11 11 read-write 0 Bus master MPU error reset not detected #0 1 Bus master MPU error reset detected #1 TZERF TrustZone Error Reset Detect Flag 13 13 read-write 0 TrustZone error reset not detected. #0 1 TrustZone error reset detected. #1 CPERF Cache Parity Error Reset Detect Flag 15 15 read-write 0 Cache Parity error reset not detected. #0 1 Cache Parity error reset detected. #1 LVD1CR1 Voltage Monitor 1 Circuit Control Register 0x0E0 8 read-write 0x01 0xff IDTSEL Voltage Monitor 1 Interrupt Generation Condition Select 0 1 read-write 00 When VCC >= Vdet1 (rise) is detected #00 01 When VCC < Vdet1 (fall) is detected #01 10 When fall and rise are detected #10 11 Settings prohibited #11 IRQSEL Voltage Monitor 1 Interrupt Type Select 2 2 read-write 0 Non-maskable interrupt #0 1 Maskable interrupt #1 LVD1SR Voltage Monitor 1 Circuit Status Register 0x0E1 8 read-write 0x02 0xff DET Voltage Monitor 1 Voltage Variation Detection Flag 0 0 read-write 0 Not detected #0 1 Vdet1 crossing is detected #1 MON Voltage Monitor 1 Signal Monitor Flag 1 1 read-only 0 VCC < Vdet1 #0 1 VCC >= Vdet1 or MON is disabled #1 LVD2CR1 Voltage Monitor 2 Circuit Control Register 1 0x0E2 8 read-write 0x01 0xff IDTSEL Voltage Monitor 2 Interrupt Generation Condition Select 0 1 read-write 00 When VCC>= Vdet2 (rise) is detected #00 01 When VCC < Vdet2 (fall) is detected #01 10 When fall and rise are detected #10 11 Settings prohibited #11 IRQSEL Voltage Monitor 2 Interrupt Type Select 2 2 read-write 0 Non-maskable interrupt #0 1 Maskable interrupt #1 LVD2SR Voltage Monitor 2 Circuit Status Register 0x0E3 8 read-write 0x02 0xff DET Voltage Monitor 2 Voltage Variation Detection Flag 0 0 read-write 0 Not detected #0 1 Vdet2 crossing is detected #1 MON Voltage Monitor 2 Signal Monitor Flag 1 1 read-only 0 VCC < Vdet2 #0 1 VCC>= Vdet2 or MON is disabled #1 CGFSAR Clock Generation Function Security Attribute Register 0x3C0 32 read-write 0xffffffff 0xffffffff NONSEC00 Non Secure Attribute bit 00 0 0 read-write 0 Secure #0 1 Non Secure #1 NONSEC02 Non Secure Attribute bit 02 2 2 read-write 0 Secure #0 1 Non Secure #1 NONSEC03 Non Secure Attribute bit 03 3 3 read-write 0 Secure #0 1 Non Secure #1 NONSEC04 Non Secure Attribute bit 04 4 4 read-write 0 Secure #0 1 Non Secure #1 NONSEC05 Non Secure Attribute bit 05 5 5 read-write 0 Secure #0 1 Non Secure #1 NONSEC06 Non Secure Attribute bit 06 6 6 read-write 0 Secure #0 1 Non Secure #1 NONSEC08 Non Secure Attribute bit 08 8 8 read-write 0 Secure #0 1 Non Secure #1 NONSEC09 Non Secure Attribute bit 09 9 9 read-write 0 Secure #0 1 Non Secure #1 NONSEC11 Non Secure Attribute bit 11 11 11 read-write 0 Secure #0 1 Non Secure #1 NONSEC17 Non Secure Attribute bit 17 17 17 read-write 0 Secure #0 1 Non Secure #1 NONSEC18 Non Secure Attribute bit 18 18 18 read-write 0 Secure #0 1 Non Secure #1 NONSEC19 Non Secure Attribute bit 19 19 19 read-write 0 Secure #0 1 Non Secure #1 NONSEC20 Non Secure Attribute bit 20 20 20 read-write 0 Secure #0 1 Non Secure #1 RSTSAR Reset Security Attribution Register 0x3C4 32 read-write 0xffffffff 0xffffffff NONSEC0 Non Secure Attribute bit 0 0 0 read-write 0 Secure #0 1 Non Secure #1 NONSEC1 Non Secure Attribute bit 1 1 1 read-write 0 Secure #0 1 Non Secure #1 NONSEC2 Non Secure Attribute bit 2 2 2 read-write 0 Secure #0 1 Non Secure #1 LPMSAR Low Power Mode Security Attribution Register 0x3C8 32 read-write 0xffffffff 0xffffffff NONSEC0 Non Secure Attribute bit 0 0 0 read-write 0 Secure #0 1 Non Secure #1 NONSEC2 Non Secure Attribute bit 2 2 2 read-write 0 Secure #0 1 Non Secure #1 NONSEC4 Non Secure Attribute bit 4 4 4 read-write 0 Secure #0 1 Non Secure #1 NONSEC8 Non Secure Attribute bit 8 8 8 read-write 0 Secure #0 1 Non Secure #1 NONSEC9 Non Secure Attribute bit 9 9 9 read-write 0 Secure #0 1 Non Secure #1 LVDSAR Low Voltage Detection Security Attribution Register 0x3CC 32 read-write 0xffffffff 0xffffffff NONSEC0 Non Secure Attribute bit 0 0 0 read-write 0 Secure #0 1 Non Secure #1 NONSEC1 Non Secure Attribute bit 1 1 1 read-write 0 Secure #0 1 Non Secure #1 DPFSAR Deep Software Standby Interrupt Factor Security Attribution Register 0x3E0 32 read-write 0xffffffff 0xffffffff DPFSA0 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7) 0 0 read-write 0 Secure #0 1 Non Secure #1 DPFSA1 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7) 1 1 read-write 0 Secure #0 1 Non Secure #1 DPFSA2 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7) 2 2 read-write 0 Secure #0 1 Non Secure #1 DPFSA3 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7) 3 3 read-write 0 Secure #0 1 Non Secure #1 DPFSA4 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7) 4 4 read-write 0 Secure #0 1 Non Secure #1 DPFSA5 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7) 5 5 read-write 0 Secure #0 1 Non Secure #1 DPFSA6 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7) 6 6 read-write 0 Secure #0 1 Non Secure #1 DPFSA7 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7) 7 7 read-write 0 Secure #0 1 Non Secure #1 DPFSA8 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15) 8 8 read-write 0 Secure #0 1 Non Secure #1 DPFSA9 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15) 9 9 read-write 0 Secure #0 1 Non Secure #1 DPFSA10 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15) 10 10 read-write 0 Secure #0 1 Non Secure #1 DPFSA11 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15) 11 11 read-write 0 Secure #0 1 Non Secure #1 DPFSA12 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15) 12 12 read-write 0 Secure #0 1 Non Secure #1 DPFSA13 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15) 13 13 read-write 0 Secure #0 1 Non Secure #1 DPFSA14 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15) 14 14 read-write 0 Secure #0 1 Non Secure #1 DPFSA15 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15) 15 15 read-write 0 Secure #0 1 Non Secure #1 DPFSA16 Deep Software Standby Interrupt Factor Security Attribute bit 16 16 16 read-write 0 Secure #0 1 Non Secure #1 DPFSA17 Deep Software Standby Interrupt Factor Security Attribute bit 17 17 17 read-write 0 Secure #0 1 Non Secure #1 DPFSA20 Deep Software Standby Interrupt Factor Security Attribute bit 20 20 20 read-write 0 Secure #0 1 Non Secure #1 PRCR Protect Register 0x3FE 16 read-write 0x0000 0xffff PRC0 Enable writing to the registers related to the clock generation circuit 0 0 read-write 0 Disable writes #0 1 Enable writes #1 PRC1 Enable writing to the registers related to the low power modes 1 1 read-write 0 Disable writes #0 1 Enable writes #1 PRC3 Enable writing to the registers related to the LVD 3 3 read-write 0 Disable writes #0 1 Enable writes #1 PRC4 4 4 read-write 0 Disable writes #0 1 Enable writes #1 PRKEY PRC Key Code 8 15 write-only DPSBYCR Deep Software Standby Control Register 0x400 8 read-write 0x01 0xff DEEPCUT Power-Supply Control 0 1 read-write 00 Power to the standby RAM and Low-speed on-chip oscillator is supplied in Deep Software Standby mode. #00 01 Power to the standby RAM and Low-speed on-chip oscillator is not supplied in Deep Software Standby mode. #01 10 Setting prohibited #10 11 Power to the standby RAM and Low-speed on-chip oscillator is not supplied in Deep Software Standby mode. In addition, LVD is disabled and the low power function in a power-on reset circuit is enabled. #11 IOKEEP I/O Port Rentention 6 6 read-write 0 When the Deep Software Standby mode is canceled, the I/O ports are in the reset state. #0 1 When the Deep Software Standby mode is canceled, the I/O ports are in the same state as in the Deep Software Standby mode. #1 DPSBY Deep Software Standby 7 7 read-write 0 Sleep mode (SBYCR.SSBY=0) / Software Standby mode (SBYCR.SSBY=1) #0 1 Sleep mode (SBYCR.SSBY=0) / Deep Software Standby mode (SBYCR.SSBY=1) #1 DPSWCR Deep Software Standby Wait Control Register 0x401 8 read-write 0x19 0xff WTSTS Deep Software Wait Standby Time Setting Bit 0 5 read-write 0x0E Wait cycle for fast recovery 0x0e 0x19 Wait cycle for slow recovery 0x19 Others Setting prohibited true DPSIER0 Deep Software Standby Interrupt Enable Register 0 0x402 8 read-write 0x00 0xff DIRQ0E IRQ0-DS Pin Enable 0 0 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ1E IRQ1-DS Pin Enable 1 1 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ2E IRQ2-DS Pin Enable 2 2 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ3E IRQ3-DS Pin Enable 3 3 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ4E IRQ4-DS Pin Enable 4 4 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ5E IRQ5-DS Pin Enable 5 5 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ6E IRQ6-DS Pin Enable 6 6 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ7E IRQ7-DS Pin Enable 7 7 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DPSIER1 Deep Software Standby Interrupt Enable Register 1 0x403 8 read-write 0x00 0xff DIRQ8E IRQ8-DS Pin Enable 0 0 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ9E IRQ9-DS Pin Enable 1 1 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ10E IRQ10-DS Pin Enable 2 2 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ11E IRQ11-DS Pin Enable 3 3 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ12E IRQ12-DS Pin Enable 4 4 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ13E IRQ13-DS Pin Enable 5 5 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ14E IRQ14-DS Pin Enable 6 6 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ15E IRQ15-DS Pin Enable 7 7 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DPSIER2 Deep Software Standby Interrupt Enable Register 2 0x404 8 read-write 0x00 0xff DLVD1IE LVD1 Deep Software Standby Cancel Signal Enable 0 0 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DLVD2IE LVD2 Deep Software Standby Cancel Signal Enable 1 1 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DNMIE NMI Pin Enable 4 4 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DPSIFR0 Deep Software Standby Interrupt Flag Register 0 0x406 8 read-write 0x00 0xff DIRQ0F IRQ0-DS Pin Deep Software Standby Cancel Flag 0 0 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ1F IRQ1-DS Pin Deep Software Standby Cancel Flag 1 1 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ2F IRQ2-DS Pin Deep Software Standby Cancel Flag 2 2 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ3F IRQ3-DS Pin Deep Software Standby Cancel Flag 3 3 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ4F IRQ4-DS Pin Deep Software Standby Cancel Flag 4 4 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ5F IRQ5-DS Pin Deep Software Standby Cancel Flag 5 5 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ6F IRQ6-DS Pin Deep Software Standby Cancel Flag 6 6 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ7F IRQ7-DS Pin Deep Software Standby Cancel Flag 7 7 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DPSIFR1 Deep Software Standby Interrupt Flag Register 1 0x407 8 read-write 0x00 0xff DIRQ8F IRQ8-DS Pin Deep Software Standby Cancel Flag 0 0 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ9F IRQ9-DS Pin Deep Software Standby Cancel Flag 1 1 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ10F IRQ10-DS Pin Deep Software Standby Cancel Flag 2 2 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ11F IRQ11-DS Pin Deep Software Standby Cancel Flag 3 3 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ12F IRQ12-DS Pin Deep Software Standby Cancel Flag 4 4 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ13F IRQ13-DS Pin Deep Software Standby Cancel Flag 5 5 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ14F IRQ14-DS Pin Deep Software Standby Cancel Flag 6 6 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ15F IRQ15-DS Pin Deep Software Standby Cancel Flag 7 7 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DPSIFR2 Deep Software Standby Interrupt Flag Register 2 0x408 8 read-write 0x00 0xff DLVD1IF LVD1 Deep Software Standby Cancel Flag 0 0 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DLVD2IF LVD2 Deep Software Standby Cancel Flag 1 1 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DNMIF NMI Pin Deep Software Standby Cancel Flag 4 4 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DPSIEGR0 Deep Software Standby Interrupt Edge Register 0 0x40A 8 read-write 0x00 0xff DIRQ0EG IRQ0-DS Pin Edge Select 0 0 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ1EG IRQ1-DS Pin Edge Select 1 1 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ2EG IRQ2-DS Pin Edge Select 2 2 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ3EG IRQ3-DS Pin Edge Select 3 3 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ4EG IRQ4-DS Pin Edge Select 4 4 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ5EG IRQ5-DS Pin Edge Select 5 5 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ6EG IRQ6-DS Pin Edge Select 6 6 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ7EG IRQ7-DS Pin Edge Select 7 7 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DPSIEGR1 Deep Software Standby Interrupt Edge Register 1 0x40B 8 read-write 0x00 0xff DIRQ8EG IRQ8-DS Pin Edge Select 0 0 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ9EG IRQ9-DS Pin Edge Select 1 1 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ10EG IRQ10-DS Pin Edge Select 2 2 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge #1 DIRQ11EG IRQ11-DS Pin Edge Select 3 3 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ12EG IRQ12-DS Pin Edge Select 4 4 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ13EG IRQ13-DS Pin Edge Select 5 5 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ14EG IRQ14-DS Pin Edge Select 6 6 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ15EG IRQ15-DS Pin Edge Select 7 7 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DPSIEGR2 Deep Software Standby Interrupt Edge Register 2 0x40C 8 read-write 0x00 0xff DLVD1EG LVD1 Edge Select 0 0 read-write 0 A cancel request is generated when VCC < Vdet1 (fall) is detected #0 1 A cancel request is generated when VCC ≥ Vdet1 (rise) is detected #1 DLVD2EG LVD2 Edge Select 1 1 read-write 0 A cancel request is generated when VCC < Vdet2 (fall) is detected #0 1 A cancel request is generated when VCC ≥ Vdet2 (rise) is detected #1 DNMIEG NMI Pin Edge Select 4 4 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 SYOCDCR System Control OCD Control Register 0x040E 8 read-write 0x00 0xfe DOCDF Deep Software Standby OCD flag 0 0 read-write 0 DBIRQ is not generated #0 1 DBIRQ is generated #1 DBGEN Debugger Enable bit 7 7 read-write 0 On-chip debugger is disabled #0 1 On-chip debugger is enabled #1 RSTSR0 Reset Status Register 0 0x410 8 read-write 0x00 0x70 PORF Power-On Reset Detect Flag 0 0 read-write 0 Power-on reset not detected #0 1 Power-on reset detected #1 LVD0RF Voltage Monitor 0 Reset Detect Flag 1 1 read-write 0 Voltage monitor 0 reset not detected #0 1 Voltage monitor 0 reset detected #1 LVD1RF Voltage Monitor 1 Reset Detect Flag 2 2 read-write 0 Voltage monitor 1 reset not detected #0 1 Voltage monitor 1 reset detected #1 LVD2RF Voltage Monitor 2 Reset Detect Flag 3 3 read-write 0 Voltage monitor 2 reset not detected #0 1 Voltage monitor 2 reset detected #1 DPSRSTF Deep Software Standby Reset Detect Flag 7 7 read-write 0 Deep software standby mode cancellation not requested by an interrupt. #0 1 Deep software standby mode cancellation requested by an interrupt. #1 RSTSR2 Reset Status Register 2 0x411 8 read-write 0x00 0xfe CWSF Cold/Warm Start Determination Flag 0 0 read-write 0 Cold start #0 1 Warm start #1 MOMCR Main Clock Oscillator Mode Oscillation Control Register 0x413 8 read-write 0x00 0xff MODRV Main Clock Oscillator Drive Capability 0 Switching 4 5 read-write 00 20 MHz to 24 MHz #00 01 16 MHz to 20 MHz #01 10 8 MHz to 16 MHz #10 11 8 MHz #11 MOSEL Main Clock Oscillator Switching 6 6 read-write 0 Resonator #0 1 External clock input #1 FWEPROR Flash P/E Protect Register 0x416 8 read-write 0x02 0xff FLWE Flash Programming and Erasure 0 1 read-write 00 Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing. #00 01 Permits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing. #01 10 Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing. #10 11 Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing. #11 LVD1CMPCR Voltage Monitoring 1 Comparator Control Register 0x417 8 read-write 0x13 0xff LVD1LVL Voltage Detection 1 Level Select (Standard voltage during drop in voltage) 0 4 read-write 0x11 2.99 V (Vdet1_1) 0x11 0x12 2.92 V (Vdet1_2) 0x12 0x13 2.85 V (Vdet1_3) 0x13 Others Setting prohibited true LVD1E Voltage Detection 1 Enable 7 7 read-write 0 Voltage detection 1 circuit disabled #0 1 Voltage detection 1 circuit enabled #1 LVD2CMPCR Voltage Monitoring 2 Comparator Control Register 0x418 8 read-write 0x07 0xff LVD2LVL Voltage Detection 2 Level Select (Standard voltage during drop in voltage) 0 2 read-write 101 2.99 V (Vdet2_1) #101 110 2.92 V (Vdet2_2) #110 111 2.85 V (Vdet2_3) #111 Others Setting prohibited true LVD2E Voltage Detection 2 Enable 7 7 read-write 0 Voltage detection 2 circuit disabled #0 1 Voltage detection 2 circuit enabled #1 LVD1CR0 Voltage Monitor 1 Circuit Control Register 0 0x41A 8 read-write 0x82 0xf7 RIE Voltage Monitor 1 Interrupt/Reset Enable 0 0 read-write 0 Disable #0 1 Enable #1 DFDIS Voltage monitor 1 Digital Filter Disabled Mode Select 1 1 read-write 0 Enable the digital filter #0 1 Disable the digital filter #1 CMPE Voltage Monitor 1 Circuit Comparison Result Output Enable 2 2 read-write 0 Disable voltage monitor 1 circuit comparison result output #0 1 Enable voltage monitor 1 circuit comparison result output #1 FSAMP Sampling Clock Select 4 5 read-write 00 1/2 LOCO frequency #00 01 1/4 LOCO frequency #01 10 1/8 LOCO frequency #10 11 1/16 LOCO frequency #11 RI Voltage Monitor 1 Circuit Mode Select 6 6 read-write 0 Generate voltage monitor 1 interrupt on Vdet1 crossing #0 1 Enable voltage monitor 1 reset when the voltage falls to and below Vdet1 #1 RN Voltage Monitor 1 Reset Negate Select 7 7 read-write 0 Negate after a stabilization time (tLVD1) when VCC > Vdet1 is detected #0 1 Negate after a stabilization time (tLVD1) on assertion of the LVD1 reset #1 LVD2CR0 Voltage Monitor 2 Circuit Control Register 0 0x41B 8 read-write 0x82 0xf7 RIE Voltage Monitor 2 Interrupt/Reset Enable 0 0 read-write 0 Disable #0 1 Enable #1 DFDIS Voltage monitor 2 Digital Filter Disabled Mode Select 1 1 read-write 0 Enable the digital filter #0 1 Disable the digital filter #1 CMPE Voltage Monitor 2 Circuit Comparison Result Output Enable 2 2 read-write 0 Disable voltage monitor 2 circuit comparison result output #0 1 Enable voltage monitor 2 circuit comparison result output #1 FSAMP Sampling Clock Select 4 5 read-write 00 1/2 LOCO frequency #00 01 1/4 LOCO frequency #01 10 1/8 LOCO frequency #10 11 1/16 LOCO frequency #11 RI Voltage Monitor 2 Circuit Mode Select 6 6 read-write 0 Generate voltage monitor 2 interrupt on Vdet2 crossing #0 1 Enable voltage monitor 2 reset when the voltage falls to and below Vdet2 #1 RN Voltage Monitor 2 Reset Negate Select 7 7 read-write 0 Negate after a stabilization time (tLVD2) when VCC > Vdet2 is detected #0 1 Negate after a stabilization time (tLVD2) on assertion of the LVD2 reset #1 LOCOCR Low-Speed On-Chip Oscillator Control Register 0x490 8 read-write 0x00 0xff LCSTP LOCO Stop 0 0 read-write 0 Operate the LOCO clock #0 1 Stop the LOCO clock #1 LOCOUTCR LOCO User Trimming Control Register 0x492 8 read-write 0x00 0xff LOCOUTRM LOCO User Trimming 0 7 read-write PORT0 Port 0 Control Registers 0x4001F000 0x00 8 registers 0x08 4 registers PCNTR1 Port Control Register 1 0x000 32 read-write 0x00000000 0xffffffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 31 read-write 0 Low output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x000 16 read-write 0x0000 0xffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR Port Control Register 1 PCNTR1 0x002 16 read-write 0x0000 0xffff PODR00 Pmn Output Data 0 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 15 read-write 0 Low output #0 1 High output #1 PCNTR2 Port Control Register 2 0x004 32 read-only 0x00000000 0xffff0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 PIDR Port Control Register 2 PCNTR2 0x004 16 read-only 0x0000 0x0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 PCNTR3 Port Control Register 3 0x008 32 write-only 0x00000000 0xffffffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR00 Pmn Output Reset 16 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 31 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0x008 16 write-only 0x0000 0xffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR Port Control Register 3 PCNTR3 0x00A 16 write-only 0x0000 0xffff PORR00 Pmn Output Reset 0 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 15 write-only 0 No effect on output #0 1 Low output #1 PORT2 Port 2 Control Registers 0x4001F040 0x00 8 registers 0x08 4 registers PCNTR1 Port Control Register 1 0x000 32 read-write 0x00000000 0xffffffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 31 read-write 0 Low output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x000 16 read-write 0x0000 0xffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR Port Control Register 1 PCNTR1 0x002 16 read-write 0x0000 0xffff PODR00 Pmn Output Data 0 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 15 read-write 0 Low output #0 1 High output #1 PCNTR2 Port Control Register 2 0x004 32 read-only 0x00000000 0xffff0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 PIDR Port Control Register 2 PCNTR2 0x004 16 read-only 0x0000 0x0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 PCNTR3 Port Control Register 3 0x008 32 write-only 0x00000000 0xffffffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR00 Pmn Output Reset 16 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 31 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0x008 16 write-only 0x0000 0xffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR Port Control Register 3 PCNTR3 0x00A 16 write-only 0x0000 0xffff PORR00 Pmn Output Reset 0 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 15 write-only 0 No effect on output #0 1 Low output #1 PORTA Port A Control Registers 0x4001F140 0x00 8 registers 0x08 4 registers PCNTR1 Port Control Register 1 0x000 32 read-write 0x00000000 0xffffffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 31 read-write 0 Low output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x000 16 read-write 0x0000 0xffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR Port Control Register 1 PCNTR1 0x002 16 read-write 0x0000 0xffff PODR00 Pmn Output Data 0 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 15 read-write 0 Low output #0 1 High output #1 PCNTR2 Port Control Register 2 0x004 32 read-only 0x00000000 0xffff0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 PIDR Port Control Register 2 PCNTR2 0x004 16 read-only 0x0000 0x0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 PCNTR3 Port Control Register 3 0x008 32 write-only 0x00000000 0xffffffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR00 Pmn Output Reset 16 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 31 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0x008 16 write-only 0x0000 0xffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR Port Control Register 3 PCNTR3 0x00A 16 write-only 0x0000 0xffff PORR00 Pmn Output Reset 0 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 15 write-only 0 No effect on output #0 1 Low output #1 PORTB Port B Control Registers 0x4001F160 0x00 16 registers PCNTR1 Port Control Register 1 0x000 32 read-write 0x00000000 0xffffffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 31 read-write 0 Low output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x000 16 read-write 0x0000 0xffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR Port Control Register 1 PCNTR1 0x002 16 read-write 0x0000 0xffff PODR00 Pmn Output Data 0 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 15 read-write 0 Low output #0 1 High output #1 PCNTR2 Port Control Register 2 0x004 32 read-only 0x00000000 0xffff0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 EIDR00 Port Event Input Data 16 16 read-only 0 Low input #0 1 High input #1 EIDR01 Port Event Input Data 17 17 read-only 0 Low input #0 1 High input #1 EIDR02 Port Event Input Data 18 18 read-only 0 Low input #0 1 High input #1 EIDR03 Port Event Input Data 19 19 read-only 0 Low input #0 1 High input #1 EIDR04 Port Event Input Data 20 20 read-only 0 Low input #0 1 High input #1 EIDR05 Port Event Input Data 21 21 read-only 0 Low input #0 1 High input #1 EIDR06 Port Event Input Data 22 22 read-only 0 Low input #0 1 High input #1 EIDR07 Port Event Input Data 23 23 read-only 0 Low input #0 1 High input #1 EIDR08 Port Event Input Data 24 24 read-only 0 Low input #0 1 High input #1 EIDR09 Port Event Input Data 25 25 read-only 0 Low input #0 1 High input #1 EIDR10 Port Event Input Data 26 26 read-only 0 Low input #0 1 High input #1 EIDR11 Port Event Input Data 27 27 read-only 0 Low input #0 1 High input #1 EIDR12 Port Event Input Data 28 28 read-only 0 Low input #0 1 High input #1 EIDR13 Port Event Input Data 29 29 read-only 0 Low input #0 1 High input #1 EIDR14 Port Event Input Data 30 30 read-only 0 Low input #0 1 High input #1 EIDR15 Port Event Input Data 31 31 read-only 0 Low input #0 1 High input #1 PIDR Port Control Register 2 PCNTR2 0x004 16 read-only 0x0000 0x0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 EIDR Port Control Register 2 PCNTR2 0x006 16 read-only 0x0000 0xffff EIDR00 Port Event Input Data 0 0 read-only 0 Low input #0 1 High input #1 EIDR01 Port Event Input Data 1 1 read-only 0 Low input #0 1 High input #1 EIDR02 Port Event Input Data 2 2 read-only 0 Low input #0 1 High input #1 EIDR03 Port Event Input Data 3 3 read-only 0 Low input #0 1 High input #1 EIDR04 Port Event Input Data 4 4 read-only 0 Low input #0 1 High input #1 EIDR05 Port Event Input Data 5 5 read-only 0 Low input #0 1 High input #1 EIDR06 Port Event Input Data 6 6 read-only 0 Low input #0 1 High input #1 EIDR07 Port Event Input Data 7 7 read-only 0 Low input #0 1 High input #1 EIDR08 Port Event Input Data 8 8 read-only 0 Low input #0 1 High input #1 EIDR09 Port Event Input Data 9 9 read-only 0 Low input #0 1 High input #1 EIDR10 Port Event Input Data 10 10 read-only 0 Low input #0 1 High input #1 EIDR11 Port Event Input Data 11 11 read-only 0 Low input #0 1 High input #1 EIDR12 Port Event Input Data 12 12 read-only 0 Low input #0 1 High input #1 EIDR13 Port Event Input Data 13 13 read-only 0 Low input #0 1 High input #1 EIDR14 Port Event Input Data 14 14 read-only 0 Low input #0 1 High input #1 EIDR15 Port Event Input Data 15 15 read-only 0 Low input #0 1 High input #1 PCNTR3 Port Control Register 3 0x008 32 write-only 0x00000000 0xffffffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR00 Pmn Output Reset 16 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 31 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0x008 16 write-only 0x0000 0xffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR Port Control Register 3 PCNTR3 0x00A 16 write-only 0x0000 0xffff PORR00 Pmn Output Reset 0 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 15 write-only 0 No effect on output #0 1 Low output #1 PCNTR4 Port Control Register 4 0x00C 32 read-write 0x00000000 0xffffffff EOSR00 Pmn Event Output Set 0 0 read-write 0 No effect on output #0 1 High output #1 EOSR01 Pmn Event Output Set 1 1 read-write 0 No effect on output #0 1 High output #1 EOSR02 Pmn Event Output Set 2 2 read-write 0 No effect on output #0 1 High output #1 EOSR03 Pmn Event Output Set 3 3 read-write 0 No effect on output #0 1 High output #1 EOSR04 Pmn Event Output Set 4 4 read-write 0 No effect on output #0 1 High output #1 EOSR05 Pmn Event Output Set 5 5 read-write 0 No effect on output #0 1 High output #1 EOSR06 Pmn Event Output Set 6 6 read-write 0 No effect on output #0 1 High output #1 EOSR07 Pmn Event Output Set 7 7 read-write 0 No effect on output #0 1 High output #1 EOSR08 Pmn Event Output Set 8 8 read-write 0 No effect on output #0 1 High output #1 EOSR09 Pmn Event Output Set 9 9 read-write 0 No effect on output #0 1 High output #1 EOSR10 Pmn Event Output Set 10 10 read-write 0 No effect on output #0 1 High output #1 EOSR11 Pmn Event Output Set 11 11 read-write 0 No effect on output #0 1 High output #1 EOSR12 Pmn Event Output Set 12 12 read-write 0 No effect on output #0 1 High output #1 EOSR13 Pmn Event Output Set 13 13 read-write 0 No effect on output #0 1 High output #1 EOSR14 Pmn Event Output Set 14 14 read-write 0 No effect on output #0 1 High output #1 EOSR15 Pmn Event Output Set 15 15 read-write 0 No effect on output #0 1 High output #1 EORR00 Pmn Event Output Reset 16 16 read-write 0 No effect on output #0 1 Low output #1 EORR01 Pmn Event Output Reset 17 17 read-write 0 No effect on output #0 1 Low output #1 EORR02 Pmn Event Output Reset 18 18 read-write 0 No effect on output #0 1 Low output #1 EORR03 Pmn Event Output Reset 19 19 read-write 0 No effect on output #0 1 Low output #1 EORR04 Pmn Event Output Reset 20 20 read-write 0 No effect on output #0 1 Low output #1 EORR05 Pmn Event Output Reset 21 21 read-write 0 No effect on output #0 1 Low output #1 EORR06 Pmn Event Output Reset 22 22 read-write 0 No effect on output #0 1 Low output #1 EORR07 Pmn Event Output Reset 23 23 read-write 0 No effect on output #0 1 Low output #1 EORR08 Pmn Event Output Reset 24 24 read-write 0 No effect on output #0 1 Low output #1 EORR09 Pmn Event Output Reset 25 25 read-write 0 No effect on output #0 1 Low output #1 EORR10 Pmn Event Output Reset 26 26 read-write 0 No effect on output #0 1 Low output #1 EORR11 Pmn Event Output Reset 27 27 read-write 0 No effect on output #0 1 Low output #1 EORR12 Pmn Event Output Reset 28 28 read-write 0 No effect on output #0 1 Low output #1 EORR13 Pmn Event Output Reset 29 29 read-write 0 No effect on output #0 1 Low output #1 EORR14 Pmn Event Output Reset 30 30 read-write 0 No effect on output #0 1 Low output #1 EORR15 Pmn Event Output Reset 31 31 read-write 0 No effect on output #0 1 Low output #1 EOSR Port Control Register 4 PCNTR4 0x00C 16 read-write 0x0000 0xffff EOSR00 Pmn Event Output Set 0 0 read-write 0 No effect on output #0 1 High output #1 EOSR01 Pmn Event Output Set 1 1 read-write 0 No effect on output #0 1 High output #1 EOSR02 Pmn Event Output Set 2 2 read-write 0 No effect on output #0 1 High output #1 EOSR03 Pmn Event Output Set 3 3 read-write 0 No effect on output #0 1 High output #1 EOSR04 Pmn Event Output Set 4 4 read-write 0 No effect on output #0 1 High output #1 EOSR05 Pmn Event Output Set 5 5 read-write 0 No effect on output #0 1 High output #1 EOSR06 Pmn Event Output Set 6 6 read-write 0 No effect on output #0 1 High output #1 EOSR07 Pmn Event Output Set 7 7 read-write 0 No effect on output #0 1 High output #1 EOSR08 Pmn Event Output Set 8 8 read-write 0 No effect on output #0 1 High output #1 EOSR09 Pmn Event Output Set 9 9 read-write 0 No effect on output #0 1 High output #1 EOSR10 Pmn Event Output Set 10 10 read-write 0 No effect on output #0 1 High output #1 EOSR11 Pmn Event Output Set 11 11 read-write 0 No effect on output #0 1 High output #1 EOSR12 Pmn Event Output Set 12 12 read-write 0 No effect on output #0 1 High output #1 EOSR13 Pmn Event Output Set 13 13 read-write 0 No effect on output #0 1 High output #1 EOSR14 Pmn Event Output Set 14 14 read-write 0 No effect on output #0 1 High output #1 EOSR15 Pmn Event Output Set 15 15 read-write 0 No effect on output #0 1 High output #1 EORR Port Control Register 4 PCNTR4 0x00E 16 read-write 0x0000 0xffff EORR00 Pmn Event Output Reset 0 0 read-write 0 No effect on output #0 1 Low output #1 EORR01 Pmn Event Output Reset 1 1 read-write 0 No effect on output #0 1 Low output #1 EORR02 Pmn Event Output Reset 2 2 read-write 0 No effect on output #0 1 Low output #1 EORR03 Pmn Event Output Reset 3 3 read-write 0 No effect on output #0 1 Low output #1 EORR04 Pmn Event Output Reset 4 4 read-write 0 No effect on output #0 1 Low output #1 EORR05 Pmn Event Output Reset 5 5 read-write 0 No effect on output #0 1 Low output #1 EORR06 Pmn Event Output Reset 6 6 read-write 0 No effect on output #0 1 Low output #1 EORR07 Pmn Event Output Reset 7 7 read-write 0 No effect on output #0 1 Low output #1 EORR08 Pmn Event Output Reset 8 8 read-write 0 No effect on output #0 1 Low output #1 EORR09 Pmn Event Output Reset 9 9 read-write 0 No effect on output #0 1 Low output #1 EORR10 Pmn Event Output Reset 10 10 read-write 0 No effect on output #0 1 Low output #1 EORR11 Pmn Event Output Reset 11 11 read-write 0 No effect on output #0 1 Low output #1 EORR12 Pmn Event Output Reset 12 12 read-write 0 No effect on output #0 1 Low output #1 EORR13 Pmn Event Output Reset 13 13 read-write 0 No effect on output #0 1 Low output #1 EORR14 Pmn Event Output Reset 14 14 read-write 0 No effect on output #0 1 Low output #1 EORR15 Pmn Event Output Reset 15 15 read-write 0 No effect on output #0 1 Low output #1 PORTC Port C Control Registers 0x4001F180 0x00 16 registers PCNTR1 Port Control Register 1 0x000 32 read-write 0x00000000 0xffffffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 31 read-write 0 Low output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x000 16 read-write 0x0000 0xffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR Port Control Register 1 PCNTR1 0x002 16 read-write 0x0000 0xffff PODR00 Pmn Output Data 0 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 15 read-write 0 Low output #0 1 High output #1 PCNTR2 Port Control Register 2 0x004 32 read-only 0x00000000 0xffff0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 EIDR00 Port Event Input Data 16 16 read-only 0 Low input #0 1 High input #1 EIDR01 Port Event Input Data 17 17 read-only 0 Low input #0 1 High input #1 EIDR02 Port Event Input Data 18 18 read-only 0 Low input #0 1 High input #1 EIDR03 Port Event Input Data 19 19 read-only 0 Low input #0 1 High input #1 EIDR04 Port Event Input Data 20 20 read-only 0 Low input #0 1 High input #1 EIDR05 Port Event Input Data 21 21 read-only 0 Low input #0 1 High input #1 EIDR06 Port Event Input Data 22 22 read-only 0 Low input #0 1 High input #1 EIDR07 Port Event Input Data 23 23 read-only 0 Low input #0 1 High input #1 EIDR08 Port Event Input Data 24 24 read-only 0 Low input #0 1 High input #1 EIDR09 Port Event Input Data 25 25 read-only 0 Low input #0 1 High input #1 EIDR10 Port Event Input Data 26 26 read-only 0 Low input #0 1 High input #1 EIDR11 Port Event Input Data 27 27 read-only 0 Low input #0 1 High input #1 EIDR12 Port Event Input Data 28 28 read-only 0 Low input #0 1 High input #1 EIDR13 Port Event Input Data 29 29 read-only 0 Low input #0 1 High input #1 EIDR14 Port Event Input Data 30 30 read-only 0 Low input #0 1 High input #1 EIDR15 Port Event Input Data 31 31 read-only 0 Low input #0 1 High input #1 PIDR Port Control Register 2 PCNTR2 0x004 16 read-only 0x0000 0x0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 EIDR Port Control Register 2 PCNTR2 0x006 16 read-only 0x0000 0xffff EIDR00 Port Event Input Data 0 0 read-only 0 Low input #0 1 High input #1 EIDR01 Port Event Input Data 1 1 read-only 0 Low input #0 1 High input #1 EIDR02 Port Event Input Data 2 2 read-only 0 Low input #0 1 High input #1 EIDR03 Port Event Input Data 3 3 read-only 0 Low input #0 1 High input #1 EIDR04 Port Event Input Data 4 4 read-only 0 Low input #0 1 High input #1 EIDR05 Port Event Input Data 5 5 read-only 0 Low input #0 1 High input #1 EIDR06 Port Event Input Data 6 6 read-only 0 Low input #0 1 High input #1 EIDR07 Port Event Input Data 7 7 read-only 0 Low input #0 1 High input #1 EIDR08 Port Event Input Data 8 8 read-only 0 Low input #0 1 High input #1 EIDR09 Port Event Input Data 9 9 read-only 0 Low input #0 1 High input #1 EIDR10 Port Event Input Data 10 10 read-only 0 Low input #0 1 High input #1 EIDR11 Port Event Input Data 11 11 read-only 0 Low input #0 1 High input #1 EIDR12 Port Event Input Data 12 12 read-only 0 Low input #0 1 High input #1 EIDR13 Port Event Input Data 13 13 read-only 0 Low input #0 1 High input #1 EIDR14 Port Event Input Data 14 14 read-only 0 Low input #0 1 High input #1 EIDR15 Port Event Input Data 15 15 read-only 0 Low input #0 1 High input #1 PCNTR3 Port Control Register 3 0x008 32 write-only 0x00000000 0xffffffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR00 Pmn Output Reset 16 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 31 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0x008 16 write-only 0x0000 0xffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR Port Control Register 3 PCNTR3 0x00A 16 write-only 0x0000 0xffff PORR00 Pmn Output Reset 0 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 15 write-only 0 No effect on output #0 1 Low output #1 PCNTR4 Port Control Register 4 0x00C 32 read-write 0x00000000 0xffffffff EOSR00 Pmn Event Output Set 0 0 read-write 0 No effect on output #0 1 High output #1 EOSR01 Pmn Event Output Set 1 1 read-write 0 No effect on output #0 1 High output #1 EOSR02 Pmn Event Output Set 2 2 read-write 0 No effect on output #0 1 High output #1 EOSR03 Pmn Event Output Set 3 3 read-write 0 No effect on output #0 1 High output #1 EOSR04 Pmn Event Output Set 4 4 read-write 0 No effect on output #0 1 High output #1 EOSR05 Pmn Event Output Set 5 5 read-write 0 No effect on output #0 1 High output #1 EOSR06 Pmn Event Output Set 6 6 read-write 0 No effect on output #0 1 High output #1 EOSR07 Pmn Event Output Set 7 7 read-write 0 No effect on output #0 1 High output #1 EOSR08 Pmn Event Output Set 8 8 read-write 0 No effect on output #0 1 High output #1 EOSR09 Pmn Event Output Set 9 9 read-write 0 No effect on output #0 1 High output #1 EOSR10 Pmn Event Output Set 10 10 read-write 0 No effect on output #0 1 High output #1 EOSR11 Pmn Event Output Set 11 11 read-write 0 No effect on output #0 1 High output #1 EOSR12 Pmn Event Output Set 12 12 read-write 0 No effect on output #0 1 High output #1 EOSR13 Pmn Event Output Set 13 13 read-write 0 No effect on output #0 1 High output #1 EOSR14 Pmn Event Output Set 14 14 read-write 0 No effect on output #0 1 High output #1 EOSR15 Pmn Event Output Set 15 15 read-write 0 No effect on output #0 1 High output #1 EORR00 Pmn Event Output Reset 16 16 read-write 0 No effect on output #0 1 Low output #1 EORR01 Pmn Event Output Reset 17 17 read-write 0 No effect on output #0 1 Low output #1 EORR02 Pmn Event Output Reset 18 18 read-write 0 No effect on output #0 1 Low output #1 EORR03 Pmn Event Output Reset 19 19 read-write 0 No effect on output #0 1 Low output #1 EORR04 Pmn Event Output Reset 20 20 read-write 0 No effect on output #0 1 Low output #1 EORR05 Pmn Event Output Reset 21 21 read-write 0 No effect on output #0 1 Low output #1 EORR06 Pmn Event Output Reset 22 22 read-write 0 No effect on output #0 1 Low output #1 EORR07 Pmn Event Output Reset 23 23 read-write 0 No effect on output #0 1 Low output #1 EORR08 Pmn Event Output Reset 24 24 read-write 0 No effect on output #0 1 Low output #1 EORR09 Pmn Event Output Reset 25 25 read-write 0 No effect on output #0 1 Low output #1 EORR10 Pmn Event Output Reset 26 26 read-write 0 No effect on output #0 1 Low output #1 EORR11 Pmn Event Output Reset 27 27 read-write 0 No effect on output #0 1 Low output #1 EORR12 Pmn Event Output Reset 28 28 read-write 0 No effect on output #0 1 Low output #1 EORR13 Pmn Event Output Reset 29 29 read-write 0 No effect on output #0 1 Low output #1 EORR14 Pmn Event Output Reset 30 30 read-write 0 No effect on output #0 1 Low output #1 EORR15 Pmn Event Output Reset 31 31 read-write 0 No effect on output #0 1 Low output #1 EOSR Port Control Register 4 PCNTR4 0x00C 16 read-write 0x0000 0xffff EOSR00 Pmn Event Output Set 0 0 read-write 0 No effect on output #0 1 High output #1 EOSR01 Pmn Event Output Set 1 1 read-write 0 No effect on output #0 1 High output #1 EOSR02 Pmn Event Output Set 2 2 read-write 0 No effect on output #0 1 High output #1 EOSR03 Pmn Event Output Set 3 3 read-write 0 No effect on output #0 1 High output #1 EOSR04 Pmn Event Output Set 4 4 read-write 0 No effect on output #0 1 High output #1 EOSR05 Pmn Event Output Set 5 5 read-write 0 No effect on output #0 1 High output #1 EOSR06 Pmn Event Output Set 6 6 read-write 0 No effect on output #0 1 High output #1 EOSR07 Pmn Event Output Set 7 7 read-write 0 No effect on output #0 1 High output #1 EOSR08 Pmn Event Output Set 8 8 read-write 0 No effect on output #0 1 High output #1 EOSR09 Pmn Event Output Set 9 9 read-write 0 No effect on output #0 1 High output #1 EOSR10 Pmn Event Output Set 10 10 read-write 0 No effect on output #0 1 High output #1 EOSR11 Pmn Event Output Set 11 11 read-write 0 No effect on output #0 1 High output #1 EOSR12 Pmn Event Output Set 12 12 read-write 0 No effect on output #0 1 High output #1 EOSR13 Pmn Event Output Set 13 13 read-write 0 No effect on output #0 1 High output #1 EOSR14 Pmn Event Output Set 14 14 read-write 0 No effect on output #0 1 High output #1 EOSR15 Pmn Event Output Set 15 15 read-write 0 No effect on output #0 1 High output #1 EORR Port Control Register 4 PCNTR4 0x00E 16 read-write 0x0000 0xffff EORR00 Pmn Event Output Reset 0 0 read-write 0 No effect on output #0 1 Low output #1 EORR01 Pmn Event Output Reset 1 1 read-write 0 No effect on output #0 1 Low output #1 EORR02 Pmn Event Output Reset 2 2 read-write 0 No effect on output #0 1 Low output #1 EORR03 Pmn Event Output Reset 3 3 read-write 0 No effect on output #0 1 Low output #1 EORR04 Pmn Event Output Reset 4 4 read-write 0 No effect on output #0 1 Low output #1 EORR05 Pmn Event Output Reset 5 5 read-write 0 No effect on output #0 1 Low output #1 EORR06 Pmn Event Output Reset 6 6 read-write 0 No effect on output #0 1 Low output #1 EORR07 Pmn Event Output Reset 7 7 read-write 0 No effect on output #0 1 Low output #1 EORR08 Pmn Event Output Reset 8 8 read-write 0 No effect on output #0 1 Low output #1 EORR09 Pmn Event Output Reset 9 9 read-write 0 No effect on output #0 1 Low output #1 EORR10 Pmn Event Output Reset 10 10 read-write 0 No effect on output #0 1 Low output #1 EORR11 Pmn Event Output Reset 11 11 read-write 0 No effect on output #0 1 Low output #1 EORR12 Pmn Event Output Reset 12 12 read-write 0 No effect on output #0 1 Low output #1 EORR13 Pmn Event Output Reset 13 13 read-write 0 No effect on output #0 1 Low output #1 EORR14 Pmn Event Output Reset 14 14 read-write 0 No effect on output #0 1 Low output #1 EORR15 Pmn Event Output Reset 15 15 read-write 0 No effect on output #0 1 Low output #1 PORTD Port D Control Registers 0x4001F1A0 0x00 16 registers PCNTR1 Port Control Register 1 0x000 32 read-write 0x00000000 0xffffffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 31 read-write 0 Low output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x000 16 read-write 0x0000 0xffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR Port Control Register 1 PCNTR1 0x002 16 read-write 0x0000 0xffff PODR00 Pmn Output Data 0 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 15 read-write 0 Low output #0 1 High output #1 PCNTR2 Port Control Register 2 0x004 32 read-only 0x00000000 0xffff0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 EIDR00 Port Event Input Data 16 16 read-only 0 Low input #0 1 High input #1 EIDR01 Port Event Input Data 17 17 read-only 0 Low input #0 1 High input #1 EIDR02 Port Event Input Data 18 18 read-only 0 Low input #0 1 High input #1 EIDR03 Port Event Input Data 19 19 read-only 0 Low input #0 1 High input #1 EIDR04 Port Event Input Data 20 20 read-only 0 Low input #0 1 High input #1 EIDR05 Port Event Input Data 21 21 read-only 0 Low input #0 1 High input #1 EIDR06 Port Event Input Data 22 22 read-only 0 Low input #0 1 High input #1 EIDR07 Port Event Input Data 23 23 read-only 0 Low input #0 1 High input #1 EIDR08 Port Event Input Data 24 24 read-only 0 Low input #0 1 High input #1 EIDR09 Port Event Input Data 25 25 read-only 0 Low input #0 1 High input #1 EIDR10 Port Event Input Data 26 26 read-only 0 Low input #0 1 High input #1 EIDR11 Port Event Input Data 27 27 read-only 0 Low input #0 1 High input #1 EIDR12 Port Event Input Data 28 28 read-only 0 Low input #0 1 High input #1 EIDR13 Port Event Input Data 29 29 read-only 0 Low input #0 1 High input #1 EIDR14 Port Event Input Data 30 30 read-only 0 Low input #0 1 High input #1 EIDR15 Port Event Input Data 31 31 read-only 0 Low input #0 1 High input #1 PIDR Port Control Register 2 PCNTR2 0x004 16 read-only 0x0000 0x0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 EIDR Port Control Register 2 PCNTR2 0x006 16 read-only 0x0000 0xffff EIDR00 Port Event Input Data 0 0 read-only 0 Low input #0 1 High input #1 EIDR01 Port Event Input Data 1 1 read-only 0 Low input #0 1 High input #1 EIDR02 Port Event Input Data 2 2 read-only 0 Low input #0 1 High input #1 EIDR03 Port Event Input Data 3 3 read-only 0 Low input #0 1 High input #1 EIDR04 Port Event Input Data 4 4 read-only 0 Low input #0 1 High input #1 EIDR05 Port Event Input Data 5 5 read-only 0 Low input #0 1 High input #1 EIDR06 Port Event Input Data 6 6 read-only 0 Low input #0 1 High input #1 EIDR07 Port Event Input Data 7 7 read-only 0 Low input #0 1 High input #1 EIDR08 Port Event Input Data 8 8 read-only 0 Low input #0 1 High input #1 EIDR09 Port Event Input Data 9 9 read-only 0 Low input #0 1 High input #1 EIDR10 Port Event Input Data 10 10 read-only 0 Low input #0 1 High input #1 EIDR11 Port Event Input Data 11 11 read-only 0 Low input #0 1 High input #1 EIDR12 Port Event Input Data 12 12 read-only 0 Low input #0 1 High input #1 EIDR13 Port Event Input Data 13 13 read-only 0 Low input #0 1 High input #1 EIDR14 Port Event Input Data 14 14 read-only 0 Low input #0 1 High input #1 EIDR15 Port Event Input Data 15 15 read-only 0 Low input #0 1 High input #1 PCNTR3 Port Control Register 3 0x008 32 write-only 0x00000000 0xffffffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR00 Pmn Output Reset 16 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 31 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0x008 16 write-only 0x0000 0xffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR Port Control Register 3 PCNTR3 0x00A 16 write-only 0x0000 0xffff PORR00 Pmn Output Reset 0 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 15 write-only 0 No effect on output #0 1 Low output #1 PCNTR4 Port Control Register 4 0x00C 32 read-write 0x00000000 0xffffffff EOSR00 Pmn Event Output Set 0 0 read-write 0 No effect on output #0 1 High output #1 EOSR01 Pmn Event Output Set 1 1 read-write 0 No effect on output #0 1 High output #1 EOSR02 Pmn Event Output Set 2 2 read-write 0 No effect on output #0 1 High output #1 EOSR03 Pmn Event Output Set 3 3 read-write 0 No effect on output #0 1 High output #1 EOSR04 Pmn Event Output Set 4 4 read-write 0 No effect on output #0 1 High output #1 EOSR05 Pmn Event Output Set 5 5 read-write 0 No effect on output #0 1 High output #1 EOSR06 Pmn Event Output Set 6 6 read-write 0 No effect on output #0 1 High output #1 EOSR07 Pmn Event Output Set 7 7 read-write 0 No effect on output #0 1 High output #1 EOSR08 Pmn Event Output Set 8 8 read-write 0 No effect on output #0 1 High output #1 EOSR09 Pmn Event Output Set 9 9 read-write 0 No effect on output #0 1 High output #1 EOSR10 Pmn Event Output Set 10 10 read-write 0 No effect on output #0 1 High output #1 EOSR11 Pmn Event Output Set 11 11 read-write 0 No effect on output #0 1 High output #1 EOSR12 Pmn Event Output Set 12 12 read-write 0 No effect on output #0 1 High output #1 EOSR13 Pmn Event Output Set 13 13 read-write 0 No effect on output #0 1 High output #1 EOSR14 Pmn Event Output Set 14 14 read-write 0 No effect on output #0 1 High output #1 EOSR15 Pmn Event Output Set 15 15 read-write 0 No effect on output #0 1 High output #1 EORR00 Pmn Event Output Reset 16 16 read-write 0 No effect on output #0 1 Low output #1 EORR01 Pmn Event Output Reset 17 17 read-write 0 No effect on output #0 1 Low output #1 EORR02 Pmn Event Output Reset 18 18 read-write 0 No effect on output #0 1 Low output #1 EORR03 Pmn Event Output Reset 19 19 read-write 0 No effect on output #0 1 Low output #1 EORR04 Pmn Event Output Reset 20 20 read-write 0 No effect on output #0 1 Low output #1 EORR05 Pmn Event Output Reset 21 21 read-write 0 No effect on output #0 1 Low output #1 EORR06 Pmn Event Output Reset 22 22 read-write 0 No effect on output #0 1 Low output #1 EORR07 Pmn Event Output Reset 23 23 read-write 0 No effect on output #0 1 Low output #1 EORR08 Pmn Event Output Reset 24 24 read-write 0 No effect on output #0 1 Low output #1 EORR09 Pmn Event Output Reset 25 25 read-write 0 No effect on output #0 1 Low output #1 EORR10 Pmn Event Output Reset 26 26 read-write 0 No effect on output #0 1 Low output #1 EORR11 Pmn Event Output Reset 27 27 read-write 0 No effect on output #0 1 Low output #1 EORR12 Pmn Event Output Reset 28 28 read-write 0 No effect on output #0 1 Low output #1 EORR13 Pmn Event Output Reset 29 29 read-write 0 No effect on output #0 1 Low output #1 EORR14 Pmn Event Output Reset 30 30 read-write 0 No effect on output #0 1 Low output #1 EORR15 Pmn Event Output Reset 31 31 read-write 0 No effect on output #0 1 Low output #1 EOSR Port Control Register 4 PCNTR4 0x00C 16 read-write 0x0000 0xffff EOSR00 Pmn Event Output Set 0 0 read-write 0 No effect on output #0 1 High output #1 EOSR01 Pmn Event Output Set 1 1 read-write 0 No effect on output #0 1 High output #1 EOSR02 Pmn Event Output Set 2 2 read-write 0 No effect on output #0 1 High output #1 EOSR03 Pmn Event Output Set 3 3 read-write 0 No effect on output #0 1 High output #1 EOSR04 Pmn Event Output Set 4 4 read-write 0 No effect on output #0 1 High output #1 EOSR05 Pmn Event Output Set 5 5 read-write 0 No effect on output #0 1 High output #1 EOSR06 Pmn Event Output Set 6 6 read-write 0 No effect on output #0 1 High output #1 EOSR07 Pmn Event Output Set 7 7 read-write 0 No effect on output #0 1 High output #1 EOSR08 Pmn Event Output Set 8 8 read-write 0 No effect on output #0 1 High output #1 EOSR09 Pmn Event Output Set 9 9 read-write 0 No effect on output #0 1 High output #1 EOSR10 Pmn Event Output Set 10 10 read-write 0 No effect on output #0 1 High output #1 EOSR11 Pmn Event Output Set 11 11 read-write 0 No effect on output #0 1 High output #1 EOSR12 Pmn Event Output Set 12 12 read-write 0 No effect on output #0 1 High output #1 EOSR13 Pmn Event Output Set 13 13 read-write 0 No effect on output #0 1 High output #1 EOSR14 Pmn Event Output Set 14 14 read-write 0 No effect on output #0 1 High output #1 EOSR15 Pmn Event Output Set 15 15 read-write 0 No effect on output #0 1 High output #1 EORR Port Control Register 4 PCNTR4 0x00E 16 read-write 0x0000 0xffff EORR00 Pmn Event Output Reset 0 0 read-write 0 No effect on output #0 1 Low output #1 EORR01 Pmn Event Output Reset 1 1 read-write 0 No effect on output #0 1 Low output #1 EORR02 Pmn Event Output Reset 2 2 read-write 0 No effect on output #0 1 Low output #1 EORR03 Pmn Event Output Reset 3 3 read-write 0 No effect on output #0 1 Low output #1 EORR04 Pmn Event Output Reset 4 4 read-write 0 No effect on output #0 1 Low output #1 EORR05 Pmn Event Output Reset 5 5 read-write 0 No effect on output #0 1 Low output #1 EORR06 Pmn Event Output Reset 6 6 read-write 0 No effect on output #0 1 Low output #1 EORR07 Pmn Event Output Reset 7 7 read-write 0 No effect on output #0 1 Low output #1 EORR08 Pmn Event Output Reset 8 8 read-write 0 No effect on output #0 1 Low output #1 EORR09 Pmn Event Output Reset 9 9 read-write 0 No effect on output #0 1 Low output #1 EORR10 Pmn Event Output Reset 10 10 read-write 0 No effect on output #0 1 Low output #1 EORR11 Pmn Event Output Reset 11 11 read-write 0 No effect on output #0 1 Low output #1 EORR12 Pmn Event Output Reset 12 12 read-write 0 No effect on output #0 1 Low output #1 EORR13 Pmn Event Output Reset 13 13 read-write 0 No effect on output #0 1 Low output #1 EORR14 Pmn Event Output Reset 14 14 read-write 0 No effect on output #0 1 Low output #1 EORR15 Pmn Event Output Reset 15 15 read-write 0 No effect on output #0 1 Low output #1 PORTE Port E Control Registers 0x4001F1C0 0x00 16 registers PCNTR1 Port Control Register 1 0x000 32 read-write 0x00000000 0xffffffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 31 read-write 0 Low output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x000 16 read-write 0x0000 0xffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR Port Control Register 1 PCNTR1 0x002 16 read-write 0x0000 0xffff PODR00 Pmn Output Data 0 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 15 read-write 0 Low output #0 1 High output #1 PCNTR2 Port Control Register 2 0x004 32 read-only 0x00000000 0xffff0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 EIDR00 Port Event Input Data 16 16 read-only 0 Low input #0 1 High input #1 EIDR01 Port Event Input Data 17 17 read-only 0 Low input #0 1 High input #1 EIDR02 Port Event Input Data 18 18 read-only 0 Low input #0 1 High input #1 EIDR03 Port Event Input Data 19 19 read-only 0 Low input #0 1 High input #1 EIDR04 Port Event Input Data 20 20 read-only 0 Low input #0 1 High input #1 EIDR05 Port Event Input Data 21 21 read-only 0 Low input #0 1 High input #1 EIDR06 Port Event Input Data 22 22 read-only 0 Low input #0 1 High input #1 EIDR07 Port Event Input Data 23 23 read-only 0 Low input #0 1 High input #1 EIDR08 Port Event Input Data 24 24 read-only 0 Low input #0 1 High input #1 EIDR09 Port Event Input Data 25 25 read-only 0 Low input #0 1 High input #1 EIDR10 Port Event Input Data 26 26 read-only 0 Low input #0 1 High input #1 EIDR11 Port Event Input Data 27 27 read-only 0 Low input #0 1 High input #1 EIDR12 Port Event Input Data 28 28 read-only 0 Low input #0 1 High input #1 EIDR13 Port Event Input Data 29 29 read-only 0 Low input #0 1 High input #1 EIDR14 Port Event Input Data 30 30 read-only 0 Low input #0 1 High input #1 EIDR15 Port Event Input Data 31 31 read-only 0 Low input #0 1 High input #1 PIDR Port Control Register 2 PCNTR2 0x004 16 read-only 0x0000 0x0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 EIDR Port Control Register 2 PCNTR2 0x006 16 read-only 0x0000 0xffff EIDR00 Port Event Input Data 0 0 read-only 0 Low input #0 1 High input #1 EIDR01 Port Event Input Data 1 1 read-only 0 Low input #0 1 High input #1 EIDR02 Port Event Input Data 2 2 read-only 0 Low input #0 1 High input #1 EIDR03 Port Event Input Data 3 3 read-only 0 Low input #0 1 High input #1 EIDR04 Port Event Input Data 4 4 read-only 0 Low input #0 1 High input #1 EIDR05 Port Event Input Data 5 5 read-only 0 Low input #0 1 High input #1 EIDR06 Port Event Input Data 6 6 read-only 0 Low input #0 1 High input #1 EIDR07 Port Event Input Data 7 7 read-only 0 Low input #0 1 High input #1 EIDR08 Port Event Input Data 8 8 read-only 0 Low input #0 1 High input #1 EIDR09 Port Event Input Data 9 9 read-only 0 Low input #0 1 High input #1 EIDR10 Port Event Input Data 10 10 read-only 0 Low input #0 1 High input #1 EIDR11 Port Event Input Data 11 11 read-only 0 Low input #0 1 High input #1 EIDR12 Port Event Input Data 12 12 read-only 0 Low input #0 1 High input #1 EIDR13 Port Event Input Data 13 13 read-only 0 Low input #0 1 High input #1 EIDR14 Port Event Input Data 14 14 read-only 0 Low input #0 1 High input #1 EIDR15 Port Event Input Data 15 15 read-only 0 Low input #0 1 High input #1 PCNTR3 Port Control Register 3 0x008 32 write-only 0x00000000 0xffffffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR00 Pmn Output Reset 16 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 31 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0x008 16 write-only 0x0000 0xffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR Port Control Register 3 PCNTR3 0x00A 16 write-only 0x0000 0xffff PORR00 Pmn Output Reset 0 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 15 write-only 0 No effect on output #0 1 Low output #1 PCNTR4 Port Control Register 4 0x00C 32 read-write 0x00000000 0xffffffff EOSR00 Pmn Event Output Set 0 0 read-write 0 No effect on output #0 1 High output #1 EOSR01 Pmn Event Output Set 1 1 read-write 0 No effect on output #0 1 High output #1 EOSR02 Pmn Event Output Set 2 2 read-write 0 No effect on output #0 1 High output #1 EOSR03 Pmn Event Output Set 3 3 read-write 0 No effect on output #0 1 High output #1 EOSR04 Pmn Event Output Set 4 4 read-write 0 No effect on output #0 1 High output #1 EOSR05 Pmn Event Output Set 5 5 read-write 0 No effect on output #0 1 High output #1 EOSR06 Pmn Event Output Set 6 6 read-write 0 No effect on output #0 1 High output #1 EOSR07 Pmn Event Output Set 7 7 read-write 0 No effect on output #0 1 High output #1 EOSR08 Pmn Event Output Set 8 8 read-write 0 No effect on output #0 1 High output #1 EOSR09 Pmn Event Output Set 9 9 read-write 0 No effect on output #0 1 High output #1 EOSR10 Pmn Event Output Set 10 10 read-write 0 No effect on output #0 1 High output #1 EOSR11 Pmn Event Output Set 11 11 read-write 0 No effect on output #0 1 High output #1 EOSR12 Pmn Event Output Set 12 12 read-write 0 No effect on output #0 1 High output #1 EOSR13 Pmn Event Output Set 13 13 read-write 0 No effect on output #0 1 High output #1 EOSR14 Pmn Event Output Set 14 14 read-write 0 No effect on output #0 1 High output #1 EOSR15 Pmn Event Output Set 15 15 read-write 0 No effect on output #0 1 High output #1 EORR00 Pmn Event Output Reset 16 16 read-write 0 No effect on output #0 1 Low output #1 EORR01 Pmn Event Output Reset 17 17 read-write 0 No effect on output #0 1 Low output #1 EORR02 Pmn Event Output Reset 18 18 read-write 0 No effect on output #0 1 Low output #1 EORR03 Pmn Event Output Reset 19 19 read-write 0 No effect on output #0 1 Low output #1 EORR04 Pmn Event Output Reset 20 20 read-write 0 No effect on output #0 1 Low output #1 EORR05 Pmn Event Output Reset 21 21 read-write 0 No effect on output #0 1 Low output #1 EORR06 Pmn Event Output Reset 22 22 read-write 0 No effect on output #0 1 Low output #1 EORR07 Pmn Event Output Reset 23 23 read-write 0 No effect on output #0 1 Low output #1 EORR08 Pmn Event Output Reset 24 24 read-write 0 No effect on output #0 1 Low output #1 EORR09 Pmn Event Output Reset 25 25 read-write 0 No effect on output #0 1 Low output #1 EORR10 Pmn Event Output Reset 26 26 read-write 0 No effect on output #0 1 Low output #1 EORR11 Pmn Event Output Reset 27 27 read-write 0 No effect on output #0 1 Low output #1 EORR12 Pmn Event Output Reset 28 28 read-write 0 No effect on output #0 1 Low output #1 EORR13 Pmn Event Output Reset 29 29 read-write 0 No effect on output #0 1 Low output #1 EORR14 Pmn Event Output Reset 30 30 read-write 0 No effect on output #0 1 Low output #1 EORR15 Pmn Event Output Reset 31 31 read-write 0 No effect on output #0 1 Low output #1 EOSR Port Control Register 4 PCNTR4 0x00C 16 read-write 0x0000 0xffff EOSR00 Pmn Event Output Set 0 0 read-write 0 No effect on output #0 1 High output #1 EOSR01 Pmn Event Output Set 1 1 read-write 0 No effect on output #0 1 High output #1 EOSR02 Pmn Event Output Set 2 2 read-write 0 No effect on output #0 1 High output #1 EOSR03 Pmn Event Output Set 3 3 read-write 0 No effect on output #0 1 High output #1 EOSR04 Pmn Event Output Set 4 4 read-write 0 No effect on output #0 1 High output #1 EOSR05 Pmn Event Output Set 5 5 read-write 0 No effect on output #0 1 High output #1 EOSR06 Pmn Event Output Set 6 6 read-write 0 No effect on output #0 1 High output #1 EOSR07 Pmn Event Output Set 7 7 read-write 0 No effect on output #0 1 High output #1 EOSR08 Pmn Event Output Set 8 8 read-write 0 No effect on output #0 1 High output #1 EOSR09 Pmn Event Output Set 9 9 read-write 0 No effect on output #0 1 High output #1 EOSR10 Pmn Event Output Set 10 10 read-write 0 No effect on output #0 1 High output #1 EOSR11 Pmn Event Output Set 11 11 read-write 0 No effect on output #0 1 High output #1 EOSR12 Pmn Event Output Set 12 12 read-write 0 No effect on output #0 1 High output #1 EOSR13 Pmn Event Output Set 13 13 read-write 0 No effect on output #0 1 High output #1 EOSR14 Pmn Event Output Set 14 14 read-write 0 No effect on output #0 1 High output #1 EOSR15 Pmn Event Output Set 15 15 read-write 0 No effect on output #0 1 High output #1 EORR Port Control Register 4 PCNTR4 0x00E 16 read-write 0x0000 0xffff EORR00 Pmn Event Output Reset 0 0 read-write 0 No effect on output #0 1 Low output #1 EORR01 Pmn Event Output Reset 1 1 read-write 0 No effect on output #0 1 Low output #1 EORR02 Pmn Event Output Reset 2 2 read-write 0 No effect on output #0 1 Low output #1 EORR03 Pmn Event Output Reset 3 3 read-write 0 No effect on output #0 1 Low output #1 EORR04 Pmn Event Output Reset 4 4 read-write 0 No effect on output #0 1 Low output #1 EORR05 Pmn Event Output Reset 5 5 read-write 0 No effect on output #0 1 Low output #1 EORR06 Pmn Event Output Reset 6 6 read-write 0 No effect on output #0 1 Low output #1 EORR07 Pmn Event Output Reset 7 7 read-write 0 No effect on output #0 1 Low output #1 EORR08 Pmn Event Output Reset 8 8 read-write 0 No effect on output #0 1 Low output #1 EORR09 Pmn Event Output Reset 9 9 read-write 0 No effect on output #0 1 Low output #1 EORR10 Pmn Event Output Reset 10 10 read-write 0 No effect on output #0 1 Low output #1 EORR11 Pmn Event Output Reset 11 11 read-write 0 No effect on output #0 1 Low output #1 EORR12 Pmn Event Output Reset 12 12 read-write 0 No effect on output #0 1 Low output #1 EORR13 Pmn Event Output Reset 13 13 read-write 0 No effect on output #0 1 Low output #1 EORR14 Pmn Event Output Reset 14 14 read-write 0 No effect on output #0 1 Low output #1 EORR15 Pmn Event Output Reset 15 15 read-write 0 No effect on output #0 1 Low output #1 PFS_B Pmn Pin Function Control Register 0x4001F800 0x00 12 registers 0x84 4 registers 0x280 56 registers 0x2B8 20 registers 0x2CC 4 registers 0x2D0 28 registers 0x2F0 172 registers 0x3A0 32 registers 0x50C 1 registers 0x514 1 registers 0x530 2 registers 0x538 2 registers 0x558 2 registers 0x55C 2 registers 0x560 2 registers 0x564 2 registers 0x568 2 registers 2 0x004 0-1 P00%sPFS Port 00%s Pin Function Select Register 0x000 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 2 0x004 0-1 P00%sPFS_HA Port 00%s Pin Function Select Register P00%sPFS 0x000 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 2 0x004 0-1 P00%sPFS_BY Port 00%s Pin Function Select Register P00%sPFS 0x000 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 P002PFS Port 002 Pin Function Select Register 0x008 32 read-write 0x00008000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P002PFS_HA Port 002 Pin Function Select Register P002PFS 0x008 16 read-write 0x8000 0xfffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 P002PFS_BY Port 002 Pin Function Select Register P002PFS 0x008 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 P201PFS Port 201 Pin Function Select Register 0x084 32 read-write 0x00000010 0xfffffffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P201PFS_HA Port 201 Pin Function Select Register P201PFS 0x084 16 read-write 0x0010 0xfffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 P201PFS_BY Port 201 Pin Function Select Register P201PFS 0x084 8 read-write 0x10 0xfd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 6 0x004 0-5 PA0%sPFS Port A0%s Pin Function Select Register 0x280 32 read-write 0x00008000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 6 0x004 0-5 PA0%sPFS_HA Port A0%s Pin Function Select Register PA0%sPFS 0x280 16 read-write 0x8000 0xfffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 6 0x004 0-5 PA0%sPFS_BY Port A0%s Pin Function Select Register PA0%sPFS 0x280 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 4 0x004 6-9 PA0%sPFS Port A0%s Pin Function Select Register 0x298 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 4 0x004 6-9 PA0%sPFS_HA Port A0%s Pin Function Select Register PA0%sPFS 0x298 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 4 0x004 6-9 PA0%sPFS_BY Port A0%s Pin Function Select Register PA0%sPFS 0x298 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 3 0x004 0-2 PA1%sPFS Port A1%s Pin Function Select Register 0x2A8 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 3 0x004 0-2 PA1%sPFS_HA Port A1%s Pin Function Select Register PA1%sPFS 0x2A8 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 3 0x004 0-2 PA1%sPFS_BY Port A1%s Pin Function Select Register PA1%sPFS 0x2A8 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PA13PFS Port A13 Pin Function Select Register 0x2B4 32 read-write 0x00010410 0xfffffffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write PA13PFS_HA Port A13 Pin Function Select Register PA13PFS 0x2B4 16 read-write 0x0410 0xfffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PA13PFS_BY Port A13 Pin Function Select Register PA13PFS 0x2B4 8 read-write 0x10 0xfd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 2 0x004 4-5 PA1%sPFS Port A1%s Pin Function Select Register 0x2B8 32 read-write 0x00010010 0xfffffffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 2 0x004 4-5 PA1%sPFS_HA Port A1%s Pin Function Select Register PA1%sPFS 0x2B8 16 read-write 0x0010 0xfffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 2 0x004 4-5 PA1%sPFS_BY Port A1%s Pin Function Select Register PA1%sPFS 0x2B8 8 read-write 0x10 0xfd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 2 0x004 0-1 PB0%sPFS Port B0%s Pin Function Select Register 0x2C0 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 2 0x004 0-1 PB0%sPFS_HA Port B0%s Pin Function Select Register PB0%sPFS 0x2C0 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 2 0x004 0-1 PB0%sPFS_BY Port B0%s Pin Function Select Register PB0%sPFS 0x2C0 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PB02PFS Port B02 Pin Function Select Register 0x2C8 32 read-write 0x00008000 0xfffefbed PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write PB02PFS_HA Port B02 Pin Function Select Register PB02PFS 0x2C8 16 read-write 0x8000 0xfbed PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PB02PFS_BY Port B02 Pin Function Select Register PB02PFS 0x2C8 8 read-write 0x00 0xed PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PB03PFS Port B03 Pin Function Select Register 0x2CC 32 read-write 0x00010400 0xfffffffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write PB03PFS_HA Port B03 Pin Function Select Register PB03PFS 0x2CC 16 read-write 0x0400 0xfffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PB03PFS_BY Port B03 Pin Function Select Register PB03PFS 0x2CC 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 6 0x004 4-9 PB0%sPFS Port B0%s Pin Function Select Register 0x2D0 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 6 0x004 4-9 PB0%sPFS_HA Port B0%s Pin Function Select Register PB0%sPFS 0x2D0 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 6 0x004 4-9 PB0%sPFS_BY Port B0%s Pin Function Select Register PB0%sPFS 0x2D0 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PB10PFS Port B10 Pin Function Select Register 0x2E8 32 read-write 0x00000000 0xfffe7bed PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write PB10PFS_HA Port B10 Pin Function Select Register PB10PFS 0x2E8 16 read-write 0x0000 0x7bed PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PB10PFS_BY Port B10 Pin Function Select Register PB10PFS 0x2E8 8 read-write 0x00 0xed PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 4 0x004 2-5 PB1%sPFS Port B1%s Pin Function Select Register 0x2F0 32 read-write 0x00000000 0xfffe7bed PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 4 0x004 2-5 PB1%sPFS_HA Port B1%s Pin Function Select Register PB1%sPFS 0x2F0 16 read-write 0x0000 0x7bed PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 4 0x004 2-5 PB1%sPFS_BY Port B1%s Pin Function Select Register PB1%sPFS 0x2F0 8 read-write 0x00 0xed PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 10 0x004 0-9 PC0%sPFS Port C0%s Pin Function Select Register 0x300 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 10 0x004 0-9 PC0%sPFS_HA Port C0%s Pin Function Select Register PC0%sPFS 0x300 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 10 0x004 0-9 PC0%sPFS_BY Port C0%s Pin Function Select Register PC0%sPFS 0x300 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 6 0x004 0-5 PC1%sPFS Port C1%s Pin Function Select Register 0x328 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 6 0x004 0-5 PC1%sPFS_HA Port C1%s Pin Function Select Register PC1%sPFS 0x328 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 6 0x004 0-5 PC1%sPFS_BY Port C1%s Pin Function Select Register PC1%sPFS 0x328 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 10 0x004 0-9 PD0%sPFS Port D0%s Pin Function Select Register 0x340 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 10 0x004 0-9 PD0%sPFS_HA Port D0%s Pin Function Select Register PD0%sPFS 0x340 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 10 0x004 0-9 PD0%sPFS_BY Port D0%s Pin Function Select Register PD0%sPFS 0x340 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 6 0x004 0-5 PD1%sPFS Port D1%s Pin Function Select Register 0x368 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 6 0x004 0-5 PD1%sPFS_HA Port D1%s Pin Function Select Register PD1%sPFS 0x368 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 6 0x004 0-5 PD1%sPFS_BY Port D1%s Pin Function Select Register PD1%sPFS 0x368 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 7 0x004 0-6 PE0%sPFS Port E0%s Pin Function Select Register 0x380 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 7 0x004 0-6 PE0%sPFS_HA Port E0%s Pin Function Select Register PE0%sPFS 0x380 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 7 0x004 0-6 PE0%sPFS_BY Port E0%s Pin Function Select Register PE0%sPFS 0x380 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 2 0x004 8-9 PE0%sPFS Port E0%s Pin Function Select Register 0x3A0 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 2 0x004 8-9 PE0%sPFS_HA Port E0%s Pin Function Select Register PE0%sPFS 0x3A0 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 2 0x004 8-9 PE0%sPFS_BY Port E0%s Pin Function Select Register PE0%sPFS 0x3A0 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 6 0x004 0-5 PE1%sPFS Port E1%s Pin Function Select Register 0x3A8 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 PMR Port Mode Control 16 16 read-write 0 Used as a general I/O pin #0 1 Used as an I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 6 0x004 0-5 PE1%sPFS_HA Port E1%s Pin Function Select Register PE1%sPFS 0x3A8 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive / High current drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Not used as an IRQn input pin #0 1 Used as an IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Not used as an analog pin #0 1 Used as an analog pin #1 6 0x004 0-5 PE1%sPFS_BY Port E1%s Pin Function Select Register PE1%sPFS 0x3A8 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 PIDR Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PWPR Write-Protect Register 0x50C 8 read-write 0x80 0xff PFSWE PmnPFS Register Write Enable 6 6 read-write 0 Writing to the PmnPFS register is disabled #0 1 Writing to the PmnPFS register is enabled #1 B0WI PFSWE Bit Write Disable 7 7 read-write 0 Writing to the PFSWE bit is enabled #0 1 Writing to the PFSWE bit is disabled #1 PWPRS Write-Protect Register for Secure 0x514 8 read-write 0x80 0xff PFSWE PmnPFS Register Write Enable 6 6 read-write 0 Disable writes to the PmnPFS register #0 1 Enable writes to the PmnPFS register #1 B0WI PFSWE Bit Write Disable 7 7 read-write 0 Enable writes the PFSWE bit #0 1 Disable writes to the PFSWE bit #1 P0SAR Port 0 Security Attribution register 0x530 16 read-write 0xffff 0xffff PMNSA Pmn Security Attribution 0 15 read-write 0 Secure #0 1 Non Secure #1 P2SAR Port 2 Security Attribution register 0x538 16 read-write 0xffff 0xffff PMNSA Pmn Security Attribution 0 15 read-write 0 Secure #0 1 Non Secure #1 PASAR Port A Security Attribution register 0x558 16 read-write 0xffff 0xffff PMNSA Pmn Security Attribution 0 15 read-write 0 Secure #0 1 Non Secure #1 PBSAR Port B Security Attribution register 0x55C 16 read-write 0xffff 0xffff PMNSA Pmn Security Attribution 0 15 read-write 0 Secure #0 1 Non Secure #1 PCSAR Port C Security Attribution register 0x560 16 read-write 0xffff 0xffff PMNSA Pmn Security Attribution 0 15 read-write 0 Secure #0 1 Non Secure #1 PDSAR Port D Security Attribution register 0x564 16 read-write 0xffff 0xffff PMNSA Pmn Security Attribution 0 15 read-write 0 Secure #0 1 Non Secure #1 PESAR Port E Security Attribution register 0x568 16 read-write 0xffff 0xffff PMNSA Pmn Security Attribution 0 15 read-write 0 Secure #0 1 Non Secure #1 IIRFA IIR filter accelerator 0x40020000 0x00 20 registers 0x20 4 registers 0x28 4 registers 0x30 16 registers 0x100 270 registers 0x400 1048 registers IIRCPRCS Channel Processing Status Register 0x000 32 read-only 0x00000000 0xffffffff CPRCS Channel processing status bit 0 15 read-only 0 The channel processing of the corresponding channel is not being performed. #0 1 The channel processing of the corresponding channel is being performed. #1 IIRCPRCFF Channel Processing Completion Flag Register 0x004 32 read-only 0x00000000 0xffffffff CPRCFF Channel processing completion flag 0 15 read-only 0 The channel processing of the corresponding channel is not completed. #0 1 The channel processing of the corresponding channel is completed. #1 IIRORDYF Output Data Preparation Completion Flag Register 0x008 32 read-only 0x00000000 0xffffffff ORDYF Output data preparation completion flag 0 15 read-only 0 The output data preparation of the corresponding channel is not completed. #0 1 The output data preparation of the corresponding channel is completed. #1 IIRCERRF Operation Error Flag Register 0x00C 32 read-only 0x00000000 0xffffffff CERRF Operation error flag 0 15 read-only 0 No operation error has occurred in the corresponding channel. #0 1 An operation error has occurred in the corresponding channel. #1 IIROPCNT Operation Control Register 0x010 32 read-write 0x00000000 0xffffffff RND Setting for the rounding mode for addition and multiplication 0 2 read-write 000 Round to nearest #000 001 Round toward zero #001 Others Setting prohibited. true IIRECCCNT ECC Control Register 0x020 32 read-write 0x00000000 0xffffffff ECCMD ECC setting bit 0 0 read-write 0 The ECC error detection/correction function is disabled. #0 1 The ECC error detection/correction function is enabled. #1 ECCWBDIS ECC-corrected data write-back disable bit 1 1 read-write 0 The error-corrected data write-back is enabled. #0 1 The error-corrected data write-back is disabled. #1 IIRECCINT ECC Interrupt Enable Register 0x028 32 read-write 0x00000000 0xffffffff ESEIE ECC 1-bit error interrupt enable bit 0 0 read-write 0 The generation of ECC 1-bit error interrupt requests is disabled. #0 1 The generation of ECC 1-bit error interrupt requests is enabled. #1 EDEIE ECC 2-bit error interrupt enable bit 1 1 read-write 0 The generation of ECC 2-bit error interrupt requests is disabled. #0 1 The generation of ECC 2-bit error interrupt requests is enabled. #1 IIRECCEF ECC Error Flag Register 0x030 32 read-only 0x00000000 0xffffffff ESEF ECC 1-bit error flag 0 0 read-only 0 No 1-bit ECC error is detected. #0 1 1-bit ECC error is detected. #1 EDEF ECC 2-bit error flag 1 1 read-only 0 No 2-bit ECC error is detected. #0 1 2-bit ECC error is detected. #1 IIRECCEFCLR ECC Error Flag Clear Register 0x034 32 write-only 0x00000000 0xffffffff ESEFCLR ECC 1-bit error flag clear bit 0 0 write-only 0 No effect #0 1 Clears the ESEF flag of the IIRECCEF register. #1 EDEFCLR ECC 2-bit error status flag clear bit 1 1 write-only 0 No effect #0 1 Clears the EDEF flag of the IIRECCEF register. #1 IIRESEADR ECC 1-bit Error Address Register 0x038 32 read-only 0x00000000 0xffffffff SEADR Error address 0 10 read-only IIREDEADR ECC 2-bit Error Address Register 0x03C 32 read-only 0x00000000 0xffffffff DEADR Error address 0 10 read-only 16 0x10 0-15 IIRCH%sINP Channel %s Input Register 0x100 32 write-only 0x00000000 0x00000000 16 0x10 0-15 IIRCH%sOUT Channel %s Output Register 0x104 32 read-only 0x00000000 0xffffffff 16 0x10 0-15 IIRCH%sCNT Channel %s Control Register 0x108 32 read-write 0x00000000 0xffffffff STGSEL Stage selection bit 0 31 read-write 0 The corresponding stage is not used for channel n. #0 1 The corresponding stage is used for channel n. #1 16 0x10 0-15 IIRCH%sINT Channel %s Interrupt Enable Register 0x10C 8 read-write 0x00 0xff CPRCFIE Channel processing completion interrupt enable bit 1 1 read-write 0 The generation of channel processing completion interrupt requests is disabled. #0 1 The generation of channel processing completion interrupt requests is enabled. #1 ORDYIE Output data preparation completion interrupt enable bit 2 2 read-write 0 The generation of output data preparation completion interrupt requests is disabled. #0 1 The generation of output data preparation completion interrupt requests is enabled. #1 CERRIE Operation error interrupt enable bit 3 3 read-write 0 The generation of operation error interrupt requests is disabled. #0 1 The generation of operation error interrupt requests is enabled. #1 16 0x10 0-15 IIRCH%sSTS Channel %s Status Register 0x10D 8 read-only 0x00 0xff CPRCS Channel processing status flag 0 0 read-only 0 The channel processing is not being performed. #0 1 The channel processing is being performed. #1 CPRCFF Channel processing completion flag 1 1 read-only 0 The channel processing is not completed. #0 1 The channel processing is completed. #1 ORDYF Output data preparation completion flag 2 2 read-only 0 The output data preparation is not completed. #0 1 The output data preparation is completed. #1 CERRF Operation error flag 3 3 read-only 0 No operation error has occurred. #0 1 An operation error has occurred. #1 16 0x10 0-15 IIRCH%sFCLR Channel %s Flag Clear Register 0x10E 8 write-only 0x00 0xff CPRCFFCLR Channel processing completion flag clear bit 1 1 write-only 0 No effect #0 1 Clears the CPRCFF flag of the IIRCHnSTS register. #1 CERRFCLR Operation error flag clear bit 3 3 write-only 0 No effect #0 1 Clears the CERRF flag of the IIRCHnSTS register. #1 32 0x20 0-31 IIRSTG%sB0 Stage %s Coefficient b0 Register 0x400 32 read-write 0x00000000 0x00000000 32 0x20 0-31 IIRSTG%sB1 Stage %s Coefficient b1 Register 0x404 32 read-write 0x00000000 0x00000000 32 0x20 0-31 IIRSTG%sB2 Stage %s Coefficient b2 Register 0x408 32 read-write 0x00000000 0x00000000 32 0x20 0-31 IIRSTG%sA1 Stage %s Coefficient a1 Register 0x40C 32 read-write 0x00000000 0x00000000 32 0x20 0-31 IIRSTG%sA2 Stage %s Coefficient a2 Register 0x410 32 read-write 0x00000000 0x00000000 32 0x20 0-31 IIRSTG%sD0 Stage %s Delay Data D0 Register 0x414 32 read-write 0x00000000 0x00000000 32 0x20 0-31 IIRSTG%sD1 Stage %s Delay Data D1 Register 0x418 32 read-write 0x00000000 0x00000000 TFU Trigonometric Function Unit 0x40021000 0x08 1 registers 0x10 16 registers TRGSTS Trigonometric Status Register 0x08 8 read-only 0x00 0xff BSYF Calculation in progress flag 0 0 read-only 0 No calculating #0 1 Calculating #1 ERRF Input error flag 1 1 read-only 0 No input error occurred #0 1 Input error occurred #1 SCDT0 Sine Cosine Data Register 0 0x10 32 read-write 0x00000000 0xffffffff SCDT0 Sine Cosine Data Register 0 (single-precision floating-point) 0 31 read-write SCDT1 Sine Cosine Data Register 1 0x14 32 read-write 0x00000000 0xffffffff SCDT1 Sine Cosine Data Register 1 (single-precision floating-point) 0 31 read-write ATDT0 Arctangent Data Register 0 0x18 32 read-write 0x00000000 0xffffffff ATDT0 Arctangent Data Register 0 (single-precision floating-point) 0 31 read-write ATDT1 Arctangent Data Register 1 0x1C 32 read-write 0x00000000 0xffffffff ATDT1 Arctangent Data Register 1 (single-precision floating-point) 0 31 read-write ELC_B Event Link Controller 0x40082000 0x00 1 registers 0x04 8 registers 0x20 32 registers 0x50 24 registers 0x6C 24 registers 0x90 8 registers 0xE0 8 registers ELCR Event Link Controller Register 0x00 8 read-write 0x00 0xff ELCON All Event Link Enable 7 7 read-write 0 ELC function is disabled. #0 1 ELC function is enabled. #1 2 0x04 0-1 ELSEGR%s Event Link Software Event Generation Register %s 0x04 8 read-write 0x80 0xff SEG Software Event Generation 0 0 write-only 0 Normal operation #0 1 Software event is generated. #1 WE SEG Bit Write Enable 6 6 read-write 0 Write to SEG bit disabled. #0 1 Write to SEG bit enabled. #1 WI ELSEGR Register Write Disable 7 7 write-only 0 Write to ELSEGR register enabled. #0 1 Write to ELSEGR register disabled. #1 8 0x04 0-7 ELSR%s Event Link Setting Register %s 0x20 16 read-write 0x0000 0xffff ELS Event Link Select 0 8 read-write 6 0x04 12-17 ELSR%s Event Link Setting Register %s 0x50 16 read-write 0x0000 0xffff ELS Event Link Select 0 8 read-write 6 0x04 19-24 ELSR%s Event Link Setting Register %s 0x6C 16 read-write 0x0000 0xffff ELS Event Link Select 0 8 read-write 2 0x04 28-29 ELSR%s Event Link Setting Register %s 0x90 16 read-write 0x0000 0xffff ELS Event Link Select 0 8 read-write ELCSARA Event Link Controller Security Attribution Register A 0xE0 32 read-write 0xffffffff 0xffffffff ELCR Event Link Controller Register Security Attribution 0 0 read-write 0 Secure #0 1 Non-secure #1 ELSEGR0 Event Link Software Event Generation Register 0 Security Attribution 1 1 read-write 0 Secure #0 1 Non-secure #1 ELSEGR1 Event Link Software Event Generation Register 1 Security Attribution 2 2 read-write 0 Secure #0 1 Non-secure #1 ELCSARB Event Link Controller Security Attribution Register B 0xE4 32 read-write 0xffffffff 0xffffffff ELSR0 Event Link Setting Register n Security Attribution 0 0 read-write 0 Secure #0 1 Non-secure #1 ELSR1 Event Link Setting Register n Security Attribution 1 1 read-write 0 Secure #0 1 Non-secure #1 ELSR2 Event Link Setting Register n Security Attribution 2 2 read-write 0 Secure #0 1 Non-secure #1 ELSR3 Event Link Setting Register n Security Attribution 3 3 read-write 0 Secure #0 1 Non-secure #1 ELSR4 Event Link Setting Register n Security Attribution 4 4 read-write 0 Secure #0 1 Non-secure #1 ELSR5 Event Link Setting Register n Security Attribution 5 5 read-write 0 Secure #0 1 Non-secure #1 ELSR6 Event Link Setting Register n Security Attribution 6 6 read-write 0 Secure #0 1 Non-secure #1 ELSR7 Event Link Setting Register n Security Attribution 7 7 read-write 0 Secure #0 1 Non-secure #1 ELSR12 Event Link Setting Register n Security Attribution 12 12 read-write 0 Secure #0 1 Non-secure #1 ELSR13 Event Link Setting Register n Security Attribution 13 13 read-write 0 Secure #0 1 Non-secure #1 ELSR14 Event Link Setting Register n Security Attribution 14 14 read-write 0 Secure #0 1 Non-secure #1 ELSR15 Event Link Setting Register n Security Attribution 15 15 read-write 0 Secure #0 1 Non-secure #1 ELSR16 Event Link Setting Register n Security Attribution 16 16 read-write 0 Secure #0 1 Non-secure #1 ELSR17 Event Link Setting Register n Security Attribution 17 17 read-write 0 Secure #0 1 Non-secure #1 ELSR19 Event Link Setting Register n Security Attribution 19 19 read-write 0 Secure #0 1 Non-secure #1 ELSR20 Event Link Setting Register n Security Attribution 20 20 read-write 0 Secure #0 1 Non-secure #1 ELSR21 Event Link Setting Register n Security Attribution 21 21 read-write 0 Secure #0 1 Non-secure #1 ELSR22 Event Link Setting Register n Security Attribution 22 22 read-write 0 Secure #0 1 Non-secure #1 ELSR23 Event Link Setting Register n Security Attribution 23 23 read-write 0 Secure #0 1 Non-secure #1 ELSR24 Event Link Setting Register n Security Attribution 24 24 read-write 0 Secure #0 1 Non-secure #1 ELSR28 Event Link Setting Register n Security Attribution 28 28 read-write 0 Secure #0 1 Non-secure #1 ELSR29 Event Link Setting Register n Security Attribution 29 29 read-write 0 Secure #0 1 Non-secure #1 IWDT Independent Watchdog Timer 0x40083200 0x00 1 registers 0x04 2 registers IWDTRR IWDT Refresh Register 0x00 8 read-write 0xff 0xff IWDTSR IWDT Status Register 0x04 16 read-write 0x0000 0xffff CNTVAL Down-counter Value 0 13 read-only UNDFF Underflow Flag 14 14 read-write 0 No underflow occurred #0 1 Underflow occurred #1 REFEF Refresh Error Flag 15 15 read-write 0 No refresh error occurred #0 1 Refresh error occurred #1 WDT Watchdog Timer 0x40083400 0x00 1 registers 0x02 5 registers 0x08 1 registers WDTRR WDT Refresh Register 0x00 8 read-write 0xff 0xff WDTCR WDT Control Register 0x02 16 read-write 0x33f3 0xffff TOPS Timeout Period Select 0 1 read-write 00 1024 cycles (0x03FF) #00 01 4096 cycles (0x0FFF) #01 10 8192 cycles (0x1FFF) #10 11 16384 cycles (0x3FFF) #11 CKS Clock Division Ratio Select 4 7 read-write 0x1 PCLKB/4 0x1 0x4 PCLKB/64 0x4 0xF PCLKB/128 0xf 0x6 PCLKB/512 0x6 0x7 PCLKB/2048 0x7 0x8 PCLKB/8192 0x8 Others Setting prohibited true RPES Window End Position Select 8 9 read-write 00 75% #00 01 50% #01 10 25% #10 11 0% (do not specify window end position). #11 RPSS Window Start Position Select 12 13 read-write 00 25% #00 01 50% #01 10 75% #10 11 100% (do not specify window start position). #11 WDTSR WDT Status Register 0x04 16 read-write 0x0000 0xffff CNTVAL Down-Counter Value 0 13 read-only UNDFF Underflow Flag 14 14 read-write 0 No underflow occurred #0 1 Underflow occurred #1 REFEF Refresh Error Flag 15 15 read-write 0 No refresh error occurred #0 1 Refresh error occurred #1 WDTRCR WDT Reset Control Register 0x06 8 read-write 0x80 0xff RSTIRQS Reset Interrupt Request Select 7 7 read-write 0 Enable non-maskable interrupt request or interrupt request output #0 1 Enable reset output #1 WDTCSTPR WDT Count Stop Control Register 0x08 8 read-write 0x80 0xff SLCSTP WDT Count Stop Control Register 7 7 read-write 0 Disable count stop #0 1 Stop count on transition to Sleep mode #1 CAC Clock Frequency Accuracy Measurement Circuit 0x40083600 0x00 5 registers 0x06 6 registers CACR0 CAC Control Register 0 0x00 8 read-write 0x00 0xff CFME Clock Frequency Measurement Enable 0 0 read-write 0 Disable #0 1 Enable #1 CACR1 CAC Control Register 1 0x01 8 read-write 0x00 0xff CACREFE CACREF Pin Input Enable 0 0 read-write 0 Disable #0 1 Enable #1 FMCS Measurement Target Clock Select 1 3 read-write 000 Main clock oscillator #000 001 Setting prohibited #001 010 HOCO clock #010 011 MOCO clock #011 100 LOCO clock #100 101 Peripheral module clock B (PCLKB) #101 110 IWDT-dedicated clock #110 111 Setting prohibited #111 TCSS Timer Count Clock Source Select 4 5 read-write 00 No division #00 01 x 1/4 clock #01 10 x 1/8 clock #10 11 x 1/32 clock #11 EDGES Valid Edge Select 6 7 read-write 00 Rising edge #00 01 Falling edge #01 10 Both rising and falling edges #10 11 Setting prohibited #11 CACR2 CAC Control Register 2 0x02 8 read-write 0x00 0xff RPS Reference Signal Select 0 0 read-write 0 CACREF pin input #0 1 Internal clock (internally generated signal) #1 RSCS Measurement Reference Clock Select 1 3 read-write 000 Main clock oscillator #000 001 Setting prohibited #001 010 HOCO clock #010 011 MOCO clock #011 100 LOCO clock #100 101 Peripheral module clock B (PCLKB) #101 110 IWDT-dedicated clock #110 111 Setting prohibited #111 RCDS Measurement Reference Clock Frequency Division Ratio Select 4 5 read-write 00 x 1/32 clock #00 01 x 1/128 clock #01 10 x 1/1024 clock #10 11 x 1/8192 clock #11 DFS Digital Filter Select 6 7 read-write 00 Disable digital filtering #00 01 Use sampling clock for the digital filter as the frequency measuring clock #01 10 Use sampling clock for the digital filter as the frequency measuring clock divided by 4 #10 11 Use sampling clock for the digital filter as the frequency measuring clock divided by 16. #11 CAICR CAC Interrupt Control Register 0x03 8 read-write 0x00 0xff FERRIE Frequency Error Interrupt Request Enable 0 0 read-write 0 Disable #0 1 Enable #1 MENDIE Measurement End Interrupt Request Enable 1 1 read-write 0 Disable #0 1 Enable #1 OVFIE Overflow Interrupt Request Enable 2 2 read-write 0 Disable #0 1 Enable #1 FERRFCL FERRF Clear 4 4 write-only 0 No effect #0 1 The CASTR.FERRF flag is cleared #1 MENDFCL MENDF Clear 5 5 write-only 0 No effect #0 1 The CASTR.MENDF flag is cleared #1 OVFFCL OVFF Clear 6 6 write-only 0 No effect #0 1 The CASTR.OVFF flag is cleared. #1 CASTR CAC Status Register 0x04 8 read-only 0x00 0xff FERRF Frequency Error Flag 0 0 read-only 0 Clock frequency is within the allowable range #0 1 Clock frequency has deviated beyond the allowable range (frequency error). #1 MENDF Measurement End Flag 1 1 read-only 0 Measurement is in progress #0 1 Measurement ended #1 OVFF Overflow Flag 2 2 read-only 0 Counter has not overflowed #0 1 Counter overflowed #1 CAULVR CAC Upper-Limit Value Setting Register 0x06 16 read-write 0x0000 0xffff CALLVR CAC Lower-Limit Value Setting Register 0x08 16 read-write 0x0000 0xffff CACNTBR CAC Counter Buffer Register 0x0A 16 read-only 0x0000 0xffff MSTP Module Stop Control 0x40084000 0x00 20 registers MSTPCRA Module Stop Control Register A 0x000 32 read-write 0xffbfff7e 0xffffffff MSTPA0 SRAM0 Module Stop 0 0 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPA7 Standby SRAM Module Stop 7 7 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPA22 DMA Controller/Data Transfer Controller Module Stop 22 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRB Module Stop Control Register B 0x004 32 read-write 0xffffffff 0xffffffff MSTPB8 I2C Bus Interface 1 Module Stop 8 8 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB9 I2C Bus Interface 0 Module Stop 9 9 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB18 Serial Peripheral Interface 1 Module Stop 18 18 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB19 Serial Peripheral Interface 0 Module Stop 19 19 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB22 Serial Communication Interface 9 Module Stop 22 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB27 Serial Communication Interface 4 Module Stop 27 27 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB28 Serial Communication Interface 3 Module Stop 28 28 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB29 Serial Communication Interface 2 Module Stop 29 29 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB30 Serial Communication Interface 1 Module Stop 30 30 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB31 Serial Communication Interface 0 Module Stop 31 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRC Module Stop Control Register C 0x008 32 read-write 0xffffffff 0xffffffff MSTPC0 Clock Frequency Accuracy Measurement Circuit Module Stop 0 0 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC1 Cyclic Redundancy Check Module Stop 1 1 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC13 Data Operation Circuit Module Stop 13 13 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC14 Event Link Controller Module Stop 14 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC20 Trigonometric Function Unit Module Stop 20 20 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC21 IIR Filter Accelerator Module Stop 21 21 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC27 CANFD Module Stop 27 27 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC31 Secure Cryptographic Engine Module Stop 31 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRD Module Stop Control Register D 0x00C 32 read-write 0xffffffff 0xffffffff MSTPD2 Low Power Asynchronous General Purpose Timer 1 Module Stop 2 2 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD3 Low Power Asynchronous General Purpose Timer 0 Module Stop 3 3 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD11 Port Output Enable for GPT Group D Module Stop 11 11 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD12 Port Output Enable for GPT Group C Module Stop 12 12 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD13 Port Output Enable for GPT Group B Module Stop 13 13 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD14 Port Output Enable for GPT Group A Module Stop 14 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD16 A/D Converter Module Stop 16 16 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD19 12-bit D/A Converter 1 Module Stop 19 19 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD20 12-bit D/A Converter 0 Module Stop 20 20 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD22 Temperature Sensor Module Stop 22 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD25 High-Speed Analog Comparator 3 Module Stop 25 25 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD26 High-Speed Analog Comparator 2 Module Stop 26 26 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD27 High-Speed Analog Comparator 1 Module Stop 27 27 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD28 High-Speed Analog Comparator 0 Module Stop 28 28 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRE Module Stop Control Register E 0x010 32 read-write 0xffffffff 0xffffffff MSTPE4 Key Interrupt Function Module Stop 4 4 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE31 General PWM Timer and PWM Delay Generation Circuit Module Stop 31 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 KINT Key Interrupt Function 0x40085000 0x00 1 registers 0x04 1 registers 0x08 1 registers KRCTL Key Return Control Register 0x00 8 read-write 0x00 0xff KREG Detection Edge Selection (KR00 to KR07 pins) 0 0 read-write 0 Falling edge #0 1 Rising edge #1 KRMD Usage of Key Interrupt Flags (KRF.KIF0 to KRF.KIF7) 7 7 read-write 0 Do not use key interrupt flags #0 1 Use key interrupt flags #1 KRF Key Return Flag Register 0x04 8 read-write 0x00 0xff KIF0 Key Interrupt Flag n 0 0 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KIF1 Key Interrupt Flag n 1 1 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KIF2 Key Interrupt Flag n 2 2 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KIF3 Key Interrupt Flag n 3 3 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KIF4 Key Interrupt Flag n 4 4 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KIF5 Key Interrupt Flag n 5 5 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KIF6 Key Interrupt Flag n 6 6 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KIF7 Key Interrupt Flag n 7 7 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KRM Key Return Mode Register 0x08 8 read-write 0x00 0xff KIMC0 Key Interrupt Mode Control n 0 0 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 KIMC1 Key Interrupt Mode Control n 1 1 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 KIMC2 Key Interrupt Mode Control n 2 2 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 KIMC3 Key Interrupt Mode Control n 3 3 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 KIMC4 Key Interrupt Mode Control n 4 4 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 KIMC5 Key Interrupt Mode Control n 5 5 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 KIMC6 Key Interrupt Mode Control n 6 6 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 KIMC7 Key Interrupt Mode Control n 7 7 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 POEG Port Output Enable for GPT 0x4008A000 0x00 4 registers 0x40 2 registers 0x44 2 registers 0x100 4 registers 0x140 2 registers 0x144 2 registers 0x200 4 registers 0x240 2 registers 0x244 2 registers 0x300 4 registers 0x340 2 registers 0x344 2 registers POEGGA POEG Group A Setting Register 0x000 32 read-write 0x00000000 0xffffffff PIDF Port Input Detection Flag 0 0 read-write 0 The selected input level was not detected on the GTETRGn pin #0 1 The selected input level was detected on the GTETRGn pin #1 IOCF GPT or ACMPHS Output Stop Request Detection Flag 1 1 read-write 0 Neither stopping of GPT output nor a comparator edge was detected #0 1 Either stopping of GPT output or comparator edge was detected #1 OSTPF Oscillation Stop Detection Flag 2 2 read-write 0 Stopping of oscillation was not detected #0 1 Stopping of oscillation was detected #1 SSF Software Stop Flag 3 3 read-write 0 Software has not stopped output #0 1 Software has stopped output #1 PIDE Port Input Detection Enable 4 4 read-write 0 Detection of input levels on the corresponding GTETRGn pin is disabled #0 1 Detection of input levels on the corresponding GTETRGn pin is enabled #1 IOCE GPT Output Stop Request Enable 5 5 read-write 0 Detection of stopping of output from the GPT is disabled #0 1 Detection of stopping of output from the GPT is enabled #1 OSTPE Enable Stopping Output on Stopping of Oscillation 6 6 read-write 0 Detection of stopping of oscillation is disabled #0 1 Detection of stopping of oscillation is enabled #1 CDRE0 ACMPHS0 Enable 8 8 read-write 0 Comparator edge detection 0 is disabled #0 1 Comparator edge detection 0 is enabled #1 CDRE1 ACMPHS1 Enable 9 9 read-write 0 Comparator edge detection 1 is disabled #0 1 Comparator edge detection 1 is enabled #1 CDRE2 ACMPHS2 Enable 10 10 read-write 0 Comparator edge detection 2 is disabled #0 1 Comparator edge detection 2 is enabled #1 CDRE3 ACMPHS3 Enable 11 11 read-write 0 Comparator edge detection 3 is disabled #0 1 Comparator edge detection 3 is enabled #1 ST GTETRGn Input Status Flag 16 16 read-only 0 The corresponding external trigger for output to the GPT is 0 #0 1 The corresponding external trigger for output to the GPT is 1 #1 INV GTETRGn Input Inverting 28 28 read-write 0 Input on the GTETRGn pin is not inverted #0 1 Input on the GTETRGn pin is inverted #1 NFEN Noise filter Enable 29 29 read-write 0 Digital noise filter on the GTETRGn pin is disabled #0 1 Digital noise filter on the GTETRGn pin is enabled #1 NFCS Noise filter Clock Select 30 31 read-write 00 Samples the input level of GTETRGn pin three times per PCLKB/1 clock #00 01 Samples the input level of GTETRGn pin three times per PCLKB/8 clock #01 10 Samples the input level of GTETRGn pin three times per PCLKB/32 clock #10 11 Samples the input level of GTETRGn pin three times per PCLKB/128 clock #11 GTONCWPA GPT Output Stopping Control Group A Write Protection Register 0x040 16 read-write 0x0000 0xffff WP Register Writing Disable 0 0 read-write 0 Writing to the GTONCCRn register is enabled #0 1 Writing to the GTONCCRn register is disabled #1 PRKEY Key Code 8 15 read-write GTONCCRA GPT Output Stopping Control Group A Controlling Register 0x044 16 read-write 0x0100 0xffff NE Direct Stopping Request Setting 0 0 read-write 0 The signal for detection is not set as a direct stopping request signal #0 1 The signal for detection is set as a direct stopping request signal #1 NFS Direct Stopping Request Selection 4 7 read-write 0x0 Comparator level detection 0 0x0 0x1 Comparator level detection 1 0x1 0x2 Comparator level detection 2 0x2 0x4 Comparator level detection 3 0x4 0x7 GTETRGn pin input level detection (n = A to D) 0x7 Others Setting prohibited true NFV Direct Stopping Request Active Sense 8 8 read-write 0 Stopping output is requested when the output stopping detection signal is 0 #0 1 Stopping output is requested when the output stopping detection signal is 1 #1 POEGGB POEG Group B Setting Register 0x100 32 read-write 0x00000000 0xffffffff PIDF Port Input Detection Flag 0 0 read-write 0 The selected input level was not detected on the GTETRGn pin #0 1 The selected input level was detected on the GTETRGn pin #1 IOCF GPT or ACMPHS Output Stop Request Detection Flag 1 1 read-write 0 Neither stopping of GPT output nor a comparator edge was detected #0 1 Either stopping of GPT output or comparator edge was detected #1 OSTPF Oscillation Stop Detection Flag 2 2 read-write 0 Stopping of oscillation was not detected #0 1 Stopping of oscillation was detected #1 SSF Software Stop Flag 3 3 read-write 0 Software has not stopped output #0 1 Software has stopped output #1 PIDE Port Input Detection Enable 4 4 read-write 0 Detection of input levels on the corresponding GTETRGn pin is disabled #0 1 Detection of input levels on the corresponding GTETRGn pin is enabled #1 IOCE GPT Output Stop Request Enable 5 5 read-write 0 Detection of stopping of output from the GPT is disabled #0 1 Detection of stopping of output from the GPT is enabled #1 OSTPE Enable Stopping Output on Stopping of Oscillation 6 6 read-write 0 Detection of stopping of oscillation is disabled #0 1 Detection of stopping of oscillation is enabled #1 CDRE0 ACMPHS0 Enable 8 8 read-write 0 Comparator edge detection 0 is disabled #0 1 Comparator edge detection 0 is enabled #1 CDRE1 ACMPHS1 Enable 9 9 read-write 0 Comparator edge detection 1 is disabled #0 1 Comparator edge detection 1 is enabled #1 CDRE2 ACMPHS2 Enable 10 10 read-write 0 Comparator edge detection 2 is disabled #0 1 Comparator edge detection 2 is enabled #1 CDRE3 ACMPHS3 Enable 11 11 read-write 0 Comparator edge detection 3 is disabled #0 1 Comparator edge detection 3 is enabled #1 ST GTETRGn Input Status Flag 16 16 read-only 0 The corresponding external trigger for output to the GPT is 0 #0 1 The corresponding external trigger for output to the GPT is 1 #1 INV GTETRGn Input Inverting 28 28 read-write 0 Input on the GTETRGn pin is not inverted #0 1 Input on the GTETRGn pin is inverted #1 NFEN Noise filter Enable 29 29 read-write 0 Digital noise filter on the GTETRGn pin is disabled #0 1 Digital noise filter on the GTETRGn pin is enabled #1 NFCS Noise filter Clock Select 30 31 read-write 00 Samples the input level of GTETRGn pin three times per PCLKB/1 clock #00 01 Samples the input level of GTETRGn pin three times per PCLKB/8 clock #01 10 Samples the input level of GTETRGn pin three times per PCLKB/32 clock #10 11 Samples the input level of GTETRGn pin three times per PCLKB/128 clock #11 GTONCWPB GPT Output Stopping Control Group B Write Protection Register 0x140 16 read-write 0x0000 0xffff WP Register Writing Disable 0 0 read-write 0 Writing to the GTONCCRn register is enabled #0 1 Writing to the GTONCCRn register is disabled #1 PRKEY Key Code 8 15 read-write GTONCCRB GPT Output Stopping Control Group B Controlling Register 0x144 16 read-write 0x0100 0xffff NE Direct Stopping Request Setting 0 0 read-write 0 The signal for detection is not set as a direct stopping request signal #0 1 The signal for detection is set as a direct stopping request signal #1 NFS Direct Stopping Request Selection 4 7 read-write 0x0 Comparator level detection 0 0x0 0x1 Comparator level detection 1 0x1 0x2 Comparator level detection 2 0x2 0x4 Comparator level detection 3 0x4 0x7 GTETRGn pin input level detection (n = A to D) 0x7 Others Setting prohibited true NFV Direct Stopping Request Active Sense 8 8 read-write 0 Stopping output is requested when the output stopping detection signal is 0 #0 1 Stopping output is requested when the output stopping detection signal is 1 #1 POEGGC POEG Group C Setting Register 0x200 32 read-write 0x00000000 0xffffffff PIDF Port Input Detection Flag 0 0 read-write 0 The selected input level was not detected on the GTETRGn pin #0 1 The selected input level was detected on the GTETRGn pin #1 IOCF GPT or ACMPHS Output Stop Request Detection Flag 1 1 read-write 0 Neither stopping of GPT output nor a comparator edge was detected #0 1 Either stopping of GPT output or comparator edge was detected #1 OSTPF Oscillation Stop Detection Flag 2 2 read-write 0 Stopping of oscillation was not detected #0 1 Stopping of oscillation was detected #1 SSF Software Stop Flag 3 3 read-write 0 Software has not stopped output #0 1 Software has stopped output #1 PIDE Port Input Detection Enable 4 4 read-write 0 Detection of input levels on the corresponding GTETRGn pin is disabled #0 1 Detection of input levels on the corresponding GTETRGn pin is enabled #1 IOCE GPT Output Stop Request Enable 5 5 read-write 0 Detection of stopping of output from the GPT is disabled #0 1 Detection of stopping of output from the GPT is enabled #1 OSTPE Enable Stopping Output on Stopping of Oscillation 6 6 read-write 0 Detection of stopping of oscillation is disabled #0 1 Detection of stopping of oscillation is enabled #1 CDRE0 ACMPHS0 Enable 8 8 read-write 0 Comparator edge detection 0 is disabled #0 1 Comparator edge detection 0 is enabled #1 CDRE1 ACMPHS1 Enable 9 9 read-write 0 Comparator edge detection 1 is disabled #0 1 Comparator edge detection 1 is enabled #1 CDRE2 ACMPHS2 Enable 10 10 read-write 0 Comparator edge detection 2 is disabled #0 1 Comparator edge detection 2 is enabled #1 CDRE3 ACMPHS3 Enable 11 11 read-write 0 Comparator edge detection 3 is disabled #0 1 Comparator edge detection 3 is enabled #1 ST GTETRGn Input Status Flag 16 16 read-only 0 The corresponding external trigger for output to the GPT is 0 #0 1 The corresponding external trigger for output to the GPT is 1 #1 INV GTETRGn Input Inverting 28 28 read-write 0 Input on the GTETRGn pin is not inverted #0 1 Input on the GTETRGn pin is inverted #1 NFEN Noise filter Enable 29 29 read-write 0 Digital noise filter on the GTETRGn pin is disabled #0 1 Digital noise filter on the GTETRGn pin is enabled #1 NFCS Noise filter Clock Select 30 31 read-write 00 Samples the input level of GTETRGn pin three times per PCLKB/1 clock #00 01 Samples the input level of GTETRGn pin three times per PCLKB/8 clock #01 10 Samples the input level of GTETRGn pin three times per PCLKB/32 clock #10 11 Samples the input level of GTETRGn pin three times per PCLKB/128 clock #11 GTONCWPC GPT Output Stopping Control Group C Write Protection Register 0x240 16 read-write 0x0000 0xffff WP Register Writing Disable 0 0 read-write 0 Writing to the GTONCCRn register is enabled #0 1 Writing to the GTONCCRn register is disabled #1 PRKEY Key Code 8 15 read-write GTONCCRC GPT Output Stopping Control Group C Controlling Register 0x244 16 read-write 0x0100 0xffff NE Direct Stopping Request Setting 0 0 read-write 0 The signal for detection is not set as a direct stopping request signal #0 1 The signal for detection is set as a direct stopping request signal #1 NFS Direct Stopping Request Selection 4 7 read-write 0x0 Comparator level detection 0 0x0 0x1 Comparator level detection 1 0x1 0x2 Comparator level detection 2 0x2 0x4 Comparator level detection 3 0x4 0x7 GTETRGn pin input level detection (n = A to D) 0x7 Others Setting prohibited true NFV Direct Stopping Request Active Sense 8 8 read-write 0 Stopping output is requested when the output stopping detection signal is 0 #0 1 Stopping output is requested when the output stopping detection signal is 1 #1 POEGGD POEG Group D Setting Register 0x300 32 read-write 0x00000000 0xffffffff PIDF Port Input Detection Flag 0 0 read-write 0 The selected input level was not detected on the GTETRGn pin #0 1 The selected input level was detected on the GTETRGn pin #1 IOCF GPT or ACMPHS Output Stop Request Detection Flag 1 1 read-write 0 Neither stopping of GPT output nor a comparator edge was detected #0 1 Either stopping of GPT output or comparator edge was detected #1 OSTPF Oscillation Stop Detection Flag 2 2 read-write 0 Stopping of oscillation was not detected #0 1 Stopping of oscillation was detected #1 SSF Software Stop Flag 3 3 read-write 0 Software has not stopped output #0 1 Software has stopped output #1 PIDE Port Input Detection Enable 4 4 read-write 0 Detection of input levels on the corresponding GTETRGn pin is disabled #0 1 Detection of input levels on the corresponding GTETRGn pin is enabled #1 IOCE GPT Output Stop Request Enable 5 5 read-write 0 Detection of stopping of output from the GPT is disabled #0 1 Detection of stopping of output from the GPT is enabled #1 OSTPE Enable Stopping Output on Stopping of Oscillation 6 6 read-write 0 Detection of stopping of oscillation is disabled #0 1 Detection of stopping of oscillation is enabled #1 CDRE0 ACMPHS0 Enable 8 8 read-write 0 Comparator edge detection 0 is disabled #0 1 Comparator edge detection 0 is enabled #1 CDRE1 ACMPHS1 Enable 9 9 read-write 0 Comparator edge detection 1 is disabled #0 1 Comparator edge detection 1 is enabled #1 CDRE2 ACMPHS2 Enable 10 10 read-write 0 Comparator edge detection 2 is disabled #0 1 Comparator edge detection 2 is enabled #1 CDRE3 ACMPHS3 Enable 11 11 read-write 0 Comparator edge detection 3 is disabled #0 1 Comparator edge detection 3 is enabled #1 ST GTETRGn Input Status Flag 16 16 read-only 0 The corresponding external trigger for output to the GPT is 0 #0 1 The corresponding external trigger for output to the GPT is 1 #1 INV GTETRGn Input Inverting 28 28 read-write 0 Input on the GTETRGn pin is not inverted #0 1 Input on the GTETRGn pin is inverted #1 NFEN Noise filter Enable 29 29 read-write 0 Digital noise filter on the GTETRGn pin is disabled #0 1 Digital noise filter on the GTETRGn pin is enabled #1 NFCS Noise filter Clock Select 30 31 read-write 00 Samples the input level of GTETRGn pin three times per PCLKB/1 clock #00 01 Samples the input level of GTETRGn pin three times per PCLKB/8 clock #01 10 Samples the input level of GTETRGn pin three times per PCLKB/32 clock #10 11 Samples the input level of GTETRGn pin three times per PCLKB/128 clock #11 GTONCWPD GPT Output Stopping Control Group D Write Protection Register 0x340 16 read-write 0x0000 0xffff WP Register Writing Disable 0 0 read-write 0 Writing to the GTONCCRn register is enabled #0 1 Writing to the GTONCCRn register is disabled #1 PRKEY Key Code 8 15 read-write GTONCCRD GPT Output Stopping Control Group D Controlling Register 0x344 16 read-write 0x0100 0xffff NE Direct Stopping Request Setting 0 0 read-write 0 The signal for detection is not set as a direct stopping request signal #0 1 The signal for detection is set as a direct stopping request signal #1 NFS Direct Stopping Request Selection 4 7 read-write 0x0 Comparator level detection 0 0x0 0x1 Comparator level detection 1 0x1 0x2 Comparator level detection 2 0x2 0x4 Comparator level detection 3 0x4 0x7 GTETRGn pin input level detection (n = A to D) 0x7 Others Setting prohibited true NFV Direct Stopping Request Active Sense 8 8 read-write 0 Stopping output is requested when the output stopping detection signal is 0 #0 1 Stopping output is requested when the output stopping detection signal is 1 #1 CANFD_B CANFD Module Control 0x400B0000 0x00 16 registers 0x14 160 registers 0xB8 4 registers 0xC0 16 registers 0xD8 4 registers 0x100 20 registers 0x120 268 registers 0x280 256 registers 0x520 604 registers 0x920 680 registers 0xD20 680 registers 0x1120 680 registers 0x1520 680 registers CFDC0NCFG Channel 0 Nominal Bitrate Configuration Register 0x0000 32 read-write 0x00000000 0xffffffff NBRP Channel Nominal Baud Rate Prescaler 0 9 read-write NSJW Resynchronization Jump Width 10 16 read-write NTSEG1 Timing Segment 1 17 24 read-write NTSEG2 Timing Segment 2 25 31 read-write CFDC0CTR Channel 0 Control Register 0x0004 32 read-write 0x00000005 0xffffffff CHMDC Channel Mode Control 0 1 read-write 00 Channel operation mode request #00 01 Channel reset request #01 10 Channel halt request #10 11 Keep current value #11 CSLPR Channel Sleep Request 2 2 read-write 0 Channel sleep request disabled #0 1 Channel sleep request enabled #1 RTBO Return from Bus-Off 3 3 read-write 0 Channel is not forced to return from bus-off #0 1 Channel is forced to return from bus-off #1 BEIE Bus Error Interrupt Enable 8 8 read-write 0 Bus error interrupt disabled #0 1 Bus error interrupt enabled #1 EWIE Error Warning Interrupt Enable 9 9 read-write 0 Error warning interrupt disabled #0 1 Error warning interrupt enabled #1 EPIE Error Passive Interrupt Enable 10 10 read-write 0 Error passive interrupt disabled #0 1 Error passive interrupt enabled #1 BOEIE Bus-Off Entry Interrupt Enable 11 11 read-write 0 Bus-off entry interrupt disabled #0 1 Bus-off entry interrupt enabled #1 BORIE Bus-Off Recovery Interrupt Enable 12 12 read-write 0 Bus-off recovery interrupt disabled #0 1 Bus-off recovery interrupt enabled #1 OLIE Overload Interrupt Enable 13 13 read-write 0 Overload interrupt disabled #0 1 Overload interrupt enabled #1 BLIE Bus Lock Interrupt Enable 14 14 read-write 0 Bus lock interrupt disabled #0 1 Bus lock interrupt enabled #1 ALIE Arbitration Lost Interrupt Enable 15 15 read-write 0 Arbitration lost interrupt disabled #0 1 Arbitration lost interrupt enabled #1 TAIE Transmission Abort Interrupt Enable 16 16 read-write 0 TX abort interrupt disabled #0 1 TX abort interrupt enabled #1 EOCOIE Error Occurrence Counter Overflow Interrupt Enable 17 17 read-write 0 Error occurrence counter overflow interrupt disabled #0 1 Error occurrence counter overflow interrupt enabled #1 SOCOIE Successful Occurrence Counter Overflow Interrupt Enable 18 18 read-write 0 Successful occurrence counter overflow interrupt disabled #0 1 Successful occurrence counter overflow interrupt enabled #1 TDCVFIE Transceiver Delay Compensation Violation Interrupt Enable 19 19 read-write 0 Transceiver delay compensation violation interrupt disabled #0 1 Transceiver delay compensation violation interrupt enabled #1 BOM Channel Bus-Off Mode 21 22 read-write 00 Normal mode (comply with ISO 11898-1) #00 01 Entry to Halt mode automatically at bus-off start #01 10 Entry to Halt mode automatically at bus-off end #10 11 Entry to Halt mode (during bus-off recovery period) by software #11 ERRD Channel Error Display 23 23 read-write 0 Only the first set of error codes displayed #0 1 Accumulated error codes displayed #1 CTME Channel Test Mode Enable 24 24 read-write 0 Channel test mode disabled #0 1 Channel test mode enabled #1 CTMS Channel Test Mode Select 25 26 read-write 00 Basic test mode #00 01 Listen-only mode #01 10 Self-test mode 0 (External loopback mode) #10 11 Self-test mode 1 (Internal loopback mode) #11 BFT Bit Flip Test 30 30 read-write 0 First data bit of reception stream not inverted #0 1 First data bit of reception stream inverted #1 ROM Restricted Operation Mode 31 31 read-write 0 Restricted operation mode disabled #0 1 Restricted operation mode enabled #1 CFDC0STS Channel 0 Status Register 0x0008 32 read-write 0x00000005 0xffffffff CRSTSTS Channel Reset Status 0 0 read-only 0 Channel not in Reset mode #0 1 Channel in Reset mode #1 CHLTSTS Channel Halt Status 1 1 read-only 0 Channel not in Halt mode #0 1 Channel in Halt mode #1 CSLPSTS Channel Sleep Status 2 2 read-only 0 Channel not in Sleep mode #0 1 Channel in Sleep mode #1 EPSTS Channel Error Passive Status 3 3 read-only 0 Channel not in error passive state #0 1 Channel in error passive state #1 BOSTS Channel Bus-Off Status 4 4 read-only 0 Channel not in bus-off state #0 1 Channel in bus-off state #1 TRMSTS Channel Transmit Status 5 5 read-only 0 Channel is not transmitting #0 1 Channel is transmitting #1 RECSTS Channel Receive Status 6 6 read-only 0 Channel is not receiving #0 1 Channel is receiving #1 COMSTS Channel Communication Status 7 7 read-only 0 Channel is not ready for communication #0 1 Channel is ready for communication #1 ESIF Error State Indication Flag 8 8 read-write 0 No CANFD message has been received when the ESI flag was set #0 1 At least one CANFD message was received when the ESI flag was set #1 REC Reception Error Count 16 23 read-only TEC Transmission Error Count 24 31 read-only CFDC0ERFL Channel 0 Error Flag Register 0x000C 32 read-write 0x00000000 0xffffffff BEF Bus Error Flag 0 0 read-write 0 Channel bus error not detected #0 1 Channel bus error detected #1 EWF Error Warning Flag 1 1 read-write 0 Channel error warning not detected #0 1 Channel error warning detected #1 EPF Error Passive Flag 2 2 read-write 0 Channel error passive not detected #0 1 Channel error passive detected #1 BOEF Bus-Off Entry Flag 3 3 read-write 0 Channel bus-off entry not detected #0 1 Channel bus-off entry detected #1 BORF Bus-Off Recovery Flag 4 4 read-write 0 Channel bus-off recovery not detected #0 1 Channel bus-off recovery detected #1 OVLF Overload Flag 5 5 read-write 0 Channel overload not detected #0 1 Channel overload detected #1 BLF Bus Lock Flag 6 6 read-write 0 Channel bus lock not detected #0 1 Channel bus lock detected #1 ALF Arbitration Lost Flag 7 7 read-write 0 Channel arbitration lost not detected #0 1 Channel arbitration lost detected #1 SERR Stuff Error 8 8 read-write 0 Channel stuff error not detected #0 1 Channel stuff error detected #1 FERR Form Error 9 9 read-write 0 Channel form error not detected #0 1 Channel form error detected #1 AERR Acknowledge Error 10 10 read-write 0 Channel acknowledge error not detected #0 1 Channel acknowledge error detected #1 CERR CRC Error 11 11 read-write 0 Channel CRC error not detected #0 1 Channel CRC error detected #1 B1ERR Bit 1 Error 12 12 read-write 0 Channel bit 1 error not detected #0 1 Channel bit 1 error detected #1 B0ERR Bit 0 Error 13 13 read-write 0 Channel bit 0 error not detected #0 1 Channel bit 0 error detected #1 ADERR Acknowledge Delimiter Error 14 14 read-write 0 Channel acknowledge delimiter error not detected #0 1 Channel acknowledge delimiter error detected #1 CRCREG CRC Register value 16 30 read-only CFDGCFG Global Configuration Register 0x0014 32 read-write 0x00000000 0xffffffff TPRI Transmission Priority 0 0 read-write 0 ID priority #0 1 Message buffer number priority #1 DCE DLC Check Enable 1 1 read-write 0 DLC check disabled #0 1 DLC check enabled #1 DRE DLC Replacement Enable 2 2 read-write 0 DLC replacement disabled #0 1 DLC replacement enabled #1 MME Mirror Mode Enable 3 3 read-write 0 Mirror mode disabled #0 1 Mirror mode enabled #1 DCS Data Link Controller Clock Select 4 4 read-write 0 Internal clean clock #0 1 External clock source connected to CANMCLK pin #1 CMPOC CANFD Message Payload Overflow Configuration 5 5 read-write 0 Message is rejected #0 1 Message payload is cut to fit to configured message size #1 TSP Timestamp Prescaler 8 11 read-write TSSS Timestamp Source Select 12 12 read-write 0 Source clock for timestamp counter is peripheral clock #0 1 Source clock for timestamp counter is bit time clock #1 ITRCP Interval Timer Reference Clock Prescaler 16 31 read-write CFDGCTR Global Control Register 0x0018 32 read-write 0x00000005 0xffffffff GMDC Global Mode Control 0 1 read-write 00 Global operation mode request #00 01 Global reset mode request #01 10 Global halt mode request #10 11 Keep current value #11 GSLPR Global Sleep Request 2 2 read-write 0 Global sleep request disabled #0 1 Global sleep request enabled #1 DEIE DLC Check Interrupt Enable 8 8 read-write 0 DLC check interrupt disabled #0 1 DLC check interrupt enabled #1 MEIE Message Lost Error Interrupt Enable 9 9 read-write 0 Message lost error interrupt disabled #0 1 Message lost error interrupt enabled #1 THLEIE TX History List Entry Lost Interrupt Enable 10 10 read-write 0 TX history list entry lost interrupt disabled #0 1 TX history list entry lost interrupt enabled #1 CMPOFIE CANFD Message Payload Overflow Flag Interrupt Enable 11 11 read-write 0 CANFD message payload overflow flag interrupt disabled #0 1 CANFD message payload overflow flag interrupt enabled #1 TSRST Timestamp Reset 16 16 read-write 0 Timestamp not reset #0 1 Timestamp reset #1 CFDGSTS Global Status Register 0x001C 32 read-only 0x0000000d 0xffffffff GRSTSTS Global Reset Status 0 0 read-only 0 Not in Reset mode #0 1 In Reset mode #1 GHLTSTS Global Halt Status 1 1 read-only 0 Not in Halt mode #0 1 In Halt mode #1 GSLPSTS Global Sleep Status 2 2 read-only 0 Not in Sleep mode #0 1 In Sleep mode #1 GRAMINIT Global RAM Initialization 3 3 read-only 0 RAM initialization is complete #0 1 RAM initialization is ongoing #1 CFDGERFL Global Error Flag Register 0x0020 32 read-write 0x00000000 0xffffffff DEF DLC Error Flag 0 0 read-write 0 DLC error not detected #0 1 DLC error detected #1 MES Message Lost Error Status 1 1 read-only 0 Message lost error not detected #0 1 Message lost error detected #1 THLES TX History List Entry Lost Error Status 2 2 read-only 0 TX history list entry lost error not detected #0 1 TX history list entry lost error detected #1 CMPOF CANFD Message Payload Overflow Flag 3 3 read-write 0 CANFD message payload overflow not detected #0 1 CANFD message payload overflow detected #1 EEF0 ECC Error Flag 16 16 read-write 0 ECC error not detected during TX-SCAN #0 1 ECC error detected during TX-SCAN #1 CFDGTSC Global Timestamp Counter Register 0x0024 32 read-only 0x00000000 0xffffffff TS Timestamp value 0 15 read-only CFDGAFLECTR Global Acceptance Filter List Entry Control Register 0x0028 32 read-write 0x00000000 0xffffffff AFLPN Acceptance Filter List Page Number 0 0 read-write AFLDAE Acceptance Filter List Data Access Enable 8 8 read-write 0 Acceptance Filter List data access disabled #0 1 Acceptance Filter List data access enabled #1 CFDGAFLCFG Global Acceptance Filter List Configuration Register 0x002C 32 read-write 0x00000000 0xffffffff RNC0 Rule Number 16 21 read-write CFDRMNB RX Message Buffer Number Register 0x0030 32 read-write 0x00000000 0xffffffff NRXMB Number of RX Message Buffers 0 5 read-write RMPLS Reception Message Buffer Payload Data Size 8 10 read-write 000 8 bytes #000 001 12 bytes #001 010 16 bytes #010 011 20 bytes #011 100 24 bytes #100 101 32 bytes #101 110 48 bytes #110 111 64 bytes #111 CFDRMND RX Message Buffer New Data Register 0x0034 32 read-write 0x00000000 0xffffffff RMNS RX Message Buffer New Data Status 0 31 read-write 0 New data not stored in corresponding RX message buffer #0 1 New data stored in corresponding RX message buffer #1 CFDRMIEC RX Message Buffer Interrupt Enable Configuration Register 0x0038 32 read-write 0x00000000 0xffffffff RMIEg RX Message Buffer Interrupt Enable 0 31 read-write 0 RX Message Buffer Interrupt disabled for corresponding RX message buffer #0 1 RX Message Buffer Interrupt enabled for corresponding RX message buffer #1 2 0x04 0-1 CFDRFCC%s RX FIFO Configuration/Control Registers %s 0x003C 32 read-write 0x00000000 0xffffffff RFE RX FIFO Enable 0 0 read-write 0 FIFO disabled #0 1 FIFO enabled #1 RFIE RX FIFO Interrupt Enable 1 1 read-write 0 FIFO interrupt generation disabled #0 1 FIFO interrupt generation enabled #1 RFPLS Rx FIFO Payload Data Size Configuration 4 6 read-write 000 8 bytes #000 001 12 bytes #001 010 16 bytes #010 011 20 bytes #011 100 24 bytes #100 101 32 bytes #101 110 48 bytes #110 111 64 bytes #111 RFDC RX FIFO Depth Configuration 8 10 read-write 000 FIFO Depth = 0 message #000 001 FIFO Depth = 4 messages #001 010 FIFO Depth = 8 messages #010 011 FIFO Depth = 16 messages #011 100 FIFO Depth = 32 essages #100 101 FIFO Depth = 48 messages #101 110 Reserved #110 111 Reserved #111 RFIM RX FIFO Interrupt Mode 12 12 read-write 0 Interrupt generated when RX FIFO counter reaches RFIGCV value from values smaller than RFIGCV #0 1 Interrupt generated at the end of every received message storage #1 RFIGCV RX FIFO Interrupt Generation Counter Value 13 15 read-write 000 Interrupt generated when FIFO is 1/8th full #000 001 Interrupt generated when FIFO is 1/4th full #001 010 Interrupt generated when FIFO is 3/8th full #010 011 Interrupt generated when FIFO is 1/2 full #011 100 Interrupt generated when FIFO is 5/8th full #100 101 Interrupt generated when FIFO is 3/4th full #101 110 Interrupt generated when FIFO is 7/8th full #110 111 Interrupt generated when FIFO is full #111 2 0x04 0-1 CFDRFSTS%s RX FIFO Status Registers %s 0x0044 32 read-write 0x00000001 0xffffffff RFEMP RX FIFO Empty 0 0 read-only 0 FIFO not empty #0 1 FIFO empty #1 RFFLL RX FIFO Full 1 1 read-only 0 FIFO not full #0 1 FIFO full #1 RFMLT RX FIFO Message Lost 2 2 read-write 0 No message lost in FIFO #0 1 FIFO message lost #1 RFIF RX FIFO Interrupt Flag 3 3 read-write 0 FIFO interrupt condition not satisfied #0 1 FIFO interrupt condition satisfied #1 RFMC RX FIFO Message Count 8 13 read-only 2 0x04 0-1 CFDRFPCTR%s RX FIFO Pointer Control Registers %s 0x004C 32 write-only 0x00000000 0xffffffff RFPC RX FIFO Pointer Control 0 7 write-only CFDCFCC Common FIFO Configuration/Control Register 0x0054 32 read-write 0x00000000 0xffffffff CFE Common FIFO Enable 0 0 read-write 0 FIFO disabled #0 1 FIFO enabled #1 CFRXIE Common FIFO RX Interrupt Enable 1 1 read-write 0 FIFO interrupt generation disabled for Frame RX #0 1 FIFO interrupt generation enabled for Frame RX #1 CFTXIE Common FIFO TX Interrupt Enable 2 2 read-write 0 FIFO interrupt generation disabled for Frame TX #0 1 FIFO interrupt generation enabled for Frame TX #1 CFPLS Common FIFO Payload Data Size Configuration 4 6 read-write 000 8 bytes #000 001 12 bytes #001 010 16 bytes #010 011 20 bytes #011 100 24 bytes #100 101 32 bytes #101 110 48 bytes #110 111 64 bytes #111 CFM Common FIFO Mode 8 8 read-write 0 RX FIFO mode #0 1 TX FIFO mode #1 CFITSS Common FIFO Interval Timer Source Select 10 10 read-write 0 Reference clock (× 1 / × 10 period) #0 1 Bit time clock of related channel (FIFO is linked to fixed channel) #1 CFITR Common FIFO Interval Timer Resolution 11 11 read-write 0 Reference clock period × 1 #0 1 Reference clock period × 10 #1 CFIM Common FIFO Interrupt Mode 12 12 read-write 0 RX FIFO mode: RX interrupt generated when Common FIFO counter reaches CFIGCV value from a lower value TX FIFO mode: TX interrupt generated when Common FIFO transmits the last message successfully #0 1 RX FIFO mode: RX interrupt generated at the end of every received message storage TX FIFO mode: interrupt generated for every successfully transmitted message #1 CFIGCV Common FIFO Interrupt Generation Counter Value 13 15 read-write 000 Interrupt generated when FIFO is 1/8th full #000 001 Interrupt generated when FIFO is 1/4th full #001 010 Interrupt generated when FIFO is 3/8th full #010 011 Interrupt generated when FIFO is 1/2 full #011 100 Interrupt generated when FIFO is 5/8th full #100 101 Interrupt generated when FIFO is 3/4th full #101 110 Interrupt generated when FIFO is 7/8th full #110 111 Interrupt generated when FIFO is full #111 CFTML Common FIFO TX Message Buffer Link 16 17 read-write CFDC Common FIFO Depth Configuration 21 23 read-write 000 FIFO Depth = 0 message #000 001 FIFO Depth = 4 messages #001 010 FIFO Depth = 8 messages #010 011 FIFO Depth = 16 messages #011 100 FIFO Depth = 32 messages #100 101 FIFO Depth = 48 messages #101 110 FIFO Depth = Reserved #110 111 FIFO Depth = Reserved #111 CFITT Common FIFO Interval Transmission Time 24 31 read-write CFDCFSTS Common FIFO Status Register 0x0058 32 read-write 0x00000001 0xffffffff CFEMP Common FIFO Empty 0 0 read-only 0 FIFO not empty #0 1 FIFO empty #1 CFFLL Common FIFO Full 1 1 read-only 0 FIFO not full #0 1 FIFO full #1 CFMLT Common FIFO Message Lost 2 2 read-write 0 Number of message lost in FIFO #0 1 FIFO message lost #1 CFRXIF Common RX FIFO Interrupt Flag 3 3 read-write 0 FIFO interrupt condition not satisfied after frame reception #0 1 FIFO interrupt condition satisfied after frame reception #1 CFTXIF Common TX FIFO Interrupt Flag 4 4 read-write 0 FIFO interrupt condition not satisfied after frame transmission #0 1 FIFO Interrupt condition satisfied after frame transmission #1 CFMC Common FIFO Message Count 8 13 read-only CFDCFPCTR Common FIFO Pointer Control Register 0x005C 32 write-only 0x00000000 0xffffffff CFPC Common FIFO Pointer Control 0 7 write-only CFDFESTS FIFO Empty Status Register 0x0060 32 read-only 0x00000103 0xffffffff RFXEMP RX FIFO Empty Status 0 1 read-only 0 Corresponding FIFO not empty #0 1 Corresponding FIFO empty #1 CFEMP Common FIFO Empty Status 8 8 read-only 0 Corresponding FIFO not empty #0 1 Corresponding FIFO empty #1 CFDFFSTS FIFO Full Status Register 0x0064 32 read-only 0x00000000 0xffffffff RFXFLL RX FIF0 Full Status 0 1 read-only 0 Corresponding FIFO not full #0 1 Corresponding FIFO full #1 CFFLL Common FIF0 Full Status 8 8 read-only 0 Corresponding FIFO not full #0 1 Corresponding FIFO full #1 CFDFMSTS FIFO Message Lost Status Register 0x0068 32 read-only 0x00000000 0xffffffff RFXMLT RX FIFO Message Lost Status 0 1 read-only 0 Corresponding FIFO Message Lost flag not set #0 1 Corresponding FIFO Message Lost flag set #1 CFMLT Common FIFO Message Lost Status 8 8 read-only 0 Corresponding FIFO Message Lost flag not set #0 1 Corresponding FIFO Message Lost flag set #1 CFDRFISTS RX FIFO Interrupt Flag Status Register 0x006C 32 read-only 0x00000000 0xffffffff RFXIF RX FIFO[x] Interrupt Flag Status 0 1 read-only 0 Corresponding RX FIFO Interrupt flag not set #0 1 Corresponding RX FIFO Interrupt flag set #1 4 0x01 0-3 CFDTMC%s TX Message Buffer Control Registers %s 0x0070 8 read-write 0x00 0xff TMTR TX Message Buffer Transmission Request 0 0 read-write 0 TX Message buffer transmission not requested #0 1 TX message buffer transmission requested #1 TMTAR TX Message Buffer Transmission Abort Request 1 1 read-write 0 TX message buffer transmission request abort not requested #0 1 TX message buffer transmission request abort requested #1 TMOM TX Message Buffer One-shot Mode 2 2 read-write 0 TX message buffer not configured in one-shot mode #0 1 TX message buffer configured in one-shot mode #1 4 0x01 0-3 CFDTMSTS%s TX Message Buffer Status Registers %s 0x0074 8 read-write 0x00 0xff TMTSTS TX Message Buffer Transmission Status 0 0 read-only 0 No on-going transmission #0 1 On-going transmission #1 TMTRF TX Message Buffer Transmission Result Flag 1 2 read-write 00 No result #00 01 Transmission aborted from the TX message buffer #01 10 Transmission successful from the TX message buffer and transmission abort was not requested #10 11 Transmission successful from the TX message buffer and transmission abort was requested #11 TMTRM TX Message Buffer Transmission Request Mirrored 3 3 read-only 0 TX message buffer transmission not requested #0 1 TX message buffer transmission requested #1 TMTARM TX Message Buffer Transmission Abort Request Mirrored 4 4 read-only 0 TX message buffer transmission request abort not requested #0 1 TX message buffer transmission request abort requested #1 CFDTMTRSTS TX Message Buffer Transmission Request Status Register 0x0078 32 read-only 0x00000000 0xffffffff CFDTMTRSTS TX Message Buffer Transmission Request Status 0 3 read-only 0 Transmission not requested for corresponding TX message buffer #0 1 Transmission requested for corresponding TX message buffer #1 CFDTMTARSTS TX Message Buffer Transmission Abort Request Status Register 0x007C 32 read-only 0x00000000 0xffffffff CFDTMTARSTS TX Message Buffer Transmission Abort Request Status 0 3 read-only 0 Transmission abort not requested for corresponding TX message buffer #0 1 Transmission abort requested for corresponding TX message buffer #1 CFDTMTCSTS TX Message Buffer Transmission Completion Status Register 0x0080 32 read-only 0x00000000 0xffffffff CFDTMTCSTS TX Message Buffer Transmission Completion Status 0 3 read-only 0 Transmission not complete for corresponding TX message buffer #0 1 Transmission completed for corresponding TX message buffer #1 CFDTMTASTS TX Message Buffer Transmission Abort Status Register 0x0084 32 read-only 0x00000000 0xffffffff CFDTMTASTS TX Message Buffer Transmission Abort Status 0 3 read-only 0 Transmission not aborted for corresponding TX message buffer #0 1 Transmission aborted for corresponding TX message buffer #1 CFDTMIEC TX Message Buffer Interrupt Enable Configuration Register 0x0088 32 read-write 0x00000000 0xffffffff TMIEg TX Message Buffer Interrupt Enable 0 3 read-write 0 TX message buffer interrupt disabled for corresponding TX message buffer #0 1 TX message buffer interrupt enabled for corresponding TX message buffer #1 CFDTXQCC TX Queue Configuration/Control Register 0x008C 32 read-write 0x00000000 0xffffffff TXQE TX Queue Enable 0 0 read-write 0 TX Queue disabled #0 1 TX Queue enabled #1 TXQTXIE TX Queue TX Interrupt Enable 5 5 read-write 0 TX Queue TX interrupt disabled #0 1 TX Queue TX interrupt enabled #1 TXQIM TX Queue Interrupt Mode 7 7 read-write 0 When the last message is successfully transmitted #0 1 At every successful transmission #1 TXQDC TX Queue Depth Configuration 8 9 read-write 0x00 0 messages 0x00 0x01 Reserved 0x01 0x10 3 messages 0x10 0x11 4 messages 0x11 CFDTXQSTS TX Queue Status Register 0x0090 32 read-write 0x00000001 0xffffffff TXQEMP TX Queue Empty 0 0 read-only 0 TX Queue not empty #0 1 TX Queue empty #1 TXQFLL TX Queue Full 1 1 read-only 0 TX Queue not full #0 1 TX Queue full #1 TXQTXIF TX Queue TX Interrupt Flag 2 2 read-write 0 TX Queue interrupt condition not satisfied after a frame TX #0 1 TX Queue interrupt condition satisfied after a frame TX #1 TXQMC TX Queue Message Count 8 10 read-only CFDTXQPCTR TX Queue Pointer Control Register 0x0094 32 write-only 0x00000000 0xffffffff TXQPC TX Queue Pointer Control 0 7 write-only CFDTHLCC TX History List Configuration/Control Register 0x0098 32 read-write 0x00000000 0xffffffff THLE TX History List Enable 0 0 read-write 0 TX History List disabled #0 1 TX History List enabled #1 THLIE TX History List Interrupt Enable 8 8 read-write 0 TX History List Interrupt disabled #0 1 TX History List Interrupt enabled #1 THLIM TX History List Interrupt Mode 9 9 read-write 0 Interrupt generated if TX History List level reaches ¾ of the TX History List depth #0 1 Interrupt generated for every successfully stored entry #1 THLDTE TX History List Dedicated TX Enable 10 10 read-write 0 TX FIFO + TX Queue #0 1 Flat TX MB + TX FIFO + TX Queue #1 CFDTHLSTS TX History List Status Register 0x009C 32 read-write 0x00000001 0xffffffff THLEMP TX History List Empty 0 0 read-only 0 TX History List not empty #0 1 TX History List empty #1 THLFLL TX History List Full 1 1 read-only 0 TX History List not full #0 1 TX History List full #1 THLELT TX History List Entry Lost 2 2 read-write 0 No entry lost in TX History List #0 1 TX History List entry Lost #1 THLIF TX History List Interrupt Flag 3 3 read-write 0 TX History List interrupt condition not satisfied #0 1 TX History List interrupt condition satisfied #1 THLMC TX History List Message Count 8 11 read-only CFDTHLPCTR TX History List Pointer Control Register 0x00A0 32 write-only 0x00000000 0xffffffff THLPC TX History List Pointer Control 0 7 write-only CFDGTINTSTS Global TX Interrupt Status Register 0x00A4 32 read-only 0x00000000 0xffffffff TSIF0 TX Successful Interrupt Flag 0 0 read-only 0 Channel n TX Successful Interrupt flag not set #0 1 Channel n TX Successful Interrupt flag set #1 TAI0 TX Abort Interrupt Flag 1 1 read-only 0 Channel n TX Abort Interrupt flag not set #0 1 Channel n TX Abort Interrupt flag set #1 TQIF0 TX Queue Interrupt Flag 2 2 read-only 0 Channel n TX Queue Interrupt flag not set #0 1 Channel n TX Queue Interrupt flag set #1 CFTIF0 COM FIFO TX Mode Interrupt Flag 3 3 read-only 0 Channel n COM FIFO TX Mode Interrupt flag not set #0 1 Channel n COM FIFO TX Mode Interrupt flag set #1 THIF0 TX History List Interrupt 4 4 read-only 0 Channel n TX History List Interrupt flag not set #0 1 Channel n TX History List Interrupt flag set #1 CFDGTSTCFG Global Test Configuration Register 0x00A8 32 read-write 0x00000000 0xffffffff RTMPS RAM Test Mode Page Select 16 19 read-write CFDGTSTCTR Global Test Control Register 0x00AC 32 read-write 0x00000000 0xffffffff RTME RAM Test Mode Enable 2 2 read-write 0 RAM test mode disabled #0 1 RAM test mode enabled #1 CFDGFDCFG Global FD Configuration Register 0x00B0 32 read-write 0x00000000 0xffffffff RPED RES Bit Protocol Exception Disable 0 0 read-write 0 Protocol exception event detection enabled #0 1 Protocol exception event detection disabled #1 TSCCFG Timestamp Capture Configuration 8 9 read-write 00 Timestamp capture at the sample point of SOF (start of frame) #00 01 Timestamp capture at frame valid indication #01 10 Timestamp capture at the sample point of RES bit #10 11 Reserved #11 CFDGLOCKK Global Lock Key Register 0x00B8 32 write-only 0x00000000 0xffffffff LOCK Lock Key 0 15 write-only CFDGAFLIGNENT Global AFL Ignore Entry Register 0x00C0 32 read-write 0x00000000 0xffffffff IRN Ignore Rule Number 0 4 read-write CFDGAFLIGNCTR Global AFL Ignore Control Register 0x00C4 32 read-write 0x00000000 0xffffffff IREN Ignore Rule Enable 0 0 read-write 0 AFL entry number is not ignored #0 1 AFL entry number is ignored #1 KEY Key Code 8 15 write-only CFDCDTCT DMA Transfer Control Register 0x00C8 32 read-write 0x00000000 0xffffffff RFDMAE0 DMA Transfer Enable for RXFIFO 0 0 0 read-write 0 DMA transfer request disabled #0 1 DMA transfer request enabled #1 RFDMAE1 DMA Transfer Enable for RXFIFO 1 1 1 read-write 0 DMA transfer request disabled #0 1 DMA transfer request enabled #1 CFDMAE DMA Transfer Enable for Common FIFO 0 8 8 read-write 0 DMA transfer request disabled #0 1 DMA transfer request enabled #1 CFDCDTSTS DMA Transfer Status Register 0x00CC 32 read-only 0x00000000 0xffffffff RFDMASTS0 DMA Transfer Status for RX FIFO 0 0 0 read-only 0 DMA transfer stopped #0 1 DMA transfer on going #1 RFDMASTS1 DMA Transfer Status for RX FIFO 1 1 1 read-only 0 DMA transfer stopped #0 1 DMA transfer on going #1 CFDMASTS DMA Transfer Status only for Common FIFO 8 8 read-only 0 DMA transfer stopped #0 1 DMA transfer on going #1 CFDGRSTC Global SW reset Register 0x00D8 32 read-write 0x00000000 0xffffffff SRST SW Reset 0 0 read-write 0 Normal state #0 1 SW reset state #1 KEY Key Code 8 15 write-only CFDC0DCFG Channel 0 Data Bitrate Configuration Register 0x0100 32 read-write 0x00000000 0xffffffff DBRP Channel Data Baud Rate Prescaler 0 7 read-write DTSEG1 Timing Segment 1 8 12 read-write DTSEG2 Timing Segment 2 16 19 read-write DSJW Resynchronization Jump Width 24 27 read-write CFDC0FDCFG Channel 0 CANFD Configuration Register 0x0104 32 read-write 0x00000000 0xbfffffff EOCCFG Error Occurrence Counter Configuration 0 2 read-write 000 All transmitter or receiver CAN frames #000 001 All transmitter CAN frames #001 010 All receiver CAN frames #010 011 Reserved #011 100 Only transmitter or receiver CANFD data-phase (fast bits) #100 101 Only transmitter CANFD data-phase (fast bits) #101 110 Only receiver CANFD data-phase (fast bits) #110 111 Reserved #111 TDCOC Transceiver Delay Compensation Offset Configuration 8 8 read-write 0 Measured + offset #0 1 Offset-only #1 TDCE Transceiver Delay Compensation Enable 9 9 read-write 0 Transceiver delay compensation disabled #0 1 Transceiver delay compensation enabled #1 ESIC Error State Indication Configuration 10 10 read-write 0 The ESI bit in the frame represents the error state of the node itself #0 1 The ESI bit in the frame represents the error state of the message buffer if the node itself is not in error passive. If the node is in error passive, then the ESI bit is driven by the node itself. #1 TDCO Transceiver Delay Compensation Offset 16 23 read-write FDOE FD-Only Enable 28 28 read-write 0 FD-only mode disabled #0 1 FD-only mode enabled #1 REFE RX Edge Filter Enable 29 29 read-write 0 RX edge filter disabled #0 1 RX edge filter enabled #1 CLOE Classical CAN Enable 30 30 read-write 0 Classical CAN mode disabled #0 1 Classical CAN mode enabled #1 CFDC0FDCTR Channel 0 CANFD Control Register 0x0108 32 read-write 0x00000000 0xffffffff EOCCLR Error Occurrence Counter Clear 0 0 read-write 0 No error occurrence counter clear #0 1 Clear error occurrence counter #1 SOCCLR Successful Occurrence Counter Clear 1 1 read-write 0 No successful occurrence counter clear #0 1 Clear successful occurrence counter #1 CFDC0FDSTS Channel 0 CANFD Status Register 0x010C 32 read-write 0x00000000 0xffffffff TDCR Transceiver Delay Compensation Result 0 7 read-only EOCO Error Occurrence Counter Overflow 8 8 read-write 0 Error occurrence counter has not overflowed #0 1 Error occurrence counter has overflowed #1 SOCO Successful Occurrence Counter Overflow 9 9 read-write 0 Successful occurrence counter has not overflowed #0 1 Successful occurrence counter has overflowed #1 TDCVF Transceiver Delay Compensation Violation Flag 15 15 read-write 0 Transceiver delay compensation violation has not occurred #0 1 Transceiver delay compensation violation has occurred #1 EOC Error Occurrence Counter 16 23 read-only SOC Successful occurrence counter 24 31 read-only CFDC0FDCRC Channel 0 CANFD CRC Register 0x0110 32 read-write 0x00000000 0xffffffff CRCREG CRC Register value 0 20 read-only SCNT Stuff bit count 24 27 read-only 16 0x0010 1-16 CFDGAFLID%s Global Acceptance Filter List ID Registers 0x0120 32 read-write 0x00000000 0xffffffff GAFLID Global Acceptance Filter List Entry ID Field 0 28 read-write GAFLLB Global Acceptance Filter List Entry Loopback Configuration 29 29 read-write 0 Global Acceptance Filter List entry ID for acceptance filtering with attribute RX #0 1 Global Acceptance Filter List entry ID for acceptance filtering with attribute TX #1 GAFLRTR Global Acceptance Filter List Entry RTR Field 30 30 read-write 0 Data frame #0 1 Remote frame #1 GAFLIDE Global Acceptance Filter List Entry IDE Field 31 31 read-write 0 Standard identifier of rule entry ID is valid for acceptance filtering #0 1 Extended identifier of rule entry ID is valid for acceptance filtering #1 16 0x0010 1-16 CFDGAFLM%s Global Acceptance Filter List Mask Registers 0x0124 32 read-write 0x00000000 0xffffffff GAFLIDM Global Acceptance Filter List ID Mask Field 0 28 read-write GAFLIFL1 Global Acceptance Filter List Information Label 1 29 29 read-write GAFLRTRM Global Acceptance Filter List Entry RTR Mask 30 30 read-write 0 RTR bit is not used for ID matching #0 1 RTR bit is used for ID matching #1 GAFLIDEM Global Acceptance Filter List IDE Mask 31 31 read-write 0 IDE bit is not used for ID matching #0 1 IDE bit is used for ID matching #1 16 0x0010 1-16 CFDGAFLP0%s Global Acceptance Filter List Pointer 0 Registers 0x0128 32 read-write 0x00000000 0xffffffff GAFLDLC Global Acceptance Filter List DLC Field 0 3 read-write GAFLIFL0 Global Acceptance Filter List Information Label 0 7 7 read-write GAFLRMDP Global Acceptance Filter List RX Message Buffer Direction Pointer 8 12 read-write GAFLRMV Global Acceptance Filter List RX Message Buffer Valid 15 15 read-write 0 Single message buffer direction pointer is invalid #0 1 Single message buffer direction pointer is valid #1 GAFLPTR Global Acceptance Filter List Pointer 16 31 read-write 16 0x0010 1-16 CFDGAFLP1%s Global Acceptance Filter List Pointer 1 Registers 0x012C 32 read-write 0x00000000 0xffffffff GAFLFDP0 Global Acceptance Filter List FIFO Direction Pointer 0 0 read-write 0 Disable RX FIFO 0 as target for reception #0 1 Enable RX FIFO 0 as target for reception #1 GAFLFDP1 Global Acceptance Filter List FIFO Direction Pointer 1 1 read-write 0 Disable RX FIFO 1 as target for reception #0 1 Enable RX FIFO 1 as target for reception #1 GAFLFDP8 Global Acceptance Filter List FIFO Direction Pointer 8 8 read-write 0 Disable Common FIFO as target for reception #0 1 Enable Common FIFO as target for reception #1 64 0x0004 0-63 CFDRPGACC%s RAM Test Page Access Registers %s 0x0280 32 read-write 0x00000000 0xffffffff RDTA RAM Data Test Access 0 31 read-write 2 0x004C 0-1 CFDRFID%s RX FIFO Access ID Register %s 0x0520 32 read-only 0x00000000 0xffffffff RFID RX FIFO Buffer ID Field 0 28 read-only RFRTR RX FIFO Buffer RTR bit 30 30 read-only 0 Data frame #0 1 Remote frame #1 RFIDE RX FIFO Buffer IDE bit 31 31 read-only 0 STD-ID has been received #0 1 EXT-ID has been received #1 2 0x004C 0-1 CFDRFPTR%s RX FIFO Access Pointer Register %s 0x0524 32 read-only 0x00000000 0xffffffff RFTS RX FIFO Timestamp Value 0 15 read-only RFDLC RX FIFO Buffer DLC Field 28 31 read-only 2 0x004C 0-1 CFDRFFDSTS%s RX FIFO Access CANFD Status Register %s 0x0528 32 read-only 0x00000000 0xffffffff RFESI Error State Indicator bit 0 0 read-only 0 CANFD frame received from error active node #0 1 CANFD frame received from error passive node #1 RFBRS Bit Rate Switch bit 1 1 read-only 0 CANFD frame received with no bit rate switch #0 1 CANFD frame received with bit rate switch #1 RFFDF CAN FD Format bit 2 2 read-only 0 Non CANFD frame received #0 1 CANFD frame received #1 RFIFL RX FIFO Buffer Information Label Field 8 9 read-only CFDRFPTR RX FIFO Buffer Pointer Field 16 31 read-only 2 0x04C 0-1 CFDRFDF%s_0 RX FIFO Access Data Field 0 Register %s 0x052C 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_1 RX FIFO Access Data Field 1 Register %s 0x0530 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_2 RX FIFO Access Data Field 2 Register %s 0x0534 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_3 RX FIFO Access Data Field 3 Register %s 0x0538 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_4 RX FIFO Access Data Field 4 Register %s 0x053C 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_5 RX FIFO Access Data Field 5 Register %s 0x0540 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_6 RX FIFO Access Data Field 6 Register %s 0x0544 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_7 RX FIFO Access Data Field 7 Register %s 0x0548 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_8 RX FIFO Access Data Field 8 Register %s 0x054C 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_9 RX FIFO Access Data Field 9 Register %s 0x0550 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_10 RX FIFO Access Data Field 10 Register %s 0x0554 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_11 RX FIFO Access Data Field 11 Register %s 0x0558 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_12 RX FIFO Access Data Field 12 Register %s 0x055C 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_13 RX FIFO Access Data Field 13 Register %s 0x0560 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_14 RX FIFO Access Data Field 14 Register %s 0x0564 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only 2 0x04C 0-1 CFDRFDF%s_15 RX FIFO Access Data Field 15 Register %s 0x0568 32 read-only 0x00000000 0xffffffff RFDB_LL RX FIFO Buffer Data Byte (p × 4) 0 7 read-only RFDB_LH RX FIFO Buffer Data Byte ((p × 4) + 1) 8 15 read-only RFDB_HL RX FIFO Buffer Data Byte ((p × 4) + 2) 16 23 read-only RFDB_HH RX FIFO Buffer Data Byte ((p × 4) + 3) 24 31 read-only CFDCFID Common FIFO Access ID Register 0x05B8 32 read-write 0x00000000 0xffffffff CFID Common FIFO Buffer ID Field 0 28 read-write THLEN THL Entry enable 29 29 read-write 0 Entry will not be stored in THL after successful TX. #0 1 Entry will be stored in THL after successful TX. #1 CFRTR Common FIFO Buffer RTR Bit 30 30 read-write 0 Data Frame #0 1 Remote Frame #1 CFIDE Common FIFO Buffer IDE Bit 31 31 read-write 0 STD-ID will be transmitted or has been received #0 1 EXT-ID will be transmitted or has been received #1 CFDCFPTR Common FIFO Access Pointer Register 0x05BC 32 read-write 0x00000000 0xffffffff CFTS Common FIFO Timestamp Value 0 15 read-write CFDLC Common FIFO Buffer DLC Field 28 31 read-write CFDCFFDCSTS Common FIFO Access CANFD Control/Status Register 0x05C0 32 read-write 0x00000000 0xffffffff CFESI Error State Indicator bit 0 0 read-write 0 CANFD frame received or to transmit by error active node #0 1 CANFD frame received or to transmit by error passive node #1 CFBRS Bit Rate Switch bit 1 1 read-write 0 CANFD frame received or to transmit with no bit rate switch #0 1 CANFD frame received or to transmit with bit rate switch #1 CFFDF CAN FD Format bit 2 2 read-write 0 Non CANFD frame received or to transmit #0 1 CANFD frame received or to transmit #1 CFIFL COMMON FIFO Buffer Information Label Field 8 9 read-write CFPTR Common FIFO Buffer Pointer Field 16 31 read-write 16 0x004 0-15 CFDCFDF%s Common FIFO Access Data Field %s Registers 0x05C4 32 read-write 0x00000000 0xffffffff CFDB_LL Common FIFO Buffer Data Bytes (p × 4) 0 7 read-write CFDB_LH Common FIFO Buffer Data Bytes ((p × 4) + 1) 8 15 read-write CFDB_HL Common FIFO Buffer Data Bytes ((p × 4) + 2) 16 23 read-write CFDB_HH Common FIFO Buffer Data Bytes ((p × 4) + 3) 24 31 read-write 4 0x004C 0-3 CFDTMID%s TX Message Buffer ID Registers 0x0604 32 read-write 0x00000000 0xffffffff TMID TX Message Buffer ID Field 0 28 read-write THLEN Tx History List Entry 29 29 read-write 0 Entry not stored in THL after successful TX #0 1 Entry stored in THL after successful TX #1 TMRTR TX Message Buffer RTR bit 30 30 read-write 0 Data frame #0 1 Remote frame #1 TMIDE TX Message Buffer IDE bit 31 31 read-write 0 STD-ID is transmitted #0 1 EXT-ID is transmitted #1 4 0x004C 0-3 CFDTMPTR%s TX Message Buffer Pointer Register 0x0608 32 read-write 0x00000000 0xffffffff TMDLC TX Message Buffer DLC Field 28 31 read-write 4 0x004C 0-3 CFDTMFDCTR%s TX Message Buffer CANFD Control Register 0x060C 32 read-write 0x00000000 0xffffffff TMESI Error State Indicator bit 0 0 read-write 0 CANFD frame to transmit by error active node #0 1 CANFD frame to transmit by error passive node #1 TMBRS Bit Rate Switch bit 1 1 read-write 0 CANFD frame to transmit with no bit rate switch #0 1 CANFD frame to transmit with bit rate switch #1 TMFDF CAN FD Format bit 2 2 read-write 0 Non CANFD frame to transmit #0 1 CANFD frame to transmit #1 TMIFL TX Message Buffer Information Label Field 8 9 read-write TMPTR TX Message Buffer Pointer Field 16 31 read-write 4 0x04c 0-3 CFDTMDF%s_0 TX Message Buffer Data Field Register 0x0610 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_1 TX Message Buffer Data Field Register 0x0614 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_2 TX Message Buffer Data Field Register 0x0618 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_3 TX Message Buffer Data Field Register 0x061C 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_4 TX Message Buffer Data Field Register 0x0620 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_5 TX Message Buffer Data Field Register 0x0624 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_6 TX Message Buffer Data Field Register 0x0628 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_7 TX Message Buffer Data Field Register 0x062C 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_8 TX Message Buffer Data Field Register 0x0630 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_9 TX Message Buffer Data Field Register 0x0634 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_10 TX Message Buffer Data Field Register 0x0638 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_11 TX Message Buffer Data Field Register 0x063C 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_12 TX Message Buffer Data Field Register 0x0640 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_13 TX Message Buffer Data Field Register 0x0644 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_14 TX Message Buffer Data Field Register 0x0648 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write 4 0x04c 0-3 CFDTMDF%s_15 TX Message Buffer Data Field Register 0x064C 32 read-write 0x00000000 0xffffffff TMDB_LL TX Message Buffer Data Byte ((p × 4) 0 7 read-write TMDB_LH TX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-write TMDB_HL TX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-write TMDB_HH TX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-write CFDTHLACC0 TX History List Access Register 0 0x0740 32 read-only 0x00000000 0xffffffff BT Buffer Type 0 2 read-only 001 Flat TX message buffer #001 010 TX FIFO message buffer number #010 100 TX Queue message buffer number #100 BN Buffer Number 3 4 read-only TMTS Transmit Timestamp 16 31 read-only CFDTHLACC1 TX History List Access Register 1 0x0744 32 read-only 0x00000000 0xffffffff TID Transmit ID 0 15 read-only TIFL Transmit Information Label 16 17 read-only 8 0x004C 0-7 CFDRMID%s RX Message Buffer ID Registers 0x0920 32 read-only 0x00000000 0xffffffff RMID RX Message Buffer ID Field 0 28 read-only RMRTR RX Message Buffer RTR Bit 30 30 read-only 0 Data frame #0 1 Remote frame #1 RMIDE RX Message Buffer IDE Bit 31 31 read-only 0 STD-ID is stored #0 1 EXT-ID is stored #1 8 0x004C 0-7 CFDRMPTR%s RX Message Buffer Pointer Registers 0x0924 32 read-only 0x00000000 0xffffffff RMTS RX Message Buffer Timestamp Field 0 15 read-only RMDLC RX Message Buffer DLC Field 28 31 read-only 8 0x004C 0-7 CFDRMFDSTS%s RX Message Buffer CANFD Status Registers 0x0928 32 read-only 0x00000000 0xffffffff RMESI Error State Indicator bit 0 0 read-only 0 CANFD frame received from error active node #0 1 CANFD frame received from error passive node #1 RMBRS Bit Rate Switch bit 1 1 read-only 0 CANFD frame received with no bit rate switch #0 1 CANFD frame received with bit rate switch #1 RMFDF CAN FD Format bit 2 2 read-only 0 Non CANFD frame received #0 1 CANFD frame received #1 RMIFL RX Message Buffer Information Label Field 8 9 read-only RMPTR RX Message Buffer Pointer Field 16 31 read-only 8 0x004C 0-7 CFDRMDF%s_0 RX Message Buffer Data Field 0 Registers 0x092C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_1 RX Message Buffer Data Field 1 Registers 0x0930 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_2 RX Message Buffer Data Field 2 Registers 0x0934 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_3 RX Message Buffer Data Field 3 Registers 0x0938 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_4 RX Message Buffer Data Field 4 Registers 0x093C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_5 RX Message Buffer Data Field 5 Registers 0x0940 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_6 RX Message Buffer Data Field 6 Registers 0x0944 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_7 RX Message Buffer Data Field 7 Registers 0x0948 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_8 RX Message Buffer Data Field 8 Registers 0x094C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_9 RX Message Buffer Data Field 9 Registers 0x0950 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_10 RX Message Buffer Data Field 10 Registers 0x0954 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_11 RX Message Buffer Data Field 11 Registers 0x0958 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_12 RX Message Buffer Data Field 12 Registers 0x095C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_13 RX Message Buffer Data Field 13 Registers 0x0960 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_14 RX Message Buffer Data Field 14 Registers 0x0964 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 0-7 CFDRMDF%s_15 RX Message Buffer Data Field 15 Registers 0x0968 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMID%s RX Message Buffer ID Registers 0x0D20 32 read-only 0x00000000 0xffffffff RMID RX Message Buffer ID Field 0 28 read-only RMRTR RX Message Buffer RTR Bit 30 30 read-only 0 Data frame #0 1 Remote frame #1 RMIDE RX Message Buffer IDE Bit 31 31 read-only 0 STD-ID is stored #0 1 EXT-ID is stored #1 8 0x004C 8-15 CFDRMPTR%s RX Message Buffer Pointer Registers 0x0D24 32 read-only 0x00000000 0xffffffff RMTS RX Message Buffer Timestamp Field 0 15 read-only RMDLC RX Message Buffer DLC Field 28 31 read-only 8 0x004C 8-15 CFDRMFDSTS%s RX Message Buffer CANFD Status Registers 0x0D28 32 read-only 0x00000000 0xffffffff RMESI Error State Indicator bit 0 0 read-only 0 CANFD frame received from error active node #0 1 CANFD frame received from error passive node #1 RMBRS Bit Rate Switch bit 1 1 read-only 0 CANFD frame received with no bit rate switch #0 1 CANFD frame received with bit rate switch #1 RMFDF CAN FD Format bit 2 2 read-only 0 Non CANFD frame received #0 1 CANFD frame received #1 RMIFL RX Message Buffer Information Label Field 8 9 read-only RMPTR RX Message Buffer Pointer Field 16 31 read-only 8 0x004C 8-15 CFDRMDF%s_0 RX Message Buffer Data Field 0 Registers 0x0D2C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_1 RX Message Buffer Data Field 1 Registers 0x0D30 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_2 RX Message Buffer Data Field 2 Registers 0x0D34 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_3 RX Message Buffer Data Field 3 Registers 0x0D38 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_4 RX Message Buffer Data Field 4 Registers 0x0D3C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_5 RX Message Buffer Data Field 5 Registers 0x0D40 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_6 RX Message Buffer Data Field 6 Registers 0x0D44 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_7 RX Message Buffer Data Field 7 Registers 0x0D48 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_8 RX Message Buffer Data Field 8 Registers 0x0D4C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_9 RX Message Buffer Data Field 9 Registers 0x0D50 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_10 RX Message Buffer Data Field 10 Registers 0x0D54 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_11 RX Message Buffer Data Field 11 Registers 0x0D58 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_12 RX Message Buffer Data Field 12 Registers 0x0D5C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_13 RX Message Buffer Data Field 13 Registers 0x0D60 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_14 RX Message Buffer Data Field 14 Registers 0x0D64 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 8-15 CFDRMDF%s_15 RX Message Buffer Data Field 15 Registers 0x0D68 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMID%s RX Message Buffer ID Registers 0x01120 32 read-only 0x00000000 0xffffffff RMID RX Message Buffer ID Field 0 28 read-only RMRTR RX Message Buffer RTR Bit 30 30 read-only 0 Data frame #0 1 Remote frame #1 RMIDE RX Message Buffer IDE Bit 31 31 read-only 0 STD-ID is stored #0 1 EXT-ID is stored #1 8 0x004C 16-23 CFDRMPTR%s RX Message Buffer Pointer Registers 0x01124 32 read-only 0x00000000 0xffffffff RMTS RX Message Buffer Timestamp Field 0 15 read-only RMDLC RX Message Buffer DLC Field 28 31 read-only 8 0x004C 16-23 CFDRMFDSTS%s RX Message Buffer CANFD Status Registers 0x01128 32 read-only 0x00000000 0xffffffff RMESI Error State Indicator bit 0 0 read-only 0 CANFD frame received from error active node #0 1 CANFD frame received from error passive node #1 RMBRS Bit Rate Switch bit 1 1 read-only 0 CANFD frame received with no bit rate switch #0 1 CANFD frame received with bit rate switch #1 RMFDF CAN FD Format bit 2 2 read-only 0 Non CANFD frame received #0 1 CANFD frame received #1 RMIFL RX Message Buffer Information Label Field 8 9 read-only RMPTR RX Message Buffer Pointer Field 16 31 read-only 8 0x004C 16-23 CFDRMDF%s_0 RX Message Buffer Data Field 0 Registers 0x112C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_1 RX Message Buffer Data Field 1 Registers 0x1130 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_2 RX Message Buffer Data Field 2 Registers 0x1134 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_3 RX Message Buffer Data Field 3 Registers 0x1138 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_4 RX Message Buffer Data Field 4 Registers 0x113C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_5 RX Message Buffer Data Field 5 Registers 0x1140 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_6 RX Message Buffer Data Field 6 Registers 0x1144 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_7 RX Message Buffer Data Field 7 Registers 0x1148 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_8 RX Message Buffer Data Field 8 Registers 0x114C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_9 RX Message Buffer Data Field 9 Registers 0x1150 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_10 RX Message Buffer Data Field 10 Registers 0x1154 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_11 RX Message Buffer Data Field 11 Registers 0x1158 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_12 RX Message Buffer Data Field 12 Registers 0x115C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_13 RX Message Buffer Data Field 13 Registers 0x1160 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_14 RX Message Buffer Data Field 14 Registers 0x1164 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 16-23 CFDRMDF%s_15 RX Message Buffer Data Field 15 Registers 0x1168 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMID%s RX Message Buffer ID Registers 0x01520 32 read-only 0x00000000 0xffffffff RMID RX Message Buffer ID Field 0 28 read-only RMRTR RX Message Buffer RTR Bit 30 30 read-only 0 Data frame #0 1 Remote frame #1 RMIDE RX Message Buffer IDE Bit 31 31 read-only 0 STD-ID is stored #0 1 EXT-ID is stored #1 8 0x004C 24-31 CFDRMPTR%s RX Message Buffer Pointer Registers 0x01524 32 read-only 0x00000000 0xffffffff RMTS RX Message Buffer Timestamp Field 0 15 read-only RMDLC RX Message Buffer DLC Field 28 31 read-only 8 0x004C 24-31 CFDRMFDSTS%s RX Message Buffer CANFD Status Registers 0x01528 32 read-only 0x00000000 0xffffffff RMESI Error State Indicator bit 0 0 read-only 0 CANFD frame received from error active node #0 1 CANFD frame received from error passive node #1 RMBRS Bit Rate Switch bit 1 1 read-only 0 CANFD frame received with no bit rate switch #0 1 CANFD frame received with bit rate switch #1 RMFDF CAN FD Format bit 2 2 read-only 0 Non CANFD frame received #0 1 CANFD frame received #1 RMIFL RX Message Buffer Information Label Field 8 9 read-only RMPTR RX Message Buffer Pointer Field 16 31 read-only 8 0x004C 24-31 CFDRMDF%s_0 RX Message Buffer Data Field 0 Registers 0x152C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_1 RX Message Buffer Data Field 1 Registers 0x1530 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_2 RX Message Buffer Data Field 2 Registers 0x1534 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_3 RX Message Buffer Data Field 3 Registers 0x1538 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_4 RX Message Buffer Data Field 4 Registers 0x153C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_5 RX Message Buffer Data Field 5 Registers 0x1540 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_6 RX Message Buffer Data Field 6 Registers 0x1544 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_7 RX Message Buffer Data Field 7 Registers 0x1548 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_8 RX Message Buffer Data Field 8 Registers 0x154C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_9 RX Message Buffer Data Field 9 Registers 0x1550 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_10 RX Message Buffer Data Field 10 Registers 0x1554 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_11 RX Message Buffer Data Field 11 Registers 0x1558 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_12 RX Message Buffer Data Field 12 Registers 0x155C 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_13 RX Message Buffer Data Field 13 Registers 0x1560 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_14 RX Message Buffer Data Field 14 Registers 0x1564 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only 8 0x004C 24-31 CFDRMDF%s_15 RX Message Buffer Data Field 15 Registers 0x1568 32 read-only 0x00000000 0xffffffff RMDB_LL RX Message Buffer Data Byte (p × 4) 0 7 read-only RMDB_LH RX Message Buffer Data Byte ((p × 4) + 1) 8 15 read-only RMDB_HL RX Message Buffer Data Byte ((p × 4) + 2) 16 23 read-only RMDB_HH RX Message Buffer Data Byte ((p × 4) + 3) 24 31 read-only PSCU Peripheral Security Control Unit 0x400E0000 0x04 44 registers PSARB Peripheral Security Attribution Register B 0x04 32 read-write 0xffffffff 0xffffffff PSARB8 IIC1 and the MSTPCRB.MSTPB8 bit security attribution 8 8 read-write 0 Secure #0 1 Non-secure #1 PSARB9 IIC0 and the MSTPCRB.MSTPB9 bit security attribution 9 9 read-write 0 Secure #0 1 Non-secure #1 PSARB18 SPI1 and the MSTPCRB.MSTPB18 bit security attribution 18 18 read-write 0 Secure #0 1 Non-secure #1 PSARB19 SPI0 and the MSTPCRB.MSTPB19 bit security attribution 19 19 read-write 0 Secure #0 1 Non-secure #1 PSARB22 SCI9 and the MSTPCRB.MSTPB22 bit security attribution 22 22 read-write 0 Secure #0 1 Non-secure #1 PSARB27 SCI4 and the MSTPCRB.MSTPB27 bit security attribution 27 27 read-write 0 Secure #0 1 Non-secure #1 PSARB28 SCI3 and the MSTPCRB.MSTPB28 bit security attribution 28 28 read-write 0 Secure #0 1 Non-secure #1 PSARB29 SCI2 and the MSTPCRB.MSTPB29 bit security attribution 29 29 read-write 0 Secure #0 1 Non-secure #1 PSARB30 SCI1 and the MSTPCRB.MSTPB30 bit security attribution 30 30 read-write 0 Secure #0 1 Non-secure #1 PSARB31 SCI0 and the MSTPCRB.MSTPB31 bit security attribution 31 31 read-write 0 Secure #0 1 Non-secure #1 PSARC Peripheral Security Attribution Register C 0x08 32 read-write 0xffffffff 0xffffffff PSARC0 CAC and the MSTPCRC.MSTPC0 bit security attribution 0 0 read-write 0 Secure #0 1 Non-secure #1 PSARC1 CRC and the MSTPCRC.MSTPC1 bit security attribution 1 1 read-write 0 Secure #0 1 Non-secure #1 PSARC13 DOC and the MSTPCRC.MSTPC13 bit security attribution 13 13 read-write 0 Secure #0 1 Non-secure #1 PSARC20 TFU and the MSTPCRC.MSTPC20 bit security attribution 20 20 read-write 0 Secure #0 1 Non-secure #1 PSARC21 IIRFA and the MSTPCRC.MSTPC21 bit security attribution 21 21 read-write 0 Secure #0 1 Non-secure #1 PSARC27 CANFD and the MSTPCRC.MSTPC27 bit security attribution 27 27 read-write 0 Secure #0 1 Non-secure #1 PSARC31 SCE5 and the MSTPCRC.MSTPC31 bit security attribution 31 31 read-write 0 Secure #0 1 Non-secure #1 PSARD Peripheral Security Attribution Register D 0x0C 32 read-write 0xffffffff 0xffffffff PSARD2 AGT1 and the MSTPCRD.MSTPD2 bit security attribution 2 2 read-write 0 Secure #0 1 Non-secure #1 PSARD3 AGT0 and the MSTPCRD.MSTPD3 bit security attribution 3 3 read-write 0 Secure #0 1 Non-secure #1 PSARD11 POEG Group D and the MSTPCRD.MSTPD11 bit security attribution 11 11 read-write 0 Secure #0 1 Non-secure #1 PSARD12 POEG Group C and the MSTPCRD.MSTPD12 bit security attribution 12 12 read-write 0 Secure #0 1 Non-secure #1 PSARD13 POEG Group B and the MSTPCRD.MSTPD13 bit security attribution 13 13 read-write 0 Secure #0 1 Non-secure #1 PSARD14 POEG Group A and the MSTPCRD.MSTPD14 bit security attribution 14 14 read-write 0 Secure #0 1 Non-secure #1 PSARD16 ADC and the MSTPCRD.MSTPD16 bit security attribution 16 16 read-write 0 Secure #0 1 Non-secure #1 PSARD19 DAC12 unit1 and the MSTPCRD.MSTPD19 bit security attribution 19 19 read-write 0 Secure #0 1 Non-secure #1 PSARD20 DAC12 unit0 and the MSTPCRD.MSTPD20 bit security attribution 20 20 read-write 0 Secure #0 1 Non-secure #1 PSARD22 TSN and the MSTPCRD.MSTPD22 bit security attribution 22 22 read-write 0 Secure #0 1 Non-secure #1 PSARD25 ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution 25 25 read-write 0 Secure #0 1 Non-secure #1 PSARD26 ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution 26 26 read-write 0 Secure #0 1 Non-secure #1 PSARD27 ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution 27 27 read-write 0 Secure #0 1 Non-secure #1 PSARD28 ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution 28 28 read-write 0 Secure #0 1 Non-secure #1 PSARE Peripheral Security Attribution Register E 0x10 32 read-write 0xffffffff 0xffffffff PSARE0 WDT security attribution 0 0 read-write 0 Secure #0 1 Non-secure #1 PSARE1 IWDT security attribution 1 1 read-write 0 Secure #0 1 Non-secure #1 PSARE4 KINT and the MSTPCRE.MSTPE4 bit security attribution 4 4 read-write 0 Secure #0 1 Non-secure #1 MSSAR Module Stop Security Attribution Register 0x14 32 read-write 0xffffffff 0xffffffff MSSAR0 The MSTPCRC.MSTPC14 bit security attribution 0 0 read-write 0 Secure #0 1 Non-secure #1 MSSAR1 The MSTPCRA.MSTPA22 bit security attribution 1 1 read-write 0 Secure #0 1 Non-secure #1 MSSAR2 The MSTPCRA.MSTPA7 bit security attribution 2 2 read-write 0 Secure #0 1 Non-secure #1 MSSAR3 The MSTPCRA.MSTPA0 bit security attribution 3 3 read-write 0 Secure #0 1 Non-secure #1 CFSAMONA Code Flash Security Attribution Monitor Register A 0x18 32 read-only 0x00000000 0xff007fff CFS2 Code Flash Secure area 2 15 23 read-only CFSAMONB Code Flash Security Attribution Monitor Register B 0x1C 32 read-only 0x00000000 0xff0003ff CFS1 Code Flash Secure area 1 10 23 read-only DFSAMON Data Flash Security Attribution Monitor Register 0x20 32 read-only 0x00000000 0xffff03ff DFS Data flash Secure area 10 15 read-only SSAMONA SRAM Security Attribution Monitor Register A 0x24 32 read-only 0x00000000 0xffe01fff SS2 SRAM Secure area 2 13 20 read-only SSAMONB SRAM Security Attribution Monitor Register B 0x28 32 read-only 0x00000000 0xffe003ff SS1 SRAM secure area 1 10 20 read-only DLMMON Device Lifecycle Management State Monitor Register 0x2C 32 read-only 0x00000000 0xfffffff0 DLMMON Device Lifecycle Management State Monitor 0 3 read-only 0x1 CM 0x1 0x2 SSD 0x2 0x3 NSECSD 0x3 0x4 DPL 0x4 0x5 LCK_DBG 0x5 0x6 LCK_BOOT 0x6 0x7 RMA_REQ 0x7 0x8 RMA_ACK 0x8 Others Reserved true AGTW_B0 Low Power Asynchronous General Purpose Timer 0 0x400E8000 0x00 15 registers 0x10 4 registers AGT AGT Counter Register 0x00 32 read-write 0xffffffff 0xffffffff AGTCMA AGT CounterCompare Match A Register 0x04 32 read-write 0xffffffff 0xffffffff AGTCMB AGT CounterCompare Match B Register 0x08 32 read-write 0xffffffff 0xffffffff AGTCR AGT Control Register 0x0C 8 read-write 0x00 0xff TSTART AGT Count Start 0 0 read-write 0 Count stops #0 1 Count starts #1 TCSTF AGT Count Status Flag 1 1 read-only 0 Count stopped #0 1 Count in progress #1 TSTOP AGT Count Forced Stop 2 2 write-only 0 Writing is invalid #0 1 The count is forcibly stopped #1 TEDGF Active Edge Judgment Flag 4 4 read-write 0 No active edge received #0 1 Active edge received #1 TUNDF Underflow Flag 5 5 read-write 0 No underflow #0 1 Underflow #1 TCMAF Compare Match A Flag 6 6 read-write 0 No match #0 1 Match #1 TCMBF Compare Match B Flag 7 7 read-write 0 No match #0 1 Match #1 AGTMR1 AGT Mode Register 1 0x0D 8 read-write 0x40 0xff TMOD Operating Mode 0 2 read-write 000 Timer mode #000 001 Pulse output mode #001 010 Event counter mode #010 011 Pulse width measurement mode #011 100 Pulse period measurement mode #100 Others Setting prohibited true TEDGPL Edge Polarity 3 3 read-write 0 Single-edge #0 1 Both-edge #1 TCK Count Source 4 6 read-write 000 PCLKB #000 001 PCLKB/8 #001 011 PCLKB/2 #011 100 Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register #100 101 Underflow event signal from AGTW0 #101 110 Setting prohibited #110 Others Setting prohibited true AGTMR2 AGT Mode Register 2 0x0E 8 read-write 0x00 0xff CKS AGTLCLK Count Source Clock Frequency Division Ratio 0 2 read-write 000 1/1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 111 1/128 #111 LPM Low Power Mode 7 7 read-write 0 Normal mode #0 1 Low power mode #1 AGTIOC AGT I/O Control Register 0x10 8 read-write 0x00 0xff TEDGSEL I/O Polarity Switch 0 0 read-write TOE AGTWOn pin Output Enable 2 2 read-write 0 AGTWOn pin output disabled #0 1 AGTWOn pin output enabled #1 TIPF Input Filter 4 5 read-write 00 No filter #00 01 Filter sampled at PCLKB #01 10 Filter sampled at PCLKB/8 #10 11 Filter sampled at PCLKB/32 #11 TIOGT Count Control 6 7 read-write 00 Event is always counted #00 01 Event is counted during polarity period specified for AGTWEEn pin #01 Others Setting prohibited true AGTISR AGT Event Pin Select Register 0x11 8 read-write 0x00 0xff EEPS AGTWEEn Polarity Selection 2 2 read-write 0 An event is counted during the low-level period #0 1 An event is counted during the high-level period #1 AGTCMSR AGT Compare Match Function Select Register 0x12 8 read-write 0x00 0xff TCMEA AGT Compare Match A Register Enable 0 0 read-write 0 AGT Compare match A register disabled #0 1 AGT Compare match A register enabled #1 TOEA AGTWOAn Pin Output Enable 1 1 read-write 0 AGTWOAn pin output disabled #0 1 AGTWOAn pin output enabled #1 TOPOLA AGTWOAn Pin Polarity Select 2 2 read-write 0 AGTWOAn pin output is started on low. i.e. normal output #0 1 AGTWOAn pin output is started on high. i.e. inverted output #1 TCMEB AGT Compare Match B Register Enable 4 4 read-write 0 Compare match B register disabled #0 1 Compare match B register enabled #1 TOEB AGTWOBn Pin Output Enable 5 5 read-write 0 AGTWOBn pin output disabled #0 1 AGTWOBn pin output enabled #1 TOPOLB AGTWOBn Pin Polarity Select 6 6 read-write 0 AGTWOBn pin output is started on low. i.e. normal output #0 1 AGTWOBn pin output is started on high. i.e. inverted output #1 AGTIOSEL AGT Pin Select Register 0x13 8 read-write 0x00 0xff TIES AGTWIOn Pin Input Enable 4 4 read-write 0 External event input is disabled during Software Standby mode #0 1 External event input is enabled during Software Standby mode #1 AGTW_B1 Low Power Asynchronous General Purpose Timer 1 0x400E8100 TSN Temperature Sensor 0x400F3000 0x00 1 registers TSCR Temperature Sensor Control Register 0x00 8 read-write 0x00 0xff TSOE Temperature Sensor Output Enable 4 4 read-write 0 Disable output from the temperature sensor to the ADC #0 1 Enable output from the temperature sensor to the ADC #1 TSEN Temperature Sensor Enable 7 7 read-write 0 Stop the temperature sensor #0 1 Start the temperature sensor. #1 ACMPHS0 High-Speed Analog Comparator 0 0x400F4000 0x00 1 registers 0x04 1 registers 0x08 1 registers 0x0C 1 registers 0x10 1 registers CMPCTL Comparator Control Register 0x000 8 read-write 0x00 0xff CINV Comparator Output Polarity Selection 0 0 read-write 0 Do not invert comparator output #0 1 Invert comparator output #1 COE Comparator Output Enable 1 1 read-write 0 Disable comparator output (output signal is low level) #0 1 Enable comparator output #1 CEG Selection of Valid Edge (Edge Selector) 3 4 read-write 00 Do not detect edge #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 CDFS Noise Filter Selection 5 6 read-write 00 Do not use noise filter #00 01 Use noise filter sampling frequency of PCLKB/23 #01 10 Use noise filter sampling frequency of PCLKB/24 #10 11 Use noise filter sampling frequency of PCLKB/25 #11 HCMPON Comparator Operation Control 7 7 read-write 0 Stop operation (comparator outputs a low-level signal) #0 1 Enable operation (enables input to the comparator pins) #1 CMPSEL0 Comparator Input Select Register 0x004 8 read-write 0x00 0xff CMPSEL Comparator Input Selection 0 3 read-write 0x0 Do not input 0x0 0x1 Select IVCMP0 0x1 0x2 Setting prohibited 0x2 0x4 Select IVCMP2 0x4 0x8 Select IVCMP3 0x8 Others Setting prohibited true CMPSEL1 Comparator Reference Voltage Select Register 0x008 8 read-write 0x00 0xff CRVS Reference Voltage Selection 0 3 read-write 0x0 Do not input 0x0 0x1 Select IVREF0 0x1 0x2 Select IVREF1 0x2 0x4 Select IVREF2 0x4 0x8 Select IVREF3 0x8 Others Setting prohibited true CMPMON Comparator Output Monitor Register 0x00C 8 read-only 0x00 0xff CMPMON Comparator Output Monitor 0 0 read-only 0 Comparator output is low #0 1 Comparator output is high #1 CPIOC Comparator Output Control Register 0x010 8 read-write 0x00 0xff CPOE Comparator Output Selection 0 0 read-write 0 Disable CMPOUTn pin output of the comparator (output signal is low fixed) #0 1 Enable CMPOUTn pin output of the comparator #1 ACMPHS1 High-Speed Analog Comparator 1 0x400F4100 ACMPHS2 High-Speed Analog Comparator 2 0x400F4200 ACMPHS3 High-Speed Analog Comparator 3 0x400F4300 CRC Cyclic Redundancy Check 0x40108000 0x00 2 registers 0x04 4 registers 0x08 4 registers 0x0C 2 registers CRCCR0 CRC Control Register 0 0x00 8 read-write 0x00 0xff GPS CRC Generating Polynomial Switching 0 2 read-write 001 8-bit CRC-8 (X8 + X2 + X + 1) #001 010 16-bit CRC-16 (X16 + X15 + X2 + 1) #010 011 16-bit CRC-CCITT (X16 + X12 + X5 + 1) #011 100 32-bit CRC-32 (X32 + X26 + X23 + X22 + X16 + X12 + X11 +X10 + X8 + X7 + X5 + X4 + X2 + X + 1) #100 101 32-bit CRC-32C (X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20 + X19 + X18 + X14 + X13 + X11 + X10 + X9 + X8 + X6 + 1) #101 Others No calculation is executed true LMS CRC Calculation Switching 6 6 read-write 0 Generate CRC code for LSB-first communication #0 1 Generate CRC code for MSB-first communication #1 DORCLR CRCDOR/CRCDOR_HA/CRCDOR_BY Register Clear 7 7 write-only 0 No effect #0 1 Clear the CRCDOR/CRCDOR_HA/CRCDOR_BY register #1 CRCCR1 CRC Control Register 1 0x01 8 read-write 0x00 0xff CRCSWR Snoop-On-Write/Read Switch 6 6 read-write 0 Snoop-on-read #0 1 Snoop-on-write #1 CRCSEN Snoop Enable 7 7 read-write 0 Disabled #0 1 Enabled #1 CRCDIR CRC Data Input Register 0x04 32 read-write 0x00000000 0xffffffff CRCDIR_BY CRC Data Input Register CRCDIR 0x04 8 read-write 0x00 0xff CRCDOR CRC Data Output Register 0x08 32 read-write 0x00000000 0xffffffff CRCDOR_HA CRC Data Output Register CRCDOR 0x08 16 read-write 0x0000 0xffff CRCDOR_BY CRC Data Output Register CRCDOR 0x08 8 read-write 0x00 0xff CRCSAR Snoop Address Register 0x0C 16 read-write 0x0000 0xffff CRCSA Register Snoop Address 0 13 read-write DOC_B Data Operation Circuit 0x40109000 0x00 1 registers 0x04 1 registers 0x08 1 registers 0x0C 12 registers DOCR DOC Control Register 0x00 8 read-write 0x00 0xff OMS Operating Mode Select 0 1 read-write 00 Data comparison mode #00 01 Data addition mode #01 10 Data subtraction mode #10 11 Setting prohibited #11 DOBW Data Operation Bit Width Select 3 3 read-write 0 16-bit #0 1 32-bit #1 DCSEL Detection Condition Select 4 6 read-write 000 Mismatch (DODSR0 ≠ DODIR) #000 001 Match (DODSR0 = DODIR) #001 010 Lower (DODSR0 > DODIR) #010 011 Upper (DODSR0 < DODIR) #011 100 Inside window (DODSR0 < DODIR < DODSR1) #100 101 Outside window (DODIR < DODSR0, DODSR1 < DODIR) #101 Others Setting prohibited true DOPCIE Data Operation Circuit Interrupt Enable 7 7 read-write 0 Disables interrupts from the data operation circuit. #0 1 Enables interrupts from the data operation circuit. #1 DOSR DOC Flag Status Register 0x04 8 read-only 0x00 0xff DOPCF Data Operation Circuit Flag 0 0 read-only DOSCR DOC Flag Status Clear Register 0x08 8 write-only 0x00 0xff DOPCFCL DOPCF Clear 0 0 write-only 0 Maintains the DOPCF flag state. #0 1 Clears the DOPCF flag. #1 DODIR DOC Data Input Register 0x0C 32 read-write 0x00000000 0xffffffff DODSR0 DOC Data Setting Register 0 0x10 32 read-write 0x00000000 0xffffffff DODSR1 DOC Data Setting Register 1 0x14 32 read-write 0x00000000 0xffffffff SCI_B0 Serial Communication Interface 0 0x40118000 0x00 29 registers 0x20 8 registers 0x2C 20 registers 0x48 28 registers 0x68 20 registers RDR Receive Data Register 0x00 32 read-only 0x00000000 0xffffffff RDAT Serial receive data 0 8 read-only MPB Multi-processor flag 9 9 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 DR Receive data ready flag 10 10 read-only FPER FIFO parity error flag 11 11 read-only 0 There is no parity error in the data read from the receive-FIFO #0 1 There is parity error in the data read from the receive-FIFO #1 FFER FIFO framing error flag 12 12 read-only 0 There is no framing error in the data read from the receive-FIFO #0 1 There is framing error in the data read from the receive-FIFO #1 ORER Overrun Error flag 24 24 read-only PER Parity error flag 27 27 read-only FER Framing error flag 28 28 read-only TDR Transmit Data Register 0x04 32 read-write 0xffffffff 0xffffffff TDAT Serial transmit data 0 8 read-write MPBT Multi-processor transfer bit flag 9 9 read-write 0 Data transmission cycles #0 1 ID transmission cycles #1 TSYNC Transmit SYNC data 12 12 read-write 0 The Start Bit is transmitted as DATA SYNC. #0 1 The Start Bit is transmitted as COMMAND SYNC. #1 CCR0 Common Control Register 0 0x08 32 read-write 0x00000000 0xffffffff RE Receive Enable 0 0 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 TE Transmit Enable 4 4 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 MPIE Multi-Processor Interrupt Enable 8 8 read-write 0 Non-Multi-Processor reception #0 1 Multi -Processor reception When the data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags to 1 is disabled. When the data with the multiprocessor bit set to 1 is received, the MPIE bit is automatically cleared to 0, and non-multi-processor reception is resumed. If you want to continue receiving operation using the multiprocessor function, set this bit to 1 sufficiently earlier than receiving the STOP bit of the next received frame. (Consider the synchronization delay time.) #1 DCME Data Compare Match Enable 9 9 read-write 0 Address match function is disabled #0 1 Address match function is enabled #1 IDSEL ID frame select 10 10 read-write 0 It's always compared data in spite of the value of the MPB bit. #0 1 It's compared data when the MPB bit is 1 (ID frame) only. #1 RIE Receive Interrupt Enable 16 16 read-write 0 SCIn_RXI and SCIn_ERI interrupt requests are disabled #0 1 SCIn_RXI and SCIn_ERI interrupt requests are enabled #1 TIE Transmit Interrupt Enable 20 20 read-write 0 SCIn_TXI interrupt request is disabled #0 1 SCIn_TXI interrupt request is enabled #1 TEIE Transmit End Interrupt Enable 21 21 read-write 0 SCIn_TEI interrupt request is disabled #0 1 SCIn_TEI interrupt request is enabled #1 SSE SSn Pin Function Enable 24 24 read-write 0 SSn pin function is disabled. #0 1 SSn pin function is enabled. #1 CCR1 Common Control Register 1 0x0C 32 read-write 0x00000010 0xffffffff CTSE CTS Enable 0 0 read-write 0 CTS function is disabled (RTS output function is enabled). #0 1 CTS function is enabled. #1 CTSPEN CTS external pin Enable 1 1 read-write 0 Alternate setting to use CTS and RTS functions as either one pin #0 1 Dedicated setting for separately using CTS and RTS functions with 2 pins #1 SPB2DT Serial port break data select 4 4 read-write 0 When TINV is 0, Low level is output in TXDn pin. When TINV is 1, High level is output in TXDn pin. #0 1 When TINV is 0, High level is output in TXDn pin. When TINV is 1, Low level is output in TXDn pin. #1 SPB2IO Serial port break I/O 5 5 read-write 0 The value of SPB2DT bit is not output in TXDn pin. #0 1 The value of SPB2DT bit is output in TXDn pin. #1 PE Parity Enable 8 8 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 PM Parity Mode 9 9 read-write 0 Selects even parity #0 1 Selects odd parity #1 TINV TXD invert 12 12 read-write 0 Transmit data is not inverted and output to TXDn. #0 1 Transmit data is inverted and output to TXDn. #1 RINV RXD invert 13 13 read-write 0 Received data from RXDn is not inverted and input. #0 1 Received data from RXDn is inverted and input. #1 SPLP Loopback Control 16 16 read-write 0 Normal mode #0 1 Loopback mode #1 SHARPS Half-duplex communication select 20 20 read-write 0 TXDn pin, RXDn pin independent #0 1 TXDn / RXDn pin combination use (Half-duplex communication using TXDn pin) #1 NFCS Noise Filter Clock Select 24 26 read-write 000 The base clock signal divided by 1. #000 001 The on-chip baud rate generator source clock divided by 1. #001 010 The on-chip baud rate generator source clock divided by 2. #010 011 The on-chip baud rate generator source clock divided by 4. #011 100 The on-chip baud rate generator source clock divided by 8. #100 others Setting prohibited. true NFEN Digital Noise Filter Function Enable 28 28 read-write 0 In Asynchronous, Manchester, Simple LIN mode: Disable noise cancellation function for RXDn input signal In Simple IIC mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In Asynchronous, Manchester, Simple LIN mode: Enable noise cancellation function for RXDn input signal In Simple IIC mode: Enable noise cancellation function for SCLn and SDAn input signals #1 CCR2 Common Control Register 2 0x10 32 read-write 0xff00ff04 0xffffffff BCP Base Clock Pulse 0 2 read-write 000 93 clock cycles (S = 93) #000 001 128 clock cycles (S = 128) #001 010 186 clock cycles (S = 186) #010 011 512 clock cycles (S = 512) #011 100 32 clock cycles (S = 32) (Initial value) #100 101 64 clock cycles (S = 64) #101 110 372 clock cycles (S = 372) #110 111 256 clock cycles (S = 256) #111 BGDM Baud Rate Generator Double-Speed Mode Select 4 4 read-write 0 Baud rate generator outputs the clock with single frequency. #0 1 Baud rate generator outputs the clock with doubled frequency. #1 ABCS Asynchronous Mode Base Clock Select 5 5 read-write 0 Selects 16 base clock cycles for 1-bit period. #0 1 Selects 8 base clock cycles for 1-bit period. #1 ABCSE Asynchronous Mode Extended Base Clock Select 6 6 read-write 0 Clock cycles for 1-bit period is decided with combination be-tween CCR2.BGDM and CCR2.ABCS. #0 1 Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator. #1 BRR Bit rate setting 8 15 read-write BRME Bit Modulation Enable 16 16 read-write 0 Bit rate modulation function is disabled. #0 1 Bit rate modulation function is enabled. #1 CKS Clock Select 20 21 read-write 00 TCLK clock (n = 0) #00 01 TCLK/4 clock (n = 1) #01 10 TCLK/16 clock (n = 2) #10 11 TCLK/64 clock (n = 3) #11 MDDR Modulation Duty Setting 24 31 read-write CCR3 Common Control Register 3 0x14 32 read-write 0x00001203 0xffffffff CPHA Clock Phase Select 0 0 read-write 0 Data is sampled at an odd edge and changes at an even edge. (Clock is delayed.) #0 1 Data changes at an odd edge and is sampled at an even edge. (Clock is not delayed) #1 CPOL Clock Polarity Select 1 1 read-write 0 SCKn in idle state is 0. #0 1 SCKn in idle state is 1. #1 BPEN Synchronizer bypass enable 7 7 read-write 0 Synchronizer circuit is not bypassed. #0 1 Synchronizer circuit is bypassed. #1 CHR Character Length 8 9 read-write 00 Transmit/receive in 9-bit data length #00 01 Transmit/receive in 9-bit data length #01 10 Transmit/receive in 8-bit data length (initial value) #10 11 Transmit/receive in 7-bit data length #11 LSBF LSB First select 12 12 read-write 0 MSB first #0 1 LSB first #1 SINV Transmitted/Received Data Invert 13 13 read-write 0 TDR contents are transmitted to TSR as they are. RSR contents are stored to RDR as they are. #0 1 TDR contents are inverted before being transmitted to TSR. RSR contents are inverted and stored to RDR. #1 STP Stop Bit Length 14 14 read-write 0 1 stop bit / Break Delimiter length is 1bit #0 1 2 stop bits / Break Delimiter length is 2bits #1 RXDESEL Asynchronous Start Bit Edge Detection Select 15 15 read-write 0 The low level on the RXDn pin is detected as the start bit. #0 1 A falling edge on the RXDn pin is detected as the start bit. #1 MOD Communication mode select 16 18 read-write 000 Asynchronous mode (Multi-processor mode) #000 001 Smart card interface mode #001 010 Clock synchronous mode #010 011 Simple SPI mode #011 100 Simple IIC mode #100 101 Manchester mode #101 110 Simple LIN mode #110 111 Setting prohibited #111 MP Multi-Processor Mode 19 19 read-write 0 Multi-processor communications function is disabled #0 1 Multi-processor communications function is enabled #1 FM FIFO Mode select 20 20 read-write 0 TDR register, RDR register is non-FIFO buffer configuration #0 1 TDR register, RDR register is FIFO buffer configuration #1 DEN Driver enable 21 21 read-write 0 RS-485 Driver control function disable. #0 1 RS-485 Driver control function enable. #1 CKE Clock enable 24 25 read-write 00 In the case of Asynchronous modeOn-chip baud rate generatorThe SCKn pin is available for use as an I/O port in accord with the I/O port settings. In the case of Manchester mode and Simple LIN modeOn-chip baud rate generatorThe SCKn pin functions as I/O port. In the case of Clock synchronous mode, Simple SPI modeInternal clock (Master operation)The SCKn pin functions as the clock output pin. In the case of Smart card interface mode and CCR3.GM = 0Output disabled (The SCKn pin is available for use as an I/O port in accord with the I/O port settings.) In the case of Smart card interface mode and CCR3.GM = 1Output fixed low #00 01 In the case of Asynchronous modeOn-chip baud rate generatorThe clock with the same frequency as the bit rate is output from the SCKn pin. In the case of Manchester mode and Simple LIN modeProhibited In the case of Clock synchronous mode, Simple SPI modeInternal clock (Master operation)The SCKn pin functions as the clock output pin. In the case of Smart card interface mode and CCR3.GM = 0Clock output In the case of Smart card interface mode and CCR3.GM = 1Clock output #01 10 In the case of Asynchronous modeExternal clock When using the external clock16 times the bit rate should be input from the SCKn pin when CCR2.ABCS bit is 0. Input a clock signal with a frequency 8 times the bit rate when the CCR2.ABCS bit is 1. In the case of Manchester mode and Simple LIN modeProhibited In the case of Clock synchronous mode, Simple SPI modeExternal clock (Slave operation)The SCKn pin functions as the clock input pin. In the case of Smart card interface mode and CCR3.GM = 0Prohibited In the case of Smart card interface mode and CCR3.GM = 1Output fixed high #10 11 In the case of Asynchronous modeExternal clock When using the external clock16 times the bit rate should be input from the SCKn pin when CCR2.ABCS bit is 0. Input a clock signal with a frequency 8 times the bit rate when the CCR2.ABCS bit is 1. In the case of Manchester mode and Simple LIN modeProhibited In the case of Clock synchronous mode, Simple SPI modeExternal clock (Slave operation)The SCKn pin functions as the clock input pin. In the case of Smart card interface mode and CCR3.GM = 0Prohibited In the case of Smart card interface mode and CCR3.GM = 1Clock output #11 GM GSM Mode 28 28 read-write 0 Non-GSM mode operation #0 1 GSM mode operation #1 BLK Block Transfer Mode 29 29 read-write 0 Non-block transfer mode operation #0 1 Block transfer mode operation #1 CCR4 Common Control Register 4 0x18 32 read-write 0x00000000 0xffffffff CMPD Compare Match Data 0 8 read-write ASEN Adjust receive sampling timing enable 16 16 read-write 0 Adjust sampling timing disable. #0 1 Adjust sampling timing enable. #1 ATEN Adjust transmit timing enable 17 17 read-write 0 Adjust transmit timing disable. #0 1 Adjust transmit timing enable. #1 AST Adjustment value for receive Sampling Timing 24 26 read-write 000 1TCLK delay #000 001 2TCLK delay #001 010 3TCLK delay #010 011 4TCLK delay #011 Others Setting prohibited true AJD Adjustment Direction for receive sampling timing 27 27 read-write 0 The sampling timing is adjusted backward to the middle of bit. #0 1 The sampling timing is adjusted forward to the middle of bit. #1 ATT Adjustment value for Transmit timing 28 30 read-write AET Adjustment edge for transmit timing 31 31 read-write 0 When CCR1.TINV is 0, adjust the rising edge timing. When CCR1.TINV is 1, adjust the falling edge timing. #0 1 When CCR1.TINV is 0, adjust the falling edge timing. When CCR1.TINV is 1, adjust the rising edge timing. #1 CESR Communication Enable Status Register 0x1C 8 read-only 0x00 0xff RIST RE Internal status 0 0 read-only 0 RE signal internal state value 0 #0 1 RE signal internal state value 1 #1 TIST TE Internal status 4 4 read-only 0 TE signal internal state value 0 #0 1 TE signal internal state value 1 #1 ICR Simple IIC Control Register 0x20 32 read-write 0x00000000 0xffffffff IICDL SDA Delay Output Select 0 4 read-write IICINTM IIC Interrupt Mode Select 8 8 read-write 0 Use ACK/NACK interrupts. #0 1 Use reception and transmission interrupts #1 IICCSC Clock Synchronization 9 9 read-write 0 No synchronization with the clock signal #0 1 Synchronization with the clock signal #1 IICACKT ACK Transmission Data 13 13 read-write 0 ACK transmission #0 1 NACK transmission and reception of ACK/NACK #1 IICSTAREQ Start Condition Generation 16 16 read-write 0 A start condition is not generated #0 1 A start condition is generated. #1 IICRSTAREQ Restart Condition Generation 17 17 read-write 0 A restart condition is not generated. #0 1 A restart condition is generated. #1 IICSTPREQ Stop Condition Generation 18 18 read-write 0 A stop condition is not generated. #0 1 A stop condition is generated #1 IICSDAS SDA Output Select 20 21 read-write 00 Serial data output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SDAn pin. #10 11 Place the SDAn pin in the high-impedance state. #11 IICSCLS SCL Output Select 22 23 read-write 00 Serial clock output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SCLn pin. #10 11 Place the SCLn pin in the high-impedance state. #11 FCR FIFO Control Register 0x24 32 read-write 0x1f1f0000 0xffffffff DRES Receive data ready error select bit 0 0 read-write 0 reception data full interrupt (SCIn_RXI) #0 1 receive error interrupt (SCIn_ERI) #1 TTRG Transmit FIFO data trigger number 8 12 read-write TFRST Transmit FIFO Data Register Reset 15 15 write-only 0 It is invalid. It does not affect the operation. #0 1 The number of data stored in Transmit-FIFO (TDR register) are made 0 #1 RTRG Receive FIFO data trigger number 16 20 read-write RFRST Receive FIFO Data Register Reset 23 23 write-only 0 It is invalid. It does not affect the operation. #0 1 The number of data stored in Receive-FIFO(RDR register) are made 0 #1 RSTRG RTS Output Active Trigger Number Select 24 28 read-write MCR Manchester Control Register 0x2C 32 read-write 0x00000000 0xffffffff RMPOL Polarity of Received Manchester Code 0 0 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 TMPOL Polarity of Transmit Manchester Code 1 1 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 ERTEN Manchester Edge Retiming Enable 2 2 read-write 0 Disables the receive retiming function #0 1 Enables the receive retiming function #1 SYNVAL SYNC value Setting 4 4 read-write SYNSEL SYNC Select 5 5 read-write 0 The start bit pattern is set with the SYNVAL bit #0 1 The start bit pattern is set with the TSYNC bit. #1 SBSEL Start Bit Select 6 6 read-write 0 The start bit area consists of one bit. #0 1 The start bit area consists of three bits (COMMAND SYNC or DATA SYNC) #1 TPLEN Transmit preface length 8 11 read-write 0x0 Disables the transmit preface generation 0x0 Others Transmit preface length (bit length) true TPPAT Transmit preface pattern 12 13 read-write 00 ALL ZERO #00 01 ZERO ONE #01 10 ONE ZERO #10 11 ALL ONE #11 RPLEN Receive Preface Length 16 19 read-write 0x0 Disables the receive preface generation 0x0 Others Receive preface length (bit length) true RPPAT Receive Preface Pattern 20 21 read-write 00 ALL ZERO #00 01 ZERO ONE #01 10 ONE ZERO #10 11 ALL ONE #11 PFEREN Preface Error Enable 24 24 read-write 0 Does not handle a preface error as an interrupt source #0 1 Handles a preface error as an interrupt source #1 SYEREN Receive SYNC Error Enable 25 25 read-write 0 Does not handle a receive SYNC error as an interrupt source #0 1 Handles a receive SYNC error as an interrupt source #1 SBEREN Start Bit Error Enable 26 26 read-write 0 Does not handle a start bit error as an interrupt source #0 1 Handles a start bit error as an interrupt source #1 DCR Driver Control Register 0x30 32 read-write 0x00000000 0xffffffff DEPOL Driver effective polarity select 0 0 read-write 0 The DEn signal is active high. #0 1 The DEn signal is active low. #1 DEAST Driver Assertion Time 8 12 read-write DENGT Driver negate time 16 20 read-write XCR0 Simple LIN Control Register 0 0x34 32 read-write 0x00000000 0xffffffff TCSS Timer count clock source selection 0 1 read-write 01 TCLK/4 #01 10 TCLK/16 #10 11 TCLK/64 #11 BFE Break Field enable 8 8 read-write 0 No Break Field #0 1 With Break Field #1 CF0RE Control Field 0 enable 9 9 read-write 0 No Control Field 0 #0 1 With Control Field 0 #1 CF1DS Control Field1 compare data select 10 11 read-write 00 Select XCR1.PCF1D[7:0] as the compare data #00 01 Select XCR1.SCF1D[7:0] as the compare data #01 10 Select both XCR1.PCF1D[7:0] and XCR1.SCF1D[7:0] as the compare data #10 11 Setting prohibited #11 PIBE Priority interrupt bit enable 12 12 read-write 0 Priority interrupt bit disable #0 1 Priority interrupt bit enable #1 PIBS Priority interrupt bit select 13 15 read-write 000 bit 0 of Control Field 1 #000 001 bit 1 of Control Field 1 #001 010 bit 2 of Control Field 1 #010 011 bit 3 of Control Field 1 #011 100 bit 4 of Control Field 1 #100 101 bit 5 of Control Field 1 #101 110 bit 6 of Control Field 1 #110 111 bit 7 of Control Field 1 #111 BFOIE Break Field output completion interrupt enable 16 16 read-write 0 Break Field output completion is not included in SCIn_TXI interrupt factor #0 1 Break Field output completion is included in SCIn_TXI interrupt factor #1 BCDIE Bus conflict detection interrupt enable 17 17 read-write 0 Bus conflict detection is not included in SCIn_ERI interrupt factor #0 1 Bus conflict detection is included in SCIn_ERI interrupt factor #1 BFDIE Break Field detection interrupt enable 20 20 read-write 0 Break Field detection interrupt disable #0 1 Break Field detection interrupt enable #1 COFIE Counter overflow interrupt enable 21 21 read-write 0 Counter overflow is not included in SCIn_ERI interrupt factor #0 1 Counter overflow is included in SCIn_ERI interrupt factor #1 AEDIE Active edge detection interrupt enable 22 22 read-write 0 Active edge detection interrupt disable #0 1 Active edge detection interrupt enable #1 BCCS Bus conflict detection clock selection 24 25 read-write 00 Base clock #00 01 Base clock/2 #01 10 Base clock/4 #10 11 Setting prohibited #11 XCR1 Simple LIN Control Register 1 0x38 32 read-write 0x00000000 0xffffffff TCST Break Field output timer count start trigger 0 0 read-write 0 Break Field output timer count stopped #0 1 Break Field output timer count start #1 SDST Start Frame detection enable 4 4 read-write 0 Start Frame/Break Field detection disabled #0 1 Start Frame/Break Field detection enabled #1 BMEN Bit rate measurement enable 5 5 read-write 0 Bit rate measurement disabled #0 1 Bit rate measurement enabled #1 PCF1D Priority compare data for Control Field 1 8 15 read-write SCF1D Secondary compare data for Control Field 1 16 23 read-write CF1CE Control Field 1 compare bit enable 24 31 read-write 0 Control Field 1 bit N compare disabled #0 1 Control Field 1 bit N compare enabled #1 XCR2 Simple LIN Control Register 2 0x3C 32 read-write 0xfffe0000 0xffffffff CF0D Control Field 0 compare data 0 7 read-write CF0CE Control Field 0 compare bit enable 8 15 read-write 0 Control Field 0 bit N compare disabled #0 1 Control Field 0 bit N compare enabled #1 BFLW Break Field length setting 16 31 read-write CSR Common Status Register 0x48 32 read-only 0x60008000 0xffffffff ERS Error Signal Status Flag 4 4 read-only 0 Error signal Low not responded #0 1 Error signal Low responded #1 RXDMON Serial input data monitor bit 15 15 read-only 0 When RINV is 0, RXDn pin is the Low level. When RINV is 1, RXDn pin is the High level. #0 1 When RINV is 0, RXDn pin is the High level. When RINV is 1, RXDn pin is the Low level. #1 DCMF Data Compare Match Flag 16 16 read-only 0 No matched #0 1 Matched #1 DPER Data Compare Match Parity Error Flag 17 17 read-only 0 No parity error occurred at address match detection #0 1 A parity error has occurred at address match detection #1 DFER Data Compare Match Framing Error Flag 18 18 read-only 0 No framing error occurred at address match detection #0 1 A framing error has occurred at address match detection #1 ORER Overrun Error Flag 24 24 read-only 0 No overrun error occurred #0 1 An overrun error has occurred #1 MFF Mode Fault Flag 26 26 read-only 0 No mode fault error #0 1 Mode fault error #1 PER Parity Error Flag 27 27 read-only 0 Non-FIFO selected (CCR3.FM = 0): No parity error occurred FIFO selected (CCR3.FM = 1): No parity error in all received data in receive-FIFO #0 1 Non-FIFO selected (CCR3.FM = 0): A parity error has occurred FIFO selected (CCR3.FM = 1): One or more parity errors occurred in received data in receive-FIFO #1 FER Framing Error Flag 28 28 read-only 0 Non-FIFO selected (CCR3.FM = 0): No framing error occurred FIFO selected (CCR3.FM = 1): No framing error in all received data in receive-FIFO #0 1 Non-FIFO selected (CCR3.FM = 0): A framing error has occurred FIFO selected (CCR3.FM = 1): One or more framing errors occurred in received data in receive-FIFO #1 TDRE Transmit Data Empty Flag 29 29 read-only 0 Non-FIFO selected (CCR3.FM = 0): Transmit data is in TDR register FIFO selected (CCR3.FM = 1): The quantity of transmit data written in transmit-FIFO exceeds the specified transmit triggering number. #0 1 Non-FIFO selected (CCR3.FM = 0): No transmit data is in TDR register FIFO selected (CCR3.FM = 1): The quantity of transmit data written in transmit-FIFO is equal to or less than the specified transmit triggering number. #1 TEND Transmit End Flag 30 30 read-only 0 A character is being transmitted or standing by for transmission. #0 1 Character transfer has been completed, or sending Break Field. #1 RDRF Receive Data Full Flag 31 31 read-only 0 Non-FIFO selected (CCR3.FM = 0): No received data is in RDR register FIFO selected (CCR3.FM = 1): The quantity of receive data written in receive-FIFO falls below the specified receive triggering number. #0 1 Non-FIFO selected (CCR3.FM = 0): Received data is in RDR register FIFO selected (CCR3.FM = 1): The quantity of receive data written in receive-FIFO is equal to or greater than the specified receive triggering number. #1 ISR Simple IIC Status Register 0x4C 32 read-only 0x00000000 0xffffffcb IICACKR ACK Reception Data Flag 0 0 read-only 0 ACK received #0 1 NACK received #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 3 read-only 0 There are no requests for generating conditions or a condition is being generated. #0 1 A start, restart, or stop condition is completely generated. #1 FRSR FIFO Receive Status Register 0x50 32 read-only 0x00000000 0xfffffffd DR Receive Data Ready flag 0 0 read-only 0 Receiving is in progress, or no received data has remained in receive-FIFO after normally completed receiving.(receive-FIFO is empty) #0 1 The following receive data does not come for a fixed period after storing data under the threshold in the receive-FIFO #1 R Receive-FIFO Data Count 8 13 read-only PNUM Parity Error Count 16 21 read-only FNUM Framing Error Count 24 29 read-only FTSR FIFO Transmit Status Register 0x54 32 read-only 0x00000000 0xffffffff T Transmit-FIFO Data Count 0 5 read-only MSR Manchester Status Register 0x58 32 read-only 0x00000000 0xffffffff PFER Preface Error flag 0 0 read-only 0 No preface error detected #0 1 Preface error detected #1 SYER SYNC Error flag 1 1 read-only 0 No receive SYNC error detected #0 1 Receive SYNC error detected #1 SBER Start Bit Error flag 2 2 read-only 0 No start bit error detected #0 1 Start bit error detected #1 MER Manchester Error Flag 4 4 read-only 0 No Manchester error occurred #0 1 Manchester error has occurred #1 RSYNC Receive SYNC data bit 6 6 read-only 0 The received the Start Bit is DATA SYNC #0 1 The received the Start Bit is COMMAND SYNC #1 XSR0 Simple LIN Status Register 0 0x5C 32 read-only 0x00000000 0xffffffff SFSF Start Frame Status flag 0 0 read-only 0 Start Frame detection disabled or Start Frame detection complete #0 1 Before Start Frame detection or during detection #1 RXDSF RXDn input status flag 1 1 read-only 0 RXDn input to SCI is enabled #0 1 RXDn input to SCI is disabled #1 BFOF Break Field Output completion flag 8 8 read-only 0 When Break Field is not output or during output #0 1 When Break Field output is completed #1 BCDF Bus Conflict detection flag 9 9 read-only 0 When no Bus Conflict is detected #0 1 When Bus Conflict is detected #1 BFDF Break Field detection flag 10 10 read-only 0 When Break Field is not detected #0 1 When Break Field is detected #1 CF0MF Control Field 0 compare match flag 11 11 read-only 0 When Control-Field-0 data and the compare data does not match #0 1 When Control-Field-0 data and the compare data match #1 CF1MF Control Field 1 compare match flag 12 12 read-only 0 When Control-Field-1 data and the compare data does not match #0 1 When Control-Field-1 data and the compare data match #1 PIBDF Priority interrupt bit detection flag 13 13 read-only 0 When Priority interrupt bit is not detected #0 1 When Priority interrupt bit is detected #1 COF Counter Overflow flag 14 14 read-only 0 When the counter for Break Field detection does not overflows #0 1 When the counter for Break Field detection overflows #1 AEDF Active Edge detection flag 15 15 read-only 0 When Active edge is not detected #0 1 When Active edge is detected #1 CF0RD Control Field 0 received data 16 23 read-only CF1RD Control Field 1 received data 24 31 read-only XSR1 Simple LIN Status Register 1 0x60 32 read-only 0x00000000 0xffffffff TCNT Timer Count Capture value 0 15 read-only CFCLR Common Flag Clear Register 0x68 32 write-only 0x00000000 0xffffffff ERSC ERS clear bit 4 4 write-only DCMFC DCMF clear bit 16 16 write-only DPERC DPER clear bit 17 17 write-only DFERC DFER clear bit 18 18 write-only ORERC ORER clear bit 24 24 write-only MFFC MFF clear bit 26 26 write-only PERC PER clear bit 27 27 write-only FERC FER clear bit 28 28 write-only TDREC TDRE clear bit 29 29 write-only RDRFC RDRF clear bit 31 31 write-only ICFCLR Simple IIC Flag Clear Register 0x6C 32 write-only 0x00000000 0xffffffff IICSTIFC IICSTIF clear bit 3 3 write-only FFCLR FIFO Flag Clear Register 0x70 32 write-only 0x00000000 0xffffffff DRC DR clear bit 0 0 write-only MFCLR Manchester Flag Clear Register 0x74 32 write-only 0x00000000 0xffffffff PFERC PFER clear bit 0 0 write-only SYERC SYER clear bit 1 1 write-only SBERC SBER clear bit 2 2 write-only MERC MER clear bit 4 4 write-only XFCLR Simple LIN Flag Clear Register 0x78 32 write-only 0x00000000 0xffffffff BFOC BFOF clear bit 8 8 write-only BCDC BCDF clear bit 9 9 write-only BFDC BFDF clear bit 10 10 write-only CF0MC CF0MF clear bit 11 11 write-only CF1MC CF1MF clear bit 12 12 write-only PIBDC PIBDF clear bit 13 13 write-only COFC COFF clear bit 14 14 write-only AEDC AEDF clear bit 15 15 write-only SCI_B1 Serial Communication Interface 1 0x40118100 SCI_B2 Serial Communication Interface 2 0x40118200 SCI_B3 Serial Communication Interface 3 0x40118300 SCI_B4 Serial Communication Interface 4 0x40118400 SCI_B9 Serial Communication Interface 9 0x40118900 SPI_B0 Serial Peripheral Interface 0 0x4011A000 0x00 52 registers 0x40 8 registers 0x50 4 registers 0x58 12 registers 0x68 8 registers SPDR SPI Data Register 0x00 32 read-write 0x00000000 0xffffffff SPDECR SPI Delay Control Register 0x04 32 read-write 0x00000000 0xffffffff SCKDL RSPCK Delay 0 2 read-write 000 1RSPCK #000 001 2RSPCK #001 010 3RSPCK #010 011 4RSPCK #011 100 5RSPCK #100 101 6RSPCK #101 110 7RSPCK #110 111 8RSPCK #111 SLNDL SSL Negation Delay 8 10 read-write 000 1RSPCK #000 001 2RSPCK #001 010 3RSPCK #010 011 4RSPCK #011 100 5RSPCK #100 101 6RSPCK #101 110 7RSPCK #110 111 8RSPCK #111 SPNDL SPI Next-Access Delay 16 18 read-write 000 1RSPCK + 5TCLK #000 001 2RSPCK + 5TCLK #001 010 3RSPCK + 5TCLK #010 011 4RSPCK + 5TCLK #011 100 5RSPCK + 5TCLK #100 101 6RSPCK + 5TCLK #101 110 7RSPCK + 5TCLK #110 111 8RSPCK + 5TCLK #111 SPCR SPI Control Register 0x08 32 read-write 0x00000000 0xffffffff SPE SPI Function Enable 0 0 read-write 0 SPI function is disabled. #0 1 SPI function is enabled. #1 SPPE Parity Enable 8 8 read-write 0 A parity bit is not added to transmit data. Received-data parity check is not performed. #0 1 A parity bit is added to transmit data. Received-data parity check is performed. #1 SPOE Parity Mode 9 9 read-write 0 Even parity is used for transmission and reception. #0 1 Odd parity is used for transmission and reception. #1 PTE Parity Self-Diagnosis Enable 11 11 read-write 0 Parity circuit self-diagnosis function is disabled. #0 1 Parity circuit self-diagnosis function is enabled. #1 SCKASE RSPCK Auto-Stop Function Enable 12 12 read-write 0 RSPCK auto-stop function is disabled. #0 1 RSPCK auto-stop function is enabled. #1 BFDS Between Burst Transfer Frames Delay Select 13 13 read-write 0 Delay (RSPCK delay, SSL negation delay and next-access delay) between frames is inserted in burst transfer #0 1 Delay between frames is not inserted in burst transfer. #1 MODFEN Mode Fault Error Detection Enable 14 14 read-write 0 Mode fault error detection is disabled. #0 1 Mode fault error detection is enabled. #1 SPEIE SPI Error Interrupt Enable 16 16 read-write 0 SPI error interrupt request is disabled. #0 1 SPI error interrupt request is enabled. #1 SPRIE SPI Receive Buffer Full Interrupt Enable 17 17 read-write 0 SPI receive buffer full interrupt request is disabled. #0 1 SPI receive buffer full interrupt request is enabled. #1 SPIIE SPI Idle Interrupt Enable 18 18 read-write 0 Idle interrupt request is disabled. #0 1 Idle interrupt request is enabled. #1 SPDRES SPI receive data ready error select 19 19 read-write 0 Receive data full interrupt #0 1 Error interrupt #1 SPTIE SPI Transmit Buffer Empty Interrupt Enable 20 20 read-write 0 SPI transmit buffer empty interrupt request is disabled. #0 1 SPI transmit buffer empty interrupt request is enabled. #1 CENDIE SPI Communication End Interrupt Enable 21 21 read-write 0 Communication end interrupt request is disabled. #0 1 Communication end interrupt request is enabled. #1 SPMS SPI Mode Select 24 24 read-write 0 SPI operation (4-wire) #0 1 Clock synchronous operation (3-wire) #1 SPFRF SPI Frame Format Select 25 25 read-write 0 Motorola-SPI #0 1 TI-SSP #1 TXMD Communication Mode Select 28 29 read-write 00 Transmit-Receive #00 01 Transmit only #01 Others Receive only true MSTR SPI Master/Slave Mode Select 30 30 read-write 0 Slave mode #0 1 Master mode #1 BPEN Synchronization Circuit Bypass Enable 31 31 read-write 0 Non-Bypass #0 1 Bypass #1 SPCR2 SPI Control Register 2 0x0C 32 read-write 0x00000000 0xffffffff RMFM Frame processing count setting in Master Receive only 0 4 read-write RMEDTG End Trigger in Master Receive only 6 6 write-only 1 Receive End (Writable only when Master Receive only) Reading value is always 0 #1 RMSTTG Start Trigger in Master Receive only 7 7 write-only 1 Receive Start (Writable only when Master Receive only) Reading value is always 0 #1 SPDRC SPI received data ready detect adjustment 8 15 read-write SPLP SPI Loopback 16 16 read-write 0 Normal mode #0 1 Loopback mode (inverted transmit data = receive data) #1 SPLP2 SPI Loopback 2 17 17 read-write 0 Normal mode #0 1 Loopback mode (transmit data = receive data) #1 MOIFV MOSI Idle Fixed Value 20 20 read-write 0 The fixed value of MOSI idle = 0. #0 1 The fixed value of MOSI idle = 1. #1 MOIFE MOSI Idle Fixed Value Enable 21 21 read-write 0 The MOSI output value is the last data of previous transfer. #0 1 The MOSI output value is the set MOIFV bit value. #1 SPCR3 SPI Control Register 3 0x10 32 read-write 0x0000ff00 0xffffffff SSL0P SSL0 Signal Polarity 0 0 read-write 0 The SSL0 signal is active low (0). #0 1 The SSL0 signal is active high (1). #1 SSL1P SSL1 Signal Polarity 1 1 read-write 0 The SSL1 signal is active low (0). #0 1 The SSL1 signal is active high (1). #1 SSL2P SSL2 Signal Polarity 2 2 read-write 0 The SSL2 signal is active low (0). #0 1 The SSL2 signal is active high (1). #1 SSL3P SSL3 Signal Polarity 3 3 read-write 0 The SSL3 signal is active low (0). #0 1 The SSL3 signal is active high (1). #1 SPBR SPI Bit Rate 8 15 read-write SPSLN SPI Sequence Length 24 26 read-write 000 Sequence Length is 1 (Referenced SPCMDn, n = 0→0→…) #000 001 Sequence Length is 2 (Referenced SPCMDn, n = 0→1→0→…) #001 010 Sequence Length is 3 (Referenced SPCMDn, n = 0→1→2→0→…) #010 011 Sequence Length is 4 (Referenced SPCMDn, n = 0→1→2→3→0→…) #011 100 Sequence Length is 5 (Referenced SPCMDn, n = 0→1→2→3→4→0→…) #100 101 Sequence Length is 6 (Referenced SPCMDn, n = 0→1→2→3→4→5→0→…) #101 110 Sequence Length is 7 (Referenced SPCMDn, n = 0→1→2→3→4→5→6→0→…) #110 111 Sequence Length is 8 (Referenced SPCMDn, n = 0→1→2→3→4→5→6→7→0→…) #111 8 0x04 0-7 SPCMD%s SPI Command Register 0x14 32 read-write 0x00070000 0xffffffff CPHA RSPCK Phase 0 0 read-write 0 Data is sampled at an odd edge and changes at an even edge. #0 1 Data changes at an odd edge and is sampled at an even edge. #1 CPOL RSPCK Polarity 1 1 read-write 0 RSPCK in idle state is 0. #0 1 RSPCK in idle state is 1. #1 BRDV Bit Rate Division 2 3 read-write 00 The base bit rate is selected. #00 01 Two-divided base bit rate is selected. #01 10 Four-divided base bit rate is selected. #10 11 Eight-divided base bit rate is selected. #11 SSLKP SSL Signal Level Hold 7 7 read-write 0 All SSL signals are negated at the end of transfer. #0 1 SSL signal level is held after the transfer ends until the next access starts. #1 LSBF SPI LSB First 12 12 read-write 0 MSB first #0 1 LSB first #1 SPNDEN SPI Next-Access Delay Enable 13 13 read-write 0 Next-access delay is 1RSPCK + 5TCLK #0 1 Next-access delay is the set value of the SPI next-access delay register (SPDECR.SPNDL). #1 SLNDEN SSL Negation Delay Setting Enable 14 14 read-write 0 [Master] SSL negation delay is 1RSPCK. [Slave in the TI-SSP] SSL negation delay is 1TCLK #0 1 SSL negation delay is the set value of the slave select negation delay register (SPDECR.SLNDL). #1 SCKDEN RSPCK Delay Setting Enable 15 15 read-write 0 RSPCK delay is 1 RSPCK. #0 1 RSPCK delay is the set value of the RSPCK delay register (SPDECR.SCKDL). #1 SPB SPI Data Length 16 20 read-write SSLA SSL Signal Assertion 24 26 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 Others Setting prohibited true SPDCR SPI Data Control Register 0x40 32 read-write 0x00000000 0xffffffff BYSW Byte Swap Operating Mode Select 0 0 read-write 0 Byte Swap OFF #0 1 Byte Swap ON #1 SPRDTD SPI Receive Data or Transmit Data Select 3 3 read-write 0 The SPDR reads the receive buffer. #0 1 The SPDR reads the transmit buffer #1 SINV Serial data invert bit 4 4 read-write 0 Not invert serial data #0 1 Invert serial data. #1 SPFC Frame Count 8 9 read-write 00 1 frame #00 01 2 frame #01 10 3 frame #10 11 4 frame #11 SPDCR2 SPI Data Control Register 2 0x44 32 read-write 0x00000000 0xffffffff RTRG Receive FIFO threshold setting 0 1 read-write 00 threshold 0 #00 01 threshold 1 #01 10 threshold 2 #10 11 threshold 3 #11 TTRG Transmission FIFO threshold setting 8 9 read-write 00 threshold 0 #00 01 threshold 1 #01 10 threshold 2 #10 11 threshold 3 #11 SPSR SPI Status Register 0x50 32 read-only 0x20000000 0xffffffff SPCP SPI Command Pointer 8 10 read-only 000 SPCMD0 #000 001 SPCMD1 #001 010 SPCMD2 #010 011 SPCMD3 #011 100 SPCMD4 #100 101 SPCMD5 #101 110 SPCMD6 #110 111 SPCMD7 #111 SPECM SPI Error Command 12 14 read-only 000 SPCMD0 #000 001 SPCMD1 #001 010 SPCMD2 #010 011 SPCMD3 #011 100 SPCMD4 #100 101 SPCMD5 #101 110 SPCMD6 #110 111 SPCMD7 #111 SPDRF SPI Receive Data Ready Flag 23 23 read-only 0 Receive data ready not detected #0 1 Receive data ready detected #1 OVRF Overrun Error Flag 24 24 read-only 0 No overrun error is present. #0 1 An overrun error is present. #1 IDLNF SPI Idle Flag 25 25 read-only 0 The SPI is in the idle state. #0 1 The SPI is in the transfer state. #1 MODF Mode Fault Error Flag 26 26 read-only 0 Neither mode fault error nor underrun error is present. #0 1 A mode fault error or underrun error is present. #1 PERF Parity Error Flag 27 27 read-only 0 No parity error is present. #0 1 A parity error is present. #1 UDRF Underrun Error Flag 28 28 read-only 0 When MODF=0, neither mode fault error nor underrun error is present. When MODF=1, a mode fault error is present. #0 1 When MODF=0, neither mode fault error nor underrun error is present. When MODF=1, an underrun error is present. #1 SPTEF SPI Transmit Buffer Empty Flag 29 29 read-only 0 The number of empty stages in the transmit FIFO ≤ the value set in SPDCR2.TTRG #0 1 The number of empty stages in the transmit FIFO > the value set in SPDCR2.TTRG #1 CENDF Communication End Flag 30 30 read-only 0 The SPI is not communicating or communicating. #0 1 The SPI communication completed. #1 SPRF SPI Receive Buffer Full Flag 31 31 read-only 0 The number of data stored in the receive FIFO ≤ number of frames set by the SPDCR2.RTRG bit. #0 1 The number of data stored in the receive FIFO > number of frames set by the SPDCR2.RTRG bit. #1 SPTFSR SPI Transfer FIFO Status Register 0x58 32 read-only 0x00000004 0xffffffff TFDN Transmit FIFO data empty stage number 0 2 read-only SPRFSR SPI Receive FIFO Status Register 0x5C 32 read-only 0x00000004 0xffffffff RFDN Receive FIFO data store stage number 0 2 read-only SPPSR SPI Polling Register 0x60 32 read-only 0x00000000 0xffffffff SPEPS SPI Polling Status 0 0 read-only 0 SPCR.SPE is 0 #0 1 SPCR.SPE is 1 #1 SPSRC SPI Status Clear Register 0x68 32 read-write 0x00000000 0xffffffff SPDRFC SPI Receive Data Ready Flag Clear 23 23 write-only OVRFC Overrun Error Flag Clear 24 24 write-only MODFC Mode Fault Error Flag Clear 26 26 write-only PERFC Parity Error Flag Clear 27 27 write-only UDRFC Underrun Error Flag Clear 28 28 write-only SPTEFC SPI Transmit Buffer Empty Flag Clear 29 29 write-only CENDFC Communication End Flag Clear 30 30 write-only SPRFC SPI Receive Buffer Full Flag Clear 31 31 write-only SPFCR SPI FIFO Clear Register 0x6C 32 read-write 0x00000000 0xffffffff SPFRST SPI FIFO clear 0 0 write-only SPI_B1 Serial Peripheral Interface 1 0x4011A100 IIC_B0 Inter-Integrated Circuit 0 0x4011F000 0x14 4 registers 0x20 8 registers 0x60 8 registers 0x70 16 registers 0x88 12 registers 0xA0 8 registers 0x140 4 registers 0x158 4 registers 0x1D0 32 registers 0x210 8 registers 0x2B0 12 registers 0x330 12 registers 0x380 4 registers 0x3CC 4 registers BCTL Bus Control Register 0x014 32 read-write 0x00000000 0xffffffff BUSE Bus Enable 31 31 read-write 0 IIC bus operation is disabled. #0 1 IIC bus operation is enabled. #1 RSTCTL Reset Control Register 0x020 32 read-write 0x00000000 0xffffffff RI2CRST IIC Software Reset 0 0 read-write 0 Reset of all registers and internal state. #0 1 Releases of all registers and internal state. #1 INTLRST Internal Software Reset 16 16 read-write 0 Releases of some registers and internal state. #0 1 Resets of some registers and internal state. #1 PRSST Present State Register 0x024 32 read-write 0x00000000 0xffffffff CRMS Current Master 2 2 read-write 0 The Master is not the Current Master, and must request and acquire bus ownership before initiating any transfer. #0 1 The Master is the Current Master, and as a result can initiate transfers. #1 TRMD Transmit/Receive Mode 4 4 read-only 0 Receive mode #0 1 Transmit mode #1 PRSSTWP Present State Write Protect 7 7 write-only 0 CRMS bit is protected. #0 1 CRMS bit can be written when writing simultaneously with the value of the target bit. #1 BFCTL Bus Function Control Register 0x060 32 read-write 0x00000101 0xffffffff MALE Master Arbitration-Lost Detection Enable 0 0 read-write 0 Master arbitration-lost detection disables. Disables the arbitration-lost detection function and does not clear the CRMS and TRMD bits in PRSST automatically when arbitration is lost. #0 1 Master arbitration-lost detection enables. Enables the arbitration-lost detection function and clears the CRMS and TRMD bits in PRSST automatically when arbitration is lost. #1 NALE NACK Transmission Arbitration-Lost Detection Enable 1 1 read-write 0 NACK transmission arbitration-lost detection disables. #0 1 NACK transmission arbitration-lost detection enables. #1 SALE Slave Arbitration-Lost Detection Enable 2 2 read-write 0 Slave arbitration-lost detection disables. #0 1 Slave arbitration-lost detection enables. #1 SCSYNE SCL Synchronous Circuit Enable 8 8 read-write 0 No SCL synchronous circuit uses. #0 1 An SCL synchronous circuit uses. #1 SMBS SMBus/I2C Bus Selection 12 12 read-write 0 The I2C bus select. #0 1 The SMBus select. #1 FMPE Fast-mode Plus Enable 14 14 read-write 0 No Fm+ slope control circuit uses for the SCLn pin and SDAn pin. (n = 0, 1) #0 1 An Fm+ slope control circuit uses for the SCLn pin and SDAn pin. (n = 0, 1) #1 HSME High Speed Mode Enable 15 15 read-write 0 Disable High Speed Mode. #0 1 Enable High Speed Mode. #1 SVCTL Slave Control Register 0x064 32 read-write 0x00000000 0xffffffff GCAE General Call Address Enable 0 0 read-write 0 General call address detection disables. #0 1 General call address detection enables. #1 HSMCE Hs-mode Master Code Enable 5 5 read-write 0 Hs-mode Master Code Detection disables. #0 1 Hs-mode Master Code Detection enables. #1 DVIDE Device-ID Address Enable 6 6 read-write 0 Device-ID address detection disables. #0 1 Device-ID address detection enables. #1 HOAE Host Address Enable 15 15 read-write 0 Host address detection disables. #0 1 Host address detection enables. #1 SVAE0 Slave Address Enable 0 16 16 read-write 0 Slave 0 disables #0 1 Slave 0 enables #1 SVAE1 Slave Address Enable 1 17 17 read-write 0 Slave 1 disables #0 1 Slave 1 enables #1 SVAE2 Slave Address Enable 2 18 18 read-write 0 Slave 2 disables #0 1 Slave 2 enables #1 REFCKCTL Reference Clock Control Register 0x070 32 read-write 0x00000000 0xffffffff IREFCKS Internal Reference Clock Selection 0 2 read-write 000 IICCLK/1 clock #000 001 IICCLK/2 clock #001 010 IICCLK/4 clock #010 011 IICCLK/8 clock #011 100 IICCLK/16 clock #100 101 IICCLK/32 clock #101 110 IICCLK/64 clock #110 111 IICCLK/128 clock #111 STDBR Standard Bit Rate Register 0x074 32 read-write 0x0000ffff 0xffffffff SBRLO Count value of the Low-level period of SCL clock 0 7 read-write SBRHO Count value of the High-level period of SCL clock 8 15 read-write DSBRPO Double the Standard Bit Rate Period for Open-Drain 31 31 read-write 0 The time period set for SBRHO[7:0] and SBRLO[7:0] is not doubled. #0 1 The time period set for SBRHO[7:0] and SBRLO[7:0] is doubled. #1 EXTBR Extended Bit Rate Register 0x078 32 read-write 0x0000ffff 0xffffffff EBRLO Extended Bit Rate Low-Level Period Open-Drain 0 7 read-write EBRHO Extended Bit Rate High-Level Period Open-Drain 8 15 read-write BFRECDT Bus Free Condition Detection Time Register 0x07C 32 read-write 0x00000000 0xffffffff FRECYC Bus Free Condition Detection Cycle 0 8 read-write OUTCTL Output Control Register 0x088 32 read-write 0x00000003 0xffffffff SDOC SDA Output Control 0 0 read-write 0 IIC drives the SDAn pin low. #0 1 IIC releases the SDAn pin. #1 SCOC SCL Output Control 1 1 read-write 0 IIC drives the SCLn pin low. #0 1 IIC releases the SCLn pin. #1 SOCWP SCL/SDA Output Control Write Protect 2 2 write-only 0 Bits SCOC and SDOC are protected. #0 1 Bits SCOC and SDOC can be written (When writing simultaneously with the value of the target bit). This bit is read as 0. #1 EXCYC Extra SCL Clock Cycle Output 4 4 read-write 0 Does not output an extra SCL clock cycle (default). #0 1 Outputs an extra SCL clock cycle. #1 SDOD SDA Output Delay 8 10 read-write 000 No output delay #000 001 1 IICφ cycle (When OUTCTL.SDODCS = 0 (IICφ)) 1 or 2 IICφ cycles (When OUTCTL.SDODCS = 1 (IICφ/2)) #001 010 2 IICφ cycles (When OUTCTL.SDODCS = 0 (IICφ)) 3 or 4 IICφ cycles (When OUTCTL.SDODCS = 1 (IICφ/2)) #010 011 3 IICφ cycles (When OUTCTL.SDODCS = 0 (IICφ)) 5 or 6 IICφ cycles (When OUTCTL.SDODCS = 1 (IICφ/2)) #011 100 4 IICφ cycles (When OUTCTL.SDODCS = 0 (IICφ)) 7 or 8 IICφ cycles (When OUTCTL.SDODCS = 1 (IICφ/2)) #100 101 5 IICφ cycles (When OUTCTL.SDODCS = 0 (IICφ)) 9 or 10 IICφ cycles (When OUTCTL.SDODCS = 1 (IICφ/2)) #101 110 6 IICφ cycles (When OUTCTL.SDODCS = 0 (IICφ)) 11 or 12 IICφ cycles (When OUTCTL.SDODCS = 1 (IICφ/2)) #110 111 7 IICφ cycles (When OUTCTL.SDODCS = 0 (IICφ)) 13 or 14 IICφ cycles (When OUTCTL.SDODCS = 1 (IICφ/2)) #111 SDODCS SDA Output Delay Clock Source Selection 15 15 read-write 0 The internal reference clock (IICφ) is selected as the clock source of the SDA output delay counter. #0 1 The internal reference clock divided by 2 (IICφ/2) is selected as the clock source of the SDA output delay counter. #1 INCTL Input Control Register 0x08C 32 read-write 0x000000d0 0xffffffff DNFS Digital Noise Filter Stage Selection 0 3 read-write DNFE Digital Noise Filter Circuit Enable 4 4 read-write 0 No digital noise filter circuit is used. #0 1 A digital noise filter circuit is used. #1 TMOCTL Timeout Control Register 0x090 32 read-write 0x00000030 0xffffffff TODTS Timeout Detection Time Selection 0 1 read-write 00 16bit-timeout #00 01 14bit-timeout #01 10 8bit-timeout #10 11 6bit-timeout #11 TOLCTL Timeout L Count Control 4 4 read-write 0 Count is disabled while the SCLn line is at a low level. #0 1 Count is enabled while the SCLn line is at a low level. #1 TOHCTL Timeout H Count Control 5 5 read-write 0 Count is disabled while the SCLn line is at a high level. #0 1 Count is enabled while the SCLn line is at a high level. #1 TOMDS Timeout Operation Mode Selection 6 7 read-write 00 Timeout is detected during the following conditions: The bus is busy (BCST.BFREF = 0) in master mode.IIC’s own slave address is detected and the bus is busy in slave mode.The bus is free (BCST.BFREF = 1) while generation of a START condition is requested (CNDCTL.STCND = 1). #00 01 Timeout is detected while the bus is busy. #01 10 Timeout is detected while the bus is free. #10 11 Setting prohibited #11 ACKCTL Acknowledge Control Register 0x0A0 32 read-write 0x00000000 0xffffffff ACKR Acknowledge Reception 0 0 read-only 0 A 0 is received as the acknowledge bit (ACK reception). #0 1 A 1 is received as the acknowledge bit (NACK reception). #1 ACKT Acknowledge Transmission 1 1 read-write 0 A 0 is sent as the acknowledge bit (ACK transmission). #0 1 A 1 is sent as the acknowledge bit (NACK transmission). #1 ACKTWP ACKT Write Protect 2 2 write-only 0 The ACKT bit are protected. #0 1 The ACKT bit can be written (when writing simultaneously with the value of the target bit). This bit is read as 0. #1 SCSTRCTL SCL Stretch Control Register 0x0A4 32 read-write 0x00000000 0xffffffff ACKTWE Acknowledge Transmission Wait Enable 0 0 read-write 0 NTST.RDBFF0 is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.) #0 1 NTST.RDBFF0 is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.) Low-hold is released by writing a value to the ACKCTL.ACKT bit. #1 RWE Receive Wait Enable 1 1 read-write 0 No WAIT (The period between ninth clock cycle and first clock cycle is not held low.) #0 1 WAIT (The period between ninth clock cycle and first clock cycle is held low.) Low-hold is released by reading NTDTBP0. #1 CNDCTL Condition Control Register 0x140 32 read-write 0x00000000 0xffffffff STCND START (S) Condition Issuance 0 0 read-write 0 Does not request to issue a START condition. #0 1 Requests to issue a START condition. #1 SRCND Repeated START (Sr) Condition Issuance 1 1 read-write 0 Does not request to issue a Repeated START condition. #0 1 Requests to issue a Repeated START condition. #1 SPCND STOP (P) Condition Issuance 2 2 read-write 0 Does not request to issue a STOP condition. #0 1 Requests to issue a STOP condition. #1 NTDTBP0 Normal Transfer Data Buffer Port Register 0 0x158 32 read-write 0x00000000 0xffffffff NTDTBP0_BY Normal Transfer Data Buffer Port Register 0 NTDTBP0 0x158 8 read-write 0x00 0xff BST Bus Status Register 0x1D0 32 read-write 0x00000000 0xffffffff STCNDDF START Condition Detection Flag 0 0 read-write 0 START condition is not detected. #0 1 START condition is detected. #1 SPCNDDF STOP Condition Detection Flag 1 1 read-write 0 STOP condition is not detected. #0 1 STOP condition is detected. #1 NACKDF NACK Detection Flag 4 4 read-write 0 NACK is not detected. #0 1 NACK is detected. #1 TENDF Transmit End Flag 8 8 read-write 0 Data is being transmitted. #0 1 Data has been transmitted. #1 ALF Arbitration Lost Flag 16 16 read-write 0 Arbitration is not lost #0 1 Arbitration is lost. #1 TODF Timeout Detection Flag 20 20 read-write 0 Timeout is not detected. #0 1 Timeout is detected. #1 WUCNDDF Wake-Up Condition Detection Flag 24 24 read-write 0 Wake-Up is not detected. #0 1 Wake-Up is detected. #1 BSTE Bus Status Enable Register 0x1D4 32 read-write 0x00000000 0xffffffff STCNDDE START Condition Detection Enable 0 0 read-write 0 Disables START condition Detection Interrupt Status logging. #0 1 Enables START condition Detection Interrupt Status logging. #1 SPCNDDE STOP Condition Detection Enable 1 1 read-write 0 Disables STOP condition Detection Interrupt Status logging. #0 1 Enables STOP condition Detection Interrupt Status logging. #1 NACKDE NACK Detection Enable 4 4 read-write 0 Disables NACK Detection Interrupt Status logging. #0 1 Enables NACK Detection Interrupt Status logging. #1 TENDE Transmit End Enable 8 8 read-write 0 Disables Transmit End Interrupt Status logging. #0 1 Enables Transmit End Interrupt Status logging. #1 ALE Arbitration Lost Enable 16 16 read-write 0 Disables Arbitration Lost Interrupt Status logging. #0 1 Enables Arbitration Lost Interrupt Status logging. #1 TODE Timeout Detection Enable 20 20 read-write 0 Disables Timeout Detection Interrupt Status logging. #0 1 Enables Timeout Detection Interrupt Status logging. #1 WUCNDDE Wake-up Condition Detection Enable 24 24 read-write 0 Disables Wake-up Condition Detection Status logging. #0 1 Enables Wake-up Condition Detection Status logging. #1 BIE Bus Interrupt Enable Register 0x1D8 32 read-write 0x00000000 0xffffffff STCNDDIE START Condition Detection Interrupt Enable 0 0 read-write 0 Disables START condition Detection Interrupt Signal. #0 1 Enables START condition Detection Interrupt Signal. #1 SPCNDDIE STOP Condition Detection Interrupt Enable 1 1 read-write 0 Disables STOP condition Detection Interrupt Signal. #0 1 Enables STOP condition Detection Interrupt Signal. #1 NACKDIE NACK Detection Interrupt Enable 4 4 read-write 0 Disables NACK Detection Interrupt Signal. #0 1 Enables NACK Detection Interrupt Signal. #1 TENDIE Transmit End Interrupt Enable 8 8 read-write 0 Disables Transmit End Interrupt Signal. #0 1 Enables Transmit End Interrupt Signal. #1 ALIE Arbitration Lost Interrupt Enable 16 16 read-write 0 Disables Arbitration Lost Interrupt Signal. #0 1 Enables Arbitration Lost Interrupt Signal. #1 TODIE Timeout Detection Interrupt Enable 20 20 read-write 0 Disables Timeout Detection Interrupt Signal. #0 1 Enables Timeout Detection Interrupt Signal. #1 WUCNDDIE Wake-Up Condition Detection Interrupt Enable 24 24 read-write 0 Disables Wake-Up Condition Detection Interrupt Signal. #0 1 Enables Wake-Up Condition Detection Interrupt Signal. #1 BSTFC Bus Status Force Register 0x1DC 32 read-write 0x00000000 0xffffffff STCNDDFC START condition Detection Force 0 0 write-only 0 Not Force START condition Detection Interrupt for software testing. #0 1 Force START condition Detection Interrupt for software testing. #1 SPCNDDFC STOP condition Detection Force 1 1 write-only 0 Not Force STOP condition Detection Interrupt for software testing. #0 1 Force STOP condition Detection Interrupt for software testing. #1 NACKDFC NACK Detection Force 4 4 write-only 0 Not Force NACK Detection Interrupt for software testing. #0 1 Force NACK Detection Interrupt for software testing. #1 TENDFC Transmit End Force 8 8 write-only 0 Not Force Transmit End Interrupt for software testing. #0 1 Force Transmit End Interrupt for software testing. #1 ALFC Arbitration Lost Force 16 16 write-only 0 Not Force Arbitration Lost Interrupt for software testing. #0 1 Force Arbitration Lost Interrupt for software testing. #1 TODFC Timeout Detection Force 20 20 write-only 0 Not Force Timeout Detection Interrupt for software testing. #0 1 Force Timeout Detection Interrupt for software testing. #1 WUCNDDFC Wake-Up Condition Detection Force 24 24 write-only 0 Not Force Wake-Up Condition Detection Interrupt for software testing. #0 1 Force Wake-Up Condition Detection Interrupt for software testing. #1 NTST Normal Transfer Status Register 0x1E0 32 read-write 0x00000000 0xffffffff TDBEF0 Normal Transmit Data Buffer Empty Flag 0 0 0 read-write 0 Normal Transmit Data Buffer 0 contains transmit data. #0 1 Normal Transmit Data Buffer 0 contains no transmit data. #1 RDBFF0 Normal Receive Data Buffer Full Flag 0 1 1 read-write 0 Normal Receive Data Buffer0 contains no receive data. #0 1 Normal Receive Data Buffer0 contains receive data. #1 NTSTE Normal Transfer Status Enable Register 0x1E4 32 read-write 0x00000000 0xffffffff TDBEE0 Normal Transmit Data Buffer Empty Enable 0 0 0 read-write 0 Disables Tx0 Data Buffer Empty Interrupt Status logging. #0 1 Enables Tx0 Data Buffer Empty Interrupt Status logging. #1 RDBFE0 Normal Receive Data Buffer Full Enable 0 1 1 read-write 0 Disables Rx0 Data Buffer Full Interrupt Status logging. #0 1 Enables Rx0 Data Buffer Full Interrupt Status logging. #1 NTIE Normal Transfer Interrupt Enable Register 0x1E8 32 read-write 0x00000000 0xffffffff TDBEIE0 Normal Transmit Data Buffer Empty Interrupt Enable 0 0 0 read-write 0 Disables Tx0 Data Buffer Empty Interrupt Signal. #0 1 Enables Tx0 Data Buffer Empty Interrupt Signal. #1 RDBFIE0 Normal Receive Data Buffer Full Interrupt Enable 0 1 1 read-write 0 Disables Rx0 Data Buffer Full Interrupt Signal. #0 1 Enables Rx0 Data Buffer Full Interrupt Signal. #1 NTSTFC Normal Transfer Status Force Register 0x1EC 32 write-only 0x00000000 0xffffffff TDBEFC0 Normal Transmit Data Buffer Empty Force 0 0 0 write-only 0 Not Force Tx0 Data Buffer Empty Interrupt for software testing. #0 1 Force Tx0 Data Buffer Empty Interrupt for software testing. #1 RDBFFC0 Normal Receive Data Buffer Full Force 0 1 1 write-only 0 Not Force Rx0 Data Buffer Full Interrupt for software testing. #0 1 Force Rx0 Data Buffer Full Interrupt for software testing. #1 BCST Bus Condition Status Register 0x210 32 read-only 0x00000000 0xffffffff BFREF Bus Free Detection Flag 0 0 read-only 0 Have not Detected Bus Free #0 1 Have Detected Bus Free #1 SVST Slave Status Register 0x214 32 read-write 0x00000000 0xffffffff GCAF General Call Address Detection Flag 0 0 read-write 0 General call address does not detect. #0 1 General call address detects. #1 HSMCF Hs-mode Master Code Detection Flag 5 5 read-write 0 Hs-mode Master Code does not detect. #0 1 Hs-mode Master Code detects. #1 DVIDF Device-ID Address Detection Flag 6 6 read-write 0 Device-ID command does not detect. #0 1 Device-ID command detects. This bit set to 1 when the first frame received immediately after a START condition is detected matches a value of (device ID (1111 100) + 0[W]). #1 HOAF Host Address Detection Flag 15 15 read-write 0 Host address does not detect. #0 1 Host address detects. This bit set to 1 when the received slave address matches the host address (0001 000). #1 SVAF0 Slave Address Detection Flag 0 16 16 read-write 0 Slave 0 does not detect #0 1 Slave 0 detect #1 SVAF1 Slave Address Detection Flag 1 17 17 read-write 0 Slave 1 does not detect #0 1 Slave 1 detect #1 SVAF2 Slave Address Detection Flag 2 18 18 read-write 0 Slave 2 does not detect #0 1 Slave 2 detect #1 3 0x04 0-2 SDATBAS%s Slave Device Address Table Basic Register %s 0x2B0 32 read-write 0x00000000 0xffffffff SDSTAD Slave Device Static Address 0 9 read-write SDADLS Slave Device Address Length Selection 10 10 read-write 0 Slave Device address length 7 bits selected. #0 1 Slave Device address length 10 bits selected. (I2C device only) #1 3 0x04 0-2 SVDVAD%s Slave Device Address Register %s 0x330 32 read-only 0x00000000 0xffffffff SVAD Slave Address 16 25 read-only SADLG Slave Address Length 27 27 read-only 0 The 7-bit address format is selected. #0 1 The 10-bit address format is selected. #1 SSTADV Slave Static Address Valid 30 30 read-only 0 Slave address is disabled. #0 1 Slave address is enabled. #1 BITCNT Bit Count Register 0x380 32 read-only 0x00000000 0xffffffff BCNT Bit Counter 0 4 read-only PRSTDBG Present State Debug Register 0x3CC 32 read-only 0x00000000 0xffffffff SCILV SCL Line Signal Level 0 0 read-only SDILV SDA Line Signal Level 1 1 read-only SCOLV SCL Output Level 2 2 read-only 0 IIC has driven the SCL pin low. #0 1 IIC has released the SCL pin. #1 SDOLV SDA Output Level 3 3 read-only 0 IIC has driven the SDA pin low. #0 1 IIC has released the SDA pin. #1 IIC0WU_B Inter-Integrated Circuit 0 Wake-up Unit 0x4011F098 0x00 4 registers 0x180 4 registers WUCTL Wake Up Unit Control Register 0x000 32 read-write 0x00000041 0xffffffff WUACKS Wake-Up Acknowledge Selection 0 0 read-write WUANFS Wake-Up Analog Noise Filter Selection 4 4 read-write 0 Do not add the Wake Up analog filter. #0 1 Add the Wake Up analog filter. #1 WUFSYNE Wake-Up function PCLKA Synchronous Enable 6 6 read-write 0 IIC asynchronous circuit enable #0 1 IIC synchronous circuit enable #1 WUFE Wake-Up function Enable 7 7 read-write 0 Wake-up function disables #0 1 Wake-up function enables #1 WUST Wake Up Unit Operating Status Register 0x180 32 read-only 0x00000000 0xffffffff WUASYNF Wake-up function asynchronous operation status flag 0 0 read-only 0 IIC synchronous circuit enable condition. #0 1 IIC asynchronous circuit enable condition. #1 IIC_B1 Inter-Integrated Circuit 1 0x4011F400 ECCMB CANFD ECC Module 0x4012F200 0x00 6 registers 0x0C 8 registers EC710CTL ECC Control Register 0x00 32 read-write 0x00000010 0xffffffff ECEMF ECC Error Message Flag 0 0 read-only 0 There is no bit error in present RAM output data #0 1 There is bit error in present RAM output data #1 ECER1F ECC Error Detection and Correction Flag 1 1 read-only 0 After clearing this bit, 1-bit error correction has not occurred #0 1 1-bit error has occurred #1 ECER2F 2-bit ECC Error Detection Flag 2 2 read-only 0 After clearing this bit, 2-bit error has not occurred #0 1 2-bit error has occurred #1 EC1EDIC ECC 1-bit Error Detection Interrupt Control 3 3 read-write 0 Disable 1-bit error detection interrupt request #0 1 Enable 1-bit error detection interrupt request #1 EC2EDIC ECC 2-bit Error Detection Interrupt Control 4 4 read-write 0 Disable 2-bit error detection interrupt request #0 1 Enable 2-bit error detection interrupt request #1 EC1ECP ECC 1-bit Error Correction Permission 5 5 read-write 0 At 1-bit error detection, the error correction is executed #0 1 At 1-bit error detection, the error correction is not executed #1 ECERVF ECC Error Judgment Enable Flag 6 6 read-write 0 Error judgment disable #0 1 Error judgment enable #1 ECER1C Accumulating ECC Error Detection and Correction Flag Clear 9 9 read-write 0 No effect #0 1 Clear accumulating ECC error detection and correction flag #1 ECER2C 2-bit ECC Error Detection Flag Clear 10 10 read-write 0 No effect #0 1 Clear 2-bit ECC error detection flag #1 ECOVFF ECC Overflow Detection Flag 11 11 read-only 0 No effect #0 1 ECC overflow detection flag #1 EMCA Access Control to ECC Mode Select bit 14 15 read-write ECSEDF0 ECC Single bit Error Address Detection Flag 16 16 read-only 0 There is no bit error in EC710EAD0 after reset or clearing ECER1F bit #0 1 Address captured in EC710EAD0 shows that 1-bit error occurred and captured #1 ECDEDF0 ECC Dual Bit Error Address Detection Flag 17 17 read-only 0 There is no bit error in EC710EAD0 after reset or clearing ECER2F bit #0 1 Address captured in EC710EAD0 shows that 2-bit error occurred and captured #1 EC710TMC ECC Test Mode Control Register 0x04 16 read-write 0x0000 0xffff ECDCS ECC Decode Input Select 1 1 read-write 0 Input lower 32 bits of RAM output data to data area of decode circuit #0 1 Input ECEDB31-0 in EC710TED register to data area of decode circuit #1 ECTMCE ECC Test Mode Control Enable 7 7 read-write 0 The access to test mode register and bit is disabled #0 1 The access to test mode register and bit is enabled #1 ETMA ECC Test Mode Bit Access Control 14 15 read-write EC710TED ECC Test Substitute Data Register 0x0C 32 read-write 0x00000000 0xffffffff ECEDB ECC Test Substitute Data 0 31 read-write EC710EAD0 ECC Error Address Register 0x10 32 read-only 0x00000000 0xffffffff ECEAD ECC Error Address 0 10 read-only GPT320 General PWM 32-bit Timer 0 0x40169000 0x00 192 registers 0xD0 8 registers 0xE0 8 registers 0xEC 4 registers GTWP General PWM Timer Write-Protection Register 0x00 32 read-write 0x00000000 0xffffffff WP Register Write Disable 0 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 STRWP GTSTR.CSTRT Bit Write Disable 1 1 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 STPWP GTSTP.CSTOP Bit Write Disable 2 2 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CLRWP GTCLR.CCLR Bit Write Disable 3 3 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CMNWP Common Register Write Disabled 4 4 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 PRKEY GTWP Key Code 8 15 write-only GTSTR General PWM Timer Software Start Register 0x04 32 read-write 0x00000000 0xffffffff CSTRT0 Channel n GTCNT Count Start (n is the same as the bit position value) 0 0 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT1 Channel n GTCNT Count Start (n is the same as the bit position value) 1 1 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT2 Channel n GTCNT Count Start (n is the same as the bit position value) 2 2 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT3 Channel n GTCNT Count Start (n is the same as the bit position value) 3 3 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT4 Channel n GTCNT Count Start (n is the same as the bit position value) 4 4 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT5 Channel n GTCNT Count Start (n is the same as the bit position value) 5 5 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT6 Channel n GTCNT Count Start (n is the same as the bit position value) 6 6 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT7 Channel n GTCNT Count Start (n is the same as the bit position value) 7 7 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT8 Channel n GTCNT Count Start (n is the same as the bit position value) 8 8 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT9 Channel n GTCNT Count Start (n is the same as the bit position value) 9 9 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT10 Channel n GTCNT Count Start (n is the same as the bit position value) 10 10 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT11 Channel n GTCNT Count Start (n is the same as the bit position value) 11 11 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT12 Channel n GTCNT Count Start (n is the same as the bit position value) 12 12 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT13 Channel n GTCNT Count Start (n is the same as the bit position value) 13 13 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT14 Channel n GTCNT Count Start (n is the same as the bit position value) 14 14 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT15 Channel n GTCNT Count Start (n is the same as the bit position value) 15 15 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT16 Channel n GTCNT Count Start (n is the same as the bit position value) 16 16 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT17 Channel n GTCNT Count Start (n is the same as the bit position value) 17 17 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT18 Channel n GTCNT Count Start (n is the same as the bit position value) 18 18 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT19 Channel n GTCNT Count Start (n is the same as the bit position value) 19 19 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT20 Channel n GTCNT Count Start (n is the same as the bit position value) 20 20 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT21 Channel n GTCNT Count Start (n is the same as the bit position value) 21 21 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT22 Channel n GTCNT Count Start (n is the same as the bit position value) 22 22 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT23 Channel n GTCNT Count Start (n is the same as the bit position value) 23 23 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT24 Channel n GTCNT Count Start (n is the same as the bit position value) 24 24 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT25 Channel n GTCNT Count Start (n is the same as the bit position value) 25 25 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT26 Channel n GTCNT Count Start (n is the same as the bit position value) 26 26 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT27 Channel n GTCNT Count Start (n is the same as the bit position value) 27 27 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT28 Channel n GTCNT Count Start (n is the same as the bit position value) 28 28 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT29 Channel n GTCNT Count Start (n is the same as the bit position value) 29 29 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT30 Channel n GTCNT Count Start (n is the same as the bit position value) 30 30 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT31 Channel n GTCNT Count Start (n is the same as the bit position value) 31 31 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 GTSTP General PWM Timer Software Stop Register 0x08 32 read-write 0xffffffff 0xffffffff CSTOP0 Channel n GTCNT Count Stop (n is the same as the bit position value) 0 0 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP1 Channel n GTCNT Count Stop (n is the same as the bit position value) 1 1 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP2 Channel n GTCNT Count Stop (n is the same as the bit position value) 2 2 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP3 Channel n GTCNT Count Stop (n is the same as the bit position value) 3 3 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP4 Channel n GTCNT Count Stop (n is the same as the bit position value) 4 4 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP5 Channel n GTCNT Count Stop (n is the same as the bit position value) 5 5 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP6 Channel n GTCNT Count Stop (n is the same as the bit position value) 6 6 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP7 Channel n GTCNT Count Stop (n is the same as the bit position value) 7 7 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP8 Channel n GTCNT Count Stop (n is the same as the bit position value) 8 8 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP9 Channel n GTCNT Count Stop (n is the same as the bit position value) 9 9 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP10 Channel n GTCNT Count Stop (n is the same as the bit position value) 10 10 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP11 Channel n GTCNT Count Stop (n is the same as the bit position value) 11 11 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP12 Channel n GTCNT Count Stop (n is the same as the bit position value) 12 12 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP13 Channel n GTCNT Count Stop (n is the same as the bit position value) 13 13 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP14 Channel n GTCNT Count Stop (n is the same as the bit position value) 14 14 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP15 Channel n GTCNT Count Stop (n is the same as the bit position value) 15 15 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP16 Channel n GTCNT Count Stop (n is the same as the bit position value) 16 16 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP17 Channel n GTCNT Count Stop (n is the same as the bit position value) 17 17 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP18 Channel n GTCNT Count Stop (n is the same as the bit position value) 18 18 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP19 Channel n GTCNT Count Stop (n is the same as the bit position value) 19 19 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP20 Channel n GTCNT Count Stop (n is the same as the bit position value) 20 20 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP21 Channel n GTCNT Count Stop (n is the same as the bit position value) 21 21 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP22 Channel n GTCNT Count Stop (n is the same as the bit position value) 22 22 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP23 Channel n GTCNT Count Stop (n is the same as the bit position value) 23 23 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP24 Channel n GTCNT Count Stop (n is the same as the bit position value) 24 24 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP25 Channel n GTCNT Count Stop (n is the same as the bit position value) 25 25 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP26 Channel n GTCNT Count Stop (n is the same as the bit position value) 26 26 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP27 Channel n GTCNT Count Stop (n is the same as the bit position value) 27 27 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP28 Channel n GTCNT Count Stop (n is the same as the bit position value) 28 28 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP29 Channel n GTCNT Count Stop (n is the same as the bit position value) 29 29 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP30 Channel n GTCNT Count Stop (n is the same as the bit position value) 30 30 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP31 Channel n GTCNT Count Stop (n is the same as the bit position value) 31 31 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 GTCLR General PWM Timer Software Clear Register 0x0C 32 write-only 0x00000000 0xffffffff CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR10 Channel n GTCNT Count Clear (n : the same as bit position value) 10 10 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR11 Channel n GTCNT Count Clear (n : the same as bit position value) 11 11 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR12 Channel n GTCNT Count Clear (n : the same as bit position value) 12 12 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR13 Channel n GTCNT Count Clear (n : the same as bit position value) 13 13 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR14 Channel n GTCNT Count Clear (n : the same as bit position value) 14 14 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR15 Channel n GTCNT Count Clear (n : the same as bit position value) 15 15 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR16 Channel n GTCNT Count Clear (n : the same as bit position value) 16 16 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR17 Channel n GTCNT Count Clear (n : the same as bit position value) 17 17 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR18 Channel n GTCNT Count Clear (n : the same as bit position value) 18 18 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR19 Channel n GTCNT Count Clear (n : the same as bit position value) 19 19 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR20 Channel n GTCNT Count Clear (n : the same as bit position value) 20 20 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR21 Channel n GTCNT Count Clear (n : the same as bit position value) 21 21 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR22 Channel n GTCNT Count Clear (n : the same as bit position value) 22 22 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR23 Channel n GTCNT Count Clear (n : the same as bit position value) 23 23 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR24 Channel n GTCNT Count Clear (n : the same as bit position value) 24 24 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR25 Channel n GTCNT Count Clear (n : the same as bit position value) 25 25 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR26 Channel n GTCNT Count Clear (n : the same as bit position value) 26 26 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR27 Channel n GTCNT Count Clear (n : the same as bit position value) 27 27 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR28 Channel n GTCNT Count Clear (n : the same as bit position value) 28 28 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR29 Channel n GTCNT Count Clear (n : the same as bit position value) 29 29 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR30 Channel n GTCNT Count Clear (n : the same as bit position value) 30 30 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR31 Channel n GTCNT Count Clear (n : the same as bit position value) 31 31 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write 0x00000000 0xffffffff SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGCR GTETRGC Pin Rising Input Source Counter Start Enable 4 4 read-write 0 Counter start disabled on the rising edge of GTETRGC input #0 1 Counter start enabled on the rising edge of GTETRGC input #1 SSGTRGCF GTETRGC Pin Falling Input Source Counter Start Enable 5 5 read-write 0 Counter start disabled on the falling edge of GTETRGC input #0 1 Counter start enabled on the falling edge of GTETRGC input #1 SSGTRGDR GTETRGD Pin Rising Input Source Counter Start Enable 6 6 read-write 0 Counter start disabled on the rising edge of GTETRGD input #0 1 Counter start enabled on the rising edge of GTETRGD input #1 SSGTRGDF GTETRGD Pin Falling Input Source Counter Start Enable 7 7 read-write 0 Counter start disabled on the falling edge of GTETRGD input #0 1 Counter start enabled on the falling edge of GTETRGD input #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 20 read-write 0 Counter start disabled at the ELC_GPTE input #0 1 Counter start enabled at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 21 read-write 0 Counter start disabled at the ELC_GPTF input #0 1 Counter start enabled at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 22 read-write 0 Counter start disabled at the ELC_GPTG input #0 1 Counter start enabled at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 23 read-write 0 Counter start disabled at the ELC_GPTH input #0 1 Counter start enabled at the ELC_GPTH input #1 CSTRT Software Source Counter Start Enable 31 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write 0x00000000 0xffffffff PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGCR GTETRGC Pin Rising Input Source Counter Stop Enable 4 4 read-write 0 Counter stop disabled on the rising edge of GTETRGC input #0 1 Counter stop enabled on the rising edge of GTETRGC input #1 PSGTRGCF GTETRGC Pin Falling Input Source Counter Stop Enable 5 5 read-write 0 Counter stop disabled on the falling edge of GTETRGC input #0 1 Counter stop enabled on the falling edge of GTETRGC input #1 PSGTRGDR GTETRGD Pin Rising Input Source Counter Stop Enable 6 6 read-write 0 Counter stop disabled on the rising edge of GTETRGD input #0 1 Counter stop enabled on the rising edge of GTETRGD input #1 PSGTRGDF GTETRGD Pin Falling Input Source Counter Stop Enable 7 7 read-write 0 Counter stop disabled on the falling edge of GTETRGD input #0 1 Counter stop enabled on the falling edge of GTETRGD input #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 20 read-write 0 Counter stop disabled at the ELC_GPTE input #0 1 Counter stop enabled at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 21 read-write 0 Counter stop disabled at the ELC_GPTF input #0 1 Counter stop enabled at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 22 read-write 0 Counter stop disabled at the ELC_GPTG input #0 1 Counter stop enabled at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 23 read-write 0 Counter stop disabled at the ELC_GPTH input #0 1 Counter stop enabled at the ELC_GPTH input #1 CSTOP Software Source Counter Stop Enable 31 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write 0x00000000 0xffffffff CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGCR GTETRGC Pin Rising Input Source Counter Clear Enable 4 4 read-write 0 Disable counter clear on the rising edge of GTETRGC input #0 1 Enable counter clear on the rising edge of GTETRGC input #1 CSGTRGCF GTETRGC Pin Falling Input Source Counter Clear Enable 5 5 read-write 0 Counter clear disabled on the falling edge of GTETRGC input #0 1 Counter clear enabled on the falling edge of GTETRGC input #1 CSGTRGDR GTETRGD Pin Rising Input Source Counter Clear Enable 6 6 read-write 0 Disable counter clear on the rising edge of GTETRGD input #0 1 Enable counter clear on the rising edge of GTETRGD input #1 CSGTRGDF GTETRGD Pin Falling Input Source Counter Clear Enable 7 7 read-write 0 Counter clear disabled on the falling edge of GTETRGD input #0 1 Counter clear enabled on the falling edge of GTETRGD input #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 20 read-write 0 Counter clear disabled at the ELC_GPTE input #0 1 Counter clear enabled at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 21 read-write 0 Counter clear disabled at the ELC_GPTF input #0 1 Counter clear enabled at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 22 read-write 0 Counter clear disabled at the ELC_GPTG input #0 1 Counter clear enabled at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 23 read-write 0 Counter clear disabled at the ELC_GPTH input #0 1 Counter clear enabled at the ELC_GPTH input #1 CSCMSC Compare Match/Input Capture/Synchronous counter clearing Source Counter Clear Enable 24 26 read-write 000 Counter clear disabled by Compare match/ Input capture/ Synchronous counter clearing group #000 001 Counter clear enabled at the GTCCRA register compare match/ Input capture #001 010 Counter clear enabled at the GTCCRB register compare match/ Input capture #010 011 Counter clear enabled at the GTCCRC register compare match #011 100 Counter clear enabled at the GTCCRD register compare match #100 101 Counter clear enabled at the GTCCRE register compare match #101 110 Counter clear enabled at the GTCCRF register compare match #110 111 Counter clear enabled at the synchronous counter clearing group #111 CP1CCE Complementary PWM mode1 Crest Source Counter Clear Enable 27 27 read-write 0 Counter clear disabled at the crest of complementary PWM mode1 #0 1 Counter clear enabled at the crest of complementary PWM mode1 #1 CCLR Software Source Counter Clear Enable 31 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write 0x00000000 0xffffffff USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGCR GTETRGC Pin Rising Input Source Counter Count Up Enable 4 4 read-write 0 Counter count up disabled on the rising edge of GTETRGC input #0 1 Counter count up enabled on the rising edge of GTETRGC input #1 USGTRGCF GTETRGC Pin Falling Input Source Counter Count Up Enable 5 5 read-write 0 Counter count up disabled on the falling edge of GTETRGC input #0 1 Counter count up enabled on the falling edge of GTETRGC input #1 USGTRGDR GTETRGD Pin Rising Input Source Counter Count Up Enable 6 6 read-write 0 Counter count up disabled on the rising edge of GTETRGD input #0 1 Counter count up enabled on the rising edge of GTETRGD input #1 USGTRGDF GTETRGD Pin Falling Input Source Counter Count Up Enable 7 7 read-write 0 Counter count up disabled on the falling edge of GTETRGD input #0 1 Counter count up enabled on the falling edge of GTETRGD input #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 20 read-write 0 Counter count up disabled at the ELC_GPTE input #0 1 Counter count up enabled at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 21 read-write 0 Counter count up disabled at the ELC_GPTF input #0 1 Counter count up enabled at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 22 read-write 0 Counter count up disabled at the ELC_GPTG input #0 1 Counter count up enabled at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 23 read-write 0 Counter count up disabled at the ELC_GPTH input #0 1 Counter count up enabled at the ELC_GPTH input #1 USILVL External Input Level Source Count-Up Enable 24 27 read-write 0000 Disables count-up by external input level #0000 0001 Setting prohibited #0001 0010 Enables count-up by GTIOCnA pin input level 0 #0010 0011 Enables count-up by GTIOCnA pin input level 1 #0011 0100 Enables count-up by GTIOCnB pin input level 0 #0100 0101 Enables count-up by GTIOCnB pin input level 1 #0101 0110 Setting prohibited #0110 0111 Setting prohibited #0111 1000 Enables count-up by GTETRGA pin input level 0 #1000 1001 Enables count-up by GTETRGA pin input level 1 #1001 1010 Enables count-up by GTETRGB pin input level 0 #1010 1011 Enables count-up by GTETRGB pin input level 1 #1011 1100 Enables count-up by GTETRGC pin input level 0 #1100 1101 Enables count-up by GTETRGC pin input level 1 #1101 1110 Enables count-up by GTETRGD pin input level 0 #1110 1111 Enables count-up by GTETRGD pin input level 1 #1111 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write 0x00000000 0xffffffff DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGCR GTETRGC Pin Rising Input Source Counter Count Down Enable 4 4 read-write 0 Counter count down disabled on the rising edge of GTETRGC input #0 1 Counter count down enabled on the rising edge of GTETRGC input #1 DSGTRGCF GTETRGC Pin Falling Input Source Counter Count Down Enable 5 5 read-write 0 Counter count down disabled on the falling edge of GTETRGC input #0 1 Counter count down enabled on the falling edge of GTETRGC input #1 DSGTRGDR GTETRGD Pin Rising Input Source Counter Count Down Enable 6 6 read-write 0 Counter count down disabled on the rising edge of GTETRGD input #0 1 Counter count down enabled on the rising edge of GTETRGD input #1 DSGTRGDF GTETRGD Pin Falling Input Source Counter Count Down Enable 7 7 read-write 0 Counter count down disabled on the falling edge of GTETRGD input #0 1 Counter count down enabled on the falling edge of GTETRGD input #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 20 read-write 0 Counter count down disabled at the ELC_GPTE input #0 1 Counter count down enabled at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 21 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 22 read-write 0 Counter count down disabled at the ELC_GPTG input #0 1 Counter count down enabled at the ELC_GPTG input #1 DSELCH ELC_GPTF Event Source Counter Count Down Enable 23 23 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSILVL External Input Level Source Count-Down Enable 24 27 read-write 0000 Disables count-down by external input level #0000 0001 Setting prohibited #0001 0010 Enables count-down by GTIOCnA pin input level 0 #0010 0011 Enables count-down by GTIOCnA pin input level 1 #0011 0100 Enables count-down by GTIOCnB pin input level 0 #0100 0101 Enables count-down by GTIOCnB pin input level 1 #0101 0110 Setting prohibited #0110 0111 Setting prohibited #0111 1000 Enables count-down by GTETRGA pin input level 0 #1000 1001 Enables count-down by GTETRGA pin input level 1 #1001 1010 Enables count-down by GTETRGB pin input level 0 #1010 1011 Enables count-down by GTETRGB pin input level 1 #1011 1100 Enables count-down by GTETRGC pin input level 0 #1100 1101 Enables count-down by GTETRGC pin input level 1 #1101 1110 Enables count-down by GTETRGD pin input level 0 #1110 1111 Enables count-down by GTETRGD pin input level 1 #1111 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write 0x00000000 0xffffffff ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGCR GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable 4 4 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGC input #1 ASGTRGCF GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable 5 5 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGC input #1 ASGTRGDR GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable 6 6 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGD input #1 ASGTRGDF GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable 7 7 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGD input #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 20 read-write 0 GTCCRA input capture disabled at the ELC_GPTE input #0 1 GTCCRA input capture enabled at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 21 read-write 0 GTCCRA input capture disabled at the ELC_GPTF input #0 1 GTCCRA input capture enabled at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 22 read-write 0 GTCCRA input capture disabled at the ELC_GPTG input #0 1 GTCCRA input capture enabled at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 23 read-write 0 GTCCRA input capture disabled at the ELC_GPTH input #0 1 GTCCRA input capture enabled at the ELC_GPTH input #1 ASOC Other channel Source GTCCRA Input Capture Enable 24 24 read-write 0 Disables GTCCRA input capture by other channel factor #0 1 Enables GTCCRA input capture by other channel factor #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write 0x00000000 0xffffffff BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGCR GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable 4 4 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGC input #1 BSGTRGCF GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable 5 5 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGC input #1 BSGTRGDR GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable 6 6 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGD input #1 BSGTRGDF GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable 7 7 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGD input #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 20 read-write 0 GTCCRB input capture disabled at the ELC_GPTE input #0 1 GTCCRB input capture enabled at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 21 read-write 0 GTCCRB input capture disabled at the ELC_GPTF input #0 1 GTCCRB input capture enabled at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 22 read-write 0 GTCCRB input capture disabled at the ELC_GPTG input #0 1 GTCCRB input capture enabled at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 23 read-write 0 GTCCRB input capture disabled at the ELC_GPTH input #0 1 GTCCRB input capture enabled at the ELC_GPTH input #1 BSOC Other channel Source GTCCRB Input Capture Enable 24 24 read-write 0 Disables GTCCRB input capture by other channel factor #0 1 Enables GTCCRB input capture by other channel factor #1 GTCR General PWM Timer Control Register 0x2C 32 read-write 0x00000000 0xffffffff CST Count Start 0 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 ICDS Input Capture Operation Select During Count Stop 8 8 read-write 0 Input capture is operated during count stop. #0 1 Input capture is not operated during count stop. #1 SCGTIOC GTIOC input Source Synchronous Clear Enable 9 9 read-write 0 Disables to use the counter clear by GTIOC input as the clear factor for other channels #0 1 Enables to use the counter clear by GTIOC input as the clear factor for other channels #1 SSCGRP Synchronous Set/Clear Group Select 10 11 read-write 00 Select synchronous set/clear group A #00 01 Select synchronous set/clear group B #01 10 Select synchronous set/clear group C #10 11 Select synchronous set/clear group D #11 CPSCD Complementary PWM Mode Synchronous Clear Disable 12 12 read-write 0 Enable synchronous counter clear by other channel other than the section of trough in complementary PWM mode #0 1 Disable synchronous counter clear by other channel other than the section of trough in complementary PWM mode #1 SSCEN Synchronous Set/Clear Enable 15 15 read-write 0 Disable Synchronous set/clear of the GTCNT counter #0 1 Enable Synchronous set/clear of the GTCNT counter #1 MD Mode Select 16 19 read-write 0000 Saw-wave PWM mode 1(single buffer or double buffer possible) #0000 0001 Saw-wave one-shot pulse mode (fixed buffer operation) #0001 0010 Saw-wave PWM mode 2(single buffer or double buffer possible) #0010 0011 Setting prohibited #0011 0100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer possible) #0100 0101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer possible) #0101 0110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #0110 0111 Setting prohibited #0111 1000 Setting prohibited #1000 1001 Setting prohibited #1001 1010 Setting prohibited #1010 1011 Setting prohibited #1011 1100 Complementary PWM mode 1(transfer at crest) #1100 1101 Complementary PWM mode 2(transfer at trough) #1101 1110 Complementary PWM mode 3(transfer at crest and trough) #1110 1111 Complementary PWM mode 4(immediate transfer) #1111 TPCS Timer Prescaler Select 23 26 read-write 0000 GTCLK/1 #0000 0001 GTCLK/2 #0001 0010 GTCLK/4 #0010 0011 GTCLK/8 #0011 0100 GTCLK/16 #0100 0101 GTCLK/32 #0101 0110 GTCLK/64 #0110 0111 GTCLK/128 #0111 1000 GTCLK/256 #1000 1001 GTCLK/512 #1001 1010 GTCLK/1024 #1010 1011 Setting prohibited #1011 1100 GTETRGA (Via the POEG) #1100 1101 GTETRGB (Via the POEG) #1101 1110 GTETRGC (Via the POEG) #1110 1111 GTETRGD (Via the POEG)POEG接続数に応じた、GTETRGA-D表示制御必要。 #1111 CKEG Clock Edge Select 27 28 read-write 00 Select rising edge of GTETRG for clock count #00 01 Select falling edge of GTETRG for clock count #01 Others Select both edge of GTETRG for clock count true GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write 0x00000001 0xffffffff UD Count Direction Setting 0 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTY GTIOCnA Output Duty Setting 16 17 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 19 read-write 0 The function selected by the GTIOA[3:2] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting. #0 1 The function selected by the GTIOA[3:2] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting. #1 OBDTY GTIOCnB Output Duty Setting 24 25 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 27 read-write 0 The function selected by the GTIOB[3:2] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting. #0 1 The function selected by the GTIOB[3:2] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting. #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write 0x00000000 0xffffffff GTIOA GTIOCnA Pin Function Select 0 4 read-write CPSCIR Complementary PWM Mode Initial Output at Synchronous Clear Disable 5 5 read-write 0 Output the initial value set by the GTIOR.GTIOA and GTIOB bits when synchronous clear occurs in Trough section of complementary PWM mode #0 1 Disable output the initial value #1 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OAE GTIOCnA Pin Output Enable 8 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OADF GTIOCnA Pin Disable Value Setting 9 10 read-write 00 None of the below options are specified #00 01 GTIOCnA pin is set to Hi-Z in response to controlling the output negation #01 10 GTIOCnA pin is set to 0 in response to controlling the output negation #10 11 GTIOCnA pin is set to 1 in response to controlling the output negation #11 OAEOCD GTCCRA Compare Match Cycle End Output Invalidate 11 11 read-write 0 Validate GTIOA[3:2] setting #0 1 Invalidate GTIOA[3:2] setting (GTIOCnA pin output is retained) #1 PSYE PWM Synchronous output Enable 12 12 read-write 0 Disable GTCPPOm pin output #0 1 Enable GTCPPOm pin output #1 NFAEN Noise Filter A Enable 13 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 15 read-write 00 GTCLK/1 #00 01 GTCLK/4 #01 10 GTCLK/16 #10 11 GTCLK/64 #11 GTIOB GTIOCnB Pin Function Select 16 20 read-write OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 OBE GTIOCnB Pin Output Enable 24 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBDF GTIOCnB Pin Disable Value Setting 25 26 read-write 00 None of the below options are specified #00 01 GTIOCnB pin is set to Hi-Z in response to controlling the output negation #01 10 GTIOCnB pin is set to 0 in response to controlling the output negation #10 11 GTIOCnB pin is set to 1 in response to controlling the output negation #11 OBEOCD GTCCRB Compare Match Cycle End Output Invalidate 27 27 read-write 0 When Saw-wave PWM mode 1, validate GTIOB[3:2] setting When Saw-wave PWM mode 2, validate GTIOA[3:2] setting #0 1 When Saw-wave PWM mode 1, invalidate GTIOB[3:2] setting (GTIOCnB pin output is retained) When Saw-wave PWM mode 2, invalidate GTIOA[3:2] setting (GTIOCnA pin output is retained) #1 NFBEN Noise Filter B Enable 29 29 read-write 0 The noise filter for the GTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSB Noise Filter B Sampling Clock Select 30 31 read-write 00 GTCLK/1 #00 01 GTCLK/4 #01 10 GTCLK/16 #10 11 GTCLK/64 #11 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write 0x00000000 0xffffffff SCFA GTCCRA Register Compare Match/Input Capture Source Synchronous Clear Enable 8 8 read-write 0 Disable use of GTCCRA register compare match/input capture as a clear factor for other channels. #0 1 Enable use of GTCCRA register compare match/input capture as a clear factor for other channels. #1 SCFB GTCCRB Register Compare Match/Input Capture Source Synchronous Clear Enable 9 9 read-write 0 Disable use of GTCCRB register compare match/input capture as a clear factor for other channels. #0 1 Enable use of GTCCRB register compare match/input capture as a clear factor for other channels. #1 SCFC GTCCRC Register Compare Match Source Synchronous Clear Enable 10 10 read-write 0 Disable use of GTCCRC register compare match as a clear factor for other channels. #0 1 Enable use of GTCCRC register compare match as a clear factor for other channels. #1 SCFD GTCCRD Register Compare Match Source Synchronous Clear Enable 11 11 read-write 0 Disable use of GTCCRD register compare match as a clear factor for other channels. #0 1 Enable use of GTCCRD register compare match as a clear factor for other channels. #1 SCFE GTCCRE Register Compare Match Source Synchronous Clear Enable 12 12 read-write 0 Disable use of GTCCRE register compare match as a clear factor for other channels. #0 1 Enable use of GTCCRE register compare match as a clear factor for other channels #1 SCFF GTCCRF Register Compare Match Source Synchronous Clear Enable 13 13 read-write 0 Disable use of GTCCRF register compare match as a clear factor for other channels. #0 1 Enable use of GTCCRF register compare match as a clear factor for other channels #1 SCFPO Overflow Source Synchronous Clear Enable 14 14 read-write 0 Disable use of overflow as a clear factor for other channels. #0 1 Enable use of overflow as a clear factor for other channels. #1 SCFPU Underflow Source Synchronous Clear Enable 15 15 read-write 0 Disable use of underflow as a clear factor for other channels #0 1 Enable use of underflow as a clear factor for other channels #1 ADTRAUEN GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Enable 16 16 read-write 0 A/D conversion start request is disabled. #0 1 A/D conversion start request is enabled. #1 ADTRADEN GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Enable 17 17 read-write 0 A/D conversion start request is disabled. #0 1 A/D conversion start request is enabled. #1 ADTRBUEN GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Enable 18 18 read-write 0 A/D conversion start request is disabled. #0 1 A/D conversion start request is enabled. #1 ADTRBDEN GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Enable 19 19 read-write 0 A/D conversion start request is disabled. #0 1 A/D conversion start request is enabled. #1 GRP Output Disable Source Select 24 25 read-write 00 Group A output disable source is selected Group B output disable source is selected Group C output disable source is selected Group D output disable source is selected #00 GRPDTE Dead Time Error Output Disable Request Enable 28 28 read-write 0 Dead time error output disable request is disabled. #0 1 Dead time error output disable request is enabled. #1 GRPABH Same Time Output Level High Disable Request Enable 29 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTST General PWM Timer Status Register 0x3C 32 read-write 0x00008000 0xffffffff TCFA Input Capture/Compare Match Flag A 0 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 ITCNT GPTn_OVF/GPTn_UDF Interrupt Skipping Count Counter 8 10 read-only TUCF Count Direction Flag 15 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 ADTRAUF GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag 16 16 read-write 0 No GTADTRA register compare match has occurred in up-counting. #0 1 A GTADTRA register compare match has occurred in up-counting. #1 ADTRADF GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag 17 17 read-write 0 No GTADTRA register compare match has occurred in down-counting. #0 1 A GTADTRA register compare match has occurred in down-counting. #1 ADTRBUF GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag 18 18 read-write 0 No GTADTRB register compare match has occurred in up-counting. #0 1 A GTADTRB register compare match has occurred in up-counting. #1 ADTRBDF GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag 19 19 read-write 0 No GTADTRB register compare match has occurred in down-counting. #0 1 A GTADTRB register compare match has occurred in down-counting. #1 ODF Output Disable Flag 24 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 DTEF Dead Time Error Flag 28 28 read-only 0 No dead time error has occurred. #0 1 A dead time error has occurred. #1 OABHF Same Time Output Level High Flag 29 29 read-only 0 No simultaneous generation of 1 both for the GTIOCA and GTIOCB pins has occurred. #0 1 A simultaneous generation of 1 both for the GTIOCA and GTIOCB pins has occurred. #1 OABLF Same Time Output Level Low Flag 30 30 read-only 0 No simultaneous generation of 0 both for the GTIOCA and GTIOCB pins has occurred. #0 1 A simultaneous generation of 0 both for the GTIOCA and GTIOCB pins has occurred. #1 PCF Period Count Function Finish Flag 31 31 read-write 0 No period count function finish has occurred #0 1 A period count function finish has occurred #1 GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write 0x00000000 0xffffffff BD0 GTCCR Buffer Operation Disable 0 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD2 GTADTRA/GTADTRB Registers Buffer Operation Disable 2 2 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD3 GTDVU/GTDVD Registers Buffer Operation Disable 3 3 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 DBRTECA GTCCRA Register Double Buffer Repeat Operation Enable 8 8 read-write 0 GTCCRA register double buffer repeat operation is disabled #0 1 GTCCRA register double buffer repeat operation is enabled #1 DBRTECB GTCCRB Register Double Buffer Repeat Operation Enable 10 10 read-write 0 GTCCRB register double buffer repeat operation is disabled #0 1 GTCCRB register double buffer repeat operation is enabled #1 CCRA GTCCRA Buffer Operation 16 17 read-write 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) true CCRB GTCCRB Buffer Operation 18 19 read-write 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) true PR GTPR Buffer Operation 20 21 read-write 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 Others Double buffer operation (GTPDBR --> GTPBR --> GTPR) true CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 22 write-only ADTTA GTADTRA Register Buffer Transfer Timing Select 24 25 read-write 00 In triangle wave or complementary PWM mode, no transfer. In saw-wave mode, no transfer. #00 01 In triangle wave or complementary PWM mode, transfer at crest. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing. #01 10 In triangle wave or complementary PWM mode, transfer at trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing. #10 11 In triangle wave or complementary PWM mode, transfer at both crest and trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing. #11 ADTDA GTADTRA Register Double Buffer Operation 26 26 read-write 0 Single buffer operation (GTADTBRA --> GTADTRA) #0 1 Double buffer operation (GTADTDBRA --> GTADTBRA --> GTADTRA) #1 ADTTB GTADTRB Register Buffer Transfer Timing Select 28 29 read-write 00 In triangle wave or complementary PWM mode, no transfer. In saw-wave mode, no transfer. #00 01 In triangle wave or complementary PWM mode, transfer at crest. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing. #01 10 In triangle wave or complementary PWM mode, transfer at trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing. #10 11 In triangle wave or complementary PWM mode, transfer at both crest and trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing. #11 ADTDB GTADTRB Register Double Buffer Operation 30 30 read-write 0 Single buffer operation (GTADTBRB --> GTADTRB) #0 1 Double buffer operation (GTADTDBRB --> GTADTBRB --> GTADTRB) #1 GTITC General PWM Timer Interrupt and A/D Conversion Start Request Skipping Setting Register 0x44 32 read-write 0x00000000 0xffffffff ITLA GTCCRA Register Compare Match/Input Capture Interrupt Link 0 0 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 ITLB GTCCRB Register Compare Match/Input Capture Interrupt Link 1 1 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 ITLC GTCCRC Register Compare Match Interrupt Link 2 2 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 ITLD GTCCRD Register Compare Match Interrupt Link 3 3 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 ITLE GTCCRE Register Compare Match Interrupt Link 4 4 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 ITLF GTCCRF Register Compare Match Interrupt Link 5 5 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 IVTC GPTn_OVF/GPTn_UDF Interrupt Skipping Function Select 6 7 read-write 00 Skipping is not performed. #00 01 Both overflow and underflow for saw waves and crest for triangle waves and complementary PWM mode are counted and skipped. #01 10 Both overflow and underflow for saw waves and trough for triangle waves and complementary PWM mode are counted and skipped. #10 11 Both overflow and underflow for saw waves and both crest and trough for triangle waves and complementary PWM mode are counted and skipped. #11 IVTT GPTn_OVF/GPTn_UDF Interrupt Skipping Count Select 8 10 read-write 000 Skipping is not performed #000 001 Skipping count of 1 #001 010 Skipping count of 2 #010 011 Skipping count of 3 #011 100 Skipping count of 4 #100 101 Skipping count of 5 #101 110 Skipping count of 6 #110 111 Skipping count of 7 #111 ADTAL GTADTRA Register A/D Conversion Start Request Link 12 12 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 ADTBL GTADTRB Register A/D Conversion Start Request Link 14 14 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 GTCNT General PWM Timer Counter 0x48 32 read-write 0x00000000 0xffffffff GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write 0xffffffff 0xffffffff GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write 0xffffffff 0xffffffff GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write 0xffffffff 0xffffffff GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write 0xffffffff 0xffffffff GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write 0xffffffff 0xffffffff GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write 0xffffffff 0xffffffff GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write 0xffffffff 0xffffffff GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write 0xffffffff 0xffffffff GTPDBR General PWM Timer Cycle Setting Double-Buffer Register 0x6C 32 read-write 0xffffffff 0xffffffff GTADTRA A/D Conversion Start Request Timing Register A 0x70 32 read-write 0xffffffff 0xffffffff GTADTBRA A/D Conversion Start Request Timing Buffer Register A 0x74 32 read-write 0xffffffff 0xffffffff GTADTDBRA A/D Conversion Start Request Timing Double-Buffer Register A 0x78 32 read-write 0xffffffff 0xffffffff GTADTRB A/D Conversion Start Request Timing Register B 0x7C 32 read-write 0xffffffff 0xffffffff GTADTBRB A/D Conversion Start Request Timing Buffer Register B 0x80 32 read-write 0xffffffff 0xffffffff GTADTDBRB A/D Conversion Start Request Timing Double-Buffer Register B 0x84 32 read-write 0xffffffff 0xffffffff GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write 0x00000000 0xffffffff TDE Negative-Phase Waveform Setting 0 0 read-write 0 GTCCRB is set without using GTDVU and GTDVD #0 1 GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB #1 TDBUE GTDVU Register Buffer Operation Enable 4 4 read-write 0 GTDVU register buffer operation is disabled #0 1 GTDVU register buffer operation is enabled #1 TDBDE GTDVD Register Buffer Operation Enable 5 5 read-write 0 GTDVD register buffer operation is disabled #0 1 GTDVD register buffer operation is enabled #1 TDFER GTDVD Register Setting 8 8 read-write 0 GTDVU and GTDVD registers are set separately. #0 1 The value written to GTDVU register is automatically set to GTDVD register. #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write 0xffffffff 0xffffffff GTDVD General PWM Timer Dead Time Value Register D 0x90 32 read-write 0xffffffff 0xffffffff GTDBU General PWM Timer Dead Time Buffer Register U 0x94 32 read-write 0xffffffff 0xffffffff GTDBD General PWM Timer Dead Time Buffer Register D 0x98 32 read-write 0xffffffff 0xffffffff GTSOS General PWM Timer Output Protection Function Status Register 0x9C 32 read-only 0x00000000 0xffffffff SOS Output Protection Function Status 0 1 read-only 00 Normal operation #00 01 Protected state (GTCCRA = 0 is set during transfer at trough or crest) #01 10 Protected state (GTCCRA ≥ GTPR is set during transfer at trough) #10 11 Protected state (GTCCRA ≥ GTPR is set during transfer at crest) #11 GTSOTR General PWM Timer Output Protection Function Temporary Release Register 0xA0 32 read-write 0x00000000 0xffffffff SOTR Output Protection Function Temporary Release 0 0 read-write 0 Protected state is not released #0 1 Protected state is released #1 GTADSMR General PWM Timer A/D Conversion Start Request Signal Monitoring Register 0xA4 32 read-write 0x00000000 0xffffffff ADSMS0 A/D Conversion Start Request Signal Monitor 0 Selection 0 1 read-write 00 A/D conversion start request signal generated by the GTADTRA register during up-counting. #00 01 A/D conversion start request signal generated by the GTADTRA register during down-counting. #01 10 A/D conversion start request signal generated by the GTADTRB register during up-counting. #10 11 A/D conversion start request signal generated by the GTADTRB register during down-counting. #11 ADSMEN0 A/D Conversion Start Request Signal Monitor 0 Output Enabling 8 8 read-write 0 Output of A/D conversion start request signal monitor 0 is disabled. #0 1 Output of A/D conversion start request signal monitor 0 is enabled. #1 ADSMS1 A/D Conversion Start Request Signal Monitor 1 Selection 16 17 read-write 00 A/D conversion start request signal generated by the GTADTRA register during up-counting. #00 01 A/D conversion start request signal generated by the GTADTRA register during down-counting. #01 10 A/D conversion start request signal generated by the GTADTRB register during up-counting. #10 11 A/D conversion start request signal generated by the GTADTRB register during down-counting. #11 ADSMEN1 A/D Conversion Start Request Signal Monitor 1 Output Enabling 24 24 read-write 0 Output of A/D conversion start request signal monitor 1 is disabled. #0 1 Output of A/D conversion start request signal monitor 1 is enabled. #1 GTEITC General PWM Timer Extended Interrupt Skipping Counter Control Register 0xA8 32 read-write 0x00000000 0xffffffff EIVTC1 Extended Interrupt Skipping Counter 1 Count Source Select 0 1 read-write 00 Not counted (not skipped) #00 01 Counting both at overflow or underflow in saw-wave mode, and counting crests in triangle-wave mode or complementary PWM mode #01 10 Counting both at overflow or underflow in saw-wave mode, and counting troughs in triangle-wave mode or complementary PWM mode #10 11 Counting both at overflow or underflow in saw-wave mode, and counting both crests and troughs in triangle-wave mode or complementary PWM mode #11 EIVTT1 Extended Interrupt Skipping 1 Skipping Count Setting 4 7 read-write EITCNT1 Extended Interrupt Skipping Counter 1 12 15 read-only EIVTC2 Extended Interrupt Skipping Counter 2 Count Source select 16 17 read-write 00 Not counted (not skipped) #00 01 Counting both at overflow or underflow in saw-wave mode, and counting crests in triangle-wave mode or complementary PWM mode #01 10 Counting both at overflow or underflow in saw-wave mode, and counting troughs in triangle-wave mode or complementary PWM mode #10 11 Counting both at overflow or underflow in saw-wave mode, and counting both crests and troughs in triangle-wave mode or complementary PWM mode #11 EIVTT2 Extended Interrupt Skipping 2 Skipping Count Setting 20 23 read-write EITCNT2IV Extended Interrupt Skipping Counter 2 Initial Value 24 27 read-write EITCNT2 Extended Interrupt Skipping Counter 2 28 31 read-only GTEITLI1 General PWM Timer Extended Interrupt Skipping Setting Register 1 0xAC 32 read-write 0x00000000 0xffffffff EITLA GTCCRA Register Compare Match/Input Capture Interrupt Extended Skipping Function Select 0 2 read-write EITLB GTCCRB Register Compare Match/Input Capture Interrupt Extended Skipping Function Select 4 6 read-write EITLC GTCCRC Register Compare Match Interrupt Extended Skipping Function Select 8 10 read-write EITLD GTCCRD Register Compare Match Interrupt Extended Skipping Function Select 12 14 read-write EITLE GTCCRE Register Compare Match Interrupt Extended Skipping Function Select 16 18 read-write EITLF GTCCRF Register Compare Match Interrupt Extended Skipping Function Select 20 22 read-write EITLV Overflow Interrupt Extended Skipping Function Select 24 26 read-write EITLU Underflow Interrupt Extended Skipping Function Select 28 30 read-write GTEITLI2 General PWM Timer Extended Interrupt Skipping Setting Register 2 0xB0 32 read-write 0x00000000 0xffffffff EADTAL GTADTRA Register A/D Conversion Start Request Extended Skipping Function Select 0 2 read-write EADTBL GTADTRB Register A/D Conversion Start Request Extended Skipping Function Select 4 6 read-write GTEITLB General PWM Timer Extended Buffer Transfer Skipping Setting Register 0xB4 32 read-write 0x00000000 0xffffffff EBTLCA GTCCRA Register Buffer Transfer Extended Skipping Function Select 0 2 read-write EBTLCB GTCCRB Register Buffer Transfer Extended Skipping Function Select 4 6 read-write EBTLPR GTPR Register Buffer Transfer Extended Skipping Function Select 8 10 read-write EBTLADA GTADTRA Register Buffer Transfer Extended Skipping Function Select 16 18 read-write EBTLADB GTADTRB Register Buffer Transfer Extended Skipping Function Select 20 22 read-write EBTLDVU GTDVU Register Buffer Transfer Extended Skipping Function Select 24 26 read-write EBTLDVD GTDVD Register Buffer Transfer Extended Skipping Function Select 28 30 read-write GTICLF General PWM Timer Inter Channel Logical Operation Function Setting Register 0xB8 32 read-write 0x00000000 0xffffffff ICLFA GTIOCnA Output Logical Operation Function Select 0 2 read-write 000 A (no delay) #000 001 NOT A (no delay) #001 010 C (1GTCLK delay) #010 011 NOT C (1GTCLK delay) #011 100 A AND C (1GTCLK delay) #100 101 A OR C (1GTCLK delay) #101 110 A EXOR C (1GTCLK delay) #110 111 A NOR C (1GTCLK delay) #111 ICLFSELC Inter Channel Signal C Select 4 9 read-write ICLFB GTIOCnB Output Logical Operation Function Select 16 18 read-write 000 B (no delay) #000 001 NOT B (no delay) #001 010 D (1GTCLK delay) #010 011 NOT D (1GTCLK delay) #011 100 B AND D (1GTCLK delay) #100 101 B OR D (1GTCLK delay) #101 110 B EXOR D (1GTCLK delay) #110 111 B NOR D (1GTCLK delay) #111 ICLFSELD Inter Channel Signal D Select 20 25 read-write GTPC General PWM Timer Period Count Register 0xBC 32 read-write 0x00000000 0xffffffff PCEN Period Count Function Enable 0 0 read-write 0 Period count function is disabled #0 1 Period count function is enabled #1 ASTP Automatic Stop Function Enable 8 8 read-write 0 Automatic stop function is disabled #0 1 Automatic stop function is enabled #1 PCNT Period Counter 16 27 read-write GTSECSR General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register 0xD0 32 read-write 0x00000000 0xffffffff SECSEL0 Channel 0 Operation Enable Bit Simultaneous Control Channel Select 0 0 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL1 Channel 1 Operation Enable Bit Simultaneous Control Channel Select 1 1 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL2 Channel 2 Operation Enable Bit Simultaneous Control Channel Select 2 2 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL3 Channel 3 Operation Enable Bit Simultaneous Control Channel Select 3 3 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL4 Channel 4 Operation Enable Bit Simultaneous Control Channel Select 4 4 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL5 Channel 5 Operation Enable Bit Simultaneous Control Channel Select 5 5 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL6 Channel 6 Operation Enable Bit Simultaneous Control Channel Select 6 6 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL7 Channel 7 Operation Enable Bit Simultaneous Control Channel Select 7 7 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL8 Channel 8 Operation Enable Bit Simultaneous Control Channel Select 8 8 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL9 Channel 9 Operation Enable Bit Simultaneous Control Channel Select 9 9 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 GTSECR General PWM Timer Operation Enable Bit Simultaneous Control Register 0xD4 32 read-write 0x00000000 0xffffffff SBDCE GTCCR Register Buffer Operation Simultaneous Enable 0 0 read-write 0 Disable simultaneous enabling GTCCR buffer operations #0 1 Enable GTCCR register buffer operations simultaneously #1 SBDPE GTPR Register Buffer Operation Simultaneous Enable 1 1 read-write 0 Disable simultaneous enabling GTPR buffer operations #0 1 Enable GTPR register buffer operations simultaneously #1 SBDAE GTADTR Register Buffer Operation Simultaneous Enable 2 2 read-write 0 Disable simultaneous enabling GTADTR buffer operations #0 1 Enable GTADTR register buffer operations simultaneously #1 SBDDE GTDV Register Buffer Operation Simultaneous Enable 3 3 read-write 0 Disable simultaneous enabling GTDV buffer operations #0 1 Enable GTDV register buffer operations simultaneously #1 SBDCD GTCCR Register Buffer Operation Simultaneous Disable 8 8 read-write 0 Disable simultaneous disabling GTCCR buffer operations #0 1 Disable GTCCR register buffer operations simultaneously #1 SBDPD GTPR Register Buffer Operation Simultaneous Disable 9 9 read-write 0 Disable simultaneous disabling GTPR buffer operations #0 1 Disable GTPR register buffer operations simultaneously #1 SBDAD GTADTR Register Buffer Operation Simultaneous Disable 10 10 read-write 0 Disable simultaneous disabling GTADTR buffer operations #0 1 Disable GTADTR register buffer operations simultaneously #1 SBDDD GTDV Register Buffer Operation Simultaneous Disable 11 11 read-write 0 Disable simultaneous disabling GTDV buffer operations #0 1 Disable GTDV register buffer operations simultaneously #1 SPCE Period Count Function Simultaneous Enable 16 16 read-write 0 Disable simultaneous enabling period count function #0 1 Enable period count function simultaneously #1 SSCE Synchronous Set/Clear Simultaneous Enable 17 17 read-write 0 Disable simultaneous enabling synchronous set/clear #0 1 Enable synchronous set/clear simultaneously #1 SPCD Period Count Function Simultaneous Disable 24 24 read-write 0 Disable simultaneous disabling period count function #0 1 Disable period count function simultaneously #1 SSCD Synchronous Set/Clear Simultaneous Disable 25 25 read-write 0 Disable simultaneous disabling synchronous set/clear #0 1 Disable synchronous set/clear simultaneously #1 GTBER2 General PWM Timer Buffer Enable Register 2 0xE0 32 read-write 0x00000000 0xffffffff CCTCA Counter Clear Source GTCCRA Register Buffer Transfer Disable 0 0 read-write 0 Enable GTCCRA register buffer transfer by counter clear #0 1 Disable GTCCRA register buffer transfer by counter clear #1 CCTCB Counter Clear Source GTCCRB Register Buffer Transfer Disable 1 1 read-write 0 Enable GTCCRB register buffer transfer by counter clear #0 1 Disable GTCCRB register buffer transfer by counter clear #1 CCTPR Counter Clear Source GTPR Register Buffer Transfer Disable 2 2 read-write 0 Enable GTPR register buffer transfer by counter clear #0 1 Disable GTPR register buffer transfer by counter clear #1 CCTADA Counter Clear Source GTADTRA Register Buffer Transfer Disable 3 3 read-write 0 Enable GTADTRA register buffer transfer by counter clear #0 1 Disable GTADTRA register buffer transfer by counter clear #1 CCTADB Counter Clear Source GTADTRB Register Buffer Transfer Disable 4 4 read-write 0 Enable GTADTRB register buffer transfer by counter clear #0 1 Disable GTADTRB register buffer transfer by counter clear #1 CCTDV Counter Clear Source GTDVU/GTDVD Register Buffer Transfer Disable 5 5 read-write 0 Enable GTDVU/GTDVD register buffer transfer by counter clear #0 1 Disable GTDVU/GTDVD register buffer transfer by counter clear #1 CMTCA Compare Match Source GTCCRA Register Buffer Transfer Enable 8 9 read-write 00 Disable GTCCRA register Buffer Transfer by compare match of GTCCRA register and GTCCRB register #00 01 Enable GTCCRA register Buffer Transfer by compare match of GTCCRA register #01 10 Enable GTCCRA register Buffer Transfer by compare match of GTCCRB register #10 11 Enable GTCCRA register Buffer Transfer by compare match of GTCCRA register and GTCCRB register #11 CMTCB Compare Match Source GTCCRB Register Buffer Transfer Enable 10 11 read-write 00 Disable GTCCRB register Buffer Transfer by compare match of GTCCRA register and GTCCRB register #00 01 Enable GTCCRB register Buffer Transfer by compare match of GTCCRA register #01 10 Enable GTCCRB register Buffer Transfer by compare match of GTCCRB register #10 11 Enable GTCCRB register Buffer Transfer by compare match of GTCCRA register and GTCCRB register #11 CMTADA Compare Match Source GTADTRA Register Buffer Transfer Enable 13 13 read-write 0 Disable GTADTRA register buffer transfer by compare match of GTADTRA register #0 1 Enable GTADTRA register buffer transfer by compare match of GTADTRA register #1 CMTADB Compare Match Source GTADTRB Register Buffer Transfer Enable 14 14 read-write 0 Disable GTADTRB register buffer transfer by compare match of GTADTRB register #0 1 Enable GTADTRB register buffer transfer by compare match of GTADTRB register #1 CPTCA Overflow/Underflow Source GTCCRA Register Buffer Transfer Disable 16 16 read-write 0 Enable GTCCRA register buffer transfer by overflow/underflow #0 1 Disable GTCCRA register buffer transfer by overflow/underflow #1 CPTCB Overflow/Underflow Source GTCCRB Register Buffer Transfer Disable 17 17 read-write 0 Enable GTCCRB register buffer transfer by overflow/underflow #0 1 Disable GTCCRB register buffer transfer by overflow/underflow #1 CPTPR Overflow/Underflow Source GTPR Register Buffer Transfer Disable 18 18 read-write 0 Enable GTPR register buffer transfer by overflow/underflow #0 1 Disable GTPR register buffer transfer by overflow/underflow #1 CPTADA Overflow/Underflow Source GTADTRA Register Buffer Transfer Disable 19 19 read-write 0 Enable GTADTRA register buffer transfer by overflow/underflow #0 1 Disable GTADTRA register buffer transfer by overflow/underflow #1 CPTADB Overflow/Underflow Source GTADTRB Register Buffer Transfer Disable 20 20 read-write 0 Enable GTADTRB register buffer transfer by overflow/underflow #0 1 Disable GTADTRB register buffer transfer by overflow/underflow #1 CPTDV Overflow/Underflow Source GTDVU/GTDVD Register Buffer Transfer Disable 21 21 read-write 0 Enable GTDVU/GTDVD register buffer transfer by overflow/underflow #0 1 Disable GTDVU/GTDVD register buffer transfer by overflow/underflow #1 CP3DB Complementary PWM mode 3,4 Double Buffer select 24 24 read-write 0 Disable double buffer function in complementary PWM mode 3, 4 #0 1 Enable double buffer function in complementary PWM mode 3, 4 #1 CPBTD Complementary PWM mode Buffer Transfer Disable 25 25 read-write 0 Enable buffer transfer from temporary register to GTCCRC and GTPBR register #0 1 Disable buffer transfer from temporary register to GTCCRC and GTPBR register #1 OLTTA GTIOCnA Output Level Buffer Transfer Timing Select 26 27 read-write 00 No transfer #00 01 Triangle waves, complementary PWM mode: Transfer at crest Saw waves: Transfer at the end of period #01 10 Triangle waves, complementary PWM mode: Transfer at trough Saw waves: Transfer by compare match of GTCCRA register #10 11 Triangle waves, complementary PWM mode: Transfer at both crest and trough Saw waves: Setting prohibited #11 OLTTB GTIOCnB Output Level Buffer Transfer Timing Select 28 29 read-write 00 No transfer #00 01 Triangle waves, complementary PWM mode: Transfer at crest Saw waves: Transfer at the end of period #01 10 Triangle waves, complementary PWM mode: Transfer at trough Saw waves: Transfer by compare match of GTCCRB register #10 11 Triangle waves, complementary PWM mode: Transfer at both crest and trough Saw waves: Setting prohibited #11 GTOLBR General PWM Timer Output Level Buffer Register 0xE4 32 read-write 0x00000000 0xffffffff GTIOAB GTIOA buffer bits 0 4 read-write GTIOBB GTIOB buffer bits 16 20 read-write GTICCR General PWM Timer Inter Channel Cooperation Input Capture Control Register 0xEC 32 read-write 0x00000000 0xffffffff ICAFA Forwarding GTCCRA register Compare Match/Input Capture to Other Channel GTCCRA Input Capture Source Enable 0 0 read-write 0 Disable forwarding GTCCRA register compare match/input capture to GTCCRA input capture source of other channels #0 1 Enable forwarding GTCCRA register compare match/input capture to GTCCRA input capture source of other channels #1 ICAFB Forwarding GTCCRB register Compare Match/Input Capture to Other Channel GTCCRA Input Capture Source Enable 1 1 read-write 0 Disable forwarding GTCCRB register compare match/input capture to GTCCRA input capture source of other channels #0 1 Enable forwarding GTCCRB register compare match/input capture to GTCCRA input capture source of other channels #1 ICAFC Forwarding GTCCRC register Compare Match to Other Channel GTCCRA Input Source Capture Enable 2 2 read-write 0 Disable forwarding GTCCRC register compare match to GTCCRA input capture source of other channels #0 1 Enable forwarding GTCCRC register compare match to GTCCRA input capture source of other channels #1 ICAFD Forwarding GTCCRD register Compare Match to Other Channel GTCCRA Input Capture Source Enable 3 3 read-write 0 Disable forwarding GTCCRD register compare match to GTCCRA input capture source of other channels #0 1 Enable forwarding GTCCRD register compare match to GTCCRA input capture source of other channels #1 ICAFE Forwarding GTCCRE register Compare Match to Other Channel GTCCRA Input Capture Source Enable 4 4 read-write 0 Disable forwarding GTCCRE register compare match to GTCCRA input capture source of other channels #0 1 Enable forwarding GTCCRE register compare match to GTCCRA input capture source of other channels #1 ICAFF Forwarding GTCCRF register Compare Match to Other Channel GTCCRA Input Capture Source Enable 5 5 read-write 0 Disable forwarding GTCCRF register compare match to GTCCRA input capture source of other channels #0 1 Enable forwarding GTCCRF register compare match to GTCCRA input capture source of other channels #1 ICAFPO Forwarding Overflow to Other Channel GTCCRA Input Capture Source Enable 6 6 read-write 0 Disable forwarding overflow in saw-waves or the crest in triangle-waves or complementary PWM mode to GTCCRA input capture source of other channels #0 1 Enable forwarding overflow in saw-waves or the crest in triangle-waves or complementary PWM mode to GTCCRA input capture source of other channels #1 ICAFPU Forwarding Underflow to Other Channel GTCCRA Input Capture Source Enable 7 7 read-write 0 Disable forwarding underflow in saw-waves or the trough in triangle-waves or complementary PWM mode to GTCCRA input capture source of other channels #0 1 Enable forwarding underflow in saw-waves or the trough in triangle-waves or complementary PWM mode to GTCCRA input capture source of other channels #1 ICACLK Forwarding Count Clock to Other Channel GTCCRA Input Capture Source Enable 8 8 read-write 0 Disable forwarding count clock to GTCCRA input capture source of other channels #0 1 Enable forwarding count clock to GTCCRA input capture source of other channels #1 ICAGRP GTCCRA Input Capture Group Select 14 15 read-write 00 Select group A #00 01 Select group B #01 10 Select group C #10 11 Select group D #11 ICBFA Forwarding GTCCRA register Compare Match/Input Capture to Other Channel GTCCRB Input Capture Source Enable 16 16 read-write 0 Disable forwarding GTCCRA register compare match/input capture to GTCCRB input capture source of other channels #0 1 Enable forwarding GTCCRA register compare match/input capture to GTCCRB input capture source of other channels #1 ICBFB Forwarding GTCCRB register Compare Match/Input Capture to Other Channel GTCCRB Input Capture Source Enable 17 17 read-write 0 Disable forwarding GTCCRB register compare match/input capture to GTCCRB input capture source of other channels #0 1 Enable forwarding GTCCRB register compare match/input capture to GTCCRB input capture source of other channels #1 ICBFC Forwarding GTCCRC register Compare Match to Other Channel GTCCRB Input Source Capture Enable 18 18 read-write 0 Disable forwarding GTCCRD register compare match to GTCCRB input capture source of other channels #0 1 Enable forwarding GTCCRD register compare match to GTCCRB input capture source of other channels #1 ICBFD Forwarding GTCCRD register Compare Match to Other Channel GTCCRB Input Capture Source Enable 19 19 read-write 0 Disable forwarding GTCCRD register compare match to GTCCRB input capture source of other channels #0 1 Enable forwarding GTCCRD register compare match to GTCCRB input capture source of other channels #1 ICBFE Forwarding GTCCRE register Compare Match to Other Channel GTCCRB Input Capture Source Enable 20 20 read-write 0 Disable forwarding GTCCRE register compare match to GTCCRB input capture source of other channels #0 1 Enable forwarding GTCCRE register compare match to GTCCRB input capture source of other channels #1 ICBFF Forwarding GTCCRF register Compare Match to Other Channel GTCCRB Input Capture Source Enable 21 21 read-write 0 Disable forwarding GTCCRF register compare match to GTCCRB input capture source of other channels #0 1 Enable forwarding GTCCRF register compare match to GTCCRB input capture source of other channels #1 ICBFPO Forwarding Overflow to Other Channel GTCCRB Input Capture Source Enable 22 22 read-write 0 Disable forwarding overflow in saw-waves or the crest in triangle-waves or complementary PWM mode to GTCCRB input capture source of other channels #0 1 Enable forwarding overflow in saw-waves or the crest in triangle-waves or complementary PWM mode to GTCCRB input capture source of other channels #1 ICBFPU Forwarding Underflow to Other Channel GTCCRB Input Capture Source Enable 23 23 read-write 0 Disable forwarding underflow in saw-waves or the trough in triangle-waves or complementary PWM mode to GTCCRB input capture source of other channels #0 1 Enable forwarding underflow in saw-waves or the trough in triangle-waves or complementary PWM mode to GTCCRB input capture source of other channels #1 ICBCLK Forwarding Count Clock to Other Channel GTCCRB Input Capture Source Enable 24 24 read-write 0 Disable forwarding count clock to GTCCRB input capture source of other channels #0 1 Enable forwarding count clock to GTCCRB input capture source of other channels #1 ICBGRP GTCCRB Input Capture Group Select 30 31 read-write 00 Select group A #00 01 Select group B #01 10 Select group C #10 11 Select group D #11 GPT321 General PWM 32-bit Timer 1 0x40169100 GPT322 General PWM 32-bit Timer 2 0x40169200 GPT323 General PWM 32-bit Timer 3 0x40169300 GPT324 General PWM 32-bit Timer 4 0x40169400 0x00 28 registers 0x24 152 registers 0xC0 8 registers 0xD0 8 registers 0xE0 8 registers 0xEC 4 registers GTWP General PWM Timer Write-Protection Register 0x00 32 read-write 0x00000000 0xffffffff WP Register Write Disable 0 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 STRWP GTSTR.CSTRT Bit Write Disable 1 1 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 STPWP GTSTP.CSTOP Bit Write Disable 2 2 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CLRWP GTCLR.CCLR Bit Write Disable 3 3 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CMNWP Common Register Write Disabled 4 4 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 PRKEY GTWP Key Code 8 15 write-only GTSTR General PWM Timer Software Start Register 0x04 32 read-write 0x00000000 0xffffffff CSTRT0 Channel n GTCNT Count Start (n is the same as the bit position value) 0 0 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT1 Channel n GTCNT Count Start (n is the same as the bit position value) 1 1 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT2 Channel n GTCNT Count Start (n is the same as the bit position value) 2 2 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT3 Channel n GTCNT Count Start (n is the same as the bit position value) 3 3 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT4 Channel n GTCNT Count Start (n is the same as the bit position value) 4 4 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT5 Channel n GTCNT Count Start (n is the same as the bit position value) 5 5 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT6 Channel n GTCNT Count Start (n is the same as the bit position value) 6 6 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT7 Channel n GTCNT Count Start (n is the same as the bit position value) 7 7 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT8 Channel n GTCNT Count Start (n is the same as the bit position value) 8 8 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT9 Channel n GTCNT Count Start (n is the same as the bit position value) 9 9 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT10 Channel n GTCNT Count Start (n is the same as the bit position value) 10 10 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT11 Channel n GTCNT Count Start (n is the same as the bit position value) 11 11 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT12 Channel n GTCNT Count Start (n is the same as the bit position value) 12 12 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT13 Channel n GTCNT Count Start (n is the same as the bit position value) 13 13 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT14 Channel n GTCNT Count Start (n is the same as the bit position value) 14 14 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT15 Channel n GTCNT Count Start (n is the same as the bit position value) 15 15 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT16 Channel n GTCNT Count Start (n is the same as the bit position value) 16 16 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT17 Channel n GTCNT Count Start (n is the same as the bit position value) 17 17 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT18 Channel n GTCNT Count Start (n is the same as the bit position value) 18 18 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT19 Channel n GTCNT Count Start (n is the same as the bit position value) 19 19 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT20 Channel n GTCNT Count Start (n is the same as the bit position value) 20 20 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT21 Channel n GTCNT Count Start (n is the same as the bit position value) 21 21 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT22 Channel n GTCNT Count Start (n is the same as the bit position value) 22 22 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT23 Channel n GTCNT Count Start (n is the same as the bit position value) 23 23 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT24 Channel n GTCNT Count Start (n is the same as the bit position value) 24 24 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT25 Channel n GTCNT Count Start (n is the same as the bit position value) 25 25 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT26 Channel n GTCNT Count Start (n is the same as the bit position value) 26 26 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT27 Channel n GTCNT Count Start (n is the same as the bit position value) 27 27 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT28 Channel n GTCNT Count Start (n is the same as the bit position value) 28 28 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT29 Channel n GTCNT Count Start (n is the same as the bit position value) 29 29 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT30 Channel n GTCNT Count Start (n is the same as the bit position value) 30 30 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 CSTRT31 Channel n GTCNT Count Start (n is the same as the bit position value) 31 31 read-write 0 GTCNT counter is not started #0 1 GTCNT counter is started #1 GTSTP General PWM Timer Software Stop Register 0x08 32 read-write 0xffffffff 0xffffffff CSTOP0 Channel n GTCNT Count Stop (n is the same as the bit position value) 0 0 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP1 Channel n GTCNT Count Stop (n is the same as the bit position value) 1 1 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP2 Channel n GTCNT Count Stop (n is the same as the bit position value) 2 2 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP3 Channel n GTCNT Count Stop (n is the same as the bit position value) 3 3 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP4 Channel n GTCNT Count Stop (n is the same as the bit position value) 4 4 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP5 Channel n GTCNT Count Stop (n is the same as the bit position value) 5 5 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP6 Channel n GTCNT Count Stop (n is the same as the bit position value) 6 6 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP7 Channel n GTCNT Count Stop (n is the same as the bit position value) 7 7 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP8 Channel n GTCNT Count Stop (n is the same as the bit position value) 8 8 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP9 Channel n GTCNT Count Stop (n is the same as the bit position value) 9 9 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP10 Channel n GTCNT Count Stop (n is the same as the bit position value) 10 10 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP11 Channel n GTCNT Count Stop (n is the same as the bit position value) 11 11 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP12 Channel n GTCNT Count Stop (n is the same as the bit position value) 12 12 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP13 Channel n GTCNT Count Stop (n is the same as the bit position value) 13 13 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP14 Channel n GTCNT Count Stop (n is the same as the bit position value) 14 14 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP15 Channel n GTCNT Count Stop (n is the same as the bit position value) 15 15 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP16 Channel n GTCNT Count Stop (n is the same as the bit position value) 16 16 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP17 Channel n GTCNT Count Stop (n is the same as the bit position value) 17 17 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP18 Channel n GTCNT Count Stop (n is the same as the bit position value) 18 18 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP19 Channel n GTCNT Count Stop (n is the same as the bit position value) 19 19 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP20 Channel n GTCNT Count Stop (n is the same as the bit position value) 20 20 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP21 Channel n GTCNT Count Stop (n is the same as the bit position value) 21 21 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP22 Channel n GTCNT Count Stop (n is the same as the bit position value) 22 22 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP23 Channel n GTCNT Count Stop (n is the same as the bit position value) 23 23 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP24 Channel n GTCNT Count Stop (n is the same as the bit position value) 24 24 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP25 Channel n GTCNT Count Stop (n is the same as the bit position value) 25 25 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP26 Channel n GTCNT Count Stop (n is the same as the bit position value) 26 26 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP27 Channel n GTCNT Count Stop (n is the same as the bit position value) 27 27 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP28 Channel n GTCNT Count Stop (n is the same as the bit position value) 28 28 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP29 Channel n GTCNT Count Stop (n is the same as the bit position value) 29 29 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP30 Channel n GTCNT Count Stop (n is the same as the bit position value) 30 30 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 CSTOP31 Channel n GTCNT Count Stop (n is the same as the bit position value) 31 31 read-write 0 GTCNT counter is not stopped #0 1 GTCNT counter stopped #1 GTCLR General PWM Timer Software Clear Register 0x0C 32 write-only 0x00000000 0xffffffff CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR10 Channel n GTCNT Count Clear (n : the same as bit position value) 10 10 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR11 Channel n GTCNT Count Clear (n : the same as bit position value) 11 11 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR12 Channel n GTCNT Count Clear (n : the same as bit position value) 12 12 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR13 Channel n GTCNT Count Clear (n : the same as bit position value) 13 13 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR14 Channel n GTCNT Count Clear (n : the same as bit position value) 14 14 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR15 Channel n GTCNT Count Clear (n : the same as bit position value) 15 15 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR16 Channel n GTCNT Count Clear (n : the same as bit position value) 16 16 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR17 Channel n GTCNT Count Clear (n : the same as bit position value) 17 17 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR18 Channel n GTCNT Count Clear (n : the same as bit position value) 18 18 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR19 Channel n GTCNT Count Clear (n : the same as bit position value) 19 19 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR20 Channel n GTCNT Count Clear (n : the same as bit position value) 20 20 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR21 Channel n GTCNT Count Clear (n : the same as bit position value) 21 21 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR22 Channel n GTCNT Count Clear (n : the same as bit position value) 22 22 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR23 Channel n GTCNT Count Clear (n : the same as bit position value) 23 23 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR24 Channel n GTCNT Count Clear (n : the same as bit position value) 24 24 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR25 Channel n GTCNT Count Clear (n : the same as bit position value) 25 25 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR26 Channel n GTCNT Count Clear (n : the same as bit position value) 26 26 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR27 Channel n GTCNT Count Clear (n : the same as bit position value) 27 27 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR28 Channel n GTCNT Count Clear (n : the same as bit position value) 28 28 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR29 Channel n GTCNT Count Clear (n : the same as bit position value) 29 29 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR30 Channel n GTCNT Count Clear (n : the same as bit position value) 30 30 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR31 Channel n GTCNT Count Clear (n : the same as bit position value) 31 31 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write 0x00000000 0xffffffff SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGCR GTETRGC Pin Rising Input Source Counter Start Enable 4 4 read-write 0 Counter start disabled on the rising edge of GTETRGC input #0 1 Counter start enabled on the rising edge of GTETRGC input #1 SSGTRGCF GTETRGC Pin Falling Input Source Counter Start Enable 5 5 read-write 0 Counter start disabled on the falling edge of GTETRGC input #0 1 Counter start enabled on the falling edge of GTETRGC input #1 SSGTRGDR GTETRGD Pin Rising Input Source Counter Start Enable 6 6 read-write 0 Counter start disabled on the rising edge of GTETRGD input #0 1 Counter start enabled on the rising edge of GTETRGD input #1 SSGTRGDF GTETRGD Pin Falling Input Source Counter Start Enable 7 7 read-write 0 Counter start disabled on the falling edge of GTETRGD input #0 1 Counter start enabled on the falling edge of GTETRGD input #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 20 read-write 0 Counter start disabled at the ELC_GPTE input #0 1 Counter start enabled at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 21 read-write 0 Counter start disabled at the ELC_GPTF input #0 1 Counter start enabled at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 22 read-write 0 Counter start disabled at the ELC_GPTG input #0 1 Counter start enabled at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 23 read-write 0 Counter start disabled at the ELC_GPTH input #0 1 Counter start enabled at the ELC_GPTH input #1 CSTRT Software Source Counter Start Enable 31 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write 0x00000000 0xffffffff PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGCR GTETRGC Pin Rising Input Source Counter Stop Enable 4 4 read-write 0 Counter stop disabled on the rising edge of GTETRGC input #0 1 Counter stop enabled on the rising edge of GTETRGC input #1 PSGTRGCF GTETRGC Pin Falling Input Source Counter Stop Enable 5 5 read-write 0 Counter stop disabled on the falling edge of GTETRGC input #0 1 Counter stop enabled on the falling edge of GTETRGC input #1 PSGTRGDR GTETRGD Pin Rising Input Source Counter Stop Enable 6 6 read-write 0 Counter stop disabled on the rising edge of GTETRGD input #0 1 Counter stop enabled on the rising edge of GTETRGD input #1 PSGTRGDF GTETRGD Pin Falling Input Source Counter Stop Enable 7 7 read-write 0 Counter stop disabled on the falling edge of GTETRGD input #0 1 Counter stop enabled on the falling edge of GTETRGD input #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 20 read-write 0 Counter stop disabled at the ELC_GPTE input #0 1 Counter stop enabled at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 21 read-write 0 Counter stop disabled at the ELC_GPTF input #0 1 Counter stop enabled at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 22 read-write 0 Counter stop disabled at the ELC_GPTG input #0 1 Counter stop enabled at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 23 read-write 0 Counter stop disabled at the ELC_GPTH input #0 1 Counter stop enabled at the ELC_GPTH input #1 CSTOP Software Source Counter Stop Enable 31 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write 0x00000000 0xffffffff CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGCR GTETRGC Pin Rising Input Source Counter Clear Enable 4 4 read-write 0 Disable counter clear on the rising edge of GTETRGC input #0 1 Enable counter clear on the rising edge of GTETRGC input #1 CSGTRGCF GTETRGC Pin Falling Input Source Counter Clear Enable 5 5 read-write 0 Counter clear disabled on the falling edge of GTETRGC input #0 1 Counter clear enabled on the falling edge of GTETRGC input #1 CSGTRGDR GTETRGD Pin Rising Input Source Counter Clear Enable 6 6 read-write 0 Disable counter clear on the rising edge of GTETRGD input #0 1 Enable counter clear on the rising edge of GTETRGD input #1 CSGTRGDF GTETRGD Pin Falling Input Source Counter Clear Enable 7 7 read-write 0 Counter clear disabled on the falling edge of GTETRGD input #0 1 Counter clear enabled on the falling edge of GTETRGD input #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 20 read-write 0 Counter clear disabled at the ELC_GPTE input #0 1 Counter clear enabled at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 21 read-write 0 Counter clear disabled at the ELC_GPTF input #0 1 Counter clear enabled at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 22 read-write 0 Counter clear disabled at the ELC_GPTG input #0 1 Counter clear enabled at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 23 read-write 0 Counter clear disabled at the ELC_GPTH input #0 1 Counter clear enabled at the ELC_GPTH input #1 CSCMSC Compare Match/Input Capture/Synchronous counter clearing Source Counter Clear Enable 24 26 read-write 000 Counter clear disabled by Compare match/ Input capture/ Synchronous counter clearing group #000 001 Counter clear enabled at the GTCCRA register compare match/ Input capture #001 010 Counter clear enabled at the GTCCRB register compare match/ Input capture #010 011 Counter clear enabled at the GTCCRC register compare match #011 100 Counter clear enabled at the GTCCRD register compare match #100 101 Counter clear enabled at the GTCCRE register compare match #101 110 Counter clear enabled at the GTCCRF register compare match #110 111 Counter clear enabled at the synchronous counter clearing group #111 CP1CCE Complementary PWM mode1 Crest Source Counter Clear Enable 27 27 read-write 0 Counter clear disabled at the crest of complementary PWM mode1 #0 1 Counter clear enabled at the crest of complementary PWM mode1 #1 CCLR Software Source Counter Clear Enable 31 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write 0x00000000 0xffffffff ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGCR GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable 4 4 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGC input #1 ASGTRGCF GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable 5 5 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGC input #1 ASGTRGDR GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable 6 6 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGD input #1 ASGTRGDF GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable 7 7 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGD input #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 20 read-write 0 GTCCRA input capture disabled at the ELC_GPTE input #0 1 GTCCRA input capture enabled at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 21 read-write 0 GTCCRA input capture disabled at the ELC_GPTF input #0 1 GTCCRA input capture enabled at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 22 read-write 0 GTCCRA input capture disabled at the ELC_GPTG input #0 1 GTCCRA input capture enabled at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 23 read-write 0 GTCCRA input capture disabled at the ELC_GPTH input #0 1 GTCCRA input capture enabled at the ELC_GPTH input #1 ASOC Other channel Source GTCCRA Input Capture Enable 24 24 read-write 0 Disables GTCCRA input capture by other channel factor #0 1 Enables GTCCRA input capture by other channel factor #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write 0x00000000 0xffffffff BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGCR GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable 4 4 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGC input #1 BSGTRGCF GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable 5 5 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGC input #1 BSGTRGDR GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable 6 6 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGD input #1 BSGTRGDF GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable 7 7 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGD input #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 20 read-write 0 GTCCRB input capture disabled at the ELC_GPTE input #0 1 GTCCRB input capture enabled at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 21 read-write 0 GTCCRB input capture disabled at the ELC_GPTF input #0 1 GTCCRB input capture enabled at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 22 read-write 0 GTCCRB input capture disabled at the ELC_GPTG input #0 1 GTCCRB input capture enabled at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 23 read-write 0 GTCCRB input capture disabled at the ELC_GPTH input #0 1 GTCCRB input capture enabled at the ELC_GPTH input #1 BSOC Other channel Source GTCCRB Input Capture Enable 24 24 read-write 0 Disables GTCCRB input capture by other channel factor #0 1 Enables GTCCRB input capture by other channel factor #1 GTCR General PWM Timer Control Register 0x2C 32 read-write 0x00000000 0xffffffff CST Count Start 0 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 ICDS Input Capture Operation Select During Count Stop 8 8 read-write 0 Input capture is operated during count stop. #0 1 Input capture is not operated during count stop. #1 SCGTIOC GTIOC input Source Synchronous Clear Enable 9 9 read-write 0 Disables to use the counter clear by GTIOC input as the clear factor for other channels #0 1 Enables to use the counter clear by GTIOC input as the clear factor for other channels #1 SSCGRP Synchronous Set/Clear Group Select 10 11 read-write 00 Select synchronous set/clear group A #00 01 Select synchronous set/clear group B #01 10 Select synchronous set/clear group C #10 11 Select synchronous set/clear group D #11 CPSCD Complementary PWM Mode Synchronous Clear Disable 12 12 read-write 0 Enable synchronous counter clear by other channel other than the section of trough in complementary PWM mode #0 1 Disable synchronous counter clear by other channel other than the section of trough in complementary PWM mode #1 SSCEN Synchronous Set/Clear Enable 15 15 read-write 0 Disable Synchronous set/clear of the GTCNT counter #0 1 Enable Synchronous set/clear of the GTCNT counter #1 MD Mode Select 16 19 read-write 0000 Saw-wave PWM mode 1(single buffer or double buffer possible) #0000 0001 Saw-wave one-shot pulse mode (fixed buffer operation) #0001 0010 Saw-wave PWM mode 2(single buffer or double buffer possible) #0010 0011 Setting prohibited #0011 0100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer possible) #0100 0101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer possible) #0101 0110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #0110 0111 Setting prohibited #0111 1000 Setting prohibited #1000 1001 Setting prohibited #1001 1010 Setting prohibited #1010 1011 Setting prohibited #1011 1100 Complementary PWM mode 1(transfer at crest) #1100 1101 Complementary PWM mode 2(transfer at trough) #1101 1110 Complementary PWM mode 3(transfer at crest and trough) #1110 1111 Complementary PWM mode 4(immediate transfer) #1111 TPCS Timer Prescaler Select 23 26 read-write 0000 GTCLK/1 #0000 0001 GTCLK/2 #0001 0010 GTCLK/4 #0010 0011 GTCLK/8 #0011 0100 GTCLK/16 #0100 0101 GTCLK/32 #0101 0110 GTCLK/64 #0110 0111 GTCLK/128 #0111 1000 GTCLK/256 #1000 1001 GTCLK/512 #1001 1010 GTCLK/1024 #1010 1011 Setting prohibited #1011 1100 GTETRGA (Via the POEG) #1100 1101 GTETRGB (Via the POEG) #1101 1110 GTETRGC (Via the POEG) #1110 1111 GTETRGD (Via the POEG)POEG接続数に応じた、GTETRGA-D表示制御必要。 #1111 CKEG Clock Edge Select 27 28 read-write 00 Select rising edge of GTETRG for clock count #00 01 Select falling edge of GTETRG for clock count #01 Others Select both edge of GTETRG for clock count true GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write 0x00000001 0xffffffff UD Count Direction Setting 0 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTY GTIOCnA Output Duty Setting 16 17 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 19 read-write 0 The function selected by the GTIOA[3:2] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting. #0 1 The function selected by the GTIOA[3:2] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting. #1 OBDTY GTIOCnB Output Duty Setting 24 25 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 27 read-write 0 The function selected by the GTIOB[3:2] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting. #0 1 The function selected by the GTIOB[3:2] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting. #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write 0x00000000 0xffffffff GTIOA GTIOCnA Pin Function Select 0 4 read-write CPSCIR Complementary PWM Mode Initial Output at Synchronous Clear Disable 5 5 read-write 0 Output the initial value set by the GTIOR.GTIOA and GTIOB bits when synchronous clear occurs in Trough section of complementary PWM mode #0 1 Disable output the initial value #1 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OAE GTIOCnA Pin Output Enable 8 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OADF GTIOCnA Pin Disable Value Setting 9 10 read-write 00 None of the below options are specified #00 01 GTIOCnA pin is set to Hi-Z in response to controlling the output negation #01 10 GTIOCnA pin is set to 0 in response to controlling the output negation #10 11 GTIOCnA pin is set to 1 in response to controlling the output negation #11 OAEOCD GTCCRA Compare Match Cycle End Output Invalidate 11 11 read-write 0 Validate GTIOA[3:2] setting #0 1 Invalidate GTIOA[3:2] setting (GTIOCnA pin output is retained) #1 PSYE PWM Synchronous output Enable 12 12 read-write 0 Disable GTCPPOm pin output #0 1 Enable GTCPPOm pin output #1 NFAEN Noise Filter A Enable 13 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 15 read-write 00 GTCLK/1 #00 01 GTCLK/4 #01 10 GTCLK/16 #10 11 GTCLK/64 #11 GTIOB GTIOCnB Pin Function Select 16 20 read-write OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 OBE GTIOCnB Pin Output Enable 24 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBDF GTIOCnB Pin Disable Value Setting 25 26 read-write 00 None of the below options are specified #00 01 GTIOCnB pin is set to Hi-Z in response to controlling the output negation #01 10 GTIOCnB pin is set to 0 in response to controlling the output negation #10 11 GTIOCnB pin is set to 1 in response to controlling the output negation #11 OBEOCD GTCCRB Compare Match Cycle End Output Invalidate 27 27 read-write 0 When Saw-wave PWM mode 1, validate GTIOB[3:2] setting When Saw-wave PWM mode 2, validate GTIOA[3:2] setting #0 1 When Saw-wave PWM mode 1, invalidate GTIOB[3:2] setting (GTIOCnB pin output is retained) When Saw-wave PWM mode 2, invalidate GTIOA[3:2] setting (GTIOCnA pin output is retained) #1 NFBEN Noise Filter B Enable 29 29 read-write 0 The noise filter for the GTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSB Noise Filter B Sampling Clock Select 30 31 read-write 00 GTCLK/1 #00 01 GTCLK/4 #01 10 GTCLK/16 #10 11 GTCLK/64 #11 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write 0x00000000 0xffffffff SCFA GTCCRA Register Compare Match/Input Capture Source Synchronous Clear Enable 8 8 read-write 0 Disable use of GTCCRA register compare match/input capture as a clear factor for other channels. #0 1 Enable use of GTCCRA register compare match/input capture as a clear factor for other channels. #1 SCFB GTCCRB Register Compare Match/Input Capture Source Synchronous Clear Enable 9 9 read-write 0 Disable use of GTCCRB register compare match/input capture as a clear factor for other channels. #0 1 Enable use of GTCCRB register compare match/input capture as a clear factor for other channels. #1 SCFC GTCCRC Register Compare Match Source Synchronous Clear Enable 10 10 read-write 0 Disable use of GTCCRC register compare match as a clear factor for other channels. #0 1 Enable use of GTCCRC register compare match as a clear factor for other channels. #1 SCFD GTCCRD Register Compare Match Source Synchronous Clear Enable 11 11 read-write 0 Disable use of GTCCRD register compare match as a clear factor for other channels. #0 1 Enable use of GTCCRD register compare match as a clear factor for other channels. #1 SCFE GTCCRE Register Compare Match Source Synchronous Clear Enable 12 12 read-write 0 Disable use of GTCCRE register compare match as a clear factor for other channels. #0 1 Enable use of GTCCRE register compare match as a clear factor for other channels #1 SCFF GTCCRF Register Compare Match Source Synchronous Clear Enable 13 13 read-write 0 Disable use of GTCCRF register compare match as a clear factor for other channels. #0 1 Enable use of GTCCRF register compare match as a clear factor for other channels #1 SCFPO Overflow Source Synchronous Clear Enable 14 14 read-write 0 Disable use of overflow as a clear factor for other channels. #0 1 Enable use of overflow as a clear factor for other channels. #1 SCFPU Underflow Source Synchronous Clear Enable 15 15 read-write 0 Disable use of underflow as a clear factor for other channels #0 1 Enable use of underflow as a clear factor for other channels #1 ADTRAUEN GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Enable 16 16 read-write 0 A/D conversion start request is disabled. #0 1 A/D conversion start request is enabled. #1 ADTRADEN GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Enable 17 17 read-write 0 A/D conversion start request is disabled. #0 1 A/D conversion start request is enabled. #1 ADTRBUEN GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Enable 18 18 read-write 0 A/D conversion start request is disabled. #0 1 A/D conversion start request is enabled. #1 ADTRBDEN GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Enable 19 19 read-write 0 A/D conversion start request is disabled. #0 1 A/D conversion start request is enabled. #1 GRP Output Disable Source Select 24 25 read-write 00 Group A output disable source is selected Group B output disable source is selected Group C output disable source is selected Group D output disable source is selected #00 GRPDTE Dead Time Error Output Disable Request Enable 28 28 read-write 0 Dead time error output disable request is disabled. #0 1 Dead time error output disable request is enabled. #1 GRPABH Same Time Output Level High Disable Request Enable 29 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTST General PWM Timer Status Register 0x3C 32 read-write 0x00008000 0xffffffff TCFA Input Capture/Compare Match Flag A 0 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 ITCNT GPTn_OVF/GPTn_UDF Interrupt Skipping Count Counter 8 10 read-only TUCF Count Direction Flag 15 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 ADTRAUF GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag 16 16 read-write 0 No GTADTRA register compare match has occurred in up-counting. #0 1 A GTADTRA register compare match has occurred in up-counting. #1 ADTRADF GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag 17 17 read-write 0 No GTADTRA register compare match has occurred in down-counting. #0 1 A GTADTRA register compare match has occurred in down-counting. #1 ADTRBUF GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag 18 18 read-write 0 No GTADTRB register compare match has occurred in up-counting. #0 1 A GTADTRB register compare match has occurred in up-counting. #1 ADTRBDF GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag 19 19 read-write 0 No GTADTRB register compare match has occurred in down-counting. #0 1 A GTADTRB register compare match has occurred in down-counting. #1 ODF Output Disable Flag 24 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 DTEF Dead Time Error Flag 28 28 read-only 0 No dead time error has occurred. #0 1 A dead time error has occurred. #1 OABHF Same Time Output Level High Flag 29 29 read-only 0 No simultaneous generation of 1 both for the GTIOCA and GTIOCB pins has occurred. #0 1 A simultaneous generation of 1 both for the GTIOCA and GTIOCB pins has occurred. #1 OABLF Same Time Output Level Low Flag 30 30 read-only 0 No simultaneous generation of 0 both for the GTIOCA and GTIOCB pins has occurred. #0 1 A simultaneous generation of 0 both for the GTIOCA and GTIOCB pins has occurred. #1 PCF Period Count Function Finish Flag 31 31 read-write 0 No period count function finish has occurred #0 1 A period count function finish has occurred #1 GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write 0x00000000 0xffffffff BD0 GTCCR Buffer Operation Disable 0 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD2 GTADTRA/GTADTRB Registers Buffer Operation Disable 2 2 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD3 GTDVU/GTDVD Registers Buffer Operation Disable 3 3 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 DBRTECA GTCCRA Register Double Buffer Repeat Operation Enable 8 8 read-write 0 GTCCRA register double buffer repeat operation is disabled #0 1 GTCCRA register double buffer repeat operation is enabled #1 DBRTECB GTCCRB Register Double Buffer Repeat Operation Enable 10 10 read-write 0 GTCCRB register double buffer repeat operation is disabled #0 1 GTCCRB register double buffer repeat operation is enabled #1 CCRA GTCCRA Buffer Operation 16 17 read-write 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) true CCRB GTCCRB Buffer Operation 18 19 read-write 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) true PR GTPR Buffer Operation 20 21 read-write 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 Others Double buffer operation (GTPDBR --> GTPBR --> GTPR) true CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 22 write-only ADTTA GTADTRA Register Buffer Transfer Timing Select 24 25 read-write 00 In triangle wave or complementary PWM mode, no transfer. In saw-wave mode, no transfer. #00 01 In triangle wave or complementary PWM mode, transfer at crest. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing. #01 10 In triangle wave or complementary PWM mode, transfer at trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing. #10 11 In triangle wave or complementary PWM mode, transfer at both crest and trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing. #11 ADTDA GTADTRA Register Double Buffer Operation 26 26 read-write 0 Single buffer operation (GTADTBRA --> GTADTRA) #0 1 Double buffer operation (GTADTDBRA --> GTADTBRA --> GTADTRA) #1 ADTTB GTADTRB Register Buffer Transfer Timing Select 28 29 read-write 00 In triangle wave or complementary PWM mode, no transfer. In saw-wave mode, no transfer. #00 01 In triangle wave or complementary PWM mode, transfer at crest. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing. #01 10 In triangle wave or complementary PWM mode, transfer at trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing. #10 11 In triangle wave or complementary PWM mode, transfer at both crest and trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing. #11 ADTDB GTADTRB Register Double Buffer Operation 30 30 read-write 0 Single buffer operation (GTADTBRB --> GTADTRB) #0 1 Double buffer operation (GTADTDBRB --> GTADTBRB --> GTADTRB) #1 GTITC General PWM Timer Interrupt and A/D Conversion Start Request Skipping Setting Register 0x44 32 read-write 0x00000000 0xffffffff ITLA GTCCRA Register Compare Match/Input Capture Interrupt Link 0 0 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 ITLB GTCCRB Register Compare Match/Input Capture Interrupt Link 1 1 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 ITLC GTCCRC Register Compare Match Interrupt Link 2 2 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 ITLD GTCCRD Register Compare Match Interrupt Link 3 3 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 ITLE GTCCRE Register Compare Match Interrupt Link 4 4 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 ITLF GTCCRF Register Compare Match Interrupt Link 5 5 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 IVTC GPTn_OVF/GPTn_UDF Interrupt Skipping Function Select 6 7 read-write 00 Skipping is not performed. #00 01 Both overflow and underflow for saw waves and crest for triangle waves and complementary PWM mode are counted and skipped. #01 10 Both overflow and underflow for saw waves and trough for triangle waves and complementary PWM mode are counted and skipped. #10 11 Both overflow and underflow for saw waves and both crest and trough for triangle waves and complementary PWM mode are counted and skipped. #11 IVTT GPTn_OVF/GPTn_UDF Interrupt Skipping Count Select 8 10 read-write 000 Skipping is not performed #000 001 Skipping count of 1 #001 010 Skipping count of 2 #010 011 Skipping count of 3 #011 100 Skipping count of 4 #100 101 Skipping count of 5 #101 110 Skipping count of 6 #110 111 Skipping count of 7 #111 ADTAL GTADTRA Register A/D Conversion Start Request Link 12 12 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 ADTBL GTADTRB Register A/D Conversion Start Request Link 14 14 read-write 0 Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #0 1 Linked with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 GTCNT General PWM Timer Counter 0x48 32 read-write 0x00000000 0xffffffff GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write 0xffffffff 0xffffffff GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write 0xffffffff 0xffffffff GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write 0xffffffff 0xffffffff GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write 0xffffffff 0xffffffff GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write 0xffffffff 0xffffffff GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write 0xffffffff 0xffffffff GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write 0xffffffff 0xffffffff GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write 0xffffffff 0xffffffff GTPDBR General PWM Timer Cycle Setting Double-Buffer Register 0x6C 32 read-write 0xffffffff 0xffffffff GTADTRA A/D Conversion Start Request Timing Register A 0x70 32 read-write 0xffffffff 0xffffffff GTADTBRA A/D Conversion Start Request Timing Buffer Register A 0x74 32 read-write 0xffffffff 0xffffffff GTADTDBRA A/D Conversion Start Request Timing Double-Buffer Register A 0x78 32 read-write 0xffffffff 0xffffffff GTADTRB A/D Conversion Start Request Timing Register B 0x7C 32 read-write 0xffffffff 0xffffffff GTADTBRB A/D Conversion Start Request Timing Buffer Register B 0x80 32 read-write 0xffffffff 0xffffffff GTADTDBRB A/D Conversion Start Request Timing Double-Buffer Register B 0x84 32 read-write 0xffffffff 0xffffffff GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write 0x00000000 0xffffffff TDE Negative-Phase Waveform Setting 0 0 read-write 0 GTCCRB is set without using GTDVU and GTDVD #0 1 GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB #1 TDBUE GTDVU Register Buffer Operation Enable 4 4 read-write 0 GTDVU register buffer operation is disabled #0 1 GTDVU register buffer operation is enabled #1 TDBDE GTDVD Register Buffer Operation Enable 5 5 read-write 0 GTDVD register buffer operation is disabled #0 1 GTDVD register buffer operation is enabled #1 TDFER GTDVD Register Setting 8 8 read-write 0 GTDVU and GTDVD registers are set separately. #0 1 The value written to GTDVU register is automatically set to GTDVD register. #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write 0xffffffff 0xffffffff GTDVD General PWM Timer Dead Time Value Register D 0x90 32 read-write 0xffffffff 0xffffffff GTDBU General PWM Timer Dead Time Buffer Register U 0x94 32 read-write 0xffffffff 0xffffffff GTDBD General PWM Timer Dead Time Buffer Register D 0x98 32 read-write 0xffffffff 0xffffffff GTSOS General PWM Timer Output Protection Function Status Register 0x9C 32 read-only 0x00000000 0xffffffff SOS Output Protection Function Status 0 1 read-only 00 Normal operation #00 01 Protected state (GTCCRA = 0 is set during transfer at trough or crest) #01 10 Protected state (GTCCRA ≥ GTPR is set during transfer at trough) #10 11 Protected state (GTCCRA ≥ GTPR is set during transfer at crest) #11 GTSOTR General PWM Timer Output Protection Function Temporary Release Register 0xA0 32 read-write 0x00000000 0xffffffff SOTR Output Protection Function Temporary Release 0 0 read-write 0 Protected state is not released #0 1 Protected state is released #1 GTADSMR General PWM Timer A/D Conversion Start Request Signal Monitoring Register 0xA4 32 read-write 0x00000000 0xffffffff ADSMS0 A/D Conversion Start Request Signal Monitor 0 Selection 0 1 read-write 00 A/D conversion start request signal generated by the GTADTRA register during up-counting. #00 01 A/D conversion start request signal generated by the GTADTRA register during down-counting. #01 10 A/D conversion start request signal generated by the GTADTRB register during up-counting. #10 11 A/D conversion start request signal generated by the GTADTRB register during down-counting. #11 ADSMEN0 A/D Conversion Start Request Signal Monitor 0 Output Enabling 8 8 read-write 0 Output of A/D conversion start request signal monitor 0 is disabled. #0 1 Output of A/D conversion start request signal monitor 0 is enabled. #1 ADSMS1 A/D Conversion Start Request Signal Monitor 1 Selection 16 17 read-write 00 A/D conversion start request signal generated by the GTADTRA register during up-counting. #00 01 A/D conversion start request signal generated by the GTADTRA register during down-counting. #01 10 A/D conversion start request signal generated by the GTADTRB register during up-counting. #10 11 A/D conversion start request signal generated by the GTADTRB register during down-counting. #11 ADSMEN1 A/D Conversion Start Request Signal Monitor 1 Output Enabling 24 24 read-write 0 Output of A/D conversion start request signal monitor 1 is disabled. #0 1 Output of A/D conversion start request signal monitor 1 is enabled. #1 GTEITC General PWM Timer Extended Interrupt Skipping Counter Control Register 0xA8 32 read-write 0x00000000 0xffffffff EIVTC1 Extended Interrupt Skipping Counter 1 Count Source Select 0 1 read-write 00 Not counted (not skipped) #00 01 Counting both at overflow or underflow in saw-wave mode, and counting crests in triangle-wave mode or complementary PWM mode #01 10 Counting both at overflow or underflow in saw-wave mode, and counting troughs in triangle-wave mode or complementary PWM mode #10 11 Counting both at overflow or underflow in saw-wave mode, and counting both crests and troughs in triangle-wave mode or complementary PWM mode #11 EIVTT1 Extended Interrupt Skipping 1 Skipping Count Setting 4 7 read-write EITCNT1 Extended Interrupt Skipping Counter 1 12 15 read-only EIVTC2 Extended Interrupt Skipping Counter 2 Count Source select 16 17 read-write 00 Not counted (not skipped) #00 01 Counting both at overflow or underflow in saw-wave mode, and counting crests in triangle-wave mode or complementary PWM mode #01 10 Counting both at overflow or underflow in saw-wave mode, and counting troughs in triangle-wave mode or complementary PWM mode #10 11 Counting both at overflow or underflow in saw-wave mode, and counting both crests and troughs in triangle-wave mode or complementary PWM mode #11 EIVTT2 Extended Interrupt Skipping 2 Skipping Count Setting 20 23 read-write EITCNT2IV Extended Interrupt Skipping Counter 2 Initial Value 24 27 read-write EITCNT2 Extended Interrupt Skipping Counter 2 28 31 read-only GTEITLI1 General PWM Timer Extended Interrupt Skipping Setting Register 1 0xAC 32 read-write 0x00000000 0xffffffff EITLA GTCCRA Register Compare Match/Input Capture Interrupt Extended Skipping Function Select 0 2 read-write EITLB GTCCRB Register Compare Match/Input Capture Interrupt Extended Skipping Function Select 4 6 read-write EITLC GTCCRC Register Compare Match Interrupt Extended Skipping Function Select 8 10 read-write EITLD GTCCRD Register Compare Match Interrupt Extended Skipping Function Select 12 14 read-write EITLE GTCCRE Register Compare Match Interrupt Extended Skipping Function Select 16 18 read-write EITLF GTCCRF Register Compare Match Interrupt Extended Skipping Function Select 20 22 read-write EITLV Overflow Interrupt Extended Skipping Function Select 24 26 read-write EITLU Underflow Interrupt Extended Skipping Function Select 28 30 read-write GTEITLI2 General PWM Timer Extended Interrupt Skipping Setting Register 2 0xB0 32 read-write 0x00000000 0xffffffff EADTAL GTADTRA Register A/D Conversion Start Request Extended Skipping Function Select 0 2 read-write EADTBL GTADTRB Register A/D Conversion Start Request Extended Skipping Function Select 4 6 read-write GTEITLB General PWM Timer Extended Buffer Transfer Skipping Setting Register 0xB4 32 read-write 0x00000000 0xffffffff EBTLCA GTCCRA Register Buffer Transfer Extended Skipping Function Select 0 2 read-write EBTLCB GTCCRB Register Buffer Transfer Extended Skipping Function Select 4 6 read-write EBTLPR GTPR Register Buffer Transfer Extended Skipping Function Select 8 10 read-write EBTLADA GTADTRA Register Buffer Transfer Extended Skipping Function Select 16 18 read-write EBTLADB GTADTRB Register Buffer Transfer Extended Skipping Function Select 20 22 read-write EBTLDVU GTDVU Register Buffer Transfer Extended Skipping Function Select 24 26 read-write EBTLDVD GTDVD Register Buffer Transfer Extended Skipping Function Select 28 30 read-write GTICLF General PWM Timer Inter Channel Logical Operation Function Setting Register 0xB8 32 read-write 0x00000000 0xffffffff ICLFA GTIOCnA Output Logical Operation Function Select 0 2 read-write 000 A (no delay) #000 001 NOT A (no delay) #001 010 C (1GTCLK delay) #010 011 NOT C (1GTCLK delay) #011 100 A AND C (1GTCLK delay) #100 101 A OR C (1GTCLK delay) #101 110 A EXOR C (1GTCLK delay) #110 111 A NOR C (1GTCLK delay) #111 ICLFSELC Inter Channel Signal C Select 4 9 read-write ICLFB GTIOCnB Output Logical Operation Function Select 16 18 read-write 000 B (no delay) #000 001 NOT B (no delay) #001 010 D (1GTCLK delay) #010 011 NOT D (1GTCLK delay) #011 100 B AND D (1GTCLK delay) #100 101 B OR D (1GTCLK delay) #101 110 B EXOR D (1GTCLK delay) #110 111 B NOR D (1GTCLK delay) #111 ICLFSELD Inter Channel Signal D Select 20 25 read-write GTADCMSC General PWM Timer A/D Conversion Start Request Compare Match Skipping Control Register 0xC0 32 read-write 0x00000000 0xffffffff ADCMSC1 A/D Conversion Start Request Compare Match Skipping Counter 1 Count Source Select 0 1 read-write 00 Not counted (not skipped) #00 01 Counting GTADTRA register compare match #01 10 Counting GTADTRB register compare match #10 11 Counting both GTADTRA register compare match and GTADTRB register compare match #11 ADCMST1 A/D Conversion Start Request Compare Match Skipping 1 Skipping Count Setting 4 7 read-write ADCMSCNT1IV A/D Conversion Start Request Compare Match Skipping Counter 1 Initial Value 8 11 read-write ADCMSCNT1 A/D Conversion Start Request Compare Match Skipping Counter 1 12 15 read-only ADCMSC2 A/D Conversion Start Request Compare Match Skipping Counter 2 Count Source Select 16 17 read-write 00 Not counted (not skipped) #00 01 Counting GTADTRA register compare match #01 10 Counting GTADTRB register compare match #10 11 Counting both GTADTRA register compare match and GTADTRB register compare match #11 ADCMST2 A/D Conversion Start Request Compare Match Skipping 2 Skipping Count Setting 20 23 read-write ADCMSCNT2IV A/D Conversion Start Request Compare Match Skipping Counter 2 Initial Value 24 27 read-write ADCMSCNT2 A/D Conversion Start Request Compare Match Skipping Counter 2 28 31 read-only GTADCMSS General PWM Timer A/D Conversion Start Request Compare Match Skipping Setting Register 0xC4 32 read-write 0x00000000 0xffffffff ADCMSAL GTADTRA Register A/D Conversion Start Request Compare Match Skipping Function Select 0 2 read-write ADCMSBL GTADTRB Register A/D Conversion Start Request Compare Match Skipping Function Select 4 6 read-write ADCMBSA GTADTRA Register Buffer Transfer by A/D Conversion Start Request Compare Match Skipping Function Select 16 18 read-write ADCMBSB GTADTRB Register Buffer Transfer by A/D Conversion Start Request Compare Match Skipping Function Select 20 22 read-write GTSECSR General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register 0xD0 32 read-write 0x00000000 0xffffffff SECSEL0 Channel 0 Operation Enable Bit Simultaneous Control Channel Select 0 0 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL1 Channel 1 Operation Enable Bit Simultaneous Control Channel Select 1 1 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL2 Channel 2 Operation Enable Bit Simultaneous Control Channel Select 2 2 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL3 Channel 3 Operation Enable Bit Simultaneous Control Channel Select 3 3 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL4 Channel 4 Operation Enable Bit Simultaneous Control Channel Select 4 4 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL5 Channel 5 Operation Enable Bit Simultaneous Control Channel Select 5 5 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL6 Channel 6 Operation Enable Bit Simultaneous Control Channel Select 6 6 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL7 Channel 7 Operation Enable Bit Simultaneous Control Channel Select 7 7 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL8 Channel 8 Operation Enable Bit Simultaneous Control Channel Select 8 8 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL9 Channel 9 Operation Enable Bit Simultaneous Control Channel Select 9 9 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 GTSECR General PWM Timer Operation Enable Bit Simultaneous Control Register 0xD4 32 read-write 0x00000000 0xffffffff SBDCE GTCCR Register Buffer Operation Simultaneous Enable 0 0 read-write 0 Disable simultaneous enabling GTCCR buffer operations #0 1 Enable GTCCR register buffer operations simultaneously #1 SBDPE GTPR Register Buffer Operation Simultaneous Enable 1 1 read-write 0 Disable simultaneous enabling GTPR buffer operations #0 1 Enable GTPR register buffer operations simultaneously #1 SBDAE GTADTR Register Buffer Operation Simultaneous Enable 2 2 read-write 0 Disable simultaneous enabling GTADTR buffer operations #0 1 Enable GTADTR register buffer operations simultaneously #1 SBDDE GTDV Register Buffer Operation Simultaneous Enable 3 3 read-write 0 Disable simultaneous enabling GTDV buffer operations #0 1 Enable GTDV register buffer operations simultaneously #1 SBDCD GTCCR Register Buffer Operation Simultaneous Disable 8 8 read-write 0 Disable simultaneous disabling GTCCR buffer operations #0 1 Disable GTCCR register buffer operations simultaneously #1 SBDPD GTPR Register Buffer Operation Simultaneous Disable 9 9 read-write 0 Disable simultaneous disabling GTPR buffer operations #0 1 Disable GTPR register buffer operations simultaneously #1 SBDAD GTADTR Register Buffer Operation Simultaneous Disable 10 10 read-write 0 Disable simultaneous disabling GTADTR buffer operations #0 1 Disable GTADTR register buffer operations simultaneously #1 SBDDD GTDV Register Buffer Operation Simultaneous Disable 11 11 read-write 0 Disable simultaneous disabling GTDV buffer operations #0 1 Disable GTDV register buffer operations simultaneously #1 SPCE Period Count Function Simultaneous Enable 16 16 read-write 0 Disable simultaneous enabling period count function #0 1 Enable period count function simultaneously #1 SSCE Synchronous Set/Clear Simultaneous Enable 17 17 read-write 0 Disable simultaneous enabling synchronous set/clear #0 1 Enable synchronous set/clear simultaneously #1 SPCD Period Count Function Simultaneous Disable 24 24 read-write 0 Disable simultaneous disabling period count function #0 1 Disable period count function simultaneously #1 SSCD Synchronous Set/Clear Simultaneous Disable 25 25 read-write 0 Disable simultaneous disabling synchronous set/clear #0 1 Disable synchronous set/clear simultaneously #1 GTBER2 General PWM Timer Buffer Enable Register 2 0xE0 32 read-write 0x00000000 0xffffffff CCTCA Counter Clear Source GTCCRA Register Buffer Transfer Disable 0 0 read-write 0 Enable GTCCRA register buffer transfer by counter clear #0 1 Disable GTCCRA register buffer transfer by counter clear #1 CCTCB Counter Clear Source GTCCRB Register Buffer Transfer Disable 1 1 read-write 0 Enable GTCCRB register buffer transfer by counter clear #0 1 Disable GTCCRB register buffer transfer by counter clear #1 CCTPR Counter Clear Source GTPR Register Buffer Transfer Disable 2 2 read-write 0 Enable GTPR register buffer transfer by counter clear #0 1 Disable GTPR register buffer transfer by counter clear #1 CCTADA Counter Clear Source GTADTRA Register Buffer Transfer Disable 3 3 read-write 0 Enable GTADTRA register buffer transfer by counter clear #0 1 Disable GTADTRA register buffer transfer by counter clear #1 CCTADB Counter Clear Source GTADTRB Register Buffer Transfer Disable 4 4 read-write 0 Enable GTADTRB register buffer transfer by counter clear #0 1 Disable GTADTRB register buffer transfer by counter clear #1 CCTDV Counter Clear Source GTDVU/GTDVD Register Buffer Transfer Disable 5 5 read-write 0 Enable GTDVU/GTDVD register buffer transfer by counter clear #0 1 Disable GTDVU/GTDVD register buffer transfer by counter clear #1 CMTCA Compare Match Source GTCCRA Register Buffer Transfer Enable 8 9 read-write 00 Disable GTCCRA register Buffer Transfer by compare match of GTCCRA register and GTCCRB register #00 01 Enable GTCCRA register Buffer Transfer by compare match of GTCCRA register #01 10 Enable GTCCRA register Buffer Transfer by compare match of GTCCRB register #10 11 Enable GTCCRA register Buffer Transfer by compare match of GTCCRA register and GTCCRB register #11 CMTCB Compare Match Source GTCCRB Register Buffer Transfer Enable 10 11 read-write 00 Disable GTCCRB register Buffer Transfer by compare match of GTCCRA register and GTCCRB register #00 01 Enable GTCCRB register Buffer Transfer by compare match of GTCCRA register #01 10 Enable GTCCRB register Buffer Transfer by compare match of GTCCRB register #10 11 Enable GTCCRB register Buffer Transfer by compare match of GTCCRA register and GTCCRB register #11 CMTADA Compare Match Source GTADTRA Register Buffer Transfer Enable 13 13 read-write 0 Disable GTADTRA register buffer transfer by compare match of GTADTRA register #0 1 Enable GTADTRA register buffer transfer by compare match of GTADTRA register #1 CMTADB Compare Match Source GTADTRB Register Buffer Transfer Enable 14 14 read-write 0 Disable GTADTRB register buffer transfer by compare match of GTADTRB register #0 1 Enable GTADTRB register buffer transfer by compare match of GTADTRB register #1 CPTCA Overflow/Underflow Source GTCCRA Register Buffer Transfer Disable 16 16 read-write 0 Enable GTCCRA register buffer transfer by overflow/underflow #0 1 Disable GTCCRA register buffer transfer by overflow/underflow #1 CPTCB Overflow/Underflow Source GTCCRB Register Buffer Transfer Disable 17 17 read-write 0 Enable GTCCRB register buffer transfer by overflow/underflow #0 1 Disable GTCCRB register buffer transfer by overflow/underflow #1 CPTPR Overflow/Underflow Source GTPR Register Buffer Transfer Disable 18 18 read-write 0 Enable GTPR register buffer transfer by overflow/underflow #0 1 Disable GTPR register buffer transfer by overflow/underflow #1 CPTADA Overflow/Underflow Source GTADTRA Register Buffer Transfer Disable 19 19 read-write 0 Enable GTADTRA register buffer transfer by overflow/underflow #0 1 Disable GTADTRA register buffer transfer by overflow/underflow #1 CPTADB Overflow/Underflow Source GTADTRB Register Buffer Transfer Disable 20 20 read-write 0 Enable GTADTRB register buffer transfer by overflow/underflow #0 1 Disable GTADTRB register buffer transfer by overflow/underflow #1 CPTDV Overflow/Underflow Source GTDVU/GTDVD Register Buffer Transfer Disable 21 21 read-write 0 Enable GTDVU/GTDVD register buffer transfer by overflow/underflow #0 1 Disable GTDVU/GTDVD register buffer transfer by overflow/underflow #1 CP3DB Complementary PWM mode 3,4 Double Buffer select 24 24 read-write 0 Disable double buffer function in complementary PWM mode 3, 4 #0 1 Enable double buffer function in complementary PWM mode 3, 4 #1 CPBTD Complementary PWM mode Buffer Transfer Disable 25 25 read-write 0 Enable buffer transfer from temporary register to GTCCRC and GTPBR register #0 1 Disable buffer transfer from temporary register to GTCCRC and GTPBR register #1 OLTTA GTIOCnA Output Level Buffer Transfer Timing Select 26 27 read-write 00 No transfer #00 01 Triangle waves, complementary PWM mode: Transfer at crest Saw waves: Transfer at the end of period #01 10 Triangle waves, complementary PWM mode: Transfer at trough Saw waves: Transfer by compare match of GTCCRA register #10 11 Triangle waves, complementary PWM mode: Transfer at both crest and trough Saw waves: Setting prohibited #11 OLTTB GTIOCnB Output Level Buffer Transfer Timing Select 28 29 read-write 00 No transfer #00 01 Triangle waves, complementary PWM mode: Transfer at crest Saw waves: Transfer at the end of period #01 10 Triangle waves, complementary PWM mode: Transfer at trough Saw waves: Transfer by compare match of GTCCRB register #10 11 Triangle waves, complementary PWM mode: Transfer at both crest and trough Saw waves: Setting prohibited #11 GTOLBR General PWM Timer Output Level Buffer Register 0xE4 32 read-write 0x00000000 0xffffffff GTIOAB GTIOA buffer bits 0 4 read-write GTIOBB GTIOB buffer bits 16 20 read-write GTICCR General PWM Timer Inter Channel Cooperation Input Capture Control Register 0xEC 32 read-write 0x00000000 0xffffffff ICAFA Forwarding GTCCRA register Compare Match/Input Capture to Other Channel GTCCRA Input Capture Source Enable 0 0 read-write 0 Disable forwarding GTCCRA register compare match/input capture to GTCCRA input capture source of other channels #0 1 Enable forwarding GTCCRA register compare match/input capture to GTCCRA input capture source of other channels #1 ICAFB Forwarding GTCCRB register Compare Match/Input Capture to Other Channel GTCCRA Input Capture Source Enable 1 1 read-write 0 Disable forwarding GTCCRB register compare match/input capture to GTCCRA input capture source of other channels #0 1 Enable forwarding GTCCRB register compare match/input capture to GTCCRA input capture source of other channels #1 ICAFC Forwarding GTCCRC register Compare Match to Other Channel GTCCRA Input Source Capture Enable 2 2 read-write 0 Disable forwarding GTCCRC register compare match to GTCCRA input capture source of other channels #0 1 Enable forwarding GTCCRC register compare match to GTCCRA input capture source of other channels #1 ICAFD Forwarding GTCCRD register Compare Match to Other Channel GTCCRA Input Capture Source Enable 3 3 read-write 0 Disable forwarding GTCCRD register compare match to GTCCRA input capture source of other channels #0 1 Enable forwarding GTCCRD register compare match to GTCCRA input capture source of other channels #1 ICAFE Forwarding GTCCRE register Compare Match to Other Channel GTCCRA Input Capture Source Enable 4 4 read-write 0 Disable forwarding GTCCRE register compare match to GTCCRA input capture source of other channels #0 1 Enable forwarding GTCCRE register compare match to GTCCRA input capture source of other channels #1 ICAFF Forwarding GTCCRF register Compare Match to Other Channel GTCCRA Input Capture Source Enable 5 5 read-write 0 Disable forwarding GTCCRF register compare match to GTCCRA input capture source of other channels #0 1 Enable forwarding GTCCRF register compare match to GTCCRA input capture source of other channels #1 ICAFPO Forwarding Overflow to Other Channel GTCCRA Input Capture Source Enable 6 6 read-write 0 Disable forwarding overflow in saw-waves or the crest in triangle-waves or complementary PWM mode to GTCCRA input capture source of other channels #0 1 Enable forwarding overflow in saw-waves or the crest in triangle-waves or complementary PWM mode to GTCCRA input capture source of other channels #1 ICAFPU Forwarding Underflow to Other Channel GTCCRA Input Capture Source Enable 7 7 read-write 0 Disable forwarding underflow in saw-waves or the trough in triangle-waves or complementary PWM mode to GTCCRA input capture source of other channels #0 1 Enable forwarding underflow in saw-waves or the trough in triangle-waves or complementary PWM mode to GTCCRA input capture source of other channels #1 ICACLK Forwarding Count Clock to Other Channel GTCCRA Input Capture Source Enable 8 8 read-write 0 Disable forwarding count clock to GTCCRA input capture source of other channels #0 1 Enable forwarding count clock to GTCCRA input capture source of other channels #1 ICAGRP GTCCRA Input Capture Group Select 14 15 read-write 00 Select group A #00 01 Select group B #01 10 Select group C #10 11 Select group D #11 ICBFA Forwarding GTCCRA register Compare Match/Input Capture to Other Channel GTCCRB Input Capture Source Enable 16 16 read-write 0 Disable forwarding GTCCRA register compare match/input capture to GTCCRB input capture source of other channels #0 1 Enable forwarding GTCCRA register compare match/input capture to GTCCRB input capture source of other channels #1 ICBFB Forwarding GTCCRB register Compare Match/Input Capture to Other Channel GTCCRB Input Capture Source Enable 17 17 read-write 0 Disable forwarding GTCCRB register compare match/input capture to GTCCRB input capture source of other channels #0 1 Enable forwarding GTCCRB register compare match/input capture to GTCCRB input capture source of other channels #1 ICBFC Forwarding GTCCRC register Compare Match to Other Channel GTCCRB Input Source Capture Enable 18 18 read-write 0 Disable forwarding GTCCRD register compare match to GTCCRB input capture source of other channels #0 1 Enable forwarding GTCCRD register compare match to GTCCRB input capture source of other channels #1 ICBFD Forwarding GTCCRD register Compare Match to Other Channel GTCCRB Input Capture Source Enable 19 19 read-write 0 Disable forwarding GTCCRD register compare match to GTCCRB input capture source of other channels #0 1 Enable forwarding GTCCRD register compare match to GTCCRB input capture source of other channels #1 ICBFE Forwarding GTCCRE register Compare Match to Other Channel GTCCRB Input Capture Source Enable 20 20 read-write 0 Disable forwarding GTCCRE register compare match to GTCCRB input capture source of other channels #0 1 Enable forwarding GTCCRE register compare match to GTCCRB input capture source of other channels #1 ICBFF Forwarding GTCCRF register Compare Match to Other Channel GTCCRB Input Capture Source Enable 21 21 read-write 0 Disable forwarding GTCCRF register compare match to GTCCRB input capture source of other channels #0 1 Enable forwarding GTCCRF register compare match to GTCCRB input capture source of other channels #1 ICBFPO Forwarding Overflow to Other Channel GTCCRB Input Capture Source Enable 22 22 read-write 0 Disable forwarding overflow in saw-waves or the crest in triangle-waves or complementary PWM mode to GTCCRB input capture source of other channels #0 1 Enable forwarding overflow in saw-waves or the crest in triangle-waves or complementary PWM mode to GTCCRB input capture source of other channels #1 ICBFPU Forwarding Underflow to Other Channel GTCCRB Input Capture Source Enable 23 23 read-write 0 Disable forwarding underflow in saw-waves or the trough in triangle-waves or complementary PWM mode to GTCCRB input capture source of other channels #0 1 Enable forwarding underflow in saw-waves or the trough in triangle-waves or complementary PWM mode to GTCCRB input capture source of other channels #1 ICBCLK Forwarding Count Clock to Other Channel GTCCRB Input Capture Source Enable 24 24 read-write 0 Disable forwarding count clock to GTCCRB input capture source of other channels #0 1 Enable forwarding count clock to GTCCRB input capture source of other channels #1 ICBGRP GTCCRB Input Capture Group Select 30 31 read-write 00 Select group A #00 01 Select group B #01 10 Select group C #10 11 Select group D #11 GPT325 General PWM 32-bit Timer 5 0x40169500 GPT326 General PWM 32-bit Timer 6 0x40169600 GPT327 General PWM 32-bit Timer 7 0x40169700 GPT328 General PWM 32-bit Timer 8 0x40169800 GPT329 General PWM 32-bit Timer 9 0x40169900 GPT_OPS Output Phase Switching Controller 0x40169A00 0x00 4 registers OPSCR Output Phase Switching Control Register 0x00 32 read-write 0x00000000 0xffffffff UF 0 0 read-write VF 1 1 read-write WF 2 2 read-write U Input U-Phase Monitor 4 4 read-only V Input V-Phase Monitor 5 5 read-only W Input W-Phase Monitor 6 6 read-only EN Output Phase Enable 8 8 read-write 0 Do not output (Hi-Z external pin) #0 1 Output #1 FB External Feedback Signal Enable 16 16 read-write 0 Select the external input #0 1 Select the soft setting (OPSCR.UF, VF, WF) #1 P Positive-Phase Output (P) Control 17 17 read-write 0 Level signal output #0 1 PWM signal output #1 N Negative-Phase Output (N) Control 18 18 read-write 0 Level signal output #0 1 PWM signal output #1 INV Output Phase Invert Control 19 19 read-write 0 Positive logic (active-high) output #0 1 Negative logic (active-low) output #1 RV Output Phase Rotation Direction Reversal Control 20 20 read-write 0 Positive rotation #0 1 Reverse rotation #1 ALIGN Input Phase Alignment 21 21 read-write 0 Input phase aligned to GTCLK #0 1 Input phase aligned to the falling edge of PWM #1 GRP Output Disabled Source Selection 24 25 read-write GODF Group Output Disable Function 26 26 read-write 0 This bit function is ignored #0 1 Group disable clears the OPSCR.EN bit #1 NFEN External Input Noise Filter Enable 29 29 read-write 0 Do not use a noise filter on the external input #0 1 Use a noise filter on the external input #1 NFCS External Input Noise Filter Clock Selection 30 31 read-write 00 GTCLK/1 #00 01 GTCLK/4 #01 10 GTCLK/16 #10 11 GTCLK/64 #11 GPT_GTCLK GTCLK 0x40169B00 0x00 4 registers GTCLKCR General PWM Timer Clock Control Register 0x00 32 read-write 0x00000000 0xffffffff BPEN Synchronization Circuit Bypass Enable 0 0 read-write 0 In case of using Bus Clock and GPT Core Clock asynchronously #0 1 In case of using Bus Clock and GPT Core Clock synchronously #1 PDG PWM Delay Generation Circuit 0x4016A000 0x00 4 registers 0x18 34 registers GTDLYCR PWM Output Delay Control Register 0x0000 16 read-write 0x0000 0xffff DLLEN DLL Operation Enable 0 0 read-write 0 DLL operation disabled #0 1 DLL operation enabled #1 DLYRST PWM Delay Generation Circuit Reset 1 1 read-write 0 Normal operation #0 1 Reset #1 FRANGE GPT core clock Frequency Range 8 8 read-write 0 GPT core clock frequency is 115 MHz to 200 MHz #0 1 GPT core clock frequency is 80 MHz to 120 MHz #1 GTDLYCR2 PWM Output Delay Control Register 2 0x0002 16 read-write 0x0000 0xffff DLYBS0 PWM Delay Generation Circuit bypass for channel 0 0 0 read-write 0 Delay generation circuit of channel 0 bypassed #0 1 Delay generation circuit of channel 0 not bypassed #1 DLYBS1 PWM Delay Generation Circuit bypass for channel 1 1 1 read-write 0 Delay generation circuit of channel 1 bypassed #0 1 Delay generation circuit of channel 1 not bypassed #1 DLYBS2 PWM Delay Generation Circuit bypass for channel 2 2 2 read-write 0 Delay generation circuit of channel 2 bypassed #0 1 Delay generation circuit of channel 2 not bypassed #1 DLYBS3 PWM Delay Generation Circuit bypass for channel 3 3 3 read-write 0 Delay generation circuit of channel 3 bypassed #0 1 Delay generation circuit of channel 3 not bypassed #1 DLYEN0 PWM Delay Generation Circuit enable for channel 0 8 8 read-write 0 Delay generation circuit of channel 0 enabled #0 1 Delay generation circuit of channel 0 disabled #1 DLYEN1 PWM Delay Generation Circuit enable for channel 1 9 9 read-write 0 Delay generation circuit of channel 1 enabled #0 1 Delay generation circuit of channel 1 disabled #1 DLYEN2 PWM Delay Generation Circuit enable for channel 2 10 10 read-write 0 Delay generation circuit of channel 2 enabled #0 1 Delay generation circuit of channel 2 disabled #1 DLYEN3 PWM Delay Generation Circuit enable for channel 3 11 11 read-write 0 Delay generation circuit of channel 3 enabled #0 1 Delay generation circuit of channel 3 disabled #1 4 0x4 0-3 GTDLYR%sA GTIOCnA Rising Output Delay Register 0x018 16 read-write 0x0000 0xffff DLY GTIOCnA Output Rising Edge Delay Setting 0 4 read-write 0x00 Delay on rising edges is not applied 0x00 0x01 Delay of 1/32 times GTCLK period applied 0x01 0x02 Delay of 2/32 times GTCLK period applied 0x02 0x03 Delay of 3/32 times GTCLK period applied 0x03 0x04 Delay of 4/32 times GTCLK period applied 0x04 0x05 Delay of 5/32 times GTCLK period applied 0x05 0x06 Delay of 6/32 times GTCLK period applied 0x06 0x07 Delay of 7/32 times GTCLK period applied 0x07 0x08 Delay of 8/32 times GTCLK period applied 0x08 0x09 Delay of 9/32 times GTCLK period applied 0x09 0x0A Delay of 10/32 times GTCLK period applied 0x0a 0x0B Delay of 11/32 times GTCLK period applied 0x0b 0x0C Delay of 12/32 times GTCLK period applied 0x0c 0x0D Delay of 13/32 times GTCLK period applied 0x0d 0x0E Delay of 14/32 times GTCLK period applied 0x0e 0x0F Delay of 15/32 times GTCLK period applied 0x0f 0x10 Delay of 16/32 times GTCLK period applied 0x10 0x11 Delay of 17/32 times GTCLK period applied 0x11 0x12 Delay of 18/32 times GTCLK period applied 0x12 0x13 Delay of 19/32 times GTCLK period applied 0x13 0x14 Delay of 20/32 times GTCLK period applied 0x14 0x15 Delay of 21/32 times GTCLK period applied 0x15 0x16 Delay of 22/32 times GTCLK period applied 0x16 0x17 Delay of 23/32 times GTCLK period applied 0x17 0x18 Delay of 24/32 times GTCLK period applied 0x18 0x19 Delay of 25/32 times GTCLK period applied 0x19 0x1A Delay of 26/32 times GTCLK period applied 0x1a 0x1B Delay of 27/32 times GTCLK period applied 0x1b 0x1C Delay of 28/32 times GTCLK period applied 0x1c 0x1D Delay of 29/32 times GTCLK period applied 0x1d 0x1E Delay of 30/32 times GTCLK period applied 0x1e 0x1F Delay of 31/32 times GTCLK period applied 0x1f 4 0x4 0-3 GTDLYR%sB GTIOCnB Rising Output Delay Register 0x01A 16 read-write 0x0000 0xffff DLY GTIOCnB Output Rising Edge Delay Setting 0 4 read-write 0x00 Delay on rising edges is not applied 0x00 0x01 Delay of 1/32 times GTCLK period applied 0x01 0x02 Delay of 2/32 times GTCLK period applied 0x02 0x03 Delay of 3/32 times GTCLK period applied 0x03 0x04 Delay of 4/32 times GTCLK period applied 0x04 0x05 Delay of 5/32 times GTCLK period applied 0x05 0x06 Delay of 6/32 times GTCLK period applied 0x06 0x07 Delay of 7/32 times GTCLK period applied 0x07 0x08 Delay of 8/32 times GTCLK period applied 0x08 0x09 Delay of 9/32 times GTCLK period applied 0x09 0x0A Delay of 10/32 times GTCLK period applied 0x0a 0x0B Delay of 11/32 times GTCLK period applied 0x0b 0x0C Delay of 12/32 times GTCLK period applied 0x0c 0x0D Delay of 13/32 times GTCLK period applied 0x0d 0x0E Delay of 14/32 times GTCLK period applied 0x0e 0x0F Delay of 15/32 times GTCLK period applied 0x0f 0x10 Delay of 16/32 times GTCLK period applied 0x10 0x11 Delay of 17/32 times GTCLK period applied 0x11 0x12 Delay of 18/32 times GTCLK period applied 0x12 0x13 Delay of 19/32 times GTCLK period applied 0x13 0x14 Delay of 20/32 times GTCLK period applied 0x14 0x15 Delay of 21/32 times GTCLK period applied 0x15 0x16 Delay of 22/32 times GTCLK period applied 0x16 0x17 Delay of 23/32 times GTCLK period applied 0x17 0x18 Delay of 24/32 times GTCLK period applied 0x18 0x19 Delay of 25/32 times GTCLK period applied 0x19 0x1A Delay of 26/32 times GTCLK period applied 0x1a 0x1B Delay of 27/32 times GTCLK period applied 0x1b 0x1C Delay of 28/32 times GTCLK period applied 0x1c 0x1D Delay of 29/32 times GTCLK period applied 0x1d 0x1E Delay of 30/32 times GTCLK period applied 0x1e 0x1F Delay of 31/32 times GTCLK period applied 0x1f 4 0x4 0-3 GTDLYF%sA GTIOCnA Falling Output Delay Register 0x028 16 read-write 0x0000 0xffff DLY GTIOCnA Output Falling Edge Delay Setting 0 4 read-write 0x00 Delay on falling edges is not applied 0x00 0x01 Delay of 1/32 times GTCLK period applied 0x01 0x02 Delay of 2/32 times GTCLK period applied 0x02 0x03 Delay of 3/32 times GTCLK period applied 0x03 0x04 Delay of 4/32 times GTCLK period applied 0x04 0x05 Delay of 5/32 times GTCLK period applied 0x05 0x06 Delay of 6/32 times GTCLK period applied 0x06 0x07 Delay of 7/32 times GTCLK period applied 0x07 0x08 Delay of 8/32 times GTCLK period applied 0x08 0x09 Delay of 9/32 times GTCLK period applied 0x09 0x0A Delay of 10/32 times GTCLK period applied 0x0a 0x0B Delay of 11/32 times GTCLK period applied 0x0b 0x0C Delay of 12/32 times GTCLK period applied 0x0c 0x0D Delay of 13/32 times GTCLK period applied 0x0d 0x0E Delay of 14/32 times GTCLK period applied 0x0e 0x0F Delay of 15/32 times GTCLK period applied 0x0f 0x10 Delay of 16/32 times GTCLK period applied 0x10 0x11 Delay of 17/32 times GTCLK period applied 0x11 0x12 Delay of 18/32 times GTCLK period applied 0x12 0x13 Delay of 19/32 times GTCLK period applied 0x13 0x14 Delay of 20/32 times GTCLK period applied 0x14 0x15 Delay of 21/32 times GTCLK period applied 0x15 0x16 Delay of 22/32 times GTCLK period applied 0x16 0x17 Delay of 23/32 times GTCLK period applied 0x17 0x18 Delay of 24/32 times GTCLK period applied 0x18 0x19 Delay of 25/32 times GTCLK period applied 0x19 0x1A Delay of 26/32 times GTCLK period applied 0x1a 0x1B Delay of 27/32 times GTCLK period applied 0x1b 0x1C Delay of 28/32 times GTCLK period applied 0x1c 0x1D Delay of 29/32 times GTCLK period applied 0x1d 0x1E Delay of 30/32 times GTCLK period applied 0x1e 0x1F Delay of 31/32 times GTCLK period applied 0x1f 4 0x4 0-3 GTDLYF%sB GTIOCnB Falling Output Delay Register 0x02A 16 read-write 0x0000 0xffff DLY GTIOCnB Output Falling Edge Delay Setting 0 4 read-write 0x00 Delay on falling edges is not applied 0x00 0x01 Delay of 1/32 times GTCLK period applied 0x01 0x02 Delay of 2/32 times GTCLK period applied 0x02 0x03 Delay of 3/32 times GTCLK period applied 0x03 0x04 Delay of 4/32 times GTCLK period applied 0x04 0x05 Delay of 5/32 times GTCLK period applied 0x05 0x06 Delay of 6/32 times GTCLK period applied 0x06 0x07 Delay of 7/32 times GTCLK period applied 0x07 0x08 Delay of 8/32 times GTCLK period applied 0x08 0x09 Delay of 9/32 times GTCLK period applied 0x09 0x0A Delay of 10/32 times GTCLK period applied 0x0a 0x0B Delay of 11/32 times GTCLK period applied 0x0b 0x0C Delay of 12/32 times GTCLK period applied 0x0c 0x0D Delay of 13/32 times GTCLK period applied 0x0d 0x0E Delay of 14/32 times GTCLK period applied 0x0e 0x0F Delay of 15/32 times GTCLK period applied 0x0f 0x10 Delay of 16/32 times GTCLK period applied 0x10 0x11 Delay of 17/32 times GTCLK period applied 0x11 0x12 Delay of 18/32 times GTCLK period applied 0x12 0x13 Delay of 19/32 times GTCLK period applied 0x13 0x14 Delay of 20/32 times GTCLK period applied 0x14 0x15 Delay of 21/32 times GTCLK period applied 0x15 0x16 Delay of 22/32 times GTCLK period applied 0x16 0x17 Delay of 23/32 times GTCLK period applied 0x17 0x18 Delay of 24/32 times GTCLK period applied 0x18 0x19 Delay of 25/32 times GTCLK period applied 0x19 0x1A Delay of 26/32 times GTCLK period applied 0x1a 0x1B Delay of 27/32 times GTCLK period applied 0x1b 0x1C Delay of 28/32 times GTCLK period applied 0x1c 0x1D Delay of 29/32 times GTCLK period applied 0x1d 0x1E Delay of 30/32 times GTCLK period applied 0x1e 0x1F Delay of 31/32 times GTCLK period applied 0x1f ADC_B 12-bit A/D Converter 0x40170000 0x00 16 registers 0x20 12 registers 0x40 24 registers 0x5C 4 registers 0xC0 152 registers 0x1C0 20 registers 0x200 36 registers 0x240 40 registers 0x280 4 registers 0x288 8 registers 0x294 4 registers 0x2B0 4 registers 0x2C0 16 registers 0x300 4 registers 0x320 4 registers 0x340 8 registers 0x360 100 registers 0x400 16 registers 0x448 8 registers 0x458 32 registers 0x4C0 28 registers 0x600 604 registers 0xC00 4 registers 0xC08 4 registers 0xC10 4 registers 0xC20 36 registers 0xC60 4 registers 0xC80 16 registers 0xC98 16 registers 0xCB0 12 registers 0xCC4 4 registers 0xCD0 20 registers 0xCF0 12 registers 0xD00 12 registers 0xD14 8 registers 0xD24 12 registers 0xD38 12 registers 0xD4C 12 registers 0x1000 116 registers 0x1180 12 registers 0x1194 16 registers 0x1200 36 registers ADCLKENR A/D Conversion Clock Enable Register 0x000 32 read-write 0x00000000 0xffffffff CLKEN ADCLK Operating Enable 0 0 read-write 0 Stop ADCLK #0 1 Supply ADCLK #1 ADCLKSR A/D Conversion Clock Status Register 0x004 32 read-only 0x00000000 0xffffffff CLKSR ADCLK status 0 0 read-only 0 ADCLK is stopped #0 1 ADCLK is in supply #1 ADCLKCR A/D Conversion Clock Control Register 0x008 32 read-write 0x00000000 0xffffffff CLKSEL ADCLK Clock Source Select 0 1 read-write 00 Peripheral Module Clock C (PCLKC) #00 01 GPT clock (GPTCLK) #01 10 Peripheral Module Clock A (PCLKA) #10 01 Setting prohibited #01 DIVR Clock Division Ratio Select 16 18 read-write 000 1/1 #000 001 1/2 #001 010 1/3 #010 011 1/4 #011 100 1/5 #100 101 1/6 #101 110 1/7 #110 111 1/8 #111 ADSYCR A/D Converter Synchronous Operation Control Register 0x00C 32 read-write 0x00000005 0xffffffff ADSYCYC Synchronous Operation Period Cycle 0 10 read-write ADSYDIS0 ADC0 Synchronous Operation Select 16 16 read-write 0 Enable ADC0 synchronous operation #0 1 Disable ADC0 synchronous operation #1 ADSYDIS1 ADC1 Synchronous Operation Select 17 17 read-write 0 Enable ADC1 synchronous operation #0 1 Disable ADC1 synchronous operation #1 ADERINTCR A/D Conversion Error Interrupt Enable Register 0x020 32 read-write 0x00000000 0xffffffff ADEIE0 ADC0 A/D Conversion Error Interrupt Enable 0 0 read-write 0 Disable A/D conversion error interrupt for ADC0 #0 1 Enable A/D conversion error interrupt for ADC0 #1 ADEIE1 ADC1 A/D Conversion Error Interrupt Enable 1 1 read-write 0 Disable A/D conversion error interrupt for ADC1 #0 1 Enable A/D conversion error interrupt for ADC1 #1 ADOVFINTCR A/D Conversion Overflow Interrupt Enable Register 0x024 32 read-write 0x00000000 0xffffffff ADOVFIE0 ADC0 A/D Conversion Overflow Interrupt Enable 0 0 read-write 0 Disable A/D conversion overflow interrupt for ADC0 #0 1 Enable A/D conversion overflow interrupt for ADC0 #1 ADOVFIE1 ADC1 A/D Conversion Overflow Interrupt Enable 1 1 read-write 0 Disable A/D conversion overflow interrupt for ADC1 #0 1 Enable A/D conversion overflow interrupt for ADC1 #1 ADCALINTCR Calibration interrupt Enable Register 0x028 32 read-write 0x00000000 0xffffffff CALENDIE0 ADC0 Calibration End Interrupt Enable 16 16 read-write 0 Disable Calibration End Interrupt for ADC0 #0 1 Enable Calibration End Interrupt for ADC0 #1 CALENDIE1 ADC1 Calibration End Interrupt Enable 17 17 read-write 0 Disable Calibration End Interrupt for ADC1 #0 1 Enable Calibration End Interrupt for ADC1 #1 ADMDR A/D Converter Mode Selection Register 0x040 32 read-write 0x00000000 0xffffffff ADMD0 ADC0 Mode Selection 0 3 read-write 0x0 SAR mode – Single scan mode 0x0 0x1 SAR mode – Continuous scan mode 0x1 0x4 Oversampling mode – Single scan mode 0x4 0x5 Oversampling mode – Continuous scan mode 0x5 0x8 Hybrid mode – Single scan mode 0x8 0x9 Hybrid mode – Continuous scan mode 0x9 0xA Hybrid mode – Background continuous scan mode 0xa Others Setting prohibited true ADMD1 ADC1 Mode Selection 8 11 read-write 0x0 SAR mode – Single scan mode 0x0 0x1 SAR mode – Continuous scan mode 0x1 0x4 Oversampling mode – Single scan mode 0x4 0x5 Oversampling mode – Continuous scan mode 0x5 0x8 Hybrid mode – Single scan mode 0x8 0x9 Hybrid mode – Continuous scan mode 0x9 0xA Hybrid mode – Background continuous scan mode 0xa Others Setting prohibited true ADGSPCR A/D Group scan Priority Control Register 0x044 32 read-write 0x00000000 0xffffffff PGS0 ADC0 Group Priority Control Setting 0 0 read-write 0 ADC0 operation is without group priority control #0 1 ADC0 operation is with group priority control in SAR mode. Setting prohibited when other than SAR mode. #1 RSCN0 ADC0 Group Priority Control Setting 2 1 1 read-write 0 Set when PGS0 is set to 0. #0 1 Set when PGS0 is set to 1. #1 LGRRS0 ADC0 Group Priority Control Setting 3 2 2 read-write 0 Set when PGS0 is set to 0. #0 1 Set when PGS0 is set to 1. #1 GRP0 ADC0 Group Priority Control Setting 4 3 3 read-write 0 Set the following case: When PGS0 is set to 0When PGS0 is set to 1 and ADC0 is SAR mode – Single scan mode. #0 1 Set when PGS0 is set to 1 and ADC0 is SAR mode – Continuous scan mode. #1 PGS1 ADC1 Group Priority Control Setting 8 8 read-write 0 ADC1 operation is without group priority control #0 1 ADC1 operation is with group priority control in SAR mode. Setting prohibited when other than SAR mode. #1 RSCN1 ADC1 Group Priority Control Setting 2 9 9 read-write 0 Set when PGS1 is set to 0. #0 1 Set when PGS1 is set to 1. #1 LGRRS1 ADC1 Group Priority Control Setting 3 10 10 read-write 0 Set when PGS1 is set to 0. #0 1 Set when PGS1 is set to 1. #1 GRP1 ADC1 Group Priority Control Setting 4 11 11 read-write 0 Set the following case: When PGS1 is set to 0When PGS1 is set to 1 and ADC1 is SAR mode – Single scan mode. #0 1 Set when PGS1 is set to 1 and ADC1 is SAR mode – Continuous scan mode. #1 ADSGER Scan Group Enable Register 0x048 32 read-write 0x00000000 0xffffffff SGRE0 Scan Group n Enable 0 0 read-write 0 Disable the scan group n #0 1 Enable the scan group n #1 SGRE1 Scan Group n Enable 1 1 read-write 0 Disable the scan group n #0 1 Enable the scan group n #1 SGRE2 Scan Group n Enable 2 2 read-write 0 Disable the scan group n #0 1 Enable the scan group n #1 SGRE3 Scan Group n Enable 3 3 read-write 0 Disable the scan group n #0 1 Enable the scan group n #1 SGRE4 Scan Group n Enable 4 4 read-write 0 Disable the scan group n #0 1 Enable the scan group n #1 SGRE5 Scan Group n Enable 5 5 read-write 0 Disable the scan group n #0 1 Enable the scan group n #1 SGRE6 Scan Group n Enable 6 6 read-write 0 Disable the scan group n #0 1 Enable the scan group n #1 SGRE7 Scan Group n Enable 7 7 read-write 0 Disable the scan group n #0 1 Enable the scan group n #1 SGRE8 Scan Group n Enable 8 8 read-write 0 Disable the scan group n #0 1 Enable the scan group n #1 ADSGCR0 Scan Group Control Register 0 0x04C 32 read-write 0x00000000 0xffffffff SGADS0 Scan Group 0 A/D Converter Selection 0 1 read-write 00 Select ADC0 #00 01 Select ADC1 #01 Others Setting prohibited true SGADS1 Scan Group 1 A/D Converter Selection 8 9 read-write 00 Select ADC0 #00 01 Select ADC1 #01 Others Setting prohibited true SGADS2 Scan Group 2 A/D Converter Selection 16 17 read-write 00 Select ADC0 #00 01 Select ADC1 #01 Others Setting prohibited true SGADS3 Scan Group 3 A/D Converter Selection 24 25 read-write 00 Select ADC0 #00 01 Select ADC1 #01 Others Setting prohibited true ADSGCR1 Scan Group Control Register 1 0x050 32 read-write 0x00000000 0xffffffff SGADS4 Scan Group 4 A/D Converter Selection 0 1 read-write 00 Select ADC0 #00 01 Select ADC1 #01 Others Setting prohibited true SGADS5 Scan Group 5 A/D Converter Selection 8 9 read-write 00 Select ADC0 #00 01 Select ADC1 #01 Others Setting prohibited true SGADS6 Scan Group 6 A/D Converter Selection 16 17 read-write 00 Select ADC0 #00 01 Select ADC1 #01 Others Setting prohibited true SGADS7 Scan Group 7 A/D Converter Selection 24 25 read-write 00 Select ADC0 #00 01 Select ADC1 #01 Others Setting prohibited true ADSGCR2 Scan Group Control Register 2 0x054 32 read-write 0x00000000 0xffffffff SGADS8 Scan Group 8 A/D Converter Selection 0 1 read-write 00 Select ADC0 #00 01 Select ADC1 #01 Others Setting prohibited true ADINTCR Scan End Interrupt Enable Register 0x05C 32 read-write 0x00000000 0xffffffff ADIE0 Scan Group n Scan End Interrupt Enable 0 0 read-write 0 Disable scan end interrupt #0 1 Enable scan end interrupt #1 ADIE1 Scan Group n Scan End Interrupt Enable 1 1 read-write 0 Disable scan end interrupt #0 1 Enable scan end interrupt #1 ADIE2 Scan Group n Scan End Interrupt Enable 2 2 read-write 0 Disable scan end interrupt #0 1 Enable scan end interrupt #1 ADIE3 Scan Group n Scan End Interrupt Enable 3 3 read-write 0 Disable scan end interrupt #0 1 Enable scan end interrupt #1 ADIE4 Scan Group n Scan End Interrupt Enable 4 4 read-write 0 Disable scan end interrupt #0 1 Enable scan end interrupt #1 ADIE5 Scan Group n Scan End Interrupt Enable 5 5 read-write 0 Disable scan end interrupt #0 1 Enable scan end interrupt #1 ADIE6 Scan Group n Scan End Interrupt Enable 6 6 read-write 0 Disable scan end interrupt #0 1 Enable scan end interrupt #1 ADIE7 Scan Group n Scan End Interrupt Enable 7 7 read-write 0 Disable scan end interrupt #0 1 Enable scan end interrupt #1 ADIE8 Scan Group n Scan End Interrupt Enable 8 8 read-write 0 Disable scan end interrupt #0 1 Enable scan end interrupt #1 9 0x10 0-8 ADTRGEXT%s External Trigger Enable Register %s 0x0C0 32 read-write 0x00000000 0xffffffff TRGEXT0 External Trigger Input 0 (ADTRG0) Enable 0 0 read-write 0 Disable ADTRG0 #0 1 Enable ADTRG0 #1 TRGEXT1 External Trigger Input 1 (ADTRG1) Enable 1 1 read-write 0 Disable ADTRG1 #0 1 Enable ADTRG1 #1 9 0x10 0-8 ADTRGELC%s ELC Trigger Enable Register %s 0x0C4 32 read-write 0x00000000 0xffffffff TRGELC0 ELC Trigger m Enable 0 0 read-write 0 Disable ELC Trigger m #0 1 Enable ELC Trigger m #1 TRGELC1 ELC Trigger m Enable 1 1 read-write 0 Disable ELC Trigger m #0 1 Enable ELC Trigger m #1 TRGELC2 ELC Trigger m Enable 2 2 read-write 0 Disable ELC Trigger m #0 1 Enable ELC Trigger m #1 TRGELC3 ELC Trigger m Enable 3 3 read-write 0 Disable ELC Trigger m #0 1 Enable ELC Trigger m #1 TRGELC4 ELC Trigger m Enable 4 4 read-write 0 Disable ELC Trigger m #0 1 Enable ELC Trigger m #1 TRGELC5 ELC Trigger m Enable 5 5 read-write 0 Disable ELC Trigger m #0 1 Enable ELC Trigger m #1 9 0x10 0-8 ADTRGGPT%s GPT Trigger Enable Register %s 0x0C8 32 read-write 0x00000000 0xffffffff TRGGPTA0 GPT channel m A/D Conversion Starting Request A Enable 0 0 read-write 0 Disable the A/D conversion stating request A from GPT channel m #0 1 Enable the A/D conversion stating request A from GPT channel m #1 TRGGPTA1 GPT channel m A/D Conversion Starting Request A Enable 1 1 read-write 0 Disable the A/D conversion stating request A from GPT channel m #0 1 Enable the A/D conversion stating request A from GPT channel m #1 TRGGPTA2 GPT channel m A/D Conversion Starting Request A Enable 2 2 read-write 0 Disable the A/D conversion stating request A from GPT channel m #0 1 Enable the A/D conversion stating request A from GPT channel m #1 TRGGPTA3 GPT channel m A/D Conversion Starting Request A Enable 3 3 read-write 0 Disable the A/D conversion stating request A from GPT channel m #0 1 Enable the A/D conversion stating request A from GPT channel m #1 TRGGPTA4 GPT channel m A/D Conversion Starting Request A Enable 4 4 read-write 0 Disable the A/D conversion stating request A from GPT channel m #0 1 Enable the A/D conversion stating request A from GPT channel m #1 TRGGPTA5 GPT channel m A/D Conversion Starting Request A Enable 5 5 read-write 0 Disable the A/D conversion stating request A from GPT channel m #0 1 Enable the A/D conversion stating request A from GPT channel m #1 TRGGPTA6 GPT channel m A/D Conversion Starting Request A Enable 6 6 read-write 0 Disable the A/D conversion stating request A from GPT channel m #0 1 Enable the A/D conversion stating request A from GPT channel m #1 TRGGPTA7 GPT channel m A/D Conversion Starting Request A Enable 7 7 read-write 0 Disable the A/D conversion stating request A from GPT channel m #0 1 Enable the A/D conversion stating request A from GPT channel m #1 TRGGPTA8 GPT channel m A/D Conversion Starting Request A Enable 8 8 read-write 0 Disable the A/D conversion stating request A from GPT channel m #0 1 Enable the A/D conversion stating request A from GPT channel m #1 TRGGPTA9 GPT channel m A/D Conversion Starting Request A Enable 9 9 read-write 0 Disable the A/D conversion stating request A from GPT channel m #0 1 Enable the A/D conversion stating request A from GPT channel m #1 TRGGPTB0 GPT channel m A/D Conversion Starting Request B Enable 16 16 read-write 0 Disable the A/D conversion stating request B from GPT channel m #0 1 Enable the A/D conversion stating request B from GPT channel m #1 TRGGPTB1 GPT channel m A/D Conversion Starting Request B Enable 17 17 read-write 0 Disable the A/D conversion stating request B from GPT channel m #0 1 Enable the A/D conversion stating request B from GPT channel m #1 TRGGPTB2 GPT channel m A/D Conversion Starting Request B Enable 18 18 read-write 0 Disable the A/D conversion stating request B from GPT channel m #0 1 Enable the A/D conversion stating request B from GPT channel m #1 TRGGPTB3 GPT channel m A/D Conversion Starting Request B Enable 19 19 read-write 0 Disable the A/D conversion stating request B from GPT channel m #0 1 Enable the A/D conversion stating request B from GPT channel m #1 TRGGPTB4 GPT channel m A/D Conversion Starting Request B Enable 20 20 read-write 0 Disable the A/D conversion stating request B from GPT channel m #0 1 Enable the A/D conversion stating request B from GPT channel m #1 TRGGPTB5 GPT channel m A/D Conversion Starting Request B Enable 21 21 read-write 0 Disable the A/D conversion stating request B from GPT channel m #0 1 Enable the A/D conversion stating request B from GPT channel m #1 TRGGPTB6 GPT channel m A/D Conversion Starting Request B Enable 22 22 read-write 0 Disable the A/D conversion stating request B from GPT channel m #0 1 Enable the A/D conversion stating request B from GPT channel m #1 TRGGPTB7 GPT channel m A/D Conversion Starting Request B Enable 23 23 read-write 0 Disable the A/D conversion stating request B from GPT channel m #0 1 Enable the A/D conversion stating request B from GPT channel m #1 TRGGPTB8 GPT channel m A/D Conversion Starting Request B Enable 24 24 read-write 0 Disable the A/D conversion stating request B from GPT channel m #0 1 Enable the A/D conversion stating request B from GPT channel m #1 TRGGPTB9 GPT channel m A/D Conversion Starting Request B Enable 25 25 read-write 0 Disable the A/D conversion stating request B from GPT channel m #0 1 Enable the A/D conversion stating request B from GPT channel m #1 ADTRGDLR0 A/D Conversion Start Trigger Delay Register 0 0x1C0 32 read-write 0x00000000 0xffffffff TRGDLY0 Scan Group 0 Trigger Input Delay Configuration 0 7 read-write TRGDLY1 Scan Group 1 Trigger Input Delay Configuration 16 23 read-write ADTRGDLR1 A/D Conversion Start Trigger Delay Register 1 0x1C4 32 read-write 0x00000000 0xffffffff TRGDLY2 Scan Group 2 Trigger Input Delay Configuration 0 7 read-write TRGDLY3 Scan Group 3 Trigger Input Delay Configuration 16 23 read-write ADTRGDLR2 A/D Conversion Start Trigger Delay Register 2 0x1C8 32 read-write 0x00000000 0xffffffff TRGDLY4 Scan Group 4 Trigger Input Delay Configuration 0 7 read-write TRGDLY5 Scan Group 5 Trigger Input Delay Configuration 16 23 read-write ADTRGDLR3 A/D Conversion Start Trigger Delay Register 3 0x1CC 32 read-write 0x00000000 0xffffffff TRGDLY6 Scan Group 6 Trigger Input Delay Configuration 0 7 read-write TRGDLY7 Scan Group 7 Trigger Input Delay Configuration 16 23 read-write ADTRGDLR4 A/D Conversion Start Trigger Delay Register 4 0x1D0 32 read-write 0x00000000 0xffffffff TRGDLY8 Scan Group 8 Trigger Input Delay Configuration 0 7 read-write 9 0x04 0-8 ADSGDCR%s Scan Group Diagnosis Function Control Register %s 0x200 32 read-write 0x00000000 0xffffffff DIAGVAL Self-diagnosis Mode Selection 0 2 read-write 000 Set when any self-diagnosis channel are not included. Setting prohibited when any self-diagnosis channels are included. #000 100 Self-diagnosis mode 1 #100 101 Self-diagnosis mode 2 #101 110 Self-diagnosis mode 3 #110 Others Setting prohibited true ADDISEN Disconnection Detection Assist Enable 16 16 read-write 0 Disable the disconnection detection assist function #0 1 Enable the disconnection detection assist function #1 ADDISP Disconnection Detection Assist Mode Selection 20 20 read-write 0 Discharge #0 1 Precharge #1 ADDISN Disconnection Detection Assist Mode Selection 21 21 read-write 0 Discharge #0 1 Precharge #1 ADNDIS Disconnection Detection Assist Period 24 27 read-write 0x0 Setting prohibited when the disconnection detection assist function is enabled 0x0 0x1 Setting prohibited 0x1 0x2 Setting prohibited 0x2 Others The number of states for the discharge or precharge period true ADSSTR0 Sampling State Table Register 0 0x240 32 read-write 0x00020002 0xffffffff SST0 Sampling State Table 0 0 9 read-write SST1 Sampling State Table 1 16 25 read-write ADSSTR1 Sampling State Table Register 1 0x244 32 read-write 0x00020002 0xffffffff SST2 Sampling State Table 2 0 9 read-write SST3 Sampling State Table 3 16 25 read-write ADSSTR2 Sampling State Table Register 2 0x248 32 read-write 0x00020002 0xffffffff SST4 Sampling State Table 4 0 9 read-write SST5 Sampling State Table 5 16 25 read-write ADSSTR3 Sampling State Table Register 3 0x24C 32 read-write 0x00020002 0xffffffff SST6 Sampling State Table 6 0 9 read-write SST7 Sampling State Table 7 16 25 read-write ADSSTR4 Sampling State Table Register 4 0x250 32 read-write 0x00020002 0xffffffff SST8 Sampling State Table 8 0 9 read-write SST9 Sampling State Table 9 16 25 read-write ADSSTR5 Sampling State Table Register 5 0x254 32 read-write 0x00020002 0xffffffff SST10 Sampling State Table 10 0 9 read-write SST11 Sampling State Table 11 16 25 read-write ADSSTR6 Sampling State Table Register 6 0x258 32 read-write 0x00020002 0xffffffff SST12 Sampling State Table 12 0 9 read-write SST13 Sampling State Table 13 16 25 read-write ADSSTR7 Sampling State Table Register 7 0x25C 32 read-write 0x00020002 0xffffffff SST14 Sampling State Table 14 0 9 read-write SST15 Sampling State Table 15 16 25 read-write ADCNVSTR A/D Conversion State Register 0x260 32 read-write 0x00000303 0xffffffff CST0 A/D Converter Unit 0 (ADC0) 0 5 read-write CST1 A/D Converter Unit 1 (ADC1) 8 13 read-write ADCALSTCR A/D Converter Self-calibration State Register 0x264 32 read-write 0x00030002 0xffffffff CALADSST A/D Converter Self-calibration Sampling Time Configuration 0 9 read-write CALADCST A/D Converter Self-calibration Successive Approximation Time Configuration. 16 21 read-write ADSHCR0 Channel-dedicated Sample-and-hold Circuit Control Register 0 0x280 32 read-write 0x00000000 0xffffffff SHEN0 Channel-dedicated Sample-and-hold Circuit Unit 0 Select 0 0 read-write 0 Bypass the circuit unit 0 #0 1 Use the circuit unit 0 #1 SHEN1 Channel-dedicated Sample-and-hold Circuit Unit 1 Select 1 1 read-write 0 Bypass the circuit unit 1 #0 1 Use the circuit unit 1 #1 SHEN2 Channel-dedicated Sample-and-hold Circuit Unit 2 Select 2 2 read-write 0 Bypass the circuit unit 2 #0 1 Use the circuit unit 2 #1 SHMD0 Channel-dedicated Sample-and-hold Circuit Unit 0 Input Mode Select 16 16 read-write 0 Single-ended Input mode #0 1 Differential Input mode #1 SHMD1 Channel-dedicated Sample-and-hold Circuit Unit 1 Input Mode Select 17 17 read-write 0 Single-ended Input mode #0 1 Differential Input mode #1 SHMD2 Channel-dedicated Sample-and-hold Circuit Unit 2 Input Mode Select 18 18 read-write 0 Single-ended Input mode #0 1 Differential Input mode #1 ADSHSTR0 Channel-dedicated Sample-and-hold Circuit State Register 0 0x288 32 read-write 0x00020004 0xffffffff SHSST Channel-dedicated Sample-and-hold Circuit Unit 0 to 2 0 7 read-write SHHST Channel-dedicated Sample-and-hold Circuit Unit 0 to 2 16 18 read-write ADSHCR1 Channel-dedicated Sample-and-hold Circuit Control Register 1 0x28C 32 read-write 0x00000000 0xffffffff SHEN4 Channel-dedicated Sample-and-hold Circuit Unit 4 Select 0 0 read-write 0 Bypass the circuit unit 4 #0 1 Use the circuit unit 4 #1 SHEN5 Channel-dedicated Sample-and-hold Circuit Unit 5 Select 1 1 read-write 0 Bypass the circuit unit 5 #0 1 Use the circuit unit 5 #1 SHEN6 Channel-dedicated Sample-and-hold Circuit Unit 6 Select 2 2 read-write 0 Bypass the circuit unit 6 #0 1 Use the circuit unit 6 #1 SHMD4 Channel-dedicated Sample-and-hold Circuit Unit 4 Input Mode Select 16 16 read-write 0 Single-ended Input mode #0 1 Differential Input mode #1 SHMD5 Channel-dedicated Sample-and-hold Circuit Unit 5 Input Mode Select 17 17 read-write 0 Single-ended Input mode #0 1 Differential Input mode #1 SHMD6 Channel-dedicated Sample-and-hold Circuit Unit 6 Input Mode Select 18 18 read-write 0 Single-ended Input mode #0 1 Differential Input mode #1 ADSHSTR1 Channel-dedicated Sample-and-hold Circuit State Register 1 0x294 32 read-write 0x00020004 0xffffffff SHSST Channel-dedicated Sample-and-hold Circuit Unit 4 to 6 0 7 read-write SHHST Channel-dedicated Sample-and-hold Circuit Unit 4 to 6 16 18 read-write ADCALSHCR Channel-dedicated Sample-and-hold Circuit Self-calibration State Register 0x2B0 32 read-write 0x00020004 0xffffffff CALSHSST Channel-dedicated Sample-and-hold Circuit Self-calibration Sampling Time Configuration 0 7 read-write CALSHHST Channel-dedicated Sample-and-hold Circuit Self-calibration Hold Mode Switching Time Configuration 16 18 read-write 4 0x04 0-3 ADPGACR%s Programmable Gain Amplifier Control Register %s 0x2C0 32 read-write 0x00000000 0xfffffffd PGADEN PGA Unit n Input Mode Select 1 1 read-write 0 Single-ended Input mode #0 1 Pseudo-differential Input mode #1 PGASEL1 PGA Unit n Amplifier Output Enable 2 2 read-write 0 Not output the signal in a path through the PGA #0 1 Output the signal in a path through the PGA #1 PGAENAMP PGA Unit n Enable 3 3 read-write 0 Disable the PGA #0 1 Enable the PGA #1 PGAGEN PGA Unit n Gain Setting Enable 16 16 read-write 0 Disable gain setting #0 1 Enable gain setting #1 PGADG PGA Unit n Differential Input Gain Setting 20 21 read-write 00 × 1.500 #00 01 × 2.333 #01 10 × 4.000 #10 11 × 5.667 #11 PGAGAIN PGA Unit n Gain Setting 24 27 read-write 0x0 × 2.000 (PGA is Single-ended Input mode) Setting prohibited (PGA is Pseudo-differential Input mode) 0x0 0x1 × 2.500 (PGA is Single-ended Input mode) × 1.500 (PGA is Pseudo-differential Input mode) 0x1 0x2 × 2.667 (PGA is Single-ended Input mode) Setting prohibited (PGA is Pseudo-differential Input mode) 0x2 0x3 × 2.857 (PGA is Single-ended Input mode) Setting prohibited (PGA is Pseudo-differential Input mode) 0x3 0x4 × 3.077 (PGA is Single-ended Input mode) Setting prohibited (PGA is Pseudo-differential Input mode) 0x4 0x5 × 3.333 (PGA is Single-ended Input mode) × 2.333 (PGA is Pseudo-differential Input mode) 0x5 0x6 × 3.636 (PGA is Single-ended Input mode) Setting prohibited (PGA is Pseudo-differential Input mode) 0x6 0x7 × 4.000 (PGA is Single-ended Input mode) Setting prohibited (PGA is Pseudo-differential Input mode) 0x7 0x8 × 4.444 (PGA is Single-ended Input mode) Setting prohibited (PGA is Pseudo-differential Input mode) 0x8 0x9 × 5.000 (PGA is Single-ended Input mode) × 4.000 (PGA is Pseudo-differential Input mode) 0x9 0xA × 5.714 (PGA is Single-ended Input mode) Setting prohibited (PGA is Pseudo-differential Input mode) 0xa 0xB × 6.667 (PGA is Single-ended Input mode) × 5.667 (PGA is Pseudo-differential Input mode) 0xb 0xC × 8.000 (PGA is Single-ended Input mode) Setting prohibited (PGA is Pseudo-differential Input mode) 0xc 0xD × 10.000 (PGA is Single-ended Input mode) Setting prohibited (PGA is Pseudo-differential Input mode) 0xd 0xE × 13.333 (PGA is Single-ended Input mode) Setting prohibited (PGA is Pseudo-differential Input mode) 0xe 0xF Setting prohibited 0xf ADPGAMONCR Programable Gain Amp Monitor Output Control Register 0x300 32 read-write 0x00000000 0xffffffff PGAMON PGA Monitor Signal Selection 0 2 read-write 0x0 Not select monitor signal (Hi-Z) 0x0 0x1 PGA output 0x1 Others Setting prohibited true MONSEL0 PGA Unit 0 Monitor Output Enable 16 16 read-write 0 Disable monitor output #0 1 Enable monitor output #1 MONSEL1 PGA Unit 1 Monitor Output Enable 17 17 read-write 0 Disable monitor output #0 1 Enable monitor output #1 MONSEL2 PGA Unit 2 Monitor Output Enable 18 18 read-write 0 Disable monitor output #0 1 Enable monitor output #1 MONSEL3 PGA Unit 3 Monitor Output Enable 19 19 read-write 0 Disable monitor output #0 1 Enable monitor output #1 ADREFCR Internal Reference Voltage Monitor Enable Register 0x320 32 read-write 0x00000000 0xffffffff VDE Internal Reference Voltage A/D Conversion Select 0 0 read-write 0 Disable A/D conversion of internal reference voltage #0 1 Enable A/D conversion of internal reference voltage #1 2 0x04 0-1 ADDFSR%s A/D Converter Digital Filter Selection Register %s 0x340 32 read-write 0x00000000 0xffffffff DFSEL0 A/D Converter Unit n the 1st Digital Filter Characteristic Selection 0 1 read-write 01 Sinc filter #01 10 Minimum phase filter #10 Others Setting prohibited true DFSEL1 A/D Converter Unit n the 2nd Digital Filter Characteristic Selection 8 9 read-write 01 Sinc filter #01 10 Minimum phase filter #10 Others Setting prohibited true DFSEL2 A/D Converter Unit n the 3rd Digital Filter Characteristic Selection 16 17 read-write 01 Sinc filter #01 10 Minimum phase filter #10 Others Setting prohibited true DFSEL3 A/D Converter Unit n the 4th Digital Filter Characteristic Selection 24 25 read-write 01 Sinc filter #01 10 Minimum phase filter #10 Others Setting prohibited true 8 0x04 0-7 ADUOFTR%s User Offset Table Register %s 0x360 32 read-write 0x00000000 0xffffffff UOFSET User Offset Table n 0 15 read-write 8 0x04 0-7 ADUGTR%s User Gain Table Register %s 0x380 32 read-write 0x00400000 0xffffffff UGAIN User Gain Table n 0 23 read-write ADLIMINTCR Limiter Clip Interrupt Enable Register 0x3A0 32 read-write 0x00000000 0xffffffff LIMIE0 Limiter Clip Interrupt n Enable bit 0 0 read-write 0 Disable the limiter clip interrupt n #0 1 Enable the limiter clip interrupt n #1 LIMIE1 Limiter Clip Interrupt n Enable bit 1 1 read-write 0 Disable the limiter clip interrupt n #0 1 Enable the limiter clip interrupt n #1 LIMIE2 Limiter Clip Interrupt n Enable bit 2 2 read-write 0 Disable the limiter clip interrupt n #0 1 Enable the limiter clip interrupt n #1 LIMIE3 Limiter Clip Interrupt n Enable bit 3 3 read-write 0 Disable the limiter clip interrupt n #0 1 Enable the limiter clip interrupt n #1 LIMIE4 Limiter Clip Interrupt n Enable bit 4 4 read-write 0 Disable the limiter clip interrupt n #0 1 Enable the limiter clip interrupt n #1 LIMIE5 Limiter Clip Interrupt n Enable bit 5 5 read-write 0 Disable the limiter clip interrupt n #0 1 Enable the limiter clip interrupt n #1 LIMIE6 Limiter Clip Interrupt n Enable bit 6 6 read-write 0 Disable the limiter clip interrupt n #0 1 Enable the limiter clip interrupt n #1 LIMIE7 Limiter Clip Interrupt n Enable bit 7 7 read-write 0 Disable the limiter clip interrupt n #0 1 Enable the limiter clip interrupt n #1 LIMIE8 Limiter Clip Interrupt n Enable bit 8 8 read-write 0 Disable the limiter clip interrupt n #0 1 Enable the limiter clip interrupt n #1 8 0x04 0-7 ADLIMTR%s Limiter Clip Table Register %s 0x3A4 32 read-write 0x00000000 0xffffffff LIML Limiter clip table n : Lower-side limit value 0 15 read-write LIMU Limiter clip table n : Upper-side limit value 16 31 read-write ADCMPENR Compare Match Enable Register 0x400 32 read-write 0x00000000 0xffffffff CMPEN0 Compare Match n Enable 0 0 read-write 0 Disable the compare match n #0 1 Enable the compare match n #1 CMPEN1 Compare Match n Enable 1 1 read-write 0 Disable the compare match n #0 1 Enable the compare match n #1 CMPEN2 Compare Match n Enable 2 2 read-write 0 Disable the compare match n #0 1 Enable the compare match n #1 CMPEN3 Compare Match n Enable 3 3 read-write 0 Disable the compare match n #0 1 Enable the compare match n #1 CMPEN4 Compare Match n Enable 4 4 read-write 0 Disable the compare match n #0 1 Enable the compare match n #1 CMPEN5 Compare Match n Enable 5 5 read-write 0 Disable the compare match n #0 1 Enable the compare match n #1 CMPEN6 Compare Match n Enable 6 6 read-write 0 Disable the compare match n #0 1 Enable the compare match n #1 CMPEN7 Compare Match n Enable 7 7 read-write 0 Disable the compare match n #0 1 Enable the compare match n #1 ADCMPINTCR Compare Match Interrupt Enable Register 0x404 32 read-write 0x00000000 0xffffffff CMPIE0 Compare Match Interrupt n Enable 0 0 read-write 0 Disable the compare match interrupt n #0 1 Enable the compare match interrupt n #1 CMPIE1 Compare Match Interrupt n Enable 1 1 read-write 0 Disable the compare match interrupt n #0 1 Enable the compare match interrupt n #1 CMPIE2 Compare Match Interrupt n Enable 2 2 read-write 0 Disable the compare match interrupt n #0 1 Enable the compare match interrupt n #1 CMPIE3 Compare Match Interrupt n Enable 3 3 read-write 0 Disable the compare match interrupt n #0 1 Enable the compare match interrupt n #1 2 0x04 0-1 ADCCMPCR%s Composite Compare Match Configuration Register %s 0x408 32 read-write 0x00000000 0xffffffff CCMPCND Composite Compare Match Condition Selection 0 1 read-write 00 Logical disjunction (OR) conditions #00 01 Logical conjunction (AND) conditions #01 10 Logical exclusive disjunction (EXOR) conditions #10 11 Setting prohibited #11 CCMPTBL0 Composite Compare Match Condition Table Selection 16 16 read-write 0 Not use the compare match table m #0 1 Use the compare match table m #1 CCMPTBL1 Composite Compare Match Condition Table Selection 17 17 read-write 0 Not use the compare match table m #0 1 Use the compare match table m #1 CCMPTBL2 Composite Compare Match Condition Table Selection 18 18 read-write 0 Not use the compare match table m #0 1 Use the compare match table m #1 CCMPTBL3 Composite Compare Match Condition Table Selection 19 19 read-write 0 Not use the compare match table m #0 1 Use the compare match table m #1 CCMPTBL4 Composite Compare Match Condition Table Selection 20 20 read-write 0 Not use the compare match table m #0 1 Use the compare match table m #1 CCMPTBL5 Composite Compare Match Condition Table Selection 21 21 read-write 0 Not use the compare match table m #0 1 Use the compare match table m #1 CCMPTBL6 Composite Compare Match Condition Table Selection 22 22 read-write 0 Not use the compare match table m #0 1 Use the compare match table m #1 CCMPTBL7 Composite Compare Match Condition Table Selection 23 23 read-write 0 Not use the compare match table m #0 1 Use the compare match table m #1 ADCMPMDR0 Compare Match Mode Selection Register 0 0x448 32 read-write 0x00000000 0xffffffff CMPMD0 Compare Match 0 : Match Mode Selection 0 1 read-write 00 Generate the match event when high-side level or more #00 01 Generate the match event when low-side level or less #01 10 Generate the match event when high-side level or more, or low-side level or less #10 11 Generate the match event when low-side level or more and high-side level or less #11 CMPMD1 Compare Match 1 : Match Mode Selection 8 9 read-write 00 Generate the match event when high-side level or more #00 01 Generate the match event when low-side level or less #01 10 Generate the match event when high-side level or more, or low-side level or less #10 11 Generate the match event when low-side level or more and high-side level or less #11 CMPMD2 Compare Match 2 : Match Mode Selection 16 17 read-write 00 Generate the match event when high-side level or more #00 01 Generate the match event when low-side level or less #01 10 Generate the match event when high-side level or more, or low-side level or less #10 11 Generate the match event when low-side level or more and high-side level or less #11 CMPMD3 Compare Match 3 : Match Mode Selection 24 25 read-write 00 Generate the match event when high-side level or more #00 01 Generate the match event when low-side level or less #01 10 Generate the match event when high-side level or more, or low-side level or less #10 11 Generate the match event when low-side level or more and high-side level or less #11 ADCMPMDR1 Compare Match Mode Selection Register 1 0x44C 32 read-write 0x00000000 0xffffffff CMPMD4 Compare Match 4 : Match Mode Selection 0 1 read-write 00 Generate the match event when high-side level or more #00 01 Generate the match event when low-side level or less #01 10 Generate the match event when high-side level or more, or low-side level or less #10 11 Generate the match event when low-side level or more and high-side level or less #11 CMPMD5 Compare Match 5 : Match Mode Selection 8 9 read-write 00 Generate the match event when high-side level or more #00 01 Generate the match event when low-side level or less #01 10 Generate the match event when high-side level or more, or low-side level or less #10 11 Generate the match event when low-side level or more and high-side level or less #11 CMPMD6 Compare Match 6 : Match Mode Selection 16 17 read-write 00 Generate the match event when high-side level or more #00 01 Generate the match event when low-side level or less #01 10 Generate the match event when high-side level or more, or low-side level or less #10 11 Generate the match event when low-side level or more and high-side level or less #11 CMPMD7 Compare Match 7 : Match Mode Selection 24 25 read-write 00 Generate the match event when high-side level or more #00 01 Generate the match event when low-side level or less #01 10 Generate the match event when high-side level or more, or low-side level or less #10 11 Generate the match event when low-side level or more and high-side level or less #11 8 0x04 0-7 ADCMPTBR%s Compare Match Table Register %s 0x458 32 read-write 0xffff0000 0xffffffff CMPTBL Compare Match Table n : Low-side level 0 15 read-write CMPTBH Compare Match Table n : High-side level 16 31 read-write ADFIFOCR FIFO Control Register 0x4C0 32 read-write 0x00000000 0xffffffff FIFOEN0 Scan Group n FIFO Enable 0 0 read-write 0 Disable scan group n FIFO function #0 1 Enable scan group n FIFO function #1 FIFOEN1 Scan Group n FIFO Enable 1 1 read-write 0 Disable scan group n FIFO function #0 1 Enable scan group n FIFO function #1 FIFOEN2 Scan Group n FIFO Enable 2 2 read-write 0 Disable scan group n FIFO function #0 1 Enable scan group n FIFO function #1 FIFOEN3 Scan Group n FIFO Enable 3 3 read-write 0 Disable scan group n FIFO function #0 1 Enable scan group n FIFO function #1 FIFOEN4 Scan Group n FIFO Enable 4 4 read-write 0 Disable scan group n FIFO function #0 1 Enable scan group n FIFO function #1 FIFOEN5 Scan Group n FIFO Enable 5 5 read-write 0 Disable scan group n FIFO function #0 1 Enable scan group n FIFO function #1 FIFOEN6 Scan Group n FIFO Enable 6 6 read-write 0 Disable scan group n FIFO function #0 1 Enable scan group n FIFO function #1 FIFOEN7 Scan Group n FIFO Enable 7 7 read-write 0 Disable scan group n FIFO function #0 1 Enable scan group n FIFO function #1 FIFOEN8 Scan Group n FIFO Enable 8 8 read-write 0 Disable scan group n FIFO function #0 1 Enable scan group n FIFO function #1 ADFIFOINTCR FIFO Interrupt Control Register 0x4C4 32 read-write 0x00000000 0xffffffff FIFOIE0 Scan Group n FIFO Interrupt Enable 0 0 read-write 0 Disable scan group n FIFO interrupt #0 1 Enable scan group n FIFO interrupt #1 FIFOIE1 Scan Group n FIFO Interrupt Enable 1 1 read-write 0 Disable scan group n FIFO interrupt #0 1 Enable scan group n FIFO interrupt #1 FIFOIE2 Scan Group n FIFO Interrupt Enable 2 2 read-write 0 Disable scan group n FIFO interrupt #0 1 Enable scan group n FIFO interrupt #1 FIFOIE3 Scan Group n FIFO Interrupt Enable 3 3 read-write 0 Disable scan group n FIFO interrupt #0 1 Enable scan group n FIFO interrupt #1 FIFOIE4 Scan Group n FIFO Interrupt Enable 4 4 read-write 0 Disable scan group n FIFO interrupt #0 1 Enable scan group n FIFO interrupt #1 FIFOIE5 Scan Group n FIFO Interrupt Enable 5 5 read-write 0 Disable scan group n FIFO interrupt #0 1 Enable scan group n FIFO interrupt #1 FIFOIE6 Scan Group n FIFO Interrupt Enable 6 6 read-write 0 Disable scan group n FIFO interrupt #0 1 Enable scan group n FIFO interrupt #1 FIFOIE7 Scan Group n FIFO Interrupt Enable 7 7 read-write 0 Disable scan group n FIFO interrupt #0 1 Enable scan group n FIFO interrupt #1 FIFOIE8 Scan Group n FIFO Interrupt Enable 8 8 read-write 0 Disable scan group n FIFO interrupt #0 1 Enable scan group n FIFO interrupt #1 ADFIFOINTLR0 FIFO Interrupt Generation Level Register 0 0x4C8 32 read-write 0x00000000 0xffffffff FIFOILV0 Scan Group 0 FIFO Interrupt Output Timing Setting 0 3 read-write FIFOILV1 Scan Group 1 FIFO Interrupt Output Timing Setting 16 19 read-write ADFIFOINTLR1 FIFO Interrupt Generation Level Register 1 0x4CC 32 read-write 0x00000000 0xffffffff FIFOILV2 Scan Group 2 FIFO Interrupt Output Timing Setting 0 3 read-write FIFOILV3 Scan Group 3 FIFO Interrupt Output Timing Setting 16 19 read-write ADFIFOINTLR2 FIFO Interrupt Generation Level Register 2 0x4D0 32 read-write 0x00000000 0xffffffff FIFOILV4 Scan Group 4 FIFO Interrupt Output Timing Setting 0 3 read-write FIFOILV5 Scan Group 5 FIFO Interrupt Output Timing Setting 16 19 read-write ADFIFOINTLR3 FIFO Interrupt Generation Level Register 3 0x4D4 32 read-write 0x00000000 0xffffffff FIFOILV6 Scan Group 6 FIFO Interrupt Output Timing Setting 0 3 read-write FIFOILV7 Scan Group 7 FIFO Interrupt Output Timing Setting 16 19 read-write ADFIFOINTLR4 FIFO Interrupt Generation Level Register 4 0x4D8 32 read-write 0x00000000 0xffffffff FIFOILV8 Scan Group 8 FIFO Interrupt Output Timing Setting 0 3 read-write 37 0x10 0-36 ADCHCR%s A/D Conversion Channel Configuration Register %s 0x600 32 read-write 0x00000000 0xffffffff SGSEL Scan Group Selection 0 4 read-write CNVCS A/D Conversion Channel Selection 8 14 read-write AINMD Analog Input mode selection 15 15 read-write 0 Single-ended input #0 1 Differential input #1 SSTSEL Sampling State Table Selection 16 19 read-write 37 0x10 0-36 ADDOPCRA%s A/D Conversion Data Operation Control A Register %s 0x604 32 read-write 0x00000000 0xffffffff DFSEL Digital Filter Selection 0 2 read-write 0x0 Not use the digital filter 0x0 0x1 Use the 1st digital filter 0x1 0x2 Use the 2nd digital filter 0x2 0x3 Use the 3rd digital filter 0x3 0x4 Use the 4th digital filter 0x4 Others Setting prohibited true GAINSEL User Gain Table Selection 16 19 read-write OFSETSEL User Offset Table Selection 24 27 read-write 37 0x10 0-36 ADDOPCRB%s A/D Conversion Data Operation Control B Register %s 0x608 32 read-write 0x00000000 0xffffffff AVEMD Addition/Averaging Mode Selection 0 1 read-write 00 Not use Addition/Averaging mode #00 01 Addition mode #01 10 Averaging mode #10 11 Setting prohibited #11 ADC Addition/Averaging Times Selection 8 11 read-write 0x0 1-time conversion (no addition, same as normal conversion) 0x0 0x1 2-time conversion (1 addition) 0x1 0x3 4-time conversion (3 additions) 0x3 0x4 8-time conversion (7 additions) 0x4 0x5 16-time conversion (15 additions) 0x5 0x6 32-time conversion (31 additions) 0x6 0x7 64-time conversion (63 additions) 0x7 0x8 128-time conversion (127 additions) 0x8 0x9 256-time conversion (255 additions) 0x9 0xA 512-time conversion (511 additions) 0xa 0xB 1024-time conversion (1023 additions) 0xb Others Setting prohibited true CMPTBLE0 Compare Match Enable 16 16 read-write 0 Disable the compare match with the compare match table m #0 1 Enable the compare match with the compare match table m #1 CMPTBLE1 Compare Match Enable 17 17 read-write 0 Disable the compare match with the compare match table m #0 1 Enable the compare match with the compare match table m #1 CMPTBLE2 Compare Match Enable 18 18 read-write 0 Disable the compare match with the compare match table m #0 1 Enable the compare match with the compare match table m #1 CMPTBLE3 Compare Match Enable 19 19 read-write 0 Disable the compare match with the compare match table m #0 1 Enable the compare match with the compare match table m #1 CMPTBLE4 Compare Match Enable 20 20 read-write 0 Disable the compare match with the compare match table m #0 1 Enable the compare match with the compare match table m #1 CMPTBLE5 Compare Match Enable 21 21 read-write 0 Disable the compare match with the compare match table m #0 1 Enable the compare match with the compare match table m #1 CMPTBLE6 Compare Match Enable 22 22 read-write 0 Disable the compare match with the compare match table m #0 1 Enable the compare match with the compare match table m #1 CMPTBLE7 Compare Match Enable 23 23 read-write 0 Disable the compare match with the compare match table m #0 1 Enable the compare match with the compare match table m #1 37 0x10 0-36 ADDOPCRC%s A/D Conversion Data Operation Control C Register %s 0x60C 32 read-write 0x00000000 0xffffffff LIMTBLS Limiter Clip Table Selection 0 3 read-write ADPRC A/D Conversion Data Format Selection 16 17 read-write 00 Store the A/D conversion result as 16-bit data format #00 01 Store the A/D conversion result as 14-bit data format #01 10 Store the A/D conversion result as 12-bit data format #10 11 Store the A/D conversion result as 10-bit data format #11 SIGNSEL A/D Conversion Data Signed/Un-signed Selection 20 20 read-write 0 Signed data format #0 1 Un-signed data format #1 ADCALSTR A/D Converter Self-calibration Start Register 0xC00 32 write-only 0x00000000 0xffffffff ADCALST0 A/D Converter Unit 0 (ADC0) Self-calibration Start Control 0 2 write-only ADCALST1 A/D Converter Unit 1 (ADC1) Self-calibration Start Control 8 10 write-only ADTRGENR A/D Conversion Start Trigger Enable Register 0xC08 32 read-write 0x00000000 0xffffffff STTRGEN0 Scan Group n A/D Conversion Start Trigger Enable 0 0 read-write 0 Disable the A/D conversion start trigger #0 1 Enable the A/D conversion start trigger #1 STTRGEN1 Scan Group n A/D Conversion Start Trigger Enable 1 1 read-write 0 Disable the A/D conversion start trigger #0 1 Enable the A/D conversion start trigger #1 STTRGEN2 Scan Group n A/D Conversion Start Trigger Enable 2 2 read-write 0 Disable the A/D conversion start trigger #0 1 Enable the A/D conversion start trigger #1 STTRGEN3 Scan Group n A/D Conversion Start Trigger Enable 3 3 read-write 0 Disable the A/D conversion start trigger #0 1 Enable the A/D conversion start trigger #1 STTRGEN4 Scan Group n A/D Conversion Start Trigger Enable 4 4 read-write 0 Disable the A/D conversion start trigger #0 1 Enable the A/D conversion start trigger #1 STTRGEN5 Scan Group n A/D Conversion Start Trigger Enable 5 5 read-write 0 Disable the A/D conversion start trigger #0 1 Enable the A/D conversion start trigger #1 STTRGEN6 Scan Group n A/D Conversion Start Trigger Enable 6 6 read-write 0 Disable the A/D conversion start trigger #0 1 Enable the A/D conversion start trigger #1 STTRGEN7 Scan Group n A/D Conversion Start Trigger Enable 7 7 read-write 0 Disable the A/D conversion start trigger #0 1 Enable the A/D conversion start trigger #1 STTRGEN8 Scan Group n A/D Conversion Start Trigger Enable 8 8 read-write 0 Disable the A/D conversion start trigger #0 1 Enable the A/D conversion start trigger #1 ADSYSTR A/D Conversion Synchronous Software Start Register 0xC10 32 write-only 0x00000000 0xffffffff ADSYST0 Scan Group n: A/D Conversion start 0 0 write-only 0 No effect #0 1 Start the A/D conversion of scan group n #1 ADSYST1 Scan Group n: A/D Conversion start 1 1 write-only 0 No effect #0 1 Start the A/D conversion of scan group n #1 ADSYST2 Scan Group n: A/D Conversion start 2 2 write-only 0 No effect #0 1 Start the A/D conversion of scan group n #1 ADSYST3 Scan Group n: A/D Conversion start 3 3 write-only 0 No effect #0 1 Start the A/D conversion of scan group n #1 ADSYST4 Scan Group n: A/D Conversion start 4 4 write-only 0 No effect #0 1 Start the A/D conversion of scan group n #1 ADSYST5 Scan Group n: A/D Conversion start 5 5 write-only 0 No effect #0 1 Start the A/D conversion of scan group n #1 ADSYST6 Scan Group n: A/D Conversion start 6 6 write-only 0 No effect #0 1 Start the A/D conversion of scan group n #1 ADSYST7 Scan Group n: A/D Conversion start 7 7 write-only 0 No effect #0 1 Start the A/D conversion of scan group n #1 ADSYST8 Scan Group n: A/D Conversion start 8 8 write-only 0 No effect #0 1 Start the A/D conversion of scan group n #1 9 0x04 0-8 ADSTR%s A/D Conversion Software Start Register %s 0xC20 32 write-only 0x00000000 0xffffffff ADST Scan Group n A/D Conversion Start 0 0 write-only 0 No effect #0 1 Start the A/D conversion of scan group n #1 ADSTOPR A/D Conversion Stop Register 0xC60 32 write-only 0x00000000 0xffffffff ADSTOP0 A/D Converter Unit 0 Force Stop 0 0 write-only 0 No effect #0 1 Force stop the operation of A/D converter unit 0 #1 ADSTOP1 A/D Converter Unit 1 Force Stop 8 8 write-only 0 No effect #0 1 Force stop the operation of A/D converter unit 1 #1 ADSR A/D Conversion Status Register 0xC80 32 read-only 0x00000000 0xffffffff ADACT0 A/D Converter Unit 0 (ADC0) A/D Conversion Status 0 0 read-only 0 ADC0 is not in A/D conversion #0 1 ADC0 is in A/D conversion #1 ADACT1 A/D Converter Unit 1 (ADC1) A/D Conversion Status 1 1 read-only 0 ADC1 is not in A/D conversion #0 1 ADC1 is in A/D conversion #1 CALACT0 A/D Converter Unit 0 (ADC0) : Calibration Status 16 16 read-only 0 ADC0 is not in the calibration operation #0 1 ADC0 is in the calibration operation #1 CALACT1 A/D Converter Unit 1 (ADC1) : Calibration Status 17 17 read-only 0 ADC1 is not in the calibration operation #0 1 ADC1 is in the calibration operation #1 ADGRSR Scan Group Status Register 0xC84 32 read-only 0x00000000 0xffffffff ACTGR0 Scan Group n Status 0 0 read-only 0 Scan group n is idle #0 1 Scan group n is in the scanning operation #1 ACTGR1 Scan Group n Status 1 1 read-only 0 Scan group n is idle #0 1 Scan group n is in the scanning operation #1 ACTGR2 Scan Group n Status 2 2 read-only 0 Scan group n is idle #0 1 Scan group n is in the scanning operation #1 ACTGR3 Scan Group n Status 3 3 read-only 0 Scan group n is idle #0 1 Scan group n is in the scanning operation #1 ACTGR4 Scan Group n Status 4 4 read-only 0 Scan group n is idle #0 1 Scan group n is in the scanning operation #1 ACTGR5 Scan Group n Status 5 5 read-only 0 Scan group n is idle #0 1 Scan group n is in the scanning operation #1 ACTGR6 Scan Group n Status 6 6 read-only 0 Scan group n is idle #0 1 Scan group n is in the scanning operation #1 ACTGR7 Scan Group n Status 7 7 read-only 0 Scan group n is idle #0 1 Scan group n is in the scanning operation #1 ACTGR8 Scan Group n Status 8 8 read-only 0 Scan group n is idle #0 1 Scan group n is in the scanning operation #1 ADERSR A/D Conversion Error Status Register 0xC88 32 read-only 0x00000000 0xffffffff ADERF0 A/D Converter Unit 0 (ADC0) Error Flag 0 0 read-only 0 Error is not detected #0 1 Error is detected #1 ADERF1 A/D Converter Unit 1 (ADC1) Error Flag 1 1 read-only 0 Error is not detected #0 1 Error is detected #1 ADERSCR A/D Conversion Error Status Clear Register 0xC8C 32 write-only 0x00000000 0xffffffff ADERCLR0 A/D Converter Unit 0 Error Flag Clear 0 0 write-only 0 No effect #0 1 ADERSR.ADERF0 is cleared #1 ADERCLR1 A/D Converter Unit 1 Error Flag Clear 1 1 write-only 0 No effect #0 1 ADERSR.ADERF1 is cleared #1 ADCALENDSR A/D Converter Calibration End Status Register 0xC98 32 read-only 0x00000000 0xffffffff CALENDF0 A/D Converter Unit 0 Calibration End flag 0 0 read-only 0 End of the calibration is not detected #0 1 End of the calibration is detected #1 CALENDF1 A/D Converter Unit 1 Calibration End flag 1 1 read-only 0 End of the calibration is not detected #0 1 End of the calibration is detected #1 ADCALENDSCR A/D Converter Calibration End Status Clear Register 0xC9C 32 write-only 0x00000000 0xffffffff CALENDC0 A/D Converter Unit 0 Calibration End Flag Clear 0 0 write-only 0 No effect #0 1 ADCALENDSR.CALENDF0 is cleared #1 CALENDC1 A/D Converter Unit 1 Calibration End Flag Clear 1 1 write-only 0 No effect #0 1 ADCALENDSR.CALENDF1 is cleared #1 ADOVFERSR A/D Conversion Overflow Error Status Register 0xCA0 32 read-only 0x00000000 0xffffffff ADOVFEF0 A/D Converter Unit 0 (ADC0) Overflow Error Flag 0 0 read-only 0 ADC0 overflow error is not detected #0 1 ADC0 overflow error is detected #1 ADOVFEF1 A/D Converter Unit 1 (ADC1) Overflow Error Flag 1 1 read-only 0 ADC1 overflow error is not detected #0 1 ADC1 overflow error is detected #1 ADOVFCHSR0 A/D Conversion Overflow Channel Status Register 0 0xCA4 32 read-only 0x00000000 0xffffffff OVFCHF0 Analog Channel n: Overflow Flag 0 0 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF1 Analog Channel n: Overflow Flag 1 1 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF2 Analog Channel n: Overflow Flag 2 2 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF3 Analog Channel n: Overflow Flag 3 3 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF4 Analog Channel n: Overflow Flag 4 4 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF5 Analog Channel n: Overflow Flag 5 5 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF6 Analog Channel n: Overflow Flag 6 6 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF7 Analog Channel n: Overflow Flag 7 7 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF8 Analog Channel n: Overflow Flag 8 8 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF9 Analog Channel n: Overflow Flag 9 9 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF10 Analog Channel n: Overflow Flag 10 10 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF11 Analog Channel n: Overflow Flag 11 11 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF12 Analog Channel n: Overflow Flag 12 12 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF13 Analog Channel n: Overflow Flag 13 13 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF14 Analog Channel n: Overflow Flag 14 14 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF15 Analog Channel n: Overflow Flag 15 15 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF16 Analog Channel n: Overflow Flag 16 16 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF17 Analog Channel n: Overflow Flag 17 17 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF18 Analog Channel n: Overflow Flag 18 18 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF19 Analog Channel n: Overflow Flag 19 19 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF20 Analog Channel n: Overflow Flag 20 20 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF21 Analog Channel n: Overflow Flag 21 21 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF22 Analog Channel n: Overflow Flag 22 22 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF23 Analog Channel n: Overflow Flag 23 23 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF24 Analog Channel n: Overflow Flag 24 24 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF25 Analog Channel n: Overflow Flag 25 25 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF26 Analog Channel n: Overflow Flag 26 26 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF27 Analog Channel n: Overflow Flag 27 27 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFCHF28 Analog Channel n: Overflow Flag 28 28 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 ADOVFEXSR Extended Analog A/D Conversion Overflow Status Register 0xCB0 32 read-only 0x00000000 0xffffffff OVFEXF0 Self-diagnosis Channel: Overflow Flag 0 0 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFEXF1 Temperature Sensor Channel: Overflow Flag 1 1 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFEXF2 Internal Reference Voltage Channel: Overflow Flag 2 2 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFEXF5 D/A Converter 0 Channel: Overflow Flag 5 5 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFEXF6 D/A Converter 1 Channel: Overflow Flag 6 6 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFEXF7 D/A Converter 2 Channel: Overflow Flag 7 7 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 OVFEXF8 D/A Converter 3 Channel: Overflow Flag 8 8 read-only 0 Overflow is not detected #0 1 Overflow is detected #1 ADOVFERSCR A/D Conversion Overflow Error Status Clear Register 0xCB4 32 write-only 0x00000000 0xffffffff ADOVFEC0 A/D Converter Unit 0 (ADC0) Overflow Error Flag Clear 0 0 write-only 0 No effect #0 1 ADOVFERSR.ADOVFEF0 is cleared #1 ADOVFEC1 A/D Converter Unit 1 (ADC1) Overflow Error Flag Clear 1 1 write-only 0 No effect #0 1 ADOVFERSR.ADOVFEF1 is cleared #1 ADOVFCHSCR0 A/D Conversion Overflow Channel Status Clear Register 0 0xCB8 32 write-only 0x00000000 0xffffffff OVFCHC0 Analog Channel n: Overflow Flag Clear 0 0 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC1 Analog Channel n: Overflow Flag Clear 1 1 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC2 Analog Channel n: Overflow Flag Clear 2 2 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC3 Analog Channel n: Overflow Flag Clear 3 3 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC4 Analog Channel n: Overflow Flag Clear 4 4 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC5 Analog Channel n: Overflow Flag Clear 5 5 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC6 Analog Channel n: Overflow Flag Clear 6 6 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC7 Analog Channel n: Overflow Flag Clear 7 7 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC8 Analog Channel n: Overflow Flag Clear 8 8 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC9 Analog Channel n: Overflow Flag Clear 9 9 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC10 Analog Channel n: Overflow Flag Clear 10 10 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC11 Analog Channel n: Overflow Flag Clear 11 11 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC12 Analog Channel n: Overflow Flag Clear 12 12 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC13 Analog Channel n: Overflow Flag Clear 13 13 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC14 Analog Channel n: Overflow Flag Clear 14 14 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC15 Analog Channel n: Overflow Flag Clear 15 15 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC16 Analog Channel n: Overflow Flag Clear 16 16 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC17 Analog Channel n: Overflow Flag Clear 17 17 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC18 Analog Channel n: Overflow Flag Clear 18 18 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC19 Analog Channel n: Overflow Flag Clear 19 19 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC20 Analog Channel n: Overflow Flag Clear 20 20 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC21 Analog Channel n: Overflow Flag Clear 21 21 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC22 Analog Channel n: Overflow Flag Clear 22 22 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC23 Analog Channel n: Overflow Flag Clear 23 23 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC24 Analog Channel n: Overflow Flag Clear 24 24 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC25 Analog Channel n: Overflow Flag Clear 25 25 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC26 Analog Channel n: Overflow Flag Clear 26 26 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC27 Analog Channel n: Overflow Flag Clear 27 27 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 OVFCHC28 Analog Channel n: Overflow Flag Clear 28 28 write-only 0 No effect #0 1 ADOVFCHSR0.OVFCHFn is cleared #1 ADOVFEXSCR Extended Analog A/D Conversion Overflow Status Clear Register 0xCC4 32 write-only 0x00000000 0xffffffff OVFEXC0 Self-diagnosis Channel: Overflow Flag Clear 0 0 write-only 0 No effect #0 1 ADOVFEXSR.OVFEXF0 is cleared #1 OVFEXC1 Temperature Sensor Channel: Overflow Flag Clear 1 1 write-only 0 No effect #0 1 ADOVFEXSR.OVFEXF1 is cleared #1 OVFEXC2 Internal Reference Voltage Channel: Overflow Flag Clear 2 2 write-only 0 No effect #0 1 ADOVFEXSR.OVFEXF2 is cleared #1 OVFEXC5 D/A Converter 0 Channel: Overflow Flag Clear 5 5 write-only 0 No effect #0 1 ADOVFEXSR.OVFEXF5 is cleared #1 OVFEXC6 D/A Converter 1 Channel: Overflow Flag Clear 6 6 write-only 0 No effect #0 1 ADOVFEXSR.OVFEXF6 is cleared #1 OVFEXC7 D/A Converter 2 Channel: Overflow Flag Clear 7 7 write-only 0 No effect #0 1 ADOVFEXSR.OVFEXF7 is cleared #1 OVFEXC8 D/A Converter 3 Channel: Overflow Flag Clear 8 8 write-only 0 No effect #0 1 ADOVFEXSR.OVFEXF8 is cleared #1 ADFIFOSR0 FIFO Status Register 0 0xCD0 32 read-only 0x00080008 0xffffffff FIFOST0 Number of vacant stages in FIFO for Scan Group 0 0 3 read-only FIFOST1 Number of vacant stages in FIFO for Scan Group 1 16 19 read-only ADFIFOSR1 FIFO Status Register 1 0xCD4 32 read-only 0x00080008 0xffffffff FIFOST2 Number of vacant stages in FIFO for Scan Group 2 0 3 read-only FIFOST3 Number of vacant stages in FIFO for Scan Group 3 16 19 read-only ADFIFOSR2 FIFO Status Register 2 0xCD8 32 read-only 0x00080008 0xffffffff FIFOST4 Number of vacant stages in FIFO for Scan Group 4 0 3 read-only FIFOST5 Number of vacant stages in FIFO for Scan Group 5 16 19 read-only ADFIFOSR3 FIFO Status Register 3 0xCDC 32 read-only 0x00080008 0xffffffff FIFOST6 Number of vacant stages in FIFO for Scan Group 6 0 3 read-only FIFOST7 Number of vacant stages in FIFO for Scan Group 7 16 19 read-only ADFIFOSR4 FIFO Status Register 4 0xCE0 32 read-only 0x00000008 0xffffffff FIFOST8 Number of vacant stages in FIFO for Scan Group 8 0 3 read-only ADFIFODCR FIFO Data Clear Register 0xCF0 32 write-only 0x00000000 0xffffffff FIFODC0 Scan Group n FIFO Data Clear 0 0 write-only 0 No effect #0 1 Clear the data of scan group n FIFO #1 FIFODC1 Scan Group n FIFO Data Clear 1 1 write-only 0 No effect #0 1 Clear the data of scan group n FIFO #1 FIFODC2 Scan Group n FIFO Data Clear 2 2 write-only 0 No effect #0 1 Clear the data of scan group n FIFO #1 FIFODC3 Scan Group n FIFO Data Clear 3 3 write-only 0 No effect #0 1 Clear the data of scan group n FIFO #1 FIFODC4 Scan Group n FIFO Data Clear 4 4 write-only 0 No effect #0 1 Clear the data of scan group n FIFO #1 FIFODC5 Scan Group n FIFO Data Clear 5 5 write-only 0 No effect #0 1 Clear the data of scan group n FIFO #1 FIFODC6 Scan Group n FIFO Data Clear 6 6 write-only 0 No effect #0 1 Clear the data of scan group n FIFO #1 FIFODC7 Scan Group n FIFO Data Clear 7 7 write-only 0 No effect #0 1 Clear the data of scan group n FIFO #1 FIFODC8 Scan Group n FIFO Data Clear 8 8 write-only 0 No effect #0 1 Clear the data of scan group n FIFO #1 ADFIFOERSR FIFO Error Status Register 0xCF4 32 read-only 0x00000000 0xffffffff FIFOOVF0 Scan Group n FIFO Overflow Flag 0 0 read-only 0 No overflow #0 1 FIFO overflow is detected #1 FIFOOVF1 Scan Group n FIFO Overflow Flag 1 1 read-only 0 No overflow #0 1 FIFO overflow is detected #1 FIFOOVF2 Scan Group n FIFO Overflow Flag 2 2 read-only 0 No overflow #0 1 FIFO overflow is detected #1 FIFOOVF3 Scan Group n FIFO Overflow Flag 3 3 read-only 0 No overflow #0 1 FIFO overflow is detected #1 FIFOOVF4 Scan Group n FIFO Overflow Flag 4 4 read-only 0 No overflow #0 1 FIFO overflow is detected #1 FIFOOVF5 Scan Group n FIFO Overflow Flag 5 5 read-only 0 No overflow #0 1 FIFO overflow is detected #1 FIFOOVF6 Scan Group n FIFO Overflow Flag 6 6 read-only 0 No overflow #0 1 FIFO overflow is detected #1 FIFOOVF7 Scan Group n FIFO Overflow Flag 7 7 read-only 0 No overflow #0 1 FIFO overflow is detected #1 FIFOOVF8 Scan Group n FIFO Overflow Flag 8 8 read-only 0 No overflow #0 1 FIFO overflow is detected #1 FIFOFLF0 Scan Group n FIFO Data Read Request Flag 16 16 read-only 0 FIFO Data Read Request is not detected. #0 1 FIFO Data Read Request is detected. #1 FIFOFLF1 Scan Group n FIFO Data Read Request Flag 17 17 read-only 0 FIFO Data Read Request is not detected. #0 1 FIFO Data Read Request is detected. #1 FIFOFLF2 Scan Group n FIFO Data Read Request Flag 18 18 read-only 0 FIFO Data Read Request is not detected. #0 1 FIFO Data Read Request is detected. #1 FIFOFLF3 Scan Group n FIFO Data Read Request Flag 19 19 read-only 0 FIFO Data Read Request is not detected. #0 1 FIFO Data Read Request is detected. #1 FIFOFLF4 Scan Group n FIFO Data Read Request Flag 20 20 read-only 0 FIFO Data Read Request is not detected. #0 1 FIFO Data Read Request is detected. #1 FIFOFLF5 Scan Group n FIFO Data Read Request Flag 21 21 read-only 0 FIFO Data Read Request is not detected. #0 1 FIFO Data Read Request is detected. #1 FIFOFLF6 Scan Group n FIFO Data Read Request Flag 22 22 read-only 0 FIFO Data Read Request is not detected. #0 1 FIFO Data Read Request is detected. #1 FIFOFLF7 Scan Group n FIFO Data Read Request Flag 23 23 read-only 0 FIFO Data Read Request is not detected. #0 1 FIFO Data Read Request is detected. #1 FIFOFLF8 Scan Group n FIFO Data Read Request Flag 24 24 read-only 0 FIFO Data Read Request is not detected. #0 1 FIFO Data Read Request is detected. #1 ADFIFOERSCR FIFO Error Status Clear Register 0xCF8 32 write-only 0x00000000 0xffffffff FIFOOVFC0 Scan Group n FIFO Overflow Flag Clear 0 0 write-only 0 No effect #0 1 ADFIFOERSR.FIFOOVFn is cleared #1 FIFOOVFC1 Scan Group n FIFO Overflow Flag Clear 1 1 write-only 0 No effect #0 1 ADFIFOERSR.FIFOOVFn is cleared #1 FIFOOVFC2 Scan Group n FIFO Overflow Flag Clear 2 2 write-only 0 No effect #0 1 ADFIFOERSR.FIFOOVFn is cleared #1 FIFOOVFC3 Scan Group n FIFO Overflow Flag Clear 3 3 write-only 0 No effect #0 1 ADFIFOERSR.FIFOOVFn is cleared #1 FIFOOVFC4 Scan Group n FIFO Overflow Flag Clear 4 4 write-only 0 No effect #0 1 ADFIFOERSR.FIFOOVFn is cleared #1 FIFOOVFC5 Scan Group n FIFO Overflow Flag Clear 5 5 write-only 0 No effect #0 1 ADFIFOERSR.FIFOOVFn is cleared #1 FIFOOVFC6 Scan Group n FIFO Overflow Flag Clear 6 6 write-only 0 No effect #0 1 ADFIFOERSR.FIFOOVFn is cleared #1 FIFOOVFC7 Scan Group n FIFO Overflow Flag Clear 7 7 write-only 0 No effect #0 1 ADFIFOERSR.FIFOOVFn is cleared #1 FIFOOVFC8 Scan Group n FIFO Overflow Flag Clear 8 8 write-only 0 No effect #0 1 ADFIFOERSR.FIFOOVFn is cleared #1 FIFOFLC0 Scan Group n FIFO Data Read Request Flag Clear 16 16 write-only 0 No effect #0 1 ADFIFOERSR.FIFOFLFn is cleared #1 FIFOFLC1 Scan Group n FIFO Data Read Request Flag Clear 17 17 write-only 0 No effect #0 1 ADFIFOERSR.FIFOFLFn is cleared #1 FIFOFLC2 Scan Group n FIFO Data Read Request Flag Clear 18 18 write-only 0 No effect #0 1 ADFIFOERSR.FIFOFLFn is cleared #1 FIFOFLC3 Scan Group n FIFO Data Read Request Flag Clear 19 19 write-only 0 No effect #0 1 ADFIFOERSR.FIFOFLFn is cleared #1 FIFOFLC4 Scan Group n FIFO Data Read Request Flag Clear 20 20 write-only 0 No effect #0 1 ADFIFOERSR.FIFOFLFn is cleared #1 FIFOFLC5 Scan Group n FIFO Data Read Request Flag Clear 21 21 write-only 0 No effect #0 1 ADFIFOERSR.FIFOFLFn is cleared #1 FIFOFLC6 Scan Group n FIFO Data Read Request Flag Clear 22 22 write-only 0 No effect #0 1 ADFIFOERSR.FIFOFLFn is cleared #1 FIFOFLC7 Scan Group n FIFO Data Read Request Flag Clear 23 23 write-only 0 No effect #0 1 ADFIFOERSR.FIFOFLFn is cleared #1 FIFOFLC8 Scan Group n FIFO Data Read Request Flag Clear 24 24 write-only 0 No effect #0 1 ADFIFOERSR.FIFOFLFn is cleared #1 ADCMPTBSR Compare Match Table Status Register 0xD00 32 read-only 0x00000000 0xffffffff CMPTBF0 Compare Match Table n Match Flag 0 0 read-only 0 Match event with compare match table n is not detected #0 1 Match event with compare match table n is detected #1 CMPTBF1 Compare Match Table n Match Flag 1 1 read-only 0 Match event with compare match table n is not detected #0 1 Match event with compare match table n is detected #1 CMPTBF2 Compare Match Table n Match Flag 2 2 read-only 0 Match event with compare match table n is not detected #0 1 Match event with compare match table n is detected #1 CMPTBF3 Compare Match Table n Match Flag 3 3 read-only 0 Match event with compare match table n is not detected #0 1 Match event with compare match table n is detected #1 CMPTBF4 Compare Match Table n Match Flag 4 4 read-only 0 Match event with compare match table n is not detected #0 1 Match event with compare match table n is detected #1 CMPTBF5 Compare Match Table n Match Flag 5 5 read-only 0 Match event with compare match table n is not detected #0 1 Match event with compare match table n is detected #1 CMPTBF6 Compare Match Table n Match Flag 6 6 read-only 0 Match event with compare match table n is not detected #0 1 Match event with compare match table n is detected #1 CMPTBF7 Compare Match Table n Match Flag 7 7 read-only 0 Match event with compare match table n is not detected #0 1 Match event with compare match table n is detected #1 ADCMPTBSCR Compare Match Table Status Clear Register 0xD04 32 write-only 0x00000000 0xffffffff CMPTBC0 Compare Match Table n: Match Flag Clear 0 0 write-only 0 No effect #0 1 ADCMPTBSR.CMPTBFn is cleared #1 CMPTBC1 Compare Match Table n: Match Flag Clear 1 1 write-only 0 No effect #0 1 ADCMPTBSR.CMPTBFn is cleared #1 CMPTBC2 Compare Match Table n: Match Flag Clear 2 2 write-only 0 No effect #0 1 ADCMPTBSR.CMPTBFn is cleared #1 CMPTBC3 Compare Match Table n: Match Flag Clear 3 3 write-only 0 No effect #0 1 ADCMPTBSR.CMPTBFn is cleared #1 CMPTBC4 Compare Match Table n: Match Flag Clear 4 4 write-only 0 No effect #0 1 ADCMPTBSR.CMPTBFn is cleared #1 CMPTBC5 Compare Match Table n: Match Flag Clear 5 5 write-only 0 No effect #0 1 ADCMPTBSR.CMPTBFn is cleared #1 CMPTBC6 Compare Match Table n: Match Flag Clear 6 6 write-only 0 No effect #0 1 ADCMPTBSR.CMPTBFn is cleared #1 CMPTBC7 Compare Match Table n: Match Flag Clear 7 7 write-only 0 No effect #0 1 ADCMPTBSR.CMPTBFn is cleared #1 ADCMPCHSR0 Compare Match Channel Status Register 0 0xD08 32 read-only 0x00000000 0xffffffff CMPCHF0 Analog Channel n: Compare Match Flag 0 0 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF1 Analog Channel n: Compare Match Flag 1 1 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF2 Analog Channel n: Compare Match Flag 2 2 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF3 Analog Channel n: Compare Match Flag 3 3 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF4 Analog Channel n: Compare Match Flag 4 4 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF5 Analog Channel n: Compare Match Flag 5 5 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF6 Analog Channel n: Compare Match Flag 6 6 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF7 Analog Channel n: Compare Match Flag 7 7 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF8 Analog Channel n: Compare Match Flag 8 8 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF9 Analog Channel n: Compare Match Flag 9 9 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF10 Analog Channel n: Compare Match Flag 10 10 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF11 Analog Channel n: Compare Match Flag 11 11 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF12 Analog Channel n: Compare Match Flag 12 12 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF13 Analog Channel n: Compare Match Flag 13 13 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF14 Analog Channel n: Compare Match Flag 14 14 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF15 Analog Channel n: Compare Match Flag 15 15 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF16 Analog Channel n: Compare Match Flag 16 16 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF17 Analog Channel n: Compare Match Flag 17 17 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF18 Analog Channel n: Compare Match Flag 18 18 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF19 Analog Channel n: Compare Match Flag 19 19 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF20 Analog Channel n: Compare Match Flag 20 20 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF21 Analog Channel n: Compare Match Flag 21 21 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF22 Analog Channel n: Compare Match Flag 22 22 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF23 Analog Channel n: Compare Match Flag 23 23 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF24 Analog Channel n: Compare Match Flag 24 24 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF25 Analog Channel n: Compare Match Flag 25 25 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF26 Analog Channel n: Compare Match Flag 26 26 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF27 Analog Channel n: Compare Match Flag 27 27 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPCHF28 Analog Channel n: Compare Match Flag 28 28 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 ADCMPEXSR Extended Analog Compare Match Status Register 0xD14 32 read-only 0x00000000 0xffffffff CMPEXF0 Self-diagnosis Channel: Compare Match Flag 0 0 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPEXF1 Temperature Sensor Channel: Compare Match Flag 1 1 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPEXF2 Internal Reference Voltage Channel: Compare Match Flag 2 2 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPEXF5 D/A Converter 0 Channel: Compare Match Flag 5 5 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPEXF6 D/A Converter 1 Channel: Compare Match Flag 6 6 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPEXF7 D/A Converter 2 Channel: Compare Match Flag 7 7 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 CMPEXF8 D/A Converter 3 Channel: Compare Match Flag 8 8 read-only 0 Compare match is not detected #0 1 Compare match is detected #1 ADCMPCHSCR0 Compare Match Channel Status Clear Register 0 0xD18 32 write-only 0x00000000 0xffffffff CMPCHC0 Analog Channel n: Compare Match Flag Clear bit 0 0 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC1 Analog Channel n: Compare Match Flag Clear bit 1 1 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC2 Analog Channel n: Compare Match Flag Clear bit 2 2 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC3 Analog Channel n: Compare Match Flag Clear bit 3 3 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC4 Analog Channel n: Compare Match Flag Clear bit 4 4 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC5 Analog Channel n: Compare Match Flag Clear bit 5 5 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC6 Analog Channel n: Compare Match Flag Clear bit 6 6 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC7 Analog Channel n: Compare Match Flag Clear bit 7 7 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC8 Analog Channel n: Compare Match Flag Clear bit 8 8 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC9 Analog Channel n: Compare Match Flag Clear bit 9 9 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC10 Analog Channel n: Compare Match Flag Clear bit 10 10 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC11 Analog Channel n: Compare Match Flag Clear bit 11 11 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC12 Analog Channel n: Compare Match Flag Clear bit 12 12 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC13 Analog Channel n: Compare Match Flag Clear bit 13 13 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC14 Analog Channel n: Compare Match Flag Clear bit 14 14 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC15 Analog Channel n: Compare Match Flag Clear bit 15 15 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC16 Analog Channel n: Compare Match Flag Clear bit 16 16 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC17 Analog Channel n: Compare Match Flag Clear bit 17 17 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC18 Analog Channel n: Compare Match Flag Clear bit 18 18 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC19 Analog Channel n: Compare Match Flag Clear bit 19 19 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC20 Analog Channel n: Compare Match Flag Clear bit 20 20 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC21 Analog Channel n: Compare Match Flag Clear bit 21 21 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC22 Analog Channel n: Compare Match Flag Clear bit 22 22 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC23 Analog Channel n: Compare Match Flag Clear bit 23 23 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC24 Analog Channel n: Compare Match Flag Clear bit 24 24 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC25 Analog Channel n: Compare Match Flag Clear bit 25 25 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC26 Analog Channel n: Compare Match Flag Clear bit 26 26 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC27 Analog Channel n: Compare Match Flag Clear bit 27 27 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 CMPCHC28 Analog Channel n: Compare Match Flag Clear bit 28 28 write-only 0 No effect #0 1 ADCMPCHSR0.CMPCHFn is cleared #1 ADCMPEXSCR Extended Analog Compare Match Status Clear Register 0xD24 32 write-only 0x00000000 0xffffffff CMPEXC0 Self-diagnosis Channel: Compare Match Flag Clear 0 0 write-only 0 No effect #0 1 ADCMPEXSR.CMPEXF0 is cleared #1 CMPEXC1 Temperature Sensor Channel: Compare Match Flag Clear 1 1 write-only 0 No effect #0 1 ADCMPEXSR.CMPEXF1 is cleared #1 CMPEXC2 Internal Reference Voltage Channel: Compare Match Flag Clear 2 2 write-only 0 No effect #0 1 ADCMPEXSR.CMPEXF2 is cleared #1 CMPEXC5 D/A Converter 0 Channel: Compare Match Flag Clear 5 5 write-only 0 No effect #0 1 ADCMPEXSR.CMPEXF5 is cleared #1 CMPEXC6 D/A Converter 1 Channel: Compare Match Flag Clear 6 6 write-only 0 No effect #0 1 ADCMPEXSR.CMPEXF6 is cleared #1 CMPEXC7 D/A Converter 2 Channel: Compare Match Flag Clear 7 7 write-only 0 No effect #0 1 ADCMPEXSR.CMPEXF7 is cleared #1 CMPEXC8 D/A Converter 3 Channel: Compare Match Flag Clear 8 8 write-only 0 No effect #0 1 ADCMPEXSR.CMPEXF8 is cleared #1 ADLIMGRSR Limiter Clip Scan Group Status Register 0xD28 32 read-only 0x00000000 0xffffffff LIMGRF0 Scan Group n Limiter Clip Flag 0 0 read-only 0 Limiter clip for scan group n is not detected #0 1 Limiter clip for scan group n is detected #1 LIMGRF1 Scan Group n Limiter Clip Flag 1 1 read-only 0 Limiter clip for scan group n is not detected #0 1 Limiter clip for scan group n is detected #1 LIMGRF2 Scan Group n Limiter Clip Flag 2 2 read-only 0 Limiter clip for scan group n is not detected #0 1 Limiter clip for scan group n is detected #1 LIMGRF3 Scan Group n Limiter Clip Flag 3 3 read-only 0 Limiter clip for scan group n is not detected #0 1 Limiter clip for scan group n is detected #1 LIMGRF4 Scan Group n Limiter Clip Flag 4 4 read-only 0 Limiter clip for scan group n is not detected #0 1 Limiter clip for scan group n is detected #1 LIMGRF5 Scan Group n Limiter Clip Flag 5 5 read-only 0 Limiter clip for scan group n is not detected #0 1 Limiter clip for scan group n is detected #1 LIMGRF6 Scan Group n Limiter Clip Flag 6 6 read-only 0 Limiter clip for scan group n is not detected #0 1 Limiter clip for scan group n is detected #1 LIMGRF7 Scan Group n Limiter Clip Flag 7 7 read-only 0 Limiter clip for scan group n is not detected #0 1 Limiter clip for scan group n is detected #1 LIMGRF8 Scan Group n Limiter Clip Flag 8 8 read-only 0 Limiter clip for scan group n is not detected #0 1 Limiter clip for scan group n is detected #1 ADLIMCHSR0 Limiter Clip Channel Status Register 0 0xD2C 32 read-only 0x00000000 0xffffffff LIMCHF0 Analog Channel n: Limiter Clip Flag 0 0 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF1 Analog Channel n: Limiter Clip Flag 1 1 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF2 Analog Channel n: Limiter Clip Flag 2 2 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF3 Analog Channel n: Limiter Clip Flag 3 3 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF4 Analog Channel n: Limiter Clip Flag 4 4 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF5 Analog Channel n: Limiter Clip Flag 5 5 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF6 Analog Channel n: Limiter Clip Flag 6 6 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF7 Analog Channel n: Limiter Clip Flag 7 7 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF8 Analog Channel n: Limiter Clip Flag 8 8 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF9 Analog Channel n: Limiter Clip Flag 9 9 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF10 Analog Channel n: Limiter Clip Flag 10 10 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF11 Analog Channel n: Limiter Clip Flag 11 11 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF12 Analog Channel n: Limiter Clip Flag 12 12 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF13 Analog Channel n: Limiter Clip Flag 13 13 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF14 Analog Channel n: Limiter Clip Flag 14 14 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF15 Analog Channel n: Limiter Clip Flag 15 15 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF16 Analog Channel n: Limiter Clip Flag 16 16 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF17 Analog Channel n: Limiter Clip Flag 17 17 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF18 Analog Channel n: Limiter Clip Flag 18 18 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF19 Analog Channel n: Limiter Clip Flag 19 19 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF20 Analog Channel n: Limiter Clip Flag 20 20 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF21 Analog Channel n: Limiter Clip Flag 21 21 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF22 Analog Channel n: Limiter Clip Flag 22 22 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF23 Analog Channel n: Limiter Clip Flag 23 23 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF24 Analog Channel n: Limiter Clip Flag 24 24 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF25 Analog Channel n: Limiter Clip Flag 25 25 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF26 Analog Channel n: Limiter Clip Flag 26 26 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF27 Analog Channel n: Limiter Clip Flag 27 27 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMCHF28 Analog Channel n: Limiter Clip Flag 28 28 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 ADLIMEXSR Extended Analog Limiter Clip Status Register 0xD38 32 read-only 0x00000000 0xffffffff LIMEXF0 Self-diagnosis Channel: Limiter Clip Flag 0 0 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMEXF1 Temperature Sensor Channel: Limiter Clip Flag 1 1 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMEXF2 Internal Reference Voltage Channel: Limiter Clip Flag 2 2 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMEXF5 D/A Converter 0 Channel: Limiter Clip Flag 5 5 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMEXF6 D/A Converter 1 Channel: Limiter Clip Flag 6 6 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMEXF7 D/A Converter 2 Channel: Limiter Clip Flag 7 7 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 LIMEXF8 D/A Converter 3 Channel: Limiter Clip Flag 8 8 read-only 0 Limiter clip is not detected #0 1 Limiter clip is detected #1 ADLIMGRSCR Limiter Clip Scan Group Status Clear Register 0xD3C 32 write-only 0x00000000 0xffffffff LIMGRC0 Scan Group n Limiter Clip Flag Clear 0 0 write-only 0 No effect #0 1 ADLIMGRSR.LIMGRFn is cleared #1 LIMGRC1 Scan Group n Limiter Clip Flag Clear 1 1 write-only 0 No effect #0 1 ADLIMGRSR.LIMGRFn is cleared #1 LIMGRC2 Scan Group n Limiter Clip Flag Clear 2 2 write-only 0 No effect #0 1 ADLIMGRSR.LIMGRFn is cleared #1 LIMGRC3 Scan Group n Limiter Clip Flag Clear 3 3 write-only 0 No effect #0 1 ADLIMGRSR.LIMGRFn is cleared #1 LIMGRC4 Scan Group n Limiter Clip Flag Clear 4 4 write-only 0 No effect #0 1 ADLIMGRSR.LIMGRFn is cleared #1 LIMGRC5 Scan Group n Limiter Clip Flag Clear 5 5 write-only 0 No effect #0 1 ADLIMGRSR.LIMGRFn is cleared #1 LIMGRC6 Scan Group n Limiter Clip Flag Clear 6 6 write-only 0 No effect #0 1 ADLIMGRSR.LIMGRFn is cleared #1 LIMGRC7 Scan Group n Limiter Clip Flag Clear 7 7 write-only 0 No effect #0 1 ADLIMGRSR.LIMGRFn is cleared #1 LIMGRC8 Scan Group n Limiter Clip Flag Clear 8 8 write-only 0 No effect #0 1 ADLIMGRSR.LIMGRFn is cleared #1 ADLIMCHSCR0 Limiter Clip Channel Status Clear Register 0 0xD40 32 write-only 0x00000000 0xffffffff LIMCHC0 Analog Channel n Limiter Clip Flag Clear bit 0 0 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC1 Analog Channel n Limiter Clip Flag Clear bit 1 1 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC2 Analog Channel n Limiter Clip Flag Clear bit 2 2 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC3 Analog Channel n Limiter Clip Flag Clear bit 3 3 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC4 Analog Channel n Limiter Clip Flag Clear bit 4 4 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC5 Analog Channel n Limiter Clip Flag Clear bit 5 5 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC6 Analog Channel n Limiter Clip Flag Clear bit 6 6 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC7 Analog Channel n Limiter Clip Flag Clear bit 7 7 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC8 Analog Channel n Limiter Clip Flag Clear bit 8 8 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC9 Analog Channel n Limiter Clip Flag Clear bit 9 9 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC10 Analog Channel n Limiter Clip Flag Clear bit 10 10 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC11 Analog Channel n Limiter Clip Flag Clear bit 11 11 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC12 Analog Channel n Limiter Clip Flag Clear bit 12 12 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC13 Analog Channel n Limiter Clip Flag Clear bit 13 13 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC14 Analog Channel n Limiter Clip Flag Clear bit 14 14 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC15 Analog Channel n Limiter Clip Flag Clear bit 15 15 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC16 Analog Channel n Limiter Clip Flag Clear bit 16 16 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC17 Analog Channel n Limiter Clip Flag Clear bit 17 17 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC18 Analog Channel n Limiter Clip Flag Clear bit 18 18 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC19 Analog Channel n Limiter Clip Flag Clear bit 19 19 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC20 Analog Channel n Limiter Clip Flag Clear bit 20 20 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC21 Analog Channel n Limiter Clip Flag Clear bit 21 21 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC22 Analog Channel n Limiter Clip Flag Clear bit 22 22 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC23 Analog Channel n Limiter Clip Flag Clear bit 23 23 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC24 Analog Channel n Limiter Clip Flag Clear bit 24 24 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC25 Analog Channel n Limiter Clip Flag Clear bit 25 25 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC26 Analog Channel n Limiter Clip Flag Clear bit 26 26 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC27 Analog Channel n Limiter Clip Flag Clear bit 27 27 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 LIMCHC28 Analog Channel n Limiter Clip Flag Clear bit 28 28 write-only 0 No effect #0 1 ADLIMCHSR0.LIMCHFn is cleared #1 ADLIMEXSCR Extended Analog Limiter Clip Status Clear Register 0xD4C 32 write-only 0x00000000 0xffffffff LIMEXF0 Self-diagnosis Channel: Limiter Clip Flag Clear 0 0 write-only 0 No effect #0 1 ADLIMEXSR.LIMEXF0 is cleared #1 LIMEXF1 Temperature Sensor Channel: Limiter Clip Flag Clear 1 1 write-only 0 No effect #0 1 ADLIMEXSR.LIMEXF1 is cleared #1 LIMEXF2 Internal Reference Voltage Channel: Limiter Clip Flag Clear 2 2 write-only 0 No effect #0 1 ADLIMEXSR.LIMEXF2 is cleared #1 LIMEXF5 D/A Converter 0 Channel: Limiter Clip Flag Clear 5 5 write-only 0 No effect #0 1 ADLIMEXSR.LIMEXF5 is cleared #1 LIMEXF6 D/A Converter 1 Channel: Limiter Clip Flag Clear 6 6 write-only 0 No effect #0 1 ADLIMEXSR.LIMEXF6 is cleared #1 LIMEXF7 D/A Converter 2 Channel: Limiter Clip Flag Clear 7 7 write-only 0 No effect #0 1 ADLIMEXSR.LIMEXF7 is cleared #1 LIMEXF8 D/A Converter 3 Channel: Limiter Clip Flag Clear 8 8 write-only 0 No effect #0 1 ADLIMEXSR.LIMEXF8 is cleared #1 ADSCANENDSR Scan End Status Register 0xD50 32 read-only 0x00000000 0xffffffff SCENDF0 Scan Group n Scan End Flag 0 0 read-only 0 Scan group n has not been scanned #0 1 End of scan for scan group n is detected #1 SCENDF1 Scan Group n Scan End Flag 1 1 read-only 0 Scan group n has not been scanned #0 1 End of scan for scan group n is detected #1 SCENDF2 Scan Group n Scan End Flag 2 2 read-only 0 Scan group n has not been scanned #0 1 End of scan for scan group n is detected #1 SCENDF3 Scan Group n Scan End Flag 3 3 read-only 0 Scan group n has not been scanned #0 1 End of scan for scan group n is detected #1 SCENDF4 Scan Group n Scan End Flag 4 4 read-only 0 Scan group n has not been scanned #0 1 End of scan for scan group n is detected #1 SCENDF5 Scan Group n Scan End Flag 5 5 read-only 0 Scan group n has not been scanned #0 1 End of scan for scan group n is detected #1 SCENDF6 Scan Group n Scan End Flag 6 6 read-only 0 Scan group n has not been scanned #0 1 End of scan for scan group n is detected #1 SCENDF7 Scan Group n Scan End Flag 7 7 read-only 0 Scan group n has not been scanned #0 1 End of scan for scan group n is detected #1 SCENDF8 Scan Group n Scan End Flag 8 8 read-only 0 Scan group n has not been scanned #0 1 End of scan for scan group n is detected #1 ADSCANENDSCR Scan End Status Clear Register 0xD54 32 write-only 0x00000000 0xffffffff SCENDC0 Scan Group n Scan End Flag Clear 0 0 write-only 0 No effect #0 1 ADSCANENDSR.SCENDFn is cleared #1 SCENDC1 Scan Group n Scan End Flag Clear 1 1 write-only 0 No effect #0 1 ADSCANENDSR.SCENDFn is cleared #1 SCENDC2 Scan Group n Scan End Flag Clear 2 2 write-only 0 No effect #0 1 ADSCANENDSR.SCENDFn is cleared #1 SCENDC3 Scan Group n Scan End Flag Clear 3 3 write-only 0 No effect #0 1 ADSCANENDSR.SCENDFn is cleared #1 SCENDC4 Scan Group n Scan End Flag Clear 4 4 write-only 0 No effect #0 1 ADSCANENDSR.SCENDFn is cleared #1 SCENDC5 Scan Group n Scan End Flag Clear 5 5 write-only 0 No effect #0 1 ADSCANENDSR.SCENDFn is cleared #1 SCENDC6 Scan Group n Scan End Flag Clear 6 6 write-only 0 No effect #0 1 ADSCANENDSR.SCENDFn is cleared #1 SCENDC7 Scan Group n Scan End Flag Clear 7 7 write-only 0 No effect #0 1 ADSCANENDSR.SCENDFn is cleared #1 SCENDC8 Scan Group n Scan End Flag Clear 8 8 write-only 0 No effect #0 1 ADSCANENDSR.SCENDFn is cleared #1 29 0x04 0-28 ADDR%s A/D Data Register %s 0x1000 32 read-only 0x00000000 0xffffffff DATA A/D conversion data 0 15 read-only ERR A/D conversion data error status 31 31 read-only 0 No error (the A/D conversion data is valid) #0 1 Error is detected (the A/D conversion data is not guaranteed) #1 3 0x04 0-2 ADEXDR%s A/D Extended Analog Data Register %s 0x1180 32 read-only 0x00000000 0xffffffff DATA A/D conversion data 0 15 read-only DIAGSR Self-diagnosis Status 24 26 read-only ERR A/D Conversion Error Status 31 31 read-only 0 No error (the A/D conversion data is valid) #0 1 Error is detected (the A/D conversion data is not guaranteed) #1 4 0x04 5-8 ADEXDR%s A/D Extended Analog Data Register %s 0x1194 32 read-only 0x00000000 0xffffffff DATA A/D conversion data 0 15 read-only DIAGSR Self-diagnosis Status 24 26 read-only ERR A/D Conversion Error Status 31 31 read-only 0 No error (the A/D conversion data is valid) #0 1 Error is detected (the A/D conversion data is not guaranteed) #1 9 0x04 0-8 ADFIFODR%s FIFO Data Register %s 0x1200 32 read-only 0x00000000 0xffffffff DATA A/D Conversion Data 0 15 read-only CH A/D Conversion Channel Number 24 30 read-only ERR A/D Conversion Data Error Status 31 31 read-only 0 No error (the A/D conversion data is valid) #0 1 Error is detected (the A/D conversion data is not guaranteed) #1 DAC120 12-bit D/A converter 0 0x40172000 0x00 6 registers 0x08 1 registers 0x1C 1 registers 2 0x02 0-1 DADR%s D/A Data Register %s 0x00 16 read-write 0x0000 0xffff DACR D/A Control Register 0x04 8 read-write 0x1f 0xff DAE D/A Enable 5 5 read-write 0 Control D/A conversion of channels 0 and 1 individually Control D/A conversion of channels 2 and 3 individually #0 1 Control D/A conversion of channels 0 and 1 collectively Control D/A conversion of channels 2 and 3 collectively #1 DAOE0 D/A Output Enable 0 6 6 read-write 0 Disable analog output of channel 0 (DA0) Disable analog output of channel 2 (DA2) #0 1 Enable D/A conversion of channel 0 (DA0) Enable D/A conversion of channel 2 (DA2) #1 DAOE1 D/A Output Enable 1 7 7 read-write 0 Disable analog output of channel 1 (DA1) Disable analog output of channel 3 (DA3) #0 1 Enable D/A conversion of channel 1 (DA1) Enable D/A conversion of channel 3 (DA3) #1 DADPR DADRn Format Select Register 0x05 8 read-write 0x00 0xff DPSEL DADRn Format Select 7 7 read-write 0 Right-justified format #0 1 Left-justified format #1 DAAMPCR D/A Output Amplifier Control Register 0x08 8 read-write 0x00 0xff DAAMP0 Amplifier Control 0 6 6 read-write 0 Do not use channel 0 output amplifier (m = 0) Do not use channel 2 output amplifier (m = 1) #0 1 Use channel 0 output amplifier (m = 0) Use channel 2 output amplifier (m = 1) #1 DAAMP1 Amplifier Control 1 7 7 read-write 0 Do not use channel 1 output amplifier (m = 0) Do not use channel 3 output amplifier (m = 1) #0 1 Use channel 1 output amplifier (m = 0) Use channel 3 output amplifier (m = 1) #1 DAASWCR D/A Amplifier Stabilization Wait Control Register 0x1C 8 read-write 0x00 0xff DAASW0 D/A Amplifier Stabilization Wait 0 and D/A internal output control 6 6 read-write 0 For output to external pin: Amplifier stabilization wait off (output) for channel 0 For output to internal module: Disable output for channel 0 #0 1 For output to external pin: Amplifier stabilization wait on (high-Z) for channel 0 For output to internal module: Enable output for channel 0 #1 DAASW1 D/A Amplifier Stabilization Wait 1 and D/A internal output control 7 7 read-write 0 For output to external pin: Amplifier stabilization wait off (output) for channel 1 For output to internal module: Disable output for channel 1 #0 1 For output to external pin: Amplifier stabilization wait on (high-Z) for channel 1 For output to internal module: Enable output for channel 1 #1 DAC121 12-bit D/A converter 1 0x40172100 TSD Temperature Sensor Calibration Data 0x407FB000 0x17C 4 registers TSCDR Temperature Sensor Calibration Data Register 0x017C 32 read-only 0x00000000 0xffff0000 TSCDR Temperature Sensor Calibration Data 0 15 read-only FLAD Data Flash 0x407FC000 0x40 1 registers FCKMHZ Data Flash Access Frequency Register 0x40 8 read-write 0x3c 0xff FCKMHZ Data Flash Access Frequency Register 0 7 read-write FACI Flash Application Command Interface 0x407FE000 0x10 1 registers 0x14 1 registers 0x18 1 registers 0x30 8 registers 0x44 2 registers 0x78 2 registers 0x7C 2 registers 0x80 6 registers 0x8C 2 registers 0xA0 2 registers 0xD0 1 registers 0xD4 1 registers 0xD8 10 registers 0xE4 2 registers 0xE8 2 registers FASTAT Flash Access Status Register 0x10 8 read-write 0x00 0xff DFAE Data Flash Memory Access Violation Flag 3 3 read-write 0 No data flash memory access violation has occurred #0 1 A data flash memory access violation has occurred. #1 CMDLK Command Lock Flag 4 4 read-only 0 The flash sequencer is not in the command-locked state #0 1 The flash sequencer is in the command-locked state. #1 CFAE Code Flash Memory Access Violation Flag 7 7 read-write 0 No code flash memory access violation has occurred #0 1 A code flash memory access violation has occurred. #1 FAEINT Flash Access Error Interrupt Enable Register 0x14 8 read-write 0x98 0xff DFAEIE Data Flash Memory Access Violation Interrupt Enable 3 3 read-write 0 Generation of an FIFERR interrupt request is disabled when FASTAT.DFAE is set to 1 #0 1 Generation of an FIFERR interrupt request is enabled when FASTAT.DFAE is set to 1. #1 CMDLKIE Command Lock Interrupt Enable 4 4 read-write 0 Generation of an FIFERR interrupt request is disabled when FASTAT.CMDLK is set to 1 #0 1 Generation of an FIFERR interrupt request is enabled when FASTAT.CMDLK is set to 1. #1 CFAEIE Code Flash Memory Access Violation Interrupt Enable 7 7 read-write 0 Generation of an FIFERR interrupt request is disabled when FASTAT.CFAE is set to 1 #0 1 Generation of an FIFERR interrupt request is enabled when FASTAT.CFAE is set to 1. #1 FRDYIE Flash Ready Interrupt Enable Register 0x18 8 read-write 0x00 0xff FRDYIE Flash Ready Interrupt Enable 0 0 read-write 0 Generation of an FRDY interrupt request is disabled #0 1 Generation of an FRDY interrupt request is enabled. #1 FSADDR FACI Command Start Address Register 0x30 32 read-write 0x00000000 0xffffffff FEADDR FACI Command End Address Register 0x34 32 read-write 0x00000000 0xffffffff FEADDR End Address for FACI Command Processing 0 31 read-write FMEPROT Flash P/E Mode Entry Protection Register 0x44 16 read-write 0x0001 0xffff CEPROT Code Flash P/E Mode Entry Protection 0 0 read-write 0 FENTRYC bit is not protected #0 1 FENTRYC bit is protected. #1 KEY Key Code 8 15 write-only FBPROT0 Flash Block Protection Register 0x78 16 read-write 0x0000 0xffff BPCN0 Block Protection for Non-secure Cancel 0 0 read-write 0 Block protection is enabled #0 1 Block protection is disabled. #1 KEY Key Code 8 15 write-only FBPROT1 Flash Block Protection for Secure Register 0x7C 16 read-write 0x0000 0xffff BPCN1 Block Protection for Secure Cancel 0 0 read-write 0 Block protection is enabled #0 1 Block protection is disabled. #1 KEY Key Code 8 15 write-only FSTATR Flash Status Register 0x80 32 read-write 0x00008000 0xffffffff FLWEERR Flash Write/Erase Protect Error Flag 6 6 read-only 0 An error has not occurred #0 1 An error has occurred. #1 PRGSPD Programming Suspend Status Flag 8 8 read-only 0 The flash sequencer is not in the programming suspension processing state or programming suspended state #0 1 The flash sequencer is in the programming suspension processing state or programming suspended state. #1 ERSSPD Erasure Suspend Status Flag 9 9 read-only 0 The flash sequencer is not in the erasure suspension processing state or the erasure suspended state #0 1 The flash sequencer is in the erasure suspension processing state or the erasure suspended state. #1 DBFULL Data Buffer Full Flag 10 10 read-only 0 The data buffer is empty #0 1 The data buffer is full. #1 SUSRDY Suspend Ready Flag 11 11 read-only 0 The flash sequencer cannot receive P/E suspend commands #0 1 The flash sequencer can receive P/E suspend commands. #1 PRGERR Programming Error Flag 12 12 read-only 0 Programming has completed successfully #0 1 An error has occurred during programming. #1 ERSERR Erasure Error Flag 13 13 read-only 0 Erasure has completed successfully #0 1 An error has occurred during erasure. #1 ILGLERR Illegal Command Error Flag 14 14 read-only 0 The flash sequencer has not detected an illegal FACI command or illegal flash memory access #0 1 The flash sequencer has detected an illegal FACI command or illegal flash memory access. #1 FRDY Flash Ready Flag 15 15 read-only 0 Program, Block Erase, Multi Block Erase, P/E suspend, P/E resume, Forced Stop, Blank Check, or Configuration set command processing is in progress #0 1 None of the above is in progress. #1 OTERR Other Error 20 20 read-only 0 A status clear or forced stop command processing is complete #0 1 An error has occurred. #1 SECERR Security Error 21 21 read-only 0 A status clear or forced stop command processing is complete #0 1 An error has occurred. #1 FESETERR FENTRY Setting Error 22 22 read-only 0 A status clear or forced stop command processing is complete #0 1 An error has occurred. #1 ILGCOMERR Illegal Command Error 23 23 read-only 0 A status clear or forced stop command processing is complete #0 1 An error has occurred. #1 FENTRYR Flash P/E Mode Entry Register 0x84 16 read-write 0x0000 0xffff FENTRYC Code Flash P/E Mode Entry 0 0 read-write 0 Code flash is in read mode #0 1 Code flash is in P/E mode. #1 FENTRYD Data Flash P/E Mode Entry 7 7 read-write 0 Data flash is in read mode #0 1 Data flash is in P/E mode. #1 KEY Key Code 8 15 write-only FSUINITR Flash Sequencer Setup Initialization Register 0x8C 16 read-write 0x0000 0xffff SUINIT Set-Up Initialization 0 0 read-write 0 The FSADDR, FEADDR, FBPROT0, FBPROT1, FENTRYR, FBCCNT, and FCPSR flash sequencer setup registers keep their current values #0 1 The FSADDR, FEADDR, FBPROT0, FBRPOT1, FENTRYR, FBCCNT, and FCPSR flash sequencer setup registers are initialized. #1 KEY Key Code 8 15 write-only FCMDR FACI Command Register 0xA0 16 read-only 0x0000 0xffff PCMDR Pre-command Flag 0 7 read-only CMDR Command Flag 8 15 read-only FBCCNT Blank Check Control Register 0xD0 8 read-write 0x00 0xff BCDIR Blank Check Direction 0 0 read-write 0 Blank checking is executed from the lower addresses to the higher addresses (incremental mode) #0 1 Blank checking is executed from the higher addresses to the lower addresses (decremental mode). #1 FBCSTAT Blank Check Status Register 0xD4 8 read-write 0x00 0xff BCST Blank Check Status Flag 0 0 read-only 0 The target area is in the non-programmed state, that is, the area has been erased but has not yet been reprogrammed #0 1 The target area has been programmed with 0s or 1s. #1 FPSADDR Data Flash Programming Start Address Register 0xD8 32 read-write 0x00000000 0xffffffff PSADR Programmed Area Start Address 0 16 read-only FSUASMON Flash Startup Area Select Monitor Register 0xDC 32 read-only 0x00000000 0x7fff7fff FSPR Protection Programming Flag to set Boot Flag and Startup Area Control 15 15 read-only 0 Protected state #0 1 Non-protected state. #1 BTFLG Flag of Startup Area Select for Boot Swap 31 31 read-only 0 The startup area is the alternate block (block 1) #0 1 The startup area is the default block (block 0). #1 FCPSR Flash Sequencer Processing Switching Register 0xE0 16 read-write 0x0000 0xffff ESUSPMD Erasure Suspend Mode 0 0 read-write 0 Suspension priority mode #0 1 Erasure priority mode. #1 FPCKAR Flash Sequencer Processing Clock Notification Register 0xE4 16 read-write 0x003c 0xffff PCKA Flash Sequencer Operating Clock Notification 0 7 read-write KEY Key Code 8 15 write-only FSUACR Flash Startup Area Control Register 0xE8 16 read-write 0x0000 0xffff SAS Startup Area Select 0 1 read-write 00 Startup area is selected by BTFLG bit #00 01 Startup area is selected by BTFLG bit #01 10 Startup area is temporarily switched to the default area (block 0) #10 11 Startup area is temporarily switched to the alternate area (block 1). #11 KEY Key Code 8 15 write-only