Renesas Electronics Corporation Renesas R7FA4M2AD RA4 1.20.00 Arm Cortex-M33 based Microcontroller RA4M2 group This software is supplied by Renesas Electronics Corporation and is only intended for \n use with Renesas products. No other uses are authorized. This software is owned by \n Renesas Electronics Corporation and is protected under all applicable laws, including \n copyright laws. \n \n THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING \n THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO \n WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. \n ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT \n PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED \n COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL \n DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE \n BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. \n \n Renesas reserves the right, without notice, to make changes to this software and to \n discontinue the availability of this software. By using this software, you agree to \n the additional terms and conditions found by accessing the following link: \n http://www.renesas.com/disclaimer \n \n CM33 r0p4 little true true true 4 false 96 system_RA4M2 8 32 32 read-write n 0 0xFFFFFFFF RMPU Renesas Memory Protection Unit 0x40000000 0x00 2 registers 0x04 2 registers 0x100 2 registers 0x104 2 registers 0x108 2 registers 0x10C 2 registers 0x200 136 registers MMPUOAD MMPU Operation After Detection Register 0x0000 16 read-write 0x0000 0xffff OAD Operation after detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 KEY This bit enables or disables writes to the OAD bit. 8 15 write-only MMPUOADPT MMPU Operation After Detection Protect Register 0x0004 16 read-write 0x0000 0xffff PROTECT Protection of register 0 0 read-write 0 MMPUOAD register writes are possible. #0 1 MMPUOAD register writes are protected. Read is possible. #1 KEY Key code 8 15 write-only MMPUENDMAC MMPU Enable Register for DMAC 0x0100 16 read-write 0x0000 0xffff ENABLE Bus Master MPU of DMAC enable 0 0 read-write 0 Bus Master MPU of DMAC is disabled. #0 1 Bus Master MPU of DMAC is enabled. #1 KEY These bits enable or disable writes to the ENABLE bit. 8 15 write-only MMPUENPTDMAC MMPU Enable Protect Register for DMAC 0x0104 16 read-write 0x0000 0xffff PROTECT Protection of register 0 0 read-write 0 MMPUENDMAC register writes are possible. #0 1 MMPUENDMAC register writes are protected. Read is possible. #1 KEY These bits enable or disable writes to the PROTECT bit. 8 15 write-only MMPURPTDMAC MMPU Regions Protect Register for DMAC 0x0108 16 read-write 0x0000 0xffff PROTECT Protection of register 0 0 read-write 0 Bus Master MPU register for DMAC writing is possible. #0 1 Bus Master MPU register for DMAC writing is protected. Read is possible. #1 KEY These bits enable or disable writes to the PROTECT bit. 8 15 write-only MMPURPTDMAC_SEC MMPU Regions Protect register for DMAC Secure 0x010C 16 read-write 0x0000 0xffff PROTECT Protection of register 0 0 read-write 0 Bus master MPU register for DMAC secure writes are possible. #0 1 Bus master MPU register for DMAC secure writes are protected. Read is possible. #1 KEY These bits enable or disable writes to the PROTECT bit. 8 15 write-only 8 0x010 0-7 MMPUACDMAC%s MMPU Access Control Register for DMAC 0x0200 16 read-write 0x0000 0xffff ENABLE Region enable 0 0 read-write 0 DMAC Region n unit is disabled #0 1 DMAC Region n unit is enabled #1 RP Read protection 1 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 2 read-write 0 Write permission #0 1 Write protection #1 8 0x010 0-7 MMPUSDMAC%s MMPU Start Address Register for DMAC 0x0204 32 read-write 0x00000000 0x0000001f MMPUS Region start address register 5 31 read-write 8 0x010 0-7 MMPUEDMAC%s MMPU End Address Register for DMAC 0x0208 32 read-write 0x0000001f 0x0000001f MMPUE Region end address register 5 31 read-write TZF TrustZone Filter 0x40000E00 0x00 2 registers 0x04 2 registers TZFOAD TrustZone Filter Operation After Detection Register 0x00 16 read-write 0x0000 0xffff OAD Operation after detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 KEY KeyCode 8 15 write-only TZFPT TrustZone Filter Protect Register 0x04 16 read-write 0x0000 0xffff PROTECT Protection of register 0 0 read-write 0 All Bus TrustZone Filter register writing is protected. Read is possible. #0 1 All Bus TrustZone Filter register writing is possible. #1 KEY KeyCode 8 15 write-only SRAM SRAM Control 0x40002000 0x00 1 registers 0x04 1 registers 0x08 1 registers 0x0C 1 registers 0xC0 5 registers 0xD0 1 registers 0xD4 1 registers 0xD8 1 registers PARIOAD SRAM Parity Error Operation After Detection Register 0x00 8 read-write 0x00 0xff OAD Operation After Detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 SRAMPRCR SRAM Protection Register 0x04 8 read-write 0x00 0xff SRAMPRCR Register Write Control 0 0 read-write 0 Disable writes to protected registers #0 1 Enable writes to protected registers #1 KW Write Key Code 1 7 write-only SRAMWTSC SRAM Wait State Control Register 0x08 8 read-write 0x01 0xff SRAM0WTEN SRAM0 wait enable 0 0 read-write 0 No wait #0 1 Add wait state in read access cycle to SRAM0 #1 SRAMPRCR2 SRAM Protection Register 2 0x0C 8 read-write 0x00 0xff SRAMPRCR2 Register Write Control 0 0 read-write 0 Disable writes to the protectedregisters #0 1 Enable writes to the protected registers #1 KW Write Key Code 1 7 write-only ECCMODE ECC Operating Mode Control Register 0xC0 8 read-write 0x00 0xff ECCMOD ECC Operating Mode Select 0 1 read-write 00 Disable ECC function #00 01 Setting prohibited #01 10 Enable ECC function without error checking #10 11 Enable ECC function with error checking #11 ECC2STS ECC 2-Bit Error Status Register 0xC1 8 read-write 0x00 0xff ECC2ERR ECC 2-Bit Error Status 0 0 read-write 0 No 2-bit ECC error occurred #0 1 2-bit ECC error occurred #1 ECC1STSEN ECC 1-Bit Error Information Update Enable Register 0xC2 8 read-write 0x00 0xff E1STSEN ECC 1-Bit Error Information Update Enable 0 0 read-write 0 Disable updating of 1-bit ECC error information #0 1 Enable updating of 1-bit ECC error information #1 ECC1STS ECC 1-Bit Error Status Register 0xC3 8 read-write 0x00 0xff ECC1ERR ECC 1-Bit Error Status 0 0 read-write 0 No 1-bit ECC error occurred #0 1 1-bit ECC error occurred #1 ECCPRCR ECC Protection Register 0xC4 8 read-write 0x00 0xff ECCPRCR Register Write Control 0 0 read-write 0 Disable writes to the protected registers #0 1 Enable writes to the protected registers #1 KW Write Key Code 1 7 write-only 0x78 Enable write to the ECCPRCR bit 0x78 Others Disable write to the ECCPRCR bit true ECCPRCR2 ECC Protection Register 2 0xD0 8 read-write 0x00 0xff ECCPRCR2 Register Write Control 0 0 read-write 0 Disable writes to the protected registers #0 1 Enable writes to the protected registers #1 KW2 Write Key Code 1 7 write-only 0x78 Enable write to the ECCPRCR2 bit 0x78 Others Disable write to the ECCPRCR2 bit true ECCETST ECC Test Control Register 0xD4 8 read-write 0x00 0xff TSTBYP ECC Bypass Select 0 0 read-write 0 Disable ECC bypass #0 1 Enable ECC bypass #1 ECCOAD SRAM ECC Error Operation After Detection Register 0xD8 8 read-write 0x00 0xff OAD Operation After Detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 BUS Bus Control 0x40003000 0x1100 2 registers 0x1104 2 registers 0x1110 2 registers 0x1120 2 registers 0x1130 2 registers 0x1134 2 registers 0x1140 2 registers 0x1800 52 registers 0x1900 52 registers 0x1A00 56 registers BUSSCNTFHBIU Slave Bus Control Register 0x1100 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 1 read-write 00 DMAC/DTC > CPU #00 01 DMAC/DTC ↔ CPU #01 10 Setting prohibited #10 11 Setting prohibited #11 BUSSCNTFLBIU Slave Bus Control Register 0x1104 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 1 read-write 00 DMAC/DTC > CPU #00 01 DMAC/DTC ↔ CPU #01 10 Setting prohibited #10 11 Setting prohibited #11 BUSSCNTS0BIU Slave Bus Control Register 0x1110 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 1 read-write 00 DMAC/DTC > CPU #00 01 DMAC/DTC ↔ CPU #01 10 Setting prohibited #10 11 Setting prohibited #11 BUSSCNTPSBIU Slave Bus Control Register 0x1120 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 0 read-write 0 DMAC/DTC > CPU #0 1 DMAC/DTC ↔ CPU #1 BUSSCNTPLBIU Slave Bus Control Register 0x1130 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 0 read-write 0 DMAC/DTC > CPU #0 1 DMAC/DTC ↔ CPU #1 BUSSCNTPHBIU Slave Bus Control Register 0x1134 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 0 read-write 0 DMAC/DTC > CPU #0 1 DMAC/DTC ↔ CPU #1 BUSSCNTEQBIU Slave Bus Control Register 0x1140 16 read-write 0x0000 0xffff ARBS Arbitration Select for two masters 0 1 read-write 00 DMAC/DTC > CPU #00 01 DMAC/DTC ↔ CPU #01 10 Setting prohibited #10 11 Setting prohibited #11 3 0x10 1-3 BUS%sERRADD BUS Error Address Register 0x1800 32 read-only 0x00000000 0xffffffff BERAD Bus Error Address 0 31 read-only 3 0x10 1-3 BUS%sERRRW BUS Error Read Write Register 0x1804 8 read-write 0x00 0xff RWSTAT Error Access Read/Write Status 0 0 read-only 0 Read access #0 1 Write access #1 3 0x10 1-3 BTZF%sERRADD BUS TZF Error Address Register 0x1900 32 read-only 0x00000000 0xffffffff BTZFERAD Bus TrustZone Filter Error Address 0 31 read-only 3 0x10 1-3 BTZF%sERRRW BUS TZF Error Read Write Register 0x1904 8 read-write 0x00 0xff TRWSTAT TrustZone filter error access Read/Write Status 0 0 read-only 0 Read access #0 1 Write access #1 3 0x10 1-3 BUS%sERRSTAT BUS Error Status Register %s 0x1A00 8 read-only 0x00 0xff SLERRSTAT Slave bus Error Status 0 0 read-only 0 No error occurred #0 1 Error occurred #1 STERRSTAT Slave TrustZone filter Error Status 1 1 read-only 0 No error occurred #0 1 Error occurred #1 MMERRSTAT Master MPU Error Status 3 3 read-only 0 No error occurred #0 1 Error occurred #1 ILERRSTAT Illegal address access Error Status 4 4 read-only 0 No error occurred #0 1 Error occurred #1 3 0x10 1-3 BUS%sERRCLR BUS Error Clear Register %s 0x1A08 8 read-write 0x00 0xff SLERRCLR Slave bus Error Clear 0 0 read-write STERRCLR Slave TrustZone filter Error Clear 1 1 read-write MMERRCLR Master MPU Error Clear 3 3 read-write ILERRCLR Illegal Address Access Error Clear 4 4 read-write DMACDTCERRSTAT DMAC/DTC Error Status Register 0x1A24 8 read-only 0x00 0xff MTERRSTAT Master TrustZone Filter Error Status 0 0 read-only 0 No error occurred #0 1 Error occurred #1 DMACDTCERRCLR DMAC/DTC Error Clear Register 0x1A2C 8 read-write 0x00 0xff MTERRCLR Master TrustZone filter Error Clear 0 0 read-write DMAC0 Direct memory access controller 0 0x40005000 0x00 18 registers 0x13 3 registers 0x18 7 registers 0x20 16 registers DMSAR DMA Source Address Register 0x00 32 read-write 0x00000000 0xffffffff DMDAR DMA Destination Address Register 0x04 32 read-write 0x00000000 0xffffffff DMCRA DMA Transfer Count Register 0x08 32 read-write 0x00000000 0xffffffff DMCRAL Lower bits of transfer count 0 15 read-write DMCRAH Upper bits of transfer count 16 25 read-write DMCRB DMA Block Transfer Count Register 0x0C 32 read-write 0x00000000 0xffffffff DMCRBL Functions as a number of block, repeat or repeat-block transfer counter. 0 15 read-write DMCRBH Specifies the number of block, repeat or repeat-block transfer operations. 16 31 read-write DMTMD DMA Transfer Mode Register 0x10 16 read-write 0x0000 0xffff DCTG Transfer Request Source Select 0 1 read-write 00 Software request #00 01 Hardware request #01 10 Setting prohibited #10 11 Setting prohibited #11 SZ Transfer Data Size Select 8 9 read-write 00 8 bits #00 01 16 bits #01 10 32 bits #10 11 Setting prohibited #11 TKP Transfer Keeping 10 10 read-write 0 Transfer is stopped by completion of specified total number of transfer operations. #0 1 Transfer is not stopped by completion of specified total number of transfer operations (free-running). #1 DTS Repeat Area Select 12 13 read-write 00 The destination is specified as the repeat area or block area. #00 01 The source is specified as the repeat area or block area. #01 10 The repeat area or block area is not specified. #10 11 Setting prohibited. #11 MD Transfer Mode Select 14 15 read-write 00 Normal transfer #00 01 Repeat transfer #01 10 Block transfer #10 11 Repeat-block transfer #11 DMINT DMA Interrupt Setting Register 0x13 8 read-write 0x00 0xff DARIE Destination Address Extended Repeat Area Overflow Interrupt Enable 0 0 read-write 0 Disables an interrupt request for an extended repeat area overflow on the destination address. #0 1 Enables an interrupt request for an extended repeat area overflow on the destination address. #1 SARIE Source Address Extended Repeat Area Overflow Interrupt Enable 1 1 read-write 0 Disables an interrupt request for an extended repeat area overflow on the source address. #0 1 Enables an interrupt request for an extended repeat area overflow on the source address. #1 RPTIE Repeat Size End Interrupt Enable 2 2 read-write 0 Disables the repeat size end interrupt request. #0 1 Enables the repeat size end interrupt request. #1 ESIE Transfer Escape End Interrupt Enable 3 3 read-write 0 Disables the transfer escape end interrupt request. #0 1 Enables the transfer escape end interrupt request. #1 DTIE Transfer End Interrupt Enable 4 4 read-write 0 Disables the transfer end interrupt request. #0 1 Enables the transfer end interrupt request. #1 DMAMD DMA Address Mode Register 0x14 16 read-write 0x0000 0xffff DARA Destination Address Extended Repeat Area 0 4 read-write DADR Destination Address Update Select After Reload 5 5 read-write 0 Only reloading. #0 1 Add index after reloading. #1 DM Destination Address Update Mode 6 7 read-write 00 Destination address is fixed. #00 01 Offset addition. #01 10 Destination address is incremented. #10 11 Destination address is decremented. #11 SARA Source Address Extended Repeat Area 8 12 read-write SADR Source Address Update Select After Reload 13 13 read-write 0 Only reloading. #0 1 Add index after reloading. #1 SM Source Address Update Mode 14 15 read-write 00 Source address is fixed. #00 01 Offset addition. #01 10 Source address is incremented. #10 11 Source address is decremented. #11 DMOFR DMA Offset Register 0x18 32 read-write 0x00000000 0xffffffff DMCNT DMA Transfer Enable Register 0x1C 8 read-write 0x00 0xff DTE DMA Transfer Enable 0 0 read-write 0 Disables DMA transfer. #0 1 Enables DMA transfer. #1 DMREQ DMA Software Start Register 0x1D 8 read-write 0x00 0xff SWREQ DMA Software Start 0 0 read-write 0 DMA transfer is not requested. #0 1 DMA transfer is requested. #1 CLRS DMA Software Start Bit Auto Clear Select 4 4 read-write 0 SWREQ bit is cleared after DMA transfer is started by software. #0 1 SWREQ bit is not cleared after DMA transfer is started by software. #1 DMSTS DMA Status Register 0x1E 8 read-write 0x00 0xff ESIF Transfer Escape End Interrupt Flag 0 0 read-write 0 A transfer escape end interrupt has not been generated. #0 1 A transfer escape end interrupt has been generated. #1 DTIF Transfer End Interrupt Flag 4 4 read-write 0 A transfer end interrupt has not been generated. #0 1 A transfer end interrupt has been generated. #1 ACT DMAC Active Flag 7 7 read-only 0 DMAC is in the idle state. #0 1 DMAC is operating. #1 DMSRR DMA Source Reload Address Register 0x20 32 read-write 0x00000000 0xffffffff DMDRR DMA Destination Reload Address Register 0x24 32 read-write 0x00000000 0xffffffff DMSBS DMA Source Buffer Size Register 0x28 32 read-write 0x00000000 0xffffffff DMSBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMSBSH Specifies the repeat-area size in repeat-block transfer mode 16 31 read-write DMDBS DMA Destination Buffer Size Register 0x2C 32 read-write 0x00000000 0xffffffff DMDBSL Functions as data transfer counter in repeat-block transfer mode. 0 15 read-write DMDBSH Specifies the repeat-area size in repeat-block transfer mode. 16 31 read-write DMAC1 Direct memory access controller 1 0x40005040 DMAC2 Direct memory access controller 2 0x40005080 DMAC3 Direct memory access controller 3 0x400050C0 DMAC4 Direct memory access controller 4 0x40005100 DMAC5 Direct memory access controller 5 0x40005140 DMAC6 Direct memory access controller 6 0x40005180 DMAC7 Direct memory access controller 7 0x400051C0 DMA DMAC Module Activation 0x40005200 0x00 1 registers 0x40 4 registers DMAST DMA Module Activation Register 0x00 8 read-write 0x00 0xff DMST DMAC Operation Enable 0 0 read-write 0 DMAC activation is disabled. #0 1 DMAC activation is enabled. #1 DMECHR DMAC Error Channel Register 0x40 32 read-write 0x00000000 0xffffffff DMECH DMAC Error channel 0 2 read-only DMECHSAM DMAC Error channel Security Attribution Monitor 8 8 read-only 0 secure channel #0 1 non-secure channel #1 DMESTA DMAC Error Status 16 16 read-write 0 No DMA transfer error occurred #0 1 DMA transfer error occurred #1 DTC Data Transfer Controller 0x40005400 0x00 1 registers 0x04 4 registers 0x0C 1 registers 0x0E 3 registers 0x14 4 registers 0x20 4 registers DTCCR DTC Control Register 0x00 8 read-write 0x08 0xff RRS DTC Transfer Information Read Skip Enable 4 4 read-write 0 Transfer information read is not skipped #0 1 Transfer information read is skipped when vector numbers match #1 DTCVBR DTC Vector Base Register 0x04 32 read-write 0x00000000 0xffffffff DTCST DTC Module Start Register 0x0C 8 read-write 0x00 0xff DTCST DTC Module Start 0 0 read-write 0 DTC module stopped. #0 1 DTC module started. #1 DTCSTS DTC Status Register 0x0E 16 read-only 0x0000 0xffff VECN DTC-Activating Vector Number Monitoring 0 7 read-only ACT DTC Active Flag 15 15 read-only 0 DTC transfer operation is not in progress. #0 1 DTC transfer operation is in progress. #1 DTCCR_SEC DTC Control Register for secure Region 0x10 8 read-write 0x08 0xff RRS DTC Transfer Information Read Skip Enable for Secure 4 4 read-write 0 Transfer information read is not skipped. #0 1 Transfer information read is skipped when vector numbers match. #1 DTCVBR_SEC DTC Vector Base Register for secure Region 0x14 32 read-write 0x00000000 0xffffffff DTEVR DTC Error Vector Register 0x20 32 read-write 0x00000000 0xffffffff DTEV DTC Error Vector Number 0 7 read-only DTEVSAM DTC Error Vector Number SA Monitor 8 8 read-only 0 Secure vector number #0 1 Non-Secure vector number #1 DTESTA DTC Error Status Flag 16 16 read-write 0 No DTC transfer error occurred #0 1 DTC transfer error occurred #1 ICU Interrupt Controller 0x40006000 0x00 16 registers 0x100 1 registers 0x120 2 registers 0x130 2 registers 0x140 2 registers 0x1A0 8 registers 0x200 2 registers 0x280 32 registers 0x300 384 registers IEL0 ICU Interrupt 0 0 IEL1 ICU Interrupt 1 1 IEL2 ICU Interrupt 2 2 IEL3 ICU Interrupt 3 3 IEL4 ICU Interrupt 4 4 IEL5 ICU Interrupt 5 5 IEL6 ICU Interrupt 6 6 IEL7 ICU Interrupt 7 7 IEL8 ICU Interrupt 8 8 IEL9 ICU Interrupt 9 9 IEL10 ICU Interrupt 10 10 IEL11 ICU Interrupt 11 11 IEL12 ICU Interrupt 12 12 IEL13 ICU Interrupt 13 13 IEL14 ICU Interrupt 14 14 IEL15 ICU Interrupt 15 15 IEL16 ICU Interrupt 16 16 IEL17 ICU Interrupt 17 17 IEL18 ICU Interrupt 18 18 IEL19 ICU Interrupt 19 19 IEL20 ICU Interrupt 20 20 IEL21 ICU Interrupt 21 21 IEL22 ICU Interrupt 22 22 IEL23 ICU Interrupt 23 23 IEL24 ICU Interrupt 24 24 IEL25 ICU Interrupt 25 25 IEL26 ICU Interrupt 26 26 IEL27 ICU Interrupt 27 27 IEL28 ICU Interrupt 28 28 IEL29 ICU Interrupt 29 29 IEL30 ICU Interrupt 30 30 IEL31 ICU Interrupt 31 31 IEL32 ICU Interrupt 32 32 IEL33 ICU Interrupt 33 33 IEL34 ICU Interrupt 34 34 IEL35 ICU Interrupt 35 35 IEL36 ICU Interrupt 36 36 IEL37 ICU Interrupt 37 37 IEL38 ICU Interrupt 38 38 IEL39 ICU Interrupt 39 39 IEL40 ICU Interrupt 40 40 IEL41 ICU Interrupt 41 41 IEL42 ICU Interrupt 42 42 IEL43 ICU Interrupt 43 43 IEL44 ICU Interrupt 44 44 IEL45 ICU Interrupt 45 45 IEL46 ICU Interrupt 46 46 IEL47 ICU Interrupt 47 47 IEL48 ICU Interrupt 48 48 IEL49 ICU Interrupt 49 49 IEL50 ICU Interrupt 50 50 IEL51 ICU Interrupt 51 51 IEL52 ICU Interrupt 52 52 IEL53 ICU Interrupt 53 53 IEL54 ICU Interrupt 54 54 IEL55 ICU Interrupt 55 55 IEL56 ICU Interrupt 56 56 IEL57 ICU Interrupt 57 57 IEL58 ICU Interrupt 58 58 IEL59 ICU Interrupt 59 59 IEL60 ICU Interrupt 60 60 IEL61 ICU Interrupt 61 61 IEL62 ICU Interrupt 62 62 IEL63 ICU Interrupt 63 63 IEL64 ICU Interrupt 64 64 IEL65 ICU Interrupt 65 65 IEL66 ICU Interrupt 66 66 IEL67 ICU Interrupt 67 67 IEL68 ICU Interrupt 68 68 IEL69 ICU Interrupt 69 69 IEL70 ICU Interrupt 70 70 IEL71 ICU Interrupt 71 71 IEL72 ICU Interrupt 72 72 IEL73 ICU Interrupt 73 73 IEL74 ICU Interrupt 74 74 IEL75 ICU Interrupt 75 75 IEL76 ICU Interrupt 76 76 IEL77 ICU Interrupt 77 77 IEL78 ICU Interrupt 78 78 IEL79 ICU Interrupt 79 79 IEL80 ICU Interrupt 80 80 IEL81 ICU Interrupt 81 81 IEL82 ICU Interrupt 82 82 IEL83 ICU Interrupt 83 83 IEL84 ICU Interrupt 84 84 IEL85 ICU Interrupt 85 85 IEL86 ICU Interrupt 86 86 IEL87 ICU Interrupt 87 87 IEL88 ICU Interrupt 88 88 IEL89 ICU Interrupt 89 89 IEL90 ICU Interrupt 90 90 IEL91 ICU Interrupt 91 91 IEL92 ICU Interrupt 92 92 IEL93 ICU Interrupt 93 93 IEL94 ICU Interrupt 94 94 IEL95 ICU Interrupt 95 95 16 0x1 0-15 IRQCR%s IRQ Control Register %s 0x000 8 read-write 0x00 0xff IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 5 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQi Digital Filter Enable 7 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 NMICR NMI Pin Interrupt Control Register 0x100 8 read-write 0x00 0xff NMIMD NMI Detection Set 0 0 read-write 0 Falling edge #0 1 Rising edge #1 NFCLKSEL NMI Digital Filter Sampling Clock Select 4 5 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 NFLTEN NMI Digital Filter Enable 7 7 read-write 0 Disabled. #0 1 Enabled. #1 NMIER Non-Maskable Interrupt Enable Register 0x120 16 read-write 0x0000 0xffff IWDTEN IWDT Underflow/Refresh Error Interrupt Enable 0 0 read-write 0 Disabled #0 1 Enabled. #1 WDTEN WDT Underflow/Refresh Error Interrupt Enable 1 1 read-write 0 Disabled #0 1 Enabled #1 LVD1EN Voltage monitor 1 Interrupt Enable 2 2 read-write 0 Disabled #0 1 Enabled #1 LVD2EN Voltage monitor 2 Interrupt Enable 3 3 read-write 0 Disabled #0 1 Enabled #1 OSTEN Main Clock Oscillation Stop Detection Interrupt Enable 6 6 read-write 0 Disabled #0 1 Enabled #1 NMIEN NMI Pin Interrupt Enable 7 7 read-write 0 Disabled #0 1 Enabled #1 RPEEN SRAM Parity Error Interrupt Enable 8 8 read-write 0 Disabled #0 1 Enabled #1 RECCEN SRAM ECC Error Interrupt Enable 9 9 read-write 0 Disabled #0 1 Enabled #1 BUSMEN Bus Master MPU Error Interrupt Enable 11 11 read-write 0 Disabled #0 1 Enabled #1 TZFEN 13 13 read-write 0 Disabled #0 1 Enabled #1 NMICLR Non-Maskable Interrupt Status Clear Register 0x130 16 read-write 0x0000 0xffff IWDTCLR IWDT Underflow/Refresh Error Interrupt Status Flag Clear 0 0 read-write 0 No effect #0 1 Clear the NMISR.IWDTST flag #1 WDTCLR WDT Underflow/Refresh Error Interrupt Status Flag Clear 1 1 read-write 0 No effect #0 1 Clear the NMISR.WDTST flag #1 LVD1CLR Voltage Monitor 1 Interrupt Status Flag Clear 2 2 read-write 0 No effect #0 1 Clear the NMISR.LVD1ST flag #1 LVD2CLR Voltage Monitor 2 Interrupt Status Flag Clear 3 3 read-write 0 No effect #0 1 Clear the NMISR.LVD2ST flag. #1 OSTCLR Oscillation Stop Detection Interrupt Status Flag Clear 6 6 read-write 0 No effect #0 1 Clear the NMISR.OSTST flag #1 NMICLR NMI Pin Interrupt Status Flag Clear 7 7 read-write 0 No effect #0 1 Clear the NMISR.NMIST flag #1 RPECLR SRAM Parity Error Interrupt Status Flag Clear 8 8 read-write 0 No effect #0 1 Clear the NMISR.RPEST flag #1 RECCCLR SRAM ECC Error Interrupt Status Flag Clear 9 9 read-write 0 No effect #0 1 Clear the NMISR.RECCST flag #1 BUSMCLR Bus Master MPU Error Interrupt Status Flag Clear 11 11 read-write 0 No effect #0 1 Clear the NMISR.BUSMST flag #1 TZFCLR 13 13 read-write 0 No effect #0 1 Clear the NMISR.TZFCLR flag #1 NMISR Non-Maskable Interrupt Status Register 0x140 16 read-only 0x0000 0xffff IWDTST IWDT Underflow/Refresh Error Interrupt Status Flag 0 0 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 WDTST WDT Underflow/Refresh Error Interrupt Status Flag 1 1 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 LVD1ST Voltage Monitor 1 Interrupt Status Flag 2 2 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 LVD2ST Voltage Monitor 2 Interrupt Status Flag 3 3 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 OSTST Main Clock Oscillation Stop Detection Interrupt Status Flag 6 6 read-only 0 Interrupt not requested for main clock oscillation stop #0 1 Interrupt requested for main clock oscillation stop #1 NMIST NMI Pin Interrupt Status Flag 7 7 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 RPEST SRAM Parity Error Interrupt Status Flag 8 8 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 RECCST SRAM ECC Error Interrupt Status Flag 9 9 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 BUSMST Bus Master MPU Error Interrupt Status Flag 11 11 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 TZFST 13 13 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 WUPEN0 Wake Up Interrupt Enable Register 0 0x1A0 32 read-write 0x00000000 0xffffffff IRQWUPEN IRQn Interrupt Software Standby/Snooze Mode Returns Enable bit (n = 0 to 15) 0 15 read-write 0 Software Standby/Snooze Mode returns by IRQn interrupt is disabled #0 1 Software Standby/Snooze Mode returns by IRQn interrupt is enabled #1 IWDTWUPEN IWDT Interrupt Software Standby/Snooze Mode Returns Enable bit 16 16 read-write 0 Software Standby/Snooze Mode returns by IWDT interrupt is disabled #0 1 Software Standby/Snooze Mode returns by IWDT interrupt is enabled #1 LVD1WUPEN LVD1 Interrupt Software Standby/Snooze Mode Returns Enable bit 18 18 read-write 0 Software Standby/Snooze Mode returns by LVD1 interrupt is disabled #0 1 Software Standby/Snooze Mode returns by LVD1 interrupt is enabled #1 LVD2WUPEN LVD2 Interrupt Software Standby/Snooze Mode Returns Enable bit 19 19 read-write 0 Software Standby/Snooze Mode returns by LVD2 interrupt is disabled #0 1 Software Standby/Snooze Mode returns by LVD2 interrupt is enabled #1 RTCALMWUPEN RTC Alarm Interrupt Software Standby/Snooze Mode Returns Enable bit 24 24 read-write 0 Software Standby/Snooze Mode returns by RTC alarm interrupt is disabled #0 1 Software Standby/Snooze Mode returns by RTC alarm interrupt is enabled #1 RTCPRDWUPEN RTC Period Interrupt Software Standby/Snooze Mode Returns Enable bit 25 25 read-write 0 Software Standby/Snooze Mode returns by RTC period interrupt is disabled #0 1 Software Standby/Snooze Mode returns by RTC period interrupt is enabled #1 USBFS0WUPEN USBFS0 Interrupt Software Standby/Snooze Mode Returns Enable bit 27 27 read-write 0 Software Standby/Snooze Mode returns by USBFS0 interrupt is disabled #0 1 Software Standby/Snooze Mode returns by USBFS0 interrupt is enabled #1 AGT1UDWUPEN AGT1 Underflow Interrupt Software Standby/Snooze Mode Returns Enable bit 28 28 read-write 0 Software Standby/Snooze Mode returns by AGT1 underflow interrupt is disabled #0 1 Software Standby/Snooze Mode returns by AGT1 underflow interrupt is enabled #1 AGT1CAWUPEN AGT1 Compare Match A Interrupt Software Standby/Snooze Mode Returns Enable bit 29 29 read-write 0 Software Standby/Snooze Mode returns by AGT1 compare match A interrupt is disabled #0 1 Software Standby/Snooze Mode returns by AGT1 compare match A interrupt is enabled #1 AGT1CBWUPEN AGT1 Compare Match B Interrupt Software Standby/Snooze Mode Returns Enable bit 30 30 read-write 0 Software Standby/Snooze Mode returns by AGT1 compare match B interrupt is disabled #0 1 Software Standby/Snooze Mode returns by AGT1 compare match B interrupt is enabled #1 IIC0WUPEN IIC0 Address Match Interrupt Software Standby/Snooze Mode Returns Enable bit 31 31 read-write 0 Software Standby/Snooze Mode returns by IIC0 address match interrupt is disabled #0 1 Software Standby/Snooze Mode returns by IIC0 address match interrupt is enabled #1 WUPEN1 Wake Up interrupt enable register 1 0x1A4 32 read-write 0x00000000 0xffffffff AGT3UDWUPEN AGT3 Underflow Interrupt Software Standby Return Enable bit 0 0 read-write 0 Software standby returns by AGT3 underflow interrupt is disabled #0 1 Software standby returns by AGT3 underflow interrupt is enabled #1 AGT3CAWUPEN AGT3 Compare Match A Interrupt Software Standby Return Enable bit 1 1 read-write 0 Software standby returns by AGT3 compare match A interrupt is disabled #0 1 Software standby returns by AGT3 compare match A interrupt is enabled #1 AGT3CBWUPEN AGT3 Compare Match B Interrupt Software Standby Return Enable bit 2 2 read-write 0 Software standby returns by AGT3 compare match B interrupt is disabled #0 1 Software standby returns by AGT3 compare match B interrupt is enabled #1 SELSR0 SYS Event Link Setting Register 0x200 16 read-write 0x0000 0xffff 8 0x4 0-7 DELSR%s DMAC Event Link Setting Register %s 0x280 32 read-write 0x00000000 0xffffffff DELS DMAC Event Link Select 0 8 read-write 0x00 Disable interrupts to the associated DMAC module. 0x00 Others Event signal number to be linked. For details, see . true IR DMAC Activation Request Status Flag 16 16 read-write 0 No DMAC activation request occurred. #0 1 DMAC activation request occurred. #1 96 0x4 0-95 IELSR%s ICU Event Link Setting Register %s 0x300 32 read-write 0x00000000 0xffffffff CPSCU CPU System Security Control Unit 0x40008000 0x10 8 registers 0x30 8 registers 0x40 16 registers 0x54 4 registers 0x70 12 registers 0x100 8 registers 0x130 8 registers 0x180 4 registers 0x1B0 4 registers SRAMSAR SRAM Security Attribution Register 0x10 32 read-write 0xffffffff 0xffffffff SRAMSA0 Security attributes of registers for SRAM Protection 0 0 read-write 0 Secure #0 1 Non-Secure #1 SRAMSA1 Security attributes of registers for SRAM Protection 2 1 1 read-write 0 Secure #0 1 Non-Secure #1 SRAMSA2 Security attributes of registers for ECC Relation 2 2 read-write 0 Secure #0 1 Non-Secure #1 STBRAMSAR Standby RAM memory Security Attribution Register 0x014 32 read-write 0xfffffff0 0xffffffff NSBSTBR Security attributes of each region for Standby RAM 0 3 read-write 0x0 Region7-0 are all Secure. 0x0 0x1 Region7 is Non-secure. Region6-0 are Secure 0x1 0x2 Region7-6 are Non-secure. Region5-0 are Secure. 0x2 0x3 Region7-5 are Non-secure. Region4-0 are Secure. 0x3 0x4 Region7-4 are Non-secure. Region 3-0 are Secure. 0x4 0x5 Region7-3 are Non-secure. Region 2-0 are Secure. 0x5 0x6 Region7-2 are Non-secure. Region 1-0 are Secure. 0x6 0x7 Region7-1 are Non-Secure. Region0 is Secure. 0x7 Others Region7-0 are all Non-Secure. true DTCSAR DTC Controller Security Attribution Register 0x30 32 read-write 0xffffffff 0xffffffff DTCSTSA DTC Security Attribution 0 0 read-write 0 Secure. #0 1 Non-Secure. #1 DMACSAR DMAC Controller Security Attribution Register 0x34 32 read-write 0xffffffff 0xffffffff DMASTSA DMAST Security Attribution 0 0 read-write 0 Secure #0 1 Non-secure #1 ICUSARA Interrupt Controller Unit Security Attribution Register A 0x40 32 read-write 0xffffffff 0xffffffff SAIRQCR00 Security attributes of registers for the IRQCRn register 0 0 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR01 Security attributes of registers for the IRQCRn register 1 1 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR02 Security attributes of registers for the IRQCRn register 2 2 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR03 Security attributes of registers for the IRQCRn register 3 3 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR04 Security attributes of registers for the IRQCRn register 4 4 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR05 Security attributes of registers for the IRQCRn register 5 5 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR06 Security attributes of registers for the IRQCRn register 6 6 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR07 Security attributes of registers for the IRQCRn register 7 7 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR08 Security attributes of registers for the IRQCRn register 8 8 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR09 Security attributes of registers for the IRQCRn register 9 9 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR10 Security attributes of registers for the IRQCRn register 10 10 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR11 Security attributes of registers for the IRQCRn register 11 11 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR12 Security attributes of registers for the IRQCRn register 12 12 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR13 Security attributes of registers for the IRQCRn register 13 13 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR14 Security attributes of registers for the IRQCRn register 14 14 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR15 Security attributes of registers for the IRQCRn register 15 15 read-write 0 Secure #0 1 Non-secure #1 ICUSARB Interrupt Controller Unit Security Attribution Register B 0x44 32 read-write 0xffffffff 0xffffffff SANMI Security attributes of registers for nonmaskable interrupt 0 0 read-write 0 Secure #0 1 Non-secure #1 ICUSARC Interrupt Controller Unit Security Attribution Register C 0x48 32 read-write 0xffffffff 0xffffffff SADMAC0 Security attributes of registers for DMAC channel 0 0 read-write 0 Secure #0 1 Non-secure #1 SADMAC1 Security attributes of registers for DMAC channel 1 1 read-write 0 Secure #0 1 Non-secure #1 SADMAC2 Security attributes of registers for DMAC channel 2 2 read-write 0 Secure #0 1 Non-secure #1 SADMAC3 Security attributes of registers for DMAC channel 3 3 read-write 0 Secure #0 1 Non-secure #1 SADMAC4 Security attributes of registers for DMAC channel 4 4 read-write 0 Secure #0 1 Non-secure #1 SADMAC5 Security attributes of registers for DMAC channel 5 5 read-write 0 Secure #0 1 Non-secure #1 SADMAC6 Security attributes of registers for DMAC channel 6 6 read-write 0 Secure #0 1 Non-secure #1 SADMAC7 Security attributes of registers for DMAC channel 7 7 read-write 0 Secure #0 1 Non-secure #1 ICUSARD Interrupt Controller Unit Security Attribution Register D 0x4C 32 read-write 0xffffffff 0xffffffff SASELSR0 Security attributes of registers for SELSR0 0 0 read-write 0 Secure #0 1 Non-secure #1 ICUSARF Interrupt Controller Unit Security Attribution Register F 0x54 32 read-write 0xffffffff 0xffffffff SAAGT3UDWUP Security attributes of registers for WUPEN1.b0 0 0 read-write 0 Secure #0 1 Non-secure #1 SAAGT3CAWUP Security attributes of registers for WUPEN1.b1 1 1 read-write 0 Secure #0 1 Non-secure #1 SAAGT3CBWUP Security attributes of registers for WUPEN1.b2 2 2 read-write 0 Secure #0 1 Non-secure #1 ICUSARG Interrupt Controller Unit Security Attribution Register G 0x70 32 read-write 0xffffffff 0xffffffff SAIELSR00 Security attributes of registers for IELSR31 to IELSR0 0 0 read-write 0 Secure #0 1 Non-secure #1 SAIELSR01 Security attributes of registers for IELSR31 to IELSR0 1 1 read-write 0 Secure #0 1 Non-secure #1 SAIELSR02 Security attributes of registers for IELSR31 to IELSR0 2 2 read-write 0 Secure #0 1 Non-secure #1 SAIELSR03 Security attributes of registers for IELSR31 to IELSR0 3 3 read-write 0 Secure #0 1 Non-secure #1 SAIELSR04 Security attributes of registers for IELSR31 to IELSR0 4 4 read-write 0 Secure #0 1 Non-secure #1 SAIELSR05 Security attributes of registers for IELSR31 to IELSR0 5 5 read-write 0 Secure #0 1 Non-secure #1 SAIELSR06 Security attributes of registers for IELSR31 to IELSR0 6 6 read-write 0 Secure #0 1 Non-secure #1 SAIELSR07 Security attributes of registers for IELSR31 to IELSR0 7 7 read-write 0 Secure #0 1 Non-secure #1 SAIELSR08 Security attributes of registers for IELSR31 to IELSR0 8 8 read-write 0 Secure #0 1 Non-secure #1 SAIELSR09 Security attributes of registers for IELSR31 to IELSR0 9 9 read-write 0 Secure #0 1 Non-secure #1 SAIELSR10 Security attributes of registers for IELSR31 to IELSR0 10 10 read-write 0 Secure #0 1 Non-secure #1 SAIELSR11 Security attributes of registers for IELSR31 to IELSR0 11 11 read-write 0 Secure #0 1 Non-secure #1 SAIELSR12 Security attributes of registers for IELSR31 to IELSR0 12 12 read-write 0 Secure #0 1 Non-secure #1 SAIELSR13 Security attributes of registers for IELSR31 to IELSR0 13 13 read-write 0 Secure #0 1 Non-secure #1 SAIELSR14 Security attributes of registers for IELSR31 to IELSR0 14 14 read-write 0 Secure #0 1 Non-secure #1 SAIELSR15 Security attributes of registers for IELSR31 to IELSR0 15 15 read-write 0 Secure #0 1 Non-secure #1 SAIELSR16 Security attributes of registers for IELSR31 to IELSR0 16 16 read-write 0 Secure #0 1 Non-secure #1 SAIELSR17 Security attributes of registers for IELSR31 to IELSR0 17 17 read-write 0 Secure #0 1 Non-secure #1 SAIELSR18 Security attributes of registers for IELSR31 to IELSR0 18 18 read-write 0 Secure #0 1 Non-secure #1 SAIELSR19 Security attributes of registers for IELSR31 to IELSR0 19 19 read-write 0 Secure #0 1 Non-secure #1 SAIELSR20 Security attributes of registers for IELSR31 to IELSR0 20 20 read-write 0 Secure #0 1 Non-secure #1 SAIELSR21 Security attributes of registers for IELSR31 to IELSR0 21 21 read-write 0 Secure #0 1 Non-secure #1 SAIELSR22 Security attributes of registers for IELSR31 to IELSR0 22 22 read-write 0 Secure #0 1 Non-secure #1 SAIELSR23 Security attributes of registers for IELSR31 to IELSR0 23 23 read-write 0 Secure #0 1 Non-secure #1 SAIELSR24 Security attributes of registers for IELSR31 to IELSR0 24 24 read-write 0 Secure #0 1 Non-secure #1 SAIELSR25 Security attributes of registers for IELSR31 to IELSR0 25 25 read-write 0 Secure #0 1 Non-secure #1 SAIELSR26 Security attributes of registers for IELSR31 to IELSR0 26 26 read-write 0 Secure #0 1 Non-secure #1 SAIELSR27 Security attributes of registers for IELSR31 to IELSR0 27 27 read-write 0 Secure #0 1 Non-secure #1 SAIELSR28 Security attributes of registers for IELSR31 to IELSR0 28 28 read-write 0 Secure #0 1 Non-secure #1 SAIELSR29 Security attributes of registers for IELSR31 to IELSR0 29 29 read-write 0 Secure #0 1 Non-secure #1 SAIELSR30 Security attributes of registers for IELSR31 to IELSR0 30 30 read-write 0 Secure #0 1 Non-secure #1 SAIELSR31 Security attributes of registers for IELSR31 to IELSR0 31 31 read-write 0 Secure #0 1 Non-secure #1 ICUSARH Interrupt Controller Unit Security Attribution Register H 0x74 32 read-write 0xffffffff 0xffffffff SAIELSR32 Security attributes of registers for IELSR63 to IELSR32 0 0 read-write 0 Secure #0 1 Non-secure #1 SAIELSR33 Security attributes of registers for IELSR63 to IELSR32 1 1 read-write 0 Secure #0 1 Non-secure #1 SAIELSR34 Security attributes of registers for IELSR63 to IELSR32 2 2 read-write 0 Secure #0 1 Non-secure #1 SAIELSR35 Security attributes of registers for IELSR63 to IELSR32 3 3 read-write 0 Secure #0 1 Non-secure #1 SAIELSR36 Security attributes of registers for IELSR63 to IELSR32 4 4 read-write 0 Secure #0 1 Non-secure #1 SAIELSR37 Security attributes of registers for IELSR63 to IELSR32 5 5 read-write 0 Secure #0 1 Non-secure #1 SAIELSR38 Security attributes of registers for IELSR63 to IELSR32 6 6 read-write 0 Secure #0 1 Non-secure #1 SAIELSR39 Security attributes of registers for IELSR63 to IELSR32 7 7 read-write 0 Secure #0 1 Non-secure #1 SAIELSR40 Security attributes of registers for IELSR63 to IELSR32 8 8 read-write 0 Secure #0 1 Non-secure #1 SAIELSR41 Security attributes of registers for IELSR63 to IELSR32 9 9 read-write 0 Secure #0 1 Non-secure #1 SAIELSR42 Security attributes of registers for IELSR63 to IELSR32 10 10 read-write 0 Secure #0 1 Non-secure #1 SAIELSR43 Security attributes of registers for IELSR63 to IELSR32 11 11 read-write 0 Secure #0 1 Non-secure #1 SAIELSR44 Security attributes of registers for IELSR63 to IELSR32 12 12 read-write 0 Secure #0 1 Non-secure #1 SAIELSR45 Security attributes of registers for IELSR63 to IELSR32 13 13 read-write 0 Secure #0 1 Non-secure #1 SAIELSR46 Security attributes of registers for IELSR63 to IELSR32 14 14 read-write 0 Secure #0 1 Non-secure #1 SAIELSR47 Security attributes of registers for IELSR63 to IELSR32 15 15 read-write 0 Secure #0 1 Non-secure #1 SAIELSR48 Security attributes of registers for IELSR63 to IELSR32 16 16 read-write 0 Secure #0 1 Non-secure #1 SAIELSR49 Security attributes of registers for IELSR63 to IELSR32 17 17 read-write 0 Secure #0 1 Non-secure #1 SAIELSR50 Security attributes of registers for IELSR63 to IELSR32 18 18 read-write 0 Secure #0 1 Non-secure #1 SAIELSR51 Security attributes of registers for IELSR63 to IELSR32 19 19 read-write 0 Secure #0 1 Non-secure #1 SAIELSR52 Security attributes of registers for IELSR63 to IELSR32 20 20 read-write 0 Secure #0 1 Non-secure #1 SAIELSR53 Security attributes of registers for IELSR63 to IELSR32 21 21 read-write 0 Secure #0 1 Non-secure #1 SAIELSR54 Security attributes of registers for IELSR63 to IELSR32 22 22 read-write 0 Secure #0 1 Non-secure #1 SAIELSR55 Security attributes of registers for IELSR63 to IELSR32 23 23 read-write 0 Secure #0 1 Non-secure #1 SAIELSR56 Security attributes of registers for IELSR63 to IELSR32 24 24 read-write 0 Secure #0 1 Non-secure #1 SAIELSR57 Security attributes of registers for IELSR63 to IELSR32 25 25 read-write 0 Secure #0 1 Non-secure #1 SAIELSR58 Security attributes of registers for IELSR63 to IELSR32 26 26 read-write 0 Secure #0 1 Non-secure #1 SAIELSR59 Security attributes of registers for IELSR63 to IELSR32 27 27 read-write 0 Secure #0 1 Non-secure #1 SAIELSR60 Security attributes of registers for IELSR63 to IELSR32 28 28 read-write 0 Secure #0 1 Non-secure #1 SAIELSR61 Security attributes of registers for IELSR63 to IELSR32 29 29 read-write 0 Secure #0 1 Non-secure #1 SAIELSR62 Security attributes of registers for IELSR63 to IELSR32 30 30 read-write 0 Secure #0 1 Non-secure #1 SAIELSR63 Security attributes of registers for IELSR63 to IELSR32 31 31 read-write 0 Secure #0 1 Non-secure #1 ICUSARI Interrupt Controller Unit Security Attribution Register I 0x78 32 read-write 0xffffffff 0xffffffff SAIELSR64 Security attributes of registers for IELSR95 to IELSR64 0 0 read-write 0 Secure #0 1 Non-secure #1 SAIELSR65 Security attributes of registers for IELSR95 to IELSR64 1 1 read-write 0 Secure #0 1 Non-secure #1 SAIELSR66 Security attributes of registers for IELSR95 to IELSR64 2 2 read-write 0 Secure #0 1 Non-secure #1 SAIELSR67 Security attributes of registers for IELSR95 to IELSR64 3 3 read-write 0 Secure #0 1 Non-secure #1 SAIELSR68 Security attributes of registers for IELSR95 to IELSR64 4 4 read-write 0 Secure #0 1 Non-secure #1 SAIELSR69 Security attributes of registers for IELSR95 to IELSR64 5 5 read-write 0 Secure #0 1 Non-secure #1 SAIELSR70 Security attributes of registers for IELSR95 to IELSR64 6 6 read-write 0 Secure #0 1 Non-secure #1 SAIELSR71 Security attributes of registers for IELSR95 to IELSR64 7 7 read-write 0 Secure #0 1 Non-secure #1 SAIELSR72 Security attributes of registers for IELSR95 to IELSR64 8 8 read-write 0 Secure #0 1 Non-secure #1 SAIELSR73 Security attributes of registers for IELSR95 to IELSR64 9 9 read-write 0 Secure #0 1 Non-secure #1 SAIELSR74 Security attributes of registers for IELSR95 to IELSR64 10 10 read-write 0 Secure #0 1 Non-secure #1 SAIELSR75 Security attributes of registers for IELSR95 to IELSR64 11 11 read-write 0 Secure #0 1 Non-secure #1 SAIELSR76 Security attributes of registers for IELSR95 to IELSR64 12 12 read-write 0 Secure #0 1 Non-secure #1 SAIELSR77 Security attributes of registers for IELSR95 to IELSR64 13 13 read-write 0 Secure #0 1 Non-secure #1 SAIELSR78 Security attributes of registers for IELSR95 to IELSR64 14 14 read-write 0 Secure #0 1 Non-secure #1 SAIELSR79 Security attributes of registers for IELSR95 to IELSR64 15 15 read-write 0 Secure #0 1 Non-secure #1 SAIELSR80 Security attributes of registers for IELSR95 to IELSR64 16 16 read-write 0 Secure #0 1 Non-secure #1 SAIELSR81 Security attributes of registers for IELSR95 to IELSR64 17 17 read-write 0 Secure #0 1 Non-secure #1 SAIELSR82 Security attributes of registers for IELSR95 to IELSR64 18 18 read-write 0 Secure #0 1 Non-secure #1 SAIELSR83 Security attributes of registers for IELSR95 to IELSR64 19 19 read-write 0 Secure #0 1 Non-secure #1 SAIELSR84 Security attributes of registers for IELSR95 to IELSR64 20 20 read-write 0 Secure #0 1 Non-secure #1 SAIELSR85 Security attributes of registers for IELSR95 to IELSR64 21 21 read-write 0 Secure #0 1 Non-secure #1 SAIELSR86 Security attributes of registers for IELSR95 to IELSR64 22 22 read-write 0 Secure #0 1 Non-secure #1 SAIELSR87 Security attributes of registers for IELSR95 to IELSR64 23 23 read-write 0 Secure #0 1 Non-secure #1 SAIELSR88 Security attributes of registers for IELSR95 to IELSR64 24 24 read-write 0 Secure #0 1 Non-secure #1 SAIELSR89 Security attributes of registers for IELSR95 to IELSR64 25 25 read-write 0 Secure #0 1 Non-secure #1 SAIELSR90 Security attributes of registers for IELSR95 to IELSR64 26 26 read-write 0 Secure #0 1 Non-secure #1 SAIELSR91 Security attributes of registers for IELSR95 to IELSR64 27 27 read-write 0 Secure #0 1 Non-secure #1 SAIELSR92 Security attributes of registers for IELSR95 to IELSR64 28 28 read-write 0 Secure #0 1 Non-secure #1 SAIELSR93 Security attributes of registers for IELSR95 to IELSR64 29 29 read-write 0 Secure #0 1 Non-secure #1 SAIELSR94 Security attributes of registers for IELSR95 to IELSR64 30 30 read-write 0 Secure #0 1 Non-secure #1 SAIELSR95 Security attributes of registers for IELSR95 to IELSR64 31 31 read-write 0 Secure #0 1 Non-secure #1 BUSSARA BUS Security Attribution Register A 0x0100 32 read-write 0xffffffff 0xffffffff BUSSA0 BUS Security Attribution A0 0 0 read-write 0 Secure #0 1 Non-Secure #1 BUSSARB BUS Security Attribution Register B 0x0104 32 read-write 0xffffffff 0xffffffff BUSSB0 BUS Security Attribution B0 0 0 read-write 0 Secure #0 1 Non-Secure #1 MMPUSARA Master Memory Protection Unit Security Attribution Register A 0x130 32 read-write 0xffffffff 0xffffffff MMPUASAn MMPUA Security Attribution (n = 0 to 7) 0 7 read-write 0 Secure #0 1 Non-Secure #1 MMPUSARB Master Memory Protection Unit Security Attribution Register B 0x134 32 read-write 0xffffffff 0xffffffff MMPUBSA0 MMPUB Security Attribution 0 0 read-write 0 Secure #0 1 Non-Secure #1 TZFSAR TrustZone Filter Security Attribution Register 0x180 32 read-write 0xfffffffe 0xffffffff TZFSA0 Security attributes of registers for TrustZone Filter 0 0 read-write 0 Secure #0 1 Non-secure #1 CPUDSAR CPU Debug Security Attribution Register 0x1B0 32 read-write 0xfffffffe 0xffffffff CPUDSA0 CPU Debug Security Attribution 0 0 0 read-write 0 Secure #0 1 Non-secure #1 DBG Debug Function 0x4001B000 0x00 4 registers 0x10 4 registers DBGSTR Debug Status Register 0x00 32 read-only 0x00000000 0xffffffff CDBGPWRUPREQ Debug power-up request 28 28 read-only 0 OCD is not requesting debug power up #0 1 OCD is requesting debug power up #1 CDBGPWRUPACK Debug power-up acknowledge 29 29 read-only 0 Debug power-up request is not acknowledged #0 1 Debug power-up request is acknowledged #1 DBGSTOPCR Debug Stop Control Register 0x10 32 read-write 0x00000003 0xffffffff DBGSTOP_IWDT Mask bit for IWDT reset/interrupt in the OCD run mode 0 0 read-write 0 Enable IWDT reset/interrupt #0 1 Mask IWDT reset/interrupt and stop IWDT counter #1 DBGSTOP_WDT Mask bit for WDT reset/interrupt in the OCD run mode 1 1 read-write 0 Enable WDT reset/interrupt #0 1 Mask WDT reset/interrupt and stop WDT counter #1 DBGSTOP_LVD0 Mask bit for LVD0 reset 16 16 read-write 0 Enable LVD0 reset #0 1 Mask LVD0 reset #1 DBGSTOP_LVD1 Mask bit for LVD1 reset/interrupt 17 17 read-write 0 Enable LVD1 reset/interrupt #0 1 Mask LVD1 reset/interrupt #1 DBGSTOP_LVD2 Mask bit for LVD2 reset/interrupt 18 18 read-write 0 Enable LVD2 reset/interrupt #0 1 Mask LVD2 reset/interrupt #1 DBGSTOP_RPER Mask bit for SRAM parity error reset/interrupt 24 24 read-write 0 Enable SRAM parity error reset/interrupt #0 1 Mask SRAM parity error reset/interrupt #1 DBGSTOP_RECCR Mask bit for SRAM ECC error reset/interrupt 25 25 read-write 0 Enable SRAM ECC error reset/interrupt #0 1 Mask SRAM ECC error reset/interrupt #1 FCACHE SYSTEM/FLASH 0x4001C100 0x00 2 registers 0x04 2 registers 0x1C 1 registers 0x40 2 registers FCACHEE Flash Cache Enable Register 0x000 16 read-write 0x0000 0xffff FCACHEEN Flash Cache Enable 0 0 read-write 0 FCACHE is disabled #0 1 FCACHE is enabled #1 FCACHEIV Flash Cache Invalidate Register 0x004 16 read-write 0x0000 0xffff FCACHEIV Flash Cache Invalidate 0 0 read-write 0 Read: Do not invalidate. Write: The setting is ignored. #0 1 Invalidate FCACHE is invalidated. #1 FLWT Flash Wait Cycle Register 0x01C 8 read-write 0x00 0xff FLWT Flash Wait Cycle 0 2 read-write FSAR Flash Security Attribution Register 0x040 16 read-write 0xffff 0xffff FLWTSA FLWT Security Attribution 0 0 read-write 0 Secure #0 1 Non-Secure #1 FCKMHZSA FCKMHZ Security Attribution 8 8 read-write 0 Secure #0 1 Non-Secure #1 SYSC System Control 0x4001E000 0x0C 2 registers 0x20 4 registers 0x26 1 registers 0x28 3 registers 0x32 1 registers 0x36 1 registers 0x38 5 registers 0x3E 4 registers 0x48 3 registers 0x61 2 registers 0x6C 1 registers 0x74 1 registers 0x88 4 registers 0x92 1 registers 0x94 2 registers 0x98 4 registers 0xA0 1 registers 0xA2 1 registers 0xAA 1 registers 0xC0 2 registers 0xE0 4 registers 0x3C0 20 registers 0x3E0 4 registers 0x3FE 15 registers 0x40E 1 registers 0x410 2 registers 0x413 1 registers 0x416 3 registers 0x41A 2 registers 0x41D 2 registers 0x440 1 registers 0x444 1 registers 0x480 2 registers 0x490 1 registers 0x492 1 registers 0x4BB 1 registers 0x4C0 1 registers 0x500 128 registers SBYCR Standby Control Register 0x00C 16 read-write 0x4000 0xffff SSBY Software Standby Mode Select 15 15 read-write 0 Sleep mode #0 1 Software Standby mode. #1 SCKDIVCR System Clock Division Control Register 0x020 32 read-write 0x22022222 0xffffffff PCKD Peripheral Module Clock D (PCLKD) Select 0 2 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Setting prohibited. true PCKC Peripheral Module Clock C (PCLKC) Select 4 6 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Setting prohibited. true PCKB Peripheral Module Clock B (PCLKB) Select 8 10 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Setting prohibited. true PCKA Peripheral Module Clock A (PCLKA) Select 12 14 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Setting prohibited. true RSV Reserved. Set these bits to the same value as PCKB[2:0]. 16 18 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Settings prohibited true ICK System Clock (ICLK) Select 24 26 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Setting prohibited. true FCK FlashIF Clock (FCLK) Select 28 30 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Setting prohibited. true SCKSCR System Clock Source Control Register 0x026 8 read-write 0x01 0xff CKSEL Clock Source Select 0 2 read-write 000 HOCO #000 001 MOCO #001 010 LOCO #010 011 Main clock oscillator (MOSC) #011 100 Sub-clock oscillator (SOSC) #100 101 PLL #101 110 Setting prohibited #110 111 Setting prohibited #111 PLLCCR PLL Clock Control Register 0x028 16 read-write 0x1300 0xffff PLIDIV PLL Input Frequency Division Ratio Select 0 1 read-write 00 /1 #00 01 /2 #01 10 /3 #10 Others Setting prohibited. true PLSRCSEL PLL Clock Source Select 4 4 read-write 0 Main clock oscillator #0 1 HOCO #1 PLLMUL PLL Frequency Multiplication Factor Select 8 13 read-write 0x13 0x3B PLLCR PLL Control Register 0x02A 8 read-write 0x01 0xff PLLSTP PLL Stop Control 0 0 read-write 0 PLL is operating #0 1 PLL is stopped. #1 MOSCCR Main Clock Oscillator Control Register 0x032 8 read-write 0x01 0xff MOSTP Main Clock Oscillator Stop 0 0 read-write 0 Operate the main clock oscillator #0 1 Stop the main clock oscillator #1 HOCOCR High-Speed On-Chip Oscillator Control Register 0x036 8 read-write 0x00 0xfe HCSTP HOCO Stop 0 0 read-write 0 Operate the HOCO clock #0 1 Stop the HOCO clock #1 MOCOCR Middle-Speed On-Chip Oscillator Control Register 0x038 8 read-write 0x00 0xff MCSTP MOCO Stop 0 0 read-write 0 MOCO clock is operating #0 1 MOCO clock is stopped #1 FLLCR1 FLL Control Register1 0x039 8 read-write 0x00 0xff FLLEN FLL Enable 0 0 read-write 0 FLL function is disabled #0 1 FLL function is enabled. #1 FLLCR2 FLL Control Register2 0x03A 16 read-write 0x0000 0xffff FLLCNTL FLL Multiplication Control 0 10 read-write OSCSF Oscillation Stabilization Flag Register 0x03C 8 read-only 0x00 0xfe HOCOSF HOCO Clock Oscillation Stabilization Flag 0 0 read-only 0 The HOCO clock is stopped or is not yet stable #0 1 The HOCO clock is stable, so is available for use as the system clock #1 MOSCSF Main Clock Oscillation Stabilization Flag 3 3 read-only 0 The main clock oscillator is stopped (MOSTP = 1) or is not yet stable #0 1 The main clock oscillator is stable, so is available for use as the system clock #1 PLLSF PLL Clock Oscillation Stabilization Flag 5 5 read-only 0 The PLL clock is stopped, or oscillation of the PLL clock is not stable yet #0 1 The PLL clock is stable, so is available for use as the system clock #1 PLL2SF PLL2 Clock Oscillation Stabilization Flag 6 6 read-only 0 The PLL2 clock is stopped, or oscillation of the PLL2 clock is not stable yet #0 1 The PLL2 clock is stable #1 CKOCR Clock Out Control Register 0x03E 8 read-write 0x00 0xff CKOSEL Clock Out Source Select 0 2 read-write 000 HOCO (value after reset) #000 001 MOCO #001 010 LOCO #010 011 MOSC #011 100 SOSC #100 101 Setting prohibited #101 Others Setting prohibited true CKODIV Clock Output Frequency Division Ratio 4 6 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 111 x 1/128 #111 CKOEN Clock Out Enable 7 7 read-write 0 Disable clock out #0 1 Enable clock out #1 TRCKCR Trace Clock Control Register 0x03F 8 read-write 0x01 0xff TRCK Trace Clock operating frequency select 0 3 read-write 0x0 /1 0x0 0x1 /2 (value after reset) 0x1 0x2 /4 0x2 Others Setting prohibited true TRCKEN Trace Clock operating Enable 7 7 read-write 0 Stop #0 1 Operation enable #1 OSTDCR Oscillation Stop Detection Control Register 0x040 8 read-write 0x00 0xff OSTDIE Oscillation Stop Detection Interrupt Enable 0 0 read-write 0 Disable oscillation stop detection interrupt (do not notify the POEG) #0 1 Enable oscillation stop detection interrupt (notify the POEG) #1 OSTDE Oscillation Stop Detection Function Enable 7 7 read-write 0 Disable oscillation stop detection function #0 1 Enable oscillation stop detection function #1 OSTDSR Oscillation Stop Detection Status Register 0x041 8 read-write 0x00 0xff OSTDF Oscillation Stop Detection Flag 0 0 read-write 0 Main clock oscillation stop not detected #0 1 Main clock oscillation stop detected #1 PLL2CCR PLL2 Clock Control Register 0x048 16 read-write 0x1300 0xffff PL2IDIV PLL2 Input Frequency Division Ratio Select 0 1 read-write 00 ∕ 1 (value after reset) #00 01 ∕ 2 #01 10 ∕ 3 #10 Others Setting prohibited. true PL2SRCSEL PLL2 Clock Source Select 4 4 read-write 0 Main clock oscillator #0 1 HOCO #1 PLL2MUL PLL2 Frequency Multiplication Factor Select 8 13 read-write PLL2CR PLL2 Control Register 0x04A 8 read-write 0x01 0xff PLL2STP PLL2 Stop Control 0 0 read-write 0 PLL2 is operating #0 1 PLL2 is stopped. #1 MOCOUTCR MOCO User Trimming Control Register 0x061 8 read-write 0x00 0xff MOCOUTRM MOCO User Trimming 0 7 read-write HOCOUTCR HOCO User Trimming Control Register 0x062 8 read-write 0x00 0xff HOCOUTRM HOCO User Trimming 0 7 read-write USBCKDIVCR USB Clock Division Control Register 0x06C 8 read-write 0x00 0xff USBCKDIV USB Clock (USBCLK) Division Select 0 2 read-write 010 ∕ 4 #010 101 ∕ 3 #101 110 ∕ 5 #110 Others Setting prohibited. true USBCKCR USB Clock Control Register 0x074 8 read-write 0x01 0xff USBCKSEL USB Clock (USBCLK) Source Select 0 2 read-write 101 PLL #101 110 PLL2 #110 Others Setting prohibited. true USBCKSREQ USB Clock (USBCLK) Switching Request 6 6 read-write 0 No request #0 1 Request switching. #1 USBCKSRDY USB Clock (USBCLK) Switching Ready state flag 7 7 read-only 0 Impossible to Switch #0 1 Possible to Switch #1 SNZREQCR1 Snooze Request Control Register 1 0x088 32 read-write 0x00000000 0xffffffff SNZREQEN0 Enable AGT3 underflow snooze request 0 0 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN1 Enable AGT3 compare match A snooze request 1 1 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN2 Enable AGT3 compare match B snooze request 2 2 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZCR Snooze Control Register 0x092 8 read-write 0x00 0xff RXDREQEN RXD0 Snooze Request Enable 0 0 read-write 0 Ignore RXD0 falling edge in Software Standby mode #0 1 Detect RXD0 falling edge in Software Standby mode #1 SNZDTCEN DTC Enable in Snooze mode 1 1 read-write 0 Disable DTC operation #0 1 Enable DTC operation #1 SNZE Snooze mode Enable 7 7 read-write 0 Disable Snooze mode #0 1 Enable Snooze mode #1 SNZEDCR0 Snooze End Control Register 0 0x094 8 read-write 0x00 0xff AGTUNFED AGT1 Underflow Snooze End Enable 0 0 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 DTCZRED Last DTC Transmission Completion Snooze End Enable 1 1 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 DTCNZRED Not Last DTC Transmission Completion Snooze End Enable 2 2 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 AD0MATED ADC12 Compare Match Snooze End Enable 3 3 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 AD0UMTED ADC12 Compare Mismatch Snooze End Enable 4 4 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 SCI0UMTED SCI0 Address Mismatch Snooze End Enable 7 7 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 SNZEDCR1 Snooze End Control Register 1 0x095 8 read-write 0x00 0xff AGT3UNFED AGT3 underflow Snooze End Enable 0 0 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 SNZREQCR0 Snooze Request Control Register 0 0x098 32 read-write 0x00000000 0xffffffff SNZREQEN0 Enable IRQ0 pin snooze request 0 0 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN1 Enable IRQ1 pin snooze request 1 1 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN2 Enable IRQ2 pin snooze request 2 2 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN3 Enable IRQ3 pin snooze request 3 3 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN4 Enable IRQ4 pin snooze request 4 4 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN5 Enable IRQ5 pin snooze request 5 5 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN6 Enable IRQ6 pin snooze request 6 6 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN7 Enable IRQ7 pin snooze request 7 7 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN8 Enable IRQ8 pin snooze request 8 8 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN9 Enable IRQ9 pin snooze request 9 9 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN10 Enable IRQ10 pin snooze request 10 10 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN11 Enable IRQ11 pin snooze request 11 11 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN12 Enable IRQ12 pin snooze request 12 12 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN13 Enable IRQ13 pin snooze request 13 13 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN14 Enable IRQ14 pin snooze request 14 14 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN15 Enable IRQ15 pin snooze request 15 15 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN24 Enable RTC alarm snooze request 24 24 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN25 Enable RTC period snooze request 25 25 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN28 Enable AGT1 underflow snooze request 28 28 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN29 Enable AGT1 compare match A snooze request 29 29 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN30 Enable AGT1 compare match B snooze request 30 30 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 OPCCR Operating Power Control Register 0x0A0 8 read-write 0x00 0xff OPCM Operating Power Control Mode Select 0 1 read-write 00 High-speed mode #00 01 Setting prohibited #01 10 Setting prohibited #10 11 Low-speed mode #11 OPCMTSF Operating Power Control Mode Transition Status Flag 4 4 read-only 0 Transition completed #0 1 During transition #1 MOSCWTCR Main Clock Oscillator Wait Control Register 0x0A2 8 read-write 0x05 0xff MSTS Main Clock Oscillator Wait Time Setting 0 3 read-write 0x0 Wait time = 3 cycles (11.4 us) 0x0 0x1 Wait time = 35 cycles (133.5 us) 0x1 0x2 Wait time = 67 cycles (255.6 us) 0x2 0x3 Wait time = 131 cycles (499.7 us) 0x3 0x4 Wait time = 259 cycles (988.0 us) 0x4 0x5 Wait time = 547 cycles (2086.6 us) 0x5 0x6 Wait time = 1059 cycles (4039.8 us) 0x6 0x7 Wait time = 2147 cycles (8190.2 us) 0x7 0x8 Wait time = 4291 cycles (16368.9 us) 0x8 0x9 Wait time = 8163 cycles (31139.4 us) 0x9 Others Setting prohibited true SOPCCR Sub Operating Power Control Register 0x0AA 8 read-write 0x00 0xff SOPCM Sub Operating Power Control Mode Select 0 0 read-write 0 Other than Subosc-speed mode #0 1 Subosc-speed mode #1 SOPCMTSF Operating Power Control Mode Transition Status Flag 4 4 read-only 0 Transition completed #0 1 During transition #1 RSTSR1 Reset Status Register 1 0x0C0 16 read-write 0x0000 0xd4f8 IWDTRF Independent Watchdog Timer Reset Detect Flag 0 0 read-write 0 Independent watchdog timer reset not detected #0 1 Independent watchdog timer reset detected #1 WDTRF Watchdog Timer Reset Detect Flag 1 1 read-write 0 Watchdog timer reset not detected #0 1 Watchdog timer reset detected #1 SWRF Software Reset Detect Flag 2 2 read-write 0 Software reset not detected #0 1 Software reset detected #1 RPERF SRAM Parity Error Reset Detect Flag 8 8 read-write 0 SRAM parity error reset not detected #0 1 SRAM parity error reset detected #1 REERF SRAM ECC Error Reset Detect Flag 9 9 read-write 0 SRAM ECC error reset not detected #0 1 SRAM ECC error reset detected #1 BUSMRF Bus Master MPU Error Reset Detect Flag 11 11 read-write 0 Bus master MPU error reset not detected #0 1 Bus master MPU error reset detected #1 TZERF TrustZone Error Reset Detect Flag 13 13 read-write 0 TrustZone error reset not detected. #0 1 TrustZone error reset detected. #1 LVD1CR1 Voltage Monitor 1 Circuit Control Register 0x0E0 8 read-write 0x01 0xff IDTSEL Voltage Monitor 1 Interrupt Generation Condition Select 0 1 read-write 00 When VCC >= Vdet1 (rise) is detected #00 01 When VCC < Vdet1 (fall) is detected #01 10 When fall and rise are detected #10 11 Settings prohibited #11 IRQSEL Voltage Monitor 1 Interrupt Type Select 2 2 read-write 0 Non-maskable interrupt #0 1 Maskable interrupt #1 LVD1SR Voltage Monitor 1 Circuit Status Register 0x0E1 8 read-write 0x02 0xff DET Voltage Monitor 1 Voltage Variation Detection Flag 0 0 read-write 0 Not detected #0 1 Vdet1 crossing is detected #1 MON Voltage Monitor 1 Signal Monitor Flag 1 1 read-only 0 VCC < Vdet1 #0 1 VCC >= Vdet1 or MON is disabled #1 LVD2CR1 Voltage Monitor 2 Circuit Control Register 1 0x0E2 8 read-write 0x01 0xff IDTSEL Voltage Monitor 2 Interrupt Generation Condition Select 0 1 read-write 00 When VCC>= Vdet2 (rise) is detected #00 01 When VCC < Vdet2 (fall) is detected #01 10 When fall and rise are detected #10 11 Settings prohibited #11 IRQSEL Voltage Monitor 2 Interrupt Type Select 2 2 read-write 0 Non-maskable interrupt #0 1 Maskable interrupt #1 LVD2SR Voltage Monitor 2 Circuit Status Register 0x0E3 8 read-write 0x02 0xff DET Voltage Monitor 2 Voltage Variation Detection Flag 0 0 read-write 0 Not detected #0 1 Vdet2 crossing is detected #1 MON Voltage Monitor 2 Signal Monitor Flag 1 1 read-only 0 VCC < Vdet2 #0 1 VCC>= Vdet2 or MON is disabled #1 CGFSAR Clock Generation Function Security Attribute Register 0x3C0 32 read-write 0xffffffff 0xffffffff NONSEC00 Non Secure Attribute bit 00 0 0 read-write 0 Secure #0 1 Non Secure #1 NONSEC02 Non Secure Attribute bit 02 2 2 read-write 0 Secure #0 1 Non Secure #1 NONSEC03 Non Secure Attribute bit 03 3 3 read-write 0 Secure #0 1 Non Secure #1 NONSEC04 Non Secure Attribute bit 04 4 4 read-write 0 Secure #0 1 Non Secure #1 NONSEC05 Non Secure Attribute bit 05 5 5 read-write 0 Secure #0 1 Non Secure #1 NONSEC06 Non Secure Attribute bit 06 6 6 read-write 0 Secure #0 1 Non Secure #1 NONSEC07 Non Secure Attribute bit 07 7 7 read-write 0 Secure #0 1 Non Secure #1 NONSEC08 Non Secure Attribute bit 08 8 8 read-write 0 Secure #0 1 Non Secure #1 NONSEC09 Non Secure Attribute bit 09 9 9 read-write 0 Secure #0 1 Non Secure #1 NONSEC11 Non Secure Attribute bit 11 11 11 read-write 0 Secure #0 1 Non Secure #1 NONSEC16 Non Secure Attribute bit 16 16 16 read-write 0 Secure #0 1 Non Secure #1 RSTSAR Reset Security Attribution Register 0x3C4 32 read-write 0xffffffff 0xffffffff NONSEC0 Non Secure Attribute bit 0 0 0 read-write 0 Secure #0 1 Non Secure #1 NONSEC1 Non Secure Attribute bit 1 1 1 read-write 0 Secure #0 1 Non Secure #1 NONSEC2 Non Secure Attribute bit 2 2 2 read-write 0 Secure #0 1 Non Secure #1 LPMSAR Low Power Mode Security Attribution Register 0x3C8 32 read-write 0xffffffff 0xffffffff NONSEC0 Non Secure Attribute bit 0 0 0 read-write 0 Secure #0 1 Non Secure #1 NONSEC2 Non Secure Attribute bit 2 2 2 read-write 0 Secure #0 1 Non Secure #1 NONSEC4 Non Secure Attribute bit 4 4 4 read-write 0 Secure #0 1 Non Secure #1 NONSEC8 Non Secure Attribute bit 8 8 8 read-write 0 Secure #0 1 Non Secure #1 NONSEC9 Non Secure Attribute bit 9 9 9 read-write 0 Secure #0 1 Non Secure #1 NONSEC13 Non Secure Attribute bit 13 13 13 read-write 0 Secure #0 1 Non Secure #1 LVDSAR Low Voltage Detection Security Attribution Register 0x3CC 32 read-write 0xffffffff 0xffffffff NONSEC0 Non Secure Attribute bit 0 0 0 read-write 0 Secure #0 1 Non Secure #1 NONSEC1 Non Secure Attribute bit 1 1 1 read-write 0 Secure #0 1 Non Secure #1 BBFSAR Battery Backup Function Security Attribute Register 0x3D0 32 read-write 0x0000ffff 0xffffffff NONSEC0 Non Secure Attribute bit 0 0 0 read-write 0 Secure #0 1 Non Secure #1 NONSEC1 Non Secure Attribute bit 1 1 1 read-write 0 Secure #0 1 Non Secure #1 NONSEC2 Non Secure Attribute bit 2 2 2 read-write 0 Secure #0 1 Non Secure #1 NONSEC16 Non Secure Attribute bit 16 16 16 read-write 0 Secure #0 1 Non Secure #1 NONSEC17 Non Secure Attribute bit 17 17 17 read-write 0 Secure #0 1 Non Secure #1 NONSEC18 Non Secure Attribute bit 18 18 18 read-write 0 Secure #0 1 Non Secure #1 NONSEC19 Non Secure Attribute bit 19 19 19 read-write 0 Secure #0 1 Non Secure #1 NONSEC20 Non Secure Attribute bit 20 20 20 read-write 0 Secure #0 1 Non Secure #1 NONSEC21 Non Secure Attribute bit 21 21 21 read-write 0 Secure #0 1 Non Secure #1 NONSEC22 Non Secure Attribute bit 22 22 22 read-write 0 Secure #0 1 Non Secure #1 NONSEC23 Non Secure Attribute bit 23 23 23 read-write 0 Secure #0 1 Non Secure #1 DPFSAR Deep Software Standby Interrupt Factor Security Attribution Register 0x3E0 32 read-write 0xffffffff 0xffffffff DPFSA00 Deep Software Standby Interrupt Factor Security Attribute bit 0 0 0 read-write 0 Secure #0 1 Non Secure #1 DPFSA01 Deep Software Standby Interrupt Factor Security Attribute bit 1 1 1 read-write 0 Secure #0 1 Non Secure #1 DPFSA04 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 4 to 12) 4 4 read-write 0 Secure #0 1 Non Secure #1 DPFSA05 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 4 to 12) 5 5 read-write 0 Secure #0 1 Non Secure #1 DPFSA06 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 4 to 12) 6 6 read-write 0 Secure #0 1 Non Secure #1 DPFSA07 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 4 to 12) 7 7 read-write 0 Secure #0 1 Non Secure #1 DPFSA08 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 4 to 12) 8 8 read-write 0 Secure #0 1 Non Secure #1 DPFSA09 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 4 to 12) 9 9 read-write 0 Secure #0 1 Non Secure #1 DPFSA10 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 4 to 12) 10 10 read-write 0 Secure #0 1 Non Secure #1 DPFSA11 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 4 to 12) 11 11 read-write 0 Secure #0 1 Non Secure #1 DPFSA12 Deep Software Standby Interrupt Factor Security Attribute bit n (n = 4 to 12) 12 12 read-write 0 Secure #0 1 Non Secure #1 DPFSA14 Deep Software Standby Interrupt Factor Security Attribute bit 14 14 14 read-write 0 Secure #0 1 Non Secure #1 DPFSA15 Deep Software Standby Interrupt Factor Security Attribute bit 15 15 15 read-write 0 Secure #0 1 Non Secure #1 DPFSA16 Deep Software Standby Interrupt Factor Security Attribute bit 16 16 16 read-write 0 Secure #0 1 Non Secure #1 DPFSA17 Deep Software Standby Interrupt Factor Security Attribute bit 17 17 17 read-write 0 Secure #0 1 Non Secure #1 DPFSA18 Deep Software Standby Interrupt Factor Security Attribute bit 18 18 18 read-write 0 Secure #0 1 Non Secure #1 DPFSA19 Deep Software Standby Interrupt Factor Security Attribute bit 19 19 19 read-write 0 Secure #0 1 Non Secure #1 DPFSA20 Deep Software Standby Interrupt Factor Security Attribute bit 20 20 20 read-write 0 Secure #0 1 Non Secure #1 DPFSA24 Deep Software Standby Interrupt Factor Security Attribute bit 24 24 24 read-write 0 Secure #0 1 Non Secure #1 DPFSA26 Deep Software Standby Interrupt Factor Security Attribute bit 26 26 26 read-write 0 Secure #0 1 Non Secure #1 DPFSA27 Deep Software Standby Interrupt Factor Security Attribute bit 27 27 27 read-write 0 Secure #0 1 Non Secure #1 PRCR Protect Register 0x3FE 16 read-write 0x0000 0xffff PRC0 Enable writing to the registers related to the clock generation circuit 0 0 read-write 0 Disable writes #0 1 Enable writes #1 PRC1 Enable writing to the registers related to the low power modes, and the battery backup function 1 1 read-write 0 Disable writes #0 1 Enable writes #1 PRC3 Enable writing to the registers related to the LVD 3 3 read-write 0 Disable writes #0 1 Enable writes #1 PRC4 4 4 read-write 0 Disable writes #0 1 Enable writes #1 PRKEY PRC Key Code 8 15 write-only DPSBYCR Deep Software Standby Control Register 0x400 8 read-write 0x01 0xff DEEPCUT Power-Supply Control 0 1 read-write 00 Power to the standby RAM, Low-speed on-chip oscillator, AGTn (n = 0 to 3), and USBFS resume detecting unit is supplied in Deep Software Standby mode. #00 01 Power to the standby RAM, Low-speed on-chip oscillator, AGT, and USBFS resume detecting unit is not supplied in Deep Software Standby mode. #01 10 Setting prohibited #10 11 Power to the standby RAM, Low-speed on-chip oscillator, AGT, and USBFS resume detecting unit is not supplied in Deep Software Standby mode. In addition, LVD is disabled and the low power function in a power-on reset circuit is enabled. #11 IOKEEP I/O Port Rentention 6 6 read-write 0 When the Deep Software Standby mode is canceled, the I/O ports are in the reset state. #0 1 When the Deep Software Standby mode is canceled, the I/O ports are in the same state as in the Deep Software Standby mode. #1 DPSBY Deep Software Standby 7 7 read-write 0 Sleep mode (SBYCR.SSBY=0) / Software Standby mode (SBYCR.SSBY=1) #0 1 Sleep mode (SBYCR.SSBY=0) / Deep Software Standby mode (SBYCR.SSBY=1) #1 DPSWCR Deep Software Standby Wait Control Register 0x401 8 read-write 0x19 0xff WTSTS Deep Software Wait Standby Time Setting Bit 0 5 read-write 0x0E Wait cycle for fast recovery 0x0e 0x19 Wait cycle for slow recovery 0x19 Others Setting prohibited true DPSIER0 Deep Software Standby Interrupt Enable Register 0 0x402 8 read-write 0x00 0xff DIRQ0E IRQ0-DS Pin Enable 0 0 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ1E IRQ1-DS Pin Enable 1 1 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ4E IRQ4-DS Pin Enable 4 4 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ5E IRQ5-DS Pin Enable 5 5 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ6E IRQ6-DS Pin Enable 6 6 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ7E IRQ7-DS Pin Enable 7 7 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DPSIER1 Deep Software Standby Interrupt Enable Register 1 0x403 8 read-write 0x00 0xff DIRQ8E IRQ8-DS Pin Enable 0 0 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ9E IRQ9-DS Pin Enable 1 1 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ10E IRQ10-DS Pin Enable 2 2 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ11E IRQ11-DS Pin Enable 3 3 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ12E IRQ12-DS Pin Enable 4 4 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ14E IRQ14-DS Pin Enable 6 6 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ15E IRQ15-DS Pin Enable 7 7 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DPSIER2 Deep Software Standby Interrupt Enable Register 2 0x404 8 read-write 0x00 0xff DLVD1IE LVD1 Deep Software Standby Cancel Signal Enable 0 0 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DLVD2IE LVD2 Deep Software Standby Cancel Signal Enable 1 1 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DRTCIIE RTC Interval interrupt Deep Software Standby Cancel Signal Enable 2 2 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DRTCAIE RTC Alarm interrupt Deep Software Standby Cancel Signal Enable 3 3 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DNMIE NMI Pin Enable 4 4 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DPSIER3 Deep Software Standby Interrupt Enable Register 3 0x405 8 read-write 0x00 0xff DUSBFS0IE USBFS0 Suspend/Resume Deep Software Standby Cancel Signal Enable 0 0 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DAGT1IE AGT1 Underflow Deep Software Standby Cancel Signal Enable 2 2 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DAGT3IE AGT3 Underflow Deep Software Standby Cancel Signal Enable 3 3 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DPSIFR0 Deep Software Standby Interrupt Flag Register 0 0x406 8 read-write 0x00 0xff DIRQ0F IRQ0-DS Pin Deep Software Standby Cancel Flag 0 0 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ1F IRQ1-DS Pin Deep Software Standby Cancel Flag 1 1 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ4F IRQ4-DS Pin Deep Software Standby Cancel Flag 4 4 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ5F IRQ5-DS Pin Deep Software Standby Cancel Flag 5 5 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ6F IRQ6-DS Pin Deep Software Standby Cancel Flag 6 6 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ7F IRQ7-DS Pin Deep Software Standby Cancel Flag 7 7 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DPSIFR1 Deep Software Standby Interrupt Flag Register 1 0x407 8 read-write 0x00 0xff DIRQ8F IRQ8-DS Pin Deep Software Standby Cancel Flag 0 0 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ9F IRQ9-DS Pin Deep Software Standby Cancel Flag 1 1 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ10F IRQ10-DS Pin Deep Software Standby Cancel Flag 2 2 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ11F IRQ11-DS Pin Deep Software Standby Cancel Flag 3 3 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ12F IRQ12-DS Pin Deep Software Standby Cancel Flag 4 4 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ14F IRQ14-DS Pin Deep Software Standby Cancel Flag 6 6 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ15F IRQ15-DS Pin Deep Software Standby Cancel Flag 7 7 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DPSIFR2 Deep Software Standby Interrupt Flag Register 2 0x408 8 read-write 0x00 0xff DLVD1IF LVD1 Deep Software Standby Cancel Flag 0 0 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DLVD2IF LVD2 Deep Software Standby Cancel Flag 1 1 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DRTCIIF RTC Interval Interrupt Deep Software Standby Cancel Flag 2 2 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DRTCAIF RTC Alarm Interrupt Deep Software Standby Cancel Flag 3 3 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DNMIF NMI Pin Deep Software Standby Cancel Flag 4 4 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DPSIFR3 Deep Software Standby Interrupt Flag Register 3 0x409 8 read-write 0x00 0xff DUSBFS0IF USBFS0 Suspend/Resume Deep Software Standby Cancel Flag 0 0 read-write 0 The cancel request is not generated. #0 1 The cancel request is generated. #1 DAGT1IF AGT1 Underflow Deep Software Standby Cancel Flag 2 2 read-write 0 The cancel request is not generated. #0 1 The cancel request is generated. #1 DAGT3IF AGT3 Underflow Deep Software Standby Cancel Flag 3 3 read-write 0 The cancel request is not generated. #0 1 The cancel request is generated. #1 DPSIEGR0 Deep Software Standby Interrupt Edge Register 0 0x40A 8 read-write 0x00 0xff DIRQ0EG IRQ0-DS Pin Edge Select 0 0 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ1EG IRQ1-DS Pin Edge Select 1 1 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ4EG IRQ4-DS Pin Edge Select 4 4 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ5EG IRQ5-DS Pin Edge Select 5 5 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ6EG IRQ6-DS Pin Edge Select 6 6 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ7EG IRQ7-DS Pin Edge Select 7 7 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DPSIEGR1 Deep Software Standby Interrupt Edge Register 1 0x40B 8 read-write 0x00 0xff DIRQ8EG IRQ8-DS Pin Edge Select 0 0 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ9EG IRQ9-DS Pin Edge Select 1 1 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ10EG IRQ10-DS Pin Edge Select 2 2 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge #1 DIRQ11EG IRQ11-DS Pin Edge Select 3 3 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ12EG IRQ12-DS Pin Edge Select 4 4 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ14EG IRQ14-DS Pin Edge Select 6 6 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ15EG IRQ15-DS Pin Edge Select 7 7 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DPSIEGR2 Deep Software Standby Interrupt Edge Register 2 0x40C 8 read-write 0x00 0xff DLVD1EG LVD1 Edge Select 0 0 read-write 0 A cancel request is generated when VCC < Vdet1 (fall) is detected #0 1 A cancel request is generated when VCC ≥ Vdet1 (rise) is detected #1 DLVD2EG LVD2 Edge Select 1 1 read-write 0 A cancel request is generated when VCC < Vdet2 (fall) is detected #0 1 A cancel request is generated when VCC ≥ Vdet2 (rise) is detected #1 DNMIEG NMI Pin Edge Select 4 4 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 SYOCDCR System Control OCD Control Register 0x040E 8 read-write 0x00 0xfe DOCDF Deep Software Standby OCD flag 0 0 read-write 0 DBIRQ is not generated #0 1 DBIRQ is generated #1 DBGEN Debugger Enable bit 7 7 read-write 0 On-chip debugger is disabled #0 1 On-chip debugger is enabled #1 RSTSR0 Reset Status Register 0 0x410 8 read-write 0x00 0x70 PORF Power-On Reset Detect Flag 0 0 read-write 0 Power-on reset not detected #0 1 Power-on reset detected #1 LVD0RF Voltage Monitor 0 Reset Detect Flag 1 1 read-write 0 Voltage monitor 0 reset not detected #0 1 Voltage monitor 0 reset detected #1 LVD1RF Voltage Monitor 1 Reset Detect Flag 2 2 read-write 0 Voltage monitor 1 reset not detected #0 1 Voltage monitor 1 reset detected #1 LVD2RF Voltage Monitor 2 Reset Detect Flag 3 3 read-write 0 Voltage monitor 2 reset not detected #0 1 Voltage monitor 2 reset detected #1 DPSRSTF Deep Software Standby Reset Detect Flag 7 7 read-write 0 Deep software standby mode cancellation not requested by an interrupt. #0 1 Deep software standby mode cancellation requested by an interrupt. #1 RSTSR2 Reset Status Register 2 0x411 8 read-write 0x00 0xfe CWSF Cold/Warm Start Determination Flag 0 0 read-write 0 Cold start #0 1 Warm start #1 MOMCR Main Clock Oscillator Mode Oscillation Control Register 0x413 8 read-write 0x00 0xff MODRV Main Clock Oscillator Drive Capability 0 Switching 4 5 read-write 00 20 MHz to 24 MHz #00 01 16 MHz to 20 MHz #01 10 8 MHz to 16 MHz #10 11 8 MHz #11 MOSEL Main Clock Oscillator Switching 6 6 read-write 0 Resonator #0 1 External clock input #1 FWEPROR Flash P/E Protect Register 0x416 8 read-write 0x02 0xff FLWE Flash Programming and Erasure 0 1 read-write 00 Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing. #00 01 Permits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing. #01 10 Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing. #10 11 Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing. #11 LVD1CMPCR Voltage Monitoring 1 Comparator Control Register 0x417 8 read-write 0x13 0xff LVD1LVL Voltage Detection 1 Level Select (Standard voltage during drop in voltage) 0 4 read-write 0x11 2.99 V (Vdet1_1) 0x11 0x12 2.92 V (Vdet1_2) 0x12 0x13 2.85 V (Vdet1_3) 0x13 Others Setting prohibited true LVD1E Voltage Detection 1 Enable 7 7 read-write 0 Voltage detection 1 circuit disabled #0 1 Voltage detection 1 circuit enabled #1 LVD2CMPCR Voltage Monitoring 2 Comparator Control Register 0x418 8 read-write 0x07 0xff LVD2LVL Voltage Detection 2 Level Select (Standard voltage during drop in voltage) 0 2 read-write 101 2.99 V (Vdet2_1) #101 110 2.92 V (Vdet2_2) #110 111 2.85 V (Vdet2_3) #111 Others Setting prohibited true LVD2E Voltage Detection 2 Enable 7 7 read-write 0 Voltage detection 2 circuit disabled #0 1 Voltage detection 2 circuit enabled #1 LVD1CR0 Voltage Monitor 1 Circuit Control Register 0 0x41A 8 read-write 0x82 0xf7 RIE Voltage Monitor 1 Interrupt/Reset Enable 0 0 read-write 0 Disable #0 1 Enable #1 DFDIS Voltage monitor 1 Digital Filter Disabled Mode Select 1 1 read-write 0 Enable the digital filter #0 1 Disable the digital filter #1 CMPE Voltage Monitor 1 Circuit Comparison Result Output Enable 2 2 read-write 0 Disable voltage monitor 1 circuit comparison result output #0 1 Enable voltage monitor 1 circuit comparison result output #1 FSAMP Sampling Clock Select 4 5 read-write 00 1/2 LOCO frequency #00 01 1/4 LOCO frequency #01 10 1/8 LOCO frequency #10 11 1/16 LOCO frequency #11 RI Voltage Monitor 1 Circuit Mode Select 6 6 read-write 0 Generate voltage monitor 1 interrupt on Vdet1 crossing #0 1 Enable voltage monitor 1 reset when the voltage falls to and below Vdet1 #1 RN Voltage Monitor 1 Reset Negate Select 7 7 read-write 0 Negate after a stabilization time (tLVD1) when VCC > Vdet1 is detected #0 1 Negate after a stabilization time (tLVD1) on assertion of the LVD1 reset #1 LVD2CR0 Voltage Monitor 2 Circuit Control Register 0 0x41B 8 read-write 0x82 0xf7 RIE Voltage Monitor 2 Interrupt/Reset Enable 0 0 read-write 0 Disable #0 1 Enable #1 DFDIS Voltage monitor 2 Digital Filter Disabled Mode Select 1 1 read-write 0 Enable the digital filter #0 1 Disable the digital filter #1 CMPE Voltage Monitor 2 Circuit Comparison Result Output Enable 2 2 read-write 0 Disable voltage monitor 2 circuit comparison result output #0 1 Enable voltage monitor 2 circuit comparison result output #1 FSAMP Sampling Clock Select 4 5 read-write 00 1/2 LOCO frequency #00 01 1/4 LOCO frequency #01 10 1/8 LOCO frequency #10 11 1/16 LOCO frequency #11 RI Voltage Monitor 2 Circuit Mode Select 6 6 read-write 0 Generate voltage monitor 2 interrupt on Vdet2 crossing #0 1 Enable voltage monitor 2 reset when the voltage falls to and below Vdet2 #1 RN Voltage Monitor 2 Reset Negate Select 7 7 read-write 0 Negate after a stabilization time (tLVD2) when VCC > Vdet2 is detected #0 1 Negate after a stabilization time (tLVD2) on assertion of the LVD2 reset #1 VBATTMNSELR Battery Backup Voltage Monitor Function Select Register 0x41D 8 read-write 0x00 0xff VBATTMNSEL VBATT Low Voltage Detect Function Select Bit 0 0 read-write 0 Disables VBATT low voltage detect function #0 1 Enables VBATT low voltage detect function #1 VBATTMONR Battery Backup Voltage Monitor Register 0x41E 8 read-only 0x00 0xff VBATTMON VBATT Voltage Monitor Bit 0 0 read-only 0 VBATT ≥ Vbattldet #0 1 VBATT < Vbattldet #1 LDOSCR LDO Stop Control Register 0x0440 8 read-write 0x00 0xff LDOSTP0 LDO0 Stop 0 0 read-write 0 LDO0 is enabled #0 1 LDO0 is stopped #1 LDOSTP1 LDO1 Stop 1 1 read-write 0 LDO1 is enabled #0 1 LDO1 is stopped #1 PL2LDOSCR PLL2-LDO Stop Control Register 0x0444 8 read-write 0x00 0xff PL2LDOSTP PLL2-LDO Stop 0 0 read-write 0 PLL2-LDO is enabled #0 1 PLL2-LDO is stopped #1 SOSCCR Sub-Clock Oscillator Control Register 0x480 8 read-write 0x00 0xff SOSTP Sub Clock Oscillator Stop 0 0 read-write 0 Operate the sub-clock oscillator #0 1 Stop the sub-clock oscillator #1 SOMCR Sub-Clock Oscillator Mode Control Register 0x481 8 read-write 0x00 0xff SODRV Sub-Clock Oscillator Drive Capability Switching 1 1 read-write 0 Standard #0 1 Low #1 LOCOCR Low-Speed On-Chip Oscillator Control Register 0x490 8 read-write 0x00 0xff LCSTP LOCO Stop 0 0 read-write 0 Operate the LOCO clock #0 1 Stop the LOCO clock #1 LOCOUTCR LOCO User Trimming Control Register 0x492 8 read-write 0x00 0xff LOCOUTRM LOCO User Trimming 0 7 read-write VBTICTLR VBATT Input Control Register 0x4BB 8 read-write 0x00 0xf8 VCH0INEN VBATT CH0 Input Enable 0 0 read-write 0 RTCIC0 input disable #0 1 RTCIC0 input enable #1 VCH1INEN VBATT CH1 Input Enable 1 1 read-write 0 RTCIC1 input disable #0 1 RTCIC1 input enable #1 VCH2INEN VBATT CH2 Input Enable 2 2 read-write 0 RTCIC2 input disable #0 1 RTCIC2 input enable #1 VBTBER VBATT Backup Enable Register 0x4C0 8 read-write 0x08 0xff VBAE VBATT backup register access enable bit 3 3 read-write 0 Disable to access VBTBKR #0 1 Enable to access VBTBKR #1 128 0x001 VBTBKR[%s] VBATT Backup Register 0x500 8 read-write 0x00 0x00 VBTBKR VBATT Backup Register 0 7 read-write PORT0 Pmn Pin FunctionPort 0 Control RegistersPmn Pin Function Control Register 0x40080000 0x00 12 registers PCNTR1 Port Control Register 1 0x000 32 read-write 0x00000000 0xffffffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 31 read-write 0 Low output #0 1 High output #1 PODR Port Control Register 1 PCNTR1 0x000 16 read-write 0x0000 0xffff PODR00 Pmn Output Data 0 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 15 read-write 0 Low output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x002 16 read-write 0x0000 0xffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCNTR2 Port Control Register 2 0x004 32 read-only 0x00000000 0xffff0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 PIDR Port Control Register 2 PCNTR2 0x006 16 read-only 0x0000 0x0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 PCNTR3 Port Control Register 3 0x008 32 write-only 0x00000000 0xffffffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR00 Pmn Output Reset 16 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 31 write-only 0 No effect on output #0 1 Low output #1 PORR Port Control Register 3 PCNTR3 0x008 16 write-only 0x0000 0xffff PORR00 Pmn Output Reset 0 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 15 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0x00A 16 write-only 0x0000 0xffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORT1 Pmn Pin FunctionPort 1 Control RegistersPmn Pin Function Control Register 0x40080020 0x00 16 registers PCNTR1 Port Control Register 1 0x000 32 read-write 0x00000000 0xffffffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 31 read-write 0 Low output #0 1 High output #1 PODR Port Control Register 1 PCNTR1 0x000 16 read-write 0x0000 0xffff PODR00 Pmn Output Data 0 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 15 read-write 0 Low output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x002 16 read-write 0x0000 0xffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCNTR2 Port Control Register 2 0x004 32 read-only 0x00000000 0xffff0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 EIDR00 Port Event Input Data 16 16 read-only 0 Low input #0 1 High input #1 EIDR01 Port Event Input Data 17 17 read-only 0 Low input #0 1 High input #1 EIDR02 Port Event Input Data 18 18 read-only 0 Low input #0 1 High input #1 EIDR03 Port Event Input Data 19 19 read-only 0 Low input #0 1 High input #1 EIDR04 Port Event Input Data 20 20 read-only 0 Low input #0 1 High input #1 EIDR05 Port Event Input Data 21 21 read-only 0 Low input #0 1 High input #1 EIDR06 Port Event Input Data 22 22 read-only 0 Low input #0 1 High input #1 EIDR07 Port Event Input Data 23 23 read-only 0 Low input #0 1 High input #1 EIDR08 Port Event Input Data 24 24 read-only 0 Low input #0 1 High input #1 EIDR09 Port Event Input Data 25 25 read-only 0 Low input #0 1 High input #1 EIDR10 Port Event Input Data 26 26 read-only 0 Low input #0 1 High input #1 EIDR11 Port Event Input Data 27 27 read-only 0 Low input #0 1 High input #1 EIDR12 Port Event Input Data 28 28 read-only 0 Low input #0 1 High input #1 EIDR13 Port Event Input Data 29 29 read-only 0 Low input #0 1 High input #1 EIDR14 Port Event Input Data 30 30 read-only 0 Low input #0 1 High input #1 EIDR15 Port Event Input Data 31 31 read-only 0 Low input #0 1 High input #1 EIDR Port Control Register 2 PCNTR2 0x004 16 read-only 0x0000 0xffff EIDR00 Port Event Input Data 0 0 read-only 0 Low input #0 1 High input #1 EIDR01 Port Event Input Data 1 1 read-only 0 Low input #0 1 High input #1 EIDR02 Port Event Input Data 2 2 read-only 0 Low input #0 1 High input #1 EIDR03 Port Event Input Data 3 3 read-only 0 Low input #0 1 High input #1 EIDR04 Port Event Input Data 4 4 read-only 0 Low input #0 1 High input #1 EIDR05 Port Event Input Data 5 5 read-only 0 Low input #0 1 High input #1 EIDR06 Port Event Input Data 6 6 read-only 0 Low input #0 1 High input #1 EIDR07 Port Event Input Data 7 7 read-only 0 Low input #0 1 High input #1 EIDR08 Port Event Input Data 8 8 read-only 0 Low input #0 1 High input #1 EIDR09 Port Event Input Data 9 9 read-only 0 Low input #0 1 High input #1 EIDR10 Port Event Input Data 10 10 read-only 0 Low input #0 1 High input #1 EIDR11 Port Event Input Data 11 11 read-only 0 Low input #0 1 High input #1 EIDR12 Port Event Input Data 12 12 read-only 0 Low input #0 1 High input #1 EIDR13 Port Event Input Data 13 13 read-only 0 Low input #0 1 High input #1 EIDR14 Port Event Input Data 14 14 read-only 0 Low input #0 1 High input #1 EIDR15 Port Event Input Data 15 15 read-only 0 Low input #0 1 High input #1 PIDR Port Control Register 2 PCNTR2 0x006 16 read-only 0x0000 0x0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 PCNTR3 Port Control Register 3 0x008 32 write-only 0x00000000 0xffffffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR00 Pmn Output Reset 16 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 31 write-only 0 No effect on output #0 1 Low output #1 PORR Port Control Register 3 PCNTR3 0x008 16 write-only 0x0000 0xffff PORR00 Pmn Output Reset 0 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 15 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0x00A 16 write-only 0x0000 0xffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PCNTR4 Port Control Register 4 0x00C 32 read-write 0x00000000 0xffffffff EOSR00 Pmn Event Output Set 0 0 read-write 0 No effect on output #0 1 High output #1 EOSR01 Pmn Event Output Set 1 1 read-write 0 No effect on output #0 1 High output #1 EOSR02 Pmn Event Output Set 2 2 read-write 0 No effect on output #0 1 High output #1 EOSR03 Pmn Event Output Set 3 3 read-write 0 No effect on output #0 1 High output #1 EOSR04 Pmn Event Output Set 4 4 read-write 0 No effect on output #0 1 High output #1 EOSR05 Pmn Event Output Set 5 5 read-write 0 No effect on output #0 1 High output #1 EOSR06 Pmn Event Output Set 6 6 read-write 0 No effect on output #0 1 High output #1 EOSR07 Pmn Event Output Set 7 7 read-write 0 No effect on output #0 1 High output #1 EOSR08 Pmn Event Output Set 8 8 read-write 0 No effect on output #0 1 High output #1 EOSR09 Pmn Event Output Set 9 9 read-write 0 No effect on output #0 1 High output #1 EOSR10 Pmn Event Output Set 10 10 read-write 0 No effect on output #0 1 High output #1 EOSR11 Pmn Event Output Set 11 11 read-write 0 No effect on output #0 1 High output #1 EOSR12 Pmn Event Output Set 12 12 read-write 0 No effect on output #0 1 High output #1 EOSR13 Pmn Event Output Set 13 13 read-write 0 No effect on output #0 1 High output #1 EOSR14 Pmn Event Output Set 14 14 read-write 0 No effect on output #0 1 High output #1 EOSR15 Pmn Event Output Set 15 15 read-write 0 No effect on output #0 1 High output #1 EORR00 Pmn Event Output Reset 16 16 read-write 0 No effect on output #0 1 Low output #1 EORR01 Pmn Event Output Reset 17 17 read-write 0 No effect on output #0 1 Low output #1 EORR02 Pmn Event Output Reset 18 18 read-write 0 No effect on output #0 1 Low output #1 EORR03 Pmn Event Output Reset 19 19 read-write 0 No effect on output #0 1 Low output #1 EORR04 Pmn Event Output Reset 20 20 read-write 0 No effect on output #0 1 Low output #1 EORR05 Pmn Event Output Reset 21 21 read-write 0 No effect on output #0 1 Low output #1 EORR06 Pmn Event Output Reset 22 22 read-write 0 No effect on output #0 1 Low output #1 EORR07 Pmn Event Output Reset 23 23 read-write 0 No effect on output #0 1 Low output #1 EORR08 Pmn Event Output Reset 24 24 read-write 0 No effect on output #0 1 Low output #1 EORR09 Pmn Event Output Reset 25 25 read-write 0 No effect on output #0 1 Low output #1 EORR10 Pmn Event Output Reset 26 26 read-write 0 No effect on output #0 1 Low output #1 EORR11 Pmn Event Output Reset 27 27 read-write 0 No effect on output #0 1 Low output #1 EORR12 Pmn Event Output Reset 28 28 read-write 0 No effect on output #0 1 Low output #1 EORR13 Pmn Event Output Reset 29 29 read-write 0 No effect on output #0 1 Low output #1 EORR14 Pmn Event Output Reset 30 30 read-write 0 No effect on output #0 1 Low output #1 EORR15 Pmn Event Output Reset 31 31 read-write 0 No effect on output #0 1 Low output #1 EORR Port Control Register 4 PCNTR4 0x00C 16 read-write 0x0000 0xffff EORR00 Pmn Event Output Reset 0 0 read-write 0 No effect on output #0 1 Low output #1 EORR01 Pmn Event Output Reset 1 1 read-write 0 No effect on output #0 1 Low output #1 EORR02 Pmn Event Output Reset 2 2 read-write 0 No effect on output #0 1 Low output #1 EORR03 Pmn Event Output Reset 3 3 read-write 0 No effect on output #0 1 Low output #1 EORR04 Pmn Event Output Reset 4 4 read-write 0 No effect on output #0 1 Low output #1 EORR05 Pmn Event Output Reset 5 5 read-write 0 No effect on output #0 1 Low output #1 EORR06 Pmn Event Output Reset 6 6 read-write 0 No effect on output #0 1 Low output #1 EORR07 Pmn Event Output Reset 7 7 read-write 0 No effect on output #0 1 Low output #1 EORR08 Pmn Event Output Reset 8 8 read-write 0 No effect on output #0 1 Low output #1 EORR09 Pmn Event Output Reset 9 9 read-write 0 No effect on output #0 1 Low output #1 EORR10 Pmn Event Output Reset 10 10 read-write 0 No effect on output #0 1 Low output #1 EORR11 Pmn Event Output Reset 11 11 read-write 0 No effect on output #0 1 Low output #1 EORR12 Pmn Event Output Reset 12 12 read-write 0 No effect on output #0 1 Low output #1 EORR13 Pmn Event Output Reset 13 13 read-write 0 No effect on output #0 1 Low output #1 EORR14 Pmn Event Output Reset 14 14 read-write 0 No effect on output #0 1 Low output #1 EORR15 Pmn Event Output Reset 15 15 read-write 0 No effect on output #0 1 Low output #1 EOSR Port Control Register 4 PCNTR4 0x00E 16 read-write 0x0000 0xffff EOSR00 Pmn Event Output Set 0 0 read-write 0 No effect on output #0 1 High output #1 EOSR01 Pmn Event Output Set 1 1 read-write 0 No effect on output #0 1 High output #1 EOSR02 Pmn Event Output Set 2 2 read-write 0 No effect on output #0 1 High output #1 EOSR03 Pmn Event Output Set 3 3 read-write 0 No effect on output #0 1 High output #1 EOSR04 Pmn Event Output Set 4 4 read-write 0 No effect on output #0 1 High output #1 EOSR05 Pmn Event Output Set 5 5 read-write 0 No effect on output #0 1 High output #1 EOSR06 Pmn Event Output Set 6 6 read-write 0 No effect on output #0 1 High output #1 EOSR07 Pmn Event Output Set 7 7 read-write 0 No effect on output #0 1 High output #1 EOSR08 Pmn Event Output Set 8 8 read-write 0 No effect on output #0 1 High output #1 EOSR09 Pmn Event Output Set 9 9 read-write 0 No effect on output #0 1 High output #1 EOSR10 Pmn Event Output Set 10 10 read-write 0 No effect on output #0 1 High output #1 EOSR11 Pmn Event Output Set 11 11 read-write 0 No effect on output #0 1 High output #1 EOSR12 Pmn Event Output Set 12 12 read-write 0 No effect on output #0 1 High output #1 EOSR13 Pmn Event Output Set 13 13 read-write 0 No effect on output #0 1 High output #1 EOSR14 Pmn Event Output Set 14 14 read-write 0 No effect on output #0 1 High output #1 EOSR15 Pmn Event Output Set 15 15 read-write 0 No effect on output #0 1 High output #1 PORT2 Pmn Pin FunctionPort 2 Control RegistersPmn Pin Function Control Register 0x40080040 PORT3 Pmn Pin FunctionPort 3 Control RegistersPmn Pin Function Control Register 0x40080060 PORT4 Pmn Pin FunctionPort 4 Control RegistersPmn Pin Function Control Register 0x40080080 PORT5 Pmn Pin FunctionPort 5 Control RegistersPmn Pin Function Control Register 0x400800A0 PORT6 Pmn Pin FunctionPort 6 Control RegistersPmn Pin Function Control Register 0x400800C0 PORT7 Pmn Pin FunctionPort 7 Control RegistersPmn Pin Function Control Register 0x400800E0 PFS Control Register 0x40080800 0x00 36 registers 0x34 84 registers 0x94 43 registers 0xC0 35 registers 0x100 91 registers 0x180 19 registers 0x1A0 12 registers 0x1E0 4 registers 0x503 1 registers 0x505 1 registers 0x510 16 registers 8 0x4 0-7 P00%sPFS Port 00%s Pin Function Select Register 0x000 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 8 0x4 0-7 P00%sPFS_HA Port 00%s Pin Function Select Register P00%sPFS 0x002 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 8 0x4 0-7 P00%sPFS_BY Port 00%s Pin Function Select Register P00%sPFS 0x003 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 P008PFS Port 008 Pin Function Select Register 0x020 32 read-write 0x00010410 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P008PFS_HA Port 008 Pin Function Select Register P008PFS 0x022 16 read-write 0x0410 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 P008PFS_BY Port 008 Pin Function Select Register P008PFS 0x023 8 read-write 0x10 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 3 0x4 13-15 P0%sPFS Port 0%s Pin Function Select Register 0x034 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 3 0x4 13-15 P0%sPFS_HA Port 0%s Pin Function Select Register P0%sPFS 0x036 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 3 0x4 13-15 P0%sPFS_BY Port 0%s Pin Function Select Register P0%sPFS 0x037 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 10 0x4 0-9 P10%sPFS Port 10%s Pin Function Select Register 0x040 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 10 0x4 0-9 P10%sPFS_HA Port 10%s Pin Function Select Register P10%sPFS 0x042 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 10 0x4 0-9 P10%sPFS_BY Port 10%s Pin Function Select Register P10%sPFS 0x043 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 6 0x4 10-15 P1%sPFS Port 1%s Pin Function Select Register 0x068 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 6 0x4 10-15 P1%sPFS_HA Port 1%s Pin Function Select Register P1%sPFS 0x06A 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 6 0x4 10-15 P1%sPFS_BY Port 1%s Pin Function Select Register P1%sPFS 0x06B 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 P200PFS Port 200 Pin Function Select Register 0x080 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P200PFS_HA Port 200 Pin Function Select Register P200PFS 0x082 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 P200PFS_BY Port 200 Pin Function Select Register P200PFS 0x083 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 P201PFS Port 201 Pin Function Select Register 0x084 32 read-write 0x00000010 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P201PFS_HA Port 201 Pin Function Select Register P201PFS 0x086 16 read-write 0x0010 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 P201PFS_BY Port 201 Pin Function Select Register P201PFS 0x087 8 read-write 0x10 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 5 0x4 5-9 P20%sPFS Port 20%s Pin Function Select Register 0x094 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 5 0x4 5-9 P20%sPFS_HA Port 20%s Pin Function Select Register P20%sPFS 0x096 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 5 0x4 5-9 P20%sPFS_BY Port 20%s Pin Function Select Register P20%sPFS 0x097 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 5 0x4 10-14 P2%sPFS Port 2%s Pin Function Select Register 0x0A8 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 5 0x4 10-14 P2%sPFS_HA Port 2%s Pin Function Select Register P2%sPFS 0x0AA 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 5 0x4 10-14 P2%sPFS_BY Port 2%s Pin Function Select Register P2%sPFS 0x0AB 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 P300PFS Port 300 Pin Function Select Register 0x0C0 32 read-write 0x00010010 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P300PFS_HA Port 300 Pin Function Select Register P300PFS 0x0C2 16 read-write 0x0010 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 P300PFS_BY Port 300 Pin Function Select Register P300PFS 0x0C3 8 read-write 0x10 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 7 0x4 1-7 P30%sPFS Port 30%s Pin Function Select Register 0x0C4 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 7 0x4 1-7 P30%sPFS_HA Port 30%s Pin Function Select Register P30%sPFS 0x0C6 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 7 0x4 1-7 P30%sPFS_BY Port 30%s Pin Function Select Register P30%sPFS 0x0C7 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 10 0x4 0-9 P40%sPFS Port 40%s Pin Function Select Register 0x100 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 10 0x4 0-9 P40%sPFS_HA Port 40%s Pin Function Select Register P40%sPFS 0x102 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 10 0x4 0-9 P40%sPFS_BY Port 40%s Pin Function Select Register P40%sPFS 0x103 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 6 0x4 10-15 P4%sPFS Port 4%s Pin Function Select Register 0x128 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 6 0x4 10-15 P4%sPFS_HA Port 4%s Pin Function Select Register P4%sPFS 0x12A 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 6 0x4 10-15 P4%sPFS_BY Port 4%s Pin Function Select Register P4%sPFS 0x12B 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 6 0x4 0-5 P50%sPFS Port 50%s Pin Function Select Register 0x140 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 6 0x4 0-5 P50%sPFS_HA Port 50%s Pin Function Select Register P50%sPFS 0x142 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 6 0x4 0-5 P50%sPFS_BY Port 50%s Pin Function Select Register P50%sPFS 0x143 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 4 0x4 0-3 P60%sPFS Port 60%s Pin Function Select Register 0x180 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 4 0x4 0-3 P60%sPFS_HA Port 60%s Pin Function Select Register P60%sPFS 0x182 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 4 0x4 0-3 P60%sPFS_BY Port 60%s Pin Function Select Register P60%sPFS 0x183 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 2 0x4 8-9 P60%sPFS Port 60%s Pin Function Select Register 0x1A0 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 2 0x4 8-9 P60%sPFS_HA Port 60%s Pin Function Select Register P60%sPFS 0x1A2 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 2 0x4 8-9 P60%sPFS_BY Port 60%s Pin Function Select Register P60%sPFS 0x1A3 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 P610PFS Port 610 Pin Function Select Register 0x1A8 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P610PFS_HA Port 610 Pin Function Select Register P610PFS 0x1AA 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 Setting prohibited #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 P610PFS_BY Port 610 Pin Function Select Register P610PFS 0x1AB 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 P708PFS Port 708 Pin Function Select Register 0x1E0 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P708PFS_HA Port 708 Pin Function Select Register P708PFS 0x1E2 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 DSCR Port Drive Capability 10 11 read-write 00 Low drive #00 01 Middle drive #01 10 High-speed high-drive #10 11 High drive #11 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 P708PFS_BY Port 708 Pin Function Select Register P708PFS 0x1E3 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PWPR Write-Protect Register 0x503 8 read-write 0x80 0xff PFSWE PmnPFS Register Write Enable 6 6 read-write 0 Writing to the PmnPFS register is disabled #0 1 Writing to the PmnPFS register is enabled #1 B0WI PFSWE Bit Write Disable 7 7 read-write 0 Writing to the PFSWE bit is enabled #0 1 Writing to the PFSWE bit is disabled #1 PWPRS Write-Protect Register for Secure 0x505 8 read-write 0x80 0xff PFSWE PmnPFS Register Write Enable 6 6 read-write 0 Disable writes to the PmnPFS register #0 1 Enable writes to the PmnPFS register #1 B0WI PFSWE Bit Write Disable 7 7 read-write 0 Enable writes the PFSWE bit #0 1 Disable writes to the PFSWE bit #1 8 0x002 0-7 P%sSAR Port Security Attribution register 0x510 16 read-write 0xffff 0xffff PMNSA Pmn Security Attribution 0 15 read-write 0 Secure #0 1 Non Secure #1 ELC Event Link Controller 0x40082000 0x00 1 registers 0x02 4 registers 0x10 40 registers 0x40 28 registers 0x74 2 registers 0x78 2 registers 0x7C 2 registers ELCR Event Link Controller Register 0x00 8 read-write 0x00 0xff ELCON All Event Link Enable 7 7 read-write 0 ELC function is disabled. #0 1 ELC function is enabled. #1 2 0x02 0-1 ELSEGR%s Event Link Software Event Generation Register %s 0x02 8 read-write 0x80 0xff SEG Software Event Generation 0 0 write-only 0 Normal operation #0 1 Software event is generated. #1 WE SEG Bit Write Enable 6 6 read-write 0 Write to SEG bit disabled. #0 1 Write to SEG bit enabled. #1 WI ELSEGR Register Write Disable 7 7 write-only 0 Write to ELSEGR register enabled. #0 1 Write to ELSEGR register disabled. #1 10 0x04 0-9 ELSR%s Event Link Setting Register %s 0x10 16 read-write 0x0000 0xffff ELS Event Link Select 0 8 read-write 7 0x04 12-18 ELSR%s Event Link Setting Register %s 0x40 16 read-write 0x0000 0xffff ELS Event Link Select 0 8 read-write ELCSARA Event Link Controller Security Attribution Register A 0x74 16 read-write 0xffff 0xffff ELCR Event Link Controller Register Security Attribution 0 0 read-write 0 Secure #0 1 Non-secure #1 ELSEGR0 Event Link Software Event Generation Register 0 Security Attribution 1 1 read-write 0 Secure #0 1 Non-secure #1 ELSEGR1 Event Link Software Event Generation Register 1 Security Attribution 2 2 read-write 0 Secure #0 1 Non-secure #1 ELCSARB Event Link Controller Security Attribution Register B 0x78 16 read-write 0xffff 0xffff ELSR Event Link Setting Register n Security Attribution 0 15 read-write 0 Secure #0 1 Non-secure #1 ELCSARC Event Link Controller Security Attribution Register C 0x7C 16 read-write 0xffff 0xffff ELSR Event Link Setting Register n Security Attribution (n = 16 to 18) 0 2 read-write 0 Secure #0 1 Non-secure #1 RTC Realtime Clock 0x40083000 0x00 1 registers 0x02 8 registers 0x0A 1 registers 0x0C 1 registers 0x0E 10 registers 0x18 4 registers 0x1C 3 registers 0x22 1 registers 0x24 1 registers 0x28 1 registers 0x2A 5 registers 0x40 6 registers 0x52 58 registers R64CNT 64-Hz Counter 0x00 8 read-only 0x00 0x80 F64HZ 64-Hz Flag 0 0 read-only F32HZ 32-Hz Flag 1 1 read-only F16HZ 16-Hz Flag 2 2 read-only F8HZ 8-Hz Flag 3 3 read-only F4HZ 4-Hz Flag 4 4 read-only F2HZ 2-Hz Flag 5 5 read-only F1HZ 1-Hz Flag 6 6 read-only 4 0x02 0-3 BCNT%s Binary Counter %s 0x02 8 read-write 0x00 0x00 BCNT Binary Counter 0 7 read-write RSECCNT Second Counter (in Calendar Count Mode) 0x02 8 read-write 0x00 0x00 SEC1 1-Second Count 0 3 read-write SEC10 10-Second Count 4 6 read-write RMINCNT Minute Counter (in Calendar Count Mode) 0x04 8 read-write 0x00 0x00 MIN1 1-Minute Count 0 3 read-write MIN10 10-Minute Count 4 6 read-write RHRCNT Hour Counter (in Calendar Count Mode) 0x06 8 read-write 0x00 0x00 HR1 1-Hour Count 0 3 read-write HR10 10-Hour Count 4 5 read-write PM AM/PM select for time counter setting. 6 6 read-write 0 AM #0 1 PM #1 RWKCNT Day-of-Week Counter (in Calendar Count Mode) 0x08 8 read-write 0x00 0x00 DAYW Day-of-Week Counting 0 2 read-write 000 Sunday #000 001 Monday #001 010 Tuesday #010 011 Wednesday #011 100 Thursday #100 101 Friday #101 110 Saturday #110 111 Setting prohibited #111 RDAYCNT Day Counter 0x0A 8 read-write 0x00 0xc0 DATE1 1-Day Count 0 3 read-write DATE10 10-Day Count 4 5 read-write RMONCNT Month Counter 0x0C 8 read-write 0x00 0xe0 MON1 1-Month Count 0 3 read-write MON10 10-Month Count 4 4 read-write RYRCNT Year Counter 0x0E 16 read-write 0x0000 0xff00 YR1 1-Year Count 0 3 read-write YR10 10-Year Count 4 7 read-write 4 0x02 0-3 BCNT%sAR Binary Counter %s Alarm Register 0x10 8 read-write 0x00 0x00 BCNTAR Alarm register associated with the 32-bit binary counter 0 7 read-write RSECAR Second Alarm Register (in Calendar Count Mode) 0x10 8 read-write 0x00 0x00 SEC1 1 Second 0 3 read-write SEC10 10 Seconds 4 6 read-write ENB ENB 7 7 read-write 0 Do not compare register value with RSECCNT counter value #0 1 Compare register value with RSECCNT counter value #1 RMINAR Minute Alarm Register (in Calendar Count Mode) 0x12 8 read-write 0x00 0x00 MIN1 1 Minute 0 3 read-write MIN10 10 Minutes 4 6 read-write ENB ENB 7 7 read-write 0 Do not compare register value with RMINCNT counter value #0 1 Compare register value with RMINCNT counter value #1 RHRAR Hour Alarm Register (in Calendar Count Mode) 0x14 8 read-write 0x00 0x00 HR1 1 Hour 0 3 read-write HR10 10 Hours 4 5 read-write PM AM/PM select for alarm setting. 6 6 read-write 0 AM #0 1 PM #1 ENB ENB 7 7 read-write 0 Do not compare register value with RHRCNT counter value #0 1 Compare register value with RHRCNT counter value #1 RWKAR Day-of-Week Alarm Register (in Calendar Count Mode) 0x16 8 read-write 0x00 0x00 DAYW Day-of-Week Setting 0 2 read-write 000 Sunday #000 001 Monday #001 010 Tuesday #010 011 Wednesday #011 100 Thursday #100 101 Friday #101 110 Saturday #110 111 Setting prohibited #111 ENB ENB 7 7 read-write 0 Do not compare register value with RWKCNT counter value #0 1 Compare register value with RWKCNT counter value #1 2 0x02 0-1 BCNT%sAER Binary Counter %s Alarm Enable Register 0x18 8 read-write 0x00 0x00 ENB Setting the alarm enable associated with the 32-bit binary counter 0 7 read-write RDAYAR Date Alarm Register (in Calendar Count Mode) 0x18 8 read-write 0x00 0x00 DATE1 1 Day 0 3 read-write DATE10 10 Days 4 5 read-write ENB ENB 7 7 read-write 0 Do not compare register value with RDAYCNT counter value #0 1 Compare register value with RDAYCNT counter value #1 RMONAR Month Alarm Register (in Calendar Count Mode) 0x1A 8 read-write 0x00 0x00 MON1 1 Month 0 3 read-write MON10 10 Months 4 4 read-write ENB ENB 7 7 read-write 0 Do not compare register value with RMONCNT counter value #0 1 Compare register value with RMONCNT counter value #1 BCNT2AER Binary Counter 2 Alarm Enable Register 0x1C 16 read-write 0x0000 0xff00 ENB Setting the alarm enable associated with the 32-bit binary counter 0 7 read-write RYRAR Year Alarm Register (in Calendar Count Mode) BCNT2AER 0x1C 16 read-write 0x0000 0xff00 YR1 1 Year 0 3 read-write YR10 10 Years 4 7 read-write BCNT3AER Binary Counter 3 Alarm Enable Register 0x1E 8 read-write 0x00 0x00 ENB Setting the alarm enable associated with the 32-bit binary counter 0 7 read-write RYRAREN Year Alarm Enable Register (in Calendar Count Mode) BCNT3AER 0x1E 8 read-write 0x00 0x00 ENB ENB 7 7 read-write 0 Do not compare register value with the RYRCNT counter value #0 1 Compare register value with the RYRCNT counter value #1 RCR1 RTC Control Register 1 0x22 8 read-write 0x00 0x0a AIE Alarm Interrupt Enable 0 0 read-write 0 Disable alarm interrupt requests #0 1 Enable alarm interrupt requests #1 CIE Carry Interrupt Enable 1 1 read-write 0 Disable carry interrupt requests #0 1 Enable carry interrupt requests #1 PIE Periodic Interrupt Enable 2 2 read-write 0 Disable periodic interrupt requests #0 1 Enable periodic interrupt requests #1 RTCOS RTCOUT Output Select 3 3 read-write 0 Outputs 1 Hz on RTCOUT #0 1 Outputs 64 Hz RTCOUT #1 PES Periodic Interrupt Select 4 7 read-write 0x6 Generate periodic interrupt every 1/256 second 0x6 0x7 Generate periodic interrupt every 1/128 second 0x7 0x8 Generate periodic interrupt every 1/64 second 0x8 0x9 Generate periodic interrupt every 1/32 second 0x9 0xA Generate periodic interrupt every 1/16 second 0xa 0xB Generate periodic interrupt every 1/8 second 0xb 0xC Generate periodic interrupt every 1/4 second 0xc 0xD Generate periodic interrupt every 1/2 second 0xd 0xE Generate periodic interrupt every 1 second 0xe 0xF Generate periodic interrupt every 2 seconds 0xf Others Do not generate periodic interrupts true RCR2 RTC Control Register 2 (in Calendar Count Mode) 0x24 8 read-write 0x00 0x0e START Start 0 0 read-write 0 Stop prescaler and time counter #0 1 Operate prescaler and time counter normally #1 RESET RTC Software Reset 1 1 read-write 0 In writing: Invalid (writing 0 has no effect). In reading: Normal time operation in progress, or an RTC software reset has completed. #0 1 In writing: Initialize the prescaler and target registers for RTC software reset. In reading: RTC software reset in progress. #1 ADJ30 30-Second Adjustment 2 2 read-write 0 In writing: Invalid (writing 0 has no effect). In reading: Normal time operation in progress, or 30-second adjustment has completed. #0 1 In writing: Execute 30-second adjustment. In reading: 30-second adjustment in progress. #1 RTCOE RTCOUT Output Enable 3 3 read-write 0 Disable RTCOUT output #0 1 Enable RTCOUT output #1 AADJE Automatic Adjustment Enable 4 4 read-write 0 Disable automatic adjustment #0 1 Enable automatic adjustment #1 AADJP Automatic Adjustment Period Select 5 5 read-write 0 The RADJ.ADJ[5:0] setting from the count value of the prescaler every minute. #0 1 The RADJ.ADJ[5:0] setting value is adjusted from the coun tvalue of the prescaler every 10 seconds. #1 HR24 Hours Mode 6 6 read-write 0 Operate RTC in 12-hour mode #0 1 Operate RTC in 24-hour mode #1 CNTMD Count Mode Select 7 7 read-write 0 Calendar count mode #0 1 Binary count mode #1 RCR2_BCNT RTC Control Register 2 (in Binary Count Mode) RCR2 0x24 8 read-write 0x00 0x0e START Start 0 0 read-write 0 Stop the 32-bit binary counter, 64-Hz counter, and prescaler #0 1 Operate the 32-bit binary counter, 64-Hz counter, and prescaler normally #1 RESET RTC Software Reset 1 1 read-write 0 In writing: Invalid (writing 0 has no effect). In reading: Normal time operation in progress, or an RTC software reset has completed. #0 1 In writing: Initialize the prescaler and target registers for RTC software reset. In reading: RTC software reset in progress. #1 RTCOE RTCOUT Output Enable 3 3 read-write 0 Disable RTCOUT output #0 1 Enable RTCOUT output #1 AADJE Automatic Adjustment Enable 4 4 read-write 0 Disable automatic adjustment #0 1 Enable automatic adjustment #1 AADJP Automatic Adjustment Period Select 5 5 read-write 0 Add or subtract RADJ.ADJ [5:0] bits from prescaler count value every 32 seconds #0 1 Add or subtract RADJ.ADJ [5:0] bits from prescaler countvalue every 8 seconds. #1 CNTMD Count Mode Select 7 7 read-write 0 Calendar count mode #0 1 Binary count mode #1 RCR4 RTC Control Register 4 0x28 8 read-write 0x00 0xfe RCKSEL Count Source Select 0 0 read-write 0 Sub-clock oscillator is selected #0 1 LOCO is selected #1 RFRH Frequency Register H 0x2A 16 read-write 0x0000 0xfffe RFC16 Write 0 before writing to the RFRL register after a cold start. 0 0 read-write RFRL Frequency Register L 0x2C 16 read-write 0x0000 0x0000 RFC Frequency Comparison Value 0 15 read-write RADJ Time Error Adjustment Register 0x2E 8 read-write 0x00 0x00 ADJ Adjustment Value 0 5 read-write PMADJ Plus-Minus 6 7 read-write 00 Do not perform adjustment. #00 01 Adjustment is performed by the addition to the prescaler #01 10 Adjustment is performed by the subtraction from the prescaler #10 11 Setting prohibited. #11 3 0x02 0-2 RTCCR%s Time Capture Control Register %s 0x40 8 read-write 0x00 0x48 TCCT Time Capture Control 0 1 read-write 00 Do not detect events #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 TCST Time Capture Status 2 2 read-write 0 No event detected #0 1 Event detected #1 TCNF Time Capture Noise Filter Control 4 5 read-write 00 Turn noise filter off #00 01 Setting prohibited #01 10 Turn noise filter on (count source) #10 11 Turn noise filter on (count source by divided by 32) #11 TCEN Time Capture Event Input Pin Enable 7 7 read-write 0 Disable the RTCICn pin as the time capture event input pin #0 1 Enable the RTCICn pin as the time capture event input pin #1 3 0x10 0-2 BCNT0CP%s BCNT0 Capture Register %s 0x52 8 read-only 0x00 0x00 3 0x10 0-2 RSECCP%s Second Capture Register %s BCNT0CP%s 0x52 8 read-only 0x00 0x00 SEC1 1-Second Capture 0 3 read-only SEC10 10-Second Capture 4 6 read-only 3 0x10 0-2 BCNT1CP%s BCNT1 Capture Register %s 0x54 8 read-only 0x00 0x00 3 0x10 0-2 RMINCP%s Minute Capture Register %s BCNT1CP%s 0x54 8 read-only 0x00 0x00 MIN1 1-Minute Capture 0 3 read-only MIN10 10-Minute Capture 4 6 read-only 3 0x10 0-2 BCNT2CP%s BCNT2 Capture Register %s 0x56 8 read-only 0x00 0x00 3 0x10 0-2 RHRCP%s Hour Capture Register %s BCNT2CP%s 0x56 8 read-only 0x00 0x00 HR1 1-Hour Capture 0 3 read-only HR10 10-Hour Capture 4 5 read-only PM PM 6 6 read-only 0 AM #0 1 PM #1 3 0x10 0-2 BCNT3CP%s BCNT3 Capture Register %s 0x5A 8 read-only 0x00 0x00 3 0x10 0-2 RDAYCP%s Date Capture Register %s BCNT3CP%s 0x5A 8 read-only 0x00 0x00 DATE1 1-Day Capture 0 3 read-only DATE10 10-Day Capture 4 5 read-only 3 0x10 0-2 RMONCP%s Month Capture Register %s 0x5C 8 read-only 0x00 0xe0 MON1 1-Month Capture 0 3 read-only MON10 10-Month Capture 4 4 read-only IWDT Independent Watchdog Timer 0x40083200 0x00 1 registers 0x04 2 registers IWDTRR IWDT Refresh Register 0x00 8 read-write 0xff 0xff IWDTSR IWDT Status Register 0x04 16 read-write 0x0000 0xffff CNTVAL Down-counter Value 0 13 read-only UNDFF Underflow Flag 14 14 read-write 0 No underflow occurred #0 1 Underflow occurred #1 REFEF Refresh Error Flag 15 15 read-write 0 No refresh error occurred #0 1 Refresh error occurred #1 WDT Watchdog Timer 0x40083400 0x00 1 registers 0x02 5 registers 0x08 1 registers WDTRR WDT Refresh Register 0x00 8 read-write 0xff 0xff WDTCR WDT Control Register 0x02 16 read-write 0x33f3 0xffff TOPS Timeout Period Select 0 1 read-write 00 1024 cycles (0x03FF) #00 01 4096 cycles (0x0FFF) #01 10 8192 cycles (0x1FFF) #10 11 16384 cycles (0x3FFF) #11 CKS Clock Division Ratio Select 4 7 read-write 0x1 PCLKB/4 0x1 0x4 PCLKB/64 0x4 0xF PCLKB/128 0xf 0x6 PCLKB/512 0x6 0x7 PCLKB/2048 0x7 0x8 PCLKB/8192 0x8 Others Setting prohibited true RPES Window End Position Select 8 9 read-write 00 75% #00 01 50% #01 10 25% #10 11 0% (do not specify window end position). #11 RPSS Window Start Position Select 12 13 read-write 00 25% #00 01 50% #01 10 75% #10 11 100% (do not specify window start position). #11 WDTSR WDT Status Register 0x04 16 read-write 0x0000 0xffff CNTVAL Down-Counter Value 0 13 read-only UNDFF Underflow Flag 14 14 read-write 0 No underflow occurred #0 1 Underflow occurred #1 REFEF Refresh Error Flag 15 15 read-write 0 No refresh error occurred #0 1 Refresh error occurred #1 WDTRCR WDT Reset Control Register 0x06 8 read-write 0x80 0xff RSTIRQS WDT Behavior Selection 7 7 read-write 0 Interrupt #0 1 Reset #1 WDTCSTPR WDT Count Stop Control Register 0x08 8 read-write 0x80 0xff SLCSTP Sleep-Mode Count Stop Control Register 7 7 read-write 0 Disable count stop #0 1 Stop count on transition to Sleep mode #1 CAC Clock Frequency Accuracy Measurement Circuit 0x40083600 0x00 5 registers 0x06 6 registers CACR0 CAC Control Register 0 0x00 8 read-write 0x00 0xff CFME Clock Frequency Measurement Enable 0 0 read-write 0 Disable #0 1 Enable #1 CACR1 CAC Control Register 1 0x01 8 read-write 0x00 0xff CACREFE CACREF Pin Input Enable 0 0 read-write 0 Disable #0 1 Enable #1 FMCS Measurement Target Clock Select 1 3 read-write 000 Main clock oscillator #000 001 Sub-clock oscillator #001 010 HOCO clock #010 011 MOCO clock #011 100 LOCO clock #100 101 Peripheral module clock B (PCLKB) #101 110 IWDT-dedicated clock #110 111 Setting prohibited #111 TCSS Timer Count Clock Source Select 4 5 read-write 00 No division #00 01 x 1/4 clock #01 10 x 1/8 clock #10 11 x 1/32 clock #11 EDGES Valid Edge Select 6 7 read-write 00 Rising edge #00 01 Falling edge #01 10 Both rising and falling edges #10 11 Setting prohibited #11 CACR2 CAC Control Register 2 0x02 8 read-write 0x00 0xff RPS Reference Signal Select 0 0 read-write 0 CACREF pin input #0 1 Internal clock (internally generated signal) #1 RSCS Measurement Reference Clock Select 1 3 read-write 000 Main clock oscillator #000 001 Sub-clock oscillator #001 010 HOCO clock #010 011 MOCO clock #011 100 LOCO clock #100 101 Peripheral module clock B (PCLKB) #101 110 IWDT-dedicated clock #110 111 Setting prohibited #111 RCDS Measurement Reference Clock Frequency Division Ratio Select 4 5 read-write 00 x 1/32 clock #00 01 x 1/128 clock #01 10 x 1/1024 clock #10 11 x 1/8192 clock #11 DFS Digital Filter Select 6 7 read-write 00 Disable digital filtering #00 01 Use sampling clock for the digital filter as the frequency measuring clock #01 10 Use sampling clock for the digital filter as the frequency measuring clock divided by 4 #10 11 Use sampling clock for the digital filter as the frequency measuring clock divided by 16. #11 CAICR CAC Interrupt Control Register 0x03 8 read-write 0x00 0xff FERRIE Frequency Error Interrupt Request Enable 0 0 read-write 0 Disable #0 1 Enable #1 MENDIE Measurement End Interrupt Request Enable 1 1 read-write 0 Disable #0 1 Enable #1 OVFIE Overflow Interrupt Request Enable 2 2 read-write 0 Disable #0 1 Enable #1 FERRFCL FERRF Clear 4 4 write-only 0 No effect #0 1 The CASTR.FERRF flag is cleared #1 MENDFCL MENDF Clear 5 5 write-only 0 No effect #0 1 The CASTR.MENDF flag is cleared #1 OVFFCL OVFF Clear 6 6 write-only 0 No effect #0 1 The CASTR.OVFF flag is cleared. #1 CASTR CAC Status Register 0x04 8 read-only 0x00 0xff FERRF Frequency Error Flag 0 0 read-only 0 Clock frequency is within the allowable range #0 1 Clock frequency has deviated beyond the allowable range (frequency error). #1 MENDF Measurement End Flag 1 1 read-only 0 Measurement is in progress #0 1 Measurement ended #1 OVFF Overflow Flag 2 2 read-only 0 Counter has not overflowed #0 1 Counter overflowed #1 CAULVR CAC Upper-Limit Value Setting Register 0x06 16 read-write 0x0000 0xffff CALLVR CAC Lower-Limit Value Setting Register 0x08 16 read-write 0x0000 0xffff CACNTBR CAC Counter Buffer Register 0x0A 16 read-only 0x0000 0xffff MSTP Module Stop Control 0x40084000 0x00 20 registers MSTPCRA Module Stop Control Register A 0x000 32 read-write 0xffbfff7e 0xffffffff MSTPA0 SRAM0 Module Stop 0 0 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPA7 Standby SRAM Module Stop 7 7 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPA22 DMA Controller/Data Transfer Controller Module Stop 22 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRB Module Stop Control Register B 0x004 32 read-write 0xffffffff 0xffffffff MSTPB2 Controller Area Network 0 Module Stop 2 2 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB6 Quad Serial Peripheral Interface Module Stop 6 6 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB8 I2C Bus Interface 1 Module Stop 8 8 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB9 I2C Bus Interface 0 Module Stop 9 9 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB11 Universal Serial Bus 2.0 FS Interface 0 Module Stop 11 11 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB19 Serial Peripheral Interface 0 Module Stop 19 19 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB22 Serial Communication Interface 9 Module Stop 22 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB27 Serial Communication Interface 4 Module Stop 27 27 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB28 Serial Communication Interface 3 Module Stop 28 28 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB29 Serial Communication Interface 2 Module Stop 29 29 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB30 Serial Communication Interface 1 Module Stop 30 30 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB31 Serial Communication Interface 0 Module Stop 31 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRC Module Stop Control Register C 0x008 32 read-write 0xffffffff 0xffffffff MSTPC0 Clock Frequency Accuracy Measurement Circuit Module Stop 0 0 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC1 Cyclic Redundancy Check Calculator Module Stop 1 1 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC3 Capacitive Touch Sensing Unit Module Stop 3 3 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC8 Serial Sound Interface Enhanced Module Stop 8 8 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC12 Secure Digital HOST IF / Multi Media Card 0 Module Stop 12 12 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC13 Data Operation Circuit Module Stop 13 13 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC14 Event Link Controller Module Stop 14 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC31 SCE9 Module Stop 31 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRD Module Stop Control Register D 0x00C 32 read-write 0xffffffff 0xffffffff MSTPD0 Low Power Asynchronous General Purpose Timer 3 Module Stop 0 0 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD1 Low Power Asynchronous General Purpose Timer 2 Module Stop 1 1 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD2 Low Power Asynchronous General Purpose Timer 1 Module Stop 2 2 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD3 Low Power Asynchronous General Purpose Timer 0 Module Stop 3 3 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD11 Port Output Enable for GPT Group D Module Stop 11 11 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD12 Port Output Enable for GPT Group C Module Stop 12 12 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD13 Port Output Enable for GPT Group B Module Stop 13 13 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD14 Port Output Enable for GPT Group A Module Stop 14 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD16 12-bit A/D Converter 0 Module Stop 16 16 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD20 12-bit D/A Converter Module Stop 20 20 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD22 Temperature Sensor Module Stop 22 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRE Module Stop Control Register E 0x010 32 read-write 0xffffffff 0xffffffff MSTPE14 Low Power Asynchronous General Purpose Timer 5 Module Stop 14 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE15 Low Power Asynchronous General Purpose Timer 4 Module Stop 15 15 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE24 GPT7 Module Stop 24 24 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE25 GPT6 Module Stop 25 25 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE26 GPT5 Module Stop 26 26 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE27 GPT4 Module Stop 27 27 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE28 GPT3 Module Stop 28 28 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE29 GPT2 Module Stop 29 29 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE30 GPT1 Module Stop 30 30 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE31 GPT0 Module Stop 31 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 POEG Port Output Enable Module for GPT 0x4008A000 0x00 4 registers 0x100 4 registers 0x200 4 registers 0x300 4 registers POEGGA POEG Group A Setting Register 0x000 32 read-write 0x00000000 0xffffffff PIDF Port Input Detection Flag 0 0 read-write 0 No output-disable request from the GTETRGn pin occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 IOCF Detection Flag for GPT Output-Disable Request 1 1 read-write 0 No output-disable request from GPT occurred. #0 1 Output-disable request from GPT occurred. #1 OSTPF Oscillation Stop Detection Flag 2 2 read-write 0 No output-disable request from oscillation stop detection occurred #0 1 Output-disable request from oscillation stop detection occurred #1 SSF Software Stop Flag 3 3 read-write 0 No output-disable request from software occurred #0 1 Output-disable request from software occurred #1 PIDE Port Input Detection Enable 4 4 read-write 0 Disable output-disable requests from the GTETRGn pins #0 1 Enable output-disable requests from the GTETRGn pins #1 IOCE Enable for GPT Output-Disable Request 5 5 read-write 0 Disable output-disable requests from GPT #0 1 Enable output-disable requests from GPT #1 OSTPE Oscillation Stop Detection Enable 6 6 read-write 0 Disable output-disable requests from oscillation stop detection #0 1 Enable output-disable requests from oscillation stop detection #1 ST GTETRGn Input Status Flag 16 16 read-only 0 GTETRGn input after filtering was 0 #0 1 GTETRGn input after filtering was 1 #1 INV GTETRGn Input Reverse 28 28 read-write 0 Input GTETRGn as-is #0 1 Input GTETRGn in reverse #1 NFEN Noise Filter Enable 29 29 read-write 0 Disable noise filtering #0 1 Enable noise filtering #1 NFCS Noise Filter Clock Select 30 31 read-write 00 Sample GTETRGn pin input level three times every PCLKB #00 01 Sample GTETRGn pin input level three times every PCLKB/8 #01 10 Sample GTETRGn pin input level three times every PCLKB/32 #10 11 Sample GTETRGn pin input level three times every PCLKB/128 #11 POEGGB POEG Group B Setting Register 0x100 32 read-write 0x00000000 0xffffffff PIDF Port Input Detection Flag 0 0 read-write 0 No output-disable request from the GTETRGn pin occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 IOCF Detection Flag for GPT Output-Disable Request 1 1 read-write 0 No output-disable request from GPT occurred. #0 1 Output-disable request from GPT occurred. #1 OSTPF Oscillation Stop Detection Flag 2 2 read-write 0 No output-disable request from oscillation stop detection occurred #0 1 Output-disable request from oscillation stop detection occurred #1 SSF Software Stop Flag 3 3 read-write 0 No output-disable request from software occurred #0 1 Output-disable request from software occurred #1 PIDE Port Input Detection Enable 4 4 read-write 0 Disable output-disable requests from the GTETRGn pins #0 1 Enable output-disable requests from the GTETRGn pins #1 IOCE Enable for GPT Output-Disable Request 5 5 read-write 0 Disable output-disable requests from GPT #0 1 Enable output-disable requests from GPT #1 OSTPE Oscillation Stop Detection Enable 6 6 read-write 0 Disable output-disable requests from oscillation stop detection #0 1 Enable output-disable requests from oscillation stop detection #1 ST GTETRGn Input Status Flag 16 16 read-only 0 GTETRGn input after filtering was 0 #0 1 GTETRGn input after filtering was 1 #1 INV GTETRGn Input Reverse 28 28 read-write 0 Input GTETRGn as-is #0 1 Input GTETRGn in reverse #1 NFEN Noise Filter Enable 29 29 read-write 0 Disable noise filtering #0 1 Enable noise filtering #1 NFCS Noise Filter Clock Select 30 31 read-write 00 Sample GTETRGn pin input level three times every PCLKB #00 01 Sample GTETRGn pin input level three times every PCLKB/8 #01 10 Sample GTETRGn pin input level three times every PCLKB/32 #10 11 Sample GTETRGn pin input level three times every PCLKB/128 #11 POEGGC POEG Group C Setting Register 0x200 32 read-write 0x00000000 0xffffffff PIDF Port Input Detection Flag 0 0 read-write 0 No output-disable request from the GTETRGn pin occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 IOCF Detection Flag for GPT Output-Disable Request 1 1 read-write 0 No output-disable request from GPT occurred. #0 1 Output-disable request from GPT occurred. #1 OSTPF Oscillation Stop Detection Flag 2 2 read-write 0 No output-disable request from oscillation stop detection occurred #0 1 Output-disable request from oscillation stop detection occurred #1 SSF Software Stop Flag 3 3 read-write 0 No output-disable request from software occurred #0 1 Output-disable request from software occurred #1 PIDE Port Input Detection Enable 4 4 read-write 0 Disable output-disable requests from the GTETRGn pins #0 1 Enable output-disable requests from the GTETRGn pins #1 IOCE Enable for GPT Output-Disable Request 5 5 read-write 0 Disable output-disable requests from GPT #0 1 Enable output-disable requests from GPT #1 OSTPE Oscillation Stop Detection Enable 6 6 read-write 0 Disable output-disable requests from oscillation stop detection #0 1 Enable output-disable requests from oscillation stop detection #1 ST GTETRGn Input Status Flag 16 16 read-only 0 GTETRGn input after filtering was 0 #0 1 GTETRGn input after filtering was 1 #1 INV GTETRGn Input Reverse 28 28 read-write 0 Input GTETRGn as-is #0 1 Input GTETRGn in reverse #1 NFEN Noise Filter Enable 29 29 read-write 0 Disable noise filtering #0 1 Enable noise filtering #1 NFCS Noise Filter Clock Select 30 31 read-write 00 Sample GTETRGn pin input level three times every PCLKB #00 01 Sample GTETRGn pin input level three times every PCLKB/8 #01 10 Sample GTETRGn pin input level three times every PCLKB/32 #10 11 Sample GTETRGn pin input level three times every PCLKB/128 #11 POEGGD POEG Group D Setting Register 0x300 32 read-write 0x00000000 0xffffffff PIDF Port Input Detection Flag 0 0 read-write 0 No output-disable request from the GTETRGn pin occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 IOCF Detection Flag for GPT Output-Disable Request 1 1 read-write 0 No output-disable request from GPT occurred. #0 1 Output-disable request from GPT occurred. #1 OSTPF Oscillation Stop Detection Flag 2 2 read-write 0 No output-disable request from oscillation stop detection occurred #0 1 Output-disable request from oscillation stop detection occurred #1 SSF Software Stop Flag 3 3 read-write 0 No output-disable request from software occurred #0 1 Output-disable request from software occurred #1 PIDE Port Input Detection Enable 4 4 read-write 0 Disable output-disable requests from the GTETRGn pins #0 1 Enable output-disable requests from the GTETRGn pins #1 IOCE Enable for GPT Output-Disable Request 5 5 read-write 0 Disable output-disable requests from GPT #0 1 Enable output-disable requests from GPT #1 OSTPE Oscillation Stop Detection Enable 6 6 read-write 0 Disable output-disable requests from oscillation stop detection #0 1 Enable output-disable requests from oscillation stop detection #1 ST GTETRGn Input Status Flag 16 16 read-only 0 GTETRGn input after filtering was 0 #0 1 GTETRGn input after filtering was 1 #1 INV GTETRGn Input Reverse 28 28 read-write 0 Input GTETRGn as-is #0 1 Input GTETRGn in reverse #1 NFEN Noise Filter Enable 29 29 read-write 0 Disable noise filtering #0 1 Enable noise filtering #1 NFCS Noise Filter Clock Select 30 31 read-write 00 Sample GTETRGn pin input level three times every PCLKB #00 01 Sample GTETRGn pin input level three times every PCLKB/8 #01 10 Sample GTETRGn pin input level three times every PCLKB/32 #10 11 Sample GTETRGn pin input level three times every PCLKB/128 #11 USBFS USB 2.0 Full-Speed Module 0x40090000 0x00 2 registers 0x04 2 registers 0x08 2 registers 0x14 2 registers 0x18 12 registers 0x28 12 registers 0x36 8 registers 0x40 4 registers 0x46 12 registers 0x54 14 registers 0x64 2 registers 0x68 2 registers 0x6C 22 registers 0x90 22 registers 0xB0 8 registers 0xD0 12 registers 0xF4 4 registers 0x400 8 registers SYSCFG System Configuration Control Register 0x000 16 read-write 0x0000 0xffff USBE USBFS Operation Enable 0 0 read-write 0 Disable #0 1 Enable #1 DPRPU D+ Line Resistor Control 4 4 read-write 0 Disable line pull-up #0 1 Enable line pull-up #1 DRPD D+/D– Line Resistor Control 5 5 read-write 0 Disable line pull-down #0 1 Enable line pull-down #1 DCFM Controller Function Select 6 6 read-write 0 Select device controller #0 1 Select host controller #1 SCKE USB Clock Enable 10 10 read-write 0 Stop clock supply to the USBFS #0 1 Enable clock supply to the USBFS #1 SYSSTS0 System Configuration Status Register 0 0x004 16 read-only 0x0000 0x3ffb LNST USB Data Line Status Monitor 0 1 read-only IDMON External ID0 Input Pin Monitor 2 2 read-only 0 USB_ID pin is low #0 1 USB_ID pin is high #1 SOFEA Active Monitor When the Host Controller Is Selected 5 5 read-only 0 SOF output stopped #0 1 SOF output operating #1 HTACT USB Host Sequencer Status Monitor 6 6 read-only 0 Host sequencer completely stopped #0 1 Host sequencer not completely stopped #1 OVCMON External USB_OVRCURA/ USB_OVRCURB Input Pin Monitor 14 15 read-only DVSTCTR0 Device State Control Register 0 0x008 16 read-write 0x0000 0xffff RHST USB Bus Reset Status 0 2 read-only 000 In host controller mode: Communication speed indeterminate (powered state or no connection) In device controller mode: Communication speed indeterminate #000 001 In host controller mode: Low-speed connection In device controller mode: USB bus reset in progress #001 010 In host controller mode: Full-speed connection In device controller mode: USB bus reset in progress or full-speed connection #010 011 Setting prohibited #011 Others In host controller mode: USB bus reset in progress In device controller mode: Setting prohibited true UACT USB Bus Enable 4 4 read-write 0 Disable downstream port (disable SOF transmission) #0 1 Enable downstream port (enable SOF transmission) #1 RESUME Resume Output 5 5 read-write 0 Do not output resume signal #0 1 Output resume signal #1 USBRST USB Bus Reset Output 6 6 read-write 0 Do not output USB bus reset signal #0 1 Output USB bus reset signal #1 RWUPE Wakeup Detection Enable 7 7 read-write 0 Disable downstream port remote wakeup #0 1 Enable downstream port remote wakeup #1 WKUP Wakeup Output 8 8 read-write 0 Do not output remote wakeup signal #0 1 Output remote wakeup signal #1 VBUSEN USB_VBUSEN Output Pin Control 9 9 read-write 0 Output low on external USB_VBUSEN pin #0 1 Output high on external USB_VBUSEN pin #1 EXICEN USB_EXICEN Output Pin Control 10 10 read-write 0 Output low on external USB_EXICEN pin #0 1 Output high on external USB_EXICEN pin #1 HNPBTOA Host Negotiation Protocol (HNP) Control 11 11 read-write CFIFO CFIFO Port Register 0x014 16 read-write 0x0000 0xffff FIFOPORT FIFO Port 0 15 read-write CFIFOL CFIFO Port Register CFIFO 0x014 8 read-write 0x00 0xff 2 0x4 0-1 D%sFIFO D%sFIFO Port Register 0x018 16 read-write 0x0000 0xffff FIFOPORT FIFO Port 0 15 read-write 2 0x4 0-1 D%sFIFOL D%sFIFO Port Register D%sFIFO 0x018 8 read-write 0x00 0xff CFIFOSEL CFIFO Port Select Register 0x020 16 read-write 0x0000 0xffff CURPIPE CFIFO Port Access Pipe Specification 0 3 read-write 0x0 Default Control Pipe 0x0 0x1 Pipe 1 0x1 0x2 Pipe 2 0x2 0x3 Pipe 3 0x3 0x4 Pipe 4 0x4 0x5 Pipe 5 0x5 0x6 Pipe 6 0x6 0x7 Pipe 7 0x7 0x8 Pipe 8 0x8 0x9 Pipe 9 0x9 Others Setting prohibited true ISEL CFIFO Port Access Direction When DCP Is Selected 5 5 read-write 0 Select reading from the FIFO buffer #0 1 Select writing to the FIFO buffer #1 BIGEND CFIFO Port Endian Control 8 8 read-write 0 Little endian #0 1 Big endian #1 MBW CFIFO Port Access Bit Width 10 10 read-write 0 8-bit width #0 1 16-bit width #1 REW Buffer Pointer Rewind 14 14 write-only 0 Do not rewind buffer pointer #0 1 Rewind buffer pointer #1 RCNT Read Count Mode 15 15 read-write 0 The DTLN[8:0] bits (CFIFOCTR.DTLN[8:0], D0FIFOCTR.DTLN[8:0], D1FIFOCTR.DTLN[8:0]) are cleared when all receive data is read from the CFIFO. In double buffer mode, the DTLN[8:0] value is cleared when all data is read from only a single plane. #0 1 The DTLN[8:0] bits are decremented each time the receive data is read from the CFIFO. #1 CFIFOCTR CFIFO Port Control Register 0x022 16 read-write 0x0000 0xffff DTLN Receive Data Length 0 8 read-only FRDY FIFO Port Ready 13 13 read-only 0 FIFO port access disabled #0 1 FIFO port access enabled #1 BCLR CPU Buffer Clear 14 14 write-only 0 No operation #0 1 Clear FIFO buffer on the CPU side #1 BVAL Buffer Memory Valid Flag 15 15 read-write 0 Invalid (writing 0 has no effect) #0 1 Writing ended #1 2 0x4 0-1 D%sFIFOSEL D%sFIFO Port Select Register 0x028 16 read-write 0x0000 0xffff CURPIPE FIFO Port Access Pipe Specification 0 3 read-write 0x0 Default Control Pipe 0x0 0x1 Pipe 1 0x1 0x2 Pipe 2 0x2 0x3 Pipe 3 0x3 0x4 Pipe 4 0x4 0x5 Pipe 5 0x5 0x6 Pipe 6 0x6 0x7 Pipe 7 0x7 0x8 Pipe 8 0x8 0x9 Pipe 9 0x9 Others Setting prohibited true BIGEND FIFO Port Endian Control 8 8 read-write 0 Little endian #0 1 Big endian #1 MBW FIFO Port Access Bit Width 10 10 read-write 0 8-bit width #0 1 16-bit width #1 DREQE DMA/DTC Transfer Request Enable 12 12 read-write 0 Disable DMA/DTC transfer request #0 1 Enable DMA/DTC transfer request #1 DCLRM Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read 13 13 read-write 0 Disable auto buffer clear mode #0 1 Enable auto buffer clear mode #1 REW Buffer Pointer Rewind 14 14 write-only 0 Do not rewind buffer pointer #0 1 Rewind buffer pointer #1 RCNT Read Count Mode 15 15 read-write 0 Clear DTLN[8:0] bits in (CFIFOCTR.DTLN[8:0], D0FIFOCTR.DTLN[8:0], D1FIFOCTR.DTLN[8:0]) when all receive data is read from DnFIFO (after read of a single plane in double buffer mode) #0 1 Decrement DTLN[8:0] bits each time receive data is read from DnFIFO #1 2 0x4 0-1 D%sFIFOCTR D%sFIFO Port Control Register 0x02A 16 read-write 0x0000 0xffff DTLN Receive Data Length 0 8 read-only FRDY FIFO Port Ready 13 13 read-only 0 FIFO port access disabled #0 1 FIFO port access enabled #1 BCLR CPU Buffer Clear 14 14 read-write 0 No operation #0 1 Clear FIFO buffer on the CPU side #1 BVAL Buffer Memory Valid Flag 15 15 read-write 0 Invalid (writing 0 has no effect) #0 1 Writing ended #1 INTENB0 Interrupt Enable Register 0 0x030 16 read-write 0x0000 0xffff BRDYE Buffer Ready Interrupt Enable 8 8 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 NRDYE Buffer Not Ready Response Interrupt Enable 9 9 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 BEMPE Buffer Empty Interrupt Enable 10 10 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 CTRE Control Transfer Stage Transition Interrupt Enable 11 11 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 DVSE Device State Transition Interrupt Enable 12 12 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 SOFE Frame Number Update Interrupt Enable 13 13 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 RSME Resume Interrupt Enable 14 14 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 VBSE VBUS Interrupt Enable 15 15 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 INTENB1 Interrupt Enable Register 1 0x032 16 read-write 0x0000 0xffff PDDETINTE PDDETINT Detection Interrupt Request Enable 0 0 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 SACKE Setup Transaction Normal Response Interrupt Enable 4 4 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 SIGNE Setup Transaction Error Interrupt Enable 5 5 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 EOFERRE EOF Error Detection Interrupt Enable 6 6 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 ATTCHE Connection Detection Interrupt Enable 11 11 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 DTCHE Disconnection Detection Interrupt Enable 12 12 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 BCHGE USB Bus Change Interrupt Enable 14 14 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 OVRCRE Overcurrent Input Change Interrupt Enable 15 15 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 BRDYENB BRDY Interrupt Enable Register 0x036 16 read-write 0x0000 0xffff PIPE0BRDYE BRDY Interrupt Enable for Pipe 0 0 0 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE1BRDYE BRDY Interrupt Enable for Pipe 1 1 1 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE2BRDYE BRDY Interrupt Enable for Pipe 2 2 2 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE3BRDYE BRDY Interrupt Enable for Pipe 3 3 3 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE4BRDYE BRDY Interrupt Enable for Pipe 4 4 4 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE5BRDYE BRDY Interrupt Enable for Pipe 5 5 5 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE6BRDYE BRDY Interrupt Enable for Pipe 6 6 6 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE7BRDYE BRDY Interrupt Enable for Pipe 7 7 7 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE8BRDYE BRDY Interrupt Enable for Pipe 8 8 8 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE9BRDYE BRDY Interrupt Enable for Pipe 9 9 9 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 NRDYENB NRDY Interrupt Enable Register 0x038 16 read-write 0x0000 0xffff PIPE0NRDYE NRDY Interrupt Enable for Pipe 0 0 0 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE1NRDYE NRDY Interrupt Enable for Pipe 1 1 1 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE2NRDYE NRDY Interrupt Enable for Pipe 2 2 2 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE3NRDYE NRDY Interrupt Enable for Pipe 3 3 3 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE4NRDYE NRDY Interrupt Enable for Pipe 4 4 4 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE5NRDYE NRDY Interrupt Enable for Pipe 5 5 5 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE6NRDYE NRDY Interrupt Enable for Pipe 6 6 6 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE7NRDYE NRDY Interrupt Enable for Pipe 7 7 7 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE8NRDYE NRDY Interrupt Enable for Pipe 8 8 8 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE9NRDYE NRDY Interrupt Enable for Pipe 9 9 9 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 BEMPENB BEMP Interrupt Enable Register 0x03A 16 read-write 0x0000 0xffff PIPE0BEMPE BEMP Interrupt Enable for Pipe 0 0 0 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE1BEMPE BEMP Interrupt Enable for Pipe 1 1 1 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE2BEMPE BEMP Interrupt Enable for Pipe 2 2 2 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE3BEMPE BEMP Interrupt Enable for Pipe 3 3 3 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE4BEMPE BEMP Interrupt Enable for Pipe 4 4 4 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE5BEMPE BEMP Interrupt Enable for Pipe 5 5 5 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE6BEMPE BEMP Interrupt Enable for Pipe 6 6 6 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE7BEMPE BEMP Interrupt Enable for Pipe 7 7 7 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE8BEMPE BEMP Interrupt Enable for Pipe 8 8 8 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE9BEMPE BEMP Interrupt Enable for Pipe 9 9 9 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 SOFCFG SOF Output Configuration Register 0x03C 16 read-write 0x0000 0xffff EDGESTS Edge Interrupt Output Status Monitor 4 4 read-only BRDYM BRDY Interrupt Status Clear Timing 6 6 read-write 0 Clear BRDY flag by software #0 1 Clear BRDY flag by the USBFS through a data read from the FIFO buffer or data write to the FIFO buffer #1 TRNENSEL Transaction-Enabled Time Select 8 8 read-write 0 Not low-speed communication #0 1 Low-speed communication #1 INTSTS0 Interrupt Status Register 0 0x040 16 read-write 0x0000 0xef6f CTSQ Control Transfer Stage 0 2 read-only 000 Idle or setup stage #000 001 Control read data stage #001 010 Control read status stage #010 011 Control write data stage #011 100 Control write status stage #100 101 Control write (no data) status stage #101 110 Control transfer sequence error #110 VALID USB Request Reception 3 3 read-write 0 Setup packet not received #0 1 Setup packet received #1 DVSQ Device State 4 6 read-only 000 Powered state #000 001 Default state #001 010 Address state #010 011 Configured state #011 Others Suspend state true VBSTS VBUS Input Status 7 7 read-only 0 USB_VBUS pin is low #0 1 USB_VBUS pin is high #1 BRDY Buffer Ready Interrupt Status 8 8 read-only 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 NRDY Buffer Not Ready Interrupt Status 9 9 read-only 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 BEMP Buffer Empty Interrupt Status 10 10 read-only 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 CTRT Control Transfer Stage Transition Interrupt Status 11 11 read-write 0 No control transfer stage transition interrupt occurred #0 1 Control transfer stage transition interrupt occurred #1 DVST Device State Transition Interrupt Status 12 12 read-write 0 No device state transition interrupt occurred #0 1 Device state transition interrupt occurred #1 SOFR Frame Number Refresh Interrupt Status 13 13 read-write 0 No SOF interrupt occurred #0 1 SOF interrupt occurred #1 RESM Resume Interrupt Status 14 14 read-write 0 No resume interrupt occurred #0 1 Resume interrupt occurred #1 VBINT VBUS Interrupt Status 15 15 read-write 0 No VBUS interrupt occurred #0 1 VBUS interrupt occurred #1 INTSTS1 Interrupt Status Register 1 0x042 16 read-write 0x0000 0xffff PDDETINT PDDET Detection Interrupt Status Flag 0 0 read-write 0 No PDDET interrupt occurred #0 1 PDDET interrupt occurred #1 SACK Setup Transaction Normal Response Interrupt Status 4 4 read-write 0 No SACK interrupt occurred #0 1 SACK interrupt occurred #1 SIGN Setup Transaction Error Interrupt Status 5 5 read-write 0 No SIGN interrupt occurred #0 1 SIGN interrupt occurred #1 EOFERR EOF Error Detection Interrupt Status 6 6 read-write 0 No EOFERR interrupt occurred #0 1 EOFERR interrupt occurred #1 ATTCH ATTCH Interrupt Status 11 11 read-write 0 No ATTCH interrupt occurred #0 1 ATTCH interrupt occurred #1 DTCH USB Disconnection Detection Interrupt Status 12 12 read-write 0 No DTCH interrupt occurred #0 1 DTCH interrupt occurred #1 BCHG USB Bus Change Interrupt Status 14 14 read-write 0 No BCHG interrupt occurred #0 1 BCHG interrupt occurred #1 OVRCR Overcurrent Input Change Interrupt Status 15 15 read-write 0 No OVRCR interrupt occurred #0 1 OVRCR interrupt occurred #1 BRDYSTS BRDY Interrupt Status Register 0x046 16 read-write 0x0000 0xffff PIPE0BRDY BRDY Interrupt Status for Pipe 0 0 0 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 PIPE1BRDY BRDY Interrupt Status for Pipe 1 1 1 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 PIPE2BRDY BRDY Interrupt Status for Pipe 2 2 2 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 PIPE3BRDY BRDY Interrupt Status for Pipe 3 3 3 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 PIPE4BRDY BRDY Interrupt Status for Pipe 4 4 4 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 PIPE5BRDY BRDY Interrupt Status for Pipe 5 5 5 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 PIPE6BRDY BRDY Interrupt Status for Pipe 6 6 6 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 PIPE7BRDY BRDY Interrupt Status for Pipe 7 7 7 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 PIPE8BRDY BRDY Interrupt Status for Pipe 8 8 8 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 PIPE9BRDY BRDY Interrupt Status for Pipe 9 9 9 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 NRDYSTS NRDY Interrupt Status Register 0x048 16 read-write 0x0000 0xffff PIPE0NRDY NRDY Interrupt Status for Pipe 0 0 0 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE1NRDY NRDY Interrupt Status for Pipe 1 1 1 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE2NRDY NRDY Interrupt Status for Pipe 2 2 2 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE3NRDY NRDY Interrupt Status for Pipe 3 3 3 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE4NRDY NRDY Interrupt Status for Pipe 4 4 4 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE5NRDY NRDY Interrupt Status for Pipe 5 5 5 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE6NRDY NRDY Interrupt Status for Pipe 6 6 6 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE7NRDY NRDY Interrupt Status for Pipe 7 7 7 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE8NRDY NRDY Interrupt Status for Pipe 8 8 8 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE9NRDY NRDY Interrupt Status for Pipe 9 9 9 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 BEMPSTS BEMP Interrupt Status Register 0x04A 16 read-write 0x0000 0xffff PIPE0BEMP BEMP Interrupt Status for Pipe 0 0 0 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 PIPE1BEMP BEMP Interrupt Status for Pipe 1 1 1 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 PIPE2BEMP BEMP Interrupt Status for Pipe 2 2 2 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 PIPE3BEMP BEMP Interrupt Status for Pipe 3 3 3 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 PIPE4BEMP BEMP Interrupt Status for Pipe 4 4 4 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 PIPE5BEMP BEMP Interrupt Status for Pipe 5 5 5 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 PIPE6BEMP BEMP Interrupt Status for Pipe 6 6 6 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 PIPE7BEMP BEMP Interrupt Status for Pipe 7 7 7 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 PIPE8BEMP BEMP Interrupt Status for Pipe 8 8 8 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 PIPE9BEMP BEMP Interrupt Status for Pipe 9 9 9 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 FRMNUM Frame Number Register 0x04C 16 read-write 0x0000 0xffff FRNM Frame Number 0 10 read-only CRCE Receive Data Error 14 14 read-write 0 No error occurred #0 1 Error occurred #1 OVRN Overrun/Underrun Detection Status 15 15 read-write 0 No error occurred #0 1 Error occurred #1 DVCHGR Device State Change Register 0x04E 16 read-write 0x0000 0xffff DVCHG Device State Change 15 15 read-write 0 Disable writes to the USBADDR.STSRECOV[3:0] and USBADDR.USBADDR[6:0] bits #0 1 Enable writes to the USBADDR.STSRECOV[3:0] and USBADDR.USBADDR[6:0] bits #1 USBADDR USB Address Register 0x050 16 read-write 0x0000 0xffff USBADDR USB Address 0 6 read-write STSRECOV Status Recovery 8 11 read-write 0x4 Recovery in device controller mode: Setting prohibited Recovery in host controller mode: Return to the low-speed state (bits DVSTCTR0.RHST[2:0] = 001b) 0x4 0x8 Recovery in device controller mode: Setting prohibited Recovery in host controller mode: Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b) 0x8 0x9 Recovery in device controller mode: Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 001b (default state) Recovery in host controller mode: Setting prohibited 0x9 0xA Recovery in device controller mode: Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 010b (address state) Recovery in host controller mode: Setting prohibited 0xa 0xB Recovery in device controller mode: Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 011b (configured state) Recovery in host controller mode: Setting prohibited 0xb Others Setting prohibited true USBREQ USB Request Type Register 0x054 16 read-write 0x0000 0xffff BMREQUESTTYPE Request Type 0 7 read-write BREQUEST Request 8 15 read-write USBVAL USB Request Value Register 0x056 16 read-write 0x0000 0xffff WVALUE Value 0 15 read-write USBINDX USB Request Index Register 0x058 16 read-write 0x0000 0xffff WINDEX Index 0 15 read-write USBLENG USB Request Length Register 0x05A 16 read-write 0x0000 0xffff WLENTUH Length 0 15 read-write DCPCFG DCP Configuration Register 0x05C 16 read-write 0x0000 0xffff DIR Transfer Direction 4 4 read-write 0 Data receiving direction #0 1 Data transmitting direction #1 SHTNAK Pipe Disabled at End of Transfer 7 7 read-write 0 Keep pipe open after transfer ends #0 1 Disable pipe after transfer ends #1 DCPMAXP DCP Maximum Packet Size Register 0x05E 16 read-write 0x0040 0xffff MXPS Maximum Packet Size 0 6 read-write DEVSEL Device Select 12 15 read-write 0x0 Address 0000b 0x0 0x1 Address 0001b 0x1 0x2 Address 0010b 0x2 0x3 Address 0011b 0x3 0x4 Address 0100b 0x4 0x5 Address 0101b 0x5 Others Setting prohibited true DCPCTR DCP Control Register 0x060 16 read-write 0x0040 0xffff PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depends on the buffer state) #01 10 STALL response #10 11 STALL response #11 CCPL Control Transfer End Enable 2 2 read-write 0 Disable control transfer completion #0 1 Enable control transfer completion #1 PBUSY Pipe Busy 5 5 read-only 0 DCP not used for the USB bus #0 1 DCP in use for the USB bus #1 SQMON Sequence Toggle Bit Monitor 6 6 read-only 0 DATA0 #0 1 ATA1 #1 SQSET Sequence Toggle Bit Set 7 7 read-write 0 Invalid (writing 0 has no effect) #0 1 Set the expected value for the next transaction to DATA1 #1 SQCLR Sequence Toggle Bit Clear 8 8 read-write 0 Invalid (writing 0 has no effect) #0 1 Clear the expected value for the next transaction to DATA0 #1 SUREQCLR SUREQ Bit Clear 11 11 read-write 0 Invalid (writing 0 has no effect) #0 1 Clear SUREQ to 0 #1 SUREQ Setup Token Transmission 14 14 read-write 0 Invalid (writing 0 has no effect) #0 1 Transmit setup packet #1 BSTS Buffer Status 15 15 read-only 0 Buffer access disabled #0 1 Buffer access enabled #1 PIPESEL Pipe Window Select Register 0x064 16 read-write 0x0000 0xffff PIPESEL Pipe Window Select 0 3 read-write 0x0 No pipe selected 0x0 0x1 Pipe 1 0x1 0x2 Pipe 2 0x2 0x3 Pipe 3 0x3 0x4 Pipe 4 0x4 0x5 Pipe 5 0x5 0x6 Pipe 6 0x6 0x7 Pipe 7 0x7 0x8 Pipe 8 0x8 0x9 Pipe 9 0x9 Others Setting prohibited true PIPECFG Pipe Configuration Register 0x068 16 read-write 0x0000 0xffff EPNUM Endpoint Number 0 3 read-write DIR Transfer Direction 4 4 read-write 0 Receiving direction #0 1 Transmitting direction #1 SHTNAK Pipe Disabled at End of Transfer 7 7 read-write 0 Continue pipe operation after transfer ends #0 1 Disable pipe after transfer ends #1 DBLB Double Buffer Mode 9 9 read-write 0 Single buffer #0 1 Double buffer #1 BFRE BRDY Interrupt Operation Specification 10 10 read-write 0 Generate BRDY interrupt on transmitting or receiving data #0 1 Generate BRDY interrupt on completion of reading data #1 TYPE Transfer Type 14 15 read-write 00 Pipe not used #00 01 Pipes 1 and 2: Bulk transfer Pipes 3 to 5: Bulk transfer Pipes 6 to 9: Setting prohibited #01 10 Pipes 1 and 2: Setting prohibited Pipes 3 to 5: Setting prohibited Pipes 6 to 9: Interrupt transfer #10 11 Pipes 1 and 2: Isochronous transfer Pipes 3 to 5: Setting prohibited Pipes 6 to 9: Setting prohibited #11 PIPEMAXP Pipe Maximum Packet Size Register 0x06C 16 read-write 0x0000 0xffbf MXPS Maximum Packet Size 0 8 read-write DEVSEL Device Select 12 15 read-write 0x0 Address 0000b 0x0 0x1 Address 0001b 0x1 0x2 Address 0010b 0x2 0x3 Address 0011b 0x3 0x4 Address 0100b 0x4 0x5 Address 0101b 0x5 Others Setting prohibited true PIPEPERI Pipe Cycle Control Register 0x06E 16 read-write 0x0000 0xffff IITV Interval Error Detection Interval 0 2 read-write IFIS Isochronous IN Buffer Flush 12 12 read-write 0 Do not flush buffer #0 1 Flush buffer #1 5 0x2 1-5 PIPE%sCTR PIPE%s Control Registers 0x070 16 read-write 0x0000 0xffff PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depends buffer state) #01 10 STALL response #10 11 STALL response #11 PBUSY Pipe Busy 5 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction #1 SQMON Sequence Toggle Bit Confirmation 6 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 7 read-write 0 Invalid (writing 0 has no effect) #0 1 Set the expected value for the next transaction to DATA1 #1 SQCLR Sequence Toggle Bit Clear 8 8 read-write 0 Invalid (writing 0 has no effect) #0 1 Clear the expected value for the next transaction to DATA0 #1 ACLRM Auto Buffer Clear Mode 9 9 read-write 0 Disable #0 1 Enable (initialize all buffers) #1 ATREPM Auto Response Mode 10 10 read-write 0 Disable auto response mode #0 1 Enable auto response mode #1 INBUFM Transmit Buffer Monitor 14 14 read-only 0 No data to be transmitted is in the FIFO buffer #0 1 Data to be transmitted is in the FIFO buffer #1 BSTS Buffer Status 15 15 read-only 0 Buffer access by the CPU disabled #0 1 Buffer access by the CPU enabled #1 4 0x2 6-9 PIPE%sCTR PIPE%s Control Registers 0x07A 16 read-write 0x0000 0xffff PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depends buffer state) #01 10 STALL response #10 11 STALL response #11 PBUSY Pipe Busy 5 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction #1 SQMON Sequence Toggle Bit Confirmation 6 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 7 write-only 0 Invalid (writing 0 has no effect) #0 1 Set the expected value for the next transaction to DATA0 #1 SQCLR Sequence Toggle Bit Clear 8 8 write-only 0 Invalid (writing 0 has no effect) #0 1 Clear the expected value for the next transaction to DATA0 #1 ACLRM Auto Buffer Clear Mode 9 9 read-write 0 Disable #0 1 Enable (all buffers initialized) #1 BSTS Buffer Status 15 15 read-only 0 Buffer access disabled #0 1 Buffer access enabled #1 5 0x4 1-5 PIPE%sTRE PIPE%s Transaction Counter Enable Register 0x090 16 read-write 0x0000 0xffff TRCLR Transaction Counter Clear 8 8 read-write 0 Invalid (writing 0 has no effect) #0 1 Clear counter value #1 TRENB Transaction Counter Enable 9 9 read-write 0 Disable transaction counter #0 1 Enable transaction counter #1 5 0x4 1-5 PIPE%sTRN PIPE%s Transaction Counter Register 0x092 16 read-write 0x0000 0xffff TRNCNT Transaction Counter 0 15 read-write BCCTRL1 Battery Charging Control Register 1 0x0B0 32 read-write 0x00000000 0xffffffff RPDME D- Line Pull-down Control 0 0 read-write 0 Disable D- Line Pull-down #0 1 Enable D- Line Pull-down #1 IDPSRCE D+ Line IDPSRC Output Control 1 1 read-write 0 Stopped #0 1 10 µA output #1 VDMSRCE D- Line VDMSRC (0.6 V) Output Control 2 2 read-write 0 Stopped #0 1 0.6 V output #1 VDPSRCE D+ Line VDPSRC (0.6 V) Output Control 3 3 read-write 0 Stopped #0 1 0.6 V output #1 PDDETE D+ Line 0.6 V Input Detection Control 4 4 read-write 0 Disable detection #0 1 Enable detection #1 CHGDETE D- Line 0.6 V Input Detection Control 5 5 read-write 0 Disable detection #0 1 Enable detection #1 PDDETSTS D+ Line 0.6 V Input Detection Status Flag 8 8 read-only 0 Not detected #0 1 Detected #1 CHGDETSTS D- Line 0.6 V Input Detection Status Flag 9 9 read-only 0 Not detected #0 1 Detected #1 BCCTRL2 Battery Charging Control Register 2 0x0B4 32 read-write 0x00002000 0xffffffff DCPMODE Dedicated Charging Port (DCP) Mode Control 6 6 read-write 0 Disable DCP #0 1 Enable DCP #1 BATCHGE Battery Charging Enable 7 7 read-write 0 Disable Battery Charging #0 1 Enable Battery Charging #1 PHYDET Detect Sensitivity Adjustment 12 13 read-write 6 0x2 0-5 DEVADD%s Device Address %s Configuration Register 0x0D0 16 read-write 0x0000 0xffff USBSPD Transfer Speed of Communication Target Device 6 7 read-write 00 Do not use DEVADDn #00 01 Low-speed #01 10 Full-speed #10 11 Setting prohibited #11 PHYSECTRL PHY Single-ended Receiver Control Register 0x0F4 32 read-write 0x00000000 0xffffffff CNEN Single-ended Receiver Enable 4 4 read-write 0 Single-ended receiver operation is disabled #0 1 Single-ended receiver operation is enabled #1 DPUSR0R Deep Software Standby USB Transceiver Control/Pin Monitor Register 0x400 32 read-write 0x00000000 0xff6cffff SRPC0 USB Single-ended Receiver Control 0 0 read-write 0 Disable input through DP and DM inputs #0 1 Enable input through DP and DM inputs #1 RPUE0 DP Pull-Up Resistor Control 1 1 read-write 0 Disable DP pull-up resistor #0 1 Enable DP pull-up resistor #1 DRPD0 D+/D- Pull-Down Resistor Control 3 3 read-write 0 Disable DP/DM pull-down resistor #0 1 Enable DP/DM pull-down resistor #1 FIXPHY0 USB Transceiver Output Fix 4 4 read-write 0 Fix outputs in Normal mode and on return from Deep Software Standby mode #0 1 Fix outputs on transition to Deep Software Standby mode #1 DP0 USB D+ Input 16 16 read-only DM0 USB D- Input 17 17 read-only DOVCA0 USB OVRCURA Input 20 20 read-only DVBSTS0 USB VBUS Input 23 23 read-only DPUSR1R Deep Software Standby USB Suspend/Resume Interrupt Register 0x404 32 read-write 0x00000000 0xffffffff DPINTE0 USB DP Interrupt Enable/Clear 0 0 read-write 0 Disable recovery from Deep Software Standby mode by DP input #0 1 Enable recovery from Deep Software Standby mode by DP input #1 DMINTE0 USB DM Interrupt Enable/Clear 1 1 read-write 0 Disable recovery from Deep Software Standby mode by DM input #0 1 Enable recovery from Deep Software Standby mode by DM input #1 DOVRCRAE0 USB OVRCURA Interrupt Enable/Clear 4 4 read-write 0 Disable recovery from Deep Software Standby mode by OVRCURA input #0 1 Enable recovery from Deep Software Standby mode by OVRCURA input #1 DVBSE0 USB VBUS Interrupt Enable/Clear 7 7 read-write 0 Disable recovery from Deep Software Standby mode by VBUS input #0 1 Enable recovery from Deep Software Standby mode by VBUS input #1 DPINT0 USB DP Interrupt Source Recovery 16 16 read-only 0 System has not recovered from Deep Software Standby mode #0 1 System recovered from Deep Software Standby mode because of DP #1 DMINT0 USB DM Interrupt Source Recovery 17 17 read-only 0 System has not recovered from Deep Software Standby mode #0 1 System recovered from Deep Software Standby mode because of DM input #1 DOVRCRA0 USB OVRCURA Interrupt Source Recovery 20 20 read-only 0 System has not recovered from Deep Software Standby mode #0 1 System recovered from Deep Software Standby mode because of OVRCURA input #1 DVBINT0 USB VBUS Interrupt Source Recovery 23 23 read-only 0 System has not recovered from Deep Software Standby mode #0 1 System recovered from Deep Software Standby mode because of VBUS input #1 SDHI0 SD Host Interface 0 0x40092000 0x00 4 registers 0x08 76 registers 0x58 12 registers 0x68 12 registers 0x1B0 4 registers 0x1C0 4 registers 0x1CC 4 registers 0x1E0 4 registers SD_CMD Command Type Register 0x000 32 read-write 0x00000000 0xffffffff CMDIDX Command Index Field Value Select 0 5 read-write 0x06 CMD6 0x06 0x12 CMD18 0x12 0x4D ACMD13 0x4d ACMD Command Type Select 6 7 read-write 00 CMD #00 01 ACMD #01 Others Setting prohibited true RSPTP Response Type Select 8 10 read-write 000 Normal mode Depending on the command, the response type and transfer method are selected in the ACMD[1:0] and CMDIDX[5:0] bits. At this time, the values for bits 15 to 11 in this register are invalid. #000 011 Extended mode and no response #011 100 Extended mode and R1, R5, R6, or R7 response #100 101 Extended mode and R1b response #101 110 Extended mode and R2 response #110 111 Extended mode and R3 or R4 response #111 Others Setting prohibited true CMDTP Data Transfer Select 11 11 read-write 0 Do not include data transfer (bc, bcr, or ac) in command #0 1 Include data transfer (adtc) in command #1 CMDRW Data Transfer Direction Select 12 12 read-write 0 Write (SD/MMC Host Interface → SD card/MMC) #0 1 Read (SD/MMC Host Interface ← SD card/MMC) #1 TRSTP Block Transfer Select 13 13 read-write 0 Single block transfer #0 1 Multiple blocks transfer #1 CMD12AT CMD12 Automatic Issue Select 14 15 read-write 00 Automatically issue CMD12 during multiblock transfer #00 01 Do not automatically issue CMD12 during multiblock transfer #01 Others Setting prohibited true SD_ARG SD Command Argument Register 0x008 32 read-write 0x00000000 0xffffffff SD_ARG1 SD Command Argument Register 1 0x00C 32 read-write 0x00000000 0xffffffff SD_STOP Data Stop Register 0x010 32 read-write 0x00000000 0xffffffff STP Transfer Stop 0 0 read-write SEC Block Count Register Value Select 8 8 read-write 0 Disable SD_SECCNT register value #0 1 Enable SD_SECCNT register value #1 SD_SECCNT Block Count Register 0x014 32 read-write 0x00000000 0xffffffff SD_RSP10 SD Card Response Register 10 0x018 32 read-write 0x00000000 0xffffffff SD_RSP1 SD Card Response Register 1 0x01C 32 read-only 0x00000000 0xffffffff SD_RSP32 SD Card Response Register 32 0x020 32 read-write 0x00000000 0xffffffff SD_RSP3 SD Card Response Register 3 0x024 32 read-only 0x00000000 0xffffffff SD_RSP54 SD Card Response Register 54 0x028 32 read-write 0x00000000 0xffffffff SD_RSP5 SD Card Response Register 5 0x02C 32 read-only 0x00000000 0xffffffff SD_RSP76 SD Card Response Register 76 0x030 32 read-only 0x00000000 0xffffffff SD_RSP76 These bits store the response from the SD card/MMC. 0 23 read-only SD_RSP7 SD Card Response Register 7 0x034 32 read-only 0x00000000 0xffffffff SD_RSP7 These bits store the response from the SD card/MMC. 0 7 read-only SD_INFO1 SD Card Interrupt Flag Register 1 0x038 32 read-write 0x00000000 0xfffffb5f RSPEND Response End Detection Flag 0 0 read-write 0 Response end not detected #0 1 Response end detected #1 ACEND Access End Detection Flag 2 2 read-write 0 Access end not detected #0 1 Access end detected #1 SDCDRM SDnCD Removal Flag 3 3 read-write 0 SD card/MMC removal not detected by the SDnCD pin #0 1 SD card/MMC removal detected by the SDnCD pin #1 SDCDIN SDnCD Insertion Flag 4 4 read-write 0 SD card/MMC insertion not detected by the SDnCD pin #0 1 SD card/MMC insertion detected by the SDnCD pin #1 SDCDMON SDnCD Pin Monitor Flag 5 5 read-only 0 SDnCD pin level is high #0 1 SDnCD pin level is low #1 SDWPMON SDnWP Pin Monitor Flag 7 7 read-only 0 SDnWP pin level is high #0 1 SDnWP pin level is low #1 SDD3RM SDnDAT3 Removal Flag 8 8 read-write 0 SD card/MMC removal not detected by the SDnDAT3 pin #0 1 SD card/MMC removal detected by the SDnDAT3 pin #1 SDD3IN SDnDAT3 Insertion Flag 9 9 read-write 0 SD card/MMC insertion not detected by the SDnDAT3 pin #0 1 SD card/MMC insertion detected by the SDnDAT3 pin #1 SDD3MON SDnDAT3 Pin Monitor Flag 10 10 read-only 0 SDnDAT3 pin level is low #0 1 SDnDAT3 pin level is high #1 SD_INFO2 SD Card Interrupt Flag Register 2 0x03C 32 read-write 0x00002000 0xfffff77f CMDE Command Error Detection Flag 0 0 read-write 0 Command error not detected #0 1 Command error detected #1 CRCE CRC Error Detection Flag 1 1 read-write 0 CRC error not detected #0 1 CRC error detected #1 ENDE End Bit Error Detection Flag 2 2 read-write 0 End bit error not detected #0 1 End bit error detected #1 DTO Data Timeout Detection Flag 3 3 read-write 0 Data timeout not detected #0 1 Data timeout detected #1 ILW SD_BUF0 Illegal Write Access Detection Flag 4 4 read-write 0 Illegal write access to the SD_BUF0 register not detected #0 1 Illegal write access to the SD_BUF0 register detected #1 ILR SD_BUF0 Illegal Read Access Detection Flag 5 5 read-write 0 Illegal read access to the SD_BUF0 register not detected #0 1 Illegal read access to the SD_BUF0 register detected #1 RSPTO Response Timeout Detection Flag 6 6 read-write 0 Response timeout not detected #0 1 Response timeout detected #1 SDD0MON SDnDAT0 Pin Status Flag 7 7 read-only 0 SDnDAT0 pin is low #0 1 SDnDAT0 pin is high #1 BRE SD_BUF0 Read Enable Flag 8 8 read-write 0 Disable read access to the SD_BUF0 register #0 1 Enable read access to the SD_BUF0 register #1 BWE SD_BUF0 Write Enable Flag 9 9 read-write 0 Disable write access to the SD_BUF0 register #0 1 Enable write access to the SD_BUF0 register #1 SD_CLK_CTRLEN SD_CLK_CTRL Write Enable Flag 13 13 read-only 0 SD/MMC bus (CMD and DAT lines) is busy, so write access to the SD_CLK_CTRL.CLKEN and CLKSEL[7:0] bits is disabled #0 1 SD/MMC bus (CMD and DAT lines) is not busy, so write access to the SD_CLK_CTRL.CLKEN and CLKSEL[7:0] bits is enabled #1 CBSY Command Sequence Status Flag 14 14 read-only 0 Command sequence complete #0 1 Command sequence in progress (busy) #1 ILA Illegal Access Error Detection Flag 15 15 read-write 0 Illegal access error not detected #0 1 Illegal access error detected #1 SD_INFO1_MASK SD INFO1 Interrupt Mask Register 0x040 32 read-write 0x0000031d 0xffffffff RSPENDM Response End Interrupt Request Mask 0 0 read-write 0 Do not mask response end interrupt request #0 1 Mask response end interrupt request #1 ACENDM Access End Interrupt Request Mask 2 2 read-write 0 Do not mask access end interrupt request #0 1 Mask access end interrupt request #1 SDCDRMM SDnCD Removal Interrupt Request Mask 3 3 read-write 0 Do not mask SD card/MMC removal interrupt request by the SDnCD pin #0 1 Mask SD card/MMC removal interrupt request by the SDnCD pin #1 SDCDINM SDnCD Insertion Interrupt Request Mask 4 4 read-write 0 Do not mask SD card/MMC insertion interrupt request by the SDnCD pin #0 1 Mask SD card/MMC insertion interrupt request by the SDnCD pin #1 SDD3RMM SDnDAT3 Removal Interrupt Request Mask 8 8 read-write 0 Do not mask SD card/MMC removal interrupt request by the SDnDAT3 pin #0 1 Mask SD card/MMC removal interrupt request by the SDnDAT3 pin #1 SDD3INM SDnDAT3 Insertion Interrupt Request Mask 9 9 read-write 0 Do not mask SD card/MMC insertion interrupt request by the SDnDAT3 pin #0 1 Mask SD card/MMC insertion interrupt request by the SDnDAT3 pin #1 SD_INFO2_MASK SD INFO2 Interrupt Mask Register 0x044 32 read-write 0x00008b7f 0xffffffff CMDEM Command Error Interrupt Request Mask 0 0 read-write 0 Do not mask command error interrupt request #0 1 Mask command error interrupt request #1 CRCEM CRC Error Interrupt Request Mask 1 1 read-write 0 Do not mask CRC error interrupt request #0 1 Mask CRC error interrupt request #1 ENDEM End Bit Error Interrupt Request Mask 2 2 read-write 0 Do not mask end bit detection error interrupt request #0 1 Mask end bit detection error interrupt request #1 DTOM Data Timeout Interrupt Request Mask 3 3 read-write 0 Do not mask data timeout interrupt request #0 1 Mask data timeout interrupt request #1 ILWM SD_BUF0 Register Illegal Write Interrupt Request Mask 4 4 read-write 0 Do not mask illegal write detection interrupt request for the SD_BUF0 register #0 1 Mask illegal write detection interrupt request for the SD_BUF0 register #1 ILRM SD_BUF0 Register Illegal Read Interrupt Request Mask 5 5 read-write 0 Do not mask illegal read detection interrupt request for the SD_BUF0 register #0 1 Mask illegal read detection interrupt request for the SD_BUF0 register #1 RSPTOM Response Timeout Interrupt Request Mask 6 6 read-write 0 Do not mask response timeout interrupt request #0 1 Mask response timeout interrupt request #1 BREM BRE Interrupt Request Mask 8 8 read-write 0 Do not mask read enable interrupt request for the SD buffer #0 1 Mask read enable interrupt request for the SD buffer #1 BWEM BWE Interrupt Request Mask 9 9 read-write 0 Do not mask write enable interrupt request for the SD_BUF0 register #0 1 Mask write enable interrupt request for the SD_BUF0 register #1 ILAM Illegal Access Error Interrupt Request Mask 15 15 read-write 0 Do not mask illegal access error interrupt request #0 1 Mask illegal access error interrupt request #1 SD_CLK_CTRL SD Clock Control Register 0x048 32 read-write 0x00000020 0xffffffff CLKSEL SDHI Clock Frequency Select 0 7 read-write 0xFF PCLKB 0xff 0x00 PCLKB/2 0x00 0x01 PCLKB/4 0x01 0x02 PCLKB/8 0x02 0x04 PCLKB/16 0x04 0x08 PCLKB/32 0x08 0x10 PCLKB/64 0x10 0x20 PCLKB/128 0x20 0x40 PCLKB/256 0x40 0x80 PCLKB/512 0x80 Others Setting prohibited true CLKEN SD/MMC Clock Output Control 8 8 read-write 0 Disable SD/MMC clock output (fix SDnCLK signal low) #0 1 Enable SD/MMC clock output #1 CLKCTRLEN SD/MMC Clock Output Automatic Control Select 9 9 read-write 0 Disable automatic control of SD/MMC clock output #0 1 Enable automatic control of SD/MMC clock output #1 SD_SIZE Transfer Data Length Register 0x04C 32 read-write 0x00000200 0xffffffff LEN Transfer Data Size Setting 0 9 read-write SD_OPTION SD Card Access Control Option Register 0x050 32 read-write 0x000040ee 0xffffffff CTOP Card Detection Time Counter 0 3 read-write 0x0 PCLKB × 210 0x0 0x1 PCLKB × 211 0x1 0x2 PCLKB × 212 0x2 0x3 PCLKB × 213 0x3 0x4 PCLKB × 214 0x4 0x5 PCLKB × 215 0x5 0x6 PCLKB × 216 0x6 0x7 PCLKB × 217 0x7 0x8 PCLKB × 218 0x8 0x9 PCLKB × 219 0x9 0xA PCLKB × 220 0xa 0xB PCLKB × 221 0xb 0xC PCLKB × 222 0xc 0xD PCLKB × 223 0xd 0xE PCLKB × 224 0xe 0xF Setting prohibited 0xf TOP Timeout Counter 4 7 read-write 0x0 SDHI clock × 213 0x0 0x1 SDHI clock × 214 0x1 0x2 SDHI clock × 215 0x2 0x3 SDHI clock × 216 0x3 0x4 SDHI clock × 217 0x4 0x5 SDHI clock × 218 0x5 0x6 SDHI clock × 219 0x6 0x7 SDHI clock × 220 0x7 0x8 SDHI clock × 221 0x8 0x9 SDHI clock × 222 0x9 0xA SDHI clock × 223 0xa 0xB SDHI clock × 224 0xb 0xC SDHI clock × 225 0xc 0xD SDHI clock × 226 0xd 0xE SDHI clock × 227 0xe 0xF Setting prohibited 0xf TOUTMASK Timeout Mask 8 8 read-write 0 Activate timeout #0 1 Inactivate timeout (do not set RSPTO and DTO bits of SD_INFO2 or CRCBSYTO, CRCTO, RDTO, BSYTO1, BSYTO0, RSPTO1 and RSPTO0 bits of SD_ERR_STS2) When timeout occurs because of an inactivated timeout, execute a software reset to terminate the command sequence. #1 WIDTH8 Bus Width 13 13 read-write WIDTH Bus Width 15 15 read-write SD_ERR_STS1 SD Error Status Register 1 0x058 32 read-only 0x00002000 0x0000ffff CMDE0 Command Error Flag 0 0 0 read-only 0 No error exists in command index field value of a command response #0 1 Error exists in command index field value of a command response #1 CMDE1 Command Error Flag 1 1 1 read-only 0 No error exists in command index field value of a command response #0 1 Error exists in command index field value of a command response (with SD_CMD.CMDIDX[5:0] setting, an error that occurs with CMD12 issue is indicated in the CMDE0 flag) #1 RSPLENE0 Response Length Error Flag 0 2 2 read-only 0 No error exists in command response length #0 1 Error exists in command response length #1 RSPLENE1 Response Length Error Flag 1 3 3 read-only 0 No error exists in command response length #0 1 Error exists in command response length (with SD_CMD.CMDIDX[5:0] setting, an error that occurs with CMD12 issue is indicated in the RSPLENE0 flag) #1 RDLENE Read Data Length Error Flag 4 4 read-only 0 No read data length error occurred #0 1 Read data length error occurred #1 CRCLENE CRC Status Token Length Error Flag 5 5 read-only 0 No CRC status token length error occurred #0 1 CRC status token length error occurred #1 RSPCRCE0 Response CRC Error Flag 0 8 8 read-only 0 No CRC error detected in command response #0 1 CRC error detected in command response #1 RSPCRCE1 Response CRC Error Flag 1 9 9 read-only 0 No CRC error detected in command response (with SD_CMD.CMDIDX[5:0] setting, an error that occurs with CMD12 issue is indicated in the RSPCRCE0 flag) #0 1 CRC error detected in command response #1 RDCRCE Read Data CRC Error Flag 10 10 read-only 0 No CRC error detected in read data #0 1 CRC error detected in read data #1 CRCTKE CRC Status Token Error Flag 11 11 read-only 0 No error detected in CRC status token #0 1 Error detected in CRC status token #1 CRCTK CRC Status Token 12 14 read-only SD_ERR_STS2 SD Error Status Register 2 0x05C 32 read-only 0x00000000 0xffffffff RSPTO0 Response Timeout Flag 0 0 0 read-only 0 After command was issued, response was received in less than 640 cycles of the SD/MMC clock #0 1 After command was issued, response was not received in 640 or more cycles of the SD/MMC clock #1 RSPTO1 Response Timeout Flag 1 1 1 read-only 0 After command was issued, response was received in less than 640 cycles of the SD/MMC clock #0 1 After command was issued, response was not received after 640 or more cycles of the SD/MMC clock (with SD_CMD.CMDIDX[5:0] setting, an error that occurs with CMD12 issue is indicated in the RSPTO0 flag) #1 BSYTO0 Busy Timeout Flag 0 2 2 read-only 0 After R1b response was received, SD/MMC was released from the busy state during the specified period #0 1 After R1b response was received, SD/MMC was in the busy state after the specified period elapsed #1 BSYTO1 Busy Timeout Flag 1 3 3 read-only 0 After CMD12 was automatically issued, SD/MMC was released from the busy state during the specified period #0 1 After CMD12 was automatically issued, SD/MMC was in the busy state after the specified period elapsed (with SD_CMD.CMDIDX[5:0] setting, an error that occurs with CMD12 issue is indicated in the BSYTO0 flag) #1 RDTO Read Data Timeout Flag 4 4 read-only CRCTO CRC Status Token Timeout Flag 5 5 read-only 0 After CRC data was written to the SD card/MMC, a CRC status token was received during the specified period #0 1 After CRC data was written to the SD card/MMC, a CRC status token was not received after the specified period elapsed #1 CRCBSYTO CRC Status Token Busy Timeout Flag 6 6 read-only 0 After a CRC status token was received, the SD/MMC was released from the busy state during the specified period #0 1 After a CRC status token was received, the SD/MMC was in the busy state after the specified period elapsed #1 SD_BUF0 SD Buffer Register 0x060 32 read-write 0x00000000 0x00000000 SDIO_MODE SDIO Mode Control Register 0x068 32 read-write 0x00000000 0xffffffff INTEN SDIO Interrupt Acceptance Enable 0 0 read-write 0 Disable SDIO interrupt acceptance #0 1 Enable SDIO interrupt acceptance #1 RWREQ Read Wait Request 2 2 read-write 0 Allow SD/MMC to exit read wait state #0 1 Request for SD/MMC to enter read wait state #1 IOABT SDIO Abort 8 8 read-write C52PUB SDIO None Abort 9 9 read-write SDIO_INFO1 SDIO Interrupt Flag Register 0x06C 32 read-write 0x00000000 0xfffffff9 IOIRQ SDIO Interrupt Status Flag 0 0 read-write 0 No SDIO interrupt detected #0 1 SDIO interrupt detected #1 EXPUB52 EXPUB52 Status Flag 14 14 read-write EXWT EXWT Status Flag 15 15 read-write SDIO_INFO1_MASK SDIO INFO1 Interrupt Mask Register 0x070 32 read-write 0x0000c007 0xffffffff IOIRQM IOIRQ Interrupt Mask Control 0 0 read-write 0 Do not mask IOIRQ interrupts #0 1 Mask IOIRQ interrupts #1 EXPUB52M EXPUB52 Interrupt Request Mask Control 14 14 read-write 0 Do not mask EXPUB52 interrupt requests #0 1 Mask EXPUB52 interrupt requests #1 EXWTM EXWT Interrupt Request Mask Control 15 15 read-write 0 Do not mask EXWT interrupt requests #0 1 Mask EXWT interrupt requests #1 SD_DMAEN DMA Mode Enable Register 0x1B0 32 read-write 0x00001010 0xffffffff DMAEN DMA Transfer Enable 1 1 read-write 0 Disable use of DMA transfer to access SD_BUF0 register #0 1 Enable use of DMA transfer to access SD_BUF0 register #1 SOFT_RST Software Reset Register 0x1C0 32 read-write 0x00000007 0xffffffff SDRST Software Reset Control 0 0 read-write 0 Reset SD/MMC Host Interface software #0 1 Cancel reset of SD/MMC Host Interface software #1 SDIF_MODE SD Interface Mode Setting Register 0x1CC 32 read-write 0x00000000 0xffffffff NOCHKCR CRC Check Mask 8 8 read-write 0 Enable CRC check #0 1 Disable CRC Check (ignore CRC16 valued when reading and ignore CRC status value when writing) #1 EXT_SWAP Swap Control Register 0x1E0 32 read-write 0x00000000 0xffffffff BWSWP SD_BUF0 Swap Write 6 6 read-write 0 Normal write operation #0 1 Swap the byte endian order before writing to SD_BUF0 register #1 BRSWP SD_BUF0 Swap Read 7 7 read-write 0 Normal read operation #0 1 Swap the byte endian order before reading SD_BUF0 register #1 SSIE0 Serial Sound Interface Enhanced (SSIE) 0x4009D000 0x00 8 registers 0x10 24 registers SSICR Control Register 0x00 32 read-write 0x00000000 0xffffffff REN Reception Enable 0 0 read-write 0 Disables reception #0 1 Enables reception (starts reception) #1 TEN Transmission Enable 1 1 read-write 0 Disables transmission #0 1 Enables transmission (starts transmission) #1 MUEN Mute Enable 3 3 read-write 0 Disables muting on the next frame boundary #0 1 Enables muting on the next frame boundary #1 CKDV Selects Bit Clock Division Ratio 4 7 read-write 0x0 AUDIO_MCK 0x0 0x1 AUDIO_MCK/2 0x1 0x2 AUDIO_MCK/4 0x2 0x3 AUDIO_MCK/8 0x3 0x4 AUDIO_MCK/16 0x4 0x5 AUDIO_MCK/32 0x5 0x6 AUDIO_MCK/64 0x6 0x7 AUDIO_MCK/128 0x7 0x8 AUDIO_MCK/6 0x8 0x9 AUDIO_MCK/12 0x9 0xA AUDIO_MCK/24 0xa 0xB AUDIO_MCK/48 0xb 0xC AUDIO_MCK/96 0xc Others Setting prohibited true DEL Selects Serial Data Delay 8 8 read-write 0 Delay of 1 cycle of SSIBCK between SSILRCK/SSIFS and SSITXD0/SSIRXD0 #0 1 No delay between SSILRCK/SSIFS and SSITXD0/SSIRXD0 #1 PDTA Selects Placement Data Alignment 9 9 read-write 0 Left-justifies placement data (SSIFTDR, SSIFRDR) #0 1 Right-justifies placement data (SSIFTDR, SSIFRDR) #1 SDTA Selects Serial Data Alignment 10 10 read-write 0 Transmits and receives serial data first and then padding bits #0 1 Transmit and receives padding bits first and then serial data #1 SPDP Selects Serial Padding Polarity 11 11 read-write 0 Padding data is at a low level #0 1 Padding data is at a high level #1 LRCKP Selects the Initial Value and Polarity of LR Clock/Frame Synchronization Signal 12 12 read-write 0 The initial value is at a high level. The start trigger for a frame is synchronized with a falling edge of SSILRCK/SSIFS. #0 1 The initial value is at a low level. The start trigger for a frame is synchronized with a rising edge of SSILRCK/SSIFS. #1 BCKP Selects Bit Clock Polarity 13 13 read-write 0 SSILRCK/SSIFS and SSITXD0/SSIRXD0 change at a falling edge (SSILRCK/SSIFS and SSIRXD0 are sampled at a rising edge of SSIBCK). #0 1 SSILRCK/SSIFS and SSITXD0/SSIRXD0 change at a rising edge (SSILRCK/SSIFS and SSIRXD0 are sampled at a falling edge of SSIBCK). #1 MST Master Enable 14 14 read-write 0 Slave-mode communication #0 1 Master-mode communication #1 SWL Selects System Word Length 16 18 read-write 000 8 bits #000 001 16 bits #001 010 24 bits #010 011 32 bits #011 100 48 bits #100 101 64 bits #101 110 128 bits #110 111 256 bits #111 DWL Selects Data Word Length 19 21 read-write 000 8 bits #000 001 16 bits #001 010 18 bits #010 011 20 bits #011 100 22 bits #100 101 24 bits #101 110 32 bits #110 111 Setting prohibited #111 FRM Selects Frame Word Number 22 23 read-write IIEN Idle Mode Interrupt Output Enable 25 25 read-write 0 Disables idle mode interrupt output #0 1 Enables idle mode interrupt output #1 ROIEN Receive Overflow Interrupt Output Enable 26 26 read-write 0 Disables receive overflow interrupt output #0 1 Enables receive overflow interrupt output #1 RUIEN Receive Underflow Interrupt Output Enable 27 27 read-write 0 Disables receive underflow interrupt output #0 1 Enables receive underflow interrupt output #1 TOIEN Transmit Overflow Interrupt Output Enable 28 28 read-write 0 Disables transmit overflow interrupt output #0 1 Enables transmit overflow interrupt output #1 TUIEN Transmit Underflow Interrupt Output Enable 29 29 read-write 0 Disables transmit underflow interrupt output #0 1 Enables transmit underflow interrupt output #1 CKS Selects an Audio Clock for Master-mode Communication 30 30 read-write 0 Selects the AUDIO_CLK input #0 1 Selects the GTIOC2A (GPT output) #1 SSISR Status Register 0x04 32 read-write 0x02000000 0xffffffff IIRQ Idle Mode Status Flag 25 25 read-only 0 In the communication state #0 1 In the idle state #1 ROIRQ Receive Overflow Error Status Flag 26 26 read-write 0 No receive overflow error is generated. #0 1 A receive overflow error is generated. #1 RUIRQ Receive Underflow Error Status Flag 27 27 read-write 0 No receive underflow error is generated. #0 1 A receive underflow error is generated. #1 TOIRQ Transmit Overflow Error Status Flag 28 28 read-write 0 No transmit overflow error is generated. #0 1 A transmit overflow error is generated. #1 TUIRQ Transmit Underflow Error Status flag 29 29 read-write 0 No transmit underflow error is generated. #0 1 A transmit underflow error is generated. #1 SSIFCR FIFO Control Register 0x10 32 read-write 0x00000000 0xffffffff RFRST Receive FIFO Data Register Reset 0 0 read-write 0 Clears a receive data FIFO reset condition #0 1 Sets a receive data FIFO reset condition #1 TFRST Transmit FIFO Data Register Reset 1 1 read-write 0 Clears a transmit data FIFO reset condition #0 1 Sets a transmit data FIFO reset condition #1 RIE Receive Data Full Interrupt Output Enable 2 2 read-write 0 Disables receive data full interrupts #0 1 Enables receive data full interrupts #1 TIE Transmit Data Empty Interrupt Output Enable 3 3 read-write 0 Disables transmit data empty interrupts #0 1 Enables transmit data empty interrupts #1 BSW Byte Swap Enable 11 11 read-write 0 Disables byte swap #0 1 Enables byte swap #1 SSIRST Software Reset 16 16 read-write 0 Clears a software reset condition #0 1 Sets a software reset condition #1 AUCKE AUDIO_MCK Enable in Mastermode Communication 31 31 read-write 0 Disables supply of AUDIO_MCK #0 1 Enables supply of AUDIO_MCK #1 SSIFSR FIFO Status Register 0x14 32 read-write 0x00010000 0xffffffff RDF Receive Data Full Flag 0 0 read-write 0 The size of received data in SSIFRDR is not more than the value of SSISCR.RDFS. #0 1 The size of received data in SSIFRDR is not less than the value of SSISCR.RDFS plus one. #1 RDC Number of Receive FIFO Data Indication Flag 8 13 read-only TDE Transmit Data Empty Flag 16 16 read-write 0 The free space of SSIFTDR is not more than the value of SSISCR.TDES. #0 1 The free space of SSIFTDR is not less than the value of SSISCR.TDES plus one. #1 TDC Number of Transmit FIFO Data Indication Flag 24 29 read-only SSIFTDR Transmit FIFO Data Register 0x18 32 write-only 0x00000000 0xffffffff SSIFTDR Transmit FIFO Data 0 31 write-only SSIFRDR Receive FIFO Data Register 0x1C 32 read-only 0x00000000 0xffffffff SSIFRDR Receive FIFO Data 0 31 read-only SSIOFR Audio Format Register 0x20 32 read-write 0x00000000 0xffffffff OMOD Audio Format Select 0 1 read-write 00 I2S format #00 01 TDM format #01 10 Monaural format #10 11 Setting prohibited #11 LRCONT Whether to Enable LRCK/FS Continuation 8 8 read-write 0 Disables LRCK/FS continuation #0 1 Enables LRCK/FS continuation #1 BCKASTP Whether to Enable Stopping BCK Output When SSIE is in Idle Status 9 9 read-write 0 Always outputs BCK to the SSIBCK pin #0 1 Automatically controls output of BCK to the SSIBCK pin #1 SSISCR Status Control Register 0x24 32 read-write 0x00000000 0xffffffff RDFS RDF Setting Condition Select 0 4 read-write TDES TDE Setting Condition Select 8 12 read-write IIC0 Inter-Integrated Circuit 0 0x4009F000 0x00 20 registers ICCR1 I2C Bus Control Register 1 0x00 8 read-write 0x1f 0xff SDAI SDA Line Monitor 0 0 read-only 0 SDAn line is low #0 1 SDAn line is high #1 SCLI SCL Line Monitor 1 1 read-only 0 SCLn line is low #0 1 SCLn line is high #1 SDAO SDA Output Control/Monitor 2 2 read-write 0 Read: IIC drives SDAn pin low Write: IIC drives SDAn pin low #0 1 Read: IIC releases SDAn pin Write: IIC releases SDAn pin #1 SCLO SCL Output Control/Monitor 3 3 read-write 0 Read: IIC drives SCLn pin low Write: IIC drives SCLn pin low #0 1 Read: IIC releases SCLn pin Write: IIC releases SCLn pin #1 SOWP SCLO/SDAO Write Protect 4 4 write-only 0 Write enable SCLO and SDAO bits #0 1 Write protect SCLO and SDAO bits #1 CLO Extra SCL Clock Cycle Output 5 5 read-write 0 Do not output extra SCL clock cycle (default) #0 1 Output extra SCL clock cycle #1 IICRST I2C Bus Interface Internal Reset 6 6 read-write 0 Release IIC reset or internal reset #0 1 Initiate IIC reset or internal reset #1 ICE I2C Bus Interface Enable 7 7 read-write 0 Disable (SCLn and SDAn pins in inactive state) #0 1 Enable (SCLn and SDAn pins in active state) #1 ICCR2 I2C Bus Control Register 2 0x01 8 read-write 0x00 0xff ST Start Condition Issuance Request 1 1 read-write 0 Do not issue a start condition request #0 1 Issue a start condition request #1 RS Restart Condition Issuance Request 2 2 read-write 0 Do not issue a restart condition request #0 1 Issue a restart condition request #1 SP Stop Condition Issuance Request 3 3 read-write 0 Do not issue a stop condition request #0 1 Issue a stop condition request #1 TRS Transmit/Receive Mode 5 5 read-write 0 Receive mode #0 1 Transmit mode #1 MST Master/Slave Mode 6 6 read-write 0 Slave mode #0 1 Master mode #1 BBSY Bus Busy Detection Flag 7 7 read-only 0 I2C bus released (bus free state) #0 1 I2C bus occupied (bus busy state) #1 ICMR1 I2C Bus Mode Register 1 0x02 8 read-write 0x08 0xff BC Bit Counter 0 2 read-write 000 9 bits #000 001 2 bits #001 010 3 bits #010 011 4 bits #011 100 5 bits #100 101 6 bits #101 110 7 bits #110 111 8 bits #111 BCWP BC Write Protect 3 3 write-only 0 Write enable BC[2:0] bits #0 1 Write protect BC[2:0] bits #1 CKS Internal Reference Clock Select 4 6 read-write MTWP MST/TRS Write Protect 7 7 read-write 0 Write protect MST and TRS bits in ICCR2 #0 1 Write enable MST and TRS bits in ICCR2 #1 ICMR2 I2C Bus Mode Register 2 0x03 8 read-write 0x06 0xff TMOS Timeout Detection Time Select 0 0 read-write 0 Select long mode #0 1 Select short mode #1 TMOL Timeout L Count Control 1 1 read-write 0 Disable count while SCLn line is low #0 1 Enable count while SCLn line is low #1 TMOH Timeout H Count Control 2 2 read-write 0 Disable count while SCLn line is high #0 1 Enable count while SCLn line is high #1 SDDL SDA Output Delay Counter 4 6 read-write 000 No output delay #000 001 1 IIC-phi cycle (When ICMR2.DLCS = 0 (IIC-phi)) 1 or 2 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #001 010 2 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 3 or 4 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #010 011 3 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 5 or 6 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #011 100 4 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 7 or 8 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #100 101 5 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 9 or 10 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #101 110 6 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 11 or 12 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #110 111 7 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 13 or 14 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #111 DLCS SDA Output Delay Clock Source Select 7 7 read-write 0 Select internal reference clock (IIC-phi) as the clock source for SDA output delay counter #0 1 Select internal reference clock divided by 2 (IIC-phi/2) as the clock source for SDA output delay counter #1 ICMR3 I2C Bus Mode Register 3 0x04 8 read-write 0x00 0xff NF Noise Filter Stage Select 0 1 read-write 00 Filter out noise of up to 1 IIC-phi cycle (single-stage filter) #00 01 Filter out noise of up to 2 IIC-phi cycles (2-stage filter) #01 10 Filter out noise of up to 3 IIC-phi cycles (3-stage filter) #10 11 Filter out noise of up to 4 IIC-phi cycles (4-stage filter) #11 ACKBR Receive Acknowledge 2 2 read-only 0 0 received as the acknowledge bit (ACK reception) #0 1 1 received as the acknowledge bit (NACK reception) #1 ACKBT Transmit Acknowledge 3 3 read-write 0 Send 0 as the acknowledge bit (ACK transmission) #0 1 Send 1 as the acknowledge bit (NACK transmission) #1 ACKWP ACKBT Write Protect 4 4 read-write 0 Write protect ACKBT bit #0 1 Write enable ACKBT bit #1 RDRFS RDRF Flag Set Timing Select 5 5 read-write 0 Set the RDRF flag on the rising edge of the 9th SCL clock cycle. The SCLn line is not held low on the falling edge of the 8th clock cycle. #0 1 Set the RDRF flag on the rising edge of the 8th SCL clock cycle. The SCLn line is held low on the falling edge of the 8th clock cycle. #1 WAIT Low-hold is released by reading ICDRR. 6 6 read-write 0 No wait (The SCLn line is not held low during the period between the 9th clock cycle and the 1st clock cycle.) #0 1 Wait (The SCLn line is held low during the period between the 9th clock cycle and the 1st clock cycle.) #1 SMBS SMBus/I2C Bus Select 7 7 read-write 0 Select I2C Bus #0 1 Select SMBus #1 ICFER I2C Bus Function Enable Register 0x05 8 read-write 0x72 0xff TMOE Timeout Function Enable 0 0 read-write 0 Disable #0 1 Enable #1 MALE Master Arbitration-Lost Detection Enable 1 1 read-write 0 Disable the arbitration-lost detection function and disable automatic clearing of the MST and TRS bits in ICCR2 when arbitration is lost #0 1 Enable the arbitration-lost detection function and enable automatic clearing of the MST and TRS bits in ICCR2 when arbitration is lost #1 NALE NACK Transmission Arbitration-Lost Detection Enable 2 2 read-write 0 Disable #0 1 Enable #1 SALE Slave Arbitration-Lost Detection Enable 3 3 read-write 0 Disable #0 1 Enable #1 NACKE NACK Reception Transfer Suspension Enable 4 4 read-write 0 Do not suspend transfer operation during NACK reception (disable transfer suspension) #0 1 Suspend transfer operation during NACK reception (enable transfer suspension) #1 NFE Digital Noise Filter Circuit Enable 5 5 read-write 0 Do not use the digital noise filter circuit #0 1 Use the digital noise filter circuit #1 SCLE SCL Synchronous Circuit Enable 6 6 read-write 0 Do not use the SCL synchronous circuit #0 1 Use the SCL synchronous circuit #1 FMPE Fast-Mode Plus Enable 7 7 read-write 0 Do not use the Fm+ slope control circuit for the SCLn and SDAn pins #0 1 Use the Fm+ slope control circuit for the SCLn and SDAn pins. #1 ICSER I2C Bus Status Enable Register 0x06 8 read-write 0x09 0xff SAR0E Slave Address Register 0 Enable 0 0 read-write 0 Disable slave address in SARL0 and SARU0 #0 1 Enable slave address in SARL0 and SARU0 #1 SAR1E Slave Address Register 1 Enable 1 1 read-write 0 Disable slave address in SARL1 and SARU1 #0 1 Enable slave address in SARL1 and SARU1 #1 SAR2E Slave Address Register 2 Enable 2 2 read-write 0 Disable slave address in SARL2 and SARU2 #0 1 Enable slave address in SARL2 and SARU2 #1 GCAE General Call Address Enable 3 3 read-write 0 Disable general call address detection #0 1 Enable general call address detection #1 DIDE Device-ID Address Detection Enable 5 5 read-write 0 Disable device-ID address detection #0 1 Enable device-ID address detection #1 HOAE Host Address Enable 7 7 read-write 0 Disable host address detection #0 1 Enable host address detection #1 ICIER I2C Bus Interrupt Enable Register 0x07 8 read-write 0x00 0xff TMOIE Timeout Interrupt Request Enable 0 0 read-write 0 Disable timeout interrupt (TMOI) request #0 1 Enable timeout interrupt (TMOI) request #1 ALIE Arbitration-Lost Interrupt Request Enable 1 1 read-write 0 Disable arbitration-lost interrupt (ALI) request #0 1 Enable arbitration-lost interrupt (ALI) request #1 STIE Start Condition Detection Interrupt Request Enable 2 2 read-write 0 Disable start condition detection interrupt (STI) request #0 1 Enable start condition detection interrupt (STI) request #1 SPIE Stop Condition Detection Interrupt Request Enable 3 3 read-write 0 Disable stop condition detection interrupt (SPI) request #0 1 Enable stop condition detection interrupt (SPI) request #1 NAKIE NACK Reception Interrupt Request Enable 4 4 read-write 0 Disable NACK reception interrupt (NAKI) request #0 1 Enable NACK reception interrupt (NAKI) request #1 RIE Receive Data Full Interrupt Request Enable 5 5 read-write 0 Disable receive data full interrupt (IICn_RXI) request #0 1 Enable receive data full interrupt (IICn_RXI) request #1 TEIE Transmit End Interrupt Request Enable 6 6 read-write 0 Disable transmit end interrupt (IICn_TEI) request #0 1 Enable transmit end interrupt (IICn_TEI) request #1 TIE Transmit Data Empty Interrupt Request Enable 7 7 read-write 0 Disable transmit data empty interrupt (IICn_TXI) request #0 1 Enable transmit data empty interrupt (IICn_TXI) request #1 ICSR1 I2C Bus Status Register 1 0x08 8 read-write 0x00 0xff AAS0 Slave Address 0 Detection Flag 0 0 read-write 0 Slave address 0 not detected #0 1 Slave address 0 detected #1 AAS1 Slave Address 1 Detection Flag 1 1 read-write 0 Slave address 1 not detected #0 1 Slave address 1 detected #1 AAS2 Slave Address 2 Detection Flag 2 2 read-write 0 Slave address 2 not detected #0 1 Slave address 2 detected #1 GCA General Call Address Detection Flag 3 3 read-write 0 General call address not detected #0 1 General call address detected #1 DID Device-ID Address Detection Flag 5 5 read-write 0 Device-ID command not detected #0 1 Device-ID command detected #1 HOA Host Address Detection Flag 7 7 read-write 0 Host address not detected #0 1 Host address detected #1 ICSR2 I2C Bus Status Register 2 0x09 8 read-write 0x00 0xff TMOF Timeout Detection Flag 0 0 read-write 0 Timeout not detected #0 1 Timeout detected #1 AL Arbitration-Lost Flag 1 1 read-write 0 Arbitration not lost #0 1 Arbitration lost #1 START Start Condition Detection Flag 2 2 read-write 0 Start condition not detected #0 1 Start condition detected #1 STOP Stop Condition Detection Flag 3 3 read-write 0 Stop condition not detected #0 1 Stop condition detected #1 NACKF NACK Detection Flag 4 4 read-write 0 NACK not detected #0 1 NACK detected #1 RDRF Receive Data Full Flag 5 5 read-write 0 ICDRR contains no receive data #0 1 ICDRR contains receive data #1 TEND Transmit End Flag 6 6 read-write 0 Data being transmitted #0 1 Data transmit complete #1 TDRE Transmit Data Empty Flag 7 7 read-only 0 ICDRT contains transmit data #0 1 ICDRT contains no transmit data #1 3 0x02 0-2 SARL%s Slave Address Register Ly 0x0A 8 read-write 0x00 0xff SVA0 10-bit Address LSB 0 0 read-write SVA 7-bit Address/10-bit Address Lower Bits 1 7 read-write 3 0x02 0-2 SARU%s Slave Address Register Uy 0x0B 8 read-write 0x00 0xff FS 7-bit/10-bit Address Format Select 0 0 read-write 0 Select 7-bit address format #0 1 Select 10-bit address format #1 SVA 10-bit Address Upper Bits 1 2 read-write ICBRL I2C Bus Bit Rate Low-Level Register 0x10 8 read-write 0xff 0xff BRL Bit Rate Low-Level Period 0 4 read-write ICBRH I2C Bus Bit Rate High-Level Register 0x11 8 read-write 0xff 0xff BRH Bit Rate High-Level Period 0 4 read-write ICDRT I2C Bus Transmit Data Register 0x12 8 read-write 0xff 0xff ICDRR I2C Bus Receive Data Register 0x13 8 read-only 0x00 0xff IIC0WU Inter-Integrated Circuit 0 Wake-up Unit 0x4009F014 0x02 2 registers ICWUR I2C Bus Wakeup Unit Register 0x02 8 read-write 0x10 0xff WUAFA Wakeup Analog Filter Additional Selection 0 0 read-write 0 Do not add the wakeup analog filter #0 1 Add the wakeup analog filter #1 WUACK ACK Bit for Wakeup Mode 4 4 read-write WUF Wakeup Event Occurrence Flag 5 5 read-write 0 Slave address not matching during wakeup #0 1 Slave address matching during wakeup #1 WUIE Wakeup Interrupt Request Enable 6 6 read-write 0 Disable wakeup interrupt request (IIC0_WUI) #0 1 Enable wakeup interrupt request (IIC0_WUI) #1 WUE Wakeup Function Enable 7 7 read-write 0 Disable wakeup function #0 1 Enable wakeup function #1 ICWUR2 I2C Bus Wakeup Unit Register 2 0x03 8 read-write 0xfd 0xff WUSEN Wakeup Function Synchronous Enable 0 0 read-write 0 IIC asynchronous circuit enable #0 1 IIC synchronous circuit enable #1 WUASYF Wakeup Function Asynchronous Operation Status Flag 1 1 read-only 0 IIC synchronous circuit enable condition #0 1 IIC asynchronous circuit enable condition #1 WUSYF Wakeup Function Synchronous Operation Status Flag 2 2 read-only 0 IIC asynchronous circuit enable condition #0 1 IIC synchronous circuit enable condition #1 IIC1 Inter-Integrated Circuit 1 0x4009F100 CAN0 Controller Area Network 0x400A8000 0x200 560 registers 0x820 57 registers 32 0x10 0-31 MB%s_ID Mailbox ID Register %s 0x200 32 read-write 0x00000000 0x00000001 EID Extended ID of data and remote frames 0 17 read-write SID Standard ID of data and remote frames 18 28 read-write RTR Remote Transmission Request 30 30 read-write 0 Data frame #0 1 Remote frame #1 IDE ID Extension 31 31 read-write 0 Standard ID #0 1 Extended ID #1 32 0x10 0-31 MB%s_DL Mailbox Data Length Register %s 0x204 16 read-write 0x0000 0x0000 DLC Data Length Code 0 3 read-write 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 Others Data length = 8 bytes true 32 0x10 0-31 MB%s_D0 Mailbox Data Register %s 0x206 8 read-write 0x00 0x00 DATA0 Data Bytes 0 0 7 read-write 32 0x10 0-31 MB%s_D1 Mailbox Data Register %s 0x207 8 read-write 0x00 0x00 DATA1 Data Bytes 1 0 7 read-write 32 0x10 0-31 MB%s_D2 Mailbox Data Register %s 0x208 8 read-write 0x00 0x00 DATA2 Data Bytes 2 0 7 read-write 32 0x10 0-31 MB%s_D3 Mailbox Data Register %s 0x209 8 read-write 0x00 0x00 DATA3 Data Bytes 3 0 7 read-write 32 0x10 0-31 MB%s_D4 Mailbox Data Register %s 0x20A 8 read-write 0x00 0x00 DATA4 Data Bytes 4 0 7 read-write 32 0x10 0-31 MB%s_D5 Mailbox Data Register %s 0x20B 8 read-write 0x00 0x00 DATA5 Data Bytes 5 0 7 read-write 32 0x10 0-31 MB%s_D6 Mailbox Data Register %s 0x20C 8 read-write 0x00 0x00 DATA6 Data Bytes 6 0 7 read-write 32 0x10 0-31 MB%s_D7 Mailbox Data Register %s 0x20D 8 read-write 0x00 0x00 DATA7 Data Bytes 7 0 7 read-write 32 0x10 0-31 MB%s_TS Mailbox Time Stamp Register %s 0x20E 16 read-write 0x0000 0x0000 TSL Time Stamp Lower Byte 0 7 read-write TSH Time Stamp Higher Byte 8 15 read-write 8 0x04 MKR[%s] Mask Register %s 0x400 32 read-write 0x00000000 0x00000000 EID Extended ID 0 17 read-write 0 Do not compare associated EID[17:0] bits #0 1 Compare associated EID[17:0] bits #1 SID Standard ID 18 28 read-write 0 Do not compare associated SID[10:0] bits #0 1 Compare associated SID[10:0] bits #1 2 0x04 0-1 FIDCR%s FIFO Received ID Compare Register %s 0x420 32 read-write 0x00000000 0x00000000 EID Extended ID of data and remote frames 0 17 read-write SID Standard ID of data and remote frames 18 28 read-write RTR Remote Transmission Request 30 30 read-write 0 Data frame #0 1 Remote frame #1 IDE ID Extension 31 31 read-write 0 Standard ID #0 1 Extended ID #1 MKIVLR Mask Invalid Register 0x428 32 read-write 0x00000000 0x00000000 MB00 Mask Invalid 0 0 read-write 0 Mask valid #0 1 Mask invalid #1 MB01 Mask Invalid 1 1 read-write 0 Mask valid #0 1 Mask invalid #1 MB02 Mask Invalid 2 2 read-write 0 Mask valid #0 1 Mask invalid #1 MB03 Mask Invalid 3 3 read-write 0 Mask valid #0 1 Mask invalid #1 MB04 Mask Invalid 4 4 read-write 0 Mask valid #0 1 Mask invalid #1 MB05 Mask Invalid 5 5 read-write 0 Mask valid #0 1 Mask invalid #1 MB06 Mask Invalid 6 6 read-write 0 Mask valid #0 1 Mask invalid #1 MB07 Mask Invalid 7 7 read-write 0 Mask valid #0 1 Mask invalid #1 MB08 Mask Invalid 8 8 read-write 0 Mask valid #0 1 Mask invalid #1 MB09 Mask Invalid 9 9 read-write 0 Mask valid #0 1 Mask invalid #1 MB10 Mask Invalid 10 10 read-write 0 Mask valid #0 1 Mask invalid #1 MB11 Mask Invalid 11 11 read-write 0 Mask valid #0 1 Mask invalid #1 MB12 Mask Invalid 12 12 read-write 0 Mask valid #0 1 Mask invalid #1 MB13 Mask Invalid 13 13 read-write 0 Mask valid #0 1 Mask invalid #1 MB14 Mask Invalid 14 14 read-write 0 Mask valid #0 1 Mask invalid #1 MB15 Mask Invalid 15 15 read-write 0 Mask valid #0 1 Mask invalid #1 MB16 Mask Invalid 16 16 read-write 0 Mask valid #0 1 Mask invalid #1 MB17 Mask Invalid 17 17 read-write 0 Mask valid #0 1 Mask invalid #1 MB18 Mask Invalid 18 18 read-write 0 Mask valid #0 1 Mask invalid #1 MB19 Mask Invalid 19 19 read-write 0 Mask valid #0 1 Mask invalid #1 MB20 Mask Invalid 20 20 read-write 0 Mask valid #0 1 Mask invalid #1 MB21 Mask Invalid 21 21 read-write 0 Mask valid #0 1 Mask invalid #1 MB22 Mask Invalid 22 22 read-write 0 Mask valid #0 1 Mask invalid #1 MB23 Mask Invalid 23 23 read-write 0 Mask valid #0 1 Mask invalid #1 MB24 Mask Invalid 24 24 read-write 0 Mask valid #0 1 Mask invalid #1 MB25 Mask Invalid 25 25 read-write 0 Mask valid #0 1 Mask invalid #1 MB26 Mask Invalid 26 26 read-write 0 Mask valid #0 1 Mask invalid #1 MB27 Mask Invalid 27 27 read-write 0 Mask valid #0 1 Mask invalid #1 MB28 Mask Invalid 28 28 read-write 0 Mask valid #0 1 Mask invalid #1 MB29 Mask Invalid 29 29 read-write 0 Mask valid #0 1 Mask invalid #1 MB30 Mask Invalid 30 30 read-write 0 Mask valid #0 1 Mask invalid #1 MB31 Mask Invalid 31 31 read-write 0 Mask valid #0 1 Mask invalid #1 MIER Mailbox Interrupt Enable Register 0x42C 32 read-write 0x00000000 0x00000000 MB00 Interrupt Enable 0 0 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB01 Interrupt Enable 1 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB02 Interrupt Enable 2 2 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB03 Interrupt Enable 3 3 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB04 Interrupt Enable 4 4 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB05 Interrupt Enable 5 5 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB06 Interrupt Enable 6 6 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB07 Interrupt Enable 7 7 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB08 Interrupt Enable 8 8 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB09 Interrupt Enable 9 9 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB10 Interrupt Enable 10 10 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB11 Interrupt Enable 11 11 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB12 Interrupt Enable 12 12 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB13 Interrupt Enable 13 13 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB14 Interrupt Enable 14 14 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB15 Interrupt Enable 15 15 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB16 Interrupt Enable 16 16 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB17 Interrupt Enable 17 17 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB18 Interrupt Enable 18 18 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB19 Interrupt Enable 19 19 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB20 Interrupt Enable 20 20 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB21 Interrupt Enable 21 21 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB22 Interrupt Enable 22 22 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB23 Interrupt Enable 23 23 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB24 Interrupt Enable 24 24 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB25 Interrupt Enable 25 25 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB26 Interrupt Enable 26 26 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB27 Interrupt Enable 27 27 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB28 Interrupt Enable 28 28 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB29 Interrupt Enable 29 29 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB30 Interrupt Enable 30 30 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB31 Interrupt Enable 31 31 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MIER_FIFO Mailbox Interrupt Enable Register for FIFO Mailbox Mode MIER 0x42C 32 read-write 0x00000000 0x00000000 MB00 Interrupt Enable 0 0 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB01 Interrupt Enable 1 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB02 Interrupt Enable 2 2 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB03 Interrupt Enable 3 3 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB04 Interrupt Enable 4 4 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB05 Interrupt Enable 5 5 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB06 Interrupt Enable 6 6 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB07 Interrupt Enable 7 7 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB08 Interrupt Enable 8 8 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB09 Interrupt Enable 9 9 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB10 Interrupt Enable 10 10 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB11 Interrupt Enable 11 11 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB12 Interrupt Enable 12 12 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB13 Interrupt Enable 13 13 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB14 Interrupt Enable 14 14 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB15 Interrupt Enable 15 15 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB16 Interrupt Enable 16 16 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB17 Interrupt Enable 17 17 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB18 Interrupt Enable 18 18 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB19 Interrupt Enable 19 19 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB20 Interrupt Enable 20 20 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB21 Interrupt Enable 21 21 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB22 Interrupt Enable 22 22 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB23 Interrupt Enable 23 23 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB24 Transmit FIFO Interrupt Enable 24 24 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB25 Transmit FIFO Interrupt Generation Timing Control 25 25 read-write 0 Generate every time transmission completes #0 1 Generate when the transmit FIFO empties on transmission completion #1 MB28 Receive FIFO Interrupt Enable 28 28 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB29 Receive FIFO Interrupt Generation Timing Control 29 29 read-write 0 Generate every time reception completes #0 1 Generate when the receive FIFO becomes a buffer warning on reception completion #1 32 0x01 MCTL_RX[%s] Message Control Register for Receive 0x820 8 read-write 0x00 0xff NEWDATA Reception Complete Flag 0 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 INVALDATA Reception-in-Progress Status Flag 1 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 ONESHOT One-Shot Enable 4 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 32 0x01 MCTL_TX[%s] Message Control Register for Transmit MCTL_RX[%s] 0x820 8 read-write 0x00 0xff SENTDATA Transmission Complete Flag 0 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMABT Transmission Abort Complete Flag 2 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 ONESHOT One-Shot Enable 4 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 CTLR Control Register 0x840 16 read-write 0x0500 0xffff MBM CAN Mailbox Mode Select 0 0 read-write 0 Normal mailbox mode #0 1 FIFO mailbox mode #1 IDFM ID Format Mode Select 1 2 read-write 00 Standard ID mode All mailboxes, including FIFO mailboxes, handle only standard IDs #00 01 Extended ID mode All mailboxes, including FIFO mailboxes, handle only extended IDs #01 10 Mixed ID mode All mailboxes, including FIFO mailboxes, handle both standard and extended IDs. In normal mailbox mode, use the associated IDE bit to differentiate standard and extended IDs. In FIFO mailbox mode, the associated IDE bits are used for mailboxes 0 to 23, the IDE bits in FIDCR0 and FIDCR1 are used for the receive FIFO, and the IDE bit associated with mailbox 24 is used for the transmit FIFO. #10 11 Setting prohibited #11 MLM Message Lost Mode Select 3 3 read-write 0 Overwrite mode #0 1 Overrun mode #1 TPM Transmission Priority Mode Select 4 4 read-write 0 ID priority transmit mode #0 1 Mailbox number priority transmit mode #1 TSRC Time Stamp Counter Reset Command 5 5 read-write 0 Do not reset time stamp counter #0 1 Reset time stamp counter #1 TSPS Time Stamp Prescaler Select 6 7 read-write 00 Every 1-bit time #00 01 Every 2-bit time #01 10 Every 4-bit time #10 11 Every 8-bit time #11 CANM CAN Operating Mode Select 8 9 read-write 00 CAN operation mode #00 01 CAN reset mode #01 10 CAN halt mode #10 11 CAN reset mode (forced transition) #11 SLPM CAN Sleep Mode 10 10 read-write 0 All other modes #0 1 CAN sleep mode #1 BOM Bus-Off Recovery Mode 11 12 read-write 00 Normal mode (ISO11898-1-compliant) #00 01 Enter CAN halt mode automatically on entering bus-off state #01 10 Enter CAN halt mode automatically at the end of bus-off state #10 11 Enter CAN halt mode during bus-off recovery period through a software request #11 RBOC Forcible Return from Bus-Off 13 13 read-write 0 No return occurred #0 1 Forced return from bus-off state #1 STR Status Register 0x842 16 read-only 0x0500 0xffff NDST NEWDATA Status Flag 0 0 read-only 0 No mailbox with NEWDATA = 1 #0 1 One or more mailboxes with NEWDATA = 1 #1 SDST SENTDATA Status Flag 1 1 read-only 0 No mailbox with SENTDATA = 1 #0 1 One or more mailboxes with SENTDATA = 1 #1 RFST Receive FIFO Status Flag 2 2 read-only 0 Receive FIFO empty #0 1 Message in receive FIFO #1 TFST Transmit FIFO Status Flag 3 3 read-only 0 Transmit FIFO is full #0 1 Transmit FIFO is not full #1 NMLST Normal Mailbox Message Lost Status Flag 4 4 read-only 0 No mailbox with MSGLOST = 1 #0 1 One or more mailboxes with MSGLOST = 1 #1 FMLST FIFO Mailbox Message Lost Status Flag 5 5 read-only 0 RFMLF = 0 #0 1 RFMLF = 1 #1 TABST Transmission Abort Status Flag 6 6 read-only 0 No mailbox with TRMABT = 1 #0 1 One or more mailboxes with TRMABT = 1 #1 EST Error Status Flag 7 7 read-only 0 No error occurred #0 1 Error occurred #1 RSTST CAN Reset Status Flag 8 8 read-only 0 Not in CAN reset mode #0 1 In CAN reset mode #1 HLTST CAN Halt Status Flag 9 9 read-only 0 Not in CAN halt mode #0 1 In CAN halt mode #1 SLPST CAN Sleep Status Flag 10 10 read-only 0 Not in CAN sleep mode #0 1 In CAN sleep mode #1 EPST Error-Passive Status Flag 11 11 read-only 0 Not in error-passive state #0 1 In error-passive state #1 BOST Bus-Off Status Flag 12 12 read-only 0 Not in bus-off state #0 1 In bus-off state #1 TRMST Transmit Status Flag 13 13 read-only 0 Bus idle or reception in progress #0 1 Transmission in progress or module in bus-off state #1 RECST Receive Status Flag 14 14 read-only 0 Bus idle or transmission in progress #0 1 Reception in progress #1 BCR Bit Configuration Register 0x844 32 read-write 0x00000000 0xffffffff CCLKS CAN Clock Source Selection 0 0 read-write 0 PCLKB (generated by the PLL clock) #0 1 CANMCLK (generated by the main clock oscillator) #1 TSEG2 Time Segment 2 Control 8 10 read-write 000 Setting prohibited #000 001 2 Tq #001 010 3 Tq #010 011 4 Tq #011 100 5 Tq #100 101 6 Tq #101 110 7 Tq #110 111 8 Tq #111 SJW Synchronization Jump Width Control 12 13 read-write 00 1 Tq #00 01 2 Tq #01 10 3 Tq #10 11 4 Tq #11 BRP Baud Rate Prescaler Select 16 25 read-write TSEG1 Time Segment 1 Control 28 31 read-write 0x3 4 Tq 0x3 0x4 5 Tq 0x4 0x5 6 Tq 0x5 0x6 7 Tq 0x6 0x7 8 Tq 0x7 0x8 9 Tq 0x8 0x9 10 Tq 0x9 0xA 11 Tq 0xa 0xB 12 Tq 0xb 0xC 13 Tq 0xc 0xD 14 Tq 0xd 0xE 15 Tq 0xe 0xF 16 Tq 0xf Others Setting prohibited true RFCR Receive FIFO Control Register 0x848 8 read-write 0x80 0xff RFE Receive FIFO Enable 0 0 read-write 0 Disable receive FIFO #0 1 Enable receive FIFO #1 RFUST Receive FIFO Unread Message Number Status 1 3 read-only 000 No unread message #000 001 1 unread message #001 010 2 unread messages #010 011 3 unread messages #011 100 4 unread messages #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 RFMLF Receive FIFO Message Lost Flag 4 4 read-write 0 Receive FIFO message not lost #0 1 Receive FIFO message lost #1 RFFST Receive FIFO Full Status Flag 5 5 read-only 0 Receive FIFO not full #0 1 Receive FIFO full (4 unread messages) #1 RFWST Receive FIFO Buffer Warning Status Flag 6 6 read-only 0 Receive FIFO is not buffer warning #0 1 Receive FIFO is buffer warning (3 unread messages) #1 RFEST Receive FIFO Empty Status Flag 7 7 read-only 0 Unread message in receive FIFO #0 1 No unread message in receive FIFO #1 RFPCR Receive FIFO Pointer Control Register 0x849 8 write-only 0x00 0x00 TFCR Transmit FIFO Control Register 0x84A 8 read-write 0x80 0xff TFE Transmit FIFO Enable 0 0 read-write 0 Disable transmit FIFO #0 1 Enable transmit FIFO #1 TFUST Transmit FIFO Unsent Message Number Status 1 3 read-only 000 0 unsent messages #000 001 1 unsent message #001 010 2 unsent messages #010 011 3 unread messages #011 100 4 unread messages #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TFFST Transmit FIFO Full Status 6 6 read-only 0 Transmit FIFO not full #0 1 Transmit FIFO full (4 unsent messages) #1 TFEST Transmit FIFO Empty Status 7 7 read-only 0 Unsent message in transmit FIFO #0 1 No unsent message in transmit FIFO #1 TFPCR Transmit FIFO Pointer Control Register 0x84B 8 write-only 0x00 0x00 EIER Error Interrupt Enable Register 0x84C 8 read-write 0x00 0xff BEIE Bus Error Interrupt Enable 0 0 read-write 0 Disable interrupt #0 1 Enable interrupt #1 EWIE Error-Warning Interrupt Enable 1 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 EPIE Error-Passive Interrupt Enable 2 2 read-write 0 Disable interrupt #0 1 Enable interrupt #1 BOEIE Bus-Off Entry Interrupt Enable 3 3 read-write 0 Disable interrupt #0 1 Enable interrupt #1 BORIE Bus-Off Recovery Interrupt Enable 4 4 read-write 0 Disable interrupt #0 1 Enable interrupt #1 ORIE Overrun Interrupt Enable 5 5 read-write 0 Disable interrupt #0 1 Enable interrupt #1 OLIE Overload Frame Transmit Interrupt Enable 6 6 read-write 0 Disable interrupt #0 1 Enable interrupt #1 BLIE Bus Lock Interrupt Enable 7 7 read-write 0 Disable interrupt #0 1 Enable interrupt #1 EIFR Error Interrupt Factor Judge Register 0x84D 8 read-write 0x00 0xff BEIF Bus Error Detect Flag 0 0 read-write 0 No bus error detected #0 1 Bus error detected #1 EWIF Error-Warning Detect Flag 1 1 read-write 0 No error-warning detected #0 1 Error-warning detected #1 EPIF Error-Passive Detect Flag 2 2 read-write 0 No error-passive detected #0 1 Error-passive detected #1 BOEIF Bus-Off Entry Detect Flag 3 3 read-write 0 No bus-off entry detected #0 1 Bus-off entry detected #1 BORIF Bus-Off Recovery Detect Flag 4 4 read-write 0 No bus-off recovery detected #0 1 Bus-off recovery detected #1 ORIF Receive Overrun Detect Flag 5 5 read-write 0 No receive overrun detected #0 1 Receive overrun detected #1 OLIF Overload Frame Transmission Detect Flag 6 6 read-write 0 No overload frame transmission detected #0 1 Overload frame transmission detected #1 BLIF Bus Lock Detect Flag 7 7 read-write 0 No bus lock detected #0 1 Bus lock detected #1 RECR Receive Error Count Register 0x84E 8 read-only 0x00 0xff TECR Transmit Error Count Register 0x84F 8 read-only 0x00 0xff ECSR Error Code Store Register 0x850 8 read-write 0x00 0xff SEF Stuff Error Flag 0 0 read-write 0 No stuff error detected #0 1 Stuff error detected #1 FEF Form Error Flag 1 1 read-write 0 No form error detected #0 1 Form error detected #1 AEF ACK Error Flag 2 2 read-write 0 No ACK error detected #0 1 ACK error detected #1 CEF CRC Error Flag 3 3 read-write 0 No CRC error detected #0 1 CRC error detected #1 BE1F Bit Error (recessive) Flag 4 4 read-write 0 No bit error (recessive) detected #0 1 Bit error (recessive) detected #1 BE0F Bit Error (dominant) Flag 5 5 read-write 0 No bit error (dominant) detected #0 1 Bit error (dominant) detected #1 ADEF ACK Delimiter Error Flag 6 6 read-write 0 No ACK delimiter error detected #0 1 ACK delimiter error detected #1 EDPM Error Display Mode Select 7 7 read-write 0 Output first detected error code #0 1 Output accumulated error code #1 CSSR Channel Search Support Register 0x851 8 read-write 0x00 0x00 MSSR Mailbox Search Status Register 0x852 8 read-only 0x80 0xff MBNST Search Result Mailbox Number Status 0 4 read-only SEST Search Result Status 7 7 read-only 0 Search result found #0 1 No search result #1 MSMR Mailbox Search Mode Register 0x853 8 read-write 0x00 0xff MBSM Mailbox Search Mode Select 0 1 read-write 00 Receive mailbox search mode #00 01 Transmit mailbox search mode #01 10 Message lost search mode #10 11 Channel search mode #11 TSR Time Stamp Register 0x854 16 read-only 0x0000 0xffff AFSR Acceptance Filter Support Register 0x856 16 read-write 0x0000 0x0000 TCR Test Control Register 0x858 8 read-write 0x00 0xff TSTE CAN Test Mode Enable 0 0 read-write 0 Disable CAN test mode #0 1 Enable CAN test mode #1 TSTM CAN Test Mode Select 1 2 read-write 00 Not CAN test mode #00 01 Listen-only mode #01 10 Self-test mode 0 (external loopback) #10 11 Self-test mode 1 (internal loopback) #11 CTSU Capacitive Touch Sensing Unit 0x400D0000 0x00 8 registers 0x0B 2 registers 0x10 14 registers 0x20 1 registers CTSUCR0 CTSU Control Register 0 0x00 8 read-write 0x00 0xff CTSUCR1 CTSU Control Register 1 0x01 8 read-write 0x00 0xff CTSUSDPRS CTSU Synchronous Noise Reduction Setting Register 0x02 8 read-write 0x00 0xff CTSUSST CTSU Sensor Stabilization Wait Control Register 0x03 8 read-write 0x00 0xff CTSUMCH0 CTSU Measurement Channel Register 0 0x04 8 read-write 0x1f 0xff CTSUMCH1 CTSU Measurement Channel Register 1 0x05 8 read-only 0x1f 0xff CTSUCHAC0 CTSU Channel Enable Control Register 0 0x06 8 read-write 0x00 0xff CTSUCHAC1 CTSU Channel Enable Control Register 1 0x07 8 read-write 0x00 0xff CTSUCHTRC0 CTSU Channel Transmit/Receive Control Register 0 0x0B 8 read-write 0x00 0xff CTSUCHTRC1 CTSU Channel Transmit/Receive Control Register 1 0x0C 8 read-write 0x00 0xff CTSUDCLKC CTSU High-Pass Noise Reduction Control Register 0x10 8 read-write 0x00 0xff CTSUST CTSU Status Register 0x11 8 read-write 0x00 0xff CTSUSSC CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register 0x12 16 read-write 0x0000 0xffff CTSUSSDIV CTSU Spectrum Diffusion Frequency Division Setting 8 11 read-write CTSUSO0 CTSU Sensor Offset Register 0 0x14 16 read-write 0x0000 0xffff CTSUSO1 CTSU Sensor Offset Register 1 0x16 16 read-write 0x0000 0xffff CTSUSC CTSU Sensor Counter 0x18 16 read-only 0x0000 0xffff CTSURC CTSU Reference Counter 0x1A 16 read-only 0x0000 0xffff CTSURC CTSU Reference Counter 0 15 read-only CTSUERRS CTSU Error Status Register 0x1C 16 read-write 0x0000 0x7fff CTSUSPMD Calibration Mode 0 1 read-write 00 Capacitance measurement mode #00 10 Calibration mode #10 Others Seting prohibited true CTSUTSOD TS Pin Fixed Output 2 2 read-write 0 Capacitance measurement mode #0 1 TS pins are forced to be high or low #1 CTSUDRV Calibration Setting 1 3 3 read-write 0 Capacitance measurement mode #0 1 Calibration setting 1 #1 CTSUCLKSEL1 Calibration Setting 3 6 6 read-write 0 Capacitance measurement mode #0 1 Calibration setting 3 #1 CTSUTSOC Calibration Setting 2 7 7 read-write 0 Capacitance measurement mode #0 1 Calibration setting 2 #1 CTSUICOMP TSCAP Voltage Error Monitor 15 15 read-only 0 Normal TSCAP voltage #0 1 Abnormal TSCAP voltage #1 CTSUTRMR CTSU Reference Current Calibration Register 0x20 8 read-write 0x00 0x00 PSCU Peripheral Security Control Unit 0x400E0000 0x04 44 registers PSARB Peripheral Security Attribution Register B 0x04 32 read-write 0xffffffff 0xffffffff PSARB2 CAN0 and the MSTPCRB.MSTPB2 bit security attribution 2 2 read-write 0 Secure #0 1 Non-secure #1 PSARB6 QSPI and the MSTPCRB.MSTPB6 bit security attribution 6 6 read-only PSARB8 IIC1 and the MSTPCRB.MSTPB8 bit security attribution 8 8 read-write 0 Secure #0 1 Non-secure #1 PSARB9 IIC0 and the MSTPCRB.MSTPB9 bit security attribution 9 9 read-write 0 Secure #0 1 Non-secure #1 PSARB11 USBFS and the MSTPCRB.MSTPB11 bit security attribution 11 11 read-write 0 Secure #0 1 Non-secure #1 PSARB19 SPI0 and the MSTPCRB.MSTPB19 bit security attribution 19 19 read-write 0 Secure #0 1 Non-secure #1 PSARB22 SCI9 and the MSTPCRB.MSTPB22 bit security attribution 22 22 read-write 0 Secure #0 1 Non-secure #1 PSARB27 SCI4 and the MSTPCRB.MSTPB27 bit security attribution 27 27 read-write 0 Secure #0 1 Non-secure #1 PSARB28 SCI3 and the MSTPCRB.MSTPB28 bit security attribution 28 28 read-write 0 Secure #0 1 Non-secure #1 PSARB29 SCI2 and the MSTPCRB.MSTPB29 bit security attribution 29 29 read-write 0 Secure #0 1 Non-secure #1 PSARB30 SCI1 and the MSTPCRB.MSTPB30 bit security attribution 30 30 read-write 0 Secure #0 1 Non-secure #1 PSARB31 SCI0 and the MSTPCRB.MSTPB31 bit security attribution 31 31 read-write 0 Secure #0 1 Non-secure #1 PSARC Peripheral Security Attribution Register C 0x08 32 read-write 0xffffffff 0xffffffff PSARC0 CAC and the MSTPCRC.MSTPC0 bit security attribution 0 0 read-write 0 Secure #0 1 Non-secure #1 PSARC1 CRC and the MSTPCRC.MSTPC1 bit security attribution 1 1 read-write 0 Secure #0 1 Non-secure #1 PSARC3 CTSU and the MSTPCRC.MSTPC3 bit security attribution 3 3 read-write 0 Secure #0 1 Non-secure #1 PSARC8 SSIE0 and the MSTPCRC.MSTPC8 bit security attribution 8 8 read-write 0 Secure #0 1 Non-secure #1 PSARC12 SDHI0 and the MSTPCRC.MSTPC12 bit security attribution 12 12 read-write 0 Secure #0 1 Non-secure #1 PSARC13 DOC and the MSTPCRC.MSTPC13 bit security attribution 13 13 read-write 0 Secure #0 1 Non-secure #1 PSARC31 SCE9 and the MSTPCRC.MSTPC31 bit security attribution 31 31 read-write 0 Secure #0 1 Non-secure #1 PSARD Peripheral Security Attribution Register D 0x0C 32 read-write 0xffffffff 0xffffffff PSARD0 AGT3 and the MSTPCRD.MSTPD0 bit security attribution 0 0 read-write 0 Secure #0 1 Non-secure #1 PSARD1 AGT2 and the MSTPCRD.MSTPD1 bit security attribution 1 1 read-write 0 Secure #0 1 Non-secure #1 PSARD2 AGT1 and the MSTPCRD.MSTPD2 bit security attribution 2 2 read-write 0 Secure #0 1 Non-secure #1 PSARD3 AGT0 and the MSTPCRD.MSTPD3 bit security attribution 3 3 read-write 0 Secure #0 1 Non-secure #1 PSARD11 POEG Group D and the MSTPCRD.MSTPD11 bit security attribution 11 11 read-write 0 Secure #0 1 Non-secure #1 PSARD12 POEG Group C and the MSTPCRD.MSTPD12 bit security attribution 12 12 read-write 0 Secure #0 1 Non-secure #1 PSARD13 POEG Group B and the MSTPCRD.MSTPD13 bit security attribution 13 13 read-write 0 Secure #0 1 Non-secure #1 PSARD14 POEG Group A and the MSTPCRD.MSTPD14 bit security attribution 14 14 read-write 0 Secure #0 1 Non-secure #1 PSARD16 ADC120 and the MSTPCRD.MSTPD16 bit security attribution 16 16 read-write 0 Secure #0 1 Non-secure #1 PSARD20 DAC12 and the MSTPCRD.MSTPD20 bit security attribution 20 20 read-write 0 Secure #0 1 Non-secure #1 PSARD22 TSN and the MSTPCRD.MSTPD22 bit security attribution 22 22 read-write 0 Secure #0 1 Non-secure #1 PSARE Peripheral Security Attribution Register E 0x10 32 read-write 0xffffffff 0xffffffff PSARE0 WDT security attribution 0 0 read-write 0 Secure #0 1 Non-secure #1 PSARE1 IWDT security attribution 1 1 read-write 0 Secure #0 1 Non-secure #1 PSARE2 RTC security attribution 2 2 read-write 0 Secure #0 1 Non-secure #1 PSARE14 AGT5 and the MSTPCRE.MSTPE14 bit security attribution 14 14 read-write 0 Secure #0 1 Non-secure #1 PSARE15 AGT4 and the MSTPCRE.MSTPE15 bit security attribution 15 15 read-write 0 Secure #0 1 Non-secure #1 PSARE24 GPT7 and the MSTPCRE.MSTPE24 bit security attribution 24 24 read-write 0 Secure #0 1 Non-secure #1 PSARE25 GPT6 and the MSTPCRE.MSTPE25 bit security attribution 25 25 read-write 0 Secure #0 1 Non-secure #1 PSARE26 GPT5 and the MSTPCRE.MSTPE26 bit security attribution 26 26 read-write 0 Secure #0 1 Non-secure #1 PSARE27 GPT4 and the MSTPCRE.MSTPE27 bit security attribution 27 27 read-write 0 Secure #0 1 Non-secure #1 PSARE28 GPT3 and the MSTPCRE.MSTPE28 bit security attribution 28 28 read-write 0 Secure #0 1 Non-secure #1 PSARE29 GPT2 and the MSTPCRE.MSTPE29 bit security attribution 29 29 read-write 0 Secure #0 1 Non-secure #1 PSARE30 GPT1 and the MSTPCRE.MSTPE30 bit security attribution 30 30 read-write 0 Secure #0 1 Non-secure #1 PSARE31 GPT0, GPT_OPS and the MSTPCRE.MSTPE31 bit security attribution 31 31 read-write 0 Secure #0 1 Non-secure #1 MSSAR Module Stop Security Attribution Register 0x14 32 read-write 0xffffffff 0xffffffff MSSAR0 The MSTPCRC.MSTPC14 bit security attribution 0 0 read-write 0 Secure #0 1 Non-secure #1 MSSAR1 The MSTPCRA.MSTPA22 bit security attribution 1 1 read-write 0 Secure #0 1 Non-secure #1 MSSAR2 The MSTPCRA.MSTPA7 bit security attribution 2 2 read-write 0 Secure #0 1 Non-secure #1 MSSAR3 The MSTPCRA.MSTPA0 bit security attribution 3 3 read-write 0 Secure #0 1 Non-secure #1 CFSAMONA Code Flash Security Attribution Monitor Register A 0x18 32 read-only 0x00000000 0xff007fff CFS2 Code Flash Secure area 2 15 23 read-only CFSAMONB Code Flash Security Attribution Monitor Register B 0x1C 32 read-only 0x00000000 0xff0003ff CFS1 Code Flash Secure area 1 10 23 read-only DFSAMON Data Flash Security Attribution Monitor Register 0x20 32 read-only 0x00000000 0xffff03ff DFS Data flash Secure area 10 15 read-only SSAMONA SRAM Security Attribution Monitor Register A 0x24 32 read-only 0x00000000 0xffe01fff SS2 SRAM Secure area 2 13 20 read-only SSAMONB SRAM Security Attribution Monitor Register B 0x28 32 read-only 0x00000000 0xffe003ff SS1 SRAM secure area 1 10 20 read-only DLMMON Device Lifecycle Management State Monitor Register 0x2C 32 read-only 0x00000000 0xfffffff0 DLMMON Device Lifecycle Management State Monitor 0 3 read-only 0x1 CM 0x1 0x2 SSD 0x2 0x3 NSECSD 0x3 0x4 DPL 0x4 0x5 LCK_DBG 0x5 0x6 LCK_BOOT 0x6 0x7 RMA_REQ 0x7 0x8 RMA_ACK 0x8 Others Reserved true AGT0 Low Power Asynchronous General Purpose Timer 0 0x400E8000 0x00 6 registers 0x08 3 registers 0x0C 4 registers AGT AGT Counter Register 0x00 16 read-write 0xffff 0xffff AGTCMA AGT Compare Match A Register 0x02 16 read-write 0xffff 0xffff AGTCMB AGT Compare Match B Register 0x04 16 read-write 0xffff 0xffff AGTCR AGT Control Register 0x08 8 read-write 0x00 0xff TSTART AGT Count Start 0 0 read-write 0 Count stops #0 1 Count starts #1 TCSTF AGT Count Status Flag 1 1 read-only 0 Count stopped #0 1 Count in progress #1 TSTOP AGT Count Forced Stop 2 2 write-only 0 Writing is invalid #0 1 The count is forcibly stopped #1 TEDGF Active Edge Judgment Flag 4 4 read-write 0 No active edge received #0 1 Active edge received #1 TUNDF Underflow Flag 5 5 read-write 0 No underflow #0 1 Underflow #1 TCMAF Compare Match A Flag 6 6 read-write 0 No match #0 1 Match #1 TCMBF Compare Match B Flag 7 7 read-write 0 No match #0 1 Match #1 AGTMR1 AGT Mode Register 1 0x09 8 read-write 0x00 0xff TMOD Operating Mode 0 2 read-write 000 Timer mode #000 001 Pulse output mode #001 010 Event counter mode #010 011 Pulse width measurement mode #011 100 Pulse period measurement mode #100 Others Setting prohibited true TEDGPL Edge Polarity 3 3 read-write 0 Single-edge #0 1 Both-edge #1 TCK Count Source 4 6 read-write 000 PCLKB #000 001 PCLKB/8 #001 011 PCLKB/2 #011 100 Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register #100 101 Underflow event signal from AGTn (n = 0, 2, 4) #101 110 Divided clock AGTSCLK specified by CKS[2:0] bits in the AGTMR2 register #110 Others Setting prohibited true AGTMR2 AGT Mode Register 2 0x0A 8 read-write 0x00 0xff CKS AGTLCLK or AGTSCLK Count Source Clock Frequency Division Ratio 0 2 read-write 000 1/1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 111 1/128 #111 LPM Low Power Mode 7 7 read-write 0 Normal mode #0 1 Low power mode #1 AGTIOC AGT I/O Control Register 0x0C 8 read-write 0x00 0xff TEDGSEL I/O Polarity Switch 0 0 read-write TOE AGTOn pin Output Enable 2 2 read-write 0 AGTOn pin output disabled #0 1 AGTOn pin output enabled #1 TIPF Input Filter 4 5 read-write 00 No filter #00 01 Filter sampled at PCLKB #01 10 Filter sampled at PCLKB/8 #10 11 Filter sampled at PCLKB/32 #11 TIOGT Count Control 6 7 read-write 00 Event is always counted #00 01 Event is counted during polarity period specified for AGTEEn pin #01 Others Setting prohibited true AGTISR AGT Event Pin Select Register 0x0D 8 read-write 0x00 0xff EEPS AGTEEn Polarity Selection 2 2 read-write 0 An event is counted during the low-level period #0 1 An event is counted during the high-level period #1 AGTCMSR AGT Compare Match Function Select Register 0x0E 8 read-write 0x00 0xff TCMEA AGT Compare Match A Register Enable 0 0 read-write 0 AGT Compare match A register disabled #0 1 AGT Compare match A register enabled #1 TOEA AGTOAn Pin Output Enable 1 1 read-write 0 AGTOAn pin output disabled #0 1 AGTOAn pin output enabled #1 TOPOLA AGTOAn Pin Polarity Select 2 2 read-write 0 AGTOAn pin output is started on low. i.e. normal output #0 1 AGTOAn pin output is started on high. i.e. inverted output #1 TCMEB AGT Compare Match B Register Enable 4 4 read-write 0 Compare match B register disabled #0 1 Compare match B register enabled #1 TOEB AGTOBn Pin Output Enable 5 5 read-write 0 AGTOBn pin output disabled #0 1 AGTOBn pin output enabled #1 TOPOLB AGTOBn Pin Polarity Select 6 6 read-write 0 AGTOBn pin output is started on low. i.e. normal output #0 1 AGTOBn pin output is started on high. i.e. inverted output #1 AGTIOSEL AGT Pin Select Register 0x0F 8 read-write 0x00 0xff SEL AGTIOn Pin Select 0 1 read-write 00 Select Pm/AGTIO as AGTIO. Pm/AGTIO can not be used as AGTIO input pin in Deep Software Standby mode. (m = 100, 301, and 407 (AGT0), m = 400 (AGT1), m = 103 (AGT2), m = 600(AGT3).) #00 01 Select P404/AGTIO as AGTIO P404/AGTIO can be used as AGTIO input pin in Deep Software Standby mode. P404/AGTIOn is input only. It cannot be used for output. #01 10 Select P402/AGTIO as AGTIO P402/AGTIO can be used as AGTIO input pin in Deep Software Standby mode. P402/AGTIOn is input only. It cannot be used for output. #10 11 Select P403/AGTIO as AGTIO. P403/AGTIO can be used as AGTIO input pin in Deep Software Standby mode. P403/AGTIOn is input only. It cannot be used for output. #11 TIES AGTIOn Pin Input Enable 4 4 read-write 0 External event input is disabled during Software Standby mode #0 1 External event input is enabled during Software Standby mode #1 AGT1 Low Power Asynchronous General Purpose Timer 1 0x400E8100 AGT2 Low Power Asynchronous General Purpose Timer 2 0x400E8200 AGT3 Low Power Asynchronous General Purpose Timer 3 0x400E8300 AGT4 Low Power Asynchronous General Purpose Timer 4 0x400E8400 AGT5 Low Power Asynchronous General Purpose Timer 5 0x400E8500 TSN Temperature Sensor 0x400F3000 0x00 1 registers TSCR Temperature Sensor Control Register 0x00 8 read-write 0x00 0xff TSOE Temperature Sensor Output Enable 4 4 read-write 0 Disable output from the temperature sensor to the ADC12 #0 1 Enable output from the temperature sensor to the ADC12 #1 TSEN Temperature Sensor Enable 7 7 read-write 0 Stop the temperature sensor #0 1 Start the temperature sensor. #1 CRC Cyclic Redundancy Check Calculator 0x40108000 0x00 1 registers 0x04 4 registers 0x08 4 registers CRCCR0 CRC Control Register 0 0x00 8 read-write 0x00 0xff GPS CRC Generating Polynomial Switching 0 2 read-write 001 8-bit CRC-8 (X8 + X2 + X + 1) #001 010 16-bit CRC-16 (X16 + X15 + X2 + 1) #010 011 16-bit CRC-CCITT (X16 + X12 + X5 + 1) #011 100 32-bit CRC-32 (X32 + X26 + X23 + X22 + X16 + X12 + X11 +X10 + X8 + X7 + X5 + X4 + X2 + X + 1) #100 101 32-bit CRC-32C (X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20 + X19 + X18 + X14 + X13 + X11 + X10 + X9 + X8 + X6 + 1) #101 Others No calculation is executed true LMS CRC Calculation Switching 6 6 read-write 0 Generate CRC code for LSB-first communication #0 1 Generate CRC code for MSB-first communication #1 DORCLR CRCDOR/CRCDOR_HA/CRCDOR_BY Register Clear 7 7 write-only 0 No effect #0 1 Clear the CRCDOR/CRCDOR_HA/CRCDOR_BY register #1 CRCDIR CRC Data Input Register 0x04 32 read-write 0x00000000 0xffffffff CRCDIR_BY CRC Data Input Register CRCDIR 0x04 8 read-write 0x00 0xff CRCDOR CRC Data Output Register 0x08 32 read-write 0x00000000 0xffffffff CRCDOR_HA CRC Data Output Register CRCDOR 0x08 16 read-write 0x0000 0xffff CRCDOR_BY CRC Data Output Register CRCDOR 0x08 8 read-write 0x00 0xff DOC Data Operation Circuit 0x40109000 0x00 1 registers 0x02 4 registers DOCR DOC Control Register 0x00 8 read-write 0x00 0xff OMS Operating Mode Select 0 1 read-write 00 Data comparison mode #00 01 Data addition mode #01 10 Data subtraction mode #10 11 Setting prohibited #11 DCSEL Detection Condition Select 2 2 read-write 0 Set DOPCF flag when data mismatch is detected #0 1 Set DOPCF flag when data match is detected #1 DOPCF DOC Flag 5 5 read-only DOPCFCL DOPCF Clear 6 6 read-write 0 Retain DOPCF flag state #0 1 Clear DOPCF flag #1 DODIR DOC Data Input Register 0x02 16 read-write 0x0000 0xffff DODSR DOC Data Setting Register 0x04 16 read-write 0x0000 0xffff SCI0 Serial Communication Interface 0x40118000 0x00 30 registers SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x00 8 read-write 0x00 0xff CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 MP Multi-Processor Mode 2 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 STOP Stop Bit Length 3 3 read-write 0 1 stop bit #0 1 2 stop bits #1 PM Parity Mode 4 4 read-write 0 Even parity #0 1 Odd parity #1 PE Parity Enable 5 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 CHR Character Length 6 6 read-write 0 SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CM Communication Mode 7 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x00 8 read-write 0x00 0xff CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 BCP Base Clock Pulse 2 3 read-write PM Parity Mode 4 4 read-write 0 Even parity #0 1 Odd parity #1 PE Parity Enable 5 5 read-write BLK Block Transfer Mode 6 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 GM GSM Mode 7 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 BRR Bit Rate Register 0x01 8 read-write 0xff 0xff SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x02 8 read-write 0x00 0xff CKE Clock Enable 0 1 read-write 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. The SCKn pin is available for use as an I/O port based on the I/O port settings when the GPT clock is used. In clock synchronous mode, the SCKn pin functions as the clock input pin. true TEIE Transmit End Interrupt Enable 2 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 MPIE Multi-Processor Interrupt Enable 3 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 TE Transmit Enable 5 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 RIE Receive Interrupt Enable 6 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TIE Transmit Interrupt Enable 7 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x02 8 read-write 0x00 0xff CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 TEIE Transmit End Interrupt Enable 2 2 read-write MPIE Multi-Processor Interrupt Enable 3 3 read-write RE Receive Enable 4 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 TE Transmit Enable 5 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 RIE Receive Interrupt Enable 6 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TIE Transmit Interrupt Enable 7 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 TDR Transmit Data Register 0x03 8 read-write 0xff 0xff SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0, and MMR.MANEN = 0) 0x04 8 read-write 0x84 0xff MPBT Multi-Processor Bit Transfer 0 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 MPB Multi-Processor 1 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TEND Transmit End Flag 2 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 PER Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 FER Framing Error Flag 4 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 RDRF Receive Data Full Flag 6 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 SSR_FIFO Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0, FCR.FM = 1, and MMR.MANEN = 0) SSR 0x04 8 read-write 0x80 0xfd DR Receive Data Ready Flag 0 0 read-write 0 Receiving is in progress, or no received data remains in FRDRHL after successfully completed reception (receive FIFO empty) #0 1 Next receive data is not received for a period after normal receiving is complete, when the amount of data stored in the FIFO is equal to or less than the receive triggering number #1 TEND Transmit End Flag 2 2 read-write 0 A character is being transmitted #0 1 Character transfer is complete #1 PER Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 FER Framing Error Flag 4 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 RDF Receive FIFO Data Full Flag 6 6 read-write 0 The amount of receive data written in FRDRHL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRHL is equal to or greater than the specified receive triggering number #1 TDFE Transmit FIFO Data Empty Flag 7 7 read-write 0 The amount of transmit data written in FTDRHL exceeds the specified transmit triggering number #0 1 The amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering number #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1, and MMR.MANEN = 0) SSR 0x04 8 read-write 0x84 0xff MPBT Multi-Processor Bit Transfer 0 0 read-write MPB Multi-Processor 1 1 read-only TEND Transmit End Flag 2 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 PER Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 ERS Error Signal Status Flag 4 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 ORER Overrun Error Flag 5 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 RDRF Receive Data Full Flag 6 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 RDR Receive Data Register 0x05 8 read-only 0x00 0xff SCMR Smart Card Mode Register 0x06 8 read-write 0xf2 0xff SMIF Smart Card Interface Mode Select 0 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SINV Transmitted/Received Data Invert 2 2 read-write 0 TDR contents are transmitted as they are. Received data is stored as received in the RDR register. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SDIR Transmitted/Received Data Transfer Direction 3 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 CHR1 Character Length 1 4 4 read-write 0 SMR.CHR = 0: Transmit/receive in 9-bit data length SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) SMR.CHR = 1: Transmit/receive in 7-bit data length #1 BCP2 Base Clock Pulse 2 7 7 read-write SEMR Serial Extended Mode Register 0x07 8 read-write 0x00 0xff ACS0 Asynchronous Mode Clock Source Select 0 0 read-write 0 External clock input #0 1 Logical AND of compare matches output from the internal GPT. These bit for the other SCI channels than SCIn (n = 1, 2) are reserved. #1 PADIS Preamble function Disable 1 1 read-write 0 Preamble output function is enabled #0 1 Preamble output function is disabled These bits for the other SCI channels than SCIn (n = 0, 3, 4, 9) are reserved. #1 BRME Bit Rate Modulation Enable 2 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period These bits for the other SCI channels than SCIn (n = 0, 3, 4, 9) are reserved. #1 ABCS Asynchronous Mode Base Clock Select 4 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 NFEN Digital Noise Filter Function Enable 5 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple I2C mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple I2C mode: Enable noise cancellation function for SCLn and SDAn input signals #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SNFR Noise Filter Setting Register 0x08 8 read-write 0x00 0xff NFCS Noise Filter Clock Select 0 2 read-write 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple I2C mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 8 with noise filter #100 Others Setting prohibited true SIMR1 IIC Mode Register 1 0x09 8 read-write 0x00 0xff IICM Simple IIC Mode Select 0 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 IICDL SDAn Delay Output Select 3 7 read-write 0x00 No output delay 0x00 Others (IICDL - 1) to (IICDL) cycles true SIMR2 IIC Mode Register 2 0x0A 8 read-write 0x00 0xff IICINTM IIC Interrupt Mode Select 0 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 IICCSC Clock Synchronization 1 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICACKT ACK Transmission Data 5 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 SIMR3 IIC Mode Register 3 0x0B 8 read-write 0x00 0xff IICSTAREQ Start Condition Generation 0 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICRSTAREQ Restart Condition Generation 1 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSTPREQ Stop Condition Generation 2 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSDAS SDAn Output Select 4 5 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSCLS SCLn Output Select 6 7 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 SISR IIC Status Register 0x0C 8 read-only 0x00 0xcb IICACKR ACK Reception Data Flag 0 0 read-only 0 ACK received #0 1 NACK received #1 SPMR SPI Mode Register 0x0D 8 read-write 0x00 0xff SSE SSn Pin Function Enable 0 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 CTSE CTS Enable 1 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MSS Master Slave Select 2 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 CTSPEN CTS external pin Enable 3 3 read-write 0 Alternate setting to use CTS and RTS functions as either one terminal #0 1 Dedicated setting for separately using CTS and RTS functions with 2 terminals These bits for the other SCI channels than SCIn (n = 0, 3, 4, 9) are reserved. #1 MFF Mode Fault Flag 4 4 read-write 0 No mode fault error #0 1 Mode fault error #1 CKPOL Clock Polarity Select 6 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CKPH Clock Phase Select 7 7 read-write 0 Do not delay clock #0 1 Delay clock #1 FTDRHL Transmit FIFO Data Register 0x0E 16 write-only 0xffff 0xffff TDAT Serial transmit data 0 8 write-only MPBT Multi-Processor Transfer Bit Flag 9 9 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TDRHL Transmit Data Register for Non-Manchester mode (MMR.MANEN = 0) FTDRHL 0x0E 16 read-write 0xffff 0xffff TDAT Serial Transmit Data 0 8 read-write FTDRH Transmit FIFO Data Register FTDRHL 0x0E 8 write-only 0xff 0xff MPBT Multi-Processor Transfer Bit Flag 1 1 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 FTDRL Transmit FIFO Data Register FTDRHL 0x0F 8 write-only 0xff 0xff TDAT Serial transmit data 0 7 write-only FRDRHL Receive FIFO Data Register 0x10 16 read-only 0x0000 0xffff RDAT Serial receive data 0 8 read-only MPB Multi-Processor Bit Flag 9 9 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 DR Receive Data Ready Flag 10 10 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 PER Parity Error Flag 11 11 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 FER Framing Error Flag 12 12 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 ORER Overrun Error Flag 13 13 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 RDF Receive FIFO Data Full Flag 14 14 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 RDRHL Receive Data Register for Non-Manchester mode (MMR.MANEN = 0) FRDRHL 0x10 16 read-only 0x0000 0xffff RDAT Serial Receive Data 0 8 read-only FRDRH Receive FIFO Data Register FRDRHL 0x10 8 read-only 0x00 0xff MPB Multi-Processor Bit Flag 1 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 DR Receive Data Ready Flag 2 2 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 PER Parity Error Flag 3 3 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 FER Framing Error Flag 4 4 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 ORER Overrun Error Flag 5 5 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 RDF Receive FIFO Data Full Flag 6 6 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRL Receive FIFO Data Register FRDRHL 0x11 8 read-only 0x00 0xff RDAT Serial receive data 0 7 read-only MDDR Modulation Duty Register 0x12 8 read-write 0xff 0xff DCCR Data Compare Match Control Register 0x13 8 read-write 0x40 0xff DCMF Data Compare Match Flag 0 0 read-write 0 Not matched #0 1 Matched #1 DPER Data Compare Match Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 DFER Data Compare Match Framing Error Flag 4 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 IDSEL ID Frame Select 6 6 read-write 0 Always compare data regardless of the MPB bit value #0 1 Only compare data when MPB bit = 1 (ID frame) #1 DCME Data Compare Match Enable 7 7 read-write 0 Disable address match function #0 1 Enable address match function #1 FCR FIFO Control Register 0x14 16 read-write 0xf800 0xffff FM FIFO Mode Select 0 0 read-write 0 Non-FIFO mode. Selects TDR/RDR or TDRHL/RDRHL for communication. #0 1 FIFO mode. Selects FTDRHL/FRDRHL for communication. #1 RFRST Receive FIFO Data Register Reset 1 1 read-write 0 Do not reset FRDRHL #0 1 Reset FRDRHL #1 TFRST Transmit FIFO Data Register Reset 2 2 read-write 0 Do not reset FTDRHL #0 1 Reset FTDRHL #1 DRES Receive Data Ready Error Select 3 3 read-write 0 Receive data full interrupt (SCIn_RXI) #0 1 Receive error interrupt (SCIn_ERI) #1 TTRG Transmit FIFO Data Trigger Number 4 7 read-write RTRG Receive FIFO Data Trigger Number 8 11 read-write RSTRG RTS Output Active Trigger Number Select 12 15 read-write FDR FIFO Data Count Register 0x16 16 read-only 0x0000 0xffff R Receive FIFO Data Count 0 4 read-only T Transmit FIFO Data Count 8 12 read-only LSR Line Status Register 0x18 16 read-only 0x0000 0xffff ORER Overrun Error Flag 0 0 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 FNUM Framing Error Count 2 6 read-only PNUM Parity Error Count 8 12 read-only CDR Compare Match Data Register 0x1A 16 read-write 0x0000 0xffff CMPD Compare Match Data 0 8 read-write SPTR Serial Port Register 0x1C 8 read-write 0x03 0xff RXDMON Serial Input Data Monitor 0 0 read-only SPB2DT Serial Port Break Data Select 1 1 read-write SPB2IO Serial Port Break I/O 2 2 read-write 0 Do not output value of SPB2DT bit on TXDn pin #0 1 Output value of SPB2DT bit on TXDn pin #1 RINV RXD invert bit 4 4 read-write 0 Received data from RXDn is not inverted and input. #0 1 Received data from RXDn is inverted and input. #1 TINV TXD invert bit 5 5 read-write 0 Transmit data is not inverted and output to TXDn. #0 1 Transmit data is inverted and output to TXDn. #1 ASEN Adjust receive sampling timing enable 6 6 read-write 0 Adjust sampling timing disable. #0 1 Adjust sampling timing enable. #1 ATEN Adjust transmit timing enable 7 7 read-write 0 Adjust transmit timing disable. #0 1 Adjust transmit timing enable. #1 ACTR Adjustment Communication Timing Register 0x1D 8 read-write 0x00 0xff AST Adjustment value for receive Sampling Timing 0 2 read-write AJD Adjustment Direction for receive sampling timing 3 3 read-write 0 The sampling timing is adjusted backward to the middle of bit. #0 1 The sampling timing is adjusted forward to the middle of bit. #1 ATT Adjustment value for Transmit timing 4 6 read-write AET Adjustment edge for transmit timing 7 7 read-write 0 Adjust the rising edge timing. #0 1 Adjust the falling edge timing. #1 SCI1 Serial Communication Interface 0 0x40118100 0x00 19 registers 0x20 20 registers SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x00 8 read-write 0x00 0xff CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 MP Multi-Processor Mode 2 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 STOP Stop Bit Length 3 3 read-write 0 1 stop bit #0 1 2 stop bits #1 PM Parity Mode 4 4 read-write 0 Even parity #0 1 Odd parity #1 PE Parity Enable 5 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 CHR Character Length 6 6 read-write 0 SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CM Communication Mode 7 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x00 8 read-write 0x00 0xff CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 BCP Base Clock Pulse 2 3 read-write PM Parity Mode 4 4 read-write 0 Even parity #0 1 Odd parity #1 PE Parity Enable 5 5 read-write BLK Block Transfer Mode 6 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 GM GSM Mode 7 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 BRR Bit Rate Register 0x01 8 read-write 0xff 0xff SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x02 8 read-write 0x00 0xff CKE Clock Enable 0 1 read-write 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. The SCKn pin is available for use as an I/O port based on the I/O port settings when the GPT clock is used. In clock synchronous mode, the SCKn pin functions as the clock input pin. true TEIE Transmit End Interrupt Enable 2 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 MPIE Multi-Processor Interrupt Enable 3 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 TE Transmit Enable 5 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 RIE Receive Interrupt Enable 6 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TIE Transmit Interrupt Enable 7 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x02 8 read-write 0x00 0xff CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 TEIE Transmit End Interrupt Enable 2 2 read-write MPIE Multi-Processor Interrupt Enable 3 3 read-write RE Receive Enable 4 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 TE Transmit Enable 5 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 RIE Receive Interrupt Enable 6 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TIE Transmit Interrupt Enable 7 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 TDR Transmit Data Register 0x03 8 read-write 0xff 0xff SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0, and MMR.MANEN = 0) 0x04 8 read-write 0x84 0xff MPBT Multi-Processor Bit Transfer 0 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 MPB Multi-Processor 1 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TEND Transmit End Flag 2 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 PER Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 FER Framing Error Flag 4 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 RDRF Receive Data Full Flag 6 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1, and MMR.MANEN = 0) SSR 0x04 8 read-write 0x84 0xff MPBT Multi-Processor Bit Transfer 0 0 read-write MPB Multi-Processor 1 1 read-only TEND Transmit End Flag 2 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 PER Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 ERS Error Signal Status Flag 4 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 ORER Overrun Error Flag 5 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 RDRF Receive Data Full Flag 6 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 RDR Receive Data Register 0x05 8 read-only 0x00 0xff SCMR Smart Card Mode Register 0x06 8 read-write 0xf2 0xff SMIF Smart Card Interface Mode Select 0 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SINV Transmitted/Received Data Invert 2 2 read-write 0 TDR contents are transmitted as they are. Received data is stored as received in the RDR register. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SDIR Transmitted/Received Data Transfer Direction 3 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 CHR1 Character Length 1 4 4 read-write 0 SMR.CHR = 0: Transmit/receive in 9-bit data length SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) SMR.CHR = 1: Transmit/receive in 7-bit data length #1 BCP2 Base Clock Pulse 2 7 7 read-write SEMR Serial Extended Mode Register 0x07 8 read-write 0x00 0xff ACS0 Asynchronous Mode Clock Source Select 0 0 read-write 0 External clock input #0 1 Logical AND of compare matches output from the internal GPT. These bit for the other SCI channels than SCIn (n = 1, 2) are reserved. #1 PADIS Preamble function Disable 1 1 read-write 0 Preamble output function is enabled #0 1 Preamble output function is disabled These bits for the other SCI channels than SCIn (n = 0, 3, 4, 9) are reserved. #1 BRME Bit Rate Modulation Enable 2 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period These bits for the other SCI channels than SCIn (n = 0, 3, 4, 9) are reserved. #1 ABCS Asynchronous Mode Base Clock Select 4 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 NFEN Digital Noise Filter Function Enable 5 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple I2C mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple I2C mode: Enable noise cancellation function for SCLn and SDAn input signals #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SNFR Noise Filter Setting Register 0x08 8 read-write 0x00 0xff NFCS Noise Filter Clock Select 0 2 read-write 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple I2C mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 8 with noise filter #100 Others Setting prohibited true SIMR1 IIC Mode Register 1 0x09 8 read-write 0x00 0xff IICM Simple IIC Mode Select 0 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 IICDL SDAn Delay Output Select 3 7 read-write 0x00 No output delay 0x00 Others (IICDL - 1) to (IICDL) cycles true SIMR2 IIC Mode Register 2 0x0A 8 read-write 0x00 0xff IICINTM IIC Interrupt Mode Select 0 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 IICCSC Clock Synchronization 1 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICACKT ACK Transmission Data 5 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 SIMR3 IIC Mode Register 3 0x0B 8 read-write 0x00 0xff IICSTAREQ Start Condition Generation 0 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICRSTAREQ Restart Condition Generation 1 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSTPREQ Stop Condition Generation 2 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSDAS SDAn Output Select 4 5 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSCLS SCLn Output Select 6 7 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 SISR IIC Status Register 0x0C 8 read-only 0x00 0xcb IICACKR ACK Reception Data Flag 0 0 read-only 0 ACK received #0 1 NACK received #1 SPMR SPI Mode Register 0x0D 8 read-write 0x00 0xff SSE SSn Pin Function Enable 0 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 CTSE CTS Enable 1 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MSS Master Slave Select 2 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 CTSPEN CTS external pin Enable 3 3 read-write 0 Alternate setting to use CTS and RTS functions as either one terminal #0 1 Dedicated setting for separately using CTS and RTS functions with 2 terminals These bits for the other SCI channels than SCIn (n = 0, 3, 4, 9) are reserved. #1 MFF Mode Fault Flag 4 4 read-write 0 No mode fault error #0 1 Mode fault error #1 CKPOL Clock Polarity Select 6 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CKPH Clock Phase Select 7 7 read-write 0 Do not delay clock #0 1 Delay clock #1 TDRHL Transmit Data Register for Non-Manchester mode (MMR.MANEN = 0) FTDRHL 0x0E 16 read-write 0xffff 0xffff TDAT Serial Transmit Data 0 8 read-write RDRHL Receive Data Register for Non-Manchester mode (MMR.MANEN = 0) FRDRHL 0x10 16 read-only 0x0000 0xffff RDAT Serial Receive Data 0 8 read-only MDDR Modulation Duty Register 0x12 8 read-write 0xff 0xff ESMER Extended Serial Module Enable Register 0x20 8 read-write 0x00 0xff ESME Extended Serial Mode Enable 0 0 read-write 0 The extended serial mode is disabled. #0 1 The extended serial mode is enabled. #1 CR0 Control Register 0 0x21 8 read-write 0x00 0xff SFSF Start Frame Status Flag 1 1 read-only 0 Start Frame detection function is disabled. #0 1 Start Frame detection function is enabled. #1 RXDSF RXDXn Input Status Flag 2 2 read-only 0 RXDXn input is enabled. #0 1 RXDXn input is disabled. #1 BRME Bit Rate Measurement Enable 3 3 read-write 0 Measurement of bit rate is disabled. #0 1 Measurement of bit rate is enabled. #1 CR1 Control Register 1 0x22 8 read-write 0x00 0xff BFE Break Field Enable 0 0 read-write 0 Break Field detection is disabled. #0 1 Break Field detection is enabled. #1 CF0RE Control Field 0 Reception Enable 1 1 read-write 0 Reception of Control Field 0 is disabled. #0 1 Reception of Control Field 0 is enabled. #1 CF1DS Control Field 1 Data Register Select 2 3 read-write 00 Selects comparison with the value in PCF1DR. #00 01 Selects comparison with the value in SCF1DR. #01 10 Selects comparison with the values in PCF1DR and SCF1DR. #10 11 Setting prohibited. #11 PIBE Priority Interrupt Bit Enable 4 4 read-write 0 The priority interrupt bit is disabled. #0 1 The priority interrupt bit is enabled. #1 PIBS Priority Interrupt Bit Select 5 7 read-write 000 0th bit of Control Field 1 #000 001 1st bit of Control Field 1 #001 010 2nd bit of Control Field 1 #010 011 3rd bit of Control Field 1 #011 100 4th bit of Control Field 1 #100 101 5th bit of Control Field 1 #101 110 6th bit of Control Field 1 #110 111 7th bit of Control Field 1 #111 CR2 Control Register 2 0x23 8 read-write 0x00 0xff DFCS RXDXn Signal Digital Filter Clock Select 0 2 read-write 000 Filter is disabled. #000 001 Filter clock is SCI base clock #001 010 Filter clock is PCLK/8 #010 011 Filter clock is PCLK/16 #011 100 Filter clock is PCLK/32 #100 101 Filter clock is PCLK/64 #101 110 Filter clock is PCLK/128 #110 111 Setting prohibited #111 BCCS Bus Collision Detection Clock Select 4 5 read-write 00 SCI base clock #00 01 SCI base clock frequency divided by 2 #01 10 SCI base clock frequency divided by 4 #10 11 Setting prohibited #11 RTS RXDXn Reception Sampling Timing Select 6 7 read-write 00 Rising edge of the 8th cycle of SCI base clock #00 01 Rising edge of the 10th cycle of SCI base clock #01 10 Rising edge of the 12th cycle of SCI base clock #10 11 Rising edge of the 14th cycle of SCI base clock #11 CR3 Control Register 3 0x24 8 read-write 0x00 0xff SDST Start Frame Detection Start 0 0 read-write 0 Detection of Start Frame is not performed. #0 1 Detection of Start Frame is performed. #1 PCR Port Control Register 0x25 8 read-write 0x00 0xff TXDXPS TXDXn Signal Polarity Select 0 0 read-write 0 The polarity of TXDXn signal is not inverted for output. #0 1 The polarity of TXDXn signal is inverted for output. #1 RXDXPS RXDXn Signal Polarity Select 1 1 read-write 0 The polarity of RXDXn signal is not inverted for input. #0 1 The polarity of RXDXn signal is inverted for input. #1 SHARPS TXDXn/RXDXn Pin Multiplexing Select 4 4 read-write 0 The TXDXn and RXDXn pins are independent. #0 1 The TXDXn and RXDXn signals are multiplexed on the same pin. #1 ICR Interrupt Control Register 0x26 8 read-write 0x00 0xff BFDIE Break Field Low Width Detected Interrupt Enable 0 0 read-write 0 Interrupts on detection of the low width for a Break Field are disabled. #0 1 Interrupts on detection of the low width for a Break Field are enabled. #1 CF0MIE Control Field 0 Match Detected Interrupt Enable 1 1 read-write 0 Interrupts on detection of a match with Control Field 0 are disabled. #0 1 Interrupts on detection of a match with Control Field 0 are enabled. #1 CF1MIE Control Field 1 Match Detected Interrupt Enable 2 2 read-write 0 Interrupts on detection of a match with Control Field 1 are disabled. #0 1 Interrupts on detection of a match with Control Field 1 are enabled. #1 PIBDIE Priority Interrupt Bit Detected Interrupt Enable 3 3 read-write 0 Interrupts on detection of the priority interrupt bit are disabled. #0 1 Interrupts on detection of the priority interrupt bit are enabled. #1 BCDIE Bus Collision Detected Interrupt Enable 4 4 read-write 0 Interrupts on detection of a bus collision are disabled. #0 1 Interrupts on detection of a bus collision are enabled. #1 AEDIE Valid Edge Detected Interrupt Enable 5 5 read-write 0 Interrupts on detection of a valid edge are disabled. #0 1 Interrupts on detection of a valid edge are enabled. #1 STR Status Register 0x27 8 read-only 0x00 0xff BFDF Break Field Low Width Detection Flag 0 0 read-only CF0MF Control Field 0 Match Flag 1 1 read-only CF1MF Control Field 1 Match Flag 2 2 read-only PIBDF Priority Interrupt Bit Detection Flag 3 3 read-only BCDF Bus Collision Detected Flag 4 4 read-only AEDF Valid Edge Detection Flag 5 5 read-only STCR Status Clear Register 0x28 8 read-write 0x00 0xff BFDCL BFDF Clear 0 0 read-write CF0MCL CF0MF Clear 1 1 read-write CF1MCL CF1MF Clear 2 2 read-write PIBDCL PIBDF Clear 3 3 read-write BCDCL BCDF Clear 4 4 read-write AEDCL AEDF Clear 5 5 read-write CF0DR Control Field 0 Data Register 0x29 8 read-write 0x00 0xff CF0CR Control Field 0 Compare Enable Register 0x2A 8 read-write 0x00 0xff CF0CE0 Control Field 0 Bit 0 Compare Enable 0 0 read-write 0 Comparison with bit 0 of Control Field 0 is disabled. #0 1 Comparison with bit 0 of Control Field 0 is enabled. #1 CF0CE1 Control Field 1 Bit 0 Compare Enable 1 1 read-write 0 Comparison with bit 1 of Control Field 0 is disabled. #0 1 Comparison with bit 1 of Control Field 0 is enabled. #1 CF0CE2 Control Field 2 Bit 0 Compare Enable 2 2 read-write 0 Comparison with bit 2 of Control Field 0 is disabled. #0 1 Comparison with bit 2 of Control Field 0 is enabled. #1 CF0CE3 Control Field 3 Bit 0 Compare Enable 3 3 read-write 0 Comparison with bit 3 of Control Field 0 is disabled. #0 1 Comparison with bit 3 of Control Field 0 is enabled. #1 CF0CE4 Control Field 4 Bit 0 Compare Enable 4 4 read-write 0 Comparison with bit 4 of Control Field 0 is disabled. #0 1 Comparison with bit 4 of Control Field 0 is enabled. #1 CF0CE5 Control Field 5 Bit 0 Compare Enable 5 5 read-write 0 Comparison with bit 5 of Control Field 0 is disabled. #0 1 Comparison with bit 5 of Control Field 0 is enabled. #1 CF0CE6 Control Field 6 Bit 0 Compare Enable 6 6 read-write 0 Comparison with bit 6 of Control Field 0 is disabled. #0 1 Comparison with bit 6 of Control Field 0 is enabled. #1 CF0CE7 Control Field 7 Bit 0 Compare Enable 7 7 read-write 0 Comparison with bit 7 of Control Field 0 is disabled. #0 1 Comparison with bit 7 of Control Field 0 is enabled. #1 CF0RR Control Field 0 Receive Data Register 0x2B 8 read-write 0x00 0xff PCF1DR Primary Control Field 1 Data Register 0x2C 8 read-write 0x00 0xff SCF1DR Secondary Control Field 1 Data Register 0x2D 8 read-write 0x00 0xff CF1CR Control Field 1 Compare Enable Register 0x2E 8 read-write 0x00 0xff CF1CE0 Control Field 1 Bit 0 Compare Enable 0 0 read-write 0 Comparison with bit 0 of Control Field 1 is disabled. #0 1 Comparison with bit 0 of Control Field 1 is enabled. #1 CF1CE1 Control Field 1 Bit 1 Compare Enable 1 1 read-write 0 Comparison with bit 1 of Control Field 1 is disabled. #0 1 Comparison with bit 1 of Control Field 1 is enabled. #1 CF1CE2 Control Field 1 Bit 2 Compare Enable 2 2 read-write 0 Comparison with bit 2 of Control Field 1 is disabled. #0 1 Comparison with bit 2 of Control Field 1 is enabled. #1 CF1CE3 Control Field 1 Bit 3 Compare Enable 3 3 read-write 0 Comparison with bit 3 of Control Field 1 is disabled. #0 1 Comparison with bit 3 of Control Field 1 is enabled. #1 CF1CE4 Control Field 1 Bit 4 Compare Enable 4 4 read-write 0 Comparison with bit 4 of Control Field 1 is disabled. #0 1 Comparison with bit 4 of Control Field 1 is enabled. #1 CF1CE5 Control Field 1 Bit 5 Compare Enable 5 5 read-write 0 Comparison with bit 5 of Control Field 1 is disabled. #0 1 Comparison with bit 5 of Control Field 1 is enabled. #1 CF1CE6 Control Field 1 Bit 6 Compare Enable 6 6 read-write 0 Comparison with bit 6 of Control Field 1 is disabled. #0 1 Comparison with bit 6 of Control Field 1 is enabled. #1 CF1CE7 Control Field 1 Bit 7 Compare Enable 7 7 read-write 0 Comparison with bit 7 of Control Field 1 is disabled. #0 1 Comparison with bit 7 of Control Field 1 is enabled. #1 CF1RR Control Field 1 Receive Data Register 0x2F 8 read-write 0x00 0xff TCR Timer Control Register 0x30 8 read-write 0x00 0xff TCST Timer Count Start 0 0 read-write 0 Stops the timer counting #0 1 Starts the timer counting #1 TMR Timer Mode Register 0x31 8 read-write 0x00 0xff TOMS Timer Operating Mode Select 0 1 read-write 00 Timer mode #00 01 Break Field low width determination mode #01 10 Break Field low width output mode #10 11 Setting prohibited #11 TWRC Counter Write Control 3 3 read-write 0 Data is written to the reload register and counter #0 1 Data is written to the reload register only #1 TCSS Timer Count Clock Source Select 4 6 read-write 000 PCLK #000 001 PCLK/2 #001 010 PCLK/4 #010 011 PCLK/8 #011 100 PCLK/16 #100 101 PCLK/32 #101 110 PCLK/64 #110 111 PCLK/128 #111 TPRE Timer Prescaler Register 0x32 8 read-write 0xff 0xff TCNT Timer Count Register 0x33 8 read-write 0xff 0xff SCI2 Serial Communication Interface 0 0x40118200 SCI3 Serial Communication Interface 0x40118300 0x00 30 registers 0x20 1 registers 0x22 4 registers SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x00 8 read-write 0x00 0xff CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 MP Multi-Processor Mode 2 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 STOP Stop Bit Length 3 3 read-write 0 1 stop bit #0 1 2 stop bits #1 PM Parity Mode 4 4 read-write 0 Even parity #0 1 Odd parity #1 PE Parity Enable 5 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 CHR Character Length 6 6 read-write 0 SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CM Communication Mode 7 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x00 8 read-write 0x00 0xff CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 BCP Base Clock Pulse 2 3 read-write PM Parity Mode 4 4 read-write 0 Even parity #0 1 Odd parity #1 PE Parity Enable 5 5 read-write BLK Block Transfer Mode 6 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 GM GSM Mode 7 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 BRR Bit Rate Register 0x01 8 read-write 0xff 0xff SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x02 8 read-write 0x00 0xff CKE Clock Enable 0 1 read-write 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. The SCKn pin is available for use as an I/O port based on the I/O port settings when the GPT clock is used. In clock synchronous mode, the SCKn pin functions as the clock input pin. true TEIE Transmit End Interrupt Enable 2 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 MPIE Multi-Processor Interrupt Enable 3 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 TE Transmit Enable 5 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 RIE Receive Interrupt Enable 6 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TIE Transmit Interrupt Enable 7 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x02 8 read-write 0x00 0xff CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 TEIE Transmit End Interrupt Enable 2 2 read-write MPIE Multi-Processor Interrupt Enable 3 3 read-write RE Receive Enable 4 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 TE Transmit Enable 5 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 RIE Receive Interrupt Enable 6 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TIE Transmit Interrupt Enable 7 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 TDR Transmit Data Register 0x03 8 read-write 0xff 0xff SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0, and MMR.MANEN = 0) 0x04 8 read-write 0x84 0xff MPBT Multi-Processor Bit Transfer 0 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 MPB Multi-Processor 1 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TEND Transmit End Flag 2 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 PER Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 FER Framing Error Flag 4 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 RDRF Receive Data Full Flag 6 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 SSR_FIFO Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0, FCR.FM = 1, and MMR.MANEN = 0) SSR 0x04 8 read-write 0x80 0xfd DR Receive Data Ready Flag 0 0 read-write 0 Receiving is in progress, or no received data remains in FRDRHL after successfully completed reception (receive FIFO empty) #0 1 Next receive data is not received for a period after normal receiving is complete, when the amount of data stored in the FIFO is equal to or less than the receive triggering number #1 TEND Transmit End Flag 2 2 read-write 0 A character is being transmitted #0 1 Character transfer is complete #1 PER Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 FER Framing Error Flag 4 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 RDF Receive FIFO Data Full Flag 6 6 read-write 0 The amount of receive data written in FRDRHL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRHL is equal to or greater than the specified receive triggering number #1 TDFE Transmit FIFO Data Empty Flag 7 7 read-write 0 The amount of transmit data written in FTDRHL exceeds the specified transmit triggering number #0 1 The amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering number #1 SSR_MANC Serial Status Register for Manchester Mode (SCMR.SMIF = 0, and MMR.MANEN = 1) SSR 0x04 8 read-write 0x84 0xff MER Manchester Error Flag 0 0 read-write 0 No Manchester error occurred #0 1 Manchester error has occurred #1 MPB Multi-Processor 1 1 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 TEND Transmit End Flag 2 2 read-only 0 A character is being transmitted #0 1 Character transfer has been completed. #1 PER Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 A parity error has occurred #1 FER Framing Error Flag 4 4 read-write 0 No framing error occurred #0 1 A framing error has occurred #1 ORER Overrun Error Flag 5 5 read-write 0 No overrun error occurred #0 1 An overrun error has occurred #1 RDRF Receive Data Full Flag 6 6 read-write 0 No received data is in RDR register #0 1 Received data is in RDR register #1 TDRE Transmit Data Empty Flag 7 7 read-write 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1, and MMR.MANEN = 0) SSR 0x04 8 read-write 0x84 0xff MPBT Multi-Processor Bit Transfer 0 0 read-write MPB Multi-Processor 1 1 read-only TEND Transmit End Flag 2 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 PER Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 ERS Error Signal Status Flag 4 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 ORER Overrun Error Flag 5 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 RDRF Receive Data Full Flag 6 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 RDR Receive Data Register 0x05 8 read-only 0x00 0xff SCMR Smart Card Mode Register 0x06 8 read-write 0xf2 0xff SMIF Smart Card Interface Mode Select 0 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SINV Transmitted/Received Data Invert 2 2 read-write 0 TDR contents are transmitted as they are. Received data is stored as received in the RDR register. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SDIR Transmitted/Received Data Transfer Direction 3 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 CHR1 Character Length 1 4 4 read-write 0 SMR.CHR = 0: Transmit/receive in 9-bit data length SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) SMR.CHR = 1: Transmit/receive in 7-bit data length #1 BCP2 Base Clock Pulse 2 7 7 read-write SEMR Serial Extended Mode Register 0x07 8 read-write 0x00 0xff ACS0 Asynchronous Mode Clock Source Select 0 0 read-write 0 External clock input #0 1 Logical AND of compare matches output from the internal GPT. These bit for the other SCI channels than SCIn (n = 1, 2) are reserved. #1 PADIS Preamble function Disable 1 1 read-write 0 Preamble output function is enabled #0 1 Preamble output function is disabled These bits for the other SCI channels than SCIn (n = 0, 3, 4, 9) are reserved. #1 BRME Bit Rate Modulation Enable 2 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period These bits for the other SCI channels than SCIn (n = 0, 3, 4, 9) are reserved. #1 ABCS Asynchronous Mode Base Clock Select 4 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 NFEN Digital Noise Filter Function Enable 5 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple I2C mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple I2C mode: Enable noise cancellation function for SCLn and SDAn input signals #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SNFR Noise Filter Setting Register 0x08 8 read-write 0x00 0xff NFCS Noise Filter Clock Select 0 2 read-write 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple I2C mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 8 with noise filter #100 Others Setting prohibited true SIMR1 IIC Mode Register 1 0x09 8 read-write 0x00 0xff IICM Simple IIC Mode Select 0 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 IICDL SDAn Delay Output Select 3 7 read-write 0x00 No output delay 0x00 Others (IICDL - 1) to (IICDL) cycles true SIMR2 IIC Mode Register 2 0x0A 8 read-write 0x00 0xff IICINTM IIC Interrupt Mode Select 0 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 IICCSC Clock Synchronization 1 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICACKT ACK Transmission Data 5 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 SIMR3 IIC Mode Register 3 0x0B 8 read-write 0x00 0xff IICSTAREQ Start Condition Generation 0 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICRSTAREQ Restart Condition Generation 1 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSTPREQ Stop Condition Generation 2 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSDAS SDAn Output Select 4 5 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSCLS SCLn Output Select 6 7 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 SISR IIC Status Register 0x0C 8 read-only 0x00 0xcb IICACKR ACK Reception Data Flag 0 0 read-only 0 ACK received #0 1 NACK received #1 SPMR SPI Mode Register 0x0D 8 read-write 0x00 0xff SSE SSn Pin Function Enable 0 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 CTSE CTS Enable 1 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MSS Master Slave Select 2 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 CTSPEN CTS external pin Enable 3 3 read-write 0 Alternate setting to use CTS and RTS functions as either one terminal #0 1 Dedicated setting for separately using CTS and RTS functions with 2 terminals These bits for the other SCI channels than SCIn (n = 0, 3, 4, 9) are reserved. #1 MFF Mode Fault Flag 4 4 read-write 0 No mode fault error #0 1 Mode fault error #1 CKPOL Clock Polarity Select 6 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CKPH Clock Phase Select 7 7 read-write 0 Do not delay clock #0 1 Delay clock #1 FTDRHL Transmit FIFO Data Register 0x0E 16 write-only 0xffff 0xffff TDAT Serial transmit data 0 8 write-only MPBT Multi-Processor Transfer Bit Flag 9 9 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TDRHL Transmit Data Register for Non-Manchester mode (MMR.MANEN = 0) FTDRHL 0x0E 16 read-write 0xffff 0xffff TDAT Serial Transmit Data 0 8 read-write TDRHL_MAN Transmit Data Register for Manchester mode (MMR.MANEN = 1) FTDRHL 0x0E 16 read-write 0xffff 0xffff TDAT Serial transmit data 0 8 read-write MPBT Multi-processor transfer bit flag 9 9 read-write 0 Data transmission cycles #0 1 ID transmission cycles #1 TSYNC Transmit SYNC data bit 12 12 read-write 0 The Start Bit is transmitted as DATA SYNC. #0 1 The Start Bit is transmitted as COMMAND SYNC. #1 FTDRH Transmit FIFO Data Register FTDRHL 0x0E 8 write-only 0xff 0xff MPBT Multi-Processor Transfer Bit Flag 1 1 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 FTDRL Transmit FIFO Data Register FTDRHL 0x0F 8 write-only 0xff 0xff TDAT Serial transmit data 0 7 write-only FRDRHL Receive FIFO Data Register 0x10 16 read-only 0x0000 0xffff RDAT Serial receive data 0 8 read-only MPB Multi-Processor Bit Flag 9 9 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 DR Receive Data Ready Flag 10 10 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 PER Parity Error Flag 11 11 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 FER Framing Error Flag 12 12 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 ORER Overrun Error Flag 13 13 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 RDF Receive FIFO Data Full Flag 14 14 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 RDRHL Receive Data Register for Non-Manchester mode (MMR.MANEN = 0) FRDRHL 0x10 16 read-only 0x0000 0xffff RDAT Serial Receive Data 0 8 read-only RDRHL_MAN Receive Data Register for Manchester mode (MMR.MANEN = 1) FRDRHL 0x10 16 read-only 0x0000 0xffff RDAT Serial receive data 0 8 read-only MPB Multi-processor bit 9 9 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 RSYNC Receive SYNC data bit 12 12 read-only 0 The received the Start Bit is DATA SYNC #0 1 The received the Start Bit is COMMAND SYNC #1 FRDRH Receive FIFO Data Register FRDRHL 0x10 8 read-only 0x00 0xff MPB Multi-Processor Bit Flag 1 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 DR Receive Data Ready Flag 2 2 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 PER Parity Error Flag 3 3 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 FER Framing Error Flag 4 4 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 ORER Overrun Error Flag 5 5 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 RDF Receive FIFO Data Full Flag 6 6 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRL Receive FIFO Data Register FRDRHL 0x11 8 read-only 0x00 0xff RDAT Serial receive data 0 7 read-only MDDR Modulation Duty Register 0x12 8 read-write 0xff 0xff DCCR Data Compare Match Control Register 0x13 8 read-write 0x40 0xff DCMF Data Compare Match Flag 0 0 read-write 0 Not matched #0 1 Matched #1 DPER Data Compare Match Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 DFER Data Compare Match Framing Error Flag 4 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 IDSEL ID Frame Select 6 6 read-write 0 Always compare data regardless of the MPB bit value #0 1 Only compare data when MPB bit = 1 (ID frame) #1 DCME Data Compare Match Enable 7 7 read-write 0 Disable address match function #0 1 Enable address match function #1 FCR FIFO Control Register 0x14 16 read-write 0xf800 0xffff FM FIFO Mode Select 0 0 read-write 0 Non-FIFO mode. Selects TDR/RDR or TDRHL/RDRHL for communication. #0 1 FIFO mode. Selects FTDRHL/FRDRHL for communication. #1 RFRST Receive FIFO Data Register Reset 1 1 read-write 0 Do not reset FRDRHL #0 1 Reset FRDRHL #1 TFRST Transmit FIFO Data Register Reset 2 2 read-write 0 Do not reset FTDRHL #0 1 Reset FTDRHL #1 DRES Receive Data Ready Error Select 3 3 read-write 0 Receive data full interrupt (SCIn_RXI) #0 1 Receive error interrupt (SCIn_ERI) #1 TTRG Transmit FIFO Data Trigger Number 4 7 read-write RTRG Receive FIFO Data Trigger Number 8 11 read-write RSTRG RTS Output Active Trigger Number Select 12 15 read-write FDR FIFO Data Count Register 0x16 16 read-only 0x0000 0xffff R Receive FIFO Data Count 0 4 read-only T Transmit FIFO Data Count 8 12 read-only LSR Line Status Register 0x18 16 read-only 0x0000 0xffff ORER Overrun Error Flag 0 0 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 FNUM Framing Error Count 2 6 read-only PNUM Parity Error Count 8 12 read-only CDR Compare Match Data Register 0x1A 16 read-write 0x0000 0xffff CMPD Compare Match Data 0 8 read-write SPTR Serial Port Register 0x1C 8 read-write 0x03 0xff RXDMON Serial Input Data Monitor 0 0 read-only SPB2DT Serial Port Break Data Select 1 1 read-write SPB2IO Serial Port Break I/O 2 2 read-write 0 Do not output value of SPB2DT bit on TXDn pin #0 1 Output value of SPB2DT bit on TXDn pin #1 RINV RXD invert bit 4 4 read-write 0 Received data from RXDn is not inverted and input. #0 1 Received data from RXDn is inverted and input. #1 TINV TXD invert bit 5 5 read-write 0 Transmit data is not inverted and output to TXDn. #0 1 Transmit data is inverted and output to TXDn. #1 ASEN Adjust receive sampling timing enable 6 6 read-write 0 Adjust sampling timing disable. #0 1 Adjust sampling timing enable. #1 ATEN Adjust transmit timing enable 7 7 read-write 0 Adjust transmit timing disable. #0 1 Adjust transmit timing enable. #1 ACTR Adjustment Communication Timing Register 0x1D 8 read-write 0x00 0xff AST Adjustment value for receive Sampling Timing 0 2 read-write AJD Adjustment Direction for receive sampling timing 3 3 read-write 0 The sampling timing is adjusted backward to the middle of bit. #0 1 The sampling timing is adjusted forward to the middle of bit. #1 ATT Adjustment value for Transmit timing 4 6 read-write AET Adjustment edge for transmit timing 7 7 read-write 0 Adjust the rising edge timing. #0 1 Adjust the falling edge timing. #1 MMR Manchester Mode Register 0x20 8 read-write 0x00 0xff RMPOL Polarity of Received Manchester Code 0 0 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 TMPOL Polarity of Transmit Manchester Code 1 1 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 ERTEN Manchester Edge Retiming Enable 2 2 read-write 0 Disables the receive retiming function #0 1 Enables the receive retiming function #1 SYNVAL SYNC value Setting 4 4 read-write 0 The start bit is added as a zero-to-one transition. #0 1 The start bit is added as a one-to-zero transition. #1 SYNSEL SYNC Select 5 5 read-write 0 The start bit pattern is set with the SYNVAL bit #0 1 The start bit pattern is set with the TSYNC bit. #1 SBSEL Start Bit Select 6 6 read-write 0 The start bit area consists of one bit. #0 1 The start bit area consists of three bits (COMMAND SYNC or DATA SYNC) #1 MANEN Manchester Mode Enable 7 7 read-write 0 Disables the Manchester mode #0 1 Enables the Manchester mode #1 TMPR Transmit Manchester Preface Setting Register 0x22 8 read-write 0x00 0xff TPLEN Transmit preface length 0 3 read-write 0x0 Disables the transmit preface generation 0x0 Others Transmit preface length (bit length) true TPPAT Transmit preface pattern 4 5 read-write 00 ALL ZERO #00 01 ZERO ONE #01 10 ONE ZERO #10 11 ALL ONE #11 RMPR Receive Manchester Preface Setting Register 0x23 8 read-write 0x00 0xff RPLEN Receive Preface Length 0 3 read-write 0 Disables the receive preface generation #0 Others Receive preface length (bit length) true RPPAT Receive Preface Pattern 4 5 read-write 00 ALL ZERO #00 01 ZERO ONE #01 10 ONE ZERO #10 11 ALL ONE #11 MESR Manchester Extended Error Status Register 0x24 8 read-write 0x00 0xff PFER Preface Error flag 0 0 read-write 0 No preface error detected #0 1 Preface error detected #1 SYER SYNC Error flag 1 1 read-write 0 No receive SYNC error detected #0 1 Receive SYNC error detected #1 SBER Start Bit Error flag 2 2 read-write 0 No start bit error detected #0 1 Start bit error detected #1 MECR Manchester Extended Error Control Register 0x25 8 read-write 0x00 0xff PFEREN Preface Error Enable 0 0 read-write 0 Does not handle a preface error as an interrupt source #0 1 Handles a preface error as an interrupt source #1 SYEREN Receive SYNC Error Enable 1 1 read-write 0 Does not handle a receive SYNC error as an interrupt source #0 1 Handles a receive SYNC error as an interrupt source #1 SBEREN Start Bit Error Enable 2 2 read-write 0 Does not handle a start bit error as an interrupt source #0 1 Handles a start bit error as an interrupt source #1 SCI4 Serial Communication Interface 0x40118400 SCI9 Serial Communication Interface 0x40118900 SPI0 Serial Peripheral Interface 0x4011A000 0x00 8 registers 0x08 26 registers SPCR SPI Control Register 0x00 8 read-write 0x00 0xff SPMS SPI Mode Select 0 0 read-write 0 Select SPI operation (4-wire method) #0 1 Select clock synchronous operation (3-wire method) #1 TXMD Communications Operating Mode Select 1 1 read-write 0 Select full-duplex synchronous serial communications #0 1 Select serial communications with transmit-only #1 MODFEN Mode Fault Error Detection Enable 2 2 read-write 0 Disable detection of mode fault errors #0 1 Enable detection of mode fault errors #1 MSTR SPI Master/Slave Mode Select 3 3 read-write 0 Select slave mode #0 1 Select master mode #1 SPEIE SPI Error Interrupt Enable 4 4 read-write 0 Disable SPI error interrupt requests #0 1 Enable SPI error interrupt requests #1 SPTIE Transmit Buffer Empty Interrupt Enable 5 5 read-write 0 Disable transmit buffer empty interrupt requests #0 1 Enable transmit buffer empty interrupt requests #1 SPE SPI Function Enable 6 6 read-write 0 Disable SPI function #0 1 Enable SPI function #1 SPRIE SPI Receive Buffer Full Interrupt Enable 7 7 read-write 0 Disable SPI receive buffer full interrupt requests #0 1 Enable SPI receive buffer full interrupt requests #1 SSLP SPI Slave Select Polarity Register 0x01 8 read-write 0x00 0xff SSL0P SSLn0 Signal Polarity Setting 0 0 read-write 0 Set SSLn0 signal to active-low #0 1 Set SSLn0 signal to active-high #1 SSL1P SSLn1 Signal Polarity Setting 1 1 read-write 0 Set SSLn1 signal to active-low #0 1 Set SSLn1 signal to active-high #1 SSL2P SSLn2 Signal Polarity Setting 2 2 read-write 0 Set SSLn2 signal to active-low #0 1 Set SSLn2 signal to active-high #1 SSL3P SSLn3 Signal Polarity Setting 3 3 read-write 0 Set SSLn3 signal to active-low #0 1 Set SSLn3 signal to active-high #1 SPPCR SPI Pin Control Register 0x02 8 read-write 0x00 0xff SPLP SPI Loopback 0 0 read-write 0 Normal mode #0 1 Loopback mode (receive data = inverted transmit data) #1 SPLP2 SPI Loopback 2 1 1 read-write 0 Normal mode #0 1 Loopback mode (receive data = transmit data) #1 MOIFV MOSI Idle Fixed Value 4 4 read-write 0 Set level output on MOSIn pin during MOSI idling to low #0 1 Set level output on MOSIn pin during MOSI idling to high #1 MOIFE MOSI Idle Value Fixing Enable 5 5 read-write 0 Set MOSI output value to equal final data from previous transfer #0 1 Set MOSI output value to equal value set in the MOIFV bit #1 SPSR SPI Status Register 0x03 8 read-write 0x20 0xff OVRF Overrun Error Flag 0 0 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 IDLNF SPI Idle Flag 1 1 read-only 0 SPI is in the idle state #0 1 SPI is in the transfer state #1 MODF Mode Fault Error Flag 2 2 read-write 0 No mode fault or underrun error occurred #0 1 Mode fault error or underrun error occurred #1 PERF Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 UDRF Underrun Error Flag 4 4 read-write 0 Mode fault error occurred (MODF = 1) #0 1 Underrun error occurred (MODF = 1) #1 SPTEF SPI Transmit Buffer Empty Flag 5 5 read-write 0 Data is in the transmit buffer #0 1 No data is in the transmit buffer #1 CENDF Communication End Flag 6 6 read-write 0 Not communicating or communicating #0 1 Communication completed #1 SPRF SPI Receive Buffer Full Flag 7 7 read-write 0 No valid data is in SPDR/SPDR_HA #0 1 Valid data is in SPDR/SPDR_HA #1 SPDR SPI Data Register 0x04 32 read-write 0x00000000 0xffffffff SPDR_HA SPI Data Register SPDR 0x04 16 read-write 0x0000 0xffff SPDR_BY SPI Data Register SPDR 0x04 8 read-write 0x00 0xff SPSCR SPI Sequence Control Register 0x08 8 read-write 0x00 0xff SPSLN SPI Sequence Length Specification 0 2 read-write 000 Sequence Length is 1 (Referenced SPCMDn, n = 0→0→…) #000 001 Sequence Length is 2 (Referenced SPCMDn, n = 0→1→0→…) #001 010 Sequence Length is 3 (Referenced SPCMDn, n = 0→1→2→0→…) #010 011 Sequence Length is 4 (Referenced SPCMDn, n = 0→1→2→3→0→…) #011 100 Sequence Length is 5 (Referenced SPCMDn, n = 0→1→2→3→4→0→…) #100 101 Sequence Length is 6 (Referenced SPCMDn, n = 0→1→2→3→4→5→0→…) #101 110 Sequence Length is 7 (Referenced SPCMDn, n = 0→1→2→3→4→5→6→0→…) #110 111 Sequence Length is 8 (Referenced SPCMDn, n = 0→1→2→3→4→5→6→7→0→…) #111 SPSSR SPI Sequence Status Register 0x09 8 read-only 0x00 0xff SPCP SPI Command Pointer 0 2 read-only 000 SPCMD0 #000 001 SPCMD1 #001 010 SPCMD2 #010 011 SPCMD3 #011 100 SPCMD4 #100 101 SPCMD5 #101 110 SPCMD6 #110 111 SPCMD7 #111 SPECM SPI Error Command 4 6 read-only 000 SPCMD0 #000 001 SPCMD1 #001 010 SPCMD2 #010 011 SPCMD3 #011 100 SPCMD4 #100 101 SPCMD5 #101 110 SPCMD6 #110 111 SPCMD7 #111 SPBR SPI Bit Rate Register 0x0A 8 read-write 0xff 0xff SPDCR SPI Data Control Register 0x0B 8 read-write 0x00 0xff SPFC Number of Frames Specification 0 1 read-write 00 1 frame #00 01 2 frames #01 10 3 frames #10 11 4 frames #11 SPRDTD SPI Receive/Transmit Data Select 4 4 read-write 0 Read SPDR/SPDR_HA values from receive buffer #0 1 Read SPDR/SPDR_HA values from transmit buffer, but only if the transmit buffer is empty #1 SPLW SPI Word Access/Halfword Access Specification 5 5 read-write 0 Set SPDR_HA to valid for halfword access #0 1 Set SPDR to valid for word access #1 SPBYT SPI Byte Access Specification 6 6 read-write 0 SPDR/SPDR_HA is accessed in halfword or word (SPLW is valid) #0 1 SPDR_BY is accessed in byte (SPLW is invalid) #1 SPCKD SPI Clock Delay Register 0x0C 8 read-write 0x00 0xff SCKDL RSPCK Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SSLND SPI Slave Select Negation Delay Register 0x0D 8 read-write 0x00 0xff SLNDL SSL Negation Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SPND SPI Next-Access Delay Register 0x0E 8 read-write 0x00 0xff SPNDL SPI Next-Access Delay Setting 0 2 read-write 000 1 RSPCK + 2 PCLKA #000 001 2 RSPCK + 2 PCLKA #001 010 3 RSPCK + 2 PCLKA #010 011 4 RSPCK + 2 PCLKA #011 100 5 RSPCK + 2 PCLKA #100 101 6 RSPCK + 2 PCLKA #101 110 7 RSPCK + 2 PCLKA #110 111 8 RSPCK + 2 PCLKA #111 SPCR2 SPI Control Register 2 0x0F 8 read-write 0x00 0xff SPPE Parity Enable 0 0 read-write 0 Do not add parity bit to transmit data and do not check parity bit of receive data #0 1 When SPCR.TXMD = 0: Add parity bit to transmit data and check parity bit of receive data When SPCR.TXMD = 1: Add parity bit to transmit data but do not check parity bit of receive data #1 SPOE Parity Mode 1 1 read-write 0 Select even parity for transmission and reception #0 1 Select odd parity for transmission and reception #1 SPIIE SPI Idle Interrupt Enable 2 2 read-write 0 Disable idle interrupt requests #0 1 Enable idle interrupt requests #1 PTE Parity Self-Testing 3 3 read-write 0 Disable self-diagnosis function of the parity circuit #0 1 Enable self-diagnosis function of the parity circuit #1 SCKASE RSPCK Auto-Stop Function Enable 4 4 read-write 0 Disable RSPCK auto-stop function #0 1 Enable RSPCK auto-stop function #1 8 0x02 0-7 SPCMD%s SPI Command Register %s 0x10 16 read-write 0x070d 0xffff CPHA RSPCK Phase Setting 0 0 read-write 0 Select data sampling on leading edge, data change on trailing edge #0 1 Select data change on leading edge, data sampling on trailing edge #1 CPOL RSPCK Polarity Setting 1 1 read-write 0 Set RSPCK low during idle #0 1 Set RSPCK high during idle #1 BRDV Bit Rate Division Setting 2 3 read-write 00 Base bit rate #00 01 Base bit rate divided by 2 #01 10 Base bit rate divided by 4 #10 11 Base bit rate divided by 8 #11 SSLA SSL Signal Assertion Setting 4 6 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 Others Setting prohibited true SSLKP SSL Signal Level Keeping 7 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning of the next access #1 SPB SPI Data Length Setting 8 11 read-write 0x0 20 bits 0x0 0x1 24 bits 0x1 0x2 32 bits 0x2 0x3 32 bits 0x3 0x8 9 bits 0x8 0x9 10 bits 0x9 0xA 11 bits 0xa 0xB 12 bits 0xb 0xC 13 bits 0xc 0xD 14 bits 0xd 0xE 15 bits 0xe 0xF 16 bits 0xf Others 8 bits true LSBF SPI LSB First 12 12 read-write 0 MSB-first #0 1 LSB-first #1 SPNDEN SPI Next-Access Delay Enable 13 13 read-write 0 Select next-access delay of 1 RSPCK + 2 PCLKA #0 1 Select next-access delay equal to the setting in the SPI Next-Access Delay Register (SPND) #1 SLNDEN SSL Negation Delay Setting Enable 14 14 read-write 0 Select SSL negation delay of 1 RSPCK #0 1 Select SSL negation delay equal to the setting in the SPI Slave Select Negation Delay Register (SSLND) #1 SCKDEN RSPCK Delay Setting Enable 15 15 read-write 0 Select RSPCK delay of 1 RSPCK #0 1 Select RSPCK delay equal to the setting in the SPI Clock Delay Register (SPCKD) #1 SPDCR2 SPI Data Control Register 2 0x20 8 read-write 0x00 0xff BYSW Byte Swap Operating Mode Select 0 0 read-write 0 Byte Swap OFF #0 1 Byte Swap ON #1 SINV Serial Data Invert Bit 1 1 read-write 0 Not invert serial data #0 1 Invert serial data #1 SPCR3 SPI Control Register 3 0x21 8 read-write 0x00 0xff ETXMD Extended Communication Mode Select 0 0 read-write 0 Full-duplex synchronous or transmit-only serial communications. [the SPCR.TXMD bit is enabled] #0 1 Receive-only serial communications in slave mode (SPCR.MSTR bit = 0). [the SPCR.TXMD bit is disabled] Setting is prohibited in master mode (SPCR.MSTR bit = 1). #1 BFDS Between Burst Transfer Frames Delay Select 1 1 read-write 0 Delay (RSPCK delay, SSL negation delay and next-access delay) between frames is inserted in burst transfer. #0 1 Delay between frames is not inserted in burst transfer. #1 CENDIE SPI Communication End Interrupt Enable 4 4 read-write 0 Communication end interrupt request is disabled. #0 1 Communication end interrupt request is enabled. #1 GPT320 General PWM 32-bit Timer 0 0x40169000 0x00 68 registers 0x48 36 registers 0x88 8 registers 0xB8 8 registers 0xD0 8 registers GTWP General PWM Timer Write-Protection Register 0x00 32 read-write 0x00000000 0xffffffff WP Register Write Disable 0 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 STRWP GTSTR.CSTRT Bit Write Disable 1 1 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 STPWP GTSTP.CSTOP Bit Write Disable 2 2 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CLRWP GTCLR.CCLR Bit Write Disable 3 3 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CMNWP Common Register Write Disabled 4 4 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 PRKEY GTWP Key Code 8 15 write-only GTSTR General PWM Timer Software Start Register 0x04 32 read-write 0x00000000 0xffffffff CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTSTP General PWM Timer Software Stop Register 0x08 32 read-write 0xffffffff 0xffffffff CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTCLR General PWM Timer Software Clear Register 0x0C 32 write-only 0x00000000 0xffffffff CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write 0x00000000 0xffffffff SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGCR GTETRGC Pin Rising Input Source Counter Start Enable 4 4 read-write 0 Counter start disabled on the rising edge of GTETRGC input #0 1 Counter start enabled on the rising edge of GTETRGC input #1 SSGTRGCF GTETRGC Pin Falling Input Source Counter Start Enable 5 5 read-write 0 Counter start disabled on the falling edge of GTETRGC input #0 1 Counter start enabled on the falling edge of GTETRGC input #1 SSGTRGDR GTETRGD Pin Rising Input Source Counter Start Enable 6 6 read-write 0 Counter start disabled on the rising edge of GTETRGD input #0 1 Counter start enabled on the rising edge of GTETRGD input #1 SSGTRGDF GTETRGD Pin Falling Input Source Counter Start Enable 7 7 read-write 0 Counter start disabled on the falling edge of GTETRGD input #0 1 Counter start enabled on the falling edge of GTETRGD input #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 20 read-write 0 Counter start disabled at the ELC_GPTE input #0 1 Counter start enabled at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 21 read-write 0 Counter start disabled at the ELC_GPTF input #0 1 Counter start enabled at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 22 read-write 0 Counter start disabled at the ELC_GPTG input #0 1 Counter start enabled at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 23 read-write 0 Counter start disabled at the ELC_GPTH input #0 1 Counter start enabled at the ELC_GPTH input #1 CSTRT Software Source Counter Start Enable 31 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write 0x00000000 0xffffffff PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGCR GTETRGC Pin Rising Input Source Counter Stop Enable 4 4 read-write 0 Counter stop disabled on the rising edge of GTETRGC input #0 1 Counter stop enabled on the rising edge of GTETRGC input #1 PSGTRGCF GTETRGC Pin Falling Input Source Counter Stop Enable 5 5 read-write 0 Counter stop disabled on the falling edge of GTETRGC input #0 1 Counter stop enabled on the falling edge of GTETRGC input #1 PSGTRGDR GTETRGD Pin Rising Input Source Counter Stop Enable 6 6 read-write 0 Counter stop disabled on the rising edge of GTETRGD input #0 1 Counter stop enabled on the rising edge of GTETRGD input #1 PSGTRGDF GTETRGD Pin Falling Input Source Counter Stop Enable 7 7 read-write 0 Counter stop disabled on the falling edge of GTETRGD input #0 1 Counter stop enabled on the falling edge of GTETRGD input #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 20 read-write 0 Counter stop disabled at the ELC_GPTE input #0 1 Counter stop enabled at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 21 read-write 0 Counter stop disabled at the ELC_GPTF input #0 1 Counter stop enabled at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 22 read-write 0 Counter stop disabled at the ELC_GPTG input #0 1 Counter stop enabled at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 23 read-write 0 Counter stop disabled at the ELC_GPTH input #0 1 Counter stop enabled at the ELC_GPTH input #1 CSTOP Software Source Counter Stop Enable 31 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write 0x00000000 0xffffffff CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGCR GTETRGC Pin Rising Input Source Counter Clear Enable 4 4 read-write 0 Disable counter clear on the rising edge of GTETRGC input #0 1 Enable counter clear on the rising edge of GTETRGC input #1 CSGTRGCF GTETRGC Pin Falling Input Source Counter Clear Enable 5 5 read-write 0 Counter clear disabled on the falling edge of GTETRGC input #0 1 Counter clear enabled on the falling edge of GTETRGC input #1 CSGTRGDR GTETRGD Pin Rising Input Source Counter Clear Enable 6 6 read-write 0 Disable counter clear on the rising edge of GTETRGD input #0 1 Enable counter clear on the rising edge of GTETRGD input #1 CSGTRGDF GTETRGD Pin Falling Input Source Counter Clear Enable 7 7 read-write 0 Counter clear disabled on the falling edge of GTETRGD input #0 1 Counter clear enabled on the falling edge of GTETRGD input #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 20 read-write 0 Counter clear disabled at the ELC_GPTE input #0 1 Counter clear enabled at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 21 read-write 0 Counter clear disabled at the ELC_GPTF input #0 1 Counter clear enabled at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 22 read-write 0 Counter clear disabled at the ELC_GPTG input #0 1 Counter clear enabled at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 23 read-write 0 Counter clear disabled at the ELC_GPTH input #0 1 Counter clear enabled at the ELC_GPTH input #1 CCLR Software Source Counter Clear Enable 31 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write 0x00000000 0xffffffff USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGCR GTETRGC Pin Rising Input Source Counter Count Up Enable 4 4 read-write 0 Counter count up disabled on the rising edge of GTETRGC input #0 1 Counter count up enabled on the rising edge of GTETRGC input #1 USGTRGCF GTETRGC Pin Falling Input Source Counter Count Up Enable 5 5 read-write 0 Counter count up disabled on the falling edge of GTETRGC input #0 1 Counter count up enabled on the falling edge of GTETRGC input #1 USGTRGDR GTETRGD Pin Rising Input Source Counter Count Up Enable 6 6 read-write 0 Counter count up disabled on the rising edge of GTETRGD input #0 1 Counter count up enabled on the rising edge of GTETRGD input #1 USGTRGDF GTETRGD Pin Falling Input Source Counter Count Up Enable 7 7 read-write 0 Counter count up disabled on the falling edge of GTETRGD input #0 1 Counter count up enabled on the falling edge of GTETRGD input #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 20 read-write 0 Counter count up disabled at the ELC_GPTE input #0 1 Counter count up enabled at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 21 read-write 0 Counter count up disabled at the ELC_GPTF input #0 1 Counter count up enabled at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 22 read-write 0 Counter count up disabled at the ELC_GPTG input #0 1 Counter count up enabled at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 23 read-write 0 Counter count up disabled at the ELC_GPTH input #0 1 Counter count up enabled at the ELC_GPTH input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write 0x00000000 0xffffffff DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGCR GTETRGC Pin Rising Input Source Counter Count Down Enable 4 4 read-write 0 Counter count down disabled on the rising edge of GTETRGC input #0 1 Counter count down enabled on the rising edge of GTETRGC input #1 DSGTRGCF GTETRGC Pin Falling Input Source Counter Count Down Enable 5 5 read-write 0 Counter count down disabled on the falling edge of GTETRGC input #0 1 Counter count down enabled on the falling edge of GTETRGC input #1 DSGTRGDR GTETRGD Pin Rising Input Source Counter Count Down Enable 6 6 read-write 0 Counter count down disabled on the rising edge of GTETRGD input #0 1 Counter count down enabled on the rising edge of GTETRGD input #1 DSGTRGDF GTETRGD Pin Falling Input Source Counter Count Down Enable 7 7 read-write 0 Counter count down disabled on the falling edge of GTETRGD input #0 1 Counter count down enabled on the falling edge of GTETRGD input #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 20 read-write 0 Counter count down disabled at the ELC_GPTE input #0 1 Counter count down enabled at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 21 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 22 read-write 0 Counter count down disabled at the ELC_GPTG input #0 1 Counter count down enabled at the ELC_GPTG input #1 DSELCH ELC_GPTF Event Source Counter Count Down Enable 23 23 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write 0x00000000 0xffffffff ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGCR GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable 4 4 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGC input #1 ASGTRGCF GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable 5 5 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGC input #1 ASGTRGDR GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable 6 6 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGD input #1 ASGTRGDF GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable 7 7 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGD input #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 20 read-write 0 GTCCRA input capture disabled at the ELC_GPTE input #0 1 GTCCRA input capture enabled at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 21 read-write 0 GTCCRA input capture disabled at the ELC_GPTF input #0 1 GTCCRA input capture enabled at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 22 read-write 0 GTCCRA input capture disabled at the ELC_GPTG input #0 1 GTCCRA input capture enabled at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 23 read-write 0 GTCCRA input capture disabled at the ELC_GPTH input #0 1 GTCCRA input capture enabled at the ELC_GPTH input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write 0x00000000 0xffffffff BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGCR GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable 4 4 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGC input #1 BSGTRGCF GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable 5 5 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGC input #1 BSGTRGDR GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable 6 6 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGD input #1 BSGTRGDF GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable 7 7 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGD input #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 20 read-write 0 GTCCRB input capture disabled at the ELC_GPTE input #0 1 GTCCRB input capture enabled at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 21 read-write 0 GTCCRB input capture disabled at the ELC_GPTF input #0 1 GTCCRB input capture enabled at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 22 read-write 0 GTCCRB input capture disabled at the ELC_GPTG input #0 1 GTCCRB input capture enabled at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 23 read-write 0 GTCCRB input capture disabled at the ELC_GPTH input #0 1 GTCCRB input capture enabled at the ELC_GPTH input #1 GTCR General PWM Timer Control Register 0x2C 32 read-write 0x00000000 0xffffffff CST Count Start 0 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 18 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 23 26 read-write 0x0 PCLKD/1 0x0 0x1 PCLKD/2 0x1 0x2 PCLKD/4 0x2 0x3 PCLKD/8 0x3 0x4 PCLKD/16 0x4 0x5 PCLKD/32 0x5 0x6 PCLKD/64 0x6 0x7 Setting prohibited 0x7 0x8 PCLKD/256 0x8 0x9 Setting prohibited 0x9 0xA PCLKD/1024 0xa 0xB Setting prohibited 0xb 0xC GTETRGA (Via the POEG) 0xc 0xD GTETRGB (Via the POEG) 0xd 0xE GTETRGC (Via the POEG) 0xe 0xF GTETRGD (Via the POEG) 0xf GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write 0x00000001 0xffffffff UD Count Direction Setting 0 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTY GTIOCnA Output Duty Setting 16 17 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 19 read-write 0 The function selected by the GTIOA[3:2] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting. #0 1 The function selected by the GTIOA[3:2] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting. #1 OBDTY GTIOCnB Output Duty Setting 24 25 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 27 read-write 0 The function selected by the GTIOB[3:2] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting. #0 1 The function selected by the GTIOB[3:2] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting. #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write 0x00000000 0xffffffff GTIOA GTIOCnA Pin Function Select 0 4 read-write OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OAE GTIOCnA Pin Output Enable 8 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OADF GTIOCnA Pin Disable Value Setting 9 10 read-write 00 None of the below options are specified #00 01 GTIOCnA pin is set to Hi-Z in response to controlling the output negation #01 10 GTIOCnA pin is set to 0 in response to controlling the output negation #10 11 GTIOCnA pin is set to 1 in response to controlling the output negation #11 NFAEN Noise Filter A Enable 13 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 15 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 GTIOB GTIOCnB Pin Function Select 16 20 read-write OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 OBE GTIOCnB Pin Output Enable 24 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBDF GTIOCnB Pin Disable Value Setting 25 26 read-write 00 None of the below options are specified #00 01 GTIOCnB pin is set to Hi-Z in response to controlling the output negation #01 10 GTIOCnB pin is set to 0 in response to controlling the output negation #10 11 GTIOCnB pin is set to 1 in response to controlling the output negation #11 NFBEN Noise Filter B Enable 29 29 read-write 0 The noise filter for the GTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSB Noise Filter B Sampling Clock Select 30 31 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write 0x00000000 0xffffffff GRP Output Disable Source Select 24 25 read-write 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 10 Group C output disable request is selected #10 11 Group D output disable request is selected #11 GRPABH Same Time Output Level High Disable Request Enable 29 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTST General PWM Timer Status Register 0x3C 32 read-write 0x00008000 0xffffffff TCFA Input Capture/Compare Match Flag A 0 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 ODF Output Disable Flag 24 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 OABHF Same Time Output Level High Flag 29 29 read-only 0 No simultaneous generation of 1 both for the GTIOCA and GTIOCB pins has occurred. #0 1 A simultaneous generation of 1 both for the GTIOCA and GTIOCB pins has occurred. #1 OABLF Same Time Output Level Low Flag 30 30 read-only 0 No simultaneous generation of 0 both for the GTIOCA and GTIOCB pins has occurred. #0 1 A simultaneous generation of 0 both for the GTIOCA and GTIOCB pins has occurred. #1 PCF Period Count Function Finish Flag 31 31 read-write 0 No period count function finish has occurred #0 1 A period count function finish has occurred #1 GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write 0x00000000 0xffffffff BD0 GTCCR Buffer Operation Disable 0 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 17 read-write 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) true CCRB GTCCRB Buffer Operation 18 19 read-write 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) true PR GTPR Buffer Operation 20 21 read-write 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 Others Setting prohibited true CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 22 write-only GTCNT General PWM Timer Counter 0x48 32 read-write 0x00000000 0xffffffff GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write 0xffffffff 0xffffffff GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write 0xffffffff 0xffffffff GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write 0xffffffff 0xffffffff GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write 0xffffffff 0xffffffff GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write 0xffffffff 0xffffffff GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write 0xffffffff 0xffffffff GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write 0xffffffff 0xffffffff GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write 0xffffffff 0xffffffff GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write 0x00000000 0xffffffff TDE Negative-Phase Waveform Setting 0 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU is used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write 0xffffffff 0xffffffff GTICLF General PWM Timer Inter Channel Logical Operation Function Setting Register 0xB8 32 read-write 0x00000000 0xffffffff ICLFA GTIOCnA Output Logical Operation Function Select 0 2 read-write 000 A (no delay) #000 001 NOT A (no delay) #001 010 C (1PCLKD delay) #010 011 NOT C (1PCLKD delay) #011 100 A AND C (1PCLKD delay) #100 101 A OR C (1PCLKD delay) #101 110 A EXOR C (1PCLKD delay) #110 111 A NOR C (1PCLKD delay) #111 ICLFSELC Inter Channel Signal C Select 4 9 read-write 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 Others Setting prohibited true ICLFB GTIOCnB Output Logical Operation Function Select 16 18 read-write 000 B (no delay) #000 001 NOT B (no delay) #001 010 D (1PCLKD delay) #010 011 NOT D (1PCLKD delay) #011 100 B AND D (1PCLKD delay) #100 101 B OR D (1PCLKDn delay) #101 110 B EXOR D (1PCLKD delay) #110 111 B NOR D (1PCLKD delay) #111 ICLFSELD Inter Channel Signal D Select 20 25 read-write 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 Others Setting prohibited true GTPC General PWM Timer Period Count Register 0xBC 32 read-write 0x00000000 0xffffffff PCEN Period Count Function Enable 0 0 read-write 0 Period count function is disabled #0 1 Period count function is enabled #1 ASTP Automatic Stop Function Enable 8 8 read-write 0 Automatic stop function is disabled #0 1 Automatic stop function is enabled #1 PCNT Period Counter 16 27 read-write GTSECSR General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register 0xD0 32 read-write 0x00000000 0xffffffff SECSEL0 Channel 0 Operation Enable Bit Simultaneous Control Channel Select 0 0 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL1 Channel 1 Operation Enable Bit Simultaneous Control Channel Select 1 1 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL2 Channel 2 Operation Enable Bit Simultaneous Control Channel Select 2 2 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL3 Channel 3 Operation Enable Bit Simultaneous Control Channel Select 3 3 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL4 Channel 4 Operation Enable Bit Simultaneous Control Channel Select 4 4 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL5 Channel 5 Operation Enable Bit Simultaneous Control Channel Select 5 5 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL6 Channel 6 Operation Enable Bit Simultaneous Control Channel Select 6 6 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL7 Channel 7 Operation Enable Bit Simultaneous Control Channel Select 7 7 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 GTSECR General PWM Timer Operation Enable Bit Simultaneous Control Register 0xD4 32 read-write 0x00000000 0xffffffff SBDCE GTCCR Register Buffer Operation Simultaneous Enable 0 0 read-write 0 Disable simultaneous enabling GTCCR buffer operations #0 1 Enable GTCCR register buffer operations simultaneously #1 SBDPE GTPR Register Buffer Operation Simultaneous Enable 1 1 read-write 0 Disable simultaneous enabling GTPR buffer operations #0 1 Enable GTPR register buffer operations simultaneously #1 SBDCD GTCCR Register Buffer Operation Simultaneous Disable 8 8 read-write 0 Disable simultaneous disabling GTCCR buffer operations #0 1 Disable GTCCR register buffer operations simultaneously #1 SBDPD GTPR Register Buffer Operation Simultaneous Disable 9 9 read-write 0 Disable simultaneous disabling GTPR buffer operations #0 1 Disable GTPR register buffer operations simultaneously #1 SPCE Period Count Function Simultaneous Enable 16 16 read-write 0 Disable simultaneous enabling period count function #0 1 Enable period count function simultaneously #1 SPCD Period Count Function Simultaneous Disable 24 24 read-write 0 Disable simultaneous disabling period count function #0 1 Disable period count function simultaneously #1 GPT321 General PWM 32-bit Timer 1 0x40169100 GPT322 General PWM 32-bit Timer 2 0x40169200 GPT323 General PWM 32-bit Timer 3 0x40169300 GPT164 General PWM 16-bit Timer 4 0x40169400 0x00 68 registers 0x48 36 registers 0x88 8 registers 0xB8 8 registers 0xD0 8 registers GTWP General PWM Timer Write-Protection Register 0x00 32 read-write 0x00000000 0xffffffff WP Register Write Disable 0 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 STRWP GTSTR.CSTRT Bit Write Disable 1 1 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 STPWP GTSTP.CSTOP Bit Write Disable 2 2 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CLRWP GTCLR.CCLR Bit Write Disable 3 3 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CMNWP Common Register Write Disabled 4 4 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 PRKEY GTWP Key Code 8 15 write-only GTSTR General PWM Timer Software Start Register 0x04 32 read-write 0x00000000 0xffffffff CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTSTP General PWM Timer Software Stop Register 0x08 32 read-write 0xffffffff 0xffffffff CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTCLR General PWM Timer Software Clear Register 0x0C 32 write-only 0x00000000 0xffffffff CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write 0x00000000 0xffffffff SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGCR GTETRGC Pin Rising Input Source Counter Start Enable 4 4 read-write 0 Counter start disabled on the rising edge of GTETRGC input #0 1 Counter start enabled on the rising edge of GTETRGC input #1 SSGTRGCF GTETRGC Pin Falling Input Source Counter Start Enable 5 5 read-write 0 Counter start disabled on the falling edge of GTETRGC input #0 1 Counter start enabled on the falling edge of GTETRGC input #1 SSGTRGDR GTETRGD Pin Rising Input Source Counter Start Enable 6 6 read-write 0 Counter start disabled on the rising edge of GTETRGD input #0 1 Counter start enabled on the rising edge of GTETRGD input #1 SSGTRGDF GTETRGD Pin Falling Input Source Counter Start Enable 7 7 read-write 0 Counter start disabled on the falling edge of GTETRGD input #0 1 Counter start enabled on the falling edge of GTETRGD input #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 20 read-write 0 Counter start disabled at the ELC_GPTE input #0 1 Counter start enabled at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 21 read-write 0 Counter start disabled at the ELC_GPTF input #0 1 Counter start enabled at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 22 read-write 0 Counter start disabled at the ELC_GPTG input #0 1 Counter start enabled at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 23 read-write 0 Counter start disabled at the ELC_GPTH input #0 1 Counter start enabled at the ELC_GPTH input #1 CSTRT Software Source Counter Start Enable 31 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write 0x00000000 0xffffffff PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGCR GTETRGC Pin Rising Input Source Counter Stop Enable 4 4 read-write 0 Counter stop disabled on the rising edge of GTETRGC input #0 1 Counter stop enabled on the rising edge of GTETRGC input #1 PSGTRGCF GTETRGC Pin Falling Input Source Counter Stop Enable 5 5 read-write 0 Counter stop disabled on the falling edge of GTETRGC input #0 1 Counter stop enabled on the falling edge of GTETRGC input #1 PSGTRGDR GTETRGD Pin Rising Input Source Counter Stop Enable 6 6 read-write 0 Counter stop disabled on the rising edge of GTETRGD input #0 1 Counter stop enabled on the rising edge of GTETRGD input #1 PSGTRGDF GTETRGD Pin Falling Input Source Counter Stop Enable 7 7 read-write 0 Counter stop disabled on the falling edge of GTETRGD input #0 1 Counter stop enabled on the falling edge of GTETRGD input #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 20 read-write 0 Counter stop disabled at the ELC_GPTE input #0 1 Counter stop enabled at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 21 read-write 0 Counter stop disabled at the ELC_GPTF input #0 1 Counter stop enabled at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 22 read-write 0 Counter stop disabled at the ELC_GPTG input #0 1 Counter stop enabled at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 23 read-write 0 Counter stop disabled at the ELC_GPTH input #0 1 Counter stop enabled at the ELC_GPTH input #1 CSTOP Software Source Counter Stop Enable 31 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write 0x00000000 0xffffffff CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGCR GTETRGC Pin Rising Input Source Counter Clear Enable 4 4 read-write 0 Disable counter clear on the rising edge of GTETRGC input #0 1 Enable counter clear on the rising edge of GTETRGC input #1 CSGTRGCF GTETRGC Pin Falling Input Source Counter Clear Enable 5 5 read-write 0 Counter clear disabled on the falling edge of GTETRGC input #0 1 Counter clear enabled on the falling edge of GTETRGC input #1 CSGTRGDR GTETRGD Pin Rising Input Source Counter Clear Enable 6 6 read-write 0 Disable counter clear on the rising edge of GTETRGD input #0 1 Enable counter clear on the rising edge of GTETRGD input #1 CSGTRGDF GTETRGD Pin Falling Input Source Counter Clear Enable 7 7 read-write 0 Counter clear disabled on the falling edge of GTETRGD input #0 1 Counter clear enabled on the falling edge of GTETRGD input #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 20 read-write 0 Counter clear disabled at the ELC_GPTE input #0 1 Counter clear enabled at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 21 read-write 0 Counter clear disabled at the ELC_GPTF input #0 1 Counter clear enabled at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 22 read-write 0 Counter clear disabled at the ELC_GPTG input #0 1 Counter clear enabled at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 23 read-write 0 Counter clear disabled at the ELC_GPTH input #0 1 Counter clear enabled at the ELC_GPTH input #1 CCLR Software Source Counter Clear Enable 31 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write 0x00000000 0xffffffff USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGCR GTETRGC Pin Rising Input Source Counter Count Up Enable 4 4 read-write 0 Counter count up disabled on the rising edge of GTETRGC input #0 1 Counter count up enabled on the rising edge of GTETRGC input #1 USGTRGCF GTETRGC Pin Falling Input Source Counter Count Up Enable 5 5 read-write 0 Counter count up disabled on the falling edge of GTETRGC input #0 1 Counter count up enabled on the falling edge of GTETRGC input #1 USGTRGDR GTETRGD Pin Rising Input Source Counter Count Up Enable 6 6 read-write 0 Counter count up disabled on the rising edge of GTETRGD input #0 1 Counter count up enabled on the rising edge of GTETRGD input #1 USGTRGDF GTETRGD Pin Falling Input Source Counter Count Up Enable 7 7 read-write 0 Counter count up disabled on the falling edge of GTETRGD input #0 1 Counter count up enabled on the falling edge of GTETRGD input #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 20 read-write 0 Counter count up disabled at the ELC_GPTE input #0 1 Counter count up enabled at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 21 read-write 0 Counter count up disabled at the ELC_GPTF input #0 1 Counter count up enabled at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 22 read-write 0 Counter count up disabled at the ELC_GPTG input #0 1 Counter count up enabled at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 23 read-write 0 Counter count up disabled at the ELC_GPTH input #0 1 Counter count up enabled at the ELC_GPTH input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write 0x00000000 0xffffffff DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGCR GTETRGC Pin Rising Input Source Counter Count Down Enable 4 4 read-write 0 Counter count down disabled on the rising edge of GTETRGC input #0 1 Counter count down enabled on the rising edge of GTETRGC input #1 DSGTRGCF GTETRGC Pin Falling Input Source Counter Count Down Enable 5 5 read-write 0 Counter count down disabled on the falling edge of GTETRGC input #0 1 Counter count down enabled on the falling edge of GTETRGC input #1 DSGTRGDR GTETRGD Pin Rising Input Source Counter Count Down Enable 6 6 read-write 0 Counter count down disabled on the rising edge of GTETRGD input #0 1 Counter count down enabled on the rising edge of GTETRGD input #1 DSGTRGDF GTETRGD Pin Falling Input Source Counter Count Down Enable 7 7 read-write 0 Counter count down disabled on the falling edge of GTETRGD input #0 1 Counter count down enabled on the falling edge of GTETRGD input #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 20 read-write 0 Counter count down disabled at the ELC_GPTE input #0 1 Counter count down enabled at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 21 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 22 read-write 0 Counter count down disabled at the ELC_GPTG input #0 1 Counter count down enabled at the ELC_GPTG input #1 DSELCH ELC_GPTF Event Source Counter Count Down Enable 23 23 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write 0x00000000 0xffffffff ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGCR GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable 4 4 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGC input #1 ASGTRGCF GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable 5 5 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGC input #1 ASGTRGDR GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable 6 6 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGD input #1 ASGTRGDF GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable 7 7 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGD input #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 20 read-write 0 GTCCRA input capture disabled at the ELC_GPTE input #0 1 GTCCRA input capture enabled at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 21 read-write 0 GTCCRA input capture disabled at the ELC_GPTF input #0 1 GTCCRA input capture enabled at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 22 read-write 0 GTCCRA input capture disabled at the ELC_GPTG input #0 1 GTCCRA input capture enabled at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 23 read-write 0 GTCCRA input capture disabled at the ELC_GPTH input #0 1 GTCCRA input capture enabled at the ELC_GPTH input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write 0x00000000 0xffffffff BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGCR GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable 4 4 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGC input #1 BSGTRGCF GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable 5 5 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGC input #1 BSGTRGDR GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable 6 6 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGD input #1 BSGTRGDF GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable 7 7 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGD input #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 20 read-write 0 GTCCRB input capture disabled at the ELC_GPTE input #0 1 GTCCRB input capture enabled at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 21 read-write 0 GTCCRB input capture disabled at the ELC_GPTF input #0 1 GTCCRB input capture enabled at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 22 read-write 0 GTCCRB input capture disabled at the ELC_GPTG input #0 1 GTCCRB input capture enabled at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 23 read-write 0 GTCCRB input capture disabled at the ELC_GPTH input #0 1 GTCCRB input capture enabled at the ELC_GPTH input #1 GTCR General PWM Timer Control Register 0x2C 32 read-write 0x00000000 0xffffffff CST Count Start 0 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 18 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 23 26 read-write 0x0 PCLKD/1 0x0 0x1 PCLKD/2 0x1 0x2 PCLKD/4 0x2 0x3 PCLKD/8 0x3 0x4 PCLKD/16 0x4 0x5 PCLKD/32 0x5 0x6 PCLKD/64 0x6 0x7 Setting prohibited 0x7 0x8 PCLKD/256 0x8 0x9 Setting prohibited 0x9 0xA PCLKD/1024 0xa 0xB Setting prohibited 0xb 0xC GTETRGA (Via the POEG) 0xc 0xD GTETRGB (Via the POEG) 0xd 0xE GTETRGC (Via the POEG) 0xe 0xF GTETRGD (Via the POEG) 0xf GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write 0x00000001 0xffffffff UD Count Direction Setting 0 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTY GTIOCnA Output Duty Setting 16 17 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 19 read-write 0 The function selected by the GTIOA[3:2] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting. #0 1 The function selected by the GTIOA[3:2] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting. #1 OBDTY GTIOCnB Output Duty Setting 24 25 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 27 read-write 0 The function selected by the GTIOB[3:2] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting. #0 1 The function selected by the GTIOB[3:2] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting. #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write 0x00000000 0xffffffff GTIOA GTIOCnA Pin Function Select 0 4 read-write OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OAE GTIOCnA Pin Output Enable 8 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OADF GTIOCnA Pin Disable Value Setting 9 10 read-write 00 None of the below options are specified #00 01 GTIOCnA pin is set to Hi-Z in response to controlling the output negation #01 10 GTIOCnA pin is set to 0 in response to controlling the output negation #10 11 GTIOCnA pin is set to 1 in response to controlling the output negation #11 NFAEN Noise Filter A Enable 13 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 15 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 GTIOB GTIOCnB Pin Function Select 16 20 read-write OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 OBE GTIOCnB Pin Output Enable 24 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBDF GTIOCnB Pin Disable Value Setting 25 26 read-write 00 None of the below options are specified #00 01 GTIOCnB pin is set to Hi-Z in response to controlling the output negation #01 10 GTIOCnB pin is set to 0 in response to controlling the output negation #10 11 GTIOCnB pin is set to 1 in response to controlling the output negation #11 NFBEN Noise Filter B Enable 29 29 read-write 0 The noise filter for the GTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSB Noise Filter B Sampling Clock Select 30 31 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write 0x00000000 0xffffffff GRP Output Disable Source Select 24 25 read-write 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 10 Group C output disable request is selected #10 11 Group D output disable request is selected #11 GRPABH Same Time Output Level High Disable Request Enable 29 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTST General PWM Timer Status Register 0x3C 32 read-write 0x00008000 0xffffffff TCFA Input Capture/Compare Match Flag A 0 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 ODF Output Disable Flag 24 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 OABHF Same Time Output Level High Flag 29 29 read-only 0 No simultaneous generation of 1 both for the GTIOCA and GTIOCB pins has occurred. #0 1 A simultaneous generation of 1 both for the GTIOCA and GTIOCB pins has occurred. #1 OABLF Same Time Output Level Low Flag 30 30 read-only 0 No simultaneous generation of 0 both for the GTIOCA and GTIOCB pins has occurred. #0 1 A simultaneous generation of 0 both for the GTIOCA and GTIOCB pins has occurred. #1 PCF Period Count Function Finish Flag 31 31 read-write 0 No period count function finish has occurred #0 1 A period count function finish has occurred #1 GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write 0x00000000 0xffffffff BD0 GTCCR Buffer Operation Disable 0 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 17 read-write 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) true CCRB GTCCRB Buffer Operation 18 19 read-write 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) true PR GTPR Buffer Operation 20 21 read-write 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 Others Setting prohibited true CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 22 write-only GTCNT General PWM Timer Counter 0x48 32 read-write 0x00000000 0xffffffff GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write 0x0000ffff 0xffffffff GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write 0x0000ffff 0xffffffff GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write 0x0000ffff 0xffffffff GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write 0x0000ffff 0xffffffff GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write 0x0000ffff 0xffffffff GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write 0x0000ffff 0xffffffff GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write 0x0000ffff 0xffffffff GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write 0x0000ffff 0xffffffff GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write 0x00000000 0xffffffff TDE Negative-Phase Waveform Setting 0 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU is used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write 0x0000ffff 0xffffffff GTICLF General PWM Timer Inter Channel Logical Operation Function Setting Register 0xB8 32 read-write 0x00000000 0xffffffff ICLFA GTIOCnA Output Logical Operation Function Select 0 2 read-write 000 A (no delay) #000 001 NOT A (no delay) #001 010 C (1PCLKD delay) #010 011 NOT C (1PCLKD delay) #011 100 A AND C (1PCLKD delay) #100 101 A OR C (1PCLKD delay) #101 110 A EXOR C (1PCLKD delay) #110 111 A NOR C (1PCLKD delay) #111 ICLFSELC Inter Channel Signal C Select 4 9 read-write 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 Others Setting prohibited true ICLFB GTIOCnB Output Logical Operation Function Select 16 18 read-write 000 B (no delay) #000 001 NOT B (no delay) #001 010 D (1PCLKD delay) #010 011 NOT D (1PCLKD delay) #011 100 B AND D (1PCLKD delay) #100 101 B OR D (1PCLKDn delay) #101 110 B EXOR D (1PCLKD delay) #110 111 B NOR D (1PCLKD delay) #111 ICLFSELD Inter Channel Signal D Select 20 25 read-write 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 Others Setting prohibited true GTPC General PWM Timer Period Count Register 0xBC 32 read-write 0x00000000 0xffffffff PCEN Period Count Function Enable 0 0 read-write 0 Period count function is disabled #0 1 Period count function is enabled #1 ASTP Automatic Stop Function Enable 8 8 read-write 0 Automatic stop function is disabled #0 1 Automatic stop function is enabled #1 PCNT Period Counter 16 27 read-write GTSECSR General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register 0xD0 32 read-write 0x00000000 0xffffffff SECSEL0 Channel 0 Operation Enable Bit Simultaneous Control Channel Select 0 0 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL1 Channel 1 Operation Enable Bit Simultaneous Control Channel Select 1 1 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL2 Channel 2 Operation Enable Bit Simultaneous Control Channel Select 2 2 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL3 Channel 3 Operation Enable Bit Simultaneous Control Channel Select 3 3 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL4 Channel 4 Operation Enable Bit Simultaneous Control Channel Select 4 4 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL5 Channel 5 Operation Enable Bit Simultaneous Control Channel Select 5 5 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL6 Channel 6 Operation Enable Bit Simultaneous Control Channel Select 6 6 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL7 Channel 7 Operation Enable Bit Simultaneous Control Channel Select 7 7 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 GTSECR General PWM Timer Operation Enable Bit Simultaneous Control Register 0xD4 32 read-write 0x00000000 0xffffffff SBDCE GTCCR Register Buffer Operation Simultaneous Enable 0 0 read-write 0 Disable simultaneous enabling GTCCR buffer operations #0 1 Enable GTCCR register buffer operations simultaneously #1 SBDPE GTPR Register Buffer Operation Simultaneous Enable 1 1 read-write 0 Disable simultaneous enabling GTPR buffer operations #0 1 Enable GTPR register buffer operations simultaneously #1 SBDCD GTCCR Register Buffer Operation Simultaneous Disable 8 8 read-write 0 Disable simultaneous disabling GTCCR buffer operations #0 1 Disable GTCCR register buffer operations simultaneously #1 SBDPD GTPR Register Buffer Operation Simultaneous Disable 9 9 read-write 0 Disable simultaneous disabling GTPR buffer operations #0 1 Disable GTPR register buffer operations simultaneously #1 SPCE Period Count Function Simultaneous Enable 16 16 read-write 0 Disable simultaneous enabling period count function #0 1 Enable period count function simultaneously #1 SPCD Period Count Function Simultaneous Disable 24 24 read-write 0 Disable simultaneous disabling period count function #0 1 Disable period count function simultaneously #1 GPT165 General PWM 16-bit Timer 5 0x40169500 GPT166 General PWM 16-bit Timer 6 0x40169600 GPT167 General PWM 16-bit Timer 7 0x40169700 GPT_OPS Output Phase Switching Controller 0x40169A00 0x00 4 registers OPSCR Output Phase Switching Control Register 0x00 32 read-write 0x00000000 0xffffffff UF 0 0 read-write VF 1 1 read-write WF 2 2 read-write U Input U-Phase Monitor 4 4 read-only V Input V-Phase Monitor 5 5 read-only W Input W-Phase Monitor 6 6 read-only EN Output Phase Enable 8 8 read-write 0 Do not output (Hi-Z external pin) #0 1 Output #1 FB External Feedback Signal Enable 16 16 read-write 0 Select the external input #0 1 Select the soft setting (OPSCR.UF, VF, WF) #1 P Positive-Phase Output (P) Control 17 17 read-write 0 Level signal output #0 1 PWM signal output #1 N Negative-Phase Output (N) Control 18 18 read-write 0 Level signal output #0 1 PWM signal output #1 INV Output Phase Invert Control 19 19 read-write 0 Positive logic (active-high) output #0 1 Negative logic (active-low) output #1 RV Output Phase Rotation Direction Reversal Control 20 20 read-write 0 Positive rotation #0 1 Reverse rotation #1 ALIGN Input Phase Alignment 21 21 read-write 0 Input phase aligned to PCLKD #0 1 Input phase aligned to the falling edge of PWM #1 GRP Output Disabled Source Selection 24 25 read-write GODF Group Output Disable Function 26 26 read-write 0 This bit function is ignored #0 1 Group disable clears the OPSCR.EN bit #1 NFEN External Input Noise Filter Enable 29 29 read-write 0 Do not use a noise filter on the external input #0 1 Use a noise filter on the external input #1 NFCS External Input Noise Filter Clock Selection 30 31 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 ADC120 12-bit A/D Converter 0x40170000 0x00 2 registers 0x04 9 registers 0x0E 36 registers 0x36 6 registers 0x40 2 registers 0x7A 1 registers 0x80 2 registers 0x84 4 registers 0x8C 1 registers 0x90 21 registers 0xA6 1 registers 0xA8 5 registers 0xB0 33 registers 0xD2 1 registers 0xDD 12 registers 0xEB 3 registers ADCSR A/D Control Register 0x000 16 read-write 0x0000 0xffff DBLANS Double Trigger Channel Select 0 4 read-write GBADIE Group B Scan End Interrupt and ELC Event Enable 6 6 read-write 0 Disable ADC120_GBADI interrupt generation on group B scan completion. #0 1 Enable ADC120_GBADI interrupt generation on group B scan completion. #1 DBLE Double Trigger Mode Select 7 7 read-write 0 Deselect double-trigger mode. #0 1 Select double-trigger mode. #1 EXTRG Trigger Select 8 8 read-write 0 Start A/D conversion by the synchronous trigger (ELC). #0 1 Start A/D conversion by the asynchronous trigger (ADTRG0). #1 TRGE Trigger Start Enable 9 9 read-write 0 Disable A/D conversion to be started by the synchronous or asynchronous trigger #0 1 Enable A/D conversion to be started by the synchronous or asynchronous trigger #1 ADCS Scan Mode Select 13 14 read-write 00 Single scan mode #00 01 Group scan mode #01 10 Continuous scan mode #10 11 Setting prohibited #11 ADST A/D Conversion Start 15 15 read-write 0 Stop A/D conversion process. #0 1 Start A/D conversion process. #1 ADANSA0 A/D Channel Select Register A0 0x004 16 read-write 0x0000 0xffff ANSA00 A/D Conversion Channels Select 0 0 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA01 A/D Conversion Channels Select 1 1 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA02 A/D Conversion Channels Select 2 2 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA03 A/D Conversion Channels Select 3 3 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA04 A/D Conversion Channels Select 4 4 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA05 A/D Conversion Channels Select 5 5 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA06 A/D Conversion Channels Select 6 6 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA07 A/D Conversion Channels Select 7 7 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA08 A/D Conversion Channels Select 8 8 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA09 A/D Conversion Channels Select 9 9 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA10 A/D Conversion Channels Select 10 10 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA11 A/D Conversion Channels Select 11 11 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA12 A/D Conversion Channels Select 12 12 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA13 A/D Conversion Channels Select 13 13 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA14 A/D Conversion Channels Select 14 14 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA15 A/D Conversion Channels Select 15 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADANSA1 A/D Channel Select Register A1 0x006 16 read-write 0x0000 0xffff ANSA16 A/D Conversion Channels Select 0 0 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA17 A/D Conversion Channels Select 1 1 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA18 A/D Conversion Channels Select 2 2 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA19 A/D Conversion Channels Select 3 3 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA20 A/D Conversion Channels Select 4 4 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA21 A/D Conversion Channels Select 5 5 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA22 A/D Conversion Channels Select 6 6 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA23 A/D Conversion Channels Select 7 7 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA24 A/D Conversion Channels Select 8 8 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA25 A/D Conversion Channels Select 9 9 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA26 A/D Conversion Channels Select 10 10 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA27 A/D Conversion Channels Select 11 11 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA28 A/D Conversion Channels Select 12 12 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA29 A/D Conversion Channels Select 13 13 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA30 A/D Conversion Channels Select 14 14 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA31 A/D Conversion Channels Select 15 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADADS0 A/D-Converted Value Addition/Average Channel Select Register 0 0x008 16 read-write 0x0000 0xffff ADS00 A/D-Converted Value Addition/Average Channel Select 0 0 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS01 A/D-Converted Value Addition/Average Channel Select 1 1 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS02 A/D-Converted Value Addition/Average Channel Select 2 2 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS03 A/D-Converted Value Addition/Average Channel Select 3 3 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS04 A/D-Converted Value Addition/Average Channel Select 4 4 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS05 A/D-Converted Value Addition/Average Channel Select 5 5 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS06 A/D-Converted Value Addition/Average Channel Select 6 6 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS07 A/D-Converted Value Addition/Average Channel Select 7 7 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS08 A/D-Converted Value Addition/Average Channel Select 8 8 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS09 A/D-Converted Value Addition/Average Channel Select 9 9 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS10 A/D-Converted Value Addition/Average Channel Select 10 10 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS11 A/D-Converted Value Addition/Average Channel Select 11 11 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS12 A/D-Converted Value Addition/Average Channel Select 12 12 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS13 A/D-Converted Value Addition/Average Channel Select 13 13 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS14 A/D-Converted Value Addition/Average Channel Select 14 14 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS15 A/D-Converted Value Addition/Average Channel Select 15 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADADS1 A/D-Converted Value Addition/Average Channel Select Register 1 0x00A 16 read-write 0x0000 0xffff ADS16 A/D-Converted Value Addition/Average Channel Select 0 0 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS17 A/D-Converted Value Addition/Average Channel Select 1 1 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS18 A/D-Converted Value Addition/Average Channel Select 2 2 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS19 A/D-Converted Value Addition/Average Channel Select 3 3 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS20 A/D-Converted Value Addition/Average Channel Select 4 4 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS21 A/D-Converted Value Addition/Average Channel Select 5 5 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS22 A/D-Converted Value Addition/Average Channel Select 6 6 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS23 A/D-Converted Value Addition/Average Channel Select 7 7 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS24 A/D-Converted Value Addition/Average Channel Select 8 8 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS25 A/D-Converted Value Addition/Average Channel Select 9 9 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS26 A/D-Converted Value Addition/Average Channel Select 10 10 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS27 A/D-Converted Value Addition/Average Channel Select 11 11 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS28 A/D-Converted Value Addition/Average Channel Select 12 12 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS29 A/D-Converted Value Addition/Average Channel Select 13 13 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS30 A/D-Converted Value Addition/Average Channel Select 14 14 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS31 A/D-Converted Value Addition/Average Channel Select 15 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADADC A/D-Converted Value Addition/Average Count Select Register 0x00C 8 read-write 0x00 0xff ADC Addition/Average Count Select 0 2 read-write 000 1-time conversion (no addition, same as normal conversion) #000 001 2-time conversion (1 addition) #001 010 3-time conversion (2 additions)Setting prohibited #010 011 4-time conversion (3 additions) #011 101 16-time conversion (15 additions) #101 Others Setting prohibited true AVEE Average Mode Select 7 7 read-write 0 Enable addition mode #0 1 Enable average mode #1 ADCER A/D Control Extended Register 0x00E 16 read-write 0x0000 0xffff ADPRC 1 2 read-write 00 12-bit accuracy #00 01 10-bit accuracy #01 10 8-bit accuracy #10 11 Setting prohibited #11 ACE A/D Data Register Automatic Clearing Enable 5 5 read-write 0 Disable automatic clearing #0 1 Enable automatic clearing #1 DIAGVAL Self-Diagnosis Conversion Voltage Select 8 9 read-write 00 Setting prohibited when self-diagnosis is enabled #00 01 0 volts #01 10 Reference voltage × 1/2 #10 11 Reference voltage #11 DIAGLD Self-Diagnosis Mode Select 10 10 read-write 0 Select rotation mode for self-diagnosis voltage #0 1 Select mixed mode for self-diagnosis voltage #1 DIAGM Self-Diagnosis Enable 11 11 read-write 0 Disable ADC12 self-diagnosis #0 1 Enable ADC12 self-diagnosis #1 ADRFMT A/D Data Register Format Select 15 15 read-write 0 Select right-justified for the A/D data register format #0 1 Select left-justified for the A/D data register format #1 ADSTRGR A/D Conversion Start Trigger Select Register 0x010 16 read-write 0x0000 0xffff TRSB A/D Conversion Start Trigger Select for Group B 0 5 read-write TRSA A/D Conversion Start Trigger Select 8 13 read-write ADEXICR A/D Conversion Extended Input Control Registers 0x012 16 read-write 0x0000 0xffff TSSAD Temperature Sensor Output A/D-Converted Value Addition/Average Mode Select 0 0 read-write 0 Do not select addition/average mode for temperature sensor output. #0 1 Select addition/average mode for temperature sensor output. #1 OCSAD Internal Reference Voltage A/D-Converted Value Addition/Average Mode Select 1 1 read-write 0 Do not select addition/average mode for internal reference voltage. #0 1 Select addition/average mode for internal reference voltage. #1 TSSA Temperature Sensor Output A/D Conversion Select 8 8 read-write 0 Disable A/D conversion of temperature sensor output #0 1 Enable A/D conversion of temperature sensor output #1 OCSA Internal Reference Voltage A/D Conversion Select 9 9 read-write 0 Disable A/D conversion of internal reference voltage #0 1 Enable A/D conversion of internal reference voltage #1 TSSB Temperature Sensor Output A/D Conversion Select for Group B 10 10 read-write 0 Disable A/D conversion of temperature sensor output #0 1 Enable A/D conversion of temperature sensor output #1 OCSB Internal Reference Voltage A/D Conversion Select for Group B 11 11 read-write 0 Disable A/D conversion of internal reference voltage #0 1 Enable A/D conversion of internal reference voltage #1 ADANSB0 A/D Channel Select Register B0 0x014 16 read-write 0x0000 0xffff ANSB00 A/D Conversion Channels Select 0 0 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB01 A/D Conversion Channels Select 1 1 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB02 A/D Conversion Channels Select 2 2 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB03 A/D Conversion Channels Select 3 3 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB04 A/D Conversion Channels Select 4 4 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB05 A/D Conversion Channels Select 5 5 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB06 A/D Conversion Channels Select 6 6 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB07 A/D Conversion Channels Select 7 7 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB08 A/D Conversion Channels Select 8 8 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB09 A/D Conversion Channels Select 9 9 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB10 A/D Conversion Channels Select 10 10 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB11 A/D Conversion Channels Select 11 11 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB12 A/D Conversion Channels Select 12 12 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB13 A/D Conversion Channels Select 13 13 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB14 A/D Conversion Channels Select 14 14 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB15 A/D Conversion Channels Select 15 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADANSB1 A/D Channel Select Register B1 0x016 16 read-write 0x0000 0xffff ANSB16 A/D Conversion Channels Select 0 0 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB17 A/D Conversion Channels Select 1 1 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB18 A/D Conversion Channels Select 2 2 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB19 A/D Conversion Channels Select 3 3 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB20 A/D Conversion Channels Select 4 4 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB21 A/D Conversion Channels Select 5 5 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB22 A/D Conversion Channels Select 6 6 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB23 A/D Conversion Channels Select 7 7 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB24 A/D Conversion Channels Select 8 8 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB25 A/D Conversion Channels Select 9 9 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB26 A/D Conversion Channels Select 10 10 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB27 A/D Conversion Channels Select 11 11 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB28 A/D Conversion Channels Select 12 12 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB29 A/D Conversion Channels Select 13 13 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB30 A/D Conversion Channels Select 14 14 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB31 A/D Conversion Channels Select 15 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADDBLDR A/D Data Duplexing Register 0x018 16 read-only 0x0000 0xffff ADDBLDR Converted Value 15 to 0 0 15 read-only ADTSDR A/D Temperature Sensor Data Register 0x01A 16 read-only 0x0000 0xffff ADTSDR Converted Value 15 to 0 0 15 read-only ADOCDR A/D Internal Reference Voltage Data Register 0x01C 16 read-only 0x0000 0xffff ADOCDR Converted Value 15 to 0 0 15 read-only ADRD A/D Self-Diagnosis Data Register 0x01E 16 read-only 0x0000 0xffff AD Converted Value 11 to 0 0 11 read-only DIAGST Self-Diagnosis Status 14 15 read-only 00 Self-diagnosis not executed after power-on. #00 01 Self-diagnosis was executed using the 0 V voltage. #01 10 Self-diagnosis was executed using the reference voltage × 1/2. #10 11 Self-diagnosis was executed using the reference voltage . #11 9 0x2 0-8 ADDR%s A/D Data Registers %s 0x020 16 read-only 0x0000 0xffff ADDR Converted Value 15 to 0 0 15 read-only 3 0x2 11-13 ADDR%s A/D Data Registers %s 0x036 16 read-only 0x0000 0xffff ADDR Converted Value 15 to 0 0 15 read-only ADDR16 A/D Data Registers 16 0x040 16 read-only 0x0000 0xffff ADDR Converted Value 15 to 0 0 15 read-only ADDISCR A/D Disconnection Detection Control Register 0x07A 8 read-write 0x00 0xff ADNDIS Disconnection Detection Assist Setting 0 3 read-write 0x0 The disconnection detection assist function is disabled 0x0 0x1 Setting prohibited 0x1 Others The number of states for the discharge or precharge period. true PCHG Precharge/discharge select 4 4 read-write 0 Discharge #0 1 Precharge #1 ADGSPCR A/D Group Scan Priority Control Register 0x080 16 read-write 0x0000 0xffff PGS Group Priority Operation Setting 0 0 read-write 0 Operate without group priority control. #0 1 Operate with group priority control. #1 GBRSCN Lower-Priority Group Restart Setting 1 1 read-write 0 Disable rescanning of the group that was stopped in group priority operation #0 1 Enable rescanning of the group that was stopped in group priority operation. #1 LGRRS Enabled only when PGS = 1 and GBRSCN = 1. 14 14 read-write 0 Start rescanning from the first channel for scanning #0 1 Start rescanning from the channel for which A/D conversion is not completed. #1 GBRP Single Scan Continuous Start 15 15 read-write 0 Single scan is not continuously activated. #0 1 Single scan for the group with the lower-priority is continuously activated. #1 ADDBLDRA A/D Data Duplexing Register A 0x084 16 read-only 0x0000 0xffff ADDBLDR Converted Value 15 to 0 0 15 read-only ADDBLDRB A/D Data Duplexing Register B 0x086 16 read-only 0x0000 0xffff ADDBLDR Converted Value 15 to 0 0 15 read-only ADWINMON A/D Compare Function Window A/B Status Monitor Register 0x08C 8 read-only 0x00 0xff MONCOMB Combination Result Monitor 0 0 read-only 0 Window A/B composite conditions are not met. #0 1 Window A/B composite conditions are met. #1 MONCMPA Comparison Result Monitor A 4 4 read-only 0 Window A comparison conditions are not met. #0 1 Window A comparison conditions are met. #1 MONCMPB Comparison Result Monitor B 5 5 read-only 0 Window B comparison conditions are not met. #0 1 Window B comparison conditions are met. #1 ADCMPCR A/D Compare Function Control Register 0x090 16 read-write 0x0000 0xffff CMPAB Window A/B Composite Conditions Setting 0 1 read-write 00 Output ADC120_WCMPM when window A OR window B comparison conditions are met. Otherwise, output ADC120_WCMPUM. #00 01 Output ADC120_WCMPM when window A EXOR window B comparison conditions are met. Otherwise, output ADC120_WCMPUM. #01 10 Output ADC120_WCMPM when window A AND window B comparison conditions are met. Otherwise, output ADC120_WCMPUM. #10 11 Setting prohibited. #11 CMPBE Compare Window B Operation Enable 9 9 read-write 0 Disable compare window B operation. Disable ADC120_WCMPM and ADC120_WCMPUM outputs. #0 1 Enable compare window B operation. #1 CMPAE Compare Window A Operation Enable 11 11 read-write 0 Disable compare window A operation. Disable ADC120_WCMPM and ADC120_WCMPUM outputs. #0 1 Enable compare window A operation. #1 CMPBIE Compare B Interrupt Enable 13 13 read-write 0 Disable ADC120_CMPBI interrupt when comparison conditions (window B) are met. #0 1 Enable ADC120_CMPBI interrupt when comparison conditions (window B) are met. #1 WCMPE Window Function Setting 14 14 read-write 0 Disable window function Window A and window B operate as a comparator to compare the single value on the lower side with the A/D conversion result. #0 1 Enable window function Window A and window B operate as a comparator to compare the two values on the upper and lower sides with the A/D conversion result. #1 CMPAIE Compare A Interrupt Enable 15 15 read-write 0 Disable ADC120_CMPAI interrupt when comparison conditions (window A) are met. #0 1 Enable ADC120_CMPAI interrupt when comparison conditions (window A) are met. #1 ADCMPANSER A/D Compare Function Window A Extended Input Select Register 0x092 8 read-write 0x00 0xff CMPTSA Temperature Sensor Output Compare Select 0 0 read-write 0 Exclude the temperature sensor output from the compare Window A target range. #0 1 Include the temperature sensor output in the compare Window A target range. #1 CMPOCA Internal Reference Voltage Compare Select 1 1 read-write 0 Exclude the internal reference voltage from the compare Window A target range. #0 1 Include the internal reference voltage in the compare Window A target range. #1 ADCMPLER A/D Compare Function Window A Extended Input Comparison Condition Setting Register 0x093 8 read-write 0x00 0xff CMPLTSA Compare Window A Temperature Sensor Output Comparison Condition Select 0 0 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0) : ADCMPDR0 value > A/D-converted valueCompare Window A Temperature Sensor Output Comparison Condition Select When window function is enabled (ADCMPCR.WCMPE = 1) : Compare Window A Temperature Sensor Output Comparison ConditionA/D-converted value < ADCMPDR0 value, or A/D-converted value > ADCMPDR1 value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0) : ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1) : ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLOCA Compare Window A Internal Reference Voltage Comparison Condition Select 1 1 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0) : ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or A/D-converted value > ADCMPDR1 value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 ADCMPANSR0 A/D Compare Function Window A Channel Select Register 0 0x094 16 read-write 0x0000 0xffff CMPCHA00 Compare Window A Channel Select 0 0 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA01 Compare Window A Channel Select 1 1 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA02 Compare Window A Channel Select 2 2 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA03 Compare Window A Channel Select 3 3 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA04 Compare Window A Channel Select 4 4 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA05 Compare Window A Channel Select 5 5 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA06 Compare Window A Channel Select 6 6 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA07 Compare Window A Channel Select 7 7 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA08 Compare Window A Channel Select 8 8 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA09 Compare Window A Channel Select 9 9 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA10 Compare Window A Channel Select 10 10 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA11 Compare Window A Channel Select 11 11 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA12 Compare Window A Channel Select 12 12 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA13 Compare Window A Channel Select 13 13 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA14 Compare Window A Channel Select 14 14 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA15 Compare Window A Channel Select 15 15 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 ADCMPANSR1 A/D Compare Function Window A Channel Select Register 1 0x096 16 read-write 0x0000 0xffff CMPCHA16 Compare Window A Channel Select 0 0 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA17 Compare Window A Channel Select 1 1 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA18 Compare Window A Channel Select 2 2 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA19 Compare Window A Channel Select 3 3 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA20 Compare Window A Channel Select 4 4 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA21 Compare Window A Channel Select 5 5 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA22 Compare Window A Channel Select 6 6 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA23 Compare Window A Channel Select 7 7 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA24 Compare Window A Channel Select 8 8 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA25 Compare Window A Channel Select 9 9 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA26 Compare Window A Channel Select 10 10 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA27 Compare Window A Channel Select 11 11 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA28 Compare Window A Channel Select 12 12 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA29 Compare Window A Channel Select 13 13 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA30 Compare Window A Channel Select 14 14 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA31 Compare Window A Channel Select 15 15 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 ADCMPLR0 A/D Compare Function Window A Comparison Condition Setting Register 0 0x098 16 read-write 0x0000 0xffff CMPLCHA00 Compare Window A Comparison Condition Select 0 0 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA01 Compare Window A Comparison Condition Select 1 1 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA02 Compare Window A Comparison Condition Select 2 2 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA03 Compare Window A Comparison Condition Select 3 3 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA04 Compare Window A Comparison Condition Select 4 4 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA05 Compare Window A Comparison Condition Select 5 5 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA06 Compare Window A Comparison Condition Select 6 6 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA07 Compare Window A Comparison Condition Select 7 7 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA08 Compare Window A Comparison Condition Select 8 8 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA09 Compare Window A Comparison Condition Select 9 9 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA10 Compare Window A Comparison Condition Select 10 10 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA11 Compare Window A Comparison Condition Select 11 11 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA12 Compare Window A Comparison Condition Select 12 12 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA13 Compare Window A Comparison Condition Select 13 13 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA14 Compare Window A Comparison Condition Select 14 14 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA15 Compare Window A Comparison Condition Select 15 15 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 ADCMPLR1 A/D Compare Function Window A Comparison Condition Setting Register 1 0x09A 16 read-write 0x0000 0xffff CMPLCHA16 Compare Window A Comparison Condition Select 0 0 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA17 Compare Window A Comparison Condition Select 1 1 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA18 Compare Window A Comparison Condition Select 2 2 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA19 Compare Window A Comparison Condition Select 3 3 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA20 Compare Window A Comparison Condition Select 4 4 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA21 Compare Window A Comparison Condition Select 5 5 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA22 Compare Window A Comparison Condition Select 6 6 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA23 Compare Window A Comparison Condition Select 7 7 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA24 Compare Window A Comparison Condition Select 8 8 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA25 Compare Window A Comparison Condition Select 9 9 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA26 Compare Window A Comparison Condition Select 10 10 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA27 Compare Window A Comparison Condition Select 11 11 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA28 Compare Window A Comparison Condition Select 12 12 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA29 Compare Window A Comparison Condition Select 13 13 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA30 Compare Window A Comparison Condition Select 14 14 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA31 Compare Window A Comparison Condition Select 15 15 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 2 0x2 0-1 ADCMPDR%s A/D Compare Function Window A Lower-Side/Upper-Side Level Setting Register 0x09C 16 read-write 0x0000 0xffff ADCMPSR0 A/D Compare Function Window A Channel Status Register 0 0x0A0 16 read-write 0x0000 0xffff CMPSTCHA00 Compare Window A Flag 0 0 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA01 Compare Window A Flag 1 1 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA02 Compare Window A Flag 2 2 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA03 Compare Window A Flag 3 3 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA04 Compare Window A Flag 4 4 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA05 Compare Window A Flag 5 5 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA06 Compare Window A Flag 6 6 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA07 Compare Window A Flag 7 7 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA08 Compare Window A Flag 8 8 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA09 Compare Window A Flag 9 9 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA10 Compare Window A Flag 10 10 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA11 Compare Window A Flag 11 11 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA12 Compare Window A Flag 12 12 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA13 Compare Window A Flag 13 13 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA14 Compare Window A Flag 14 14 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA15 Compare Window A Flag 15 15 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPSR1 A/D Compare Function Window A Channel Status Register1 0x0A2 16 read-write 0x0000 0xffff CMPSTCHA16 Compare Window A Flag 0 0 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA17 Compare Window A Flag 1 1 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA18 Compare Window A Flag 2 2 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA19 Compare Window A Flag 3 3 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA20 Compare Window A Flag 4 4 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA21 Compare Window A Flag 5 5 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA22 Compare Window A Flag 6 6 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA23 Compare Window A Flag 7 7 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA24 Compare Window A Flag 8 8 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA25 Compare Window A Flag 9 9 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA26 Compare Window A Flag 10 10 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA27 Compare Window A Flag 11 11 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA28 Compare Window A Flag 12 12 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA29 Compare Window A Flag 13 13 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA30 Compare Window A Flag 14 14 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA31 Compare Window A Flag 15 15 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPSER A/D Compare Function Window A Extended Input Channel Status Register 0x0A4 8 read-write 0x00 0xff CMPSTTSA Compare Window A Temperature Sensor Output Compare Flag 0 0 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTOCA Compare Window A Internal Reference Voltage Compare Flag 1 1 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPBNSR A/D Compare Function Window B Channel Select Register 0x0A6 8 read-write 0x00 0xff CMPCHB Compare Window B Channel Select 0 5 read-write CMPLB Compare Window B Comparison Condition Setting 7 7 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADWINLLB value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADWINLLB value, or ADWINULB value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADWINLLB value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADWINLLB value < A/D-converted value < ADWINULB value #1 ADWINLLB A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register 0x0A8 16 read-write 0x0000 0xffff ADWINULB A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register 0x0AA 16 read-write 0x0000 0xffff ADCMPBSR A/D Compare Function Window B Status Register 0x0AC 8 read-write 0x00 0xff CMPSTB Compare Window B Flag 0 0 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 16 0x2 0-15 ADBUF%s A/D Data Buffer Registers %s 0x0B0 16 read-only 0x0000 0xffff ADBUF Converted Value 15 to 0 0 15 read-only ADBUFEN A/D Data Buffer Enable Register 0x0D0 8 read-write 0x00 0xff BUFEN Data Buffer Enable 0 0 read-write 0 The data buffer is not used. #0 1 The data buffer is used. #1 ADBUFPTR A/D Data Buffer Pointer Register 0x0D2 8 read-write 0x00 0xff BUFPTR Data Buffer Pointer 0 3 read-write PTROVF Pointer Overflow Flag 4 4 read-write 0 The data buffer pointer has not overflowed. #0 1 The data buffer pointer has overflowed. #1 ADSSTRL A/D Sampling State Register 0x0DD 8 read-write 0x0b 0xff SST Sampling Time Setting 0 7 read-write ADSSTRT A/D Sampling State Register 0x0DE 8 read-write 0x0b 0xff SST Sampling Time Setting 0 7 read-write ADSSTRO A/D Sampling State Register 0x0DF 8 read-write 0x0b 0xff SST Sampling Time Setting 0 7 read-write 9 0x1 0-8 ADSSTR%s A/D Sampling State Register 0x0E0 8 read-write 0x0b 0xff SST Sampling Time Setting 0 7 read-write 3 0x1 11-13 ADSSTR%s A/D Sampling State Register 0x0EB 8 read-write 0x0b 0xff SST Sampling Time Setting 0 7 read-write DAC12 12-bit D/A converter 0x40171000 0x00 7 registers 0x08 1 registers 0x1C 1 registers 0x10C0 1 registers 2 0x02 0-1 DADR%s D/A Data Register %s 0x00 16 read-write 0x0000 0xffff DACR D/A Control Register 0x04 8 read-write 0x1f 0xff DAE D/A Enable 5 5 read-write 0 Control D/A conversion of channels 0 and 1 individually #0 1 Control D/A conversion of channels 0 and 1 collectively #1 DAOE0 D/A Output Enable 0 6 6 read-write 0 Disable analog output of channel 0 (DA0) #0 1 Enable D/A conversion of channel 0 (DA0) #1 DAOE1 D/A Output Enable 1 7 7 read-write 0 Disable analog output of channel 1 (DA1) #0 1 Enable D/A conversion of channel 1 (DA1) #1 DADPR DADRn Format Select Register 0x05 8 read-write 0x00 0xff DPSEL DADRn Format Select 7 7 read-write 0 Right-justified format #0 1 Left-justified format #1 DAADSCR D/A A/D Synchronous Start Control Register 0x06 8 read-write 0x00 0xff DAADST D/A A/D Synchronous Conversion 7 7 read-write 0 Do not synchronize DAC12 with ADC12 operation (disable interference reduction between D/A and A/D conversion). #0 1 Synchronize DAC12 with ADC12 operation (enable interference reduction between D/A and A/D conversion). #1 DAAMPCR D/A Output Amplifier Control Register 0x08 8 read-write 0x00 0xff DAAMP0 Amplifier Control 0 6 6 read-write 0 Do not use channel 0 output amplifier #0 1 Use channel 0 output amplifier #1 DAAMP1 Amplifier Control 1 7 7 read-write 0 Do not use channel 1 output amplifier #0 1 Use channel 1 output amplifier #1 DAASWCR D/A Amplifier Stabilization Wait Control Register 0x1C 8 read-write 0x00 0xff DAASW0 D/A Amplifier Stabilization Wait 0 6 6 read-write 0 Amplifier stabilization wait off (output) for channel 0 #0 1 Amplifier stabilization wait on (high-Z) for channel 0 #1 DAASW1 D/A Amplifier Stabilization Wait 1 7 7 read-write 0 Amplifier stabilization wait off (output) for channel 1 #0 1 Amplifier stabilization wait on (high-Z) for channel 1 #1 DAADUSR D/A A/D Synchronous Unit Select Register 0x10C0 8 read-write 0x00 0xff AMADSEL0 A/D Unit 0 Select 0 0 read-write 0 Do not select unit 0 #0 1 Select unit 0 #1 TSD Temperature Sensor Calibration Data 0x407FB000 0x17C 4 registers TSCDR Temperature Sensor Calibration Data Register 0x017C 32 read-only 0x00000000 0xffff0000 TSCDR Temperature Sensor Calibration Data 0 15 read-only FLAD Data Flash 0x407FC000 0x40 1 registers FCKMHZ Data Flash Access Frequency Register 0x40 8 read-write 0x3c 0xff FCKMHZ Data Flash Access Frequency Register 0 7 read-write FACI Flash/CPU Interface 0x407FE000 0x10 1 registers 0x14 1 registers 0x18 1 registers 0x30 8 registers 0x44 2 registers 0x78 2 registers 0x7C 2 registers 0x80 6 registers 0x8C 2 registers 0xA0 2 registers 0xD0 1 registers 0xD4 1 registers 0xD8 10 registers 0xE4 2 registers 0xE8 2 registers FASTAT Flash Access Status Register 0x10 8 read-write 0x00 0xff DFAE Data Flash Memory Access Violation Flag 3 3 read-write 0 No data flash memory access violation has occurred #0 1 A data flash memory access violation has occurred. #1 CMDLK Command Lock Flag 4 4 read-only 0 The flash sequencer is not in the command-locked state #0 1 The flash sequencer is in the command-locked state. #1 CFAE Code Flash Memory Access Violation Flag 7 7 read-write 0 No code flash memory access violation has occurred #0 1 A code flash memory access violation has occurred. #1 FAEINT Flash Access Error Interrupt Enable Register 0x14 8 read-write 0x98 0xff DFAEIE Data Flash Memory Access Violation Interrupt Enable 3 3 read-write 0 Generation of an FIFERR interrupt request is disabled when FASTAT.DFAE is set to 1 #0 1 Generation of an FIFERR interrupt request is enabled when FASTAT.DFAE is set to 1. #1 CMDLKIE Command Lock Interrupt Enable 4 4 read-write 0 Generation of an FIFERR interrupt request is disabled when FASTAT.CMDLK is set to 1 #0 1 Generation of an FIFERR interrupt request is enabled when FASTAT.CMDLK is set to 1. #1 CFAEIE Code Flash Memory Access Violation Interrupt Enable 7 7 read-write 0 Generation of an FIFERR interrupt request is disabled when FASTAT.CFAE is set to 1 #0 1 Generation of an FIFERR interrupt request is enabled when FASTAT.CFAE is set to 1. #1 FRDYIE Flash Ready Interrupt Enable Register 0x18 8 read-write 0x00 0xff FRDYIE Flash Ready Interrupt Enable 0 0 read-write 0 Generation of an FRDY interrupt request is disabled #0 1 Generation of an FRDY interrupt request is enabled. #1 FSADDR FACI Command Start Address Register 0x30 32 read-write 0x00000000 0xffffffff FSADDR Start Address for FACI Command Processing 0 31 read-write FEADDR FACI Command End Address Register 0x34 32 read-write 0x00000000 0xffffffff FEADDR End Address for FACI Command Processing 0 31 read-write FMEPROT Flash P/E Mode Entry Protection Register 0x44 16 read-write 0x0001 0xffff CEPROT Code Flash P/E Mode Entry Protection 0 0 read-write 0 FENTRYC bit is not protected #0 1 FENTRYC bit is protected. #1 KEY Key Code 8 15 write-only FBPROT0 Flash Block Protection Register 0x78 16 read-write 0x0000 0xffff BPCN0 Block Protection for Non-secure Cancel 0 0 read-write 0 Block protection is enabled #0 1 Block protection is disabled. #1 KEY Key Code 8 15 write-only FBPROT1 Flash Block Protection for Secure Register 0x7C 16 read-write 0x0000 0xffff BPCN1 Block Protection for Secure Cancel 0 0 read-write 0 Block protection is enabled #0 1 Block protection is disabled. #1 KEY Key Code 8 15 write-only FSTATR Flash Status Register 0x80 32 read-write 0x00008000 0xffffffff FLWEERR Flash Write/Erase Protect Error Flag 6 6 read-only 0 An error has not occurred #0 1 An error has occurred. #1 PRGSPD Programming Suspend Status Flag 8 8 read-only 0 The flash sequencer is not in the programming suspension processing state or programming suspended state #0 1 The flash sequencer is in the programming suspension processing state or programming suspended state. #1 ERSSPD Erasure Suspend Status Flag 9 9 read-only 0 The flash sequencer is not in the erasure suspension processing state or the erasure suspended state #0 1 The flash sequencer is in the erasure suspension processing state or the erasure suspended state. #1 DBFULL Data Buffer Full Flag 10 10 read-only 0 The data buffer is empty #0 1 The data buffer is full. #1 SUSRDY Suspend Ready Flag 11 11 read-only 0 The flash sequencer cannot receive P/E suspend commands #0 1 The flash sequencer can receive P/E suspend commands. #1 PRGERR Programming Error Flag 12 12 read-only 0 Programming has completed successfully #0 1 An error has occurred during programming. #1 ERSERR Erasure Error Flag 13 13 read-only 0 Erasure has completed successfully #0 1 An error has occurred during erasure. #1 ILGLERR Illegal Command Error Flag 14 14 read-only 0 The flash sequencer has not detected an illegal FACI command or illegal flash memory access #0 1 The flash sequencer has detected an illegal FACI command or illegal flash memory access. #1 FRDY Flash Ready Flag 15 15 read-only 0 Program, Block Erase, Multi Block Erase, P/E suspend, P/E resume, Forced Stop, Blank Check, or Configuration set command processing is in progress #0 1 None of the above is in progress. #1 OTERR Other Error 20 20 read-only 0 A status clear or forced stop command processing is complete #0 1 An error has occurred. #1 SECERR Security Error 21 21 read-only 0 A status clear or forced stop command processing is complete #0 1 An error has occurred. #1 FESETERR FENTRY Setting Error 22 22 read-only 0 A status clear or forced stop command processing is complete #0 1 An error has occurred. #1 ILGCOMERR Illegal Command Error 23 23 read-only 0 A status clear or forced stop command processing is complete #0 1 An error has occurred. #1 FENTRYR Flash P/E Mode Entry Register 0x84 16 read-write 0x0000 0xffff FENTRYC Code Flash P/E Mode Entry 0 0 read-write 0 Code flash is in read mode #0 1 Code flash is in P/E mode. #1 FENTRYD Data Flash P/E Mode Entry 7 7 read-write 0 Data flash is in read mode #0 1 Data flash is in P/E mode. #1 KEY Key Code 8 15 write-only FSUINITR Flash Sequencer Setup Initialization Register 0x8C 16 read-write 0x0000 0xffff SUINIT Set-Up Initialization 0 0 read-write 0 The FSADDR, FEADDR, FBPROT0, FBPROT1, FENTRYR, FBCCNT, and FCPSR flash sequencer setup registers keep their current values #0 1 The FSADDR, FEADDR, FBPROT0, FBRPOT1, FENTRYR, FBCCNT, and FCPSR flash sequencer setup registers are initialized. #1 KEY Key Code 8 15 write-only FCMDR FACI Command Register 0xA0 16 read-only 0x0000 0xffff PCMDR Pre-command Flag 0 7 read-only CMDR Command Flag 8 15 read-only FBCCNT Blank Check Control Register 0xD0 8 read-write 0x00 0xff BCDIR Blank Check Direction 0 0 read-write 0 Blank checking is executed from the lower addresses to the higher addresses (incremental mode) #0 1 Blank checking is executed from the higher addresses to the lower addresses (decremental mode). #1 FBCSTAT Blank Check Status Register 0xD4 8 read-write 0x00 0xff BCST Blank Check Status Flag 0 0 read-only 0 The target area is in the non-programmed state, that is, the area has been erased but has not yet been reprogrammed #0 1 The target area has been programmed with 0s or 1s. #1 FPSADDR Data Flash Programming Start Address Register 0xD8 32 read-write 0x00000000 0xffffffff PSADR Programmed Area Start Address 0 16 read-only FSUASMON Flash Startup Area Select Monitor Register 0xDC 32 read-only 0x00000000 0x7fff7fff FSPR Protection Programming Flag to set Boot Flag and Startup Area Control 15 15 read-only 0 Protected state #0 1 Non-protected state. #1 BTFLG Flag of Startup Area Select for Boot Swap 31 31 read-only 0 The startup area is the alternate block (block 1) #0 1 The startup area is the default block (block 0). #1 FCPSR Flash Sequencer Processing Switching Register 0xE0 16 read-write 0x0000 0xffff ESUSPMD Erasure Suspend Mode 0 0 read-write 0 Suspension priority mode #0 1 Erasure priority mode. #1 FPCKAR Flash Sequencer Processing Clock Notification Register 0xE4 16 read-write 0x0032 0xffff PCKA Flash Sequencer Operating Clock Notification 0 7 read-write KEY Key Code 8 15 write-only FSUACR Flash Startup Area Control Register 0xE8 16 read-write 0x0000 0xffff SAS Startup Area Select 0 1 read-write 00 Startup area is selected by BTFLG bit #00 01 Startup area is selected by BTFLG bit #01 10 Startup area is temporarily switched to the default area (block 0) #10 11 Startup area is temporarily switched to the alternate area (block 1). #11 KEY Key Code 8 15 write-only QSPI Quad Serial Peripheral Interface 0x64000000 0x00 28 registers 0x20 12 registers 0x30 8 registers 0x804 4 registers SFMSMD Transfer Mode Control Register 0x000 32 read-write 0x00000000 0xffffffff SFMRM Serial interface read mode select 0 2 read-write 000 Standard Read #000 001 Fast Read #001 010 Fast Read Dual Output #010 011 Fast Read Dual I/O #011 100 Fast Read Quad Output #100 101 Fast Read Quad I/O #101 Others Setting prohibited true SFMSE QSSL extension function select after SPI bus access 4 5 read-write 00 Do not extend QSSL #00 01 Extend QSSL by 33 QSPCLK #01 10 Extend QSSL by 129 QSPCLK #10 11 Extend QSSL infinitely #11 SFMPFE Prefetch function select 6 6 read-write 0 Disable function #0 1 Enable function #1 SFMPAE Function select for stopping prefetch at locations other than on byte boundaries 7 7 read-write 0 Disable function #0 1 Enable function #1 SFMMD3 SPI mode select. 8 8 read-write 0 SPI mode 0 #0 1 SPI mode 3 #1 SFMOEX Extension select for the I/O buffer output enable signal for the serial interface 9 9 read-write 0 Do not extend #0 1 Extend by 1 QSPCLK #1 SFMOHW Hold time adjustment for serial transmission 10 10 read-write 0 Do not extend high-level width of QSPCLK during transmission #0 1 Extend high-level width of QSPCLK by 1 PCLKA during transmission #1 SFMOSW Setup time adjustment for serial transmission 11 11 read-write 0 Do not extend low-level width of QSPCLK during transmission #0 1 Extend low-level width of QSPCLK by 1 PCLKA during transmission #1 SFMCCE Read instruction code select 15 15 read-write 0 Uses automatically generated SPI instruction code #0 1 Use instruction code in the SFMSIC register #1 SFMSSC Chip Selection Control Register 0x004 32 read-write 0x00000037 0xffffffff SFMSW Minimum High-level Width Select for QSSL Signal 0 3 read-write 0x0 1 QSPCLK 0x0 0x1 2 QSPCLK 0x1 0x2 3 QSPCLK 0x2 0x3 4 QSPCLK 0x3 0x4 5 QSPCLK 0x4 0x5 6 QSPCLK 0x5 0x6 7 QSPCLK 0x6 0x7 8 QSPCLK 0x7 0x8 9 QSPCLK 0x8 0x9 10 QSPCLK 0x9 0xA 11 QSPCLK 0xa 0xB 12 QSPCLK 0xb 0xC 13 QSPCLK 0xc 0xD 14 QSPCLK 0xd 0xE 15 QSPCLK 0xe 0xF 16 QSPCLK 0xf SFMSHD QSSL Signal Hold Time 4 4 read-write 0 QSSL outputs high after 0.5 QSPCLK cycles from the last rising edge of QSPCLK. #0 1 QSSL outputs high after 1.5 QSPCLK cycles from the last rising edge of QSPCLK. #1 SFMSLD QSSL Signal Setup Time 5 5 read-write 0 QSSL outputs low before 0.5 QSPCLK cycles from the first rising edge of QSPCLK. #0 1 QSSL outputs low before 1.5 QSPCLK cycles from the first rising edge of QSPCLK. #1 SFMSKC Clock Control Register 0x008 32 read-write 0x00000008 0xffffffff SFMDV Serial interface reference cycle select. (Pay attention to irregularities.) 0 4 read-write 0x00 2 PCLKA 0x00 0x01 3 PCLKA (divided by an odd number) 0x01 0x02 4 PCLKA 0x02 0x03 5 PCLKA (divided by an odd number) 0x03 0x04 6 PCLKA 0x04 0x05 7 PCLKA (divided by an odd number) 0x05 0x06 8 PCLKA 0x06 0x07 9 PCLKA (divided by an odd number) 0x07 0x08 10 PCLKA 0x08 0x09 11 PCLKA (divided by an odd number) 0x09 0x0A 12 PCLKA 0x0a 0x0B 13 PCLKA (divided by an odd number) 0x0b 0x0C 14 PCLKA 0x0c 0x0D 15 PCLKA (divided by an odd number) 0x0d 0x0E 16 PCLKA 0x0e 0x0F 17 PCLKA (divided by an odd number) 0x0f 0x10 18 PCLKA 0x10 0x11 20 PCLKA 0x11 0x12 22 PCLKA 0x12 0x13 24 PCLKA 0x13 0x14 26 PCLKA 0x14 0x15 28 PCLKA 0x15 0x16 30 PCLKA 0x16 0x17 32 PCLKA 0x17 0x18 34 PCLKA 0x18 0x19 36 PCLKA 0x19 0x1A 38 PCLKA 0x1a 0x1B 40 PCLKA 0x1b 0x1C 42 PCLKA 0x1c 0x1D 44 PCLKA 0x1d 0x1E 46 PCLKA 0x1e 0x1F 48 PCLKA 0x1f SFMDTY Duty ratio correction function select for the QSPCLK signal when devided by an odd number 5 5 read-write 0 Make no correction #0 1 Make correction #1 SFMSST Status Register 0x00C 32 read-only 0x00000080 0xffffffff PFCNT Number of bytes of prefetched data 0 4 read-only 0x00 0 byte 0x00 0x01 1 byte 0x01 0x02 2 bytes 0x02 0x03 3 bytes 0x03 0x04 4 bytes 0x04 0x05 5 bytes 0x05 0x06 6 bytes 0x06 0x07 7 bytes 0x07 0x08 8 bytes 0x08 0x09 9 bytes 0x09 0x0A 10 bytes 0x0a 0x0B 11 bytes 0x0b 0x0C 12 bytes 0x0c 0x0D 13 bytes 0x0d 0x0E 14 bytes 0x0e 0x0F 15 bytes 0x0f 0x10 16 bytes 0x10 0x11 17 bytes 0x11 0x12 18 bytes 0x12 Others Reserved true PFFUL Prefetch buffer state 6 6 read-only 0 Prefetch buffer has free space #0 1 Prefetch buffer is full #1 PFOFF Prefetch function operating state 7 7 read-only 0 Prefetch function operating #0 1 Prefetch function not enabled or not operating #1 SFMCOM Communication Port Register 0x010 32 read-write 0x00000000 0xffffff00 SFMD Port for direct communication with the SPI bus 0 7 read-write SFMCMD Communication Mode Control Register 0x014 32 read-write 0x00000000 0xffffffff DCOM Mode select for communication with the SPI bus 0 0 read-write 0 ROM access mode #0 1 Direct communication mode #1 SFMCST Communication Status Register 0x018 32 read-write 0x00000000 0xffffffff COMBSY SPI bus cycle completion state in direct communication 0 0 read-only 0 No serial transfer being processed #0 1 Serial transfer being processed #1 EROMR ROM access detection status in direct communication mode 7 7 read-write 0 ROM access not detected #0 1 ROM access detected #1 SFMSIC Instruction Code Register 0x020 32 read-write 0x00000000 0xffffffff SFMCIC Serial flash instruction code to substitute 0 7 read-write SFMSAC Address Mode Control Register 0x024 32 read-write 0x00000002 0xffffffff SFMAS Number of address bytes select for the serial interface 0 1 read-write 00 1 byte #00 01 2 bytes #01 10 3 bytes #10 11 4 bytes #11 SFM4BC Selection of instruction code automatically generated when the serial interface address width is 4 bytes 4 4 read-write 0 Do not use 4-byte address read instruction code #0 1 Use 4-byte address read instruction code #1 SFMSDC Dummy Cycle Control Register 0x028 32 read-write 0x0000ff00 0xffffffff SFMDN Number of dummy cycles select for Fast Read instructions 0 3 read-write 0x0 Default dummy cycles for each instruction: - Fast Read Quad I/O: 6 QSPCLK - Fast Read Quad Output: 8 QSPCLK - Fast Read Dual I/O: 4 QSPCLK - Fast Read Dual Output: 8 QSPCLK - Fast Read: 8 QSPCLK 0x0 0x1 3 QSPCLK 0x1 0x2 4 QSPCLK 0x2 0x3 5 QSPCLK 0x3 0x4 6 QSPCLK 0x4 0x5 7 QSPCLK 0x5 0x6 8 QSPCLK 0x6 0x7 9 QSPCLK 0x7 0x8 10 QSPCLK 0x8 0x9 11 QSPCLK 0x9 0xA 12 QSPCLK 0xa 0xB 13 QSPCLK 0xb 0xC 14 QSPCLK 0xc 0xD 15 QSPCLK 0xd 0xE 16 QSPCLK 0xe 0xF 17 QSPCLK 0xf SFMXST XIP mode status 6 6 read-only 0 Normal (non-XIP) mode #0 1 XIP mode #1 SFMXEN XIP mode permission 7 7 read-write 0 Prohibit XIP mode #0 1 Permit XIP mode #1 SFMXD Mode data for serial flash (Controls XIP mode.) 8 15 read-write SFMSPC SPI Protocol Control Register 0x030 32 read-write 0x00000010 0xffffffff SFMSPI SPI protocol select 0 1 read-write 00 Single SPI Protocol, Extended SPI protocol #00 01 Dual SPI protocol #01 10 Quad SPI protocol #10 11 Setting prohibited #11 SFMSDE QSPCLK extended selection bit when switching I/O of QIOn pin 4 4 read-write 0 No QSPCLK extension #0 1 QSPCLK expansion when switching I/O direction of QIOn pin #1 SFMPMD Port Control Register 0x034 32 read-write 0x00000000 0xffffffff SFMWPL WP pin level specification 2 2 read-write 0 Low level #0 1 High level #1 SFMCNT1 External QSPI Address Register 0x804 32 read-write 0x00000000 0xffffffff QSPI_EXT Bank switching address 26 31 read-write