Renesas Renesas R7FA4M1AB RA4 1.2 ARM 32-bit Cortex-M4F Microcontroller based device, CPU clock up to 48MHz, etc. CM4 r0p1 little true true true 4 false 8 32 SYSTEM System Control 0x4001E000 0x41D 3 registers 0x4B0 3 registers 0x4B4 1 registers 0x4B6 1 registers 0x4B8 8 registers 0x500 512 registers 0x20 5 registers 0x26 1 registers 0x2A 2 registers 0x30 3 registers 0x36 3 registers 0x3C 1 registers 0x3E 4 registers 0x50 1 registers 0x52 1 registers 0x61 2 registers 0xA2 1 registers 0xA5 1 registers 0xD0 1 registers 0x413 1 registers 0x480 2 registers 0x490 1 registers 0x492 1 registers 0x20 5 registers 0x26 1 registers 0x2A 2 registers 0x30 3 registers 0x36 3 registers 0x3C 1 registers 0x3E 4 registers 0x50 1 registers 0x52 1 registers 0x61 2 registers 0xA2 1 registers 0xA5 1 registers 0xD0 1 registers 0x413 1 registers 0x480 2 registers 0x490 1 registers 0x492 1 registers 0x0C 2 registers 0x1C 4 registers 0x92 1 registers 0x94 1 registers 0x98 5 registers 0x9F 1 registers 0x9E 1 registers 0xA0 1 registers 0xAA 1 registers 0x40E 1 registers 0x0C 2 registers 0x1C 4 registers 0x92 1 registers 0x94 1 registers 0x98 5 registers 0x9F 1 registers 0x9E 1 registers 0xA0 1 registers 0xAA 1 registers 0x40E 1 registers 0x417 5 registers 0xE0 4 registers 0xE1 4 registers 0x417 5 registers 0xE0 4 registers 0xE1 4 registers 0x3FE 2 registers 0x3FE 2 registers 0x410 2 registers 0xC0 2 registers 0x410 2 registers 0xC0 2 registers 0xC6 1 registers 0xC6 1 registers VBTCR1 VBATT Control Register1 0x41F 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write BPWSWSTP Battery Power supply Switch Stop 0 0 read-write 0 Battery Power supply Switch Enable #0 1 Battery Power supply Switch stop #1 VBTCR2 VBATT Control Register2 0x4B0 8 read-write 0x00 0xFF VBTLVDLVL VBATT Pin Voltage Low Voltage Detect Level Select Bit 6 7 read-write 00 2.7V #00 01 Setting prohibited #01 10 2.3V #10 11 2.1V #11 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write VBTLVDEN VBATT Pin Low Voltage Detect Enable Bit 4 4 read-write 0 VBATT pin low voltage detect disable #0 1 VBATT pin low voltage detect enable #1 Reserved These bits are read as 0000. The write value should be 0000. 0 3 read-write VBTSR VBATT Status Register 0x4B1 8 read-write 0x01 0xEC Reserved These bits are read as 000. The write value should be 000. 5 7 read-write VBTRVLD VBATT_R Valid 4 4 read-only 0 VBATT_R area not valid #0 1 VBATT_R area valid #1 Reserved These bits are read as 00. The write value should be 00. 2 3 read-write VBTBLDF VBATT Battery Low voltage Detect Flag 1 1 read-write zeroToClear modify 0 VBATT pin low voltage not detected #0 1 VBATT pin low voltage detected. #1 VBTRDF VBAT_R Reset Detect Flag 0 0 read-write zeroToClear modify 0 VBATT_R voltage power-on reset not detected #0 1 VBATT_R selected voltage power-on reset detected. #1 VBTCMPCR VBATT Comparator Control Register 0x4B2 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write VBTCMPE VBATT pin low voltage detect circuit output enable 0 0 read-write 0 VBATT pin low voltage detect circuit output disabled #0 1 VBATT pin low voltage detect circuit output enabled #1 VBTLVDICR VBATT Pin Low Voltage Detect Interrupt Control Register 0x4B4 8 read-write 0x00 0xFF Reserved These bits are read as 000000. The write value should be 000000. 2 7 read-write VBTLVDISEL Pin Low Voltage Detect Interrupt Select bit 1 1 read-write 0 Non Maskable Interrupt #0 1 Maskable Interrupt #1 VBTLVDIE VBATT Pin Low Voltage Detect Interrupt Enable bit 0 0 read-write 0 VBATT Pin Low Voltage Detect Interrupt Disable #0 1 VBATT Pin Low Voltage Detect Interrupt Enable #1 VBTWCTLR VBATT Wakeup function Control Register 0x4B6 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write VWEN VBATT wakeup enable 0 0 read-write 0 Disable Wakeup function #0 1 Enable Wakeup function #1 VBTWCH0OTSR VBATT Wakeup I/O 0 Output Trigger Select Register 0x4B8 8 read-write 0x00 0xFF Reserved These bits are read as 000. The write value should be 000. 5 7 read-write CH0VRTCATE VBATWIO0 Output RTC Alarm Signal Enable 4 4 read-write 0 VBATT wakeup I/O 0 output trigger by the RTC alarm signal is disabled #0 1 VBATT wakeup I/O 0 output trigger by the RTC alarm signal is enabled. #1 CH0VRTCTE VBATWIO0 Output RTC Periodic Signal Enable 3 3 read-write 0 VBATT wakeup I/O 0 output trigger by the RTC periodic signal is disabled #0 1 VBATT wakeup I/O 0 output trigger by the RTC periodic signal is enabled. #1 CH0VCH2TE VBATWIO0 Output VBATWIO2 Trigger Enable 2 2 read-write 0 VBATT wakeup I/O 0 output trigger by the VBATWIO2 pin is disabled #0 1 VBATT wakeup I/O 0 output trigger by the VBATWIO2 pin is enabled. #1 CH0VCH1TE VBATWIO0 Output VBATWIO1 Trigger Enable 1 1 read-write 0 VBATT wakeup I/O 0 output trigger by the VBATWIO1 pin is disabled #0 1 VBATT wakeup I/O 0 output trigger by the VBATWIO1 pin is enabled. #1 Reserved This bit is read as 0. The write value should be 0. 0 0 read-write VBTWCH1OTSR VBATT Wakeup I/O 1 Output Trigger Select Register 0x4B9 8 read-write 0x00 0xFF Reserved These bits are read as 000. The write value should be 000. 5 7 read-write CH1VRTCATE VBATWIO1 Output RTC Alarm Signal Enable 4 4 read-write 0 VBATT wakeup I/O 1 output trigger by the RTC alarm signal is disabled #0 1 VBATT wakeup I/O 1 output trigger by the RTC alarm signal is enabled. #1 CH1VRTCTE VBATWIO1 Output RTC Periodic Signal Enable 3 3 read-write 0 VBATT wakeup I/O 1 output trigger by the RTC periodic signal is disabled #0 1 VBATT wakeup I/O 1 output trigger by the RTC periodic signal is enabled #1 CH1VCH2TE VBATWIO1 Output VBATWIO2 Trigger Enable 2 2 read-write 0 VBATT wakeup I/O 1 output trigger by the VBATWIO2 pin is disabled #0 1 VBATT wakeup I/O 1 output trigger by the VBATWIO2 pin is enabled. #1 Reserved This bit is read as 0. The write value should be 0. 1 1 read-write CH1VCH0TE VBATWIO1 Output VBATWIO0 Trigger Enable 0 0 read-write 0 VBATT wakeup I/O 1 output trigger by the VBATWIO0 pin is disabled #0 1 VBATT wakeup I/O 1 output trigger by the VBATWIO0 pin is enabled. #1 VBTWCH2OTSR VBATT Wakeup I/O 2 Output Trigger Select Register 0x4BA 8 read-write 0x00 0xFF Reserved These bits are read as 000. The write value should be 000. 5 7 read-write CH2VRTCATE VBATWIO2 Output RTC Alarm Signal Enable 4 4 read-write 0 VBATT wakeup I/O 2 output trigger by the RTC alarm signal is disabled #0 1 VBATT wakeup I/O 2 output trigger by the RTC alarm signal is enabled. #1 CH2VRTCTE VBATWIO2 Output RTC Periodic Signal Enable 3 3 read-write 0 VBATT wakeup I/O 2 output trigger by the RTC periodic signal is disabled #0 1 VBATT wakeup I/O 2 output trigger by the RTC periodic signal is enabled. #1 Reserved This bit is read as 0. The write value should be 0. 2 2 read-write CH2VCH1TE VBATWIO2 Output VBATWIO1 Trigger Enable 1 1 read-write 0 VBATT wakeup I/O 2 output trigger by the VBATWIO1 pin is disabled #0 1 VBATT wakeup I/O 2 output trigger by the VBATWIO1 pin is enabled. #1 CH2VCH0TE VBATWIO2 Output VBATWIO0 Trigger Enable 0 0 read-write 0 VBATT wakeup I/O 2 output trigger by the VBATWIO0 pin is disabled #0 1 VBATT wakeup I/O 2 output trigger by the VBATWIO0 pin is enabled. #1 VBTICTLR VBATT Input Control Register 0x4BB 8 read-write 0x00 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write VCH2INEN VBATT Wakeup I/O 2 Input Enable 2 2 read-write 0 VBATWIO2 and RTCIC2 inputs disabled #0 1 VBATWIO2 and RTCIC2 inputs enabled. #1 VCH1INEN VBATT Wakeup I/O 1 Input Enable 1 1 read-write 0 VBATWIO1, RTCIC1 inputs disabled #0 1 VBATWIO1, RTCIC1 inputs enabled. #1 VCH0INEN VBATT Wakeup I/O 0 Input Enable 0 0 read-write 0 VBATWIO0, RTCIC0 inputs disabled #0 1 VBATWIO0, RTCIC0 inputs enabled. #1 VBTOCTLR VBATT Output Control Register 0x4BC 8 read-write 0x00 0xFF Reserved These bits are read as 00. The write value should be 00. 6 7 read-write VOUT2LSEL VBATT Wakeup I/O 2 Output Level Selection 5 5 read-write 0 Output L before VBATT wake up trigger #0 1 Output H before VBATT wake up trigger #1 VOUT1LSEL VBATT Wakeup I/O 1 Output Level Selection 4 4 read-write 0 Output L before VBATT wake up trigger #0 1 Output H before VBATT wake up trigger #1 VOUT0LSEL VBATT Wakeup I/O 0 Output Level Selection 3 3 read-write 0 Output L before VBATT wakeup trigger #0 1 Output H before VBATT wakeup trigger #1 VCH2OEN VBATT Wakeup I/O 2 Output Enable 2 2 read-write 0 VBATWIO2 output disabled #0 1 VBATWIO2 output enabled #1 VCH1OEN VBATT Wakeup I/O 1 Output Enable 1 1 read-write 0 VBATWIO1 output disabled #0 1 VBATWIO1 output enabled #1 VCH0OEN VBATT Wakeup I/O 0 Output Enable 0 0 read-write 0 VBATWIO0 output disabled #0 1 VBATWIO0 output enabled #1 VBTWTER VBATT Wakeup Trigger source Enable Register 0x4BD 8 read-write 0x00 0xFF Reserved These bits are read as 000. The write value should be 000. 5 7 read-write VRTCAE RTC Alarm Signal Enable 4 4 read-write 0 VBATT wakeup triggered by RTC alarm signal is disabled #0 1 VBATT wakeup triggered by RTC alarm signal is enabled. #1 VRTCIE RTC Periodic Signal Enable 3 3 read-write 0 VBATT wakeup triggered by RTC periodic signal is disabled #0 1 VBATT wakeup triggered by RTC periodic signal is enabled. #1 VCH2E VBATWIO2 Pin Enable 2 2 read-write 0 VBATT wakeup triggered by the VBATWIO2 pin is disabled #0 1 VBATT wakeup triggered by the VBATWIO2 pin is enabled. #1 VCH1E VBATWIO1 Pin Enable 1 1 read-write 0 VBATT wakeup triggered by the VBATWIO1 pin is disabled #0 1 VBATT wakeup triggered by the VBATWIO1 pin is enabled. #1 VCH0E VBATWIO0 Pin Enable 0 0 read-write 0 VBATT wakeup triggered by the VBATWIO0 pin is disabled #0 1 VBATT wakeup triggered by the VBATWIO0 pin is enabled. #1 VBTWEGR VBATT Wakeup Trigger source Edge Register 0x4BE 8 read-write 0x00 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write VCH2EG VBATWIO2 Wakeup Trigger Source Edge Select 2 2 read-write 0 Wakeup trigger is generated at a falling edge #0 1 Wakeup trigger is generated at a rising edge. #1 VCH1EG VBATWIO1 Wakeup Trigger Source Edge Select 1 1 read-write 0 Wakeup trigger is generated at a falling edge #0 1 Wakeup trigger is generated at a rising edge. #1 VCH0EG VBATWIO0 Wakeup Trigger Source Edge Select 0 0 read-write 0 Wakeup trigger is generated at a falling edge #0 1 Wakeup trigger is generated at a rising edge. #1 VBTWFR VBATT Wakeup trigger source Flag Register 0x4BF 8 read-write 0x00 0xFF Reserved These bits are read as 000. The write value should be 000. 5 7 read-write VRTCAF VBATT RTC-Alarm Wakeup Trigger Flag 4 4 read-write zeroToClear modify 0 No wakeup trigger by the RTC alarm is generated #0 1 A wakeup trigger by the RTC alarm is generated #1 VRTCIF VBATT RTC-Interval Wakeup Trigger Flag 3 3 read-write zeroToClear modify 0 No wakeup trigger by the RTC interval is generated #0 1 A wakeup trigger by the RTC interval is generated #1 VCH2F VBATWIO2 Wakeup Trigger Flag 2 2 read-write zeroToClear modify 0 No wakeup trigger by the VBATWIO2 pin is generated #0 1 A wakeup trigger by the VBATWIO2 pin is generated #1 VCH1F VBATWIO1 Wakeup Trigger Flag 1 1 read-write zeroToClear modify 0 No wakeup trigger by the VBATWIO1 pin is generated #0 1 A wakeup trigger by the VBATWIO1 pin is generated #1 VCH0F VBATWIO0 Wakeup Trigger Flag 0 0 read-write zeroToClear modify 0 No wakeup trigger by the VBATWIO0 pin is generated #0 1 A wakeup trigger by the VBATWIO0 pin is generated #1 512 0x1 0-511 VBTBKR[%s] VBATT Backup Register [%s] 0x500 8 read-write 0x00 0x00 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT. The value of this register is retained even when VCC is not powered but VBATT is powered. VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write SCKDIVCR System Clock Division Control Register 0x020 32 read-write 0x44044444 0xFFFFFFFF Reserved This bit is read as 0. The write value should be 0. 31 31 read-write FCK Flash IF Clock (FCLK) Select 28 30 read-write 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 others Setting prohibited true Reserved This bit is read as 0. The write value should be 0. 27 27 read-write ICK System Clock (ICLK) Select 24 26 read-write 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 others Setting prohibited true Reserved These bits are read as 00000. The write value should be 00000. 19 23 read-write Reserved This bit is read as 1. The write value should be 1. 18 18 read-write Reserved These bits are read as 00. The write value should be 00. 16 17 read-write Reserved This bit is read as 0. The write value should be 0. 15 15 read-write PCKA Peripheral Module Clock A (PCLKA) Select 12 14 read-write 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 others Setting prohibited true Reserved This bit is read as 0. The write value should be 0. 11 11 read-write PCKB Peripheral Module Clock B (PCLKB) Select 8 10 read-write 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 others Setting prohibited true Reserved This bit is read as 0. The write value should be 0. 7 7 read-write PCKC Peripheral Module Clock C (PCLKC) Select 4 6 read-write 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 others Setting prohibited true Reserved This bit is read as 0. The write value should be 0. 3 3 read-write PCKD Peripheral Module Clock D (PCLKD) Select 0 2 read-write 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 others Setting prohibited true SCKSCR System Clock Source Control Register 0x026 8 read-write 0x01 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write CKSEL Clock Source Select Selecting the system clock source faster than 32MHz(system clock source > 32MHz ) is prohibit when SCKDIVCR.ICK[2:0] bits select the division-by-1 and MEMWAIT.MEMWAIT =0. 0 2 read-write 000 HOCO #000 001 MOCO #001 010 LOCO #010 011 Main clock oscillator #011 100 Sub-clock oscillator #100 101 PLL #101 others Setting prohibited true PLLCR PLL Control Register 0x02A 8 read-write 0x01 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write PLLSTP PLL Stop Control 0 0 read-write 0 PLL is operating. #0 1 PLL is stopped. #1 PLLCCR2 PLL Clock Control Register2 0x02B 8 read-write 0x07 0xFF PLODIV PLL Output Frequency Division Ratio Select 6 7 read-write 00 /1. #00 01 /2. #01 10 /4. #10 11 Setting prohibited. #11 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write PLLMUL PLL Frequency Multiplication Factor Select 0 4 read-write 1111 Settings prohibited. #1111 others x PLLMUL[4:0] +1 true MEMWAIT Memory Wait Cycle Control Register 0x031 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write MEMWAIT Memory Wait Cycle Select Note: Writing 0 to the MEMWAIT is prohibited when SCKDIVCR.ICK selects division by 1 and SCKSCR.CKSEL[2:0] bits select the system clock source that is faster than 32 MHz (ICLK > 32 MHz). 0 0 read-write 0 no wait #0 1 wait #1 MOSCCR Main Clock Oscillator Control Register 0x032 8 read-write 0x01 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write MOSTP Main Clock Oscillator Stop Note: MOMCR register must be set before setting MOSTP to 0. 0 0 read-write 0 Main clock oscillator is operating. #0 1 Main clock oscillator is stopped. #1 HOCOCR High-Speed On-Chip Oscillator Control Register 0x036 8 read-write 0x00 0xFE Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write HCSTP HOCO Stop 0 0 read-write 0 HOCO is operating. #0 1 HOCO is stopped. #1 MOCOCR Middle-Speed On-Chip Oscillator Control Register 0x038 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write MCSTP MOCO Stop 0 0 read-write 0 MOCO is operating. #0 1 MOCO is stopped. #1 OSCSF Oscillation Stabilization Flag Register 0x03C 8 read-only 0x00 0xFE Reserved These bits are read as 00. 6 7 read-only PLLSF PLL Clock Oscillation Stabilization Flag 5 5 read-only 0 The PLL clock is stopped or oscillation of the PLL clock has not yet become stable. #0 1 Oscillation of the PLL clock is stable so the clock is available for use as the system clock. #1 Reserved This bit is read as 0. 4 4 read-only MOSCSF Main Clock Oscillation Stabilization Flag 3 3 read-only 0 MOSTP = 1 (stopping the main clock oscillator) or oscillation of the main clock has not yet become stable. #0 1 Oscillation of the main clock is stable so the clock is available for use as the system clock. #1 Reserved These bits are read as 00. 1 2 read-only HOCOSF HOCO Clock Oscillation Stabilization Flag NOTE: The HOCOSF bit value after a reset is 1 when the OFS1.HOCOEN bit is 0. It is 0 when the OFS1.HOCOEN bit is 1. 0 0 read-only 0 The HOCO clock is stopped or oscillation of the HOCO clock has not yet become stable. #0 1 Oscillation of the HOCO clock is stable so the clock is available for use as the system clock. #1 CKOCR Clock Out Control Register 0x03E 8 read-write 0x00 0xFF CKOEN Clock out enable 7 7 read-write 0 Clock Out disable #0 1 Clock Out enable #1 CKODIV Clock out input frequency Division Select 4 6 read-write 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 111 /128 #111 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write CKOSEL Clock out source select 0 2 read-write 000 HOCO #000 001 MOCO #001 010 LOCO #010 011 MOSC #011 100 SOSC #100 others Setting prohibited true TRCKCR Trace Clock Control Register 0x03F 8 read-write 0x01 0xFF TRCKEN Trace Clock operating enable 7 7 read-write 0 Operation disabled #0 1 Operation enabled. #1 Reserved These bits are read as 000. The write value should be 000. 4 6 read-write TRCK Trace Clock operating frequency select 0 3 read-write 0000 /1 #0000 0001 /2(value after reset) #0001 0010 /4 #0010 others Setting prohibited true OSTDCR Oscillation Stop Detection Control Register 0x040 8 read-write 0x00 0xFF OSTDE Oscillation Stop Detection Function Enable 7 7 read-write 0 Oscillation stop detection function is disabled. #0 1 Oscillation stop detection function is enabled. #1 Reserved These bits are read as 000000. The write value should be 000000. 1 6 read-write OSTDIE Oscillation Stop Detection Interrupt Enable 0 0 read-write 0 The oscillation stop detection interrupt is disabled. Oscillation stop detection is not notified to the POEG. #0 1 The oscillation stop detection interrupt is enabled. Oscillation stop detection is notified to the POEG. #1 OSTDSR Oscillation Stop Detection Status Register 0x041 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write OSTDF Oscillation Stop Detection Flag 0 0 read-write zeroToClear modify 0 The main clock oscillation stop has not been detected. #0 1 The main clock oscillation stop has been detected. #1 SLCDSCKCR Segment LCD Source Clock Control Register 0x050 8 read-write 0x00 0xFF LCDSCKEN LCD Source Clock Out Enable 7 7 read-write 0 LCD source clock out disabled #0 1 LCD source clock out enabled. #1 Reserved These bits are read as 0000. The write value should be 0000. 3 6 read-write LCDSCKSEL LCD Source Clock (LCDSRCCLK) Select 0 2 read-write 000 LOCO #000 001 SOSC #001 010 MOSC #010 100 HOCO #100 others Settings other than above are prohibited. true MOCOUTCR MOCO User Trimming Control Register 0x061 8 read-write 0x00 0xFF MOCOUTRM MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127 These bits are added to original MOCO trimming bits 0 7 read-write HOCOUTCR HOCO User Trimming Control Register 0x062 8 read-write 0x00 0xFF HOCOUTRM HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127 These bits are added to original HOCO trimming bits 0 7 read-write MOSCWTCR Main Clock Oscillator Wait Control Register 0x0A2 8 read-write 0x05 0xFF Reserved These bits are read as 0000. The write value should be 0000. 4 7 read-write MSTS Main clock oscillator wait time setting 0 3 read-write 0000 Wait time = 2 cycles (0.25 us) #0000 0001 Wait time = 1024 cycles (128 us) #0001 0010 Wait time = 2048 cycles (256 us) #0010 0011 Wait time = 4096 cycles (512 us) #0011 0100 Wait time = 8192 cycles (1024 us) #0100 0101 Wait time = 16384 cycles (2048 us) (value after reset) #0101 0110 Wait time = 32768 cycles (4096 us) #0110 0111 Wait time = 65536 cycles (8192 us) #0111 1000 Wait time = 131072 cycles (16384 us) #1000 1001 Wait time = 262144 cycles (32768 us). #1001 others Setting prohibited true HOCOWTCR High-Speed On-Chip Oscillator Wait Control Register 0x0A5 8 read-write 0x05 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write HSTS HOCO wait time setting 0 2 read-write 101 If HOCO frequency is other than 64MHz, should set the value to 101b. #101 110 If HOCO frequency = 64MHz, should set the value to 110b. #110 others Setting prohibited true USBCKCR USB Clock Control register 0x0D0 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write USBCLKSEL USB Clock Source Select 0 0 read-write 0 PLL(Value after reset) #0 1 HOCO #1 MOMCR Main Clock Oscillator Mode Oscillation Control Register 0x413 8 read-write 0x00 0xFF Reserved This bit is read as 0. The write value should be 0. 7 7 read-write MOSEL Main Clock Oscillator Switching 6 6 read-write 0 Resonator #0 1 External clock input #1 Reserved These bits are read as 00. The write value should be 00. 4 5 read-write MODRV1 Main Clock Oscillator Drive Capability 1 Switching 3 3 read-write 0 10 MHz to 20 MHz #0 1 1 MHz to 10 MHz. #1 Reserved These bits are read as 000. The write value should be 000. 0 2 read-write SOSCCR Sub-Clock Oscillator Control Register 0x480 8 read-write 0x01 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write SOSTP Sub-Clock Oscillator Stop 0 0 read-write 0 Sub-clock oscillator is operating. #0 1 Sub-clock oscillator is stopped. #1 SOMCR Sub Clock Oscillator Mode Control Register 0x481 8 read-write 0x00 0xFF Reserved These bits are read as 000000. The write value should be 000000. 2 7 read-write SODRV Sub-Clock Oscillator Drive Capability Switching 0 1 read-write 00 Normal mode #00 01 Low power mode 1 #01 10 Low power mode 2 #10 11 Low power mode 3. #11 LOCOCR Low-Speed On-Chip Oscillator Control Register 0x490 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write LCSTP LOCO Stop 0 0 read-write 0 LOCO is operating. #0 1 LOCO is stopped. #1 LOCOUTCR LOCO User Trimming Control Register 0x492 8 read-write 0x00 0xFF LOCOUTRM LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127 These bits are added to original LOCO trimming bits 0 7 read-write SBYCR Standby Control Register 0x00C 16 read-write 0x4000 0xFFFF SSBY Software Standby 15 15 read-write 0 Sleep mode #0 1 Software Standby mode #1 Reserved This bit is read as 1. The write value should be 1. 14 14 read-write Reserved These bits are read as 00000000000000. The write value should be 00000000000000. 0 13 read-write MSTPCRA Module Stop Control Register A 0x01C 32 read-write 0xFFBFFFBE 0xFFFFFFFF Reserved These bits are read as 111111111. The write value should be 111111111. 23 31 read-write MSTPA22 DMA Controller/Data Transfer Controller Module Stop 22 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved These bits are read as 111111111111111. The write value should be 111111111111111. 7 21 read-write MSTPA6 ECCRAM Module Stop 6 6 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved These bits are read as 11111. The write value should be 11111. 1 5 read-write MSTPA0 RAM0 Module Stop 0 0 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 SNZCR Snooze Control Register 0x092 8 read-write 0x00 0xFF SNZE Snooze Mode Enable 7 7 read-write 0 Disable Snooze Mode #0 1 Enable Snooze Mode #1 Reserved These bits are read as 00000. The write value should be 00000. 2 6 read-write SNZDTCEN DTC Enable in Snooze Mode 1 1 read-write 0 Disable DTC operation #0 1 Enable DTC operation #1 RXDREQEN RXD0 Snooze Request Enable NOTE: Do not set to 1 other than in asynchronous mode. 0 0 read-write 0 Ignore RXD0 falling edge in Software Standby mode. #0 1 Accept RXD0 falling edge in Standby mode as a request to transit to Snooze mode. #1 SNZEDCR Snooze End Control Register 0x094 8 read-write 0x00 0xFF SCI0UMTED SCI0 Address Mismatch Snooze End Enable 7 7 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 Reserved These bits are read as 00. The write value should be 00. 5 6 read-write AD0UMTED ADC140 Compare Mismatch Snooze End Enable 4 4 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 AD0MATED ADC140 Compare Match Snooze End Enable 3 3 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 DTCNZRED Not Last DTC Transmission Completion Snooze End Enable 2 2 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 DTCZRED Last DTC Transmission Completion Snooze End Enable 1 1 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 AGTUNFED AGT1 Underflow Snooze End Enable 0 0 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 SNZREQCR Snooze Request Control Register 0x098 32 read-write 0x00000000 0xFFFFFFFF Reserved This bit is read as 0. The write value should be 0. 31 31 read-write SNZREQEN30 Snooze Request Enable 30 Enable AGT1 compare match B snooze request 30 30 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN29 Snooze Request Enable 29 Enable AGT1 compare match A snooze request 29 29 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN28 Snooze Request Enable 28 Enable AGT1 underflow snooze request 28 28 read-write 0 Disable snooze request #0 1 Enable snooze request #1 Reserved These bits are read as 00. The write value should be 00. 26 27 read-write SNZREQEN25 Snooze Request Enable 25 Enable RTC period snooze request 25 25 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN24 Snooze Request Enable 24 Enable RTC alarm snooze request 24 24 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN23 Snooze Request Enable 23 Enable RTC alarm snooze request 23 23 read-write 0 Disable snooze request #0 1 Enable snooze request #1 Reserved These bits are read as 00000. The write value should be 00000. 18 22 read-write SNZREQEN17 Snooze Request Enable 17 Enable KINT snooze request 17 17 read-write 0 Disable snooze request #0 1 Enable snooze request #1 Reserved This bit is read as 0. The write value should be 0. 16 16 read-write SNZREQEN15 Snooze Request Enable 15 Enable IRQ15 pin snooze request 15 15 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN14 Snooze Request Enable 14 Enable IRQ14 pin snooze request 14 14 read-write 0 Disable snooze request #0 1 Enable snooze request #1 Reserved This bit is read as 0. The write value should be 0. 13 13 read-write SNZREQEN12 Snooze Request Enable 12 Enable IRQ12 pin snooze request 12 12 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN11 Snooze Request Enable 11 Enable IRQ11 pin snooze request 11 11 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN10 Snooze Request Enable 10 Enable IRQ10 pin snooze request 10 10 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN9 Snooze Request Enable 9 Enable IRQ9 pin snooze request 9 9 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN8 Snooze Request Enable 8 Enable IRQ8 pin snooze request 8 8 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN7 Snooze Request Enable 7 Enable IRQ7 pin snooze request 7 7 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN6 Snooze Request Enable 6 Enable IRQ6 pin snooze request 6 6 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN5 Snooze Request Enable 5 Enable IRQ5 pin snooze request 5 5 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN4 Snooze Request Enable 4 Enable IRQ4 pin snooze request 4 4 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN3 Snooze Request Enable 3 Enable IRQ3 pin snooze request 3 3 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN2 Snooze Request Enable 2 Enable IRQ2 pin snooze request 2 2 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN1 Snooze Request Enable 1 Enable IRQ1 pin snooze request 1 1 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN0 Snooze Request Enable 0 Enable IRQ0 pin snooze request 0 0 read-write 0 Disable snooze request #0 1 Enable snooze request #1 FLSTOP Flash Operation Control Register 0x09E 8 read-write 0x00 0xFF Reserved These bits are read as 000. The write value should be 000. 5 7 read-write FLSTPF Flash Memory Operation Status Flag 4 4 read-only 0 Transition completed #0 1 During transition (from the flash-stop-status to flash-operating-status or vice versa) #1 Reserved These bits are read as 000. The write value should be 000. 1 3 read-write FLSTOP Selecting ON/OFF of the Flash Memory Operation 0 0 read-write 0 Code flash and data flash memory operates #0 1 Code flash and data flash memory stops. #1 OPCCR Operating Power Control Register 0x0A0 8 read-write 0x02 0xFF Reserved These bits are read as 000. The write value should be 000. 5 7 read-write OPCMTSF Operating Power Control Mode Transition Status Flag 4 4 read-only 0 Transition completed #0 1 During transition #1 Reserved These bits are read as 00. The write value should be 00. 2 3 read-write OPCM Operating Power Control Mode Select 0 1 read-write 00 High-speed mode #00 01 Middle-speed mode #01 10 Low-voltage mode #10 11 Low-speed mode #11 SOPCCR Sub Operating Power Control Register 0x0AA 8 read-write 0x00 0xFF Reserved These bits are read as 000. The write value should be 000. 5 7 read-write SOPCMTSF Sub Operating Power Control Mode Transition Status Flag 4 4 read-only 0 Transition completed #0 1 During transition #1 Reserved These bits are read as 000. The write value should be 000. 1 3 read-write SOPCM Sub Operating Power Control Mode Select 0 0 read-write 0 Other than Subosc-speed mode #0 1 Subosc-speed mode #1 SYOCDCR System Control OCD Control Register 0x40E 8 read-write 0x00 0xFF DBGEN Debugger Enable bit 7 7 read-write 0 On-chip debugger is disabled #0 1 On-chip debugger is enabled #1 Reserved These bits are read as 0000000. The write value should be 0000000. 0 6 read-write LVCMPCR Voltage Monitor Circuit Control Register 0x417 8 read-write 0x00 0xFF Reserved This bit is read as 0. The write value should be 0. 7 7 read-write LVD2E Voltage Detection 2 Enable 6 6 read-write 0 Voltage detection 2 circuit disabled #0 1 Voltage detection 2 circuit enabled #1 LVD1E Voltage Detection 1 Enable 5 5 read-write 0 Voltage detection 1 circuit disabled #0 1 Voltage detection 1 circuit enabled #1 Reserved This bit is read as 0. The write value should be 0. 4 4 read-write Reserved These bits are read as 00. The write value should be 00. 2 3 read-write Reserved These bits are read as 00. The write value should be 00. 0 1 read-write LVDLVLR Voltage Detection Level Select Register 0x418 8 read-write 0x07 0xFF LVD2LVL Voltage Detection 2 Level Select (Standard voltage during drop in voltage) 5 7 read-write 000 4.29V (Vdet2_0) #000 001 4.14V (Vdet2_1) #001 010 4.02V (Vdet2_2) #010 011 3.84V (Vdet2_3) #011 others Setting prohibited. true LVD1LVL Voltage Detection 1 Level Select (Standard voltage during drop in voltage) 0 4 read-write 00000 4.29V (Vdet1_0) #00000 00001 4.14V (Vdet1_1) #00001 00010 4.02V (Vdet1_2) #00010 00011 3.84V (Vdet1_3) #00011 00100 3.10V (Vdet1_4) #00100 00101 3.00V (Vdet1_5) #00101 00110 2.90V (Vdet1_6) #00110 00111 2.79V (Vdet1_7) #00111 01000 2.68V (Vdet1_8) #01000 01001 2.58V (Vdet1_9) #01001 01010 2.48V (Vdet1_A) #01010 01011 2.20V (Vdet1_B) #01011 01100 1.96V (Vdet1_C) #01100 01101 1.86V (Vdet1_D) #01101 01110 1.75V (Vdet1_E) #01110 01111 1.65V (Vdet1_F) #01111 others Setting prohibited true 2 0x1 1,2 LVD%sCR0 Voltage Monitor %s Circuit Control Register 0 0x41A 8 read-write 0x80 0xF7 RN Voltage Monitor Reset Negate Select 7 7 read-write 0 Negation follows a stabilization time (tLVD) after VCC > Vdet1 is detected. #0 1 Negation follows a stabilization time (tLVD) after assertion of the LVD reset. #1 RI Voltage Monitor Circuit Mode Select 6 6 read-write 0 Voltage Monitor interrupt during Vdet1 passage #0 1 Voltage Monitor reset enabled when the voltage falls to and below Vdet1 #1 Reserved These bits are read as 000. The write value should be 000. 3 5 read-write CMPE Voltage Monitor Circuit Comparison Result Output Enable 2 2 read-write 0 Voltage Monitor circuit comparison result output disabled. #0 1 Voltage Monitor circuit comparison result output enabled. #1 Reserved This bit is read as 0. The write value should be 0. 1 1 read-write RIE Voltage Monitor Interrupt/Reset Enable 0 0 read-write 0 Disabled #0 1 Enabled #1 2 0x2 1,2 LVD%sCR1 Voltage Monitor %s Circuit Control Register 1 0x0E0 8 read-write 0x01 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write IRQSEL Voltage Monitor Interrupt Type Select 2 2 read-write 0 Non-maskable interrupt #0 1 Maskable interrupt #1 IDTSEL Voltage Monitor Interrupt Generation Condition Select 0 1 read-write 00 When VCC>=Vdet (rise) is detected #00 01 When VCC<Vdet (drop) is detected #01 10 When drop and rise are detected #10 11 Settings prohibited #11 2 0x2 1,2 LVD%sSR Voltage Monitor %s Circuit Status Register 0x0E1 8 read-write 0x02 0xFF Reserved These bits are read as 000000. The write value should be 000000. 2 7 read-write MON Voltage Monitor 1 Signal Monitor Flag 1 1 read-only 0 VCC < Vdet #0 1 VCC >= Vdet or MON bit is disabled #1 DET Voltage Monitor Voltage Change Detection Flag NOTE: Only 0 can be written to this bit. After writing 0 to this bit, it takes 2 system clock cycles for the bit to be read as 0. 0 0 read-write zeroToClear modify 0 Not detected #0 1 Vdet1 passage detection #1 PRCR Protect Register 0x3FE 16 read-write 0x0000 0xFFFF PRKEY PRC Key Code 8 15 write-only 0x5A Enables writing to the PRCR register. 0x5A others Disables writing to the PRCR register. true Reserved These bits are read as 0000. The write value should be 0000. 4 7 read-write PRC3 Protect Bit 3 3 3 read-write 0 Writes protected. #0 1 Writes not protected. #1 Reserved This bit is read as 0. The write value should be 0. 2 2 read-write PRC1 Protect Bit 1 1 1 read-write 0 Writes protected. #0 1 Writes not protected. #1 PRC0 Protect Bit 0 0 0 read-write 0 Writes protected. #0 1 Writes not protected. #1 RSTSR0 Reset Status Register 0 0x410 8 read-write 0x00 0xF0 Reserved These bits are read as 0000. The write value should be 0000. 4 7 read-write LVD2RF Voltage Monitor 2 Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written with 0 after the reset flag is read as 1. 3 3 read-write zeroToClear modify 0 Voltage Monitor 2 reset not detected. #0 1 Voltage Monitor 2 reset detected. #1 LVD1RF Voltage Monitor 1 Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written with 0 after the reset flag is read as 1. 2 2 read-write zeroToClear modify 0 Voltage Monitor 1 reset not detected. #0 1 Voltage Monitor 1 reset detected. #1 LVD0RF Voltage Monitor 0 Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written with 0 after the reset flag is read as 1. 1 1 read-write zeroToClear modify 0 Voltage Monitor 0 reset not detected. #0 1 Voltage Monitor 0 reset detected. #1 PORF Power-On Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written with 0 after the reset flag is read as 1. 0 0 read-write zeroToClear modify 0 Power-on reset not detected. #0 1 Power-on reset detected. #1 RSTSR2 Reset Status Register 2 0x411 8 read-write 0x00 0xFE Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write CWSF Cold/Warm Start Determination Flag Note: Only 1 can be written to set the flag. 0 0 read-write oneToSet modify 0 Cold start #0 1 Warm start #1 RSTSR1 Reset Status Register 1 0x0C0 16 read-write 0x0000 0xE0F8 Reserved These bits are read as 000. The write value should be 000. 13 15 read-write SPERF SP Error Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 12 12 read-write zeroToClear modify 0 SP error reset not detected. #0 1 SP error reset detected. #1 BUSMRF Bus Master MPU Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 11 11 read-write zeroToClear modify 0 Bus Master MPU reset not detected. #0 1 Bus Master MPU reset detected. #1 BUSSRF Bus Slave MPU Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 10 10 read-write zeroToClear modify 0 Bus Slave MPU reset not detected. #0 1 Bus Slave MPU reset detected. #1 REERF RAM ECC Error Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 9 9 read-write zeroToClear modify 0 RAM ECC error reset not detected. #0 1 RAM ECC error reset detected. #1 RPERF RAM Parity Error Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 8 8 read-write zeroToClear modify 0 RAM parity error reset not detected. #0 1 RAM parity error reset detected. #1 Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write SWRF Software Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 2 2 read-write zeroToClear modify 0 Software reset not detected. #0 1 Software reset detected. #1 WDTRF Watchdog Timer Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 1 1 read-write zeroToClear modify 0 Watchdog timer reset not detected. #0 1 Watchdog timer reset detected. #1 IWDTRF Independent Watchdog Timer Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 0 0 read-write zeroToClear modify 0 Independent watchdog timer reset not detected. #0 1 Independent watchdog timer reset detected. #1 BKRACR Backup Register Access Control Register 0x0C6 8 read-write 0x06 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write BKRACS Backup Register Access Control Register 0 2 read-write 000 Access control disable. When System clock source is SOSC or LOCO. #000 110 Access control enable. System clock source is other than SOSC or LOCO. #110 others Setting prohibited true BUS BUS Control 0x40003000 0x02 64 registers 0x04 64 registers 0x08 64 registers 0x802 2 registers 0x80A 64 registers 0x812 48 registers 0x880 2 registers 0x1000 16 registers 0x1100 2 registers 0x1108 8 registers 0x1114 16 registers 0x1128 2 registers 0x1130 2 registers 0x1800 64 registers 0x1804 64 registers 4 0x4 M4I,M4D,SYS,DMA BUSMCNT%s Master Bus Control Register %s 0x1000 16 read-write 0x0000 0xFFFF IERES Ignore Error Responses 15 15 read-write 0 A bus error is reported #0 1 A bus error is not reported. #1 Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 0 14 read-write BUSSCNTFLI Slave Bus Control Register FLI 0x1100 16 read-write 0x0000 0xFFFF Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 15 read-write ARBMET Arbitration Method Specify the priority between groups 4 5 read-write 00 fixed priority #00 01 round-robin #01 others Setting prohibited true Reserved These bits are read as 0000. The write value should be 0000. 0 3 read-write 2 0x4 MBIU,RAM0 BUSSCNT%s Slave Bus Control Register %s 0x1108 16 read-write 0x0000 0xFFFF Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 15 read-write ARBMET Arbitration Method Specify the priority between groups 4 5 read-write 00 fixed priority #00 01 round-robin #01 others Setting prohibited true Reserved These bits are read as 0000. The write value should be 0000. 0 3 read-write 4 0x4 P0B,P2B,P3B,P4B BUSSCNT%s Slave Bus Control Register %s 0x1114 16 read-write 0x0000 0xFFFF Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 15 read-write ARBMET Arbitration Method Specify the priority between groups 4 5 read-write 00 fixed priority #00 01 round-robin #01 others Setting prohibited true Reserved These bits are read as 0000. The write value should be 0000. 0 3 read-write BUSSCNTP6B Slave Bus Control Register P6B 0x1128 16 read-write 0x0000 0xFFFF Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 15 read-write ARBMET Arbitration Method Specify the priority between groups 4 5 read-write 00 fixed priority #00 01 round-robin #01 others Setting prohibited true Reserved These bits are read as 0000. The write value should be 0000. 0 3 read-write BUSSCNTFBU Slave Bus Control Register FBU 0x1130 16 read-write 0x0000 0xFFFF Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 15 read-write ARBMET Arbitration Method Specify the priority between groups 4 5 read-write 00 fixed priority #00 01 round-robin #01 others Setting prohibited true Reserved These bits are read as 0000. The write value should be 0000. 0 3 read-write 4 0x10 1-4 BUS%sERRADD Bus Error Address Register %s 0x1800 32 read-only 0x00000000 0x00000000 BERAD Bus Error Address When a bus error occurs, It stores an error address. 0 31 read-only 4 0x10 1-4 BUS%sERRSTAT Bus Error Status Register %s 0x1804 8 read-only 0x00 0xFE ERRSTAT Bus Error Status When bus error assert, error flag occurs. 7 7 read-only 0 No bus error occurred #0 1 Bus error occurred. #1 Reserved These bits are read as 000000. 1 6 read-only ACCSTAT Error Access Status The status at the time of the error 0 0 read-only 0 Read access #0 1 Write Access #1 CAC Clock Frequency Accuracy Measurement Circuit 0x40044600 0x00 5 registers 0x06 6 registers CACR0 CAC Control Register 0 0x00 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write CFME Clock Frequency Measurement Enable. 0 0 read-write 0 Disable #0 1 Enable #1 CACR1 CAC Control Register 1 0x01 8 read-write 0x00 0xFF EDGES Valid Edge Select 6 7 read-write 00 Rising edge #00 01 Falling edge #01 10 Both rising and falling edges #10 11 Setting prohibited #11 TCSS Measurement Target Clock Frequency Division Ratio Select 4 5 read-write 00 No division #00 01 x 1/4 clock #01 10 x 1/8 clock #10 11 x 1/32 clock #11 FMCS Measurement Target Clock Select 1 3 read-write 000 Main clock #000 001 Sub-clock #001 010 HOCO clock #010 011 MOCO clock #011 100 LOCO clock #100 101 Peripheral module clock(PCLKB) #101 110 IWDTCLK clock #110 111 Setting prohibited #111 CACREFE CACREF Pin Input Enable 0 0 read-write 0 Disable #0 1 Enable #1 CACR2 CAC Control Register 2 0x02 8 read-write 0x00 0xFF DFS Digital Filter Selection 6 7 read-write 00 Digital filtering is disabled. #00 01 The sampling clock for the digital filter is the frequency measuring clock. #01 10 The sampling clock for the digital filter is the frequency measuring clock divided by 4. #10 11 The sampling clock for the digital filter is the frequency measuring clock divided by 16. #11 RCDS Measurement Reference Clock Frequency Division Ratio Select 4 5 read-write 00 1/32 clock #00 01 1/128 clock #01 10 1/1024 clock #10 11 1/8192 clock #11 RSCS Measurement Reference Clock Select 1 3 read-write 000 Main clock #000 001 Sub-clock #001 010 HOCO clock #010 011 MOCO clock #011 100 LOCO clock #100 101 Peripheral module clock(PCLKB) #101 110 IWDTCLK clock #110 111 Setting prohibited #111 RPS Reference Signal Select 0 0 read-write 0 CACREF pin input #0 1 Internal clock (internally generated signal) #1 CAICR CAC Interrupt Control Register 0x03 8 read-write 0x00 0xFF Reserved This bit is read as 0. The write value should be 0. 7 7 read-write OVFFCL OVFF Clear 6 6 write-only 0 No effect on operations #0 1 Clears the OVFF flag #1 MENDFCL MENDF Clear 5 5 write-only 0 No effect on operations #0 1 Clears the MENDF flag #1 FERRFCL FERRF Clear 4 4 write-only 0 No effect on operations #0 1 Clears the FERRF flag #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write OVFIE Overflow Interrupt Request Enable 2 2 read-write 0 Disable #0 1 Enable #1 MENDIE Measurement End Interrupt Request Enable 1 1 read-write 0 Disable #0 1 Enable #1 FERRIE Frequency Error Interrupt Request Enable 0 0 read-write 0 Disable #0 1 Enable #1 CASTR CAC Status Register 0x04 8 read-only 0x00 0xFF OVFF Counter Overflow Flag 2 2 read-only 0 The counter has not overflowed. #0 1 The counter has overflowed. #1 MENDF Measurement End Flag 1 1 read-only 0 Measurement is in progress. #0 1 Measurement has ended. #1 FERRF Frequency Error Flag 0 0 read-only 0 The clock frequency is within the range corresponding to the settings. #0 1 The clock frequency has deviated beyond the range corresponding to the settings (frequency error). #1 CAULVR CAC Upper-Limit Value Setting Register 0x06 16 read-write 0x0000 0xFFFF CAULVR CAULVR is a 16-bit readable/writable register that stores the upper-limit value of the frequency. 0 15 read-write CALLVR CAC Lower-Limit Value Setting Register 0x08 16 read-write 0x0000 0xFFFF CALLVR CALLVR is a 16-bit readable/writable register that stores the lower-limit value of the frequency. 0 15 read-write CACNTBR CAC Counter Buffer Register 0x0A 16 read-only 0x0000 0xFFFF CACNTBR CACNTBR is a 16-bit read-only register that retains the counter value at the time a valid reference signal edge is input 0 15 read-only CAN0 CAN0 Module 0x40050000 0x200 512 registers 0x204 512 registers 0x206 512 registers 0x207 512 registers 0x208 512 registers 0x209 512 registers 0x20A 512 registers 0x20B 512 registers 0x20C 512 registers 0x20D 512 registers 0x20E 512 registers 0x400 48 registers 0x42C 4 registers 0x820 32 registers 0x820 57 registers 32 0x10 0-31 MB%s_ID Mailbox Register 0x200 32 read-write 0x00000000 0x00000000 IDE ID Extension 31 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 30 read-write 0 Data frame #0 1 Remote frame #1 Reserved This bit is read as 0. The write value should be 0. 29 29 read-write SID Standard ID 18 28 read-write EID Extended ID 0 17 read-write 32 0x10 0-31 MB%s_DL Mailbox Register 0x204 16 read-write 0x0000 0x0000 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 15 read-write DLC Data Length Code 0 3 read-write 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 others Data length = 8 bytes true 32 0x10 0-31 MB%s_D0 Mailbox Register 0x206 8 read-write 0x00 0x00 DATA0 Data Bytes 0. DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write 32 0x10 0-31 MB%s_D1 Mailbox Register 0x207 8 read-write 0x00 0x00 DATA1 Data Bytes 1 DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write 32 0x10 0-31 MB%s_D2 Mailbox Register 0x208 8 read-write 0x00 0x00 DATA2 Data Bytes 2 DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write 32 0x10 0-31 MB%s_D3 Mailbox Register 0x209 8 read-write 0x00 0x00 DATA3 Data Bytes 3 DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write 32 0x10 0-31 MB%s_D4 Mailbox Register 0x20A 8 read-write 0x00 0x00 DATA4 Data Bytes 4 DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write 32 0x10 0-31 MB%s_D5 Mailbox Register 0x20B 8 read-write 0x00 0x00 DATA5 Data Bytes 5 DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write 32 0x10 0-31 MB%s_D6 Mailbox Register 0x20C 8 read-write 0x00 0x00 DATA6 Data Bytes 6 DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write 32 0x10 0-31 MB%s_D7 Mailbox Register 0x20D 8 read-write 0x00 0x00 DATA7 Data Bytes 7 DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write 32 0x10 0-31 MB%s_TS Mailbox Register 0x20E 16 read-write 0x0000 0x0000 TSH Time Stamp Lower Byte Bits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 15 read-write TSL Time Stamp Higher Byte Bits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write 8 0x4 0-7 MKR[%s] Mask Register 0x400 32 read-write 0x00000000 0x00000000 Reserved These bits are read as 000. The write value should be 000. 29 31 read-write SID Standard ID 18 28 read-write EID Extended ID 0 17 read-write 2 0x4 0,1 FIDCR%s FIFO Received ID Compare Registers 0x420 32 read-write 0x00000000 0x00000000 IDE ID Extension 31 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 30 read-write 0 Data frame #0 1 Remote frame #1 Reserved This bit is read as 0. The write value should be 0. 29 29 read-write SID Standard ID 18 28 read-write EID Extended ID 0 17 read-write MKIVLR Mask Invalid Register 0x428 32 read-write 0x00000000 0x00000000 MB31 mailbox 31 Mask Invalid 31 31 read-write 0 Mask valid #0 1 Mask invalid #1 MB30 mailbox 30 Mask Invalid 30 30 read-write 0 Mask valid #0 1 Mask invalid #1 MB29 mailbox 29 Mask Invalid 29 29 read-write 0 Mask valid #0 1 Mask invalid #1 MB28 mailbox 28 Mask Invalid 28 28 read-write 0 Mask valid #0 1 Mask invalid #1 MB27 mailbox 27 Mask Invalid 27 27 read-write 0 Mask valid #0 1 Mask invalid #1 MB26 mailbox 26 Mask Invalid 26 26 read-write 0 Mask valid #0 1 Mask invalid #1 MB25 mailbox 25 Mask Invalid 25 25 read-write 0 Mask valid #0 1 Mask invalid #1 MB24 mailbox 24 Mask Invalid 24 24 read-write 0 Mask valid #0 1 Mask invalid #1 MB23 mailbox 23 Mask Invalid 23 23 read-write 0 Mask valid #0 1 Mask invalid #1 MB22 mailbox 22 Mask Invalid 22 22 read-write 0 Mask valid #0 1 Mask invalid #1 MB21 mailbox 21 Mask Invalid 21 21 read-write 0 Mask valid #0 1 Mask invalid #1 MB20 mailbox 20 Mask Invalid 20 20 read-write 0 Mask valid #0 1 Mask invalid #1 MB19 mailbox 19 Mask Invalid 19 19 read-write 0 Mask valid #0 1 Mask invalid #1 MB18 mailbox 18 Mask Invalid 18 18 read-write 0 Mask valid #0 1 Mask invalid #1 MB17 mailbox 17 Mask Invalid 17 17 read-write 0 Mask valid #0 1 Mask invalid #1 MB16 mailbox 16 Mask Invalid 16 16 read-write 0 Mask valid #0 1 Mask invalid #1 MB15 mailbox 15 Mask Invalid 15 15 read-write 0 Mask valid #0 1 Mask invalid #1 MB14 mailbox 14 Mask Invalid 14 14 read-write 0 Mask valid #0 1 Mask invalid #1 MB13 mailbox 13 Mask Invalid 13 13 read-write 0 Mask valid #0 1 Mask invalid #1 MB12 mailbox 12 Mask Invalid 12 12 read-write 0 Mask valid #0 1 Mask invalid #1 MB11 mailbox 11 Mask Invalid 11 11 read-write 0 Mask valid #0 1 Mask invalid #1 MB10 mailbox 10 Mask Invalid 10 10 read-write 0 Mask valid #0 1 Mask invalid #1 MB9 mailbox 9 Mask Invalid 9 9 read-write 0 Mask valid #0 1 Mask invalid #1 MB8 mailbox 8 Mask Invalid 8 8 read-write 0 Mask valid #0 1 Mask invalid #1 MB7 mailbox 7 Mask Invalid 7 7 read-write 0 Mask valid #0 1 Mask invalid #1 MB6 mailbox 6 Mask Invalid 6 6 read-write 0 Mask valid #0 1 Mask invalid #1 MB5 mailbox 5 Mask Invalid 5 5 read-write 0 Mask valid #0 1 Mask invalid #1 MB4 mailbox 4 Mask Invalid 4 4 read-write 0 Mask valid #0 1 Mask invalid #1 MB3 mailbox 3 Mask Invalid 3 3 read-write 0 Mask valid #0 1 Mask invalid #1 MB2 mailbox 2 Mask Invalid 2 2 read-write 0 Mask valid #0 1 Mask invalid #1 MB1 mailbox 1 Mask Invalid 1 1 read-write 0 Mask valid #0 1 Mask invalid #1 MB0 mailbox 0 Mask Invalid 0 0 read-write 0 Mask valid #0 1 Mask invalid #1 MIER Mailbox Interrupt Enable Register 0x42C 32 read-write 0x00000000 0x00000000 MB31 mailbox 31 Interrupt Enable 31 31 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB30 mailbox 30 Interrupt Enable 30 30 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB29 mailbox 29 Interrupt Enable 29 29 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB28 mailbox 28 Interrupt Enable 28 28 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB27 mailbox 27 Interrupt Enable 27 27 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB26 mailbox 26 Interrupt Enable 26 26 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB25 mailbox 25 Interrupt Enable 25 25 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB24 mailbox 24 Interrupt Enable 24 24 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB23 mailbox 23 Interrupt Enable 23 23 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB22 mailbox 22 Interrupt Enable 22 22 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB21 mailbox 21 Interrupt Enable 21 21 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB20 mailbox 20 Interrupt Enable 20 20 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB19 mailbox 19 Interrupt Enable 19 19 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB18 mailbox 18 Interrupt Enable 18 18 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB17 mailbox 17 Interrupt Enable 17 17 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB16 mailbox 16 Interrupt Enable 16 16 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB15 mailbox 15 Interrupt Enable 15 15 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB14 mailbox 14 Interrupt Enable 14 14 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB13 mailbox 13 Interrupt Enable 13 13 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB12 mailbox 12 Interrupt Enable 12 12 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB11 mailbox 11 Interrupt Enable 11 11 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB10 mailbox 10 Interrupt Enable 10 10 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB9 mailbox 9 Interrupt Enable 9 9 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB8 mailbox 8 Interrupt Enable 8 8 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB7 mailbox 7 Interrupt Enable 7 7 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB6 mailbox 6 Interrupt Enable 6 6 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB5 mailbox 5 Interrupt Enable 5 5 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB4 mailbox 4 Interrupt Enable 4 4 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB3 mailbox 3 Interrupt Enable 3 3 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB2 mailbox 2 Interrupt Enable 2 2 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB1 mailbox 1 Interrupt Enable 1 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB0 mailbox 0 Interrupt Enable 0 0 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MIER_FIFO Mailbox Interrupt Enable Register for FIFO Mailbox Mode MIER 0x42C 32 read-write 0x00000000 0x00000000 MB29 Receive FIFO Interrupt Generation Timing Control 29 29 read-write 0 Every time reception is completed #0 1 When the receive FIFO becomes buffer warning by completion of reception #1 MB28 Receive FIFO Interrupt Enable 28 28 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 Reserved These bits are read as 00. The write value should be 00. 26 27 read-write MB25 Transmit FIFO Interrupt Generation Timing Control 25 25 read-write 0 Every time transmission is completed #0 1 When the transmit FIFO becomes empty due to completion of transmission #1 MB24 Transmit FIFO Interrupt Enable 24 24 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB23 mailbox 23 Interrupt Enable 23 23 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB22 mailbox 22 Interrupt Enable 22 22 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB21 mailbox 21 Interrupt Enable 21 21 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB20 mailbox 20 Interrupt Enable 20 20 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB19 mailbox 19 Interrupt Enable 19 19 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB18 mailbox 18 Interrupt Enable 18 18 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB17 mailbox 17 Interrupt Enable 17 17 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB16 mailbox 16 Interrupt Enable 16 16 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB15 mailbox 15 Interrupt Enable 15 15 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB14 mailbox 14 Interrupt Enable 14 14 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB13 mailbox 13 Interrupt Enable 13 13 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB12 mailbox 12 Interrupt Enable 12 12 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB11 mailbox 11 Interrupt Enable 11 11 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB10 mailbox 10 Interrupt Enable 10 10 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB9 mailbox 9 Interrupt Enable 9 9 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB8 mailbox 8 Interrupt Enable 8 8 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB7 mailbox 7 Interrupt Enable 7 7 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB6 mailbox 6 Interrupt Enable 6 6 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB5 mailbox 5 Interrupt Enable 5 5 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB4 mailbox 4 Interrupt Enable 4 4 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB3 mailbox 3 Interrupt Enable 3 3 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB2 mailbox 2 Interrupt Enable 2 2 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB1 mailbox 1 Interrupt Enable 1 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB0 mailbox 0 Interrupt Enable 0 0 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 32 0x1 0-31 MCTL_TX[%s] Message Control Register for Transmit 0x820 8 read-write 0x00 0xFF TRMREQ Transmit Mailbox Request 7 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 RECREQ Receive Mailbox Request 6 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write ONESHOT One-Shot Enable 4 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 SENTDATA Transmission Complete Flag 0 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 32 0x1 0-31 MCTL_RX[%s] Message Control Register for Receive MCTL_TX[%s] 0x820 8 read-write 0x00 0xFF TRMREQ Transmit Mailbox Request 7 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 RECREQ Receive Mailbox Request 6 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write ONESHOT One-Shot Enable 4 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write MSGLOST Message Lost Flag (Receive mailbox setting enabled) 2 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 1 read-only 0 Message valid #0 1 Message being updated #1 NEWDATA Reception Complete Flag 0 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 CTLR Control Register 0x840 16 read-write 0x0500 0xFFFF Reserved These bits are read as 00. The write value should be 00. 14 15 read-write RBOC Forcible Return From Bus-Off 13 13 read-write 0 Nothing occurred #0 1 Forcible return from bus-off #1 BOM Bus-Off Recovery Mode by a program request 11 12 read-write 00 Normal mode (ISO11898-1 compliant) #00 01 Entry to CAN halt mode automatically at bus-off entry #01 10 Entry to CAN halt mode automatically at bus-off end #10 11 Entry to CAN halt mode (during bus-off recovery period) #11 SLPM CAN Sleep Mode 10 10 read-write 0 Other than CAN sleep mode #0 1 CAN sleep mode #1 CANM CAN Operating Mode Select 8 9 read-write 00 CAN operation mode #00 01 CAN reset mode #01 10 CAN halt mode #10 11 CAN reset mode (forcible transition) #11 TSPS Time Stamp Prescaler Select 6 7 read-write 00 Every bit time #00 01 Every 2-bit time #01 10 Every 4-bit time #10 11 Every 8-bit time #11 TSRC Time Stamp Counter Reset Command 5 5 read-write 0 Nothing occurred #0 1 Reset #1 TPM Transmission Priority Mode Select 4 4 read-write 0 ID priority transmit mode #0 1 Mailbox number priority transmit mode #1 MLM Message Lost Mode Select 3 3 read-write 0 Overwrite mode #0 1 Overrun mode #1 IDFM ID Format Mode Select 1 2 read-write 00 Standard ID mode.All mailboxes (including FIFO mailboxes) handle only standard Ids. #00 01 Extended ID mode.All mailboxes (including FIFO mailboxes) handle only extended IDs. #01 10 Mixed ID mode.All mailboxes (including FIFO mailboxes) handle both standard IDs and extended IDs. Standard IDs or extended IDs are specified by using the IDE bit in the corresponding mailbox in normal mailbox mode. In FIFO mailbox mode, the IDE bit in the corresponding mailbox is used for mailboxes [0] to [23], the IDE bits in FIDCR0 and FIDCR1 are used for the receive FIFO, and the IDE bit in mailbox [24] is used for the transmit FIFO. #10 11 Do not use this combination #11 MBM CAN Mailbox Mode Select 0 0 read-write 0 Normal mailbox mode #0 1 FIFO mailbox mode #1 STR Status Register 0x842 16 read-only 0x0500 0xFFFF Reserved This bit is read as 0. 15 15 read-only RECST Receive Status Flag (receiver) 14 14 read-only 0 Bus idle or transmission in progress #0 1 Reception in progress #1 TRMST Transmit Status Flag (transmitter) 13 13 read-only 0 Bus idle or reception in progress #0 1 Transmission in progress or in bus-off state #1 BOST Bus-Off Status Flag 12 12 read-only 0 Not in bus-off state #0 1 In bus-off state #1 EPST Error-Passive Status Flag 11 11 read-only 0 Not in error-passive state #0 1 In error-passive state #1 SLPST CAN Sleep Status Flag 10 10 read-only 0 Not in CAN sleep mode #0 1 In CAN sleep mode #1 HLTST CAN Halt Status Flag 9 9 read-only 0 Not in CAN halt mode #0 1 In CAN halt mode #1 RSTST CAN Reset Status Flag 8 8 read-only 0 Not in CAN reset mode #0 1 In CAN reset mode #1 EST Error Status Flag 7 7 read-only 0 No error occurred #0 1 Error occurred #1 TABST Transmission Abort Status Flag 6 6 read-only 0 No mailbox with TRMABT bit = 1 #0 1 Mailbox(es) with TRMABT bit = 1 #1 FMLST FIFO Mailbox Message Lost Status Flag 5 5 read-only 0 RFMLF bit = 0 #0 1 RFMLF bit = 1 #1 NMLST Normal Mailbox Message Lost Status Flag 4 4 read-only 0 No mailbox with MSGLOST bit = 1 #0 1 Mailbox(es) with MSGLOST bit = 1 #1 TFST Transmit FIFO Status Flag 3 3 read-only 0 Transmit FIFO is full #0 1 Transmit FIFO is not full #1 RFST Receive FIFO Status Flag 2 2 read-only 0 No message in receive FIFO (empty) #0 1 Message in receive FIFO #1 SDST SENTDATA Status Flag 1 1 read-only 0 No mailbox with SENTDATA bit = 1 #0 1 Mailbox(es) with SENTDATA bit = 1 #1 NDST NEWDATA Status Flag 0 0 read-only 0 No mailbox with NEWDATA bit = 1 #0 1 Mailbox(es) with NEWDATA bit = 1 #1 BCR Bit Configuration Register 0x844 32 read-write 0x00000000 0xFFFFFFFF TSEG1 Time Segment 1 Control 28 31 read-write 0011 4 Tq #0011 0100 5 Tq #0100 0101 6 Tq #0101 0110 7 Tq #0110 0111 8 Tq #0111 1000 9 Tq #1000 1001 10 Tq #1001 1010 11 Tq #1010 1011 12 Tq #1011 1100 13 Tq #1100 1101 14 Tq #1101 1110 15 Tq #1110 1111 16 Tq #1111 others Setting prohibited true Reserved These bits are read as 00. The write value should be 00. 26 27 read-write BRP Prescaler Division Ratio Select . These bits set the frequency of the CAN communication clock (fCANCLK). 16 25 read-write Reserved These bits are read as 00. The write value should be 00. 14 15 read-write SJW Resynchronization Jump Width Control 12 13 read-write 00 1 Tq #00 01 2 Tq #01 10 3 Tq #10 11 4 Tq #11 Reserved This bit is read as 0. The write value should be 0. 11 11 read-write TSEG2 Time Segment 2 Control 8 10 read-write 000 Setting prohibited #000 001 2 Tq #001 010 3 Tq #010 011 4 Tq #011 100 5 Tq #100 101 6 Tq #101 110 7 Tq #110 111 8 Tq #111 Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write CCLKS CAN Clock Source Selection 0 0 read-write 0 PCLK (generated by the PLL clock) #0 1 CANMCLK (generated by the main clock) #1 RFCR Receive FIFO Control Register 0x848 8 read-write 0x80 0xFF RFEST Receive FIFO Empty Status Flag 7 7 read-only 0 Unread message in receive FIFO #0 1 No unread message in receive FIFO #1 RFWST Receive FIFO Buffer Warning Status Flag 6 6 read-only 0 Receive FIFO is not buffer warning #0 1 Receive FIFO is buffer warning (3 unread messages) #1 RFFST Receive FIFO Full Status Flag 5 5 read-only 0 Receive FIFO is not full #0 1 Receive FIFO is full (4 unread messages) #1 RFMLF Receive FIFO Message Lost Flag 4 4 read-write 0 No receive FIFO message lost has occurred #0 1 Receive FIFO message lost has occurred #1 RFUST Receive FIFO Unread Message Number Status 1 3 read-only 000 No unread message #000 001 1 unread message #001 010 2 unread messages #010 011 3 unread messages #011 100 4 unread messages #100 others Setting prohibited true RFE Receive FIFO Enable 0 0 read-write 0 Receive FIFO disabled #0 1 Receive FIFO enabled #1 RFPCR Receive FIFO Pointer Control Register 0x849 8 write-only 0x00 0x00 RFPCR The CPU-side pointer for the receive FIFO is incremented by writing FFh to RFPCR. 0 7 write-only TFCR Transmit FIFO Control Register 0x84A 8 read-write 0x80 0xFF TFEST Transmit FIFO Empty Status 7 7 read-only 0 Unsent message in transmit FIFO #0 1 No unsent message in transmit FIFO #1 TFFST Transmit FIFO Full Status 6 6 read-only 0 Transmit FIFO is not full #0 1 Transmit FIFO is full (4 unsent messages) #1 Reserved These bits are read as 00. The write value should be 00. 4 5 read-write TFUST Transmit FIFO Unsent Message Number Status 1 3 read-only 000 No unsent message #000 001 1 unsent message #001 010 2 unsent messages #010 011 3 unsent messages #011 100 4 unsent messages #100 others Setting prohibited true TFE Transmit FIFO Enable 0 0 read-write 0 Transmit FIFO disabled #0 1 Transmit FIFO enabled #1 TFPCR Transmit FIFO Pointer Control Register 0x84B 8 write-only 0x00 0x00 TFPCR The CPU-side pointer for the transmit FIFO is incremented by writing FFh to TFPCR. 0 7 write-only EIER Error Interrupt Enable Register 0x84C 8 read-write 0x00 0xFF BLIE Bus Lock Interrupt Enable 7 7 read-write 0 Bus lock interrupt disabled #0 1 Bus lock interrupt enabled #1 OLIE Overload Frame Transmit Interrupt Enable 6 6 read-write 0 Overload frame transmit interrupt disabled #0 1 Overload frame transmit interrupt enabled #1 ORIE Overrun Interrupt Enable 5 5 read-write 0 Receive overrun interrupt disabled #0 1 Receive overrun interrupt enabled #1 BORIE Bus-Off Recovery Interrupt Enable 4 4 read-write 0 Bus-off recovery interrupt disabled #0 1 Bus-off recovery interrupt enabled #1 BOEIE Bus-Off Entry Interrupt Enable 3 3 read-write 0 Bus-off entry interrupt disabled #0 1 Bus-off entry interrupt enabled #1 EPIE Error-Passive Interrupt Enable 2 2 read-write 0 Error-passive interrupt disabled #0 1 Error-passive interrupt enabled #1 EWIE Error-Warning Interrupt Enable 1 1 read-write 0 Error-warning interrupt disabled #0 1 Error-warning interrupt enabled #1 BEIE Bus Error Interrupt Enable 0 0 read-write 0 Bus error interrupt disabled #0 1 Bus error interrupt enabled #1 EIFR Error Interrupt Factor Judge Register 0x84D 8 read-write 0x00 0xFF BLIF Bus Lock Detect Flag 7 7 read-write 0 No bus lock detected #0 1 Bus lock detected #1 OLIF Overload Frame Transmission Detect Flag 6 6 read-write 0 No overload frame transmission detected #0 1 Overload frame transmission detected #1 ORIF Receive Overrun Detect Flag 5 5 read-write 0 No receive overrun detected #0 1 Receive overrun detected #1 BORIF Bus-Off Recovery Detect Flag 4 4 read-write 0 No bus-off recovery detected #0 1 Bus-off recovery detected #1 BOEIF Bus-Off Entry Detect Flag 3 3 read-write 0 No bus-off entry detected #0 1 Bus-off entry detected #1 EPIF Error-Passive Detect Flag 2 2 read-write 0 No error-passive detected #0 1 Error-passive detected #1 EWIF Error-Warning Detect Flag 1 1 read-write 0 No error-warning detected #0 1 Error-warning detected #1 BEIF Bus Error Detect Flag 0 0 read-write 0 No bus error detected #0 1 Bus error detected #1 RECR Receive Error Count Register 0x84E 8 read-only 0x00 0xFF RECR Receive error count function RECR increments or decrements the counter value according to the error status of the CAN module during reception. 0 7 read-only TECR Transmit Error Count Register 0x84F 8 read-only 0x00 0xFF TECR Transmit error count function TECR increments or decrements the counter value according to the error status of the CAN module during transmission. 0 7 read-only ECSR Error Code Store Register 0x850 8 read-write 0x00 0xFF EDPM Error Display Mode Select 7 7 read-write 0 Output of first detected error code #0 1 Output of accumulated error code #1 ADEF ACK Delimiter Error Flag 6 6 read-write 0 No ACK delimiter error detected #0 1 ACK delimiter error detected #1 BE0F Bit Error (dominant) Flag 5 5 read-write 0 No bit error (dominant) detected #0 1 Bit error (dominant) detected #1 BE1F Bit Error (recessive) Flag 4 4 read-write 0 No bit error (recessive) detected #0 1 Bit error (recessive) detected #1 CEF CRC Error Flag 3 3 read-write 0 No CRC error detected #0 1 CRC error detected #1 AEF ACK Error Flag 2 2 read-write 0 No ACK error detected #0 1 ACK error detected #1 FEF Form Error Flag 1 1 read-write 0 No form error detected #0 1 Form error detected #1 SEF Stuff Error Flag 0 0 read-write 0 No stuff error detected #0 1 Stuff error detected #1 CSSR Channel Search Support Register 0x851 8 read-write 0x00 0x00 CSSR When the value for the channel search is input, the channel number is output to MSSR. 0 7 read-write MSSR Mailbox Search Status Register 0x852 8 read-only 0x80 0xFF SEST Search Result Status 7 7 read-only 0 Search result found #0 1 No search result #1 Reserved These bits are read as 00. 5 6 read-only MBNST Search Result Mailbox Number Status These bits output the smallest mailbox number that is searched in each mode of MSMR. 0 4 read-only MSMR Mailbox Search Mode Register 0x853 8 read-write 0x00 0xFF Reserved These bits are read as 000000. The write value should be 000000. 2 7 read-write MBSM Mailbox Search Mode Select 0 1 read-write 00 Receive mailbox search mode #00 01 Transmit mailbox search mode #01 10 Message lost search mode #10 11 Channel search mode #11 TSR Time Stamp Register 0x854 16 read-only 0x0000 0xFFFF TSR Free-running counter value for the time stamp function 0 15 read-only AFSR Acceptance Filter Support Register 0x856 16 read-write 0x0000 0x0000 AFSR After the standard ID of a received message is written, the value converted for data table search can be read. 0 15 read-write TCR Test Control Register 0x858 8 read-write 0x00 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write TSTM CAN Test Mode Select 1 2 read-write 00 Other than CAN test mode #00 01 Listen-only mode #01 10 Self-test mode 0 (external loopback) #10 11 Self-test mode 1 (internal loopback) #11 TSTE CAN Test Mode Enable 0 0 read-write 0 CAN test mode disabled #0 1 CAN test mode enabled #1 DBG Debug Function 0x4001B000 0x00 4 registers 0x10 4 registers 0x20 4 registers DBGSTR Debug Status Register 0x000 32 read-only 0x00000000 0xFFFFFFFF Reserved These bits are read as 00. 30 31 read-only CDBGPWRUPACK Debug power-up acknowledge 29 29 read-only 0 Debug power-up request is not acknowledged #0 1 Debug power-up request is acknowledged #1 CDBGPWRUPREQ Debug power-up request 28 28 read-only 0 OCD is not requesting debug power-up #0 1 OCD is requesting debug power-up #1 Reserved These bits are read as 0000000000000000000000000000. 0 27 read-only DBGSTOPCR Debug Stop Control Register 0x010 32 read-write 0x00000003 0xFFFFFFFF Reserved These bits are read as 000000. The write value should be 000000. 26 31 read-write DBGSTOP_RECCR Mask bit for RAM ECC error reset/interrupt 25 25 read-write 0 Enable RAM ECC error reset/interrupt #0 1 Mask RAM ECC error reset/interrupt #1 DBGSTOP_RPER Mask bit for RAM parity error reset/interrupt 24 24 read-write 0 Enable RAM parity error reset/interrupt #0 1 Mask RAM parity error reset/interrupt #1 Reserved These bits are read as 00000. The write value should be 00000. 19 23 read-write DBGSTOP_LVD b18: Mask bit for LVD2 reset/interrupt (0:enable / 1:Mask) b17: Mask bit for LVD1 reset/interrupt (0:enable / 1:Mask) b16: Mask bit for LVD0 reset (0:enable / 1:Mask) 16 18 read-write Reserved These bits are read as 00000000000000. The write value should be 00000000000000. 2 15 read-write DBGSTOP_WDT Mask bit for WDT reset/interrupt 1 1 read-write 0 Mask WDT reset/interrupt #0 1 Enable WDT reset #1 DBGSTOP_IWDT Mask bit for IWDT reset/interrupt 0 0 read-write 0 Mask IWDT reset/interrupt #0 1 Enable IWDT reset #1 TRACECTR Trace Control Register 0x020 32 read-write 0x00000000 0xFFFFFFFF ENETBFULL Enable bit for halt request by ETB full 31 31 read-write 0 ETB full does not cause CPU halt #0 1 ETB full cause CPU halt #1 Reserved These bits are read as 0000000000000000000000000000000. The write value should be 0000000000000000000000000000000. 0 30 read-write CRC CRC Calculator 0x40074000 0x00 2 registers 0x04 4 registers 0x04 1 registers 0x08 4 registers 0x08 2 registers 0x08 1 registers 0x0C 2 registers CRCCR0 CRC Control Register0 0x00 8 read-write 0x00 0xFF DORCLR CRCDOR Register Clear 7 7 write-only 0 No effect. #0 1 Clears the CRCDOR register. #1 LMS CRC Calculation Switching 6 6 read-write 0 Generates CRC for LSB first communication. #0 1 Generates CRC for MSB first communication. #1 Reserved These bits are read as 000. The write value should be 000. 3 5 read-write GPS CRC Generating Polynomial Switching 0 2 read-write 000 No calculation is executed. #000 001 8-bit CRC-8 (X8 + X2 + X + 1) #001 010 16-bit CRC-16 (X16 + X15 + X2 + 1) #010 011 16-bit CRC-CCITT (X16 + X12 + X5 + 1) #011 100 32-bit CRC-32 (X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1) #100 101 32-bit CRC-32C (X32+X28+X27+X26+ X25+X23+X22+X20+X19+X18+X14+X13+X11+X10+X9+X8+X6+1) #101 others No calculation is executed. true CRCCR1 CRC Control Register1 0x01 8 read-write 0x00 0xFF CRCSEN Snoop enable bit 7 7 read-write 0 Disabled #0 1 Enabled #1 CRCSWR Snoop-on-write/read switch bit 6 6 read-write 0 Snoop-on-read #0 1 Snoop-on-write #1 Reserved These bits are read as 000000. The write value should be 000000. 0 5 read-write CRCDIR CRC Data Input Register 0x04 32 read-write 0x00000000 0xFFFFFFFF CRCDIR Calculation input Data (Case of CRC-32, CRC-32C ) 0 31 read-write CRCDIR_BY CRC Data Input Register (byte access) CRCDIR 0x04 8 read-write 0x00 0xFF CRCDIR_BY Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT ) 0 7 read-write CRCDOR CRC Data Output Register 0x08 32 read-write 0x00000000 0xFFFFFFFF CRCDOR Calculation output Data (Case of CRC-32, CRC-32C ) 0 31 read-write CRCDOR_HA CRC Data Output Register (halfword access) CRCDOR 0x08 16 read-write 0x0000 0xFFFF CRCDOR_HA Calculation output Data (Case of CRC-16 or CRC-CCITT ) 0 15 read-write CRCDOR_BY CRC Data Output Register(byte access) CRCDOR 0x08 8 read-write 0x00 0xFF CRCDOR_BY Calculation output Data (Case of CRC-8 ) 0 7 read-write CRCSAR Snoop Address Register 0x0C 16 read-write 0x0000 0xFFFF Reserved These bits are read as 00. The write value should be 00. 14 15 read-write CRCSA snoop address bit Set the I/O register address to snoop 0 13 read-write 0x0003 SCI0.TDR 0x0003 0x0005 SCI0.RDR 0x0005 0x0023 SCI1.TDR 0x0023 0x0025 SCI1.RDR 0x0025 0x0043 SCI2.TDR 0x0043 0x0045 SCI2.RDR 0x0045 0x0063 SCI3.TDR 0x0063 0x0065 SCI3.RDR 0x0065 0x0083 SCI4.TDR 0x0083 0x0085 SCI4.RDR 0x0085 0x0123 SCI9.TDR 0x0123 0x0125 SCI9.RDR 0x0125 others Settings other than above are prohibited. true CTSU Capacitive Touch Sensing Unit 0x40081000 0x00 30 registers CTSUCR0 CTSU Control Register 0 0x00 8 read-write 0x00 0xFF CTSUINIT CTSU Control Block Initialization 4 4 read-write 0 Writing a 0 has no effect, this bit is read as 0. #0 1 initializes the CTSU control block and registers. #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write CTSUSNZ CTSU Wait State Power-Saving Enable 2 2 read-write 0 Power-saving function during wait state is disabled. #0 1 Power-saving function during wait state is enabled. #1 CTSUCAP CTSU Measurement Operation Start Trigger Select 1 1 read-write 0 Software trigger. #0 1 External trigger. #1 CTSUSTRT CTSU Measurement Operation Start 0 0 read-write 0 Measurement operation stops. #0 1 Measurement operation starts. #1 CTSUCR1 CTSU Control Register 1 0x01 8 read-write 0x00 0xFF CTSUMD CTSU Measurement Mode Select 6 7 read-write 00 Self-capacitance single scan mode #00 01 Self-capacitance multi-scan mode #01 10 Mutual capacitance simple scan mode #10 11 Mutual capacitance full scan mode #11 CTSUCLK CTSU Operating Clock Select 4 5 read-write 00 PCLK #00 01 PCLK/2 (PCLK divided by 2) #01 10 PCLK/2 (PCLK divided by 4) #10 11 Setting prohibited #11 CTSUATUNE1 CTSU Power Supply Capacity Adjustment 3 3 read-write 0 Normal output #0 1 High-current output #1 CTSUATUNE0 CTSU Power Supply Operating Mode Setting 2 2 read-write 0 Normal operating mode #0 1 Low-voltage operating mode #1 CTSUCSW CTSU LPF Capacitance Charging Control 1 1 read-write 0 Turned off capacitance switch #0 1 Turned on capacitance switch #1 CTSUPON CTSU Power Supply Enable 0 0 read-write 0 Powered off the CTSU #0 1 Powered on the CTSU #1 CTSUSDPRS CTSU Synchronous Noise Reduction Setting Register 0x02 8 read-write 0x00 0xFF Reserved This bit is read as 0. The write value should be 0. 7 7 read-write CTSUSOFF CTSU High-Pass Noise Reduction Function Off Setting 6 6 read-write 0 High-pass noise reduction function turned on #0 1 High-pass noise reduction function turned off #1 CTSUPRMODE CTSU Base Period and Pulse Count Setting 4 5 read-write 00 510 pulses #00 01 126 pulses #01 10 62 pulses (recommended setting value) #10 11 Setting prohibited #11 CTSUPRRATIO CTSU Measurement Time and Pulse Count Adjustment Recommended setting: 3 (0011b) 0 3 read-write CTSUSST CTSU Sensor Stabilization Wait Control Register 0x03 8 read-write 0x00 0xFF CTSUSST CTSU Sensor Stabilization Wait Control NOTE: The value of these bits should be fixed to 00010000b. 0 7 read-write CTSUMCH0 CTSU Measurement Channel Register 0 0x04 8 read-write 0x3F 0xFF Reserved These bits are read as 00. The write value should be 00. 6 7 read-write CTSUMCH0 CTSU Measurement Channel 0. Note1: Writing to these bits is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] bits = 00b). Note2: If the value of CTSUMCH0 was set to b'111111 in mode other than self-capacitor single scan mode, the measurement is stopped. 0 5 read-write CTSUMCH0 The value of CTSUMCH0 indicate to channel to be measured. true CTSUMCH1 CTSU Measurement Channel Register 1 0x05 8 read-write 0x3F 0xFF Reserved These bits are read as 00. The write value should be 00. 6 7 read-write CTSUMCH1 CTSU Measurement Channel 1 Note1: If the value of CTSUMCH1 was set to b'111111, the measurement is stopped. 0 5 read-only CTSUMCH1 The value of CTSUMCH1 indicate to channel to be measured. true CTSUCHAC0 CTSU Channel Enable Control Register 0 0x06 8 read-write 0x00 0xFF CTSUCHAC0 CTSU Channel Enable Control 0. 0: Not measurement target 1: Measurement target Note: CTSUCHAC0[0] corresponds to TS00 and CTSUCHAC0[7] corresponds to TS07. but the write value of CTSUCHAC0[2] should be 0. 0 7 read-write CTSUCHAC0 TS pin which correspond to the bit number of CTSUCHAC0 register set whether the measurement target. true CTSUCHAC1 CTSU Channel Enable Control Register 1 0x07 8 read-write 0x00 0xFF CTSUCHAC1 CTSU Channel Enable Control 1. 0: Not measurement target 1: Measurement target Note: CTSUCHAC1[0] corresponds to TS08 and CTSUCHAC1[7] corresponds to TS15. 0 7 read-write CTSUCHAC1 TS pin which correspond to the bit number of CTSUCHAC1 register set whether the measurement target. true CTSUCHAC2 CTSU Channel Enable Control Register 2 0x08 8 read-write 0x00 0xFF CTSUCHAC2 CTSU Channel Enable Control 2. 0: Not measurement target 1: Measurement target Note: CTSUCHAC2[0] corresponds to TS16 and CTSUCHAC2[7] corresponds to TS23. 0 7 read-write CTSUCHAC2 TS pin which correspond to the bit number of CTSUCHAC2 register set whether the measurement target. true CTSUCHAC3 CTSU Channel Enable Control Register 3 0x09 8 read-write 0x00 0xFF CTSUCHAC3 CTSU Channel Enable Control 3. 0: Not measurement target 1: Measurement target Note: CTSUCHAC3[0] corresponds to TS24 and CTSUCHAC3[7] corresponds to TS31. 0 7 read-write CTSUCHAC3 TS pin which correspond to the bit number of CTSUCHAC3 register set whether the measurement target. true CTSUCHAC4 CTSU Channel Enable Control Register 4 0x0A 8 read-write 0x00 0xFF Reserved These bits are read as 0000. The write value should be 0000. 4 7 read-write CTSUCHAC4 CTSU Channel Enable Control 4. 0: Not measurement target 1: Measurement target Note: CTSUCHAC4[0] corresponds to TS32 and CTSUCHAC4[3] corresponds to TS35. but the write value of CTSUCHAC0[4],CTSUCHAC4[5],CTSUCHAC4[6],CTSUCHAC4[7] should be 0. 0 3 read-write CTSUCHAC4 TS pin which correspond to the bit number of CTSUCHAC4 register set whether the measurement target. true CTSUCHTRC0 CTSU Channel Transmit/Receive Control Register 0 0x0B 8 read-write 0x00 0xFF CTSUCHTRC0 CTSU Channel Transmit/Receive Control 0 0 7 read-write 0 Reception #0 1 Transmission #1 CTSUCHTRC1 CTSU Channel Transmit/Receive Control Register 1 0x0C 8 read-write 0x00 0xFF CTSUCHTRC1 CTSU Channel Transmit/Receive Control 1 0 7 read-write 0 Reception #0 1 Transmission #1 CTSUCHTRC2 CTSU Channel Transmit/Receive Control Register 3 0x0D 8 read-write 0x00 0xFF CTSUCHTRC2 CTSU Channel Transmit/Receive Control 2 0 7 read-write 0 Reception #0 1 Transmission #1 CTSUCHTRC3 CTSU Channel Transmit/Receive Control Register 3 0x0E 8 read-write 0x00 0xFF CTSUCHTRC3 CTSU Channel Transmit/Receive Control 3 0 7 read-write 0 Reception #0 1 Transmission #1 CTSUCHTRC4 CTSU Channel Transmit/Receive Control Register 4 0x0F 8 read-write 0x00 0xFF Reserved These bits are read as 0000. The write value should be 0000. 4 7 read-write CTSUCHAC4 CTSU Channel Transmit/Receive Control 4 0 3 read-write 0 Reception #0 1 Transmission #1 CTSUDCLKC CTSU High-Pass Noise Reduction Control Register 0x10 8 read-write 0x00 0xFF Reserved These bits are read as 00. The write value should be 00. 6 7 read-write CTSUSSCNT CTSU Diffusion Clock Mode Control NOTE: This bit should be set to 11b. 4 5 read-write Reserved These bits are read as 00. The write value should be 00. 2 3 read-write CTSUSSMOD CTSU Diffusion Clock Mode Select NOTE: This bit should be set to 00b. 0 1 read-write CTSUST CTSU Status Register 0x11 8 read-write 0x00 0xFF CTSUPS CTSU Mutual Capacitance Status Flag 7 7 read-only 0 First measurement #0 1 Second measurement #1 CTSUROVF CTSU Reference Counter Overflow Flag 6 6 read-write 0 No overflow #0 1 An overflow #1 CTSUSOVF CTSU Sensor Counter Overflow Flag 5 5 read-write 0 No overflow #0 1 An overflow #1 CTSUDTSR CTSU Data Transfer Status Flag 4 4 read-only 0 Measurement result has been read #0 1 Measurement result has not been read #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write CTSUSTC CTSU Measurement Status Counter 0 2 read-only 000 Status 0 #000 001 Status 1 #001 010 Status 2 #010 011 Status 3 #011 100 Status 4 #100 101 Status 5 #101 CTSUSSC CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register 0x12 16 read-write 0x0000 0xFFFF Reserved These bits are read as 0000. The write value should be 0000. 12 15 read-write CTSUSSDIV CTSU Spectrum Diffusion Frequency Division Setting 8 11 read-write 0000 4.00 <= fb #0000 0001 2.00 <= fb < 4.00 #0001 0010 1.33 <= fb < 2.00 #0010 0011 1.00 <= fb < 1.33 #0011 0100 0.80 <= fb < 1.00 #0100 0101 0.67 <= fb < 0.80 #0101 0110 0.57 <= fb < 0.67 #0110 0111 0.50 <= fb < 0.57 #0111 1000 0.44 <= fb < 0.50 #1000 1001 0.40 <= fb < 0.44 #1001 1010 0.36 <= fb < 0.40 #1010 1011 0.33 <= fb < 0.36 #1011 1100 0.31 <= fb < 0.33 #1100 1101 0.29 <= fb < 0.31 #1101 1110 0.27 <= fb < 0.29 #1110 1111 fb < 0.27 #1111 Reserved These bits are read as 00000000. The write value should be 00000000. 0 7 read-write CTSUSO0 CTSU Sensor Offset Register 0 0x14 16 read-write 0x0000 0xFFFF CTSUSNUM CTSU Measurement Count Setting 10 15 read-write CTSUSO CTSU Sensor Offset Adjustment Current offset amount is CTSUSO ( 0 to 1023 ) 0 9 read-write CTSUSO1 CTSU Sensor Offset Register 1 0x16 16 read-write 0x0000 0xFFFF Reserved This bit is read as 0. The write value should be 0. 15 15 read-write CTSUICOG CTSU ICO Gain Adjustment 13 14 read-write 00 100 percent gain #00 01 66 percent gain #01 10 50 percent gain #10 11 40 percent gain #11 CTSUSDPA CTSU Base Clock Setting Operating clock divided by ( CTSUSDPA + 1 ) x 2 8 12 read-write CTSURICOA CTSU Reference ICO Current Adjustment Current offset amount is CTSUSO ( 0 to 255 ) 0 7 read-write CTSUSC CTSU Sensor Counter 0x18 16 read-only 0x0000 0xFFFF CTSUSC CTSU Sensor Counter These bits indicate the measurement result of the CTSU. These bits indicate FFFFh when an overflow occurs. 0 15 read-only CTSURC CTSU Reference Counter 0x1A 16 read-only 0x0000 0xFFFF CTSURC CTSU Reference Counter These bits indicate the measurement result of the reference ICO. These bits indicate FFFFh when an overflow occurs. 0 15 read-only CTSUERRS CTSU Error Status Register 0x1C 16 read-only 0x0000 0xFFFF CTSUICOMP TSCAP Voltage Error Monitor 15 15 read-only 0 Normal TSCAP voltage #0 1 Abnormal TSCAP voltage #1 Reserved These bits are read as 000000000000000. 0 14 read-only DAC12 12-bit D/A converter 0x4005E000 0x00 2 registers 0x04 4 registers DADR0 D/A Data Register 0 0x00 16 read-write 0x0000 0xFFFF DADR D/A Data Register NOTE: When DADPR.DPSEL = 0, the high-order 4 bits are fixed to 0: right justified format. When DADPR.DPSEL = 1, the low-order 4 bits are fixed to 0: left justified format. 0 15 read-write DACR D/A Control Register 0x04 8 read-write 0x1F 0xFF Reserved This bit is read as 0. The write value should be 0. 7 7 read-write DAOE0 D/A Output Enable 0 6 6 read-write 0 Analog output of channel 0 (DA0) is disabled. #0 1 D/A conversion of channel 0 is enabled. Analog output of channel 0 (DA0) is enabled. #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write Reserved These bits are read as 11111. The write value should be 11111. 0 4 read-write DADPR DADR0 Format Select Register 0x05 8 read-write 0x00 0xFF DPSEL DADRm Format Select 7 7 read-write 0 Right justified format. #0 1 Left justified format. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 0 6 read-write DAADSCR D/A-A/D Synchronous Start Control Register 0x06 8 read-write 0x00 0xFF DAADST D/A-A/D Synchronous Conversion 7 7 read-write 0 D/A converter operation does not synchronize with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is disabled). #0 1 D/A converter operation synchronizes with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is enabled). #1 DAVREFCR D/A VREF Control Register 0x07 8 read-write 0x00 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write REF D/A Reference Voltage Select 0 2 read-write 000 Not selected #000 001 AVCC0/AVSS0 #001 011 Internal reference voltage/AVSS0 #011 110 VREFH/VREFL #110 others Setting prohibited true DAC8 8-bit D/A converter 0x4009E000 0x00 2 registers 0x03 1 registers 2 0x01 0,1 DACS%s D/A Conversion Value Setting Register %s 0x00 8 read-write 0x00 0xFF DACS DACS D/A conversion store data note: When 8-bit D/A Converter output is selected as the reference input for the ACMPLP in the COMPSEL1 register, and ACMPLP operation is enabled (COMPMDR.CnENB = 1), changing the DACS[7:0] bits for the channel in use is prohibited. 0 7 read-write DAM D/A Converter Mode Register 0x03 8 read-write 0x00 0xFF Reserved These bits are read as 00. The write value should be 00. 6 7 read-write DACE1 D/A Operation Enable 1 5 5 read-write 0 D/A conversion disabled for channel 1 #0 1 D/A conversion enabled for channel 1 #1 DACE0 D/A Operation Enable 0 4 4 read-write 0 D/A conversion disabled for channel 0 #0 1 D/A conversion enabled for channel 0. #1 Reserved These bits are read as 0000. The write value should be 0000. 0 3 read-write DMAC0 Direct memory access controller 0 0x40005000 0x00 14 registers 0x10 2 registers 0x13 3 registers 0x18 7 registers DMSAR DMA Source Address Register 0x00 32 read-write 0x00000000 0xFFFFFFFF DMSAR Specifies the transfer source start address. 0 31 read-write DMDAR DMA Destination Address Register 0x04 32 read-write 0x00000000 0xFFFFFFFF DMDAR Specifies the transfer destination start address. 0 31 read-write DMCRA DMA Transfer Count Register 0x08 32 read-write 0x00000000 0xFFFFFFFF Reserved These bits are read as 000000. The write value should be 000000. 26 31 read-write DMCRAH Upper bits of transfer count 16 25 read-write DMCRAL Lower bits of transfer count 0 15 read-write DMCRB DMA Block Transfer Count Register 0x0C 16 read-write 0x0000 0xFFFF DMCRB Specifies the number of block transfer operations or repeat transfer operations. 0 15 read-write 0000 65,536 blocks #0000 others DMCRB blocks true DMTMD DMA Transfer Mode Register 0x10 16 read-write 0x0000 0xFFFF MD Transfer Mode Select 14 15 read-write 00 Normal transfer #00 01 Repeat transfer #01 10 Block transfer #10 11 Setting prohibited #11 DTS Repeat Area Select 12 13 read-write 00 The destination is specified as the repeat area or block area. #00 01 The source is specified as the repeat area or block area. #01 10 The repeat area or block area is not specified. #10 11 Setting prohibited #11 Reserved These bits are read as 00. The write value should be 00. 10 11 read-write SZ Transfer Data Size Select 8 9 read-write 00 8 bits #00 01 16 bits #01 10 32 bits #10 11 Setting prohibited #11 Reserved These bits are read as 000000. The write value should be 000000. 2 7 read-write DCTG Transfer Request Source Select 0 1 read-write 00 Software #00 01 Interrupts*1 from peripheral modules or external interrupt input pins #01 10 Setting prohibited #10 11 Setting prohibited #11 DMINT DMA Interrupt Setting Register 0x13 8 read-write 0x00 0xFF Reserved These bits are read as 000. The write value should be 000. 5 7 read-write DTIE Transfer End Interrupt Enable 4 4 read-write 0 Disabled #0 1 Enabled #1 ESIE Transfer Escape End Interrupt Enable 3 3 read-write 0 Disabled #0 1 Enabled #1 RPTIE Repeat Size End Interrupt Enable 2 2 read-write 0 Disabled #0 1 Enabled #1 SARIE Source Address Extended Repeat Area Overflow Interrupt Enable 1 1 read-write 0 Disabled #0 1 Enabled #1 DARIE Destination Address Extended Repeat Area Overflow Interrupt Enable 0 0 read-write 0 Disabled #0 1 Enabled #1 DMAMD DMA Address Mode Register 0x14 16 read-write 0x0000 0xFFFF SM Source Address Update Mode 14 15 read-write 00 Fixed address #00 01 Offset addition #01 10 Incremented address #10 11 Decremented address. #11 Reserved This bit is read as 0. The write value should be 0. 13 13 read-write SARA Source Address Extended Repeat Area Specifies the extended repeat area on the source address. For details on the settings. 8 12 read-write DM Destination Address Update Mode 6 7 read-write 00 Fixed address #00 01 Offset addition #01 10 Incremented address #10 11 Decremented address. #11 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write DARA Destination Address Extended Repeat Area Specifies the extended repeat area on the destination address. For details on the settings. 0 4 read-write DMOFR DMA Offset Register 0x18 32 read-write 0x00000000 0xFFFFFFFF DMOFR Specifies the offset when offset addition is selected as the address update mode for transfer source or destination. 0 31 read-write DMCNT DMA Transfer Enable Register 0x1C 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write DTE DMA Transfer Enable 0 0 read-write modify 0 Disabled #0 1 Enabled. #1 DMREQ DMA Software Start Register 0x1D 8 read-write 0x00 0xFF Reserved These bits are read as 000. The write value should be 000. 5 7 read-write CLRS DMA Software Start Bit Auto Clear Select 4 4 read-write 0 SWREQ bit is cleared after DMA transfer is started by software. #0 1 SWREQ bit is not cleared after DMA transfer is started by software. #1 Reserved These bits are read as 000. The write value should be 000. 1 3 read-write SWREQ DMA Software Start 0 0 read-write modify 0 DMA transfer is not requested. #0 1 DMA transfer is requested. #1 DMSTS DMA Status Register 0x1E 8 read-write 0x00 0xFF ACT DMA Active Flag 7 7 read-only 0 DMAC operation suspended #0 1 DMAC operating. #1 Reserved These bits are read as 00. The write value should be 00. 5 6 read-write DTIF Transfer End Interrupt Flag 4 4 read-write zeroToClear modify 0 No interrupt #0 1 Interrupt occurred. #1 Reserved These bits are read as 000. The write value should be 000. 1 3 read-write ESIF Transfer Escape End Interrupt Flag 0 0 read-write zeroToClear modify 0 No interrupt #0 1 Interrupt occurred. #1 DMAC1 Direct memory access controller 1 0x40005040 DMAC2 Direct memory access controller 2 0x40005080 DMAC3 Direct memory access controller 3 0x400050C0 DMA DMAC Module Activation 0x40005200 0x00 1 registers DMAST DMAC Module Activation Register 0x00 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write DMST DMAC Operation Enable 0 0 read-write 0 Disabled. #0 1 Enabled. #1 DOC Data Operation Circuit 0x40054100 0x00 1 registers 0x02 4 registers DOCR DOC Control Register 0x00 8 read-write 0x00 0xFF Reserved This bit is read as 0. The write value should be 0. 7 7 read-write DOPCFCL DOPCF Clear 6 6 read-write 0 Maintains the DOPCF flag state. #0 1 Clears the DOPCF flag. #1 DOPCF Data Operation Circuit Flag Indicates the result of an operation. 5 5 read-only Reserved These bits are read as 00. The write value should be 00. 3 4 read-write DCSEL Detection Condition Select 2 2 read-write 0 DOPCF is set when data mismatch is detected. #0 1 DOPCF is set when data match is detected. #1 OMS Operating Mode Select 0 1 read-write 00 Data comparison mode #00 01 Data addition mode #01 10 Data subtraction mode #10 11 Setting prohibited #11 DODIR DOC Data Input Register 0x02 16 read-write 0x0000 0xFFFF DODIR 16-bit read-write register in which 16-bit data for use in the operations are stored. 0 15 read-write DODSR DOC Data Setting Register 0x04 16 read-write 0x0000 0xFFFF DODSR This register stores 16-bit data for use as a reference in data comparison mode. This register also stores the results of operations in data addition and data subtraction modes. 0 15 read-write DTC Data Transfer Controller 0x40005400 0x00 1 registers 0x04 4 registers 0x0C 1 registers 0x0E 2 registers DTCCR DTC Control Register 0x00 8 read-write 0x08 0xFF Reserved These bits are read as 000. The write value should be 000. 5 7 read-write RRS DTC Transfer Information Read Skip Enable. 4 4 read-write 0 Do not skip transfer information read #0 1 Skip transfer information read when vector numbers match #1 Reserved This bit is read as 1. The write value should be 1. 3 3 read-write Reserved These bits are read as 000. The write value should be 000. 0 2 read-write DTCVBR DTC Vector Base Register 0x04 32 read-write 0x00000000 0xFFFFFFFF DTCVBR DTC Vector Base Address. Note: A value cannot be set in the lower-order 10 bits. These bits are fixed to 0. 0 31 read-write DTCST DTC Module Start Register 0x0C 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write DTCST DTC Module Start 0 0 read-write 0 DTC module stop #0 1 DTC module start #1 DTCSTS DTC Status Register 0x0E 16 read-only 0x0000 0xFFFF ACT DTC Active Flag 15 15 read-only 0 DTC transfer operation is not in progress. #0 1 DTC transfer operation is in progress. #1 Reserved These bits are read as 0000000. 8 14 read-only VECN DTC-Activating Vector Number Monitoring These bits indicate the vector number for the activating source when DTC transfer is in progress. The value is only valid if DTC transfer is in progress (the value of the ACT flag is 1) 0 7 read-only ELC Event Link Controller 0x40041000 0x00 1 registers 0x02 4 registers 0x10 40 registers 0x40 2 registers 0x48 20 registers ELCR Event Link Controller Register 0x00 8 read-write 0x00 0xFF ELCON All Event Link Enable 7 7 read-write 0 ELC function is disabled. #0 1 ELC function is enabled. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 0 6 read-write 2 0x2 0,1 ELSEGR%s Event Link Software Event Generation Register %s 0x02 8 read-write 0x80 0xFF WI ELSEGR Register Write Disable 7 7 write-only 0 Write to ELSEGR register is enabled. #0 1 Write to ELSEGR register is disabled. #1 WE SEG Bit Write Enable 6 6 read-write 0 Write to SEG bit is disabled. #0 1 Write to SEG bit is enabled. #1 Reserved These bits are read as 00000. The write value should be 00000. 1 5 read-write SEG Software Event Generation 0 0 write-only 0 Normal operation #0 1 Software event is generated. #1 10 0x4 0-9 ELSR%s Event Link Setting Register %s 0x10 16 read-write 0x0000 0xFFFF Reserved These bits are read as 00000000. The write value should be 00000000. 8 15 read-write ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 others Set the number for the event signal to be linked. true ELSR12 Event Link Setting Register 12 0x40 16 read-write 0x0000 0xFFFF Reserved These bits are read as 00000000. The write value should be 00000000. 8 15 read-write ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 others Set the number for the event signal to be linked. true 5 0x4 14-18 ELSR%s Event Link Setting Register %s 0x48 16 read-write 0x0000 0xFFFF Reserved These bits are read as 00000000. The write value should be 00000000. 8 15 read-write ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 others Set the number for the event signal to be linked. true FCACHE Flash Cache 0x4001C000 0x100 2 registers 0x104 2 registers 0x11C 1 registers FCACHEE Flash Cache Enable Register 0x100 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 1 15 read-write FCACHEEN FCACHE Enable 0 0 read-write 0 FCACHE is disabled #0 1 FCACHE is enabled #1 FCACHEIV Flash Cache Invalidate Register 0x104 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 1 15 read-write FCACHEIV FCACHE Invalidation 0 0 read-write oneToSet modify 0 (Read)not in progress / (Write) no effect. #0 1 (Read)in progress /(Write) Starting Cache Invalidation #1 FLWT Flash Wait Cycle Register 0x11C 8 read-write 0x00 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write FLWT These bits represent the ratio of the CPU clock period to the Flash memory access time. 0 2 read-write 000 zero wait #000 others Setting prohibited true PORT0 Port 0 Control Registers 0x40040000 0x00 4 registers 0x00 8 registers 0x06 6 registers 0x08 4 registers PCNTR1 Port Control Register 1 0x00 32 read-write 0x00000000 0xFFFFFFFF PODR Pmn Output Data 16 31 read-write 0 Low output #0 1 High output. #1 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PODR Output data register PCNTR1 0x00 16 read-write 0x0000 0xFFFF PODR Pmn Output Data 0 15 read-write 0 Low output #0 1 High output. #1 PDR Data direction register PCNTR1 0x02 16 read-write 0x0000 0xFFFF PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PCNTR2 Port Control Register 2 0x04 32 read-only 0x00000000 0xFFFF0000 Reserved These bits are read as 0000000000000000. 16 31 read-only PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PIDR Input data register PCNTR2 0x06 16 read-only 0x0000 0x0000 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PCNTR3 Port Control Register 3 0x08 32 write-only 0x00000000 0xFFFFFFFF PORR Pmn Output Reset 16 31 write-only 0 No affect to output #0 1 Low output. #1 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PORR Output reset register PCNTR3 0x08 16 write-only 0x0000 0xFFFF PORR Pmn Output Reset 0 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Output set register PCNTR3 0x0A 16 write-only 0x0000 0xFFFF POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PORT1 Port 1 Control Registers 0x40040020 0x00 4 registers 0x00 8 registers 0x04 8 registers 0x08 8 registers 0x0C 4 registers PCNTR1 Port Control Register 1 0x00 32 read-write 0x00000000 0xFFFFFFFF PODR Pmn Output Data 16 31 read-write 0 Low output #0 1 High output. #1 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PODR Output data register PCNTR1 0x00 16 read-write 0x0000 0xFFFF PODR Pmn Output Data 0 15 read-write 0 Low output #0 1 High output. #1 PDR Data direction register PCNTR1 0x02 16 read-write 0x0000 0xFFFF PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PCNTR2 Port Control Register 2 0x04 32 read-only 0x00000000 0xFFFF0000 EIDR Pmn Event Input Data 16 31 read-only 0 Low input #0 1 High input. #1 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 EIDR Event input data register PCNTR2 0x04 16 read-only 0x0000 0xFFFF EIDR Pmn Event Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PIDR Input data register PCNTR2 0x06 16 read-only 0x0000 0x0000 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PCNTR3 Port Control Register 3 0x08 32 write-only 0x00000000 0xFFFFFFFF PORR Pmn Output Reset 16 31 write-only 0 No affect to output #0 1 Low output. #1 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PORR Output set register PCNTR3 0x08 16 write-only 0x0000 0xFFFF PORR Pmn Output Reset 0 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Output reset register PCNTR3 0x0A 16 write-only 0x0000 0xFFFF POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PCNTR4 Port Control Register 4 0x0C 32 read-write 0x00000000 0xFFFFFFFF EORR Pmn Event Output Reset 16 31 read-write 0 No affect to output #0 1 Low output #1 EOSR Pmn Event Output Set 0 15 read-write 0 No affect to output #0 1 High output. #1 EORR Event output set register PCNTR4 0x0C 16 read-write 0x0000 0xFFFF EORR Pmn Event Output Reset 0 15 read-write 0 No affect to output #0 1 Low output #1 EOSR Event output reset register PCNTR4 0x0E 16 read-write 0x0000 0xFFFF EOSR Pmn Event Output Set 0 15 read-write 0 No affect to output #0 1 High output. #1 PORT2 Port 2 Control Registers 0x40040040 PORT3 Port 3 Control Registers 0x40040060 PORT4 Port 4 Control Registers 0x40040080 PORT5 Port 5 Control Registers 0x400400A0 PORT6 Port 6 Control Registers 0x400400C0 PORT7 Port 7 Control Registers 0x400400E0 PORT8 Port 8 Control Registers 0x40040100 PORT9 Port 9 Control Registers 0x40040120 PFS Pmn Pin Function Control Register 0x40040800 0x00 4 registers 0x02 2 registers 0x03 33 registers 0x06 32 registers 0x07 32 registers 0x28 24 registers 0x2A 24 registers 0x2B 24 registers 0x40 32 registers 0x42 32 registers 0x43 32 registers 0x60 4 registers 0x62 2 registers 0x63 5 registers 0x66 2 registers 0x67 5 registers 0x6A 2 registers 0x6B 21 registers 0x6E 20 registers 0x6F 20 registers 0x80 4 registers 0x82 2 registers 0x83 5 registers 0x86 2 registers 0x87 21 registers 0x8A 20 registers 0x8B 20 registers 0xB0 16 registers 0xB2 16 registers 0xB3 16 registers 0xC0 4 registers 0xC2 2 registers 0xC3 29 registers 0xC6 28 registers 0xC7 28 registers 0xE8 24 registers 0xEA 24 registers 0xEB 24 registers 0x100 32 registers 0x102 32 registers 0x103 32 registers 0x120 4 registers 0x122 2 registers 0x123 5 registers 0x126 2 registers 0x127 25 registers 0x12A 24 registers 0x12B 24 registers 0x140 24 registers 0x142 24 registers 0x143 24 registers 0x16C 8 registers 0x16E 8 registers 0x16F 8 registers 0x180 16 registers 0x182 16 registers 0x183 16 registers 0x1A0 8 registers 0x1A2 8 registers 0x1A3 8 registers 0x1A8 4 registers 0x1AA 2 registers 0x1AB 1 registers 0x1C0 24 registers 0x1C2 24 registers 0x1C3 24 registers 0x1E0 4 registers 0x1E2 2 registers 0x1E3 1 registers 0x1E8 16 registers 0x1EA 16 registers 0x1EB 16 registers 0x220 8 registers 0x222 8 registers 0x223 8 registers 0x240 12 registers 0x242 12 registers 0x243 12 registers 0x278 8 registers 0x27A 8 registers 0x27B 8 registers P000PFS P00%s Pin Function Control Register 0x000 32 read-write 0x00000000 0xFFFFFFFD Reserved These bits are read as 000. The write value should be 000. 29 31 read-write PSEL Port Function Select These bits select the peripheral function. For individual pin functions, see the MPC table 24 28 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 23 read-write PMR Port Mode Control 16 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 Reserved These bits are read as 000. The write value should be 000. 11 13 read-write DSCR Port Drive Capability 10 10 read-write 0 Low drive #0 1 Middle drive. #1 Reserved These bits are read as 000. The write value should be 000. 7 9 read-write NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P000PFS_HA P00%s Pin Function Control Register P000PFS 0x002 16 read-write 0x0000 0xFFFD ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 Reserved These bits are read as 000. The write value should be 000. 11 13 read-write DSCR Port Drive Capability 10 10 read-write 0 Low drive #0 1 Middle drive. #1 Reserved These bits are read as 000. The write value should be 000. 7 9 read-write NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P000PFS_BY P00%s Pin Function Control Register P000PFS 0x003 8 read-write 0x00 0xFD Reserved This bit is read as 0. The write value should be 0. 7 7 read-write NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 8 0x4 1-8 P00%sPFS P00%s Pin Function Control Register 0x004 32 read-write 0x00000000 0xFFFFFFFD 8 0x4 1-8 P00%sPFS_HA P00%s Pin Function Control Register P00%sPFS 0x006 16 read-write 0x0000 0xFFFD 8 0x4 1-8 P00%sPFS_BY P00%s Pin Function Control Register P00%sPFS 0x007 8 read-write 0x00 0xFD 6 0x4 10-15 P0%sPFS P0%s Pin Function Control Register 0x028 32 read-write 0x00000000 0xFFFFFFFD 6 0x4 10-15 P0%sPFS_HA P0%s Pin Function Control Register P0%sPFS 0x02A 16 read-write 0x0000 0xFFFD 6 0x4 10-15 P0%sPFS_BY P0%s Pin Function Control Register P0%sPFS 0x02B 8 read-write 0x00 0xFD 8 0x4 0-7 P10%sPFS P10%s Pin Function Control Register 0x040 32 read-write 0x00000000 0xFFFFFFFD 8 0x4 0-7 P10%sPFS_HA P10%s Pin Function Control Register P10%sPFS 0x042 16 read-write 0x0000 0xFFFD 8 0x4 0-7 P10%sPFS_BY P10%s Pin Function Control Register P10%sPFS 0x043 8 read-write 0x00 0xFD P108PFS P108 Pin Function Control Register 0x060 32 read-write 0x00010010 0xFFFFFFFD Reserved These bits are read as 000. The write value should be 000. 29 31 read-write PSEL Port Function Select These bits select the peripheral function. For individual pin functions, see the setting table. 24 28 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 23 read-write PMR Port Mode Control 16 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 EOF Event on Failing 13 13 read-write 0 No effected #0 1 Detect failing edge #1 EOR Event on Rising 12 12 read-write 0 No effected #0 1 Detect rising edge #1 Reserved This bit is read as 0. The write value should be 0. 11 11 read-write DSCR Port Drive Capability 10 10 read-write 0 Low drive #0 1 Middle drive. #1 Reserved These bits are read as 000. The write value should be 000. 7 9 read-write NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P108PFS_HA P108 Pin Function Control Register P108PFS 0x062 16 read-write 0x0010 0xFFFD ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 EOF Event on Failing 13 13 read-write 0 No effected #0 1 Detect failing edge #1 EOR Event on Rising 12 12 read-write 0 No effected #0 1 Detect rising edge #1 Reserved This bit is read as 0. The write value should be 0. 11 11 read-write DSCR Port Drive Capability 10 10 read-write 0 Low drive #0 1 Middle drive. #1 Reserved These bits are read as 000. The write value should be 000. 7 9 read-write NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P108PFS_BY P108 Pin Function Control Register P108PFS 0x063 8 read-write 0x10 0xFD Reserved This bit is read as 0. The write value should be 0. 7 7 read-write NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P109PFS P109 Pin Function Control Register 0x064 32 read-write 0x00010000 0xFFFFFFFD Reserved These bits are read as 000. The write value should be 000. 29 31 read-write PSEL Port Function Select These bits select the peripheral function. For individual pin functions, see the setting table. 24 28 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 23 read-write PMR Port Mode Control 16 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 EOF Event on Failing 13 13 read-write 0 No effected #0 1 Detect failing edge #1 EOR Event on Rising 12 12 read-write 0 No effected #0 1 Detect rising edge #1 Reserved This bit is read as 0. The write value should be 0. 11 11 read-write DSCR Port Drive Capability 10 10 read-write 0 Low drive #0 1 Middle drive. #1 Reserved These bits are read as 000. The write value should be 000. 7 9 read-write NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P109PFS_HA P109 Pin Function Control Register P109PFS 0x066 16 read-write 0x0000 0xFFFD ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 EOF Event on Failing 13 13 read-write 0 No effected #0 1 Detect failing edge #1 EOR Event on Rising 12 12 read-write 0 No effected #0 1 Detect rising edge #1 Reserved This bit is read as 0. The write value should be 0. 11 11 read-write DSCR Port Drive Capability 10 10 read-write 0 Low drive #0 1 Middle drive. #1 Reserved These bits are read as 000. The write value should be 000. 7 9 read-write NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P109PFS_BY P109 Pin Function Control Register P109PFS 0x067 8 read-write 0x00 0xFD Reserved This bit is read as 0. The write value should be 0. 7 7 read-write NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P110PFS P110 Pin Function Control Register 0x068 32 read-write 0x00010010 0xFFFFFFFD P110PFS_HA P110 Pin Function Control Register P110PFS 0x06A 16 read-write 0x0010 0xFFFD P110PFS_BY P110 Pin Function Control Register P110PFS 0x06B 8 read-write 0x10 0xFD 5 0x4 11-15 P1%sPFS P1%s Pin Function Control Register 0x06C 32 read-write 0x00000000 0xFFFFFFFD 5 0x4 11-15 P1%sPFS_HA P1%s Pin Function Control Register P1%sPFS 0x06E 16 read-write 0x0000 0xFFFD 5 0x4 11-15 P1%sPFS_BY P1%s Pin Function Control Register P1%sPFS 0x06F 8 read-write 0x00 0xFD P200PFS P200 Pin Function Control Register 0x080 32 read-write 0x00000000 0xFFFFFFFD P200PFS_HA P200 Pin Function Control Register P200PFS 0x082 16 read-write 0x0000 0xFFFD P200PFS_BY P200 Pin Function Control Register P200PFS 0x083 8 read-write 0x00 0xFD P201PFS P201 Pin Function Control Register 0x084 32 read-write 0x00000010 0xFFFFFFFD Reserved These bits are read as 000. The write value should be 000. 29 31 read-write PSEL Port Function Select These bits select the peripheral function. For individual pin functions, see the setting table. 24 28 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 23 read-write PMR Port Mode Control 16 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 EOF Event on Falling 13 13 read-write 0 Do not care #0 1 Detect falling edge #1 EOR Event on Rising 12 12 read-write 0 Do not care #0 1 Detect rising edge #1 Reserved This bit is read as 0. The write value should be 0. 11 11 read-write DSCR Drive Strength Control Register 10 10 read-write 0 Low drive #0 1 High drive #1 Reserved These bits are read as 000. The write value should be 000. 7 9 read-write NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P201PFS_HA P201 Pin Function Control Register P201PFS 0x086 16 read-write 0x0010 0xFFFD ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 EOF Event on Falling 13 13 read-write 0 Do not care #0 1 Detect falling edge #1 EOR Event on Rising 12 12 read-write 0 Do not care #0 1 Detect rising edge #1 Reserved This bit is read as 0. The write value should be 0. 11 11 read-write DSCR Drive Strength Control Register 10 10 read-write 0 Low drive #0 1 High drive #1 Reserved These bits are read as 000. The write value should be 000. 7 9 read-write NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P201PFS_BY P201 Pin Function Control Register P201PFS 0x087 8 read-write 0x10 0xFD Reserved This bit is read as 0. The write value should be 0. 7 7 read-write NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 5 0x4 2-6 P20%sPFS P20%s Pin Function Control Register 0x088 32 read-write 0x00000000 0xFFFFFFFD 5 0x4 2-6 P20%sPFS_HA P20%s Pin Function Control Register P20%sPFS 0x08A 16 read-write 0x0000 0xFFFD 5 0x4 2-6 P20%sPFS_BY P20%s Pin Function Control Register P20%sPFS 0x08B 8 read-write 0x00 0xFD 4 0x4 12-15 P2%sPFS P2%s Pin Function Control Register 0x0B0 32 read-write 0x00000000 0xFFFFFFFD 4 0x4 12-15 P2%sPFS_HA P2%s Pin Function Control Register P2%sPFS 0x0B2 16 read-write 0x0000 0xFFFD 4 0x4 12-15 P2%sPFS_BY P2%s Pin Function Control Register P2%sPFS 0x0B3 8 read-write 0x00 0xFD P300PFS P300 Pin Function Control Register 0x0C0 32 read-write 0x00010010 0xFFFFFFFD P300PFS_HA P300 Pin Function Control Register P300PFS 0x0C2 16 read-write 0x0010 0xFFFD P300PFS_BY P300 Pin Function Control Register P300PFS 0x0C3 8 read-write 0x10 0xFD 7 0x4 1-7 P30%sPFS P30%s Pin Function Control Register 0x0C4 32 read-write 0x00000000 0xFFFFFFFD 7 0x4 1-7 P30%sPFS_HA P30%s Pin Function Control Register P30%sPFS 0x0C6 16 read-write 0x0000 0xFFFD 7 0x4 1-7 P30%sPFS_BY P30%s Pin Function Control Register P30%sPFS 0x0C7 8 read-write 0x00 0xFD 8 0x4 0-7 P40%sPFS P40%s Pin Function Control Register 0x100 32 read-write 0x00000000 0xFFFFFFFD 8 0x4 0-7 P40%sPFS_HA P40%s Pin Function Control Register P40%sPFS 0x102 16 read-write 0x0000 0xFFFD 8 0x4 0-7 P40%sPFS_BY P40%s Pin Function Control Register P40%sPFS 0x103 8 read-write 0x00 0xFD P408PFS P408 Pin Function Control Register 0x120 32 read-write 0x00000000 0xFFFFFFFD Reserved These bits are read as 000. The write value should be 000. 29 31 read-write PSEL Port Function Select These bits select the peripheral function. For individual pin functions, see the setting table. 24 28 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 23 read-write PMR Port Mode Control 16 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 EOF Event on Falling 13 13 read-write 0 Do not care #0 1 Detect falling edge #1 EOR Event on Rising 12 12 read-write 0 Do not care #0 1 Detect rising edge #1 DSCR1 Drive Strength Control Register 11 11 read-write 0 Low drive(DSCR = 0)/Middle drive(DSCR = 1) #0 1 Middle drive for IIC Fast-mode(DSCR = 0)/Setting prohibited(DSCR = 1) #1 DSCR Drive Strength Control Register 10 10 read-write 0 Low drive(DSCR1 = 0)/Middle drive for llC Fast-mode(DSCR1 = 1) #0 1 Middle drive(DSCR1 = 0)/Setting prohibited(DSCR1 = 1) #1 Reserved These bits are read as 000. The write value should be 000. 7 9 read-write NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P408PFS_HA P408 Pin Function Control Register P408PFS 0x122 16 read-write 0x0000 0xFFFD ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 EOF Event on Falling 13 13 read-write 0 Do not care #0 1 Detect falling edge #1 EOR Event on Rising 12 12 read-write 0 Do not care #0 1 Detect rising edge #1 DSCR1 Drive Strength Control Register 11 11 read-write 0 Low drive(DSCR = 0)/Middle drive(DSCR = 1) #0 1 Middle drive for IIC Fast-mode(DSCR = 0)/Setting prohibited(DSCR = 1) #1 DSCR Drive Strength Control Register 10 10 read-write 0 Low drive(DSCR1 = 0)/Middle drive for llC Fast-mode(DSCR1 = 1) #0 1 Middle drive(DSCR1 = 0)/Setting prohibited(DSCR1 = 1) #1 Reserved These bits are read as 000. The write value should be 000. 7 9 read-write NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P408PFS_BY P408 Pin Function Control Register P408PFS 0x123 8 read-write 0x00 0xFD Reserved This bit is read as 0. The write value should be 0. 7 7 read-write NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P409PFS P409 Pin Function Control Register 0x124 32 read-write 0x00000000 0xFFFFFFFD P409PFS_HA P409 Pin Function Control Register P409PFS 0x126 16 read-write 0x0000 0xFFFD P409PFS_BY P409 Pin Function Control Register P409PFS 0x127 8 read-write 0x00 0xFD 6 0x4 10-15 P4%sPFS P4%s Pin Function Control Register 0x128 32 read-write 0x00000000 0xFFFFFFFD 6 0x4 10-15 P4%sPFS_HA P4%s Pin Function Control Register P409PFS 0x12A 16 read-write 0x0000 0xFFFD 6 0x4 10-15 P4%sPFS_BY P4%s Pin Function Control Register P409PFS 0x12B 8 read-write 0x00 0xFD 6 0x4 0-5 P50%sPFS P50%s Pin Function Control Register 0x140 32 read-write 0x00000000 0xFFFFFFFD 6 0x4 0-5 P50%sPFS_HA P50%s Pin Function Control Register P50%sPFS 0x142 16 read-write 0x0000 0xFFFD 6 0x4 0-5 P50%sPFS_BY P50%s Pin Function Control Register P50%sPFS 0x143 8 read-write 0x00 0xFD 4 0x4 0-3 P60%sPFS P60%s Pin Function Control Register 0x180 32 read-write 0x00000000 0xFFFFFFFD 4 0x4 0-3 P60%sPFS_HA P60%s Pin Function Control Register P60%sPFS 0x182 16 read-write 0x0000 0xFFFD 4 0x4 0-3 P60%sPFS_BY P60%s Pin Function Control Register P60%sPFS 0x183 8 read-write 0x00 0xFD 2 0x4 8-9 P60%sPFS P60%s Pin Function Control Register 0x1A0 32 read-write 0x00000000 0xFFFFFFFD 2 0x4 8-9 P60%sPFS_HA P60%s Pin Function Control Register P60%sPFS 0x1A2 16 read-write 0x0000 0xFFFD 2 0x4 8-9 P60%sPFS_BY P60%s Pin Function Control Register P60%sPFS 0x1A3 8 read-write 0x00 0xFD P610PFS P610 Pin Function Control Register 0x1A8 32 read-write 0x00000000 0xFFFFFFFD P610PFS_HA P610 Pin Function Control Register P610PFS 0x1AA 16 read-write 0x0000 0xFFFD P610PFS_BY P610 Pin Function Control Register P610PFS 0x1AB 8 read-write 0x00 0xFD P708PFS P708 Pin Function Control Register 0x1E0 32 read-write 0x00000000 0xFFFFFFFD P708PFS_HA P708 Pin Function Control Register P708PFS 0x1E2 16 read-write 0x0000 0xFFFD P708PFS_BY P708 Pin Function Control Register P708PFS 0x1E3 8 read-write 0x00 0xFD 2 0x4 8-9 P80%sPFS P80%s Pin Function Control Register 0x220 32 read-write 0x00000000 0xFFFFFFFD 2 0x4 8-9 P80%sPFS_HA P80%s Pin Function Control Register P80%sPFS 0x222 16 read-write 0x0000 0xFFFD 2 0x4 8-9 P80%sPFS_BY P80%s Pin Function Control Register P80%sPFS 0x223 8 read-write 0x00 0xFD 2 0x4 14,15 P9%sPFS P9%s Pin Function Control Register 0x278 32 read-write 0x00010000 0xFFFFFFFD 2 0x4 14,15 P9%sPFS_HA P9%s Pin Function Control Register P9%sPFS 0x27A 16 read-write 0x0000 0xFFFD 2 0x4 14,15 P9%sPFS_BY P9%s Pin Function Control Register P9%sPFS 0x27B 8 read-write 0x00 0xFD PMISC Miscellaneous Port Control Register 0x40040D00 0x00 4 registers PWPR Write-Protect Register 0x03 8 read-write 0x80 0xFF B0WI PFSWE Bit Write Disable 7 7 read-write 0 Writing to the PFSWE bit is enabled #0 1 Writing to the PFSWE bit is disabled #1 PFSWE PFS Register Write Enable 6 6 read-write 0 Writing to the PFS register is disabled #0 1 Writing to the PFS register is enabled #1 Reserved These bits are read as 000000. The write value should be 000000. 0 5 read-write ICU Interrupt Controller 0x40006000 0x00 13 registers 0x0E 2 registers 0x140 2 registers 0x120 2 registers 0x130 2 registers 0x100 1 registers 0x300 128 registers 0x280 16 registers 0x200 2 registers 0x1A0 4 registers IEL0 ICU Interrupt 0 0 IEL1 ICU Interrupt 1 1 IEL2 ICU Interrupt 2 2 IEL3 ICU Interrupt 3 3 IEL4 ICU Interrupt 4 4 IEL5 ICU Interrupt 5 5 IEL6 ICU Interrupt 6 6 IEL7 ICU Interrupt 7 7 IEL8 ICU Interrupt 8 8 IEL9 ICU Interrupt 9 9 IEL10 ICU Interrupt 10 10 IEL11 ICU Interrupt 11 11 IEL12 ICU Interrupt 12 12 IEL13 ICU Interrupt 13 13 IEL14 ICU Interrupt 14 14 IEL15 ICU Interrupt 15 15 IEL16 ICU Interrupt 16 16 IEL17 ICU Interrupt 17 17 IEL18 ICU Interrupt 18 18 IEL19 ICU Interrupt 19 19 IEL20 ICU Interrupt 20 20 IEL21 ICU Interrupt 21 21 IEL22 ICU Interrupt 22 22 IEL23 ICU Interrupt 23 23 IEL24 ICU Interrupt 24 24 IEL25 ICU Interrupt 25 25 IEL26 ICU Interrupt 26 26 IEL27 ICU Interrupt 27 27 IEL28 ICU Interrupt 28 28 IEL29 ICU Interrupt 29 29 IEL30 ICU Interrupt 30 30 IEL31 ICU Interrupt 31 31 13 0x1 0-12 IRQCR%s IRQ Control Register %s 0x000 8 read-write 0x00 0xFF FLTEN IRQ Digital Filter Enable 7 7 read-write 0 Digital filter disabled. #0 1 Digital filter enabled. #1 Reserved This bit is read as 0. The write value should be 0. 6 6 read-write FCLKSEL IRQ Digital Filter Sampling Clock Select 4 5 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 Reserved These bits are read as 00. The write value should be 00. 2 3 read-write IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 2 0x1 14,15 IRQCR%s IRQ Control Register %s 0x00E 8 read-write 0x00 0xFF FLTEN IRQ Digital Filter Enable 7 7 read-write 0 Digital filter disabled. #0 1 Digital filter enabled. #1 Reserved This bit is read as 0. The write value should be 0. 6 6 read-write FCLKSEL IRQ Digital Filter Sampling Clock Select 4 5 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 Reserved These bits are read as 00. The write value should be 00. 2 3 read-write IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 NMISR Non-Maskable Interrupt Status Register 0x140 16 read-only 0x0000 0xFFFF Reserved These bits are read as 000. 13 15 read-only SPEST CPU Stack pointer monitor Interrupt Status Flag 12 12 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 BUSMST MPU Bus Master Error Interrupt Status Flag 11 11 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 BUSSST MPU Bus Slave Error Interrupt Status Flag 10 10 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 RECCST RAM ECC Error Interrupt Status Flag 9 9 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 RPEST RAM Parity Error Interrupt Status Flag 8 8 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 NMIST NMI Status Flag 7 7 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 OSTST Oscillation Stop Detection Interrupt Status Flag 6 6 read-only 0 Interrupt not requested for main oscillation stop #0 1 Interrupt requested for main oscillation stop. #1 Reserved This bit is read as 0. 5 5 read-only VBATTST VBATT monitor Interrupt Status Flag 4 4 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 LVD2ST Voltage-Monitoring 2 Interrupt Status Flag 3 3 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 LVD1ST Voltage-Monitoring 1 Interrupt Status Flag 2 2 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 WDTST WDT Underflow/Refresh Error Status Flag 1 1 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 IWDTST IWDT Underflow/Refresh Error Status Flag 0 0 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 NMIER Non-Maskable Interrupt Enable Register 0x120 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000. The write value should be 000. 13 15 read-write SPEEN CPU Stack pointer monitor Interrupt Enable 12 12 read-write 0 Disabled #0 1 Enabled. #1 BUSMEN MPU Bus Master Error Interrupt Enable 11 11 read-write 0 Disabled #0 1 Enabled. #1 BUSSEN MPU Bus Slave Error Interrupt Enable 10 10 read-write 0 Disabled #0 1 Enabled. #1 RECCEN RAM ECC Error Interrupt Enable 9 9 read-write 0 Disabled #0 1 Enabled. #1 RPEEN RAM Parity Error Interrupt Enable 8 8 read-write 0 Disabled #0 1 Enabled. #1 NMIEN NMI Pin Interrupt Enable 7 7 read-write 0 Disabled #0 1 Enabled. #1 OSTEN Oscillation Stop Detection Interrupt Enable 6 6 read-write 0 Disabled #0 1 Enabled. #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write VBATTEN VBATT monitor Interrupt Enable 4 4 read-write 0 Disabled #0 1 Enabled. #1 LVD2EN Voltage-Monitoring 2 Interrupt Enable 3 3 read-write 0 Disabled #0 1 Enabled. #1 LVD1EN Voltage-Monitoring 1 Interrupt Enable 2 2 read-write 0 Disabled #0 1 Enabled. #1 WDTEN WDT Underflow/Refresh Error Interrupt Enable 1 1 read-write 0 Disabled #0 1 Enabled. #1 IWDTEN IWDT Underflow/Refresh Error Interrupt Enable 0 0 read-write 0 Disabled #0 1 Enabled. #1 NMICLR Non-Maskable Interrupt Status Clear Register 0x130 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000. The write value should be 000. 13 15 read-write SPECLR CPU Stack Pointer Monitor Interrupt Clear 12 12 write-only 0 No effect. #0 1 Clear the NMISR.SPEST flag. #1 BUSMCLR Bus Master Error Clear 11 11 write-only 0 No effect. #0 1 Clear the NMISR.BUSMST flag. #1 BUSSCLR Bus Slave Error Clear 10 10 write-only 0 No effect. #0 1 Clear the NMISR.BUSSST flag. #1 RECCCLR SRAM ECC Error Clear 9 9 write-only 0 No effect. #0 1 Clear the NMISR.RECCST flag. #1 RPECLR SRAM Parity Error Clear 8 8 write-only 0 No effect. #0 1 Clear the NMISR.RPEST flag. #1 NMICLR NMI Clear 7 7 write-only 0 No effect. #0 1 Clear the NMISR.NMIST flag. #1 OSTCLR OST Clear 6 6 write-only 0 No effect. #0 1 Clear the NMISR.OSTST flag. #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write VBATTCLR VBATT Clear 4 4 write-only 0 No effect. #0 1 Clear the NMISR.VBATTST flag. #1 LVD2CLR LVD2 Clear 3 3 write-only 0 No effect. #0 1 Clear the NMISR.LVD2ST flag. #1 LVD1CLR LVD1 Clear 2 2 write-only 0 No effect. #0 1 Clear the NMISR.LVD1ST flag. #1 WDTCLR WDT Clear 1 1 write-only 0 No effect. #0 1 Clear the NMISR.WDTST flag. #1 IWDTCLR IWDT Clear 0 0 write-only 0 No effect. #0 1 Clear the NMISR.IWDTST flag. #1 NMICR NMI Pin Interrupt Control Register 0x100 8 read-write 0x00 0xFF NFLTEN NMI Digital Filter Enable 7 7 read-write 0 Digital filter is disabled. #0 1 Digital filter is enabled. #1 Reserved This bit is read as 0. The write value should be 0. 6 6 read-write NFCLKSEL NMI Digital Filter Sampling Clock Select 4 5 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 Reserved These bits are read as 000. The write value should be 000. 1 3 read-write NMIMD NMI Detection Set 0 0 read-write 0 Falling edge #0 1 Rising edge #1 32 0x4 0-31 IELSR%s ICU Event Link Setting Register %s 0x300 32 read-write 0x00000000 0xFFFFFFFF Reserved These bits are read as 0000000. The write value should be 0000000. 25 31 read-write DTCE DTC Activation Enable 24 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 23 read-write IR Interrupt Status Flag 16 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 00000000. The write value should be 00000000. 8 15 read-write IELS ICU Event selection to NVIC Set the number for the event signal to be linked . 0 7 read-write 0x000 Nothing is selected 0x000 others See Event Table true 4 0x4 0-3 DELSR%s DMAC Event Link Setting Register %s 0x280 16 read-write 0x0000 0xFFFF Reserved These bits are read as 00000000. The write value should be 00000000. 8 15 read-write DELS Event selection to DMAC Start request 0 7 read-write 0x000 Nothing is selected. 0x000 others See Event Table true SELSR0 SYS Event Link Setting Register 0x200 16 read-write 0x0000 0xFFFF Reserved These bits are read as 00000000. The write value should be 00000000. 8 15 read-write SELS SYS Event Link Select 0 7 read-write 0x00 Disable event output to the associated low-power mode module 0x00 others Event signal number to be linked true WUPEN Wake Up Interrupt Enable Register 0x1A0 32 read-write 0x00000000 0xFFFFFFFF IIC0WUPEN IIC0 address match interrupt S/W standby returns enable 31 31 read-write 0 S/W standby returns by IIC0 address match interrupt is disabled #0 1 S/W standby returns by IIC0 address match interrupt is enabled #1 AGT1CBWUPEN AGT1 compare match B interrupt S/W standby returns enable 30 30 read-write 0 S/W standby returns by AGT1 compare match B interrupt is disabled #0 1 S/W standby returns by AGT1 compare match B interrupt is enabled #1 AGT1CAWUPEN AGT1 compare match A interrupt S/W standby returns enable 29 29 read-write 0 S/W standby returns by AGT1 compare match A interrupt is disabled #0 1 S/W standby returns by AGT1 compare match A interrupt is enabled #1 AGT1UDWUPEN AGT1 underflow interrupt S/W standby returns enable 28 28 read-write 0 S/W standby returns by AGT1 underflow interrupt is disabled #0 1 S/W standby returns by AGT1 underflow interrupt is enabled #1 USBFSWUPEN USBFS interrupt S/W standby returns enable 27 27 read-write 0 S/W standby returns by USBFS interrupt is disabled #0 1 S/W standby returns by USBFS interrupt is enabled #1 Reserved This bit is read as 0. The write value should be 0. 26 26 read-write RTCPRDWUPEN RCT period interrupt S/W standby returns enable 25 25 read-write 0 S/W standby returns by RTC period interrupt is disabled #0 1 S/W standby returns by RTC period interrupt is enabled #1 RTCALMWUPEN RTC alarm interrupt S/W standby returns enable 24 24 read-write 0 S/W standby returns by RTC alarm interrupt is disabled #0 1 S/W standby returns by RTC alarm interrupt is enabled #1 ACMPLP0WUPEN ACMPLP0 interrupt S/W standby returns enable 23 23 read-write 0 S/W standby returns by ACMPLP0 interrupt is disabled #0 1 S/W standby returns by ACMPLP0 interrupt is enabled #1 Reserved These bits are read as 00. The write value should be 00. 21 22 read-write VBATTWUPEN VBATT monitor interrupt S/W standby returns enable 20 20 read-write 0 S/W standby returns by VBATT monitor interrupt is disabled #0 1 S/W standby returns by VBATT monitor interrupt is enabled #1 LVD2WUPEN LVD2 interrupt S/W standby returns enable 19 19 read-write 0 S/W standby returns by LVD2 interrupt is disabled #0 1 S/W standby returns by LVD2 interrupt is enabled #1 LVD1WUPEN LVD1 interrupt S/W standby returns enable 18 18 read-write 0 S/W standby returns by LVD1 interrupt is disabled #0 1 S/W standby returns by LVD1 interrupt is enabled #1 KEYWUPEN Key interrupt S/W standby returns enable 17 17 read-write 0 S/W standby returns by KEY interrupt is disabled #0 1 S/W standby returns by KEY interrupt is enabled #1 IWDTWUPEN IWDT interrupt S/W standby returns enable 16 16 read-write 0 S/W standby returns by IWDT interrupt is disabled #0 1 S/W standby returns by IWDT interrupt is enabled #1 IRQWUPEN15 IRQ15 interrupt S/W standby returns enable 15 15 read-write 0 S/W standby returns by IRQ15 interrupt is disabled #0 1 S/W standby returns by IRQ15 interrupt is enabled #1 IRQWUPEN14 IRQ14 interrupt S/W standby returns enable 14 14 read-write 0 S/W standby returns by IRQ14 interrupt is disabled #0 1 S/W standby returns by IRQ14 interrupt is enabled #1 Reserved This bit is read as 0. The write value should be 0. 13 13 read-write IRQWUPEN12 IRQ12 interrupt S/W standby returns enable 12 12 read-write 0 S/W standby returns by IRQ12 interrupt is disabled #0 1 S/W standby returns by IRQ12 interrupt is enabled #1 IRQWUPEN11 IRQ11 interrupt S/W standby returns enable 11 11 read-write 0 S/W standby returns by IRQ11 interrupt is disabled #0 1 S/W standby returns by IRQ11 interrupt is enabled #1 IRQWUPEN10 IRQ10 interrupt S/W standby returns enable 10 10 read-write 0 S/W standby returns by IRQ10 interrupt is disabled #0 1 S/W standby returns by IRQ10 interrupt is enabled #1 IRQWUPEN9 IRQ9 interrupt S/W standby returns enable 9 9 read-write 0 S/W standby returns by IRQ9 interrupt is disabled #0 1 S/W standby returns by IRQ9 interrupt is enabled #1 IRQWUPEN8 IRQ8 interrupt S/W standby returns enable 8 8 read-write 0 S/W standby returns by IRQ8 interrupt is disabled #0 1 S/W standby returns by IRQ8 interrupt is enabled #1 IRQWUPEN7 IRQ7 interrupt S/W standby returns enable 7 7 read-write 0 S/W standby returns by IRQ7 interrupt is disabled #0 1 S/W standby returns by IRQ7 interrupt is enabled #1 IRQWUPEN6 IRQ6 interrupt S/W standby returns enable 6 6 read-write 0 S/W standby returns by IRQ6 interrupt is disabled #0 1 S/W standby returns by IRQ6 interrupt is enabled #1 IRQWUPEN5 IRQ5 interrupt S/W standby returns enable 5 5 read-write 0 S/W standby returns by IRQ5 interrupt is disabled #0 1 S/W standby returns by IRQ5 interrupt is enabled #1 IRQWUPEN4 IRQ4 interrupt S/W standby returns enable 4 4 read-write 0 S/W standby returns by IRQ4 interrupt is disabled #0 1 S/W standby returns by IRQ4 interrupt is enabled #1 IRQWUPEN3 IRQ3 interrupt S/W standby returns enable 3 3 read-write 0 S/W standby returns by IRQ3 interrupt is disabled #0 1 S/W standby returns by IRQ3 interrupt is enabled #1 IRQWUPEN2 IRQ2 interrupt S/W standby returns enable 2 2 read-write 0 S/W standby returns by IRQ2 interrupt is disabled #0 1 S/W standby returns by IRQ2 interrupt is enabled #1 IRQWUPEN1 IRQ1 interrupt S/W standby returns enable 1 1 read-write 0 S/W standby returns by IRQ1 interrupt is disabled #0 1 S/W standby returns by IRQ1 interrupt is enabled #1 IRQWUPEN0 IRQ0 interrupt S/W standby returns enable 0 0 read-write 0 S/W standby returns by IRQ0 interrupt is disabled #0 1 S/W standby returns by IRQ0 interrupt is enabled #1 IIC0 Inter-Integrated Circuit 0 0x40053000 0x00 16 registers 0x0B 6 registers 0x10 4 registers 0x16 2 registers ICCR1 I2C Bus Control Register 1 0x00 8 read-write 0x1F 0xFF ICE I2C Bus Interface Enable 7 7 read-write 0 Disable (SCLn and SDAn pins in inactive state) #0 1 Enable (SCLn and SDAn pins in active state) #1 IICRST I2C Bus Interface Internal Reset Note:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information). 6 6 read-write 0 Releases the RIIC reset or internal reset. #0 1 Initiates the RIIC reset or internal reset. #1 CLO Extra SCL Clock Cycle Output 5 5 read-write 0 Does not output an extra SCL clock cycle. #0 1 Outputs an extra SCL clock cycle. #1 SOWP SCLO/SDAO Write Protect 4 4 read-write 0 Bits SCLO and SDAO can be written #0 1 Bits SCLO and SDAO are protected. #1 SCLO SCL Output Control/Monitor 3 3 read-write 0 (Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low. #0 1 (Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin. #1 SDAO SDA Output Control/Monitor 2 2 read-write 0 (Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low. #0 1 (Read)The RIIC has released the SDAn pin./ (Write)The RIIC releases the SDAn pin. #1 SCLI SCL Line Monitor 1 1 read-only 0 SCLn line is low. #0 1 SCLn line is high. #1 SDAI SDA Line Monitor 0 0 read-only 0 SDAn line is low. #0 1 SDAn line is high. #1 ICCR2 I2C Bus Control Register 2 0x01 8 read-write 0x00 0xFF BBSY Bus Busy Detection Flag 7 7 read-only 0 The I2C bus is released (bus free state). #0 1 The I2C bus is occupied (bus busy state). #1 MST Master/Slave Mode 6 6 read-write 0 Slave mode #0 1 Master mode #1 TRS Transmit/Receive Mode 5 5 read-write 0 Receive mode #0 1 Transmit mode #1 Reserved This bit is read as 0. The write value should be 0. 4 4 read-write SP Stop Condition Issuance Request Note: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state). Note: Do not set the SP bit to 1 while a restart condition is being issued. 3 3 read-write 0 Does not request to issue a stop condition. #0 1 Requests to issue a stop condition. #1 RS Restart Condition Issuance Request Note: Do not set the RS bit to 1 while issuing a stop condition. 2 2 read-write 0 Does not request to issue a restart condition. #0 1 Requests to issue a restart condition. #1 ST Start Condition Issuance Request Set the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state). 1 1 read-write 0 Does not request to issue a start condition. #0 1 Requests to issue a start condition. #1 Reserved This bit is read as 0. The write value should be 0. 0 0 read-write ICMR1 I2C Bus Mode Register 1 0x02 8 read-write 0x08 0xFF MTWP MST/TRS Write Protect 7 7 read-write 0 Disables writing to the MST and TRS bits in ICCR2. #0 1 Enables writing to the MST and TRS bits in ICCR2. #1 CKS Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS ) 4 6 read-write 000 PCLKB/1 clock #000 001 PCLKB/2 clock #001 010 PCLKB/4 clock #010 011 PCLKB/8 clock #011 100 PCLKB/16 clock #100 101 PCLKB/32 clock #101 110 PCLKB/64 clock #110 111 PCLKB/128 clock #111 BCWP BC Write Protect (This bit is read as 1.) 3 3 write-only 0 Enables a value to be written in the BC[2:0] bits. #0 1 Disables a value to be written in the BC[2:0] bits. #1 BC Bit Counter 0 2 read-write 000 9 bits #000 001 2 bits #001 010 3 bits #010 011 4 bits #011 100 5 bits #100 101 6 bits #101 110 7 bits #110 111 8 bits #111 ICMR2 I2C Bus Mode Register 2 0x03 8 read-write 0x06 0xFF DLCS SDA Output Delay Clock Source Select 7 7 read-write 0 The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter. #0 1 The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter. #1 SDDL SDA Output Delay Counter 4 6 read-write 000 No output delay #000 001 1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles (ICMR2.DLCS=1) #001 010 2 fIIC cycles (ICMR2.DLCS=0) / 3 or 4 fIIC cycles (ICMR2.DLCS=1) #010 011 3 fIIC cycles (ICMR2.DLCS=0) / 5 or 6 fIIC cycles (ICMR2.DLCS=1) #011 100 4 fIIC cycles (ICMR2.DLCS=0) / 7 or 8 fIIC cycles (ICMR2.DLCS=1) #100 101 5 fIIC cycles (ICMR2.DLCS=0) / 9 or 10 fIIC cycles (ICMR2.DLCS=1) #101 110 6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1) #110 111 7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1) #111 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write TMOH Timeout H Count Control 2 2 read-write 0 Count is disabled while the SCLn line is at a high level. #0 1 Count is enabled while the SCLn line is at a high level. #1 TMOL Timeout L Count Control 1 1 read-write 0 Count is disabled while the SCLn line is at a low level. #0 1 Count is enabled while the SCLn line is at a low level. #1 TMOS Timeout Detection Time Select 0 0 read-write 0 Long mode is selected. #0 1 Short mode is selected. #1 ICMR3 I2C Bus Mode Register 3 0x04 8 read-write 0x00 0xFF SMBS SMBus/I2C Bus Selection 7 7 read-write 0 The I2C bus is selected. #0 1 The SMBus is selected. #1 WAIT WAIT Note: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand. 6 6 read-write 0 No WAIT (The period between ninth clock cycle and first clock cycle is not held low.) #0 1 WAIT (The period between ninth clock cycle and first clock cycle is held low.) #1 RDRFS RDRF Flag Set Timing Selection 5 5 read-write 0 The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.) #0 1 The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.) #1 ACKWP ACKBT Write Protect 4 4 read-write 0 Modification of the ACKBT bit is disabled. #0 1 Modification of the ACKBT bit is enabled. #1 ACKBT Transmit Acknowledge 3 3 read-write 0 A 0 is sent as the acknowledge bit (ACK transmission). #0 1 A 1 is sent as the acknowledge bit (NACK transmission). #1 ACKBR Receive Acknowledge 2 2 read-only 0 A 0 is received as the acknowledge bit (ACK reception). #0 1 A 1 is received as the acknowledge bit (NACK reception). #1 NF Noise Filter Stage Selection 0 1 read-write 00 Noise of up to one fIIC cycle is filtered out (single-stage filter). #00 01 Noise of up to two fIIC cycles is filtered out (2-stage filter). #01 10 Noise of up to three fIIC cycles is filtered out (3-stage filter). #10 11 Noise of up to four fIIC cycles is filtered out (4-stage filter) #11 ICFER I2C Bus Function Enable Register 0x05 8 read-write 0x72 0xFF Reserved This bit is read as 0. The write value should be 0. 7 7 read-write SCLE SCL Synchronous Circuit Enable 6 6 read-write 0 No SCL synchronous circuit is used. #0 1 An SCL synchronous circuit is used. #1 NFE Digital Noise Filter Circuit Enable 5 5 read-write 0 No digital noise filter circuit is used. #0 1 A digital noise filter circuit is used. #1 NACKE NACK Reception Transfer Suspension Enable 4 4 read-write 0 Transfer operation is not suspended during NACK reception (transfer suspension disabled). #0 1 Transfer operation is suspended during NACK reception (transfer suspension enabled). #1 SALE Slave Arbitration-Lost Detection Enable 3 3 read-write 0 Slave arbitration-lost detection is disabled. #0 1 Slave arbitration-lost detection is enabled. #1 NALE NACK Transmission Arbitration-Lost Detection Enable 2 2 read-write 0 NACK transmission arbitration-lost detection is disabled. #0 1 NACK transmission arbitration-lost detection is enabled. #1 MALE Master Arbitration-Lost Detection Enable 1 1 read-write 0 Master arbitration-lost detection is disabled. #0 1 Master arbitration-lost detection is enabled. #1 TMOE Timeout Function Enable 0 0 read-write 0 The timeout function is disabled. #0 1 The timeout function is enabled. #1 ICSER I2C Bus Status Enable Register 0x06 8 read-write 0x09 0xFF HOAE Host Address Enable 7 7 read-write 0 Host address detection is disabled. #0 1 Host address detection is enabled. #1 Reserved This bit is read as 0. The write value should be 0. 6 6 read-write DIDE Device-ID Address Detection Enable 5 5 read-write 0 Device-ID address detection is disabled. #0 1 Device-ID address detection is enabled. #1 Reserved This bit is read as 0. The write value should be 0. 4 4 read-write GCAE General Call Address Enable 3 3 read-write 0 General call address detection is disabled. #0 1 General call address detection is enabled. #1 SAR2E Slave Address Register 2 Enable 2 2 read-write 0 Slave address in SARL2 and SARU2 is disabled. #0 1 Slave address in SARL2 and SARU2 is enabled #1 SAR1E Slave Address Register 1 Enable 1 1 read-write 0 Slave address in SARL1 and SARU1 is disabled. #0 1 Slave address in SARL1 and SARU1 is enabled. #1 SAR0E Slave Address Register 0 Enable 0 0 read-write 0 Slave address in SARL0 and SARU0 is disabled. #0 1 Slave address in SARL0 and SARU0 is enabled. #1 ICIER I2C Bus Interrupt Enable Register 0x07 8 read-write 0x00 0xFF TIE Transmit Data Empty Interrupt Request Enable 7 7 read-write 0 Transmit data empty interrupt request (IIC_TXI) is disabled. #0 1 Transmit data empty interrupt request (IIC_TXI) is enabled. #1 TEIE Transmit End Interrupt Request Enable 6 6 read-write 0 Transmit end interrupt request (IIC_TEI) is disabled. #0 1 Transmit end interrupt request (IIC_TEI) is enabled. #1 RIE Receive Data Full Interrupt Request Enable 5 5 read-write 0 Receive data full interrupt request (IIC_RXI) is disabled. #0 1 Receive data full interrupt request (IIC_RXI) is enabled. #1 NAKIE NACK Reception Interrupt Request Enable 4 4 read-write 0 NACK reception interrupt request (NAKI) is disabled. #0 1 NACK reception interrupt request (NAKI) is enabled. #1 SPIE Stop Condition Detection Interrupt Request Enable 3 3 read-write 0 Stop condition detection interrupt request (SPI) is disabled. #0 1 Stop condition detection interrupt request (SPI) is enabled. #1 STIE Start Condition Detection Interrupt Request Enable 2 2 read-write 0 Start condition detection interrupt request (STI) is disabled. #0 1 Start condition detection interrupt request (STI) is enabled. #1 ALIE Arbitration-Lost Interrupt Request Enable 1 1 read-write 0 Arbitration-lost interrupt request (ALI) is disabled. #0 1 Arbitration-lost interrupt request (ALI) is enabled. #1 TMOIE Timeout Interrupt Request Enable 0 0 read-write 0 Timeout interrupt request (TMOI) is disabled. #0 1 Timeout interrupt request (TMOI) is enabled. #1 ICSR1 I2C Bus Status Register 1 0x08 8 read-write 0x00 0xFF HOA Host Address Detection Flag 7 7 read-write zeroToClear modify 0 Host address is not detected. #0 1 Host address is detected. #1 Reserved This bit is read as 0. The write value should be 0. 6 6 read-write DID Device-ID Address Detection Flag 5 5 read-write 0 Device-ID command is not detected. #0 1 Device-ID command is detected. #1 Reserved This bit is read as 0. The write value should be 0. 4 4 read-write GCA General Call Address Detection Flag 3 3 read-write 0 General call address is not detected. #0 1 General call address is detected. #1 AAS2 Slave Address 2 Detection Flag 2 2 read-write zeroToClear modify 0 Slave address 2 is not detected. #0 1 Slave address 2 is detected #1 AAS1 Slave Address 1 Detection Flag 1 1 read-write zeroToClear modify 0 Slave address 1 is not detected. #0 1 Slave address 1 is detected. #1 AAS0 Slave Address 0 Detection Flag 0 0 read-write zeroToClear modify 0 Slave address 0 is not detected. #0 1 Slave address 0 is detected. #1 ICSR2 I2C Bus Status Register 2 0x09 8 read-write 0x00 0xFF TDRE Transmit Data Empty Flag 7 7 read-only 0 ICDRT contains transmit data. #0 1 ICDRT contains no transmit data. #1 TEND Transmit End Flag 6 6 read-write zeroToClear modify 0 Data is being transmitted. #0 1 Data has been transmitted. #1 RDRF Receive Data Full Flag 5 5 read-write zeroToClear modify 0 ICDRR contains no receive data. #0 1 ICDRR contains receive data. #1 NACKF NACK Detection Flag 4 4 read-write zeroToClear modify 0 NACK is not detected. #0 1 NACK is detected. #1 STOP Stop Condition Detection Flag 3 3 read-write zeroToClear modify 0 Stop condition is not detected. #0 1 Stop condition is detected. #1 START Start Condition Detection Flag 2 2 read-write zeroToClear modify 0 Start condition is not detected. #0 1 Start condition is detected. #1 AL Arbitration-Lost Flag 1 1 read-write zeroToClear modify 0 Arbitration is not lost. #0 1 Arbitration is lost. #1 TMOF Timeout Detection Flag 0 0 read-write zeroToClear modify 0 Timeout is not detected. #0 1 Timeout is detected. #1 3 0x2 0-2 SARL%s Slave Address Register L%s 0x0A 8 read-write 0x00 0xFF SVA A slave address is set. 7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] } 0 7 read-write 3 0x2 0-2 SARU%s Slave Address Register U%s 0x0B 8 read-write 0x00 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write SVA9 10-Bit Address(bit9) 2 2 read-write SVA8 10-Bit Address(bit8) 1 1 read-write FS 7-Bit/10-Bit Address Format Selection 0 0 read-write 0 The 7-bit address format is selected. #0 1 The 10-bit address format is selected. #1 ICBRL I2C Bus Bit Rate Low-Level Register 0x10 8 read-write 0xFF 0xFF Reserved These bits are read as 111. The write value should be 111. 5 7 read-write BRL Bit Rate Low-Level Period (Low-level period of SCL clock) 0 4 read-write ICBRH I2C Bus Bit Rate High-Level Register 0x11 8 read-write 0xFF 0xFF Reserved These bits are read as 111. The write value should be 111. 5 7 read-write BRH Bit Rate High-Level Period (High-level period of SCL clock) 0 4 read-write ICDRT I2C Bus Transmit Data Register 0x12 8 read-write 0xFF 0xFF ICDRT 8-bit read-write register that stores transmit data. 0 7 read-write ICDRR I2C Bus Receive Data Register 0x13 8 read-only 0x00 0xFF ICDRR 8-bit register that stores the received data 0 7 read-only ICWUR I2C Bus Wake Up Unit Register 0x16 8 read-write 0x10 0xFF WUE Wakeup Function Enable 7 7 read-write 0 Wakeup function disabled #0 1 Wakeup function enabled. #1 WUIE Wakeup Interrupt Request Enable 6 6 read-write 0 Wakeup Interrupt Request (IIC0_WUI) disabled #0 1 Wakeup Interrupt Request (IIC0_WUI) enabled. #1 WUF Wakeup Event Occurrence Flag 5 5 read-write 0 Slave address does not match during wakeup function #0 1 Slave address matches during wakeup function. #1 WUACK ACK bit for Wakeup Mode 4 4 read-write 0 State of synchronous operation #0 1 State of asynchronous operation #1 Reserved These bits are read as 000. The write value should be 000. 1 3 read-write WUAFA Wakeup Analog Filter Additional Selection 0 0 read-write 0 Do not add the wakeup analog filter #0 1 Add the wakeup analog filter. #1 ICWUR2 I2C Bus Wake up Unit Register 2 0x17 8 read-write 0xFD 0xFF Reserved These bits are read as 11111. The write value should be 11111. 3 7 read-write WUSYF Wake-up Function Synchronous Operation Status Flag 2 2 read-only 0 IIC asynchronous circuit enable condition #0 1 IIC synchronous circuit enable condition. #1 WUASYF Wake-up Function Asynchronous Operation Status Flag 1 1 read-only 0 IIC synchronous circuit enable condition #0 1 IIC asynchronous circuit enable condition. #1 WUSEN Wake-up Function Synchronous Enable 0 0 read-write 0 IIC asynchronous circuit enable #0 1 IIC synchronous circuit enable #1 IIC1 Inter-Integrated Circuit 1 0x40053100 0x00 16 registers 0x0B 6 registers 0x10 4 registers ICCR1 I2C Bus Control Register 1 0x00 8 read-write 0x1F 0xFF ICE I2C Bus Interface Enable 7 7 read-write 0 Disable (SCLn and SDAn pins in inactive state) #0 1 Enable (SCLn and SDAn pins in active state) #1 IICRST I2C Bus Interface Internal Reset Note:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information). 6 6 read-write 0 Releases the RIIC reset or internal reset. #0 1 Initiates the RIIC reset or internal reset. #1 CLO Extra SCL Clock Cycle Output 5 5 read-write 0 Does not output an extra SCL clock cycle. #0 1 Outputs an extra SCL clock cycle. #1 SOWP SCLO/SDAO Write Protect 4 4 read-write 0 Bits SCLO and SDAO can be written #0 1 Bits SCLO and SDAO are protected. #1 SCLO SCL Output Control/Monitor 3 3 read-write 0 (Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low. #0 1 (Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin. #1 SDAO SDA Output Control/Monitor 2 2 read-write 0 (Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low. #0 1 (Read)The RIIC has released the SDAn pin./ (Write)The RIIC releases the SDAn pin. #1 SCLI SCL Line Monitor 1 1 read-only 0 SCLn line is low. #0 1 SCLn line is high. #1 SDAI SDA Line Monitor 0 0 read-only 0 SDAn line is low. #0 1 SDAn line is high. #1 ICCR2 I2C Bus Control Register 2 0x01 8 read-write 0x00 0xFF BBSY Bus Busy Detection Flag 7 7 read-only 0 The I2C bus is released (bus free state). #0 1 The I2C bus is occupied (bus busy state). #1 MST Master/Slave Mode 6 6 read-write 0 Slave mode #0 1 Master mode #1 TRS Transmit/Receive Mode 5 5 read-write 0 Receive mode #0 1 Transmit mode #1 Reserved This bit is read as 0. The write value should be 0. 4 4 read-write SP Stop Condition Issuance Request Note: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state). Note: Do not set the SP bit to 1 while a restart condition is being issued. 3 3 read-write 0 Does not request to issue a stop condition. #0 1 Requests to issue a stop condition. #1 RS Restart Condition Issuance Request Note: Do not set the RS bit to 1 while issuing a stop condition. 2 2 read-write 0 Does not request to issue a restart condition. #0 1 Requests to issue a restart condition. #1 ST Start Condition Issuance Request Set the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state). 1 1 read-write 0 Does not request to issue a start condition. #0 1 Requests to issue a start condition. #1 Reserved This bit is read as 0. The write value should be 0. 0 0 read-write ICMR1 I2C Bus Mode Register 1 0x02 8 read-write 0x08 0xFF MTWP MST/TRS Write Protect 7 7 read-write 0 Disables writing to the MST and TRS bits in ICCR2. #0 1 Enables writing to the MST and TRS bits in ICCR2. #1 CKS Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS ) 4 6 read-write 000 PCLKB/1 clock #000 001 PCLKB/2 clock #001 010 PCLKB/4 clock #010 011 PCLKB/8 clock #011 100 PCLKB/16 clock #100 101 PCLKB/32 clock #101 110 PCLKB/64 clock #110 111 PCLKB/128 clock #111 BCWP BC Write Protect (This bit is read as 1.) 3 3 write-only 0 Enables a value to be written in the BC[2:0] bits. #0 1 Disables a value to be written in the BC[2:0] bits. #1 BC Bit Counter 0 2 read-write 000 9 bits #000 001 2 bits #001 010 3 bits #010 011 4 bits #011 100 5 bits #100 101 6 bits #101 110 7 bits #110 111 8 bits #111 ICMR2 I2C Bus Mode Register 2 0x03 8 read-write 0x06 0xFF DLCS SDA Output Delay Clock Source Select 7 7 read-write 0 The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter. #0 1 The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter. #1 SDDL SDA Output Delay Counter 4 6 read-write 000 No output delay #000 001 1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles (ICMR2.DLCS=1) #001 010 2 fIIC cycles (ICMR2.DLCS=0) / 3 or 4 fIIC cycles (ICMR2.DLCS=1) #010 011 3 fIIC cycles (ICMR2.DLCS=0) / 5 or 6 fIIC cycles (ICMR2.DLCS=1) #011 100 4 fIIC cycles (ICMR2.DLCS=0) / 7 or 8 fIIC cycles (ICMR2.DLCS=1) #100 101 5 fIIC cycles (ICMR2.DLCS=0) / 9 or 10 fIIC cycles (ICMR2.DLCS=1) #101 110 6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1) #110 111 7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1) #111 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write TMOH Timeout H Count Control 2 2 read-write 0 Count is disabled while the SCLn line is at a high level. #0 1 Count is enabled while the SCLn line is at a high level. #1 TMOL Timeout L Count Control 1 1 read-write 0 Count is disabled while the SCLn line is at a low level. #0 1 Count is enabled while the SCLn line is at a low level. #1 TMOS Timeout Detection Time Select 0 0 read-write 0 Long mode is selected. #0 1 Short mode is selected. #1 ICMR3 I2C Bus Mode Register 3 0x04 8 read-write 0x00 0xFF SMBS SMBus/I2C Bus Selection 7 7 read-write 0 The I2C bus is selected. #0 1 The SMBus is selected. #1 WAIT WAIT Note: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand. 6 6 read-write 0 No WAIT (The period between ninth clock cycle and first clock cycle is not held low.) #0 1 WAIT (The period between ninth clock cycle and first clock cycle is held low.) #1 RDRFS RDRF Flag Set Timing Selection 5 5 read-write 0 The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.) #0 1 The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.) #1 ACKWP ACKBT Write Protect 4 4 read-write 0 Modification of the ACKBT bit is disabled. #0 1 Modification of the ACKBT bit is enabled. #1 ACKBT Transmit Acknowledge 3 3 read-write 0 A 0 is sent as the acknowledge bit (ACK transmission). #0 1 A 1 is sent as the acknowledge bit (NACK transmission). #1 ACKBR Receive Acknowledge 2 2 read-only 0 A 0 is received as the acknowledge bit (ACK reception). #0 1 A 1 is received as the acknowledge bit (NACK reception). #1 NF Noise Filter Stage Selection 0 1 read-write 00 Noise of up to one fIIC cycle is filtered out (single-stage filter). #00 01 Noise of up to two fIIC cycles is filtered out (2-stage filter). #01 10 Noise of up to three fIIC cycles is filtered out (3-stage filter). #10 11 Noise of up to four fIIC cycles is filtered out (4-stage filter) #11 ICFER I2C Bus Function Enable Register 0x05 8 read-write 0x72 0xFF Reserved This bit is read as 0. The write value should be 0. 7 7 read-write SCLE SCL Synchronous Circuit Enable 6 6 read-write 0 No SCL synchronous circuit is used. #0 1 An SCL synchronous circuit is used. #1 NFE Digital Noise Filter Circuit Enable 5 5 read-write 0 No digital noise filter circuit is used. #0 1 A digital noise filter circuit is used. #1 NACKE NACK Reception Transfer Suspension Enable 4 4 read-write 0 Transfer operation is not suspended during NACK reception (transfer suspension disabled). #0 1 Transfer operation is suspended during NACK reception (transfer suspension enabled). #1 SALE Slave Arbitration-Lost Detection Enable 3 3 read-write 0 Slave arbitration-lost detection is disabled. #0 1 Slave arbitration-lost detection is enabled. #1 NALE NACK Transmission Arbitration-Lost Detection Enable 2 2 read-write 0 NACK transmission arbitration-lost detection is disabled. #0 1 NACK transmission arbitration-lost detection is enabled. #1 MALE Master Arbitration-Lost Detection Enable 1 1 read-write 0 Master arbitration-lost detection is disabled. #0 1 Master arbitration-lost detection is enabled. #1 TMOE Timeout Function Enable 0 0 read-write 0 The timeout function is disabled. #0 1 The timeout function is enabled. #1 ICSER I2C Bus Status Enable Register 0x06 8 read-write 0x09 0xFF HOAE Host Address Enable 7 7 read-write 0 Host address detection is disabled. #0 1 Host address detection is enabled. #1 Reserved This bit is read as 0. The write value should be 0. 6 6 read-write DIDE Device-ID Address Detection Enable 5 5 read-write 0 Device-ID address detection is disabled. #0 1 Device-ID address detection is enabled. #1 Reserved This bit is read as 0. The write value should be 0. 4 4 read-write GCAE General Call Address Enable 3 3 read-write 0 General call address detection is disabled. #0 1 General call address detection is enabled. #1 SAR2E Slave Address Register 2 Enable 2 2 read-write 0 Slave address in SARL2 and SARU2 is disabled. #0 1 Slave address in SARL2 and SARU2 is enabled #1 SAR1E Slave Address Register 1 Enable 1 1 read-write 0 Slave address in SARL1 and SARU1 is disabled. #0 1 Slave address in SARL1 and SARU1 is enabled. #1 SAR0E Slave Address Register 0 Enable 0 0 read-write 0 Slave address in SARL0 and SARU0 is disabled. #0 1 Slave address in SARL0 and SARU0 is enabled. #1 ICIER I2C Bus Interrupt Enable Register 0x07 8 read-write 0x00 0xFF TIE Transmit Data Empty Interrupt Request Enable 7 7 read-write 0 Transmit data empty interrupt request (IIC_TXI) is disabled. #0 1 Transmit data empty interrupt request (IIC_TXI) is enabled. #1 TEIE Transmit End Interrupt Request Enable 6 6 read-write 0 Transmit end interrupt request (IIC_TEI) is disabled. #0 1 Transmit end interrupt request (IIC_TEI) is enabled. #1 RIE Receive Data Full Interrupt Request Enable 5 5 read-write 0 Receive data full interrupt request (IIC_RXI) is disabled. #0 1 Receive data full interrupt request (IIC_RXI) is enabled. #1 NAKIE NACK Reception Interrupt Request Enable 4 4 read-write 0 NACK reception interrupt request (NAKI) is disabled. #0 1 NACK reception interrupt request (NAKI) is enabled. #1 SPIE Stop Condition Detection Interrupt Request Enable 3 3 read-write 0 Stop condition detection interrupt request (SPI) is disabled. #0 1 Stop condition detection interrupt request (SPI) is enabled. #1 STIE Start Condition Detection Interrupt Request Enable 2 2 read-write 0 Start condition detection interrupt request (STI) is disabled. #0 1 Start condition detection interrupt request (STI) is enabled. #1 ALIE Arbitration-Lost Interrupt Request Enable 1 1 read-write 0 Arbitration-lost interrupt request (ALI) is disabled. #0 1 Arbitration-lost interrupt request (ALI) is enabled. #1 TMOIE Timeout Interrupt Request Enable 0 0 read-write 0 Timeout interrupt request (TMOI) is disabled. #0 1 Timeout interrupt request (TMOI) is enabled. #1 ICSR1 I2C Bus Status Register 1 0x08 8 read-write 0x00 0xFF HOA Host Address Detection Flag 7 7 read-write zeroToClear modify 0 Host address is not detected. #0 1 Host address is detected. #1 Reserved This bit is read as 0. The write value should be 0. 6 6 read-write DID Device-ID Address Detection Flag 5 5 read-write 0 Device-ID command is not detected. #0 1 Device-ID command is detected. #1 Reserved This bit is read as 0. The write value should be 0. 4 4 read-write GCA General Call Address Detection Flag 3 3 read-write 0 General call address is not detected. #0 1 General call address is detected. #1 AAS2 Slave Address 2 Detection Flag 2 2 read-write zeroToClear modify 0 Slave address 2 is not detected. #0 1 Slave address 2 is detected #1 AAS1 Slave Address 1 Detection Flag 1 1 read-write zeroToClear modify 0 Slave address 1 is not detected. #0 1 Slave address 1 is detected. #1 AAS0 Slave Address 0 Detection Flag 0 0 read-write zeroToClear modify 0 Slave address 0 is not detected. #0 1 Slave address 0 is detected. #1 ICSR2 I2C Bus Status Register 2 0x09 8 read-write 0x00 0xFF TDRE Transmit Data Empty Flag 7 7 read-only 0 ICDRT contains transmit data. #0 1 ICDRT contains no transmit data. #1 TEND Transmit End Flag 6 6 read-write zeroToClear modify 0 Data is being transmitted. #0 1 Data has been transmitted. #1 RDRF Receive Data Full Flag 5 5 read-write zeroToClear modify 0 ICDRR contains no receive data. #0 1 ICDRR contains receive data. #1 NACKF NACK Detection Flag 4 4 read-write zeroToClear modify 0 NACK is not detected. #0 1 NACK is detected. #1 STOP Stop Condition Detection Flag 3 3 read-write zeroToClear modify 0 Stop condition is not detected. #0 1 Stop condition is detected. #1 START Start Condition Detection Flag 2 2 read-write zeroToClear modify 0 Start condition is not detected. #0 1 Start condition is detected. #1 AL Arbitration-Lost Flag 1 1 read-write zeroToClear modify 0 Arbitration is not lost. #0 1 Arbitration is lost. #1 TMOF Timeout Detection Flag 0 0 read-write zeroToClear modify 0 Timeout is not detected. #0 1 Timeout is detected. #1 3 0x2 0-2 SARL%s Slave Address Register L%s 0x0A 8 read-write 0x00 0xFF SVA A slave address is set. 7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] } 0 7 read-write 3 0x2 0-2 SARU%s Slave Address Register U%s 0x0B 8 read-write 0x00 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write SVA9 10-Bit Address(bit9) 2 2 read-write SVA8 10-Bit Address(bit8) 1 1 read-write FS 7-Bit/10-Bit Address Format Selection 0 0 read-write 0 The 7-bit address format is selected. #0 1 The 10-bit address format is selected. #1 ICBRL I2C Bus Bit Rate Low-Level Register 0x10 8 read-write 0xFF 0xFF Reserved These bits are read as 111. The write value should be 111. 5 7 read-write BRL Bit Rate Low-Level Period (Low-level period of SCL clock) 0 4 read-write ICBRH I2C Bus Bit Rate High-Level Register 0x11 8 read-write 0xFF 0xFF Reserved These bits are read as 111. The write value should be 111. 5 7 read-write BRH Bit Rate High-Level Period (High-level period of SCL clock) 0 4 read-write ICDRT I2C Bus Transmit Data Register 0x12 8 read-write 0xFF 0xFF ICDRT 8-bit read-write register that stores transmit data. 0 7 read-write ICDRR I2C Bus Receive Data Register 0x13 8 read-only 0x00 0xFF ICDRR 8-bit register that stores the received data 0 7 read-only IWDT Independent Watchdog Timer 0x40044400 0x00 1 registers 0x04 2 registers IWDTRR IWDT Refresh Register 0x00 8 read-write 0xFF 0xFF IWDTRR The counter is refreshed by writing 0x00 and then writing 0xFF to this register. 0 7 read-write IWDTSR IWDT Status Register 0x04 16 read-write 0x0000 0xFFFF REFEF Refresh Error Flag 15 15 read-write zeroToClear modify 0 Refresh error not occurred #0 1 Refresh error occurred #1 UNDFF Underflow Flag 14 14 read-write zeroToClear modify 0 Underflow not occurred #0 1 Underflow occurred #1 CNTVAL Counter Value Value counted by the counter 0 13 read-only KINT Key Interrupt Function 0x40080000 0x00 1 registers 0x04 1 registers 0x08 1 registers KRCTL KEY Return Control Register 0x00 8 read-write 0x00 0xFF KRMD Usage of Key Interrupt Flags(KR0 to KR7) 7 7 read-write 0 Do not use key interrupt flags #0 1 Use key interrupt flags. #1 Reserved These bits are read as 000000. The write value should be 000000. 1 6 read-write KREG Detection Edge Selection (KRF0 to KRF7) 0 0 read-write 0 Falling edge #0 1 Rising edge #1 KRF KEY Return Flag Register 0x04 8 read-write 0x00 0xFF zeroToClear modify KRF7 Key interrupt flag 7 7 7 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF6 Key interrupt flag 6 6 6 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF5 Key interrupt flag 5 5 5 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF4 Key interrupt flag 4 4 4 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF3 Key interrupt flag 3 3 3 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF2 Key interrupt flag 2 2 2 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF1 Key interrupt flag 1 1 1 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF0 Key interrupt flag 0 0 0 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRM KEY Return Mode Register 0x08 8 read-write 0x00 0xFF KRM7 Key interrupt mode control 7 7 7 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM6 Key interrupt mode control 6 6 6 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM5 Key interrupt mode control 5 5 5 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM4 Key interrupt mode control 4 4 4 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM3 Key interrupt mode control 3 3 3 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM2 Key interrupt mode control 2 2 2 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM1 Key interrupt mode control 1 1 1 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM0 Key interrupt mode control 0 0 0 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 MSTP Module Stop Control B,C,D 0x40047000 0x00 12 registers MSTPCRB Module Stop Control Register B 0x00 32 read-write 0xFFFFFFFF 0xFFFFFFFF MSTPB31 Serial Communication Interface 0 Module Stop 31 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB30 Serial Communication Interface 1 Module Stop 30 30 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB29 Serial Communication Interface 2 Module Stop 29 29 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved These bits are read as 111111. The write value should be 111111. 23 28 read-write MSTPB22 Serial Communication Interface 9 Module Stop 22 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved These bits are read as 11. The write value should be 11. 20 21 read-write MSTPB19 Serial Peripheral Interface 0 Module Stop 19 19 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB18 Serial Peripheral Interface 1 Module Stop 18 18 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved These bits are read as 111111. The write value should be 111111. 12 17 read-write MSTPB11 Universal Serial Bus 2.0 FS Interface Module Stop 11 11 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved This bit is read as 1. The write value should be 1. 10 10 read-write MSTPB9 I2C Bus Interface 0 Module Stop 9 9 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB8 I2C Bus Interface 1 Module Stop 8 8 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved These bits are read as 11111. The write value should be 11111. 3 7 read-write MSTPB2 Controller Area Network Module Stop 2 2 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved These bits are read as 11. The write value should be 11. 0 1 read-write MSTPCRC Module Stop Control Register C 0x04 32 read-write 0xFFFFFFFF 0xFFFFFFFF MSTPC31 SCE5 Module Stop 31 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved These bits are read as 1111111111111111. The write value should be 1111111111111111. 15 30 read-write MSTPC14 Event Link Controller Module Stop 14 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC13 Data Operation Circuit Module Stop 13 13 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved These bits are read as 1111. The write value should be 1111. 9 12 read-write MSTPC8 Synchronous Serial Interface 0 Module Stop 8 8 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved These bits are read as 111. The write value should be 111. 5 7 read-write MSTPC4 Segment LCD Controller Module Stop 4 4 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC3 Capacitive Touch Sensing Unit Module Stop 3 3 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved This bit is read as 1. The write value should be 1. 2 2 read-write MSTPC1 Cyclic Redundancy Check Calculator Module Stop 1 1 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC0 Clock Frequency Accuracy Measurement Circuit Module Stop 0 0 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRD Module Stop Control Register D 0x08 32 read-write 0xFFFFFFFF 0xFFFFFFFF MSTPD31 Operational Amplifier Module Stop 31 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved This bit is read as 1. The write value should be 1. 30 30 read-write MSTPD29 Low-Power Analog Comparator Module Stop 29 29 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved These bits are read as 11111111. The write value should be 11111111. 21 28 read-write MSTPD20 12-Bit D/A Converter Module Stop 20 20 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD19 8-bit D/A Converter Module Stop 19 19 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved These bits are read as 11. The write value should be 11. 17 18 read-write MSTPD16 14-Bit A/D Converter Module Stop 16 16 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved This bit is read as 1. The write value should be 1. 15 15 read-write MSTPD14 Port Output Enable for GPT Module Stop 14 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved These bits are read as 1111111. The write value should be 1111111. 7 13 read-write MSTPD6 General PWM Timer 169 to 164 Module Stop 6 6 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD5 General PWM Timer 323 to 320 Module Stop 5 5 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved This bit is read as 1. The write value should be 1. 4 4 read-write MSTPD3 Asynchronous General Purpose Timer 0 Module Stop 3 3 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD2 Asynchronous General Purpose Timer 1 Module Stop 2 2 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved These bits are read as 11. The write value should be 11. 0 1 read-write MMPU Bus Master MPU 0x40000000 0x00 2 registers 0x200 256 registers 0x204 256 registers 0x208 256 registers 0x102 2 registers MMPUCTLA Bus Master MPU Control Register A 0x000 16 read-write 0x0000 0xFFFF KEY Key Code These bits are used to enable or disable writing of the OAD and ENABLE bit. 8 15 write-only Reserved These bits are read as 000000. The write value should be 000000. 2 7 read-write OAD Operation after detection 1 1 read-write 0 Non-maskable interrupt. #0 1 Internal reset. #1 ENABLE Master Group enable 0 0 read-write 0 Master Group A disabled #0 1 Master Group A enabled. #1 16 0x010 0-15 MMPUACA%s Group A Region %s Access Control Register 0x200 16 read-write 0x0000 0xFFFF Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 15 read-write WP Write protection 2 2 read-write 0 Write permission #0 1 Write protection #1 RP Read protection 1 1 read-write 0 Read permission #0 1 Read protection #1 ENABLE Region enable 0 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 16 0x010 0-15 MMPUSA%s Group A Region %s Start Address Register 0x204 32 read-write 0x00000000 0x00000003 MMPUSA Address where the region starts, for use in region determination. NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write 16 0x010 0-15 MMPUEA%s Group A Region %s End Address Register 0x208 32 read-write 0x00000003 0x00000003 MMPUEA Region end address register Address where the region end, for use in region determination. NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write MMPUPTA Group A Protection of Register 0x102 16 read-write 0x0000 0xFFFF KEY Write Keyword The data written to these bits are not stored. 8 15 write-only 0xA5 Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5. 0xA5 others Writing to the PROTECT bit is invalid. true Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write PROTECT Protection of register (MMPUSAn, MMPUEAn and MMPUACAn) 0 0 read-write 0 All Bus Master MPU Group A register writing is possible. #0 1 All Bus Master MPU Group A register writing is protected. Read is possible. #1 SMPU Bus Slave MPU 0x40000C00 0x00 2 registers 0x10 2 registers 0x14 2 registers 0x18 2 registers 0x20 12 registers 0x30 2 registers 0x34 2 registers 0x38 2 registers SMPUCTL Slave MPU Control Register 0x00 16 read-write 0x0000 0xFFFF KEY Key Code This bit is used to enable or disable rewriting of the PROTECT and OAD bit. 8 15 read-write 0xA5 Writing to the PROTECT and OAD bit is valid, when the KEY bits are written 0xA5. 0xA5 others Writing to the PROTECT and OAD bit is invalid. true Reserved These bits are read as 000000. The write value should be 000000. 2 7 read-write PROTECT Protection of register 1 1 read-write 0 All Bus Slave register writing is possible. #0 1 All Bus Slave register writing is protected. Read is possible. #1 OAD Master Group enable 0 0 read-write 0 Non-maskable interrupt. #0 1 Internal reset. #1 SMPUMBIU Access Control Register for MBIU 0x10 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 15 read-write WPGRPA Master Group A Write protection 3 3 read-write 0 Master group A write of memory protection disabled. #0 1 Master group A write of memory protection enabled. #1 RPGRPA Master Group A Read protection 2 2 read-write 0 Master group A read of memory protection disabled. #0 1 Master group A read of memory protection enabled. #1 Reserved These bits are read as 00. The write value should be 00. 0 1 read-write SMPUFBIU Access Control Register for FBIU 0x14 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 15 read-write WPGRPA Master Group A Write protection 3 3 read-write 0 Master group A write of memory protection disabled. #0 1 Master group A write of memory protection enabled. #1 RPGRPA Master Group A Read protection 2 2 read-write 0 Master group A read of memory protection disabled. #0 1 Master group A read of memory protection enabled. #1 WPCPU CPU Write protection 1 1 read-write 0 CPU write of memory protection disabled. #0 1 CPU write of memory protection enabled. #1 RPCPU CPU Read protection 0 0 read-write 0 CPU read of memory protection disabled. #0 1 CPU read of memory protection enabled. #1 SMPUSRAM0 Access Control Register for SRAM0 0x18 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 15 read-write WPGRPA Master Group A Write protection 3 3 read-write 0 Master group A write of memory protection disabled. #0 1 Master group A write of memory protection enabled. #1 RPGRPA Master Group A Read protection 2 2 read-write 0 Master group A read of memory protection disabled. #0 1 Master group A read of memory protection enabled. #1 WPCPU CPU Write protection 1 1 read-write 0 CPU write of memory protection disabled. #0 1 CPU write of memory protection enabled. #1 RPCPU CPU Read protection 0 0 read-write 0 CPU read of memory protection disabled. #0 1 CPU read of memory protection enabled. #1 3 0x4 0,2,6 SMPUP%sBIU Access Control Register for P%sBIU 0x20 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 15 read-write WPGRPA Master Group A Write protection 3 3 read-write 0 Master group A write of memory protection disabled. #0 1 Master group A write of memory protection enabled. #1 RPGRPA Master Group A Read protection 2 2 read-write 0 Master group A read of memory protection disabled. #0 1 Master group A read of memory protection enabled. #1 WPCPU CPU Write protection 1 1 read-write 0 CPU write of memory protection disabled. #0 1 CPU write of memory protection enabled. #1 RPCPU CPU Read protection 0 0 read-write 0 CPU read of memory protection disabled. #0 1 CPU read of memory protection enabled. #1 SPMON CPU Stack Pointer Monitor 0x40000D00 0x00 2 registers 0x04 14 registers 0x14 12 registers MSPMPUOAD Stack Pointer Monitor Operation After Detection Register 0x00 16 read-write 0x0000 0xFFFF KEY Write Keyword The data written to these bits are not stored. 8 15 write-only 0xA5 Writing to the OAD bit is valid, when the KEY bits are written 0xA5. 0xA5 others Writing to the OAD bit is invalid. true Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write OAD Operation after detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset. #1 MSPMPUCTL Stack Pointer Monitor Access Control Register 0x04 16 read-write 0x0000 0xFEFF Reserved These bits are read as 0000000. The write value should be 0000000. 9 15 read-write ERROR Stack Pointer Monitor Error Flag 8 8 read-write 0 Stack pointer has not overflowed or underflowed #0 1 Stack pointer has overflowed or underflowed #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write ENABLE Stack Pointer Monitor Enable 0 0 read-write 0 Stack pointer monitor is disabled #0 1 Stack pointer monitor is enabled. #1 MSPMPUPT Stack Pointer Monitor Protection Register 0x06 16 read-write 0x0000 0xFFFF KEY Write Keyword The data written to these bits are not stored. 8 15 write-only 0xA5 Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5. 0xA5 others Writing to the PROTECT bit is invalid. true Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write PROTECT Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) 0 0 read-write 0 Stack Pointer Monitor register writing is possible. #0 1 Stack Pointer Monitor register writing is protected. #1 MSPMPUSA Main Stack Pointer (MSP) Monitor Start Address Register 0x08 32 read-write 0x00000000 0x00000003 MSPMPUSA Region start address register Address where the region starts, for use in region determination. NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are fixed to 0. 0 31 read-write 0x1FF00000 0x200FFFFC MSPMPUEA Main Stack Pointer (MSP) Monitor End Address Register 0x0C 32 read-write 0x00000003 0x00000003 MSPMPUEA Region end address register Address where the region starts, for use in region determination. NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1. 0 31 read-write 0x1FF00003 0x200FFFFF PSPMPUOAD Stack Pointer Monitor Operation After Detection Register 0x10 16 read-write 0x0000 0xFFFF KEY Key Code The data written to these bits are not stored. 8 15 write-only 0xA5 Writing to the OAD bit is valid, when the KEY bits are written 0xA5. 0xA5 others Writing to the OAD bit is invalid. true Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write OAD Operation after detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset. #1 PSPMPUCTL Stack Pointer Monitor Access Control Register 0x14 16 read-write 0x0000 0xFEFF Reserved These bits are read as 0000000. The write value should be 0000000. 9 15 read-write ERROR Stack Pointer Monitor Error Flag 8 8 read-write 0 Stack pointer has not overflowed or underflowed #0 1 Stack pointer has overflowed or underflowed #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write ENABLE Stack Pointer Monitor Enable 0 0 read-write 0 Stack pointer monitor is disabled #0 1 Stack pointer monitor is enabled #1 PSPMPUPT Stack Pointer Monitor Protection Register 0x16 16 read-write 0x0000 0xFFFF KEY Key Code The data written to these bits are not stored. 8 15 write-only 0xA5 Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5. 0xA5 others Writing to the PROTECT bit is invalid. true Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write PROTECT Protection register (PSPMPUAC, PSPMPUSA and PSPMPUSE) 0 0 read-write 0 Stack Pointer Monitor register writing is possible. #0 1 Stack Pointer Monitor register writing is protected. #1 PSPMPUSA Process Stack Pointer (PSP) Monitor Start Address Register 0x18 32 read-write 0x00000000 0x00000003 PSPMPUSA Region start address register Address where the region starts, for use in region determination. NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are fixed to 0. 0 31 read-write 0x1FF00000 0x200FFFFC PSPMPUEA Process Stack Pointer (PSP) Monitor End Address Register 0x1C 32 read-write 0x00000003 0x00000003 PSPMPUEA Region end address register Address where the region starts, for use in region determination. NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1. 0 31 read-write 0x1FF00003 0x200FFFFF OPAMP OperationalAmplifier 0x40086000 0x08 5 registers AMPMC Operational amplifier mode control register 0x08 8 read-write 0x00 0xFF AMPSP Operation mode selection 7 7 read-write 0 Low-power mode (low-speed). #0 1 High-speed mode. #1 Reserved These bits are read as 000. The write value should be 000. 4 6 read-write AMPPC3 Operational amplifier precharge control status 3 3 read-write 0 Precharging is stopped. #0 1 Precharging is enabled. #1 AMPPC2 Operational amplifier precharge control status 2 2 read-write 0 Precharging is stopped. #0 1 Precharging is enabled. #1 AMPPC1 Operational amplifier precharge control status 1 1 read-write 0 Precharging is stopped. #0 1 Precharging is enabled. #1 AMPPC0 Operational amplifier precharge control status 0 0 read-write 0 Precharging is stopped. #0 1 Precharging is enabled. #1 AMPTRM Operational amplifier trigger mode control register 0x09 8 read-write 0x00 0xFF AMPTRM31 Operational amplifier function activation/stop trigger control 7 7 read-write 0 Software trigger mode(AMPTRM30=0)/An activation trigger mode(AMPTRM30=1). #0 1 Setting prohibited(AMPTRM30=0)/An activation and A/D trigger mode(AMPTRM30=1). #1 AMPTRM30 Operational amplifier function activation/stop trigger control 6 6 read-write 0 Software trigger mode(AMPTRM31=0)/Setting prohibited(AMPTRM31=1). #0 1 An activation trigger mode(AMPTRM31=0)/An activation and A/D trigger mode(AMPTRM31=1). #1 AMPTRM21 Operational amplifier function activation/stop trigger control 5 5 read-write 0 Software trigger mode(AMPTRM20=0)/An activation trigger mode(AMPTRM20=1). #0 1 Setting prohibited(AMPTRM20=0)/An activation and A/D trigger mode(AMPTRM20=1). #1 AMPTRM20 Operational amplifier function activation/stop trigger control 4 4 read-write 0 Software trigger mode(AMPTRM21=0)/Setting prohibited(AMPTRM21=1). #0 1 An activation trigger mode(AMPTRM21=0)/An activation and A/D trigger mode(AMPTRM21=1). #1 AMPTRM11 Operational amplifier function activation/stop trigger control 3 3 read-write 0 Software trigger mode(AMPTRM10=0)/An activation trigger mode(AMPTRM10=1). #0 1 Setting prohibited(AMPTRM10=0)/An activation and A/D trigger mode(AMPTRM10=1). #1 AMPTRM10 Operational amplifier function activation/stop trigger control 2 2 read-write 0 Software trigger mode(AMPTRM11=0)/Setting prohibited(AMPTRM11=1). #0 1 An activation trigger mode(AMPTRM11=0)/An activation and A/D trigger mode(AMPTRM11=1). #1 AMPTRM01 Operational amplifier function activation/stop trigger control 1 1 read-write 0 Software trigger mode(AMPTRM00=0)/An activation trigger mode(AMPTRM00=1). #0 1 Setting prohibited(AMPTRM00=0)/An activation and A/D trigger mode(AMPTRM00=1). #1 AMPTRM00 Operational amplifier function activation/stop trigger control 0 0 read-write 0 Software trigger mode(AMPTRM01=0)/Setting prohibited(AMPTRM01=1). #0 1 An activation trigger mode(AMPTRM01=0)/An activation and A/D trigger mode(AMPTRM01=1). #1 AMPTRS Operational Amplifier Activation Trigger Select Register 0x0A 8 read-write 0x00 0xFF AMPTRS ELC trigger selection Do not change the value of the AMPTRS register after setting the AMPTRM register. 0 1 read-write 00 Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 1.Operational amplifier 2: Operational amplifier An activation trigger 2.Operational amplifier 3: Operational amplifier An activation trigger 3 #00 01 Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 0.Operational amplifier 2: Operational amplifier An activation trigger 1.Operational amplifier 3: Operational amplifier An activation trigger 1 #01 10 Setting prohibited #10 11 Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 0.Operational amplifier 2: Operational amplifier An activation trigger 0.Operational amplifier 3: Operational amplifier An activation trigger 0 #11 AMPC Operational amplifier control register 0x0B 8 read-write 0x00 0xFF IREFE Operation control of operational amplifier reference current circuit 7 7 read-write 0 Operational amplifier reference current circuit is stopped. #0 1 Operation of operational amplifier reference current circuit is enabled. #1 Reserved These bits are read as 000. The write value should be 000. 4 6 read-write AMPE3 Operation control of operational amplifier(UNIT3) 3 3 read-write 0 Operation amplifier is stopped. #0 1 Software trigger mode: Operation of operational amplifier is enabled Operation of the operational amplifier reference current circuit is also enabled regardless of the IREFE bit se An activation trigger mode or An activation and A/D trigger mode: Wait for An activation is enabled. #1 AMPE2 Operation control of operational amplifier(UNIT2) 2 2 read-write 0 Operation amplifier is stopped. #0 1 Software trigger mode: Operation of operational amplifier is enabled Operation of the operational amplifier reference current circuit is also enabled regardless of the IREFE bit se An activation trigger mode or An activation and A/D trigger mode: Wait for An activation is enabled. #1 AMPE1 Operation control of operational amplifier(UNIT1) 1 1 read-write 0 Operation amplifier is stopped. #0 1 Software trigger mode: Operation of operational amplifier is enabled Operation of the operational amplifier reference current circuit is also enabled regardless of the IREFE bit se An activation trigger mode or An activation and A/D trigger mode: Wait for An activation is enabled. #1 AMPE0 Operation control of operational amplifier(UNIT0) 0 0 read-write 0 Operation amplifier is stopped. #0 1 Software trigger mode: Operation of operational amplifier is enabled Operation of the operational amplifier reference current circuit is also enabled regardless of the IREFE bit se An activation trigger mode or An activation and A/D trigger mode: Wait for AGT is enabled. #1 AMPMON Operational amplifier monitor register 0x0C 8 read-only 0x00 0xFF Reserved These bits are read as 0000. 4 7 read-only AMPMON3 Operational amplifier status(UNIT3) 3 3 read-only 0 Operational amplifier 3 is stopped. #0 1 Operational amplifier 3 is operating. #1 AMPMON2 Operational amplifier status(UNIT2) 2 2 read-only 0 Operational amplifier 2 is stopped. #0 1 Operational amplifier 2 is operating. #1 AMPMON1 Operational amplifier status(UNIT1) 1 1 read-only 0 Operational amplifier 1 is stopped. #0 1 Operational amplifier 1 is operating. #1 AMPMON0 Operational amplifier status(UNIT0) 0 0 read-only 0 Operational amplifier 0 is stopped. #0 1 Operational amplifier 0 is operating. #1 POEG Port Output Enable Module for GPT 0x40042000 0x00 512 registers 2 0x100 A,B POEGG%s POEG Group %s Setting Register 0x00 32 read-write 0x00000000 0xFFFFFFFF NFCS Noise Filter Clock Select 30 31 read-write 00 Sampling GTETRG pin input level for three times in every PCLKB. #00 01 Sampling GTETRG pin input level for three times in every PCLKB /8. #01 10 Sampling GTETRG pin input level for three times in every PCLKB /32. #10 11 Sampling GTETRG pin input level for three times in every PCLKB /128. #11 NFEN Noise Filter Enable 29 29 read-write 0 Filtering noise disabled #0 1 Filtering noise enabled #1 INV GTETRG Input Reverse 28 28 read-write 0 GTETRG Input #0 1 GTETRG Input Reversed. #1 Reserved These bits are read as 00000000000. The write value should be 00000000000. 17 27 read-write ST GTETRG Input Status Flag 16 16 read-only 0 GTETRG input after filtering is 0. #0 1 GTETRG input after filtering is 1. #1 OSTPE Oscillation Stop Detection Enable Note: Can be modified only once after a reset. 6 6 read-write 0 A output-disable request from the oscillation stop detection disabled. #0 1 A output-disable request from the oscillation stop detection enabled. #1 IOCE Output-disable Request Enable from GPT Note: Can be modified only once after a reset. 5 5 read-write 0 Output-disable request from the GPT disable request disabled #0 1 Output-disable request from the GPT disable request enabled. #1 PIDE Port Input Detection Enable Note: Can be modified only once after a reset. 4 4 read-write 0 Output-disable request from the GTETRG pins disabled #0 1 Output-disable request from the GTETRG pins enabled. #1 SSF Software Stop Flag 3 3 read-write 0 No output-disable request from software has occurred #0 1 Output-disable request from software occurred. #1 OSTPF Oscillation Stop Detection Flag 2 2 read-write zeroToClear modify 0 No output-disable request from oscillation stop detection has occurred #0 1 Output-disable request from oscillation stop detection occurred. #1 IOCF Output-disable Request Detection Flag from GPT 1 1 read-write zeroToClear modify 0 No output-disable request from the GPT disable request has occurred #0 1 Output-disable request from the GPT disable request occurred. #1 PIDF Port Input Detection Flag 0 0 read-write zeroToClear modify 0 No output-disable request from the GTETRGn pin has occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 SRAM SRAM Control 0x40002000 0x00 1 registers 0x04 1 registers 0x08 1 registers 0xC0 5 registers 0xD0 1 registers 0xD4 1 registers 0xD8 1 registers PARIOAD SRAM Parity Error Operation After Detection Register 0x00 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write OAD Operation after Detection 0 0 read-write 1 Reset #1 0 Non maskable interrupt. #0 SRAMPRCR SRAM Protection Register 0x04 8 read-write 0x00 0xFF KW Write Key Code 1 7 write-only 1111000 Writing to the RAMPRCR bit is valid, when the KEY bits are written 1111000b. #1111000 others Writing to the RAMPRCR bit is invalid. true SRAMPRCR Register Write Control 0 0 read-write 0 Disable writes to protected registers #0 1 Enable writes to protected registers. #1 ECCMODE ECC Operating Mode Control Register 0xC0 8 read-write 0x00 0xFF Reserved These bits are read as 000000. The write value should be 000000. 2 7 read-write ECCMOD ECC Operating Mode Select 0 1 read-write 00 Disable ECC function #00 01 Setting prohibited #01 10 Enable ECC function without error checking #10 11 Enable ECC function with error checking #11 ECC2STS ECC 2-Bit Error Status Register 0xC1 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write ECC2ERR ECC 2-Bit Error Status 0 0 read-write zeroToClear modify 0 No 2-bit ECC error occurred #0 1 2-bit ECC error occurred. #1 ECC1STSEN ECC 1-Bit Error Information Update Enable Register 0xC2 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write E1STSEN ECC 1-Bit Error Information Update Enable 0 0 read-write 0 Disables updating of the 1-bit ECC error information. #0 1 Enables updating of the 1-bit ECC error information. #1 ECC1STS ECC 1-Bit Error Status Register 0xC3 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write ECC1ERR ECC 1-Bit Error Status 0 0 read-write zeroToClear modify 0 No 1-bit ECC error occurred #0 1 1-bit ECC error occurred #1 ECCPRCR ECC Protection Register 0xC4 8 read-write 0x00 0xFF KW Write Key Code 1 7 write-only 1111000 Writing to the ECCRAMPRCR bit is valid, when the KEY bits are written 1111000b. #1111000 others Writing to the ECCRAMPRCR bit is invalid. true ECCPRCR Register Write Control 0 0 read-write 0 Disable writes to the protected registers #0 1 Enable writes to the protected registers #1 ECCPRCR2 ECC Protection Register 2 0xD0 8 read-write 0x00 0xFF KW2 Write Key Code 1 7 write-only 1111000 These bits enable or disable writes to the ECCPRCR2 bit.. #1111000 others Writing to the ECCRAMPRCR2 bit is invalid. true ECCPRCR2 Register Write Control 0 0 read-write 0 Disable writes to the protected registers #0 1 Enable writes to the protected registers. #1 ECCETST ECC Test Control Register 0xD4 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write TSTBYP ECC Bypass Select 0 0 read-write 0 ECC bypass disabled. #0 1 ECC bypass enabled. #1 ECCOAD SRAM ECC Error Operation After Detection Register 0xD8 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write OAD Operation after Detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 RTC Realtime Clock 0x40044000 0x00 1 registers 0x02 1 registers 0x02 1 registers 0x04 1 registers 0x04 1 registers 0x06 1 registers 0x06 1 registers 0x08 1 registers 0x08 1 registers 0x0A 1 registers 0x0C 1 registers 0x0E 3 registers 0x10 1 registers 0x12 1 registers 0x12 1 registers 0x14 1 registers 0x14 1 registers 0x16 1 registers 0x16 1 registers 0x18 1 registers 0x18 1 registers 0x1A 1 registers 0x1A 1 registers 0x1C 2 registers 0x1C 3 registers 0x1E 1 registers 0x22 1 registers 0x24 1 registers 0x28 1 registers 0x2A 5 registers 0x40 6 registers 0x52 48 registers 0x52 48 registers 0x54 48 registers 0x54 48 registers 0x56 48 registers 0x56 48 registers 0x5A 48 registers 0x5A 48 registers 0x5C 48 registers R64CNT 64-Hz Counter 0x00 8 read-only 0x00 0x80 F1HZ 1Hz 6 6 read-only F2HZ 2Hz 5 5 read-only F4HZ 4Hz 4 4 read-only F8HZ 8Hz 3 3 read-only F16HZ 16Hz 2 2 read-only F32HZ 32Hz 1 1 read-only F64HZ 64Hz 0 0 read-only RSECCNT Second Counter 0x02 8 read-write 0x00 0x00 SEC10 10-Second Count Counts from 0 to 5 for 60-second counting. 4 6 read-write SEC1 1-Second Count Counts from 0 to 9 every second. When a carry is generated, 1 is added to the tens place. 0 3 read-write BCNT0 Binary Counter 0 RSECCNT 0x02 8 read-write 0x00 0x00 BCNT0 The BCNT0 counter is a readable/writable 32-bit binary counter b7 to b0. 0 7 read-write RMINCNT Minute Counter 0x04 8 read-write 0x00 0x00 MIN10 10-Minute Count Counts from 0 to 5 for 60-minute counting. 4 6 read-write MIN1 1-Minute Count Counts from 0 to 9 every minute. When a carry is generated, 1 is added to the tens place. 0 3 read-write BCNT1 Binary Counter 1 RMINCNT 0x04 8 read-write 0x00 0x00 BCNT1 The BCNT1 counter is a readable/writable 32-bit binary counter b15 to b8. 0 7 read-write RHRCNT Hour Counter 0x06 8 read-write 0x00 0x00 PM Time Counter Setting for a.m./p.m. 6 6 read-write 0 a.m. #0 1 p.m. #1 HR10 10-Hour Count Counts from 0 to 2 once per carry from the ones place. 4 5 read-write HR1 1-Hour Count Counts from 0 to 9 once per hour. When a carry is generated, 1 is added to the tens place. 0 3 read-write BCNT2 Binary Counter 2 RHRCNT 0x06 8 read-write 0x00 0x00 BCNT2 The BCNT2 counter is a readable/writable 32-bit binary counter b23 to b16. 0 7 read-write RWKCNT Day-of-Week Counter 0x08 8 read-write 0x00 0x00 DAYW Day-of-Week Counting 0 2 read-write 000 Sunday #000 001 Monday #001 010 Tuesday #010 011 Wednesday #011 100 Thursday #100 101 Friday #101 110 Saturday #110 111 Setting Prohibited #111 BCNT3 Binary Counter 3 RWKCNT 0x08 8 read-write 0x00 0x00 BCNT3 The BCNT3 counter is a readable/writable 32-bit binary counter b31 to b24. 0 7 read-write RDAYCNT Day Counter 0x0A 8 read-write 0x00 0xC0 DATE10 10-Day Count Counts from 0 to 3 once per carry from the ones place. 4 5 read-write DATE1 1-Day Count Counts from 0 to 9 once per day. When a carry is generated, 1 is added to the tens place. 0 3 read-write RMONCNT Month Counter 0x0C 8 read-write 0x00 0xE0 Reserved These bits are read as 000. The write value should be 000. 5 7 read-write MON10 10-Month Count Counts from 0 to 1 once per carry from the ones place. 4 4 read-write MON1 1-Month Count Counts from 0 to 9 once per month. When a carry is generated, 1 is added to the tens place. 0 3 read-write RYRCNT Year Counter 0x0E 16 read-write 0x0000 0xFF00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 15 read-write YR10 10-Year Count Counts from 0 to 9 once per carry from ones place. When a carry is generated in the tens place, 1 is added to the hundreds place. 4 7 read-write YR1 1-Year Count Counts from 0 to 9 once per year. When a carry is generated, 1 is added to the tens place. 0 3 read-write RSECAR Second Alarm Register 0x10 8 read-write 0x00 0x00 ENB Compare enable 7 7 read-write 0 The register value is not compared with the RSECCNT counter value. #0 1 The register value is compared with the RSECCNT counter value. #1 SEC10 10-Seconds Value for the tens place of seconds 4 6 read-write SEC1 1-Second Value for the ones place of seconds 0 3 read-write BCNT0AR Binary Counter 0 Alarm Register RSECAR 0x10 8 read-write 0x00 0x00 BCNT0AR he BCNT0AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b7 to b0. 0 7 read-write RMINAR Minute Alarm Register 0x12 8 read-write 0x00 0x00 ENB Compare enable 7 7 read-write 0 The register value is not compared with the RMINCNT counter value. #0 1 The register value is compared with the RMINCNT counter value. #1 MIN10 10-Minute Count Value for the tens place of minutes 4 6 read-write MIN1 1-Minute Count Value for the ones place of minutes 0 3 read-write BCNT1AR Binary Counter 1 Alarm Register RMINAR 0x12 8 read-write 0x00 0x00 BCNT1AR he BCNT1AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b15 to b8. 0 7 read-write RHRAR Hour Alarm Register 0x14 8 read-write 0x00 0x00 ENB Compare enable 7 7 read-write 0 The register value is not compared with the RHRCNT counter value. #0 1 The register value is compared with the RHRCNT counter value. #1 PM Time Counter Setting for a.m./p.m. 6 6 read-write 0 a.m. #0 1 p.m. #1 HR10 10-Hour Count Value for the tens place of hours 4 5 read-write HR1 1-Hour Count Value for the ones place of hours 0 3 read-write BCNT2AR Binary Counter 2 Alarm Register RHRAR 0x14 8 read-write 0x00 0x00 BCNT2AR The BCNT2AR counter is a readable/writable 32-bit binary counter b23 to b16. 0 7 read-write RWKAR Day-of-Week Alarm Register 0x16 8 read-write 0x00 0x00 ENB Compare enable 7 7 read-write 0 The register value is not compared with the RWKCNT counter value. #0 1 The register value is compared with the RWKCNT counter value. #1 Reserved These bits are read as 0000. The write value should be 0000. 3 6 read-write DAYW Day-of-Week Counting 0 2 read-write 000 Sunday #000 001 Monday #001 010 Tuesday #010 011 Wednesday #011 100 Thursday #100 101 Friday #101 110 Saturday #110 111 Setting Prohibited #111 BCNT3AR Binary Counter 3 Alarm Register RWKAR 0x16 8 read-write 0x00 0x00 BCNT3AR The BCNT3AR counter is a readable/writable 32-bit binary counter b31 to b24. 0 7 read-write RDAYAR Date Alarm Register 0x18 8 read-write 0x00 0x00 ENB Compare enable 7 7 read-write 0 The register value is not compared with the RDAYCNT counter value. #0 1 The register value is compared with the RDAYCNT counter value. #1 Reserved This bit is read as 0. The write value should be 0. 6 6 read-write DATE10 10 Days Value for the tens place of days 4 5 read-write DATE1 1 Day Value for the ones place of days 0 3 read-write BCNT0AER Binary Counter 0 Alarm Enable Register RDAYAR 0x18 8 read-write 0x00 0x00 ENB The BCNT0AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b7 to b0. 0 7 read-write RMONAR Month Alarm Register 0x1A 8 read-write 0x00 0x00 ENB Compare enable 7 7 read-write 0 The register value is not compared with the RMONCNT counter value. #0 1 The register value is compared with the RMONCNT counter value. #1 Reserved These bits are read as 00. The write value should be 00. 5 6 read-write MON10 10 Months Value for the tens place of months 4 4 read-write MON1 1 Month Value for the ones place of months 0 3 read-write BCNT1AER Binary Counter 1 Alarm Enable Register RMONAR 0x1A 8 read-write 0x00 0x00 ENB The BCNT1AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b15 to b8. 0 7 read-write RYRAR Year Alarm Register 0x1C 16 read-write 0x0000 0xFF00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 15 read-write YR10 10 Years Value for the tens place of years 4 7 read-write YR1 1 Year Value for the ones place of years 0 3 read-write BCNT2AER Binary Counter 2 Alarm Enable Register RYRAR 0x1C 16 read-write 0x0000 0xFF00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 15 read-write ENB The BCNT2AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b23 to b16. 0 7 read-write RYRAREN Year Alarm Enable Register 0x1E 8 read-write 0x00 0x00 ENB Compare enable 7 7 read-write 0 The register value is not compared with the RYRCNT counter value. #0 1 The register value is compared with the RYRCNT counter value. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 0 6 read-write BCNT3AER Binary Counter 3 Alarm Enable Register RYRAREN 0x1E 8 read-write 0x00 0x00 ENB The BCNT3AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b31 to b24. 0 7 read-write RCR1 RTC Control Register 1 0x22 8 read-write 0x00 0x0A PES Periodic Interrupt Select 4 7 read-write 0110 A periodic interrupt is generated every 1/256 second((RCR4.RCKSEL = 0)./A periodic interrupt is generated every 1/128 second((RCR4.RCKSEL = 1). #0110 0111 A periodic interrupt is generated every 1/128 second. #0111 1000 A periodic interrupt is generated every 1/64 second. #1000 1001 A periodic interrupt is generated every 1/32 second. #1001 1010 A periodic interrupt is generated every 1/16 second. #1010 1011 A periodic interrupt is generated every 1/8 second. #1011 1100 A periodic interrupt is generated every 1/4 second. #1100 1101 A periodic interrupt is generated every 1/2 second. #1101 1110 A periodic interrupt is generated every 1 second. #1110 1111 A periodic interrupt is generated every 2 seconds. #1111 others No periodic interrupts are generated. true RTCOS RTCOUT Output Select 3 3 read-write 0 RTCOUT outputs 1 Hz. #0 1 RTCOUT outputs 64 Hz. #1 PIE Periodic Interrupt Enable 2 2 read-write 0 A periodic interrupt request is disabled. #0 1 A periodic interrupt request is enabled. #1 CIE Carry Interrupt Enable 1 1 read-write 0 A carry interrupt request is disabled. #0 1 A carry interrupt request is enabled. #1 AIE Alarm Interrupt Enable 0 0 read-write 0 An alarm interrupt request is disabled. #0 1 An alarm interrupt request is enabled. #1 RCR2 RTC Control Register 2 0x24 8 read-write 0x00 0x0E CNTMD Count Mode Select 7 7 read-write 0 The calendar count mode. #0 1 The binary count mode. #1 HR24 Hours Mode 6 6 read-write 0 The RTC operates in 12-hour mode. #0 1 The RTC operates in 24-hour mode. #1 AADJP Automatic Adjustment Period Select (When the LOCO clock is selected, the setting of this bit is disabled.) 5 5 read-write 0 The RADJ.ADJ[5:0] setting value is adjusted from the count value of the prescaler every minute. #0 1 The RADJ.ADJ[5:0] setting value is adjusted from the count value of the prescaler every 10 seconds. #1 AADJE Automatic Adjustment Enable (When the LOCO clock is selected, the setting of this bit is disabled.) 4 4 read-write 0 Automatic adjustment is disabled. #0 1 Automatic adjustment is enabled. #1 RTCOE RTCOUT Output Enable 3 3 read-write 0 RTCOUT output disabled. #0 1 RTCOUT output enabled. #1 ADJ30 30-Second Adjustment 2 2 read-write 0 Writing is invalid.(write) / In normal time operation, or 30-second adjustment has completed.(read) #0 1 30-second adjustment is executed.(write) / During 30-second adjustment.(read) #1 RESET RTC Software Reset 1 1 read-write 0 Writing is invalid.(write) / In normal time operation, or an RTC software reset has completed.(read) #0 1 The prescaler and the target registers for RTC software reset *1 are initialized.(write) / During an RTC software reset.(read) #1 START Start 0 0 read-write 0 Prescaler and time counter are stopped. #0 1 Prescaler and time counter operate normally. #1 RCR4 RTC Control Register 4 0x28 8 read-write 0x00 0xFE Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write RCKSEL Count Source Select 0 0 read-write 0 Sub-clock oscillator is selected. #0 1 LOCO clock oscillator is selected. #1 RFRH Frequency Register H 0x2A 16 read-write 0x0000 0xFFFE Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 1 15 read-write RFC16 Frequency Comparison Value (b16) To generate the operating clock from the LOCOclock, this bit sets the comparison value of the 128-Hz clock cycle. 0 0 read-write RFRL Frequency Register L 0x2C 16 read-write 0x0000 0x0000 RFC Frequency Comparison Value(b15-b0) To generate the operating clock from the main clock, this bit sets the comparison value of the 128-Hz clock cycle. 0 15 read-write RADJ Time Error Adjustment Register 0x2E 8 read-write 0x00 0x00 PMADJ Plus-Minus 6 7 read-write 00 Adjustment is not performed. #00 01 Adjustment is performed by the addition to the prescaler. #01 10 Adjustment is performed by the subtraction from the prescaler. #10 11 Setting prohibited #11 ADJ Adjustment Value These bits specify the adjustment value from the prescaler. 0 5 read-write 3 0x2 0-2 RTCCR%s Time Capture Control Register %s 0x40 8 read-write 0x00 0x00 Reserved This bit is read as 0. The write value should be 0. 7 7 read-write Reserved This bit is read as 0. The write value should be 0. 6 6 read-write TCNF Time Capture Noise Filter Control 4 5 read-write 00 The noise filter is off. #00 01 Setting prohibited #01 10 The noise filter is on (count source). #10 11 The noise filter is on (count source by divided by 32). #11 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write TCST Time Capture Status 2 2 read-write zeroToClear modify 0 No event is detected. #0 1 An event is detected. #1 TCCT Time Capture Control 0 1 read-write 00 No event is detected. #00 01 Rising edge is detected. #01 10 Falling edge is detected. #10 11 Both edges are detected. #11 3 0x10 0-2 RSECCP%s Second Capture Register %s 0x52 8 read-only 0x00 0x00 Reserved This bit is read as 0. 7 7 read-only SEC10 10-Second Capture Capture value for the tens place of seconds 4 6 read-only SEC1 1-Second Capture Capture value for the ones place of seconds 0 3 read-only 3 0x10 0-2 BCNT0CP%s BCNT0 Capture Register %s RSECCP%s 0x52 8 read-only 0x00 0x00 BCNT0CP BCNT0CP is a read-only register that captures the BCNT0 value when a time capture event is detected. 0 7 read-only 3 0x10 0-2 RMINCP%s Minute Capture Register %s 0x54 8 read-only 0x00 0x00 Reserved This bit is read as 0. 7 7 read-only MIN10 10-Minute Capture Capture value for the tens place of minutes 4 6 read-only MIN1 1-Minute Capture Capture value for the ones place of minutes 0 3 read-only 3 0x10 0-2 BCNT1CP%s BCNT1 Capture Register %s RMINCP%s 0x54 8 read-only 0x00 0x00 BCNT1CP BCNT1CP is a read-only register that captures the BCNT1 value when a time capture event is detected. 0 7 read-only 3 0x10 0-2 RHRCP%s Hour Capture Register %s 0x56 8 read-only 0x00 0x00 Reserved This bit is read as 0. 7 7 read-only PM A.m./p.m. select for time counter setting. 6 6 read-only 0 a.m. #0 1 p.m. #1 HR10 10-Minute Capture Capture value for the tens place of minutes 4 5 read-only HR1 1-Minute Capture Capture value for the ones place of minutes 0 3 read-only 3 0x10 0-2 BCNT2CP%s BCNT2 Capture Register %s RHRCP%s 0x56 8 read-only 0x00 0x00 BCNT2CP BCNT2CP is a read-only register that captures the BCNT2 value when a time capture event is detected. 0 7 read-only 3 0x10 0-2 RDAYCP%s Date Capture Register %s 0x5A 8 read-only 0x00 0x00 Reserved These bits are read as 00. 6 7 read-only DATE10 10-Day Capture Capture value for the tens place of minutes 4 5 read-only DATE1 1-Day Capture Capture value for the ones place of minutes 0 3 read-only 3 0x10 0-2 BCNT3CP%s BCNT3 Capture Register %s RDAYCP%s 0x5A 8 read-only 0x00 0x00 BCNT3CP BCNT3CP is a read-only register that captures the BCNT3 value when a time capture event is detected. 0 7 read-only 3 0x10 0-2 RMONCP%s Month Capture Register %s 0x5C 8 read-only 0x00 0x00 MON10 10-Month Capture Capture value for the tens place of months 4 4 read-only MON1 1-Month Capture Capture value for the ones place of months 0 3 read-only SCI0 Serial Communication Interface 0 0x40070000 0x00 1 registers 0x00 3 registers 0x02 3 registers 0x04 1 registers 0x04 12 registers 0x0E 2 registers 0x0E 4 registers 0x10 2 registers 0x10 13 registers SMR Serial Mode Register (SCMR.SMIF = 0) 0x00 8 read-write 0x00 0xFF CM Communication Mode 7 7 read-write 0 Asynchronous mode or simple I2C mode #0 1 Clock synchronous mode #1 CHR Character Length (Valid only in asynchronous mode) 6 6 read-write 0 Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 8bit data length(SCMR.CHR1=1) #0 1 Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 7bit data length(SCMR.CHR1=1) #1 PE Parity Enable (Valid only in asynchronous mode) 5 5 read-write 0 Parity bit addition is not performed (transmitting) / Parity bit checking is not performed ( receiving ) #0 1 The parity bit is added (transmitting) / The parity bit is checked (receiving) #1 PM Parity Mode (Valid only when the PE bit is 1) 4 4 read-write 0 Selects even parity #0 1 Selects odd parity #1 STOP Stop Bit Length (Valid only in asynchronous mode) 3 3 read-write 0 1 stop bit #0 1 2 stop bits #1 MP Multi-Processor Mode (Valid only in asynchronous mode) 2 2 read-write 0 Multi-processor communications function is disabled #0 1 Multi-processor communications function is enabled #1 CKS Clock Select 0 1 read-write 00 PCLK clock #00 01 PCLK/4 clock #01 10 PCLK/16 clock #10 11 PCLK/64 clock #11 SMR_SMCI Serial mode register (SCMR.SMIF = 1) SMR 0x00 8 read-write 0x00 0xFF GM GSM Mode 7 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 BLK Block Transfer Mode 6 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 PE Parity Enable (Valid only in asynchronous mode) 5 5 read-write 0 Setting Prohibited #0 1 Set this bit to 1 in smart card interface mode. #1 PM Parity Mode (Valid only when the PE bit is 1) 4 4 read-write 0 Selects even parity #0 1 Selects odd parity #1 BCP Base Clock Pulse (Valid only in asynchronous mode) 2 3 read-write 00 93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock cycles(S=32) (SCMR.BCP2=1) #00 01 128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock cycles(S=64) (SCMR.BCP2=1) #01 10 186 clock cycles(S=186) (SCMR.BCP2=0) / 372 clock cycles(S=372) (SCMR.BCP2=1) #10 11 512 clock cycles(S=512) (SCMR.BCP2=0) / 256 clock cycles(S=256) (SCMR.BCP2=1) #11 CKS Clock Select 0 1 read-write 00 PCLK clock #00 01 PCLK/4 clock #01 10 PCLK/16 clock #10 11 PCLK/64 clock #11 BRR Bit Rate Register 0x01 8 read-write 0xFF 0xFF BRR BRR is an 8-bit register that adjusts the bit rate. 0 7 read-write SCR Serial Control Register (SCMR.SMIF = 0) 0x02 8 read-write 0x00 0xFF TIE Transmit Interrupt Enable 7 7 read-write 0 SCI_TXI interrupt request is disabled #0 1 SCI_TXI interrupt request is enabled #1 RIE Receive Interrupt Enable 6 6 read-write 0 SCI_RXI and SCI_ERI interrupt requests are disabled #0 1 SCI_RXI and SCI_ERI interrupt requests are enabled #1 TE Transmit Enable 5 5 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 RE Receive Enable 4 4 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 MPIE Multi-Processor Interrupt Enable (Valid in asynchronous mode when SMR.MP = 1) 3 3 read-write 0 Normal reception #0 1 When the data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF,ORER and FER in SSR to 1 is disabled. When the data with the multiprocessor bit set to 1 is received, the MPIE bit is automatically cleared to 0, and normal reception is resumed. #1 TEIE Transmit End Interrupt Enable 2 2 read-write 0 SCI_TEI interrupt request is disabled #0 1 SCI_TEI interrupt request is enabled #1 CKE Clock Enable 0 1 read-write 00 The SCKn pin is available for use as an I/O port in accord with the I/O port settings.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) #00 01 The clock with the same frequency as the bit rate is output from the SCKn pin.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) #01 others The clock with a frequency 16 times the bit rate should be input from the SCKn pin. (when SEMR.ABCS bit is 0) Input a clock signal with a frequency 8 times the bit rate when the SEMR.ABCS bit is 1.(Asynchronous mode) / The SCKn pin functions as the clock input pin(Clock synchronous mode) true SCR_SMCI Serial Control Register (SCMR.SMIF =1) SCR 0x02 8 read-write 0x00 0xFF TIE Transmit Interrupt Enable 7 7 read-write 0 A SCI_TXI interrupt request is disabled #0 1 A SCI_TXI interrupt request is enabled #1 RIE Receive Interrupt Enable 6 6 read-write 0 SCI_RXI and SCI_ERI interrupt requests are disabled #0 1 SCI_RXI and SCI_ERI interrupt requests are enabled #1 TE Transmit Enable 5 5 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 RE Receive Enable 4 4 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 MPIE Multi-Processor Interrupt Enable 3 3 read-write TEIE Transmit End Interrupt Enable 2 2 read-write CKE Clock Enable 0 1 read-write 00 Output disabled(SMR_SMCI.GM=0) / Output fixed low(SMR_SMCI.GM=1) #00 01 Clock Output #01 10 Setting prohibited(SMR_SMCI.GM=0) / Output fixed High(SMR_SMCI.GM=1) #10 11 Setting prohibited(SMR_SMCI.GM=0) / Clock Output(SMR_SMCI.GM=1) #11 TDR Transmit Data Register 0x03 8 read-write 0xFF 0xFF TDR TDR is an 8-bit register that stores transmit data. 0 7 read-write SSR Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) 0x04 8 read-write 0x84 0xFF TDRE Transmit Data Empty Flag 7 7 read-write zeroToClear modify 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 RDRF Receive Data Full Flag 6 6 read-write zeroToClear modify 0 No received data is in RDR register #0 1 Received data is in RDR register #1 ORER Overrun Error Flag 5 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 FER Framing Error Flag 4 4 read-write zeroToClear modify 0 No framing error occurred #0 1 A framing error has occurred #1 PER Parity Error Flag 3 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 TEND Transmit End Flag 2 2 read-only 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 MPB Multi-Processor 1 1 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 MPBT Multi-Processor Bit Transfer 0 0 read-write 0 Data transmission cycles #0 1 ID transmission cycles #1 SSR_FIFO Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) SSR 0x04 8 read-write 0x80 0xFD TDFE Transmit FIFO data empty flag 7 7 read-write zeroToClear modify 0 The quantity of transmit data written in FTDR exceeds the specified transmit triggering number. #0 1 The quantity of transmit data written in FTDR is equal to or less than the specified transmit triggering number #1 RDF Receive FIFO data full flag 6 6 read-write zeroToClear modify 0 The quantity of receive data written in FRDR falls below the specified receive triggering number. #0 1 The quantity of receive data written in FRDR is equal to or greater than the specified receive triggering number. #1 ORER Overrun Error Flag 5 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 FER Framing Error Flag 4 4 read-write zeroToClear modify 0 No framing error occurred. #0 1 A framing error has occurred. #1 PER Parity Error Flag 3 3 read-write zeroToClear modify 0 No parity error occurred. #0 1 A parity error has occurred. #1 TEND Transmit End Flag 2 2 read-write zeroToClear modify 0 A character is being transmitted or standing by for transmission. #0 1 Character transfer has been completed. #1 Reserved This bit is read as 0. The write value should be 0. 1 1 read-write DR Receive Data Ready flag (Valid only in asynchronous mode(including multi-processor) and FIFO selected) 0 0 read-write zeroToClear modify 0 Receiving is in progress, or no received data has remained in FRDR after normally completed receiving.(receive FIFO is empty) #0 1 Next receive data has not been received for a period after normal completed receiving, , when data is stored in FIFO to equal or less than receive triggering number. #1 SSR_SMCI Serial Status Register(SCMR.SMIF = 1) SSR 0x04 8 read-write 0x84 0xFF TDRE Transmit Data Empty Flag 7 7 read-write zeroToClear modify 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 RDRF Receive Data Full Flag 6 6 read-write zeroToClear modify 0 No received data is in RDR register #0 1 Received data is in RDR register #1 ORER Overrun Error Flag 5 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 ERS Error Signal Status Flag 4 4 read-write zeroToClear modify 0 Low error signal not responded #0 1 Low error signal responded #1 PER Parity Error Flag 3 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 TEND Transmit End Flag 2 2 read-only 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 MPB Multi-Processor This bit should be 0 in smart card interface mode. 1 1 read-only MPBT Multi-Processor Bit Transfer This bit should be 0 in smart card interface mode. 0 0 read-write RDR Receive Data Register 0x05 8 read-only 0x00 0xFF RDR RDR is an 8-bit register that stores receive data. 0 7 read-only SCMR Smart Card Mode Register 0x06 8 read-write 0xF2 0xFF BCP2 Base Clock Pulse 2 Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits 7 7 read-write 0 S=93(SMR.BCP[1:0]=00), 128(SMR.BCP[1:0]=01), 186(SMR.BCP[1:0]=10), 512(SMR.BCP[1:0]=11) #0 1 S=32(SMR.BCP[1:0]=00), 64(SMR.BCP[1:0]=01), 372(SMR.BCP[1:0]=10), 256(SMR.BCP[1:0]=11) #1 Reserved These bits are read as 11. The write value should be 11. 5 6 read-write CHR1 Character Length 1 (Only valid in asynchronous mode) 4 4 read-write 0 Transmit/receive in 9-bit data length #0 1 Transmit/receive in 8-bit data length(SMR.CHR=0) / in 7bit data length(SMR.CHR=1) #1 SDIR Transmitted/Received Data Transfer Direction NOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode. Set this bit to 1 if operation is to be in simple I2C mode. 3 3 read-write 0 Transfer with LSB first #0 1 Transfer with MSB first #1 SINV Transmitted/Received Data Invert Set this bit to 0 if operation is to be in simple I2C mode. 2 2 read-write 0 TDR contents are transmitted as they are. Receive data is stored as it is in RDR. #0 1 TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. #1 Reserved This bit is read as 1. The write value should be 1. 1 1 read-write SMIF Smart Card Interface Mode Select 0 0 read-write 0 Non-smart card interface mode(Asynchronous mode, clock synchronous mode, simple SPI mode, or simple I2C mode) #0 1 Smart card interface mode #1 SEMR Serial Extended Mode Register 0x07 8 read-write 0x00 0xFF RXDESEL Asynchronous Start Bit Edge Detection Select (Valid only in asynchronous mode) 7 7 read-write 0 The low level on the RXDn pin is detected as the start bit. #0 1 A falling edge on the RXDn pin is detected as the start bit. #1 BGDM Baud Rate Generator Double-Speed Mode Select (Only valid the CKE[1] bit in SCR is 0 in asynchronous mode). 6 6 read-write 0 Baud rate generator outputs the clock with normal frequency. #0 1 Baud rate generator outputs the clock with doubled frequency. #1 NFEN Digital Noise Filter Function Enable (The NFEN bit should be 0 without simple I2C mode and asynchronous mode.) In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input. 5 5 read-write 0 Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is disabled. #0 1 Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is enabled. #1 ABCS Asynchronous Mode Base Clock Select (Valid only in asynchronous mode) 4 4 read-write 0 Selects 16 base clock cycles for 1-bit period. #0 1 Selects 8 base clock cycles for 1-bit period. #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 (Valid only in asynchronous mode and SCR.CKE[1]=0) 3 3 read-write 0 Clock cycles for 1-bit period is decided with combination between BGDM and ABCS in SEMR. #0 1 Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator. #1 BRME Bit Rate Modulation Enable 2 2 read-write 0 Bit rate modulation function is disabled. #0 1 Bit rate modulation function is enabled. #1 Reserved These bits are read as 00. The write value should be 00. 0 1 read-write SNFR Noise Filter Setting Register 0x08 8 read-write 0x00 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write NFCS Noise Filter Clock Select 0 2 read-write 000 The clock signal divided by 1 is used with the noise filter.(In asynchronous mode) #000 001 The clock signal divided by 1 is used with the noise filter.(In simple I2C mode) #001 010 The clock signal divided by 2 is used with the noise filter.(In simple I2C mode) #010 011 The clock signal divided by 4 is used with the noise filter.(In simple I2C mode) #011 100 The clock signal divided by 8 is used with the noise filter.(In simple I2C mode) #100 others Settings prohibited. true SIMR1 I2C Mode Register 1 0x09 8 read-write 0x00 0xFF IICDL SDA Delay Output Select Cycles below are of the clock signal from the on-chip baud rate generator. 3 7 read-write 00000 No output delay #00000 others (IICDL - 1 ) to IIDCDL cycles. The delay is in the clock cycles from the on-chip baud rate generator. true Reserved These bits are read as 00. The write value should be 00. 1 2 read-write IICM Simple I2C Mode Select 0 0 read-write 0 Asynchronous mode, Multi-processor mode, Clock synchronous mode(SCMR.SMIF=0) /Smart card interface mode(SCMR.SMIF=1) #0 1 Simple I2C mode(SCMR.SMIF=0) / Setting prohibited.(SCMR.SMIF=1) #1 SIMR2 I2C Mode Register 2 0x0A 8 read-write 0x00 0xFF Reserved These bits are read as 00. The write value should be 00. 6 7 read-write IICACKT ACK Transmission Data 5 5 read-write 0 ACK transmission #0 1 NACK transmission and reception of ACK/NACK #1 Reserved These bits are read as 000. The write value should be 000. 2 4 read-write IICCSC Clock Synchronization 1 1 read-write 0 No synchronization with the clock signal #0 1 Synchronization with the clock signal #1 IICINTM I2C Interrupt Mode Select 0 0 read-write 0 Use ACK/NACK interrupts. #0 1 Use reception and transmission interrupts #1 SIMR3 I2C Mode Register 3 0x0B 8 read-write 0x00 0xFF IICSCLS SCL Output Select 6 7 read-write 00 Serial clock output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SSCLn pin. #10 11 Place the SSCLn pin in the high-impedance state. #11 IICSDAS SDA Output Select 4 5 read-write 00 Serial data output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SSDAn pin. #10 11 Place the SSDAn pin in the high-impedance state. #11 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag (When 0 is written to IICSTIF, it is cleared to 0.) 3 3 read-write zeroToClear modify 0 There are no requests for generating conditions or a condition is being generated. #0 1 A start, restart, or stop condition is completely generated. #1 IICSTPREQ Stop Condition Generation 2 2 read-write 0 A stop condition is not generated. #0 1 A stop condition is generated. #1 IICRSTAREQ Restart Condition Generation 1 1 read-write 0 A restart condition is not generated. #0 1 A restart condition is generated. #1 IICSTAREQ Start Condition Generation 0 0 read-write 0 A start condition is not generated. #0 1 A start condition is generated. #1 SISR I2C Status Register 0x0C 8 read-only 0x00 0xCB Reserved These bits are read as 00. 6 7 read-only Reserved This bit is read as 0. 5 5 read-only Reserved This bit is read as 0. 4 4 read-only Reserved This bit is read as 0. 3 3 read-only Reserved This bit is read as 0. 2 2 read-only Reserved This bit is read as 0. 1 1 read-only IICACKR ACK Reception Data Flag 0 0 read-only 0 ACK received #0 1 NACK received #1 SPMR SPI Mode Register 0x0D 8 read-write 0x00 0xFF CKPH Clock Phase Select 7 7 read-write 0 Clock is not delayed. #0 1 Clock is delayed. #1 CKPOL Clock Polarity Select 6 6 read-write 0 Clock polarity is not inverted. #0 1 Clock polarity is inverted #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write MFF Mode Fault Flag 4 4 read-write zeroToClear modify 0 No mode fault error #0 1 Mode fault error #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write MSS Master Slave Select 2 2 read-write 0 Transmission is through the TXDn pin and reception is through the RXDn pin (master mode). #0 1 Reception is through the TXDn pin and transmission is through the RXDn pin (slave mode). #1 CTSE CTS Enable 1 1 read-write 0 CTS function is disabled (RTS output function is enabled). #0 1 CTS function is enabled. #1 SSE SSn Pin Function Enable 0 0 read-write 0 SSn pin function is disabled. #0 1 SSn pin function is enabled. #1 TDRHL Transmit 9-bit Data Register 0x0E 16 read-write 0xFFFF 0xFFFF TDRHL TDRHL is a 16-bit register that stores transmit data. 0 15 write-only FTDRHL Transmit FIFO Data Register HL TDRHL 0x0E 16 write-only 0xFFFF 0xFFFF Reserved The write value should be 111111. 10 15 write-only MPBT Multi-processor transfer bit flag (Valid only in asynchronous mode and SMR.MP=1 and FIFO selected) 9 9 write-only 0 Data transmission cycles #0 1 ID transmission cycles #1 TDAT Serial transmit data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 8 write-only FTDRH Transmit FIFO Data Register H TDRHL 0x0E 8 write-only 0xFF 0xFF Reserved The write value should be 111111. 2 7 write-only MPBT Multi-processor transfer bit flag (Valid only in asynchronous mode and SMR.MP=1 and FIFO selected) 1 1 write-only 0 Data transmission cycles #0 1 ID transmission cycles #1 TDATH Serial transmit data (b8) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 0 write-only FTDRL Transmit FIFO Data Register L TDRHL 0x0F 8 write-only 0xFF 0xFF TDATL Serial transmit data(b7-b0) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 7 write-only RDRHL Receive 9-bit Data Register 0x10 16 read-only 0x0000 0xFFFF RDRHL RDRHL is an 16-bit register that stores receive data. 0 15 read-only FRDRHL Receive FIFO Data Register HL RDRHL 0x10 16 read-only 0x0000 0xFFFF Reserved This bit is read as 0. 15 15 read-only RDF Receive FIFO data full flag (It is same as SSR.RDF) 14 14 read-only 0 The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number. #0 1 The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number. #1 ORER Overrun error flag (It is same as SSR.ORER) 13 13 read-only 0 No overrun error occurred. #0 1 An overrun error has occurred. #1 FER Framing error flag 12 12 read-only 0 No framing error occurred at the first data of FRDRH and FRDRL. #0 1 A framing error has occurred at the first data of FRDRH and FRDRL. #1 PER Parity error flag 11 11 read-only 0 No parity error occurred at the first data of FRDRH and FRDRL. #0 1 A parity error has occurred at the first data of FRDRH and FRDRL. #1 DR Receive data ready flag (It is same as SSR.DR) 10 10 read-only 0 Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving. #0 1 Next receive data has not been received for a period after normal completed receiving. #1 MPB Multi-processor bit flag (Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0]) 9 9 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 RDAT Serial receive data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 8 read-only FRDRH Receive FIFO Data Register H RDRHL 0x10 8 read-only 0x00 0xFF Reserved This bit is read as 0. 7 7 read-only RDF Receive FIFO data full flag (It is same as SSR.RDF) 6 6 read-only 0 The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number. #0 1 The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number. #1 ORER Overrun error flag (It is same as SSR.ORER) 5 5 read-only 0 No overrun error occurred #0 1 An overrun error has occurred #1 FER Framing error flag 4 4 read-only 0 No framing error occurred at the first data of FRDRH and FRDRL #0 1 A framing error has occurred at the first data of FRDRH and FRDRL #1 PER Parity error flag 3 3 read-only 0 No parity error occurred at the first data of FRDRH and FRDRL #0 1 A parity error has occurred at the first data of FRDRH and FRDRL #1 DR Receive data ready flag (It is same as SSR.DR) 2 2 read-only 0 Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving. #0 1 Next receive data has not been received for a period after normal completed receiving. #1 MPB Multi-processor bit flag (Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0]) 1 1 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 RDATH Serial receive data(b8) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 0 read-only FRDRL Receive FIFO Data Register L RDRHL 0x11 8 read-only 0x00 0xFF RDATL Serial receive data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) NOTE: When reading both of FRDRH register and FRDRL register, please read by an order of the FRDRH register and the FRDRL register. 0 7 read-only MDDR Modulation Duty Register 0x12 8 read-write 0xFF 0xFF MDDR MDDR corrects the bit rate adjusted by the BRR register. 0 7 read-write DCCR Data Compare Match Control Register 0x13 8 read-write 0x40 0xFF DCME Data Compare Match Enable (Valid only in asynchronous mode(including multi-processor) 7 7 read-write 0 Address match function is disabled. #0 1 Address match function is enabled #1 IDSEL ID frame select (Valid only in asynchronous mode(including multi-processor) 6 6 read-write 0 Always compare data regardless of the value of the MPB bit. #0 1 Compare data when the MPB bit is 1 (ID frame) only. #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write DFER Data Compare Match Framing Error Flag 4 4 read-write zeroToClear modify 0 No framing error occurred #0 1 A framing error has occurred #1 DPER Data Compare Match Parity Error Flag 3 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 Reserved These bits are read as 00. The write value should be 00. 1 2 read-write DCMF Data Compare Match Flag 0 0 read-write zeroToClear modify 0 No matched #0 1 Matched #1 FCR FIFO Control Register 0x14 16 read-write 0xF800 0xFFFF RSTRG RTS Output Active Trigger Number Select (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 12 15 read-write 0000 Trigger number 0 #0000 others Triger number n (n= 0-15) true RTRG Receive FIFO data trigger number (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 8 11 read-write 0000 Trigger number 0 #0000 others Triger number n (n= 0-15) true TTRG Transmit FIFO data trigger number (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 4 7 read-write 0000 Trigger number 0 #0000 others Triger number n (n= 0-15) true DRES Receive data ready error select bit (When detecting a reception data ready, the interrupt request is selected.) 3 3 read-write 0 reception data full interrupt (RXI) #0 1 receive error interrupt (ERI) #1 TFRST Transmit FIFO Data Register Reset (Valid only in FCR.FM=1) 2 2 read-write 0 The number of data stored in FTDRH and FTDRL register are NOT made 0 #0 1 The number of data stored in FTDRH and FTDRL register are made 0 #1 RFRST Receive FIFO Data Register Reset (Valid only in FCR.FM=1) 1 1 read-write 0 The number of data stored in FRDRH and FRDRL register are NOT made 0 #0 1 The number of data stored in FRDRH and FRDRL register are made 0 #1 FM FIFO Mode Select (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 0 0 read-write 0 Non-FIFO mode(Selects o TDR/RDR for communication) #0 1 FIFO mode (Selects to FTDRH and FTDRL/FRDRH and FRDRL for communication) #1 FDR FIFO Data Count Register 0x16 16 read-only 0x0000 0xFFFF Reserved These bits are read as 000. 13 15 read-only T Transmit FIFO Data Count Indicate the quantity of non-transmit data stored in FTDRH and FTDRL (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1) 8 12 read-only Reserved These bits are read as 000. 5 7 read-only R Receive FIFO Data Count Indicate the quantity of receive data stored in FRDRH and FRDRL (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1) 0 4 read-only LSR Line Status Register 0x18 16 read-only 0x0000 0xFFFF Reserved These bits are read as 000. 13 15 read-only PNUM Parity Error Count Indicates the quantity of data with a parity error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL). 8 12 read-only Reserved This bit is read as 0. 7 7 read-only FNUM Framing Error Count Indicates the quantity of data with a framing error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL). 2 6 read-only Reserved This bit is read as 0. 1 1 read-only ORER Overrun Error Flag (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 0 read-only 0 No overrun error occurred #0 1 An overrun error has occurred #1 CDR Compare Match Data Register 0x1A 16 read-write 0x0000 0xFFFF Reserved These bits are read as 0000000. The write value should be 0000000. 9 15 read-write CMPD Compare Match Data Compare data pattern for address match wake-up function 0 8 read-write SPTR Serial Port Register 0x1C 8 read-write 0x03 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write SPB2IO Serial port break I/O bit (It's selected whether the value of SPB2DT is output to TxD terminal.) 2 2 read-write 0 The value of SPB2DT bit is not output in TXD pin. #0 1 The value of SPB2DT bit is output in TXD pin. #1 SPB2DT Serial port break data select bit (The output level of TxD terminal is selected when SCR.TE = 0.) 1 1 read-write 0 Low level is output on TXD pin #0 1 High level is output on TXD pin #1 RXDMON Serial input data monitor bit (The state of the RXD terminal is shown.) 0 0 read-only 0 RXD pin is low. #0 1 RXD pin is high. #1 SCI1 Serial Communication Interface 1 0x40070020 SCI2 Serial Communication Interface 2 0x40070040 0x00 1 registers 0x00 3 registers 0x02 3 registers 0x04 1 registers 0x04 12 registers 0x0E 2 registers 0x0E 4 registers 0x10 2 registers 0x10 13 registers SMR Serial Mode Register (SCMR.SMIF = 0) 0x00 8 read-write 0x00 0xFF CM Communication Mode 7 7 read-write 0 Asynchronous mode or simple I2C mode #0 1 Clock synchronous mode #1 CHR Character Length (Valid only in asynchronous mode) 6 6 read-write 0 Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 8bit data length(SCMR.CHR1=1) #0 1 Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 7bit data length(SCMR.CHR1=1) #1 PE Parity Enable (Valid only in asynchronous mode) 5 5 read-write 0 Parity bit addition is not performed (transmitting) / Parity bit checking is not performed ( receiving ) #0 1 The parity bit is added (transmitting) / The parity bit is checked (receiving) #1 PM Parity Mode (Valid only when the PE bit is 1) 4 4 read-write 0 Selects even parity #0 1 Selects odd parity #1 STOP Stop Bit Length (Valid only in asynchronous mode) 3 3 read-write 0 1 stop bit #0 1 2 stop bits #1 MP Multi-Processor Mode (Valid only in asynchronous mode) 2 2 read-write 0 Multi-processor communications function is disabled #0 1 Multi-processor communications function is enabled #1 CKS Clock Select 0 1 read-write 00 PCLK clock #00 01 PCLK/4 clock #01 10 PCLK/16 clock #10 11 PCLK/64 clock #11 SMR_SMCI Serial mode register (SCMR.SMIF = 1) SMR 0x00 8 read-write 0x00 0xFF GM GSM Mode 7 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 BLK Block Transfer Mode 6 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 PE Parity Enable (Valid only in asynchronous mode) 5 5 read-write 0 Setting Prohibited #0 1 Set this bit to 1 in smart card interface mode. #1 PM Parity Mode (Valid only when the PE bit is 1) 4 4 read-write 0 Selects even parity #0 1 Selects odd parity #1 BCP Base Clock Pulse (Valid only in asynchronous mode) 2 3 read-write 00 93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock cycles(S=32) (SCMR.BCP2=1) #00 01 128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock cycles(S=64) (SCMR.BCP2=1) #01 10 186 clock cycles(S=186) (SCMR.BCP2=0) / 372 clock cycles(S=372) (SCMR.BCP2=1) #10 11 512 clock cycles(S=512) (SCMR.BCP2=0) / 256 clock cycles(S=256) (SCMR.BCP2=1) #11 CKS Clock Select 0 1 read-write 00 PCLK clock #00 01 PCLK/4 clock #01 10 PCLK/16 clock #10 11 PCLK/64 clock #11 BRR Bit Rate Register 0x01 8 read-write 0xFF 0xFF BRR BRR is an 8-bit register that adjusts the bit rate. 0 7 read-write SCR Serial Control Register (SCMR.SMIF = 0) 0x02 8 read-write 0x00 0xFF TIE Transmit Interrupt Enable 7 7 read-write 0 SCI_TXI interrupt request is disabled #0 1 SCI_TXI interrupt request is enabled #1 RIE Receive Interrupt Enable 6 6 read-write 0 SCI_RXI and SCI_ERI interrupt requests are disabled #0 1 SCI_RXI and SCI_ERI interrupt requests are enabled #1 TE Transmit Enable 5 5 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 RE Receive Enable 4 4 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 MPIE Multi-Processor Interrupt Enable (Valid in asynchronous mode when SMR.MP = 1) 3 3 read-write 0 Normal reception #0 1 When the data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF,ORER and FER in SSR to 1 is disabled. When the data with the multiprocessor bit set to 1 is received, the MPIE bit is automatically cleared to 0, and normal reception is resumed. #1 TEIE Transmit End Interrupt Enable 2 2 read-write 0 SCI_TEI interrupt request is disabled #0 1 SCI_TEI interrupt request is enabled #1 CKE Clock Enable 0 1 read-write 00 The SCKn pin is available for use as an I/O port in accord with the I/O port settings.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) #00 01 The clock with the same frequency as the bit rate is output from the SCKn pin.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) #01 others The clock with a frequency 16 times the bit rate should be input from the SCKn pin. (when SEMR.ABCS bit is 0) Input a clock signal with a frequency 8 times the bit rate when the SEMR.ABCS bit is 1.(Asynchronous mode) / The SCKn pin functions as the clock input pin(Clock synchronous mode) true SCR_SMCI Serial Control Register (SCMR.SMIF =1) SCR 0x02 8 read-write 0x00 0xFF TIE Transmit Interrupt Enable 7 7 read-write 0 A SCI_TXI interrupt request is disabled #0 1 A SCI_TXI interrupt request is enabled #1 RIE Receive Interrupt Enable 6 6 read-write 0 SCI_RXI and SCI_ERI interrupt requests are disabled #0 1 SCI_RXI and SCI_ERI interrupt requests are enabled #1 TE Transmit Enable 5 5 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 RE Receive Enable 4 4 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 MPIE Multi-Processor Interrupt Enable 3 3 read-write TEIE Transmit End Interrupt Enable 2 2 read-write CKE Clock Enable 0 1 read-write 00 Output disabled(SMR_SMCI.GM=0) / Output fixed low(SMR_SMCI.GM=1) #00 01 Clock Output #01 10 Setting prohibited(SMR_SMCI.GM=0) / Output fixed High(SMR_SMCI.GM=1) #10 11 Setting prohibited(SMR_SMCI.GM=0) / Clock Output(SMR_SMCI.GM=1) #11 TDR Transmit Data Register 0x03 8 read-write 0xFF 0xFF TDR TDR is an 8-bit register that stores transmit data. 0 7 read-write SSR Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) 0x04 8 read-write 0x84 0xFF TDRE Transmit Data Empty Flag 7 7 read-write zeroToClear modify 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 RDRF Receive Data Full Flag 6 6 read-write zeroToClear modify 0 No received data is in RDR register #0 1 Received data is in RDR register #1 ORER Overrun Error Flag 5 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 FER Framing Error Flag 4 4 read-write zeroToClear modify 0 No framing error occurred #0 1 A framing error has occurred #1 PER Parity Error Flag 3 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 TEND Transmit End Flag 2 2 read-only 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 MPB Multi-Processor 1 1 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 MPBT Multi-Processor Bit Transfer 0 0 read-write 0 Data transmission cycles #0 1 ID transmission cycles #1 SSR_SMCI Serial Status Register(SCMR.SMIF = 1) SSR 0x04 8 read-write 0x84 0xFF TDRE Transmit Data Empty Flag 7 7 read-write zeroToClear modify 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 RDRF Receive Data Full Flag 6 6 read-write zeroToClear modify 0 No received data is in RDR register #0 1 Received data is in RDR register #1 ORER Overrun Error Flag 5 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 ERS Error Signal Status Flag 4 4 read-write zeroToClear modify 0 Low error signal not responded #0 1 Low error signal responded #1 PER Parity Error Flag 3 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 TEND Transmit End Flag 2 2 read-only 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 MPB Multi-Processor This bit should be 0 in smart card interface mode. 1 1 read-only MPBT Multi-Processor Bit Transfer This bit should be 0 in smart card interface mode. 0 0 read-write RDR Receive Data Register 0x05 8 read-only 0x00 0xFF RDR RDR is an 8-bit register that stores receive data. 0 7 read-only SCMR Smart Card Mode Register 0x06 8 read-write 0xF2 0xFF BCP2 Base Clock Pulse 2 Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits 7 7 read-write 0 S=93(SMR.BCP[1:0]=00), 128(SMR.BCP[1:0]=01), 186(SMR.BCP[1:0]=10), 512(SMR.BCP[1:0]=11) #0 1 S=32(SMR.BCP[1:0]=00), 64(SMR.BCP[1:0]=01), 372(SMR.BCP[1:0]=10), 256(SMR.BCP[1:0]=11) #1 Reserved These bits are read as 11. The write value should be 11. 5 6 read-write CHR1 Character Length 1 (Only valid in asynchronous mode) 4 4 read-write 0 Transmit/receive in 9-bit data length #0 1 Transmit/receive in 8-bit data length(SMR.CHR=0) / in 7bit data length(SMR.CHR=1) #1 SDIR Transmitted/Received Data Transfer Direction NOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode. Set this bit to 1 if operation is to be in simple I2C mode. 3 3 read-write 0 Transfer with LSB first #0 1 Transfer with MSB first #1 SINV Transmitted/Received Data Invert Set this bit to 0 if operation is to be in simple I2C mode. 2 2 read-write 0 TDR contents are transmitted as they are. Receive data is stored as it is in RDR. #0 1 TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. #1 Reserved This bit is read as 1. The write value should be 1. 1 1 read-write SMIF Smart Card Interface Mode Select 0 0 read-write 0 Non-smart card interface mode(Asynchronous mode, clock synchronous mode, simple SPI mode, or simple I2C mode) #0 1 Smart card interface mode #1 SEMR Serial Extended Mode Register 0x07 8 read-write 0x00 0xFF RXDESEL Asynchronous Start Bit Edge Detection Select (Valid only in asynchronous mode) 7 7 read-write 0 The low level on the RXDn pin is detected as the start bit. #0 1 A falling edge on the RXDn pin is detected as the start bit. #1 BGDM Baud Rate Generator Double-Speed Mode Select (Only valid the CKE[1] bit in SCR is 0 in asynchronous mode). 6 6 read-write 0 Baud rate generator outputs the clock with normal frequency. #0 1 Baud rate generator outputs the clock with doubled frequency. #1 NFEN Digital Noise Filter Function Enable (The NFEN bit should be 0 without simple I2C mode and asynchronous mode.) In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input. 5 5 read-write 0 Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is disabled. #0 1 Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is enabled. #1 ABCS Asynchronous Mode Base Clock Select (Valid only in asynchronous mode) 4 4 read-write 0 Selects 16 base clock cycles for 1-bit period. #0 1 Selects 8 base clock cycles for 1-bit period. #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 (Valid only in asynchronous mode and SCR.CKE[1]=0) 3 3 read-write 0 Clock cycles for 1-bit period is decided with combination between BGDM and ABCS in SEMR. #0 1 Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator. #1 BRME Bit Rate Modulation Enable 2 2 read-write 0 Bit rate modulation function is disabled. #0 1 Bit rate modulation function is enabled. #1 Reserved These bits are read as 00. The write value should be 00. 0 1 read-write SNFR Noise Filter Setting Register 0x08 8 read-write 0x00 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write NFCS Noise Filter Clock Select 0 2 read-write 000 The clock signal divided by 1 is used with the noise filter.(In asynchronous mode) #000 001 The clock signal divided by 1 is used with the noise filter.(In simple I2C mode) #001 010 The clock signal divided by 2 is used with the noise filter.(In simple I2C mode) #010 011 The clock signal divided by 4 is used with the noise filter.(In simple I2C mode) #011 100 The clock signal divided by 8 is used with the noise filter.(In simple I2C mode) #100 others Settings prohibited. true SIMR1 I2C Mode Register 1 0x09 8 read-write 0x00 0xFF IICDL SDA Delay Output Select Cycles below are of the clock signal from the on-chip baud rate generator. 3 7 read-write 00000 No output delay #00000 others (IICDL - 1 ) to IIDCDL cycles. The delay is in the clock cycles from the on-chip baud rate generator. true Reserved These bits are read as 00. The write value should be 00. 1 2 read-write IICM Simple I2C Mode Select 0 0 read-write 0 Asynchronous mode, Multi-processor mode, Clock synchronous mode(SCMR.SMIF=0) /Smart card interface mode(SCMR.SMIF=1) #0 1 Simple I2C mode(SCMR.SMIF=0) / Setting prohibited.(SCMR.SMIF=1) #1 SIMR2 I2C Mode Register 2 0x0A 8 read-write 0x00 0xFF Reserved These bits are read as 00. The write value should be 00. 6 7 read-write IICACKT ACK Transmission Data 5 5 read-write 0 ACK transmission #0 1 NACK transmission and reception of ACK/NACK #1 Reserved These bits are read as 000. The write value should be 000. 2 4 read-write IICCSC Clock Synchronization 1 1 read-write 0 No synchronization with the clock signal #0 1 Synchronization with the clock signal #1 IICINTM I2C Interrupt Mode Select 0 0 read-write 0 Use ACK/NACK interrupts. #0 1 Use reception and transmission interrupts #1 SIMR3 I2C Mode Register 3 0x0B 8 read-write 0x00 0xFF IICSCLS SCL Output Select 6 7 read-write 00 Serial clock output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SSCLn pin. #10 11 Place the SSCLn pin in the high-impedance state. #11 IICSDAS SDA Output Select 4 5 read-write 00 Serial data output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SSDAn pin. #10 11 Place the SSDAn pin in the high-impedance state. #11 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag (When 0 is written to IICSTIF, it is cleared to 0.) 3 3 read-write zeroToClear modify 0 There are no requests for generating conditions or a condition is being generated. #0 1 A start, restart, or stop condition is completely generated. #1 IICSTPREQ Stop Condition Generation 2 2 read-write 0 A stop condition is not generated. #0 1 A stop condition is generated. #1 IICRSTAREQ Restart Condition Generation 1 1 read-write 0 A restart condition is not generated. #0 1 A restart condition is generated. #1 IICSTAREQ Start Condition Generation 0 0 read-write 0 A start condition is not generated. #0 1 A start condition is generated. #1 SISR I2C Status Register 0x0C 8 read-only 0x00 0xCB Reserved These bits are read as 00. 6 7 read-only Reserved This bit is read as 0. 5 5 read-only Reserved This bit is read as 0. 4 4 read-only Reserved This bit is read as 0. 3 3 read-only Reserved This bit is read as 0. 2 2 read-only Reserved This bit is read as 0. 1 1 read-only IICACKR ACK Reception Data Flag 0 0 read-only 0 ACK received #0 1 NACK received #1 SPMR SPI Mode Register 0x0D 8 read-write 0x00 0xFF CKPH Clock Phase Select 7 7 read-write 0 Clock is not delayed. #0 1 Clock is delayed. #1 CKPOL Clock Polarity Select 6 6 read-write 0 Clock polarity is not inverted. #0 1 Clock polarity is inverted #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write MFF Mode Fault Flag 4 4 read-write zeroToClear modify 0 No mode fault error #0 1 Mode fault error #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write MSS Master Slave Select 2 2 read-write 0 Transmission is through the TXDn pin and reception is through the RXDn pin (master mode). #0 1 Reception is through the TXDn pin and transmission is through the RXDn pin (slave mode). #1 CTSE CTS Enable 1 1 read-write 0 CTS function is disabled (RTS output function is enabled). #0 1 CTS function is enabled. #1 SSE SSn Pin Function Enable 0 0 read-write 0 SSn pin function is disabled. #0 1 SSn pin function is enabled. #1 TDRHL Transmit 9-bit Data Register 0x0E 16 read-write 0xFFFF 0xFFFF TDRHL TDRHL is a 16-bit register that stores transmit data. 0 15 write-only RDRHL Receive 9-bit Data Register 0x10 16 read-only 0x0000 0xFFFF RDRHL RDRHL is an 16-bit register that stores receive data. 0 15 read-only MDDR Modulation Duty Register 0x12 8 read-write 0xFF 0xFF MDDR MDDR corrects the bit rate adjusted by the BRR register. 0 7 read-write DCCR Data Compare Match Control Register 0x13 8 read-write 0x40 0xFF DCME Data Compare Match Enable (Valid only in asynchronous mode(including multi-processor) 7 7 read-write 0 Address match function is disabled. #0 1 Address match function is enabled #1 IDSEL ID frame select (Valid only in asynchronous mode(including multi-processor) 6 6 read-write 0 Always compare data regardless of the value of the MPB bit. #0 1 Compare data when the MPB bit is 1 (ID frame) only. #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write DFER Data Compare Match Framing Error Flag 4 4 read-write zeroToClear modify 0 No framing error occurred #0 1 A framing error has occurred #1 DPER Data Compare Match Parity Error Flag 3 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 Reserved These bits are read as 00. The write value should be 00. 1 2 read-write DCMF Data Compare Match Flag 0 0 read-write zeroToClear modify 0 No matched #0 1 Matched #1 CDR Compare Match Data Register 0x1A 16 read-write 0x0000 0xFFFF Reserved These bits are read as 0000000. The write value should be 0000000. 9 15 read-write CMPD Compare Match Data Compare data pattern for address match wake-up function 0 8 read-write SPTR Serial Port Register 0x1C 8 read-write 0x03 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write SPB2IO Serial port break I/O bit (It's selected whether the value of SPB2DT is output to TxD terminal.) 2 2 read-write 0 The value of SPB2DT bit is not output in TXD pin. #0 1 The value of SPB2DT bit is output in TXD pin. #1 SPB2DT Serial port break data select bit (The output level of TxD terminal is selected when SCR.TE = 0.) 1 1 read-write 0 Low level is output on TXD pin #0 1 High level is output on TXD pin #1 RXDMON Serial input data monitor bit (The state of the RXD terminal is shown.) 0 0 read-only 0 RXD pin is low. #0 1 RXD pin is high. #1 SCI9 Serial Communication Interface 9 0x40070120 SLCDC Segment LCD Controller/Driver 0x40082000 0x00 4 registers 0x100 38 registers LCDM0 LCD Mode Register 0 0x000 8 read-write 0x00 0xFF MDSET LCD drive voltage generator selection 6 7 read-write 00 External resistance division method #00 01 Internal voltage boosting method #01 10 Capacitor split method #10 11 Setting prohibited #11 LWAVE LCD display waveform selection 5 5 read-write 0 Waveform A #0 1 Waveform B #1 LDTY Time Slice of LCD Display Select 2 4 read-write 000 Static #000 001 2-time slice #001 010 3-time slice #010 011 4-time slice #011 101 8-time slice #101 others Setting prohibited true LBAS LCD Display Bias Method Select 0 1 read-write 00 1/2 bias method #00 01 1/3 bias method #01 10 1/4 bias method #10 11 Setting prohibited #11 LCDM1 LCD Mode Register 1 0x001 8 read-write 0x00 0xFF LCDON LCD Display Enable/Disable 7 7 read-write 0 Output ground level to segment/common pin(SCOC=0)/Display off (all segment outputs are deselected)(SCOC=1) #0 1 Output ground level to segment/common pin(SCOC=0)/Display on(SCOC=1) #1 SCOC LCD Display Enable/Disable 6 6 read-write 0 Output ground level to segment/common pin(LCDON=0)/Output ground level to segment/common pin(LCDON=1) #0 1 Display off (all segment outputs are deselected)(LCDON=0)/Display on(LCDON=1) #1 VLCON Voltage boost circuit or capacitor split circuit operation enable/disable 5 5 read-write 0 Stops voltage boost circuit or capacitor split circuit operation #0 1 Enables voltage boost circuit or capacitor split circuit operation #1 BLON Display data area control 4 4 read-write 0 Displaying an A-pattern area data (lower four bits of LCD display data register)(LCDSEL=0)/Displaying a B-pattern area data (higher four bits of LCD display data register)(LCDSEL=1) #0 1 Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC)) #1 LCDSEL Display data area control 3 3 read-write 0 Displaying an A-pattern area data (lower four bits of LCD display data register)(BLON=0)/Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC))(BLON=1) #0 1 Displaying a B-pattern area data (higher four bits of LCD display data register)(BLON=0)/Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC))(BLON=1) #1 Reserved These bits are read as 00. The write value should be 00. 1 2 read-write LCDVLM Voltage Boosting Pin Initial Value Switching Control 0 0 read-write 0 Set when VDD >= 2.7 V #0 1 Set when VDD <= 4.2 V #1 LCDC0 LCD Clock Control Register 0 0x002 8 read-write 0x00 0xFF LCDC LCD clock (LCDCL) 0 5 read-write 000001 (Sub clock)/22 or (LOCO clock)/22 #000001 000010 (Sub clock)/23 or (LOCO clock)/23 #000010 000011 (Sub clock)/24 or (LOCO clock)/24 #000011 000100 (Sub clock)/25 or (LOCO clock)/25 #000100 000101 (Sub clock)/26 or (LOCO clock)/26 #000101 000110 (Sub clock)/27 or (LOCO clock)/27 #000110 000111 (Sub clock)/28 or (LOCO clock)/28 #000111 001000 (Sub clock)/29 or (LOCO clock)/29 #001000 001001 (Sub clock)/210 or (LOCO clock)/210 #001001 010001 (Main clock)/28 or (HOCO clock)/28 #010001 010010 (Main clock)/29 or (HOCO clock)/29 #010010 010011 (Main clock)/210 or (HOCO clock)/210 #010011 010100 (Main clock)/211 or (HOCO clock)/211 #010100 010101 (Main clock)/212 or (HOCO clock)/212 #010101 010110 (Main clock)/213 or (HOCO clock)/213 #010110 010111 (Main clock)/214 or (HOCO clock)/214 #010111 011000 (Main clock)/215 or (HOCO clock)/215 #011000 011001 (Main clock)/216 or (HOCO clock)/216 #011001 011010 (Main clock)/217 or (HOCO clock)/217 #011010 011011 (Main clock)/218 or (HOCO clock)/218 #011011 101011 (Main clock)/219 or (HOCO clock)/219 #101011 others Other than above Setting prohibited true VLCD LCD Boost Level Control Register 0x003 8 read-write 0x04 0xFF VLCD Reference Voltage(Contrast Adjustment) Select 0 4 read-write 00100 Reference voltageselection(contrast adjustment): 1.00 V (default) VL4 voltage: 3.00 V(1/3 bias method)/4.00 V(1/4 bias method) #00100 00101 Reference voltageselection(contrast adjustment): 1.05 V VL4 voltage: 3.15 V(1/3 bias method)/4.20 V(1/4 bias method) #00101 00110 Reference voltageselection(contrast adjustment): 1.10 V VL4 voltage: 3.30 V(1/3 bias method)/4.40 V(1/4 bias method) #00110 00111 Reference voltageselection(contrast adjustment): 1.15 V VL4 voltage: 3.45 V(1/3 bias method)/4.60 V(1/4 bias method) #00111 01000 Reference voltageselection(contrast adjustment): 1.20 V VL4 voltage: 3.60 V(1/3 bias method)/4.80 V(1/4 bias method) #01000 01001 Reference voltageselection(contrast adjustment): 1.25 V VL4 voltage: 3.75 V(1/3 bias method)/5.00 V(1/4 bias method) #01001 01010 Reference voltageselection(contrast adjustment): 1.30 V VL4 voltage: 3.90 V(1/3 bias method)/5.20 V(1/4 bias method) #01010 01011 Reference voltageselection(contrast adjustment): 1.35 V VL4 voltage: 4.05 V(1/3 bias method)/Setting prohibited(1/4 bias method) #01011 01100 Reference voltageselection(contrast adjustment): 1.40 V VL4 voltage: 4.20 V(1/3 bias method)/Setting prohibited(1/4 bias method) #01100 01101 Reference voltageselection(contrast adjustment): 1.45 V VL4 voltage: 4.35 V(1/3 bias method)/Setting prohibited(1/4 bias method) #01101 01110 Reference voltageselection(contrast adjustment): 1.50 V VL4 voltage: 4.50 V(1/3 bias method)/Setting prohibited(1/4 bias method) #01110 01111 Reference voltageselection(contrast adjustment): 1.55 V VL4 voltage: 4.65 V(1/3 bias method)/Setting prohibited(1/4 bias method) #01111 10000 Reference voltageselection(contrast adjustment): 1.60 V VL4 voltage: 4.80 V(1/3 bias method)/Setting prohibited(1/4 bias method) #10000 10001 Reference voltageselection(contrast adjustment): 1.65 V VL4 voltage: 4.95 V(1/3 bias method)/Setting prohibited(1/4 bias method) #10001 10010 Reference voltageselection(contrast adjustment): 1.70 V VL4 voltage: 5.10 V(1/3 bias method)/Setting prohibited(1/4 bias method) #10010 10011 Reference voltageselection(contrast adjustment): 1.75 V VL4 voltage: 5.25 V(1/3 bias method)/Setting prohibited(1/4 bias method) #10011 others Setting prohibited true 38 0x1 0-37 SEG%s LCD Display Data Register %s 0x100 8 read-write 0x00 0xFF SEG LCD Display Data 0 7 read-write SPI0 Serial Peripheral Interface 0 0x40072000 0x00 8 registers 0x04 2 registers 0x08 10 registers SPCR SPI Control Register 0x00 8 read-write 0x00 0xFF SPRIE SPI Receive Buffer Full Interrupt Enable 7 7 read-write 0 Disables the generation of SPI receive buffer full interrupt requests #0 1 Enables the generation of SPI receive buffer full interrupt requests #1 SPE SPI Function Enable 6 6 read-write 0 Disables the SPI function #0 1 Enables the SPI function #1 SPTIE Transmit Buffer Empty Interrupt Enable 5 5 read-write 0 Disables the generation of transmit buffer empty interrupt requests #0 1 Enables the generation of transmit buffer empty interrupt requests #1 SPEIE SPI Error Interrupt Enable 4 4 read-write 0 Disables the generation of SPI error interrupt requests #0 1 Enables the generation of SPI error interrupt requests #1 MSTR SPI Master/Slave Mode Select 3 3 read-write 0 Slave mode #0 1 Master mode #1 MODFEN Mode Fault Error Detection Enable 2 2 read-write 0 Disables the detection of mode fault error #0 1 Enables the detection of mode fault error #1 TXMD Communications Operating Mode Select 1 1 read-write 0 Full-duplex synchronous serial communications #0 1 Serial communications consisting of only transmit operations #1 SPMS SPI Mode Select 0 0 read-write 0 SPI operation (4-wire method) #0 1 Clock synchronous operation (3-wire method) #1 SSLP SPI Slave Select Polarity Register 0x01 8 read-write 0x00 0xFF Reserved These bits are read as 0000. The write value should be 0000. 4 7 read-write SSL3P SSL3 Signal Polarity Setting 3 3 read-write 0 SSL3 signal is active low #0 1 SSL3 signal is active high #1 SSL2P SSL2 Signal Polarity Setting 2 2 read-write 0 SSL2 signal is active low #0 1 SSL2 signal is active high #1 SSL1P SSL1 Signal Polarity Setting 1 1 read-write 0 SSL1 signal is active low #0 1 SSL1 signal is active high #1 SSL0P SSL0 Signal Polarity Setting 0 0 read-write 0 SSL0 signal is active low #0 1 SSL0 signal is active high #1 SPPCR SPI Pin Control Register 0x02 8 read-write 0x00 0xFF Reserved These bits are read as 00. The write value should be 00. 6 7 read-write MOIFE MOSI Idle Value Fixing Enable 5 5 read-write 0 MOSI output value equals final data from previous transfer #0 1 MOSI output value equals the value set in the MOIFV bit #1 MOIFV MOSI Idle Fixed Value 4 4 read-write 0 The level output on the MOSIn pin during MOSI idling corresponds to low. #0 1 The level output on the MOSIn pin during MOSI idling corresponds to high. #1 Reserved These bits are read as 00. The write value should be 00. 2 3 read-write SPLP2 RSPI Loopback 2 1 1 read-write 0 Normal mode #0 1 Loopback mode (data is not inverted for transmission) #1 SPLP RSPI Loopback 0 0 read-write 0 Normal mode #0 1 Loopback mode (data is inverted for transmission) #1 SPSR SPI Status Register 0x03 8 read-write 0x20 0xFF SPRF SPI Receive Buffer Full Flag 7 7 read-write zeroToClear modify 0 No valid data in SPDR #0 1 Valid data found in SPDR #1 Reserved This bit is read as 0. The write value should be 0. 6 6 read-write SPTEF SPI Transmit Buffer Empty Flag 5 5 read-write zeroToClear modify 0 Data found in the transmit buffer #0 1 No data in the transmit buffer #1 UDRF Underrun Error Flag (When MODF is 0, This bit is invalid.) 4 4 read-write zeroToClear modify 0 A mode fault error occurs (MODF=1) #0 1 An underrun error occurs (MODF=1) #1 PERF Parity Error Flag 3 3 read-write zeroToClear modify 0 No parity error occurs #0 1 A parity error occurs #1 MODF Mode Fault Error Flag 2 2 read-write zeroToClear modify 0 Neither mode fault error nor underrun error occurs #0 1 A mode fault error or an underrun error occurs. #1 IDLNF SPI Idle Flag 1 1 read-only 0 SPI is in the idle state #0 1 SPI is in the transfer state #1 OVRF Overrun Error Flag 0 0 read-write zeroToClear modify 0 No overrun error occurs #0 1 An overrun error occurs #1 SPDR SPI Data Register 0x04 32 read-write 0x00000000 0xFFFFFFFF SPDR SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI. When accessing in word (SPDCR.SPLW=1), access SPDR. 0 31 read-write SPDR_HA SPI Data Register ( halfword access ) SPDR 0x04 16 read-write 0x0000 0xFFFF SPDR_HA SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI. When accessing in halfword (SPDCR.SPLW=0), access SPDR_HA. 0 15 read-write SPBR SPI Bit Rate Register 0x0A 8 read-write 0xFF 0xFF SPR SPBR sets the bit rate in master mode. 0 7 read-write SPDCR SPI Data Control Register 0x0B 8 read-write 0x00 0xFF Reserved These bits are read as 00. The write value should be 00. 6 7 read-write SPLW SPI Word Access/Halfword Access Specification 5 5 read-write 0 SPDR_HA is valid to access in halfwords #0 1 SPDR is valid (to access in words). #1 SPRDTD RSPI Receive/Transmit Data Selection 4 4 read-write 0 SPDR values are read from the receive buffer #0 1 SPDR values are read from the transmit buffer (but only if the transmit buffer is empty) #1 Reserved These bits are read as 00. The write value should be 00. 2 3 read-write Reserved These bits are read as 00. The write value should be 00. 0 1 read-write SPCKD SPI Clock Delay Register 0x0C 8 read-write 0x00 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write SCKDL RSPCK Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SSLND SPI Slave Select Negation Delay Register 0x0D 8 read-write 0x00 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write SLNDL SSL Negation Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SPND SPI Next-Access Delay Register 0x0E 8 read-write 0x00 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write SPNDL SPI Next-Access Delay Setting 0 2 read-write 000 1 RSPCK + 2 PCLK #000 001 2 RSPCK + 2 PCLK #001 010 3 RSPCK + 2 PCLK #010 011 4 RSPCK + 2 PCLK #011 100 5 RSPCK + 2 PCLK #100 101 6 RSPCK + 2 PCLK #101 110 7 RSPCK + 2 PCLK #110 111 8 RSPCK + 2 PCLK #111 SPCR2 SPI Control Register 2 0x0F 8 read-write 0x00 0xFF Reserved These bits are read as 000. The write value should be 000. 5 7 read-write SCKASE RSPCK Auto-Stop Function Enable 4 4 read-write 0 Disables the RSPCK auto-stop function #0 1 Enables the RSPCK auto-stop function #1 PTE Parity Self-Testing 3 3 read-write 0 Disables the self-diagnosis function of the parity circuit #0 1 Enables the self-diagnosis function of the parity circuit #1 SPIIE SPI Idle Interrupt Enable 2 2 read-write 0 Disables the generation of idle interrupt requests #0 1 Enables the generation of idle interrupt requests #1 SPOE Parity Mode 1 1 read-write 0 Selects even parity for use in transmission and reception #0 1 Selects odd parity for use in transmission and reception #1 SPPE Parity Enable 0 0 read-write 0 Does not add the parity bit to transmit data and does not check the parity bit of receive data #0 1 Adds the parity bit to transmit data and checks the parity bit of receive data (when SPCR.TXMD = 0) / Adds the parity bit to transmit data but does not check the parity bit of receive data (when SPCR.TXMD = 1) #1 SPCMD0 SPI Command Register 0 0x10 16 read-write 0x070D 0xFFFF SCKDEN RSPCK Delay Setting Enable 15 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPNDEN RSPI Next-Access Delay Enable 13 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 LSBF RSPI LSB First 12 12 read-write 0 MSB first #0 1 LSB first #1 SPB RSPI Data Length Setting 8 11 read-write 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 others 8bits true Reserved This bit is read as 0. The write value should be 0. 7 7 read-write SSLA SSL Signal Assertion Setting 4 6 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 others Setting prohibited true BRDV Bit Rate Division Setting 2 3 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPOL RSPCK Polarity Setting 1 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 CPHA RSPCK Phase Setting 0 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 SPI1 Serial Peripheral Interface 1 0x40072100 0x00 8 registers 0x04 2 registers 0x08 10 registers SPCR SPI Control Register 0x00 8 read-write 0x00 0xFF SPRIE SPI Receive Buffer Full Interrupt Enable 7 7 read-write 0 Disables the generation of SPI receive buffer full interrupt requests #0 1 Enables the generation of SPI receive buffer full interrupt requests #1 SPE SPI Function Enable 6 6 read-write 0 Disables the SPI function #0 1 Enables the SPI function #1 SPTIE Transmit Buffer Empty Interrupt Enable 5 5 read-write 0 Disables the generation of transmit buffer empty interrupt requests #0 1 Enables the generation of transmit buffer empty interrupt requests #1 SPEIE SPI Error Interrupt Enable 4 4 read-write 0 Disables the generation of SPI error interrupt requests #0 1 Enables the generation of SPI error interrupt requests #1 MSTR SPI Master/Slave Mode Select 3 3 read-write 0 Slave mode #0 1 Master mode #1 MODFEN Mode Fault Error Detection Enable 2 2 read-write 0 Disables the detection of mode fault error #0 1 Enables the detection of mode fault error #1 TXMD Communications Operating Mode Select 1 1 read-write 0 Full-duplex synchronous serial communications #0 1 Serial communications consisting of only transmit operations #1 SPMS SPI Mode Select 0 0 read-write 0 SPI operation (4-wire method) #0 1 Clock synchronous operation (3-wire method) #1 SSLP SPI Slave Select Polarity Register 0x01 8 read-write 0x00 0xFF Reserved These bits are read as 0000. The write value should be 0000. 4 7 read-write SSL3P SSL3 Signal Polarity Setting 3 3 read-write 0 SSL3 signal is active low #0 1 SSL3 signal is active high #1 SSL2P SSL2 Signal Polarity Setting 2 2 read-write 0 SSL2 signal is active low #0 1 SSL2 signal is active high #1 SSL1P SSL1 Signal Polarity Setting 1 1 read-write 0 SSL1 signal is active low #0 1 SSL1 signal is active high #1 SSL0P SSL0 Signal Polarity Setting 0 0 read-write 0 SSL0 signal is active low #0 1 SSL0 signal is active high #1 SPPCR SPI Pin Control Register 0x02 8 read-write 0x00 0xFF Reserved These bits are read as 00. The write value should be 00. 6 7 read-write MOIFE MOSI Idle Value Fixing Enable 5 5 read-write 0 MOSI output value equals final data from previous transfer #0 1 MOSI output value equals the value set in the MOIFV bit #1 MOIFV MOSI Idle Fixed Value 4 4 read-write 0 The level output on the MOSIn pin during MOSI idling corresponds to low. #0 1 The level output on the MOSIn pin during MOSI idling corresponds to high. #1 Reserved These bits are read as 00. The write value should be 00. 2 3 read-write SPLP2 RSPI Loopback 2 1 1 read-write 0 Normal mode #0 1 Loopback mode (data is not inverted for transmission) #1 SPLP RSPI Loopback 0 0 read-write 0 Normal mode #0 1 Loopback mode (data is inverted for transmission) #1 SPSR SPI Status Register 0x03 8 read-write 0x20 0xFF SPRF SPI Receive Buffer Full Flag 7 7 read-write zeroToClear modify 0 No valid data in SPDR #0 1 Valid data found in SPDR #1 Reserved This bit is read as 0. The write value should be 0. 6 6 read-write SPTEF SPI Transmit Buffer Empty Flag 5 5 read-write zeroToClear modify 0 Data found in the transmit buffer #0 1 No data in the transmit buffer #1 UDRF Underrun Error Flag (When MODF is 0, This bit is invalid.) 4 4 read-write zeroToClear modify 0 A mode fault error occurs (MODF=1) #0 1 An underrun error occurs (MODF=1) #1 PERF Parity Error Flag 3 3 read-write zeroToClear modify 0 No parity error occurs #0 1 A parity error occurs #1 MODF Mode Fault Error Flag 2 2 read-write zeroToClear modify 0 Neither mode fault error nor underrun error occurs #0 1 A mode fault error or an underrun error occurs. #1 IDLNF SPI Idle Flag 1 1 read-only 0 SPI is in the idle state #0 1 SPI is in the transfer state #1 OVRF Overrun Error Flag 0 0 read-write zeroToClear modify 0 No overrun error occurs #0 1 An overrun error occurs #1 SPDR SPI Data Register 0x04 32 read-write 0x00000000 0xFFFFFFFF SPDR SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI. When accessing in word (SPDCR.SPLW=1), access SPDR. 0 31 read-write SPDR_HA SPI Data Register ( halfword access ) SPDR 0x04 16 read-write 0x0000 0xFFFF SPDR_HA SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI. When accessing in halfword (SPDCR.SPLW=0), access SPDR_HA. 0 15 read-write SPBR SPI Bit Rate Register 0x0A 8 read-write 0xFF 0xFF SPR SPBR sets the bit rate in master mode. 0 7 read-write SPDCR SPI Data Control Register 0x0B 8 read-write 0x00 0xFF Reserved These bits are read as 00. The write value should be 00. 6 7 read-write SPLW SPI Word Access/Halfword Access Specification 5 5 read-write 0 SPDR_HA is valid to access in halfwords #0 1 SPDR is valid (to access in words). #1 SPRDTD RSPI Receive/Transmit Data Selection 4 4 read-write 0 SPDR values are read from the receive buffer #0 1 SPDR values are read from the transmit buffer (but only if the transmit buffer is empty) #1 Reserved These bits are read as 0000. The write value should be 0000. 0 3 read-write SPCKD SPI Clock Delay Register 0x0C 8 read-write 0x00 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write SCKDL RSPCK Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SSLND SPI Slave Select Negation Delay Register 0x0D 8 read-write 0x00 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write SLNDL SSL Negation Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SPND SPI Next-Access Delay Register 0x0E 8 read-write 0x00 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write SPNDL SPI Next-Access Delay Setting 0 2 read-write 000 1 RSPCK + 2 PCLK #000 001 2 RSPCK + 2 PCLK #001 010 3 RSPCK + 2 PCLK #010 011 4 RSPCK + 2 PCLK #011 100 5 RSPCK + 2 PCLK #100 101 6 RSPCK + 2 PCLK #101 110 7 RSPCK + 2 PCLK #110 111 8 RSPCK + 2 PCLK #111 SPCR2 SPI Control Register 2 0x0F 8 read-write 0x00 0xFF Reserved These bits are read as 000. The write value should be 000. 5 7 read-write SCKASE RSPCK Auto-Stop Function Enable 4 4 read-write 0 Disables the RSPCK auto-stop function #0 1 Enables the RSPCK auto-stop function #1 PTE Parity Self-Testing 3 3 read-write 0 Disables the self-diagnosis function of the parity circuit #0 1 Enables the self-diagnosis function of the parity circuit #1 SPIIE SPI Idle Interrupt Enable 2 2 read-write 0 Disables the generation of idle interrupt requests #0 1 Enables the generation of idle interrupt requests #1 SPOE Parity Mode 1 1 read-write 0 Selects even parity for use in transmission and reception #0 1 Selects odd parity for use in transmission and reception #1 SPPE Parity Enable 0 0 read-write 0 Does not add the parity bit to transmit data and does not check the parity bit of receive data #0 1 Adds the parity bit to transmit data and checks the parity bit of receive data (when SPCR.TXMD = 0) / Adds the parity bit to transmit data but does not check the parity bit of receive data (when SPCR.TXMD = 1) #1 SPCMD0 SPI Command Register 0 0x10 16 read-write 0x070D 0xFFFF SCKDEN RSPCK Delay Setting Enable 15 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPNDEN RSPI Next-Access Delay Enable 13 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 LSBF RSPI LSB First 12 12 read-write 0 MSB first #0 1 LSB first #1 SPB RSPI Data Length Setting 8 11 read-write 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 others 8bits true Reserved This bit is read as 0. The write value should be 0. 7 7 read-write SSLA SSL Signal Assertion Setting 4 6 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 others Setting prohibited true BRDV Bit Rate Division Setting 2 3 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPOL RSPCK Polarity Setting 1 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 CPHA RSPCK Phase Setting 0 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 SSIE0 Serial Sound Interface Ver.2.0 0x4004E000 0x00 8 registers 0x10 24 registers SSICR Control Register 0x00 32 read-write 0x00000000 0xFFFFFFFF Reserved This bit is read as 0. The write value should be 0. 31 31 read-write CKS Selects an Audio Clock for Master-mode Communication 30 30 read-write 0 Selects the AUDIO_CLK input #0 1 Selects the GTIOC1A (GPT output). #1 TUIEN Transmit Underflow Interrupt Output Enable 29 29 read-write 0 Disables transmit underflow interrupt output #0 1 Enables transmit underflow interrupt output. #1 TOIEN Transmit Overflow Interrupt Output Enable 28 28 read-write 0 Disables transmit overflow interrupt output #0 1 Enables transmit overflow interrupt output. #1 RUIEN Receive Underflow Interrupt Output Enable 27 27 read-write 0 Disables receive underflow interrupt output #0 1 Enables receive underflow interrupt output. #1 ROIEN Receive Overflow Interrupt Output Enable 26 26 read-write 0 Disables receive overflow interrupt output #0 1 Enables receive overflow interrupt output. #1 IIEN Idle Mode Interrupt Output Enable 25 25 read-write 0 Disables idle mode interrupt output #0 1 Enables idle mode interrupt output. #1 Reserved These bits are read as 000. The write value should be 000. 22 24 read-write DWL Selects Data Word Length 19 21 read-write 000 8 bits #000 001 16 bits #001 010 18 bits #010 011 20 bits #011 100 22 bits #100 101 24 bits #101 110 32 bits #110 others Settings other than above are prohibited. true SWL Selects System Word Length 16 18 read-write 000 8 bits #000 001 16 bits #001 010 24 bits #010 011 32 bits #011 100 48 bits #100 101 64 bits #101 110 128 bits #110 111 256 bits. #111 Reserved This bit is read as 0. The write value should be 0. 15 15 read-write MST Master Enable 14 14 read-write 0 Slave-mode communication #0 1 Master-mode communication. #1 BCKP Selects Bit Clock Polarity 13 13 read-write 0 SSILRCK/SSIFS and SSITXD0/SSIRXD0 change at a falling edge (SSILRCK/SSIFS and SSIRXD0 are sampled at a rising edge of SSIBCK) #0 1 SSILRCK/SSIFS and SSITXD0/SSIRXD0 change at a rising edge (SSILRCK/SSIFS and SSIRXD0 are sampled at a falling edge of SSIBCK). #1 LRCKP Selects the Initial Value and Polarity of LR Clock/Frame Synchronization Signal 12 12 read-write 0 The initial value is at a high level The start trigger for a frame is synchronized with a falling edge of SSILRCK/SSIFS #0 1 The initial value is at a low level The start trigger for a frame is synchronized with a rising edge of SSILRCK/SSIFS. #1 SPDP Selects Serial Padding Polarity 11 11 read-write 0 Padding data is at a low level #0 1 Padding data is at a high level. #1 SDTA Selects Serial Data Alignment 10 10 read-write 0 Transmits and receives serial data first and then padding bits #0 1 Transmit and receives padding bits first and then serial data. #1 PDTA Selects Placement Data Alignment 9 9 read-write 0 Left-justifies placement data (SSIFTDR, SSIFRDR) #0 1 Right-justifies placement data (SSIFTDR, SSIFRDR). #1 DEL Selects Serial Data Delay 8 8 read-write 0 Delay of one cycle of SSIBCK between SSILRCK/SSIFS and SSITXD0/SSIRXD0 #0 1 No delay between SSILRCK/SSIFS and SSITXD0/SSIRXD0 In the monaural format, this bit controls the waveform of SSILRCK/SSIFS. #1 CKDV Selects Bit Clock Division Ratio 4 7 read-write 0000 AUDIO_MCK #0000 0001 AUDIO_MCK/2 #0001 0010 AUDIO_MCK/4 #0010 0011 AUDIO_MCK/8 #0011 0100 AUDIO_MCK/16 #0100 0101 AUDIO_MCK/32 #0101 0110 AUDIO_MCK/64 #0110 0111 AUDIO_MCK/128 #0111 1000 AUDIO_MCK/6 #1000 1001 AUDIO_MCK/12 #1001 1010 AUDIO_MCK/24 #1010 1011 AUDIO_MCK/48 #1011 1100 AUDIO_MCK/96 #1100 others Setting prohibited true MUEN Mute Enable 3 3 read-write 0 Disables muting on the next frame boundary #0 1 Enables muting on the next frame boundary. #1 Reserved This bit is read as 0. The write value should be 0. 2 2 read-write TEN Transmit Enable 1 1 read-write 0 Disables the transmit operation. #0 1 Enables the transmit operation. #1 REN Receive Enable 0 0 read-write 0 Disables the receive operation. #0 1 Enables the receive operation. #1 SSISR Status Register 0x04 32 read-write 0x02000000 0xFFFFFFFF Reserved These bits are read as 00. The write value should be 00. 30 31 read-write TUIRQ Transmit Underflow Error Status flag 29 29 read-write 0 No transmit underflow error is generated #0 1 A transmit underflow error is generated. #1 TOIRQ Transmit Overflow Error Status Flag 28 28 read-write 0 No transmit overflow error is generated #0 1 A transmit overflow error is generated. #1 RUIRQ Receive Underflow Error Status Flag 27 27 read-write 0 No receive underflow error is generated #0 1 A receive underflow error is generated. #1 ROIRQ Receive Overflow Error Status Flag 26 26 read-write 0 No receive overflow error is generated #0 1 A receive overflow error is generated. #1 IIRQ Idle Mode Status Flag 25 25 read-only 0 In the communication state #0 1 In the idle state #1 Reserved These bits are read as 0000000000000000000000000. The write value should be 0000000000000000000000000. 0 24 read-write SSIFCR FIFO Control Register 0x10 32 read-write 0x00000000 0xFFFFFFFF AUCKE AUDIO_MCK Enable in Mastermode Communication 31 31 read-write 0 Disables supply of AUDIO_MCK #0 1 Enables supply of AUDIO_MCK. #1 Reserved These bits are read as 00000000000000. The write value should be 00000000000000. 17 30 read-write SSIRST Software Reset 16 16 read-write 0 Clears a software reset condition #0 1 Sets a software reset condition. #1 Reserved These bits are read as 0000. The write value should be 0000. 12 15 read-write BSW Byte Swap Enable 11 11 read-write 0 Disables byte swap #0 1 Enables byte swap #1 Reserved These bits are read as 0000000. The write value should be 0000000. 4 10 read-write TIE Transmit Data Empty Interrupt Output Enable 3 3 read-write 0 Disables transmit data empty interrupts #0 1 Enables transmit data empty interrupts. #1 RIE Receive Data Full Interrupt Output Enable 2 2 read-write 0 Disables receive data full interrupts #0 1 Enables receive data full interrupts. #1 TFRST Transmit FIFO Data Register Reset 1 1 read-write 0 Clears a transmit data FIFO reset condition #0 1 Sets a transmit data FIFO reset condition. #1 RFRST Receive FIFO Data Register Reset 0 0 read-write 0 Clears a receive data FIFO reset condition #0 1 Sets a receive data FIFO reset condition. #1 SSIFSR FIFO Status Register 0x14 32 read-write 0x00010000 0xFFFFFFFF Reserved These bits are read as 0000. The write value should be 0000. 28 31 read-write TDC Number of Transmit FIFO Data Indication Flag Number of transmit FIFO data indication flag. 24 27 read-only Reserved These bits are read as 0000000. The write value should be 0000000. 17 23 read-write TDE Transmit Data Empty Flag 16 16 read-write zeroToClear modify 0 The free space of SSIFTDR is not more than the value of SSISCR.TDES #0 1 The free space of SSIFTDR is not less than the value of SSISCR.TDES plus one. #1 RDC Number of Receive FIFO Data Indication Flag Number of receive FIFO data indication flag. 8 11 read-only Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write RDF Receive Data Full Flag 0 0 read-write zeroToClear modify 0 The size of received data in SSIFRDR is not more than the value of SSISCR.RDFS #0 1 The size of received data in SSIFRDR is not less than the value of SSISCR.RDFS plus one. #1 SSIFTDR Transmit FIFO Data Register 0x18 32 write-only 0x00000000 0x00000000 SSIFTDR Transmit FIFO Data 0 31 write-only SSIFRDR Receive FIFO Data Register 0x1C 32 read-only 0x00000000 0x00000000 SSIFRDR Receive FIFO data. 0 31 read-only SSITDMR TDM Mode Register 0x20 32 read-write 0x00000000 0xFFFFFFFF Reserved These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000. 10 31 read-write BCKASTP Whether to Enable Stopping BCK Output When SSIE is in Idle Status 9 9 read-write 0 Always outputs BCK to the SSIBCK pin #0 1 Automatically controls output of BCK to the SSIBCK pin. #1 LRCONT Whether to Enable LRCK/FS Continuation 8 8 read-write 0 Disables LRCK/FS continuation #0 1 Enables LRCK/FS continuation. #1 Reserved These bits are read as 000000. The write value should be 000000. 2 7 read-write OMOD Audio Format Select 0 1 read-write 00 I2S format #00 01 Setting prohibited #01 10 Monaural format #10 11 Setting prohibited. #11 SSISCR Status Control Register 0x24 32 read-write 0x00000000 0xFFFFFFFF Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 31 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 15 read-write TDES TDE Setting Condition Select 8 10 read-write 000 SSIFTDR has one stage or more free space #000 001 SSIFTDR has two stages or more free space (snip) #001 110 SSIFTDR has seven stages or more free space #110 111 SSIFTDR has eight stages or more free space. #111 Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write RDFS RDF Setting Condition Select 0 2 read-write 000 SSIFRDR has one stage or more data size #000 001 SSIFRDR has two stages or more data size (snip) #001 110 SSIFRDR has seven stages or more data size #110 111 SSIFRDR has eight stages or more data size. #111 TSN Temperature Sensor 0x407EC000 0x229 1 registers 0x228 1 registers TSCDRH Temperature Sensor Calibration Data Register H 0x229 8 read-only 0x00 0x00 TSCDRH The calibration data stores the higher 8 bits of the converted value. 0 7 read-only TSCDRL Temperature Sensor Calibration Data Register L 0x228 8 read-only 0x00 0x00 TSCDRL The calibration data stores the lower 8 bits of the converted value. 0 7 read-only USBFS USB 2.0 FS Module 0x40090000 0x00 2 registers 0x04 2 registers 0x08 2 registers 0x14 2 registers 0x14 2 registers 0x18 2 registers 0x18 2 registers 0x1C 2 registers 0x1C 2 registers 0x20 4 registers 0x28 12 registers 0x36 8 registers 0x40 4 registers 0x46 12 registers 0x54 14 registers 0x64 2 registers 0x68 2 registers 0x6C 22 registers 0x90 20 registers 0x92 20 registers 0xD0 12 registers 0xCC 2 registers 0xB0 2 registers SYSCFG System Configuration Control Register 0x000 16 read-write 0x0000 0xFFFF Reserved These bits are read as 00000. The write value should be 00000. 11 15 read-write SCKE USB Clock Enable 10 10 read-write 0 Clock supply to the USBFS stopped #0 1 Clock supply to the USBFS enabled. #1 Reserved This bit is read as 0. The write value should be 0. 9 9 read-write CNEN CNEN Single End Receiver Enable 8 8 read-write 0 Single end receiver disabled #0 1 Single end receiver enabled #1 Reserved This bit is read as 0. The write value should be 0. 7 7 read-write DCFM Controller Function Select 6 6 read-write 0 Device controller selected #0 1 Host controller selected. #1 DRPD D+/D- Line Resistor Control 5 5 read-write 0 Line pull-down disabled #0 1 Line pull-down enabled. #1 DPRPU D+ Line Resistor Control 4 4 read-write 0 Line pull-down disabled #0 1 Line pull-down enabled. #1 DMRPU D- Line Resistor Control 3 3 read-write 0 Line pull-up disabled #0 1 Line pull-up enabled. #1 USBE USB Operation Enable 0 0 read-write 0 Disabled #0 1 Enabled. #1 SYSSTS0 System Configuration Status Register 0 0x004 16 read-only 0x0000 0x0000 OVCMON External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor The OCVMON[1] bit indicates the status of the USBHS_OVRCURA pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB pin. 14 15 read-only Reserved These bits are read as 0000000. 7 13 read-only HTACT USB Host Sequencer Status Monitor 6 6 read-only 0 Host sequencer completely stopped #0 1 Host sequencer not completely stopped. #1 Reserved These bits are read as 000. 3 5 read-only IDMON External ID0 Input Pin Monitor 2 2 read-only 0 USB0_ID pin is low #0 1 USB0_ID pin is high #1 LNST USB Data Line Status Monitor 0 1 read-only 00 SE0 #00 01 K-State (FS) / J-State(LS) #01 10 J-State(FS) / K-State(LS) #10 11 SE1 #11 DVSTCTR0 Device State Control Register 0 0x008 16 read-write 0x0000 0xFFFF Reserved These bits are read as 0000. The write value should be 0000. 12 15 read-write HNPBTOA Host Negotiation Protocol (HNP) Control This bit is used when switching from device B to device A while in OTG mode. If the HNPBTOA bit is 1, the internal function control keeps the suspended state until the HNP processing ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. 11 11 read-write 0 Normal Operation #0 1 Switching from device B to device A is enabled #1 EXICEN USB_EXICEN Output Pin Control 10 10 read-write 0 External USB_EXICEN pin outputs low #0 1 External USB_EXICEN pin outputs high #1 VBUSEN USB_VBUSEN Output Pin Control 9 9 read-write 0 External USB_VBUSEN pin outputs low #0 1 External USB_VBUSEN pin outputs high #1 WKUP Wakeup Output 8 8 read-write 0 Remote wakeup signal is not output. #0 1 Remote wakeup signal is output. #1 RWUPE Wakeup Detection Enable 7 7 read-write 0 Downstream port wakeup is disabled. #0 1 Downstream port wakeup is enabled. #1 USBRST USB Bus Reset Output 6 6 read-write 0 USB bus reset signal is not output. #0 1 USB bus reset signal is output. #1 RESUME Resume Output 5 5 read-write 0 Resume signal is not output. #0 1 Resume signal is output. #1 UACT USB Bus Enable 4 4 read-write 0 Downstream port is disabled (SOF transmission is disabled). #0 1 Downstream port is enabled (SOF transmission is enabled). #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write RHST USB Bus Reset Status 0 2 read-only 000 Communication speed not determined #000 001 Low-speed connection(When the host controller is selected) /USB bus reset in progress( When the function controller is selected) #001 010 Full-speed connection(When the host controller is selected) /USB bus reset in progress or full-speed connection(When the function controller is selected) #010 011 Setting prohibited #011 others USB bus reset in progress(When the host controller function is selected) true CFIFO CFIFO Port Register 0x014 16 read-write 0x0000 0xFFFF FIFOPORT FIFO Port Read receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits. 0 15 read-write CFIFOL CFIFO Port Register L CFIFO 0x014 8 read-write 0x00 0xFF D0FIFO D0FIFO Port Register 0x018 16 read-write 0x0000 0xFFFF FIFOPORT FIFO Port Read receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits. 0 15 read-write D0FIFOL D0FIFO Port Register L D0FIFO 0x018 8 read-write 0x00 0xFF D1FIFO D1FIFO Port Register 0x01C 16 read-write 0x0000 0xFFFF FIFOPORT FIFO Port Read receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits. 0 15 read-write D1FIFOL D1FIFO Port Register L D1FIFO 0x01C 8 read-write 0x00 0xFF CFIFOSEL CFIFO Port Select Register 0x020 16 read-write 0x0000 0xFFFF RCNT Read Count Mode 15 15 read-write 0 The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the CFIFO.(In double buffer mode, the DTLN[8:0] bit value is cleared when all the data has been read from only a single plane.) #0 1 The DTLN[8:0] bits are decremented each time the receive data is read from the CFIFO. #1 REW Buffer Pointer Rewind 14 14 write-only 0 The buffer pointer is not rewound. #0 1 The buffer pointer is rewound. #1 Reserved These bits are read as 000. The write value should be 000. 11 13 read-write MBW CFIFO Port Access Bit Width 10 10 read-write 0 8-bit width #0 1 16-bit width #1 Reserved This bit is read as 0. The write value should be 0. 9 9 read-write BIGEND CFIFO Port Endian Control 8 8 read-write 0 Little endian #0 1 Big endian #1 Reserved These bits are read as 00. The write value should be 00. 6 7 read-write ISEL CFIFO Port Access Direction When DCP is Selected 5 5 read-write 0 Reading from the buffer memory is selected #0 1 Writing to the buffer memory is selected #1 Reserved This bit is read as 0. The write value should be 0. 4 4 read-write CURPIPE CFIFO Port Access Pipe Specification 0 3 read-write 0000 DCP (Default control pipe) #0000 0001 Pipe 1 #0001 0010 Pipe 2 #0010 0011 Pipe 3 #0011 0100 Pipe 4 #0100 0101 Pipe 5 #0101 0110 Pipe 6 #0110 0111 Pipe 7 #0111 1000 Pipe 8 #1000 1001 Pipe 9 #1001 others Setting prohibited true CFIFOCTR CFIFO Port Control Register 0x022 16 read-write 0x0000 0xFFFF BVAL Buffer Memory Valid Flag 15 15 read-write 0 Invalid #0 1 Writing ended #1 BCLR CPU Buffer Clear Note: Only 0 can be read. 14 14 write-only 0 Does not operate #0 1 FIFO buffer cleared on the CPU side. #1 FRDY FIFO Port Ready 13 13 read-only 0 FIFO port access is disabled. #0 1 FIFO port access is enabled. #1 Reserved These bits are read as 0000. The write value should be 0000. 9 12 read-write DTLN Receive Data Length Indicates the length of the receive data. 0 8 read-only D0FIFOSEL D0FIFO Port Select Register 0x028 16 read-write 0x0000 0xFFFF RCNT Read Count Mode 15 15 read-write 0 The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.) #0 1 The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1) #1 REW Buffer Pointer Rewind Note: Only 0 can be read. 14 14 write-only 0 The buffer pointer is not rewound. #0 1 The buffer pointer is rewound. #1 DCLRM Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read 13 13 read-write 0 Auto buffer clear mode is disabled. #0 1 Auto buffer clear mode is enabled. #1 DREQE DMA/DTC Transfer Request Enable 12 12 read-write 0 DMA/DTC transfer request is disabled. #0 1 DMA/DTC transfer request is enabled. #1 Reserved This bit is read as 0. The write value should be 0. 11 11 read-write MBW FIFO Port Access Bit Width 10 10 read-write 0 8-bit width #0 1 16-bit width #1 Reserved This bit is read as 0. The write value should be 0. 9 9 read-write BIGEND FIFO Port Endian Control 8 8 read-write 0 Little endian #0 1 Big endian #1 Reserved These bits are read as 0000. The write value should be 0000. 4 7 read-write CURPIPE FIFO Port Access Pipe Specification 0 3 read-write 0000 DCP (Default control pipe) #0000 0001 Pipe 1 #0001 0010 Pipe 2 #0010 0011 Pipe 3 #0011 0100 Pipe 4 #0100 0101 Pipe 5 #0101 0110 Pipe 6 #0110 0111 Pipe 7 #0111 1000 Pipe 8 #1000 1001 Pipe 9 #1001 others Setting prohibited true D0FIFOCTR D0FIFO Port Control Register 0x02A 16 read-write 0x0000 0xFFFF BVAL Buffer Memory Valid Flag 15 15 read-write 0 Invalid #0 1 Writing ended #1 BCLR CPU Buffer Clear Note: Only 0 can be read. 14 14 write-only 0 Does not operate #0 1 FIFO buffer cleared on the CPU side. #1 FRDY FIFO Port Ready 13 13 read-only 0 FIFO port access is disabled. #0 1 FIFO port access is enabled. #1 Reserved These bits are read as 0000. The write value should be 0000. 9 12 read-write DTLN Receive Data Length Indicates the length of the receive data. 0 8 read-only D1FIFOSEL D1FIFO Port Select Register 0x02C 16 read-write 0x0000 0xFFFF RCNT Read Count Mode 15 15 read-write 0 The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.) #0 1 The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1) #1 REW Buffer Pointer Rewind 14 14 write-only 0 The buffer pointer is not rewound. #0 1 The buffer pointer is rewound. #1 DCLRM Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read 13 13 read-write 0 Auto buffer clear mode is disabled. #0 1 Auto buffer clear mode is enabled. #1 DREQE DMA/DTC Transfer Request Enable 12 12 read-write 0 DMA/DTC transfer request is disabled. #0 1 DMA/DTC transfer request is enabled. #1 Reserved This bit is read as 0. The write value should be 0. 11 11 read-write MBW FIFO Port Access Bit Width 10 10 read-write 0 8-bit width #0 1 16-bit width #1 Reserved This bit is read as 0. The write value should be 0. 9 9 read-write BIGEND FIFO Port Endian Control 8 8 read-write 0 Little endian #0 1 Big endian #1 Reserved These bits are read as 0000. The write value should be 0000. 4 7 read-write CURPIPE FIFO Port Access Pipe Specification 0 3 read-write 0000 DCP (Default control pipe) #0000 0001 Pipe 1 #0001 0010 Pipe 2 #0010 0011 Pipe 3 #0011 0100 Pipe 4 #0100 0101 Pipe 5 #0101 0110 Pipe 6 #0110 0111 Pipe 7 #0111 1000 Pipe 8 #1000 1001 Pipe 9 #1001 others Setting prohibited true D1FIFOCTR D1FIFO Port Control Register 0x02E 16 read-write 0x0000 0xFFFF BVAL Buffer Memory Valid Flag 15 15 read-write 0 Invalid #0 1 Writing ended #1 BCLR CPU Buffer Clear Note: Only 0 can be read. 14 14 write-only 0 Does not operate #0 1 FIFO buffer cleared on the CPU side. #1 FRDY FIFO Port Ready 13 13 read-only 0 FIFO port access is disabled. #0 1 FIFO port access is enabled. #1 Reserved These bits are read as 0000. The write value should be 0000. 9 12 read-write DTLN Receive Data Length Indicates the length of the receive data. 0 8 read-only INTENB0 Interrupt Enable Register 0 0x030 16 read-write 0x0000 0xFFFF VBSE VBUS Interrupt Enable 15 15 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 RSME Resume Interrupt Enable 14 14 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 SOFE Frame Number Update Interrupt Enable 13 13 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 DVSE Device State Transition Interrupt Enable 12 12 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 CTRE Control Transfer Stage Transition Interrupt Enable 11 11 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 BEMPE Buffer Empty Interrupt Enable 10 10 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 NRDYE Buffer Not Ready Response Interrupt Enable 9 9 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 BRDYE Buffer Ready Interrupt Enable 8 8 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 Reserved These bits are read as 00000000. The write value should be 00000000. 0 7 read-write INTENB1 Interrupt Enable Register 1 0x032 16 read-write 0x0000 0xFFFF OVRCRE Overcurrent Input Change Interrupt Enable 15 15 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 BCHGE USB Bus Change Interrupt Enable 14 14 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 Reserved This bit is read as 0. The write value should be 0. 13 13 read-write DTCHE Disconnection Detection Interrupt Enable 12 12 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 ATTCHE Connection Detection Interrupt Enable 11 11 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 Reserved These bits are read as 0000. The write value should be 0000. 7 10 read-write EOFERRE EOF Error Detection Interrupt Enable 6 6 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 SIGNE Setup Transaction Error Interrupt Enable 5 5 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 SACKE Setup Transaction Normal Response Interrupt Enable 4 4 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 Reserved These bits are read as 000. The write value should be 000. 1 3 read-write PDDETINTE0 PDDETINT0 Detection Interrupt Enable 0 0 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 BRDYENB BRDY Interrupt Enable Register 0x036 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000. The write value should be 000000. 10 15 read-write PIPE9BRDYE BRDY Interrupt Enable for PIPE9 9 9 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE8BRDYE BRDY Interrupt Enable for PIPE8 8 8 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE7BRDYE BRDY Interrupt Enable for PIPE7 7 7 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE6BRDYE BRDY Interrupt Enable for PIPE6 6 6 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE5BRDYE BRDY Interrupt Enable for PIPE5 5 5 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE4BRDYE BRDY Interrupt Enable for PIPE4 4 4 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE3BRDYE BRDY Interrupt Enable for PIPE3 3 3 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE2BRDYE BRDY Interrupt Enable for PIPE2 2 2 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE1BRDYE BRDY Interrupt Enable for PIPE1 1 1 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE0BRDYE BRDY Interrupt Enable for PIPE0 0 0 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 NRDYENB NRDY Interrupt Enable Register 0x038 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000. The write value should be 000000. 10 15 read-write PIPE9NRDYE NRDY Interrupt Enable for PIPE9 9 9 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE8NRDYE NRDY Interrupt Enable for PIPE8 8 8 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE7NRDYE NRDY Interrupt Enable for PIPE7 7 7 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE6NRDYE NRDY Interrupt Enable for PIPE6 6 6 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE5NRDYE NRDY Interrupt Enable for PIPE5 5 5 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE4NRDYE NRDY Interrupt Enable for PIPE4 4 4 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE3NRDYE NRDY Interrupt Enable for PIPE3 3 3 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE2NRDYE NRDY Interrupt Enable for PIPE2 2 2 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE1NRDYE NRDY Interrupt Enable for PIPE1 1 1 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE0NRDYE NRDY Interrupt Enable for PIPE0 0 0 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 BEMPENB BEMP Interrupt Enable Register 0x03A 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000. The write value should be 000000. 10 15 read-write PIPE9BEMPE BEMP Interrupt Enable for PIPE9 9 9 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE8BEMPE BEMP Interrupt Enable for PIPE8 8 8 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE7BEMPE BEMP Interrupt Enable for PIPE7 7 7 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE6BEMPE BEMP Interrupt Enable for PIPE6 6 6 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE5BEMPE BEMP Interrupt Enable for PIPE5 5 5 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE4BEMPE BEMP Interrupt Enable for PIPE4 4 4 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE3BEMPE BEMP Interrupt Enable for PIPE3 3 3 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE2BEMPE BEMP Interrupt Enable for PIPE2 2 2 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE1BEMPE BEMP Interrupt Enable for PIPE1 1 1 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE0BEMPE BEMP Interrupt Enable for PIPE0 0 0 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 SOFCFG SOF Output Configuration Register 0x03C 16 read-write 0x0000 0xFFFF Reserved These bits are read as 0000000. The write value should be 0000000. 9 15 read-write TRNENSEL Transaction-Enabled Time Select 8 8 read-write 0 Not low-speed communication #0 1 Low-speed communication. #1 Reserved This bit is read as 0. The write value should be 0. 7 7 read-write BRDYM BRDY Interrupt Status Clear Timing 6 6 read-write 0 BRDY flag cleared by software #0 1 BRDY flag cleared by the USBFS through a data read from the FIFO buffer or data write to the FIFO buffer. #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write EDGESTS Edge Interrupt Output Status Monitor 4 4 read-only 0 before stopping the clock supply to the USB module #0 1 the edge interrupt output signal is in the middle of the edge processing #1 Reserved These bits are read as 0000. The write value should be 0000. 0 3 read-write INTSTS0 Interrupt Status Register 0 0x040 16 read-write 0x0000 0xFF7F VBINT VBUS Interrupt Status 15 15 read-write zeroToClear modify 0 VBUS interrupts are not generated. #0 1 VBUS interrupts are generated. #1 RESM Resume Interrupt Status 14 14 read-write zeroToClear modify 0 Resume interrupts are not generated. #0 1 Resume interrupts are generated. #1 SOFR Frame Number Refresh Interrupt Status 13 13 read-write zeroToClear modify 0 SOF interrupts are not generated. #0 1 SOF interrupts are generated. #1 DVST Device State Transition Interrupt Status 12 12 read-write zeroToClear modify 0 Device state transition interrupts are not generated. #0 1 Device state transition interrupts are generated. #1 CTRT Control Transfer Stage Transition Interrupt Status 11 11 read-write zeroToClear modify 0 Control transfer stage transition interrupts are not generated. #0 1 Control transfer stage transition interrupts are generated. #1 BEMP Buffer Empty Interrupt Status 10 10 read-only 0 BEMP interrupts are not generated. #0 1 BEMP interrupts are generated. #1 NRDY Buffer Not Ready Interrupt Status 9 9 read-only 0 NRDY interrupts are not generated. #0 1 NRDY interrupts are generated. #1 BRDY Buffer Ready Interrupt Status 8 8 read-only 0 BRDY interrupts are not generated. #0 1 BRDY interrupts are generated. #1 VBSTS VBUS Input Status 7 7 read-only 0 USB_VBUS pin is low. #0 1 USB_VBUS pin is high. #1 DVSQ Device State 4 6 read-only 000 Powered state #000 001 Default state #001 010 Address state #010 011 Configured state #011 others Suspended state true VALID USB Request Reception 3 3 read-write 0 Setup packet is not received #0 1 Setup packet is received #1 CTSQ Control Transfer Stage 0 2 read-only 000 Idle or setup stage #000 001 Control read data stage #001 010 Control read status stage #010 011 Control write data stage #011 100 Control write status stage #100 101 Control write (no data) status stage #101 110 Control transfer sequence error #110 others Setting prohibited true INTSTS1 Interrupt Status Register 1 0x042 16 read-write 0x0000 0xFFFF OVRCR Overcurrent Input Change Interrupt Status 15 15 read-write zeroToClear modify 0 OVRCR interrupts are not generated. #0 1 OVRCR interrupts are generated. #1 BCHG USB Bus Change Interrupt Status 14 14 read-write zeroToClear modify 0 BCHG interrupts are not generated. #0 1 BCHG interrupts are generated. #1 Reserved This bit is read as 0. The write value should be 0. 13 13 read-write DTCH USB Disconnection Detection Interrupt Status 12 12 read-write zeroToClear modify 0 DTCH interrupts are not generated. #0 1 DTCH interrupts are generated. #1 ATTCH ATTCH Interrupt Status 11 11 read-write zeroToClear modify 0 ATTCH interrupts are not generated. #0 1 ATTCH interrupts are generated. #1 Reserved These bits are read as 0000. The write value should be 0000. 7 10 read-write EOFERR EOF Error Detection Interrupt Status 6 6 read-write zeroToClear modify 0 EOFERR interrupts are not generated. #0 1 EOFERR interrupts are generated. #1 SIGN Setup Transaction Error Interrupt Status 5 5 read-write zeroToClear modify 0 SIGN interrupts are not generated. #0 1 SIGN interrupts are generated. #1 SACK Setup Transaction Normal Response Interrupt Status 4 4 read-write zeroToClear modify 0 SACK interrupts are not generated. #0 1 SACK interrupts are generated. #1 Reserved These bits are read as 000. The write value should be 000. 1 3 read-write PDDETINT0 PDDET0 Detection Interrupt Status 0 0 read-write zeroToClear modify 0 PDDET0 detection interrupts are not generated. #0 1 PDDET0 detection interrupts are generated. #1 BRDYSTS BRDY Interrupt Status Register 0x046 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000. The write value should be 000000. 10 15 read-write PIPE9BRDY BRDY Interrupt Status for PIPE9 9 9 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE8BRDY BRDY Interrupt Status for PIPE8 8 8 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE7BRDY BRDY Interrupt Status for PIPE7 7 7 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE6BRDY BRDY Interrupt Status for PIPE6 6 6 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE5BRDY BRDY Interrupt Status for PIPE5 5 5 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE4BRDY BRDY Interrupt Status for PIPE4 4 4 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE3BRDY BRDY Interrupt Status for PIPE3 3 3 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE2BRDY BRDY Interrupt Status for PIPE2 2 2 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE1BRDY BRDY Interrupt Status for PIPE1 1 1 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE0BRDY BRDY Interrupt Status for PIPE0 0 0 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 NRDYSTS NRDY Interrupt Status Register 0x048 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000. The write value should be 000000. 10 15 read-write PIPE9NRDY NRDY Interrupt Status for PIPE9 9 9 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE8NRDY NRDY Interrupt Status for PIPE8 8 8 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE7NRDY NRDY Interrupt Status for PIPE7 7 7 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE6NRDY NRDY Interrupt Status for PIPE6 6 6 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE5NRDY NRDY Interrupt Status for PIPE5 5 5 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE4NRDY NRDY Interrupt Status for PIPE4 4 4 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE3NRDY NRDY Interrupt Status for PIPE3 3 3 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE2NRDY NRDY Interrupt Status for PIPE2 2 2 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE1NRDY NRDY Interrupt Status for PIPE1 1 1 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE0NRDY NRDY Interrupt Status for PIPE0 0 0 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 BEMPSTS BEMP Interrupt Status Register 0x04A 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000. The write value should be 000000. 10 15 read-write PIPE9BEMP BEMP Interrupt Status for PIPE9 9 9 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE8BEMP BEMP Interrupt Status for PIPE8 8 8 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE7BEMP BEMP Interrupt Status for PIPE7 7 7 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE6BEMP BEMP Interrupt Status for PIPE6 6 6 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE5BEMP BEMP Interrupt Status for PIPE5 5 5 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE4BEMP BEMP Interrupt Status for PIPE4 4 4 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE3BEMP BEMP Interrupt Status for PIPE3 3 3 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE2BEMP BEMP Interrupt Status for PIPE2 2 2 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE1BEMP BEMP Interrupt Status for PIPE1 1 1 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE0BEMP BEMP Interrupt Status for PIPE0 0 0 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 FRMNUM Frame Number Register 0x04C 16 read-write 0x0000 0xFFFF OVRN Overrun/Underrun Detection Status 15 15 read-write 0 No error #0 1 An error occurred #1 CRCE Receive Data Error 14 14 read-write 0 No error #0 1 An error occurred #1 Reserved These bits are read as 000. The write value should be 000. 11 13 read-write FRNM Frame Number Latest frame number 0 10 read-only USBREQ USB Request Type Register 0x054 16 read-write 0x0000 0xFFFF BREQUEST Request These bits store the USB request bRequest value. 8 15 read-write BMREQUESTTYPE Request Type These bits store the USB request bmRequestType value. 0 7 read-write USBVAL USB Request Value Register 0x056 16 read-write 0x0000 0xFFFF WVALUE Value These bits store the USB request Value value. 0 15 read-write USBINDX USB Request Index Register 0x058 16 read-write 0x0000 0xFFFF WINDEX Index These bits store the USB request wIndex value. 0 15 read-write USBLENG USB Request Length Register 0x05A 16 read-write 0x0000 0xFFFF WLENTUH Length These bits store the USB request wLength value. 0 15 read-write DCPCFG DCP Configuration Register 0x05C 16 read-write 0x0000 0xFFFF Reserved These bits are read as 00000000. The write value should be 00000000. 8 15 read-write SHTNAK Pipe Disabled at End of Transfer 7 7 read-write 0 Pipe continued at the end of transfer #0 1 Pipe disabled at the end of transfer #1 Reserved These bits are read as 00. The write value should be 00. 5 6 read-write DIR Transfer Direction 4 4 read-write 0 Data receiving direction #0 1 Data transmitting direction #1 Reserved These bits are read as 0000. The write value should be 0000. 0 3 read-write DCPMAXP DCP Maximum Packet Size Register 0x05E 16 read-write 0x0040 0xFFFF DEVSEL Device Select 12 15 read-write 0000 Address 0000 #0000 0001 Address 0001 #0001 0010 Address 0010 #0010 0011 Address 0011 #0011 0100 Address 0100 #0100 0101 Address 0101 #0101 others Settings prohibited. true Reserved These bits are read as 00000. The write value should be 00000. 7 11 read-write MXPS Maximum Packet Size These bits set the maximum amount of data (maximum packet size) in payloads for the DCP. 0 6 read-write 0x08 8 bytes 0x08 0x10 16 bytes 0x10 0x18 24 bytes 0x18 0x20 32 bytes 0x20 0x28 40 bytes 0x28 0x30 48 bytes 0x30 0x38 56 bytes 0x38 0x40 64 bytes 0x40 0x48 72 bytes 0x48 0x50 80 bytes 0x50 0x58 88 bytes 0x58 0x60 96 bytes 0x60 0x68 104 bytes 0x68 0x70 112 bytes 0x70 0x78 120 bytes 0x78 others Setting prohibited true DCPCTR DCP Control Register 0x060 16 read-write 0x0040 0xFFFF BSTS Buffer Status 15 15 read-only 0 Buffer access is disabled. #0 1 Buffer access is enabled. #1 SUREQ Setup Token Transmission 14 14 read-write 0 Invalid #0 1 Transmits the setup packet. #1 Reserved These bits are read as 00. The write value should be 00. 12 13 read-write SUREQCLR SUREQ Bit Clear 11 11 read-write 0 Invalid #0 1 Clears the SUREQ bit to 0. #1 Reserved These bits are read as 00. The write value should be 00. 9 10 read-write SQCLR Sequence Toggle Bit Clear 8 8 write-only 0 Invalid #0 1 Specifies DATA0. #1 SQSET Sequence Toggle Bit Set 7 7 write-only 0 Invalid #0 1 Specifies DATA1. #1 SQMON Sequence Toggle Bit Monitor 6 6 read-only 0 DATA0 #0 1 DATA1 #1 PBUSY Pipe Busy 5 5 read-only 0 DCP is not used for the transaction. #0 1 DCP is used for the transaction. #1 Reserved These bits are read as 00. The write value should be 00. 3 4 read-write CCPL Control Transfer End Enable 2 2 read-write 0 Invalid #0 1 Completion of control transfer is enabled. #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depending on the buffer state) #01 10 STALL response #10 11 STALL response #11 PIPESEL Pipe Window Select Register 0x064 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 15 read-write PIPESEL Pipe Window Select 0 3 read-write 0000 No pipe selected #0000 0001 PIPE1 #0001 0010 PIPE2 #0010 0011 PIPE3 #0011 0100 PIPE4 #0100 0101 PIPE5 #0101 0110 PIPE6 #0110 0111 PIPE7 #0111 1000 PIPE8 #1000 1001 PIPE9 #1001 others Settings prohibited. true PIPECFG Pipe Configuration Register 0x068 16 read-write 0x0000 0xFFFF TYPE Transfer Type 14 15 read-write 00 Pipe not used #00 01 Bulk transfer(PIPE1 and PIPE5) /Setting prohibited(PIPE6 to PIPE9) #01 10 Setting prohibited(PIPE1 and PIPE5) /Interrupt transfer(PIPE6 to PIPE9) #10 11 Isochronous transfer(PIPE1 and PIPE2) /Setting prohibited(PIPE3 to PIPE9) #11 Reserved These bits are read as 000. The write value should be 000. 11 13 read-write BFRE BRDY Interrupt Operation Specification 10 10 read-write 0 BRDY interrupt upon transmitting or receiving data #0 1 BRDY interrupt upon completion of reading data #1 DBLB Double Buffer Mode 9 9 read-write 0 Single buffer #0 1 Double buffer #1 Reserved This bit is read as 0. The write value should be 0. 8 8 read-write SHTNAK Pipe Disabled at End of Transfer 7 7 read-write 0 Continue pipe operation after transfer ends #0 1 Disable pipe operation after transfer ends. #1 Reserved This bit is read as 0. The write value should be 0. 6 6 read-write Reserved This bit is read as 0. The write value should be 0. 5 5 read-write DIR Transfer Direction 4 4 read-write 0 Receiving direction #0 1 Transmitting direction #1 EPNUM Endpoint Number These bits specify the endpoint number for the selected pipe. Setting 0000b means unused pipe. 0 3 read-write PIPEMAXP Pipe Maximum Packet Size Register 0x06C 16 read-write 0x0000 0xFFBF DEVSEL Device Select 12 15 read-write 0000 Address 0000 #0000 0001 Address 0001 #0001 0010 Address 0010 #0010 0011 Address 0011 #0011 0100 Address 0100 #0100 0101 Address 0101 #0101 others Settings prohibited. true Reserved These bits are read as 000. The write value should be 000. 9 11 read-write MXPS Maximum Packet Size PIPE1 and PIPE2: 1 byte (001h) to 256 bytes (100h) PIPE3 to PIPE5: 8 bytes (008h), 16 bytes (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and [2:0] are not provided.) PIPE6 to PIPE9: 1 byte (001h) to 64 bytes (040h) (Bits [8:7] are not provided.) 0 8 read-write PIPEPERI Pipe Cycle Control Register 0x06E 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000. The write value should be 000. 13 15 read-write IFIS Isochronous IN Buffer Flush 12 12 read-write 0 The buffer is not flushed. #0 1 The buffer is flushed. #1 Reserved These bits are read as 000000000. The write value should be 000000000. 3 11 read-write IITV Interval Error Detection Interval Specifies the interval error detection timing for the selected pipe in terms of frames, which is expressed as nth power of 2. 0 2 read-write 5 0x002 1-5 PIPE%sCTR Pipe %s Control Register 0x070 16 read-write 0x0000 0xFFFF BSTS Buffer Status 15 15 read-only 0 Buffer access by the CPU is disabled. #0 1 Buffer access by the CPU is enabled. #1 INBUFM Transmit Buffer Monitor 14 14 read-only 0 No data to be transmitted is in the FIFO buffer #0 1 Data to be transmitted is in the FIFO buffer #1 Reserved These bits are read as 000. The write value should be 000. 11 13 read-write ATREPM Auto Response Mode 10 10 read-write 0 Auto response disabled. #0 1 Auto response enabled. #1 ACLRM Auto Buffer Clear Mode 9 9 read-write 0 Disabled #0 1 Enabled (all buffers are initialized) #1 SQCLR Sequence Toggle Bit Clear 8 8 read-write 0 Write disabled #0 1 Specifies DATA0. #1 SQSET Sequence Toggle Bit Set 7 7 read-write 0 Write disabled #0 1 Specifies DATA1. #1 SQMON Sequence Toggle Bit Confirmation 6 6 read-only 0 DATA0 #0 1 DATA1 #1 PBUSY Pipe Busy 5 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction. #1 Reserved These bits are read as 000. The write value should be 000. 2 4 read-write PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depending on the buffer state) #01 10 STALL response #10 11 STALL response #11 4 0x002 6-9 PIPE%sCTR Pipe %s Control Register 0x07A 16 read-write 0x0000 0xFFFF BSTS Buffer Status 15 15 read-only 0 Buffer access is disabled. #0 1 Buffer access is enabled. #1 Reserved These bits are read as 00000. The write value should be 00000. 10 14 read-write ACLRM Auto Buffer Clear Mode 9 9 read-write 0 Auto buffer clear mode is disabled. #0 1 Auto buffer clear mode is enabled (all buffers are initialized) #1 SQCLR Sequence Toggle Bit Clear 8 8 write-only 0 Invalid #0 1 Specifies DATA0. #1 SQSET Sequence Toggle Bit Set 7 7 write-only 0 Invalid #0 1 Specifies DATA1. #1 SQMON Sequence Toggle Bit Confirmation 6 6 read-only 0 DATA0 #0 1 DATA1 #1 PBUSY Pipe Busy 5 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction. #1 Reserved These bits are read as 000. The write value should be 000. 2 4 read-write PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depending on the buffer state) #01 10 STALL response #10 11 STALL response #11 5 0x004 1-5 PIPE%sTRE Pipe %s Transaction Counter Enable Register 0x090 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000. The write value should be 000000. 10 15 read-write TRENB Transaction Counter Enable 9 9 read-write 0 Transaction counter is disabled. #0 1 Transaction counter is enabled. #1 TRCLR Transaction Counter Clear 8 8 read-write 0 Invalid #0 1 The current counter value is cleared. #1 Reserved These bits are read as 00000000. The write value should be 00000000. 0 7 read-write 5 0x004 1-5 PIPE%sTRN Pipe %s Transaction Counter Register 0x092 16 read-write 0x0000 0xFFFF TRNCNT Transaction Counter 0 15 read-write 6 0x002 0-5 DEVADD%s Device Address %s Configuration Register 0x0D0 16 read-write 0x0000 0xFFFF Reserved These bits are read as 00000000. The write value should be 00000000. 8 15 read-write USBSPD Transfer Speed of Communication Target Device 6 7 read-write 00 DEVADDn is not used #00 01 Low speed #01 10 Full speed #10 11 Setting prohibited #11 Reserved These bits are read as 000000. The write value should be 000000. 0 5 read-write USBMC USB Module Control Register 0x0CC 16 read-write 0x0002 0xFFFF Reserved These bits are read as 00000000. The write value should be 00000000. 8 15 read-write VDCEN USB Regulator On/Off Control 7 7 read-write 0 USB regulator off #0 1 USB regulator on #1 Reserved These bits are read as 00000. The write value should be 00000. 2 6 read-write Reserved This bit is read as 1. The write value should be 1. 1 1 read-write VDDUSBE USB Reference Power Supply Circuit On/Off Control 0 0 read-write 0 USB reference power supply circuit off #0 1 USB reference power supply circuit on #1 USBBCCTRL0 BC Control Register 0 0x0B0 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000. The write value should be 000000. 10 15 read-write PDDETSTS0 D+ Pin 0.6 V Input Detection Status 9 9 read-only 0 Not detected #0 1 Detected #1 CHGDETSTS0 D- Pin 0.6 V Input Detection Status 8 8 read-only 0 Not detected #0 1 Detected #1 BATCHGE0 BC (Battery Charger) Function Ch0 General Enable Control 7 7 read-write 0 Disabled #0 1 Enabled #1 Reserved This bit is read as 0. The write value should be 0. 6 6 read-write VDMSRCE0 D- Pin VDMSRC (0.6 V) Output Control 5 5 read-write 0 Stop #0 1 0.6V output #1 IDPSINKE0 D+ Pin 0.6 V Input Detection (Comparator and Sink) Control 4 4 read-write 0 Detection off #0 1 Detection on ( Comparator and sink current on ) #1 VDPSRCE0 D+ Pin VDPSRC (0.6 V) Output Control 3 3 read-write 0 Stop #0 1 0.6V output #1 IDMSINKE0 D- Pin 0.6 V Input Detection (Comparator and Sink) Control 2 2 read-write 0 Detection off #0 1 Detection on ( Comparator and sink current on ) #1 IDPSRCE0 D+ Pin IDPSRC Output Control 1 1 read-write 0 Stop #0 1 10uA output #1 RPDME0 D- Pin Pull-Down Control 0 0 read-write 0 Pull-down off #0 1 Pull-down on #1 WDT Watchdog Timer 0x40044200 0x00 1 registers 0x02 5 registers 0x08 1 registers WDTRR WDT Refresh Register 0x00 8 read-write 0xFF 0xFF WDTRR WDTRR is an 8-bit register that refreshes the down-counter of the WDT. 0 7 read-write WDTCR WDT Control Register 0x02 16 read-write 0x33F3 0xFFFF Reserved These bits are read as 00. The write value should be 00. 14 15 read-write RPSS Window Start Position Selection 12 13 read-write 00 25 percent #00 01 50 percent #01 10 75 percent #10 11 100 percent (window start position is not specified) #11 Reserved These bits are read as 00. The write value should be 00. 10 11 read-write RPES Window End Position Selection 8 9 read-write 00 75 percent #00 01 50 percent #01 10 25 percent #10 11 0 percent (window end position is not specified) #11 CKS Clock Division Ratio Selection 4 7 read-write 0001 PCLK/4 #0001 0100 PCLK/64 #0100 1111 PCLK/128 #1111 0110 PCLK/512 #0110 0111 PCLK/2048 #0111 1000 PCLK/8192 #1000 others setting prohibited true Reserved These bits are read as 00. The write value should be 00. 2 3 read-write TOPS Timeout Period Selection 0 1 read-write 00 1,024 cycles (03FFh) #00 01 4,096 cycles (0FFFh) #01 10 8,192 cycles (1FFFh) #10 11 16,384 cycles (3FFFh) #11 WDTSR WDT Status Register 0x04 16 read-write 0x0000 0xFFFF REFEF Refresh Error Flag 15 15 read-write zeroToClear modify 0 No refresh error occurred #0 1 Refresh error occurred #1 UNDFF Underflow Flag 14 14 read-write zeroToClear modify 0 No underflow occurred #0 1 Underflow occurred #1 CNTVAL Down-Counter Value Value counted by the down-counter 0 13 read-only WDTRCR WDT Reset Control Register 0x06 8 read-write 0x80 0xFF RSTIRQS Reset Interrupt Request Selection 7 7 read-write 0 Non-maskable interrupt request or interrupt request output is enabled #0 1 Reset output is enabled. #1 WDTCSTPR WDT Count Stop Control Register 0x08 8 read-write 0x80 0xFF SLCSTP Sleep-Mode Count Stop Control 7 7 read-write 0 Count stop is disabled. #0 1 Count is stopped at a transition to sleep mode. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 0 6 read-write ACMPLP Low-Power Analog Comparator 0x40085E00 0x00 3 registers 0x04 2 registers COMPMDR ACMPLP Mode Setting Register 0x00 8 read-write 0x00 0xFF C1MON ACMPLP1 Monitor Flag 7 7 read-only 0 CMPIN1 < CMPREF1, CMPIN1 < internal reference voltage, or ACMPLP1 operation disabled.(When the window function is disabled)/CMPIN1 < VRFL, CMPIN1 > VRFH, or ACMPLP1 operation disabled.(When the window function is enabled) #0 1 CMPIN1 > CMPREF1, or CMPIN1 > internal reference voltage.(When the window function is disabled)/VRFL < CMPIN1 < VRFH.(When the window function is enabled) #1 C1VRF ACMPLP1 Reference Voltage Selection 6 6 read-write 0 IVREF0 or IVREF1 #0 1 internal reference voltage (Vref) #1 C1WDE ACMPLP1 Window Function Mode Enable 5 5 read-write 0 Disabled #0 1 Enabled #1 C1ENB ACMPLP1 Operation Enable 4 4 read-write 0 Disabled #0 1 Enabled #1 C0MON ACMPLP0 Monitor Flag 3 3 read-only 0 CMPIN0 < CMPREF0, CMPIN0 < internal reference voltage, or ACMPLP0 operation disabled.(When the window function is disabled)/CMPIN0 < VRFL, CMPIN0 > VRFH, or ACMPLP0 operation disabled.(When the window function is enabled) #0 1 CMPIN0 > CMPREF0, or CMPIN0 > internal reference voltage.(When the window function is disabled)/VRFL < CMPIN0 < VRFH.(When the window function is enabled) #1 C0VRF ACMPLP0 Reference Voltage Selection 2 2 read-write 0 IVREF0 #0 1 internal reference voltage (Vref) #1 C0WDE ACMPLP0 Window Function Mode Enable 1 1 read-write 0 Disabled #0 1 Enabled #1 C0ENB ACMPLP0 Operation Enable 0 0 read-write 0 Disabled #0 1 Enabled #1 COMPFIR ACMPLP Filter Control Register 0x01 8 read-write 0x00 0xFF C1EDG ACMPLP1 Edge Detection Selection 7 7 read-write 0 Interrupt and ELC event request by one-edge detection #0 1 Interrupt and ELC event request by both-edge detection #1 C1EPO ACMPLP1 Edge Polarity Switching 6 6 read-write 0 Interrupt and ELC event request at rising edge #0 1 Interrupt and ELC event request at falling edge #1 C1FCK ACMPLP1 Filter Select 4 5 read-write 00 No Sampling (bypass) #00 01 Sampling at PCLK #01 10 Sampling at PCLK/8 #10 11 Sampling at PCLK/32 #11 C0EDG ACMPLP0 Edge Detection Selection 3 3 read-write 0 Interrupt and ELC event request by one-edge detection #0 1 Interrupt and ELC event request by both-edge detection #1 C0EPO ACMPLP0 Edge Polarity Switching 2 2 read-write 0 Interrupt and ELC event request at rising edge #0 1 Interrupt and ELC event request at falling edge #1 C0FCK ACMPLP0 Filter Select 0 1 read-write 00 No Sampling (bypass) #00 01 Sampling at PCLK #01 10 Sampling at PCLK/8 #10 11 Sampling at PCLK/32 #11 COMPOCR ACMPLP Output Control Register 0x02 8 read-write 0x00 0xFF SPDMD ACMPLP0/ACMPLP1 Speed Selection 7 7 read-write 0 Comparator low-speed mode #0 1 Comparator high-speed mode #1 C1OP ACMPLP1 VCOUT Output Polarity Selection 6 6 read-write 0 Non inverted #0 1 Inverted #1 C1OE ACMPLP1 VCOUT Pin Output Enable 5 5 read-write 0 Disabled #0 1 Enabled #1 Reserved These bits are read as 00. The write value should be 00. 3 4 read-write C0OP ACMPLP0 VCOUT Output Polarity Selection 2 2 read-write 0 Non inverted #0 1 Inverted #1 C0OE ACMPLP0 VCOUT Pin Output Enable 1 1 read-write 0 Disabled #0 1 Enabled #1 Reserved This bit is read as 0. The write value should be 0. 0 0 read-write COMPSEL0 Comparator Input Select Register 0x04 8 read-write 0x11 0xFF Reserved This bit is read as 0. The write value should be 0. 7 7 read-write CMPSEL64 ACMPLP1 Input (IVCMP1) Selection 4 6 read-write 000 No input #000 001 CMPIN1 (P102) #001 100 CMPIN1 (P501) #100 others settings prohibited true Reserved This bit is read as 0. The write value should be 0. 3 3 read-write CMPSEL20 ACMPLP0 Input(IVCMP0) Selection 0 2 read-write 000 No input #000 001 CMPIN0 (P100) #001 100 CMPIN0 (P503) #100 others settings prohibited true COMPSEL1 Comparator Reference Voltage Select Register 0x05 8 read-write 0x91 0xFF C1VRF2 ACMPLP1 Reference Voltage Selection 7 7 read-write 0 IVREF0 selected #0 1 IVREF1 selected. #1 CRVS64 ACMPLP1 Reference Voltage(IVREF1) Selection 4 6 read-write 000 No input #000 001 CMPREF1 (P103) #001 010 DAC8 (ch1) output #010 100 CMPREF1 (P500) #100 others settings prohibited. true Reserved This bit is read as 0. The write value should be 0. 3 3 read-write CRVS20 ACMPLP0 Reference Voltage(IVREF0) Selection* 0 2 read-write 000 No input #000 001 CMPREF0 (P101) #001 010 DAC8 (ch0) output #010 100 CMPREF0 (P502) #100 others settings prohibited. true ADC140 14bit A/D Converter 0x4005C000 0x00 13 registers 0x0E 48 registers 0x40 20 registers 0x62 22 registers 0x7A 4 registers 0x80 9 registers 0x8A 1 registers 0x8C 1 registers 0x90 21 registers 0xA6 1 registers 0xA8 5 registers 0xB0 33 registers 0xD2 1 registers 0xDD 18 registers 0x1A0 4 registers 0x1B0 2 registers 0x1B4 2 registers 0x1E0 1 registers ADCSR A/D Control Register 0x000 16 read-write 0x0000 0xFFFF ADST A/D Conversion Start 15 15 read-write modify 0 Stops A/D conversion process. #0 1 Starts A/D conversion process. #1 ADCS Scan Mode Select 13 14 read-write 00 Single scan mode #00 01 Group scan mode #01 10 Continuous scan mode #10 11 Setting prohibited #11 Reserved These bits are read as 00. The write value should be 00. 11 12 read-write ADHSC A/D Conversion Operation Mode Select 10 10 read-write 0 High speed A/D conversion mode #0 1 Low current A/D conversion mode #1 TRGE Trigger Start Enable 9 9 read-write 0 Disables A/D conversion to be started by the synchronous or asynchronous trigger. #0 1 Enables A/D conversion to be started by the synchronous or asynchronous trigger. #1 EXTRG Trigger Select 8 8 read-write 0 A/D conversion is started by the synchronous trigger (ELC). #0 1 A/D conversion is started by the asynchronous trigger (ADTRG0#). #1 DBLE Double Trigger Mode Select 7 7 read-write 0 Double trigger mode non-selection #0 1 Double trigger mode selection #1 GBADIE Group B Scan End Interrupt Enable 6 6 read-write 0 Disables S12GBADI0 interrupt generation upon group B scan completion. #0 1 Enables S12GBADI0 interrupt generation upon group B scan completion. #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write DBLANS Double Trigger Channel Select These bits select one analog input channel for double triggered operation. The setting is only effective while double trigger mode is selected. 0 4 read-write ADANSA0 A/D Channel Select Register A0 0x004 16 read-write 0x0000 0xFFFF Reserved This bit is read as 0. The write value should be 0. 15 15 read-write ANSA014 AN014 Select 14 14 read-write 0 AN014 is not subjected to conversion. #0 1 AN014 is subjected to conversion. #1 ANSA013 AN013 Select 13 13 read-write 0 AN013 is not subjected to conversion. #0 1 AN013 is subjected to conversion. #1 ANSA012 AN012 Select 12 12 read-write 0 AN012 is not subjected to conversion. #0 1 AN012 is subjected to conversion. #1 ANSA011 AN011 Select 11 11 read-write 0 AN011 is not subjected to conversion. #0 1 AN011 is subjected to conversion. #1 ANSA010 AN010 Select 10 10 read-write 0 AN010 is not subjected to conversion. #0 1 AN010 is subjected to conversion. #1 ANSA09 AN009 Select 9 9 read-write 0 AN009 is not subjected to conversion. #0 1 AN009 is subjected to conversion. #1 ANSA08 AN008 Select 8 8 read-write 0 AN008 is not subjected to conversion. #0 1 AN008 is subjected to conversion. #1 ANSA07 AN007 Select 7 7 read-write 0 AN007 is not subjected to conversion. #0 1 AN007 is subjected to conversion. #1 ANSA06 AN006 Select 6 6 read-write 0 AN006 is not subjected to conversion. #0 1 AN006 is subjected to conversion. #1 ANSA05 AN005 Select 5 5 read-write 0 AN005 is not subjected to conversion. #0 1 AN005 is subjected to conversion. #1 ANSA04 AN004 Select 4 4 read-write 0 AN004 is not subjected to conversion. #0 1 AN004 is subjected to conversion. #1 ANSA03 AN003 Select 3 3 read-write 0 AN003 is not subjected to conversion. #0 1 AN003 is subjected to conversion. #1 ANSA02 AN002 Select 2 2 read-write 0 AN002 is not subjected to conversion. #0 1 AN002 is subjected to conversion. #1 ANSA01 AN001 Select 1 1 read-write 0 AN001 is not subjected to conversion. #0 1 AN001 is subjected to conversion. #1 ANSA00 AN000 Select 0 0 read-write 0 AN000 is not subjected to conversion. #0 1 AN000 is subjected to conversion. #1 ADANSA1 A/D Channel Select Register A1 0x006 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000. The write value should be 000000. 10 15 read-write ANSA25 AN025 Select 9 9 read-write 0 AN025 is not subjected to conversion. #0 1 AN025 is subjected to conversion. #1 ANSA24 AN024 Select 8 8 read-write 0 AN024 is not subjected to conversion. #0 1 AN024 is subjected to conversion. #1 ANSA23 AN023 Select 7 7 read-write 0 AN023 is not subjected to conversion. #0 1 AN023 is subjected to conversion. #1 ANSA22 AN022 Select 6 6 read-write 0 AN022 is not subjected to conversion. #0 1 AN022 is subjected to conversion. #1 ANSA21 AN021 Select 5 5 read-write 0 AN021 is not subjected to conversion. #0 1 AN021 is subjected to conversion. #1 ANSA20 AN020 Select 4 4 read-write 0 AN020 is not subjected to conversion. #0 1 AN020 is subjected to conversion. #1 ANSA19 AN019 Select 3 3 read-write 0 AN019 is not subjected to conversion. #0 1 AN019 is subjected to conversion. #1 ANSA18 AN018 Select 2 2 read-write 0 AN018 is not subjected to conversion. #0 1 AN018 is subjected to conversion. #1 ANSA17 AN017 Select 1 1 read-write 0 AN017 is not subjected to conversion. #0 1 AN017 is subjected to conversion. #1 ANSA16 AN016 Select 0 0 read-write 0 AN016 is not subjected to conversion. #0 1 AN016 is subjected to conversion. #1 ADADS0 A/D-Converted Value Addition/Average Channel Select Register 0 0x008 16 read-write 0x0000 0xFFFF Reserved This bit is read as 0. The write value should be 0. 15 15 read-write ADS14 A/D-Converted Value Addition/Average Channel AN014 Select 14 14 read-write 0 AN014 is not selected. #0 1 AN014 is selected. #1 ADS13 A/D-Converted Value Addition/Average Channel AN013 Select 13 13 read-write 0 AN013 is not selected. #0 1 AN013 is selected. #1 ADS12 A/D-Converted Value Addition/Average Channel AN012 Select 12 12 read-write 0 AN012 is not selected. #0 1 AN012 is selected. #1 ADS11 A/D-Converted Value Addition/Average Channel AN011 Select 11 11 read-write 0 AN011 is not selected. #0 1 AN011 is selected. #1 ADS10 A/D-Converted Value Addition/Average Channel AN010 Select 10 10 read-write 0 AN010 is not selected. #0 1 AN010 is selected. #1 ADS09 A/D-Converted Value Addition/Average Channel AN009 Select 9 9 read-write 0 AN009 is not selected. #0 1 AN009 is selected. #1 ADS08 A/D-Converted Value Addition/Average Channel AN008 Select 8 8 read-write 0 AN008 is not selected. #0 1 AN008 is selected. #1 ADS07 A/D-Converted Value Addition/Average Channel AN007 Select 7 7 read-write 0 AN007 is not selected. #0 1 AN007 is selected. #1 ADS06 A/D-Converted Value Addition/Average Channel AN006 Select 6 6 read-write 0 AN006 is not selected. #0 1 AN006 is selected. #1 ADS05 A/D-Converted Value Addition/Average Channel AN005 Select 5 5 read-write 0 AN005 is not selected. #0 1 AN005 is selected. #1 ADS04 A/D-Converted Value Addition/Average Channel AN004 Select 4 4 read-write 0 AN004 is not selected. #0 1 AN004 is selected. #1 ADS03 A/D-Converted Value Addition/Average Channel AN003 Select 3 3 read-write 0 AN003 is not selected. #0 1 AN003 is selected. #1 ADS02 A/D-Converted Value Addition/Average Channel AN002 Select 2 2 read-write 0 AN002 is not selected. #0 1 AN002 is selected. #1 ADS01 A/D-Converted Value Addition/Average Channel AN001 Select 1 1 read-write 0 AN001 is not selected. #0 1 AN001 is selected. #1 ADS00 A/D-Converted Value Addition/Average Channel AN000 Select 0 0 read-write 0 AN000 is not selected. #0 1 AN000 is selected. #1 ADADS1 A/D-Converted Value Addition/Average Channel Select Register 1 0x00A 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000. The write value should be 000000. 10 15 read-write ADS25 A/D-Converted Value Addition/Average Channel AN025 Select 9 9 read-write 0 AN025 is not selected. #0 1 AN025 is selected. #1 ADS24 A/D-Converted Value Addition/Average Channel AN024 Select 8 8 read-write 0 AN024 is not selected. #0 1 AN024 is selected. #1 ADS23 A/D-Converted Value Addition/Average Channel AN023 Select 7 7 read-write 0 AN023 is not selected. #0 1 AN023 is selected. #1 ADS22 A/D-Converted Value Addition/Average Channel AN022 Select 6 6 read-write 0 AN022 is not selected. #0 1 AN022 is selected. #1 ADS21 A/D-Converted Value Addition/Average Channel AN021 Select 5 5 read-write 0 AN021 is not selected. #0 1 AN021 is selected. #1 ADS20 A/D-Converted Value Addition/Average Channel AN020 Select 4 4 read-write 0 AN020 is not selected. #0 1 AN020 is selected. #1 ADS19 A/D-Converted Value Addition/Average Channel AN019 Select 3 3 read-write 0 AN019 is not selected. #0 1 AN019 is selected. #1 ADS18 A/D-Converted Value Addition/Average Channel AN018 Select 2 2 read-write 0 AN018 is not selected. #0 1 AN018 is selected. #1 ADS17 A/D-Converted Value Addition/Average Channel AN017 Select 1 1 read-write 0 AN017 is not selected. #0 1 AN017 is selected. #1 ADS16 A/D-Converted Value Addition/Average Channel AN016 Select 0 0 read-write 0 AN016 is not selected. #0 1 AN016 is selected. #1 ADADC A/D-Converted Value Addition/Average Count Select Register 0x00C 8 read-write 0x00 0xFF AVEE Average mode enable bit. Note: The AVEE bit converts twice, and only when converting it four times, is effective. Please do not set (ADADC.AVEE=1) to conversion (ADADC.ADC 2:0=010b) three times when you select the average mode. 7 7 read-write 0 Disabled #0 1 Enabled #1 Reserved These bits are read as 0000. The write value should be 0000. 3 6 read-write ADC Addition frequency selection bit. NOTE: AVEE bit is valid at the only setting of ADC[2:0] bits = 001b or 011b. When average mode is selected by setting the ADADC.AVEE bit to 1, do not set the addition count to three times (ADADC.ADC[2:0] = 010b) 0 2 read-write 000 1-time conversion (no addition; same as normal conversion) #000 001 2-time conversion (addition once) #001 010 3-time conversion (addition twice) #010 011 4-time conversion (addition three times) #011 101 16-time conversion (addition 15 times), can be set when selecting 12-bit accuracy. #101 others Setting prohibited true ADCER A/D Control Extended Register 0x00E 16 read-write 0x0000 0xFFFF ADRFMT A/D Data Register Format Select 15 15 read-write 0 Flush-right is selected for the A/D data register format. #0 1 Flush-left is selected for the A/D data register format. #1 Reserved These bits are read as 000. The write value should be 000. 12 14 read-write DIAGM Self-Diagnosis Enable 11 11 read-write 0 Disables self-diagnosis of A/D converter. #0 1 Enables self-diagnosis of A/D converter. #1 DIAGLD Self-Diagnosis Mode Select 10 10 read-write 0 Rotation mode for self-diagnosis voltage #0 1 Fixed mode for self-diagnosis voltage #1 DIAGVAL Self-Diagnosis Conversion Voltage Select 8 9 read-write 00 When the self-diagnosis fixation mode is selected, it set prohibits it. #00 01 The self-diagnosis by using the voltage of 0V. #01 10 The self-diagnosis by using the voltage of reference supply x 1/2. #10 11 The self-diagnosis by using the voltage of the reference supply. #11 Reserved These bits are read as 00. The write value should be 00. 6 7 read-write ACE A/D Data Register Automatic Clearing Enable 5 5 read-write 0 Disables automatic clearing. #0 1 Enables automatic clearing. #1 Reserved This bit is read as 0. The write value should be 0. 4 4 read-write Reserved This bit is read as 0. The write value should be 0. 3 3 read-write ADPRC A/D Conversion Accuracy Specify 1 2 read-write 00 A/D conversion is performed with 12-bit accuracy. #00 11 A/D conversion is performed with 14-bit accuracy. #11 others Setting prohibited true Reserved This bit is read as 0. The write value should be 0. 0 0 read-write ADSTRGR A/D Conversion Start Trigger Select Register 0x010 16 read-write 0x0000 0xFFFF Reserved These bits are read as 00. The write value should be 00. 14 15 read-write TRSA A/D Conversion Start Trigger Select Select the A/D conversion start trigger in single scan mode and continuous mode. In group scan mode, the A/D conversion start trigger for group A is selected. 8 13 read-write Reserved These bits are read as 00. The write value should be 00. 6 7 read-write TRSB A/D Conversion Start Trigger Select for Group B Select the A/D conversion start trigger for group B in group scan mode. 0 5 read-write ADEXICR A/D Conversion Extended Input Control Register 0x012 16 read-write 0x0000 0xFFFF Reserved This bit is read as 0. The write value should be 0. 15 15 read-write Reserved This bit is read as 0. The write value should be 0. 14 14 read-write Reserved This bit is read as 0. The write value should be 0. 12 12 read-write Reserved This bit is read as 0. The write value should be 0. 11 11 read-write Reserved This bit is read as 0. The write value should be 0. 10 10 read-write OCSA Internal Reference Voltage A/D Conversion Select 9 9 read-write 0 The internal reference voltage is not selected. #0 1 The internal reference voltage is selected for group A in single scan mode, continuous scan mode, or group scan mode. #1 TSSA Temperature Sensor Output A/D Conversion Select 8 8 read-write 0 The temperature sensor output is not selected. #0 1 The temperature sensor output is selected. #1 Reserved These bits are read as 000000. The write value should be 000000. 2 7 read-write OCSAD Internal Reference Voltage A/D converted Value Addition/Average Mode Select 1 1 read-write 0 Internal reference voltage A/D-converted value addition/average mode is not selected. #0 1 Internal reference voltage A/D-converted value addition/average mode is selected. #1 TSSAD Temperature Sensor Output A/D converted Value Addition/Average Mode Select 0 0 read-write 0 Temperature sensor output A/D-converted value addition/average mode is not selected. #0 1 Temperature sensor output A/D-converted value addition/average mode is selected. #1 ADANSB0 A/D Channel Select Register B0 0x014 16 read-write 0x0000 0xFFFF Reserved This bit is read as 0. The write value should be 0. 15 15 read-write ANSB14 AN014 Select 14 14 read-write 0 AN014 is not subjected to conversion. #0 1 AN014 is subjected to conversion. #1 ANSB13 AN013 Select 13 13 read-write 0 AN013 is not subjected to conversion. #0 1 AN013 is subjected to conversion. #1 ANSB12 AN012 Select 12 12 read-write 0 AN012 is not subjected to conversion. #0 1 AN012 is subjected to conversion. #1 ANSB11 AN011 Select 11 11 read-write 0 AN011 is not subjected to conversion. #0 1 AN011 is subjected to conversion. #1 ANSB10 AN010 Select 10 10 read-write 0 AN010 is not subjected to conversion. #0 1 AN010 is subjected to conversion. #1 ANSB09 AN009 Select 9 9 read-write 0 AN009 is not subjected to conversion. #0 1 AN009 is subjected to conversion. #1 ANSB08 AN008 Select 8 8 read-write 0 AN008 is not subjected to conversion. #0 1 AN008 is subjected to conversion. #1 ANSB07 AN007 Select 7 7 read-write 0 AN007 is not subjected to conversion. #0 1 AN007 is subjected to conversion. #1 ANSB06 AN006 Select 6 6 read-write 0 AN006 is not subjected to conversion. #0 1 AN006 is subjected to conversion. #1 ANSB05 AN005 Select 5 5 read-write 0 AN005 is not subjected to conversion. #0 1 AN005 is subjected to conversion. #1 ANSB04 AN004 Select 4 4 read-write 0 AN004 is not subjected to conversion. #0 1 AN004 is subjected to conversion. #1 ANSB03 AN003 Select 3 3 read-write 0 AN003 is not subjected to conversion. #0 1 AN003 is subjected to conversion. #1 ANSB02 AN002 Select 2 2 read-write 0 AN002 is not subjected to conversion. #0 1 AN002 is subjected to conversion. #1 ANSB01 AN001 Select 1 1 read-write 0 AN001 is not subjected to conversion. #0 1 AN001 is subjected to conversion. #1 ANSB00 AN000 Select 0 0 read-write 0 AN000 is not subjected to conversion. #0 1 AN000 is subjected to conversion. #1 ADANSB1 A/D Channel Select Register B1 0x016 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000. The write value should be 000000. 10 15 read-write ANSB25 AN025 Select 9 9 read-write 0 AN025 is not subjected to conversion. #0 1 AN025 is subjected to conversion. #1 ANSB24 AN024 Select 8 8 read-write 0 AN024 is not subjected to conversion. #0 1 AN024 is subjected to conversion. #1 ANSB23 AN023 Select 7 7 read-write 0 AN023 is not subjected to conversion. #0 1 AN023 is subjected to conversion. #1 ANSB22 AN022 Select 6 6 read-write 0 AN022 is not subjected to conversion. #0 1 AN022 is subjected to conversion. #1 ANSB21 AN021 Select 5 5 read-write 0 AN021 is not subjected to conversion. #0 1 AN021 is subjected to conversion. #1 ANSB20 AN020 Select 4 4 read-write 0 AN020 is not subjected to conversion. #0 1 AN020 is subjected to conversion. #1 ANSB19 AN019 Select 3 3 read-write 0 AN019 is not subjected to conversion. #0 1 AN019 is subjected to conversion. #1 ANSB18 AN018 Select 2 2 read-write 0 AN018 is not subjected to conversion. #0 1 AN018 is subjected to conversion. #1 ANSB17 AN017 Select 1 1 read-write 0 AN017 is not subjected to conversion. #0 1 AN017 is subjected to conversion. #1 ANSB16 AN016 Select 0 0 read-write 0 AN016 is not subjected to conversion. #0 1 AN016 is subjected to conversion. #1 ADDBLDR A/D Data Duplication Register 0x018 16 read-only 0x0000 0xFFFF ADDBLDR This is a 16-bit read-only register for storing the result of A/D conversion in response to the second trigger in double trigger mode. 0 15 read-only ADTSDR A/D Temperature Sensor Data Register 0x01A 16 read-only 0x0000 0xFFFF ADTSDR This is a 16-bit read-only register for storing the A/D conversion result of temperature sensor output. 0 15 read-only ADOCDR A/D Internal Reference Voltage Data Register 0x01C 16 read-only 0x0000 0xFFFF ADOCDR This is a 16-bit read-only register for storing the A/D result of internal reference voltage. 0 15 read-only ADRD A/D Self-Diagnosis Data Register 0x01E 16 read-only 0x0000 0xFFFF DIAGST Self-Diagnosis Status 14 15 read-only 00 Self-diagnosis has never been executed since power-on. #00 01 Self-diagnosis using the voltage of 0 V has been executed. #01 10 Self-diagnosis using the voltage of reference power supply(VREFH) x 1/2 has been executed. #10 11 Self-diagnosis using the voltage of reference power supply(VREFH) has been executed. #11 AD A/D-converted value (right-justified) The format for data determine ADCER.ADRFMT and ADCER.ADPRC. 0 13 read-only 15 0x2 0-14 ADDR%s A/D Data Register %s 0x020 16 read-only 0x0000 0xFFFF ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only 10 0x2 16-25 ADDR%s A/D Data Register %s 0x040 16 read-only 0x0000 0xFFFF ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDISCR A/D Disconnection Detection Control Register 0x07A 8 read-write 0x00 0xFF Reserved These bits are read as 000. The write value should be 000. 5 7 read-write PCHG Selection of Precharge or Discharge 4 4 read-write 0 Discharge #0 1 Precharge #1 ADNDIS The charging time 0 3 read-write 0000 Disconnection detection is disabled #0000 0001 Setting prohibited #0001 others ( 1 / ADCLK ) x ADNDIS true ADGSPCR A/D Group Scan Priority Control Register 0x080 16 read-write 0x0000 0xFFFF GBRP Group B Single Scan Continuous Start (Enabled only when PGS = 1. Reserved when PGS = 0.) Note: When the GBRP bit has been set to 1, single scan is performed continuously for group B regardless of the setting of the GBRSCN bit. 15 15 read-write 0 Single scan for group B is not continuously activated. #0 1 Single scan for group B is continuously activated. #1 Reserved These bits are read as 000000. The write value should be 000000. 9 14 read-write Reserved This bit is read as 0. The write value should be 0. 8 8 read-write Reserved These bits are read as 000000. The write value should be 000000. 2 7 read-write GBRSCN Group B Restart Setting (Enabled only when PGS = 1. Reserved when PGS = 0.) 1 1 read-write 0 Scanning for group B is not restarted after having been discontinued due to group A priority control. #0 1 Scanning for group B is restarted after having been discontinued due to group A priority control. #1 PGS Group A priority control setting bit. Note: When the PGS bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be set to 01b (group scan mode). If the bits are set to any other values, proper operation is not guaranteed. 0 0 read-write 0 Operation is without group A priority control #0 1 Operation is with group A priority control #1 ADDBLDRA A/D Data Duplexing Register A 0x084 16 read-only 0x0000 0xFFFF ADDBLDRA This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode. 0 15 read-only ADDBLDRB A/D Data Duplexing Register B 0x086 16 read-only 0x0000 0xFFFF ADDBLDRB This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode. 0 15 read-only ADHVREFCNT A/D High-Potential/Low-Potential Reference Voltage Control Register 0x08A 8 read-write 0x00 0xFF ADSLP Sleep 7 7 read-write 0 Normal operation #0 1 Standby state. #1 Reserved These bits are read as 00. The write value should be 00. 5 6 read-write LVSEL Low-Potential Reference Voltage Select 2 4 read-write 0 AVSS0 is selected as the low-potential reference voltage #0 1 VREFL0 is selected as the low-potential reference voltage. #1 Reserved These bits are read as 00. The write value should be 00. 2 3 read-write HVSEL High-Potential Reference Voltage Select 0 1 read-write 00 AVCC0 is selected as the high-potential reference voltage #00 01 VREFH0 is selected as the high-potential reference voltage #01 10 Internal reference voltage is selected as the high-potential reference voltage #10 11 Internal node discharge. No reference voltage pin is selected. #11 ADWINMON A/D Compare Function Window A/B Status Monitor Register 0x08C 8 read-only 0x00 0xFF Reserved These bits are read as 00. 6 7 read-only MONCMPB Comparison Result Monitor B 5 5 read-only 0 Window B comparison conditions are not met. #0 1 Window B comparison conditions are met. #1 MONCMPA Comparison Result Monitor A 4 4 read-only 0 Window A comparison conditions are not met. #0 1 Window A comparison conditions are met. #1 Reserved These bits are read as 000. 1 3 read-only MONCOMB Combination result monitor This bit indicates the combination result. This bit is valid when both window A operation and window B operation are enabled. 0 0 read-only 0 Window A / window B composite conditions are not met. #0 1 Window A / window B composite conditions are met. #1 ADCMPCR A/D Compare Function Control Register 0x090 16 read-write 0x0000 0xFFFF CMPAIE Compare A Interrupt Enable 15 15 read-write 0 ADC140_CMPAI interrupt is disabled when comparison conditions (window A) are met. #0 1 ADC140_CMPAI interrupt is enabled when comparison conditions (window A) are met. #1 WCMPE Window Function Setting 14 14 read-write 0 Window function is disabled. Window A and window B operate as a comparator to comparator the single value on the lower side with the A/D conversion result. #0 1 Window function is enabled. Window A and window B operate as a comparator to comparator the two values on the upper and lower sides with the A/D conversion result. #1 CMPBIE Compare B Interrupt Enable 13 13 read-write 0 ADC140_CMPAI interrupt is disabled when comparison conditions (window B) are met. #0 1 ADC140_CMPAI interrupt is enabled when comparison conditions (window B) are met. #1 Reserved This bit is read as 0. The write value should be 0. 12 12 read-write CMPAE Compare Window A Operation Enable 11 11 read-write 0 Compare window A operation is disabled. ADC140_WCMPM and ADC140_WCMPUM outputs are disabled. #0 1 Compare window A operation is enabled. #1 Reserved This bit is read as 0. The write value should be 0. 10 10 read-write CMPBE Compare Window B Operation Enable 9 9 read-write 0 Compare window B operation is disabled. ADC140_WCMPM and ADC140_WCMPUM outputs are disabled. #0 1 Compare window B operation is enabled. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 2 8 read-write CMPAB Window A/B Composite Conditions Setting NOTE: These bits are valid when both window A and window B are enabled (CMPAE = 1 and CMPBE = 1). 0 1 read-write 00 ADC140_WCMPM is output when window A comparison conditions are met OR window B comparison conditions are met. ADC140_WCMPUM is output in other cases. #00 01 S14ADWMELC0 is output when window A comparison conditions are met EXOR window B comparison conditions are met. ADC140_WCMPUM is output in other cases. #01 10 ADC140_WCMPM is output when window A comparison conditions are met and window B comparison conditions are met. ADC140_WCMPUM is output in other cases. #10 11 Setting prohibited. #11 ADCMPANSER A/D Compare Function Window A Extended Input Select Register 0x092 8 read-write 0x00 0xFF Reserved These bits are read as 000000. The write value should be 000000. 2 7 read-write CMPOCA Internal reference voltage Compare selection bit. 1 1 read-write 0 Excludes the internal reference voltage from the compare window A target range. #0 1 Includes the internal reference voltage in the compare window A target range. #1 CMPTSA Temperature sensor output Compare selection bit. 0 0 read-write 0 Excludes the temperature sensor output from the compare window A target range. #0 1 Includes the temperature sensor output in the compare window A target range. #1 ADCMPLER A/D Compare Function Window A Extended Input Comparison Condition Setting Register 0x093 8 read-write 0x00 0xFF Reserved These bits are read as 000000. The write value should be 000000. 2 7 read-write CMPLOCA Compare Window A Internal Reference Voltage Comparison Condition Select 1 1 read-write 0 ADCMPDR0 value > A/D converted value(ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or A/D converted value > ADCMPDR1 value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 value < A/D converted value < ADCMPDR1 value(ADCMPCR.WCMPE=1) #1 CMPLTSA Compare Window A Temperature Sensor Output Comparison Condition Select 0 0 read-write 0 ADCMPDR0 register value > A/D-converted value(ADCMPCR.WCMPE=0) / AD-converted value < ADCMPDR0 register value or A/D-converted value > ADCMPDR1 register value(ADCMPCR.WCMPE=1). #0 1 ADCMPDR0 register value < A/D-converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 register value < A/D-converted value < ADCMPDR1 register value(ADCMPCR.WCMPE=1). #1 ADCMPANSR0 A/D Compare Function Window A Channel Select Register 0 0x094 16 read-write 0x0000 0xFFFF Reserved This bit is read as 0. The write value should be 0. 15 15 read-write CMPCHA14 AN014 Select 14 14 read-write 0 Excludes AN014 from the compare window A target range. #0 1 Includes AN014 from the compare window A target range. #1 CMPCHA13 AN013 Select 13 13 read-write 0 Excludes AN013 from the compare window A target range. #0 1 Includes AN013 from the compare window A target range. #1 CMPCHA12 AN012 Select 12 12 read-write 0 Excludes AN012 from the compare window A target range. #0 1 Includes AN012 from the compare window A target range. #1 CMPCHA11 AN011 Select 11 11 read-write 0 Excludes AN011 from the compare window A target range. #0 1 Includes AN011 from the compare window A target range. #1 CMPCHA10 AN010 Select 10 10 read-write 0 Excludes AN010 from the compare window A target range. #0 1 Includes AN010 from the compare window A target range. #1 CMPCHA09 AN009 Select 9 9 read-write 0 Excludes AN009 from the compare window A target range. #0 1 Includes AN009 from the compare window A target range. #1 CMPCHA08 AN008 Select 8 8 read-write 0 Excludes AN008 from the compare window A target range. #0 1 Includes AN008 from the compare window A target range. #1 CMPCHA07 AN007 Select 7 7 read-write 0 Excludes AN007 from the compare window A target range. #0 1 Includes AN007 from the compare window A target range. #1 CMPCHA06 AN006 Select 6 6 read-write 0 Excludes AN006 from the compare window A target range. #0 1 Includes AN006 from the compare window A target range. #1 CMPCHA05 AN005 Select 5 5 read-write 0 Excludes AN005 from the compare window A target range. #0 1 Includes AN005 from the compare window A target range. #1 CMPCHA04 AN004 Select 4 4 read-write 0 Excludes AN004 from the compare window A target range. #0 1 Includes AN004 from the compare window A target range. #1 CMPCHA03 AN003 Select 3 3 read-write 0 Excludes AN003 from the compare window A target range. #0 1 Includes AN003 from the compare window A target range. #1 CMPCHA02 AN002 Select 2 2 read-write 0 Excludes AN002 from the compare window A target range. #0 1 Includes AN002 from the compare window A target range. #1 CMPCHA01 AN001 Select 1 1 read-write 0 Excludes AN001 from the compare window A target range. #0 1 Includes AN001 from the compare window A target range. #1 CMPCHA00 AN000 Select 0 0 read-write 0 Excludes AN000 from the compare window A target range. #0 1 Includes AN000 from the compare window A target range. #1 ADCMPANSR1 A/D Compare Function Window A Channel Select Register 1 0x096 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000. The write value should be 000000. 10 15 read-write CMPCHA25 AN025 Select 9 9 read-write 0 Excludes AN025 from the compare window A target range. #0 1 Includes AN025 from the compare window A target range. #1 CMPCHA24 AN024 Select 8 8 read-write 0 Excludes AN024 from the compare window A target range. #0 1 Includes AN024 from the compare window A target range. #1 CMPCHA23 AN023 Select 7 7 read-write 0 Excludes AN023 from the compare window A target range. #0 1 Includes AN023 from the compare window A target range. #1 CMPCHA22 AN022 Select 6 6 read-write 0 Excludes AN022 from the compare window A target range. #0 1 Includes AN022 from the compare window A target range. #1 CMPCHA21 AN021 Select 5 5 read-write 0 Excludes AN021 from the compare window A target range. #0 1 Includes AN021 from the compare window A target range. #1 CMPCHA20 AN020 Select 4 4 read-write 0 Excludes AN020 from the compare window A target range. #0 1 Includes AN020 from the compare window A target range. #1 CMPCHA19 AN019 Select 3 3 read-write 0 Excludes AN019 from the compare window A target range. #0 1 Includes AN019 from the compare window A target range. #1 CMPCHA18 AN018 Select 2 2 read-write 0 Excludes AN018 from the compare window A target range. #0 1 Includes AN018 from the compare window A target range. #1 CMPCHA17 AN017 Select 1 1 read-write 0 Excludes AN017 from the compare window A target range. #0 1 Includes AN017 from the compare window A target range. #1 CMPCHA16 AN016 Select 0 0 read-write 0 Excludes AN016 from the compare window A target range. #0 1 Includes AN016 from the compare window A target range. #1 ADCMPLR0 A/D Compare Function Window A Comparison Condition Setting Register 0 0x098 16 read-write 0x0000 0xFFFF Reserved This bit is read as 0. The write value should be 0. 15 15 read-write CMPLCHA14 Comparison condition of AN014 14 14 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA13 Comparison condition of AN013 13 13 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA12 Comparison condition of AN012 12 12 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA11 Comparison condition of AN011 11 11 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA10 Comparison condition of AN010 10 10 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA09 Comparison condition of AN009 9 9 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA08 Comparison condition of AN008 8 8 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA07 Comparison condition of AN007 7 7 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA06 Comparison condition of AN006 6 6 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA05 Comparison condition of AN005 5 5 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA04 Comparison condition of AN004 4 4 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA03 Comparison condition of AN003 3 3 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA02 Comparison condition of AN002 2 2 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA01 Comparison condition of AN001 1 1 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA00 Comparison condition of AN000 0 0 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 ADCMPLR1 A/D Compare Function Window A Comparison Condition Setting Register 1 0x09A 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000. The write value should be 000000. 10 15 read-write CMPLCHA25 Comparison condition of AN025 9 9 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA24 Comparison condition of AN024 8 8 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA23 Comparison condition of AN023 7 7 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA22 Comparison condition of AN022 6 6 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA21 Comparison condition of AN021 5 5 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA20 Comparison condition of AN020 4 4 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA19 Comparison condition of AN019 3 3 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA18 Comparison condition of AN018 2 2 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA17 Comparison condition of AN017 1 1 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA16 Comparison condition of AN016 0 0 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 ADCMPDR0 A/D Compare Function Window A Lower-Side Level Setting Register 0x09C 16 read-write 0x0000 0xFFFF ADCMPDR0 The ADCMPDR0 register sets the reference data when the compare window A function is used. ADCMPDR0 sets the lower-side level of window A. 0 15 read-write ADCMPDR1 A/D Compare Function Window A Upper-Side Level Setting Register 0x09E 16 read-write 0x0000 0xFFFF ADCMPDR1 The ADCMPDR1 register sets the reference data when the compare window A function is used. ADCMPDR1 sets the upper-side level of window A.. 0 15 read-write ADCMPSR0 A/D Compare Function Window A Channel Status Register 0 0x0A0 16 read-write 0x0000 0xFFFF Reserved This bit is read as 0. The write value should be 0. 15 15 read-write CMPSTCHA14 Compare window A flag of AN014 14 14 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA13 Compare window A flag of AN013 13 13 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA12 Compare window A flag of AN012 12 12 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA11 Compare window A flag of AN011 11 11 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA10 Compare window A flag of AN010 10 10 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA09 Compare window A flag of AN009 9 9 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA08 Compare window A flag of AN008 8 8 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA07 Compare window A flag of AN007 7 7 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA06 Compare window A flag of AN006 6 6 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA05 Compare window A flag of AN005 5 5 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA04 Compare window A flag of AN004 4 4 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA03 Compare window A flag of AN003 3 3 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA02 Compare window A flag of AN002 2 2 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA01 Compare window A flag of AN001 1 1 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA00 Compare window A flag of AN000 0 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPSR1 A/D Compare Function Window A Channel Status Register 1 0x0A2 16 read-write 0x0000 0xFFFF Reserved These bits are read as 000000. The write value should be 000000. 10 15 read-write CMPSTCHA25 Compare window A flag of AN025 9 9 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA24 Compare window A flag of AN024 8 8 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA23 Compare window A flag of AN023 7 7 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA22 Compare window A flag of AN022 6 6 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA21 Compare window A flag of AN021 5 5 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA20 Compare window A flag of AN020 4 4 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA19 Compare window A flag of AN019 3 3 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA18 Compare window A flag of AN018 2 2 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA17 Compare window A flag of AN017 1 1 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA16 Compare window A flag of AN016 0 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPSER A/D Compare Function Window A Extended Input Channel Status Register 0x0A4 8 read-write 0x00 0xFF Reserved These bits are read as 000000. The write value should be 000000. 2 7 read-write CMPSTOCA Compare Window A Internal Reference Voltage Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time. 1 1 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTTSA Compare Window A Temperature Sensor Output Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time. 0 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPBNSR A/D Compare Function Window B Channel Selection Register 0x0A6 8 read-write 0x00 0xFF CMPLB Compare window B Compare condition setting bit. 7 7 read-write 0 CMPLLB value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < CMPLLB value or CMPULB value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 CMPLLB value < A/D converted value(ADCMPCR.WCMPE=0) / CMPLLB value < A/D converted value < CMPULB value (ADCMPCR.WCMPE=1) #1 Reserved This bit is read as 0. The write value should be 0. 6 6 read-write CMPCHB Compare window B channel selection bit. The channel that compares it on the condition of compare window B is selected. 0 5 read-write 0x00 AN000 0x00 0x01 AN001 0x01 0x02 AN002 0x02 0x03 AN003 0x03 0x04 AN004 0x04 0x05 AN005 0x05 0x06 AN006 0x06 0x07 AN007 0x07 0x08 AN008 0x08 0x09 AN009 0x09 0x0A AN010 0x0A 0x0B AN011 0x0B 0x0C AN012 0x0C 0x0D AN013 0x0D 0x0E AN014 0x0E 0x0F AN015 0x0F 0x10 AN016 0x10 0x11 AN017 0x11 0x12 AN018 0x12 0x13 AN019 0x13 0x14 AN020 0x14 0x15 AN021 0x15 0x16 AN022 0x16 0x17 AN023 0x17 0x18 AN024 0x18 0x19 AN025 0x19 0x1A AN026 0x1A 0x1B AN027 0x1B 0x20 Temperature sensor 0x20 0x21 Internal reference voltage 0x21 0x3F No channel is selected 0x3F others Setting prohibited true ADWINLLB A/D Compare Function Window B Lower-Side Level Setting Register 0x0A8 16 read-write 0x0000 0xFFFF ADWINLLB This register is used to compare A window function is used to set the lower level of the window B. 0 15 read-write ADWINULB A/D Compare Function Window B Upper-Side Level Setting Register 0x0AA 16 read-write 0x0000 0xFFFF ADWINULB This register is used to compare A window function is used to set the higher level of the window B. 0 15 read-write ADCMPBSR A/D Compare Function Window B Status Register 0x0AC 8 read-write 0x00 0xFF Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write CMPSTB Compare window B flag. It is a status flag that shows the comparative result of CH (AN000-AN027, temperature sensor, and internal reference voltage) made the object of window B relation condition. 0 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADSSTRL A/D Sampling State Register L 0x0DD 8 read-write 0x0D 0xFF SST Sampling Time Setting (AN016-AN027) 0 7 read-write 0x05 0xFF ADSSTRT A/D Sampling State Register T 0x0DE 8 read-write 0x0D 0xFF SST Sampling Time Setting (temperature sensor output) 0 7 read-write 0x05 0xFF ADSSTRO A/D Sampling State Register O 0x0DF 8 read-write 0x0D 0xFF SST Sampling Time Setting (Internal reference voltage) 0 7 read-write 0x05 0xFF 15 0x1 0-14 ADSSTR%s A/D Sampling State Register %s 0x0E0 8 read-write 0x0D 0xFF SST Sampling time setting 0 7 read-write 0x05 0xFF AGT0 Asynchronous General purpose Timer 0 0x40084000 0x00 6 registers 0x08 3 registers 0x0C 4 registers AGT AGT Counter Register 0x00 16 read-write 0xFFFF 0xFFFF AGT 16bit counter and reload register NOTE : When 1 is written to the TSTOP bit in the AGTCRn register, the 16-bit counter is forcibly stopped and set to FFFFH. 0 15 read-write AGTCMA AGT Compare Match A Register 0x02 16 read-write 0xFFFF 0xFFFF AGTCMA AGT Compare Match A data is stored. NOTE : When 1 is written to the TSTOP bit in the AGTCRn register, set to FFFFH 0 15 read-write AGTCMB AGT Compare Match B Register 0x04 16 read-write 0xFFFF 0xFFFF AGTCMB AGT Compare Match B data is stored. NOTE : When 1 is written to the TSTOP bit in the AGTCR register, set to FFFFH 0 15 read-write AGTCR AGT Control Register 0x08 8 read-write 0x00 0xFF TCMBF Compare match B flag 7 7 read-write zeroToClear modify 0 No match #0 1 Match. #1 TCMAF Compare match A flag 6 6 read-write zeroToClear modify 0 No match #0 1 Match. #1 TUNDF Underflow flag 5 5 read-write zeroToClear modify 0 No match #0 1 Match. #1 TEDGF Active edge judgment flag 4 4 read-write zeroToClear modify 0 No active edge received #0 1 Active edge received. #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write TSTOP AGT count forced stop 2 2 write-only 0 Writing is invalid #0 1 The count is forcibly stopped. #1 TCSTF AGT count status flag 1 1 read-only 0 Count stops #0 1 Count in progress. #1 TSTART AGT count start 0 0 read-write 0 Count stops #0 1 Count starts. #1 AGTMR1 AGT Mode Register 1 0x09 8 read-write 0x00 0xFF Reserved This bit is read as 0. The write value should be 0. 7 7 read-write TCK Count source 4 6 read-write 000 PCLKB #000 001 PCLKB/8 #001 011 PCLKB/2 #011 100 Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register #100 101 Underflow event signal from AGT0*6 #101 110 Divided clock AGTSCLK specified by CKS[2:0] bits in the AGTMR2 register. #110 others settings are prohibited. true TEDGPL Edge polarity 3 3 read-write 0 Single-edge #0 1 Both-edge. #1 TMOD Operating mode 0 2 read-write 000 Timer mode #000 001 Pulse output mode #001 010 Event counter mode #010 011 Pulse width measurement mode #011 100 Pulse period measurement mode. #100 others settings are prohibited true AGTMR2 AGT Mode Register 2 0x0A 8 read-write 0x00 0xFF LPM Low Power Mode 7 7 read-write 0 Normal mode #0 1 Low Power mode #1 Reserved These bits are read as 0000. The write value should be 0000. 3 6 read-write CKS AGTLCLK/AGTSCLK count source clock frequency division ratio 0 2 read-write 000 1/1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 111 1/128. #111 AGTIOC AGT I/O Control Register 0x0C 8 read-write 0x00 0xFF TIOGT Count control 6 7 read-write 00 Event is always counted #00 01 Event is counted during polarity period specified for AGTEEn. #01 others settings are prohibited. true TIPF Input filter 4 5 read-write 00 No filter #00 01 Filter sampled at PCLKB #01 10 Filter sampled at PCLKB/8 #10 11 Filter sampled at PCLKB/32 #11 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write TOE AGTOn output enable 2 2 read-write 0 AGTOn output disabled #0 1 AGTOn output enabled. #1 Reserved This bit is read as 0. The write value should be 0. 1 1 read-write TEDGSEL I/O polarity switch Function varies depending on the operating mode. 0 0 read-write AGTISR AGT Event Pin Select Register 0x0D 8 read-write 0x00 0xFF Reserved These bits are read as 00000. The write value should be 00000. 3 7 read-write EEPS AGTEE polarty selection 2 2 read-write 0 An event is counted during the low-level period #0 1 An event is counted during the high-level period #1 Reserved These bits are read as 00. The write value should be 00. 0 1 read-write AGTCMSR AGT Compare Match Function Select Register 0x0E 8 read-write 0x00 0xFF Reserved This bit is read as 0. The write value should be 0. 7 7 read-write TOPOLB AGTOB polarity select 6 6 read-write 0 AGTOB Output is started at low #0 1 AGTOB Output is started at high #1 TOEB AGTOB output enable 5 5 read-write 0 AGTOB output disabled (port) #0 1 AGTOB output enabled #1 TCMEB Compare match B register enable 4 4 read-write 0 Disable compare match B register #0 1 Enable compare match B register #1 Reserved This bit is read as 0. The write value should be 0. 3 3 read-write TOPOLA AGTOA polarity select 2 2 read-write 0 AGTOA Output is started at low #0 1 AGTOA Output is started at high #1 TOEA AGTOA output enable 1 1 read-write 0 AGTOA output disabled (port) #0 1 AGTOA output enabled #1 TCMEA Compare match A register enable 0 0 read-write 0 Disable compare match A register #0 1 Enable compare match A register #1 AGTIOSEL AGT Pin Select Register 0x0F 8 read-write 0x00 0xFF Reserved These bits are read as 000. The write value should be 000. 5 7 read-write TIES AGTIO input enable 4 4 read-write 0 External event input is disabled during Software Standby mode #0 1 External event input is enabled during Software Standby mode. #1 Reserved These bits are read as 00. The write value should be 00. 2 3 read-write SEL AGTIO pin select 0 1 read-write 00 Select the AGTIOn except for below pins #00 01 Setting prohibited #01 10 Select the P402/AGTIOn. P402/AGTIOn is input only. It is not possible to output #10 11 Select the P403/AGTIOn. P403/AGTIOn is input only. It is not possible to output #11 AGT1 Asynchronous General purpose Timer 1 0x40084100 GPT320 General PWM Timer 0 (32-bit) 0x40078000 0x00 116 registers 0x7C 4 registers 0x74 4 registers 0x80 4 registers 0x78 4 registers 0x84 32 registers GTWP General PWM Timer Write-Protection Register 0x00 32 read-write 0x00000000 0xFFFFFFFF Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 31 read-write PRKEY GTWP Key Code 8 15 write-only 0xA5 Written to these bits, the WP bits write is permitted. 0xA5 others The WP bits write is not permitted. true Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write WP Register Write Disable 0 0 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 GTSTR General PWM Timer Software Start Register 0x04 32 read-write 0x00000000 0xFFFFFFFF Reserved These bits are read as 000000000000000000000000. The write value should be 000000000000000000000000. 8 31 read-write CSTRT7 Channel 7 GTCNT Count Start Read data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 7 7 read-write 0 No effect (write) / counter stop (read) #0 1 GPT167.GTCNT counter starts (write) / Counter running (read) #1 CSTRT6 Channel 6 GTCNT Count Start Read data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 6 6 read-write 0 No effect (write) / counter stop (read) #0 1 GPT166.GTCNT counter starts (write) / Counter running (read) #1 CSTRT5 Channel 5 GTCNT Count Start Read data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 5 5 read-write 0 No effect (write) / counter stop (read) #0 1 GPT165.GTCNT counter starts (write) / Counter running (read) #1 CSTRT4 Channel 4 GTCNT Count Start Read data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 4 4 read-write 0 No effect (write) / counter stop (read) #0 1 GPT164.GTCNT counter starts (write) / Counter running (read) #1 CSTRT3 Channel 3 GTCNT Count Start Read data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 3 3 read-write 0 No effect (write) / counter stop (read) #0 1 GPT323.GTCNT counter starts (write) / Counter running (read) #1 CSTRT2 Channel 2 GTCNT Count Start Read data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 2 2 read-write 0 No effect (write) / counter stop (read) #0 1 GPT322.GTCNT counter starts (write) / Counter running (read) #1 CSTRT1 Channel 1 GTCNT Count Start Read data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 1 1 read-write 0 No effect (write) / counter stop (read) #0 1 GPT321.GTCNT counter starts (write) / Counter running (read) #1 CSTRT0 Channel 0 GTCNT Count Start Read data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 0 0 read-write 0 No effect (write) / counter stop (read) #0 1 GPT320.GTCNT counter starts (write) / Counter running (read) #1 GTSTP General PWM Timer Software Stop Register 0x08 32 read-write 0xFFFFFFFF 0xFFFFFFFF Reserved These bits are read as 111111111111111111111111. The write value should be 111111111111111111111111. 8 31 read-write CSTOP7 Channel 7 GTCNT Count Stop Read data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 7 7 read-write 0 No effect (write) / counter running (read) #0 1 GPT167.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP6 Channel 6 GTCNT Count Stop Read data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 6 6 read-write 0 No effect (write) / counter running (read) #0 1 GPT166.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP5 Channel 5 GTCNT Count Stop Read data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 5 5 read-write 0 No effect (write) / counter running (read) #0 1 GPT165.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP4 Channel 4 GTCNT Count Stop Read data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 4 4 read-write 0 No effect (write) / counter running (read) #0 1 GPT164.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP3 Channel 3 GTCNT Count Stop Read data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 3 3 read-write 0 No effect (write) / counter running (read) #0 1 GPT323.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP2 Channel 2 GTCNT Count Stop Read data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 2 2 read-write 0 No effect (write) / counter running (read) #0 1 GPT322.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP1 Channel 1 GTCNT Count Stop Read data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 1 1 read-write 0 No effect (write) / counter running (read) #0 1 GPT321.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP0 Channel 0 GTCNT Count Stop Read data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 0 0 read-write 0 No effect (write) / counter running (read) #0 1 GPT320.GTCNT counter stops (write) / Counter stop (read) #1 GTCLR General PWM Timer Software Clear Register 0x0C 32 write-only 0x00000000 0xFFFFFFFF Reserved The write value should be 000000000000000000000000. 8 31 write-only CCLR7 Channel 7 GTCNT Count Clear 7 7 write-only 0 No effect #0 1 GPT167.GTCNT counter clears #1 CCLR6 Channel 6 GTCNT Count Clear 6 6 write-only 0 No effect #0 1 GPT166.GTCNT counter clears #1 CCLR5 Channel 5 GTCNT Count Clear 5 5 write-only 0 No effect #0 1 GPT165.GTCNT counter clears #1 CCLR4 Channel 4 GTCNT Count Clear 4 4 write-only 0 No effect #0 1 GPT164.GTCNT counter clears #1 CCLR3 Channel 3 GTCNT Count Clear 3 3 write-only 0 No effect #0 1 GPT323.GTCNT counter clears #1 CCLR2 Channel 2 GTCNT Count Clear 2 2 write-only 0 No effect #0 1 GPT322.GTCNT counter clears #1 CCLR1 Channel 1 GTCNT Count Clear 1 1 write-only 0 No effect #0 1 GPT321.GTCNT counter clears #1 CCLR0 Channel 0 GTCNT Count Clear 0 0 write-only 0 No effect #0 1 GPT320.GTCNT counter clears #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write 0x00000000 0xFFFFFFFF CSTRT Software Source Counter Start Enable 31 31 read-write 0 Counter start is disable by the GTSTR register #0 1 Counter start is enable by the GTSTR register #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 30 read-write SSELCH ELCH Event Source Counter Start Enable 23 23 read-write 0 Counter start is disable at the ELC_GPTH input #0 1 Counter start is enable at the ELC_GPTH input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 22 read-write 0 Counter start is disable at the ELC_GPTG input #0 1 Counter start is enable at the ELC_GPTG input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 21 read-write 0 Counter start is disable at the ELC_GPTF input #0 1 Counter start is enable at the ELC_GPTF input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 20 read-write 0 Counter start is disable at the ELC_GPTE input #0 1 Counter start is enable at the ELC_GPTE input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 19 read-write 0 Counter start is disable at the ELC_GPTD input #0 1 Counter start is enable at the ELC_GPTD input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 18 read-write 0 Counter start is disable at the ELC_GPTC input #0 1 Counter start is enable at the ELC_GPTC input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 17 read-write 0 Counter start is disable at the ELC_GPTB input #0 1 Counter start is enable at the ELC_GPTB input #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 16 read-write 0 Counter start is disable at the ELC_GPTA input #0 1 Counter start is enable at the ELC_GPTA input #1 SSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable 15 15 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 SSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable 14 14 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 SSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable 13 13 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 SSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable 12 12 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 SSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable 11 11 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 SSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable 10 10 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 SSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable 9 9 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 SSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable 8 8 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 Reserved These bits are read as 0000. The write value should be 0000. 4 7 read-write SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 3 read-write 0 Counter start is disable at the falling edge of GTETRGB input #0 1 Counter start is enable at the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 2 read-write 0 Counter start is disable at the rising edge of GTETRGB input #0 1 Counter start is enable at the rising edge of GTETRGB input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 1 read-write 0 Counter start is disable at the falling edge of GTETRGA input #0 1 Counter start is enable at the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 0 read-write 0 Counter start is disable at the rising edge of GTETRGA input #0 1 Counter start is enable at the rising edge of GTETRGA input #1 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write 0x00000000 0xFFFFFFFF CSTOP Software Source Counter Stop Enable 31 31 read-write 0 Counter stop is disable by the GTSTP register #0 1 Counter stop is enable by the GTSTP register #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 30 read-write PSELCH ELCH Event Source Counter Stop Enable 23 23 read-write 0 Counter stop is disable at the ELC_GPTH input #0 1 Counter stop is enable at the ELC_GPTH input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 22 read-write 0 Counter stop is disable at the ELC_GPTG input #0 1 Counter stop is enable at the ELC_GPTG input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 21 read-write 0 Counter stop is disable at the ELC_GPTF input #0 1 Counter stop is enable at the ELC_GPTF input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 20 read-write 0 Counter stop is disable at the ELC_GPTE input #0 1 Counter stop is enable at the ELC_GPTE input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 19 read-write 0 Counter stop is disable at the ELC_GPTD input #0 1 Counter stop is enable at the ELC_GPTD input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 18 read-write 0 Counter stop is disable at the ELC_GPTC input #0 1 Counter stop is enable at the ELC_GPTC input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 17 read-write 0 Counter stop is disable at the ELC_GPTB input #0 1 Counter stop is enable at the ELC_GPTB input #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 16 read-write 0 Counter stop is disable at the ELC_GPTA input #0 1 Counter stop is enable at the ELC_GPTA input #1 PSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable 15 15 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 PSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable 14 14 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 PSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable 13 13 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 PSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable 12 12 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 PSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable 11 11 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 PSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable 10 10 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 PSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable 9 9 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 PSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable 8 8 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 Reserved These bits are read as 0000. The write value should be 0000. 4 7 read-write PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 3 read-write 0 Counter stop is disable at the falling edge of GTETRGB input #0 1 Counter stop is enable at the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 2 read-write 0 Counter stop is disable at the rising edge of GTETRGB input #0 1 Counter stop is enable at the rising edge of GTETRGB input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 1 read-write 0 Counter stop is disable at the falling edge of GTETRGA input #0 1 Counter stop is enable at the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 0 read-write 0 Counter stop is disable at the rising edge of GTETRGA input #0 1 Counter stop is enable at the rising edge of GTETRGA input #1 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write 0x00000000 0xFFFFFFFF CCLR Software Source Counter Clear Enable 31 31 read-write 0 Counter clear is disable by the GTCLR register #0 1 Counter clear is enable by the GTCLR register #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 30 read-write CSELCH ELCH Event Source Counter Clear Enable 23 23 read-write 0 Counter clear is disable at the ELC_GPTH input #0 1 Counter clear is enable at the ELC_GPTH input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 22 read-write 0 Counter clear is disable at the ELC_GPTG input #0 1 Counter clear is enable at the ELC_GPTG input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 21 read-write 0 Counter clear is disable at the ELC_GPTF input #0 1 Counter clear is enable at the ELC_GPTF input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 20 read-write 0 Counter clear is disable at the ELC_GPTE input #0 1 Counter clear is enable at the ELC_GPTE input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 19 read-write 0 Counter clear is disable at the ELC_GPTD input #0 1 Counter clear is enable at the ELC_GPTD input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 18 read-write 0 Counter clear is disable at the ELC_GPTC input #0 1 Counter clear is enable at the ELC_GPTC input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 17 read-write 0 Counter clear is disable at the ELC_GPTB input #0 1 Counter clear is enable at the ELC_GPTB input #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 16 read-write 0 Counter clear is disable at the ELC_GPTA input #0 1 Counter clear is enable at the ELC_GPTA input #1 CSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable 15 15 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 CSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable 14 14 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 CSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable 13 13 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 CSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable 12 12 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 CSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable 11 11 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 CSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable 10 10 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 CSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable 9 9 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 CSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable 8 8 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 Reserved These bits are read as 0000. The write value should be 0000. 4 7 read-write CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 3 read-write 0 Counter clear is disable at the falling edge of GTETRGB input #0 1 Counter clear is enable at the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 2 read-write 0 Counter clear is disable at the rising edge of GTETRGB input #0 1 Counter clear is enable at the rising edge of GTETRGB input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 1 read-write 0 Counter clear is disable at the falling edge of GTETRGA input #0 1 Counter clear is enable at the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 0 read-write 0 Counter clear is disable at the rising edge of GTETRGA input #0 1 Counter clear is enable at the rising edge of GTETRGA input #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write 0x00000000 0xFFFFFFFF USELCH ELCH Event Source Counter Count Up Enable 23 23 read-write 0 Counter count up is disable at the ELC_GPTH input #0 1 Counter count up is enable at the ELC_GPTH input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 22 read-write 0 Counter count up is disable at the ELC_GPTG input #0 1 Counter count up is enable at the ELC_GPTG input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 21 read-write 0 Counter count up is disable at the ELC_GPTF input #0 1 Counter count up is enable at the ELC_GPTF input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 20 read-write 0 Counter count up is disable at the ELC_GPTE input #0 1 Counter count up is enable at the ELC_GPTE input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 19 read-write 0 Counter count up is disable at the ELC_GPTD input #0 1 Counter count up is enable at the ELC_GPTD input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 18 read-write 0 Counter count up is disable at the ELC_GPTC input #0 1 Counter count up is enable at the ELC_GPTC input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 17 read-write 0 Counter count up is disable at the ELC_GPTB input #0 1 Counter count up is enable at the ELC_GPTB input #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 16 read-write 0 Counter count up is disable at the ELC_GPTA input #0 1 Counter count up is enable at the ELC_GPTA input #1 USCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable 15 15 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 USCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable 14 14 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 USCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable 13 13 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 USCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable 12 12 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 USCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable 11 11 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 USCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable 10 10 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 USCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable 9 9 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 USCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable 8 8 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 3 read-write 0 Counter count up is disable at the falling edge of GTETRGB input #0 1 Counter count up is enable at the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 2 read-write 0 Counter count up is disable at the rising edge of GTETRGB input #0 1 Counter count up is enable at the rising edge of GTETRGB input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 1 read-write 0 Counter count up is disable at the falling edge of GTETRGA input #0 1 Counter count up is enable at the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 0 read-write 0 Counter count up is disable at the rising edge of GTETRGA input #0 1 Counter count up is enable at the rising edge of GTETRGA input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write 0x00000000 0xFFFFFFFF DSELCH ELCH Event Source Counter Count Down Enable 23 23 read-write 0 Counter count down is disable at the ELC_GPTH input #0 1 Counter count down is enable at the ELC_GPTH input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 22 read-write 0 Counter count down is disable at the ELC_GPTG input #0 1 Counter count down is enable at the ELC_GPTG input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 21 read-write 0 Counter count down is disable at the ELC_GPTF input #0 1 Counter count down is enable at the ELC_GPTF input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 20 read-write 0 Counter count down is disable at the ELC_GPTE input #0 1 Counter count down is enable at the ELC_GPTE input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 19 read-write 0 Counter count down is disable at the ELC_GPTD input #0 1 Counter count down is enable at the ELC_GPTD input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 18 read-write 0 Counter count down is disable at the ELC_GPTC input #0 1 Counter count down is enable at the ELC_GPTC input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 17 read-write 0 Counter count down is disable at the ELC_GPTB input #0 1 Counter count down is enable at the ELC_GPTB input #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 16 read-write 0 Counter count down is disable at the ELC_GPTA input #0 1 Counter count down is enable at the ELC_GPTA input #1 DSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable 15 15 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 DSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable 14 14 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 DSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable 13 13 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 DSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable 12 12 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 DSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable 11 11 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 DSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable 10 10 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 DSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable 9 9 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 DSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable 8 8 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 3 read-write 0 Counter count down is disable at the falling edge of GTETRGB input #0 1 Counter count down is enable at the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 2 read-write 0 Counter count down is disable at the rising edge of GTETRGB input #0 1 Counter count down is enable at the rising edge of GTETRGB input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 1 read-write 0 Counter count down is disable at the falling edge of GTETRGA input #0 1 Counter count down is enable at the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 0 read-write 0 Counter count down is disable at the rising edge of GTETRGA input #0 1 Counter count down is enable at the rising edge of GTETRGA input #1 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write 0x00000000 0xFFFFFFFF ASELCH ELCH Event Source GTCCRA Input Capture Enable 23 23 read-write 0 GTCCRA input capture is disable at the ELC_GPTH input #0 1 GTCCRA input capture is enable at the ELC_GPTH input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 22 read-write 0 GTCCRA input capture is disable at the ELC_GPTG input #0 1 GTCCRA input capture is enable at the ELC_GPTG input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 21 read-write 0 GTCCRA input capture is disable at the ELC_GPTF input #0 1 GTCCRA input capture is enable at the ELC_GPTF input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 20 read-write 0 GTCCRA input capture is disable at the ELC_GPTE input #0 1 GTCCRA input capture is enable at the ELC_GPTE input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 19 read-write 0 GTCCRA input capture is disable at the ELC_GPTD input #0 1 GTCCRA input capture is enable at the ELC_GPTD input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 18 read-write 0 GTCCRA input capture is disable at the ELC_GPTC input #0 1 GTCCRA input capture is enable at the ELC_GPTC input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 17 read-write 0 GTCCRA input capture is disable at the ELC_GPTB input #0 1 GTCCRA input capture is enable at the ELC_GPTB input #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 16 read-write 0 GTCCRA input capture is disable at the ELC_GPTA input #0 1 GTCCRA input capture is enable at the ELC_GPTA input #1 ASCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable 15 15 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 ASCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 14 14 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 ASCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable 13 13 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 ASCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 12 12 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 ASCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable 11 11 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 ASCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 10 10 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 ASCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable 9 9 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 ASCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 8 8 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 3 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 2 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGB input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 1 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 0 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGA input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write 0x00000000 0xFFFFFFFF BSELCH ELCH Event Source GTCCRB Input Capture Enable 23 23 read-write 0 GTCCRB input capture is disable at the ELC_GPTH input #0 1 GTCCRB input capture is enable at the ELC_GPTH input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 22 read-write 0 GTCCRB input capture is disable at the ELC_GPTG input #0 1 GTCCRB input capture is enable at the ELC_GPTG input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 21 read-write 0 GTCCRB input capture is disable at the ELC_GPTF input #0 1 GTCCRB input capture is enable at the ELC_GPTF input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 20 read-write 0 GTCCRB input capture is disable at the ELC_GPTE input #0 1 GTCCRB input capture is enable at the ELC_GPTE input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 19 read-write 0 GTCCRB input capture is disable at the ELC_GPTD input #0 1 GTCCRB input capture is enable at the ELC_GPTD input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 18 read-write 0 GTCCRB input capture is disable at the ELC_GPTC input #0 1 GTCCRB input capture is enable at the ELC_GPTC input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 17 read-write 0 GTCCRB input capture is disable at the ELC_GPTB input #0 1 GTCCRB input capture is enable at the ELC_GPTB input #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 16 read-write 0 GTCCRB input capture is disable at the ELC_GPTA input #0 1 GTCCRB input capture is enable at the ELC_GPTA input #1 BSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable 15 15 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 BSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 14 14 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 BSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable 13 13 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 BSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 12 12 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 BSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable 11 11 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 BSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 10 10 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 BSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable 9 9 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 BSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 8 8 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 3 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 2 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGB input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 1 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 0 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGA input #1 GTCR General PWM Timer Control Register 0x2C 32 read-write 0x00000000 0xFFFFFFFF TPCS Timer Prescaler Select 24 26 read-write 000 PCLK/1 #000 001 PCLK/4 #001 010 PCLK/16 #010 011 PCLK/64 #011 100 PCLK/256 #100 101 PCLK/1024 #101 others Setting prohibied true Reserved These bits are read as 00000. The write value should be 00000. 19 23 read-write MD Mode Select 16 18 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible) #100 101 Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible) #101 110 Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation) #110 111 Setting prohibited #111 Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 1 15 read-write CST Count Start 0 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write 0x00000001 0xFFFFFFFF OBDTYR GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 27 27 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #1 OBDTYF Forcible GTIOCB Output Duty Setting 26 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTY GTIOCB Output Duty Setting 24 25 read-write 00 GTIOCB pin duty is depend on compare match #00 01 GTIOCB pin duty is depend on compare match #01 10 GTIOCB pin duty 0 percent #10 11 GTIOCB pin duty 100 percent #11 Reserved These bits are read as 0000. The write value should be 0000. 20 23 read-write OADTYR GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 19 19 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #1 OADTYF Forcible GTIOCA Output Duty Setting 18 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTY GTIOCA Output Duty Setting 16 17 read-write 00 GTIOCA pin duty is depend on compare match #00 01 GTIOCA pin duty is depend on compare match #01 10 GTIOCA pin duty 0 percent #10 11 GTIOCA pin duty 100 percent #11 UDF Forcible Count Direction Setting 1 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 UD Count Direction Setting 0 0 read-write 0 GTCNT counts down. #0 1 GTCNT counts up. #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write 0x00000000 0xFFFFFFFF NFCSB Noise Filter B Sampling Clock Select 30 31 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFBEN Noise Filter B Enable 29 29 read-write 0 The noise filter for the GTIOCB pin is disabled. #0 1 The noise filter for the GTIOCB pin is enabled. #1 Reserved These bits are read as 00. The write value should be 00. 27 28 read-write OBDF GTIOCB Pin Disable Value Setting 25 26 read-write 00 Output disable is prohibited. #00 01 GTIOCB pin is set to Hi-Z when output disable is performed. #01 10 GTIOCB pin is set to 0 when output disable is performed. #10 11 GTIOCB pin is set to 1 when output disable is performed. #11 OBE GTIOCB Pin Output Enable 24 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCB Pin Output Setting at the Start/Stop Count 23 23 read-write 0 The GTIOCB pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCB pin output level is retained at start/stop of counting. #1 OBDFLT GTIOCB Pin Output Value Setting at the Count Stop 22 22 read-write 0 The GTIOCB pin outputs low when counting is stopped. #0 1 The GTIOCB pin outputs high when counting is stopped. #1 Reserved This bit is read as 0. The write value should be 0. 21 21 read-write GTIOB GTIOCB Pin Function Select 16 20 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRB compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRB compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRB compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRB compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. #11111 NFCSA Noise Filter A Sampling Clock Select 14 15 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFAEN Noise Filter A Enable 13 13 read-write 0 The noise filter for the GTIOCA pin is disabled. #0 1 The noise filter for the GTIOCA pin is enabled. #1 Reserved These bits are read as 00. The write value should be 00. 11 12 read-write OADF GTIOCA Pin Disable Value Setting 9 10 read-write 00 Output disable is prohibited. #00 01 GTIOCA pin is set to Hi-Z when output disable is performed. #01 10 GTIOCA pin is set to 0 when output disable is performed. #10 11 GTIOCA pin is set to 1 when output disable is performed. #11 OAE GTIOCA Pin Output Enable 8 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCA Pin Output Setting at the Start/Stop Count 7 7 read-write 0 The GTIOCA pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCA pin output level is retained at start/stop of counting. #1 OADFLT GTIOCA Pin Output Value Setting at the Count Stop 6 6 read-write 0 The GTIOCA pin outputs low when counting is stopped. #0 1 The GTIOCA pin outputs high when counting is stopped. #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write GTIOA GTIOCA Pin Function Select 0 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRA compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRA compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRA compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRA compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. #11111 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write 0x00000000 0xFFFFFFFF GRPABL Same Time Output Level Low Disable Request Enable 30 30 read-write 0 Same time output level low disable request is disabled. #0 1 Same time output level low disable request is enabled. #1 GRPABH Same Time Output Level High Disable Request Enable 29 29 read-write 0 Same time output level high disable request is disabled. #0 1 Same time output level high disable request is enabled. #1 Reserved These bits are read as 000. The write value should be 000. 26 28 read-write GRP Output Disable Source Select 24 25 read-write 00 Group A output disable request #00 01 Group B output disable request #01 others Setting prohibited true Reserved These bits are read as 000000000000000000000000. The write value should be 000000000000000000000000. 0 23 read-write GTST General PWM Timer Status Register 0x3C 32 read-write 0x00008000 0xFFFFFFFF OABLF Same Time Output Level Low Disable Request Enable 30 30 read-only 0 GTIOCA pin and GTIOCB pin don't output 0 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 0 at the same time. #1 OABHF Same Time Output Level High Disable Request Enable 29 29 read-only 0 GTIOCA pin and GTIOCB pin don't output 1 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 1 at the same time. #1 Reserved These bits are read as 0000. The write value should be 0000. 25 28 read-write ODF Output Disable Flag 24 24 read-only 0 No output disable request is generated. #0 1 An output disable request is generated. #1 Reserved These bits are read as 00000000. The write value should be 00000000. 16 23 read-write TUCF Count Direction Flag 15 15 read-only 0 The GTCNT counter counts downward. #0 1 The GTCNT counter counts upward. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 8 14 read-write TCFPU Underflow Flag 7 7 read-write 0 No underflow (trough) has occurred. #0 1 An underflow (trough) has occurred. #1 TCFPO Overflow Flag 6 6 read-write 0 No overflow (crest) has occurred. #0 1 An overflow (crest) has occurred. #1 TCFF Input Compare Match Flag F 5 5 read-write 0 No compare match of GTCCRF is generated. #0 1 A compare match of GTCCRF is generated. #1 TCFE Input Compare Match Flag E 4 4 read-write 0 No compare match of GTCCRE is generated. #0 1 A compare match of GTCCRE is generated. #1 TCFD Input Compare Match Flag D 3 3 read-write 0 No compare match of GTCCRD is generated. #0 1 A compare match of GTCCRD is generated. #1 TCFC Input Compare Match Flag C 2 2 read-write 0 No compare match of GTCCRC is generated. #0 1 A compare match of GTCCRC is generated. #1 TCFB Input Capture/Compare Match Flag B 1 1 read-write 0 No input capture/compare match of GTCCRB is generated. #0 1 An input capture/compare match of GTCCRB is generated. #1 TCFA Input Capture/Compare Match Flag A 0 0 read-write 0 No input capture/compare match of GTCCRA is generated. #0 1 An input capture/compare match of GTCCRA is generated. #1 GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write 0x00000000 0xFFFFFFFF CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation This bit is read as 0. 22 22 write-only 0 no effect #0 1 Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. #1 PR GTPR Buffer Operation 20 21 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTPBR --> GTPR) #01 others Setting prohibited true CCRB GTCCRB Buffer Operation 18 19 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRB <--> GTCCRE) #01 10 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #10 11 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #11 CCRA GTCCRA Buffer Operation 16 17 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRA <--> GTCCRC) #01 10 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #10 11 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #11 BD BD[1]: GTPR Buffer Operation Disable BD[0]: GTCCR Buffer Operation Disable 0 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 GTCNT General PWM Timer Counter 0x48 32 read-write 0x00000000 0xFFFFFFFF GTCNT Counter 0 31 read-write GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTCCRA Compare Capture Register A 0 31 read-write GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTCCRB Compare Capture Register B 0 31 read-write GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTCCRC Compare Capture Register C 0 31 read-write GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTCCRE Compare Capture Register E 0 31 read-write GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTCCRD Compare Capture Register D 0 31 read-write GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTCCRF Compare Capture Register F 0 31 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTPR Cycle Setting Register 0 31 read-write GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTPBR Cycle Setting Buffer Register 0 31 read-write GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write 0x00000000 0xFFFFFFFF Reserved These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000. 9 31 read-write Reserved This bit is read as 0. The write value should be 0. 8 8 read-write Reserved These bits are read as 00. The write value should be 00. 6 7 read-write Reserved This bit is read as 0. The write value should be 0. 5 5 read-write Reserved This bit is read as 0. The write value should be 0. 4 4 read-write Reserved These bits are read as 000. The write value should be 000. 1 3 read-write TDE Negative-Phase Waveform Setting 0 0 read-write 0 GTCCRB is set without using GTDVU and GTDVD. #0 1 GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB. #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTDVU Dead Time Value Register U 0 31 read-write GPT321 General PWM Timer 1 (32-bit) 0x40078100 GPT162 General PWM Timer 2 (16-bit) 0x40078200 0x00 116 registers 0x7C 4 registers 0x74 4 registers 0x80 4 registers 0x78 4 registers 0x84 32 registers GTWP General PWM Timer Write-Protection Register 0x00 32 read-write 0x00000000 0xFFFFFFFF Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 31 read-write PRKEY GTWP Key Code 8 15 write-only 0xA5 Written to these bits, the WP bits write is permitted. 0xA5 others The WP bits write is not permitted. true Reserved These bits are read as 0000000. The write value should be 0000000. 1 7 read-write WP Register Write Disable 0 0 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 GTSTR General PWM Timer Software Start Register 0x04 32 read-write 0x00000000 0xFFFFFFFF Reserved These bits are read as 000000000000000000000000. The write value should be 000000000000000000000000. 8 31 read-write CSTRT7 Channel 7 GTCNT Count Start Read data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 7 7 read-write 0 No effect (write) / counter stop (read) #0 1 GPT167.GTCNT counter starts (write) / Counter running (read) #1 CSTRT6 Channel 6 GTCNT Count Start Read data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 6 6 read-write 0 No effect (write) / counter stop (read) #0 1 GPT166.GTCNT counter starts (write) / Counter running (read) #1 CSTRT5 Channel 5 GTCNT Count Start Read data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 5 5 read-write 0 No effect (write) / counter stop (read) #0 1 GPT165.GTCNT counter starts (write) / Counter running (read) #1 CSTRT4 Channel 4 GTCNT Count Start Read data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 4 4 read-write 0 No effect (write) / counter stop (read) #0 1 GPT164.GTCNT counter starts (write) / Counter running (read) #1 CSTRT3 Channel 3 GTCNT Count Start Read data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 3 3 read-write 0 No effect (write) / counter stop (read) #0 1 GPT323.GTCNT counter starts (write) / Counter running (read) #1 CSTRT2 Channel 2 GTCNT Count Start Read data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 2 2 read-write 0 No effect (write) / counter stop (read) #0 1 GPT322.GTCNT counter starts (write) / Counter running (read) #1 CSTRT1 Channel 1 GTCNT Count Start Read data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 1 1 read-write 0 No effect (write) / counter stop (read) #0 1 GPT321.GTCNT counter starts (write) / Counter running (read) #1 CSTRT0 Channel 0 GTCNT Count Start Read data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 0 0 read-write 0 No effect (write) / counter stop (read) #0 1 GPT320.GTCNT counter starts (write) / Counter running (read) #1 GTSTP General PWM Timer Software Stop Register 0x08 32 read-write 0xFFFFFFFF 0xFFFFFFFF Reserved These bits are read as 111111111111111111111111. The write value should be 111111111111111111111111. 8 31 read-write CSTOP7 Channel 7 GTCNT Count Stop Read data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 7 7 read-write 0 No effect (write) / counter running (read) #0 1 GPT167.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP6 Channel 6 GTCNT Count Stop Read data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 6 6 read-write 0 No effect (write) / counter running (read) #0 1 GPT166.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP5 Channel 5 GTCNT Count Stop Read data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 5 5 read-write 0 No effect (write) / counter running (read) #0 1 GPT165.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP4 Channel 4 GTCNT Count Stop Read data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 4 4 read-write 0 No effect (write) / counter running (read) #0 1 GPT164.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP3 Channel 3 GTCNT Count Stop Read data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 3 3 read-write 0 No effect (write) / counter running (read) #0 1 GPT323.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP2 Channel 2 GTCNT Count Stop Read data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 2 2 read-write 0 No effect (write) / counter running (read) #0 1 GPT322.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP1 Channel 1 GTCNT Count Stop Read data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 1 1 read-write 0 No effect (write) / counter running (read) #0 1 GPT321.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP0 Channel 0 GTCNT Count Stop Read data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 0 0 read-write 0 No effect (write) / counter running (read) #0 1 GPT320.GTCNT counter stops (write) / Counter stop (read) #1 GTCLR General PWM Timer Software Clear Register 0x0C 32 write-only 0x00000000 0xFFFFFFFF Reserved The write value should be 000000000000000000000000. 8 31 write-only CCLR7 Channel 7 GTCNT Count Clear 7 7 write-only 0 No effect #0 1 GPT167.GTCNT counter clears #1 CCLR6 Channel 6 GTCNT Count Clear 6 6 write-only 0 No effect #0 1 GPT166.GTCNT counter clears #1 CCLR5 Channel 5 GTCNT Count Clear 5 5 write-only 0 No effect #0 1 GPT165.GTCNT counter clears #1 CCLR4 Channel 4 GTCNT Count Clear 4 4 write-only 0 No effect #0 1 GPT164.GTCNT counter clears #1 CCLR3 Channel 3 GTCNT Count Clear 3 3 write-only 0 No effect #0 1 GPT323.GTCNT counter clears #1 CCLR2 Channel 2 GTCNT Count Clear 2 2 write-only 0 No effect #0 1 GPT322.GTCNT counter clears #1 CCLR1 Channel 1 GTCNT Count Clear 1 1 write-only 0 No effect #0 1 GPT321.GTCNT counter clears #1 CCLR0 Channel 0 GTCNT Count Clear 0 0 write-only 0 No effect #0 1 GPT320.GTCNT counter clears #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write 0x00000000 0xFFFFFFFF CSTRT Software Source Counter Start Enable 31 31 read-write 0 Counter start is disable by the GTSTR register #0 1 Counter start is enable by the GTSTR register #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 30 read-write SSELCH ELC_GPTH Event Source Counter Start Enable 23 23 read-write 0 Counter start is disable at the ELC_GPTH input #0 1 Counter start is enable at the ELC_GPTH input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 22 read-write 0 Counter start is disable at the ELC_GPTG input #0 1 Counter start is enable at the ELC_GPTG input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 21 read-write 0 Counter start is disable at the ELC_GPTF input #0 1 Counter start is enable at the ELC_GPTF input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 20 read-write 0 Counter start is disable at the ELC_GPTE input #0 1 Counter start is enable at the ELC_GPTE input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 19 read-write 0 Counter start is disable at the ELC_GPTD input #0 1 Counter start is enable at the ELC_GPTD input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 18 read-write 0 Counter start is disable at the ELC_GPTC input #0 1 Counter start is enable at the ELC_GPTC input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 17 read-write 0 Counter start is disable at the ELC_GPTB input #0 1 Counter start is enable at the ELC_GPTB input #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 16 read-write 0 Counter start is disable at the ELC_GPTA input #0 1 Counter start is enable at the ELC_GPTA input #1 SSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable 15 15 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 SSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable 14 14 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 SSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable 13 13 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 SSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable 12 12 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 SSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable 11 11 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 SSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable 10 10 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 SSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable 9 9 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 SSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable 8 8 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 Reserved These bits are read as 0000. The write value should be 0000. 4 7 read-write SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 3 read-write 0 Counter start is disable at the falling edge of GTETRGB input #0 1 Counter start is enable at the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 2 read-write 0 Counter start is disable at the rising edge of GTETRGB input #0 1 Counter start is enable at the rising edge of GTETRGB input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 1 read-write 0 Counter start is disable at the falling edge of GTETRGA input #0 1 Counter start is enable at the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 0 read-write 0 Counter start is disable at the rising edge of GTETRGA input #0 1 Counter start is enable at the rising edge of GTETRGA input #1 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write 0x00000000 0xFFFFFFFF CSTOP Software Source Counter Stop Enable 31 31 read-write 0 Counter stop is disable by the GTSTP register #0 1 Counter stop is enable by the GTSTP register #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 30 read-write PSELCH ELC_GPTH Event Source Counter Stop Enable 23 23 read-write 0 Counter stop is disable at the ELC_GPTH input #0 1 Counter stop is enable at the ELC_GPTH input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 22 read-write 0 Counter stop is disable at the ELC_GPTG input #0 1 Counter stop is enable at the ELC_GPTG input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 21 read-write 0 Counter stop is disable at the ELC_GPTF input #0 1 Counter stop is enable at the ELC_GPTF input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 20 read-write 0 Counter stop is disable at the ELC_GPTE input #0 1 Counter stop is enable at the ELC_GPTE input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 19 read-write 0 Counter stop is disable at the ELC_GPTD input #0 1 Counter stop is enable at the ELC_GPTD input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 18 read-write 0 Counter stop is disable at the ELC_GPTC input #0 1 Counter stop is enable at the ELC_GPTC input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 17 read-write 0 Counter stop is disable at the ELC_GPTB input #0 1 Counter stop is enable at the ELC_GPTB input #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 16 read-write 0 Counter stop is disable at the ELC_GPTA input #0 1 Counter stop is enable at the ELC_GPTA input #1 PSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable 15 15 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 PSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable 14 14 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 PSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable 13 13 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 PSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable 12 12 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 PSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable 11 11 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 PSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable 10 10 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 PSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable 9 9 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 PSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable 8 8 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 Reserved These bits are read as 0000. The write value should be 0000. 4 7 read-write PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 3 read-write 0 Counter stop is disable at the falling edge of GTETRGB input #0 1 Counter stop is enable at the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 2 read-write 0 Counter stop is disable at the rising edge of GTETRGB input #0 1 Counter stop is enable at the rising edge of GTETRGB input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 1 read-write 0 Counter stop is disable at the falling edge of GTETRGA input #0 1 Counter stop is enable at the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 0 read-write 0 Counter stop is disable at the rising edge of GTETRGA input #0 1 Counter stop is enable at the rising edge of GTETRGA input #1 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write 0x00000000 0xFFFFFFFF CCLR Software Source Counter Clear Enable 31 31 read-write 0 Counter clear is disable by the GTCLR register #0 1 Counter clear is enable by the GTCLR register #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 30 read-write CSELCH ELC_GPTH Event Source Counter Clear Enable 23 23 read-write 0 Counter clear is disable at the ELC_GPTH input #0 1 Counter clear is enable at the ELC_GPTH input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 22 read-write 0 Counter clear is disable at the ELC_GPTG input #0 1 Counter clear is enable at the ELC_GPTG input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 21 read-write 0 Counter clear is disable at the ELC_GPTF input #0 1 Counter clear is enable at the ELC_GPTF input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 20 read-write 0 Counter clear is disable at the ELC_GPTE input #0 1 Counter clear is enable at the ELC_GPTE input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 19 read-write 0 Counter clear is disable at the ELC_GPTD input #0 1 Counter clear is enable at the ELC_GPTD input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 18 read-write 0 Counter clear is disable at the ELC_GPTC input #0 1 Counter clear is enable at the ELC_GPTC input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 17 read-write 0 Counter clear is disable at the ELC_GPTB input #0 1 Counter clear is enable at the ELC_GPTB input #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 16 read-write 0 Counter clear is disable at the ELC_GPTA input #0 1 Counter clear is enable at the ELC_GPTA input #1 CSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable 15 15 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 CSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable 14 14 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 CSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable 13 13 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 CSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable 12 12 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 CSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable 11 11 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 CSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable 10 10 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 CSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable 9 9 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 CSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable 8 8 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 Reserved These bits are read as 0000. The write value should be 0000. 4 7 read-write CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 3 read-write 0 Counter clear is disable at the falling edge of GTETRGB input #0 1 Counter clear is enable at the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 2 read-write 0 Counter clear is disable at the rising edge of GTETRGB input #0 1 Counter clear is enable at the rising edge of GTETRGB input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 1 read-write 0 Counter clear is disable at the falling edge of GTETRGA input #0 1 Counter clear is enable at the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 0 read-write 0 Counter clear is disable at the rising edge of GTETRGA input #0 1 Counter clear is enable at the rising edge of GTETRGA input #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write 0x00000000 0xFFFFFFFF USELCH ELC_GPTH Event Source Counter Count Up Enable 23 23 read-write 0 Counter count up is disable at the ELC_GPTH input #0 1 Counter count up is enable at the ELC_GPTH input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 22 read-write 0 Counter count up is disable at the ELC_GPTG input #0 1 Counter count up is enable at the ELC_GPTG input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 21 read-write 0 Counter count up is disable at the ELC_GPTF input #0 1 Counter count up is enable at the ELC_GPTF input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 20 read-write 0 Counter count up is disable at the ELC_GPTE input #0 1 Counter count up is enable at the ELC_GPTE input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 19 read-write 0 Counter count up is disable at the ELC_GPTD input #0 1 Counter count up is enable at the ELC_GPTD input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 18 read-write 0 Counter count up is disable at the ELC_GPTC input #0 1 Counter count up is enable at the ELC_GPTC input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 17 read-write 0 Counter count up is disable at the ELC_GPTB input #0 1 Counter count up is enable at the ELC_GPTB input #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 16 read-write 0 Counter count up is disable at the ELC_GPTA input #0 1 Counter count up is enable at the ELC_GPTA input #1 USCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable 15 15 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 USCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable 14 14 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 USCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable 13 13 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 USCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable 12 12 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 USCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable 11 11 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 USCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable 10 10 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 USCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable 9 9 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 USCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable 8 8 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 3 read-write 0 Counter count up is disable at the falling edge of GTETRGB input #0 1 Counter count up is enable at the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 2 read-write 0 Counter count up is disable at the rising edge of GTETRGB input #0 1 Counter count up is enable at the rising edge of GTETRGB input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 1 read-write 0 Counter count up is disable at the falling edge of GTETRGA input #0 1 Counter count up is enable at the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 0 read-write 0 Counter count up is disable at the rising edge of GTETRGA input #0 1 Counter count up is enable at the rising edge of GTETRGA input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write 0x00000000 0xFFFFFFFF DSELCH ELC_GPTH Event Source Counter Count Down Enable 23 23 read-write 0 Counter count down is disable at the ELC_GPTH input #0 1 Counter count down is enable at the ELC_GPTH input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 22 read-write 0 Counter count down is disable at the ELC_GPTG input #0 1 Counter count down is enable at the ELC_GPTG input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 21 read-write 0 Counter count down is disable at the ELC_GPTF input #0 1 Counter count down is enable at the ELC_GPTF input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 20 read-write 0 Counter count down is disable at the ELC_GPTE input #0 1 Counter count down is enable at the ELC_GPTE input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 19 read-write 0 Counter count down is disable at the ELC_GPTD input #0 1 Counter count down is enable at the ELC_GPTD input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 18 read-write 0 Counter count down is disable at the ELC_GPTC input #0 1 Counter count down is enable at the ELC_GPTC input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 17 read-write 0 Counter count down is disable at the ELC_GPTB input #0 1 Counter count down is enable at the ELC_GPTB input #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 16 read-write 0 Counter count down is disable at the ELC_GPTA input #0 1 Counter count down is enable at the ELC_GPTA input #1 DSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable 15 15 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 DSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable 14 14 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 DSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable 13 13 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 DSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable 12 12 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 DSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable 11 11 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 DSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable 10 10 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 DSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable 9 9 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 DSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable 8 8 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 3 read-write 0 Counter count down is disable at the falling edge of GTETRGB input #0 1 Counter count down is enable at the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 2 read-write 0 Counter count down is disable at the rising edge of GTETRGB input #0 1 Counter count down is enable at the rising edge of GTETRGB input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 1 read-write 0 Counter count down is disable at the falling edge of GTETRGA input #0 1 Counter count down is enable at the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 0 read-write 0 Counter count down is disable at the rising edge of GTETRGA input #0 1 Counter count down is enable at the rising edge of GTETRGA input #1 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write 0x00000000 0xFFFFFFFF ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 23 read-write 0 GTCCRA input capture is disable at the ELC_GPTH input #0 1 GTCCRA input capture is enable at the ELC_GPTH input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 22 read-write 0 GTCCRA input capture is disable at the ELC_GPTG input #0 1 GTCCRA input capture is enable at the ELC_GPTG input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 21 read-write 0 GTCCRA input capture is disable at the ELC_GPTF input #0 1 GTCCRA input capture is enable at the ELC_GPTF input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 20 read-write 0 GTCCRA input capture is disable at the ELC_GPTE input #0 1 GTCCRA input capture is enable at the ELC_GPTE input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 19 read-write 0 GTCCRA input capture is disable at the ELC_GPTD input #0 1 GTCCRA input capture is enable at the ELC_GPTD input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 18 read-write 0 GTCCRA input capture is disable at the ELC_GPTC input #0 1 GTCCRA input capture is enable at the ELC_GPTC input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 17 read-write 0 GTCCRA input capture is disable at the ELC_GPTB input #0 1 GTCCRA input capture is enable at the ELC_GPTB input #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 16 read-write 0 GTCCRA input capture is disable at the ELC_GPTA input #0 1 GTCCRA input capture is enable at the ELC_GPTA input #1 ASCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable 15 15 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 ASCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 14 14 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 ASCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable 13 13 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 ASCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 12 12 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 ASCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable 11 11 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 ASCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 10 10 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 ASCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable 9 9 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 ASCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 8 8 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 3 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 2 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGB input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 1 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 0 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGA input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write 0x00000000 0xFFFFFFFF BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 23 read-write 0 GTCCRB input capture is disable at the ELC_GPTH input #0 1 GTCCRB input capture is enable at the ELC_GPTH input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 22 read-write 0 GTCCRB input capture is disable at the ELC_GPTG input #0 1 GTCCRB input capture is enable at the ELC_GPTG input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 21 read-write 0 GTCCRB input capture is disable at the ELC_GPTF input #0 1 GTCCRB input capture is enable at the ELC_GPTF input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 20 read-write 0 GTCCRB input capture is disable at the ELC_GPTE input #0 1 GTCCRB input capture is enable at the ELC_GPTE input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 19 read-write 0 GTCCRB input capture is disable at the ELC_GPTD input #0 1 GTCCRB input capture is enable at the ELC_GPTD input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 18 read-write 0 GTCCRB input capture is disable at the ELC_GPTC input #0 1 GTCCRB input capture is enable at the ELC_GPTC input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 17 read-write 0 GTCCRB input capture is disable at the ELC_GPTB input #0 1 GTCCRB input capture is enable at the ELC_GPTB input #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 16 read-write 0 GTCCRB input capture is disable at the ELC_GPTA input #0 1 GTCCRB input capture is enable at the ELC_GPTA input #1 BSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable 15 15 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 BSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 14 14 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 BSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable 13 13 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 BSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 12 12 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 BSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable 11 11 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 BSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 10 10 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 BSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable 9 9 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 BSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 8 8 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 3 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 2 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGB input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 1 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 0 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGA input #1 GTCR General PWM Timer Control Register 0x2C 32 read-write 0x00000000 0xFFFFFFFF TPCS Timer Prescaler Select 24 26 read-write 000 PCLK/1 #000 001 PCLK/4 #001 010 PCLK/16 #010 011 PCLK/64 #011 100 PCLK/256 #100 101 PCLK/1024 #101 others Setting prohibied true Reserved These bits are read as 00000. The write value should be 00000. 19 23 read-write MD Mode Select 16 18 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible) #100 101 Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible) #101 110 Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation) #110 111 Setting prohibited #111 Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 1 15 read-write CST Count Start 0 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write 0x00000001 0xFFFFFFFF OBDTYR GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 27 27 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #1 OBDTYF Forcible GTIOCB Output Duty Setting 26 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTY GTIOCB Output Duty Setting 24 25 read-write 00 GTIOCB pin duty is depend on compare match #00 01 GTIOCB pin duty is depend on compare match #01 10 GTIOCB pin duty 0 percent #10 11 GTIOCB pin duty 100 percent #11 Reserved These bits are read as 0000. The write value should be 0000. 20 23 read-write OADTYR GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 19 19 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #1 OADTYF Forcible GTIOCA Output Duty Setting 18 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTY GTIOCA Output Duty Setting 16 17 read-write 00 GTIOCA pin duty is depend on compare match #00 01 GTIOCA pin duty is depend on compare match #01 10 GTIOCA pin duty 0 percent #10 11 GTIOCA pin duty 100 percent #11 UDF Forcible Count Direction Setting 1 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 UD Count Direction Setting 0 0 read-write 0 GTCNT counts down. #0 1 GTCNT counts up. #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write 0x00000000 0xFFFFFFFF NFCSB Noise Filter B Sampling Clock Select 30 31 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFBEN Noise Filter B Enable 29 29 read-write 0 The noise filter for the GTIOCB pin is disabled. #0 1 The noise filter for the GTIOCB pin is enabled. #1 Reserved These bits are read as 00. The write value should be 00. 27 28 read-write OBDF GTIOCB Pin Disable Value Setting 25 26 read-write 00 Output disable is prohibited. #00 01 GTIOCB pin is set to Hi-Z when output disable is performed. #01 10 GTIOCB pin is set to 0 when output disable is performed. #10 11 GTIOCB pin is set to 1 when output disable is performed. #11 OBE GTIOCB Pin Output Enable 24 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCB Pin Output Setting at the Start/Stop Count 23 23 read-write 0 The GTIOCB pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCB pin output level is retained at start/stop of counting. #1 OBDFLT GTIOCB Pin Output Value Setting at the Count Stop 22 22 read-write 0 The GTIOCB pin outputs low when counting is stopped. #0 1 The GTIOCB pin outputs high when counting is stopped. #1 Reserved This bit is read as 0. The write value should be 0. 21 21 read-write GTIOB GTIOCB Pin Function Select 16 20 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRB compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRB compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRB compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRB compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. #11111 NFCSA Noise Filter A Sampling Clock Select 14 15 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFAEN Noise Filter A Enable 13 13 read-write 0 The noise filter for the GTIOCA pin is disabled. #0 1 The noise filter for the GTIOCA pin is enabled. #1 Reserved These bits are read as 00. The write value should be 00. 11 12 read-write OADF GTIOCA Pin Disable Value Setting 9 10 read-write 00 Output disable is prohibited. #00 01 GTIOCA pin is set to Hi-Z when output disable is performed. #01 10 GTIOCA pin is set to 0 when output disable is performed. #10 11 GTIOCA pin is set to 1 when output disable is performed. #11 OAE GTIOCA Pin Output Enable 8 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCA Pin Output Setting at the Start/Stop Count 7 7 read-write 0 The GTIOCA pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCA pin output level is retained at start/stop of counting. #1 OADFLT GTIOCA Pin Output Value Setting at the Count Stop 6 6 read-write 0 The GTIOCA pin outputs low when counting is stopped. #0 1 The GTIOCA pin outputs high when counting is stopped. #1 Reserved This bit is read as 0. The write value should be 0. 5 5 read-write GTIOA GTIOCA Pin Function Select 0 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRA compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRA compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRA compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRA compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. #11111 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write 0x00000000 0xFFFFFFFF GRPABL Same Time Output Level Low Disable Request Enable 30 30 read-write 0 Same time output level low disable request is disabled. #0 1 Same time output level low disable request is enabled. #1 GRPABH Same Time Output Level High Disable Request Enable 29 29 read-write 0 Same time output level high disable request is disabled. #0 1 Same time output level high disable request is enabled. #1 Reserved These bits are read as 000. The write value should be 000. 26 28 read-write GRP Output Disable Source Select 24 25 read-write 00 Group A output disable request #00 01 Group B output disable request #01 others Setting prohibited true Reserved These bits are read as 000000000000000000000000. The write value should be 000000000000000000000000. 0 23 read-write GTST General PWM Timer Status Register 0x3C 32 read-write 0x00008000 0xFFFFFFFF OABLF Same Time Output Level Low Disable Request Enable 30 30 read-only 0 GTIOCA pin and GTIOCB pin don't output 0 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 0 at the same time. #1 OABHF Same Time Output Level High Disable Request Enable 29 29 read-only 0 GTIOCA pin and GTIOCB pin don't output 1 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 1 at the same time. #1 Reserved These bits are read as 0000. The write value should be 0000. 25 28 read-write ODF Output Disable Flag 24 24 read-only 0 No output disable request is generated. #0 1 An output disable request is generated. #1 Reserved These bits are read as 00000000. The write value should be 00000000. 16 23 read-write TUCF Count Direction Flag 15 15 read-only 0 The GTCNT counter counts downward. #0 1 The GTCNT counter counts upward. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 8 14 read-write TCFPU Underflow Flag 7 7 read-write 0 No underflow (trough) has occurred. #0 1 An underflow (trough) has occurred. #1 TCFPO Overflow Flag 6 6 read-write 0 No overflow (crest) has occurred. #0 1 An overflow (crest) has occurred. #1 TCFF Input Compare Match Flag F 5 5 read-write 0 No compare match of GTCCRF is generated. #0 1 A compare match of GTCCRF is generated. #1 TCFE Input Compare Match Flag E 4 4 read-write 0 No compare match of GTCCRE is generated. #0 1 A compare match of GTCCRE is generated. #1 TCFD Input Compare Match Flag D 3 3 read-write 0 No compare match of GTCCRD is generated. #0 1 A compare match of GTCCRD is generated. #1 TCFC Input Compare Match Flag C 2 2 read-write 0 No compare match of GTCCRC is generated. #0 1 A compare match of GTCCRC is generated. #1 TCFB Input Capture/Compare Match Flag B 1 1 read-write 0 No input capture/compare match of GTCCRB is generated. #0 1 An input capture/compare match of GTCCRB is generated. #1 TCFA Input Capture/Compare Match Flag A 0 0 read-write 0 No input capture/compare match of GTCCRA is generated. #0 1 An input capture/compare match of GTCCRA is generated. #1 GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write 0x00000000 0xFFFFFFFF CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation This bit is read as 0. 22 22 write-only 0 no effect #0 1 Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. #1 PR GTPR Buffer Operation 20 21 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTPBR --> GTPR) #01 others Setting prohibited true CCRB GTCCRB Buffer Operation 18 19 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRB <--> GTCCRE) #01 10 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #10 11 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #11 CCRA GTCCRA Buffer Operation 16 17 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRA <--> GTCCRC) #01 10 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #10 11 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #11 BD BD[1]: GTPR Buffer Operation Disable BD[0]: GTCCR Buffer Operation Disable 0 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 GTCNT General PWM Timer Counter 0x48 32 read-write 0x00000000 0xFFFFFFFF GTCNT Counter 0 31 read-write GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write 0x0000FFFF 0xFFFFFFFF GTCCRA Compare Capture Register A 0 31 read-write GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write 0x0000FFFF 0xFFFFFFFF GTCCRB Compare Capture Register B 0 31 read-write GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write 0x0000FFFF 0xFFFFFFFF GTCCRC Compare Capture Register C 0 31 read-write GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write 0x0000FFFF 0xFFFFFFFF GTCCRE Compare Capture Register E 0 31 read-write GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write 0x0000FFFF 0xFFFFFFFF GTCCRD Compare Capture Register D 0 31 read-write GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write 0x0000FFFF 0xFFFFFFFF GTCCRF Compare Capture Register F 0 31 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write 0x0000FFFF 0xFFFFFFFF GTPR Cycle Setting Register 0 31 read-write GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write 0x0000FFFF 0xFFFFFFFF GTPBR Cycle Setting Buffer Register 0 31 read-write GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write 0x00000000 0xFFFFFFFF Reserved These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000. 9 31 read-write Reserved This bit is read as 0. The write value should be 0. 8 8 read-write Reserved These bits are read as 00. The write value should be 00. 6 7 read-write Reserved This bit is read as 0. The write value should be 0. 5 5 read-write Reserved This bit is read as 0. The write value should be 0. 4 4 read-write Reserved These bits are read as 000. The write value should be 000. 1 3 read-write TDE Negative-Phase Waveform Setting 0 0 read-write 0 GTCCRB is set without using GTDVU and GTDVD. #0 1 GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB. #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write 0x0000FFFF 0xFFFFFFFF GTDVU Dead Time Value Register U 0 31 read-write GPT163 General PWM Timer 3 (16-bit) 0x40078300 GPT164 General PWM Timer 4 (16-bit) 0x40078400 GPT165 General PWM Timer 5 (16-bit) 0x40078500 GPT166 General PWM Timer 6 (16-bit) 0x40078600 GPT167 General PWM Timer 7 (16-bit) 0x40078700 GPT_OPS Output Phase Switching Controller 0x40078FF0 0x00 4 registers OPSCR Output Phase Switching Control Register 0x00 32 read-write 0x00000000 0xFFFFFFFF NFCS External Input Noise Filter Clock selection Noise filter sampling clock setting of the external input. 30 31 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFEN External Input Noise Filter Enable 29 29 read-write 0 Do not use a noise filter to the external input. #0 1 Use a noise filter to the external input. #1 Reserved These bits are read as 00. The write value should be 00. 27 28 read-write GODF Group output disable function 26 26 read-write 0 This bit function is ignored. #0 1 Group disable will clear OPSCR.EN Bit. #1 GRP Output disabled source selection 24 25 read-write 00 Select Group A output disable source #00 01 Select Group B output disable source #01 others Setting prohibited true Reserved These bits are read as 00. The write value should be 00. 22 23 read-write ALIGN Input phase alignment 21 21 read-write 0 Input phase is aligned to PCLK. #0 1 Input phase is aligned PWM. #1 RV Output phase rotation direction reversal 20 20 read-write 0 U/V/W-Phase output #0 1 Output to reverse the V / W-phase #1 INV Invert-Phase Output Control 19 19 read-write 0 Positive Logic (Active High)output #0 1 Negative Logic (Active Low)output #1 N Negative-Phase Output (N) Control 18 18 read-write 0 Level signal output #0 1 PWM signal output (PWM of GPT0) #1 P Positive-Phase Output (P) Control 17 17 read-write 0 Level signal output #0 1 PWM signal output (PWM of GPT0) #1 FB External Feedback Signal Enable This bit selects the input phase from the software settings and external input. 16 16 read-write 0 Select the external input. #0 1 Select the soft setting(OPSCR.UF, VF, WF). #1 Reserved These bits are read as 0000000. The write value should be 0000000. 9 15 read-write EN Enable-Phase Output Control 8 8 read-write 0 Not Output(Hi-Z external terminals). #0 1 Output #1 Reserved This bit is read as 0. The write value should be 0. 7 7 read-write W Input W-Phase Monitor This bit monitors the state of the input phase. OPSCR.FB=0:External input monitoring by PCLK OPSCR.FB=1:Software settings (UF/VF/WF) 6 6 read-only V Input V-Phase Monitor This bit monitors the state of the input phase. OPSCR.FB=0:External input monitoring by PCLK OPSCR.FB=1:Software settings (UF/VF/WF) 5 5 read-only U Input U-Phase Monitor This bit monitors the state of the input phase. OPSCR.FB=0:External input monitoring by PCLK OPSCR.FB=1:Software settings (UF/VF/WF) 4 4 read-only Reserved This bit is read as 0. The write value should be 0. 3 3 read-write WF Input Phase Soft Setting UF This bit sets the input phase by the software settings. This bit setting is valid when the OPSCR.FB bit = 1. 2 2 read-write VF Input Phase Soft Setting VF This bit sets the input phase by the software settings. This bit setting is valid when the OPSCR.FB bit = 1. 1 1 read-write UF Input Phase Soft Setting WF This bit sets the input phase by the software settings. This bit setting is valid when the OPSCR.FB bit = 1. 0 0 read-write