Renesas Electronics Corporation Renesas R7FA2E2A7 RA2 1.20.00 Arm Cortex-M23 based Microcontroller RA2E2 device This software is supplied by Renesas Electronics Corporation and is only intended for \n use with Renesas products. No other uses are authorized. This software is owned by \n Renesas Electronics Corporation and is protected under all applicable laws, including \n copyright laws. \n \n THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING \n THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO \n WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. \n ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. 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By using this software, you agree to \n the additional terms and conditions found by accessing the following link: \n http://www.renesas.com/disclaimer \n \n CM23 r1p0 little true false true 2 false 32 system_RA2E2 8 32 32 read-write n 0 0xffffffff RMPU Renesas Memory Protection Unit 0x40000000 0x00 2 registers 0x102 2 registers 0x200 72 registers 0xC00 2 registers 0xC10 2 registers 0xC14 2 registers 0xC18 2 registers 0xC20 2 registers 0xC24 2 registers 0xC28 2 registers 0xD00 2 registers 0xD04 14 registers 0xD14 12 registers MMPUCTLA Bus Master MPU Control Register 0x000 16 read-write 0x0000 0xffff ENABLE Master Group Enable 0 0 read-write 0 Master group A disabled #0 1 Master group A enabled #1 OAD Operation After Detection 1 1 read-write 0 Non-maskable interrupt #0 1 Reset #1 KEY Key Code 8 15 read-write MMPUPTA Group A Protection of Register 0x102 16 read-write 0x0000 0xffff PROTECT Protection of Register 0 0 read-write 0 All bus master MPU group A register writes are permitted. #0 1 All bus master MPU group A register writes are protected. Reads are permitted. #1 KEY Key Code 8 15 read-write 4 0x010 0-3 MMPUACA%s Group A Region %s access control register 0x200 16 read-write 0x0000 0xffff ENABLE Region Enable 0 0 read-write 0 Group A region n disabled #0 1 Group A region n enabled #1 RP Read Protection 1 1 read-write 0 Read permission #0 1 Read protection #1 WP Write Protection 2 2 read-write 0 Write permission #0 1 Write protection #1 4 0x010 0-3 MMPUSA%s Group A Region %s Start Address Register 0x204 32 read-write 0x00000000 0x00000003 MMPUSA Region Start Address 0 31 read-write 4 0x010 0-3 MMPUEA%s Group A Region %s End Address Register 0x208 32 read-write 0x00000003 0x00000003 MMPUEA Region End Address 0 31 read-write SMPUCTL Slave MPU Control Register 0xC00 16 read-write 0x0000 0xffff OAD Operation After Detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 PROTECT Protection of Register 1 1 read-write 0 All bus slave register writes are permitted #0 1 All bus slave register writes are protected. Reads are permitted #1 KEY Key Code 8 15 read-write SMPUMBIU Access Control Register for Memory Bus 1 0xC10 16 read-write 0x0000 0xffff RPGRPA Master MPU Group A Read Protection 2 2 read-write 0 Memory protection read for master MPU group A disabled #0 1 Memory protection read for master MPU group A enabled #1 WPGRPA Master MPU Group A Write Protection 3 3 read-write 0 Memory protection write for master MPU group A disabled #0 1 Memory protection write for master MPU group A enabled #1 SMPUFBIU Access Control Register for Internal Peripheral Bus 9 0xC14 16 read-write 0x0000 0xffff RPCPU CPU Read Protection 0 0 read-write 0 Memory protection for CPU read disabled #0 1 Memory protection for CPU read enabled #1 WPCPU CPU Write Protection 1 1 read-write 0 Memory protection for CPU write disabled #0 1 Memory protection for CPU write enabled #1 RPGRPA Master MPU Group A Read Protection 2 2 read-write 0 Memory protection for master MPU group A read disabled #0 1 Memory protection for master MPU group A read enabled #1 WPGRPA Master MPU Group A Write Protection 3 3 read-write 0 Memory protection for master MPU group A write disabled #0 1 Memory protection for master MPU group A write enabled #1 SMPUSRAM0 Access Control Register for Memory Bus 4 0xC18 16 read-write 0x0000 0xffff RPCPU CPU Read Protection 0 0 read-write 0 Memory protection for CPU read disabled #0 1 Memory protection for CPU read enabled #1 WPCPU CPU Write Protection 1 1 read-write 0 Memory protection for CPU write disabled #0 1 Memory protection for CPU write enabled #1 RPGRPA Master MPU Group A Read Protection 2 2 read-write 0 Memory protection for master MPU group A read disabled #0 1 Memory protection for master MPU group A read enabled #1 WPGRPA Master MPU Group A Write Protection 3 3 read-write 0 Memory protection for master MPU group A write disabled #0 1 Memory protection for master MPU group A write enabled #1 SMPUP0BIU Access Control Register for Internal Peripheral Bus 1 0xC20 16 read-write 0x0000 0xffff RPCPU CPU Read Protection 0 0 read-write 0 Memory protection for CPU read disabled #0 1 Memory protection for CPU read enabled #1 WPCPU CPU Write Protection 1 1 read-write 0 Memory protection for CPU write disabled #0 1 Memory protection for CPU write enabled #1 RPGRPA Master MPU Group A Read Protection 2 2 read-write 0 Memory protection for master MPU group A read disabled #0 1 Memory protection for master MPU group A read enabled #1 WPGRPA Master MPU Group A Write Protection 3 3 read-write 0 Memory protection for master MPU group A write disabled #0 1 Memory protection for master MPU group A write enabled #1 SMPUP2BIU Access Control Register for Internal Peripheral Bus 3 0xC24 16 read-write 0x0000 0xffff RPCPU CPU Read Protection 0 0 read-write 0 Memory protection for CPU read disabled #0 1 Memory protection for CPU read enabled #1 WPCPU CPU Write Protection 1 1 read-write 0 Memory protection for CPU write disabled #0 1 Memory protection for CPU write enabled #1 RPGRPA Master MPU Group A Read Protection 2 2 read-write 0 Memory protection for master MPU group A read disabled #0 1 Memory protection for master MPU group A read enabled #1 WPGRPA Master MPU Group A Write Protection 3 3 read-write 0 Memory protection for master MPU group A write disabled #0 1 Memory protection for master MPU group A write enabled #1 SMPUP6BIU Access Control Register for Internal Peripheral Bus 7 0xC28 16 read-write 0x0000 0xffff RPCPU CPU Read Protection 0 0 read-write 0 CPU read of memory protection disabled #0 1 CPU read of memory protection enabled #1 WPCPU CPU Write Protection 1 1 read-write 0 CPU write of memory protection disabled #0 1 CPU write of memory protection enabled #1 RPGRPA Master MPU Group A Read Protection 2 2 read-write 0 Master MPU group A read of memory protection disabled #0 1 Master MPU group A read of memory protection enabled #1 WPGRPA Master MPU Group A Write Protection 3 3 read-write 0 Master MPU group A write of memory protection disabled #0 1 Master MPU group A write of memory protection enabled #1 MSPMPUOAD Stack Pointer Monitor Operation After Detection Register 0xD00 16 read-write 0x0000 0xffff OAD Operation after Detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 KEY Key Code 8 15 read-write MSPMPUCTL Stack Pointer Monitor Access Control Register 0xD04 16 read-write 0x0000 0xfeff ENABLE Stack Pointer Monitor Enable 0 0 read-write 0 Stack pointer monitor is disabled #0 1 Stack pointer monitor is enabled #1 ERROR Stack Pointer Monitor Error Flag 8 8 read-write 0 Stack pointer has not overflowed or underflowed #0 1 Stack pointer has overflowed or underflowed #1 MSPMPUPT Stack Pointer Monitor Protection Register 0xD06 16 read-write 0x0000 0xffff PROTECT Protection of Register 0 0 read-write 0 Stack pointer monitor register writes are permitted. #0 1 Stack pointer monitor register writes are protected. Reads are permitted #1 KEY Key Code 8 15 read-write MSPMPUSA Main Stack Pointer (MSP) Monitor Start Address Register 0xD08 32 read-write 0x00000000 0x00000000 MSPMPUSA Region Start Address 0 31 read-write 0x1FF00000 0x200FFFFC MSPMPUEA Main Stack Pointer (MSP) Monitor End Address Register 0xD0C 32 read-write 0x00000000 0x00000000 MSPMPUEA Region End Address 0 31 read-write 0x1FF00003 0x200FFFFF PSPMPUOAD Stack Pointer Monitor Operation After Detection Register 0xD10 16 read-write 0x0000 0xffff OAD Operation after Detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 KEY Key Code 8 15 read-write PSPMPUCTL Stack Pointer Monitor Access Control Register 0xD14 16 read-write 0x0000 0xfeff ENABLE Stack Pointer Monitor Enable 0 0 read-write 0 Stack pointer monitor is disabled #0 1 Stack pointer monitor is enabled #1 ERROR Stack Pointer Monitor Error Flag 8 8 read-write 0 Stack pointer has not overflowed or underflowed #0 1 Stack pointer has overflowed or underflowed #1 PSPMPUPT Stack Pointer Monitor Protection Register 0xD16 16 read-write 0x0000 0xffff PROTECT Protection of Register 0 0 read-write 0 Stack pointer monitor register writes are permitted. #0 1 Stack pointer monitor register writes are protected. Reads are permitted #1 KEY Key Code 8 15 read-write PSPMPUSA Process Stack Pointer (PSP) Monitor Start Address Register 0xD18 32 read-write 0x00000000 0x00000000 PSPMPUSA Region Start Address 0 31 read-write 0x1FF00000 0x200FFFFC PSPMPUEA Process Stack Pointer (PSP) Monitor End Address Register 0xD1C 32 read-write 0x00000000 0x00000000 PSPMPUEA Region End Address 0 31 read-write 0x1FF00003 0x200FFFFF SRAM SRAM Control 0x40002000 0x00 1 registers 0x04 1 registers PARIOAD SRAM Parity Error Operation After Detection Register 0x00 8 read-write 0x00 0xff OAD Operation After Detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 SRAMPRCR SRAM Protection Register 0x04 8 read-write 0x00 0xff SRAMPRCR Register Write Control 0 0 read-write 0 Disable writes to protected registers #0 1 Enable writes to protected registers #1 KW Write Key Code 1 7 write-only BUS BUS Control 0x40003000 0x1008 2 registers 0x100C 2 registers 0x1820 5 registers 0x1830 5 registers BUSMCNTSYS Master Bus Control Register SYS 0x1008 16 read-write 0x0000 0xffff IERES Ignore Error Responses 15 15 read-write 0 A bus error is reported. #0 1 A bus error is not reported. #1 BUSMCNTDMA Master Bus Control Register DMA 0x100C 16 read-write 0x0000 0xffff IERES Ignore Error Responses 15 15 read-write 0 A bus error is reported. #0 1 A bus error is not reported. #1 BUS3ERRADD Bus Error Address Register 3 0x1820 32 read-only 0x00000000 0x00000000 BERAD Bus Error Address 0 31 read-only BUS3ERRSTAT BUS Error Status Register 3 0x1824 8 read-only 0x00 0xfe ACCSTAT Error Access Status flag 0 0 read-only 0 Read access #0 1 Write access #1 ERRSTAT Bus Error Status flag 7 7 read-only 0 No bus error occurred. #0 1 Bus error occurred. #1 BUS4ERRADD Bus Error Address Register 4 0x1830 32 read-only 0x00000000 0x00000000 BERAD Bus Error Address 0 31 read-only BUS4ERRSTAT BUS Error Status Register 4 0x1834 8 read-only 0x00 0xfe ACCSTAT Error Access Status flag 0 0 read-only 0 Read access #0 1 Write access #1 ERRSTAT Bus Error Status flag 7 7 read-only 0 No bus error occurred. #0 1 Bus error occurred. #1 DTC Data Transfer Controller 0x40005400 0x00 1 registers 0x04 4 registers 0x0C 1 registers 0x0E 2 registers DTCCR DTC Control Register 0x00 8 read-write 0x08 0xff RRS DTC Transfer Information Read Skip Enable 4 4 read-write 0 Transfer information read is not skipped #0 1 Transfer information read is skipped when vector numbers match #1 DTCVBR DTC Vector Base Register 0x04 32 read-write 0x00000000 0xffffffff DTCST DTC Module Start Register 0x0C 8 read-write 0x00 0xff DTCST DTC Module Start 0 0 read-write 0 DTC module stopped. #0 1 DTC module started. #1 DTCSTS DTC Status Register 0x0E 16 read-only 0x0000 0xffff VECN DTC-Activating Vector Number Monitoring 0 7 read-only ACT DTC Active Flag 15 15 read-only 0 DTC transfer operation is not in progress. #0 1 DTC transfer operation is in progress. #1 ICU ICU for CPU 0x40006000 0x00 8 registers 0x100 1 registers 0x120 2 registers 0x130 2 registers 0x140 2 registers 0x1A0 4 registers 0x1C0 1 registers 0x200 2 registers 0x300 128 registers IEL0 ICU Interrupt 0 0 IEL1 ICU Interrupt 1 1 IEL2 ICU Interrupt 2 2 IEL3 ICU Interrupt 3 3 IEL4 ICU Interrupt 4 4 IEL5 ICU Interrupt 5 5 IEL6 ICU Interrupt 6 6 IEL7 ICU Interrupt 7 7 IEL8 ICU Interrupt 8 8 IEL9 ICU Interrupt 9 9 IEL10 ICU Interrupt 10 10 IEL11 ICU Interrupt 11 11 IEL12 ICU Interrupt 12 12 IEL13 ICU Interrupt 13 13 IEL14 ICU Interrupt 14 14 IEL15 ICU Interrupt 15 15 IEL16 ICU Interrupt 16 16 IEL17 ICU Interrupt 17 17 IEL18 ICU Interrupt 18 18 IEL19 ICU Interrupt 19 19 IEL20 ICU Interrupt 20 20 IEL21 ICU Interrupt 21 21 IEL22 ICU Interrupt 22 22 IEL23 ICU Interrupt 23 23 IEL24 ICU Interrupt 24 24 IEL25 ICU Interrupt 25 25 IEL26 ICU Interrupt 26 26 IEL27 ICU Interrupt 27 27 IEL28 ICU Interrupt 28 28 IEL29 ICU Interrupt 29 29 IEL30 ICU Interrupt 30 30 IEL31 ICU Interrupt 31 31 8 0x1 0-7 IRQCR%s IRQ Control Register %s 0x000 8 read-write 0x00 0xff IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 5 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQi Digital Filter Enable 7 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 NMICR NMI Pin Interrupt Control Register 0x100 8 read-write 0x00 0xff NMIMD NMI Detection Set 0 0 read-write 0 Falling edge #0 1 Rising edge #1 NFCLKSEL NMI Digital Filter Sampling Clock Select 4 5 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 NFLTEN NMI Digital Filter Enable 7 7 read-write 0 Disabled. #0 1 Enabled. #1 NMIER Non-Maskable Interrupt Enable Register 0x120 16 read-write 0x0000 0xffff IWDTEN IWDT Underflow/Refresh Error Interrupt Enable 0 0 read-write 0 Disabled #0 1 Enabled. #1 WDTEN WDT Underflow/Refresh Error Interrupt Enable 1 1 read-write 0 Disabled #0 1 Enabled #1 LVD1EN Voltage monitor 1 Interrupt Enable 2 2 read-write 0 Disabled #0 1 Enabled #1 LVD2EN Voltage monitor 2 Interrupt Enable 3 3 read-write 0 Disabled #0 1 Enabled #1 NMIEN NMI Pin Interrupt Enable 7 7 read-write 0 Disabled #0 1 Enabled #1 RPEEN SRAM Parity Error Interrupt Enable 8 8 read-write 0 Disabled #0 1 Enabled #1 BUSSEN Bus Slave MPU Error Interrupt Enable 10 10 read-write 0 Disabled #0 1 Enabled #1 BUSMEN Bus Master MPU Error Interrupt Enable 11 11 read-write 0 Disabled #0 1 Enabled #1 SPEEN CPU Stack Pointer Monitor Interrupt Enable 12 12 read-write 0 Disabled #0 1 Enabled #1 NMICLR Non-Maskable Interrupt Status Clear Register 0x130 16 read-write 0x0000 0xffff IWDTCLR IWDT Underflow/Refresh Error Interrupt Status Flag Clear 0 0 read-write 0 No effect #0 1 Clear the NMISR.IWDTST flag #1 WDTCLR WDT Underflow/Refresh Error Interrupt Status Flag Clear 1 1 read-write 0 No effect #0 1 Clear the NMISR.WDTST flag #1 LVD1CLR Voltage Monitor 1 Interrupt Status Flag Clear 2 2 read-write 0 No effect #0 1 Clear the NMISR.LVD1ST flag #1 LVD2CLR Voltage Monitor 2 Interrupt Status Flag Clear 3 3 read-write 0 No effect #0 1 Clear the NMISR.LVD2ST flag. #1 NMICLR NMI Pin Interrupt Status Flag Clear 7 7 read-write 0 No effect #0 1 Clear the NMISR.NMIST flag #1 RPECLR SRAM Parity Error Interrupt Status Flag Clear 8 8 read-write 0 No effect #0 1 Clear the NMISR.RPEST flag #1 BUSSCLR Bus Slave MPU Error Interrupt Status Flag Clear 10 10 read-write 0 No effect #0 1 Clear the NMISR.BUSSST flag #1 BUSMCLR Bus Master MPU Error Interrupt Status Flag Clear 11 11 read-write 0 No effect #0 1 Clear the NMISR.BUSMST flag #1 SPECLR CPU Stack Pointer Monitor Interrupt Status Flag Clear 12 12 read-write 0 No effect #0 1 Clear the NMISR.SPEST flag #1 NMISR Non-Maskable Interrupt Status Register 0x140 16 read-only 0x0000 0xffff IWDTST IWDT Underflow/Refresh Error Interrupt Status Flag 0 0 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 WDTST WDT Underflow/Refresh Error Interrupt Status Flag 1 1 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 LVD1ST Voltage Monitor 1 Interrupt Status Flag 2 2 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 LVD2ST Voltage Monitor 2 Interrupt Status Flag 3 3 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 NMIST NMI Pin Interrupt Status Flag 7 7 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 RPEST SRAM Parity Error Interrupt Status Flag 8 8 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 BUSSST Bus Slave MPU Error Interrupt Status Flag 10 10 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 BUSMST Bus Master MPU Error Interrupt Status Flag 11 11 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 SPEST CPU Stack Pointer Monitor Interrupt Status Flag 12 12 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 WUPEN Wake Up Interrupt Enable Register 0x1A0 32 read-write 0x00000000 0xffffffff IRQWUPEN IRQ Interrupt Software Standby/Snooze Mode Returns Enable 0 7 read-write 0 Software Standby/Snooze Mode returns by IRQn interrupt disabled #0 1 Software Standby/Snooze Mode returns by IRQn interrupt enabled #1 IWDTWUPEN IWDT Interrupt Software Standby/Snooze Mode Returns Enable 16 16 read-write 0 Software Standby/Snooze Mode returns by IWDT interrupt disabled #0 1 Software Standby/Snooze Mode returns by IWDT interrupt enabled #1 KEYWUPEN Key Interrupt Software Standby/Snooze Mode Returns Enable 17 17 read-write 0 Software Standby/Snooze Mode returns by KEY interrupt disabled #0 1 Software Standby/Snooze Mode returns by KEY interrupt enabled #1 LVD1WUPEN LVD1 Interrupt Software Standby/Snooze Mode Returns Enable 18 18 read-write 0 Software Standby/Snooze Mode returns by LVD1 interrupt disabled #0 1 Software Standby/Snooze Mode returns by LVD1 interrupt enabled #1 LVD2WUPEN LVD2 Interrupt Software Standby/Snooze Mode Returns Enable 19 19 read-write 0 Software Standby/Snooze Mode returns by LVD2 interrupt disabled #0 1 Software Standby/Snooze Mode returns by LVD2 interrupt enabled #1 AGT1UDWUPEN AGT1 Underflow Interrupt Software Standby/Snooze Mode Returns Enable 28 28 read-write 0 Software Standby/Snooze Mode returns by AGT1 underflow interrupt disabled #0 1 Software Standby/Snooze Mode returns by AGT1 underflow #1 AGT1CAWUPEN AGT1 Compare Match A Interrupt Software Standby/Snooze Mode Returns Enable 29 29 read-write 0 Software Standby/Snooze Mode returns by AGT1 compare match A interrupt disabled. #0 1 Software Standby/Snooze Mode returns by AGT1 compare match A interrupt enabled. #1 AGT1CBWUPEN AGT1 Compare Match B Interrupt Software Standby/Snooze Mode Returns Enable 30 30 read-write 0 Software Standby/Snooze Mode returns by AGT1 compare match B interrupt disabled. #0 1 Software Standby/Snooze Mode returns by AGT1 compare match B interrupt enabled. #1 IELEN ICU event Enable Register 0x1C0 8 read-write 0x00 0xff IELEN Parts Asynchronous Interrupts Enable (when LPOPTEN bit = 1) 1 1 read-write 0 Disabled #0 1 Enabled #1 SELSR0 SYS Event Link Setting Register 0x200 16 read-write 0x0000 0xffff 32 0x4 0-31 IELSR%s ICU Event Link Setting Register %s 0x300 32 read-write 0x00000000 0xffffffff DBG Debug Function 0x4001B000 0x00 4 registers 0x10 4 registers DBGSTR Debug Status Register 0x00 32 read-only 0x00000000 0xffffffff CDBGPWRUPREQ Debug power-up request 28 28 read-only 0 OCD is not requesting debug power up #0 1 OCD is requesting debug power up #1 CDBGPWRUPACK Debug power-up acknowledge 29 29 read-only 0 Debug power-up request is not acknowledged #0 1 Debug power-up request is acknowledged #1 DBGSTOPCR Debug Stop Control Register 0x10 32 read-write 0x00000003 0xffffffff DBGSTOP_IWDT Mask bit for IWDT reset/interrupt in the OCD run mode 0 0 read-write 0 Enable IWDT reset/interrupt #0 1 Mask IWDT reset/interrupt and stop IWDT counter #1 DBGSTOP_WDT Mask bit for WDT reset/interrupt in the OCD run mode 1 1 read-write 0 Enable WDT reset/interrupt #0 1 Mask WDT reset/interrupt and stop WDT counter #1 DBGSTOP_LVD0 Mask bit for LVD0 reset 16 16 read-write 0 Enable LVD0 reset #0 1 Mask LVD0 reset #1 DBGSTOP_LVD1 Mask bit for LVD1 reset/interrupt 17 17 read-write 0 Enable LVD1 reset/interrupt #0 1 Mask LVD1 reset/interrupt #1 DBGSTOP_LVD2 Mask bit for LVD2 reset/interrupt 18 18 read-write 0 Enable LVD2 reset/interrupt #0 1 Mask LVD2 reset/interrupt #1 DBGSTOP_RPER Mask bit for SRAM parity error reset/interrupt 24 24 read-write 0 Enable SRAM parity error reset/interrupt #0 1 Mask SRAM parity error reset/interrupt #1 SYSC System Control 0x4001E000 0x0C 2 registers 0x1C 8 registers 0x26 1 registers 0x31 1 registers 0x36 1 registers 0x38 1 registers 0x3C 1 registers 0x3E 1 registers 0x4C 1 registers 0x61 2 registers 0x92 1 registers 0x94 1 registers 0x98 4 registers 0x9F 2 registers 0xA5 1 registers 0xAA 1 registers 0xC0 2 registers 0xE0 4 registers 0x3FE 2 registers 0x40E 1 registers 0x410 2 registers 0x417 2 registers 0x41A 2 registers 0x490 1 registers 0x492 1 registers SBYCR Standby Control Register 0x00C 16 read-write 0x0000 0xffff SSBY Software Standby Mode Select 15 15 read-write 0 Sleep mode #0 1 Software Standby mode. #1 MSTPCRA Module Stop Control Register A 0x01C 32 read-write 0xffbfffff 0xffffffff MSTPA22 DTC Module Stop 22 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 SCKDIVCR System Clock Division Control Register 0x020 32 read-write 0x04000404 0xffffffff PCKD Peripheral Module Clock D (PCLKD) Select 0 2 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Settings prohibited true PCKB Peripheral Module Clock B (PCLKB) Select 8 10 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Settings prohibited true ICK System Clock (ICLK) Select 24 26 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 Others Settings prohibited true SCKSCR System Clock Source Control Register 0x026 8 read-write 0x01 0xff CKSEL Clock Source Select 0 2 read-write 000 HOCO #000 001 MOCO #001 010 LOCO #010 011 Setting prohibited #011 100 Setting prohibited #100 101 Setting prohibited #101 110 Setting prohibited #110 111 Setting prohibited #111 MEMWAIT Memory Wait Cycle Control Register for Code Flash 0x031 8 read-write 0x00 0xff MEMWAIT Memory Wait Cycle Select for Code Flash 0 0 read-write 0 No wait #0 1 Wait #1 HOCOCR High-Speed On-Chip Oscillator Control Register 0x036 8 read-write 0x00 0xfe HCSTP HOCO Stop 0 0 read-write 0 Operate the HOCO clock #0 1 Stop the HOCO clock #1 MOCOCR Middle-Speed On-Chip Oscillator Control Register 0x038 8 read-write 0x00 0xff MCSTP MOCO Stop 0 0 read-write 0 MOCO clock is operating #0 1 MOCO clock is stopped #1 OSCSF Oscillation Stabilization Flag Register 0x03C 8 read-only 0x00 0xfe HOCOSF HOCO Clock Oscillation Stabilization Flag 0 0 read-only 0 The HOCO clock is stopped or is not yet stable #0 1 The HOCO clock is stable, so is available for use as the system clock #1 CKOCR Clock Out Control Register 0x03E 8 read-write 0x00 0xff CKOSEL Clock Out Source Select 0 2 read-write 000 HOCO (value after reset) #000 001 MOCO #001 010 LOCO #010 011 Setting prohibited #011 100 Setting prohibited #100 101 Setting prohibited #101 Others Setting prohibited true CKODIV Clock Output Frequency Division Ratio 4 6 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 111 x 1/128 #111 CKOEN Clock Out Enable 7 7 read-write 0 Disable clock out #0 1 Enable clock out #1 LPOPT Lower Power Operation Control Register 0x04C 8 read-write 0x00 0xff MPUDIS MPU Clock Disable Control 0 0 read-write 0 MPU operates as normal #0 1 MPU operate clock stops (MPU function disable). #1 DCLKDIS Debug Clock Disable Control 1 2 read-write 00 Debug clock does not stop #00 Others Debug clock stops (valid only when LPOPT.LPOPTEN = 1) true BPFCLKDIS BPF Clock Disable Control 3 3 read-write 0 Flash register R/W clock operates as normal #0 1 Flash register R/W clock stops. #1 LPOPTEN Lower Power Operation Enable 7 7 read-write 0 All lower power counter measure disable #0 1 All lower power counter measure enable #1 MOCOUTCR MOCO User Trimming Control Register 0x061 8 read-write 0x00 0xff MOCOUTRM MOCO User Trimming 0 7 read-write HOCOUTCR HOCO User Trimming Control Register 0x062 8 read-write 0x00 0xff HOCOUTRM HOCO User Trimming 0 7 read-write SNZCR Snooze Control Register 0x092 8 read-write 0x00 0xff SNZDTCEN DTC Enable in Snooze mode 1 1 read-write 0 Disable DTC operation #0 1 Enable DTC operation #1 SNZE Snooze mode Enable 7 7 read-write 0 Disable Snooze mode #0 1 Enable Snooze mode #1 SNZEDCR0 Snooze End Control Register 0 0x094 8 read-write 0x00 0xff AGTUNFED AGT1 Underflow Snooze End Enable 0 0 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 DTCZRED Last DTC Transmission Completion Snooze End Enable 1 1 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 DTCNZRED Not Last DTC Transmission Completion Snooze End Enable 2 2 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 AD0MATED ADC12 Compare Match Snooze End Enable 3 3 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 AD0UMTED ADC12 Compare Mismatch Snooze End Enable 4 4 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 SNZREQCR0 Snooze Request Control Register 0 0x098 32 read-write 0x00000000 0xffffffff SNZREQEN0 Enable IRQ0 pin snooze request 0 0 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN1 Enable IRQ1 pin snooze request 1 1 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN2 Enable IRQ2 pin snooze request 2 2 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN3 Enable IRQ3 pin snooze request 3 3 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN4 Enable IRQ4 pin snooze request 4 4 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN5 Enable IRQ5 pin snooze request 5 5 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN6 Enable IRQ6 pin snooze request 6 6 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN7 Enable IRQ7 pin snooze request 7 7 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN17 Enable KEY_INTKR snooze request 17 17 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN28 Enable AGT1 underflow snooze request 28 28 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN29 Enable AGT1 compare match A snooze request 29 29 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN30 Enable AGT1 compare match B snooze request 30 30 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 PSMCR Power Save Memory Control Register 0x09F 8 read-write 0x00 0xff PSMC Power Save Memory Control 0 1 read-write 00 All SRAMs are on in Software Standby mode #00 01 4 KB SRAM (0x2000_4000 to 0x2000_4FFF) is on in Software Standby mode #01 10 Setting prohibited #10 11 Setting prohibited #11 OPCCR Operating Power Control Register 0x0A0 8 read-write 0x01 0xff OPCM Operating Power Control Mode Select 0 1 read-write 00 High-speed mode #00 01 Middle-speed mode #01 10 Setting prohibited #10 11 Low-speed mode #11 OPCMTSF Operating Power Control Mode Transition Status Flag 4 4 read-only 0 Transition completed #0 1 During transition #1 HOCOWTCR High-Speed On-Chip Oscillator Wait Control Register 0x0A5 8 read-write 0x05 0xff HSTS HOCO Wait Time Setting 0 2 read-write 101 Value after reset. #101 011 Before starting high-speed on-chip oscillator by setting HOCOCR.HCSTP bit, the HSTS[2:0] bits must be set to 011b beforehand. Wait time = 46 cycles (5.75 µs) Wait time is calculated at MOCO = 8 MHz (typically 0.125 µs). #011 Others Setting prohibited true SOPCCR Sub Operating Power Control Register 0x0AA 8 read-write 0x00 0xff SOPCM Sub Operating Power Control Mode Select 0 0 read-write 0 Other than Subosc-speed mode #0 1 Subosc-speed mode #1 SOPCMTSF Operating Power Control Mode Transition Status Flag 4 4 read-only 0 Transition completed #0 1 During transition #1 RSTSR1 Reset Status Register 1 0x0C0 16 read-write 0x0000 0xe2f8 IWDTRF Independent Watchdog Timer Reset Detect Flag 0 0 read-write 0 Independent watchdog timer reset not detected #0 1 Independent watchdog timer reset detected #1 WDTRF Watchdog Timer Reset Detect Flag 1 1 read-write 0 Watchdog timer reset not detected #0 1 Watchdog timer reset detected #1 SWRF Software Reset Detect Flag 2 2 read-write 0 Software reset not detected #0 1 Software reset detected #1 RPERF SRAM Parity Error Reset Detect Flag 8 8 read-write 0 SRAM parity error reset not detected #0 1 SRAM parity error reset detected #1 BUSSRF Bus Slave MPU Error Reset Detect Flag 10 10 read-write 0 Bus slave MPU error reset not detected #0 1 Bus slave MPU error reset detected #1 BUSMRF Bus Master MPU Error Reset Detect Flag 11 11 read-write 0 Bus master MPU error reset not detected #0 1 Bus master MPU error reset detected #1 SPERF CPU Stack Pointer Error Reset Detect Flag 12 12 read-write 0 CPU stack pointer error reset not detected #0 1 CPU stack pointer error reset detected #1 LVD1CR1 Voltage Monitor 1 Circuit Control Register 0x0E0 8 read-write 0x01 0xff IDTSEL Voltage Monitor 1 Interrupt Generation Condition Select 0 1 read-write 00 When VCC >= Vdet1 (rise) is detected #00 01 When VCC < Vdet1 (fall) is detected #01 10 When fall and rise are detected #10 11 Settings prohibited #11 IRQSEL Voltage Monitor 1 Interrupt Type Select 2 2 read-write 0 Non-maskable interrupt #0 1 Maskable interrupt #1 LVD1SR Voltage Monitor 1 Circuit Status Register 0x0E1 8 read-write 0x02 0xff DET Voltage Monitor 1 Voltage Variation Detection Flag 0 0 read-write 0 Not detected #0 1 Vdet1 crossing is detected #1 MON Voltage Monitor 1 Signal Monitor Flag 1 1 read-only 0 VCC < Vdet1 #0 1 VCC >= Vdet1 or MON is disabled #1 LVD2CR1 Voltage Monitor 2 Circuit Control Register 1 0x0E2 8 read-write 0x01 0xff IDTSEL Voltage Monitor 2 Interrupt Generation Condition Select 0 1 read-write 00 When VCC>= Vdet2 (rise) is detected #00 01 When VCC < Vdet2 (fall) is detected #01 10 When fall and rise are detected #10 11 Settings prohibited #11 IRQSEL Voltage Monitor 2 Interrupt Type Select 2 2 read-write 0 Non-maskable interrupt #0 1 Maskable interrupt #1 LVD2SR Voltage Monitor 2 Circuit Status Register 0x0E3 8 read-write 0x02 0xff DET Voltage Monitor 2 Voltage Variation Detection Flag 0 0 read-write 0 Not detected #0 1 Vdet2 crossing is detected #1 MON Voltage Monitor 2 Signal Monitor Flag 1 1 read-only 0 VCC < Vdet2 #0 1 VCC>= Vdet2 or MON is disabled #1 PRCR Protect Register 0x3FE 16 read-write 0x0000 0xffff PRC0 Enable writing to the registers related to the clock generation circuit 0 0 read-write 0 Disable writes #0 1 Enable writes #1 PRC1 Enable writing to the registers related to the low power modes 1 1 read-write 0 Disable writes #0 1 Enable writes #1 PRC3 Enable writing to the registers related to the LVD 3 3 read-write 0 Disable writes #0 1 Enable writes #1 PRKEY PRC Key Code 8 15 write-only SYOCDCR System Control OCD Control Register 0x040E 8 read-write 0x00 0xff DBGEN Debugger Enable bit 7 7 read-write 0 On-chip debugger is disabled #0 1 On-chip debugger is enabled #1 RSTSR0 Reset Status Register 0 0x410 8 read-write 0x00 0xf0 PORF Power-On Reset Detect Flag 0 0 read-write 0 Power-on reset not detected #0 1 Power-on reset detected #1 LVD0RF Voltage Monitor 0 Reset Detect Flag 1 1 read-write 0 Voltage monitor 0 reset not detected #0 1 Voltage monitor 0 reset detected #1 LVD1RF Voltage Monitor 1 Reset Detect Flag 2 2 read-write 0 Voltage monitor 1 reset not detected #0 1 Voltage monitor 1 reset detected #1 LVD2RF Voltage Monitor 2 Reset Detect Flag 3 3 read-write 0 Voltage monitor 2 reset not detected #0 1 Voltage monitor 2 reset detected #1 RSTSR2 Reset Status Register 2 0x411 8 read-write 0x00 0xfe CWSF Cold/Warm Start Determination Flag 0 0 read-write 0 Cold start #0 1 Warm start #1 LVCMPCR Voltage Monitor Circuit Control Register 0x417 8 read-write 0x00 0xff LVD1E Voltage Detection 1 Enable 5 5 read-write 0 Voltage detection 1 circuit disabled #0 1 Voltage detection 1 circuit enabled #1 LVD2E Voltage Detection 2 Enable 6 6 read-write 0 Voltage detection 2 circuit disabled #0 1 Voltage detection 2 circuit enabled #1 LVDLVLR Voltage Detection Level Select Register 0x418 8 read-write 0x07 0xff LVD1LVL Voltage Detection 1 Level Select (Standard voltage during fall in voltage) 0 4 read-write 0x00 Vdet1_0 0x00 0x01 Vdet1_1 0x01 0x02 Vdet1_2 0x02 0x03 Vdet1_3 0x03 0x04 Vdet1_4 0x04 0x05 Vdet1_5 0x05 0x06 Vdet1_6 0x06 0x07 Vdet1_7 0x07 0x08 Vdet1_8 0x08 0x09 Vdet1_9 0x09 0x0A Vdet1_A 0x0a 0x0B Vdet1_B 0x0b 0x0C Vdet1_C 0x0c 0x0D Vdet1_D 0x0d 0x0E Vdet1_E 0x0e 0x0F Vdet1_F 0x0f Others Setting prohibited true LVD2LVL Voltage Detection 2 Level Select (Standard voltage during fall in voltage) 5 7 read-write 000 Vdet2_0 #000 001 Vdet2_1 #001 010 Vdet2_2 #010 011 Vdet2_3 #011 Others Setting prohibited true LVD1CR0 Voltage Monitor 1 Circuit Control Register 0 0x41A 8 read-write 0x80 0xf7 RIE Voltage Monitor 1 Interrupt/Reset Enable 0 0 read-write 0 Disable #0 1 Enable #1 CMPE Voltage Monitor 1 Circuit Comparison Result Output Enable 2 2 read-write 0 Disable voltage monitor 1 circuit comparison result output #0 1 Enable voltage monitor 1 circuit comparison result output #1 RI Voltage Monitor 1 Circuit Mode Select 6 6 read-write 0 Generate voltage monitor 1 interrupt on Vdet1 crossing #0 1 Enable voltage monitor 1 reset when the voltage falls to and below Vdet1 #1 RN Voltage Monitor 1 Reset Negate Select 7 7 read-write 0 Negate after a stabilization time (tLVD1) when VCC > Vdet1 is detected #0 1 Negate after a stabilization time (tLVD1) on assertion of the LVD1 reset #1 LVD2CR0 Voltage Monitor 2 Circuit Control Register 0 0x41B 8 read-write 0x80 0xf7 RIE Voltage Monitor 2 Interrupt/Reset Enable 0 0 read-write 0 Disable #0 1 Enable #1 CMPE Voltage Monitor 2 Circuit Comparison Result Output Enable 2 2 read-write 0 Disable voltage monitor 2 circuit comparison result output #0 1 Enable voltage monitor 2 circuit comparison result output #1 RI Voltage Monitor 2 Circuit Mode Select 6 6 read-write 0 Generate voltage monitor 2 interrupt on Vdet2 crossing #0 1 Enable voltage monitor 2 reset when the voltage falls to and below Vdet2 #1 RN Voltage Monitor 2 Reset Negate Select 7 7 read-write 0 Negate after a stabilization time (tLVD2) when VCC > Vdet2 is detected #0 1 Negate after a stabilization time (tLVD2) on assertion of the LVD2 reset #1 LOCOCR Low-Speed On-Chip Oscillator Control Register 0x490 8 read-write 0x00 0xff LCSTP LOCO Stop 0 0 read-write 0 Operate the LOCO clock #0 1 Stop the LOCO clock #1 LOCOUTCR LOCO User Trimming Control Register 0x492 8 read-write 0x00 0xff LOCOUTRM LOCO User Trimming 0 7 read-write PORT0 Port 0 Control Registers 0x40040000 0x00 12 registers PCNTR1 Port Control Register 1 0x000 32 read-write 0x00000000 0xffffffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 31 read-write 0 Low output #0 1 High output #1 PODR Port Control Register 1 PCNTR1 0x000 16 read-write 0x0000 0xffff PODR00 Pmn Output Data 0 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 15 read-write 0 Low output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x002 16 read-write 0x0000 0xffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCNTR2 Port Control Register 2 0x004 32 read-only 0x00000000 0xffff0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 PIDR Port Control Register 2 PCNTR2 0x006 16 read-only 0x0000 0x0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 PCNTR3 Port Control Register 3 0x008 32 write-only 0x00000000 0xffffffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR00 Pmn Output Reset 16 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 31 write-only 0 No effect on output #0 1 Low output #1 PORR Port Control Register 3 PCNTR3 0x008 16 write-only 0x0000 0xffff PORR00 Pmn Output Reset 0 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 15 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0x00A 16 write-only 0x0000 0xffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORT1 Port 1 Control Registers 0x40040020 0x00 16 registers PCNTR1 Port Control Register 1 0x000 32 read-write 0x00000000 0xffffffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 31 read-write 0 Low output #0 1 High output #1 PODR Port Control Register 1 PCNTR1 0x000 16 read-write 0x0000 0xffff PODR00 Pmn Output Data 0 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 15 read-write 0 Low output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x002 16 read-write 0x0000 0xffff PDR00 Pmn Direction 0 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCNTR2 Port Control Register 2 0x004 32 read-only 0x00000000 0xffff0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 EIDR00 Port Event Input Data 16 16 read-only 0 Low input #0 1 High input #1 EIDR01 Port Event Input Data 17 17 read-only 0 Low input #0 1 High input #1 EIDR02 Port Event Input Data 18 18 read-only 0 Low input #0 1 High input #1 EIDR03 Port Event Input Data 19 19 read-only 0 Low input #0 1 High input #1 EIDR04 Port Event Input Data 20 20 read-only 0 Low input #0 1 High input #1 EIDR05 Port Event Input Data 21 21 read-only 0 Low input #0 1 High input #1 EIDR06 Port Event Input Data 22 22 read-only 0 Low input #0 1 High input #1 EIDR07 Port Event Input Data 23 23 read-only 0 Low input #0 1 High input #1 EIDR08 Port Event Input Data 24 24 read-only 0 Low input #0 1 High input #1 EIDR09 Port Event Input Data 25 25 read-only 0 Low input #0 1 High input #1 EIDR10 Port Event Input Data 26 26 read-only 0 Low input #0 1 High input #1 EIDR11 Port Event Input Data 27 27 read-only 0 Low input #0 1 High input #1 EIDR12 Port Event Input Data 28 28 read-only 0 Low input #0 1 High input #1 EIDR13 Port Event Input Data 29 29 read-only 0 Low input #0 1 High input #1 EIDR14 Port Event Input Data 30 30 read-only 0 Low input #0 1 High input #1 EIDR15 Port Event Input Data 31 31 read-only 0 Low input #0 1 High input #1 EIDR Port Control Register 2 PCNTR2 0x004 16 read-only 0x0000 0xffff EIDR00 Port Event Input Data 0 0 read-only 0 Low input #0 1 High input #1 EIDR01 Port Event Input Data 1 1 read-only 0 Low input #0 1 High input #1 EIDR02 Port Event Input Data 2 2 read-only 0 Low input #0 1 High input #1 EIDR03 Port Event Input Data 3 3 read-only 0 Low input #0 1 High input #1 EIDR04 Port Event Input Data 4 4 read-only 0 Low input #0 1 High input #1 EIDR05 Port Event Input Data 5 5 read-only 0 Low input #0 1 High input #1 EIDR06 Port Event Input Data 6 6 read-only 0 Low input #0 1 High input #1 EIDR07 Port Event Input Data 7 7 read-only 0 Low input #0 1 High input #1 EIDR08 Port Event Input Data 8 8 read-only 0 Low input #0 1 High input #1 EIDR09 Port Event Input Data 9 9 read-only 0 Low input #0 1 High input #1 EIDR10 Port Event Input Data 10 10 read-only 0 Low input #0 1 High input #1 EIDR11 Port Event Input Data 11 11 read-only 0 Low input #0 1 High input #1 EIDR12 Port Event Input Data 12 12 read-only 0 Low input #0 1 High input #1 EIDR13 Port Event Input Data 13 13 read-only 0 Low input #0 1 High input #1 EIDR14 Port Event Input Data 14 14 read-only 0 Low input #0 1 High input #1 EIDR15 Port Event Input Data 15 15 read-only 0 Low input #0 1 High input #1 PIDR Port Control Register 2 PCNTR2 0x006 16 read-only 0x0000 0x0000 PIDR00 Pmn State 0 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 15 read-only 0 Low level #0 1 High level #1 PCNTR3 Port Control Register 3 0x008 32 write-only 0x00000000 0xffffffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PORR00 Pmn Output Reset 16 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 31 write-only 0 No effect on output #0 1 Low output #1 PORR Port Control Register 3 PCNTR3 0x008 16 write-only 0x0000 0xffff PORR00 Pmn Output Reset 0 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 15 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0x00A 16 write-only 0x0000 0xffff POSR00 Pmn Output Set 0 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 15 write-only 0 No effect on output #0 1 High output #1 PCNTR4 Port Control Register 4 0x00C 32 read-write 0x00000000 0xffffffff EOSR00 Pmn Event Output Set 0 0 read-write 0 No effect on output #0 1 High output #1 EOSR01 Pmn Event Output Set 1 1 read-write 0 No effect on output #0 1 High output #1 EOSR02 Pmn Event Output Set 2 2 read-write 0 No effect on output #0 1 High output #1 EOSR03 Pmn Event Output Set 3 3 read-write 0 No effect on output #0 1 High output #1 EOSR04 Pmn Event Output Set 4 4 read-write 0 No effect on output #0 1 High output #1 EOSR05 Pmn Event Output Set 5 5 read-write 0 No effect on output #0 1 High output #1 EOSR06 Pmn Event Output Set 6 6 read-write 0 No effect on output #0 1 High output #1 EOSR07 Pmn Event Output Set 7 7 read-write 0 No effect on output #0 1 High output #1 EOSR08 Pmn Event Output Set 8 8 read-write 0 No effect on output #0 1 High output #1 EOSR09 Pmn Event Output Set 9 9 read-write 0 No effect on output #0 1 High output #1 EOSR10 Pmn Event Output Set 10 10 read-write 0 No effect on output #0 1 High output #1 EOSR11 Pmn Event Output Set 11 11 read-write 0 No effect on output #0 1 High output #1 EOSR12 Pmn Event Output Set 12 12 read-write 0 No effect on output #0 1 High output #1 EOSR13 Pmn Event Output Set 13 13 read-write 0 No effect on output #0 1 High output #1 EOSR14 Pmn Event Output Set 14 14 read-write 0 No effect on output #0 1 High output #1 EOSR15 Pmn Event Output Set 15 15 read-write 0 No effect on output #0 1 High output #1 EORR00 Pmn Event Output Reset 16 16 read-write 0 No effect on output #0 1 Low output #1 EORR01 Pmn Event Output Reset 17 17 read-write 0 No effect on output #0 1 Low output #1 EORR02 Pmn Event Output Reset 18 18 read-write 0 No effect on output #0 1 Low output #1 EORR03 Pmn Event Output Reset 19 19 read-write 0 No effect on output #0 1 Low output #1 EORR04 Pmn Event Output Reset 20 20 read-write 0 No effect on output #0 1 Low output #1 EORR05 Pmn Event Output Reset 21 21 read-write 0 No effect on output #0 1 Low output #1 EORR06 Pmn Event Output Reset 22 22 read-write 0 No effect on output #0 1 Low output #1 EORR07 Pmn Event Output Reset 23 23 read-write 0 No effect on output #0 1 Low output #1 EORR08 Pmn Event Output Reset 24 24 read-write 0 No effect on output #0 1 Low output #1 EORR09 Pmn Event Output Reset 25 25 read-write 0 No effect on output #0 1 Low output #1 EORR10 Pmn Event Output Reset 26 26 read-write 0 No effect on output #0 1 Low output #1 EORR11 Pmn Event Output Reset 27 27 read-write 0 No effect on output #0 1 Low output #1 EORR12 Pmn Event Output Reset 28 28 read-write 0 No effect on output #0 1 Low output #1 EORR13 Pmn Event Output Reset 29 29 read-write 0 No effect on output #0 1 Low output #1 EORR14 Pmn Event Output Reset 30 30 read-write 0 No effect on output #0 1 Low output #1 EORR15 Pmn Event Output Reset 31 31 read-write 0 No effect on output #0 1 Low output #1 EORR Port Control Register 4 PCNTR4 0x00C 16 read-write 0x0000 0xffff EORR00 Pmn Event Output Reset 0 0 read-write 0 No effect on output #0 1 Low output #1 EORR01 Pmn Event Output Reset 1 1 read-write 0 No effect on output #0 1 Low output #1 EORR02 Pmn Event Output Reset 2 2 read-write 0 No effect on output #0 1 Low output #1 EORR03 Pmn Event Output Reset 3 3 read-write 0 No effect on output #0 1 Low output #1 EORR04 Pmn Event Output Reset 4 4 read-write 0 No effect on output #0 1 Low output #1 EORR05 Pmn Event Output Reset 5 5 read-write 0 No effect on output #0 1 Low output #1 EORR06 Pmn Event Output Reset 6 6 read-write 0 No effect on output #0 1 Low output #1 EORR07 Pmn Event Output Reset 7 7 read-write 0 No effect on output #0 1 Low output #1 EORR08 Pmn Event Output Reset 8 8 read-write 0 No effect on output #0 1 Low output #1 EORR09 Pmn Event Output Reset 9 9 read-write 0 No effect on output #0 1 Low output #1 EORR10 Pmn Event Output Reset 10 10 read-write 0 No effect on output #0 1 Low output #1 EORR11 Pmn Event Output Reset 11 11 read-write 0 No effect on output #0 1 Low output #1 EORR12 Pmn Event Output Reset 12 12 read-write 0 No effect on output #0 1 Low output #1 EORR13 Pmn Event Output Reset 13 13 read-write 0 No effect on output #0 1 Low output #1 EORR14 Pmn Event Output Reset 14 14 read-write 0 No effect on output #0 1 Low output #1 EORR15 Pmn Event Output Reset 15 15 read-write 0 No effect on output #0 1 Low output #1 EOSR Port Control Register 4 PCNTR4 0x00E 16 read-write 0x0000 0xffff EOSR00 Pmn Event Output Set 0 0 read-write 0 No effect on output #0 1 High output #1 EOSR01 Pmn Event Output Set 1 1 read-write 0 No effect on output #0 1 High output #1 EOSR02 Pmn Event Output Set 2 2 read-write 0 No effect on output #0 1 High output #1 EOSR03 Pmn Event Output Set 3 3 read-write 0 No effect on output #0 1 High output #1 EOSR04 Pmn Event Output Set 4 4 read-write 0 No effect on output #0 1 High output #1 EOSR05 Pmn Event Output Set 5 5 read-write 0 No effect on output #0 1 High output #1 EOSR06 Pmn Event Output Set 6 6 read-write 0 No effect on output #0 1 High output #1 EOSR07 Pmn Event Output Set 7 7 read-write 0 No effect on output #0 1 High output #1 EOSR08 Pmn Event Output Set 8 8 read-write 0 No effect on output #0 1 High output #1 EOSR09 Pmn Event Output Set 9 9 read-write 0 No effect on output #0 1 High output #1 EOSR10 Pmn Event Output Set 10 10 read-write 0 No effect on output #0 1 High output #1 EOSR11 Pmn Event Output Set 11 11 read-write 0 No effect on output #0 1 High output #1 EOSR12 Pmn Event Output Set 12 12 read-write 0 No effect on output #0 1 High output #1 EOSR13 Pmn Event Output Set 13 13 read-write 0 No effect on output #0 1 High output #1 EOSR14 Pmn Event Output Set 14 14 read-write 0 No effect on output #0 1 High output #1 EOSR15 Pmn Event Output Set 15 15 read-write 0 No effect on output #0 1 High output #1 PORT2 Port 2 Control Registers 0x40040040 PORT3 Port 3 Control Registers 0x40040060 PORT4 Port 4 Control Registers 0x40040080 PORT9 Port 9 Control Registers 0x40040120 PFS Pmn Pin Function Control Register 0x40040800 0x28 11 registers 0x38 27 registers 0x60 23 registers 0x80 8 registers 0x94 4 registers 0xC0 4 registers 0x100 11 registers 0x278 4 registers 0x503 1 registers 0x50F 1 registers 2 0x4 10-11 P0%sPFS Port 0%s Pin Function Select Register 0x028 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 2 0x4 10-11 P0%sPFS_HA Port 0%s Pin Function Select Register P0%sPFS 0x02A 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 2 0x4 10-11 P0%sPFS_BY Port 0%s Pin Function Select Register P0%sPFS 0x02B 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 2 0x4 14-15 P0%sPFS Port 0%s Pin Function Select Register 0x038 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 2 0x4 14-15 P0%sPFS_HA Port 0%s Pin Function Select Register P0%sPFS 0x03A 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 2 0x4 14-15 P0%sPFS_BY Port 0%s Pin Function Select Register P0%sPFS 0x03B 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 4 0x4 0-3 P10%sPFS Port 10%s Pin Function Select Register 0x040 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 4 0x4 0-3 P10%sPFS_HA Port 10%s Pin Function Select Register P10%sPFS 0x042 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 4 0x4 0-3 P10%sPFS_BY Port 10%s Pin Function Select Register P10%sPFS 0x043 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 P108PFS Port 108 Pin Function Select Register 0x060 32 read-write 0x00010010 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P108PFS_HA Port 108 Pin Function Select Register P108PFS 0x062 16 read-write 0x0010 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 P108PFS_BY Port 108 Pin Function Select Register P108PFS 0x063 8 read-write 0x10 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 P109PFS Port 109 Pin Function Select Register 0x064 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P109PFS_HA Port 109 Pin Function Select Register P109PFS 0x066 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 P109PFS_BY Port 109 Pin Function Select Register P109PFS 0x067 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 3 0x4 10-12 P1%sPFS Port 1%s Pin Function Select Register 0x068 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 3 0x4 10-12 P1%sPFS_HA Port 1%s Pin Function Select Register P1%sPFS 0x06A 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 3 0x4 10-12 P1%sPFS_BY Port 1%s Pin Function Select Register P1%sPFS 0x06B 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 P200PFS Port 200 Pin Function Select Register 0x080 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P200PFS_HA Port 200 Pin Function Select Register P200PFS 0x082 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 P200PFS_BY Port 200 Pin Function Select Register P200PFS 0x083 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 P201PFS Port 201 Pin Function Select Register 0x084 32 read-write 0x00000010 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P201PFS_HA Port 201 Pin Function Select Register P201PFS 0x086 16 read-write 0x0010 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 P201PFS_BY Port 201 Pin Function Select Register P201PFS 0x087 8 read-write 0x10 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 P205PFS Port 205 Pin Function Select Register 0x094 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P205PFS_HA Port 205 Pin Function Select Register P205PFS 0x096 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 EOFR Event on Falling/Event on Rising 12 13 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 P205PFS_BY Port 205 Pin Function Select Register P205PFS 0x097 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 P300PFS Port 300 Pin Function Select Register 0x0C0 32 read-write 0x00010000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P300PFS_HA Port 300 Pin Function Select Register P300PFS 0x0C2 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 P300PFS_BY Port 300 Pin Function Select Register P300PFS 0x0C3 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 2 0x4 0-1 P40%sPFS Port 40%s Pin Function Select Register 0x100 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write 2 0x4 0-1 P40%sPFS_HA Port 40%s Pin Function Select Register P40%sPFS 0x102 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 2 0x4 0-1 P40%sPFS_BY Port 40%s Pin Function Select Register P40%sPFS 0x103 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 P914PFS Port 914 Pin Function Select Register 0x278 32 read-write 0x00000000 0xfffffffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 PMR Port Mode Control 16 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PSEL Peripheral Select 24 28 read-write P914PFS_HA Port 914 Pin Function Select Register P914PFS 0x27A 16 read-write 0x0000 0xfffd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 ISEL IRQ Input Enable 14 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 ASEL Analog Input Enable 15 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 P914PFS_BY Port 914 Pin Function Select Register P914PFS 0x27B 8 read-write 0x00 0xfd PODR Port Output Data 0 0 read-write 0 Output low #0 1 Output high #1 PIDR Port State 1 1 read-only 0 Low level #0 1 High level #1 PDR Port Direction 2 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PCR Pull-up Control 4 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 NCODR N-Channel Open-Drain Control 6 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PWPR Write-Protect Register 0x503 8 read-write 0x80 0xff PFSWE PmnPFS Register Write Enable 6 6 read-write 0 Writing to the PmnPFS register is disabled #0 1 Writing to the PmnPFS register is enabled #1 B0WI PFSWE Bit Write Disable 7 7 read-write 0 Writing to the PFSWE bit is enabled #0 1 Writing to the PFSWE bit is disabled #1 PRWCNTR Port Read Wait Control Register 0x50F 8 read-write 0x01 0xff WAIT Wait Cycle Control 0 1 read-write 00 Setting prohibited #00 01 Insert a 1-cycle wait #01 10 Insert a 2-cycle wait #10 11 Insert a 3-cycle wait #11 ELC Event Link Controller 0x40041000 0x00 1 registers 0x02 4 registers 0x10 16 registers 0x30 8 registers 0x48 8 registers ELCR Event Link Controller Register 0x00 8 read-write 0x00 0xff ELCON All Event Link Enable 7 7 read-write 0 ELC function is disabled. #0 1 ELC function is enabled. #1 2 0x02 0-1 ELSEGR%s Event Link Software Event Generation Register %s 0x02 8 read-write 0x80 0xff SEG Software Event Generation 0 0 write-only 0 Normal operation #0 1 Software event is generated. #1 WE SEG Bit Write Enable 6 6 read-write 0 Write to SEG bit disabled. #0 1 Write to SEG bit enabled. #1 WI ELSEGR Register Write Disable 7 7 write-only 0 Write to ELSEGR register enabled. #0 1 Write to ELSEGR register disabled. #1 4 0x04 0-3 ELSR%s Event Link Setting Register %s 0x10 16 read-write 0x0000 0xffff ELS Event Link Select 0 7 read-write 2 0x04 8-9 ELSR%s Event Link Setting Register %s 0x30 16 read-write 0x0000 0xffff ELS Event Link Select 0 7 read-write 2 0x04 14-15 ELSR%s Event Link Setting Register %s 0x48 16 read-write 0x0000 0xffff ELS Event Link Select 0 7 read-write POEG Port Output Enable Module for GPT 0x40042000 0x00 4 registers 0x100 4 registers POEGGA POEG Group A Setting Register 0x000 32 read-write 0x00000000 0xffffffff PIDF Port Input Detection Flag 0 0 read-write 0 No output-disable request from the GTETRGn pin occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 IOCF Detection Flag for GPT Output-Disable Request 1 1 read-write 0 No output-disable request from GPT occurred. #0 1 Output-disable request from GPT occurred. #1 SSF Software Stop Flag 3 3 read-write 0 No output-disable request from software occurred #0 1 Output-disable request from software occurred #1 PIDE Port Input Detection Enable 4 4 read-write 0 Disable output-disable requests from the GTETRGn pins #0 1 Enable output-disable requests from the GTETRGn pins #1 IOCE Enable for GPT Output-Disable Request 5 5 read-write 0 Disable output-disable requests from GPT #0 1 Enable output-disable requests from GPT #1 ST GTETRGn Input Status Flag 16 16 read-only 0 GTETRGn input after filtering was 0 #0 1 GTETRGn input after filtering was 1 #1 INV GTETRGn Input Reverse 28 28 read-write 0 Input GTETRGn as-is #0 1 Input GTETRGn in reverse #1 NFEN Noise Filter Enable 29 29 read-write 0 Disable noise filtering #0 1 Enable noise filtering #1 NFCS Noise Filter Clock Select 30 31 read-write 00 Sample GTETRGn pin input level three times every PCLKB #00 01 Sample GTETRGn pin input level three times every PCLKB/8 #01 10 Sample GTETRGn pin input level three times every PCLKB/32 #10 11 Sample GTETRGn pin input level three times every PCLKB/128 #11 POEGGB POEG Group B Setting Register 0x100 32 read-write 0x00000000 0xffffffff PIDF Port Input Detection Flag 0 0 read-write 0 No output-disable request from the GTETRGn pin occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 IOCF Detection Flag for GPT Output-Disable Request 1 1 read-write 0 No output-disable request from GPT occurred. #0 1 Output-disable request from GPT occurred. #1 SSF Software Stop Flag 3 3 read-write 0 No output-disable request from software occurred #0 1 Output-disable request from software occurred #1 PIDE Port Input Detection Enable 4 4 read-write 0 Disable output-disable requests from the GTETRGn pins #0 1 Enable output-disable requests from the GTETRGn pins #1 IOCE Enable for GPT Output-Disable Request 5 5 read-write 0 Disable output-disable requests from GPT #0 1 Enable output-disable requests from GPT #1 ST GTETRGn Input Status Flag 16 16 read-only 0 GTETRGn input after filtering was 0 #0 1 GTETRGn input after filtering was 1 #1 INV GTETRGn Input Reverse 28 28 read-write 0 Input GTETRGn as-is #0 1 Input GTETRGn in reverse #1 NFEN Noise Filter Enable 29 29 read-write 0 Disable noise filtering #0 1 Enable noise filtering #1 NFCS Noise Filter Clock Select 30 31 read-write 00 Sample GTETRGn pin input level three times every PCLKB #00 01 Sample GTETRGn pin input level three times every PCLKB/8 #01 10 Sample GTETRGn pin input level three times every PCLKB/32 #10 11 Sample GTETRGn pin input level three times every PCLKB/128 #11 WDT Watchdog Timer 0x40044200 0x00 1 registers 0x02 5 registers 0x08 1 registers WDTRR WDT Refresh Register 0x00 8 read-write 0xff 0xff WDTCR WDT Control Register 0x02 16 read-write 0x33f3 0xffff TOPS Timeout Period Select 0 1 read-write 00 1024 cycles (0x03FF) #00 01 4096 cycles (0x0FFF) #01 10 8192 cycles (0x1FFF) #10 11 16384 cycles (0x3FFF) #11 CKS Clock Division Ratio Select 4 7 read-write 0x1 PCLKB/4 0x1 0x4 PCLKB/64 0x4 0xF PCLKB/128 0xf 0x6 PCLKB/512 0x6 0x7 PCLKB/2048 0x7 0x8 PCLKB/8192 0x8 Others Setting prohibited true RPES Window End Position Select 8 9 read-write 00 75% #00 01 50% #01 10 25% #10 11 0% (do not specify window end position). #11 RPSS Window Start Position Select 12 13 read-write 00 25% #00 01 50% #01 10 75% #10 11 100% (do not specify window start position). #11 WDTSR WDT Status Register 0x04 16 read-write 0x0000 0xffff CNTVAL Down-Counter Value 0 13 read-only UNDFF Underflow Flag 14 14 read-write 0 No underflow occurred #0 1 Underflow occurred #1 REFEF Refresh Error Flag 15 15 read-write 0 No refresh error occurred #0 1 Refresh error occurred #1 WDTRCR WDT Reset Control Register 0x06 8 read-write 0x80 0xff RSTIRQS WDT Behavior Selection 7 7 read-write 0 Interrupt #0 1 Reset #1 WDTCSTPR WDT Count Stop Control Register 0x08 8 read-write 0x80 0xff SLCSTP Sleep-Mode Count Stop Control Register 7 7 read-write 0 Disable count stop #0 1 Stop count on transition to Sleep mode #1 IWDT Independent Watchdog Timer 0x40044400 0x00 1 registers 0x04 2 registers IWDTRR IWDT Refresh Register 0x00 8 read-write 0xff 0xff IWDTSR IWDT Status Register 0x04 16 read-write 0x0000 0xffff CNTVAL Down-counter Value 0 13 read-only UNDFF Underflow Flag 14 14 read-write 0 No underflow occurred #0 1 Underflow occurred #1 REFEF Refresh Error Flag 15 15 read-write 0 No refresh error occurred #0 1 Refresh error occurred #1 CAC Clock Frequency Accuracy Measurement Circuit 0x40044600 0x00 5 registers 0x06 6 registers CACR0 CAC Control Register 0 0x00 8 read-write 0x00 0xff CFME Clock Frequency Measurement Enable 0 0 read-write 0 Disable #0 1 Enable #1 CACR1 CAC Control Register 1 0x01 8 read-write 0x00 0xff CACREFE CACREF Pin Input Enable 0 0 read-write 0 Disable #0 1 Enable #1 FMCS Measurement Target Clock Select 1 3 read-write 000 Setting prohibited #000 001 Setting prohibited #001 010 HOCO clock #010 011 MOCO #011 100 LOCO clock #100 101 Peripheral module clock B (PCLKB) #101 110 IWDT-dedicated clock #110 111 Setting prohibited #111 TCSS Timer Count Clock Source Select 4 5 read-write 00 No division #00 01 x 1/4 clock #01 10 x 1/8 clock #10 11 x 1/32 clock #11 EDGES Valid Edge Select 6 7 read-write 00 Rising edge #00 01 Falling edge #01 10 Both rising and falling edges #10 11 Setting prohibited #11 CACR2 CAC Control Register 2 0x02 8 read-write 0x00 0xff RPS Reference Signal Select 0 0 read-write 0 CACREF pin input #0 1 Internal clock (internally generated signal) #1 RSCS Measurement Reference Clock Select 1 3 read-write 000 Setting prohibited #000 001 Setting prohibited #001 010 HOCO clock #010 011 MOCO #011 100 LOCO clock #100 101 Peripheral module clock B (PCLKB) #101 110 IWDT-dedicated clock #110 111 Setting prohibited #111 RCDS Measurement Reference Clock Frequency Division Ratio Select 4 5 read-write 00 x 1/32 clock #00 01 x 1/128 clock #01 10 x 1/1024 clock #10 11 x 1/8192 clock #11 DFS Digital Filter Select 6 7 read-write 00 Disable digital filtering #00 01 Use sampling clock for the digital filter as the frequency measuring clock #01 10 Use sampling clock for the digital filter as the frequency measuring clock divided by 4 #10 11 Use sampling clock for the digital filter as the frequency measuring clock divided by 16. #11 CAICR CAC Interrupt Control Register 0x03 8 read-write 0x00 0xff FERRIE Frequency Error Interrupt Request Enable 0 0 read-write 0 Disable #0 1 Enable #1 MENDIE Measurement End Interrupt Request Enable 1 1 read-write 0 Disable #0 1 Enable #1 OVFIE Overflow Interrupt Request Enable 2 2 read-write 0 Disable #0 1 Enable #1 FERRFCL FERRF Clear 4 4 write-only 0 No effect #0 1 The CASTR.FERRF flag is cleared #1 MENDFCL MENDF Clear 5 5 write-only 0 No effect #0 1 The CASTR.MENDF flag is cleared #1 OVFFCL OVFF Clear 6 6 write-only 0 No effect #0 1 The CASTR.OVFF flag is cleared. #1 CASTR CAC Status Register 0x04 8 read-only 0x00 0xff FERRF Frequency Error Flag 0 0 read-only 0 Clock frequency is within the allowable range #0 1 Clock frequency has deviated beyond the allowable range (frequency error). #1 MENDF Measurement End Flag 1 1 read-only 0 Measurement is in progress #0 1 Measurement ended #1 OVFF Overflow Flag 2 2 read-only 0 Counter has not overflowed #0 1 Counter overflowed #1 CAULVR CAC Upper-Limit Value Setting Register 0x06 16 read-write 0x0000 0xffff CALLVR CAC Lower-Limit Value Setting Register 0x08 16 read-write 0x0000 0xffff CACNTBR CAC Counter Buffer Register 0x0A 16 read-only 0x0000 0xffff MSTP Module Stop Control B, C, D 0x40047000 0x00 14 registers MSTPCRB Module Stop Control Register B 0x000 32 read-write 0xffffffff 0xffffffff MSTPB9 IIC/I3C Bus Interface 0 Module Stop 9 9 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB19 Serial Peripheral Interface 0 Module Stop 19 19 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB22 Serial Communication Interface 9 Module Stop 22 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRC Module Stop Control Register C 0x004 32 read-write 0xffffffff 0xffffffff MSTPC0 Clock Frequency Accuracy Measurement Circuit Module Stop 0 0 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC1 Cyclic Redundancy Check Calculator Module Stop 1 1 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC13 Data Operation Circuit Module Stop 13 13 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC14 Event Link Controller Module Stop 14 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC28 True Random Number Generator Module Stop 28 28 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC31 AES Module Stop 31 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRD Module Stop Control Register D 0x008 32 read-write 0xffffffff 0xffffffff MSTPD2 Low Power Asynchronous General Purpose Timer 1 Module Stop 2 2 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD3 Low Power Asynchronous General Purpose Timer 0 Module Stop 3 3 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD6 General PWM Timer 164 to 169 and PWM Delay Generation Circuit Module Stop 6 6 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD14 Port Output Enable for GPT Module Stop 14 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD16 12-bit A/D Converter Module Stop 16 16 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 LSMRWDIS Low Speed Module R/W Disable Control Register 0x00C 16 read-write 0x0000 0xffff WDTDIS WDT Operate Clock Control 1 1 read-write 0 WDT operates as normal #0 1 Stop the WDT clock and register R/W clock #1 IWDTIDS IWDT Register Clock Control 2 2 read-write 0 IWDT operates as normal #0 1 Stop the IWDT register R/W clock #1 WREN Write Enable for bits [2:0] 7 7 read-write 0 Write protect for bits [2:0] #0 1 Write enable for bits [2:0] #1 PRKEY LSMRWDIS Key Code 8 15 write-only DOC Data Operation Circuit 0x40054100 0x00 1 registers 0x02 4 registers DOCR DOC Control Register 0x00 8 read-write 0x00 0xff OMS Operating Mode Select 0 1 read-write 00 Data comparison mode #00 01 Data addition mode #01 10 Data subtraction mode #10 11 Setting prohibited #11 DCSEL Detection Condition Select 2 2 read-write 0 Set DOPCF flag when data mismatch is detected #0 1 Set DOPCF flag when data match is detected #1 DOPCF DOC Flag 5 5 read-only DOPCFCL DOPCF Clear 6 6 read-write 0 Retain DOPCF flag state #0 1 Clear DOPCF flag #1 DODIR DOC Data Input Register 0x02 16 read-write 0x0000 0xffff DODSR DOC Data Setting Register 0x04 16 read-write 0x0000 0xffff ADC120 12-bit A/D Converter 0x4005C000 0x00 2 registers 0x04 9 registers 0x0E 18 registers 0x2A 4 registers 0x32 4 registers 0x46 8 registers 0x7A 1 registers 0x7E 1 registers 0x80 2 registers 0x84 4 registers 0x8A 1 registers 0x8C 1 registers 0x90 21 registers 0xA6 1 registers 0xA8 5 registers 0xDD 3 registers 0xE5 2 registers 0xE9 2 registers ADCSR A/D Control Register 0x000 16 read-write 0x0000 0xffff DBLANS Double Trigger Channel Select 0 4 read-write GBADIE Group B Scan End Interrupt and ELC Event Enable 6 6 read-write 0 Disable ADC120_GBADI interrupt generation on group B scan completion. #0 1 Enable ADC120_GBADI interrupt generation on group B scan completion. #1 DBLE Double Trigger Mode Select 7 7 read-write 0 Deselect double-trigger mode. #0 1 Select double-trigger mode. #1 EXTRG Trigger Select 8 8 read-write 0 Start A/D conversion by the synchronous trigger (ELC). #0 1 Start A/D conversion by the asynchronous trigger (ADTRG0). #1 TRGE Trigger Start Enable 9 9 read-write 0 Disable A/D conversion to be started by the synchronous or asynchronous trigger #0 1 Enable A/D conversion to be started by the synchronous or asynchronous trigger #1 ADHSC A/D Conversion Mode Select 10 10 read-write 0 High-speed A/D conversion mode #0 1 Low-power A/D conversion mode #1 ADCS Scan Mode Select 13 14 read-write 00 Single scan mode #00 01 Group scan mode #01 10 Continuous scan mode #10 11 Setting prohibited #11 ADST A/D Conversion Start 15 15 read-write 0 Stop A/D conversion process. #0 1 Start A/D conversion process. #1 ADANSA0 A/D Channel Select Register A0 0x004 16 read-write 0x0000 0xffff ANSA00 A/D Conversion Channels Select 0 0 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA01 A/D Conversion Channels Select 1 1 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA02 A/D Conversion Channels Select 2 2 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA03 A/D Conversion Channels Select 3 3 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA04 A/D Conversion Channels Select 4 4 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA05 A/D Conversion Channels Select 5 5 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA06 A/D Conversion Channels Select 6 6 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA07 A/D Conversion Channels Select 7 7 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA08 A/D Conversion Channels Select 8 8 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA09 A/D Conversion Channels Select 9 9 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA10 A/D Conversion Channels Select 10 10 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA11 A/D Conversion Channels Select 11 11 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA12 A/D Conversion Channels Select 12 12 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA13 A/D Conversion Channels Select 13 13 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA14 A/D Conversion Channels Select 14 14 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA15 A/D Conversion Channels Select 15 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADANSA1 A/D Channel Select Register A1 0x006 16 read-write 0x0000 0xffff ANSA16 A/D Conversion Channels Select 0 0 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA17 A/D Conversion Channels Select 1 1 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA18 A/D Conversion Channels Select 2 2 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA19 A/D Conversion Channels Select 3 3 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA20 A/D Conversion Channels Select 4 4 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA21 A/D Conversion Channels Select 5 5 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA22 A/D Conversion Channels Select 6 6 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA23 A/D Conversion Channels Select 7 7 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA24 A/D Conversion Channels Select 8 8 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA25 A/D Conversion Channels Select 9 9 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA26 A/D Conversion Channels Select 10 10 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA27 A/D Conversion Channels Select 11 11 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA28 A/D Conversion Channels Select 12 12 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA29 A/D Conversion Channels Select 13 13 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA30 A/D Conversion Channels Select 14 14 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSA31 A/D Conversion Channels Select 15 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADADS0 A/D-Converted Value Addition/Average Channel Select Register 0 0x008 16 read-write 0x0000 0xffff ADS00 A/D-Converted Value Addition/Average Channel Select 0 0 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS01 A/D-Converted Value Addition/Average Channel Select 1 1 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS02 A/D-Converted Value Addition/Average Channel Select 2 2 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS03 A/D-Converted Value Addition/Average Channel Select 3 3 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS04 A/D-Converted Value Addition/Average Channel Select 4 4 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS05 A/D-Converted Value Addition/Average Channel Select 5 5 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS06 A/D-Converted Value Addition/Average Channel Select 6 6 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS07 A/D-Converted Value Addition/Average Channel Select 7 7 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS08 A/D-Converted Value Addition/Average Channel Select 8 8 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS09 A/D-Converted Value Addition/Average Channel Select 9 9 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS10 A/D-Converted Value Addition/Average Channel Select 10 10 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS11 A/D-Converted Value Addition/Average Channel Select 11 11 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS12 A/D-Converted Value Addition/Average Channel Select 12 12 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS13 A/D-Converted Value Addition/Average Channel Select 13 13 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS14 A/D-Converted Value Addition/Average Channel Select 14 14 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS15 A/D-Converted Value Addition/Average Channel Select 15 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADADS1 A/D-Converted Value Addition/Average Channel Select Register 1 0x00A 16 read-write 0x0000 0xffff ADS16 A/D-Converted Value Addition/Average Channel Select 0 0 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS17 A/D-Converted Value Addition/Average Channel Select 1 1 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS18 A/D-Converted Value Addition/Average Channel Select 2 2 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS19 A/D-Converted Value Addition/Average Channel Select 3 3 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS20 A/D-Converted Value Addition/Average Channel Select 4 4 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS21 A/D-Converted Value Addition/Average Channel Select 5 5 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS22 A/D-Converted Value Addition/Average Channel Select 6 6 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS23 A/D-Converted Value Addition/Average Channel Select 7 7 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS24 A/D-Converted Value Addition/Average Channel Select 8 8 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS25 A/D-Converted Value Addition/Average Channel Select 9 9 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS26 A/D-Converted Value Addition/Average Channel Select 10 10 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS27 A/D-Converted Value Addition/Average Channel Select 11 11 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS28 A/D-Converted Value Addition/Average Channel Select 12 12 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS29 A/D-Converted Value Addition/Average Channel Select 13 13 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS30 A/D-Converted Value Addition/Average Channel Select 14 14 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADS31 A/D-Converted Value Addition/Average Channel Select 15 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADADC A/D-Converted Value Addition/Average Count Select Register 0x00C 8 read-write 0x00 0xff ADC Addition/Average Count Select 0 2 read-write 000 1-time conversion (no addition, same as normal conversion) #000 001 2-time conversion (1 addition) #001 010 3-time conversion (2 additions) #010 011 4-time conversion (3 additions) #011 101 16-time conversion (15 additions) #101 Others Setting prohibited true AVEE Average Mode Select 7 7 read-write 0 Enable addition mode #0 1 Enable average mode #1 ADCER A/D Control Extended Register 0x00E 16 read-write 0x0000 0xffff ACE A/D Data Register Automatic Clearing Enable 5 5 read-write 0 Disable automatic clearing #0 1 Enable automatic clearing #1 DIAGVAL Self-Diagnosis Conversion Voltage Select 8 9 read-write 00 Setting prohibited when self-diagnosis is enabled #00 01 0 volts #01 10 Reference voltage × 1/2 #10 11 Reference voltage #11 DIAGLD Self-Diagnosis Mode Select 10 10 read-write 0 Select rotation mode for self-diagnosis voltage #0 1 Select mixed mode for self-diagnosis voltage #1 DIAGM Self-Diagnosis Enable 11 11 read-write 0 Disable ADC12 self-diagnosis #0 1 Enable ADC12 self-diagnosis #1 ADRFMT A/D Data Register Format Select 15 15 read-write 0 Select right-justified for the A/D data register format #0 1 Select left-justified for the A/D data register format #1 ADSTRGR A/D Conversion Start Trigger Select Register 0x010 16 read-write 0x0000 0xffff TRSB A/D Conversion Start Trigger Select for Group B 0 5 read-write TRSA A/D Conversion Start Trigger Select 8 13 read-write ADEXICR A/D Conversion Extended Input Control Registers 0x012 16 read-write 0x0000 0xffff TSSAD Temperature Sensor Output A/D-Converted Value Addition/Average Mode Select 0 0 read-write 0 Do not select addition/average mode for temperature sensor output. #0 1 Select addition/average mode for temperature sensor output. #1 OCSAD Internal Reference Voltage A/D-Converted Value Addition/Average Mode Select 1 1 read-write 0 Do not select addition/average mode for internal reference voltage. #0 1 Select addition/average mode for internal reference voltage. #1 TSSA Temperature Sensor Output A/D Conversion Select 8 8 read-write 0 Disable A/D conversion of temperature sensor output #0 1 Enable A/D conversion of temperature sensor output #1 OCSA Internal Reference Voltage A/D Conversion Select 9 9 read-write 0 Disable A/D conversion of internal reference voltage #0 1 Enable A/D conversion of internal reference voltage #1 ADANSB0 A/D Channel Select Register B0 0x014 16 read-write 0x0000 0xffff ANSB00 A/D Conversion Channels Select 0 0 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB01 A/D Conversion Channels Select 1 1 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB02 A/D Conversion Channels Select 2 2 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB03 A/D Conversion Channels Select 3 3 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB04 A/D Conversion Channels Select 4 4 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB05 A/D Conversion Channels Select 5 5 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB06 A/D Conversion Channels Select 6 6 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB07 A/D Conversion Channels Select 7 7 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB08 A/D Conversion Channels Select 8 8 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB09 A/D Conversion Channels Select 9 9 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB10 A/D Conversion Channels Select 10 10 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB11 A/D Conversion Channels Select 11 11 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB12 A/D Conversion Channels Select 12 12 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB13 A/D Conversion Channels Select 13 13 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB14 A/D Conversion Channels Select 14 14 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB15 A/D Conversion Channels Select 15 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADANSB1 A/D Channel Select Register B1 0x016 16 read-write 0x0000 0xffff ANSB16 A/D Conversion Channels Select 0 0 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB17 A/D Conversion Channels Select 1 1 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB18 A/D Conversion Channels Select 2 2 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB19 A/D Conversion Channels Select 3 3 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB20 A/D Conversion Channels Select 4 4 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB21 A/D Conversion Channels Select 5 5 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB22 A/D Conversion Channels Select 6 6 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB23 A/D Conversion Channels Select 7 7 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB24 A/D Conversion Channels Select 8 8 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB25 A/D Conversion Channels Select 9 9 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB26 A/D Conversion Channels Select 10 10 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB27 A/D Conversion Channels Select 11 11 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB28 A/D Conversion Channels Select 12 12 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB29 A/D Conversion Channels Select 13 13 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB30 A/D Conversion Channels Select 14 14 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ANSB31 A/D Conversion Channels Select 15 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADDBLDR A/D Data Duplexing Register 0x018 16 read-only 0x0000 0xffff ADDBLDR Converted Value 15 to 0 0 15 read-only ADTSDR A/D Temperature Sensor Data Register 0x01A 16 read-only 0x0000 0xffff ADTSDR Converted Value 15 to 0 0 15 read-only ADOCDR A/D Internal Reference Voltage Data Register 0x01C 16 read-only 0x0000 0xffff ADOCDR Converted Value 15 to 0 0 15 read-only ADRD A/D Self-Diagnosis Data Register 0x01E 16 read-only 0x0000 0xffff AD Converted Value 11 to 0 0 11 read-only DIAGST Self-Diagnosis Status 14 15 read-only 00 Self-diagnosis not executed after power-on. #00 01 Self-diagnosis was executed using the 0 V voltage. #01 10 Self-diagnosis was executed using the reference voltage × 1/2. #10 11 Self-diagnosis was executed using the reference voltage . #11 2 0x2 5-6 ADDR%s A/D Data Registers %s 0x02A 16 read-only 0x0000 0xffff ADDR Converted Value 15 to 0 0 15 read-only 2 0x2 9-10 ADDR%s A/D Data Registers %s 0x032 16 read-only 0x0000 0xffff ADDR Converted Value 15 to 0 0 15 read-only 4 0x2 19-22 ADDR%s A/D Data Registers %s 0x046 16 read-only 0x0000 0xffff ADDR Converted Value 15 to 0 0 15 read-only ADDISCR A/D Disconnection Detection Control Register 0x07A 8 read-write 0x00 0xff ADNDIS Disconnection Detection Assist Setting 0 3 read-write 0x0 The disconnection detection assist function is disabled 0x0 0x1 Setting prohibited 0x1 Others The number of states for the discharge or precharge period. true PCHG Precharge/discharge select 4 4 read-write 0 Discharge #0 1 Precharge #1 ADACSR A/D Conversion Operation Mode Select Register 0x07E 8 read-write 0x00 0xff ADSAC Successive Approximation Control Setting 1 1 read-write 0 Normal conversion mode (default) #0 1 Fast conversion mode #1 ADGSPCR A/D Group Scan Priority Control Register 0x080 16 read-write 0x0000 0xffff PGS Group Priority Operation Setting 0 0 read-write 0 Operate without group priority control. #0 1 Operate with group priority control. #1 GBRSCN Lower-Priority Group Restart Setting 1 1 read-write 0 Disable rescanning of the group that was stopped in group priority operation #0 1 Enable rescanning of the group that was stopped in group priority operation. #1 GBRP Single Scan Continuous Start 15 15 read-write 0 Single scan is not continuously activated. #0 1 Single scan for the group with the lower-priority is continuously activated. #1 ADDBLDRA A/D Data Duplexing Register A 0x084 16 read-only 0x0000 0xffff ADDBLDR Converted Value 15 to 0 0 15 read-only ADDBLDRB A/D Data Duplexing Register B 0x086 16 read-only 0x0000 0xffff ADDBLDR Converted Value 15 to 0 0 15 read-only ADHVREFCNT A/D High-Potential/Low-Potential Reference Voltage Control Register 0x08A 8 read-write 0x00 0xff HVSEL High-Potential Reference Voltage Select 0 1 read-write 00 AVCC0 is selected as the high-potential reference voltage #00 01 VREFH0 is selected as the high-potential reference voltage #01 10 Internal reference voltage is selected as the high-potential reference voltage #10 11 No reference voltage pin is selected (internal node discharge) #11 LVSEL Low-Potential Reference Voltage Select 4 4 read-write 0 AVSS0 is selected as the low-potential reference voltage. #0 1 VREFL0 is selected as the low-potential reference voltage. #1 ADSLP Sleep 7 7 read-write 0 Normal operation #0 1 Standby state #1 ADWINMON A/D Compare Function Window A/B Status Monitor Register 0x08C 8 read-only 0x00 0xff MONCOMB Combination Result Monitor 0 0 read-only 0 Window A/B composite conditions are not met. #0 1 Window A/B composite conditions are met. #1 MONCMPA Comparison Result Monitor A 4 4 read-only 0 Window A comparison conditions are not met. #0 1 Window A comparison conditions are met. #1 MONCMPB Comparison Result Monitor B 5 5 read-only 0 Window B comparison conditions are not met. #0 1 Window B comparison conditions are met. #1 ADCMPCR A/D Compare Function Control Register 0x090 16 read-write 0x0000 0xffff CMPAB Window A/B Composite Conditions Setting 0 1 read-write 00 Output ADC120_WCMPM when window A OR window B comparison conditions are met. Otherwise, output ADC120_WCMPUM. #00 01 Output ADC120_WCMPM when window A EXOR window B comparison conditions are met. Otherwise, output ADC120_WCMPUM. #01 10 Output ADC120_WCMPM when window A AND window B comparison conditions are met. Otherwise, output ADC120_WCMPUM. #10 11 Setting prohibited. #11 CMPBE Compare Window B Operation Enable 9 9 read-write 0 Disable compare window B operation. Disable ADC120_WCMPM and ADC120_WCMPUM outputs. #0 1 Enable compare window B operation. #1 CMPAE Compare Window A Operation Enable 11 11 read-write 0 Disable compare window A operation. Disable ADC120_WCMPM and ADC120_WCMPUM outputs. #0 1 Enable compare window A operation. #1 CMPBIE Compare B Interrupt Enable 13 13 read-write 0 Disable ADC120_CMPBI interrupt when comparison conditions (window B) are met. #0 1 Enable ADC120_CMPBI interrupt when comparison conditions (window B) are met. #1 WCMPE Window Function Setting 14 14 read-write 0 Disable window function Window A and window B operate as a comparator to compare the single value on the lower side with the A/D conversion result. #0 1 Enable window function Window A and window B operate as a comparator to compare the two values on the upper and lower sides with the A/D conversion result. #1 CMPAIE Compare A Interrupt Enable 15 15 read-write 0 Disable ADC120_CMPAI interrupt when comparison conditions (window A) are met. #0 1 Enable ADC120_CMPAI interrupt when comparison conditions (window A) are met. #1 ADCMPANSER A/D Compare Function Window A Extended Input Select Register 0x092 8 read-write 0x00 0xff CMPTSA Temperature Sensor Output Compare Select 0 0 read-write 0 Exclude the temperature sensor output from the compare Window A target range. #0 1 Include the temperature sensor output in the compare Window A target range. #1 CMPOCA Internal Reference Voltage Compare Select 1 1 read-write 0 Exclude the internal reference voltage from the compare Window A target range. #0 1 Include the internal reference voltage in the compare Window A target range. #1 ADCMPLER A/D Compare Function Window A Extended Input Comparison Condition Setting Register 0x093 8 read-write 0x00 0xff CMPLTSA Compare Window A Temperature Sensor Output Comparison Condition Select 0 0 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0) : ADCMPDR0 value > A/D-converted valueCompare Window A Temperature Sensor Output Comparison Condition Select When window function is enabled (ADCMPCR.WCMPE = 1) : Compare Window A Temperature Sensor Output Comparison ConditionA/D-converted value < ADCMPDR0 value, or A/D-converted value > ADCMPDR1 value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0) : ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1) : ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLOCA Compare Window A Internal Reference Voltage Comparison Condition Select 1 1 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0) : ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or A/D-converted value > ADCMPDR1 value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 ADCMPANSR0 A/D Compare Function Window A Channel Select Register 0 0x094 16 read-write 0x0000 0xffff CMPCHA00 Compare Window A Channel Select 0 0 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA01 Compare Window A Channel Select 1 1 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA02 Compare Window A Channel Select 2 2 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA03 Compare Window A Channel Select 3 3 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA04 Compare Window A Channel Select 4 4 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA05 Compare Window A Channel Select 5 5 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA06 Compare Window A Channel Select 6 6 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA07 Compare Window A Channel Select 7 7 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA08 Compare Window A Channel Select 8 8 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA09 Compare Window A Channel Select 9 9 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA10 Compare Window A Channel Select 10 10 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA11 Compare Window A Channel Select 11 11 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA12 Compare Window A Channel Select 12 12 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA13 Compare Window A Channel Select 13 13 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA14 Compare Window A Channel Select 14 14 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA15 Compare Window A Channel Select 15 15 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 ADCMPANSR1 A/D Compare Function Window A Channel Select Register 1 0x096 16 read-write 0x0000 0xffff CMPCHA16 Compare Window A Channel Select 0 0 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA17 Compare Window A Channel Select 1 1 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA18 Compare Window A Channel Select 2 2 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA19 Compare Window A Channel Select 3 3 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA20 Compare Window A Channel Select 4 4 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA21 Compare Window A Channel Select 5 5 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA22 Compare Window A Channel Select 6 6 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA23 Compare Window A Channel Select 7 7 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA24 Compare Window A Channel Select 8 8 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA25 Compare Window A Channel Select 9 9 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA26 Compare Window A Channel Select 10 10 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA27 Compare Window A Channel Select 11 11 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA28 Compare Window A Channel Select 12 12 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA29 Compare Window A Channel Select 13 13 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA30 Compare Window A Channel Select 14 14 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 CMPCHA31 Compare Window A Channel Select 15 15 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 ADCMPLR0 A/D Compare Function Window A Comparison Condition Setting Register 0 0x098 16 read-write 0x0000 0xffff CMPLCHA00 Compare Window A Comparison Condition Select 0 0 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA01 Compare Window A Comparison Condition Select 1 1 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA02 Compare Window A Comparison Condition Select 2 2 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA03 Compare Window A Comparison Condition Select 3 3 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA04 Compare Window A Comparison Condition Select 4 4 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA05 Compare Window A Comparison Condition Select 5 5 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA06 Compare Window A Comparison Condition Select 6 6 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA07 Compare Window A Comparison Condition Select 7 7 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA08 Compare Window A Comparison Condition Select 8 8 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA09 Compare Window A Comparison Condition Select 9 9 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA10 Compare Window A Comparison Condition Select 10 10 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA11 Compare Window A Comparison Condition Select 11 11 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA12 Compare Window A Comparison Condition Select 12 12 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA13 Compare Window A Comparison Condition Select 13 13 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA14 Compare Window A Comparison Condition Select 14 14 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA15 Compare Window A Comparison Condition Select 15 15 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 ADCMPLR1 A/D Compare Function Window A Comparison Condition Setting Register 1 0x09A 16 read-write 0x0000 0xffff CMPLCHA16 Compare Window A Comparison Condition Select 0 0 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA17 Compare Window A Comparison Condition Select 1 1 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA18 Compare Window A Comparison Condition Select 2 2 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA19 Compare Window A Comparison Condition Select 3 3 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA20 Compare Window A Comparison Condition Select 4 4 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA21 Compare Window A Comparison Condition Select 5 5 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA22 Compare Window A Comparison Condition Select 6 6 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA23 Compare Window A Comparison Condition Select 7 7 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA24 Compare Window A Comparison Condition Select 8 8 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA25 Compare Window A Comparison Condition Select 9 9 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA26 Compare Window A Comparison Condition Select 10 10 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA27 Compare Window A Comparison Condition Select 11 11 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA28 Compare Window A Comparison Condition Select 12 12 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA29 Compare Window A Comparison Condition Select 13 13 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA30 Compare Window A Comparison Condition Select 14 14 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLCHA31 Compare Window A Comparison Condition Select 15 15 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 2 0x2 0-1 ADCMPDR%s A/D Compare Function Window A Lower-Side/Upper-Side Level Setting Register 0x09C 16 read-write 0x0000 0xffff ADCMPSR0 A/D Compare Function Window A Channel Status Register 0 0x0A0 16 read-write 0x0000 0xffff CMPSTCHA00 Compare Window A Flag 0 0 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA01 Compare Window A Flag 1 1 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA02 Compare Window A Flag 2 2 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA03 Compare Window A Flag 3 3 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA04 Compare Window A Flag 4 4 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA05 Compare Window A Flag 5 5 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA06 Compare Window A Flag 6 6 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA07 Compare Window A Flag 7 7 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA08 Compare Window A Flag 8 8 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA09 Compare Window A Flag 9 9 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA10 Compare Window A Flag 10 10 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA11 Compare Window A Flag 11 11 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA12 Compare Window A Flag 12 12 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA13 Compare Window A Flag 13 13 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA14 Compare Window A Flag 14 14 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA15 Compare Window A Flag 15 15 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPSR1 A/D Compare Function Window A Channel Status Register1 0x0A2 16 read-write 0x0000 0xffff CMPSTCHA16 Compare Window A Flag 0 0 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA17 Compare Window A Flag 1 1 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA18 Compare Window A Flag 2 2 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA19 Compare Window A Flag 3 3 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA20 Compare Window A Flag 4 4 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA21 Compare Window A Flag 5 5 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA22 Compare Window A Flag 6 6 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA23 Compare Window A Flag 7 7 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA24 Compare Window A Flag 8 8 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA25 Compare Window A Flag 9 9 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA26 Compare Window A Flag 10 10 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA27 Compare Window A Flag 11 11 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA28 Compare Window A Flag 12 12 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA29 Compare Window A Flag 13 13 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA30 Compare Window A Flag 14 14 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA31 Compare Window A Flag 15 15 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPSER A/D Compare Function Window A Extended Input Channel Status Register 0x0A4 8 read-write 0x00 0xff CMPSTTSA Compare Window A Temperature Sensor Output Compare Flag 0 0 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTOCA Compare Window A Internal Reference Voltage Compare Flag 1 1 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPBNSR A/D Compare Function Window B Channel Select Register 0x0A6 8 read-write 0x00 0xff CMPCHB Compare Window B Channel Select 0 5 read-write CMPLB Compare Window B Comparison Condition Setting 7 7 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADWINLLB value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADWINLLB value, or ADWINULB value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADWINLLB value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADWINLLB value < A/D-converted value < ADWINULB value #1 ADWINLLB A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register 0x0A8 16 read-write 0x0000 0xffff ADWINULB A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register 0x0AA 16 read-write 0x0000 0xffff ADCMPBSR A/D Compare Function Window B Status Register 0x0AC 8 read-write 0x00 0xff CMPSTB Compare Window B Flag 0 0 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADSSTRL A/D Sampling State Register 0x0DD 8 read-write 0x0d 0xff SST Sampling Time Setting 0 7 read-write ADSSTRT A/D Sampling State Register 0x0DE 8 read-write 0x0d 0xff SST Sampling Time Setting 0 7 read-write ADSSTRO A/D Sampling State Register 0x0DF 8 read-write 0x0d 0xff SST Sampling Time Setting 0 7 read-write 2 0x1 5-6 ADSSTR%s A/D Sampling State Register 0x0E5 8 read-write 0x0d 0xff SST Sampling Time Setting 0 7 read-write 2 0x1 9-10 ADSSTR%s A/D Sampling State Register 0x0E9 8 read-write 0x0d 0xff SST Sampling Time Setting 0 7 read-write SCI9 Serial Communication Interface 0 0x40070120 0x00 20 registers 0x1A 3 registers SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x00 8 read-write 0x00 0xff CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 MP Multi-Processor Mode 2 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 STOP Stop Bit Length 3 3 read-write 0 1 stop bit #0 1 2 stop bits #1 PM Parity Mode 4 4 read-write 0 Even parity #0 1 Odd parity #1 PE Parity Enable 5 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 CHR Character Length 6 6 read-write 0 SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CM Communication Mode 7 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x00 8 read-write 0x00 0xff CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 BCP Base Clock Pulse 2 3 read-write PM Parity Mode 4 4 read-write 0 Even parity #0 1 Odd parity #1 PE Parity Enable 5 5 read-write BLK Block Transfer Mode 6 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 GM GSM Mode 7 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 BRR Bit Rate Register 0x01 8 read-write 0xff 0xff SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x02 8 read-write 0x00 0xff CKE Clock Enable 0 1 read-write 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin. true TEIE Transmit End Interrupt Enable 2 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 MPIE Multi-Processor Interrupt Enable 3 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 TE Transmit Enable 5 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 RIE Receive Interrupt Enable 6 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TIE Transmit Interrupt Enable 7 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x02 8 read-write 0x00 0xff CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 TEIE Transmit End Interrupt Enable 2 2 read-write MPIE Multi-Processor Interrupt Enable 3 3 read-write RE Receive Enable 4 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 TE Transmit Enable 5 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 RIE Receive Interrupt Enable 6 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TIE Transmit Interrupt Enable 7 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 TDR Transmit Data Register 0x03 8 read-write 0xff 0xff SSR Serial Status Register for Non-Smart Card Interface (SCMR.SMIF = 0) 0x04 8 read-write 0x84 0xff MPBT Multi-Processor Bit Transfer 0 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 MPB Multi-Processor 1 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TEND Transmit End Flag 2 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 PER Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 FER Framing Error Flag 4 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 RDRF Receive Data Full Flag 6 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1) SSR 0x04 8 read-write 0x84 0xff MPBT Multi-Processor Bit Transfer 0 0 read-write MPB Multi-Processor 1 1 read-only TEND Transmit End Flag 2 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 PER Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 ERS Error Signal Status Flag 4 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 ORER Overrun Error Flag 5 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 RDRF Receive Data Full Flag 6 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 RDR Receive Data Register 0x05 8 read-only 0x00 0xff SCMR Smart Card Mode Register 0x06 8 read-write 0xf2 0xff SMIF Smart Card Interface Mode Select 0 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SINV Transmitted/Received Data Invert 2 2 read-write 0 TDR contents are transmitted as they are. Received data is stored as received in the RDR register. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SDIR Transmitted/Received Data Transfer Direction 3 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 CHR1 Character Length 1 4 4 read-write 0 SMR.CHR = 0: Transmit/receive in 9-bit data length SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) SMR.CHR = 1: Transmit/receive in 7-bit data length #1 BCP2 Base Clock Pulse 2 7 7 read-write SEMR Serial Extended Mode Register 0x07 8 read-write 0x00 0xff BRME Bit Rate Modulation Enable 2 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period #1 ABCS Asynchronous Mode Base Clock Select 4 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 NFEN Digital Noise Filter Function Enable 5 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple I2C mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple I2C mode: Enable noise cancellation function for SCLn and SDAn input signals #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SNFR Noise Filter Setting Register 0x08 8 read-write 0x00 0xff NFCS Noise Filter Clock Select 0 2 read-write 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple I2C mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 8 with noise filter #100 Others Setting prohibited true SIMR1 IIC Mode Register 1 0x09 8 read-write 0x00 0xff IICM Simple IIC Mode Select 0 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 IICDL SDAn Delay Output Select 3 7 read-write 0x00 No output delay 0x00 Others (IICDL - 1) to (IICDL) cycles true SIMR2 IIC Mode Register 2 0x0A 8 read-write 0x00 0xff IICINTM IIC Interrupt Mode Select 0 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 IICCSC Clock Synchronization 1 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICACKT ACK Transmission Data 5 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 SIMR3 IIC Mode Register 3 0x0B 8 read-write 0x00 0xff IICSTAREQ Start Condition Generation 0 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICRSTAREQ Restart Condition Generation 1 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSTPREQ Stop Condition Generation 2 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSDAS SDAn Output Select 4 5 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSCLS SCLn Output Select 6 7 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 SISR IIC Status Register 0x0C 8 read-only 0x00 0xcb IICACKR ACK Reception Data Flag 0 0 read-only 0 ACK received #0 1 NACK received #1 SPMR SPI Mode Register 0x0D 8 read-write 0x00 0xff SSE SSn Pin Function Enable 0 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 CTSE CTS Enable 1 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MSS Master Slave Select 2 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 MFF Mode Fault Flag 4 4 read-write 0 No mode fault error #0 1 Mode fault error #1 CKPOL Clock Polarity Select 6 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CKPH Clock Phase Select 7 7 read-write 0 Do not delay clock #0 1 Delay clock #1 TDRHL Transmit Data Register 0x0E 16 read-write 0xffff 0xffff TDAT Serial Transmit Data 0 8 read-write RDRHL Receive Data Register 0x10 16 read-only 0x0000 0xffff RDAT Serial Receive Data 0 8 read-only MDDR Modulation Duty Register 0x12 8 read-write 0xff 0xff DCCR Data Compare Match Control Register 0x13 8 read-write 0x40 0xff DCMF Data Compare Match Flag 0 0 read-write 0 Not matched #0 1 Matched #1 DPER Data Compare Match Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 DFER Data Compare Match Framing Error Flag 4 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 IDSEL ID Frame Select 6 6 read-write 0 Always compare data regardless of the MPB bit value #0 1 Only compare data when MPB bit = 1 (ID frame) #1 DCME Data Compare Match Enable 7 7 read-write 0 Disable address match function #0 1 Enable address match function #1 CDR Compare Match Data Register 0x1A 16 read-write 0x0000 0xffff CMPD Compare Match Data 0 8 read-write SPTR Serial Port Register 0x1C 8 read-write 0x03 0xff RXDMON Serial Input Data Monitor 0 0 read-only SPB2DT Serial Port Break Data Select 1 1 read-write SPB2IO Serial Port Break I/O 2 2 read-write 0 Do not output value of SPB2DT bit on TXDn pin #0 1 Output value of SPB2DT bit on TXDn pin #1 SPI0 Serial Peripheral Interface 0x40072000 0x00 8 registers 0x0A 8 registers SPCR SPI Control Register 0x00 8 read-write 0x00 0xff SPMS SPI Mode Select 0 0 read-write 0 Select SPI operation (4-wire method) #0 1 Select clock synchronous operation (3-wire method) #1 TXMD Communications Operating Mode Select 1 1 read-write 0 Select full-duplex synchronous serial communications #0 1 Select serial communications with transmit-only #1 MODFEN Mode Fault Error Detection Enable 2 2 read-write 0 Disable detection of mode fault errors #0 1 Enable detection of mode fault errors #1 MSTR SPI Master/Slave Mode Select 3 3 read-write 0 Select slave mode #0 1 Select master mode #1 SPEIE SPI Error Interrupt Enable 4 4 read-write 0 Disable SPI error interrupt requests #0 1 Enable SPI error interrupt requests #1 SPTIE Transmit Buffer Empty Interrupt Enable 5 5 read-write 0 Disable transmit buffer empty interrupt requests #0 1 Enable transmit buffer empty interrupt requests #1 SPE SPI Function Enable 6 6 read-write 0 Disable SPI function #0 1 Enable SPI function #1 SPRIE SPI Receive Buffer Full Interrupt Enable 7 7 read-write 0 Disable SPI receive buffer full interrupt requests #0 1 Enable SPI receive buffer full interrupt requests #1 SSLP SPI Slave Select Polarity Register 0x01 8 read-write 0x00 0xff SSL0P SSLn0 Signal Polarity Setting 0 0 read-write 0 Set SSLn0 signal to active-low #0 1 Set SSLn0 signal to active-high #1 SPPCR SPI Pin Control Register 0x02 8 read-write 0x00 0xff SPLP SPI Loopback 0 0 read-write 0 Normal mode #0 1 Loopback mode (receive data = inverted transmit data) #1 SPLP2 SPI Loopback 2 1 1 read-write 0 Normal mode #0 1 Loopback mode (receive data = transmit data) #1 MOIFV MOSI Idle Fixed Value 4 4 read-write 0 Set level output on MOSIn pin during MOSI idling to low #0 1 Set level output on MOSIn pin during MOSI idling to high #1 MOIFE MOSI Idle Value Fixing Enable 5 5 read-write 0 Set MOSI output value to equal final data from previous transfer #0 1 Set MOSI output value to equal value set in the MOIFV bit #1 SPSR SPI Status Register 0x03 8 read-write 0x20 0xff OVRF Overrun Error Flag 0 0 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 IDLNF SPI Idle Flag 1 1 read-only 0 SPI is in the idle state #0 1 SPI is in the transfer state #1 MODF Mode Fault Error Flag 2 2 read-write 0 No mode fault or underrun error occurred #0 1 Mode fault error or underrun error occurred #1 PERF Parity Error Flag 3 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 UDRF Underrun Error Flag 4 4 read-write 0 Mode fault error occurred (MODF = 1) #0 1 Underrun error occurred (MODF = 1) #1 SPTEF SPI Transmit Buffer Empty Flag 5 5 read-write 0 Data is in the transmit buffer #0 1 No data is in the transmit buffer #1 SPRF SPI Receive Buffer Full Flag 7 7 read-write 0 No valid data is in SPDR/SPDR_HA #0 1 Valid data is in SPDR/SPDR_HA #1 SPDR SPI Data Register 0x04 32 read-write 0x00000000 0xffffffff SPDR_HA SPI Data Register SPDR 0x04 16 read-write 0x0000 0xffff SPDR_BY SPI Data Register SPDR 0x04 8 read-write 0x00 0xff SPBR SPI Bit Rate Register 0x0A 8 read-write 0xff 0xff SPDCR SPI Data Control Register 0x0B 8 read-write 0x00 0xff SPRDTD SPI Receive/Transmit Data Select 4 4 read-write 0 Read SPDR/SPDR_HA values from receive buffer #0 1 Read SPDR/SPDR_HA values from transmit buffer, but only if the transmit buffer is empty #1 SPLW SPI Word Access/Halfword Access Specification 5 5 read-write 0 Set SPDR_HA to valid for halfword access #0 1 Set SPDR to valid for word access #1 SPBYT SPI Byte Access Specification 6 6 read-write 0 SPDR/SPDR_HA is accessed in halfword or word (SPLW is valid) #0 1 SPDR_BY is accessed in byte (SPLW is invalid) #1 SPCKD SPI Clock Delay Register 0x0C 8 read-write 0x00 0xff SCKDL RSPCK Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SSLND SPI Slave Select Negation Delay Register 0x0D 8 read-write 0x00 0xff SLNDL SSL Negation Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SPND SPI Next-Access Delay Register 0x0E 8 read-write 0x00 0xff SPNDL SPI Next-Access Delay Setting 0 2 read-write 000 1 RSPCK + 2 PCLKB #000 001 2 RSPCK + 2 PCLKB #001 010 3 RSPCK + 2 PCLKB #010 011 4 RSPCK + 2 PCLKB #011 100 5 RSPCK + 2 PCLKB #100 101 6 RSPCK + 2 PCLKB #101 110 7 RSPCK + 2 PCLKB #110 111 8 RSPCK + 2 PCLKB #111 SPCR2 SPI Control Register 2 0x0F 8 read-write 0x00 0xff SPPE Parity Enable 0 0 read-write 0 Do not add parity bit to transmit data and do not check parity bit of receive data #0 1 When SPCR.TXMD = 0: Add parity bit to transmit data and check parity bit of receive data When SPCR.TXMD = 1: Add parity bit to transmit data but do not check parity bit of receive data #1 SPOE Parity Mode 1 1 read-write 0 Select even parity for transmission and reception #0 1 Select odd parity for transmission and reception #1 SPIIE SPI Idle Interrupt Enable 2 2 read-write 0 Disable idle interrupt requests #0 1 Enable idle interrupt requests #1 PTE Parity Self-Testing 3 3 read-write 0 Disable self-diagnosis function of the parity circuit #0 1 Enable self-diagnosis function of the parity circuit #1 SCKASE RSPCK Auto-Stop Function Enable 4 4 read-write 0 Disable RSPCK auto-stop function #0 1 Enable RSPCK auto-stop function #1 SPCMD0 SPI Command Register 0 0x10 16 read-write 0x070d 0xffff CPHA RSPCK Phase Setting 0 0 read-write 0 Select data sampling on leading edge, data change on trailing edge #0 1 Select data change on leading edge, data sampling on trailing edge #1 CPOL RSPCK Polarity Setting 1 1 read-write 0 Set RSPCK low during idle #0 1 Set RSPCK high during idle #1 BRDV Bit Rate Division Setting 2 3 read-write 00 Base bit rate #00 01 Base bit rate divided by 2 #01 10 Base bit rate divided by 4 #10 11 Base bit rate divided by 8 #11 SPB SPI Data Length Setting 8 11 read-write 0x0 20 bits 0x0 0x1 24 bits 0x1 0x2 32 bits 0x2 0x3 32 bits 0x3 0x8 9 bits 0x8 0x9 10 bits 0x9 0xA 11 bits 0xa 0xB 12 bits 0xb 0xC 13 bits 0xc 0xD 14 bits 0xd 0xE 15 bits 0xe 0xF 16 bits 0xf Others 8 bits true LSBF SPI LSB First 12 12 read-write 0 MSB-first #0 1 LSB-first #1 SPNDEN SPI Next-Access Delay Enable 13 13 read-write 0 Select next-access delay of 1 RSPCK + 2 PCLKB #0 1 Select next-access delay equal to the setting in the SPI Next-Access Delay Register (SPND) #1 SLNDEN SSL Negation Delay Setting Enable 14 14 read-write 0 Select SSL negation delay of 1 RSPCK #0 1 Select SSL negation delay equal to the setting in the SPI Slave Select Negation Delay Register (SSLND) #1 SCKDEN RSPCK Delay Setting Enable 15 15 read-write 0 Select RSPCK delay of 1 RSPCK #0 1 Select RSPCK delay equal to the setting in the SPI Clock Delay Register (SPCKD) #1 CRC Cyclic Redundancy Check Calculator 0x40074000 0x00 2 registers 0x04 4 registers 0x08 4 registers 0x0C 2 registers CRCCR0 CRC Control Register 0 0x00 8 read-write 0x00 0xff GPS CRC Generating Polynomial Switching 0 2 read-write 001 8-bit CRC-8 (X8 + X2 + X + 1) #001 010 16-bit CRC-16 (X16 + X15 + X2 + 1) #010 011 16-bit CRC-CCITT (X16 + X12 + X5 + 1) #011 100 32-bit CRC-32 (X32 + X26 + X23 + X22 + X16 + X12 + X11 +X10 + X8 + X7 + X5 + X4 + X2 + X + 1) #100 101 32-bit CRC-32C (X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20 + X19 + X18 + X14 + X13 + X11 + X10 + X9 + X8 + X6 + 1) #101 Others No calculation is executed true LMS CRC Calculation Switching 6 6 read-write 0 Generate CRC code for LSB-first communication #0 1 Generate CRC code for MSB-first communication #1 DORCLR CRCDOR/CRCDOR_HA/CRCDOR_BY Register Clear 7 7 write-only 0 No effect #0 1 Clear the CRCDOR/CRCDOR_HA/CRCDOR_BY register #1 CRCCR1 CRC Control Register 1 0x01 8 read-write 0x00 0xff CRCSWR Snoop-On-Write/Read Switch 6 6 read-write 0 Snoop-on-read #0 1 Snoop-on-write #1 CRCSEN Snoop Enable 7 7 read-write 0 Disabled #0 1 Enabled #1 CRCDIR CRC Data Input Register 0x04 32 read-write 0x00000000 0xffffffff CRCDIR_BY CRC Data Input Register CRCDIR 0x04 8 read-write 0x00 0xff CRCDOR CRC Data Output Register 0x08 32 read-write 0x00000000 0xffffffff CRCDOR_HA CRC Data Output Register CRCDOR 0x08 16 read-write 0x0000 0xffff CRCDOR_BY CRC Data Output Register CRCDOR 0x08 8 read-write 0x00 0xff CRCSAR Snoop Address Register 0x0C 16 read-write 0x0000 0xffff CRCSA Register Snoop Address 0 13 read-write GPT164 General PWM 16-bit Timer 4 0x40078400 0x00 68 registers 0x48 36 registers 0x88 8 registers GTWP General PWM Timer Write-Protection Register 0x00 32 read-write 0x00000000 0xffffffff WP Register Write Disable 0 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 PRKEY GTWP Key Code 8 15 write-only GTSTR General PWM Timer Software Start Register 0x04 32 read-write 0x00000000 0xffffffff CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTSTP General PWM Timer Software Stop Register 0x08 32 read-write 0xffffffff 0xffffffff CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTCLR General PWM Timer Software Clear Register 0x0C 32 write-only 0x00000000 0xffffffff CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write 0x00000000 0xffffffff SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 CSTRT Software Source Counter Start Enable 31 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write 0x00000000 0xffffffff PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 CSTOP Software Source Counter Stop Enable 31 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write 0x00000000 0xffffffff CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CCLR Software Source Counter Clear Enable 31 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write 0x00000000 0xffffffff USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write 0x00000000 0xffffffff DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write 0x00000000 0xffffffff ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write 0x00000000 0xffffffff BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 GTCR General PWM Timer Control Register 0x2C 32 read-write 0x00000000 0xffffffff CST Count Start 0 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 18 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 24 26 read-write 000 PCLKD/1 #000 001 PCLKD/4 #001 010 PCLKD/16 #010 011 PCLKD/64 #011 100 PCLKD/256 #100 101 PCLKD/1024 #101 Others Setting prohibited true GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write 0x00000001 0xffffffff UD Count Direction Setting 0 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTY GTIOCnA Output Duty Setting 16 17 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 19 read-write 0 The function selected by the GTIOA[3:2] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting. #0 1 The function selected by the GTIOA[3:2] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting. #1 OBDTY GTIOCnB Output Duty Setting 24 25 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 27 read-write 0 The function selected by the GTIOB[3:2] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting. #0 1 The function selected by the GTIOB[3:2] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting. #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write 0x00000000 0xffffffff GTIOA GTIOCnA Pin Function Select 0 4 read-write OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OAE GTIOCnA Pin Output Enable 8 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OADF GTIOCnA Pin Disable Value Setting 9 10 read-write 00 None of the below options are specified #00 01 GTIOCnA pin is set to Hi-Z in response to controlling the output negation #01 10 GTIOCnA pin is set to 0 in response to controlling the output negation #10 11 GTIOCnA pin is set to 1 in response to controlling the output negation #11 NFAEN Noise Filter A Enable 13 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 15 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 GTIOB GTIOCnB Pin Function Select 16 20 read-write OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 OBE GTIOCnB Pin Output Enable 24 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBDF GTIOCnB Pin Disable Value Setting 25 26 read-write 00 None of the below options are specified #00 01 GTIOCnB pin is set to Hi-Z in response to controlling the output negation #01 10 GTIOCnB pin is set to 0 in response to controlling the output negation #10 11 GTIOCnB pin is set to 1 in response to controlling the output negation #11 NFBEN Noise Filter B Enable 29 29 read-write 0 The noise filter for the GTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSB Noise Filter B Sampling Clock Select 30 31 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write 0x00000000 0xffffffff GRP Output Disable Source Select 24 25 read-write 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 Others Setting prohibited true GRPABH Same Time Output Level High Disable Request Enable 29 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTST General PWM Timer Status Register 0x3C 32 read-write 0x00008000 0xffffffff TCFA Input Capture/Compare Match Flag A 0 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 ODF Output Disable Flag 24 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 OABHF Same Time Output Level High Flag 29 29 read-only 0 No simultaneous generation of 1 both for the GTIOCA and GTIOCB pins has occurred. #0 1 A simultaneous generation of 1 both for the GTIOCA and GTIOCB pins has occurred. #1 OABLF Same Time Output Level Low Flag 30 30 read-only 0 No simultaneous generation of 0 both for the GTIOCA and GTIOCB pins has occurred. #0 1 A simultaneous generation of 0 both for the GTIOCA and GTIOCB pins has occurred. #1 GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write 0x00000000 0xffffffff BD0 GTCCR Buffer Operation Disable 0 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 17 read-write 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) true CCRB GTCCRB Buffer Operation 18 19 read-write 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) true PR GTPR Buffer Operation 20 21 read-write 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 Others Setting prohibited true CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 22 write-only GTCNT General PWM Timer Counter 0x48 32 read-write 0x00000000 0xffffffff GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write 0x0000ffff 0xffffffff GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write 0x0000ffff 0xffffffff GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write 0x0000ffff 0xffffffff GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write 0x0000ffff 0xffffffff GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write 0x0000ffff 0xffffffff GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write 0x0000ffff 0xffffffff GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write 0x0000ffff 0xffffffff GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write 0x0000ffff 0xffffffff GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write 0x00000000 0xffffffff TDE Negative-Phase Waveform Setting 0 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU is used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write 0x0000ffff 0xffffffff GPT165 General PWM 16-bit Timer 5 0x40078500 GPT166 General PWM 16-bit Timer 6 0x40078600 GPT167 General PWM 16-bit Timer 7 0x40078700 GPT168 General PWM 16-bit Timer 8 0x40078800 GPT169 General PWM 16-bit Timer 9 0x40078900 GPT_OPS Output Phase Switching Controller 0x40078FF0 0x00 4 registers OPSCR Output Phase Switching Control Register 0x00 32 read-write 0x00000000 0xffffffff UF 0 0 read-write VF 1 1 read-write WF 2 2 read-write EN Output Phase Enable 8 8 read-write 0 Do not output (Hi-Z external pin) #0 1 Output #1 FB External Feedback Signal Enable 16 16 read-write 0 Do not use #0 1 Select the soft setting (OPSCR.UF, VF, WF) #1 P Positive-Phase Output (P) Control 17 17 read-write 0 Level signal output #0 1 PWM signal output #1 N Negative-Phase Output (N) Control 18 18 read-write 0 Level signal output #0 1 PWM signal output #1 INV Output Phase Invert Control 19 19 read-write 0 Positive logic (active-high) output #0 1 Negative logic (active-low) output #1 RV Output Phase Rotation Direction Reversal Control 20 20 read-write 0 Positive rotation #0 1 Reverse rotation #1 ALIGN Input Phase Alignment 21 21 read-write 0 Input phase aligned to PCLKD #0 1 Input phase aligned to the falling edge of PWM #1 GRP Output Disabled Source Selection 24 25 read-write GODF Group Output Disable Function 26 26 read-write 0 This bit function is ignored #0 1 Group disable clears the OPSCR.EN bit #1 NFEN External Input Noise Filter Enable 29 29 read-write 0 Do not use a noise filter on the external input #0 1 Use a noise filter on the external input #1 NFCS External Input Noise Filter Clock Selection 30 31 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 KINT Key Interrupt Function 0x40080000 0x00 1 registers 0x04 1 registers 0x08 1 registers KRCTL Key Return Control Register 0x00 8 read-write 0x00 0xff KREG Detection Edge Selection (KR00 to KR03 pins) 0 0 read-write 0 Falling edge #0 1 Rising edge #1 KRMD Usage of Key Interrupt Flags (KRF.KIF0 to KRF.KIF3) 7 7 read-write 0 Do not use key interrupt flags #0 1 Use key interrupt flags #1 KRF Key Return Flag Register 0x04 8 read-write 0x00 0xff KIF0 Key Interrupt Flag n 0 0 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KIF1 Key Interrupt Flag n 1 1 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KIF2 Key Interrupt Flag n 2 2 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KIF3 Key Interrupt Flag n 3 3 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KRM Key Return Mode Register 0x08 8 read-write 0x00 0xff KIMC0 Key Interrupt Mode Control n 0 0 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 KIMC1 Key Interrupt Mode Control n 1 1 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 KIMC2 Key Interrupt Mode Control n 2 2 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 KIMC3 Key Interrupt Mode Control n 3 3 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 I3C I3C Bus Interface 0x40083000 0x00 4 registers 0x14 8 registers 0x20 8 registers 0x30 16 registers 0x44 4 registers 0x58 4 registers 0x60 8 registers 0x70 36 registers 0xA0 8 registers 0xB0 4 registers 0xC0 4 registers 0x140 4 registers 0x150 12 registers 0x17C 8 registers 0x190 8 registers 0x1C0 4 registers 0x1D0 32 registers 0x210 8 registers 0x224 32 registers 0x2A0 4 registers 0x2B0 4 registers 0x2D0 16 registers 0x320 12 registers 0x330 4 registers 0x350 40 registers 0x380 4 registers 0x394 8 registers 0x3C0 4 registers 0x3CC 8 registers PRTS Protocol Selection Register 0x000 32 read-write 0x00000001 0xffffffff PRTMD Protocol Mode 0 0 read-write 0 I3C protocol mode #0 1 I2C protocol mode #1 BCTL Bus Control Register 0x014 32 read-write 0x00000000 0xffffffff INCBA Include I3C Broadcast Address 0 0 read-write 0 Do not include I3C broadcast address for private transfers #0 1 Include I3C broadcast address for private transfers #1 HJACKCTL Hot-Join Acknowledge Control 8 8 read-write 0 ACK the Hot-Join request #0 1 NACK and send broadcast CCC to disable Hot-Join #1 ABT Abort 29 29 read-write 0 I3C is running. #0 1 I3C has aborted a transfer. #1 RSM Resume 30 30 read-write 0 I3C is running. #0 1 I3C is suspended (RW1C). #1 BUSE Bus Enable 31 31 read-write 0 I3C bus operation is disabled. #0 1 I3C bus operation is enabled. #1 MSDVAD Master Device Address Register 0x018 32 read-write 0x00000000 0xffffffff MDYAD Master Dynamic Address 16 22 read-write MDYADV Master Dynamic Address Valid 31 31 read-write 0 The master dynamic address field is not valid. #0 1 The master dynamic address field is valid. #1 RSTCTL Reset Control Register 0x020 32 read-write 0x00000000 0xffffffff RI3CRST I3C Software Reset 0 0 read-write 0 Release I3C reset. #0 1 Initiate I3C reset. #1 CMDQRST Command Queue Software Reset 1 1 read-write 0 The Command Queues in I3C is not flushed. #0 1 The Command Queues in I3C is flushed. #1 RSPQRST Response Queue Software Reset 2 2 read-write 0 The Response Queues in I3C is not flushed. #0 1 The Response Queues in I3C is flushed. #1 TDBRST Transmit Data Buffer Software Reset 3 3 read-write 0 The Transmit Queues in I3C is not flushed. #0 1 The Transmit Queues in I3C is flushed. #1 RDBRST Receive Data Buffer Software Reset 4 4 read-write 0 The Receive Queues in I3C is not flushed. #0 1 The Receive Queues in I3C is flushed. #1 IBIQRST IBI Queue Software Reset 5 5 read-write 0 The IBI Queues in I3C is not flushed. #0 1 The IBI Queues in I3C is flushed. #1 RSQRST Receive Status Queue Software Reset 6 6 read-write 0 The Receive Status Queue in I3C is not flushed. #0 1 The Receive Status Queue in I3C is flushed. #1 INTLRST Internal Software Reset 16 16 read-write 0 Releases of some registers and internal state. #0 1 Resets of some registers and internal state. #1 PRSST Present State Register 0x024 32 read-write 0x00000000 0xffffffff CRMS Current Master 2 2 read-write 0 The Master is not the Current Master, and must request and acquire bus ownership before initiating any transfer. #0 1 The Master is the Current Master, and as a result can initiate transfers. #1 TRMD Transmit/Receive Mode 4 4 read-only 0 Receive mode #0 1 Transmit mode #1 PRSSTWP Present State Write Protect 7 7 write-only 0 CRMS bit is protected. #0 1 CRMS bit can be written when writing simultaneously with the value of the target bit. #1 INST Internal Status Register 0x030 32 read-write 0x00000000 0xffffffff INEF Internal Error Flag 10 10 read-write 0 I3C Internal Error has not detected. #0 1 I3C Internal Error has detected. #1 INSTE Internal Status Enable Register 0x034 32 read-write 0x00000000 0xffffffff INEE Internal Error Enable 10 10 read-write 0 Disable INST.INEF #0 1 Enable INST.INEF #1 INIE Internal Interrupt Enable Register 0x038 32 read-write 0x00000000 0xffffffff INEIE Internal Error Interrupt Enable 10 10 read-write 0 Disables Non-recoverable Internal Error Interrupt Signal. #0 1 Enables Non-recoverable Internal Error Interrupt Signal. #1 INSTFC Internal Status Force Register 0x03C 32 write-only 0x00000000 0xffffffff INEFC Internal Error Force 10 10 write-only 0 Not force a specific interrupt #0 1 Force a specific interrupt #1 DVCT Device Characteristic Table Register 0x044 32 read-only 0x00000000 0xffffffff IDX DCT Table Index 19 23 read-only IBINCTL IBI Notify Control Register 0x058 32 read-write 0x00000000 0xffffffff NRHJCTL Notify Rejected Hot-Join Control 0 0 read-write 0 Do not pass rejected IBI Status to IBI Queue, if the incoming HotJoin request is NACKed and is autodisabled based on field HJACKCTL of BCTL. #0 1 Pass rejected IBI Status to the IBI Queue, if the incoming Hot Join request is NACKed and is autodisabled based on field HJACKCTL of BCTL. #1 NRMRCTL Notify Rejected Master Request Control 1 1 read-write 0 Do not pass rejected IBI Status to IBI Queue/Ring, if the incoming Master Request is NACKed and is auto-disabled based on DVMRRJ field in relevant DAT entry. #0 1 Pass rejected IBI Status to the IBI Queue, if the incoming Master Request is NACKed and is autodisabled based on DVMRRJ field in relevant DAT entry. #1 NRSIRCTL Notify Rejected Slave Interrupt Request Control 3 3 read-write 0 Do not pass rejected IBI Status to the IBI Queue/Rings, if the incoming SIR is NACKed and is auto-disabled based on DVSIRRJ field in relevant DAT entry. #0 1 Pass rejected IBI Status to the IBI Queue/Rings, if the incoming SIR is NACKed and is auto-disabled based on DVSIRRJ field in relevant DAT entry. #1 BFCTL Bus Function Control Register 0x060 32 read-write 0x00000101 0xffffffff MALE Master Arbitration-Lost Detection Enable 0 0 read-write 0 Master arbitration-lost detection disables. Disables the arbitration-lost detection function and does not clear the CRMS and TRMD bits in PRSST automatically when arbitration is lost. #0 1 Master arbitration-lost detection enables. Enables the arbitration-lost detection function and clears the CRMS and TRMD bits in PRSST automatically when arbitration is lost. #1 NALE NACK Transmission Arbitration-Lost Detection Enable 1 1 read-write 0 NACK transmission arbitration-lost detection disables. #0 1 NACK transmission arbitration-lost detection enables. #1 SALE Slave Arbitration-Lost Detection Enable 2 2 read-write 0 Slave arbitration-lost detection disables. #0 1 Slave arbitration-lost detection enables. #1 SCSYNE SCL Synchronous Circuit Enable 8 8 read-write 0 No SCL synchronous circuit uses. #0 1 An SCL synchronous circuit uses. #1 SMBS SMBus/I2C Bus Selection 12 12 read-write 0 The I2C bus select. #0 1 The SMBus select. #1 FMPE Fast-mode Plus Enable 14 14 read-write 0 No Fm+ slope control circuit uses for the SCLn pin and SDAn pin. (n = 0) #0 1 An Fm+ slope control circuit uses for the SCLn pin and SDAn pin. (n = 0) #1 HSME High Speed Mode Enable 15 15 read-write 0 Disable High Speed Mode. #0 1 Enable High Speed Mode. #1 SVCTL Slave Control Register 0x064 32 read-write 0x00000000 0xffffffff GCAE General Call Address Enable 0 0 read-write 0 General call address detection disables. #0 1 General call address detection enables. #1 HSMCE Hs-mode Master Code Enable 5 5 read-write 0 Hs-mode Master Code Detection disables. #0 1 Hs-mode Master Code Detection enables. #1 DVIDE Device-ID Address Enable 6 6 read-write 0 Device-ID address detection disables. #0 1 Device-ID address detection enables. #1 HOAE Host Address Enable 15 15 read-write 0 Host address detection disables. #0 1 Host address detection enables. #1 SVAE0 Slave Address Enable 0 16 16 read-write 0 Slave 0 disables #0 1 Slave 0 enables #1 REFCKCTL Reference Clock Control Register 0x070 32 read-write 0x00000000 0xffffffff IREFCKS Internal Reference Clock Selection 0 2 read-write 000 PCLKD/1 clock #000 001 PCLKD/2 clock #001 010 PCLKD/4 clock #010 011 PCLKD/8 clock #011 100 PCLKD/16 clock #100 101 PCLKD/32 clock #101 110 PCLKD/64 clock #110 111 PCLKD/128 clock #111 STDBR Standard Bit Rate Register 0x074 32 read-write 0x3f3fffff 0xffffffff SBRLO Count value of the Low-level period of SCL clock 0 7 read-write SBRHO Count value of the High-level period of SCL clock 8 15 read-write SBRLP Standard Bit Rate Low-level Period Push-Pull 16 21 read-write SBRHP Standard Bit Rate High-Level Period Push-Pull 24 29 read-write DSBRPO Double the Standard Bit Rate Period for Open-Drain 31 31 read-write 0 The time period set for SBRHO[7:0] and SBRLO[7:0] is not doubled. #0 1 The time period set for SBRHO[7:0] and SBRLO[7:0] is doubled. #1 EXTBR Extended Bit Rate Register 0x078 32 read-write 0x3f3fffff 0xffffffff EBRLO Extended Bit Rate Low-Level Period Open-Drain 0 7 read-write EBRHO Extended Bit Rate High-Level Period Open-Drain 8 15 read-write EBRLP Extended Bit Rate Low-Level Period Push-Pull 16 21 read-write EBRHP Extended Bit Rate Low-Level Period Push-Pull 24 29 read-write BFRECDT Bus Free Condition Detection Time Register 0x07C 32 read-write 0x00000000 0xffffffff FRECYC Bus Free Condition Detection Cycle 0 8 read-write BAVLCDT Bus Available Condition Detection Time Register 0x080 32 read-write 0x00000000 0xffffffff AVLCYC Bus Available Condition Detection Cycle 0 8 read-write BIDLCDT Bus Idle Condition Detection Time Register 0x084 32 read-write 0x00000000 0xffffffff IDLCYC Bus Idle Condition Detection Cycle 0 17 read-write OUTCTL Output Control Register 0x088 32 read-write 0x00000003 0xffffffff SDOC SDA Output Control 0 0 read-write 0 I3C drives the SDAn pin low. #0 1 I3C releases the SDAn pin. #1 SCOC SCL Output Control 1 1 read-write 0 I3C drives the SCLn pin low. #0 1 I3C releases the SCLn pin. #1 SOCWP SCL/SDA Output Control Write Protect 2 2 write-only 0 Bits SCOC and SDOC are protected. #0 1 Bits SCOC and SDOC can be written (When writing simultaneously with the value of the target bit). This bit is read as 0. #1 EXCYC Extra SCL Clock Cycle Output 4 4 read-write 0 Does not output an extra SCL clock cycle (default). #0 1 Outputs an extra SCL clock cycle. #1 SDOD SDA Output Delay 8 10 read-write 000 No output delay #000 001 1 I3Cφ cycle (When OUTCTL.SDODCS = 0 (I3Cφ)) 1 or 2 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) #001 010 2 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 3 or 4 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) #010 011 3 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 5 or 6 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) #011 100 4 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 7 or 8 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) #100 101 5 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 9 or 10 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) #101 110 6 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 11 or 12 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) #110 111 7 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 13 or 14 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) #111 SDODCS SDA Output Delay Clock Source Selection 15 15 read-write 0 The internal reference clock (I3Cφ) is selected as the clock source of the SDA output delay counter. #0 1 The internal reference clock divided by 2 (I3Cφ/2) is selected as the clock source of the SDA output delay counter. #1 INCTL Input Control Register 0x08C 32 read-write 0x000000d0 0xffffffff DNFS Digital Noise Filter Stage Selection 0 3 read-write DNFE Digital Noise Filter Circuit Enable 4 4 read-write 0 No digital noise filter circuit is used. #0 1 A digital noise filter circuit is used. #1 TMOCTL Timeout Control Register 0x090 32 read-write 0x00000030 0xffffffff TODTS Timeout Detection Time Selection 0 1 read-write 00 16bit-timeout #00 01 14bit-timeout #01 10 8bit-timeout #10 11 6bit-timeout #11 TOLCTL Timeout L Count Control 4 4 read-write 0 Count is disabled while the SCLn line is at a low level. #0 1 Count is enabled while the SCLn line is at a low level. #1 TOHCTL Timeout H Count Control 5 5 read-write 0 Count is disabled while the SCLn line is at a high level. #0 1 Count is enabled while the SCLn line is at a high level. #1 TOMDS Timeout Operation Mode Selection 6 7 read-write 00 Timeout is detected during the following conditions: The bus is busy (BCST.BFREF = 0) in master mode.I3C’s own slave address is detected and the bus is busy in slave mode.The bus is free (BCST.BFREF = 1) while generation of a START condition is requested (CNDCTL.STCND = 1). #00 01 Timeout is detected while the bus is busy. #01 10 Timeout is detected while the bus is free. #10 11 Setting prohibited #11 ACKCTL Acknowledge Control Register 0x0A0 32 read-write 0x00000000 0xffffffff ACKR Acknowledge Reception 0 0 read-only 0 A 0 is received as the acknowledge bit (ACK reception). #0 1 A 1 is received as the acknowledge bit (NACK reception). #1 ACKT Acknowledge Transmission 1 1 read-write 0 A 0 is sent as the acknowledge bit (ACK transmission). #0 1 A 1 is sent as the acknowledge bit (NACK transmission). #1 ACKTWP ACKT Write Protect 2 2 write-only 0 The ACKT bit are protected. #0 1 The ACKT bit can be written (when writing simultaneously with the value of the target bit). This bit is read as 0. #1 SCSTRCTL SCL Stretch Control Register 0x0A4 32 read-write 0x00000000 0xffffffff ACKTWE Acknowledge Transmission Wait Enable 0 0 read-write 0 NTST.RDBFF0 is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.) #0 1 NTST.RDBFF0 is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.) Low-hold is released by writing a value to the ACKCTL.ACKT bit. #1 RWE Receive Wait Enable 1 1 read-write 0 No WAIT (The period between ninth clock cycle and first clock cycle is not held low.) #0 1 WAIT (The period between ninth clock cycle and first clock cycle is held low.) Low-hold is released by reading NTDTBP0. #1 SCSTLCTL SCL Stalling Control Register 0x0B0 32 read-write 0x00000000 0xffffffff STLCYC Stalling Cycle 0 15 read-write AAPE Assigned Address Phase Enable 28 28 read-write 0 Does not stall the SCL clock during the address assignment phase. #0 1 Stall the SCL clock during address assignment phase. #1 TRAPE Transition Phase Enable 29 29 read-write 0 Does not stall the SCL clock during the transition bit in read transfer. #0 1 Stall the SCL clock during the transition bit in read transfer. #1 PARPE Parity Phase Enable 30 30 read-write 0 Does not stall the SCL clock during the parity bit period. #0 1 Stall the SCL clock during the parity bit period. #1 ACKPE ACK phase Enable 31 31 read-write 0 Does not stall the SCL clock during the ACK/NACK phase. #0 1 Stall the SCL clock during the ACK/NACK phase. #1 SVTDLG0 Slave Transfer Data Length Register 0 0x0C0 32 read-write 0x00000000 0xffffffff STDLG Slave Transfer Data Length 16 31 read-write CNDCTL Condition Control Register 0x140 32 read-write 0x00000000 0xffffffff STCND START (S) Condition Issuance 0 0 read-write 0 Does not request to issue a START condition. #0 1 Requests to issue a START condition. #1 SRCND Repeated START (Sr) Condition Issuance 1 1 read-write 0 Does not request to issue a Repeated START condition. #0 1 Requests to issue a Repeated START condition. #1 SPCND STOP (P) Condition Issuance 2 2 read-write 0 Does not request to issue a STOP condition. #0 1 Requests to issue a STOP condition. #1 NCMDQP Normal Command Queue Port Register 0x150 32 write-only 0x00000000 0xffffffff NRSPQP Normal Response Queue Port Register 0x154 32 read-only 0x00000000 0xffffffff NTDTBP0 Normal Transfer Data Buffer Port Register 0 0x158 32 read-write 0x00000000 0xffffffff NTDTBP0_BY Normal Transfer Data Buffer Port Register 0 NTDTBP0 0x158 8 read-write 0x00 0xff NIBIQP Normal IBI Queue Port Register 0x17C 32 read-write 0x00000000 0xffffffff NRSQP Normal Receive Status Queue Port Register 0x180 32 read-only 0x00000000 0xffffffff NQTHCTL Normal Queue Threshold Control Register 0x190 32 read-write 0x01010101 0xffffffff CMDQTH Normal Command Ready Queue Threshold 0 7 read-write 0x00 Interrupt is issued when Command Queue is completely empty. 0x00 Others Interrupt is issued when Command Queue contains N empties. (N = CMDQTH[7:0]) true RSPQTH Normal Response Queue Threshold 8 15 read-write 0x00 Interrupt is issued when Response Queue contains 1 entry (DWORD). 0x00 Others Interrupt is triggered when Response Queue contains N+1 entries (DWORD). (N = CMDQTH[7:0]) true IBIDSSZ Normal IBI Data Segment Size 16 23 read-write IBIQTH Normal IBI Queue Threshold 24 31 read-write 0x00 I3C Protocol mode (Master): Interrupt is generated when the Outstanding IBI Status count is 1 or more. I3C Protocol mode (Slave): Interrupt is issued when IBI Data Buffer is completely empty. 0x00 Others I3C Protocol mode (Master): Interrupt is generated when the Outstanding IBI Status count is N + 1 or more. (N = CMDQTH[7:0]) I3C Protocol mode (Slave): Interrupt is issued when IBI Data Buffer contains N empties. true NTBTHCTL0 Normal Transfer Data Buffer Threshold Control Register 0 0x194 32 read-write 0x01010101 0xffffffff TXDBTH Normal Transmit Data Buffer Threshold 0 2 read-write 000 Interrupt triggers at 2 Tx Buffer empties, DWORDs #000 001 Reserved #001 Others Setting prohibited true RXDBTH Normal Receive Data Buffer Threshold 8 10 read-write 000 Interrupt triggers at 2 Rx Buffer entries, DWORDs #000 001 Reserved #001 Others Setting prohibited true TXSTTH Normal Tx Start Threshold 16 18 read-write 000 Wait for 2 DWORDs #000 001 Reserved #001 Others Setting prohibited true RXSTTH Normal Rx Start Threshold 24 26 read-write 000 Wait for 2 empty DWORDs #000 001 Reserved #001 Others Setting prohibited true NRQTHCTL Normal Receive Status Queue Threshold Control Register 0x1C0 32 read-write 0x00000001 0xffffffff RSQTH Normal Receive Status Queue Threshold 0 7 read-write 0x00 Interrupt is issued when Receive Status Queue contains 1 entry (DWORD). 0x00 Others Interrupt is triggered when Receive Status Queue contains N+1 entries (DWORD). (N = RSQTH[7:0]) true BST Bus Status Register 0x1D0 32 read-write 0x00000000 0xffffffff STCNDDF START Condition Detection Flag 0 0 read-write 0 START condition is not detected. #0 1 START condition is detected. #1 SPCNDDF STOP Condition Detection Flag 1 1 read-write 0 STOP condition is not detected. #0 1 STOP condition is detected. #1 HDREXDF HDR Exit Pattern Detection Flag 2 2 read-write 0 HDR Exit Pattern Detection Interrupt does not occur. #0 1 HDR Exit Pattern Detection Interrupt occurs. #1 NACKDF NACK Detection Flag 4 4 read-write 0 NACK is not detected. #0 1 NACK is detected. #1 TENDF Transmit End Flag 8 8 read-write 0 Data is being transmitted. #0 1 Data has been transmitted. #1 ALF Arbitration Lost Flag 16 16 read-write 0 Arbitration is not lost #0 1 Arbitration is lost. #1 TODF Timeout Detection Flag 20 20 read-write 0 Timeout is not detected. #0 1 Timeout is detected. #1 BSTE Bus Status Enable Register 0x1D4 32 read-write 0x00000000 0xffffffff STCNDDE START Condition Detection Enable 0 0 read-write 0 Disables START condition Detection Interrupt Status logging. #0 1 Enables START condition Detection Interrupt Status logging. #1 SPCNDDE STOP Condition Detection Enable 1 1 read-write 0 Disables STOP condition Detection Interrupt Status logging. #0 1 Enables STOP condition Detection Interrupt Status logging. #1 HDREXDE HDR Exit Pattern Detection Enable 2 2 read-write 0 Disables HDR Exit Pattern Detection Interrupt Status logging. #0 1 Enables HDR Exit Pattern Detection Interrupt Status logging. #1 NACKDE NACK Detection Enable 4 4 read-write 0 Disables NACK Detection Interrupt Status logging. #0 1 Enables NACK Detection Interrupt Status logging. #1 TENDE Transmit End Enable 8 8 read-write 0 Disables Transmit End Interrupt Status logging. #0 1 Enables Transmit End Interrupt Status logging. #1 ALE Arbitration Lost Enable 16 16 read-write 0 Disables Arbitration Lost Interrupt Status logging. #0 1 Enables Arbitration Lost Interrupt Status logging. #1 TODE Timeout Detection Enable 20 20 read-write 0 Disables Timeout Detection Interrupt Status logging. #0 1 Enables Timeout Detection Interrupt Status logging. #1 BIE Bus Interrupt Enable Register 0x1D8 32 read-write 0x00000000 0xffffffff STCNDDIE START Condition Detection Interrupt Enable 0 0 read-write 0 Disables START condition Detection Interrupt Signal. #0 1 Enables START condition Detection Interrupt Signal. #1 SPCNDDIE STOP Condition Detection Interrupt Enable 1 1 read-write 0 Disables STOP condition Detection Interrupt Signal. #0 1 Enables STOP condition Detection Interrupt Signal. #1 HDREXDIE HDR Exit Pattern Detection Interrupt Enable 2 2 read-write 0 Disables HDR Exit Pattern Detection Interrupt Signal. #0 1 Enables HDR Exit Pattern Detection Interrupt Signal. #1 NACKDIE NACK Detection Interrupt Enable 4 4 read-write 0 Disables NACK Detection Interrupt Signal. #0 1 Enables NACK Detection Interrupt Signal. #1 TENDIE Transmit End Interrupt Enable 8 8 read-write 0 Disables Transmit End Interrupt Signal. #0 1 Enables Transmit End Interrupt Signal. #1 ALIE Arbitration Lost Interrupt Enable 16 16 read-write 0 Disables Arbitration Lost Interrupt Signal. #0 1 Enables Arbitration Lost Interrupt Signal. #1 TODIE Timeout Detection Interrupt Enable 20 20 read-write 0 Disables Timeout Detection Interrupt Signal. #0 1 Enables Timeout Detection Interrupt Signal. #1 BSTFC Bus Status Force Register 0x1DC 32 read-write 0x00000000 0xffffffff STCNDDFC START condition Detection Force 0 0 write-only 0 Not Force START condition Detection Interrupt for software testing. #0 1 Force START condition Detection Interrupt for software testing. #1 SPCNDDFC STOP condition Detection Force 1 1 write-only 0 Not Force STOP condition Detection Interrupt for software testing. #0 1 Force STOP condition Detection Interrupt for software testing. #1 HDREXDFC HDR Exit Pattern Detection Force 2 2 write-only 0 Not Force HDR Exit Pattern Detection Interrupt for software testing. #0 1 Force HDR Exit Pattern Detection Interrupt for software testing. #1 NACKDFC NACK Detection Force 4 4 write-only 0 Not Force NACK Detection Interrupt for software testing. #0 1 Force NACK Detection Interrupt for software testing. #1 TENDFC Transmit End Force 8 8 write-only 0 Not Force Transmit End Interrupt for software testing. #0 1 Force Transmit End Interrupt for software testing. #1 ALFC Arbitration Lost Force 16 16 write-only 0 Not Force Arbitration Lost Interrupt for software testing. #0 1 Force Arbitration Lost Interrupt for software testing. #1 TODFC Timeout Detection Force 20 20 write-only 0 Not Force Timeout Detection Interrupt for software testing. #0 1 Force Timeout Detection Interrupt for software testing. #1 NTST Normal Transfer Status Register 0x1E0 32 read-write 0x00000000 0xffffffff TDBEF0 Normal Transmit Data Buffer Empty Flag 0 0 0 read-write 0 For I2C protocol mode: PRTS.PRTMD bit = 1. Normal Transmit Data Buffer 0 contains transmit data. For I3C protocol mode: PRTS.PRTMD bit = 0. The number of empties in the Normal Transmit Data Buffer 0 is less than the NTBTHCTL0.TXDBTH[2:0] threshold. #0 1 For I2C protocol mode: PRTS.PRTMD bit = 1. Normal Transmit Data Buffer 0 contains no transmit data. For I3C protocol mode: PRTS.PRTMD bit = 0. The number of empties in the Normal Transmit Data Buffer 0 is the NTBTHCTL0.TXDBTH[2:0] threshold or more. #1 RDBFF0 Normal Receive Data Buffer Full Flag 0 1 1 read-write 0 For I2C protocol mode: PRTS.PRTMD bit = 1. Normal Receive Data Buffer0 contains no receive data. For I3C Protocol mode: PRTS.PRTMD bit = 0. The number of entries in the Normal Receive Data Buffer 0 is less than the NTBTHCTL0.RXDBTH[2:0] threshold. #0 1 For I2C protocol mode: PRTS.PRTMD bit = 1. Normal Receive Data Buffer0 contains receive data. For I3C Protocol mode: PRTS.PRTMD bit = 0. The number of entries in the Normal Receive Data Buffer 0 is the NTBTHCTL0.RXDBTH[2:0] threshold or more. #1 IBIQEFF Normal IBI Queue Empty/Full Flag 2 2 read-write 0 For I3C protocol mode (Master): PRTS.PRTMD bit = 0, PRSST.CRMS bit = 1. The number of IBI Status Queue entries is the NQTHCTL.IBIQTH threshold or less. For I3C protocol mode (Slave) : PRTS.PRTMD bit = 0, PRSST.CRMS bit = 0. If the NQTHCTL.IBIQTH = 0: The number of IBI Data Buffer empties is less than the IBI Data Buffer size. If the NQTHCTL.IBIQTH is other than 0: The number of IBI Data Buffer empties is less than the NQTHCTL.IBIQTH threshold. #0 1 For I3C protocol mode (Master): PRTS.PRTMD bit = 0, PRSST.CRMS bit = 1. The number of IBI Status Queue entries is more than the NQTHCTL.IBIQTH threshold. For I3C protocol mode (Slave) : PRTS.PRTMD bit = 0, PRSST.CRMS bit = 0. If the NQTHCTL.IBIQTH = 0: The number of IBI Data Buffer empties is the IBI Data Buffer size. If the NQTHCTL.IBIQTH is other than 0: The number of IBI Data Buffer empties is the NQTHCTL.IBIQTH threshold or more. #1 CMDQEF Normal Command Queue Empty Flag 3 3 read-write 0 If the NQTHCTL.CMDQTH = 0: The number of Command Queue empties is less than the Command Queue size. If the NQTHCTL.CMDQTH is other than 0: The number of Command Queue empties is less than the NQTHCTL.CMDQTH threshold. #0 1 If the NQTHCTL.CMDQTH = 0: The number of Command Queue empties is the Command Queue size. If the NQTHCTL.CMDQTH is other than 0: 1: The number of Command Queue empties is the NQTHCTL.CMDQTH threshold or more. #1 RSPQFF Normal Response Queue Full Flag 4 4 read-write 0 The number of Response Queue entries is the NQTHCTL.RSPQTH threshold or less. #0 1 The number of Response Queue entries is more than the NQTHCTL.RSPQTH threshold. #1 TABTF Normal Transfer Abort Flag 5 5 read-write 0 Transfer Abort does not occur. #0 1 Transfer Abort occur. To clear, write 0 to this bit after 1 state is read. #1 TEF Normal Transfer Error Flag 9 9 read-write 0 Transfer Error does not occur. #0 1 Transfer Error occurs. To clear, write 0 to this bit after 1 state is read. #1 RSQFF Normal Receive Status Queue Full Flag 20 20 read-write 0 The number of Receive Status Queue entries is the NRQTHCTL.RSQTH threshold or less. #0 1 The number of Receive Status Queue entries is more than the NRQTHCTL.RSQTH threshold. #1 NTSTE Normal Transfer Status Enable Register 0x1E4 32 read-write 0x00000000 0xffffffff TDBEE0 Normal Transmit Data Buffer Empty Enable 0 0 0 read-write 0 Disables Tx0 Data Buffer Empty Interrupt Status logging. #0 1 Enables Tx0 Data Buffer Empty Interrupt Status logging. #1 RDBFE0 Normal Receive Data Buffer Full Enable 0 1 1 read-write 0 Disables Rx0 Data Buffer Full Interrupt Status logging. #0 1 Enables Rx0 Data Buffer Full Interrupt Status logging. #1 IBIQEFE Normal IBI Queue Empty/Full Enable 2 2 read-write 0 Disables IBI Status Buffer Empty/Full Interrupt Status logging. #0 1 Enables IBI Status Buffer Empty/Full Interrupt Status logging. #1 CMDQEE Normal Command Queue Empty Enable 3 3 read-write 0 Disables Command Buffer Empty Interrupt Status logging. #0 1 Enables Command Buffer Empty Interrupt Status logging. #1 RSPQFE Normal Response Queue Full Enable 4 4 read-write 0 Disables Response Buffer Full Interrupt Status logging. #0 1 Enables Response Buffer Full Interrupt Status logging. #1 TABTE Normal Transfer Abort Enable 5 5 read-write 0 Disables Transfer Abort Interrupt Status logging. #0 1 Enables Transfer Abort Interrupt Status logging. #1 TEE Normal Transfer Error Enable 9 9 read-write 0 Disables Transfer Error Interrupt Status logging. #0 1 Enables Transfer Error Interrupt Status logging. #1 RSQFE Normal Receive Status Queue Full Enable 20 20 read-write 0 Disables Receive Status Buffer Full Interrupt Status logging. #0 1 Enables Receive Status Buffer Full Interrupt Status logging. #1 NTIE Normal Transfer Interrupt Enable Register 0x1E8 32 read-write 0x00000000 0xffffffff TDBEIE0 Normal Transmit Data Buffer Empty Interrupt Enable 0 0 0 read-write 0 Disables Tx0 Data Buffer Empty Interrupt Signal. #0 1 Enables Tx0 Data Buffer Empty Interrupt Signal. #1 RDBFIE0 Normal Receive Data Buffer Full Interrupt Enable 0 1 1 read-write 0 Disables Rx0 Data Buffer Full Interrupt Signal. #0 1 Enables Rx0 Data Buffer Full Interrupt Signal. #1 IBIQEFIE Normal IBI Queue Empty/Full Interrupt Enable 2 2 read-write 0 Disables IBI Status Buffer Empty/Full Interrupt Signal. #0 1 Enables IBI Status Buffer Empty/Full Interrupt Signal. #1 CMDQEIE Normal Command Queue Empty Interrupt Enable 3 3 read-write 0 Disables Command Buffer Empty Interrupt Signal. #0 1 Enables Command Buffer Empty Interrupt Signal. #1 RSPQFIE Normal Response Queue Full Interrupt Enable 4 4 read-write 0 Disables Response Buffer Full Interrupt Signal. #0 1 Enables Response Buffer Full Interrupt Signal. #1 TABTIE Normal Transfer Abort Interrupt Enable 5 5 read-write 0 Disables Transfer Abort Interrupt Signal. #0 1 Enables Transfer Abort Interrupt Signal. #1 TEIE Normal Transfer Error Interrupt Enable 9 9 read-write 0 Disables Transfer Error Interrupt Signal. #0 1 Enables Transfer Error Interrupt Signal. #1 RSQFIE Normal Receive Status Queue Full Interrupt Enable 20 20 read-write 0 Disables Receive Status Buffer Full Interrupt Signal. #0 1 Enables Receive Status Buffer Full Interrupt Signal. #1 NTSTFC Normal Transfer Status Force Register 0x1EC 32 write-only 0x00000000 0xffffffff TDBEFC0 Normal Transmit Data Buffer Empty Force 0 0 0 write-only 0 Not Force Tx0 Data Buffer Empty Interrupt for software testing. #0 1 Force Tx0 Data Buffer Empty Interrupt for software testing. #1 RDBFFC0 Normal Receive Data Buffer Full Force 0 1 1 write-only 0 Not Force Rx0 Data Buffer Full Interrupt for software testing. #0 1 Force Rx0 Data Buffer Full Interrupt for software testing. #1 IBIQEFFC Normal IBI Queue Empty/Full Force 2 2 write-only 0 Not Force IBI Status Buffer Full Interrupt for software testing. #0 1 Force IBI Status Buffer Full Interrupt for software testing. #1 CMDQEFC Normal Command Queue Empty Force 3 3 write-only 0 Not Force Command Buffer Empty Interrupt for software testing. #0 1 Force Command Buffer Empty Interrupt for software testing. #1 RSPQFFC Normal Response Queue Full Force 4 4 write-only 0 Not Force Response Buffer Full Interrupt for software testing. #0 1 Force Response Buffer Full Interrupt for software testing. #1 TABTFC Normal Transfer Abort Force 5 5 write-only 0 Not Force Transfer Abort Interrupt for software testing. #0 1 Force Transfer Abort Interrupt for software testing. #1 TEFC Normal Transfer Error Force 9 9 write-only 0 Not Force Transfer Error Interrupt for software testing. #0 1 Force Transfer Error Interrupt for software testing. #1 RSQFFC Normal Receive Status Queue Full Force 20 20 write-only 0 Not Force Receive Status Buffer Full Interrupt for software testing. #0 1 Force Receive Status Buffer Full Interrupt for software testing. #1 BCST Bus Condition Status Register 0x210 32 read-only 0x00000000 0xffffffff BFREF Bus Free Detection Flag 0 0 read-only 0 Have not Detected Bus Free #0 1 Have Detected Bus Free #1 BAVLF Bus Available Detection Flag 1 1 read-only 0 Have not Detected Bus Available #0 1 Have Detected Bus Available #1 BIDLF Bus Idle Detection Flag 2 2 read-only 0 Have not Detected Bus Idle #0 1 Have Detected Bus Idle #1 SVST Slave Status Register 0x214 32 read-write 0x00000000 0xffffffff GCAF General Call Address Detection Flag 0 0 read-write 0 General call address does not detect. #0 1 General call address detects. #1 HSMCF Hs-mode Master Code Detection Flag 5 5 read-write 0 Hs-mode Master Code does not detect. #0 1 Hs-mode Master Code detects. #1 DVIDF Device-ID Address Detection Flag 6 6 read-write 0 Device-ID command does not detect. #0 1 Device-ID command detects. This bit set to 1 when the first frame received immediately after a START condition is detected matches a value of (device ID (1111 100) + 0[W]). #1 HOAF Host Address Detection Flag 15 15 read-write 0 Host address does not detect. #0 1 Host address detects. This bit set to 1 when the received slave address matches the host address (0001 000). #1 SVAF0 Slave Address Detection Flag 0 16 16 read-write 0 Slave 0 does not detect #0 1 Slave 0 detect #1 4 0x08 0-3 DATBAS%s Device Address Table Basic Register %s 0x224 32 read-write 0x00000000 0xffffffff DVSTAD Device Static Address 0 6 read-write DVIBIPL Device IBI Payload 12 12 read-write 0 IBIs from this Device do not carry a Data Payload. #0 1 IBIs from this Device do carry a Data Payload. #1 DVSIRRJ Device In-Band Slave Interrupt Request Reject 13 13 read-write 0 This Device shall ACK the SIR. #0 1 This Device shall NACK the SIR and send the auto-disable CCC. #1 DVMRRJ Device In-Band Master Request Reject 14 14 read-write 0 This Device shall ACK Master Requests. #0 1 This Device shall NACK Master Requests and send the auto-disable command. #1 DVDYAD Device I3C Dynamic Address 16 23 read-write DVNACK Device NACK Retry Count 29 30 read-write DVTYP Device Type 31 31 read-write 0 I3C Device #0 1 I2C Device #1 EXDATBAS Extended Device Address Table Basic Register 0x2A0 32 read-write 0x00000000 0xffffffff EDSTAD Extended Device Static Address 0 6 read-write EDDYAD Extended Device I3C Dynamic Address 16 23 read-write EDNACK Extended Device NACK Retry Count 29 30 read-write EDTYP Extended Device Type 31 31 read-write 0 I3C Device #0 1 I2C Device #1 SDATBAS0 Slave Device Address Table Basic Register 0 0x2B0 32 read-write 0x00000000 0xffffffff SDSTAD Slave Device Static Address 0 9 read-write SDADLS Slave Device Address Length Selection 10 10 read-write 0 Slave device address length 7 bits selected. #0 1 Slave device address length 10 bits selected. (I2C device only) #1 SDIBIPL Slave Device IBI Payload 12 12 read-only 0 IBIs from this device do not carry a data payload. #0 1 IBIs from this device carry a data payload. #1 SDDYAD Slave Device I3C Dynamic Address 16 22 read-write 4 0x04 0-3 MSDCT%s Master Device Characteristic Table Register %s 0x2D0 32 read-write 0x00000000 0xffffffff RBCR0 Max Data Speed Limitation 8 8 read-write 0 No Limitation #0 1 Limitation #1 RBCR1 IBI Request Capable 9 9 read-write 0 Not Capable #0 1 Capable #1 RBCR2 IBI Payload 10 10 read-write 0 No data byte follows the accepted IBI. #0 1 Mandatory one or more data bytes follow the accepted IBI. Data byte continuation is indicated by T-Bit. #1 RBCR3 Offline Capable 11 11 read-write 0 Device will always respond to I3C bus commands. #0 1 Device will not always respond to I3C bus commands. #1 RBCR76 Device Role 14 15 read-write 00 I3C Slave #00 01 I3C Master #01 Others Setting prohibited true SVDCT Slave Device Characteristic Table Register 0x320 32 read-write 0x00000000 0xffffffff TDCR Transfar Device Characteristic Register 0 7 read-write TBCR0 Max Data Speed Limitation 8 8 read-write 0 No Limitation #0 1 Limitation #1 TBCR1 IBI Request Capable 9 9 read-write 0 Not Capable #0 1 Capable #1 TBCR2 IBI Payload 10 10 read-write 0 No data byte follows the accepted IBI. #0 1 Mandatory one or more data bytes follow the accepted IBI. Data byte continuation is indicated by T-Bit. #1 TBCR3 Offline Capable 11 11 read-write 0 Device will always respond to I3C bus commands. #0 1 Device will not always respond to I3C bus commands. #1 TBCR76 Device Role 14 15 read-write 00 I3C Slave #00 01 I3C Master #01 10 Reserved for future definition by MIPI Sensor WG #10 11 Reserved for future definition by MIPI Sensor WG #11 SDCTPIDL Slave Device Characteristic Table Provisional ID Low Register 0x324 32 read-write 0x00000000 0xffffffff SDCTPIDH Slave Device Characteristic Table Provisional ID High Register 0x328 32 read-write 0x00000000 0xffffffff SVDVAD0 Slave Device Address Register 0 0x330 32 read-only 0x00000000 0xffffffff SVAD Slave Address 16 25 read-only SADLG Slave Address Length 27 27 read-only 0 The 7-bit address format is selected. #0 1 The 10-bit address format is selected. #1 SSTADV Slave Static Address Valid 30 30 read-only 0 Slave address is disabled. #0 1 Slave address is enabled. #1 SDYADV Slave Dynamic Address Valid 31 31 read-only 0 Dynamic Address is disabled. #0 1 Dynamic Address is enabled. #1 CSECMD CCC Slave Events Command Register 0x350 32 read-write 0x00000000 0xffffffff SVIRQE Slave Interrupt Requests Enable 0 0 read-write 0 DISABLED: Slave-initiated Interrupts is Disabled by the Master to control. #0 1 ENABLED: Slave-initiated Interrupts is Enabled by the Master to control. #1 MSRQE Mastership Requests Enable 1 1 read-write 0 DISABLED: Mastership requests from Secondary Masters is Disabled by the Current Master to control. #0 1 ENABLED: Mastership requests from Secondary Masters is Enabled by the Current Master to control. #1 HJEVE Hot-Join Event Enable 3 3 read-write 0 DISABLED: Slave-initiated Hot-Join is Disabled by the Master to control. #0 1 ENABLED: Slave-initiated Hot-Join is Enabled by the Master to control. #1 CEACTST CCC Enter Activity State Register 0x354 32 read-write 0x00000000 0xffffffff ACTST Activity State 0 3 read-write 0x1 ENTAS0 (1µs: Latency-free operation) 0x1 0x2 ENTAS1 (100 µs) 0x2 0x4 ENTAS2 (2 ms) 0x4 0x8 ENTAS3 (50 ms: Lowest-activity operation) 0x8 Others Setting prohibited true CMWLG CCC Max Write Length Register 0x358 32 read-write 0x00000000 0xffffffff MWLG Max Write Length 0 15 read-write CMRLG CCC Max Read Length Register 0x35C 32 read-write 0x00000000 0xffffffff MRLG Max Read Length 0 15 read-write IBIPSZ IBI Payload Size 16 23 read-write CETSTMD CCC Enter Test Mode Register 0x360 32 read-only 0x00000000 0xffffffff TSTMD Test Mode 0 7 read-only 0x00 Exit Test Mode This value removes all I3C devices from Test Mode. 0x00 0x01 Vendor Test Mode This value indicates that I3C devices shall return a random 32bit value in the provisional ID during the Dynamic Address Assignment procedure. 0x01 Others MIPI reserved Reserved for future use by the MIPI Alliance true CGDVST CCC Get Device Status Register 0x364 32 read-write 0x00000000 0xffffffff PNDINT Pending Interrupt 0 3 read-write PRTE Protocol Error 5 5 read-only 0 The Slave has not detected a protocol error since the last Status read. #0 1 The Slave has detected a protocol error since the last Status read. #1 ACTMD Slave Device’s current Activity Mode 6 7 read-write 00 Activity Mode 0 #00 01 Activity Mode 1 #01 10 Activity Mode 2 #10 11 Activity Mode 3 #11 VDRSV Vendor Reserved 8 15 read-write CMDSPW CCC Max Data Speed W (Write) Register 0x368 32 read-write 0x00000000 0xffffffff MSWDR Maximum Sustained Write Data Rate 0 2 read-write 000 fscl Max (default value) #000 001 8 MHz #001 010 6 MHz #010 011 4 MHz #011 100 2 MHz #100 Others Setting prohibited true CMDSPR CCC Max Data Speed R (Read) Register 0x36C 32 read-write 0x00000000 0xffffffff MSRDR Maximum Sustained Read Data Rate 0 2 read-write 000 fscl Max (default value) #000 001 8 MHz #001 010 6 MHz #010 011 4 MHz #011 100 2 MHz #100 Others Setting prohibited true CDTTIM Clock to Data Turnaround Time (TSCO) 3 5 read-write 000 8 ns or less (default value) #000 001 9 ns or less #001 010 10 ns or less #010 011 11 ns or less #011 100 12 ns or less #100 111 TSCO is more than 12 ns, and is reported by private agreement. #111 Others Setting prohibited true CMDSPT CCC Max Data Speed T (Turnaround) Register 0x370 32 read-write 0x00000000 0xffffffff MRTTIM Maximum Read Turnaround Time 0 23 read-write MRTE Maximum Read Turnaround Time Enable 31 31 read-write 0 Disables transmission of the Maximum Read Turnaround Time. (GETMXDS Format 1: Without Turnaround) #0 1 Enables transmission of the Maximum Read Turnaround Time. (GETMXDS Format 2: With Turnaround) #1 CETSM CCC Exchange Timing Support Information M (Mode) Register 0x374 32 read-write 0x00000000 0xffffffff FREQ Frequency Byte 8 15 read-write 0x00 32.0 KHz 0x00 0x0F 7.5 MHz 0x0f 0x1F 15.5 MHz 0x1f 0x2F 23.5 MHz 0x2f 0x3F 31.5 MHz 0x3f 0x4F 39.5 MHz 0x4f 0x5F 47.5 MHz 0x5f 0x6F 55.5 MHz 0x6f 0x7F 63.5 MHz 0x7f Others Setting prohibited true INAC Inaccuracy Byte 16 23 read-write 0x00 0.0% 0x00 0x0F 1.5% 0x0f 0x1F 3.1% 0x1f 0x2F 4.7% 0x2f 0x3F 6.3% 0x3f 0x4F 7.9% 0x4f 0x5F 9.5% 0x5f 0x6F 11.1% 0x6f 0x7F 12.7% 0x7f 0x8F 14.3% 0x8f 0x9F 15.9% 0x9f 0xAF 17.5% 0xaf 0xBF 19.1% 0xbf 0xCF 20.7% 0xcf 0xDF 22.3% 0xdf 0xEF 23.9% 0xef 0xFF 25.5% 0xff BITCNT Bit Count Register 0x380 32 read-only 0x00000000 0xffffffff BCNT Bit Counter 0 4 read-only NQSTLV Normal Queue Status Level Register 0x394 32 read-only 0x00000002 0xffffffff CMDQFLV Normal Command Queue Free Level 0 7 read-only RSPQLV Normal Response Queue Level 8 15 read-only IBIQLV Normal IBI Queue Level 16 23 read-only IBISCNT Normal IBI Status Count 24 28 read-only NDBSTLV0 Normal Data Buffer Status Level Register 0 0x398 32 read-only 0x00000001 0xffffffff TDBFLV Normal Transmit Data Buffer Free Level 0 7 read-only RDBLV Normal Receive Data Buffer Level 8 15 read-only NRSQSTLV Normal Receive Status Queue Status Level Register 0x3C0 32 read-only 0x00000000 0xffffffff RSQLV Normal Receive Status Queue Level 0 7 read-only PRSTDBG Present State Debug Register 0x3CC 32 read-only 0x0000000f 0xffffffff SCILV SCL Line Signal Level 0 0 read-only SDILV SDA Line Signal Level 1 1 read-only SCOLV SCL Output Level 2 2 read-only 0 I3C has driven the SCL pin low. #0 1 I3C has released the SCL pin. #1 SDOLV SDA Output Level 3 3 read-only 0 I3C has driven the SDA pin low. #0 1 I3C has released the SDA pin. #1 MSERRCNT Master Error Counters Register 0x3D0 32 read-only 0x00000000 0xffffffff M2ECNT M2 Error Counter 0 7 read-only AGTW0 Low Power Asynchronous General Purpose Timer 0 0x40084000 0x00 19 registers AGT AGT Counter Register 0x00 32 read-write 0xffffffff 0xffffffff AGTCMA AGT CounterCompare Match A Register 0x04 32 read-write 0xffffffff 0xffffffff AGTCMB AGT CounterCompare Match B Register 0x08 32 read-write 0xffffffff 0xffffffff AGTCR AGT Control Register 0x0C 8 read-write 0x00 0xff TSTART AGT Count Start 0 0 read-write 0 Count stops #0 1 Count starts #1 TCSTF AGT Count Status Flag 1 1 read-only 0 Count stopped #0 1 Count in progress #1 TSTOP AGT Count Forced Stop 2 2 write-only 0 Writing is invalid #0 1 The count is forcibly stopped #1 TEDGF Active Edge Judgment Flag 4 4 read-write 0 No active edge received #0 1 Active edge received #1 TUNDF Underflow Flag 5 5 read-write 0 No underflow #0 1 Underflow #1 TCMAF Compare Match A Flag 6 6 read-write 0 No match #0 1 Match #1 TCMBF Compare Match B Flag 7 7 read-write 0 No match #0 1 Match #1 AGTMR1 AGT Mode Register 1 0x0D 8 read-write 0x40 0xff TMOD Operating Mode 0 2 read-write 000 Timer mode #000 001 Pulse output mode #001 010 Event counter mode #010 011 Pulse width measurement mode #011 100 Pulse period measurement mode #100 Others Setting prohibited true TEDGPL Edge Polarity 3 3 read-write 0 Single-edge #0 1 Both-edge #1 TCK Count Source 4 6 read-write 000 PCLKB #000 001 PCLKB/8 #001 011 PCLKB/2 #011 100 Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register #100 101 Underflow event signal from AGTW0 #101 110 Setting prohibited #110 Others Setting prohibited true AGTMR2 AGT Mode Register 2 0x0E 8 read-write 0x00 0xff CKS AGTLCLK Count Source Clock Frequency Division Ratio 0 2 read-write 000 1/1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 111 1/128 #111 LPM Low Power Mode 7 7 read-write 0 Normal mode #0 1 Low power mode #1 AGTIOSEL AGT Pin Select Register 0x0F 8 read-write 0x00 0xff TIES AGTIOn Pin Input Enable 4 4 read-write 0 External event input is disabled during Software Standby mode #0 1 External event input is enabled during Software Standby mode #1 AGTIOC AGT I/O Control Register 0x10 8 read-write 0x00 0xff TEDGSEL I/O Polarity Switch 0 0 read-write TOE AGTOn pin Output Enable 2 2 read-write 0 AGTOn pin output disabled #0 1 AGTOn pin output enabled #1 TIPF Input Filter 4 5 read-write 00 No filter #00 01 Filter sampled at PCLKB #01 10 Filter sampled at PCLKB/8 #10 11 Filter sampled at PCLKB/32 #11 TIOGT Count Control 6 7 read-write 00 Event is always counted #00 01 Event is counted during polarity period specified for AGTEEn pin #01 Others Setting prohibited true AGTISR AGT Event Pin Select Register 0x11 8 read-write 0x00 0xff EEPS AGTEEn Polarity Selection 2 2 read-write 0 An event is counted during the low-level period #0 1 An event is counted during the high-level period #1 AGTCMSR AGT Compare Match Function Select Register 0x12 8 read-write 0x00 0xff TCMEA AGT Compare Match A Register Enable 0 0 read-write 0 AGT Compare match A register disabled #0 1 AGT Compare match A register enabled #1 TOEA AGTOAn Pin Output Enable 1 1 read-write 0 AGTOAn pin output disabled #0 1 AGTOAn pin output enabled #1 TOPOLA AGTOAn Pin Polarity Select 2 2 read-write 0 AGTOAn pin output is started on low. i.e. normal output #0 1 AGTOAn pin output is started on high. i.e. inverted output #1 TCMEB AGT Compare Match B Register Enable 4 4 read-write 0 Compare match B register disabled #0 1 Compare match B register enabled #1 TOEB AGTOBn Pin Output Enable 5 5 read-write 0 AGTOBn pin output disabled #0 1 AGTOBn pin output enabled #1 TOPOLB AGTOBn Pin Polarity Select 6 6 read-write 0 AGTOBn pin output is started on low. i.e. normal output #0 1 AGTOBn pin output is started on high. i.e. inverted output #1 AGTW1 Low Power Asynchronous General Purpose Timer 1 0x40084100 FLCN Flash I/O Registers 0x407EC000 0x90 1 registers 0x100 1 registers 0x104 1 registers 0x108 2 registers 0x110 2 registers 0x114 1 registers 0x118 2 registers 0x120 2 registers 0x124 1 registers 0x12C 1 registers 0x130 2 registers 0x138 2 registers 0x180 1 registers 0x184 1 registers 0x188 2 registers 0x190 2 registers 0x1C0 2 registers 0x1C8 2 registers 0x1D0 2 registers 0x1D8 1 registers 0x1DC 1 registers 0x1E0 2 registers 0x1E8 2 registers 0x1F0 2 registers 0x228 4 registers 0x3FB0 2 registers 0x3FC4 1 registers 0x3FC8 1 registers DFLCTL Data Flash Control Register 0x0090 8 read-write 0x00 0xff DFLEN Data Flash Access Enable 0 0 read-write 0 Access to the data flash is disabled #0 1 Access to the data flash is enabled #1 FPMCR Flash P/E Mode Control Register 0x0100 8 read-write 0x08 0xff FMS0 Flash Operating Mode Select 0 1 1 read-write 0 FMS1 = 0: Read mode FMS1 = 1: Data flash P/E mode. #0 1 FMS1 = 0: Code flash P/E mode FMS1 = 1: Setting prohibited. #1 RPDIS Code Flash P/E Disable 3 3 read-write 0 Programming of the code flash is enabled #0 1 Programming of the code flash is disabled. #1 FMS1 Flash Operating Mode Select 1 4 4 read-write FASR Flash Area Select Register 0x0104 8 read-write 0x00 0xff EXS Extra Area Select 0 0 read-write 0 User area or data area #0 1 Extra area. #1 FSARL Flash Processing Start Address Register L 0x0108 16 read-write 0x0000 0xffff FSARL Flash Processing Start Address L 0 15 read-write FSARH Flash Processing Start Address Register H 0x0110 16 read-write 0x0000 0xffff FSARH Flash Processing Start Address H 0 15 read-write FCR Flash Control Register 0x0114 8 read-write 0x00 0xff CMD Software Command Setting 0 3 read-write 0x1 Program 0x1 0x3 Blank check (code flash) 0x3 0x4 Block erase 0x4 0x5 Consecutive read 0x5 0x6 Chip erase 0x6 0xB Blank check (data flash) 0xb Others Setting prohibited. true DRC Data Read Completion 4 4 read-write 0 Data is not read or next data is requested #0 1 Data reading is complete. #1 STOP Forced Processing Stop 6 6 read-write OPST Processing Start 7 7 read-write 0 Processing stops #0 1 Processing starts. #1 FEARL Flash Processing End Address Register L 0x0118 16 read-write 0x0000 0xffff FEARL Flash Processing End Address L 0 15 read-write FEARH Flash Processing End Address Register H 0x0120 16 read-write 0x0000 0xffff FEARH Flash Processing End Address H 0 15 read-write FRESETR Flash Reset Register 0x0124 8 read-write 0x00 0xff FRESET Software reset of the registers 0 0 read-write 0 The registers related to the flash programming are not reset #0 1 The registers related to the flash programming are reset. #1 FSTATR1 Flash Status Register 1 0x012C 8 read-only 0x04 0xff DRRDY Data Read Ready Flag 1 1 read-only 0 The read processing of the consecutive read command at each address is not terminated. #0 1 The read processing of the consecutive read command at each address is terminated and read data is stored to the FRBH and FRBL registers. #1 FRDY Flash Ready Flag 6 6 read-only 0 The software command of the FCR register is not terminated. #0 1 The software command of the FCR register is terminated. #1 EXRDY Extra Area Ready Flag 7 7 read-only 0 The software command of the FEXCR register is not terminated. #0 1 The software command of the FEXCR register is terminated. #1 FWBL0 Flash Write Buffer Register L0 0x0130 16 read-write 0x0000 0xffff WDATA Flash Write Buffer L0 0 15 read-write FWBH0 Flash Write Buffer Register H0 0x0138 16 read-write 0x0000 0xffff WDATA Flash Write Buffer H0 0 15 read-write FPR Protection Unlock Register 0x0180 8 read-write 0x00 0x00 FPR Protection Unlock 0 7 read-write FPSR Protection Unlock Status Register 0x0184 8 read-only 0x00 0xff PERR Protect Error Flag 0 0 read-only 0 No error #0 1 An error occurs #1 FRBL0 Flash Read Buffer Register L0 0x0188 16 read-only 0x0000 0xffff RDATA Flash Read Buffer L0 0 15 read-only FRBH0 Flash Read Buffer Register H0 0x0190 16 read-only 0x0000 0xffff RDATA Flash Read Buffer H0 0 15 read-only FSCMR Flash Start-Up Setting Monitor Register 0x01C0 16 read-only 0x0000 0xb8ff SASMF Startup Area Setting Monitor Flag 8 8 read-only 0 Setting to start up using the alternative area #0 1 Setting to start up using the default area #1 FSPR Access Window Protection Flag 14 14 read-only 0 Access window setting disabled. #0 1 Access window setting enabled. #1 FAWSMR Flash Access Window Start Address Monitor Register 0x01C8 16 read-only 0x0000 0xf800 FAWS Access Window Start Address 0 10 read-only FSPR Access Window Protection Flag 15 15 read-only FAWEMR Flash Access Window End Address Monitor Register 0x01D0 16 read-only 0x0000 0xf800 FAWE Access Window End Address 0 10 read-only SASMF Startup Area Setting Monitor Flag 15 15 read-only FISR Flash Initial Setting Register 0x01D8 8 read-write 0x00 0xff PCKA Flash-IF Clock Notification 0 5 read-write SAS Startup Area Select 6 7 read-write 10 The startup area is switched to the default area temporarily #10 11 The startup area is switched to the alternate area temporarily. #11 Others The startup area is selected according to the settings of the extra area. true FEXCR Flash Extra Area Control Register 0x01DC 8 read-write 0x00 0xff CMD Software Command Setting 0 2 read-write 010 Access window information program Startup area selection and security setting #010 011 OCDID1 program #011 100 OCDID2 program #100 101 OCDID3 program #101 110 OCDID4 program #110 Others Setting prohibited. true OPST Processing Start 7 7 read-write 0 Processing stops #0 1 Processing starts. #1 FEAML Flash Error Address Monitor Register L 0x01E0 16 read-write 0x0000 0xffff FEAML Flash Error Address Monitor Register L 0 15 read-write FEAMH Flash Error Address Monitor Register H 0x01E8 16 read-write 0x0000 0xffff FEAMH Flash Error Address Monitor Register H 0 15 read-write FSTATR2 Flash Status Register 2 0x01F0 16 read-only 0x0000 0xffff ERERR Erase Error Flag 0 0 read-only 0 Erasure terminates normally #0 1 An error occurs during erasure #1 PRGERR Program Error Flag 1 1 read-only 0 Programming terminates normally #0 1 An error occurs during programming. #1 PRGERR01 Program Error Flag 01 2 2 read-only 0 Programming by the FEXCR register terminates normally #0 1 An error occurs during programming. #1 BCERR Blank Check Error Flag 3 3 read-only 0 Blank checking terminates normally #0 1 An error occurs during blank checking. #1 ILGLERR Illegal Command Error Flag 4 4 read-only 0 No illegal software command or illegal access is detected #0 1 An illegal command or illegal access is detected. #1 EILGLERR Extra Area Illegal Command Error Flag 5 5 read-only 0 No illegal command or illegal access to the extra area is detected #0 1 An illegal command or illegal access to the extra area is detected. #1 TSCDR Temperature Sensor Calibration Data Register 0x0228 32 read-only 0x00000000 0x00000000 TSCDR Temperature Sensor Calibration Data 0 15 read-only FENTRYR Flash P/E Mode Entry Register 0x3FB0 16 read-write 0x0000 0xffff FENTRY0 Code Flash P/E Mode Entry 0 0 0 read-write 0 The code flash is the read mode #0 1 The code flash is the P/E mode. #1 FENTRYD Data Flash P/E Mode Entry 7 7 read-write 0 The data flash is the read mode #0 1 The data flash is the P/E mode. #1 FEKEY Key Code 8 15 write-only FLDWAITR Memory Wait Cycle Control Register for Data Flash 0x3FC4 8 read-write 0x00 0xff FLDWAIT1 Memory Wait Cycle Select for Data Flash 0 0 read-write 0 1 wait access (Default) #0 1 2 wait access #1 PFBER Prefetch Buffer Enable Register 0x3FC8 8 read-write 0x00 0xff PFBE Prefetch Buffer Enable bit 0 0 read-write 0 Prefetch buffer is disabled #0 1 Prefetch buffer is enabled #1