Infineon tle984x 1.9.5 TLE984x Family Copyright (c) 2022 Infineon Technologies AG \n\n Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute, and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the Software is furnished to do so, all subject to the following:\n\n The copyright notices in the Software and this entire statement, including the above license grant, this restriction and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all derivative works of the Software, unless such copies or derivative works are solely in the form of machine-executable object code generated by a source language processor.\n\n THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT \n NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND \n NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE \n LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, ARISING FROM, \n OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. CM0 r2p1 little false false 2 false 8 32 ADC1 100 10-bit Analog Digital Converter (ADC1) registers ADC1 0x40004000 0 0x4000 registers CAL_CH0_1 Calibration for channel 0 and 1 register 0x48 32 read-write 0x0 0xffffffff CALOFFS_CH0 Offset calibration for channel 0 0 4 read-write CALGAIN_CH0 Gain calibration for channel 0 8 15 read-write CALOFFS_CH1 Offset calibration for channel 1 16 20 read-write CALGAIN_CH1 Gain calibration for channel 1 24 31 read-write CAL_CH10_11 Calibration for channel 10 and 11 register 0x5C 32 read-write 0x0 0xffffffff CALOFFS_CH10 Offset calibration for channel 10 0 4 read-write CALGAIN_CH10 Gain calibration for channel 10 8 15 read-write CALOFFS_CH11 Offset calibration for channel 11 16 20 read-write CALGAIN_CH11 Gain calibration for channel 11 24 31 read-write CAL_CH2_3 Calibration for channel 2 and 3 register 0x4C 32 read-write 0x0 0xffffffff CALOFFS_CH2 Offset calibration for channel 2 0 4 read-write CALGAIN_CH2 Gain calibration for channel 2 8 15 read-write CALOFFS_CH3 Offset calibration for channel 3 16 20 read-write CALGAIN_CH3 Gain calibration for channel 3 24 31 read-write CAL_CH4_5 Calibration for channel 4 and 5 register 0x50 32 read-write 0x0 0xffffffff CALOFFS_CH4 Offset calibration for channel 4 0 4 read-write CALGAIN_CH4 Gain calibration for channel 4 8 15 read-write CALOFFS_CH5 Offset calibration for channel 5 16 20 read-write CALGAIN_CH5 Gain calibration for channel 5 24 31 read-write CAL_CH6_7 Calibration for channel 6 and 7 register 0x54 32 read-write 0x0 0xffffffff CALOFFS_CH6 Offset calibration for channel 6 0 4 read-write CALGAIN_CH6 Gain calibration for channel 6 8 15 read-write CALOFFS_CH7 Offset calibration for channel 7 16 20 read-write CALGAIN_CH7 Gain calibration for channel 7 24 31 read-write CAL_CH8_9 Calibration for channel 8 and 9 register 0x58 32 read-write 0x0 0xffffffff CALOFFS_CH8 Offset calibration for channel 8 0 4 read-write CALGAIN_CH8 Gain calibration for channel 8 8 15 read-write CALOFFS_CH9 Offset calibration for channel 9 16 20 read-write CALGAIN_CH9 Gain calibration for channel 9 24 31 read-write CHx_EIM Channel setting bits for exceptional interrupt measurement register 0x8 32 read-write 0x0 0xffffffff EIM_CHx Channel set for exceptional interrupt measurement (EIM) 0 3 read-write CH0 Channel 0 enable 0 CH1 Channel 1 enable 1 CH2 Channel 2 enable 2 CH3 Channel 3 enable 3 CH4 Channel 4 enable 4 CH5 Channel 5 enable 5 CH6 Channel 6 enable 6 CH7 Channel 7 enable 7 CH8 Channel 8 enable 8 CH9 Channel 9 enable 9 CH10 Channel 10 enable 10 CH11 Channel 11 enable 11 EIM_REP Repeat count for exceptional interrupt measurement (EIM) 8 10 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 64 64 measurements 6 128 128 measurements 7 EIM_EN Exceptional interrupt measurement (EIM) Trigger Event enable 11 11 read-write DISABLE Start of EIM disabled 0 ENABLE Start of EIM enabled 1 ADC1_EIM_TRIG_SEL Trigger selection for exceptional interrupt measurement (EIM) 16 18 read-write NONE None 0 COUT63 COUT63 1 GPT12_T6OUT GPT12_T6OUT 2 GPT12_T3OUT GPT12_T3OUT 3 T2 t2_adc_trigger 4 T21 t21_adc_trigger 5 CHx_ESM Channel setting bits for exceptional sequence measurement register 0xC 32 read-write 0x0 0xffffffff ESM_0 Channel sequence for exceptional sequence measurement (ESM) 0 11 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 CH7_EN Channel 7 enable 128 CH8_EN Channel 8 enable 256 CH9_EN Channel 9 enable 512 CH10_EN Channel 10 enable 1024 CH11_EN Channel 11 enable 2048 ADC1_ESM_TRIG_SEL Trigger selection for exceptional interrupt measurement (ESM) 16 18 read-write NONE None 0 COUT63 COUT63 1 GPT12_T6OUT GPT12_T6OUT 2 GPT12_T3OUT GPT12_T3OUT 3 T2 t2_adc_trigger 4 T21 t21_adc_trigger 5 ESM_EN Enable for Exceptional Sequence Measurement Trigger Event 30 30 read-write DISABLE Start of ESM disabled 0 ENABLE Start of ESM enabled 1 ESM_STS Exceptional sequence measurement is finished 31 31 read-write NOT_ACTIVE Exceptional Sequence Measurement not done 0 DONE Exceptional Sequence Measurement done 1 CNT0_3_LOWER Lower counter trigger level channel 0-3 register 0xD8 32 read-write 0x12131312 0xffffffff CNT_LO_CH0 Lower timer trigger threshold channel 0 0 2 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH0 Channel 0 lower hysteresis 3 4 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_LO_CH1 Lower timer trigger threshold channel 1 8 10 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH1 Channel 1 lower hysteresis 11 12 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_LO_CH2 Lower timer trigger threshold channel 2 16 18 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH2 Channel 2 lower hysteresis 19 20 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_LO_CH3 Lower timer trigger threshold channel 3 24 26 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH3 Channel 3 lower hysteresis 27 28 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT0_3_UPPER Upper counter trigger level channel 0-3 register 0xE8 32 read-write 0x12131b1a 0xffffffff CNT_UP_CH0 Upper timer trigger threshold channel 0 0 2 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH0 Channel 0 upper hysteresis 3 4 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_UP_CH1 Upper timer trigger threshold channel 1 8 10 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH1 Channel 1 upper hysteresis 11 12 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_UP_CH2 Upper timer trigger threshold channel 2 16 18 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH2 Channel 2 upper hysteresis 19 20 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_UP_CH3 Upper timer trigger threshold channel 3 24 26 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH3 Channel 3 upper hysteresis 27 28 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT4_7_LOWER Lower counter trigger level channel 4-7 register 0xDC 32 read-write 0x0 0xffffffff CNT_LO_CH4 Lower timer trigger threshold channel 4 0 2 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH4 Channel 4 lower hysteresis 3 4 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_LO_CH5 Lower timer trigger threshold channel 5 8 10 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH5 Channel 5 lower hysteresis 11 12 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_LO_CH6 Lower timer trigger threshold channel 6 16 18 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH6 Channel 6 lower hysteresis 19 20 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_LO_CH7 Lower timer trigger threshold channel 7 24 26 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH7 Channel 7 lower hysteresis 27 28 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT4_7_UPPER Upper counter trigger level channel 4-7 register 0xEC 32 read-write 0x0 0xffffffff CNT_UP_CH4 Upper timer trigger threshold channel 4 0 2 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH4 Channel 4 upper hysteresis 3 4 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_UP_CH5 Upper timer trigger threshold channel 5 8 10 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH5 Channel 5 upper hysteresis 11 12 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_UP_CH6 Upper timer trigger threshold channel 6 16 18 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH6 Channel 6 upper hysteresis 19 20 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_UP_CH7 Upper timer trigger threshold channel 7 24 26 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH7 Channel 7 upper hysteresis 27 28 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT8_11_LOWER Lower counter trigger level channel 8-11 register 0xE0 32 read-write 0x0 0xffffffff CNT_LO_CH8 Lower timer trigger threshold channel 8 0 2 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH8 Channel 8 lower hysteresis 3 4 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_LO_CH9 Lower timer trigger threshold channel 9 8 10 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH9 Channel 9 lower hysteresis 11 12 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_LO_CH10 Lower timer trigger threshold channel 10 16 18 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH10 Channel 10 lower hysteresis 19 20 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_LO_CH11 Lower timer trigger threshold channel 11 24 26 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH11 Channel 11 lower hysteresis 27 28 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT8_11_UPPER Upper counter trigger level channel 8-11 register 0xF0 32 read-write 0x0 0xffffffff CNT_UP_CH8 Upper timer trigger threshold channel 8 0 2 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH8 Channel 8 upper hysteresis 3 4 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_UP_CH9 Upper timer trigger threshold channel 9 8 10 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH9 Channel 9 upper hysteresis 11 12 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_UP_CH10 Upper timer trigger threshold channel 10 16 18 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH10 Channel 10 upper hysteresis 19 20 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_UP_CH11 Upper timer trigger threshold channel 11 24 26 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH11 Channel 11 upper hysteresis 27 28 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CTRL_STS ADC1 control and status register 0x0 32 read-write 0x0 0xffffffff PD_N ADC1 Power-down signal 0 0 read-write POWER_DOWN ADC1 is powered down 0 ACTIVE ADC1 is switched on 1 SOS ADC1 Start of sampling/conversion (software mode) 2 2 read-write DISABLE No conversion is started 0 ENABLE Conversion is started 1 READY HVADC ready bit 4 4 read-only NOT_READY Module in power-down or in init phase 0 READY Set automatically 5 ADC clock cycles after module is enabled 1 CAL_SIGN Output of comparator to steer gain/offset calibration 5 5 read-only EOC ADC1 End of Conversion (software mode) 7 7 read-only PENDING Conversion still running 0 FINISHED Conversion has finished 1 SW_CH_SEL Channel for software mode 8 11 read-write CH0_EN Channel 0 enable 0 CH1_EN Channel 1 enable 1 CH2_EN Channel 2 enable 2 CH3_EN Channel 3 enable 3 CH4_EN Channel 4 enable 4 CH5_EN Channel 5 enable 5 CH6_EN Channel 6 enable 6 CH7_EN Channel 7 enable 7 CH8_EN Channel 8 enable 8 CH9_EN Channel 9 enable 9 CH10_EN Channel 10 enable 10 CH11_EN Channel 11 enable 11 CH12_EN Channel 12 enable 12 STRTUP_DIS DPP1 startup disable 18 18 read-write START_UP_ENABLE DPP1 start-up enabled 0 START_UP_DISABLE DPP1 start-up disable 1 CTRL2 Measurement unit 1 control 2 register 0x14 32 read-write 0x0 0xffffffff CAL_EN Calibration enable for channels 0 to 11 0 11 read-write CH0_EN Channel 0 calibration enable 1 CH1_EN Channel 1 calibration enable 2 CH2_EN Channel 2 calibration enable 4 CH3_EN Channel 3 calibration enable 8 CH4_EN Channel 4 calibration enable 16 CH5_EN Channel 5 calibration enable 32 CH6_EN Channel 6 calibration enable 64 CH7_EN Channel 7 calibration enable 128 CH8_EN Channel 8 calibration enable 256 CH9_EN Channel 9 calibration enable 512 CH10_EN Channel 10 calibration enable 1024 CH11_EN Channel 11 calibration enable 2048 CTRL3 Measurement unit 1 control 3 register 0x18 32 read-write 0x401 0xffffffff MCM_PD_N Power-down signal for MCM 0 0 read-write MCM_DISABLED Measurement core module disabled 0 MCM_ENABLED Measurement core module enabled 1 SW_MODE Software mode enable 1 1 read-write SOFTWARE_MODE_DISABLE Sequencer running 0 SOFTWARE_MODE_ENABLED Sequencer stopped 1 EoC_FAIL_CLR Fail of ADC end of conversion signal clear 4 4 write-only ADC_EoC_FAIL_NOT_CLEAR No clear of EoC_FAIL flag 0 ADC_EoC_FAIL_CLEAR Clear of EoC_FAIL flag 1 EoC_FAIL Fail of ADC end of conversion signal 6 6 read-only ADC_EoC_AVAILABLE End of conversion signal was sent properly by ADC 0 ADC_EoC_NOT_AVAILABLE End of conversion signal was not sent properly by ADC 1 MCM_RDY Ready signal for MCM (Measurement core module) after power on or reset 7 7 read-only MCM_NOT_READY Measurement core module in start-up phase 0 MCM_READY Measurement core module start-up phase finished 1 SAMPLE_TIME_HVCH Sample time of ADC1 8 11 read-write MICLK4 4 ADC1_CLK clock periods 0 MICLK6 6 ADC1_CLK clock periods 1 MICLK8 8 ADC1_CLK clock periods 2 MICLK10 10 ADC1_CLK clock periods 3 MICLK12 12 ADC1_CLK clock periods (default) 4 MICLK14 14 ADC1_CLK clock periods 5 MICLK16 16 ADC1_CLK clock periods 6 MICLK18 18 ADC1_CLK clock periods 7 MICLK20 20 ADC1_CLK clock periods 8 MICLK22 22 ADC1_CLK clock periods 9 MICLK4_1 4 ADC1_CLK clock periods 10 MICLK4_2 4 ADC1_CLK clock periods 11 MICLK4_3 4 ADC1_CLK clock periods 12 MICLK4_4 4 ADC1_CLK clock periods 13 MICLK4_5 4 ADC1_CLK clock periods 14 MICLK4_6 4 ADC1_CLK clock periods 15 SAMPLE_TIME_LVCH Sample time of ADC1 16 19 read-write MICLK4 4 ADC1_CLK clock periods (default) 0 MICLK6 6 ADC1_CLK clock periods 1 MICLK8 8 ADC1_CLK clock periods 2 MICLK10 10 ADC1_CLK clock periods 3 MICLK12 12 ADC1_CLK clock periods 4 MICLK14 14 ADC1_CLK clock periods 5 MICLK16 16 ADC1_CLK clock periods 6 MICLK18 18 ADC1_CLK clock periods 7 MICLK20 20 ADC1_CLK clock periods 8 MICLK22 22 ADC1_CLK clock periods 9 MICLK12_1 12 ADC1_CLK clock periods 10 MICLK12_2 12 ADC1_CLK clock periods 11 MICLK12_3 12 ADC1_CLK clock periods 12 MICLK12_4 12 ADC1_CLK clock periods 13 MICLK12_5 12 ADC1_CLK clock periods 14 MICLK12_6 12 ADC1_CLK clock periods 15 CTRL4 Measurement unit 1 control 4 register 0x38 32 read-write 0x0 0xffffffff MAX_CALTIME Maximum ADC calibration time 0 3 read-write 1 Sequence 0 2 Sequences 1 3 Sequences 2 4 Sequences 3 5 Sequences 4 6 Sequences 5 7 Sequences 6 8 Sequences 7 9 Sequences 8 10 Sequences 9 11 Sequences 10 12 Sequences 11 13 Sequences 12 14 Sequences 13 15 Sequences 14 16 Sequences 15 CTRL5 Measurement unit 1 control 5 register 0x1C 32 read-write 0x0 0xffffffff FILT_OUT_SEL_11_0 Output filter selection for channels 0 to 11 0 11 read-write UNF ADC1 unfiltered data can be monitored in the corresponding FILT_OUTx registers 0 CH0 Channel 0 IIR data enabled for FILT_OUT0 register 1 CH1 Channel 1 IIR data enabled for FILT_OUT1 register 2 CH2 Channel 2 IIR data enabled for FILT_OUT2 register 4 CH3 Channel 3 IIR data enabled for FILT_OUT3 register 8 CH4 Channel 4 IIR data enabled for FILT_OUT4 register 16 CH5 Channel 5 IIR data enabled for FILT_OUT5 register 32 CH6 Channel 6 IIR data enabled for FILT_OUT6 register 64 CH7 Channel 7 IIR data enabled for FILT_OUT7 register 128 CH8 Channel 8 IIR data enabled for FILT_OUT8 register 256 CH9 Channel 9 IIR data enabled for FILT_OUT9 register 512 CH10 Channel 10 IIR data enabled for FILT_OUT10 register 1024 CH11 Channel 11 IIR data enabled for FILT_OUT11 register 2048 CH11_0 For channels 11-0 IIR data is enabled for FILT_OUTx registers 4095 DCHCNT1_4_LOWER Lower counter trigger level differential channel 1-4 register 0xE4 32 read-write 0x0 0xffffffff CNT_LO_DCH1 Lower timer trigger threshold differential channel 1 0 2 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_DCH1 Differential Channel 1 lower hysteresis 3 4 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_LO_DCH2 Lower timer trigger threshold differential channel 2 8 10 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_DCH2 Differential Channel 2 lower hysteresis 11 12 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_LO_DCH3 Lower timer trigger threshold differential channel 3 16 18 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_DCH3 Differential Channel 3 lower hysteresis 19 20 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_LO_DCH4 Lower timer trigger threshold differential channel 4 24 26 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_DCH4 Differential Channel 4 lower hysteresis 27 28 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 DCHCNT1_4_UPPER Upper counter trigger level differential channel 1-4 register 0xF4 32 read-write 0x0 0xffffffff CNT_UP_DCH1 Upper timer trigger threshold differential channel 1 0 2 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 15 15 measurements 4 15 15 measurements 5 15 15 measurements 6 15 15 measurements 7 HYST_UP_DCH1 Differential channel 1 upper hysteresis 3 4 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_UP_DCH2 Upper timer trigger threshold differential channel 2 8 10 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 15 15 measurements 4 15 15 measurements 5 15 15 measurements 6 15 15 measurements 7 HYST_UP_DCH2 Differential channel 2 upper hysteresis 11 12 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_UP_DCH3 Upper timer trigger threshold differential channel 3 16 18 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 15 15 measurements 4 15 15 measurements 5 15 15 measurements 6 15 15 measurements 7 HYST_UP_DCH3 Differential channel 3 upper hysteresis 19 20 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_UP_DCH4 Upper timer trigger threshold differential channel 4 24 26 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 15 15 measurements 4 15 15 measurements 5 15 15 measurements 6 15 15 measurements 7 HYST_UP_DCH4 Differential channel 4 upper hysteresis 27 28 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 DCHTH1_4_LOWER Lower comparator trigger level differential channel 1-4 register 0xC4 32 read-write 0x0 0xffffffff DCH1_LOW Differential channel 1 lower trigger level 0 7 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 DCH2_LOW Differential channel 2 lower trigger level 8 15 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 DCH3_LOW Differential channel 3 lower trigger level 16 23 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 DCH4_LOW Differential channel 4 lower trigger level 24 31 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 DCHTH1_4_UPPER Upper comparator trigger level differential channel 1-4 register 0xD4 32 read-write 0x0 0xffffffff DCH1_UP Differential channel 1 upper trigger level 0 7 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 DCH2_UP Differential channel 2 upper trigger level 8 15 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 DCH3_UP Differential channel 3 upper trigger level 16 23 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 DCH4_UP Differential channel 4 upper trigger level 24 31 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 DIFFCH_OUT1 ADC1 differential channel output 1 register 0xA0 32 read-write 0x0 0xfffff000 DCH1 ADC differential output value 1 0 11 read-only DWFR1 Wait for read mode 16 16 read-write DISABLE Overwrite mode 0 ENABLE Wait for read mode enabled 1 DVF1 Valid flag 17 17 read-only NOT_VALID No new valid data available 0 VALID Result register contains valid data and has not yet been read 1 DOF1 Overrun flag 18 18 read-only NO_OVERRUN Result register not overwritten 0 OVERRUN Result register overwritten 1 DIFFCH_OUT2 ADC1 differential channel output 2 register 0xA4 32 read-write 0x0 0xfffff000 DCH2 ADC differential output value 2 0 11 read-only DWFR2 Wait for read mode 16 16 read-write DISABLE Overwrite mode 0 ENABLE Wait for read mode enabled 1 DVF2 Valid flag 17 17 read-only NOT_VALID No new valid data available 0 VALID Result register contains valid data and has not yet been read 1 DOF2 Overrun flag 18 18 read-only NO_OVERRUN Result register not overwritten 0 OVERRUN Result register overwritten 1 DIFFCH_OUT3 ADC1 differential channel output 3 register 0xA8 32 read-write 0x0 0xfffff000 DCH3 ADC differential output value 3 0 11 read-only DWFR3 Wait for read mode 16 16 read-write DISABLE Overwrite mode 0 ENABLE Wait for read mode enabled 1 DVF3 Valid flag 17 17 read-only NOT_VALID No new valid data available 0 VALID Result register contains valid data and has not yet been read 1 DOF3 Overrun flag 18 18 read-only NO_OVERRUN Result register not overwritten 0 OVERRUN Result register overwritten 1 DIFFCH_OUT4 ADC1 differential channel output 4 register 0xAC 32 read-write 0x0 0xfffff000 DCH4 ADC differential output value 4 0 11 read-only DWFR4 Wait for read mode 16 16 read-write DISABLE Overwrite mode 0 ENABLE Wait for read mode enabled 1 DVF4 Valid flag 17 17 read-only NOT_VALID No new valid data available 0 VALID Result register contains valid data and has not yet been read 1 DOF4 Overrun flag 18 18 read-only NO_OVERRUN Result register not overwritten 0 OVERRUN Result register overwritten 1 DUIN_SEL Measurement unit 1 - Differential unit input selection register 0xFC 32 read-write 0x0 0xffffffff DU1_EN Differential unit 1 enable 0 0 read-write DU1_DISABLE Differential unit 1 is disabled 0 DU1_ENABLE Differential unit 1 is enabled 1 DU1RES_NEG Differential unit 1 result negative 4 4 read-only DU1_RESULT_POSITIVE Differential unit 1 result positive after calculation 0 DU1_RESULT_NEGATIVE Differential unit 1 result negative after calculation 1 DU2_EN Differential unit 2 enable 8 8 read-write DU2_DISABLE Differential unit 2 is disabled 0 DU2_ENABLE Differential unit 2 is enabled 1 DU2RES_NEG Differential unit 2 result negative 12 12 read-only DU2_RESULT_POSITIVE Differential unit 2 result positive after calculation 0 DU2_RESULT_NEGATIVE Differential unit 2 result negative after calculation 1 DU3_EN Differential unit 3 enable 16 16 read-write DU3_DISABLE Differential unit 3 is disabled 0 DU3_ENABLE Differential unit 3 is enabled 1 DU3RES_NEG Differential unit 3 result negative 20 20 read-only DU3_RESULT_POSITIVE Differential unit 3 result positive after calculation 0 DU3_RESULT_NEGATIVE Differential unit 3 result negative after calculation 1 DU4_EN Differential unit 4 enable 24 24 read-write DU4_DISABLE Differential unit 4 is disabled 0 DU4_ENABLE Differential unit 4 is enabled 1 DU4RES_NEG Differential unit 4 result negative 28 28 read-only DU4_RESULT_POSITIVE Differential unit 4 result positive after calculation 0 DU4_RESULT_NEGATIVE Differential unit 4 result negative after calculation 1 FILT_LO_CTRL Lower Threshold filter enable 0xB4 32 read-write 0xffff 0xffffffff FL_CH0_EN Lower threshold IIR filter enable channel 0 0 0 read-write DISABLE Disable 0 ENABLE Enable 1 FL_CH1_EN Lower threshold IIR filter enable channel 1 1 1 read-write DISABLE Disable 0 ENABLE Enable 1 FL_CH2_EN Lower threshold IIR filter enable channel 2 2 2 read-write DISABLE Disable 0 ENABLE Enable 1 FL_CH3_EN Lower threshold IIR filter enable channel 3 3 3 read-write DISABLE Disable 0 ENABLE Enable 1 FL_CH4_EN Lower threshold IIR filter enable channel 4 4 4 read-write DISABLE Disable 0 ENABLE Enable 1 FL_CH5_EN Lower threshold IIR filter enable channel 5 5 5 read-write DISABLE Disable 0 ENABLE Enable 1 FL_CH6_EN Lower threshold IIR filter enable channel 6 6 6 read-write DISABLE Disable 0 ENABLE Enable 1 FL_CH7_EN Lower threshold IIR filter enable channel 7 7 7 read-write DISABLE Disable 0 ENABLE Enable 1 FL_CH8_EN Lower threshold IIR filter enable channel 8 8 8 read-write DISABLE Disable 0 ENABLE Enable 1 FL_CH9_EN Lower threshold IIR filter enable channel 9 9 9 read-write DISABLE Disable 0 ENABLE Enable 1 FL_CH10_EN Lower threshold IIR filter enable channel 10 10 10 read-write DISABLE Disable 0 ENABLE Enable 1 FL_CH11_EN Lower threshold IIR filter enable channel 11 11 11 read-write DISABLE Disable 0 ENABLE Enable 1 FILT_OUT0 ADC1 or filter output channel 0 register 0x70 32 read-write 0x0 0xfffff000 FILT_OUT_CH0 ADC or filter output value channel 0 0 11 read-only WFR0 Wait for read mode 16 16 read-write DISABLE Overwrite mode 0 ENABLE Wait for read mode enabled 1 VF0 Valid flag 17 17 read-only NOT_VALID No new valid data available 0 VALID Result register contains valid data and has not yet been read 1 OF0 Overrun flag 18 18 read-only NO_OVERRUN Result register not overwritten 0 OVERRUN Result register overwritten 1 FILT_OUT1 ADC1 or filter output channel 1 register 0x74 32 read-write 0x0 0xfffff000 FILT_OUT_CH1 ADC or filter output value channel 1 0 11 read-only WFR1 Wait for read mode 16 16 read-write DISABLE Overwrite mode 0 ENABLE Wait for read mode enabled 1 VF1 Valid flag 17 17 read-only NOT_VALID No new valid data available 0 VALID Result register contains valid data and has not yet been read 1 OF1 Overrun flag 18 18 read-only NO_OVERRUN Result register not overwritten 0 OVERRUN Result register overwritten 1 FILT_OUT10 ADC1 or filter output channel 10 register 0x98 32 read-write 0x0 0xfffff000 FILT_OUT_CH10 ADC or filter output value channel 10 0 11 read-only WFR10 Wait for read mode 16 16 read-write DISABLE Overwrite mode 0 ENABLE Wait for read mode enabled 1 VF10 Valid flag 17 17 read-only NOT_VALID No new valid data available 0 VALID Result register contains valid data and has not yet been read 1 OF10 Overrun flag 18 18 read-only NO_OVERRUN Result register not overwritten 0 OVERRUN Result register overwritten 1 FILT_OUT11 ADC1 or filter output channel 11 register 0x9C 32 read-write 0x0 0xfffff000 FILT_OUT_CH11 ADC or filter output value channel 11 0 11 read-only WFR11 Wait for read mode 16 16 read-write DISABLE Overwrite mode 0 ENABLE Wait for read mode enabled 1 VF11 Valid flag 17 17 read-only NOT_VALID No new valid data available 0 VALID Result register contains valid data and has not yet been read 1 OF11 Overrun flag 18 18 read-only NO_OVERRUN Result register not overwritten 0 OVERRUN Result register overwritten 1 FILT_OUT12 ADC1 or filter output channel 12 register 0x110 32 read-write 0x0 0xfffff000 FILT_OUT_CH12 ADC or filter output value channel 12 0 11 read-only WFR12 Wait for read mode 16 16 read-write DISABLE Overwrite mode 0 ENABLE Wait for read mode enabled 1 VF12 Valid flag 17 17 read-only NOT_VALID No new valid data available 0 VALID Result register contains valid data and has not yet been read 1 OF12 Overrun flag 18 18 read-only NO_OVERRUN Result register not overwritten 0 OVERRUN Result register overwritten 1 FILT_OUT2 ADC1 or filter output channel 2 register 0x78 32 read-write 0x0 0xfffff000 FILT_OUT_CH2 ADC or filter output value channel 2 0 11 read-only WFR2 Wait for read mode 16 16 read-write DISABLE Overwrite mode 0 ENABLE Wait for read mode enabled 1 VF2 Valid flag 17 17 read-only NOT_VALID No new valid data available 0 VALID Result register contains valid data and has not yet been read 1 OF2 Overrun flag 18 18 read-only NO_OVERRUN Result register not overwritten 0 OVERRUN Result register overwritten 1 FILT_OUT3 ADC1 or filter output channel 3 register 0x7C 32 read-write 0x0 0xfffff000 FILT_OUT_CH3 ADC or filter output value channel 3 0 11 read-only WFR3 Wait for read mode 16 16 read-write DISABLE Overwrite mode 0 ENABLE Wait for read mode enabled 1 VF3 Valid flag 17 17 read-only NOT_VALID No new valid data available 0 VALID Result register contains valid data and has not yet been read 1 OF3 Overrun flag 18 18 read-only NO_OVERRUN Result register not overwritten 0 OVERRUN Result register overwritten 1 FILT_OUT4 ADC1 or filter output channel 4 register 0x80 32 read-write 0x0 0xfffff000 FILT_OUT_CH4 ADC or filter output value channel 4 0 11 read-only WFR4 Wait for read mode 16 16 read-write DISABLE Overwrite mode 0 ENABLE Wait for read mode enabled 1 VF4 Valid flag 17 17 read-only NOT_VALID No new valid data available 0 VALID Result register contains valid data and has not yet been read 1 OF4 Overrun flag 18 18 read-only NO_OVERRUN Result register not overwritten 0 OVERRUN Result register overwritten 1 FILT_OUT5 ADC1 or filter output channel 5 register 0x84 32 read-write 0x0 0xfffff000 FILT_OUT_CH5 ADC or filter output value channel 5 0 11 read-only WFR5 Wait for read mode 16 16 read-write DISABLE Overwrite mode 0 ENABLE Wait for read mode enabled 1 VF5 Valid flag 17 17 read-only NOT_VALID No new valid data available 0 VALID Result register contains valid data and has not yet been read 1 OF5 Overrun flag 18 18 read-only NO_OVERRUN Result register not overwritten 0 OVERRUN Result register overwritten 1 FILT_OUT6 ADC1 or filter output channel 6 register 0x88 32 read-write 0x0 0xfffff000 FILT_OUT_CH6 ADC or filter output value channel 6 0 11 read-only WFR6 Wait for read mode 16 16 read-write DISABLE Overwrite mode 0 ENABLE Wait for read mode enabled 1 VF6 Valid flag 17 17 read-only NOT_VALID No new valid data available 0 VALID Result register contains valid data and has not yet been read 1 OF6 Overrun flag 18 18 read-only NO_OVERRUN Result register not overwritten 0 OVERRUN Result register overwritten 1 FILT_OUT7 ADC1 or filter output channel 7 register 0x8C 32 read-write 0x0 0xfffff000 FILT_OUT_CH7 ADC or filter output value channel 7 0 11 read-only WFR7 Wait for read mode 16 16 read-write DISABLE Overwrite mode 0 ENABLE Wait for read mode enabled 1 VF7 Valid flag 17 17 read-only NOT_VALID No new valid data available 0 VALID Result register contains valid data and has not yet been read 1 OF7 Overrun flag 18 18 read-only NO_OVERRUN Result register not overwritten 0 OVERRUN Result register overwritten 1 FILT_OUT8 ADC1 or filter output channel 8 register 0x90 32 read-write 0x0 0xfffff000 FILT_OUT_CH8 ADC or filter output value channel 8 0 11 read-only WFR8 Wait for read mode 16 16 read-write DISABLE Overwrite mode 0 ENABLE Wait for read mode enabled 1 VF8 Valid flag 17 17 read-only NOT_VALID No new valid data available 0 VALID Result register contains valid data and has not yet been read 1 OF8 Overrun flag 18 18 read-only NO_OVERRUN Result register not overwritten 0 OVERRUN Result register overwritten 1 FILT_OUT9 ADC1 or filter output channel 9 register 0x94 32 read-write 0x0 0xfffff000 FILT_OUT_CH9 ADC or filter output value channel 9 0 11 read-only WFR9 Wait for read mode 16 16 read-write DISABLE Overwrite mode 0 ENABLE Wait for read mode enabled 1 VF9 Valid flag 17 17 read-only NOT_VALID No new valid data available 0 VALID Result register contains valid data and has not yet been read 1 OF9 Overrun flag 18 18 read-only NO_OVERRUN Result register not overwritten 0 OVERRUN Result register overwritten 1 FILT_OUTEIM ADC1 or filter output of EIM register 0x120 32 read-write 0x0 0xfffff000 FILT_OUT_EIM ADC or filter output value for last EIM measurement 0 11 read-only WFR_EIM Wait for read mode 16 16 read-write DISABLE Overwrite mode 0 ENABLE Wait for read mode enabled 1 VF_EIM Valid flag 17 17 read-only NOT_VALID No new valid data available 0 VALID Result register contains valid data and has not yet been read 1 OF_EIM Overrun flag 18 18 read-only NO_OVERRUN Result register not overwritten 0 OVERRUN Result register overwritten 1 FILT_UP_CTRL Upper threshold filter enable 0xB0 32 read-write 0xffff 0xffffffff FU_CH0_EN Upper threshold IIR filter enable channel 0 0 0 read-write DISABLE Disable 0 ENABLE Enable 1 FU_CH1_EN Upper threshold IIR filter enable channel 1 1 1 read-write DISABLE Disable 0 ENABLE Enable 1 FU_CH2_EN Upper threshold IIR filter enable channel 2 2 2 read-write DISABLE Disable 0 ENABLE Enable 1 FU_CH3_EN Upper threshold IIR filter enable channel 3 3 3 read-write DISABLE Disable 0 ENABLE Enable 1 FU_CH4_EN Upper threshold IIR filter enable channel 4 4 4 read-write DISABLE Disable 0 ENABLE Enable 1 FU_CH5_EN Upper threshold IIR filter enable channel 5 5 5 read-write DISABLE Disable 0 ENABLE Enable 1 FU_CH6_EN Upper threshold IIR filter enable channel 6 6 6 read-write DISABLE Disable 0 ENABLE Enable 1 FU_CH7_EN Upper threshold IIR filter enable channel 7 7 7 read-write DISABLE Disable 0 ENABLE Enable 1 FU_CH8_EN Upper threshold IIR filter enable channel 8 8 8 read-write DISABLE Disable 0 ENABLE Enable 1 FU_CH9_EN Upper threshold IIR filter enable channel 9 9 9 read-write DISABLE Disable 0 ENABLE Enable 1 FU_CH10_EN Upper threshold IIR filter enable channel 10 10 10 read-write DISABLE Disable 0 ENABLE Enable 1 FU_CH11_EN Upper threshold IIR filter enable channel 11 11 11 read-write DISABLE Disable 0 ENABLE Enable 1 FILTCOEFF0_11 Filter coefficients measurement unit channel 0-11 register 0x60 32 read-write 0xaaaaaa 0xffffffff CH0 Filter coefficients ADC channel 0 0 1 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 CH1 Filter coefficients ADC channel 1 2 3 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 CH2 Filter coefficients ADC channel 2 4 5 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 CH3 Filter coefficients ADC channel 3 6 7 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 CH4 Filter coefficients ADC channel 4 8 9 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 CH5 Filter coefficients ADC channel 5 10 11 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 CH6 Filter Coefficients ADC channel 6 12 13 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 CH7 Filter coefficients ADC channel 7 14 15 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 CH8 Filter coefficients ADC channel 8 16 17 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 CH9 Filter coefficients ADC channel 9 18 19 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 CH10 Filter coefficients ADC channel 10 20 21 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 CH11 Filter coefficients ADC channel 11 22 23 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 IRQCLR_1 ADC1 interrupt status clear 1 register 0x6C 32 read-write 0x0 0xffffffff VBATSEN_ISC ADC1 VBAT_SENSE interrupt status clear 0 0 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 VS_ISC ADC1 VS interrupt status clear 1 1 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 MON1_ISC ADC1 MON 1 interrupt status clear 2 2 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 MON2_ISC ADC1 MON 2 interrupt status clear 3 3 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 MON3_ISC ADC1 MON 3 interrupt status clear 4 4 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 MON4_ISC ADC1 MON 4 interrupt status clear 5 5 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 MON5_ISC ADC1 MON 5 interrupt status clear 6 6 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 P2_1_ISC ADC1 Port 2.1 interrupt status clear 7 7 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 P2_2_ISC ADC1 Port 2.2 interrupt status clear 8 8 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 P2_3_ISC ADC1 Port 2.3 interrupt status clear 9 9 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 P2_6_ISC ADC1 Port 2.6 interrupt status clear 10 10 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 P2_7_ISC ADC1 Port 2.7 interrupt status clear 11 11 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 P2_0_ISC ADC1 Port 2.0 interrupt status clear 12 12 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 EIM_ISC Exceptional interrupt measurement (EIM) status clear 16 16 write-only INACTIVE No EIM cleared 0 ACTIVE EIM cleared 1 ESM_ISC Exceptional sequence measurement (ESM) status clear 17 17 write-only INACTIVE No ESM has cleared 0 ACTIVE ESM cleared 1 DU1LO_ISC Differential unit 1 lower interrupt status clear 24 24 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 DU1UP_ISC Differential unit 1 lower interrupt status clear 25 25 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 DU2LO_ISC Differential unit 2 lower interrupt status clear 26 26 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 DU2UP_ISC Differential unit 2 lower interrupt status clear 27 27 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 DU3LO_ISC Differential unit 3 lower interrupt status clear 28 28 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 DU3UP_ISC Differential unit 3 lower interrupt status clear 29 29 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 DU4LO_ISC Differential unit 4 lower interrupt status clear 30 30 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 DU4UP_ISC Differential unit 4 lower interrupt status clear 31 31 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 IRQCLR_2 ADC1 interrupt status clear 2 register 0x108 32 read-write 0x0 0xffffffff VS_LO_ISC ADC1 VS lower threshold interrupt status clear 1 1 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 MON1_LO_ISC ADC1 MON 1 lower threshold interrupt status clear 2 2 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 MON2_LO_ISC ADC1 MON 2 lower threshold interrupt status clear 3 3 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 MON3_LO_ISC ADC1 MON 3 lower threshold interrupt status clear 4 4 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 MON4_LO_ISC ADC1 MON 4 lower threshold interrupt status clear 5 5 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 MON5_LO_ISC ADC1 MON 5 lower threshold interrupt status clear 6 6 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 P2_1_LO_ISC ADC1 port 2.1 lower threshold interrupt status clear 7 7 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 P2_2_LO_ISC ADC1 port 2.2 lower threshold interrupt status clear 8 8 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 P2_3_LO_ISC ADC1 port 2.3 lower threshold interrupt status clear 9 9 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 P2_6_LO_ISC ADC1 port 2.6 lower threshold interrupt status clear 10 10 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 P2_7_LO_ISC ADC1 port 2.7 lower threshold interrupt status clear 11 11 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 VS_UP_ISC ADC1 VS upper threshold interrupt status clear 17 17 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 MON1_UP_ISC ADC1 MON 1 upper threshold interrupt status clear 18 18 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 MON2_UP_ISC ADC1 MON 2 upper threshold interrupt status clear 19 19 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 MON3_UP_ISC ADC1 MON 3 upper threshold interrupt status clear 20 20 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 MON4_UP_ISC ADC1 MON 4 upper threshold interrupt status clear 21 21 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 MON5_UP_ISC ADC1 MON 5 upper threshold interrupt status clear 22 22 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 P2_1_UP_ISC ADC1 port 2.1 upper threshold interrupt status clear 23 23 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 P2_2_UP_ISC ADC1 port 2.2 upper threshold interrupt status clear 24 24 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 P2_3_UP_ISC ADC1 port 2.3 upper threshold interrupt status clear 25 25 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 P2_6_UP_ISC ADC1 port 2.6 upper threshold interrupt status clear 26 26 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 P2_7_UP_ISC ADC1 port 2.7 upper threshold interrupt status clear 27 27 write-only INACTIVE Interrupt status is not cleared 0 ACTIVE Interrupt status is cleared 1 IRQEN_1 ADC1 interrupt enable 1 register 0x68 32 read-write 0x0 0xffffffff VBATSEN_IEN ADC1 VBAT_SENSE interrupt enable 0 0 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 VS_IEN ADC1 VS interrupt enable 1 1 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 MON1_IEN ADC1 MON 1 interrupt enable 2 2 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 MON2_IEN ADC1 MON 2 interrupt enable 3 3 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 MON3_IEN ADC1 MON 3 interrupt enable 4 4 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 MON4_IEN ADC1 MON 4 interrupt enable 5 5 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 MON5_IEN ADC1 MON 5 interrupt enable 6 6 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 P2_1_IEN ADC1 Port 2.1 interrupt enable 7 7 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 P2_2_IEN ADC1 Port 2.2 interrupt enable 8 8 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 P2_3_IEN ADC1 Port 2.3 interrupt enable 9 9 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 P2_6_IEN ADC1 Port 2.6 interrupt enable 10 10 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 P2_7_IEN ADC1 Port 2.7 interrupt enable 11 11 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 P2_0_IEN ADC1 Port 2.0 interrupt enable 12 12 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 EIM_IEN Exceptional interrupt measurement (EIM) interrupt enable 16 16 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 ESM_IEN Exceptional sequence measurement (ESM) interrupt enable 17 17 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 DU1LO_IEN Differential unit 1 lower interrupt enable 24 24 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 DU1UP_IEN Differential unit 1 upper interrupt enable 25 25 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 DU2LO_IEN Differential unit 2 lower interrupt enable 26 26 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 DU2UP_IEN Differential unit 2 upper interrupt enable 27 27 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 DU3LO_IEN Differential unit 3 lower interrupt enable 28 28 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 DU3UP_IEN Differential unit 3 upper interrupt enable 29 29 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 DU4LO_IEN Differential unit 4 lower interrupt enable 30 30 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 DU4UP_IEN Differential unit 4 upper interrupt enable 31 31 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 IRQEN_2 ADC1 interrupt enable 2 register 0x10C 32 read-write 0x0 0xffffffff VS_LO_IEN ADC1 VS lower threshold interrupt enable 1 1 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 MON1_LO_IEN ADC1 MON 1 lower threshold interrupt enable 2 2 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 MON2_LO_IEN ADC1 MON 2 lower threshold interrupt enable 3 3 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 MON3_LO_IEN ADC1 MON 3 lower threshold interrupt enable 4 4 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 MON4_LO_IEN ADC1 MON 4 lower threshold interrupt enable 5 5 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 MON5_LO_IEN ADC1 MON 5 lower threshold interrupt enable 6 6 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 P2_1_LO_IEN ADC1 port 2.1 lower threshold interrupt enable 7 7 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 P2_2_LO_IEN ADC1 port 2.2 lower threshold interrupt enable 8 8 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 P2_3_LO_IEN ADC1 port 2.3 lower threshold interrupt enable 9 9 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 P2_6_LO_IEN ADC1 port 2.6 lower threshold interrupt enable 10 10 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 P2_7_LO_IEN ADC1 port 2.7 lower threshold interrupt enable 11 11 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 VS_UP_IEN ADC1 VS upper threshold interrupt enable 17 17 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 MON1_UP_IEN ADC1 MON 1 upper threshold interrupt enable 18 18 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 MON2_UP_IEN ADC1 MON 2 upper threshold interrupt enable 19 19 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 MON3_UP_IEN ADC1 MON 3 upper threshold interrupt enable 20 20 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 MON4_UP_IEN ADC1 MON 4 upper threshold interrupt enable 21 21 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 MON5_UP_IEN ADC1 MON 5 upper threshold interrupt enable 22 22 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 P2_1_UP_IEN ADC1 port 2.1 upper threshold interrupt enable 23 23 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 P2_2_UP_IEN ADC1 port 2.2 upper threshold interrupt enable 24 24 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 P2_3_UP_IEN ADC1 port 2.3 upper threshold interrupt enable 25 25 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 P2_6_UP_IEN ADC1 port 2.6 upper threshold interrupt enable 26 26 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 P2_7_UP_IEN ADC1 port 2.7 upper threshold interrupt enable 27 27 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 IRQS_1 ADC1 interrupt status 1 register 0x64 32 read-write 0x0 0xffffffff VBATSEN_IS ADC1 channel 1 interrupt status 0 0 read-write INACTIVE No channel 1 interrupt has occurred 0 ACTIVE Channel 1 interrupt has occurred 1 VS_IS ADC1 channel 0 interrupt status 1 1 read-write INACTIVE No channel 0 interrupt has occurred 0 ACTIVE Channel 0 interrupt has occurred 1 MON1_IS ADC1 channel 2 interrupt status 2 2 read-write INACTIVE No channel 2 interrupt has occurred 0 ACTIVE Channel 2 interrupt has occurred 1 MON2_IS ADC1 channel 3 interrupt status 3 3 read-write INACTIVE No channel 3 interrupt has occurred 0 ACTIVE Channel 3 interrupt has occurred 1 MON3_IS ADC1 channel 4 interrupt status 4 4 read-write INACTIVE No channel 4 interrupt has occurred 0 ACTIVE Channel 4 interrupt has occurred 1 MON4_IS ADC1 channel 5 interrupt status 5 5 read-write INACTIVE No channel 5 interrupt has occurred 0 ACTIVE Channel 5 interrupt has occurred 1 MON5_IS ADC1 channel 6 interrupt status 6 6 read-write INACTIVE No channel 6 interrupt has occurred 0 ACTIVE Channel 6 interrupt has occurred 1 P2_1_IS ADC1 channel 7 interrupt status 7 7 read-write INACTIVE No channel 7 interrupt has occurred 0 ACTIVE Channel 7 interrupt has occurred 1 P2_2_IS ADC1 channel 8 interrupt status 8 8 read-write INACTIVE No channel 8 interrupt has occurred 0 ACTIVE Channel 8 interrupt has occurred 1 P2_3_IS ADC1 channel 9 interrupt status 9 9 read-write INACTIVE No channel 9 interrupt has occurred 0 ACTIVE Channel 9 interrupt has occurred 1 P2_6_IS ADC1 channel 10 interrupt status 10 10 read-write INACTIVE No channel 10 interrupt has occurred 0 ACTIVE Channel 10 interrupt has occurred 1 P2_7_IS ADC1 channel 11 interrupt status 11 11 read-write INACTIVE No channel 11 interrupt has occurred 0 ACTIVE Channel 11 interrupt has occurred 1 P2_0_IS ADC1 channel 12 interrupt status 12 12 read-write INACTIVE No channel 12 interrupt has occurred 0 ACTIVE Channel 12 interrupt has occurred 1 EIM_IS Exceptional interrupt measurement (EIM) status 16 16 read-write INACTIVE No EIM occurred 0 ACTIVE EIM occurred 1 ESM_IS Exceptional sequence measurement (ESM) status 17 17 read-write INACTIVE No ESM has occurred 0 ACTIVE ESM occurred 1 DU1LO_IS ADC1 Differential Unit 1 (DU1) lower channel interrupt status 24 24 read-write INACTIVE No DU lower channel Interrupt has occurred 0 ACTIVE DU lower channel interrupt has occurred 1 DU1UP_IS ADC1 differential unit 1 (DU1) upper channel interrupt status 25 25 read-write INACTIVE No DU upper Channel Interrupt has occurred 0 ACTIVE DU upper Channel Interrupt has occurred 1 DU2LO_IS ADC1 differential unit 2 (DU2) lower channel interrupt status 26 26 read-write INACTIVE No DU lower channel interrupt has occurred 0 ACTIVE DU lower channel interrupt has occurred 1 DU2UP_IS ADC1 differential unit 2 (DU2) upper channel interrupt status 27 27 read-write INACTIVE No DU upper channel interrupt has occurred 0 ACTIVE DU upper channel interrupt has occurred 1 DU3LO_IS ADC1 differential unit 3 (DU3) lower Channel interrupt status 28 28 read-write INACTIVE No DU lower channel interrupt has occurred 0 ACTIVE DU lower channel interrupt has occurred 1 DU3UP_IS ADC1 differential unit 3 (DU3) upper channel interrupt status 29 29 read-write INACTIVE No DU upper channel interrupt has occurred 0 ACTIVE DU upper channel interrupt has occurred 1 DU4LO_IS ADC1 differential unit 4 (DU4) lower channel interrupt status 30 30 read-write INACTIVE No DU lower channel interrupt has occurred 0 ACTIVE DU lower channel interrupt has occurred 1 DU4UP_IS ADC1 differential unit 4 (DU4) upper channel interrupt dtatus 31 31 read-write INACTIVE No DU upper channel interrupt has occurred 0 ACTIVE DU upper channel interrupt has occurred 1 IRQS_2 ADC1 interrupt status 2 register 0x100 32 read-write 0x0 0xffffffff VS_LO_IS ADC1 VS lower threshold interrupt status 1 1 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 MON1_LO_IS ADC1 MON 1 lower threshold interrupt status 2 2 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 MON2_LO_IS ADC1 MON 2 lower threshold interrupt status 3 3 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 MON3_LO_IS ADC1 MON 3 lower threshold interrupt status 4 4 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 MON4_LO_IS ADC1 MON 4 lower threshold interrupt status 5 5 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 MON5_LO_IS ADC1 MON 5 lower threshold interrupt status 6 6 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 P2_1_LO_IS ADC1 port 2.1 lower threshold interrupt status 7 7 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 P2_2_LO_IS ADC1 port 2.2 lower threshold interrupt status 8 8 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 P2_3_LO_IS ADC1 port 2.3 lower threshold interrupt status 9 9 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 P2_6_LO_IS ADC1 port 2.6 lower threshold interrupt status 10 10 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 P2_7_LO_IS ADC1 port 2.7 lower threshold interrupt status 11 11 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 VS_UP_IS ADC1 VS upper threshold interrupt status 17 17 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 MON1_UP_IS ADC1 MON 1 upper threshold interrupt status 18 18 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 MON2_UP_IS ADC1 MON 2 upper threshold interrupt status 19 19 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 MON3_UP_IS ADC1 MON 3 upper threshold interrupt status 20 20 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 MON4_UP_IS ADC1 MON 4 upper threshold interrupt status 21 21 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 MON5_UP_IS ADC1 MON 5 upper threshold interrupt status 22 22 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 P2_1_UP_IS ADC1 port 2.1 upper threshold interrupt status 23 23 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 P2_2_UP_IS ADC1 port 2.2 upper threshold interrupt status 24 24 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 P2_3_UP_IS ADC1 port 2.3 upper threshold interrupt status 25 25 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 P2_6_UP_IS ADC1 port 2.6 upper threshold interrupt status 26 26 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 P2_7_UP_IS ADC1 port 2.7 upper threshold interrupt status 27 27 read-write INACTIVE No interrupt has occurred 0 ACTIVE Interrupt has occurred 1 MAX_TIME Maximum time for software mode register 0x10 32 read-write 0x0 0xffffffff MAX_TIME Maximum Time in software mode 0 7 read-write MIN Software mode is immediately left 0 MAX Software mode is active for 12.75 us 255 MMODE0_11 Overvoltage measurement mode of channel 0-11 register 0xF8 32 read-write 0x0 0xffffffff MMODE_0 Measurement mode channel 0 0 1 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MMODE_1 Measurement mode channel 1 2 3 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MMODE_2 Measurement mode channel 2 4 5 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MMODE_3 Measurement mode channel 3 6 7 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MMODE_4 Measurement mode channel 4 8 9 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MMODE_5 Measurement mode channel 5 10 11 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MMODE_6 Measurement mode channel 6 12 13 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MMODE_7 Measurement mode channel 7 14 15 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MMODE_8 Measurement mode channel 8 16 17 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MMODE_9 Measurement mode channel 9 18 19 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MMODE_10 Measurement mode channel 10 20 21 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MMODE_11 Measurement mode channel 11 22 23 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MMODE_D1 Measurement mode differential channel 1 24 25 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MMODE_D2 Measurement mode differential channel 2 26 27 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MMODE_D3 Measurement mode differential channel 3 28 29 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MMODE_D4 Measurement mode differential channel 4 30 31 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 SQ_FB Sequencer feedback register 0x4 32 read-only 0x0 0xff0000f0 SQ_FB Current sequence that caused software mode 0 4 read-only SQ0 Sequence 0 enable 0 SQ1 Sequence 1 enable 1 SQ2 Sequence 2 enable 2 SQ3 Sequence 3 enable 3 SQ4 Sequence 4 enable 4 SQ5 Sequence 5 enable 5 SQ6 Sequence 6 enable 6 SQ7 Sequence 7 enable 7 SQ8 Sequence 8 enable 8 SQ9 Sequence 9 enable 9 SQ10 Sequence 10 enable 10 SQ11 Sequence 11 enable 11 ESM ESM 12 SUSPEND_SW Software mode per flag 14 SUSPEND_DSG Debug suspend mode 15 SQ_STOP ADC1 sequencer stop signal for DPP 8 8 read-only DPP_RUNNING Postprocessing sequencer in running mode 0 DPP_STOPPED Postprocessing sequencer stopped/software mode entered 1 EIM_ACTIVE ADC1 EIM active 9 9 read-only NOT_ACTIVE EIM not active 0 ACTIVE EIM active 1 ESM_ACTIVE ADC1 ESM active 10 10 read-only NOT_ACTIVE ESM not active 0 ACTIVE ESM active 1 SQx Current active ADC1 sequence 11 14 read-only SQ0 Sequence 0 enable 0 SQ1 Sequence 1 enable 1 SQ2 Sequence 2 enable 2 SQ3 Sequence 3 enable 3 SQ4 Sequence 4 enable 4 SQ5 Sequence 5 enable 5 SQ6 Sequence 6 enable 6 SQ7 Sequence 7 enable 7 SQ8 Sequence 8 enable 8 SQ9 Sequence 9 enable 9 SQ10 Sequence 10 enable 10 SQ11 Sequence 11 enable 11 CHx Current ADC1 channel 16 19 read-only CH0 Channel 0 enable 0 CH1 Channel 1 enable 1 CH2 Channel 2 enable 2 CH3 Channel 3 enable 3 CH4 Channel 4 enable 4 CH5 Channel 5 enable 5 CH6 Channel 6 enable 6 CH7 Channel 7 enable 7 CH8 Channel 8 enable 8 CH9 Channel 9 enable 9 CH10 Channel 10 enable 10 CH11 Channel 11 enable 11 SQ0_1 Measurement unit 1 channel enable bits for cycle 0-1 register 0x20 32 read-write 0x0 0xffffffff SQ0 Sequence 0 channel enable 0 11 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 CH7_EN Channel 7 enable 128 CH8_EN Channel 8 enable 256 CH9_EN Channel 9 enable 512 CH10_EN Channel 10 enable 1024 CH11_EN Channel 11 enable 2048 SQ1 Sequence 1 channel enable 16 27 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 CH7_EN Channel 7 enable 128 CH8_EN Channel 8 enable 256 CH9_EN Channel 9 enable 512 CH10_EN Channel 10 enable 1024 CH11_EN Channel 11 enable 2048 SQ10_11 Measurement unit 1 channel enable bits for cycle 10-11 register 0x34 32 read-write 0x0 0xffffffff SQ10 Sequence 10 channel enable 0 11 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 CH7_EN Channel 7 enable 128 CH8_EN Channel 8 enable 256 CH9_EN Channel 9 enable 512 CH10_EN Channel 10 enable 1024 CH11_EN Channel 11 enable 2048 SQ11 Sequence 11 channel enable 16 27 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 CH7_EN Channel 7 enable 128 CH8_EN Channel 8 enable 256 CH9_EN Channel 9 enable 512 CH10_EN Channel 10 enable 1024 CH11_EN Channel 11 enable 2048 SQ2_3 Measurement unit 1 channel enable bits for cycle 2-3 register 0x24 32 read-write 0x0 0xffffffff SQ2 Sequence 2 channel enable 0 11 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 CH7_EN Channel 7 enable 128 CH8_EN Channel 8 enable 256 CH9_EN Channel 9 enable 512 CH10_EN Channel 10 enable 1024 CH11_EN Channel 11 enable 2048 SQ3 Sequence 3 channel enable 16 27 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 CH7_EN Channel 7 enable 128 CH8_EN Channel 8 enable 256 CH9_EN Channel 9 enable 512 CH10_EN Channel 10 enable 1024 CH11_EN Channel 11 enable 2048 SQ4_5 Measurement unit 1 channel enable bits for cycle 4-5 register 0x28 32 read-write 0x0 0xffffffff SQ4 Sequence 4 channel enable 0 11 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 CH7_EN Channel 7 enable 128 CH8_EN Channel 8 enable 256 CH9_EN Channel 9 enable 512 CH10_EN Channel 10 enable 1024 CH11_EN Channel 11 enable 2048 SQ5 Sequence 5 channel enable 16 27 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 CH7_EN Channel 7 enable 128 CH8_EN Channel 8 enable 256 CH9_EN Channel 9 enable 512 CH10_EN Channel 10 enable 1024 CH11_EN Channel 11 enable 2048 SQ6_7 Measurement unit 1 channel enable bits for cycle 6-7 register 0x2C 32 read-write 0x0 0xffffffff SQ6 Sequence 6 channel enable 0 11 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 CH7_EN Channel 7 enable 128 CH8_EN Channel 8 enable 256 CH9_EN Channel 9 enable 512 CH10_EN Channel 10 enable 1024 CH11_EN Channel 11 enable 2048 SQ7 Sequence 7 channel enable 16 27 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 CH7_EN Channel 7 enable 128 CH8_EN Channel 8 enable 256 CH9_EN Channel 9 enable 512 CH10_EN Channel 10 enable 1024 CH11_EN Channel 11 enable 2048 SQ8_9 Measurement unit 1 channel enable bits for cycle 8-9 register 0x30 32 read-write 0x0 0xffffffff SQ8 Sequence 8 channel enable 0 11 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 CH7_EN Channel 7 enable 128 CH8_EN Channel 8 enable 256 CH9_EN Channel 9 enable 512 CH10_EN Channel 10 enable 1024 CH11_EN Channel 11 enable 2048 SQ9 Sequence 9 channel enable 16 27 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 CH7_EN Channel 7 enable 128 CH8_EN Channel 8 enable 256 CH9_EN Channel 9 enable 512 CH10_EN Channel 10 enable 1024 CH11_EN Channel 11 enable 2024 STS_1 ADC1 status 1 register 0x124 32 read-write 0x0 0xffffffff DU1LO_STS ADC1 differential unit 1 (DU1) lower channel status 24 24 read-write INACTIVE No DU lower channel status has occurred 0 ACTIVE DU lower channel status has occurred 1 DU1UP_STS ADC1 differential unit 1 (DU1) upper channel status 25 25 read-write INACTIVE No DU upper channel status has occurred 0 ACTIVE DU upper channel status has occurred 1 DU2LO_STS ADC1 differential unit 2 (DU2) lower channel status 26 26 read-write INACTIVE No DU lower channel status has occurred 0 ACTIVE DU lower channel status has occurred 1 DU2UP_STS ADC1 differential unit 2 (DU2) upper channel status 27 27 read-write INACTIVE No DU upper channel status has occurred 0 ACTIVE DU upper channel status has occurred 1 DU3LO_STS ADC1 differential unit 3 (DU3) lower channel status 28 28 read-write INACTIVE No DU lower channel status has occurred 0 ACTIVE DU lower channel status has occurred 1 DU3UP_STS ADC1 differential unit 3 (DU3) upper channel status 29 29 read-write INACTIVE No DU upper channel status has occurred 0 ACTIVE DU upper channel status has occurred 1 DU4LO_STS ADC1 differential unit 4 (DU4) lower channel status 30 30 read-write INACTIVE No DU lower channel status has occurred 0 ACTIVE DU lower channel status has occurred 1 DU4UP_STS ADC1 differential unit 4 (DU4) upper channel status 31 31 read-write INACTIVE No DU upper channel status has occurred 0 ACTIVE DU upper channel status has occurred 1 STS_2 ADC1 status 2 register 0x104 32 read-only 0x0 0xffffffff VS_LO_STS ADC1 VS lower threshold status 1 1 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 MON1_LO_STS ADC1 MON 1 lower threshold status 2 2 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 MON2_LO_STS ADC1 MON 2 lower threshold status 3 3 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 MON3_LO_STS ADC1 MON 3 lower threshold status 4 4 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 MON4_LO_STS ADC1 MON 4 lower threshold status 5 5 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 MON5_LO_STS ADC1 MON 5 lower threshold status 6 6 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 P2_1_LO_STS ADC1 port 2.1 lower threshold status 7 7 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 P2_2_LO_STS ADC1 port 2.2 lower threshold status 8 8 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 P2_3_LO_STS ADC1 port 2.3 lower threshold status 9 9 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 P2_6_LO_STS ADC1 port 2.6 lower threshold status 10 10 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 P2_7_LO_STS ADC1 port 2.7 lower threshold status 11 11 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 VS_UP_STS ADC1 VS upper threshold Status 17 17 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 MON1_UP_STS ADC1 MON 1 upper threshold Status 18 18 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 MON2_UP_STS ADC1 MON 2 upper threshold Status 19 19 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 MON3_UP_STS ADC1 MON 3 upper threshold Status 20 20 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 MON4_UP_STS ADC1 MON 4 upper threshold Status 21 21 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 MON5_UP_STS ADC1 MON 5 upper threshold Status 22 22 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 P2_1_UP_STS ADC1 port 2.1 upper threshold Status 23 23 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 P2_2_UP_STS ADC1 port 2.2 upper threshold Status 24 24 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 P2_3_UP_STS ADC1 port 2.3 upper threshold status 25 25 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 P2_6_UP_STS ADC1 port 2.6 upper threshold status 26 26 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 P2_7_UP_STS ADC1 port 2.7 upper threshold status 27 27 read-only BELOW_LIMIT Status below upper threshold 0 ABOVE_LIMIT Upper threshold exceeded 1 STSCLR_1 ADC1 status clear 1 register 0x128 32 read-write 0x0 0xffffffff DU1LO_SC ADC1 differential unit 1 (DU1) lower channel status clear 24 24 write-only INACTIVE No DU lower channel status has occurred 0 ACTIVE DU lower channel status has occurred 1 DU1UP_SC ADC1 differential unit 1 (DU1) upper channel status clear 25 25 write-only INACTIVE No DU upper channel status has occurred 0 ACTIVE DU upper channel status has occurred 1 DU2LO_SC ADC1 differential unit 2 (DU2) lower channel status clear 26 26 write-only INACTIVE No DU lower channel status has occurred 0 ACTIVE DU lower channel status has occurred 1 DU2UP_SC ADC1 differential unit 2 (DU2) upper channel status clear 27 27 write-only INACTIVE No DU upper channel status has occurred 0 ACTIVE DU upper channel status has occurred 1 DU3LO_SC ADC1 differential unit 3 (DU3) lower channel status clear 28 28 write-only INACTIVE No DU lower channel status has occurred 0 ACTIVE DU lower channel status has occurred 1 DU3UP_SC ADC1 differential unit 3 (DU3) upper channel status clear 29 29 write-only INACTIVE No DU upper channel status has occurred 0 ACTIVE DU upper channel status has occurred 1 DU4LO_SC ADC1 differential unit 4 (DU4) lower channel status clear 30 30 write-only INACTIVE No DU lower channel status has occurred 0 ACTIVE DU lower channel status has occurred 1 DU4UP_SC ADC1 differential unit 4 (DU4) upper channel status clear 31 31 write-only INACTIVE No DU upper channel status has occurred 0 ACTIVE DU upper channel status has occurred 1 TH0_3_LOWER Lower comparator trigger level channel 0-3 0x40 32 read-write 0x1d2f423a 0xffffffff CH0_LOW Channel 0 lower trigger level 0 7 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 CH1_LOW Channel 1 lower trigger level 8 15 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 CH2_LOW Channel 2 lower trigger level 16 23 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 CH3_LOW Channel 3 lower trigger level 24 31 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 TH0_3_UPPER Upper comparator trigger level channel 0-3 register 0xC8 32 read-write 0xab8dc5c0 0xffffffff CH0_UP Channel 0 upper trigger level 0 7 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 CH1_UP Channel 1 upper trigger level 8 15 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 CH2_UP Channel 2 upper trigger level 16 23 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 CH3_UP Channel 3 upper trigger level 24 31 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 TH4_7_LOWER Lower comparator trigger level channel 4-7 0x44 32 read-write 0x0 0xffffffff CH4_LOW Channel 4 lower trigger level 0 7 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 CH5_LOW Channel 5 lower trigger level 8 15 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 CH6_LOW Channel 6 lower trigger level 16 23 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 CH7_LOW Channel 7 lower trigger level 24 31 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 TH4_7_UPPER Upper comparator trigger level channel 4-7 register 0xCC 32 read-write 0x0 0xffffffff CH4_UP Channel 4 upper trigger level 0 7 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 CH5_UP Channel 5 upper trigger level 8 15 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 CH6_UP Channel 6 upper trigger level 16 23 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 CH7_UP Channel 7 upper trigger level 24 31 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 TH8_11_LOWER Lower comparator trigger level channel 8-11 0xC0 32 read-write 0x0 0xffffffff CH8_LOW Channel 8 lower trigger level 0 7 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 CH9_LOW Channel 9 lower trigger level 8 15 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 CH10_LOW Channel 10 lower trigger level 16 23 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 CH11_LOW Channel 11 lower trigger level 24 31 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 TH8_11_UPPER Upper comparator trigger level channel 8-11 register 0xD0 32 read-write 0x0 0xffffffff CH8_UP Channel 8 upper trigger level 0 7 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 CH9_UP Channel 9 upper trigger level 8 15 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 CH10_UP Channel 10 upper trigger level 16 23 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 CH11_UP Channel 11 upper trigger level 24 31 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 ADC2 100 Measurement core module (incl. ADC2) registers ADC2 0x4801C000 0 0x2000 registers CAL_CH0_1 Calibration for channel 0 and 1 register 0x34 32 read-write 0x0 0xffffffff OFFS_CH0 Offset calibration for channel 0 0 4 read-write GAIN_CH0 Gain calibration for channel 0 8 15 read-only OFFS_CH1 Offset calibration for channel 1 16 20 read-only GAIN_CH1 Gain calibration for channel 1 24 31 read-write CAL_CH2_3 Calibration for channel 2 and 3 register 0x38 32 read-write 0x0 0xffffffff OFFS_CH2 Offset calibration for channel 2 0 4 read-write GAIN_CH2 Gain calibration for channel 2 8 15 read-write OFFS_CH3 Offset calibration for channel 3 16 20 read-write GAIN_CH3 Gain calibration for channel 3 24 31 read-write CAL_CH4_5 Calibration for channel 4 and 5 register 0x3C 32 read-write 0x0 0xffffffff OFFS_CH4 Offset calibration for channel 4 0 4 read-write GAIN_CH4 Gain calibration for channel 4 8 15 read-write OFFS_CH5 Offset calibration for channel 5 16 20 read-write GAIN_CH5 Gain calibration for channel 5 24 31 read-write CAL_CH6_7 Calibration for channel 6 and 7 register 0x40 32 read-write 0x0 0xffffffff OFFS_CH6 Offset calibration for channel 6 0 4 read-write GAIN_CH6 Gain calibration for channel 6 8 15 read-write CHx_EIM Channel settings bits for exceptional interrupt measurement register 0x8 32 read-write 0x0 0xffffffff CHx_SEL Channel set for exceptional interrupt measurement (EIM) 0 2 read-write CH0_EN Channel 0 enable 0 CH1_EN Channel 1 enable 1 CH2_EN Channel 2 enable 2 CH3_EN Channel 3 enable 3 CH4_EN Channel 4 enable 4 CH5_EN Channel 5 enable 5 CH6_EN Channel 6 enable 6 REP Repeat count for exceptional interrupt measurement (EIM) 8 10 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 64 64 measurements 6 128 128 measurements 7 EN Exceptional interrupt measurement (EIM) trigger event enable 11 11 read-write DISABLE Start of EIM disabled 0 ENABLE Start of EIM enabled 1 SEL Exceptional interrupt measurement (EIM) trigger select 12 12 read-write TRIGGERS GPT12PISEL.T3_GPT12_SEL, GPT12_PISEL triggers EIM 0 NOT_SUPPORTED Not supported 1 CNT0_3_LOWER Lower counter trigger level channel 0-3 register 0x98 32 read-write 0x9090909 0xffffffff CNT_LO_CH0 Lower timer trigger threshold channel 0 0 2 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH0 Channel 0 lower hysteresis 3 4 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_LO_CH1 Lower timer trigger threshold channel 1 8 10 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH1 Channel 1 lower hysteresis 11 12 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_LO_CH2 Lower timer trigger threshold channel 2 16 18 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH2 Channel 2 lower hysteresis 19 20 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_LO_CH3 Lower timer trigger threshold channel 3 24 26 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH3 Channel 3 lower hysteresis 27 28 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT0_3_UPPER Upper counter trigger level channel 0-3 register 0xA4 32 read-write 0x9090909 0xffffffff CNT_UP_CH0 Upper timer trigger threshold channel 0 0 2 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH0 Channel 0 upper hysteresis 3 4 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_UP_CH1 Upper timer trigger threshold channel 1 8 10 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH1 Channel 1 upper hysteresis 11 12 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_UP_CH2 Upper timer trigger threshold channel 2 16 18 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH2 Channel 2 upper hysteresis 19 20 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_UP_CH3 Upper timer trigger threshold channel 3 24 26 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH3 Channel 3 upper hysteresis 27 28 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT4_7_LOWER Lower counter trigger level channel 4-7 register 0x9C 32 read-write 0xb0909 0xffffffff CNT_LO_CH4 Lower timer trigger threshold channel 4 0 2 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH4 Channel 4 lower hysteresis 3 4 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_LO_CH5 Lower timer trigger threshold channel 5 8 10 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH5 Channel 5 lower hysteresis 11 12 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_LO_CH6 Lower timer trigger threshold channel 6 16 18 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH6 Channel 6 lower hysteresis 19 20 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_LO_CH7 Lower timer trigger threshold channel 6 24 26 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_LO_CH7 Channel 6 lower hysteresis 27 28 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT4_7_UPPER Upper counter trigger level channel 4-7 register 0xA8 32 read-write 0xb0909 0xffffffff CNT_UP_CH4 Upper timer trigger threshold channel 4 0 2 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH4 Channel 4 upper hysteresis 3 4 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_UP_CH5 Upper timer trigger threshold channel 5 8 10 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH5 Channel 5 upper hysteresis 11 12 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_UP_CH6 Upper timer trigger threshold channel 6 16 18 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH6 Channel 6 upper hysteresis 19 20 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CNT_UP_CH7 Upper timer trigger threshold channel 7 24 26 read-write 1 1 measurement 0 2 2 measurements 1 4 4 measurements 2 8 8 measurements 3 16 16 measurements 4 32 32 measurements 5 63 63 measurements 6 63 63 measurements 7 HYST_UP_CH7 Channel 7 upper hysteresis 27 28 read-write HYSTOFF Hysteresis switched off 0 HYST4 Hysteresis = 4 1 HYST8 Hysteresis = 8 2 HYST16 Hysteresis = 16 3 CTRL_STS ADC2 control and status register 0x0 32 read-write 0x1 0xffffffff SOS ADC2 start of sampling/conversion (software mode) 2 2 read-write DISABLE No conversion is started 0 ENABLE Conversion is started 1 EOC ADC2 end of conversion (software mode) 3 3 read-only PENDING Conversion still running 0 FINISHED Conversion has finished 1 IN_MUX_SEL Channel for software mode 8 11 read-write CH0_EN Channel 0 enable 0 CH1_EN Channel 1 enable 1 CH2_EN Channel 2 enable 2 CH3_EN Channel 3 enable 3 CH4_EN Channel 4 enable 4 CH5_EN Channel 5 enable 5 CH6_EN Channel 6 enable 6 CTRL1 Measurement unit control 1 register 0x14 32 read-write 0x0 0xffffffff CALIB_EN_6_0 Calibration enable for channels 6 to 0 0 6 read-write CH0_EN Channel 0 calibration enable 1 CH1_EN Channel 1 calibration enable 2 CH2_EN Channel 2 calibration enable 4 CH3_EN Channel 3 calibration enable 8 CH4_EN Channel 4 calibration enable 16 CH5_EN Channel 5 calibration enable 32 CH6_EN Channel 6 calibration enable 64 CTRL2 Measurement unit control 2 register 0x18 32 read-write 0x401 0xffffffff MCM_PD_N Power down signal for MCM 0 0 read-write DISABLED Measurement core module disabled 0 ENABLED Measurement core module enabled 1 MCM_RDY Ready signal for MCM 7 7 read-only NOT_READY Measurement core module in start-up phase 0 READY Measurement core module start-up phase finished 1 SAMPLE_TIME_int Sample time of ADC2 8 11 read-write MICLK4 4 MI_CLK clock periods 0 MICLK6 6 MI_CLK clock periods 1 MICLK8 8 MI_CLK clock periods 2 MICLK10 10 MI_CLK clock periods 3 MICLK12 12 MI_CLK clock periods (default) 4 MICLK14 14 MI_CLK clock periods 5 MICLK16 16 MI_CLK clock periods 6 MICLK18 18 MI_CLK clock periods 7 MICLK20 20 MI_CLK clock periods 8 MICLK22 22 MI_CLK clock periods 9 CTRL4 Measurement unit control 4 register 0x1C 32 read-write 0x7f 0xffffffff FILT_OUT_SEL_6_0 Output filter selection for channels 0 to 6 0 6 read-write UNFILTERED ADC2 unfiltered data can be monitored in the corresponding ADC2_FILT_OUTx registers 0 CH_0 Channel 0 IIR data enabled for ADC2_FILT_OUT0 register 1 CH_1 Channel 1 IIR data enabled for ADC2_FILT_OUT1 register 2 CH_2 Channel 2 IIR data enabled for ADC2_FILT_OUT2 register 4 CH_3 Channel 3 IIR data enabled for ADC2_FILT_OUT3 register 8 CH_4 Channel 4 IIR data enabled for ADC2_FILT_OUT4 register 16 CH_5 Channel 5 IIR data enabled for ADC2_FILT_OUT5 register 32 CH_6 Channel 6 IIR data enabled for ADC2_FILT_OUT6 register 64 ALL For channels 6-0 IIR data is enabled for ADC2_FILT_OUTx registers 127 FILT_LO_CTRL Lower threshold filter enable register 0x7C 32 read-write 0x7f 0xffffffff LOEN_Ch0 Lower threshold IIR filter enable ch 0 0 0 read-write DISABLE Disable 0 ENABLE Enable 1 LOEN_Ch1 Lower threshold IIR filter enable ch 1 1 1 read-write DISABLE Disable 0 ENABLE Enable 1 LOEN_Ch2 Lower threshold IIR filter enable ch 2 2 2 read-write DISABLE Disable 0 ENABLE Enable 1 LOEN_Ch3 Lower threshold IIR filter enable ch 3 3 3 read-write DISABLE Disable 0 ENABLE Enable 1 LOEN_Ch4 Lower threshold IIR filter enable ch 4 4 4 read-write DISABLE Disable 0 ENABLE Enable 1 LOEN_Ch5 Lower threshold IIR filter enable ch 5 5 5 read-write DISABLE Disable 0 ENABLE Enable 1 LOEN_Ch6 Lower threshold IIR filter enable ch 6 6 6 read-write DISABLE Disable 0 ENABLE Enable 1 FILT_OUT0 ADC or filter output channel 0 register 0x50 32 read-only 0x0 0xfffff000 OUT_CH0 ADC or filter output value channel 0 0 9 read-only FILT_OUT1 ADC or filter output channel 1 register 0x54 32 read-only 0x0 0xfffff000 OUT_CH1 ADC or filter output value channel 1 0 9 read-only FILT_OUT2 ADC or filter output channel 2 register 0x58 32 read-only 0x0 0xfffff000 OUT_CH2 ADC or filter output value channel 2 0 9 read-only FILT_OUT3 ADC or filter output channel 3 register 0x5C 32 read-only 0x0 0xfffff000 OUT_CH3 ADC or filter output value channel 3 0 9 read-only FILT_OUT4 ADC or filter output channel 4 register 0x60 32 read-only 0x0 0xfffff000 OUT_CH4 ADC or filter output value channel 4 0 9 read-only FILT_OUT5 ADC or filter output channel 5 register 0x64 32 read-only 0x0 0xfffff000 OUT_CH5 ADC or filter output value channel 5 0 9 read-only FILT_OUT6 ADC or filter output channel 6 register 0x68 32 read-only 0x0 0xfffff000 OUT_CH6 ADC or filter output value channel 6 0 9 read-only FILT_UP_CTRL Upper threshold filter enable register 0x78 32 read-write 0x7f 0xffffffff UPEN_Ch0 Upper threshold IIR filter enable ch 0 0 0 read-write DISABLE Disable 0 ENABLE Enable 1 UPEN_Ch1 Upper threshold IIR filter enable ch 1 1 1 read-write DISABLE Disable 0 ENABLE Enable 1 UPEN_Ch2 Upper threshold IIR filter enable ch 2 2 2 read-write DISABLE Disable 0 ENABLE Enable 1 UPEN_Ch3 Upper threshold IIR filter enable ch 3 3 3 read-write DISABLE Disable 0 ENABLE Enable 1 UPEN_Ch4 Upper threshold IIR filter enable ch 4 4 4 read-write DISABLE Disable 0 ENABLE Enable 1 UPEN_Ch5 Upper threshold IIR filter enable ch 5 5 5 read-write DISABLE Disable 0 ENABLE Enable 1 UPEN_Ch6 Upper threshold IIR filter enable ch 6 6 6 read-write DISABLE Disable 0 ENABLE Enable 1 FILTCOEFF0_7 Filter coefficients ADC channel 0-7 register 0x48 32 read-write 0x1555 0xffffffff A_CH0 Filter coefficient A for ADC channel 0 0 1 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 A_CH1 Filter coefficient A for ADC channel 1 2 3 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 A_CH2 Filter coefficient A for ADC channel 2 4 5 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 A_CH3 Filter coefficient A for ADC channel 3 6 7 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 A_CH4 Filter coefficient A for ADC channel 4 8 9 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 A_CH5 Filter coefficient A for ADC channel 5 10 11 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 A_CH6 Filter coefficient A for ADC channel 6 12 13 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 A_CH7 Filter coefficient A for ADC channel 7 14 15 read-write 1_2 1/2 weight of current sample 0 1_4 1/4 weight of current sample 1 1_8 1/8 weight of current sample 2 1_16 1/16 weight of current sample 3 MAX_TIME Maximum time for software mode register 0x10 32 read-write 0x0 0xffffffff MAX_TIME Maximum time in software mode 0 7 read-write MIN Software mode is immediately left 0 MAX Software mode is active for 12.75 us 255 MMODE0_7 Overvoltage measurement mode of channel 0-7 register 0xB0 32 read-write 0x2800 0xffffffff MSEL_Ch0 Measurement mode ch 0 0 1 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MSEL_Ch1 Measurement mode ch 1 2 3 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MSEL_Ch2 Measurement mode ch 2 4 5 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MSEL_Ch3 Measurement mode ch 3 6 7 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MSEL_Ch4 Measurement mode ch 4 8 9 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MSEL_Ch5 Measurement mode ch 5 10 11 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MSEL_Ch6 Measurement mode ch 6 12 13 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 MSEL_Ch7 Measurement mode ch 7 14 15 read-write MMODE0 Upper & lower voltage/limit measurement 0 MMODEUV Undervoltage/-limit measurement 1 MMODEOV Overvoltage/-limit measurement 2 SQ_FB Sequencer feedback register 0x4 32 read-only 0x0 0xff0000f0 SQ_FB Current sequence that caused software mode 0 3 read-only SQ1 Sequence 1 0 SQ2 Sequence 2 1 SQ3 Sequence 3 2 SQ4 Sequence 4 3 SQ5 Sequence 5 4 SQ6 Sequence 6 5 SQ7 Sequence 7 6 CH_MASK Channel mask = 0 11 SUSPEND Debug suspend mode 12 SQ_STOP ADC2 sequencer stop signal for DPP 8 8 read-only DPP_RUNNING Post processing sequencer in running mode 0 DPP_STOPPED Post processing sequencer stopped/software mode entered 1 EIM_ACTIVE ADC2 EIM active 9 9 read-only NOT_ACTIVE EIM not active 0 ACTIVE EIM active 1 SQx_STS Current active ADC2 sequence 11 13 read-only SQ1 Sequence 1 enable 0 SQ2 Sequence 2 enable 1 SQ3 Sequence 3 enable 2 SQ4 Sequence 4 enable 3 SQ5 Sequence 5 enable 4 SQ6 Sequence 6 enable 5 SQ7 Sequence 7 enable 6 CHx_STS Current ADC2 channel 16 19 read-only CH0 Channel 0 enable 0 CH1 Channel 1 enable 1 CH2 Channel 2 enable 2 CH3 Channel 3 enable 3 CH4 Channel 4 enable 4 CH5 Channel 5 enable 5 CH6 Channel 6 enable 6 SQ1_4 Measurement channel enable bits for cycle 1-4 register 0x20 32 read-write 0x49364837 0xffffffff SQ1 Sequence 1 channel enable 0 6 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 SQ2 Sequence 2 channel enable 8 14 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 SQ3 Sequence 3 channel enable 16 22 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 SQ4 Sequence 4 channel enable 24 30 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 SQ5_8 Measurement channel enable bits for cycle 5-8 register 0x24 32 read-write 0x374836 0xffffffff SQ5 Sequence 5 channel enable 0 6 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 SQ6 Sequence 6 channel enable 8 14 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 SQ7 Sequence 7 channel enable 16 22 read-write CH0_EN Channel 0 enable 1 CH1_EN Channel 1 enable 2 CH2_EN Channel 2 enable 4 CH3_EN Channel 3 enable 8 CH4_EN Channel 4 enable 16 CH5_EN Channel 5 enable 32 CH6_EN Channel 6 enable 64 STATUS ADC2 HV status register 0xBC 32 read-only 0x0 0xffffffff READY HVADC ready bit 1 1 read-only NOT_READY Module in power down or in init phase 0 READY Set automatically 5 ADC clock cycles after module is enabled 1 TH0_3_LOWER Lower comparator trigger level channel 0-3 register 0x80 32 read-write 0x9d6fbf25 0xffffffff THLO_CH0 Channel 0 lower trigger level 0 7 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 THLO_CH1 Channel 1 lower trigger level 8 15 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 THLO_CH2 Channel 2 lower trigger level 16 23 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 THLO_CH3 Channel 3 lower trigger level 24 31 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 TH0_3_UPPER Upper comparator trigger level channel 0-3 register 0x8C 32 read-write 0xebe9e9e4 0xffffffff THUP_CH0 Channel 0 upper trigger level 0 7 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 THUP_CH1 Channel 1 upper trigger level 8 15 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 THUP_CH2 Channel 2 upper trigger level 16 23 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 THUP_CH3 Channel 3 upper trigger level 24 31 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 TH4_7_LOWER Lower comparator trigger level channel 4-7 register 0x84 32 read-write 0xc8d4d4 0xffffffff THLO_CH4 Channel 4 lower trigger level 0 7 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 THLO_CH5 Channel 5 lower trigger level 8 15 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 THLO_CH6 Channel 6 lower trigger level 16 23 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 THLO_CH7 Channel 7 lower trigger level 24 31 read-write MIN Min. threshold value 0 MAX Max. threshold value 255 TH4_7_UPPER Upper comparator trigger level channel 4-7 register 0x90 32 read-write 0xe2e2fb 0xffffffff THUP_CH4 Channel 4 upper trigger level 0 7 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 THUP_CH5 Channel 5 upper trigger level 8 15 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 THUP_CH6 Channel 6 upper trigger level 16 23 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 THUP_CH7 Channel 7 upper trigger level 24 31 read-write MIN Min. threshold value = 0 0 MAX Max. threshold value = 255 255 CCU6 100 Capture/Compare Unit 6 (CCU6) registers CCU6 0x4000C000 0 0x4000 registers CC60R Capture/compare register for channel CC60 register 0x34 16 read-only 0x0 0xffff CCV Channel 0 capture/compare value 0 15 read-only CC60SR Capture/compare shadow register for channel CC60 register 0x14 16 read-write 0x0 0xffff CCS Shadow register for channel 0 capture/compare value 0 15 read-write CC61R Capture/compare register for channel CC61 register 0x38 16 read-only 0x0 0xffff CCV Channel 1 capture/compare value 0 15 read-only CC61SR Capture/compare shadow register for channel CC61 register 0x18 16 read-write 0x0 0xffff CCS Shadow register for channel 1 capture/compare value 0 15 read-write CC62R Capture/compare register for channel CC62 register 0x3C 16 read-only 0x0 0xffff CCV Channel 2 capture/compare value 0 15 read-only CC62SR Capture/compare shadow register for channel CC62 register 0x1C 16 read-write 0x0 0xffff CCS Shadow register for channel 2 capture/compare value 0 15 read-write CC63R Capture/compare for channel CC63 register 0x0 16 read-only 0x0 0xffff CCV Channel CC63 compare value low byte 0 15 read-only CC63SR Capture/compare shadow for channel CC63 register 0x20 16 read-write 0x0 0xffff CCS Shadow register for channel CC63 compare value 0 15 read-write CMPMODIF Compare state modification register 0x10 16 read-write 0x0 0xffff MCC60S Capture/compare status modification bit 0 (set) 0 0 write-only MCC61S Capture/compare status modification bit 1 (set) 1 1 write-only MCC62S Capture/compare status modification bit 2 (set) 2 2 write-only MCC63S Capture/compare status modification bits (set) 6 6 write-only MCC60R Capture/compare status modification bit 0 (reset) 8 8 write-only MCC61R Capture/compare status modification bit 1 (reset) 9 9 write-only MCC62R Capture/compare status modification bit 2 (reset) 10 10 write-only MCC63R Capture/compare status modification bits (reset) 14 14 write-only CMPSTAT Compare state register 0x80 16 read-write 0x0 0xffff CC60ST Capture/compare state bits 0 0 read-only Less In compare mode, the timer count is less than the compare value. In capture mode, the selected edge has not yet been detected since the bit has been reset by software the last time 0 Greater In compare mode, the counter value is greater than or equal to the compare value. In capture mode, the selected edge has been detected 1 CC61ST Capture/compare state bits 1 1 read-only Less In compare mode, the timer count is less than the compare value. In capture mode, the selected edge has not yet been detected since the bit has been reset by software the last time 0 Greater In compare mode, the counter value is greater than or equal to the compare value; In capture mode, the selected edge has been detected 1 CC62ST Capture/compare state bits 2 2 read-only Less In compare mode, the timer count is less than the compare value. In capture mode, the selected edge has not yet been detected since the bit has been reset by software the last time 0 Greater In compare mode, the counter value is greater than or equal to the compare value. In capture mode, the selected edge has been detected 1 CCPOS0 Sampled Hall pattern bit 0 3 3 read-only Zero The input CCPOS0 has been sampled as 0 0 One The input CCPOS0 has been sampled as 1 1 CCPOS1 Sampled Hall pattern bit 1 4 4 read-only Zero The input CCPOS1 has been sampled as 0 0 One The input CCPOS1 has been sampled as 1 1 CCPOS2 Sampled Hall pattern bit 2 5 5 read-only Zero The input CCPOS2 has been sampled as 0 0 One The input CCPOS2 has been sampled as 1 1 CC63ST Capture/compare state bits 6 6 read-only Less In compare mode, the timer count is less than the compare value. In capture mode, the selected edge has not yet been detected since the bit has been reset by software the last time 0 Greater In compare mode, the counter value is greater than or equal to the compare value. In capture mode, the selected edge has been detected 1 CC60PS Passive state select for compare outputs 8 8 read-write Zero The corresponding compare output drives passive level while CC6xST is 0 0 One The corresponding compare output drives passive level while CC6xST is 1 1 COUT60PS Passive state select for compare outputs 9 9 read-write Zero The corresponding compare output drives passive level while CC6xST is 0 0 One The corresponding compare output drives passive level while CC6xST is 1 1 CC61PS Passive state select for compare outputs 10 10 read-write Zero The corresponding compare output drives passive level while CC6xST is 0 0 One The corresponding compare output drives passive level while CC6xST is 1 1 COUT61PS Passive state select for compare outputs 11 11 read-write Zero The corresponding compare output drives passive level while CC6xST is 0 0 One The corresponding compare output drives passive level while CC6xST is 1 1 CC62PS Passive state select for compare outputs 12 12 read-write Zero The corresponding compare output drives passive level while CC6xST is 0 0 One The corresponding compare output drives passive level while CC6xST is 1 1 COUT62PS Passive state select for compare outputs 13 13 read-write Zero The corresponding compare output drives passive level while CC6xST is 0 0 One The corresponding compare output drives passive level while CC6xST is 1 1 COUT63PS Passive state select for compare outputs 14 14 read-write Zero The corresponding compare output drives passive level while CC6xST is 0 0 One The corresponding compare output drives passive level while CC6xST is 1 1 T13IM T13 inverted modulation 15 15 read-write Not_inverted T13 output is not inverted 0 Inverted T13 output is inverted for further modulation 1 IEN Capture/compare interrupt enable register 0x44 16 read-write 0x0 0xffff ENCC60R Capture, compare-match rising edge interrupt enable for channel 0 0 0 read-write No_interrupt No interrupt will be generated if the set condition for bit CC60R in register IS occurs 0 Interrupt An interrupt will be generated if the set condition for bit CC60R in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC60 1 ENCC60F Capture, compare-match falling edge interrupt enable for channel 0 1 1 read-write No_interrupt No interrupt will be generated if the set condition for bit CC60F in register IS occurs 0 Interrupt An interrupt will be generated if the set condition for bit CC60F in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC60 1 ENCC61R Capture, compare-match rising edge interrupt enable for channel 1 2 2 read-write No_interrupt No interrupt will be generated if the set condition for bit CC61R in register IS occurs 0 Interrupt An interrupt will be generated if the set condition for bit CC61R in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC61 1 ENCC61F Capture, compare-match falling edge interrupt enable for channel 1 3 3 read-write No_interrupt No interrupt will be generated if the set condition for bit CC61F in register IS occurs 0 Interrupt An interrupt will be generated if the set condition for bit CC61F in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC61 1 ENCC62R Capture, compare-match rising edge interrupt enable for channel 2 4 4 read-write No_interrupt No interrupt will be generated if the set condition for bit CC62R in register IS occurs 0 Interrupt An interrupt will be generated if the set condition for bit CC62R in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC62 1 ENCC62F Capture, compare-match falling edge interrupt enable for channel 2 5 5 read-write No_interrupt No interrupt will be generated if the set condition for bit CC62F in register IS occurs 0 Interrupt An interrupt will be generated if the set condition for bit CC62F in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC62 1 ENT12OM Enable interrupt for T12 one-match 6 6 read-write No_interrupt No interrupt will be generated if the set condition for bit T12OM in register IS occurs 0 Interrupt An interrupt will be generated if the set condition for bit T12OM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT12 1 ENT12PM Enable interrupt for T12 period-match 7 7 read-write No_interrupt No interrupt will be generated if the set condition for bit T12PM in register IS occurs 0 Interrupt An interrupt will be generated if the set condition for bit T12PM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT12 1 ENT13CM Enable interrupt for T13 compare-match 8 8 read-write No_interrupt No interrupt will be generated if the set condition for bit T13CM in register IS occurs 0 Interrupt An interrupt will be generated if the set condition for bit T13CM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT13 1 ENT13PM Enable interrupt for T13 period-match 9 9 read-write No_interrupt No interrupt will be generated if the set condition for bit T13PM in register IS occurs 0 Interrupt An interrupt will be generated if the set condition for bit T13PM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT13 1 ENTRPF Enable interrupt for trap flag 10 10 read-write No_interrupt No interrupt will be generated if the set condition for bit TRPF in register IS occurs 0 Interrupt An interrupt will be generated if the set condition for bit TRPF in register IS occurs. The interrupt line that will be activated is selected by bit field INPERR 1 ENCHE Enable interrupt for correct Hall Event 12 12 read-write No_interrupt No interrupt will be generated if the set condition for bit CHE in register IS occurs 0 Interrupt An interrupt will be generated if the set condition for bit CHE in register IS occurs. The interrupt line that will be activated is selected by bit field INPCHE 1 ENWHE Enable interrupt for wrong Hall Event 13 13 read-write No_interrupt No interrupt will be generated if the set condition for bit WHE in register IS occurs 0 Interrupt An interrupt will be generated if the set condition for bit WHE in register IS occurs. The interrupt line that will be activated is selected by bit field INPERR 1 ENIDLE Enable idle 14 14 read-write IDLE_not_set The bit IDLE is not automatically set when a wrong hall event is detected 0 IDLE_set The bit IDLE is automatically set when a wrong hall event is detected 1 ENSTR Enable multi-channel mode shadow transfer interrupt 15 15 read-write No_interrupt No interrupt will be generated if the set condition for bit STR in register IS occurs 0 Interrupt An interrupt will be generated if the set condition for bit STR in register IS occurs. The interrupt line that will be activated is selected by bit field INPCHE 1 INP Capture/compare interrupt node pointer register 0x48 16 read-write 0x3940 0xffff INPCC60 Interrupt node pointer for channel 0 interrupts 0 1 read-write SR0 Interrupt output line SR0 is selected 0 SR1 Interrupt output line SR1 is selected 1 SR2 Interrupt output line SR2 is selected 2 SR3 Interrupt output line SR3 is selected 3 INPCC61 Interrupt node pointer for channel 1 interrupts 2 3 read-write SR0 Interrupt output line SR0 is selected 0 SR1 Interrupt output line SR1 is selected 1 SR2 Interrupt output line SR2 is selected 2 SR3 Interrupt output line SR3 is selected 3 INPCC62 Interrupt node pointer for channel 2 interrupts 4 5 read-write SR0 Interrupt output line SR0 is selected 0 SR1 Interrupt output line SR1 is selected 1 SR2 Interrupt output line SR2 is selected 2 SR3 Interrupt output line SR3 is selected 3 INPCHE Interrupt node pointer for the CHE interrupt 6 7 read-write SR0 Interrupt output line SR0 is selected 0 SR1 Interrupt output line SR1 is selected 1 SR2 Interrupt output line SR2 is selected 2 SR3 Interrupt output line SR3 is selected 3 INPERR Interrupt node pointer for error interrupts 8 9 read-write SR0 Interrupt output line SR0 is selected 0 SR1 Interrupt output line SR1 is selected 1 SR2 Interrupt output line SR2 is selected 2 SR3 Interrupt output line SR3 is selected 3 INPT12 Interrupt node pointer for timer T12 interrupts 10 11 read-write SR0 Interrupt output line SR0 is selected 0 SR1 Interrupt output line SR1 is selected 1 SR2 Interrupt output line SR2 is selected 2 SR3 Interrupt output line SR3 is selected 3 INPT13 Interrupt node pointer for timer T13 interrupts 12 13 read-write SR0 Interrupt output line SR0 is selected 0 SR1 Interrupt output line SR1 is selected 1 SR2 Interrupt output line SR2 is selected 2 SR3 Interrupt output line SR3 is selected 3 IS Capture/compare interrupt status register 0x68 16 read-only 0x0 0xffff ICC60R Capture, compare-match rising edge flag 0 0 read-only Not_occurred The event has not yet occurred since this bit has been reset for the last time 0 Detected The event described above has been detected 1 ICC60F Capture, compare-match falling edge flag 1 1 read-only Not_occurred The event has not yet occurred since this bit has been reset for the last time 0 Detected The event described above has been detected 1 ICC61R Capture, compare-match rising edge flag 2 2 read-only Not_occurred The event has not yet occurred since this bit has been reset for the last time 0 Detected The event described above has been detected 1 ICC61F Capture, compare-match falling edge flag 3 3 read-only Not_occurred The event has not yet occurred since this bit has been reset for the last time 0 Detected The event described above has been detected 1 ICC62R Capture, compare-match rising edge flag 4 4 read-only Not_occurred The event has not yet occurred since this bit has been reset for the last time 0 Detected The event described above has been detected 1 ICC62F Capture, compare-match falling edge flag 5 5 read-only Not_occurred The event has not yet occurred since this bit has been reset for the last time 0 Detected The event described above has been detected 1 T12OM Timer T12 one-match flag 6 6 read-only Not_detected A timer T12 one-match (while counting down) has not yet been detected since this bit has been reset for the last time 0 Detected A timer T12 one-match (while counting down) has been detected 1 T12PM Timer T12 period-match flag 7 7 read-only Not_detected A timer T12 period-match (while counting up) has not yet been detected since this bit has been reset for the last time 0 Detected A timer T12 period-match (while counting up) has been detected 1 T13CM Timer T13 compare-match flag 8 8 read-only Not_detected A timer T13 compare-match has not yet been detected since this bit has been reset for the last time 0 Detected A timer T13 compare-match has been detected 1 T13PM Timer T13 period-match flag 9 9 read-only Not_detected A timer T13 period-match has not yet been detected since this bit has been reset for the last time 0 Detected A timer T13 period-match has been detected 1 TRPF Trap flag 10 10 read-only Not_detected The trap condition has not been detected 0 Detected The trap condition has been detected (input CTRAP has been 0 or by software) 1 TRPS Trap state 11 11 read-only Not_active The trap state is not active 0 Active The trap state is active. Bit TRPS is set while bit TRPF = 1. It is reset according to the mode selected in register TRPCTR 1 CHE Correct Hall event 12 12 read-only Not_detected A transition to a correct (= expected) Hall event has not yet been detected since this bit has been reset for the last time 0 Detected A transition to a correct (= expected) Hall event has been detected 1 WHE Wrong Hall event 13 13 read-only Not_detected A transition to a wrong Hall event (not the expected one) has not yet been detected since this bit has been reset for the last time 0 Detected A transition to a wrong Hall event (not the expected one) has been detected 1 IDLE IDLE state 14 14 read-only No_action No action 0 Idle Bit field MCMP is cleared and held to 0, the selected outputs are set to passive state 1 STR Multi-channel mode shadow transfer request 15 15 read-only No The shadow transfer has not yet taken place 0 Yes The shadow transfer has taken place 1 ISR Capture/compare interrupt status reset register 0xC 16 read-write 0x0 0xffff RCC60R Reset capture, compare-match rising edge flag 0 0 write-only No_action No action 0 Reset Bit CC60R in register IS will be reset 1 RCC60F Reset capture, compare-match falling edge flag 1 1 write-only No_action No action 0 Reset Bit CC60F in register IS will be reset 1 RCC61R Reset capture, compare-match rising edge Flag 2 2 write-only No_action No action 0 Reset Bit CC61R in register IS will be reset 1 RCC61F Reset capture, compare-match falling edge flag 3 3 write-only No_action No action 0 Reset Bit CC61F in register IS will be reset 1 RCC62R Reset capture, compare-match rising edge flag 4 4 write-only No_action No action 0 Reset Bit CC62R in register IS will be reset 1 RCC62F Reset capture, compare-match falling edge flag 5 5 write-only No_action No action 0 Reset Bit CC62F in register IS will be reset 1 RT12OM Reset timer T12 one-match flag 6 6 write-only No_action No action 0 Reset Bit T12OM in register IS will be reset 1 RT12PM Reset timer T12 period-match flag 7 7 write-only No_action No action 0 Reset Bit T12PM in register IS will be reset 1 RT13CM Reset timer T13 compare-match flag 8 8 write-only No_action No action 0 Reset Bit T13CM in register IS will be reset 1 RT13PM Reset timer T13 period-Match flag 9 9 write-only No_action No action 0 Reset Bit T13PM in register IS will be reset 1 RTRPF Reset trap flag 10 10 write-only No_action No action 0 Reset Bit TRPF in register IS will be reset (not taken into account while input CTRAP= 0 and TRPPEN = 1) 1 RCHE Reset correct Hall event flag 12 12 write-only No_action No action 0 Reset Bit CHE in register IS will be reset 1 RWHE Reset wrong Hall event flag 13 13 write-only No_action No action 0 Reset Bit WHE in register IS will be reset 1 RIDLE Reset IDLE flag 14 14 write-only No_action No action 0 Reset Bit IDLE in register IS will be reset 1 RSTR Reset STR flag 15 15 write-only No_action No action 0 Reset Bit STR in register IS will be reset 1 ISS Capture/compare interrupt status set register 0x4C 16 write-only 0x0 0xffff SCC60R Set capture, compare-match rising edge flag 0 0 write-only No_action No action 0 Set Bit CC60R in register IS will be set 1 SCC60F Set capture, compare-match falling edge flag 1 1 write-only No_action No action 0 Set Bit CC60F in register IS will be set 1 SCC61R Set capture, compare-match rising edge flag 2 2 write-only No_action No action 0 Set Bit CC61R in register IS will be set 1 SCC61F Set capture, compare-match falling edge flag 3 3 write-only No_action No action 0 Set Bit CC61F in register IS will be set 1 SCC62R Set capture, compare-match rising edge flag 4 4 write-only No_action No action 0 Set Bit CC62R in register IS will be set 1 SCC62F Set capture, compare-match falling edge flag 5 5 write-only No_action No action 0 Set Bit CC62F in register IS will be set 1 ST12OM Set timer T12 one-match flag 6 6 write-only No_action No action 0 Set Bit T12OM in register IS will be set 1 ST12PM Set timer T12 period-match flag 7 7 write-only No_action No action 0 Set Bit T12PM in register IS will be set 1 ST13CM Set timer T13 compare-match flag 8 8 write-only No_action No action 0 Set Bit T13CM in register IS will be set 1 ST13PM Set timer T13 period-match flag 9 9 write-only No_action No action 0 Set Bit T13PM in register IS will be set 1 STRPF Set trap flag 10 10 write-only No_action No action 0 Set Bits TRPF and TRPS in register IS will be set 1 SWHC Software Hall compare 11 11 write-only No_action No action 0 Set The Hall compare action is triggered 1 SCHE Set correct Hall event flag 12 12 write-only No_action No action 0 Set Bit CHE in register IS will be set 1 SWHE Set wrong Hall event flag 13 13 write-only No_action No action 0 Set Bit WHE in register IS will be set 1 SIDLE Set IDLE flag 14 14 write-only No_action No action 0 Set Bit IDLE in register IS will be set 1 SSTR Set STR flag 15 15 write-only No_action No action 0 Set Bit STR in register IS will be set 1 MCMCTR Multi-channel mode control register 0x54 16 read-write 0x0 0xffff SWSEL Switching selection 0 2 read-write No_request No trigger request will be generated 0 Correct_pattern Correct hall pattern on CCPOSx detected 1 T13_period_match T13 period-match detected (while counting up) 2 T12_one_match T12 one-match (while counting down) 3 T12_channel_1_compare_match T12 channel 1 compare-match detected (phase delay function) 4 T12_period_match T12 period match detected (while counting up) else reserved, no trigger request will be generated 5 SWSYN Switching Synchronization 4 5 read-write Direct The trigger event directly causes the shadow transfer 0 T13_zero_match T13 zero-match triggers the shadow transfer 1 T12_zero_match A T12 zero-match (while counting up) triggers the shadow transfer 2 STE12U Shadow transfer enable for T12 upcounting 8 8 read-write No_action No action 0 ENABLED The T12_ST shadow transfer mechanism is enabled if MCMEN = 1 1 STE12D Shadow transfer Enable for T12 downcounting 9 9 read-write No_action No action 0 ENABLED The T12_ST shadow transfer mechanism is enabled if MCMEN = 1 1 STE13U Shadow transfer enable for T13 upcounting 10 10 read-write No_action No action 0 ENABLED The T13_ST shadow transfer mechanism is enabled if MCMEN = 1 1 MCMOUT Multi-channel mode output register 0x64 16 read-only 0x0 0xffff MCMP Multi-channel PWM pattern 0 5 read-only Passive The output is set to the passive state. The PWM generated by T12 or T13 is not taken into account 0 PWM The output can deliver the PWM generated by T12 or T13 (according to register MODCTR) 1 R Reminder Flag 6 6 read-only No_shadow_transfer No shadow transfer, currently, no shadow transfer from MCMPS to MCMP is requested 0 Shadow_transfer A shadow transfer from MCMPS to MCMP has been requested by the selected trigger source, but it has not yet been executed, because the selected synchronization condition has not yet occurred 1 EXPH Expected Hall pattern 8 10 read-only CURH Current Hall pattern 11 13 read-only MCMOUTS Multi-channel mode output shadow register 0x8 16 read-write 0x0 0xffff MCMPS Multi-channel PWM pattern shadow 0 5 read-write STRMCM Shadow transfer request for MCMPS 7 7 write-only By_hardware Bit field MCMP is updated according to the defined hardware action. The write access to bit field MCMPS does not modify bit field MCMP 0 By_software Bit field MCMP is updated by the value written to bit field MCMPS 1 EXPHS Expected Hall pattern shadow 8 10 read-write CURHS Current Hall pattern shadow 11 13 read-write STRHP Shadow transfer request for the Hall pattern 15 15 write-only By_hardware The bit fields CURH and EXPH are updated according to the defined hardware action. The write access to bit fields CURHS and EXPHS does not modify the bit fields CURH and EXPH 0 By_software The bit fields CURH and EXPH are updated by the value written to the bit fields CURHS and EXPHS 1 MODCTR Modulation control register 0x5C 16 read-write 0x0 0xffff T12MODEN T12 modulation enable 0 5 read-write DISABLED The modulation of the corresponding output signal by a T12 PWM pattern is disabled 0 ENABLED The modulation of the corresponding output signal by a T12 PWM pattern is enabled 1 MCMEN Multi-channel mode enable 7 7 read-write DISABLED The modulation of the corresponding output signal by a multi-channel pattern according to bit field MCMOUT is disabled 0 ENABLED The modulation of the corresponding output signal by a multi-channel pattern according to bit field MCMOUT is enabled 1 T13MODEN T13 modulation enable 8 13 read-write DISABLED The modulation of the corresponding output signal by a T13 PWM pattern is disabled 0 ENABLED The modulation of the corresponding output signal by a T13 PWM pattern is enabled 1 ECT13O Enable compare timer T13 output 15 15 read-write DISABLED The alternate output function COUT63 is disabled 0 ENABLED The alternate output function COUT63 is enabled for the PWM signal generated by T13 1 PISEL0 Port input select 0 register 0x6C 16 read-write 0x0 0xffff ISCC60 Input select for CC60 0 1 read-write CC60_0 The input pin for CC60_0 0 CC60_1 The input pin for CC60_1 1 ISCC61 Input select for CC61 2 3 read-write CC61_0 The input pin for CC61_0 0 CC61_1 The input pin for CC61_1 1 ISCC62 Input select for CC62 4 5 read-write CC62_0 The input pin for CC62_0 0 CC62_1 The input pin for CC62_1 1 ISTRP Input select for CTRAP 6 7 read-write CTRAP_0 The input pin for CTRAP_0 0 CTRAP_1 The input pin for CTRAP_1 1 CTRAP_2 The input pin for CTRAP_2 2 CTRAP_3 Signal from differential units 3 ISPOS0 Input select for CCPOS0 8 9 read-write CCPOS0_0 The input pin for CCPOS0_0 0 CCPOS0_1 The input pin for CCPOS0_1 1 CCPOS0_2 The input pin for CCPOS0_2 2 CCPOS0_3 The input pin for CCPOS0_3 3 ISPOS1 Input select for CCPOS1 10 11 read-write CCPOS1_0 The input pin for CCPOS1_0 0 CCPOS1_1 The input pin for CCPOS1_1 1 CCPOS1_2 The input pin for CCPOS1_2 2 CCPOS1_3 The input pin for CCPOS1_3 3 ISPOS2 Input select for CCPOS2 12 13 read-write CCPOS2_0 The input pin for CCPOS2_0 0 CCPOS2_1 The input pin for CCPOS2_1 1 CCPOS2_2 The input pin for CCPOS2_2 2 CCPOS2_3 The input pin for CCPOS2_3 3 IST12HR Input select for T12HR 14 15 read-write T12HRA Either signal T12HRA (if T12EXT = 0) or T12HRE (if T12EXT = 1) is selected 0 T12HRB Either signal T12HRB (if T12EXT = 0) or T12HRF (if T12EXT = 1) is selected 1 T12HRC Either signal T12HRC (if T12EXT = 0) or T12HRG (if T12EXT = 1) is selected 2 T12HRD Either signal T12HRD (if T12EXT = 0) or T12HRH (if T12EXT = 1) is selected 3 PISEL2 Port input select 2 register 0x74 16 read-write 0x0 0xffff IST13HR Input select for T13HR 0 1 read-write T13HRA Either signal T13HRA (if T13EXT = 0) or T13HRE (if T13EXT = 1) is selected 0 T13HRB Either signal T13HRB (if T13EXT = 0) or T13HRF (if T13EXT = 1) is selected 1 T13HRC Either signal T13HRC (if T13EXT = 0) or T13HRG (if T13EXT = 1) is selected 2 T13HRD Either signal T13HRD (if T13EXT = 0) or T13HRH (if T13EXT = 1) is selected 3 ISCNT12 Input select for T12 counting input 2 3 read-write T12_prescaler The T12 prescaler generates the counting events. Bit TCTR4.T12CNT is not taken into account 0 TCTR4_T12CNT Bit TCTR4.T12CNT written with 1 is a counting event. The T12 prescaler is not taken into account 1 Rising_edge The timer T12 is counting each rising edge detected in the selected T12HR signal 2 Falling_edge The timer T12 is counting each falling edge detected in the selected T12HR signal 3 ISCNT13 Input select for T13 counting input 4 5 read-write T13_prescaler The T13 prescaler generates the counting events. Bit TCTR4.T13CNT is not taken into account 0 TCTR4_T13CNT Bit TCTR4.T13CNT written with 1 is a counting event. The T13 prescaler is not taken into account 1 Rising_edge The timer T13 is counting each rising edge detected in the selected T13HR signal 2 Falling_edge The timer T13 is counting each falling edge detected in the selected T13HR signal 3 T12EXT Extension for T12HR inputs 6 6 read-write T12HR_D_A_ T12HR[D:A], one of the signals T12HR[D:A] is selected 0 T12HR_H_E_ T12HR[H:E], one of the signals T12HR[H:E] is selected 1 T13EXT Extension for T13HR inputs 7 7 read-write T13HR_D_A_ T13HR[D:A], one of the signals T13HR[D:A] is selected 0 T13HR_H_E_ T13HR[H:E], one of the signals T13HR[H:E] is selected 1 PSLR Passive state level register 0x50 16 read-write 0x0 0xffff PSL Compare outputs passive state level 0 5 read-write Level_0 The passive level is 0 0 Level_1 The passive level is 1 1 PSL63 Passive state level of output COUT63 7 7 read-write Level_0 The passive level is 0 0 Level_1 The passive level is 1 1 T12 Timer T12 counter register 0x78 16 read-write 0x0 0xffff T12CV Timer T12 counter value 0 15 read-write T12DTC Dead-time control register for timer T12 low register 0x2C 16 read-write 0x0 0xffff DTM Dead-time 0 7 read-write DTE0 Dead-time enable bit 0 8 8 read-write DISABLED Dead-time generation is disabled. The corresponding outputs switch from the passive state to the active state (according to the actual compare status) without any delay 0 ENABLED Dead-time generation is enabled. The corresponding outputs switch from the passive state to the active state (according to the compare status) with the delay programmed in bit field DTM 1 DTE1 Dead-time enable bit 1 9 9 read-write DISABLED Dead-time generation is disabled. The corresponding outputs switch from the passive state to the active state (according to the actual compare status) without any delay 0 ENABLED Dead-time generation is enabled. The corresponding outputs switch from the passive state to the active state (according to the compare status) with the delay programmed in bit field DTM 1 DTE2 Dead-time enable bit 2 10 10 read-write DISABLED Dead-time generation is disabled. The corresponding outputs switch from the passive state to the active state (according to the actual compare status) without any delay 0 ENABLED Dead-time generation is enabled. The corresponding outputs switch from the passive state to the active state (according to the compare status) with the delay programmed in bit field DTM 1 DTR0 Dead-time run indication bit 0 12 12 read-only Zero The value of the corresponding dead-time counter channel is 0 0 Not_zero The value of the corresponding dead-time counter channel is not 0 1 DTR1 Dead-time run indication bit 1 13 13 read-only Zero The value of the corresponding dead-time counter channel is 0 0 Not_zero The value of the corresponding dead-time counter channel is not 0 1 DTR2 Dead-time run indication bit 2 14 14 read-only Zero The value of the corresponding dead-time counter channel is 0 0 Not_zero The value of the corresponding dead-time counter channel is not 0 1 T12MSEL T12 capture/compare mode select register 0x40 16 read-write 0x0 0xffff MSEL60 Capture/compare mode selection 0 3 read-write Compare_outputs_disabled Compare outputs disabled, pins CC6n and COUT6n can be used for I/O. No capture action 0 Pin_CC6n_pin_COUT6n Compare output on pin CC6n, pin COUT6n can be used for I/O. No capture action 1 Pin_COUT6n_pin_CC6n Compare output on pin COUT6n, pin CC6n can be used for I/O. No capture action 2 Pins_COUT6n_and_CC6n Compare output on pins COUT6n and CC6n 3 Double_register_Capture_modes See Table "Register capture modes" 4 Double_register_Capture_modes See Table "Register capture modes" 5 Double_register_Capture_modes See Table "Register capture modes" 6 Double_register_Capture_modes See Table "Register capture modes" 7 Hall_sensor_mode See Table "Register capture modes". In order to enable the hall edge detection, all three MSEL6x must be programmed to Hall sensor mode 8 Hysteresis_like_mode See Table "Combined T12 modes" 9 Multi_input_Capture_modes See Table "Multi-input capture modes" 10 Multi_input_Capture_modes See Table "Multi-input capture modes" 11 Multi_input_Capture_modes See Table "Multi-input capture modes" 12 Multi_input_Capture_modes See Table "Multi-input capture modes" 13 Multi_input_Capture_modes See Table "Multi-input capture modes" 14 Multi_input_Capture_modes See Table "Multi-input capture modes" 15 MSEL61 Capture/compare mode selection 4 7 read-write Compare_outputs_disabled Compare outputs disabled, compare outputs disabled, pins CC6n and COUT6n can be used for I/O. No capture action. 0 Pin_CC6n_pin_COUT6n Compare output on pin CC6n, pin COUT6n can be used for I/O; no capture action 1 Pin_COUT6n_pin_CC6n Pin CC6n, compare output on pin COUT6n, pin CC6n can be used for I/O. No capture action 2 Pins_COUT6n_and_CC6n Compare output on pins COUT6n and CC6n 3 Double_register_Capture_modes See Table "Double-register capture modes" 4 Double_register_Capture_modes See Table "Double-register capture modes" 5 Double_register_Capture_modes See Table "Double-register capture modes" 6 Double_register_Capture_modes See Table "Double-register capture modes" 7 Hall_sensor_mode See Table "Combined T12 modes". In order to enable the hall edge detection, all three MSEL6x must be programmed to Hall sensor mode 8 Hysteresis_like_mode See Table "Combined T12 modes" 9 Multi_input_Capture_modes See Table "Multi-input capture modes" 10 Multi_input_Capture_modes See Table "Multi-input capture modes" 11 Multi_input_Capture_modes See Table "Multi-input capture modes" 12 Multi_input_Capture_modes See Table "Multi-input capture modes" 13 Multi_input_Capture_modes See Table "Multi-input capture modes" 14 Multi_input_Capture_modes See Table "Multi-input capture modes" 15 MSEL62 Capture/compare mode selection 8 11 read-write Compare_outputs_disabled Compare outputs disabled, pins CC6n and COUT6n can be used for I/O. No capture action 0 Pin_CC6n_pin_COUT6n Compare output on pin CC6n, pin COUT6n can be used for I/O. No capture action 1 Pin_COUT6n_pin_CC6n Compare output on pin COUT6n, pin CC6n can be used for I/O. No capture action 2 Pins_COUT6n_and_CC6n Compare output on pins COUT6n and CC6n 3 Double_register_Capture_modes See Table "Double-register capture modes" 4 Double_register_Capture_modes See Table "Double-register capture modes" 5 Double_register_Capture_modes See Table "Double-register capture modes" 6 Double_register_Capture_modes See Table "Double-register capture modes" 7 Hall_sensor_mode See Table "Combined T12 modes". In order to enable the hall edge detection, all three MSEL6x must be programmed to Hall sensor mode 8 Hysteresis_like_mode See Table "Combined T12 modes" 9 Multi_input_Capture_modes See Table "Multi-input capture modes" 10 Multi_input_Capture_modes See Table "Multi-input capture modes" 11 Multi_input_Capture_modes See Table "Multi-input capture modes" 12 Multi_input_Capture_modes See Table "Multi-input capture modes" 13 Multi_input_Capture_modes See Table "Multi-input capture modes" 14 Multi_input_Capture_modes See Table "Multi-input capture modes" 15 HSYNC Hall synchronization 12 14 read-write Any Any edge at one of the inputs CCPOSx (x = 0, 1, 2) triggers the sampling 0 T13_compare_match A T13 compare-match triggers the sampling 1 T13_period_match A T13 period-match triggers the sampling 2 Hall The Hall sampling triggered by hardware sources is switched off 3 T12_period_match A T12 period-match (while counting up) triggers the sampling 4 T12_one_match A T12 one-match (while counting down) triggers the sampling 5 T12_compare_match_UP A T12 compare-match of channel 0 (while counting up) triggers the sampling 6 T12_compare_match_DOWN A T12 compare-match of channel 0 (while counting down) triggers the sampling 7 DBYP Delay bypass 15 15 read-write Not_active The delay bypass is not active. The dead-time counter DTC0 is generating a delay after the source signal becomes active 0 Active The delay bypass is active. The dead-time counter DTC0 is not used by the sampling of the Hall pattern 1 T12PR Timer T12 period register 0x24 16 read-write 0x0 0xffff T12PV T12 period value 0 15 read-write T13 Timer T13 counter register 0x7C 16 read-write 0x0 0xffff T13CV Timer T13 counter value 0 15 read-write T13PR Timer T13 period register 0x28 16 read-write 0x0 0xffff T13PV T13 period value 0 15 read-write TCTR0 Timer control 0 register 0x30 16 read-write 0x0 0xffff T12CLK Timer T12 input clock select 0 2 read-write 1 fT12 = fCCU 0 2 fT12 = fCCU / 2 1 4 fT12 = fCCU / 4 2 8 fT12 = fCCU / 8 3 16 fT12 = fCCU / 16 4 32 fT12 = fCCU / 32 5 64 fT12 = fCCU / 64 6 128 fT12 = fCCU / 128 7 T12PRE Timer T12 prescaler bit 3 3 read-write DISABLED The additional prescaler for T12 is disabled 0 ENABLED The additional prescaler for T12 is enabled 1 T12R Timer T12 run bit 4 4 read-only Stop Timer T12 is stopped 0 Run Timer T12 is running 1 STE12 Timer T12 shadow transfer enable 5 5 read-only DISABLED The shadow register transfer is disabled 0 ENABLED The shadow register transfer is enabled 1 CDIR Count direction of timer T12 6 6 read-only UP T12 counts up 0 DOWN T12 counts down 1 CTM T12 operating mode 7 7 read-write Edge_aligned_mode T12 always counts up and continues counting from zero after reaching the period value 0 Center_aligned_mode T12 counts down after detecting a period-match and counts up after detecting a one-match 1 T13CLK Timer T13 input clock Select 8 10 read-write 1 fT13 = fCCU 0 2 fT13 = fCCU / 2 1 4 fT13 = fCCU / 4 2 8 fT13 = fCCU / 8 3 16 fT13 = fCCU / 16 4 32 fT13 = fCCU/ 32 5 64 fT13 = fCCU / 64 6 128 fT13 = fCCU / 128 7 T13PRE Timer T13 prescaler bit 11 11 read-write DISABLED The additional prescaler for T13 is disabled 0 ENABLED The additional prescaler for T13 is enabled 1 T13R Timer T13 run bit 12 12 read-only Stop Timer T13 is stopped 0 Run Timer T13 is running 1 STE13 Timer T13 shadow transfer enable 13 13 read-only DISABLED The shadow register transfer is disabled 0 ENABLED The shadow register transfer is enabled 1 TCTR2 Timer control 2 register 0x58 16 read-write 0x0 0xffff T12SSC Timer T12 single shot control 0 0 read-write DISABLED The single-shot mode is disabled, no hardware action on T12R 0 ENABLED The single shot mode is enabled, the bit T12R is reset by hardware if: 1 T13SSC Timer T13 single shot control 1 1 read-write No_action No hardware action on T13R 0 ENABLED The single-shot mode is enabled, the bit T13R is reset by hardware if T13 reaches its period value. In parallel to the reset action of bit T13R, the bit CC63ST is reset 1 T13TEC T13 trigger event control 2 4 read-write No_action No action 0 Channel_0 Set T13R on a T12 compare event on channel 0 1 Channel_1 Set T13R on a T12 compare event on channel 1 2 Channel_2 Set T13R on a T12 compare event on channel 2 3 Channel_0_1_2 Set T13R on any T12 compare event on the channels 0, 1, or 2 4 Period_match Set T13R upon a period-match of T12 5 Zero_match Set T13R upon a zero-match of T12 (while counting up) 6 CCPOSx Set T13R on any edge of inputs CCPOSx 7 T13TED Timer T13 trigger event direction 5 6 read-write No_action No action 0 Up While T12 is counting up 1 Down While T12 is counting down 2 Independent Independent on the count direction of T12 3 T12RSEL Timer T12 external run selection 8 9 read-write DISABLED The external setting of T12R is disabled 0 Rising_edge Bit T12R is set if a rising edge of signal T12HR is detected 1 Falling_edge Bit T12R is set if a falling edge of signal T12HR is detected 2 Edge Bit T12R is set if an edge of signal T12HR is detected 3 T13RSEL Timer T13 external run selection 10 11 read-write DISABLED The external setting of T13R is disabled 0 Rising_edge Bit T13R is set if a rising edge of signal T13HR is detected 1 Falling_edge Bit T13R is set if a falling edge of signal T13HR is detected 2 Edge Bit T13R is set if an edge of signal T13HR is detected 3 TCTR4 Timer control 4 register 0x4 16 read-write 0x0 0xffff T12RR Timer T12 run reset 0 0 write-only No_influence T12R is not influenced 0 T12R_cleared T12R is cleared, T12 stops counting 1 T12RS Timer T12 run set 1 1 write-only No_influence T12R is not influenced 0 T12R_set T12R is set, T12 counts 1 T12RES Timer T12 reset 2 2 write-only No_effect No effect on T12 0 Zero The T12 counter register is reset to zero. The switching of the output signals is according to the switching rules; setting of T12RES has no impact on bit T12R 1 DTRES Dead-time counter reset 3 3 write-only No_effect No effect on the dead-time counters 0 Zero The three dead-time counter channels are reset to zero 1 T12CNT Timer T12 count event 5 5 write-only No_action No action 0 Count If enabled (PISEL2), timer T12 counts one step 1 T12STR Timer T12 shadow transfer request 6 6 write-only No_action No action 0 STE12_set STE12 is set, enabling the shadow transfer 1 T12STD Timer T12 shadow transfer disable 7 7 write-only No_action No action 0 STE12_reset STE12 is reset without triggering the shadow transfer 1 T13RR Timer T13 run reset 8 8 write-only No_influence T13R is not influenced 0 T13R_cleared T13R is cleared, T13 stops counting 1 T13RS Timer T13 run set 9 9 write-only No_influence T13R is not influenced 0 T13R_set T13R is set, T13 counts 1 T13RES Timer T13 reset 10 10 write-only No_effect No effect on T13 0 Zero The T13 counter register is reset to zero. The switching of the output signals is according to the switching rules. Setting of T13RES has no impact on bit T13R 1 T13CNT Timer T13 count event 13 13 write-only No_action No action 0 Count If enabled (PISEL2), timer T13 counts one step 1 T13STR Timer T13 shadow transfer request 14 14 write-only No_action No action 0 STE13_set STE13 is set, enabling the shadow transfer 1 T13STD Timer T13 shadow transfer disable 15 15 write-only No_action No action 0 STE13_reset STE13 is reset without triggering the shadow transfer 1 TRPCTR Trap control register 0x60 16 read-write 0x0 0xffff TRPM10 Trap mode control bits 1, 0 0 1 read-write T12_zero_match The trap state is left (return to normal operation according to TRPM2) when a zero-match of T12 (while counting up) is detected (synchronization to T12) 0 T13_zero_match The trap state is left (return to normal operation according to TRPM2) when a zero-match of T13 is detected (synchronization to T13) 1 Immediately The trap state is left (return to normal operation according to TRPM2) immediately without any synchronization to T12 or T13 3 TRPM2 Trap mode control bit 2 2 2 read-write Hardware_reset Hardware_reset 0 Software_reset Software_reset 1 TRPEN Trap enable control 8 13 read-write DISABLED The trap functionality of the corresponding output signal is disabled; the output state is independent from bit TRPS 0 ENABLED The trap functionality of the corresponding output signal is enabled; the output is set to the passive state while TRPS = 1 1 TRPEN13 Trap enable control for timer T13 14 14 read-write DISABLED The trap functionality for T13 is disabled; timer T13 (if selected and enabled) provides PWM functionality even while TRPS = 1 0 ENABLED The trap functionality for T13 is enabled; the timer T13 PWM output signal is set to the passive state while TRPS = 1 1 TRPPEN Trap pin enable 15 15 read-write DISABLED The trap functionality based on the input pin CTRAP is disabled. A trap can only be generated by software by setting bit TRPF 0 ENABLED The trap functionality based on the input pin CTRAP is enabled. A trap can be generated by software by setting bit TRPF or by CTRAP = 0 1 CPU 100 CPU processor registers CPU 0xE000E000 0 0x1000 registers GPT1_Int Interrupt node 0: GPT1 Block 0 GPT2_Int Interrupt node 1: GPT2 Block 1 ADC2_Int Interrupt node 2: ADC2 2 ADC1_Int Interrupt node 3: ADC10 bit 3 CCU6_SR0_Int Interrupt node 4: CCU6 node0 4 CCU6_SR1_Int Interrupt node 5: CCU6 node1 5 CCU6_SR2_Int Interrupt node 6: CCU6 node2 6 CCU6_SR3_Int Interrupt node 7: CCU6 node3 7 SSC1_Int Interrupt node 8: SSC1 8 SSC2_Int Interrupt node 9: SSC2 9 UART1_LIN_Tmr2_Int Interrupt node10: UART1(ASC,LIN), Timer2 10 UART2_Tmr21_EINT2_Int Interrupt node11: UART2, Timer21, EINT2 11 EXINT0_Int Interrupt node12: EINT0 12 EXINT1_Int Interrupt node13: EINT1 13 WAKEUP_Int Interrupt node14: Wake-up 14 LS1_Int Interrupt node17: Low-side 1 17 LS2_Int Interrupt node18: Low-side 2 18 HS1_Int Interrupt node19: High-side 1 19 HS2_Int Interrupt node20: High-side 2 20 DU_Int Interrupt node21: Differential unit - DPP1 (product variant dependent, only TLE9845QX) 21 MON_Int Interrupt node22: MONx 22 PORT2X_Int Interrupt node23: Port 2.x - DPP1 23 AIRCR Application interrupt/reset control register 0xD0C 32 read-write 0xfa050000 0xffffffff VECTCLRACTIVE VECTCLRACTIVE 1 1 write-only SYSRESETREQ System reset request 2 2 write-only NO_EFFECT No effect 0 RESET Request a system level reset 1 ENDIANNESS Data endianness 15 15 read-only LITTLE_ENDIAN Little endian 0 BIG_ENDIAN Big endian 1 VECTKEY Vector key 16 31 read-write CCR Configuration control register 0xD14 32 read-only 0x208 0xffffffff UNALIGN_TRP UNALIGN_TRP 3 3 read-only STKALIGN STKALIGN 9 9 read-only CPUID CPU ID base register 0xD00 32 read-only 0x410cc200 0xffffffff REVISION Revision number 0 3 read-only PARTNO Part number 4 15 read-only CONSTANT Constant 16 19 read-only VARIANT Variant number 20 23 read-only IMPLEMENTER Implementer code 24 31 read-only ICSR Interrupt control and state register 0xD04 32 read-write 0x0 0xffffffff VECTACTIVE VECTACTIVATE 0 5 read-only THREAD Thread mode 0 VECTPENDING VECTPENDING 12 17 read-only NOT_PENDING No pending exceptions 0 ISRPENDING Interrupt pending flag 22 22 read-only NOT_PENDING Interrupt not pending 0 PENDING Interrupt is pending 1 PENDSTCLR SysTick exception clear pending 25 25 write-only NO_EFFECT No effect 0 REMOVE Removes the pending state from the SysTick exception 1 PENDSTSET SysTick exception set pending 26 26 read-write NOT_PENDING On writes, has no effect. On reads, SysTick exception is not pending 0 PENDING On writes, changes SysTick exception state to pending. On reads, SysTick exception is pending 1 PENDSVCLR PendSV clear pending 27 27 write-only NO_EFFECT No effect 0 CLEAR Remove pending state from the PENDSV exception 1 PENDSVSET PendSV set pending 28 28 read-write NOT_PENDING On writes, has no effect. On reads, PendSV exception is not pending 0 PENDING On writes, changes PendSV exception state to pending. On reads, PendSV is pending 1 NMIPENDSET NMI set pending 31 31 read-write NOT_PENDING On writes, has no effect. On reads, NMI exception is not pending 0 PENDING On writes, changes the NMI exception state to pending. On reads, NMI exception is pending 1 NVIC_ICER Interrupt clear-enable register 0x180 32 read-write 0x0 0xffffffff Int_GPT1 Interrupt clear for GPT1 0 0 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_GPT2 Interrupt clear for GPT2 1 1 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_ADC2 Interrupt clear for MU, ADC2 2 2 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_ADC1 Interrupt clear for ADC1 3 3 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_CCU6SR0 Interrupt clear for CCU6 SR0 4 4 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_CCU6SR1 Interrupt clear for CCU6 SR1 5 5 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_CCU6SR2 Interrupt clear for CCU6 SR2 6 6 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_CCU6SR3 Interrupt clear for CCU6 SR3 7 7 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_SSC1 Interrupt clear for SSC1 8 8 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_SSC2 Interrupt clear for SSC2 9 9 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_UART1 Interrupt clear for UART1 10 10 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_UART2 Interrupt clear for UART2 11 11 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_EXINT0 Interrupt clear for external Int 0 12 12 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_EXINT1 Interrupt clear for external Int 1 13 13 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_WAKEUP Interrupt clear for WAKEUP 14 14 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_LS1 Interrupt clear for LS1 17 17 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_LS2 Interrupt clear for LS2 18 18 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_HS1 Interrupt clear for HS1 19 19 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_HS2 Interrupt clear for HS2 20 20 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_DU Interrupt clear for differential unit 21 21 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_MON Interrupt clear for MON 22 22 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 Int_PORT2 Interrupt Clear for PORT2 23 23 read-write DISABLE On reads the associated interrupt is disabled, no effect on write 0 ENABLE On reads the associated interrupt is enabled, on writes the associated interrupt is disabled 1 NVIC_ICPR Interrupt clear-pending register 0x280 32 read-write 0x0 0xffffffff Int_GPT1 Interrupt clear pending for GPT1 0 0 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_GPT2 Interrupt clear pending for GPT2 1 1 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_ADC2 Interrupt clear pending for MU, ADC2 2 2 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_ADC1 Interrupt clear pending for ADC1 3 3 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_CCU6SR0 Interrupt clear pending for CCU6 SR0 4 4 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_CCU6SR1 Interrupt clear pending for CCU6 SR1 5 5 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_CCU6SR2 Interrupt clear pending for CCU6 SR2 6 6 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_CCU6SR3 Interrupt clear pending for CCU6 SR3 7 7 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_SSC1 Interrupt clear pending for SSC1 8 8 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_SSC2 Interrupt clear pending for SSC2 9 9 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_UART1 Interrupt clear pending for UART1 10 10 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_UART2 Interrupt clear pending for UART2 11 11 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_EXINT0 Interrupt clear pending for external Int 0 12 12 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_EXINT1 Interrupt clear pending for external Int 1 13 13 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_WAKEUP Interrupt clear pending for WAKEUP 14 14 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_LS1 Interrupt clear pending for LS1 17 17 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_LS2 Interrupt clear pending for LS2 18 18 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_HS1 Interrupt clear pending for HS1 19 19 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_HS2 Interrupt clear pending for HS2 20 20 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_DU Interrupt clear pending for differential unit 21 21 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_MON Interrupt clear pending for MON 22 22 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 Int_PORT2 Interrupt clear pending for PORT2 23 23 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending On reads the associated interrupt is pending, on writes the status of the associated interrupt is changed to not pending 1 NVIC_IPR0 Interrupt priority 0 register 0x400 32 read-write 0x0 0xffffffff PRI_GPT1 Priority for GPT1 6 7 read-write PRI_GPT2 Priority for GPT2 14 15 read-write PRI_ADC2 Priority for MU, ADC2 22 23 read-write PRI_ADC1 Priority for ADC1 30 31 read-write NVIC_IPR1 Interrupt priority 1 register 0x404 32 read-write 0x0 0xffffffff PRI_CCU6SR0 Priority for CCU6 SR0 6 7 read-write PRI_CCU6SR1 Priority for CCU6 SR1 14 15 read-write PRI_CCU6SR2 Priority for CCU6 SR2 22 23 read-write PRI_CCU6SR3 Priority for CCU6 SR3 30 31 read-write NVIC_IPR2 Interrupt priority 2 register 0x408 32 read-write 0x0 0xffffffff PRI_SSC1 Priority for CCU6 SSC1 6 7 read-write PRI_SSC2 Priority for CCU6 SSC2 14 15 read-write PRI_UART1 Priority for CCU6 UART1 22 23 read-write PRI_UART2 Priority for CCU6 UART2 30 31 read-write NVIC_IPR3 Interrupt priority 3 register 0x40C 32 read-write 0x0 0xffffffff PRI_EXINT0 Priority for external Int 0 6 7 read-write PRI_EXINT1 Priority for external Int 1 14 15 read-write PRI_WAKEUP Priority for WAKEUP 22 23 read-write NVIC_IPR4 Interrupt priority 4 register 0x410 32 read-write 0x0 0xffffffff PRI_LS1 Priority for LS1 14 15 read-write PRI_LS2 Priority for LS2 22 23 read-write PRI_HS1 Priority for HS1 30 31 read-write NVIC_IPR5 Interrupt priority 5 register 0x414 32 read-write 0x0 0xffffffff PRI_HS2 Priority for HS2 6 7 read-write PRI_DU Priority for differential unit 14 15 read-write PRI_MON Priority for MON 22 23 read-write PRI_PORT2 Priority for PORT2 30 31 read-write NVIC_ISER Interrupt set-enable register 0x100 32 read-write 0x0 0xffffffff Int_GPT1 Interrupt set for GPT1 0 0 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_GPT2 Interrupt set for GPT2 1 1 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_ADC2 Interrupt set for MU, ADC2 2 2 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_ADC1 Interrupt set for ADC1 3 3 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_CCU6SR0 Interrupt set for CCU6 SR0 4 4 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_CCU6SR1 Interrupt set for CCU6 SR1 5 5 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_CCU6SR2 Interrupt set for CCU6 SR2 6 6 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_CCU6SR3 Interrupt set for CCU6 SR3 7 7 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_SSC1 Interrupt set for SSC1 8 8 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_SSC2 Interrupt set for SSC2 9 9 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_UART1 Interrupt set for UART1 10 10 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_UART2 Interrupt set for UART2 11 11 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_EXINT0 Interrupt set for external Int 0 12 12 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_EXINT1 Interrupt set for external Int 1 13 13 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_WAKEUP Interrupt set for WAKEUP 14 14 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_LS1 Interrupt set for LS1 17 17 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_LS2 Interrupt set for LS2 18 18 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_HS1 Interrupt set for HS1 19 19 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_HS2 Interrupt set for HS2 20 20 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_DU Interrupt set for differential unit 21 21 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_MON Interrupt set for MON 22 22 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 Int_PORT2 Interrupt set for PORT2 23 23 read-write DISABLED No effect on write 0 ENABLE Enables the associated interrupt 1 NVIC_ISPR Interrupt set-pending register 0x200 32 read-write 0x0 0xffffffff Int_GPT1 Interrupt set pending for GPT1 0 0 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_GPT2 Interrupt set pending for GPT2 1 1 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_ADC2 Interrupt set pending for MU, ADC2 2 2 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_ADC1 Interrupt set pending for ADC1 3 3 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_CCU6SR0 Interrupt set pending for CCU6 SR0 4 4 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_CCU6SR1 Interrupt set pending for CCU6 SR1 5 5 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_CCU6SR2 Interrupt set pending for CCU6 SR2 6 6 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_CCU6SR3 Interrupt set pending for CCU6 SR3 7 7 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_SSC1 Interrupt set pending for SSC1 8 8 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_SSC2 Interrupt set pending for SSC2 9 9 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_UART1 Interrupt set pending for UART1 10 10 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_UART2 Interrupt set pending for UART2 11 11 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_EXINT0 Interrupt set pending for external Int 0 12 12 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_EXINT1 Interrupt set pending for external Int 1 13 13 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_WAKEUP Interrupt set pending for WAKEUP 14 14 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_LS1 Interrupt set pending for LS1 17 17 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_LS2 Interrupt set pending for LS2 18 18 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_HS1 Interrupt set pending for HS1 19 19 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_HS2 Interrupt set pending for HS2 20 20 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_DU Interrupt set pending for differential unit 21 21 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_MON Interrupt set pending for MON 22 22 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 Int_PORT2 Interrupt set pending for PORT2 23 23 read-write Not_pending On reads the associated interrupt is not pending, no effect on writes 0 Pending The associated interrupt is pending 1 SCR System control register 0xD10 32 read-write 0x0 0xffffffff SLEEPONEXIT Sleep on exit 1 1 read-write NO_SLEEP Do not sleep when returning to Thread mode 0 SLEEP Enter sleep or deep sleep on return from an ISR to Thread mode 1 SLEEPDEEP Sleep deep 2 2 read-write SLEEP Sleep 0 DEEP_SLEEP Deep sleep 1 SEVONPEND Send event on pending bit 4 4 read-write SOME Only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded 0 ALL Enabled events and all interrupts, including disabled interrupts, can wake up the processor 1 SHPR2 System handler priority 2 register 0xD1C 32 read-write 0x0 0xffffffff PRI_11 Priority of system handler 11, SVCall 30 31 read-write SHPR3 System handler priority 3 register 0xD20 32 read-write 0x0 0xffffffff PRI_14 Priority of system handler 14, PendSV 22 23 read-write PRI_15 Priority of system handler 15, SysTick 30 31 read-write SYSTICK_CALIB SysTick calibration value register 0x1C 32 read-only 0x0 0xf000000 TENMS Tenms 0 23 read-only SKEW Skew 30 30 read-only NOREF No reference clock 31 31 read-only SYSTICK_CSR SysTick control and status register 0x10 32 read-write 0x0 0xffffffff ENABLE Enable 0 0 read-write DISABLE Counter disabled 0 ENABLE Counter enabled 1 TICKINT TICKINT 1 1 read-write DISABLE Counting down to 0 does not assert the SysTick exception request 0 ENABLE Counting down to 0 asserts the SysTick exception request 1 CLKSOURCE CLK source 2 2 read-write EXTCLK External reference clock (from fSYS/4) 0 HCLK Core clock (from fSYS) 1 COUNTFLAG Count flag 16 16 read-only SYSTICK_CVR SysTick current value register 0x18 32 read-write 0x0 0xff000000 CURRENT Current 0 23 read-write SYSTICK_RVR SysTick reload value register 0x14 32 read-write 0x0 0xff000000 RELOAD Reload 0 23 read-write GPT12E 100 General purpose timer units (GPT12) registers GPT12E 0x40010000 0 0x4000 registers CAPREL Capture/reload register 0x1C 32 read-write 0x0 0xffffffff CAPREL Current reload value or captured value 0 15 read-write ID Module identification register 0x0 32 read-only 0x5804 0xffffffff MOD_REV Module revision number 0 7 read-only MOD_TYPE Module identification number 8 15 read-only PISEL Port input select register 0x4 32 read-write 0x0 0xffffffff IST2IN Input select for T2IN 0 0 read-write T2INA Signal T2INA is selected 0 T2INB Signal T2INB is selected 1 IST2EUD Input select for T2EUD 1 1 read-write T2EUDA Signal T2EUDA is selected 0 T2EUDB Signal T2EUDB is selected 1 IST3IN Input select for T3IN 2 3 read-write T3INA Signal T3INA is selected 0 T3INB Signal T3INB is selected 1 T3INC Signal T3INC is selected 2 T3IND Signal T3IND is selected 3 IST3EUD Input select for T3EUD 4 5 read-write T3EUDA Signal T3EUDA is selected 0 T3EUDB Signal T3EUDB is selected 1 T3EUDC Signal T3EUDC is selected 2 T3EUDD Signal T3EUDD is selected 3 IST4IN Input select for T4IN 6 7 read-write T4INA Signal T4INA is selected 0 T4INB Signal T4INB is selected 1 T4INC Signal T4INC is selected 2 T4IND Signal T4IND is selected 3 IST4EUD Input select for TEUD 8 9 read-write T4EUDA Signal T4EUDA is selected 0 T4EUDB Signal T4EUDB is selected 1 T4EUDC Signal T4EUDC is selected 2 T4EUDD Signal T4EUDD is selected 3 IST5IN Input select for T5IN 10 10 read-write T5INA Signal T5INA is selected 0 T5INB Signal T5INB is selected 1 IST5EUD Input select for T5EUD 11 11 read-write T5EUDA Signal T5EUDA is selected 0 T5EUDB Signal T5EUDB is selected 1 IST6IN Input select for T6IN 12 12 read-write T6INA Signal T6INA is selected 0 T6INB Signal T6INB is selected 1 IST6EUD Input select for T6EUD 13 13 read-write T6EUDA Signal T6EUDA is selected 0 T6EUDB Signal T6EUDB is selected 1 ISCAPIN Input select for CAPIN 14 15 read-write CAPINA Signal CAPINA is selected 0 CAPINB Signal CAPINB is selected 1 CAPINC Signal CAPINC (read trigger from T3) is selected 2 CAPIND Signal CAPIND (read trigger from T2 or T3 or T4) is selected 3 T2 Timer T2 count register 0x20 32 read-write 0x0 0xffffffff T2 Timer T2 current value 0 15 read-write T2CON Timer T2 control register 0x8 32 read-write 0x0 0xffffffff T2I Timer T2 input parameter selection 0 2 read-write T2M Timer T2 input mode control 3 5 read-write TIMER_MODE Timer mode 0 COUNTER_MODE Counter mode 1 GATED_LOW Gated timer mode with gate active low 2 GATED_HIGH Gated timer mode with gate active high 3 RELOAD_MODE Reload mode 4 CAPTURE_MODE Capture mode 5 INCREMENTAL_INTERFACE_MODE Rotation detection mode 6 INCREMENTAL_INTERFACE_MODE Edge detection mode 7 T2R Timer T2 input run bit 6 6 read-write STOP Timer T2 stops 0 RUN Timer T2 runs 1 T2UD Timer T2 up/down control 7 7 read-write UP Timer T2 counts up 0 DOWN Timer T2 counts down 1 T2UDE Timer T2 external up/down enable 8 8 read-write T2UD Count direction is controlled by bit T2UD; input T2EUD is disconnected 0 T2EUD Count direction is controlled by input T2EUD 1 T2RC Timer T2 remote control 9 9 read-write T2R Timer T2 is controlled by its own run bit T2R 0 T3R Timer T2 is controlled by the run bit T3R of core timer T3, not by bit T2R 1 T2IRIDIS Timer T2 interrupt disable 12 12 read-write ENABLED Interrupt generation for T2CHDIR and T2EDGE interrupts in incremental interface mode is enabled 0 DISABLED Interrupt generation for T2CHDIR and T2EDGE interrupts in incremental interface mode is disabled 1 T2EDGE Timer T2 edge detection 13 13 read-write NO_COUNT No count edge was detected 0 COUNT A count edge was detected 1 T2CHDIR Timer T2 count direction change 14 14 read-write NO_CHANGE No change of count direction was detected 0 CHANGE A change of count direction was detected 1 T2DIR Timer T2 rotation direction 15 15 read-only UP Timer T2 counts up 0 DOWN Timer T2 counts down 1 T3 Timer T3 count register 0x24 32 read-write 0x0 0xffffffff T3 Timer T3 current value 0 15 read-write T3CON Timer T3 control register 0xC 32 read-write 0x0 0xffffffff T3I Timer T3 input parameter selection 0 2 read-write T3M Timer T3 input mode control 3 5 read-write TIMER_MODE Timer mode 0 COUNTER_MODE Counter mode 1 GATED_LOW Gated timer mode with gate active low 2 GATED_HIGH Gated timer mode with gate active high 3 INCREMENTAL_INTERFACE_MODE Rotation detection mode 6 INCREMENTAL_INTERFACE_MODE Edge detection mode 7 T3R Timer T3 input run bit 6 6 read-write STOP Timer T3 stops 0 RUN Timer T3 runs 1 T3UD Timer T3 up/down control 7 7 read-write UP Timer T3 counts up 0 DOWN Timer T3 counts down 1 T3UDE Timer T3 external up/down enable 8 8 read-write T3UD Count direction is controlled by bit T3UD; input T3EUD is disconnected 0 T3EUD Count direction is controlled by input T3EUD 1 T3OE Overflow/underflow output enable 9 9 read-write DISABLED Alternate output function disabled 0 T3OUT State of T3 toggle latch is output on pin T3OUT 1 T3OTL Timer T3 overflow toggle latch 10 10 read-write BPS1 GPT1 block prescaler control 11 12 read-write 8 fGPT/8 0 4 fGPT/4 1 32 fGPT/32 2 16 fGPT/16 3 T3EDGE Timer T3 edge detection flag 13 13 read-write NO_COUNT No count edge was detected 0 COUNT A count edge was detected 1 T3CHDIR Timer T3 count direction change flag 14 14 read-write NO_CHANGE No change of count direction was detected 0 CHANGE A change of count direction was detected 1 T3DIR Timer T3 rotation direction flag 15 15 read-only UP Timer T3 counts up 0 DOWN Timer T3 counts down 1 T4 Timer T4 count register 0x28 32 read-write 0x0 0xffffffff T4 Timer T4 current value 0 15 read-write T4CON Timer T4 control register 0x10 32 read-write 0x0 0xffffffff T4I Timer T4 input parameter selection 0 2 read-write T4M Timer T4 mode control (basic operating mode) 3 5 read-write TIMER_MODE Timer mode 0 COUNTER_MODE Counter mode 1 GATED_LOW Gated timer mode with gate active low 2 GATED_HIGH Gated timer mode with gate active high 3 RELOAD_MODE Reload mode 4 CAPTURE_MODE Capture mode 5 INCREMENTAL_INTERFACE_MODE Rotation detection mode 6 INCREMENTAL_INTERFACE_MODE Edge detection mode 7 T4R Timer T4 input run bit 6 6 read-write STOP Timer T4 stops 0 RUN Timer T4 runs 1 T4UD Timer T4 up/down control 7 7 read-write UP Timer T4 counts up 0 DOWN Timer T4 counts down 1 T4UDE Timer T4 external up/down enable 8 8 read-write T4UD Count direction is controlled by bit T4UD; input T4EUD is disconnected 0 T4EUD Count direction is controlled by input T4EUD 1 T4RC Timer T4 remote control 9 9 read-write T4R Timer T4 is controlled by its own run bit T4R 0 T3R Timer T4 is controlled by the run bit T3R of core timer T3, but not by bit T4R 1 CLRT2EN Clear timer T2 enable 10 10 read-write NO_EFFECT No effect of T4EUD on timer T2 0 CLEAR A falling edge on T4EUD clears timer T2 1 CLRT3EN Clear timer T3 enable 11 11 read-write NO_EFFECT No effect of T4IN on timer T3 0 CLEAR A falling edge on T4In clears timer T3 1 T4IRDIS Timer T4 interrupt disable 12 12 read-write ENABLED Interrupt generation for T4CHDIR and T4EDGE interrupts in incremental interface mode is enabled 0 DISABLED Interrupt generation for T4CHDIR and T4EDGE interrupts in incremental interface mode is disabled 1 T4EDGE Timer T4 edge direction 13 13 read-write NO_COUNT No count edge was detected 0 COUNT A count edge was detected 1 T4CHDIR Timer T4 count direction change 14 14 read-write NO_CHANGE No change in count direction was detected 0 CHANGE A change in count direction was detected 1 T4RDIR Timer T4 rotation direction 15 15 read-only UP Timer T4 counts up 0 DOWN Timer T4 counts down 1 T5 Timer 5 count register 0x2C 32 read-write 0x0 0xffffffff T5 Timer T5 current value 0 15 read-write T5CON Timer T5 control register 0x14 32 read-write 0x0 0xffffffff T5I Timer T5 input parameter selection 0 2 read-write T5M Timer T5 input mode control 3 4 read-write TIMER_MODE Timer mode 0 COUNTER_MODE Counter mode 1 GATED_LOW Gated timer mode with gate active low 2 GATED_HIGH Gated timer mode with gate active high 3 T5R Timer T5 run bit 6 6 read-write STOP Timer T5 stops 0 RUN Timer T5 runs 1 T5UD Timer T5 up/down control 7 7 read-write UP Timer T5 counts up 0 DOWN Timer T5 counts down 1 T5UDE Timer T5 external up/down enable 8 8 read-write T5UD Count direction is controlled by bit T5UD; input T5EUD is disconnected 0 T5EUD Count direction is controlled by input T5EUD 1 T5RC Timer T5 remote control 9 9 read-write T5R Timer T5 is controlled by its own run bit T5R 0 T6R Timer T5 is controlled by the run bit T6R of core timer T6, not by bit T5R 1 CT3 Timer T3 capture trigger enable 10 10 read-write CAPIN Capture trigger from input line CAPIN 0 T3IN Capture trigger from T3 input lines T3IN and/or T3EUD 1 CI Register CAPREL capture trigger selection 12 13 read-write DISABLED Capture disabled 0 POSITIVE Positive transition (rising edge) on CAPIN 1 NEGATIVE Negative transition (falling edge) on CAPIN or any transition on T3EUD 2 ANY Any transition (rising or falling edge) on CAPIN or any transition on T3IN or T3EUD 3 T5CLR Timer T5 clear enable bit 14 14 read-write NOT_CLEARED Timer T5 is not cleared on a capture event 0 CLEARED Timer T5 is cleared on a capture event 1 T5SC Timer T5 capture mode enable 15 15 read-write DISABLED Capture into register CAPREL disabled 0 ENABLED Capture into register CAPREL enabled 1 T6 Timer 6 count register 0x30 32 read-write 0x0 0xffffffff T6 Timer T6 current value 0 15 read-write T6CON Timer T6 control register 0x18 32 read-write 0x0 0xffffffff T6I Timer T6 input parameter selection 0 2 read-write T6M Timer T6 mode control 3 5 read-write TIMER_MODE Timer mode 0 COUNTER_MODE Counter mode 1 GATED_LOW Gated timer mode with gate active low 2 GATED_HIGH Gated timer mode with gate active high 3 T6R Timer T6 input run bit 6 6 read-write STOP Timer T3 stops 0 RUN Timer T3 runs 1 T6UD Timer T6 up/down control 7 7 read-write UP Timer T3 counts up 0 DOWN Timer T3 counts down 1 T6UDE Timer T6 external up/down enable 8 8 read-write T6UD Count direction is controlled by bit T6UD; input T6EUD is disconnected 0 T6EUD Count direction is controlled by input T6EUD 1 T6OE Overflow/underflow output enable 9 9 read-write DISABLED Alternate output function disabled 0 T6OUT State of T6 toggle latch is output on pin T6OUT 1 T6OTL Timer T6 overflow toggle latch 10 10 read-write BPS2 GPT2 block prescaler control 11 12 read-write 4 fGPT/4 0 2 fGPT/2 1 16 fGPT/16 2 8 fGPT/8 3 T6CLR Timer T6 clear enable bit 14 14 read-write NOT_CLEARED Timer T6 is not cleared on a capture event 0 CLEARED Timer T6 is cleared on a capture event 1 T6SR Timer T6 reload mode enable 15 15 read-write DISABLED Reload from register CAPREL disabled 0 ENABLED Reload from register CAPREL enabled 1 HS 100 High-side switch registers HS 0x40024000 0 0x4000 registers CTRL High-side driver control register 0x4 32 read-write 0x0 0xffffffff HS1_EN High side 1 enable 0 0 read-write DISABLE HS circuit power off 0 ENABLE HS circuit power on 1 HS1_PWM High side 1 PWM enable 1 1 read-write DISABLE Disables control by PWM input 0 ENABLE Enables control by PWM input 1 HS1_ON High side 1 on 2 2 read-write OFF HS driver off 0 ON HS driver on 1 HS1_OL_EN High side 1 open load detection enable 3 3 read-write DISABLE Disable open load detection 0 ENABLE Enable open load detection 1 HS1_CYC_ON_ACTIVE High side 1 cyclic ON driver 7 7 read-write OFF Cyclic ON driver OFF 0 ON Cyclic ON driver ON 1 HS1_SRCTL_SEL High side 1 slew rate control select 8 8 read-write SLEW_RATE_1 Slew rate 10 V/us is enabled 0 SLEW_RATE_2 Slew rate 30 V/us is enabled 1 HS1_OC_SEL High side 1 overcurrent threshold selection 12 13 read-write IOCTH0 25 mA min. 0 IOCTH1 50 mA min. 1 IOCTH2 100 mA min. 2 IOCTH3 150 mA min. 3 HS2_EN High side 2 enable 16 16 read-write DISABLE HS circuit power off 0 ENABLE HS circuit power on 1 HS2_PWM High side 2 PWM enable 17 17 read-write DISABLE Disables control by PWM input 0 ENABLE Enables control by PWM input 1 HS2_ON High side 2 on 18 18 read-write OFF HS driver off 0 ON HS driver on 1 HS2_OL_EN High side 2 open load detection enable 19 19 read-write DISABLE Disable open load detection 0 ENABLE Enable open load detection 1 HS2_CYC_ON_ACTIVE High side 2 cyclic ON driver 23 23 read-write OFF Cyclic ON driver OFF 0 ON Cyclic ON driver ON 1 HS2_SRCTL_SEL High side 2 slew rate control select 24 24 read-write SLEW_RATE_1 Slew rate 10 V/us is enabled 0 SLEW_RATE_2 Slew rate 30 V/us is enabled 1 HS2_OC_SEL High side 2 overcurrent threshold selection 28 29 read-write IOCTH0 25 mA min. 0 IOCTH1 50 mA min. 1 IOCTH2 100 mA min. 2 IOCTH3 150 mA min. 3 HS1_TRIM High-side driver 1 TRIM register 0x1C 32 read-write 0x0 0xffffffff HS1_OL_BTFILT_SEL Blanking time filter select for HS1 open load detection 0 1 read-write 2_us 4 us filter time 0 4_us 8 us filter time 1 8_us 16 us filter time 2 16_us 32 us filter time 3 HS1_OC_OT_BTFILT_SEL Blanking time filter select for HS1 overcurrent/overtemperature detection 8 9 read-write 4_us 4 us filter time 0 8_us 8 us filter time 1 16_us 16 us filter time 2 32_us 32 us filter time 3 HS2_TRIM High-side driver 2 TRIM register 0x20 32 read-write 0x0 0xffffffff HS2_OL_BTFILT_SEL Blanking time filter select for HS2 open load detection 0 1 read-write 2_us 4 us filter time 0 4_us 8 us filter time 1 8_us 16 us filter time 2 16_us 32 us filter time 3 HS2_OC_OT_BTFILT_SEL Blanking time/filter select for HS2 overcurrent/overtemperature detection 8 9 read-write 4_us 4 us filter time 0 8_us 8 us filter time 1 16_us 16 us filter time 2 32_us 32 us filter time 3 IRQCLR High-side driver interrupt status clear register 0xC 32 read-write 0x0 0xffffffff HS1_OT_ISC High Side 1 overtemperature interrupt status clear 5 5 write-only NO_CLEAR No clear 0 CLEAR Clear 1 HS1_OL_ISC High side 1 open load interrupt status clear 6 6 write-only NO_CLEAR No clear 0 CLEAR Clear 1 HS1_OC_ISC High side 1 overcurrent interrupt status clear 7 7 write-only NO_CLEAR No clear 0 CLEAR Clear 1 HS1_OT_SC High side 1 overtemperature status clear 13 13 write-only NO_CLEAR No clear 0 CLEAR Clear 1 HS1_OL_SC High side 1 open load status clear 14 14 write-only NO_CLEAR No clear 0 CLEAR Clear 1 HS2_OT_ISC High side 2 overtemperature interrupt status clear 21 21 write-only NO_CLEAR No clear 0 CLEAR Clear 1 HS2_OL_ISC High side 2 open load interrupt status clear 22 22 write-only NO_CLEAR No clear 0 CLEAR Clear 1 HS2_OC_ISC High side 2 overcurrent interrupt status clear 23 23 write-only NO_CLEAR No clear 0 CLEAR Clear 1 HS2_OT_SC High side 2 overtemperature status clear 29 29 write-only NO_CLEAR No clear 0 CLEAR Clear 1 HS2_OL_SC High side 2 open load status clear 30 30 write-only NO_CLEAR No clear 0 CLEAR Clear 1 IRQEN High-side driver interrupt enable register 0x10 32 read-write 0x0 0xffffffff HS1_OT_IEN High Side 1 overtemperature interrupt enable 5 5 read-write DISABLED Disabled 0 ENABLE Enable 1 HS1_OL_IEN High side 1 open load interrupt enable 6 6 read-write DISABLE Disabled 0 ENABLE Enable 1 HS1_OC_IEN High side 1 overcurrent interrupt enable 7 7 read-write DISABLE Disabled 0 ENABLE Enable 1 HS2_OT_IEN High side 2 overtemperature interrupt enable 21 21 read-write DISABLED Disabled 0 ENABLE Enable 1 HS2_OL_IEN High side 2 open load interrupt enable 22 22 read-write DISABLE Disabled 0 ENABLE Enable 1 HS2_OC_IEN High side 2 overcurrent interrupt enable 23 23 read-write DISABLE Disabled 0 ENABLE Enable 1 IRQS High-side driver interrupt status register 0x8 32 read-write 0x0 0xffffffff HS1_OT_IS High side 1 overtemperature interrupt status 5 5 read-write NO_OVERTEMPERATURE No overtemperature occurred 0 OVERTEMPERATURE Overtemperature occurred; switch is automatically shut down. Write sets status 1 HS1_OL_IS High side 1 open load interrupt status 6 6 read-write NORMAL Normal load 0 OPEN_LOAD Open load detected, write sets status 1 HS1_OC_IS High side 1 overcurrent interrupt status 7 7 read-write NO_OVERCURRENT No overcurrent condition occurred 0 OVERCURRENT Overcurrent occurred; switch is automatically shut down. Write sets status 1 HS1_OT_STS High side 1 overtemperature status 13 13 read-write NO_OVERTEMPERATURE No overtemperature occurred 0 OVERTEMPERATURE Overtemperature occurred; switch is automatically shut down. Write sets status 1 HS1_OL_STS High side 1 open load interrupt status 14 14 read-write NO_OPEN_LOAD No open load condition occurred 0 OPEN_LOAD Open load occurred; switch is not automatically shut down. Write sets status 1 HS2_OT_IS High side 2 overtemperature interrupt status 21 21 read-write NO_OVERTEMPERATURE No overtemperature occurred 0 OVERTEMPERATURE Overtemperature occurred; switch is automatically shut down. Write sets status 1 HS2_OL_IS High side 2 open load interrupt status 22 22 read-write NORMAL Normal load 0 OPEN_LOAD Open load detected, write sets status 1 HS2_OC_IS High side 2 overcurrent interrupt status 23 23 read-write NO_OVERCURRENT No overcurrent condition occurred 0 OVERCURRENT Overcurrent occurred; switch is automatically shut down. Write sets status 1 HS2_OT_STS High side 2 overtemperature status 29 29 read-write NO_OVERTEMPERATURE No overtemperature occurred 0 OVERTEMPERATURE Overtemperature occurred; switch is automatically shut down. Write sets status 1 HS2_OL_STS High side 2 open load interrupt status 30 30 read-write NO_OPEN_LOAD No open load condition occurred 0 OPEN_LOAD Open load occurred; switch is not automatically shut down. Write sets status 1 PWMSRCSEL High-side PWM source selection register 0x24 32 read-write 0x0 0xffffffff HS2_SRC_SEL HS2 PWM source selection 0 2 read-write CC60 PWM output of CCU6 (CC60) 0 CC61 PWM output of CCU6 (CC61) 1 CC62 PWM output of CCU6 (CC62) 2 COUT60 PWM output of CCU6 (COUT60) 3 COUT61 PWM output of CCU6 (COUT61) 4 COUT62 PWM output of CCU6 (COUT62) 5 T3OUT PWM output of GPT12 6 HS1_SRC_SEL HS1 PWM source selection 3 5 read-write CC60 PWM output of CCU6 (CC60) 0 CC61 PWM output of CCU6 (CC61) 1 CC62 PWM output of CCU6 (CC62) 2 COUT60 PWM output of CCU6 (COUT60) 3 COUT61 PWM output of CCU6 (COUT61) 4 COUT62 PWM output of CCU6 (COUT62) 5 T3OUT PWM output of GPT12 6 LS 100 Low-side switch registers LS 0x4001C000 0 0x4000 registers CTRL Low-side driver control register 0x4 32 read-write 0x0 0xffffffff LS1_EN Low-side switch 1 enable 0 0 read-write DISABLE Disables LS1 0 ENABLE Enables LS1 1 LS1_PWM Low-side switch 1 PWM enable 1 1 read-write DISABLE Normal mode controlled by LS1_ON 0 ENABLE Enables LS1 for PWM mode 1 LS1_ON Low-side switch 1 on/off 2 2 read-write OFF Switches LS1 off 0 ON Turns LS1 on 1 LS1_OL_EN Open load detection enable 3 3 read-write DISABLE Open load detection 0 ENABLE Open load detection 1 LS1_SRCTL_SEL Low-side switch 1 slew rate selection 8 8 read-write SLOW Slow slew rate is selected 0 FAST Fast slew rate is selected 1 LS2_EN Low-side switch 2 enable 16 16 read-write DISABLE Disables LS2 0 ENABLE Enables LS2 1 LS2_PWM Low-side switch 2 PWM enable 17 17 read-write DISABLE Normal mode controlled by LS2_ON 0 ENABLE Enables LS2 for PWM mode 1 LS2_ON Low-Side switch 2 on/off 18 18 read-write OFF Switches LS2 off 0 ON Turns LS2 on 1 LS2_OL_EN Open load detection enable 19 19 read-write DISABLE Open load detection 0 ENABLE Open load detection 1 LS2_SRCTL_SEL Low-side switch 2 slew rate selection 24 24 read-write SLOW Slow slew rate is selected 0 FAST Fast slew rate is selected 1 IRQCLR Low-side driver interrupt status clear register 0xC 32 read-write 0x0 0xffffffff LS1_OT_PREWARN_ISC Low-side 1 overtemperature prewarn interrupt status clear 4 4 write-only NO_CLEAR No clear 0 CLEAR Clear 1 LS1_OT_ISC Low-side 1 overtemperature interrupt status clear 5 5 write-only NO_CLEAR No clear 0 CLEAR Clear 1 LS1_OL_ISC Low-side 1 open load interrupt status clear 6 6 write-only NO_CLEAR No clear 0 CLEAR Clear 1 LS1_OC_ISC Low-side 1 overcurrent interrupt status clear 7 7 write-only NO_CLEAR No clear 0 CLEAR Clear 1 LS1_OT_PREWARN_SC Low-side 1 overtemperature prewarn status clear 12 12 write-only NO_CLEAR No clear 0 CLEAR Clear 1 LS1_OT_SC Low-side 1 overtemperature status clear 13 13 write-only NO_CLEAR No clear 0 CLEAR Clear 1 LS1_OL_SC Low-side 1 open load status clear 14 14 write-only NO_CLEAR No clear 0 CLEAR Clear 1 LS2_OT_PREWARN_ISC Low-side 2 overtemperature prewarn interrupt status clear 20 20 write-only NO_CLEAR No clear 0 CLEAR Clear 1 LS2_OT_ISC Low-side 2 overtemperature interrupt status clear 21 21 write-only NO_CLEAR No clear 0 CLEAR Clear 1 LS2_OL_ISC Low-side 2 open load interrupt status clear 22 22 write-only NO_CLEAR No clear 0 CLEAR Clear 1 LS2_OC_ISC Low-side 2 overcurrent interrupt status clear 23 23 write-only NO_CLEAR No clear 0 CLEAR Clear 1 LS2_OT_PREWARN_SC Low-side 2 overtemperature prewarn status clear 28 28 write-only NO_CLEAR No clear 0 CLEAR Clear 1 LS2_OT_SC Low-side switch 2 overtemperature status clear 29 29 write-only NO_CLEAR No clear 0 CLEAR Clear 1 LS2_OL_SC Low-side 2 open load status clear 30 30 write-only NO_CLEAR No clear 0 CLEAR Clear 1 IRQEN Low-side driver interrupt enable register 0x10 32 read-write 0x0 0xffffffff LS1_OT_PREWARN_IEN Low-side 1 overtemperature prewarn interrupt enable 4 4 read-write DISABLE Disabled 0 ENABLE Enabled 1 LS1_OT_IEN Low-side 1 overtemperature interrupt enable 5 5 read-write DISABLE Disabled 0 ENABLE Enabled 1 LS1_OL_IEN Low-side 1 open load interrupt enable 6 6 read-write DISABLE Disabled 0 ENABLE Enabled 1 LS1_OC_IEN Low-side 1 overcurrent interrupt enable 7 7 read-write DISABLE Disabled 0 ENABLE Enabled 1 LS2_OT_PREWARN_IEN Low-side 2 overtemperature prewarn interrupt enable 20 20 read-write DISABLE Disabled 0 ENABLE Enabled 1 LS2_OT_IEN Low-side 2 overtemperature interrupt enable 21 21 read-write DISABLE Disabled 0 ENABLE Enabled 1 LS2_OL_IEN Low-side 2 open load interrupt enable 22 22 read-write DISABLE Disabled 0 ENABLE Enabled 1 LS2_OC_IEN Low-side 2 overcurrent interrupt enable 23 23 read-write DISABLE Disabled 0 ENABLE Enabled 1 IRQS Low-side driver interrupt status register 0x8 32 read-write 0x0 0xffffffff LS1_OT_PREWARN_IS Low-Side 1 overtemperature prewarning interrupt status 4 4 read-write NO_OVERTEMPERATURE_PREWARN No overtemperature prewarn occurred. 0 OVERTEMPERATURE_PREWARN Overtemperature prewarn occurred. Write sets status 1 LS1_OT_IS Low-Side 1 overtemperature interrupt status 5 5 read-write NO_OVERTEMPERATURE No overtemperature occurred 0 OVERTEMPERATURE Overtemperature occurred; switch is automatically shut down. Write sets status 1 LS1_OL_IS Low-Side 1 open load interrupt status 6 6 read-write NO_OPEN_LOAD No open load condition occurred 0 OPEN_LOAD Open load occurred; switch is not automatically shut down. Write sets status 1 LS1_OC_IS Low-Side 1 overcurrent interrupt status 7 7 read-write NO_OVERCURRENT No overcurrent condition occurred 0 OVERCURRENT Overcurrent occurred; switch is automatically shut down. Write sets status 1 LS1_OT_PREWARN_STS Low-Side 1 overtemperature prewarning status 12 12 read-write NO_OVERTEMPERATURE_PREWARN No overtemperature prewarn occurred 0 OVERTEMPERATURE Overtemperature prewarn occurred; Write sets status 1 LS1_OT_STS Low-Side 1 overtemperature status 13 13 read-write NO_OVERTEMPERATURE No overtemperature occurred 0 OVERTEMPERATURE Overtemperature occurred; switch is automatically shut down. Write sets status 1 LS1_OL_STS Low-Side 1 open load status 14 14 read-write NO_OPEN_LOAD No open load condition occurred 0 OPEN_LOAD Open load occurred; switch is not automatically shut down. Write sets status 1 LS2_OT_PREWARN_IS Low-Side 2 overtemperature prewarning interrupt status 20 20 read-write NO_OVERTEMPERATURE_PREWARN No overtemperature prewarn occurred 0 OVERTEMPERATURE_PREWARN Overtemperature prewarn occurred. Write sets status 1 LS2_OT_IS Low-Side 2 overtemperature interrupt status 21 21 read-write NO_OVERTEMPERATURE No overtemperature occurred 0 OVERTEMPERATURE Overtemperature occurred; switch is automatically shut down. Write sets status 1 LS2_OL_IS Low-Side 2 open load interrupt status 22 22 read-write NO_OPEN_LOAD No open load condition occurred 0 OPEN_LOAD Open load occurred; switch is not automatically shut down. Write sets status 1 LS2_OC_IS Low-Side 2 overcurrent interrupt status 23 23 read-write NO_OVERCURRENT No overcurrent condition occurred 0 OVERCURRENT Overcurrent occurred; switch is automatically shut down. Write sets status 1 LS2_OT_PREWARN_STS Low-Side 2 overtemperature prewarning status 28 28 read-write NO_OVERTEMPERATURE_PREWARN No overtemperature prewarn occurred 0 OVERTEMPERATURE_PREWARN Overtemperature prewarn occurred. Write sets status 1 LS2_OT_STS Low-Side 2 overtemperature status 29 29 read-write NO_OVERTEMPERATURE No overtemperature occurred 0 OVERTEMPERATURE Overtemperature occurred; switch is automatically shut down. Write sets status 1 LS2_OL_STS Low-side 2 open load status 30 30 read-write NO_OPEN_LOAD No open load condition occurred 0 OPEN_LOAD Open load occurred; switch is not automatically shut down. Write sets status 1 LS1_TRIM Low-side 1 reference current trimming register 0x18 32 read-write 0x0 0xffffffff LS1_OL_BTFILT_SEL Open load blank time select for LS1 0 1 read-write 4_us 4 us filter time 0 8_us 8 us filter time 1 16_us 16 us filter time 2 32_us 32 us filter time 3 LS1_OC_BTFILT_SEL Overcurrent blanktime select for LS1 8 9 read-write 4_us 4 us filter time 0 8_us 8 us filter time 1 16_us 16 us filter time 2 32_us 32 us filter time 3 LS2_TRIM Low-side 2 reference current trimming register 0x20 32 read-write 0x0 0xffffffff LS2_OL_BTFILT_SEL Open load blank time select for LS2 0 1 read-write 4_us 4 us filter time 0 8_us 8 us filter time 1 16_us 16 us filter time 2 32_us 32 us filter time 3 LS2_OC_BTFILT_SEL Overcurrent blank time select for LS2 8 9 read-write 4_us 4 us filter time 0 8_us 8 us filter time 1 16_us 16 us filter time 2 32_us 32 us filter time 3 PWMSRCSEL Low-side PWM source selection register 0x1C 32 read-write 0x0 0xffffffff LS2_SRC_SEL LS2 PWM source selection 0 2 read-write CC60 PWM output of CCU6 (CC) 0 CC61 PWM output of CCU6 (CC) 1 CC62 PWM output of CCU6 (CC) 2 COUT60 PWM output of CCU6 (COUT) 3 COUT61 PWM output of CCU6 (COUT) 4 COUT62 PWM output of CCU6 (COUT) 5 T3OUT PWM output of GPT12 6 LS1_SRC_SEL LS1 PWM source selection 3 5 read-write CC60 PWM output of CCU6 (CC) 0 CC61 PWM output of CCU6 (CC) 1 CC62 PWM output of CCU6 (CC) 2 COUT60 PWM output of CCU6 (COUT) 3 COUT61 PWM output of CCU6 (COUT) 4 COUT62 PWM output of CCU6 (COUT) 5 T3OUT PWM output of GPT12 6 MF 100 Measurement unit registers MF 0x48018000 0 0x4000 registers REF1_STS Reference 1 status register 0x14 32 read-only 0xc1 0xffffffff REFBG_LOTHWARN_STS Status for Undervoltage threshold measurement of internal VAREF 4 4 read-only UPPER_TRIG_RESET Write clears status 0 UPPER_TRIG_SET Trigger status set 1 REFBG_UPTHWARN_STS Status for overvoltage threshold measurement of internal VAREF 5 5 read-only UPPER_TRIG_RESET Write clears status 0 UPPER_TRIG_SET Trigger status set 1 TEMPSENSE_CTRL Temperature sensor control register 0x10 32 read-write 0x3 0xffffffff LS_OTWARN_STS Low-side overtemperature warning (MU) status 4 4 read-write INACTIVE Write clears status 0 ACTIVE Interrupt status set 1 LS_OT_STS Low-side overtemperature (MU) status 5 5 read-only INACTIVE Write clears status 0 ACTIVE Interrupt status set 1 SYS_OTWARN_STS System overtemperature warning (MU) status 6 6 read-only INACTIVE Write clears status 0 ACTIVE Interrupt status set 1 SYS_OT_STS System overtemperature (MU) status 7 7 read-only INACTIVE Write clears status 0 ACTIVE Interrupt status set 1 PMU 100 Power Management Unit registers PMU 0x50004000 0 0x1000 registers CNF_RST_TFB Reset blind time register 0x6C 32 read-write 0x3 0xffffffff RST_TFB Reset pin blind time selection bits 0 1 read-write RST_TFB_0 0.5 us typ. 0 RST_TFB_1 1 us typ. 1 RST_TFB_2 5 us typ. 2 RST_TFB_3 31 us typ. 3 CNF_WAKE_FILTER PMU wake-up timing register 0xAC 32 read-write 0x0 0xffffffff CNF_LIN_FT Wake-up filter time for LIN WAKE 0 0 read-write 30_us 30 us filter time 0 50_us 50 us filter time 1 CNF_MON_FT Wake-up filter time for monitoring inputs 1 1 read-write 20_us 20 us filter time 0 40_us 40 us filter time 1 CNF_GPIO_FT Wake-up filter time for general purpose IO 2 3 read-write 10_us 10 us filter time 0 20_us 20 us filter time 1 40_us 40 us filter time 2 5_us 5 us filter time 3 GPIO_WAKE_STATUS GPIO port wake status register 0x4 32 read-only 0x0 0xffffffff GPIO1_STS_0 Wake GPIO1_0 8 8 read-only No_wake_up No wake-up detected 0 Wake_up Wake-up detected 1 GPIO1_STS_1 Wake GPIO1_1 9 9 read-only No_wake_up No wake-up detected 0 Wake_up Wake-up detected 1 GPIO1_STS_2 Wake GPIO1_2 10 10 read-only No_wake_up No wake-up detected 0 Wake_up Wake-up detected 1 GPIO1_STS_4 Wake GPIO1_4 12 12 read-only No_wake_up No wake-up detected 0 Wake_up Wake-up detected 1 GPUDATA0to3 General purpose user DATA0to3 register 0xC0 32 read-write 0x0 0xffffffff DATA0 DATA0 storage byte 0 7 read-write DATA1 DATA1 storage byte 8 15 read-write DATA2 DATA2 storage byte 16 23 read-write DATA3 DATA3 storage byte 24 31 read-write GPUDATA4to7 General purpose user DATA4to7 register 0xC4 32 read-write 0x0 0xffffffff DATA4 DATA4 storage byte 0 7 read-write DATA5 DATA5 storage byte 8 15 read-write DATA6 DATA6 storage byte 16 23 read-write DATA7 DATA7 storage byte 24 31 read-write GPUDATA8to11 General purpose user DATA8to11 register 0xC8 32 read-write 0x0 0xffffffff DATA8 DATA8 storage byte 0 7 read-write DATA9 DATA9 storage byte 8 15 read-write DATA10 DATA10 storage byte 16 23 read-write DATA11 DATA11 storage byte 24 31 read-write HIGHSIDE_CTRL High-side control register 0x5C 32 read-write 0x0 0xffffffff HS1_CYC_EN High-side 1 switch enable for cyclic sense 2 2 read-write DISABLE Disabled 0 ENABLE Enabled 1 HS2_CYC_EN High-side 2 switch enable for cyclic sense 10 10 read-write DISABLE Disabled 0 ENABLE Enabled 1 LIN_WAKE_EN LIN wake enable register 0x50 32 read-write 0x0 0xffffffff LIN_EN Lin wake enable 7 7 read-write DISABLE Disabled 0 ENABLE Enabled 1 MON_CNF1 Settings monitor 1-4 register 0x34 32 read-write 0x47474747 0xffffffff MON1_EN MON1 enable 0 0 read-write DISABLE MON1 disabled 0 ENABLE MON1 enabled 1 MON1_FALL MON1 wake-up on falling edge enable 1 1 read-write DISABLE Wake-up disabled 0 ENABLE Wake-up enabled 1 MON1_RISE MON1 wake-up on rising edge enable 2 2 read-write DISABLE Wake-up disabled 0 ENABLE Wake-up enabled 1 MON1_CYC MON1 for cycle sense enable 3 3 read-write DISABLE Cycle sense disabled 0 ENABLE Cycle sense enabled 1 MON1_PD Pull-down current source for MON1 input enable 4 4 read-write DISABLE Pull-down source disabled 0 ENABLE Pull-down source enabled 1 MON1_PU Pull-up current source for MON1 input enable 5 5 read-write DISABLE Pull-up source disabled 0 ENABLE Pull-up source enabled 1 MON1_STS MON1 status input 7 7 read-only Low_status MON input has low status 0 High_status MON input has high status 1 MON2_EN MON2 enable 8 8 read-write DISABLE MON2 disabled 0 Enabled MON2 enabled 1 MON2_FALL MON2 wake-up on falling edge enable 9 9 read-write DISABLE Wake-up disabled 0 ENABLE Wake-up enabled 1 MON2_RISE MON2 wake-up on rising edge enable 10 10 read-write DISABLE Wake-up disabled 0 ENABLE Wake-up enabled 1 MON2_CYC MON2 for cycle sense enable 11 11 read-write DISABLE Cycle sense disabled 0 ENABLE Cycle sense enabled 1 MON2_PD Pull-down current source for MON2 Input enable 12 12 read-write DISABLE Pull-down source disabled 0 ENABLE Pull-down source enabled 1 MON2_PU Pull-up current source for MON2 input enable 13 13 read-write DISABLE Pull-up source disabled 0 ENABLE Pull-up source enabled 1 MON2_STS MON2 status input 15 15 read-only Low_status MON input has low status 0 High_status MON input has high status 1 MON3_EN MON3 enable 16 16 read-write DISABLE MON3 disabled 0 ENABLE MON3 enabled 1 MON3_FALL MON3 wake-up on falling edge enable 17 17 read-write DISABLE Wake-up disabled 0 ENABLE Wake-up enabled 1 MON3_RISE MON3 wake-up on rising edge enable 18 18 read-write DISABLE Wake-up disabled 0 ENABLE Wake-up enabled 1 MON3_CYC MON3 for cycle sense enable 19 19 read-write DISABLE Cycle sense disabled 0 ENABLE Cycle sense enabled 1 MON3_PD Pull-down current source for MON3 input enable 20 20 read-write DISABLE Pull-down source disabled 0 ENABLE Pull-down source enabled 1 MON3_PU Pull-up current source for MON3 Input enable 21 21 read-write DISABLE Pull-up source disabled 0 ENABLE Pull-up source enabled 1 MON3_STS MON3 Status Input 23 23 read-only Low_status MON input has low status 0 High_status MON input has high status 1 MON4_EN MON4 Enable 24 24 read-write DISABLE MON4 disabled 0 ENABLE MON4 enabled 1 MON4_FALL MON4 wake-up on falling edge enable 25 25 read-write DISABLE Wake-up disabled 0 ENABLE Wake-up enabled 1 MON4_RISE MON4 wake-up on rising edge enable 26 26 read-write DISABLE Wake-up disabled 0 Enabled Wake-up enabled 1 MON4_CYC MON4 for cycle sense enable 27 27 read-write DISABLE Cycle sense disabled 0 ENABLE Cycle sense enabled 1 MON4_PD Pull-down current source for MON4 input enable 28 28 read-write DISABLE Pull-down source disabled 0 ENABLE Pull-down source enabled 1 MON4_PU Pull-up current source for MON4 input enable 29 29 read-write DISABLE Pull-up source disabled 0 ENABLE Pull-up source enabled 1 MON4_STS MON4 status input 31 31 read-only Low_status MON input has low status 0 High_status MON input has high status 1 MON_CNF2 Settings monitor 5 register 0x38 32 read-write 0x47 0xffffffff MON5_EN MON5 enable 0 0 read-write DISABLE MON5 disabled 0 ENABLE MON5 enabled 1 MON5_FALL MON5 wake-up on falling edge enable 1 1 read-write DISABLE Wake-up disabled 0 ENABLE Wake-up enabled 1 MON5_RISE MON5 wake-up on rising edge enable 2 2 read-write DISABLE Wake-up disabled 0 ENABLE Wake-up enabled 1 MON5_CYC MON5 for cycle sense enable 3 3 read-write DISABLE Cycle sense disabled 0 ENABLE Cycle sense enabled 1 MON5_PD Pull-down current source for MON5 input enable 4 4 read-write DISABLE Pull-down source disabled 0 ENABLE Pull-down source enabled 1 MON5_PU Pull-up current source for MON5 input enable 5 5 read-write DISABLE Pull-up source disabled 0 ENABLE Pull-up source enabled 1 MON5_STS MON5 status input 7 7 read-only Low_status MON input has low status 0 High_status MON input has high status 1 RESET_STS Reset status register 0x10 32 read-write 0x0 0xffffffff SYS_FAIL Flag which indicates a reset caused by a system fail reported in the corresponding fail register 0 0 read-write No_reset No reset caused by system fail executed 0 Reset Reset caused by system fail executed 1 PMU_WAKE Flag which indicates a reset caused by stop-exit 1 1 read-write No_reset No reset caused by stop-exit executed 0 Reset Reset caused by stop-exit executed 1 PMU_SleepEX Flag which indicates a reset caused by sleep-exit 2 2 read-write No_reset No reset caused by sleep-exit executed 0 Reset Reset caused by sleep-exit executed 1 PMU_LPR Low priority resets 3 3 read-write Low_priority_reset Low priority-reset executed 0 Low_priority Low priority executed 1 PMU_ClkWDT Clock watchdog (CLKWDT) reset flag 4 4 read-write No_reset Noclock watchdog reset executed 0 Reset Clock watchdog reset executed 1 PMU_ExtWDT External watchdog (WDT1) reset flag 5 5 read-write No_reset No external watchdog reset executed 0 Reset External watchdog reset executed 1 PMU_PIN PIN-reset flag 6 6 read-write No_reset No PIN-reset executed 0 Reset PIN-reset executed 1 PMU_VS_POR Power-on reset flag 7 7 read-write No_reset No power-on reset executed 0 Reset Power-on reset executed 1 PMU_SOFT Soft-reset flag 9 9 read-write No_reset No soft-reset executed 0 Reset Soft-reset executed 1 LOCKUP Lockup-reset flag 10 10 read-write No_reset No lockup-reset executed 0 Reset Lockup-reset executed 1 SLEEP PMU sleep behavior register 0x20 32 read-write 0x370004 0xffffffff WAKE_W_RST Wake-up with reset execution 0 0 read-write Without_reset_execution Stop-exit without reset execution 0 With_reset_execution Stop-exit with reset execution 1 EN_0V9_N Enables the reduction of the VDDC regulator output to reduced voltage during stop mode 1 1 read-write ENABLE Output voltage reduction enabled 0 DISABLE Output voltage reduction disabled 1 CYC_WAKE_EN Enabling cyclic wake 2 2 read-write DISABLE Cyclic wake disabled 0 ENABLE Cyclic wake enabled 1 CYC_SENSE_EN Enabling cyclic sense 3 3 read-write DISABLE Cyclic sense disabled 0 ENABLE Cyclic sense enabled 1 CYC_SENSE_M03 Mantissa 8 11 read-write Mantissa_value_1 Mantissa value is 1 0 Mantissa_value_16 Mantissa value is 16 15 CYC_SENSE_E01 Exponent 12 13 read-write Exponent_value_0 Exponent value is 0 0 Exponent_value_1 Exponent value is 1 1 Exponent_value_2 Exponent value is 2 2 Exponent_value_3 Exponent value is 3 3 CYC_WAKE_M03 Mantissa 16 19 read-write Mantissa_value_1 Mantissa value is 1 0 Mantissa_value_16 Mantissa value is 16 15 CYC_WAKE_E01 Exponent 20 21 read-write Exponent_value_0 Exponent value is 0 0 Exponent_value_1 Exponent value is 1 1 Exponent_value_2 Exponent value is 2 2 Exponent_value_3 Exponent value is 3 3 CYC_SENSE_S_DEL Sample delay in cyclic sense mode 24 26 read-write Delay_time_0 Is 10 us 0 Delay_time_1 Is 20 us 1 Delay_time_2 Is 30 us 2 Delay_time_3 Is 40 us 3 Delay_time_4 Is 60 us 4 Delay_time_5 Is 80 us 5 Delay_time_6 Is 100 us 6 Delay_time_7 Is 150 us 7 SUPPLY_STS Voltage reg status register 0x8 32 read-write 0x0 0xffffffff PMU_1V5_OVERVOLT Overvoltage at VDDC regulator 0 0 read-only No_overvoltage No overvoltage 0 Overvoltage Overvoltage 1 PMU_1V5_OVERLOAD Overload at VDDC regulator 1 1 read-only No_overload No overload 0 Overload Overload 1 PMU_1V5_FAIL_EN Enabling of VDDC status information as interrupt source 2 2 read-write No_interrupts No interrupts are generated 0 Interrupts Interrupts are generated 1 PMU_5V_OVERVOLT Overvoltage at VDDP regulator 4 4 read-only No_overvoltage No overvoltage 0 Overvoltage Overvoltage 1 PMU_5V_OVERLOAD Overload at VDDP regulator 5 5 read-only No_overload No overload 0 Overload Overload 1 PMU_5V_FAIL_EN Enabling of VDDP status information as interrupt source 6 6 read-write No_interrupts No interrupts are generated 0 Interrupts Interrupts are generated 1 VDDEXT_CTRL VDDEXT control register 0xC 32 read-write 0x0 0xffffffff VDDEXT_ENABLE VDDEXT supply enable 0 0 read-write DISABLE VDDEXT supply disabled 0 ENABLE VDDEXT supply enabled 1 VDDEXT_CYC_EN VDDEXT supply for cyclic sense enable 1 1 read-write DISABLE VDDEXT for cyclic sense disable 0 ENABLE VDDEXT for cyclic sense enable 1 VDDEXT_FAIL_EN Enabling of VDDEXT supply status information as interrupt source 2 2 read-write DISABLE VDDEXT fail interrupts are disabled 0 ENABLE VDDEXT fail Interrupts are enabled 1 VDDEXT_OT_IS VDDEXT supply overtemperature interrupt status 3 3 read-only No_overtemperature VDDEXT no overtemperature condition 0 Overtemperature VDDEXT overtemperature condition 1 VDDEXT_UV_IS VDDEXT supply undervoltage interrupt status 4 4 read-only Not_in_undervoltage VDDEXT not in undervoltage condition 0 In_undervoltage VDDEXT in undervoltage condition 1 VDDEXT_OT_STS VDDEXT supply overtemperature status 5 5 read-only No_overtemperature VDDEXT not in overtemperature condition 0 Overtemperature VDDEXT in overtemperature condition 1 VDDEXT_OT VDDEXT supply overtemperature 6 6 read-only No_overtemperature VDDEXT not in overtemperature condition 0 Overtemperature VDDEXT in overtemperature condition 1 VDDEXT_STABLE VDDEXT supply stable 7 7 read-only Not_stable VDDEXT not in stable condition 0 Stable VDDEXT in stable condition 1 VDDEXT_OT_ISC VDDEXT supply overtemperature interrupt status clear 11 11 write-only Not_cleared VDDEXTovertemperature not cleared 0 Cleared VDDEXTovertemperature cleared 1 VDDEXT_UV_ISC VDDEXT supply undervoltage interrupt status clear 12 12 write-only Not_cleared VDDEXT undervoltage not cleared 0 Cleared VDDEXT undervoltage cleared 1 VDDEXT_OT_SC VDDEXT supply overtemperature status clear 13 13 write-only Status_not_cleared VDDEXT overtemperature status not cleared 0 Status_cleared VDDEXT overtemperature status cleared 1 WAKE_CNF_GPIO1 Wake configuration GPIO port 1 register 0xCC 32 read-write 0x0 0xffffffff RI_0 Port 1_0 wake-up on rising edge enable 0 0 read-write DISABLE Wake-up disabled 0 ENABLE Wake-up enabled 1 RI_1 Port 1_1 wake-up on rising edge enable 1 1 read-write DISABLE Wake-up disabled 0 ENABLE Wake-up enabled 1 RI_2 Port 1_2 wake-up on rising edge enable 2 2 read-write DISABLE Wake-up disabled 0 ENABLE Wake-up enabled 1 RI_4 Port 1_4 wake-up on rising edge enable 4 4 read-write DISABLE Wake-up disabled 0 ENABLE Wake-up enabled 1 FA_0 Port 1_0 wake-up on falling edge enable 8 8 read-write DISABLE Wake-up disabled 0 ENABLE Wake-up enabled 1 FA_1 Port 1_1 wake-up on falling edge enable 9 9 read-write DISABLE Wake-up disabled 0 ENABLE Wake-up enabled 1 FA_2 Port 1_2 wake-up on falling edge enable 10 10 read-write DISABLE Wake-up disabled 0 ENABLE Wake-up enabled 1 FA_4 Port 1_4 wake-up on falling edge enable 12 12 read-write DISABLE Wake-up disabled 0 ENABLE Wake-up enabled 1 CYC_0 GPIO1_0 input for cycle sense enable 16 16 read-write DISABLE Input for cycle sense disabled 0 ENABLE Input for cycle sense enabled 1 CYC_1 GPIO1_1 input for cycle sense enable 17 17 read-write DISABLE Input for cycle sense disabled 0 ENABLE Input for cycle sense enabled 1 CYC_2 GPIO1_2 input for cycle sense enable 18 18 read-write DISABLE Input for cycle sense disabled 0 ENABLE Input for cycle sense enabled 1 CYC_4 GPIO1_4 input for cycle sense enable 20 20 read-write DISABLE Input for cycle sense disabled 0 ENABLE Input for cycle sense enabled 1 WAKE_STATUS Main wake status register 0x0 32 read-only 0x0 0xffffffff LIN_WAKE Wake-up via LIN- Message 0 0 read-only No_wake_up No wake-up occurred 0 Wake_up Wake-up occurred 1 MON Wake-up via MON which is a logical OR combination of all Wake_STS_MON bits 1 1 read-only No_wake_up No wake-up occurred 0 Wake_up Wake-up occurred 1 GPIO1 Wake-up via GPIO1 which is a logical OR combination of all Wake_STS_GPIO1 bits 3 3 read-only No_wake_up No wake-up occurred 0 Wake_up Wake-up occurred 1 CYC_WAKE Wake-up caused by cyclic wake 4 4 read-only No_wake_up No wake-up occurred 0 Wake_up Wake-up occurred 1 FAIL Wake-up after VDDEXT fail 5 5 read-only No_wake_up No wake-up occurred 0 Wake_up Wake-up occurred 1 MON1_WAKE_STS Status of MON1 8 8 read-only No_wake_up No wake-up detected 0 Wake_up Wake-up detected 1 MON2_WAKE_STS Status of MON2 9 9 read-only No_wake_up No wake-up detected 0 Wake_up Wake-up detected 1 MON3_WAKE_STS Status of MON3 10 10 read-only No_wake_up No wake-up detected 0 Wake_up Wake-up detected 1 MON4_WAKE_STS Status of MON4 11 11 read-only No_wake_up No wake-up detected 0 Wake_up Wake-up detected 1 MON5_WAKE_STS Status of MON5 12 12 read-only No_wake_up No wake-up detected 0 Wake_up Wake-up detected 1 VDDEXT_OT Wake VDDEXT overtemperature 17 17 read-only No_wake_up No wake-up detected 0 Wake_up Wake-up detected 1 VDDEXT_UV Wake VDDEXT undervoltage 18 18 read-only No_wake_up No wake-up detected 0 Wake_up Wake-up detected 1 WFS WFS system fail register 0x70 32 read-only 0x0 0xffffffff SUPP_SHORT Supply short 0 0 read-only Main_supply_ok VDDP or VDDC are in expected range 0 Main_supply_short VDDP or VDDC do not have stable operating point 1 PMU_1V5_OVL VDDC overload flag 2 2 read-only No_overload VDDC ok 0 Overload Hall VDDC overload 1 PMU_5V_OVL VDDP overload flag 3 3 read-only No_overload VDDP ok 0 Overload VDDP overload 1 SYS_OT System overtemperature indication flag 5 5 read-only NORMAL Normal operation 0 OT Overtemperature 1 WDT1_SEQ_FAIL External watchdog (WDT1) sequential fail 6 6 read-only No_fail No fail, system working properly 0 Sequential_watchdog_fail 5 consecutive watchdog fails 1 LP_CLKWD LP_CLKWD 7 7 read-only NORMAL Normal operation 0 FAIL LP_CLK clock failure 1 PORT 100 Ports registers PORT 0x48028000 0 0x2000 registers P0_ALTSEL0 Port 0 alternate select 0 register 0x14 32 read-write 0x0 0xffffffff PP0 Normal GPIO or alternate select 1, 2 or 3 (depends on bits P0_ALTSEL0.PPx and P0_ALTSEL1.PPx) 0 0 read-write Const_0 Const_0 0 Const_1 Const_1 1 PP1 Normal GPIO or alternate select 1, 2 or 3 (depends on bits P0_ALTSEL0.PPx and P0_ALTSEL1.PPx) 1 1 read-write Const_0 Const_0 0 Const_1 Const_1 1 PP2 Normal GPIO or alternate select 1, 2 or 3 (depends on bits P0_ALTSEL0.PPx and P0_ALTSEL1.PPx) 2 2 read-write Const_0 Const_0 0 Const_1 Const_1 1 PP3 Normal GPIO or alternate select 1, 2 or 3 (depends on bits P0_ALTSEL0.PPx and P0_ALTSEL1.PPx) 3 3 read-write Const_0 Const_0 0 Const_1 Const_1 1 PP4 Normal GPIO or alternate select 1, 2 or 3 (depends on bits P0_ALTSEL0.PPx and P0_ALTSEL1.PPx) 4 4 read-write Const_0 Const_0 0 Const_1 Const_1 1 PP5 Normal GPIO or alternate select 1, 2 or 3 (depends on bits P0_ALTSEL0.PPx and P0_ALTSEL1.PPx) 5 5 read-write Const_0 Const_0 0 Const_1 Const_1 1 P0_ALTSEL1 Port 0 alternate select 1 register 0x18 32 read-write 0x0 0xffffffff PP0 Normal GPIO or alternate select 1, 2 or 3 (depends on bits P0_ALTSEL0.PPx and P0_ALTSEL1.PPx) 0 0 read-write Const_0 Const_0 0 Const_1 Const_1 1 PP1 Normal GPIO or alternate select 1, 2 or 3 (depends on bits P0_ALTSEL0.PPx and P0_ALTSEL1.PPx) 1 1 read-write Const_0 Const_0 0 Const_1 Const_1 1 PP2 Normal GPIO or alternate select 1, 2 or 3 (depends on bits P0_ALTSEL0.PPx and P0_ALTSEL1.PPx) 2 2 read-write Const_0 Const_0 0 Const_1 Const_1 1 PP3 Normal GPIO or alternate select 1, 2 or 3 (depends on bits P0_ALTSEL0.PPx and P0_ALTSEL1.PPx) 3 3 read-write Const_0 Const_0 0 Const_1 Const_1 1 PP4 Normal GPIO or alternate select 1, 2 or 3 (depends on bits P0_ALTSEL0.PPx and P0_ALTSEL1.PPx) 4 4 read-write Const_0 Const_0 0 Const_1 Const_1 1 PP5 Normal GPIO or alternate select 1, 2 or 3 (depends on bits P0_ALTSEL0.PPx and P0_ALTSEL1.PPx) 5 5 read-write Const_0 Const_0 0 Const_1 Const_1 1 P0_DATA Port 0 data register 0x0 32 read-write 0x0 0xffffff00 PP0 Port 0 pin 0 data value 0 0 read-write 0 Port 0 pin 0 data value = 0 0 1 Port 0 pin 0 data value = 1 1 PP1 Port 0 pin 1 data value 1 1 read-write 0 Port 0 pin 1 data value = 0 0 1 Port 0 pin 1 data value = 1 1 PP2 Port 0 pin 2 data value 2 2 read-write 0 Port 0 pin 2 data value = 0 0 1 Port 0 pin 2 data value = 1 1 PP3 Port 0 pin 3 data value 3 3 read-write 0 Port 0 pin 3 data value = 0 0 1 Port 0 pin 3 data value = 1 1 PP4 Port 0 pin 4 data value 4 4 read-write 0 Port 0 pin 4 data value = 0 0 1 Port 0 pin 4 data value = 1 1 PP5 Port 0 pin 5 data value 5 5 read-write 0 Port 0 pin 5 data value = 0 0 1 Port 0 pin 5 data value = 1 1 PP0_STS Port 0 pin 0 data value (read back of port data when IO is configured as output) 16 16 read-only 0 Port 0 pin 0 data value = 0 0 1 Port 0 pin 0 data value = 1 1 PP1_STS Port 0 pin 1 data value (read back of port data when IO is configured as output) 17 17 read-only 0 Port 0 pin 1 data value = 0 0 1 Port 0 pin 1 data value = 1 1 PP2_STS Port 0 pin 2 data value (read back of port data when IO is configured as output) 18 18 read-only 0 Port 0 pin 2 data value = 0 0 1 Port 0 pin 2 data value = 1 1 PP3_STS Port 0 pin 3 data value (read back of port data when IO is configured as output) 19 19 read-only 0 Port 0 pin 3 data value = 0 0 1 Port 0 pin 3 data value = 1 1 PP4_STS Port 0 pin 4 data value (read back of port data when IO is configured as output) 20 20 read-only 0 Port 0 pin 4 data value = 0 0 1 Port 0 pin 4 data value = 1 1 PP5_STS Port 0 pin 5 data value (read back of port data when IO is configured as output) 21 21 read-only 0 Port 0 pin 5 data value = 0 0 1 Port 0 pin 5 data value = 1 1 P0_DIR Port 0 direction register 0x4 32 read-write 0x0 0xffffffff PP0 Port 0 pin 0 direction control 0 0 read-write 0 Direction is set to input (default) 0 1 Direction is set to output 1 PP1 Port 0 pin 1 direction control 1 1 read-write 0 Direction is set to input (default) 0 1 Direction is set to output 1 PP2 Port 0 pin 2 direction control 2 2 read-write 0 Direction is set to input (default) 0 1 Direction is set to output 1 PP3 Port 0 pin 3 direction control 3 3 read-write 0 Direction is set to input (default) 0 1 Direction is set to output 1 PP4 Port 0 pin 4 direction control 4 4 read-write 0 Direction is set to input (default) 0 1 Direction is set to output 1 PP5 Port 0 pin 5 direction control 5 5 read-write 0 Direction is set to input (default) 0 1 Direction is set to output 1 PP0_INEN Port 0 pin 0 input Schmitt trigger enable (only valid if IO is configured as output) 16 16 read-write 0 Schmitt trigger is disabled (default) 0 1 Schmitt trigger is enabled 1 PP1_INEN Port 0 pin 1 input Schmitt trigger enable (only valid if IO is configured as output) 17 17 read-write 0 Schmitt trigger is disabled (default) 0 1 Schmitt trigger is enabled 1 PP2_INEN Port 0 pin 2 input Schmitt trigger enable (only valid if IO is configured as output) 18 18 read-write 0 Schmitt trigger is disabled (default) 0 1 Schmitt trigger is enabled 1 PP3_INEN Port 0 pin 3 input Schmitt trigger enable (only valid if IO is configured as output) 19 19 read-write 0 Schmitt trigger is disabled (default) 0 1 Schmitt trigger is enabled 1 PP4_INEN Port 0 pin 4 input Schmitt trigger enable (only valid if IO is configured as output) 20 20 read-write 0 Schmitt trigger is disabled (default) 0 1 Schmitt trigger is enabled 1 PP5_INEN Port 0 pin 5 input Schmitt trigger enable (only valid if IO is configured as output) 21 21 read-write 0 Schmitt trigger is disabled (default) 0 1 Schmitt trigger is enabled 1 P0_OD Port 0 open drain control register 0x8 32 read-write 0x0 0xffffffff PP0 Port 0 pin 0 open drain mode 0 0 read-write Normal_mode Output is actively driven for 0 and 1 state (default) 0 Open_drain_mode Output is actively driven only for 0 state 1 PP1 Port 0 pin 1 open drain mode 1 1 read-write Normal_mode Output is actively driven for 0 and 1 state (default) 0 Open_drain_mode Output is actively driven only for 0 state 1 PP2 Port 0 pin 2 open drain mode 2 2 read-write Normal_mode Output is actively driven for 0 and 1 state (default) 0 Open_drain_mode Output is actively driven only for 0 state 1 PP3 Port 0 pin 3 open drain mode 3 3 read-write Normal_mode Output is actively driven for 0 and 1 state (default) 0 Open_drain_mode Output is actively driven only for 0 state 1 PP4 Port 0 pin 4 open drain mode 4 4 read-write Normal_mode Output is actively driven for 0 and 1 state (default) 0 Open_drain_mode Output is actively driven only for 0 state 1 PP5 Port 0 pin 5 open drain mode 5 5 read-write Normal_mode Output is actively driven for 0 and 1 state (default) 0 Open_drain_mode Output is actively driven only for 0 state 1 P0_PUDEN Port 0 pull-up/pull-down enable register 0x10 32 read-write 0x3f 0xffffffff PP0 Pull-up/pull-down enable at port 0 bit 0 0 0 read-write Disabled Pull-up or pull-down device is disabled 0 Enabled Pull-up or pull-down device is enabled (default) 1 PP1 Pull-up/pull-down enable at port 0 bit 1 1 1 read-write Disabled Pull-up or pull-down device is disabled 0 Enabled Pull-up or pull-down device is enabled (default) 1 PP2 Pull-up/pull-down enable at port 0 bit 2 2 2 read-write Disabled Pull-up or pull-down device is disabled 0 Enabled Pull-up or pull-down device is enabled (default) 1 PP3 Pull-up/pull-down enable at port 0 bit 3 3 3 read-write Disabled Pull-up or pull-down device is disabled 0 Enabled Pull-up or pull-down device is enabled (default) 1 PP4 Pull-up/pull-down enable at port 0 bit 4 4 4 read-write Disabled Pull-up or pull-down device is disabled 0 Enabled Pull-up or pull-down device is enabled (default) 1 PP5 Pull-up/pull-down enable at port 0 bit 5 5 5 read-write Disabled Pull-up or pull-down device is disabled 0 Enabled Pull-up or pull-down device is enabled (default) 1 P0_PUDSEL Port 0 pull-up/pull-down select register 0xC 32 read-write 0x3b 0xffffffff PP0 Pull-up/pull-down select port 0 bit 0 0 0 read-write Pull_down Pull-down device is selected 0 Pull_up Pull-up device is selected (default) 1 PP1 Pull-up/pull-down select port 0 bit 1 1 1 read-write Pull_down Pull-down device is selected 0 Pull_up Pull-up device is selected (default) 1 PP2 Pull-up/pull-down select port 0 bit 2 2 2 read-write Pull_down Pull-down device is selected 0 Pull_up Pull-up device is selected (default) 1 PP3 Pull-up/pull-down select port 0 bit 3 3 3 read-write Pull_down Pull-down device is selected 0 Pull_up Pull-up device is selected (default) 1 PP4 Pull-up/pull-down select port 0 bit 4 4 4 read-write Pull_down Pull-down device is selected 0 Pull_up Pull-up device is selected (default) 1 PP5 Pull-up/pull-down select port 0 bit 5 5 5 read-write Pull_down Pull-down device is selected 0 Pull_up Pull-up device is selected (default) 1 P1_ALTSEL0 Port 1 alternate select 0 register 0x34 32 read-write 0x0 0xffffffff PP0 Normal GPIO or alternate select 1, 2 or 3 (depends on bits P1_ALTSEL0.PPx and P1_ALTSEL1.PPx) 0 0 read-write Const_0 Const_0 0 Const_1 Const_1 1 PP1 Normal GPIO or alternate select 1, 2 or 3 (depends on bits P1_ALTSEL0.PPx and P1_ALTSEL1.PPx) 1 1 read-write Const_0 Const_0 0 Const_1 Const_1 1 PP2 Normal GPIO or alternate select 1, 2 or 3 (depends on bits P1_ALTSEL0.PPx and P1_ALTSEL1.PPx) 2 2 read-write Const_0 Const_0 0 Const_1 Const_1 1 PP4 Normal GPIO or alternate select 1, 2 or 3 (depends on bits P1_ALTSEL0.PPx and P1_ALTSEL1.PPx) 4 4 read-write Const_0 Const_0 0 Const_1 Const_1 1 P1_ALTSEL1 Port 1 alternate select 1 register 0x38 32 read-write 0x0 0xffffffff PP0 PP0 0 0 read-write Const_0 Const_0 0 Const_1 Const_1 1 PP1 PP1 1 1 read-write Const_0 Const_0 0 Const_1 Const_1 1 PP2 PP2 2 2 read-write Const_0 Const_0 0 Const_1 Const_1 1 PP4 PP4 4 4 read-write Const_0 Const_0 0 Const_1 Const_1 1 P1_DATA Port 1 data register 0x20 32 read-write 0x0 0xffffff00 PP0 Port 1 pin 0 data value 0 0 read-write 0 Port 1 pin 0 data value = 0 0 1 Port 1 pin 0 data value = 1 1 PP1 Port 1 pin 1 data value 1 1 read-write 0 Port 1 pin 1 data value = 0 0 1 Port 1 pin 1 data value = 1 1 PP2 Port 1 pin 2 data value 2 2 read-write 0 Port 1 pin 2 data value = 0 0 1 Port 1 pin 2 data value = 1 1 PP4 Port 1 pin 4 data value 4 4 read-write 0 Port 1 pin 4 data value = 0 0 1 Port 1 pin 4 data value = 1 1 PP0_STS Port 1 pin 0 data value (read back of port data when IO is configured as output) 16 16 read-write 0 Port 1 pin 0 data value = 0 0 1 Port 1 pin 0 data value = 1 1 PP1_STS Port 1 pin 1 data value (read back of port data when IO is configured as output) 17 17 read-write 0 Port 1 pin 1 data value = 0 0 1 Port 1 pin 1 data value = 1 1 PP2_STS Port 1 pin 2 data value (read back of port data when IO is configured as output) 18 18 read-write 0 Port 1 pin 2 data value = 0 0 1 Port 1 pin 2 data value = 1 1 PP4_STS Port 1 pin 4 data value (read back of port data when IO is configured as output) 20 20 read-write 0 Port 1 pin 4 data value = 0 0 1 Port 1 pin 4 data value = 1 1 P1_DIR Port 1 direction register 0x24 32 read-write 0x0 0xffffffff PP0 Port 1 pin 0 direction control 0 0 read-write 0 Direction is set to input (default) 0 1 Direction is set to output 1 PP1 Port 1 pin 1 direction control 1 1 read-write 0 Direction is set to input (default) 0 1 Direction is set to output 1 PP2 Port 1 pin 2 direction control 2 2 read-write 0 Direction is set to input (default) 0 1 Direction is set to output 1 PP4 Port 1 pin 4 direction control 4 4 read-write 0 Direction is set to input (default) 0 1 Direction is set to output 1 PP0_INEN Port 1 pin 0 input Schmitt trigger enable (only valid if IO is configured as output) 16 16 read-write 0 Schmitt trigger is disabled (default) 0 1 Schmitt trigger is enabled 1 PP1_INEN Port 1 pin 1 input Schmitt trigger enable (only valid if IO is configured as output) 17 17 read-write 0 Schmitt trigger is disabled (default) 0 1 Schmitt trigger is enabled 1 PP2_INEN Port 1 pin 2 input Schmitt trigger enable (only valid if IO is configured as output) 18 18 read-write 0 Schmitt trigger is disabled (default) 0 1 Schmitt trigger is enabled 1 PP3_INEN Port 1 pin 4 input Schmitt trigger enable (only valid if IO is configured as output) 20 20 read-write 0 Schmitt trigger is disabled (default) 0 1 Schmitt trigger is enabled 1 P1_OD Port 1 open drain control register 0x28 32 read-write 0x0 0xffffffff PP0 Port 1 pin 0 open drain mode 0 0 read-write Normal_mode Output is actively driven for 0 and 1 state (default) 0 Open_drain_mode Output is actively driven only for 0 state 1 PP1 Port 1 pin 1 open drain mode 1 1 read-write Normal_mode Output is actively driven for 0 and 1 state (default) 0 Open_drain_mode Output is actively driven only for 0 state 1 PP2 Port 1 pin 2 open drain mode 2 2 read-write Normal_mode Output is actively driven for 0 and 1 state (default) 0 Open_drain_mode Output is actively driven only for 0 state 1 PP4 Port 1 pin 4 open drain mode 4 4 read-write Normal_mode Output is actively driven for 0 and 1 state (default) 0 Open_drain_mode Output is actively driven only for 0 state 1 P1_PUDEN Port 1 pull-up/pull-down enable register 0x30 32 read-write 0x0 0xffffffff PP0 Pull-up/pull-down enable at port 1 bit 0 0 0 read-write Disabled Pull-up or pull-down device is disabled 0 Enabled Pull-up or pull-down device is enabled (default) 1 PP1 Pull-up/pull-down enable at port 1 bit 1 1 1 read-write Disabled Pull-up or pull-down device is disabled 0 Enabled Pull-up or pull-down device is enabled (default) 1 PP2 Pull-up/pull-down enable at port 1 bit 2 2 2 read-write Disabled Pull-up or pull-down device is disabled 0 Enabled Pull-up or pull-down device is enabled (default) 1 PP4 Pull-up/pull-down enable at port 1 bit 4 4 4 read-write Disabled Pull-up or pull-down device is disabled 0 Enabled Pull-up or pull-down device is enabled (default) 1 P1_PUDSEL Port 1 pull-up/pull-down select register 0x2C 32 read-write 0x17 0xffffffff PP0 Pull-up/pull-down select port 1 bit 0 0 0 read-write Pull_down Pull-down device is selected 0 Pull_up Pull-up device is selected (default) 1 PP1 Pull-up/pull-down select port 1 bit 1 1 1 read-write Pull_down Pull-down device is selected 0 Pull_up Pull-up device is selected (default) 1 PP2 Pull-up/pull-down select port 1 bit 2 2 2 read-write Pull_down Pull-down device is selected 0 Pull_up Pull-up device is selected (default) 1 PP4 Pull-up/pull-down select port 1 bit 4 4 4 read-write Pull_down Pull-down device is selected 0 Pull_up Pull-up device is selected (default) 1 P2_DATA Port 2 data register 0x40 32 read-write 0x0 0xffffff00 PP0 Port 2 pin 0 data value 0 0 read-write 0 Port 2 pin 0 data value = 0 0 1 Port 2 pin 0 data value = 1 1 PP1 Port 2 pin 1 data value 1 1 read-write 0 Port 2 pin 1 data value = 0 0 1 Port 2 pin 1 data value = 1 1 PP2 Port 2 pin 2 data value 2 2 read-write 0 Port 2 pin 2 data value = 0 0 1 Port 2 pin 2 data value = 1 1 PP3 Port 2 pin 3 data value 3 3 read-write 0 Port 2 pin 3 data value = 0 0 1 Port 2 pin 3 data value = 1 1 PP4 Port 2 pin 4 data value 4 4 read-write 0 Port 2 pin 4 data value = 0 0 1 Port 2 pin 4 data value = 1 1 PP5 Port 2 pin 5 data value 5 5 read-write 0 Port 2 pin 5 data value = 0 0 1 Port 2 pin 5 data value = 1 1 PP6 Port 2 pin 6 data value 6 6 read-write 0 Port 2 pin 6 data value = 0 0 1 Port 2 pin 6 data value = 1 1 PP7 Port 2 pin 7 data value 7 7 read-write 0 Port 2 pin 7 data value = 0 0 1 Port 2 pin 7 data value = 1 1 P2_DIR Port 2 direction register 0x44 32 read-write 0x0 0xffffffff PP0 Port 2 pin 0 direction control 0 0 read-write 0 Direction is set to input (default) 0 1 Direction is set to output 1 PP1 Port 2 pin 1 direction control 1 1 read-write 0 Direction is set to input (default) 0 1 Direction is set to output 1 PP2 Port 2 pin 2 direction control 2 2 read-write 0 Direction is set to input (default) 0 1 Direction is set to output 1 PP3 Port 2 pin 3 direction control 3 3 read-write 0 Direction is set to input (default) 0 1 Direction is set to output 1 PP4 Port 2 pin 4 direction control 4 4 read-write 0 Direction is set to input (default) 0 1 Direction is set to output 1 PP5 Port 2 pin 5 direction control 5 5 read-write 0 Direction is set to input (default) 0 1 Direction is set to output 1 PP6 Port 2 pin 6 direction control 6 6 read-write 0 Direction is set to input (default) 0 1 Direction is set to output 1 PP7 Port 2 pin 7 direction control 7 7 read-write 0 Direction is set to input (default) 0 1 Direction is set to output 1 P2_PUDEN Port 2 pull-up/pull-down enable register 0x50 32 read-write 0x0 0xffffffff PP0 Pull-up/pull-down enable at port 2 bit 0 0 0 read-write Disabled Pull-up or pull-down device is disabled 0 Enabled Pull-up or pull-down device is enabled (default) 1 PP1 Pull-up/pull-down enable at port 2 bit 1 1 1 read-write Disabled Pull-up or pull-down device is disabled 0 Enabled Pull-up or pull-down device is enabled (default) 1 PP2 Pull-up/pull-down enable at port 2 bit 2 2 2 read-write Disabled Pull-up or pull-down device is disabled 0 Enabled Pull-up or pull-down device is enabled (default) 1 PP3 Pull-up/pull-down enable at port 2 bit 3 3 3 read-write Disabled Pull-up or pull-down device is disabled 0 Enabled Pull-up or pull-down device is enabled (default) 1 PP4 Pull-up/pull-down enable at port 2 bit 4 4 4 read-write Disabled Pull-up or pull-down device is disabled 0 Enabled Pull-up or pull-down device is enabled (default) 1 PP5 Pull-up/pull-down enable at port 2 bit 5 5 5 read-write Disabled Pull-up or pull-down device is disabled 0 Enabled Pull-up or pull-down device is enabled (default) 1 PP6 Pull-up/pull-down enable at port 2 bit 6 6 6 read-write Disabled Pull-up or pull-down device is disabled 0 Enabled Pull-up or pull-down device is enabled (default) 1 PP7 Pull-up/pull-down enable at port 2 bit 7 7 7 read-write Disabled Pull-up or pull-down device is disabled 0 Enabled Pull-up or pull-down device is enabled (default) 1 P2_PUDSEL Port 2 pull-up/pull-down select register 0x4C 32 read-write 0x0 0xffffffff PP0 Pull-up/pull-down select port 2 bit 0 0 0 read-write Pull_down Pull-down device is selected 0 Pull_up Pull-up device is selected (default) 1 PP1 Pull-up/pull-down select port 2 bit 1 1 1 read-write Pull_down Pull-down device is selected 0 Pull_up Pull-up device is selected (default) 1 PP2 Pull-up/pull-down select port 2 bit 2 2 2 read-write Pull_down Pull-down device is selected 0 Pull_up Pull-up device is selected (default) 1 PP3 Pull-up/pull-down select port 2 bit 3 3 3 read-write Pull_down Pull-down device is selected 0 Pull_up Pull-up device is selected (default) 1 PP4 Pull-up/pull-down select port 2 bit 4 4 4 read-write Pull_down Pull-down device is selected 0 Pull_up Pull-up device is selected (default) 1 PP5 Pull-up/pull-down select port 2 bit 5 5 5 read-write Pull_down Pull-down device is selected 0 Pull_up Pull-up device is selected (default) 1 PP6 Pull-up/pull-down select port 2 bit 6 6 6 read-write Pull_down Pull-down device is selected 0 Pull_up Pull-up device is selected (default) 1 PP7 Pull-up/pull-down select port 2 bit 7 7 7 read-write Pull_down Pull-down device is selected 0 Pull_up Pull-up device is selected (default) 1 SCU 100 System Control Unit - Digital Modules (SCU-DM) registers SCUDM 0x50005000 0 0x1000 registers ADC1_CLK ADC1 peripheral clock register 0x6C 32 read-write 0x0 0xffffffff ADC1_CLK_DIV ADC1 clock divider 0 3 read-write 10 Divide by {$n+1} 0 21 Divide by {$n+1} 1 32 Divide by {$n+1} 2 43 Divide by {$n+1} 3 54 Divide by {$n+1} 4 16 Divide by 16 6 DPP1_CLK_DIV ADC1 post processing clock divider 8 9 read-write 1 Divide by 1 0 2 Divide by 2 1 3 Divide by 3 2 4 Divide by 4 3 APCLK Analog peripheral clock register 0x58 32 read-write 0x0 0xffffffff APCLK1FAC Analog module clock factor 0 1 read-write 1 Divide by 1 0 2 Divide by 2 1 3 Divide by 3 2 4 Divide by 4 3 APCLK2FAC Slow down clock divider for TFILT_CLK generation 8 12 read-write 1 fSYS 0 2 fSYS/2 1 3 fSYS/3 2 4 fSYS/4 3 5 fSYS/5 4 6 fSYS/6 5 7 fSYS/7 6 8 fSYS/8 7 9 fSYS/9 8 10 fSYS/10 9 11 fSYS/11 10 12 fSYS/12 11 24 fSYS/24 30 32 fSYS/32 31 BGCLK_SEL Bandgap clock selection 24 24 read-write LP_CLK LP_CLK is selected 0 fSYS fSYS is selected 1 BGCLK_DIV Bandgap clock divider 25 25 read-write 2 Divide by 2 0 1 Divide by 1 1 APCLK_CTRL Analog peripheral clock control register 0x54 32 read-write 0x0 0xffffffff APCLK_SET Set and overtake flag for clock settings 0 0 read-write IGNORED Clock settings are ignored (previous values are held) 0 OVERTAKEN Clock settings are overtaken 1 CLKWDT_IE Clock watchdog interrupt enable 8 8 read-write DISABLED Interrupt disabled 0 ENABLED Interrupt enabled 1 APCLK_SCLR Analog peripheral clock status clear register 0x64 32 read-write 0x0 0xffffffff APCLK1SCLR Analog peripherals clock status clear 0 0 write-only APCLK2SCLR Analog peripherals clock status clear 8 8 write-only APCLK3SCLR Analog peripherals clock 3 status clear 16 16 write-only PLL_LOCK_SCLR PLL lock status clear 24 24 write-only APCLK_STS Analog peripheral clock status register 0x5C 32 read-only 0x0 0xffffffff APCLK1STS Analog peripherals clock status 0 1 read-only RANGE The MI_CLK clock is in the required range 0 HIGHER The MI_CLK clock exceeds the higher limit 1 LOWER The MI_CLK clock exceeds the lower limit 2 OUTSIDE The MI_CLK clock is not inside the specified limit 3 APCLK2STS Analog peripherals clock status 8 9 read-only RANGE The TFILT_CLK clock is in the required range 0 HIGHER The TFILT_CLK clock exceeds the higher limit 1 LOWER The TFILT_CLK clock exceeds the lower limit 2 OUTSIDE The TFILT_CLK clock is not inside the specified limit 3 APCLK3STS Loss of clock status 16 16 read-only NO_LOSS No loss of clock 0 LOSS Loss of lock occurred 1 PLL_LOCK PLL LOCK status 24 24 read-only NOT_LOCKED PLL has not locked 0 LOCKED PLL has locked 1 BCON1 Baud-rate control 1 register 0x88 32 read-write 0x0 0xffffffff BR1_R Baud-rate generator run control bit 0 0 read-write DISABLED Baud-rate generator disabled 0 ENABLED Baud-rate generator enabled 1 BR1_PRE Prescaler bit 1 3 read-write 1 fDIV = fPCLK 0 2 fDIV = fPCLK/2 1 4 fDIV = fPCLK/4 2 8 fDIV = fPCLK/8 3 16 fDIV = fPCLK/16 4 32 fDIV = fPCLK/32 5 BCON2 Baud-rate control 2 register 0x98 32 read-write 0x0 0xffffffff BR2_R Baud-rate generator run control bit 0 0 read-write DISABLED Baud-rate generator disabled 0 ENABLED Baud-rate generator enabled 1 BR2_PRE Prescaler bit 1 3 read-write 1 fDIV = fPCLK 0 2 fDIV = fPCLK/2 1 4 fDIV = fPCLK/4 2 8 fDIV = fPCLK/8 3 16 fDIV = fPCLK/16 4 32 fDIV = fPCLK/32 5 BG1 Baud-rate timer/reload 1 register 0x90 32 read-write 0x0 0xffffffff BG1_BR_VALUE Baud-rate timer/reload value UART1 0 10 read-write BYPASSED Baud-rate timer is bypassed 0 1 1 1 2 2 2 2046 2046 2046 2047 2047 2047 BG2 Baud-rate timer/reload 2 register 0xA0 32 read-write 0x0 0xffffffff BG2_BR_VALUE Baud-rate timer/reload value UART2 0 10 read-write BYPASSED Baud-rate timer is bypassed 0 1 1 1 2 2 2 2046 2046 2046 2047 2047 2047 BGL1 Baud-rate timer/reload, low byte 1 register 0x8C 32 read-write 0x0 0xffffffff BG1_FD_SEL Fractional divider selection 0 4 read-write BGL2 Baud-rate timer/reload, low byte 2 register 0x9C 32 read-write 0x0 0xffffffff BG2_FD_SEL Fractional divider selection 0 4 read-write CMCON1 Clock control 1 register 0x48 32 read-write 0x100 0xffffffff CLKREL Slow down clock divider for fCCLK generation 0 3 read-write 1 fSYS 0 2 fSYS/2 1 3 fSYS/3 2 4 fSYS/4 3 8 fSYS/8 4 16 fSYS/16 5 24 fSYS/24 6 32 fSYS/32 7 48 fSYS/48 8 64 fSYS/64 9 96 fSYS/96 10 128 fSYS/128 11 192 fSYS/192 12 256 fSYS/256 13 384 fSYS/384 14 512 fSYS/512 15 K2DIV PLL K2-divider 4 5 read-write 2 K2 = 2 0 3 K2 = 3 1 4 K2 = 4 2 5 K2 = 5 3 K1DIV PLL K1-divider 6 6 read-write 2 K1 = 2 0 1 K1 = 1 1 PDIV PLL PDIV-divider 8 9 read-write 4 4 0 5 5 (default) 1 6_1 6 2 6_2 6 3 CMCON2 Clock control 2 register 0x4C 32 read-write 0x0 0xffffffff PBA0CLKREL PBA0 clock divider 0 0 read-write 1 Divide by 1 0 2 Divide by 2 1 COCON Clock output control register 0xB4 32 read-write 0x0 0xffffffff COREL Clock output divider 0 3 read-write 1 fSYS 0 2 fSYS/2 1 3 fSYS/3 2 4 fSYS/4 3 6 fSYS/6 4 8 fSYS/8 5 10 fSYS/10 6 12 fSYS/12 7 14 fSYS/14 8 16 fSYS/16 9 18 fSYS/18 10 20 fSYS/20 11 24 fSYS/24 12 32 fSYS/32 13 36 fSYS/36 14 40 fSYS/40 15 COUTS0 Clock out source select bit 0 4 4 read-write OSCILLATOR Oscillator output frequency is selected 0 COREL Clock output frequency is chosen by the bit field COREL 1 TLEN Toggle latch enable 5 5 read-write DISABLED Toggle latch is disabled. Clock output frequency is chosen by the bit field COREL 0 ENABLED Toggle latch is enabled. Clock output frequency is half of the frequency that is chosen by the bit field COREL. The resulting output frequency has 50% duty cycle 1 COUTS1 Clock out source select bit 1 6 6 read-write fCCLK fCCLK is selected 0 COUTS0 Based on setting of COUTS0 1 EN CLKOUT enable 7 7 read-write NO_EXTERNAL No external clock signal is provided 0 EXTERNAL The configured external clock signal is provided 1 EDCCON Error detection and correction control register 0xD4 32 read-write 0x0 0xffffffff RIE RAM double bit ECC error interrupt enable 0 0 read-write false No NMI is generated when a double bit ECC error occurs reading RAM 0 true An NMI is generated when a double bit ECC error occurs reading RAM 1 NVMIE NVM double bit ECC error interrupt enable 2 2 read-write false No NMI is generated when a double bit ECC error occurs reading NVM 0 true An NMI is generated when a double bit ECC error occurs reading NVM 1 EDCSCLR Error detection and correction status clear register 0x10C 32 read-write 0x0 0xffffffff RDBEC RAM double bit error clear 0 0 write-only NOT_CLEARED A double bit error on RAM is not cleared 0 CLEARED A double bit error on RAM is cleared 1 NVMDBEC NVM double bit error clear 2 2 write-only NOT_CLEARED A double bit error on NVM is not cleared 0 CLEARED A double bit error on NVM is cleared 1 RSBEC RAM single bit error clear 4 4 write-only NOT_CLEARED A single bit error on RAM is not cleared 0 CLEARED A single bit error on RAM is cleared 1 EDCSTAT Error detection and correction status register 0xD8 32 read-only 0x0 0xffffffff RDBE RAM double bit error 0 0 read-only false No double bit error on RAM has occurred 0 true A double bit error on RAM has occurred 1 NVMDBE NVM double bit error 2 2 read-only false No double bit error on NVM has occurred 0 true A double bit error on NVM has occurred 1 RSBE RAM single bit error 4 4 read-only false No single bit error on RAM has occurred 0 true A single bit error on RAM has occurred 1 EMOP Emergency and program operation status register 0xCC 32 read-write 0x0 0xffffffff NVMPROP NVM program operation status bit 0 0 read-write NOT_STARTED No NVM program operation is started 0 STARTED NVM program operation is started 1 EMPROP Emergency program operation status bit 1 1 read-write NOT_STARTED No emergency program operation is started 0 STARTED Emergency program operation is started 1 EXICON0 External interrupt control 0 register 0x28 32 read-write 0x30 0xffffffff EXINT0 External interrupt 0 trigger select 0 1 read-write DISABLED Interrupt disabled 0 RISING Interrupt on rising edge 1 FALLING Interrupt on falling edge 2 BOTH Interrupt on both rising and falling edge 3 EXINT1 External interrupt 1 trigger select 2 3 read-write DISABLED Interrupt disabled 0 RISING Interrupt on rising edge 1 FALLING Interrupt on falling edge 2 BOTH Interrupt on both rising and falling edge 3 EXINT2 External interrupt 2 trigger select 4 5 read-write DISABLED Interrupt disabled 0 RISING Interrupt on rising edge 1 FALLING Interrupt on falling edge 2 BOTH Interrupt on both rising and falling edge 3 EXICON1 External interrupt control 1 register 0x2C 32 read-write 0x0 0xffffffff MON1 MON1 input trigger select 0 1 read-write DISABLED External interrupt MON is disabled 0 RISING Interrupt on rising edge 1 FALLING Interrupt on falling edge 2 BOTH Interrupt on both rising and falling edge 3 MON2 MON2 input trigger select 2 3 read-write DISABLED External interrupt MON is disabled 0 RISING Interrupt on rising edge 1 FALLING Interrupt on falling edge 2 BOTH Interrupt on both rising and falling edge 3 MON3 MON3 input trigger select 4 5 read-write DISABLED External interrupt MON is disabled 0 RISING Interrupt on rising edge 1 FALLING Interrupt on falling edge 2 BOTH Interrupt on both rising and falling edge 3 MON4 MON4 input trigger select 6 7 read-write DISABLED External interrupt MON is disabled 0 RISING Interrupt on rising edge 1 FALLING Interrupt on falling edge 2 BOTH Interrupt on both rising and falling edge 3 MON5 MON5 input trigger select 8 9 read-write DISABLED External interrupt MON is disabled 0 RISING Interrupt on rising edge 1 FALLING Interrupt on falling edge 2 BOTH Interrupt on both rising and falling edge 3 GPT12ICLR Timer and counter control/status clear register 0x180 32 read-write 0x0 0xffffffff GPT1T2C GPT module 1 Timer2 interrupt status 0 0 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 GPT1T3C GPT module 1 Timer3 interrupt status 1 1 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 GPT1T4C GPT module 1 Timer4 interrupt status 2 2 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 GPT2T5C GPT module 2 Timer5 interrupt status 3 3 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 GPT2T6C GPT module 2 Timer6 interrupt status 4 4 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 GPT12CRC GPT12 capture reload interrupt status 5 5 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 GPT12IEN General purpose timer 12 interrupt enable register 0x15C 32 read-write 0x0 0xffffffff T2IE GPT12 T2 interrupt enable 0 0 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 T3IE GPT12 T3 interrupt enable 1 1 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 T4IE GPT12 T4 interrupt enable 2 2 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 T5IE GPT12 T5 interrupt enable 3 3 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 T6IE GPT12 T6 interrupt enable 4 4 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 CRIE GPT12 capture and reload interrupt enable 5 5 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 GPT12IRC Timer and counter control/status register 0x160 32 read-only 0x0 0xffffffff GPT1T2 GPT module 1 Timer2 interrupt status 0 0 read-only NOT_OCCURRED No Timer2 interrupt has occurred 0 OCCURRED Timer2 interrupt has occurred 1 GPT1T3 GPT module 1 Timer3 interrupt status 1 1 read-only NOT_OCCURRED No Timer3 interrupt has occurred 0 OCCURRED Timer3 interrupt has occurred 1 GPT1T4 GPT module 1 Timer4 interrupt status 2 2 read-only NOT_OCCURRED No Timer4 interrupt has occurred 0 OCCURRED Timer4 interrupt has occurred 1 GPT2T5 GPT module 2 Timer5 interrupt status 3 3 read-only NOT_OCCURRED No Timer5 interrupt has occurred 0 OCCURRED Timer5 interrupt has occurred 1 GPT2T6 GPT module 2 Timer6 interrupt status 4 4 read-only NOT_OCCURRED No Timer6 interrupt has occurred 0 OCCURRED Timer6 interrupt has occurred 1 GPT12CR GPT12 capture reload interrupt status 5 5 read-only NOT_OCCURRED No capture reload interrupt has occurred 0 OCCURRED Capture reload interrupt has occurred 1 GPT12PISEL GPT12 peripheral input select register 0xD0 32 read-write 0x0 0xffffffff GPT12 GPT12 T3INB/T4IND input select 0 3 read-write CC60 CC60 0 CC61 CC61 1 CC62 CC62 2 T12_ZM T12 ZM 3 T12_PM T12 PM 4 T12_CM0 T12 CM0 5 T12_CM1 T12 CM1 6 T12_CM2 T12 CM2 7 T13_PM T13 PM 8 T13_ZM T13 ZM 9 T13_CM T13 CM 10 ANY Any pos or neg edge on CC60/61/62 11 TRIG_CONF CCU6 trigger Configuration 4 4 read-write ONE Trigger is just for one measurement (default) 0 NEXT Trigger is present until next input edge (selected by GPT12) \u2013 continuous measurement 1 GPT12_SEL CCU6 trigger configuration 5 5 read-write T21 CCU6_INT is triggered by Timer21 0 GPT12 CCU6_INT is triggered by GPT12PISEL.GPT12 1 ID Identity register 0xA8 32 read-write 0x80 0xffffffff VERID Version ID 0 2 read-write PRODID Product ID 3 7 read-only IEN0 Interrupt enable 0 register 0x1C 32 read-write 0x0 0xffffffff EA Global interrupt mask 31 31 read-write BLOCKED All pending interrupt requests (except NMI) are blocked from the core 0 NOT_BLOCKED Pending interrupt requests are not blocked from the core 1 IRCON0 Interrupt request 0 register 0x4 32 read-only 0x0 0xffffffff EXINT0R Interrupt flag for external interrupt 0x on rising edge 0 0 read-only NOT_OCCURED Interrupt on rising edge event has not occurred 0 OCCURED Interrupt on rising edge event has occurred 1 EXINT0F Interrupt flag for external interrupt 0x on falling edge 1 1 read-only NOT_OCCURED Interrupt on falling edge event has not occurred 0 OCCURED Interrupt on falling edge event has occurred 1 EXINT1R Interrupt flag for external interrupt 1x on rising edge 2 2 read-only NOT_OCCURED Interrupt on rising edge event has not occurred 0 OCCURED Interrupt on rising edge event has occurred 1 EXINT1F Interrupt flag for external interrupt 1x on falling edge 3 3 read-only NOT_OCCURED Interrupt on falling edge event has not occurred 0 OCCURED Interrupt on falling edge event has occurred 1 EXINT2R Interrupt flag for external interrupt 2x on rising edge 4 4 read-only NOT_OCCURED Interrupt on rising edge event has not occurred 0 OCCURED Interrupt on rising edge event has occurred 1 EXINT2F Interrupt flag for external interrupt 2x on falling edge 5 5 read-only NOT_OCCURED Interrupt on falling edge event has not occurred 0 OCCURED Interrupt on falling edge event has occurred 1 IRCON0CLR Interrupt request 0 clear register 0x178 32 read-write 0x0 0xffffffff EXINT0RC Interrupt flag for external interrupt 0x on rising edge 0 0 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 EXINT0FC Interrupt flag for external interrupt 0x on falling edge 1 1 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 EXINT1RC Interrupt flag for external interrupt 1x on rising edge 2 2 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 EXINT1FC Interrupt flag for external interrupt 1x on falling edge 3 3 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 EXINT2RC Interrupt flag for external interrupt 2x on rising edge 4 4 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 EXINT2FC Interrupt flag for external interrupt 2x on falling edge 5 5 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 IRCON1 Interrupt request 1 register 0x8 32 read-only 0x0 0xffffffff MON1R Interrupt flag for MON1x on rising edge 0 0 read-only NOT_OCCURED Interrupt on rising edge event has not occurred 0 OCCURED Interrupt on rising edge event has occurred 1 MON1F Interrupt flag for MON1x on falling edge 1 1 read-only NOT_OCCURED Interrupt on falling edge event has not occurred 0 OCCURED Interrupt on falling edge event has occurred 1 MON2R Interrupt flag for MON2x on rising edge 2 2 read-only NOT_OCCURED Interrupt on rising edge event has not occurred 0 OCCURED Interrupt on rising edge event has occurred 1 MON2F Interrupt flag for MON2x on falling edge 3 3 read-only NOT_OCCURED Interrupt on falling edge event has not occurred 0 OCCURED Interrupt on falling edge event has occurred 1 MON3R Interrupt flag for MON3x on rising edge 4 4 read-only NOT_OCCURED Interrupt on rising edge event has not occurred 0 OCCURED Interrupt on rising edge event has occurred 1 MON3F Interrupt flag for MON3x on falling edge 5 5 read-only NOT_OCCURED Interrupt on falling edge event has not occurred 0 OCCURED Interrupt on falling edge event has occurred 1 MON4R Interrupt flag for MON4x on rising edge 6 6 read-only NOT_OCCURED Interrupt on rising edge event has not occurred 0 OCCURED Interrupt on rising edge event has occurred 1 MON4F Interrupt flag for MON4x on falling edge 7 7 read-only NOT_OCCURED Interrupt on falling edge event has not occurred 0 OCCURED Interrupt on falling edge event has occurred 1 MON5R Interrupt flag for MON5x on rising edge 8 8 read-only NOT_OCCURED Interrupt on rising edge event has not occurred 0 OCCURED Interrupt on rising edge event has occurred 1 MON5F Interrupt flag for MON5x on falling edge 9 9 read-only NOT_OCCURED Interrupt on falling edge event has not occurred 0 OCCURED Interrupt on falling edge event has occurred 1 IRCON1CLR Interrupt request 1 clear register 0x17C 32 read-write 0x0 0xffffffff MON1RC Interrupt flag for MON1x on rising edge 0 0 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 MON1FC Interrupt flag for MON1x on falling edge 1 1 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 MON2RC Interrupt flag for MON2x on rising edge 2 2 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 MON2FC Interrupt flag for MON2x on falling edge 3 3 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 MON3RC Interrupt flag for MON3x on rising edge 4 4 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 MON3FC Interrupt flag for MON3x on falling edge 5 5 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 MON4RC Interrupt flag for MON4x on rising edge 6 6 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 MON4FC Interrupt flag for MON4x on falling edge 7 7 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 MON5RC Interrupt flag for MON5x on rising edge 8 8 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 MON5FC Interrupt flag for MON5x on falling edge 9 9 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 IRCON2 Interrupt request 2 register 0xC 32 read-only 0x0 0xffffffff EIR1 Error interrupt flag for SSC1 0 0 read-only NOT_OCCURED Interrupt event has not occurred 0 OCCURED Interrupt event has occurred 1 TIR1 Transmit interrupt flag for SSC1 1 1 read-only NOT_OCCURED Interrupt event has not occurred 0 OCCURED Interrupt event has occurred 1 RIR1 Receive interrupt flag for SSC1 2 2 read-only NOT_OCCURED Interrupt event has not occurred 0 OCCURED Interrupt event has occurred 1 IRCON2CLR Interrupt request 2 clear register 0x190 32 read-write 0x0 0xffffffff EIR1C Error interrupt flag for SSC1 0 0 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 TIR1C Transmit interrupt flag for SSC1 1 1 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 RIR1C Receive interrupt flag for SSC1 2 2 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 IRCON3 Interrupt request 3 register 0x10 32 read-only 0x0 0xffffffff EIR2 Error interrupt flag for SSC2 0 0 read-only NOT_OCCURED Interrupt event has not occurred 0 OCCURED Interrupt event has occurred 1 TIR2 Transmit interrupt flag for SSC2 1 1 read-only NOT_OCCURED Interrupt event has not occurred 0 OCCURED Interrupt event has occurred 1 RIR2 Receive interrupt flag for SSC2 2 2 read-only NOT_OCCURED Interrupt event has not occurred 0 OCCURED Interrupt event has occurred 1 IRCON3CLR Interrupt request 3 clear register 0x194 32 read-write 0x0 0xffffffff EIR2C Error interrupt flag for SSC2 0 0 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 TIR2C Transmit interrupt flag for SSC2 1 1 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 RIR2C Receive interrupt flag for SSC2 2 2 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 IRCON4 Interrupt request 4 register 0x14 32 read-only 0x0 0xffffffff CCU6SR0 Interrupt flag 0 for CCU6 0 0 read-only NOT_OCCURED Interrupt event has not occurred 0 OCCURED Interrupt event has occurred 1 CCU6SR1 Interrupt flag 1 for CCU6 4 4 read-only NOT_OCCURED Interrupt event has not occurred 0 OCCURED Interrupt event has occurred 1 CCU6SR2 Interrupt flag 2 for CCU6 16 16 read-only NOT_OCCURED Interrupt event has not occurred 0 OCCURED Interrupt event has occurred 1 CCU6SR3 Interrupt flag 3 for CCU6 20 20 read-only NOT_OCCURED Interrupt event has not occurred 0 OCCURED Interrupt event has occurred 1 IRCON4CLR Interrupt request 4 clear register 0x198 32 read-write 0x0 0xffffffff CCU6SR0C Interrupt flag 0 for CCU6 0 0 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 CCU6SR1C Interrupt flag 1 for CCU6 4 4 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 CCU6SR2C Interrupt flag 2 for CCU6 16 16 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 CCU6SR3C Interrupt flag 3 for CCU6 20 20 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 IRCON5 Interrupt request 5 register 0x7C 32 read-only 0x0 0xffffffff WAKEUP Interrupt flag for wake-up 0 0 read-only NOT_OCCURED Interrupt event has not occurred 0 OCCURED Interrupt event has occurred 1 IRCON5CLR Interrupt request 5 clear register 0x19C 32 read-write 0x0 0xffffffff WAKEUPC Clear flag for wake-up interrupt 0 0 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 LINSCLR LIN status clear register 0xA4 32 read-write 0x0 0xffffffff BRKC Break field flag clear 3 3 write-only NOT_CLEARED Break field is not cleared 0 CLEARED Break field is cleared 1 EOFSYNC End of SYN byte interrupt flag clear 4 4 write-only NOT_CLEARED End of SYN byte is not cleared 0 CLEARED End of SYN byte is cleared 1 ERRSYNC SYN byte error interrupt flag 5 5 write-only NOT_CLEARED Error in SYN byte not cleared 0 CLEARED Error in SYN byte cleared 1 LINST LIN status register 0x94 32 read-write 0x0 0xffffffff BRDIS Baud-rate detection disable 0 0 read-write ENABLED Break/sync detection is enabled 0 DISABLED Break/sync detection is disabled 1 BGSEL Baud-rate select for detection 1 2 read-write BRK Break field flag 3 3 read-only NOT_DETECTED Break field is not detected 0 DETECTED Break field is detected 1 EOFSYN End of SYN byte interrupt flag 4 4 read-only NOT_DETECTED End of SYN byte is not detected 0 DETECTED End of SYN byte is detected 1 ERRSYN SYN byte error interrupt flag 5 5 read-only NOT_DETECTED Error is not detected in SYN byte 0 DETECTED Error is detected in SYN byte 1 SYNEN End of SYN byte and SYN byte error interrupts enable 6 6 read-write DISABLED End of SYN byte and SYN byte error interrupts are not enabled 0 ENABLED End of SYN byte and SYN byte error interrupts are enabled 1 MEM_ACC_STS Memory access status register 0xE4 32 read-only 0x0 0xffffffff NVM_PROT_ERR NVM access protection 0 0 read-only NO_ERROR No Protection error 0 ERROR Protection error 1 NVM_ADDR_ERR NVM address protection 1 1 read-only NO_ERROR No Protection error 0 ERROR Protection error 1 NVM_SFR_PROT_ERR NVM SFR access protection 2 2 read-only NO_ERROR No Protection error 0 ERROR Protection error 1 NVM_SFR_ADDR_ERR NVM SFR address protection 3 3 read-only NO_ERROR No Protection error 0 ERROR Protection error 1 ROM_PROT_ERR ROM access protection 4 4 read-only NO_ERROR No Protection error 0 ERROR Protection error 1 MEMSTAT Memory status register 0xDC 32 read-write 0x0 0xffffffff SECTORINFO Sector information 0 5 read-write SASTATUS Service algorithm status 6 7 read-write SECTORINFO Depending on SECTORINFO 0 SUCCESS SA execution is successful 1 NO_SUCCESS SA execution is not successful. Map error exists in the mapped sector 2 NO_SUCCESS SA execution is not successful. Map error exists in the mapped sector 3 MODIEN1 Peripheral interrupt enable 1 register 0x30 32 read-write 0x0 0xffffffff EIREN1 SSC 1 error interrupt enable 0 0 read-write DISABLED Error interrupt is disabled 0 ENABLED Error interrupt is enabled 1 TIREN1 SSC 1 transmit interrupt enable 1 1 read-write DISABLED Transmit interrupt is disabled 0 ENABLED Transmit interrupt is enabled 1 RIREN1 SSC 1 receive interrupt enable 2 2 read-write DISABLED Receive interrupt is disabled 0 ENABLED Receive interrupt is enabled 1 EIREN2 SSC 2 error interrupt enable 8 8 read-write DISABLED Error interrupt is disabled 0 ENABLED Error interrupt is enabled 1 TIREN2 SSC 2 transmit interrupt enable 9 9 read-write DISABLED Transmit interrupt is disabled 0 ENABLED Transmit interrupt is enabled 1 RIREN2 SSC 2 receive interrupt enable 10 10 read-write DISABLED Receive interrupt is disabled 0 ENABLED Receive interrupt is enabled 1 MODIEN2 Peripheral interrupt enable 2 register 0x34 32 read-write 0x0 0xffffffff RIEN1 UART 1 receive interrupt enable 0 0 read-write DISABLED Receive interrupt is disabled 0 ENABLED Receive interrupt is enabled 1 TIEN1 UART 1 transmit interrupt enable 1 1 read-write DISABLED Transmit interrupt is disabled 0 ENABLED Transmit interrupt is enabled 1 EXINT2_EN External interrupt 2 enable 5 5 read-write DISABLED External interrupt is disabled 0 ENABLED External interrupt is enabled 1 RIEN2 UART 2 receive interrupt enable 6 6 read-write DISABLED Receive interrupt is disabled 0 ENABLED Receive interrupt is enabled 1 TIEN2 UART 2 transmit interrupt enable 7 7 read-write DISABLED Transmit interrupt is disabled 0 ENABLED Transmit interrupt is enabled 1 MODIEN3 Peripheral interrupt enable 3 register 0x38 32 read-write 0x0 0xffffffff IE0 External interrupt enable 0 0 read-write DISABLED Disabled 0 ENABLED Enabled 1 MODIEN4 Peripheral interrupt enable 4 register 0x3C 32 read-write 0x0 0xffffffff IE1 External interrupt enable 0 0 read-write DISABLED Disabled 0 ENABLED Enabled 1 MODPISEL Peripheral input select register 0xB8 32 read-write 0x0 0xffffffff EXINT0IS External interrupt 0 input select 0 1 read-write EXINT0_0 External interrupt input EXINT0_0 is selected 0 EXINT0_1 External interrupt input EXINT0_1 is selected 1 EXINT0_2 External interrupt input EXINT0_2 is selected 2 EXINT0_3 External interrupt input EXINT0_3 is selected 3 EXINT1IS External interrupt 1 input select 2 3 read-write EXINT1_0 External interrupt input EXINT1_0 is selected 0 EXINT1_1 External interrupt input EXINT1_1 is selected 1 EXINT1_2 External interrupt input EXINT1_2 is selected 2 EXINT1_3 External interrupt input EXINT1_3 is selected 3 EXINT2IS External interrupt 2 input select 4 5 read-write EXINT2_0 External interrupt input EXINT2_0 is selected 0 EXINT2_1 External interrupt input EXINT2_1 is selected 1 EXINT2_2 External interrupt input EXINT2_2 is selected 2 EXINT2_3 External interrupt input EXINT2_3 is selected 3 URIOS1 UART1 input select 6 6 read-write TRX UART1 receiver input UART1_RXD (connected to transceiver) 0 GPIO UART1 receiver input UART1_RXD (connected to GPIO) 1 U_TX_CONDIS TRX input select 7 7 read-write UART Transceiver TXD input connected to UART1_TXD output 0 GPIO Transceiver TXD input connected to GPIO 1 SSC12_M_SCK_OUTSEL Output selection for SSC12_M_SCK 16 16 read-write SSC1 SSC1_M_SCK 0 SSC2 SSC2_M_SCK 1 SSC12_M_MTSR_OUTSEL Output selection for SSC12_M_MTSR 17 17 read-write SSC1 SSC1_M_MTSR 0 SSC2 SSC2_M_MTSR 1 SSC12_S_MRST_OUTSEL Output selection for SSC12_S_MRST 18 18 read-write SSC1 SSC1_S_MRST 0 SSC2 SSC2_S_MRST 1 MODPISEL1 Peripheral input select 1 register 0xBC 32 read-write 0x0 0xffffffff XTAL12EN Pins XTAL1/2 enable bit 0 0 read-write NOT_AVAILABLE Pins XTAL1/2 is not available. This setting overrides the OSC_CON.XPD setting 0 AVAILABLE Pins XTAL1/2 is available 1 T2EXCON Timer 2 external input control 6 6 read-write SELECT Timer2 input T2EX is selected by bit field SCU_MODPISEL2.T2EXIS 0 CONNECT Timer2 input T2EX is connected to signal from CCU6 (Output>cc6_cout60) 1 T21EXCON Timer 21 external input control 7 7 read-write SELECT Timer21 input T21EX is selected by bit field SCU_MODPISEL2.T21EXIS 0 CONNECT Timer21 input T21EX is connected to signal from CCU6 (Output >cc6_ch0) 1 MODPISEL2 Peripheral input select 2 register 0xC0 32 read-write 0x0 0xffffffff T2IS Timer 2 input select 0 1 read-write T2_0 Timer2 input T2_0 is selected 0 T2_1 Timer2 input T2_1 is selected 1 T2_2 Timer2 input T2_2 is selected 2 T21IS Timer 21 input select 2 3 read-write T21_0 Timer21 input T21_0 is selected 0 T21_1 Timer21 input T21_1 is selected 1 T21_2 Timer21 input T21_2 is selected 2 T2EXIS Timer 2 external input select 4 5 read-write T2EX_0 Timer2 input T2EX_0 is selected 0 T2EX_1 Timer2 input T2EX_1 is selected 1 T2EX_2 Timer2 input T2EX_2 i selected 2 T2EX_3 Timer2 input T2EX_3 is selected 3 T21EXIS Timer 21 external input select 6 7 read-write T21EX_0 Timer21 input T21EX_0 is selected 0 T21EX_1 Timer21 input T21EX_1 is selected 1 T21EX_2 Timer21 input T21EX_2 is selected 2 T21EX_3 Timer21 input T21EX_3 is selected 3 MODPISEL3 Peripheral input select 3 register 0xC4 32 read-write 0x0 0xffffffff URIOS2 UART2 input select 6 6 read-write GPIO UART2 receiver input UART2_RXD (connected to GPIO) 0 GPIO UART2 receiver input UART2_RXD (connected to GPIO) 1 MODPISEL4 Peripheral input select 4 register 0xFC 32 read-write 0x4030100 0xffffffff DU1TRIGGEN Differential unit trigger enable 0 2 read-write CC60 CC60 is selected 0 CC61 CC61 is selected 1 CC62 CC62 is selected 2 COUT60 COUT60 is selected 3 COUT61 COUT61 is selected 4 COUT62 COUT62 is selected 5 T3OUT T3OUT is selected 6 COUT6 COUT63 is selected 7 DU2TRIGGEN Differential unit trigger enable 8 10 read-write CC60 CC60 is selected 0 CC61 CC61 is selected 1 CC62 CC62 is selected 2 COUT60 COUT60 is selected 3 COUT61 COUT61 is selected 4 COUT62 COUT62 is selected 5 T3OUT T3OUT is selected 6 COUT63 COUT63 is selected 7 DU3TRIGGEN Differential unit trigger enable 16 18 read-write CC60 CC60 is selected 0 CC61 CC61 is selected 1 CC62 CC62 is selected 2 COUT60 COUT60 is selected 3 COUT61 COUT61 is selected 4 COUT62 COUT62 is selected 5 T3OUT T3OUT is selected 6 COUT63 COUT63 is selected 7 DU4TRIGGEN Differential unit trigger enable 24 26 read-write CC60 CC60 is selected 0 CC61 CC61 is selected 1 CC62 CC62 is selected 2 COUT60 COUT60 is selected 3 COUT61 COUT61 is selected 4 COUT62 COUT62 is selected 5 T3OUT T3OUT is selected 6 COUT63 COUT63 is selected 7 MODSUSP Module suspend control register 0xC8 32 read-write 0x81 0xffffffff T12SUSP Timer 12 debug suspend bit 1 1 read-write NOT_SUSPENDED Timer12 in capture/compare unit will not be suspended 0 SUSPENDED Timer12 in capture/compare unit will be suspended 1 T13SUSP Timer 13 debug suspend bit 2 2 read-write NOT_SUSPENDED Timer13 in capture/compare unit will not be suspended 0 SUSPENDED Timer13 in capture/compare unit will be suspended 1 T2_SUSP Timer 2 debug suspend bit 3 3 read-write NOT_SUSPENDED Timer2 will not be suspended 0 SUSPENDED Timer2 will be suspended 1 GPT12_SUSP GPT12 debug suspend bit 4 4 read-write NOT_SUSPENDED GPT12 will not be suspended 0 SUSPENDED GPT12 will be suspended 1 T21_SUSP Timer 21 debug suspend bit 6 6 read-write NOT_SUSPENDED Timer21 will not be suspended 0 SUSPENDED Timer21 will be suspended 1 WDT1SUSP Watchdog timer 1 debug suspend bit 7 7 read-write NOT_SUSPENDED WDT1 will not be suspended 0 SUSPENDED WDT1 will be suspended 1 MU_SUSP Measurement unit debug suspend bit 9 9 read-write NOT_SUSPENDED MU will not be suspended 0 SUSPENDED MU will be suspended 1 ADC1_SUSP ADC1 unit debug suspend bit 10 10 read-write NOT_SUSPENDED ADC1 will not be suspended 0 SUSPENDED ADC1 will be suspended 1 MONIEN Monitoring input interrupt enable register 0x18C 32 read-write 0x0 0xffffffff MON1IE MON1 interrupt enable 0 0 read-write DISABLED Disabled 0 ENABLED Enabled 1 MON2IE MON2 interrupt enable 1 1 read-write DISABLED Disabled 0 ENABLED Enabled 1 MON3IE MON3 interrupt enable 2 2 read-write DISABLED Disabled 0 ENABLED Enabled 1 MON4IE MON4 interrupt enable 3 3 read-write DISABLED Disabled 0 ENABLED Enabled 1 MON5IE MON5 interrupt enable 4 4 read-write DISABLED Disabled 0 ENABLED Enabled 1 NMICON NMI control register 0x24 32 read-write 0x0 0xffffffff NMIPLL PLL loss of lock NMI enable 1 1 read-write DISABLED PLL loss of lock NMI is disabled 0 ENABLED PLL loss of lock NMI is enabled 1 NMINVM NVM operation complete NMI enable 2 2 read-write DISABLED NVM operation complete NMI is disabled 0 ENABLED NVM operation complete NMI is enabled 1 NMIOT NMI OT enable 3 3 read-write DISABLED NMI OT is disabled 0 ENABLED NMI OT is enabled 1 NMIOWD Oscillator watchdog NMI enable 4 4 read-write DISABLED Oscillator watchdog NMI is disabled 0 ENABLED Oscillator watchdog NMI is enabled 1 NMIMAP NVM map error NMI enable 5 5 read-write DISABLED NVM map error NMI is disabled 0 ENABLED NVM map error NMI is enabled 1 NMIECC ECC error NMI enable 6 6 read-write DISABLED ECC Error NMI is disabled 0 ENABLED ECC Error NMI is enabled 1 NMISUP Supply prewarning NMI enable 7 7 read-write DISABLED Supply NMI is disabled 0 ENABLED Supply NMI is enabled 1 NMISR NMI status register 0x18 32 read-only 0x0 0xffffffff FNMIPLL PLL NMI flag 1 1 read-only NO_PLL No PLL NMI has occurred 0 PLL PLL loss-of-lock to the external crystal has occurred 1 FNMINVM NVM operation complete NMI flag 2 2 read-only NO_NVM No NVM NMI has occurred 0 NVM NVM operation complete event has occurred 1 FNMIOT Overtemperature NMI flag 3 3 read-only NO_OT No OT NMI has occurred 0 OT OT NMI event has occurred 1 FNMIOWD Oscillator watchdog NMI flag 4 4 read-only NO_OSCILLATOR No oscillator watchdog NMI has occurred 0 OSCILLATOR Oscillator watchdog event has occurred 1 FNMIMAP NVM map error NMI flag 5 5 read-only NO_NVM No NVM map error NMI has occurred 0 NVM NVM map error has occurred 1 FNMIECC ECC error NMI flag 6 6 read-only NO_ECC No uncorrectable ECC error has occurred on NVM, XRAM 0 ECC Uncorrectable ECC error has occurred on NVM, RAM 1 FNMISUP Supply prewarning NMI flag 7 7 read-only NO_PREWARN No supply prewarning NMI has occurred 0 PREWARN Supply prewarning has occurred 1 NMISRCLR NMI status clear register 0x0 32 read-write 0x0 0xffffffff FNMIPLLC PLL NMI flag 1 1 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 FNMINVMC NVM operation complete NMI flag 2 2 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 FNMIOTC Overtemperature NMI flag 3 3 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 FNMIOWDC Oscillator watchdog NMI flag 4 4 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 FNMIMAPC NVM map error NMI flag 5 5 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 FNMIECCC ECC error NMI flag 6 6 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 FNMISUPC Supply prewarning NMI flag 7 7 write-only NOT_CLEARED Interrupt event is not cleared 0 CLEARED Interrupt event is cleared 1 NVM_PROT_STS NVM protection status register 0xE0 32 read-write 0x0 0xffffffff EN_PRG_NL NVM protection of data in non-linear sectors 0 0 read-write NO_CHANGE The data in sectors of the non-linearly mapped area can not be changed 0 CHANGE The data in sectors of the non-linearly mapped area can be changed (erased or written) 1 EN_PRG_LIN NVM protection of data in linear sectors 1 1 read-write NO_CHANGE The data in sectors of the linearly mapped area can not be changed 0 CHANGE The data in sectors of the linearly mapped area can be changed (erased or written) 1 EN_PRG_CBSL NVM protection of data in CBSL region 2 2 read-write NO_CHANGE The data in region defined by NVMBSL can not be changed 0 CHANGE The data in region defined by NVMBSL can be changed (erased or written) 1 EN_RD_NL NVM read protection of data in non-linear sectors 3 3 read-write NO_READ The data in sectors of the non-linearly mapped area can not be read 0 READ The data in sectors of the non-linearly mapped area can be read 1 EN_RD_LIN NVM read protection of data in linear sectors 4 4 read-write NO_READ The data in sectors of the linearly mapped area can not be read 0 READ The data in sectors of the linearly mapped area can be read 1 EN_RD_CBSL NVM read protection of data in CBSL region 5 5 read-write NO_READ The data in region defined by NVMBSL can not be read 0 READ The data in region defined by NVMBSL sectors of can be read 1 EN_RD_S0 NVM read protection for sector 0 8 8 read-write NO_READ The data in sector 0 can not be read over AHB-Lite interface 0 READ The data in sector 0 can be read over AHB-Lite interface 1 DIS_RDUS Configuration of NVM read protection for sector 1...n with EN_RD_* = 0 9 9 read-write NVM_READ_UNSAVE Only active when nvm_read_unsafe_i = 1 and not for nvm_read_unsafe_i = 0 0 INDEPENTENT Independent from nvm_read_unsafe_i; also write accesses to sector 1...n are prevented 1 DIS_RDUS_S0 Configuration of NVM read protection for sector 0 with EN_RD_S0 = 0 10 10 read-write NVM_READ_S0_UNSAVE Only active when nvm_read_S0_unsafe_i = 1 and not for nvm_read_S0_unsafe_i = 0 0 INDEPENDENT Independent from nvm_read_S0_unsafe_i; also write accesses to sector 0 are prevented 1 NL_PW Status of non-linear region password/protection 11 11 read-write NOT_PROTECTED Non-linear region password is not installed; linear region is not protected 0 PROTECTED Non-linear region password is installed; linear region is protected 1 LIN_PW Status of linear region password/protection 12 12 read-write NOT_PROTECTED Linear region password is not installed; linear region is not protected 0 PROTECTED Linear region password is installed; linear region is protected 1 CBSL_PW Status of CBSL region password/protection 13 13 read-write NOT_PROTECTED CBSL region password is not installed; CBSL region is not protected 0 PROTECTED CBSL region password is installed; CBSL region is protected 1 NVMBSL CBSL region size definition 14 15 read-write 4 CBSL size is 4 K 0 8 CBSL size is 8 K 1 12 CBSL size is 12 K 2 16 CBSL size is 16 K 3 OSC_CON OSC control register 0xB0 32 read-write 0x10 0xffffffff OSCSS Oscillator source select 0 1 read-write PLL_SYNC PLL internal oscillator OSC_PLL (fINT) is selected synchronously as fR 0 XTAL XTAL (fOSC from OSC_HP) is selected synchronously as fR 1 PLL_ASYNC PLL internal oscillator OSC_PLL (fINT) is selected asynchronously as fR 2 PLL_ASYNC PLL internal oscillator OSC_PLL (fINT) is selected asynchronously as fR 3 OSCWDTRST Oscillator watchdog reset 2 2 read-write NO_EFFECT No effect 0 RESET Reset OSC2L flag and restart the oscillator watchdog of the PLL 1 OSC2L OSC-too-low condition flag 3 3 read-only ABOVE fOSC is above threshold 0 BELOW fOSC is below threshold 1 XPD XTAL (OSC_HP) power down control 4 4 read-write NOT_POWERED XTAL (OSC_HP) is not powered down 0 POWERED XTAL (OSC_HP) is powered down 1 P0_POCON0 Port output control register 0xE8 32 read-write 0x0 0xffffffff P0_PDM0 P0.0 port driver mode 0 2 read-write MEDIUM_1 Medium driver 1 0 WEAK_1 Weak driver 1 3 MEDIUM_2 Medium driver 2 4 MEDIUM_3 Medium driver 3 5 MEDIUM_4 Medium driver 4 6 WEAK_2 Weak driver 2 7 P0_PDM1 P0.1 port driver mode 4 6 read-write MEDIUM_1 Medium driver 1 0 WEAK_1 Weak driver 1 3 MEDIUM_2 Medium driver 2 4 MEDIUM_3 Medium driver 3 5 MEDIUM_4 Medium driver 4 6 WEAK_2 Weak driver 2 7 P0_PDM2 P0.2 port driver mode 8 10 read-write STRONG_SHARP Strong driver and sharp edge mode 0 STRONG_MEDIUM Strong driver and medium edge mode 1 STRONG_SOFT Strong driver and soft edge mode 2 WEAK_1 Weak driver 1 3 MEDIUM_1 Medium driver 1 4 MEDIUM_2 Medium driver 2 5 MEDIUM_3 Medium driver 3 6 WEAK_2 Weak driver 2 7 P0_PDM3 P0.3 port driver mode 12 14 read-write STRONG_SHARP Strong driver and sharp edge mode 0 STRONG_MEDIUM Strong driver and medium edge mode 1 STRONG_SOFT Strong driver and soft edge mode 2 WEAK_1 Weak driver 1 3 MEDIUM_1 Medium driver 1 4 MEDIUM_2 Medium driver 2 5 MEDIUM_3 Medium driver 3 6 WEAK_2 Weak driver 2 7 P0_PDM4 P0.4 port driver mode 16 18 read-write STRONG_SHARP Strong driver and sharp edge mode 0 STRONG_MEDIUM Strong driver and medium edge mode 1 STRONG_SOFT Strong driver and soft edge mode 2 WEAK_1 Weak driver 1 3 MEDIUM_1 Medium driver 1 4 MEDIUM_2 Medium driver 2 5 MEDIUM_3 Medium driver 3 6 WEAK_2 Weak driver 2 7 P0_PDM5 P0.5 port driver mode 20 22 read-write STRONG_SHARP Strong driver and sharp edge mode 0 STRONG_MEDIUM Strong driver and medium edge mode 1 STRONG_SOFT Strong driver and soft edge mode 2 WEAK_1 Weak driver 1 3 MEDIUM_1 Medium driver 1 4 MEDIUM_2 Medium driver 2 5 MEDIUM_3 Medium driver 3 6 WEAK_2 Weak driver 2 7 P1_POCON0 Port output control register 0xF8 32 read-write 0x0 0xffffffff P1_PDM0 P1.0 port driver mode 0 2 read-write MEDIUM_1 Medium driver 1 0 WEAK_1 Weak driver 1 3 MEDIUM_2 Medium driver 2 4 MEDIUM_3 Medium driver 3 5 MEDIUM_4 Medium driver 4 6 WEAK_2 Weak driver 2 7 P1_PDM1 P1.1 port driver mode 4 6 read-write MEDIUM_1 Medium driver 1 0 WEAK_1 Weak driver 1 3 MEDIUM_2 Medium driver 2 4 MEDIUM_3 Medium driver 3 5 MEDIUM_4 Medium driver 4 6 WEAK_2 Weak driver 2 7 P1_PDM2 P1.2 port driver mode 8 10 read-write MEDIUM_1 Medium driver 1 0 WEAK_1 Weak driver 1 3 MEDIUM_2 Medium driver 2 4 MEDIUM_3 Medium driver 3 5 MEDIUM_4 Medium driver 4 6 WEAK_2 Weak driver 2 7 P1_PDM4 P1.4 port driver mode 16 18 read-write STRONG_SHARP Strong driver and sharp edge mode 0 STRONG_MEDIUM Strong driver and medium edge mode 1 STRONG_SOFT Strong driver and soft edge mode 2 WEAK_1 Weak driver 1 3 MEDIUM_1 Medium driver 1 4 MEDIUM_2 Medium driver 2 5 MEDIUM_3 Medium driver 3 6 WEAK_2 Weak driver 2 7 PASSWD Password register 0xAC 32 read-write 0x7 0xffffffff PW_MODE Bit protection scheme control bit 0 1 read-write DISABLED Scheme disabled 0 ENABLED Scheme enabled (default) 3 PROTECT_S Bit protection signal status bit 2 2 read-only NOT_PROTECTED Software is able to write to all protected bits 0 PROTECTED Software is unable to write to any protected bits 1 PASS Password bits 3 7 read-write OPENED Opens access to writing of all protected bits 19 CLOSED Closes access to writing of all protected bits 21 ENABLED Enables writing of the bit field MODE 24 PLL_CON PLL control register 0x44 32 read-write 0xa4 0xffffffff LOCK PLL lock status flag 0 0 read-only UNLOCKED The frequency difference of fREF and fDIV is greater than allowed. The VCO part of the PLL can not lock on a target frequency 0 LOCKED The frequency difference of fREF and fDIV is small enough to enable a stable VCO operation 1 RESLD Restart lock detection 1 1 read-write NO No effect 0 RESET Reset lock flag and restart lock detection 1 OSCDISC Oscillator disconnect 2 2 read-write CONNECTED Oscillator is connected to the PLL 0 DISCONNECTED Oscillator is disconnected to the PLL 1 VCOBYP PLL VCO bypass mode select 3 3 read-write NORMAL Normal (or free running) operation (default) 0 PRESCALER Prescaler mode; VCO is bypassed (PLL output clock is derived from input clock divided by K1-divider) 1 NDIV PLL N-divider 4 7 read-write 48 N = 48 0 50 N = 50 1 51 N = 51 2 52 N = 52 3 54 N = 54 4 60 N = 60 5 67 N = 67 6 72 N = 72 7 75 N = 75 8 78 N = 78 9 80 N = 80 10 88 N = 88 11 90 N = 90 12 94 N =94 13 100 N = 100 14 160 N = 160 15 UNPROT_OSCDISC Unprotect write access of OSC_DISC 10 10 write-only UNPROT_VCOBYP Unprotect write access of VCO_BYP 11 11 write-only PMCON Peripheral management control register 0x60 32 read-write 0x0 0xffffffff ADC1_DIS ADC1 disable request, active high 0 0 read-write NORMAL ADC1 is in normal operation (default) 0 DISABLE Request to disable the ADC 1 SSC1_DIS SSC1 disable request, active high 1 1 read-write NORMAL SSC is in normal operation (default) 0 DISABLE Request to disable the SSC 1 CCU6_DIS CCU6 disable request, active high 2 2 read-write NORMAL CCU6 is in normal operation (default) 0 DISABLE Request to disable the CCU6 1 T2_DIS T2 disable request, active high 3 3 read-write NORMAL T2 is in normal operation (default) 0 DISABLE Request to disable the T2 1 GPT12_DIS General purpose timer 12 disable request, active high 4 4 read-write NORMAL GPT12 is in normal operation (default) 0 DISABLE Request to disable the GPT12 1 SSC2_DIS SSC2 disable request, active high 8 8 read-write NORMAL SSC is in normal operation (default) 0 DISABLE Request to disable the SSC 1 T21_DIS T21 disable request, active high 10 10 read-write NORMAL T21 is in normal operation (default) 0 DISABLE Request to disable the T21 1 PMCON0 Power mode control 0 register 0x40 32 read-write 0x0 0xffffffff XTAL_ON OSC_HP operation in STOP mode 0 0 read-write XTAL_OFF OSC_HP (XTAL) will be suspended by hardware in STOP mode 0 XTAL_ON OSC_HP (XTAL) continues to operate in STOP mode, if enabled by SCU_OSC_CON.XPD 1 SL Sleep mode 1 1 read-write INACTIVE No change 0 ACTIVE Device goes into Sleep mode 1 PD Power-down mode 2 2 read-write INACTIVE No change 0 ACTIVE Device goes into Power-down mode 1 SD Slow-down mode 3 3 read-write INACTIVE No change 0 ACTIVE Device goes into Slow-down mode 1 RSTCON Reset control register 0x68 32 read-write 0x0 0xffffffff LOCKUP Lockup flag 0 0 read-write NOT_ACTIVE Lockup status not active 0 ACTIVE Lockup status active 1 LOCKUP_EN Lockup reset enable flag 7 7 read-write DISABLED Lockup is disabled 0 ENABLED Lockup is enabled 1 SYS_STRTUP_STS System startup status register 0x74 32 read-write 0x0 0xffffffff INIT_FAIL Initialization at startup failed 0 0 read-write NO_ERROR No initialization error at startup 0 ERROR Initialization error at startup 1 MRAMINITSTS Map RAM initialization status 1 1 read-write NO_FAIL Map RAM initialization was successful 0 FAIL Map RAM initialization was not successful 1 PG100TP_CHKS_ERR 100 TP Page checksum error 2 2 read-write OK Initialization of trimming parameters from NMV was successful (checksum was correct) 0 NOK Initialization of trimming parameter from NMV was not successful (checksum was notcorrect). As a backup default values form Boot-ROM are used 1 SYSCON0 System control 0 register 0x70 32 read-write 0x80 0xffffffff NVMCLKFAC NVM access clock factor 4 5 read-write 1 Divide by 1 0 2 Divide by 2 1 3 Divide by 3 2 4 Divide by 4 3 SYSCLKSEL System clock select 6 7 read-write PLL The PLL clock output signal fPLL is used 0 OSC The direct clock input from fOSC is used 1 LP_CLK The direct low-precision clock input from fLP_CLK is used 2 INTOSC The direct input from internal oscillator fINTOSC is used 3 TCCR Temperature compensation control register 0xF4 32 read-write 0x0 0xffffffff TCC Temperature compensation control 0 1 read-write _40_0 Tj: -40deg C to 0deg C 0 0_40 Tj: 0deg C to 40deg C 1 40_80 Tj: 40deg C to 80deg C 2 80_150 Tj: 80deg C to 150deg C 3 VTOR Vector table reallocation register 0x20 32 read-write 0x0 0xffffffff VTOR_BYP Vector table bypass mode 0 1 read-write NOT_REMAPPED VTOR is not remapped (ROM) (start address: 0x0000000000) 0 RAM VTOR is remapped to RAM (start address: 0x1800000000) 1 BSL VTOR is remapped to NVM (start address: 0x1100000000, begin of customer BSL region) 2 NVM VTOR is remapped to NVM (start address: begin of NVM linear region after customer BSL region) 3 WAKECON Wake-up interrupt control register 0x78 32 read-write 0x0 0xffffffff WAKEUPEN Wake-up interrupt enable 0 0 read-write DISABLED Wake-up interrupt is disabled 0 ENABLED Wake-up interrupt is enabled 1 SCUPM 100 System Control Unit - Power Modules (SCU-PM) SCUPM 0x50006000 0 0x1000 registers AMCLK_CTRL Analog module clock control register 0x4 32 read-write 0x1 0xffffffff CLKWDT_PD_N Clock watchdog power down 0 0 read-write DISABLE Clock watchdog disabled 0 ENABLE Clock watchdog enabled 1 AMCLK_FREQ_STS Analog module clock frequency status register 0x0 32 read-only 0x0 0xffffffff AMCLK1_FREQ Current frequency of analog module clock system clock (MI_CLK) 0 5 read-only AMCLK2_FREQ Current frequency of analog module clock 2 (TFILT_CLK) 8 13 read-only AMCLK_TH_HYS Analog module clock limit register 0xC 32 read-write 0xd4e194b3 0xffffffff AMCLK1_UP_TH Analog module clock 1 (MI_CLK) upper limit threshold 0 5 read-write AMCLK1_UP_HYS Analog module clock 1 (MI_CLK) upper hysteresis 6 7 read-write AMCLK1_LOW_TH Analog module clock 1 (MI_CLK) lower limit threshold 8 13 read-write AMCLK1_LOW_HYS Analog module clock 1 (MI_CLK) lower hysteresis 14 15 read-write AMCLK2_UP_TH Analog module clock 2 (TFILT_CLK) upper limit threshold 16 21 read-write AMCLK2_UP_HYS Analog module clock 2 (TFILT_CLK) upper hysteresis 22 23 read-write AMCLK2_LOW_TH Analog module clock 2 (TFILT_CLK) lower limit threshold 24 29 read-write AMCLK2_LOW_HYS Analog module clock 2 (TFILT_CLK) lower hysteresis 30 31 read-write PCU_CTRL_STS Power control unit control status register 0x30 32 read-write 0xee37ef3 0xffffffff CLKWDT_SD_DIS Power modules clock watchdog shutdown disable 1 1 read-write ENABLE Power devices will be switched off when clock watchdog occurs 0 DISABLE Power devices will not be shut down when clock watchdog occurs 1 LIN_VS_UV_SD_DIS LIN module VS undervoltage transmitter shutdown 8 8 read-write ENABLE Automatic shutdown for power modules in case of VS undervoltage enabled 0 DISABLE Automatic shutdown for power modules in case of VS undervoltage disabled 1 STCALIB System tick calibration register 0x6C 32 read-write 0x0 0xffffffff STCALIB System tick calibration 0 25 read-write SYS_IRQ_CTRL System interrupt control register 0x28 32 read-write 0x0 0xffffffff SYS_OTWARN_IE System overtemperature warning interrupt enable 8 8 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 SYS_OT_IE System overtemperature shutdown interrupt enable (leads to shutdown of system) 9 9 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 REFBG_LOTHWARN_IE Reference voltage undervoltage interrupt enable 10 10 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 REFBG_UPTHWARN_IE Reference voltage overvoltage interrupt enable 11 11 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 SYS_IS System interrupt status register 0x18 32 read-write 0x0 0xffffffff LS1_FAIL_IS Low-side driver 1 fail interrupt status 0 0 read-only INACTIVE No status set 0 ACTIVE At least one status set 1 LS2_FAIL_IS Low-side driver 2 fail interrupt status 1 1 read-only INACTIVE No status set 0 ACTIVE At least one status set 1 HS1_FAIL_IS High-side driver 1 fail interrupt status 2 2 read-only INACTIVE No status set 0 ACTIVE At least one status set 1 HS2_FAIL_IS High-side driver 2 fail interrupt status 3 3 read-only INACTIVE No status set 0 ACTIVE At least one status set 1 LIN_FAIL_IS LIN fail interrupt status 6 6 read-only INACTIVE No status set 0 ACTIVE At least one status set 1 SYS_OTWARN_IS System overtemperature prewarning (ADC2, channel 6) interrupt status 8 8 read-write INACTIVE No interrupt status set 0 ACTIVE At least one interrupt status set 1 SYS_OT_IS System overtemperature shutdown (ADC2, channel 6) interrupt status 9 9 read-write INACTIVE No interrupt status set 0 ACTIVE At least one interrupt status set 1 REFBG_LOTHWARN_IS 8-bit ADC2 reference undervoltage (ADC2, channel 3) interrupt status 10 10 read-write INACTIVE No interrupt status set 0 ACTIVE At least one interrupt status set 1 REFBG_UPTHWARN_IS 8-bit ADC2 reference overvoltage (ADC2, channel 3) interrupt status 11 11 read-write INACTIVE No interrupt status set 0 ACTIVE At least one interrupt status set 1 LS1_FAIL_STS Low-side driver 1 fail status 16 16 read-only INACTIVE No status set 0 ACTIVE At least one status set 1 LS2_FAIL_STS Low-side driver 2 fail status 17 17 read-only INACTIVE No status set 0 ACTIVE At least one status set 1 HS1_FAIL_STS High-side driver 1 fail status 18 18 read-only INACTIVE No status set 0 ACTIVE At least one status set 1 HS2_FAIL_STS High-side driver 2 fail status 19 19 read-only INACTIVE No status set 0 ACTIVE At least one status set 1 LIN_FAIL_STS LIN fail status 22 22 read-only INACTIVE No status set 0 ACTIVE At least one status set 1 SYS_OTWARN_STS System overtemperature pre-warning (ADC2, channel 6) status 24 24 read-write INACTIVE No status set 0 ACTIVE At least one status set 1 SYS_OT_STS System overtemperature shutdown (ADC2, channel 6) status 25 25 read-write INACTIVE No status set 0 ACTIVE At least one status set 1 SYS_ISCLR System interrupt status clear register 0x14 32 read-write 0x0 0xffffffff SYS_OTWARN_ISC System overtemperature pre-warning status clear 8 8 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 SYS_OT_ISC System overtemperature shutdown status clear 9 9 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 REFBG_LOTHWARN_ISC 8-bit ADC2 reference undervoltage interrupt status clear 10 10 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 REFBG_UPTHWARN_ISC 8-bit ADC2 reference overvoltage interrupt status clear 11 11 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 SYS_OTWARN_SC System overtemperature pre-warning status clear 24 24 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 SYS_OT_SC System overtemperature shutdown status clear 25 25 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 SYS_SUPPLY_IRQ_CLR System supply interrupt status clear register 0x24 32 read-write 0x0 0xffffffff VBAT_UV_ISC VBAT undervoltage interrupt status clear 0 0 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VS_UV_ISC VS undervoltage interrupt status clear 1 1 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VDD5V_UV_ISC VDDP undervoltage interrupt status clear 2 2 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VDD1V5_UV_ISC VDDC undervoltage interrupt status clear 3 3 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VDDEXT_UV_ISC VDDEXT undervoltage interrupt status clear 4 4 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VBAT_OV_ISC VBAT overvoltage interrupt status clear 5 5 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VS_OV_ISC VS overvoltage interrupt status clear 6 6 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VDD5V_OV_ISC VDDP overvoltage interrupt status clear 7 7 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VDD1V5_OV_ISC VDDC overvoltage interrupt status clear 8 8 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VDDEXT_OV_ISC VDDEXT overvoltage interrupt status clear 9 9 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VBAT_UV_SC VBAT undervoltage status clear 16 16 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VS_UV_SC VS undervoltage status clear 17 17 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VDD5V_UV_SC VDDP undervoltage status clear 18 18 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VDD1V5_UV_SC VDDC undervoltage status clear 19 19 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VDDEXT_UV_SC VDDEXT undervoltage status clear 20 20 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VBAT_OV_SC VBAT overvoltage status clear 21 21 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VS_OV_SC VS overvoltage status clear 22 22 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VDD5V_OV_SC VDDP overvoltage status clear 23 23 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VDD1V5_OV_SC VDDC overvoltage status clear 24 24 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 VDDEXT_OV_SC VDDEXT overvoltage status clear 25 25 write-only NO_CLEAR The interrupt status is not cleared 0 CLEAR The interrupt status is cleared 1 SYS_SUPPLY_IRQ_CTRL System supply interrupt control register 0x20 32 read-write 0xff 0xffffffff VBAT_UV_IE VBAT undervoltage interrupt enable 0 0 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 VS_UV_IE VS undervoltage interrupt enable 1 1 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 VDD5V_UV_IE VDDP undervoltage interrupt enable 2 2 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 VDD1V5_UV_IE VDDC undervoltage interrupt enable 3 3 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 VDDEXT_UV_IE VDDEXT undervoltage interrupt enable 4 4 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 VBAT_OV_IE VBAT overvoltage interrupt enable 5 5 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 VS_OV_IE VS overvoltage interrupt enable 6 6 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 VDD5V_OV_IE VDDP overvoltage interrupt enable 7 7 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 VDD1V5_OV_IE VDDC overvoltage interrupt enable 8 8 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 VDDEXT_OV_IE VDDEXT overvoltage interrupt enable 9 9 read-write DISABLED Interrupt is disabled 0 ENABLED Interrupt is enabled 1 SYS_SUPPLY_IRQ_STS System supply interrupt status register 0x1C 32 read-write 0x0 0xffffffff VBAT_UV_IS VBAT undervoltage interrupt status 0 0 read-write NO_INTERRUPT No undervoltage interrupt occurred 0 INTERRUPT Undervoltage interrupt occurred 1 VS_UV_IS VS undervoltage interrupt status 1 1 read-write NO_INTERRUPT No undervoltage interrupt occurred 0 INTERRUPT Undervoltage interrupt occurred 1 VDD5V_UV_IS VDDP undervoltage interrupt status 2 2 read-write NO_INTERRUPT No undervoltage interrupt occurred 0 INTERRUPT Undervoltage interrupt occurred 1 VDD1V5_UV_IS VDDC undervoltage interrupt status 3 3 read-write NO_INTERRUPT No undervoltage interrupt occurred 0 INTERRUPT Undervoltage interrupt occurred 1 VDDEXT_UV_IS VDDEXT undervoltage interrupt status 4 4 read-write NO_INTERRUPT No undervoltage interrupt occurred 0 INTERRUPT Undervoltage interrupt occurred 1 VBAT_OV_IS VBAT overvoltage interrupt status 5 5 read-write NO_INTERRUPT No undervoltage interrupt occurred 0 INTERRUPT Undervoltage interrupt occurred 1 VS_OV_IS VS overvoltage interrupt status 6 6 read-write NO_INTERRUPT No undervoltage interrupt occurred 0 INTERRUPT Undervoltage interrupt occurred 1 VDD5V_OV_IS VDDP overvoltage interrupt status 7 7 read-write NO_INTERRUPT No undervoltage interrupt occurred 0 INTERRUPT Undervoltage interrupt occurred 1 VDD1V5_OV_IS VDDC overvoltage interrupt status 8 8 read-write NO_INTERRUPT No undervoltage interrupt occurred 0 INTERRUPT Undervoltage interrupt occurred 1 VDDEXT_OV_IS VDDEXT overvoltage interrupt status 9 9 read-write NO_INTERRUPT No undervoltage interrupt occurred 0 INTERRUPT Undervoltage interrupt occurred 1 VBAT_UV_STS VBAT undervoltage status 16 16 read-write NO_UNDERVOLTAGE No undervoltage occurred 0 UNDERVOLTAGE Undervoltage occurred 1 VS_UV_STS VS undervoltage status 17 17 read-write NO_UNDERVOLTAGE No undervoltage occurred 0 UNDERVOLTAGE Undervoltage occurred 1 VDD5V_UV_STS VDDP undervoltage status 18 18 read-write NO_UNDERVOLTAGE No undervoltage occurred 0 UNDERVOLTAGE Undervoltage occurred 1 VDD1V5_UV_STS VDDC undervoltage status 19 19 read-write NO_UNDERVOLTAGE No undervoltage occurred 0 UNDERVOLTAGE Undervoltage occurred 1 VDDEXT_UV_STS VDDEXT undervoltage status 20 20 read-write NO_UNDERVOLTAGE No undervoltage occurred 0 UNDERVOLTAGE Undervoltage occurred 1 VBAT_OV_STS VBAT overvoltage status 21 21 read-write NO_OVERVOLTAGE No overvoltage occurred 0 OVERVOLTAGE Overvoltage occurred 1 VS_OV_STS VS overvoltage status 22 22 read-write NO_OVERVOLTAGE No overvoltage occurred 0 OVERVOLTAGE Overvoltage occurred 1 VDD5V_OV_STS VDDP overvoltage status 23 23 read-write NO_OVERVOLTAGE No overvoltage occurred 0 OVERVOLTAGE Overvoltage occurred 1 VDD1V5_OV_STS VDDC overvoltage status 24 24 read-write NO_OVERVOLTAGE No overvoltage occurred 0 OVERVOLTAGE Overvoltage occurred 1 VDDEXT_OV_STS VDDEXT overvoltage status 25 25 read-write NO_OVERVOLTAGE No overvoltage occurred 0 OVERVOLTAGE Overvoltage occurred 1 WDT1_TRIG WDT1 watchdog control register 0x34 32 read-write 0x0 0xffffffff WDP_SEL Watchdog period selection and trigger 0 5 read-write SOW_TRIG Trigger short open window 0 WP1_1 Watchdog period {$x*16} ms ({$x}*16) 1 WP2_2 Watchdog period {$x*16} ms ({$x}*16) 2 WP3_3 Watchdog period {$x*16} ms ({$x}*16) 3 WP4_4 Watchdog period {$x*16} ms ({$x}*16) 4 WP5_5 Watchdog period {$x*16} ms ({$x}*16) 5 WP6_6 Watchdog period {$x*16} ms ({$x}*16) 6 WP7_7 Watchdog period {$x*16} ms ({$x}*16) 7 WP8_8 Watchdog period {$x*16} ms ({$x}*16) 8 WP9_9 Watchdog period {$x*16} ms ({$x}*16) 9 WP10_10 Watchdog period {$x*16} ms ({$x}*16) 10 WP11_11 Watchdog period {$x*16} ms ({$x}*16) 11 WP12_12 Watchdog period {$x*16} ms ({$x}*16) 12 WP13_13 Watchdog period {$x*16} ms ({$x}*16) 13 WP14_14 Watchdog period {$x*16} ms ({$x}*16) 14 WP15_15 Watchdog period {$x*16} ms ({$x}*16) 15 WP16_16 Watchdog period {$x*16} ms ({$x}*16) 16 WP17_17 Watchdog period {$x*16} ms ({$x}*16) 17 WP18_18 Watchdog period {$x*16} ms ({$x}*16) 18 WP19_19 Watchdog period {$x*16} ms ({$x}*16) 19 WP20_20 Watchdog period {$x*16} ms ({$x}*16) 20 WP21_21 Watchdog period {$x*16} ms ({$x}*16) 21 WP22_22 Watchdog period {$x*16} ms ({$x}*16) 22 WP23_23 Watchdog period {$x*16} ms ({$x}*16) 23 WP24_24 Watchdog period {$x*16} ms ({$x}*16) 24 WP25_25 Watchdog period {$x*16} ms ({$x}*16) 25 WP26_26 Watchdog period {$x*16} ms ({$x}*16) 26 WP27_27 Watchdog period {$x*16} ms ({$x}*16) 27 WP28_28 Watchdog period {$x*16} ms ({$x}*16) 28 WP29_29 Watchdog period {$x*16} ms ({$x}*16) 29 WP30_30 Watchdog period {$x*16} ms ({$x}*16) 30 WP31_31 Watchdog period {$x*16} ms ({$x}*16) 31 WP32_32 Watchdog period {$x*16} ms ({$x}*16) 32 WP33_33 Watchdog period {$x*16} ms ({$x}*16) 33 WP34_34 Watchdog period {$x*16} ms ({$x}*16) 34 WP35_35 Watchdog period {$x*16} ms ({$x}*16) 35 WP36_36 Watchdog period {$x*16} ms ({$x}*16) 36 WP37_37 Watchdog period {$x*16} ms ({$x}*16) 37 WP38_38 Watchdog period {$x*16} ms ({$x}*16) 38 WP39_39 Watchdog period {$x*16} ms ({$x}*16) 39 WP40_40 Watchdog period {$x*16} ms ({$x}*16) 40 WP41_41 Watchdog period {$x*16} ms ({$x}*16) 41 WP42_42 Watchdog period {$x*16} ms ({$x}*16) 42 WP43_43 Watchdog period {$x*16} ms ({$x}*16) 43 WP44_44 Watchdog period {$x*16} ms ({$x}*16) 44 WP45_45 Watchdog period {$x*16} ms ({$x}*16) 45 WP46_46 Watchdog period {$x*16} ms ({$x}*16) 46 WP47_47 Watchdog period {$x*16} ms ({$x}*16) 47 WP48_48 Watchdog period {$x*16} ms ({$x}*16) 48 WP49_49 Watchdog period {$x*16} ms ({$x}*16) 49 WP50_50 Watchdog period {$x*16} ms ({$x}*16) 50 WP51_51 Watchdog period {$x*16} ms ({$x}*16) 51 WP52_52 Watchdog period {$x*16} ms ({$x}*16) 52 WP53_53 Watchdog period {$x*16} ms ({$x}*16) 53 WP54_54 Watchdog period {$x*16} ms ({$x}*16) 54 WP55_55 Watchdog period {$x*16} ms ({$x}*16) 55 WP56_56 Watchdog period {$x*16} ms ({$x}*16) 56 WP57_57 Watchdog period {$x*16} ms ({$x}*16) 57 WP58_58 Watchdog period {$x*16} ms ({$x}*16) 58 WP59_59 Watchdog period {$x*16} ms ({$x}*16) 59 WP60_60 Watchdog period {$x*16} ms ({$x}*16) 60 WP61_61 Watchdog period {$x*16} ms ({$x}*16) 61 WP62_62 Watchdog period {$x*16} ms ({$x}*16) 62 WP63_63 Watchdog period {$x*16} ms ({$x}*16) 63 SOWCONF Short open window configuration 6 7 read-write DIS Short open windows disabled 0 SOW1 One successive short open window allowed 1 SOW2 Two successive short open windows allowed 2 SOW3 Three successive short open windows allowed 3 SSC1 100 High-Speed Synchronous Serial Interface SSC1 registers SSC1 0x48024000 0 0x2000 registers BR Baud-rate timer reload register 0x10 32 read-write 0x0 0xffffffff BR_VALUE Baud rate timer/reload register value 0 15 read-write CON Control register 0x4 32 read-write 0x0 0xffffffff BM Data width selection 0 3 read-write Const_1 Const_1 1 Transfer_data Transfer datawidth is 2 ... 16 bits (BM + 1) 15 HB Heading control 4 4 read-write LSB Transmit/Receive LSB first 0 MSB Transmit/Receive MSB first 1 PH Clock phase control 5 5 read-write SHIFT Transmit data on the leading clock edge, latch on trailing edge 0 LATCH Receive data on leading clock edge, shift on trailing edge 1 PO Clock polarity control 6 6 read-write LOW Idle clock line is low, leading clock edge is low-to-high transition 0 HIGH Idle clock line is high, leading clock edge is high-to-low transition 1 LB Loop back control 7 7 read-write NORMAL Output 0 LB Receive input is connected with transmit output (half-duplex mode) 1 TEN Transmit error enable 8 8 read-write IGNORE Transmit errors 0 CHECK Transmit errors 1 REN Receive error enable 9 9 read-write IGNORE Receive errors 0 CHECK Receive errors 1 PEN Phase error enable 10 10 read-write IGNORE Phase errors 0 CHECK Phase errors 1 BEN Baud rate error enable 11 11 read-write IGNORE Baud rate errors 0 CHECK Baud rate errors 1 AREN Automatic reset enable 12 12 read-write N_A No additional action upon a baud rate error 0 RESET The SSC is automatically reset upon a baud rate error 1 MS Master select 14 14 read-write SLAVE Slave mode. Operate on shift clock received through SCLK 0 MASTER Master mode. Generate shift clock and output it through SCLK 1 EN Enable bit 15 15 read-write Programming_mode Transmission and reception disabled. Access to control bits 0 Operating_mode Transmission and reception enabled. Access to status flags and M/S control 1 BC Bit count field 16 19 read-only TE Transmit error flag 24 24 read-only NO Error 0 ERROR Transfer starts with the slave's transmit buffer not being updated 1 RE Receive error flag 25 25 read-only NO Error 0 ERROR Reception completed before the receive buffer was read 1 PE Phase error flag 26 26 read-only NO Error 0 ERROR Received data changes around sampling clock edge 1 BE Baud rate error flag 27 27 read-only NO Error 0 ERROR More than factor 2 or 0.5 between slave's actual and expected baud rate 1 BSY Busy flag 28 28 read-only ISRCLR Interrupt status register clear 0x14 32 read-write 0x0 0xffffffff TECLR Transmit error flag clear 8 8 write-only NO No error clear 0 CLEAR Error clear 1 RECLR Receive error flag clear 9 9 write-only NO No error clear 0 CLEAR Error clear 1 PECLR Phase error flag clear 10 10 write-only NO No error clear 0 CLEAR Error clear 1 BECLR Baud rate error flag clear 11 11 write-only NO No error clear 0 CLEAR Error clear 1 PISEL Port input select register 0x0 32 read-write 0x0 0xffffffff MIS_0 Master mode input select bit 0 (master mode only) 0 0 read-write SSCx_M_MRST (x = 1 or 2, dependent form current SSC) 0 SSC12_M_MRST For both SSCs 1 SIS Slave mode input select (slave mode only) 1 1 read-write SSCx_S_MTSR (x = 1 or 2, dependent form current SSC) 0 SSC12_S_MTSR For both SSCs 1 CIS Clock input select (slave mode only) 2 2 read-write SSCx_S_SCK (x = 1 or 2, dependent form current SSC) 0 SSC12_S_SCK For both SSCs 1 MIS_1 Master mode input select bit 1 (master mode only) 3 3 read-write Default Inputs selected according to MIS_0 0 Do_not_use Connects to unused pins 1 RB Receiver buffer register 0xC 32 read-only 0x0 0xffffffff RB_VALUE Receive data register value 0 15 read-only TB Transmitter buffer register 0x8 32 read-write 0x0 0xffffffff TB_VALUE Transmit data register value 0 15 read-write SSC2 100 High-Speed Synchronous Serial Interface SSC2 registers SSC2 0x48026000 0 0x2000 registers BR Baud-rate timer reload register 0x10 32 read-write 0x0 0xffffffff BR_VALUE Baud rate timer/reload register value 0 15 read-write CON Control register 0x4 32 read-write 0x0 0xffffffff BM Data width selection 0 3 read-write Const_1 Const_1 1 Transfer_data Transfer datawidth is 2 ... 16 bits (BM + 1) 15 HB Heading control 4 4 read-write LSB Transmit/Receive LSB first 0 MSB Transmit/Receive MSB first 1 PH Clock phase control 5 5 read-write SHIFT Transmit data on the leading clock edge, latch on trailing edge 0 LATCH Receive data on leading clock edge, shift on trailing edge 1 PO Clock polarity control 6 6 read-write LOW Idle clock line is low, leading clock edge is low-to-high transition 0 HIGH Idle clock line is high, leading clock edge is high-to-low transition 1 LB Loop back control 7 7 read-write NORMAL Output 0 LB Receive input is connected with transmit output (half-duplex mode) 1 TEN Transmit error enable 8 8 read-write IGNORE Transmit errors 0 CHECK Transmit errors 1 REN Receive error enable 9 9 read-write IGNORE Receive errors 0 CHECK Receive errors 1 PEN Phase error enable 10 10 read-write IGNORE Phase errors 0 CHECK Phase errors 1 BEN Baud rate error enable 11 11 read-write IGNORE Baud rate errors 0 CHECK Baud rate errors 1 AREN Automatic reset enable 12 12 read-write N_A No additional action upon a baud rate error 0 RESET The SSC is automatically reset upon a baud rate error 1 MS Master select 14 14 read-write SLAVE Slave mode. Operate on shift clock received through SCLK 0 MASTER Master mode. Generate shift clock and output it through SCLK 1 EN Enable bit 15 15 read-write Programming_mode Transmission and reception disabled. Access to control bits 0 Operating_mode Transmission and reception enabled. Access to status flags and M/S control 1 BC Bit count field 16 19 read-only TE Transmit error flag 24 24 read-only NO Error 0 ERROR Transfer starts with the slave's transmit buffer not being updated 1 RE Receive error flag 25 25 read-only NO Error 0 ERROR Reception completed before the receive buffer was read 1 PE Phase error flag 26 26 read-only NO Error 0 ERROR Received data changes around sampling clock edge 1 BE Baud rate error flag 27 27 read-only NO Error 0 ERROR More than factor 2 or 0.5 between slave's actual and expected baud rate 1 BSY Busy flag 28 28 read-only ISRCLR Interrupt status register clear 0x14 32 read-write 0x0 0xffffffff TECLR Transmit error flag clear 8 8 write-only NO No error clear 0 CLEAR Error clear 1 RECLR Receive error flag clear 9 9 write-only NO No error clear 0 CLEAR Error clear 1 PECLR Phase error flag clear 10 10 write-only NO No error clear 0 CLEAR Error clear 1 BECLR Baud rate error flag clear 11 11 write-only NO No error clear 0 CLEAR Error clear 1 PISEL Port input select register 0x0 32 read-write 0x0 0xffffffff MIS_0 Master mode input select bit 0 (master mode only) 0 0 read-write SSCx_M_MRST (x = 1 or 2, dependent form current SSC) 0 SSC12_M_MRST For both SSCs 1 SIS Slave mode input select (slave mode only) 1 1 read-write SSCx_S_MTSR (x = 1 or 2, dependent form current SSC) 0 SSC12_S_MTSR For both SSCs 1 CIS Clock input select (slave mode only) 2 2 read-write SSCx_S_SCK (x = 1 or 2, dependent form current SSC) 0 SSC12_S_SCK For both SSCs 1 MIS_1 Master mode input select bit 1 (master mode only) 3 3 read-write Default Inputs selected according to MIS_0 0 Do_not_use Connects to unused pins 1 RB Receiver buffer register 0xC 32 read-only 0x0 0xffffffff RB_VALUE Receive data register value 0 15 read-only TB Transmitter buffer register 0x8 32 read-write 0x0 0xffffffff TB_VALUE Transmit data register value 0 15 read-write TIMER2 100 Timer2 registers TIMER2 0x48004000 0 0x1000 registers CNT Timer2 count register 0x10 32 read-write 0x0 0xffffffff T2L Timer2 value 0 7 read-write T2H Timer2 value 8 15 read-write CON Timer2 control register 0x0 32 read-write 0x0 0xffffffff CP_RL2 Capture/reload select 0 0 read-write Reload Upon overflow or upon negative/positive transition at pin T2EX (when EXEN2 = 1) 0 Capture Timer2 data register contents on the negative/positive transition at pin T2EX, provided EXEN2 = 1. The negative or positive transition at pin is selected by bit EDGESEL 1 C_T2 Timer or counter select 1 1 read-write Timer Function selected 0 Count Upon negative edge at pin T2 1 TR2 Timer2 start/stop control 2 2 read-write STOP Timer2 0 START Timer2 1 EXEN2 Timer2 external enable control 3 3 read-write DISABLED External events are disabled 0 ENABLED External events are enabled in capture/reload 1 EXF2 Timer2 external flag 6 6 read-only TF2 Timer2 overflow/underflow flag 7 7 read-only CON1 Timer2 control 1 register 0x1C 32 read-write 0x3 0xffffffff EXF2EN External interrupt enable 0 0 read-write DISABLE External interrupt 0 ENABLE External interrupt 1 TF2EN Overflow/underflow interrupt enable 1 1 read-write DISABLE Overflow/underflow interrupt 0 ENABLE Overflow/underflow interrupt 1 ICLR Timer2 interrupt clear register 0x18 32 read-write 0x0 0xffffffff EXF2CLR External interrupt clear flag 6 6 write-only N_A External interrupt is not cleared 0 Clear External interrupt 1 TF2CLR Overflow/underflow interrupt clear flag 7 7 write-only N_A Overflow/underflow interrupt is not cleared 0 Clear Overflow/underflow interrupt 1 MOD Timer2 mode register 0x4 32 read-write 0x0 0xffffffff DCEN Up/down counter enable 0 0 read-write DISABLED Up/down counter function is disabled 0 ENABLED Up/down counter function is enabled and controlled by pin T2EX (up = 1, down = 0) 1 T2PRE Timer2 prescaler bit 1 3 read-write DIV1 fT2=fSYS 0 DIV2 fT2=fSYS/2 1 DIV4 DfT2=fSYS/4 2 DIV8 fT2=fSYS/8 3 DIV16 fT2=fSYS/16 4 DIV32 fT2=fSYS/32 5 DIV64 fT2=fSYS/64 6 DIV128 fT2=fSYS/128 7 PREN Prescaler enable 4 4 read-write DISABLED Prescaler is disabled and the 2 or 12 divider takes effect 0 ENABLED Prescaler is enabled (see T2PRE bit) and the 2 or 12 divider is bypassed 1 EDGESEL Edge select in capture mode/reload mode 5 5 read-write FALLING The falling edge at Pin T2EX is selected 0 RISING The rising edge at Pin T2EX is selected 1 T2RHEN Timer2 external start enable 6 6 read-write DISABLED Timer2 external start is disabled 0 ENABLED Timer2 external start is enabled 1 T2REGS Edge select for Timer2 external start 7 7 read-write FALLING The falling edge at pin T2EX is selected 0 RISING The rising edge at Pin T2EX is selected 1 RC Timer2 reload/capture register 0x8 32 read-write 0x0 0xffffffff RCL2 Reload/capture value 0 7 read-write RCH2 Reload/capture value 8 15 read-write TIMER21 100 Timer21 registers TIMER21 0x48005000 0 0x1000 registers CNT Timer2 count register 0x10 32 read-write 0x0 0xffffffff T2L Timer2 value 0 7 read-write T2H Timer2 value 8 15 read-write CON Timer2 control register 0x0 32 read-write 0x0 0xffffffff CP_RL2 Capture/reload select 0 0 read-write Reload Upon overflow or upon negative/positive transition at pin T2EX (when EXEN2 = 1) 0 Capture Timer2 data register contents on the negative/positive transition at pin T2EX, provided EXEN2 = 1. The negative or positive transition at pin is selected by bit EDGESEL 1 C_T2 Timer or counter select 1 1 read-write Timer Function selected 0 Count Upon negative edge at pin T2 1 TR2 Timer2 start/stop control 2 2 read-write STOP Timer2 0 START Timer2 1 EXEN2 Timer2 external enable control 3 3 read-write DISABLED External events are disabled 0 ENABLED External events are enabled in capture/reload 1 EXF2 Timer2 external flag 6 6 read-only TF2 Timer2 overflow/underflow flag 7 7 read-only CON1 Timer2 control 1 register 0x1C 32 read-write 0x3 0xffffffff EXF2EN External interrupt enable 0 0 read-write DISABLE External interrupt 0 ENABLE External interrupt 1 TF2EN Overflow/underflow interrupt enable 1 1 read-write DISABLE Overflow/underflow interrupt 0 ENABLE Overflow/underflow interrupt 1 ICLR Timer2 interrupt clear register 0x18 32 read-write 0x0 0xffffffff EXF2CLR External interrupt clear flag 6 6 write-only N_A External interrupt is not cleared 0 Clear External interrupt 1 TF2CLR Overflow/underflow interrupt clear flag 7 7 write-only N_A Overflow/underflow interrupt is not cleared 0 Clear Overflow/underflow interrupt 1 MOD Timer2 mode register 0x4 32 read-write 0x0 0xffffffff DCEN Up/down counter enable 0 0 read-write DISABLED Up/down counter function is disabled 0 ENABLED Up/down counter function is enabled and controlled by pin T2EX (up = 1, down = 0) 1 T2PRE Timer2 prescaler bit 1 3 read-write DIV1 fT2=fSYS 0 DIV2 fT2=fSYS/2 1 DIV4 DfT2=fSYS/4 2 DIV8 fT2=fSYS/8 3 DIV16 fT2=fSYS/16 4 DIV32 fT2=fSYS/32 5 DIV64 fT2=fSYS/64 6 DIV128 fT2=fSYS/128 7 PREN Prescaler enable 4 4 read-write DISABLED Prescaler is disabled and the 2 or 12 divider takes effect 0 ENABLED Prescaler is enabled (see T2PRE bit) and the 2 or 12 divider is bypassed 1 EDGESEL Edge select in capture mode/reload mode 5 5 read-write FALLING The falling edge at Pin T2EX is selected 0 RISING The rising edge at Pin T2EX is selected 1 T2RHEN Timer2 external start enable 6 6 read-write DISABLED Timer2 external start is disabled 0 ENABLED Timer2 external start is enabled 1 T2REGS Edge select for Timer2 external start 7 7 read-write FALLING The falling edge at pin T2EX is selected 0 RISING The rising edge at Pin T2EX is selected 1 RC Timer2 reload/capture register 0x8 32 read-write 0x0 0xffffffff RCL2 Reload/capture value 0 7 read-write RCH2 Reload/capture value 8 15 read-write TRX 100 Transceiver registers TRX 0x4801E000 0 0x2000 registers CTRL Transceiver control register 0x0 32 read-write 0x180007 0xffff00ff MODE Transceiver power mode control 1 2 read-write SLEEP Tranceiver module switched to Sleep mode 0 RECEIVE_ONLY Tranceiver module switched to Receive-Only mode 1 NORMAL Tranceiver module switched to Normal mode 3 MODE_FB Transmitter feedback signals settings [2:1] 4 6 read-only ERROR Mode error 0 SLEEP Transceiver Sleep mode 1 ERROR Mode error 2 ERROR Mode error 3 ERROR Mode error 4 RECEIVE_ONLY Transceiver Receive-Only mode 5 ERROR Mode error 6 NORMAL Transceiver Normal mode 7 TXD Transmitter state (only used when HV_MODE is set) 9 9 read-write DOMINANT_STATE Transmitter switched on 0 RECESSIVE_STATE Transmitter switched off 1 RXD Reveiver output signal 10 10 read-only SM Transmitter slope mode control 11 12 read-write NORMAL Normal slope mode 0 FAST Fast slope mode 1 LOW Low slope mode 2 FLASH Flash mode 3 FB_SM Feedback signal for slope mode setting [3:1] 13 15 read-only DISABLED Transceiver module not enabled 0 LOW Low slope mode 1 NORMAL Normal slope mode 2 FAST Fast slope mode 3 FLASH Flash mode 4 ERROR Slope mode error 5 ERROR Slope mode error 6 ERROR Slope mode error 7 HV_MODE Transceiver high-voltage I/O mode 21 21 read-write DISABLED High-voltage mode entry disabled 0 ENABLED High-voltage mode entry enabled 1 IRQCLR Transceiver interrupt status rclear register 0x8 32 read-write 0x0 0xffffffff M_SM_ERR_ISC Transceiver mode error - slope mode error interrupt status clear 3 3 write-only NO_CLR Overtemperature not cleared 0 CLR Overtemperature cleared 1 OT_ISC Tranceiver overtemperature interrupt status / status clear 4 4 write-only NO_CLR Overtemperature not cleared 0 CLR Overtemperature cleared 1 OC_ISC Tranceiver overcurrent interrupt status clear 5 5 write-only NO_CLR Overcurrent status not cleared 0 CLR Overcurrent status cleared 1 TXD_TMOUT_ISC Transceiver TXD timeout interrupt status clear 6 6 write-only NO_CLR No timeout cleared 0 CLR Timeout cleared 1 M_SM_ERR_SC Transceiver mode error - slope mode error status clear 8 8 write-only NO_CLR Overtemperature not cleared 0 CLR Overtemperature cleared 1 OT_SC Tranceiver overtemperature status clear 9 9 write-only NO_CLR Overtemperature not cleared 0 CLR Overtemperature cleared 1 TXD_TMOUT_SC Transceiver TXD timeout status clear 11 11 write-only NO_CLR No timeout cleared 0 CLR Timeout cleared 1 IRQEN Transceiver interrupt enable register 0xC 32 read-write 0x0 0xffffffff M_SM_ERR_IEN Transceiver mode error - slope mode error interrupt 3 3 read-write DISABLED Disabled 0 ENABLED Enabled 1 OT_IEN Transceiver overtemperature interrupt 4 4 read-write DISABLED Disabled 0 ENABLED Enabled 1 OC_IEN Transceiver overcurrent interrupt 5 5 read-write DISABLED Disabled 0 ENABLED Enabled 1 TXD_TMOUT_IEN Transceiver TxD-timeout interrupt 6 6 read-write DISABLED Disabled 0 ENABLED Enabled 1 IRQS Transceiver interrupt status register 0x4 32 read-write 0x0 0xffffffff M_SM_ERR_IS Transceiver mode error - slope mode error interrupt status 3 3 read-write NO_ERROR No mode error slope mode status occurred 0 ERROR Mode error status occurred 1 OT_IS Transceiver overtemperature interrupt status 4 4 read-write NO_OT No overtemperature occurred 0 OT Overtemperature occurred 1 OC_IS Transceiver overcurrent interrupt status 5 5 read-write NO_OC No overcurrent status occurred 0 OC Overcurrent status occurred 1 TXD_TMOUT_IS Transceiver TXD timeout interrupt status 6 6 read-write NO_TMOUT No timeout occurred 0 TMOUT Timeout occurred 1 M_SM_ERR_STS Transceiver mode error - slope mode error status 8 8 read-write NO_ERROR No mode error slope mode status occurred 0 ERROR Mode error status occurred 1 OT_STS Transceiver overtemperature status 9 9 read-write NO_OT No overtemperature occurred 0 OT Overtemperature occurred 1 TXD_TMOUT_STS Transceiver TXD timeout status 11 11 read-write NO_TMOUT No timeout occurred 0 TMOUT Timeout occurred 1 UART1 100 UART1 registers UART1 0x48020000 0 0x2000 registers SBUF Serial data buffer register 0x4 32 read-write 0x0 0xffffffff VAL Serial interface buffer register 0 7 read-write SCON Serial channel control register 0x0 32 read-write 0x0 0xffffffff RI Receive interrupt flag 0 0 read-write TI Transmit interrupt flag 1 1 read-write RB8 Serial port receiver bit 9 2 2 read-write TB8 Serial port transmitter bit 9 3 3 read-write REN Enable receiver of serial port 4 4 read-write DISABLE Serial reception is disabled 0 ENABLE Serial reception is enabled 1 SM2 Enable serial port multiprocessor communication in modes 2 and 3 5 5 read-write SM1 Serial port operating mode selection 6 6 read-write SM0 Serial port operating mode selection 7 7 read-write SCONCLR Serial channel control clear register 0x8 32 read-write 0x0 0xffffffff RICLR SCON.RI clear flag 0 0 write-only Not_cleared RI flag is not cleared 0 Cleared RI flag is cleared 1 TICLR SCON.TI clear flag 1 1 write-only Not_cleared TI flag is not cleared 0 Cleared TI flag is cleared 1 RB8CLR SCON.RB8 clear flag 2 2 write-only Not_cleared RB8 flag is not cleared 0 Cleared RB8 flag is cleared 1 UART2 100 UART2 registers UART2 0x48022000 0 0x2000 registers SBUF Serial data buffer register 0x4 32 read-write 0x0 0xffffffff VAL Serial interface buffer register 0 7 read-write SCON Serial channel control register 0x0 32 read-write 0x0 0xffffffff RI Receive interrupt flag 0 0 read-write TI Transmit interrupt flag 1 1 read-write RB8 Serial port receiver bit 9 2 2 read-write TB8 Serial port transmitter bit 9 3 3 read-write REN Enable receiver of serial port 4 4 read-write DISABLE Serial reception is disabled 0 ENABLE Serial reception is enabled 1 SM2 Enable serial port multiprocessor communication in modes 2 and 3 5 5 read-write SM1 Serial port operating mode selection 6 6 read-write SM0 Serial port operating mode selection 7 7 read-write SCONCLR Serial channel control clear register 0x8 32 read-write 0x0 0xffffffff RICLR SCON.RI clear flag 0 0 write-only Not_cleared RI flag is not cleared 0 Cleared RI flag is cleared 1 TICLR SCON.TI clear flag 1 1 write-only Not_cleared TI flag is not cleared 0 Cleared TI flag is cleared 1 RB8CLR SCON.RB8 clear flag 2 2 write-only Not_cleared RB8 flag is not cleared 0 Cleared RB8 flag is cleared 1