S6E1A1 1.2 S6E1A1 Series 8 32 32 read-write 0x00000000 0x00000000 FLASH_IF Flash Memory FLASH_IF 0x40000000 0x4 0x1 registers 0x8 0x1 registers 0x10 0x1 registers 0x20 0x1 registers 0x24 0x1 registers 0x28 0x1 registers 0x100 0x4 registers BTIM0_3_FLASH 31 FRWTR Flash Read Wait Register 0x4 8 read-write 0x01 0x03 RWT Read Wait Cycle 0 1 read-write FSTR Flash Status Register 0x8 8 read-only 0x00 0x3F PGMS Flash Program Status 5 5 read-only SERS Flash Sector Erase Status 4 4 read-only ESPS Flash Erase Suspend Status 3 3 read-only CERS Flash Chip Erase Status 2 2 read-only HNG Flash Hang Status 1 1 read-only RDY Flash Ready Status 0 0 read-only FSYNDN Flash Sync Down Register 0x10 8 read-write 0x01 0x0F SD Sync Down 0 3 read-write FICR Flash Interrupt Control Register 0x20 8 read-write 0x00 0x03 HANGIE HANG Interrupt Enable 1 1 read-write RDYIE RDY Interrupt Enable 0 0 read-write FISR Flash Interrupt Status Register 0x24 8 read-write 0x00 0x03 HANGIF HANG Interrupt Flag 1 1 read-write RDYIF RDY Interrupt Flag 0 0 read-write FICLR Flash Interrupt Clear Register 0x28 8 write-only 0x00 0x03 HANGIC HANG Interrupt Clear 1 1 write-only RDYIC RDY Interrupt Clear 0 0 write-only CRTRMM CR Trimming Data Mirror Register 0x100 32 read-only 0x00000000 0x001F03FF TTRMM CR Temperature Trimming Data Mirror Bit 16 20 read-only TRMM CR Trimming Data Mirror Bit 0 9 read-only UNIQUE_ID Unique ID UNIQUE_ID 0x40000200 0x0 0x4 registers 0x4 0x4 registers UIDR0 Unique ID Register 0 0x0 32 read-only 0x00000000 0xFFFFFFF0 UID Unique ID 27 through Unique ID 0 4 31 read-only UIDR1 Unique ID Register 1 0x4 32 read-only 0x00000000 0x00001FFF UID Unique ID 40 through Unique ID 28 0 12 read-only CLOCK Clock Unit Registers CLOCK 0x40010000 0x0 0x1 registers 0x4 0x1 registers 0x8 0x4 registers 0xC 0x2 registers 0x10 0x1 registers 0x14 0x1 registers 0x18 0x1 registers 0x20 0x1 registers 0x30 0x1 registers 0x34 0x1 registers 0x38 0x1 registers 0x3C 0x1 registers 0x40 0x2 registers 0x44 0x1 registers 0x48 0x2 registers 0x4C 0x2 registers 0x50 0x2 registers 0x54 0x1 registers 0x60 0x1 registers 0x64 0x1 registers 0x68 0x1 registers CSV 0 OSC_PLL_WC_RTC 24 SCM_CTL System Clock Mode Control Register 0x0 8 read-write 0x01 0xFB RCS Master clock switch control bits 5 7 read-write PLLE PLL oscillation enable bit 4 4 read-write SOSCE Sub clock oscillation enable bit 3 3 read-write MOSCE Main clock oscillation enable bit 1 1 read-write HCRE High-speed CR clock oscillation enable bit 0 0 read-write SCM_STR System Clock Mode Status Register 0x4 8 read-only 0x01 0xFB RCM Master clock selection bits 5 7 read-only PLRDY PLL oscillation stable bit 4 4 read-only SORDY Sub clock oscillation stable bit 3 3 read-only MORDY Main clock oscillation stable bit 1 1 read-only HCRDY High-speed CR clock oscillation stable bit 0 0 read-only BSC_PSR Base Clock Prescaler Register 0x10 8 read-write 0x00 0x07 BSR Base clock frequency division ratio setting bits 0 2 read-write APBC0_PSR APB0 Prescaler Register 0x14 8 read-write 0x00 0x03 APBC0 APB0 bus clock frequency division ratio setting bits 0 1 read-write APBC1_PSR APB1 Prescaler Register 0x18 8 read-write 0x80 0x93 APBC1EN APB1 clock enable bit 7 7 read-write APBC1RST APB1 bus reset control bit 4 4 read-write APBC1 APB1 bus clock frequency division ratio setting bits 0 1 read-write SWC_PSR Software Watchdog Clock Prescaler Register 0x20 8 read-write 0x00 0x83 TESTB TEST bit 7 7 read-write SWDS Software watchdog clock frequency division ratio setting bits 0 1 read-write CSW_TMR Clock Stabilization Wait Time Register 0x30 8 read-write 0x00 0xFF SOWT Sub clock stabilization wait time setup bits 4 7 read-write MOWT Main clock stabilization wait time setup bits 0 3 read-write PSW_TMR PLL Clock Stabilization Wait Time Setup Register 0x34 8 read-write 0x00 0x17 PINC PLL input clock select bit 4 4 read-write POWT Main PLL clock stabilization wait time setup bits 0 2 read-write PLL_CTL1 PLL Control Register 1 0x38 8 read-write 0x00 0xFF PLLK PLL input clock frequency division ratio setting bits 4 7 read-write PLLM PLL VCO clock frequency division ratio setting bits 0 3 read-write PLL_CTL2 PLL Control Register 2 0x3C 8 read-write 0x00 0x3F PLLN PLL feedback frequency division ratio setting bits 0 5 read-write DBWDT_CTL Debug Break Watchdog Timer Control Register 0x54 8 read-write 0x00 0xA0 DPHWBE HW-WDG debug mode break bit 7 7 read-write DPSWBE SW-WDG debug mode break bit 5 5 read-write INT_ENR Interrupt Enable Register 0x60 8 read-write 0x00 0x27 FCSE Anomalous frequency detection interrupt enable bit 5 5 read-write PCSE PLL oscillation stabilization wait completion interrupt enable bit 2 2 read-write SCSE Sub clock oscillation stabilization wait completion interrupt enable bit 1 1 read-write MCSE Main clock oscillation stabilization wait completion interrupt enable bit 0 0 read-write INT_STR Interrupt Status Register 0x64 8 read-only 0x00 0x27 FCSI Anomalous frequency detection interrupt status bit 5 5 read-only PCSI PLL oscillation stabilization wait completion interrupt status bit 2 2 read-only SCSI Sub clock oscillation stabilization wait completion interrupt status bit 1 1 read-only MCSI Main clock oscillation stabilization wait completion interrupt status bit 0 0 read-only INT_CLR Interrupt Clear Register 0x68 8 write-only 0x00 0x27 FCSC Anomalous frequency detection interrupt factor clear bit 5 5 write-only PCSC PLL oscillation stabilization wait completion interrupt factor clear bit 2 2 write-only SCSC Sub clock oscillation stabilization wait completion interrupt factor clear bit 1 1 write-only MCSC Main clock oscillation stabilization wait completion interrupt factor clear bit 0 0 write-only STB_CTL Standby Mode Control Register 0x8 32 read-write 0x00000000 0xFFFF0017 KEY Standby mode control write control bits 16 31 read-write SPL Standby pin level setting bit 4 4 read-write DSTM Deep standby mode select bit 2 2 read-write STM Standby mode selection bits 0 1 read-write RST_STR Reset Cause Register 0xC 16 read-only 0x0001 0x01F3 SRST Software reset flag 8 8 read-only FCSR Flag for anomalous frequency detection reset 7 7 read-only CSVR Clock failure detection reset flag 6 6 read-only HWDT Hardware watchdog reset flag 5 5 read-only SWDT Software watchdog reset flag 4 4 read-only INITX INITX pin input reset flag 1 1 read-only PONR Power-on reset/low-voltage detection reset flag 0 0 read-only CSV_CTL CSV control register 0x40 16 read-write 0x7003 0x7303 FCD FCS count cycle setting bits 12 14 read-write FCSRE FCS reset output enable bit 9 9 read-write FCSDE FCS function enable bit 8 8 read-write SCSVE Sub CSV function enable bit 1 1 read-write MCSVE Main CSV function enable bit 0 0 read-write CSV_STR CSV status register 0x44 8 read-only 0x00 0x03 SCMF Sub clock failure detection flag 1 1 read-only MCMF Main clock failure detection flag 0 0 read-only FCSWH_CTL Frequency detection window setting register 0x48 16 read-write 0xFFFF 0xFFFF FWH Frequency detection window setting bits (Upper) 0 15 read-write FCSWL_CTL Frequency detection window setting register 0x4C 16 read-write 0x0000 0xFFFF FWL Frequency detection window setting bits (Lower) 0 15 read-write FCSWD_CTL Frequency detection counter register 0x50 16 read-only 0x0000 0xFFFF FWD Frequency detection count data 0 15 read-only HWWDT Hardware Watchdog Timer HWWDT 0x40011000 0x0 0x4 registers 0x4 0x4 registers 0x8 0x1 registers 0xC 0x1 registers 0x10 0x1 registers 0xC00 0x4 registers WDG_LDR Hardware Watchdog Timer Load Register 0x0 32 read-write 0x0000FFFF 0xFFFFFFFF WDG_VLR Hardware Watchdog Timer Value Register 0x4 32 read-only 0x00000000 0xFFFFFFFF WDG_CTL Hardware Watchdog Timer Control Register 0x8 8 read-write 0x03 0x03 RESEN Hardware watchdog reset enable bit 1 1 read-write INTEN Hardware watchdog interrupt and counter enable bit 0 0 read-write WDG_ICL Hardware Watchdog Timer Clear Register 0xC 8 read-write 0x00 0xFF WDG_RIS Hardware Watchdog Timer Interrupt Status Register 0x10 8 read-only 0x00 0x01 RIS Hardware watchdog interrupt status bit 0 0 read-only WDG_LCK Hardware Watchdog Timer Lock Register 0xC00 32 read-write 0x00000001 0xFFFFFFFF SWWDT Software Watchdog Timer SWWDT 0x40012000 0x0 0x4 registers 0x4 0x4 registers 0x8 0x1 registers 0xC 0x4 registers 0x10 0x1 registers 0x18 0x1 registers 0xC00 0x4 registers SWDT 1 WDOGLOAD Software Watchdog Timer Load Register 0x0 32 read-write 0xFFFFFFFF 0xFFFFFFFF WDOGVALUE Software Watchdog Timer Value Register 0x4 32 read-only 0xFFFFFFFF 0xFFFFFFFF WDOGCONTROL Software Watchdog Timer Control Register 0x8 8 read-write 0x00 0x1F SPM Software Watchdog window watchdog mode enable bit 4 4 read-write TWD Timing window setting bit of the software watchdog 2 3 read-write RESEN Reset enable bit of the software watchdog 1 1 read-write INTEN Interrupt and counter enable bit of the software watchdog 0 0 read-write WDOGINTCLR Software Watchdog Timer Clear Register 0xC 32 read-write 0x00000000 0xFFFFFFFF WDOGRIS Software Watchdog Timer Interrupt Status Register 0x10 8 read-only 0x00 0x01 RIS Software watchdog interrupt status bit 0 0 read-only WDOGSPMC Software Watchdog Timer Window Watchdog Mode Control Register 0x18 8 read-write 0x00 0x01 TGR Software watchdog trigger type bit 0 0 read-write WDOGLOCK Software Watchdog Timer Lock Register 0xC00 32 read-write 0x00000000 0xFFFFFFFF DTIM Dual Timer DTIM 0x40015000 0x0 0x1C registers 0x20 0x1C registers DTIM_QDU 6 TIMER1LOAD Load Register DualTimer1 0x0 32 read-write 0x00000000 0xFFFFFFFF TIMER1VALUE Value Register 0x4 32 read-only 0xFFFFFFFF 0xFFFFFFFF TIMER1CONTROL Control Register 0x8 32 read-write 0x00000020 0x000000EF TimerEn Enable bit 7 7 read-write TimerMode Mode bit 6 6 read-write IntEnable Interrupt enable bit 5 5 read-write TimerPre Prescale bits 2 3 read-write TimerSize Counter size bit 1 1 read-write OneShot One-shot mode bit 0 0 read-write TIMER1INTCLR Interrupt Clear Register 0xC 32 write-only 0x00000000 0xFFFFFFFF TIMER1RIS Interrupt Status Register 0x10 32 read-only 0x00000000 0x00000001 TIMER1RIS Interrupt Status Register bit 0 0 read-only TIMER1MIS Masked Interrupt Status Register 0x14 32 read-only 0x00000000 0x00000001 TIMER1MIS Masked Interrupt Status bit 0 0 read-only TIMER1BGLOAD Background Load Register 0x18 32 read-write 0x00000000 0xFFFFFFFF TIMER2LOAD Load Register 0x20 TIMER2VALUE Value Register 0x24 TIMER2CONTROL Control Register 0x28 TIMER2INTCLR Interrupt Clear Register 0x2C TIMER2RIS Interrupt Status Register 0x30 TIMER2MIS Masked Interrupt Status Register 0x34 TIMER2BGLOAD Background Load Register 0x38 MFT0 Multifunction Timer 0 MFT0 0x40020000 0x102 0x2 registers 0x106 0x2 registers 0x10A 0x2 registers 0x10E 0x2 registers 0x112 0x2 registers 0x116 0x2 registers 0x118 0x3 registers 0x11C 0x3 registers 0x120 0x3 registers 0x125 0x1 registers 0x128 0x2 registers 0x12C 0x4 registers 0x130 0x2 registers 0x134 0x4 registers 0x138 0x2 registers 0x13C 0x4 registers 0x142 0x2 registers 0x146 0x2 registers 0x148 0x4 registers 0x14E 0x2 registers 0x152 0x2 registers 0x154 0x4 registers 0x15A 0x2 registers 0x15E 0x2 registers 0x160 0x4 registers 0x164 0x4 registers 0x168 0x3 registers 0x16C 0x2 registers 0x170 0x3 registers 0x176 0x2 registers 0x17A 0x2 registers 0x17E 0x2 registers 0x182 0x2 registers 0x184 0x2 registers 0x188 0x2 registers 0x18E 0x2 registers 0x190 0x4 registers 0x196 0x2 registers 0x198 0x4 registers 0x19E 0x2 registers 0x1A0 0x4 registers 0x1A4 0x2 registers 0x1A8 0x2 registers 0x1AC 0x2 registers 0x1B0 0x2 registers 0x1B4 0x2 registers 0x1BA 0x2 registers 0x1BE 0x2 registers 0x1C2 0x2 registers 0x1C6 0x2 registers 0x1CA 0x2 registers 0x1CE 0x2 registers 0x1D0 0x2 registers 0x1D4 0x2 registers 0x1D8 0x2 registers 0x1DC 0x2 registers 0x1E0 0x2 registers 0x1E4 0x2 registers 0x1E8 0x2 registers WFG_DTIF 3 FRTIM 28 INCAP 29 OUTCOMP 30 FRT_TCCP0 FRT-ch.0 Cycle Setting Register 0x142 16 read-write 0xFFFF 0xFFFF FRT_TCDT0 FRT-ch.0 Count Value Register 0x146 16 read-write 0x0000 0xFFFF FRT_TCSA0 FRT-ch.0 Control Register A 0x148 16 read-write 0x0040 0xE3FF ECKE Uses an external input clock (FRCK) as FRT's count clock 15 15 read-write IRQZF Zero interrupt flag 14 14 read-write IRQZE Generates interrupt@ when "1" is set to TCSA.IRQZF 13 13 read-write ICLR Interrupt flag 9 9 read-write ICRE Generates interrupt when "1" is set to TCSA.ICLR 8 8 read-write BFE Enables TCCP's buffer function 7 7 read-write STOP Puts FRT in stopping state 6 6 read-write MODE FRT's count mode 5 5 read-write SCLR FRT operation state initialization request 4 4 write-only CLK FRT clock cycle 0 3 read-write FRT_TCSC0 FRT-ch.0 Control Register C 0x14A 16 read-write 0x0000 0xFFFF MSPC Reads the current counter value from a Peak value detection mask counter 12 15 read-only MSZC Reads the current counter value from a Zero value detection mask counter 8 11 read-only MSPI Sets the number of masked Peak value detections 4 7 read-write MSZI Sets the number of masked Zero value detections 0 3 read-write FRT_TCCP1 FRT-ch.1 Cycle Setting Register 0x14E FRT_TCDT1 FRT-ch.1 Count Value Register 0x152 FRT_TCSA1 FRT-ch.1 Control Register A 0x154 FRT_TCSC1 FRT-ch.1 Control Register C 0x156 FRT_TCCP2 FRT-ch.2 Cycle Setting Register 0x15A FRT_TCDT2 FRT-ch.2 Count Value Register 0x15E FRT_TCSA2 FRT-ch.2 Control Register A 0x160 FRT_TCSC2 FRT-ch.2 Control Register C 0x162 FRT_TCAL FRT Simultaneous Start Control Register 0x164 32 read-write 0x0000FFFF 0x01FF01FF SCLR22 Mirror register of the SCLR bit located in TCSA2 register of MFT-unit2 24 24 write-only SCLR21 Mirror register of the SCLR bit located in TCSA1 register of MFT-unit2 23 23 write-only SCLR20 Mirror register of the SCLR bit located in TCSA0 register of MFT-unit2 22 22 write-only SCLR12 Mirror register of the SCLR bit located in TCSA2 register of MFT-unit1 21 21 write-only SCLR11 Mirror register of the SCLR bit located in TCSA1 register of MFT-unit1 20 20 write-only SCLR10 Mirror register of the SCLR bit located in TCSA0 register of MFT-unit1 19 19 write-only SCLR02 Mirror register of the SCLR bit located in TCSA2 register of MFT-unit0 18 18 write-only SCLR01 Mirror register of the SCLR bit located in TCSA1 register of MFT-unit0 17 17 write-only SCLR00 Mirror register of the SCLR bit located in TCSA0 register of MFT-unit0 16 16 write-only STOP22 Mirror register of the STOP bit located in TCSA2 register of MFT-unit2 8 8 read-write STOP21 Mirror register of the STOP bit located in TCSA1 register of MFT-unit2 7 7 read-write STOP20 Mirror register of the STOP bit located in TCSA0 register of MFT-unit2 6 6 read-write STOP12 Mirror register of the STOP bit located in TCSA2 register of MFT-unit1 5 5 read-write STOP11 Mirror register of the STOP bit located in TCSA1 register of MFT-unit1 4 4 read-write STOP10 Mirror register of the STOP bit located in TCSA0 register of MFT-unit1 3 3 read-write STOP02 Mirror register of the STOP bit located in TCSA2 register of MFT-unit0 2 2 read-write STOP01 Mirror register of the STOP bit located in TCSA1 register of MFT-unit0 1 1 read-write STOP00 Mirror register of the STOP bit located in TCSA0 register of MFT-unit0 0 0 read-write OCU_OCCP0 OCU ch.0 Compare Value Store Register 0x102 16 read-write 0x0000 0xFFFF OCU_OCCP1 OCU ch.1 Compare Value Store Register 0x106 OCU_OCCP2 OCU ch.2 Compare Value Store Register 0x10A OCU_OCCP3 OCU ch.3 Compare Value Store Register 0x10E OCU_OCCP4 OCU ch.4 Compare Value Store Register 0x112 OCU_OCCP5 OCU ch.5 Compare Value Store Register 0x116 OCU_OCSA10 OCU ch.0/1 Control Register A 0x118 8 read-write 0x00 0xF3 IOP1 Indicates that a match has already been detected between FRT's count value and OCCP(1) value at OCU ch.(1). 7 7 read-write IOP0 Indicates that a match has already been detected between FRT's count value and OCCP(0) value at OCU ch.(0). 6 6 read-write IOE1 Generates interrupt@ when "1" is set to OCSA.IOP1 5 5 read-write IOE0 Generates interrupt@ when "1" is set to OCSA.IOP0 4 4 read-write CST1 Enables the operation of OCU ch.(1) 1 1 read-write CST0 Enables the operation of OCU ch.(0) 0 0 read-write OCU_OCSB10 OCU ch.0/1 Control Register B 0x119 8 read-write 0x00 0x93 FM4 Selects FM4 mode for operating mode 7 7 read-write CMOD Selects OCU's operation mode in combination with OCSC.MOD0 to MOD5 4 4 read-write OTD1 Indicates that the RT(1) output pin is in the High-level output state. 1 1 read-write OTD0 Indicates that the RT(0) output pin is in the High-level output state. 0 0 read-write OCU_OCSD10 OCU ch.0/1 Control Register D 0x11A 8 read-write 0x00 0xFF OCSE1BUFE Enable buffer register function of OCSE(1) 6 7 read-write OCSE0BUFE Enable buffer register function of OCSE(0) 4 5 read-write OCCP1BUFE Enable buffer register function of OCCP(1) 2 3 read-write OCCP0BUFE Enable buffer register function of OCCP(0) 0 1 read-write OCU_OCSA32 OCU ch.2/3 Control Register A 0x11C OCU_OCSB32 OCU ch.2/3 Control Register B 0x11D OCU_OCSD32 OCU ch.2/3 Control Register D 0x11E OCU_OCSA54 OCU ch.4/5 Control Register A 0x120 OCU_OCSB54 OCU ch.4/5 Control Register B 0x121 OCU_OCSD54 OCU ch.4/5 Control Register D 0x122 OCU_OCSC OCU Control Register C 0x125 8 read-write 0x00 0x3F MOD5 OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD 5 5 read-write MOD4 OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD 4 4 read-write MOD3 OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD 3 3 read-write MOD2 OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD 2 2 read-write MOD1 OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD 1 1 read-write MOD0 OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD 0 0 read-write OCU_OCSE0 OCU ch.0 Control Register E 0x128 16 read-write 0x0000 0xFFFF OCSE Specify the setting conditions of the OCU's matching detection register (IOP0) 0 15 read-write OCU_OCSE1 OCU ch.1 Control Register E 0x12C 32 read-write 0x00000000 0xFFFFFFFF OCSE Specify the setting conditions of the OCU's matching detection register (IOP0/IOP1) 0 31 read-write OCU_OCSE2 OCU ch.2 Control Register E 0x130 OCU_OCSE3 OCU ch.3 Control Register E 0x134 OCU_OCSE4 OCU ch.4 Control Register E 0x138 OCU_OCSE5 OCU ch.5 Control Register E 0x13C OCU_OCFS10 OCU ch.0/1 Connecting FRT Select Register 0x168 8 read-write 0x00 0xFF FSO1 Connects FRT ch.x to OCU ch.1 4 7 read-write FSO0 Connects FRT ch.x to OCU ch.0 0 3 read-write OCU_OCFS32 OCU ch.2/3 Connecting FRT Select Register 0x169 OCU_OCFS54 OCU ch.4/5 Connecting FRT Select Register 0x16A WFG_WFTF10 Pulse Counter Value Register for WFG ch.0/1 0x18E 16 read-write 0x0000 0xFFFF WFG_WFTA10 WFG Timer Value Register for WFG ch.0/1 0x190 16 read-write 0x0000 0xFFFF WFG_WFTB10 WFG Timer Value Register for WFG ch.0/1 0x192 16 read-write 0x0000 0xFFFF WFG_WFTF32 Pulse Counter Value Register for WFG ch.2/3 0x196 16 read-write 0x0000 0xFFFF WFG_WFTA32 WFG Timer Value Register for WFG ch.2/3 0x198 16 read-write 0x0000 0xFFFF WFG_WFTB32 WFG Timer Value Register for WFG ch.2/3 0x19A 16 read-write 0x0000 0xFFFF WFG_WFTF54 Pulse Counter Value Register for WFG ch.4/5 0x19E 16 read-write 0x0000 0xFFFF WFG_WFTA54 WFG Timer Value Register for WFG ch.4/5 0x1A0 16 read-write 0x0000 0xFFFF WFG_WFTB54 WFG Timer Value Register for WFG ch.4/5 0x1A2 16 read-write 0x0000 0xFFFF WFG_WFSA10 WFG Control Register A for WFG ch.0/1 0x1A4 16 read-write 0x0000 0x3FFF DMOD Specifies polarity for RTO(0) and RTO(1) signal outputs 12 13 read-write PGEN Specifies how to reflect the CH_PPG signal for each channel of the WFG 10 11 read-write PSEL Select the PPG timer unit to be used for each channel of the WFG 8 9 read-write GTEN Selects the output conditions for the CH_GATE output signal of the WFG 6 7 read-write TMD Select the WFG's operation mode 3 5 read-write DCK Set the count clock cycle for the WFG timer and Pulse counter 0 2 read-write WFG_WFSA32 WFG Control Register A for WFG ch.2/3 0x1A8 WFG_WFSA54 WFG Control Register A for WFG ch.4/5 0x1AC WFG_WFIR WFG Interrupt Control Register 0x1B0 16 read-write 0x0000 0xFFFF TMIS54 Stops the WFG54 reload timer and clears TMIF54 15 15 write-only TMIE54 Starts WFG54 reload timer and checks the operation state of it 14 14 read-write TMIC54 Clears TIMF54 bit 13 13 write-only TMIF54 Detects the event of WFG54 reload timer interrupt occurrence 12 12 read-only TMIS32 Stops the WFG32 reload timer and clears TMIF32 11 11 write-only TMIE32 Starts WFG32 reload timer and checks the operation state of it 10 10 read-write TMIC32 Clears TIMF32 bit 9 9 write-only TMIF32 Detects the event of WFG32 reload timer interrupt occurrence 8 8 read-only TMIS10 Stops the WFG10 reload timer and clears TMIF10 7 7 write-only TMIE10 Starts WFG10 reload timer and checks the operation state of it 6 6 read-write TMIC10 Clears TIMF10 bit 5 5 write-only TMIF10 Detects the event of WFG10 reload timer interrupt occurrence 4 4 read-only DTICB Clears DTIFB bit 3 3 write-only DTIFB Detects DTTIX signal input via analog noise filter 2 2 read-only DTICA Clears the DTIFA interrupt flag 1 1 write-only DTIFA Detects the event of DTTIX signal input via digital noise-canceller 0 0 read-only WFG_NZCL NZCL Control Register 0x1B4 16 read-write 0x0000 0x733F WIM54 Selects whether a WFG54 reload timer interrupt is masked when the WFIR.TMIF54 flag is set 14 14 read-write WIM32 Selects whether a WFG32 reload timer interrupt is masked when the WFIR.TMIF32 flag is set 13 13 read-write WIM10 Selects whether a WFG10 reload timer interrupt is masked when the WFIR.TMIF10 flag is set 12 12 read-write DIMB Selects whether a DTIF interrupt is masked when the WFIR.TIFDTIFB flag is set 9 9 read-write DIMA Selects whether a DTIF interrupt is masked when the WFIR.DTIFA flag is set 8 8 read-write DTIEB Selects whether to set the WFIR.DTIFB flag for the path from the DTTIX pin for input signal to an analog noise filter 5 5 read-write SDTI Sets the WFIR.DTIFA register by writing to the register from the CPU 4 4 write-only NWS Set the noise-canceling width for a digital noise-canceller 1 3 read-write DTIEA Selects whether the WFIR.DTIFA register is set for the path via digital noise filter from the DTTIX input pin 0 0 read-write ICU_ICFS10 ICU ch.0/1 Connecting FRT Select Register 0x16C 8 read-write 0x00 0xFF FSI1 Connects FRT ch.x to ICU ch.(1) 4 7 read-write FSI0 Connects FRT ch.x to ICU ch.(0) 0 3 read-write ICU_ICFS32 ICU ch.2/3 Connecting FRT Select Register 0x16D ICU_ICCP0 ICU-ch.0 Capture Value Store Register 0x176 16 read-only 0x0000 0xFFFF ICU_ICCP1 ICU-ch.1 Capture Value Store Register 0x17A ICU_ICCP2 ICU-ch.2 Capture Value Store Register 0x17E ICU_ICCP3 ICU-ch.3 Capture Value Store Register 0x182 ICU_ICSA10 ICU ch.0/1 Control Register A 0x184 8 read-write 0x00 0xFF ICP1 Indicates that a valid edge has been detected at ICU ch.(1) and the capture operation has been performed 7 7 read-write ICP0 Indicates that a valid edge has been detected at ICU ch.(0) and the capture operation has been performed 6 6 read-write ICE1 Generates interrupt@ when "1" is set to ICSA.ICP1. 5 5 read-write ICE0 Generates interrupt@ when "1" is set to ICSA.ICP0. 4 4 read-write EG1 Enables/disables the operation of ICU-ch.(1) and selects a valid edge(s) 2 3 read-write EG0 Enables/disables the operation of ICU-ch.(0) and selects a valid edge(s) 0 1 read-write ICU_ICSB10 ICU ch.0/1 Control Register B 0x185 8 read-only 0x00 0x03 IEI1 Indicates the latest valid edge of ICU ch.(1) 1 1 read-only IEI0 Indicates the latest valid edge of ICU ch.(0) 0 0 read-only ICU_ICSA32 ICU ch.2/3 Control Register A 0x188 ICU_ICSB32 ICU ch.2/3 Control Register B 0x189 ADCMP_ACFS10 ADCMP ch.0/1 Connecting FRT Select Register 0x170 8 read-write 0x00 0xFF FSA1 Specify the FRT to be connected to ADCMP ch.(1) 4 7 read-write FSA0 Specify the FRT to be connected to ADCMP ch.(0) 0 3 read-write ADCMP_ACFS32 ADCMP ch.2/3 Connecting FRT Select Register 0x171 ADCMP_ACFS54 ADCMP ch.4/5 Connecting FRT Select Register 0x172 ADCMP_ACMP0 ADCMP ch.0 Compare Value Store Register 0x1BA 16 read-write 0x0000 0xFFFF ACMP Specifies an AD conversion start time 0 15 read-write ADCMP_ACMP1 ADCMP ch.1 Compare Value Store Register 0x1BE ADCMP_ACMP2 ADCMP ch.2 Compare Value Store Register 0x1C2 ADCMP_ACMP3 ADCMP ch.3 Compare Value Store Register 0x1C6 ADCMP_ACMP4 ADCMP ch.4 Compare Value Store Register 0x1CA ADCMP_ACMP5 ADCMP ch.5 Compare Value Store Register 0x1CE ADCMP_ACSA ADCMP Control Register A 0x1D0 16 read-write 0x0000 0x3F3F SEL54 Selects compatible operation of ADCMP ch.5 and ch.4 with FM3 Family products 12 13 read-write SEL32 Selects compatible operation of ADCMP ch.3 and ch.2 with FM3 Family products 10 11 read-write SEL10 Selects compatible operation of ADCMP ch.1 and ch.0 with FM3 Family products 8 9 read-write CE54 Enables/disables compatibility of ADCMP ch.5 and ch.4 with FM3 Family products 4 5 read-write CE32 Enables/disables compatibility of ADCMP ch.3 and ch.2 with FM3 Family products 2 3 read-write CE10 Enables/disables compatibility of ADCMP ch.1 and ch.0 with FM3 Family products 0 1 read-write ADCMP_ACSC0 ADCMP ch.0 Control Register C 0x1D4 8 read-write 0x00 0x1F ADSEL Specify the destinations of ADC start signals that are output by ADCMP 2 4 read-write BUFE Select enable/disable and transfer timing for buffer function of the ACMP register 0 1 read-write ADCMP_ACSD0 ADCMP ch.0 Control Register D 0x1D5 8 read-write 0x00 0xF3 ZE Enables/disables the operation of the ADCMP when the FRT is "0x0000" 7 7 read-write UE Enables/disables the operation of the ADCMP that is counting up for the connected FRT 6 6 read-write PE Enables/disables the operation of the ADCMP that is counting down at the Peak value of the connected FRT 5 5 read-write DE Enables/disables the operation of the ADCMP that is counting down for the connected FRT 4 4 read-write OCUS Selects the OCU OCCP register that will become the start for offset start 1 1 read-write AMOD Selects operation mode for ADCMP 0 0 read-write ADCMP_ACSC1 ADCMP ch.1 Control Register C 0x1D8 ADCMP_ACSD1 ADCMP ch.1 Control Register D 0x1D9 ADCMP_ACSC2 ADCMP ch.2 Control Register C 0x1DC ADCMP_ACSD2 ADCMP ch.2 Control Register D 0x1DD ADCMP_ACSC3 ADCMP ch.3 Control Register C 0x1E0 ADCMP_ACSD3 ADCMP ch.3 Control Register D 0x1E1 ADCMP_ACSC4 ADCMP ch.4 Control Register C 0x1E4 ADCMP_ACSD4 ADCMP ch.4 Control Register D 0x1E5 ADCMP_ACSC5 ADCMP ch.5 Control Register C 0x1E8 ADCMP_ACSD5 ADCMP ch.5 Control Register D 0x1E9 MFT_PPG PPG Configuration Registers MFT_PPG 0x40024000 0x0 0x2 registers 0x8 0x2 registers 0xC 0x1 registers 0x10 0x2 registers 0x14 0x1 registers 0x20 0x2 registers 0x28 0x2 registers 0x2C 0x1 registers 0x30 0x2 registers 0x34 0x1 registers 0x40 0x2 registers 0x48 0x2 registers 0x4C 0x1 registers 0x50 0x2 registers 0x54 0x1 registers 0x100 0x2 registers 0x104 0x2 registers 0x140 0x2 registers 0x144 0x2 registers 0x200 0x2 registers 0x204 0x2 registers 0x208 0x2 registers 0x20C 0x2 registers 0x210 0x2 registers 0x214 0x2 registers 0x218 0x1 registers 0x240 0x2 registers 0x244 0x2 registers 0x248 0x2 registers 0x24C 0x2 registers 0x250 0x2 registers 0x254 0x2 registers 0x258 0x1 registers 0x280 0x2 registers 0x284 0x2 registers 0x288 0x2 registers 0x28C 0x2 registers 0x290 0x2 registers 0x294 0x2 registers 0x298 0x1 registers 0x2C0 0x2 registers 0x2C4 0x2 registers 0x2C8 0x2 registers 0x2CC 0x2 registers 0x2D0 0x2 registers 0x2D4 0x2 registers 0x2D8 0x1 registers 0x300 0x2 registers 0x304 0x2 registers 0x308 0x2 registers 0x30C 0x2 registers 0x310 0x2 registers 0x314 0x2 registers 0x318 0x1 registers 0x340 0x2 registers 0x344 0x2 registers 0x348 0x2 registers 0x34C 0x2 registers 0x350 0x2 registers 0x354 0x2 registers 0x358 0x1 registers 0x380 0x1 registers PPG 23 TTCR0 PPG Start Trigger Control Register 0 0x0 16 read-write 0xF000 0xFF00 TRG6O PPG6 trigger stop bit 15 15 write-only TRG4O PPG4 trigger stop bit 14 14 write-only TRG2O PPG2 trigger stop bit 13 13 write-only TRG0O PPG0 trigger stop bit 12 12 write-only CS0 8-bit UP counter clock select bits for comparison 10 11 read-write MONI0 8-bit UP counter operation state monitor bit for comparison 9 9 read-only STR0 8-bit UP counter operation enable bit for comparison 8 8 write-only TTCR1 PPG Start Trigger Control Register 1 0x20 16 read-write 0xF000 0xFF00 TRG7O PPG7 trigger stop bit 15 15 write-only TRG5O PPG5 trigger stop bit 14 14 write-only TRG3O PPG3 trigger stop bit 13 13 write-only TRG1O PPG1 trigger stop bit 12 12 write-only CS1 8-bit UP counter clock select bits for comparison 10 11 read-write MONI1 8-bit UP counter operation state monitor bit for comparison 9 9 read-only STR1 8-bit UP counter operation enable bit for comparison 8 8 write-only TTCR2 PPG Start Trigger Control Register 2 0x40 16 read-write 0xF000 0xFF00 TRG22O PPG22 trigger stop bit 15 15 write-only TRG20O PPG20 trigger stop bit 14 14 write-only TRG18O PPG18 trigger stop bit 13 13 write-only TRG16O PPG16 trigger stop bit 12 12 write-only CS2 8-bit UP counter clock select bits for comparison 10 11 read-write MONI2 8-bit UP counter operation state monitor bit for comparison 9 9 read-only STR2 8-bit UP counter operation enable bit for comparison 8 8 write-only COMP0 PPG Compare Register 0 0x9 8 read-write 0x00 0xFF COMP2 PPG Compare Register 2 0xC 8 read-write 0x00 0xFF COMP4 PPG Compare Register 4 0x11 COMP6 PPG Compare Register 6 0x14 COMP1 PPG Compare Register 1 0x29 COMP3 PPG Compare Register 3 0x2C COMP5 PPG Compare Register 5 0x31 COMP7 PPG Compare Register 7 0x34 COMP8 PPG Compare Register 8 0x49 COMP10 PPG Compare Register 10 0x4C COMP12 PPG Compare Register 12 0x51 COMP14 PPG Compare Register 14 0x54 TRG0 PPG Start Register 0 0x100 16 read-write 0x0000 0xFFFF PEN15 PPG15 Start Trigger bit 15 15 read-write PEN14 PPG14 Start Trigger bit 14 14 read-write PEN13 PPG13 Start Trigger bit 13 13 read-write PEN12 PPG12 Start Trigger bit 12 12 read-write PEN11 PPG11 Start Trigger bit 11 11 read-write PEN10 PPG10 Start Trigger bit 10 10 read-write PEN09 PPG9 Start Trigger bit 9 9 read-write PEN08 PPG8 Start Trigger bit 8 8 read-write PEN07 PPG7 Start Trigger bit 7 7 read-write PEN06 PPG6 Start Trigger bit 6 6 read-write PEN05 PPG5 Start Trigger bit 5 5 read-write PEN04 PPG4 Start Trigger bit 4 4 read-write PEN03 PPG3 Start Trigger bit 3 3 read-write PEN02 PPG2 Start Trigger bit 2 2 read-write PEN01 PPG1 Start Trigger bit 1 1 read-write PEN00 PPG0 Start Trigger bit 0 0 read-write TRG1 PPG Start Register 1 0x140 16 read-write 0x0000 0x00FF PEN23 PPG23 Start Trigger bit 7 7 read-write PEN22 PPG22 Start Trigger bit 6 6 read-write PEN21 PPG21 Start Trigger bit 5 5 read-write PEN20 PPG20 Start Trigger bit 4 4 read-write PEN19 PPG19 Start Trigger bit 3 3 read-write PEN18 PPG18 Start Trigger bit 2 2 read-write PEN17 PPG17 Start Trigger bit 1 1 read-write PEN16 PPG16 Start Trigger bit 0 0 read-write REVC0 Output Reverse Register 0 0x104 16 read-write 0x0000 0xFFFF REV15 PPG15 Output Reverse Enable bit 15 15 read-write REV14 PPG14 Output Reverse Enable bit 14 14 read-write REV13 PPG13 Output Reverse Enable bit 13 13 read-write REV12 PPG12 Output Reverse Enable bit 12 12 read-write REV11 PPG11 Output Reverse Enable bit 11 11 read-write REV10 PPG10 Output Reverse Enable bit 10 10 read-write REV09 PPG9 Output Reverse Enable bit 9 9 read-write REV08 PPG8 Output Reverse Enable bit 8 8 read-write REV07 PPG7 Output Reverse Enable bit 7 7 read-write REV06 PPG6 Output Reverse Enable bit 6 6 read-write REV05 PPG5 Output Reverse Enable bit 5 5 read-write REV04 PPG4 Output Reverse Enable bit 4 4 read-write REV03 PPG3 Output Reverse Enable bit 3 3 read-write REV02 PPG2 Output Reverse Enable bit 2 2 read-write REV01 PPG1 Output Reverse Enable bit 1 1 read-write REV00 PPG0 Output Reverse Enable bit 0 0 read-write REVC1 Output Reverse Register 1 0x144 16 read-write 0x0000 0x00FF REV23 PPG23 Output Reverse Enable bit 7 7 read-write REV22 PPG22 Output Reverse Enable bit 6 6 read-write REV21 PPG21 Output Reverse Enable bit 5 5 read-write REV20 PPG20 Output Reverse Enable bit 4 4 read-write REV19 PPG19 Output Reverse Enable bit 3 3 read-write REV18 PPG18 Output Reverse Enable bit 2 2 read-write REV17 PPG17 Output Reverse Enable bit 1 1 read-write REV16 PPG16 Output Reverse Enable bit 0 0 read-write PPGC0 PPG Operation Mode Control Register 0 0x201 8 read-write 0x00 0xFF PIE PPG Interrupt Enable bit 7 7 read-write PUF PPG Counter Underflow bit 6 6 read-write INTM Interrupt Mode Select bit 5 5 read-write PCS PPG DOWN Counter Operation Clock Select bits 3 4 read-write MD PPG Operation Mode Set bits 1 2 read-write TTRG PPG start trigger select bit 0 0 read-write PPGC1 PPG Operation Mode Control Register 1 0x200 8 read-write 0x00 0xF8 PIE PPG Interrupt Enable bit 7 7 read-write PUF PPG Counter Underflow bit 6 6 read-write INTM Interrupt Mode Select bit 5 5 read-write PCS PPG DOWN Counter Operation Clock Select bits 3 4 read-write MD PPG Operation Mode Set bits 1 2 read-write PPGC2 PPG Operation Mode Control Register 2 0x205 PPGC3 PPG Operation Mode Control Register 3 0x204 PPGC4 PPG Operation Mode Control Register 4 0x241 PPGC5 PPG Operation Mode Control Register 5 0x240 PPGC6 PPG Operation Mode Control Register 6 0x245 PPGC7 PPG Operation Mode Control Register 7 0x244 PPGC8 PPG Operation Mode Control Register 8 0x281 PPGC9 PPG Operation Mode Control Register 9 0x280 PPGC10 PPG Operation Mode Control Register 10 0x285 PPGC11 PPG Operation Mode Control Register 11 0x284 PPGC12 PPG Operation Mode Control Register 12 0x2C1 PPGC13 PPG Operation Mode Control Register 13 0x2C0 PPGC14 PPG Operation Mode Control Register 14 0x2C5 PPGC15 PPG Operation Mode Control Register 15 0x2C4 PPGC16 PPG Operation Mode Control Register 16 0x301 PPGC17 PPG Operation Mode Control Register 17 0x300 PPGC18 PPG Operation Mode Control Register 18 0x305 PPGC19 PPG Operation Mode Control Register 19 0x304 PPGC20 PPG Operation Mode Control Register 20 0x341 PPGC21 PPG Operation Mode Control Register 21 0x340 PPGC22 PPG Operation Mode Control Register 22 0x345 PPGC23 PPG Operation Mode Control Register 23 0x344 PRLH0 PPG0 Reload Registers High 0x209 8 read-write 0x00 0xFF PRLH Reload Registers High 0 7 read-write PRLL0 PPG0 Reload Registers Low 0x208 8 read-write 0x00 0xFF PRLL Reload Registers Low 0 7 read-write PRLH1 PPG1 Reload Registers High 0x20D PRLL1 PPG1 Reload Registers Low 0x20C PRLH2 PPG2 Reload Registers High 0x211 PRLL2 PPG2 Reload Registers Low 0x210 PRLH3 PPG3 Reload Registers High 0x215 PRLL3 PPG3 Reload Registers Low 0x214 PRLH4 PPG4 Reload Registers High 0x249 PRLL4 PPG4 Reload Registers Low 0x248 PRLH5 PPG5 Reload Registers High 0x24D PRLL5 PPG5 Reload Registers Low 0x24C PRLH6 PPG6 Reload Registers High 0x251 PRLL6 PPG6 Reload Registers Low 0x250 PRLH7 PPG7 Reload Registers High 0x255 PRLL7 PPG7 Reload Registers Low 0x254 PRLH8 PPG8 Reload Registers High 0x289 PRLL8 PPG8 Reload Registers Low 0x288 PRLH9 PPG9 Reload Registers High 0x28D PRLL9 PPG9 Reload Registers Low 0x28C PRLH10 PPG10 Reload Registers High 0x291 PRLL10 PPG10 Reload Registers Low 0x290 PRLH11 PPG11 Reload Registers High 0x295 PRLL11 PPG11 Reload Registers Low 0x294 PRLH12 PPG12 Reload Registers High 0x2C9 PRLL12 PPG12 Reload Registers Low 0x2C8 PRLH13 PPG13 Reload Registers High 0x2CD PRLL13 PPG13 Reload Registers Low 0x2CC PRLH14 PPG14 Reload Registers High 0x2D1 PRLL14 PPG14 Reload Registers Low 0x2D0 PRLH15 PPG15 Reload Registers High 0x2D5 PRLL15 PPG15 Reload Registers Low 0x2D4 PRLH16 PPG16 Reload Registers High 0x309 PRLL16 PPG16 Reload Registers Low 0x308 PRLH17 PPG17 Reload Registers High 0x30D PRLL17 PPG17 Reload Registers Low 0x30C PRLH18 PPG18 Reload Registers High 0x311 PRLL18 PPG18 Reload Registers Low 0x310 PRLH19 PPG19 Reload Registers High 0x315 PRLL19 PPG19 Reload Registers Low 0x314 PRLH20 PPG20 Reload Registers High 0x349 PRLL20 PPG20 Reload Registers Low 0x348 PRLH21 PPG21 Reload Registers High 0x34D PRLL21 PPG21 Reload Registers Low 0x34C PRLH22 PPG22 Reload Registers High 0x351 PRLL22 PPG22 Reload Registers Low 0x350 PRLH23 PPG23 Reload Registers High 0x355 PRLL23 PPG23 Reload Registers Low 0x354 GATEC0 PPG Gate Function Control Register 0 0x218 8 read-write 0x00 0x33 STRG2 Select trigger bit for PPG2 5 5 read-write EDGE2 Start Effective Level Select bit for PPG2 4 4 read-write STRG0 Select trigger bit for PPG0 1 1 read-write EDGE0 Start Effective Level Select bit for PPG0 0 0 read-write GATEC4 PPG Gate Function Control Register 4 0x258 8 read-write 0x00 0x33 STRG6 Select trigger bit for PPG6 5 5 read-write EDGE6 Start Effective Level Select bit for PPG6 4 4 read-write STRG4 Select trigger bit for PPG4 1 1 read-write EDGE4 Start Effective Level Select bit for PPG4 0 0 read-write GATEC8 PPG Gate Function Control Register 8 0x298 8 read-write 0x00 0x33 STRG10 Select trigger bit for PPG10 5 5 read-write EDGE10 Start Effective Level Select bit for PPG10 4 4 read-write STRG8 Select trigger bit for PPG8 1 1 read-write EDGE8 Start Effective Level Select bit for PPG8 0 0 read-write GATEC12 PPG Gate Function Control Register 12 0x2D8 8 read-write 0x00 0x33 STRG14 Select trigger bit for PPG14 5 5 read-write EDGE14 Start Effective Level Select bit for PPG14 4 4 read-write STRG12 Select trigger bit for PPG12 1 1 read-write EDGE12 Start Effective Level Select bit for PPG12 0 0 read-write GATEC16 PPG Gate Function Control Register 16 0x318 8 read-write 0x00 0x33 STRG18 Select trigger bit for PPG18 5 5 read-write EDGE18 Start Effective Level Select bit for PPG18 4 4 read-write STRG16 Select trigger bit for PPG16 1 1 read-write EDGE16 Start Effective Level Select bit for PPG16 0 0 read-write GATEC20 PPG Gate Function Control Register 20 0x358 8 read-write 0x00 0x33 STRG22 Select trigger bit for PPG22 5 5 read-write EDGE22 Start Effective Level Select bit for PPG22 4 4 read-write STRG20 Select trigger bit for PPG20 1 1 read-write EDGE20 Start Effective Level Select bit for PPG20 0 0 read-write IGBTC IGBT Mode Control Register 0x380 8 read-write 0x00 0xFF IGATIH Stop prohibition mode selection in output active bit 7 7 read-write IGNFW Noise filter width selection bit 4 6 read-write IGOSEL Output level selection bit 2 3 read-write IGTRGLV Trigger input level selection bit 1 1 read-write IGBTMD IGBT mode selection bit 0 0 read-write BT0 Base Timer 0 BT0 0x40025000 0x0 0x2 registers 0x4 0x2 registers 0x8 0x2 registers 0xC 0x2 registers 0x10 0x2 registers BTIM0_3_FLASH 31 PWM_TMCR Timer Control Register PWM 0xC 16 read-write 0x0000 0x7F7F CKS Count clock selection bits 12 14 read-write RTGEN Restart enable bit 11 11 read-write PMSK Pulse output mask bit 10 10 read-write EGS Trigger input edge selection bits 8 9 read-write FMD Timer function selection bits 4 6 read-write OSEL Output polarity specification bit 3 3 read-write MDSE Mode selection bit 2 2 read-write CTEN Count operation enable bit 1 1 read-write STRG Software trigger bit 0 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write 0x00 0x01 CKS3 Count clock selection bit 0 0 read-write PWM_STC Status Control Register PWM 0x10 8 read-write 0x00 0x77 TGIE Trigger interrupt request enable bit 6 6 read-write DTIE Duty match interrupt request enable bit 5 5 read-write UDIE Underflow interrupt request enable bit 4 4 read-write TGIR Trigger interrupt request bit 2 2 read-write DTIR Duty match interrupt request bit 1 1 read-write UDIR Underflow interrupt request bit 0 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write 0x0000 0xFFFF PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write 0x0000 0xFFFF PWM_TMR Timer Register PWM 0x8 16 read-only 0x0000 0xFFFF PPG_TMCR Timer Control Register PPG 0xC 16 read-write 0x0000 0x7F7F CKS Count clock selection bits 12 14 read-write RTGEN Restart enable bit 11 11 read-write PMSK Pulse output mask bit 10 10 read-write EGS Trigger input edge selection bits 8 9 read-write FMD Timer function selection bits 4 6 read-write OSEL Output polarity specification bit 3 3 read-write MDSE Mode selection bit 2 2 read-write CTEN Count operation enable bit 1 1 read-write STRG Software trigger bit 0 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write 0x00 0x01 CKS3 Count clock selection bit 0 0 read-write PPG_STC Status Control Register PPG 0x10 8 read-write 0x00 0x55 TGIE Trigger interrupt request enable bit 6 6 read-write UDIE Underflow interrupt request enable bit 4 4 read-write TGIR Trigger interrupt request bit 2 2 read-write UDIR Underflow interrupt request bit 0 0 read-write PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write 0x0000 0xFFFF PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write 0x0000 0xFFFF PPG_TMR Timer Register PPG 0x8 16 read-only 0x0000 0xFFFF RT_TMCR Timer Control Register RT 0xC 16 read-write 0x0000 0x73FF CKS Count clock selection bits 12 14 read-write EGS Slection bits of trigger input edge and gate function level 8 9 read-write T32 32-bit timer selection bit 7 7 read-write FMD Timer function selection bits 4 6 read-write OSEL Output polarity specification bit 3 3 read-write MDSE Mode selection bit 2 2 read-write CTEN Timer enable bit 1 1 read-write STRG Software trigger bit 0 0 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write 0x00 0x81 GATE Gate Input Enable bit 7 7 read-write CKS3 Count clock selection bit 0 0 read-write RT_STC Status Control Register RT 0x10 8 read-write 0x00 0x55 TGIE Trigger interrupt request enable bit 6 6 read-write UDIE Underflow interrupt request enable bit 4 4 read-write TGIR Trigger interrupt request bit 2 2 read-write UDIR Underflow interrupt request bit 0 0 read-write RT_PCSR Cycle Set Register RT 0x0 16 read-write 0x0000 0xFFFF RT_TMR Timer Register RT 0x8 16 read-only 0x0000 0xFFFF PWC_TMCR Timer Control Register PWC 0xC 16 read-write 0x0000 0x77F6 CKS Count clock selection bits 12 14 read-write EGS Measurement edge selection bits 8 10 read-write T32 32-bit timer selection bit 7 7 read-write FMD Timer function selection bits 4 6 read-write MDSE Mode selection bit 2 2 read-write CTEN Timer enable bit 1 1 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write 0x00 0x01 CKS3 Count clock selection bit 0 0 read-write PWC_STC Status Control Register PWC 0x10 8 read-write 0x00 0xD5 ERR Error flag bit 7 7 read-only EDIE Measurement completion interrupt request enable bit 6 6 read-write OVIE Overflow interrupt request enable bit 4 4 read-write EDIR Measurement completion interrupt request bit 2 2 read-only OVIR Overflow interrupt request bit 0 0 read-write PWC_DTBF Data Buffer Register PWC 0x4 16 read-only 0x0000 0xFFFF BT1 0x40025040 BTIM0_3_FLASH 31 BT2 0x40025080 BTIM0_3_FLASH 31 BT3 0x400250C0 BTIM0_3_FLASH 31 BTIOSEL03 Base Timer I/O Select BTIOSEL03 0x40025100 0x0 0x2 registers BTSEL0123 I/O Select Register 0x00 16 read-write 0x0000 0xFF00 SEL23 I/O select bits for Ch.2/Ch.3 12 15 read-write SEL01 I/O select bits for Ch.0/Ch.1 8 11 read-write SBSSR Software-based Simultaneous Startup Register SBSSR 0x40025F00 0x0FC 0x2 registers BTSSSR Software-based Simultaneous Startup Register 0xFC 16 write-only 0x0000 0x000F SSSR3 Software-based simultaneous startup bit of Ch.3 3 3 write-only SSSR2 Software-based simultaneous startup bit of Ch.2 2 2 write-only SSSR1 Software-based simultaneous startup bit of Ch.1 1 1 write-only SSSR0 Software-based simultaneous startup bit of Ch.0 0 0 write-only QPRC0 Quadrature Position/Revolution Counter 0 QPRC0 0x40026000 0x0 0x2 registers 0x4 0x2 registers 0x8 0x2 registers 0xC 0x2 registers 0x10 0x2 registers 0x14 0x2 registers 0x18 0x2 registers 0x1C 0x2 registers 0x3C 0x4 registers DTIM_QDU 6 QPCR QPRC Position Count Register 0x0 16 read-write 0x0000 0xFFFF QRCR QPRC Revolution Count Register 0x4 16 read-write 0x0000 0xFFFF QPCCR QPRC Position Counter Compare Register 0x8 16 read-write 0x0000 0xFFFF QPRCR QPRC Position and Revolution Counter Compare Register 0xC 16 read-write 0x0000 0xFFFF QCRH High-Order Bytes of QPRC Control Register 0x19 8 read-write 0x00 0xFF CGE Detection edge selection bits 6 7 read-write BES BIN detection edge selection bits 4 5 read-write AES AIN detection edge selection bits 2 3 read-write PCRM Position counter reset mask bits 0 1 read-write QCRL Low-Order Bytes of QPRC Control Register 0x18 8 read-write 0x00 0xFF SWAP Swap bit 7 7 read-write RSEL Register function selection bit 6 6 read-write CGSC Count clear or gate selection bit 5 5 read-write PSTP Position counter stop bit 4 4 read-write RCM Revolution counter mode bits 2 3 read-write PCM Position counter mode bits 0 1 read-write QECR QPRC Extension Control Register 0x1C 16 read-write 0x0000 0x0007 ORNGIE Outrange interrupt enable bit 2 2 read-write ORNGF Outrange interrupt request flag bit 1 1 read-write ORNGMD Outrange mode selection bit 0 0 read-write QICRL Low-Order Bytes of QPRC Interrupt Control Register 0x14 8 read-write 0x00 0xFF ZIIF Zero index interrupt request flag bit 7 7 read-write OFDF Overflow interrupt request flag bit 6 6 read-write UFDF Underflow interrupt request flag bit 5 5 read-write OUZIE Overflow@ underflow@ or zero index interrupt enable bit 4 4 read-write QPRCMF PC and RC match interrupt request flag bit 3 3 read-write QPRCMIE PC and RC match interrupt enable bit 2 2 read-write QPCMF PC match interrupt request flag bit 1 1 read-write QPCMIE PC match interrupt enable bit 0 0 read-write QICRH High-Order Bytes of QPRC Interrupt Control Register 0x15 8 read-write 0x00 0x3F QPCNRCMF PC match and RC match interrupt request flag bit 5 5 read-write QPCNRCMIE PC match and RC match interrupt enable bit 4 4 read-write DIROU Last position counter flow direction bit 3 3 read-only DIRPC Last position counter direction bit 2 2 read-only CDCF Count inversion interrupt request flag bit 1 1 read-write CDCIE Count inversion interrupt enable bit 0 0 read-write QMPR QPRC Maximum Position Register 0x10 16 read-write 0xFFFF 0xFFFF QPRCRR Quad Counter Position Rotation Count Register 0x3C 32 read-only 0x00000000 0xFFFFFFFF QRCRR Quad counter rotation count display bit 16 31 read-only QPCRR Quad counter position count display bit 0 15 read-only QPRC0_NF Quadrature Position/Revolution Counter 0 Noise Filter QPRC0_NF 0x40026100 0x0 0x2 registers 0x4 0x2 registers 0x8 0x2 registers NFCTLA AIN Noise Control Register 0x0 16 read-write 0x0000 0x0037 AINMD Mask bit 5 5 read-write AINLV Input invert bit 4 4 read-write AINNWS Noise filter width select bits 0 2 read-write NFCTLB BIN Noise Control Register 0x4 16 read-write 0x0000 0x0037 BINMD Mask bit 5 5 read-write BINLV Input invert bit 4 4 read-write BINNWS Noise filter width select bits 0 2 read-write NFCTLZ ZIN Noise Control Register 0x8 16 read-write 0x0000 0x0037 ZINMD Mask bit 5 5 read-write ZINLV Input invert bit 4 4 read-write ZINNWS Noise filter width select bits 0 2 read-write ADC0 ADC0 Registers ADC0 0x40027000 0x0 0x2 registers 0x8 0x2 registers 0xC 0x4 registers 0x10 0x2 registers 0x14 0x2 registers 0x18 0x2 registers 0x1C 0x4 registers 0x20 0x1 registers 0x24 0x1 registers 0x26 0x2 registers 0x28 0x2 registers 0x2C 0x2 registers 0x30 0x2 registers 0x34 0x1 registers 0x38 0x2 registers 0x3C 0x2 registers 0x44 0x4 registers 0x48 0x4 registers 0x4C 0x2 registers 0x50 0x4 registers ADC0 25 ADCR A/D Control Register 0x1 8 read-write 0x00 0xEF SCIF Scan conversion interrupt request bit 7 7 read-write PCIF Priority conversion interrupt request bit 6 6 read-write CMPIF Conversion result comparison interrupt request bit 5 5 read-write SCIE Scan conversion interrupt enable bit 3 3 read-write PCIE Priority conversion interrupt enable bit 2 2 read-write CMPIE Conversion result comparison interrupt enable bit 1 1 read-write OVRIE FIFO overrun interrupt enable bit 0 0 read-write ADSR A/D Status Register 0x0 8 read-write 0x00 0xC7 ADSTP A/D conversion forced stop bit 7 7 read-write FDAS FIFO data placement selection bit 6 6 read-write PCNS Priority conversion pending flag 2 2 read-only PCS Priority conversion status flag 1 1 read-only SCS Scan conversion status flag 0 0 read-only SCCR Scan Conversion Control Register 0x9 8 read-write 0x80 0xF7 SEMP Scan conversion FIFO empty bit 7 7 read-only SFUL Scan conversion FIFO full bit 6 6 read-only SOVR Scan conversion overrun flag 5 5 read-write SFCLR Scan conversion FIFO clear bit 4 4 read-write RPT Scan conversion repeat bit 2 2 read-write SHEN Scan conversion timer start enable bit 1 1 read-write SSTR Scan conversion start bit 0 0 read-write SFNS Scan Conversion FIFO Stage Count Setup Register 0x8 8 read-write 0x00 0x0F SFS Scan conversion FIFO stage count setting bits 0 3 read-write SCFD Scan Conversion FIFO Data Register 0xC 32 read-only 0x00001000 0xFFF0131F SD Scan conversion result 20 31 read-only INVL A/D conversion result disable bit 12 12 read-only RS Scan conversion start factor 8 9 read-only SC Conversion input channel bits 0 4 read-only SCIS3 Scan Conversion Input Selection Register 3 0x11 8 read-write 0x00 0xFF AN31 AN31 analog input selection bit 7 7 read-write AN30 AN30 analog input selection bit 6 6 read-write AN29 AN29 analog input selection bit 5 5 read-write AN28 AN28 analog input selection bit 4 4 read-write AN27 AN27 analog input selection bit 3 3 read-write AN26 AN26 analog input selection bit 2 2 read-write AN25 AN25 analog input selection bit 1 1 read-write AN24 AN24 analog input selection bit 0 0 read-write SCIS2 Scan Conversion Input Selection Register 2 0x10 8 read-write 0x00 0xFF AN23 AN23 analog input selection bit 7 7 read-write AN22 AN22 analog input selection bit 6 6 read-write AN21 AN21 analog input selection bit 5 5 read-write AN20 AN20 analog input selection bit 4 4 read-write AN19 AN19 analog input selection bit 3 3 read-write AN18 AN18 analog input selection bit 2 2 read-write AN17 AN17 analog input selection bit 1 1 read-write AN16 AN16 analog input selection bit 0 0 read-write SCIS1 Scan Conversion Input Selection Register 1 0x15 8 read-write 0x00 0xFF AN15 AN15 analog input selection bit 7 7 read-write AN14 AN14 analog input selection bit 6 6 read-write AN13 AN13 analog input selection bit 5 5 read-write AN12 AN12 analog input selection bit 4 4 read-write AN11 AN11 analog input selection bit 3 3 read-write AN10 AN10 analog input selection bit 2 2 read-write AN9 AN9 analog input selection bit 1 1 read-write AN8 AN8 analog input selection bit 0 0 read-write SCIS0 Scan Conversion Input Selection Register 0 0x14 8 read-write 0x00 0xFF AN7 AN7 analog input selection bit 7 7 read-write AN6 AN6 analog input selection bit 6 6 read-write AN5 AN5 analog input selection bit 5 5 read-write AN4 AN4 analog input selection bit 4 4 read-write AN3 AN3 analog input selection bit 3 3 read-write AN2 AN2 analog input selection bit 2 2 read-write AN1 AN1 analog input selection bit 1 1 read-write AN0 AN0 analog input selection bit 0 0 read-write PFNS Priority Conversion FIFO Stage Count Setup Register 0x18 8 read-write 0x00 0x33 TEST Test bits 4 5 read-only PFS Priority conversion FIFO stage count setting bits 0 1 read-write PCCR Priority Conversion Control Register 0x19 8 read-write 0x80 0xFF PEMP Priority conversion FIFO empty bit 7 7 read-only PFUL Priority conversion FIFO full bit 6 6 read-only POVR Priority conversion overrun flag 5 5 read-write PFCLR Priority conversion FIFO clear bit 4 4 read-write ESCE External trigger analog input selection bit 3 3 read-write PEEN Priority conversion external start enable bit 2 2 read-write PHEN Priority conversion timer start enable bit 1 1 read-write PSTR Priority conversion start bit 0 0 read-write PCFD Priority Conversion FIFO Data Register 0x1C 32 read-only 0x00001000 0xFFF0171F PD Priority conversion result 20 31 read-only INVL A/D conversion result disable bit 12 12 read-only RS Scan conversion start factor 8 10 read-only PC Conversion input channel bits 0 4 read-only PCIS Priority Conversion Input Selection Register 0x20 8 read-write 0x00 0xFF P2A Priority level 2 analog input selection 3 7 read-write P1A Priority level 1 analog input selection 0 2 read-write CMPCR A/D Comparison Control Register 0x24 8 read-write 0x00 0xFF CMPEN Conversion result comparison function operation enable bit 7 7 read-write CMD1 Comparison mode 1 6 6 read-write CMD0 Comparison mode 0 5 5 read-write CCH Comparison target analog input channel 0 4 read-write CMPD A/D Comparison Value Setup Register 0x26 16 read-write 0x0000 0xFFC0 CMAD A/D conversion compare value setting bits 6 15 read-write ADSS3 Sampling Time Selection Register 3 0x29 8 read-write 0x00 0xFF TS31 AN31 sampling time selection bit 7 7 read-write TS30 AN30 sampling time selection bit 6 6 read-write TS29 AN29 sampling time selection bit 5 5 read-write TS28 AN28 sampling time selection bit 4 4 read-write TS27 AN27 sampling time selection bit 3 3 read-write TS26 AN26 sampling time selection bit 2 2 read-write TS25 AN25 sampling time selection bit 1 1 read-write TS24 AN24 sampling time selection bit 0 0 read-write ADSS2 Sampling Time Selection Register 2 0x28 8 read-write 0x00 0xFF TS23 AN23 sampling time selection bit 7 7 read-write TS22 AN22 sampling time selection bit 6 6 read-write TS21 AN21 sampling time selection bit 5 5 read-write TS20 AN20 sampling time selection bit 4 4 read-write TS19 AN19 sampling time selection bit 3 3 read-write TS18 AN18 sampling time selection bit 2 2 read-write TS17 AN17 sampling time selection bit 1 1 read-write TS16 AN16 sampling time selection bit 0 0 read-write ADSS1 Sampling Time Selection Register 1 0x2D 8 read-write 0x00 0xFF TS15 AN15 sampling time selection bit 7 7 read-write TS14 AN14 sampling time selection bit 6 6 read-write TS13 AN13 sampling time selection bit 5 5 read-write TS12 AN12 sampling time selection bit 4 4 read-write TS11 AN11 sampling time selection bit 3 3 read-write TS10 AN10 sampling time selection bit 2 2 read-write TS9 AN9 sampling time selection bit 1 1 read-write TS8 AN8 sampling time selection bit 0 0 read-write ADSS0 Sampling Time Selection Register 0 0x2C 8 read-write 0x00 0xFF TS7 AN7 sampling time selection bit 7 7 read-write TS6 AN6 sampling time selection bit 6 6 read-write TS5 AN5 sampling time selection bit 5 5 read-write TS4 AN4 sampling time selection bit 4 4 read-write TS3 AN3 sampling time selection bit 3 3 read-write TS2 AN2 sampling time selection bit 2 2 read-write TS1 AN1 sampling time selection bit 1 1 read-write TS0 AN0 sampling time selection bit 0 0 read-write ADST1 Sampling Time Setup Register 1 0x30 8 read-write 0x10 0xFF STX1 Sampling time N times setting bits 5 7 read-write ST1 Sampling time setting bits 0 4 read-write ADST0 Sampling Time Setup Register 0 0x31 8 read-write 0x10 0xFF STX0 Sampling time N times setting bits 5 7 read-write ST0 Sampling time setting bits 0 4 read-write ADCT Frequency Division Ratio Setup Register 0x34 8 read-write 0x07 0xFF CT Frequency division ratio setting bits 0 7 read-write PRTSL Priority Conversion Timer Trigger Selection Register 0x38 8 read-write 0x00 0x0F PRTSL Priority conversion timer trigger selection bits 0 3 read-write SCTSL Scan Conversion Timer Trigger Selection Register 0x39 8 read-write 0x00 0x0F SCTSL Scan conversion timer trigger selection bits 0 3 read-write ADCEN A/D Operation Enable Setup Register 0x3C 16 read-write 0xFF00 0xFF03 ENBLTIME Operation enable state transition cycle selection bits 8 15 read-write READY A/D operation enable state bit 1 1 read-only ENBL A/D operation enable bit 0 0 read-write WCMRCIF Range Comparison Flag Register 0x44 32 read-write 0x00000000 0x00000001 RCINT Range comparison interrupt factor flag bit 0 0 read-write WCMRCOT Range Comparison Threshold Excess Flag Register 0x48 32 read-write 0x00000000 0x00000001 RCOOF Threshold excess flag bit 0 0 read-write WCMPCR Range Comparison Control Register 0x4C 8 read-write 0x20 0xFC RCOCD Continuous detection specification count/state indication bits 5 7 read-write RCOIRS Selection bit of within-range and out-of- range confirmation 4 4 read-write RCOIE Range comparison interrupt request enable bit 3 3 read-write RCOE Range comparison execution enable bit 2 2 read-write WCMPSR Range Comparison Channel Select Register 0x4D 8 read-write 0x00 0x3F WCMD Comparison mode select bit 5 5 read-write WCCH Comparison target analog input channel 0 4 read-write WCMPDL Lower Limit Threshold Setup Register 0x50 16 read-write 0x0000 0xFFC0 CMLD Lower limit threshold bits 6 15 read-write WCMPDH Upper Limit Setup Register 0x52 16 read-write 0x0000 0xFFC0 CMHD Upper limit threshold bits 6 15 read-write CRTRIM CR Trimming Registers CRTRIM 0x4002E000 0x0 0x1 registers 0x4 0x2 registers 0x8 0x1 registers 0xC 0x4 registers MCR_PSR High-speed CR Oscillation Frequency Division Setup Register 0x0 8 read-write 0x01 0x07 CSR High-speed CR oscillation frequency division ratio setting bits 0 2 read-write MCR_FTRM High-speed CR Oscillation Frequency Trimming Register 0x4 16 read-write 0x01EF 0x03FF TRD Frequency trimming setup bits 0 9 read-write MCR_TTRM High-speed CR Oscillation Temperature Trimming Setup Register 0x8 8 read-write 0x10 0x1F TRT Temperature trimming setup bits 0 4 read-write MCR_RLR High-Speed CR Oscillation Register Write-Protect Register 0xC 32 read-write 0x00000001 0xFFFFFFFF TRMLCK Register write-protect bits 0 31 read-write EXTI External Interrupt and NMI Control EXTI 0x40030000 0x0 0x4 registers 0x4 0x4 registers 0x8 0x4 registers 0xC 0x4 registers 0x10 0x4 registers 0x14 0x2 registers 0x18 0x2 registers EXINT0_7 4 ENIR External Interrupt Enable Register 0x0 32 read-write 0x00000000 0xFFFFFFFF EN31 External interrupt Ch.31 enable bit 31 31 read-write EN30 External interrupt Ch.30 enable bit 30 30 read-write EN29 External interrupt Ch.29 enable bit 29 29 read-write EN28 External interrupt Ch.28 enable bit 28 28 read-write EN27 External interrupt Ch.27 enable bit 27 27 read-write EN26 External interrupt Ch.26 enable bit 26 26 read-write EN25 External interrupt Ch.25 enable bit 25 25 read-write EN24 External interrupt Ch.24 enable bit 24 24 read-write EN23 External interrupt Ch.23 enable bit 23 23 read-write EN22 External interrupt Ch.22 enable bit 22 22 read-write EN21 External interrupt Ch.21 enable bit 21 21 read-write EN20 External interrupt Ch.20 enable bit 20 20 read-write EN19 External interrupt Ch.19 enable bit 19 19 read-write EN18 External interrupt Ch.18 enable bit 18 18 read-write EN17 External interrupt Ch.17 enable bit 17 17 read-write EN16 External interrupt Ch.16 enable bit 16 16 read-write EN15 External interrupt Ch.15 enable bit 15 15 read-write EN14 External interrupt Ch.14 enable bit 14 14 read-write EN13 External interrupt Ch.13 enable bit 13 13 read-write EN12 External interrupt Ch.12 enable bit 12 12 read-write EN11 External interrupt Ch.11 enable bit 11 11 read-write EN10 External interrupt Ch.10 enable bit 10 10 read-write EN9 External interrupt Ch.9 enable bit 9 9 read-write EN8 External interrupt Ch.8 enable bit 8 8 read-write EN7 External interrupt Ch.7 enable bit 7 7 read-write EN6 External interrupt Ch.6 enable bit 6 6 read-write EN5 External interrupt Ch.5 enable bit 5 5 read-write EN4 External interrupt Ch.4 enable bit 4 4 read-write EN3 External interrupt Ch.3 enable bit 3 3 read-write EN2 External interrupt Ch.2 enable bit 2 2 read-write EN1 External interrupt Ch.1 enable bit 1 1 read-write EN0 External interrupt Ch.0 enable bit 0 0 read-write EIRR External Interrupt Factor Register 0x4 32 read-only 0x00000000 0xFFFFFFFF ER31 External interrupt Ch.31 request detection bit 31 31 read-only ER30 External interrupt Ch.30 request detection bit 30 30 read-only ER29 External interrupt Ch.29 request detection bit 29 29 read-only ER28 External interrupt Ch.28 request detection bit 28 28 read-only ER27 External interrupt Ch.27 request detection bit 27 27 read-only ER26 External interrupt Ch.26 request detection bit 26 26 read-only ER25 External interrupt Ch.25 request detection bit 25 25 read-only ER24 External interrupt Ch.24 request detection bit 24 24 read-only ER23 External interrupt Ch.23 request detection bit 23 23 read-only ER22 External interrupt Ch.22 request detection bit 22 22 read-only ER21 External interrupt Ch.21 request detection bit 21 21 read-only ER20 External interrupt Ch.20 request detection bit 20 20 read-only ER19 External interrupt Ch.19 request detection bit 19 19 read-only ER18 External interrupt Ch.18 request detection bit 18 18 read-only ER17 External interrupt Ch.17 request detection bit 17 17 read-only ER16 External interrupt Ch.16 request detection bit 16 16 read-only ER15 External interrupt Ch.15 request detection bit 15 15 read-only ER14 External interrupt Ch.14 request detection bit 14 14 read-only ER13 External interrupt Ch.13 request detection bit 13 13 read-only ER12 External interrupt Ch.12 request detection bit 12 12 read-only ER11 External interrupt Ch.11 request detection bit 11 11 read-only ER10 External interrupt Ch.10 request detection bit 10 10 read-only ER9 External interrupt Ch.9 request detection bit 9 9 read-only ER8 External interrupt Ch.8 request detection bit 8 8 read-only ER7 External interrupt Ch.7 request detection bit 7 7 read-only ER6 External interrupt Ch.6 request detection bit 6 6 read-only ER5 External interrupt Ch.5 request detection bit 5 5 read-only ER4 External interrupt Ch.4 request detection bit 4 4 read-only ER3 External interrupt Ch.3 request detection bit 3 3 read-only ER2 External interrupt Ch.2 request detection bit 2 2 read-only ER1 External interrupt Ch.1 request detection bit 1 1 read-only ER0 External interrupt Ch.0 request detection bit 0 0 read-only EICL External Interrupt Factor Clear Register 0x8 32 read-write 0xFFFFFFFF 0xFFFFFFFF ECL31 External interrupt Ch.31 factor clear bit 31 31 read-write ECL30 External interrupt Ch.30 factor clear bit 30 30 read-write ECL29 External interrupt Ch.29 factor clear bit 29 29 read-write ECL28 External interrupt Ch.28 factor clear bit 28 28 read-write ECL27 External interrupt Ch.27 factor clear bit 27 27 read-write ECL26 External interrupt Ch.26 factor clear bit 26 26 read-write ECL25 External interrupt Ch.25 factor clear bit 25 25 read-write ECL24 External interrupt Ch.24 factor clear bit 24 24 read-write ECL23 External interrupt Ch.23 factor clear bit 23 23 read-write ECL22 External interrupt Ch.22 factor clear bit 22 22 read-write ECL21 External interrupt Ch.21 factor clear bit 21 21 read-write ECL20 External interrupt Ch.20 factor clear bit 20 20 read-write ECL19 External interrupt Ch.19 factor clear bit 19 19 read-write ECL18 External interrupt Ch.18 factor clear bit 18 18 read-write ECL17 External interrupt Ch.17 factor clear bit 17 17 read-write ECL16 External interrupt Ch.16 factor clear bit 16 16 read-write ECL15 External interrupt Ch.15 factor clear bit 15 15 read-write ECL14 External interrupt Ch.14 factor clear bit 14 14 read-write ECL13 External interrupt Ch.13 factor clear bit 13 13 read-write ECL12 External interrupt Ch.12 factor clear bit 12 12 read-write ECL11 External interrupt Ch.11 factor clear bit 11 11 read-write ECL10 External interrupt Ch.10 factor clear bit 10 10 read-write ECL9 External interrupt Ch.9 factor clear bit 9 9 read-write ECL8 External interrupt Ch.8 factor clear bit 8 8 read-write ECL7 External interrupt Ch.7 factor clear bit 7 7 read-write ECL6 External interrupt Ch.6 factor clear bit 6 6 read-write ECL5 External interrupt Ch.5 factor clear bit 5 5 read-write ECL4 External interrupt Ch.4 factor clear bit 4 4 read-write ECL3 External interrupt Ch.3 factor clear bit 3 3 read-write ECL2 External interrupt Ch.2 factor clear bit 2 2 read-write ECL1 External interrupt Ch.1 factor clear bit 1 1 read-write ECL0 External interrupt Ch.0 factor clear bit 0 0 read-write ELVR External Interrupt Factor Level Register 0xC 32 read-write 0x00000000 0xFFFFFFFF LB15 Bit31 of ELVR 31 31 read-write LA15 Bit30 of ELVR 30 30 read-write LB14 Bit29 of ELVR 29 29 read-write LA14 Bit28 of ELVR 28 28 read-write LB13 Bit27 of ELVR 27 27 read-write LA13 Bit26 of ELVR 26 26 read-write LB12 Bit25 of ELVR 25 25 read-write LA12 Bit24 of ELVR 24 24 read-write LB11 Bit23 of ELVR 23 23 read-write LA11 Bit22 of ELVR 22 22 read-write LB10 Bit21 of ELVR 21 21 read-write LA10 Bit20 of ELVR 20 20 read-write LB9 Bit19 of ELVR 19 19 read-write LA9 Bit18 of ELVR 18 18 read-write LB8 Bit17 of ELVR 17 17 read-write LA8 Bit16 of ELVR 16 16 read-write LB7 Bit15 of ELVR 15 15 read-write LA7 Bit14 of ELVR 14 14 read-write LB6 Bit13 of ELVR 13 13 read-write LA6 Bit12 of ELVR 12 12 read-write LB5 Bit11 of ELVR 11 11 read-write LA5 Bit10 of ELVR 10 10 read-write LB4 Bit9 of ELVR 9 9 read-write LA4 Bit8 of ELVR 8 8 read-write LB3 Bit7 of ELVR 7 7 read-write LA3 Bit6 of ELVR 6 6 read-write LB2 Bit5 of ELVR 5 5 read-write LA2 Bit4 of ELVR 4 4 read-write LB1 Bit3 of ELVR 3 3 read-write LA1 Bit2 of ELVR 2 2 read-write LB0 Bit1 of ELVR 1 1 read-write LA0 Bit0 of ELVR 0 0 read-write ELVR1 External Interrupt Factor Level Register 1 0x10 32 read-write 0x00000000 0xFFFFFFFF LB31 Bit31 of ELVR1 31 31 read-write LA31 Bit30 of ELVR1 30 30 read-write LB30 Bit29 of ELVR1 29 29 read-write LA30 Bit28 of ELVR1 28 28 read-write LB29 Bit27 of ELVR1 27 27 read-write LA29 Bit26 of ELVR1 26 26 read-write LB28 Bit25 of ELVR1 25 25 read-write LA28 Bit24 of ELVR1 24 24 read-write LB27 Bit23 of ELVR1 23 23 read-write LA27 Bit22 of ELVR1 22 22 read-write LB26 Bit21 of ELVR1 21 21 read-write LA26 Bit20 of ELVR1 20 20 read-write LB25 Bit19 of ELVR1 19 19 read-write LA25 Bit18 of ELVR1 18 18 read-write LB24 Bit17 of ELVR1 17 17 read-write LA24 Bit16 of ELVR1 16 16 read-write LB23 Bit15 of ELVR1 15 15 read-write LA23 Bit14 of ELVR1 14 14 read-write LB22 Bit13 of ELVR1 13 13 read-write LA22 Bit12 of ELVR1 12 12 read-write LB21 Bit11 of ELVR1 11 11 read-write LA21 Bit10 of ELVR1 10 10 read-write LB20 Bit9 of ELVR1 9 9 read-write LA20 Bit8 of ELVR1 8 8 read-write LB19 Bit7 of ELVR1 7 7 read-write LA19 Bit6 of ELVR1 6 6 read-write LB18 Bit5 of ELVR1 5 5 read-write LA18 Bit4 of ELVR1 4 4 read-write LB17 Bit3 of ELVR1 3 3 read-write LA17 Bit2 of ELVR1 2 2 read-write LB16 Bit1 of ELVR1 1 1 read-write LA16 Bit0 of ELVR1 0 0 read-write NMIRR Non Maskable Interrupt Factor Register 0x14 16 read-only 0x0000 0x0001 NR NMI interrupt request detection bit 0 0 read-only NMICL Non Maskable Interrupt Factor Clear Register 0x18 16 read-write 0x0001 0x0001 NCL NMI interrupt factor clear bit 0 0 read-write INTREQ Interrupts INTREQ 0x40031000 0x0 0x4 registers 0xC 0x4 registers 0x10 0x4 registers 0x14 0x4 registers 0x18 0x4 registers 0x1C 0x4 registers 0x20 0x4 registers 0x24 0x4 registers 0x28 0x4 registers 0x2C 0x4 registers 0x30 0x4 registers 0x34 0x4 registers 0x38 0x4 registers 0x3C 0x4 registers 0x40 0x4 registers 0x44 0x4 registers 0x48 0x4 registers 0x4C 0x4 registers 0x50 0x4 registers 0x54 0x4 registers 0x58 0x4 registers 0x5C 0x4 registers 0x60 0x4 registers 0x64 0x4 registers 0x68 0x4 registers 0x6C 0x4 registers 0x70 0x4 registers 0x74 0x4 registers 0x78 0x4 registers 0x7C 0x4 registers 0x80 0x4 registers 0x84 0x4 registers 0x88 0x4 registers 0x8C 0x4 registers 0x90 0x4 registers 0x210 0x4 registers 0x214 0x4 registers DRQSEL DMA Request Selection Register 0x0 32 read-write 0x00000000 0xFFFFFFE0 EXINT3 The interrupt signal of the external interrupt ch.3 is output as a transfer request to the DMAC 31 31 read-write EXINT2 The interrupt signal of the external interrupt ch.2 is output as a transfer request to the DMAC 30 30 read-write EXINT1 The interrupt signal of the external interrupt ch.1 is output as a transfer request to the DMAC 29 29 read-write EXINT0 The interrupt signal of the external interrupt ch.0 is output as a transfer request to the DMAC 28 28 read-write MFS7TX The transmission interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC 27 27 read-write MFS7RX The reception interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC 26 26 read-write MFS6TX The transmission interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC 25 25 read-write MFS6RX The reception interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC 24 24 read-write MFS5TX The transmission interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC 23 23 read-write MFS5RX The reception interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC 22 22 read-write MFS4TX The transmission interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC 21 21 read-write MFS4RX The reception interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC 20 20 read-write MFS3TX The transmission interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC 19 19 read-write MFS3RX The reception interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC 18 18 read-write MFS2TX The transmission interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC 17 17 read-write MFS2RX The reception interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC 16 16 read-write MFS1TX The transmission interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC 15 15 read-write MFS1RX The reception interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC 14 14 read-write MFS0TX The transmission interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC 13 13 read-write MFS0RX The reception interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC 12 12 read-write IRQ0BT6 The IRQ0 interrupt signal of the base timer ch.6 is output as a transfer request to the DMAC 11 11 read-write IRQ0BT4 The IRQ0 interrupt signal of the base timer ch.4 is output as a transfer request to the DMAC 10 10 read-write IRQ0BT2 The IRQ0 interrupt signal of the base timer ch.2 is output as a transfer request to the DMAC 9 9 read-write IRQ0BT0 The IRQ0 interrupt signal of the base timer ch.0 is output as a transfer request to the DMAC 8 8 read-write ADCSCAN2 The scan conversion interrupt signal of the A/D converter unit 2 is output as a transfer request to the DMAC 7 7 read-write ADCSCAN1 The scan conversion interrupt signal of the A/D converter unit 1 is output as a transfer request to the DMAC 6 6 read-write ADCSCAN0 The scan conversion interrupt signal of the A/D converter unit 0 is output as a transfer request to the DMAC 5 5 read-write IRQCMODE Interrupt Factor Vector Relocate Setting Register 0xC 32 read-write 0x00000000 0x00000001 IRQCMODE Assigns the interrupt factor vector according to Table 1-1 in chapter "Interrupt B" 0 0 read-write EXC02MON EXC02 Batch Read Register 0x10 32 read-only 0x00000000 0x00000003 HWINT Hardware watchdog timer interrupt request 1 1 read-only NMI NMIX external pin interrupt request 0 0 read-only IRQ00MON IRQ00 Batch Read Register 0x14 32 read-only 0x00000000 0x00000001 FCSINT Anomalous frequency detection by CSV interrupt request 0 0 read-only IRQ01MON IRQ01 Batch Read Register 0x18 32 read-only 0x00000000 0x00000001 SWWDTINT Software watchdog timer interrupt request 0 0 read-only IRQ02MON IRQ02 Batch Read Register 0x1C 32 read-only 0x00000000 0x00000001 LVDINT Low voltage detection (LVD) interrupt request 0 0 read-only IRQ03MON IRQ03 Batch Read Register 0x20 32 read-only 0x00000000 0x00000FFF WAVE2INT3 WFG timer 54 interrupt request in MFT unit 2 11 11 read-only WAVE2INT2 WFG timer 32 interrupt request in MFT unit 2 10 10 read-only WAVE2INT1 WFG timer 10 interrupt request in MFT unit 2 9 9 read-only WAVE2INT0 DTIF (motor emergency stop) interrupt request in MFT unit 2 8 8 read-only WAVE1INT3 WFG timer 54 interrupt request in MFT unit 1 7 7 read-only WAVE1INT2 WFG timer 32 interrupt request in MFT unit 1 6 6 read-only WAVE1INT1 WFG timer 10 interrupt request in MFT unit 1 5 5 read-only WAVE1INT0 DTIF (motor emergency stop) interrupt request in MFT unit 1 4 4 read-only WAVE0INT3 WFG timer 54 interrupt request in MFT unit 0 3 3 read-only WAVE0INT2 WFG timer 32 interrupt request in MFT unit 0 2 2 read-only WAVE0INT1 WFG timer 10 interrupt request in MFT unit 0 1 1 read-only WAVE0INT0 DTIF (motor emergency stop) interrupt request in MFT unit 0 0 0 read-only IRQ04MON IRQ04 Batch Read Register 0x24 32 read-only 0x00000000 0x000000FF EXTINT7 Interrupt request of external interrupt ch.7 7 7 read-only EXTINT6 Interrupt request of external interrupt ch.6 6 6 read-only EXTINT5 Interrupt request of external interrupt ch.5 5 5 read-only EXTINT4 Interrupt request of external interrupt ch.4 4 4 read-only EXTINT3 Interrupt request of external interrupt ch.3 3 3 read-only EXTINT2 Interrupt request of external interrupt ch.2 2 2 read-only EXTINT1 Interrupt request of external interrupt ch.1 1 1 read-only EXTINT0 Interrupt request of external interrupt ch.0 0 0 read-only IRQ05MON IRQ05 Batch Read Register 0x28 32 read-only 0x00000000 0x00FFFFFF EXTINT31 Interrupt request of external interrupt ch.31 23 23 read-only EXTINT30 Interrupt request of external interrupt ch.30 22 22 read-only EXTINT29 Interrupt request of external interrupt ch.29 21 21 read-only EXTINT28 Interrupt request of external interrupt ch.28 20 20 read-only EXTINT27 Interrupt request of external interrupt ch.27 19 19 read-only EXTINT26 Interrupt request of external interrupt ch.26 18 18 read-only EXTINT25 Interrupt request of external interrupt ch.25 17 17 read-only EXTINT24 Interrupt request of external interrupt ch.24 16 16 read-only EXTINT23 Interrupt request of external interrupt ch.23 15 15 read-only EXTINT22 Interrupt request of external interrupt ch.22 14 14 read-only EXTINT21 Interrupt request of external interrupt ch.21 13 13 read-only EXTINT20 Interrupt request of external interrupt ch.20 12 12 read-only EXTINT19 Interrupt request of external interrupt ch.19 11 11 read-only EXTINT18 Interrupt request of external interrupt ch.18 10 10 read-only EXTINT17 Interrupt request of external interrupt ch.17 9 9 read-only EXTINT16 Interrupt request of external interrupt ch.16 8 8 read-only EXTINT15 Interrupt request of external interrupt ch.15 7 7 read-only EXTINT14 Interrupt request of external interrupt ch.14 6 6 read-only EXTINT13 Interrupt request of external interrupt ch.13 5 5 read-only EXTINT12 Interrupt request of external interrupt ch.12 4 4 read-only EXTINT11 Interrupt request of external interrupt ch.11 3 3 read-only EXTINT10 Interrupt request of external interrupt ch.10 2 2 read-only EXTINT9 Interrupt request of external interrupt ch.9 1 1 read-only EXTINT8 Interrupt request of external interrupt ch.8 0 0 read-only IRQ06MON IRQ06 Batch Read Register 0x2C 32 read-only 0x00000000 0x000FFFFF QUD2INT5 PC match and RC match interrupt request of QPRC ch.2 19 19 read-only QUD2INT4 Interrupt request detected RC out of range of QPRC ch.2 18 18 read-only QUD2INT3 PC count invert interrupt request of QPRC ch.2 17 17 read-only QUD2INT2 Overflow/underflow/zero index interrupt request of QPRC ch.2 16 16 read-only QUD2INT1 PC and RC match interrupt request of QPRC ch.2 15 15 read-only QUD2INT0 PC match interrupt request of QPRC ch.2 14 14 read-only QUD1INT5 PC match and RC match interrupt request of QPRC ch.1 13 13 read-only QUD1INT4 Interrupt request detected RC out of range of QPRC ch.1 12 12 read-only QUD1INT3 PC count invert interrupt request of QPRC ch.1 11 11 read-only QUD1INT2 Overflow/underflow/zero index interrupt request of QPRC ch.1 10 10 read-only QUD1INT1 PC and RC match interrupt request of QPRC ch.1 9 9 read-only QUD1INT0 PC match interrupt request of QPRC ch.1 8 8 read-only QUD0INT5 PC match and RC match interrupt request of QPRC ch.0 7 7 read-only QUD0INT4 Interrupt request detected RC out of range of QPRC ch.0 6 6 read-only QUD0INT3 PC count invert interrupt request of QPRC ch.0 5 5 read-only QUD0INT2 Overflow/underflow/zero index interrupt request of QPRC ch.0 4 4 read-only QUD0INT1 PC and RC match interrupt request of QPRC ch.0 3 3 read-only QUD0INT0 PC match interrupt request of QPRC ch.0 2 2 read-only TIMINT2 Dual timer TIMINT2 interrupt request 1 1 read-only TIMINT1 Dual timer TIMINT1 interrupt request 0 0 read-only IRQ07MON IRQ07 Batch Read Register 0x30 32 read-only 0x00000000 0x00000003 MFSINT1 Reception interrupt request of MFS channel 8 1 1 read-only MFSINT0 Reception interrupt request of MFS channel 0 0 0 read-only IRQ08MON IRQ08 Batch Read Register 0x34 32 read-only 0x00000000 0x0000000F MFSINT3 Status interrupt request of MFS channel 8 3 3 read-only MFSINT2 Transmission interrupt request of MFS channel 8 2 2 read-only MFSINT1 Status interrupt request of MFS channel 0 1 1 read-only MFSINT0 Transmission interrupt request of MFS channel 0 0 0 read-only IRQ09MON IRQ09 Batch Read Register 0x38 32 read-only 0x00000000 0x00000003 MFSINT1 Reception interrupt request of MFS channel 9 1 1 read-only MFSINT0 Reception interrupt request of MFS channel 1 0 0 read-only IRQ10MON IRQ10 Batch Read Register 0x3C 32 read-only 0x00000000 0x0000000F MFSINT3 Status interrupt request of MFS channel 9 3 3 read-only MFSINT2 Transmission interrupt request of MFS channel 9 2 2 read-only MFSINT1 Status interrupt request of MFS channel 1 1 1 read-only MFSINT0 Transmission interrupt request of MFS channel 1 0 0 read-only IRQ11MON IRQ11 Batch Read Register 0x40 32 read-only 0x00000000 0x00000003 MFSINT1 Reception interrupt request of MFS channel 10 1 1 read-only MFSINT0 Reception interrupt request of MFS channel 2 0 0 read-only IRQ12MON IRQ12 Batch Read Register 0x44 32 read-only 0x00000000 0x0000000F MFSINT3 Status interrupt request of MFS channel 10 3 3 read-only MFSINT2 Transmission interrupt request of MFS channel 10 2 2 read-only MFSINT1 Status interrupt request of MFS channel 2 1 1 read-only MFSINT0 Transmission interrupt request of MFS channel 2 0 0 read-only IRQ13MON IRQ13 Batch Read Register 0x48 32 read-only 0x00000000 0x00000003 MFSINT1 Reception interrupt request of MFS channel 11 1 1 read-only MFSINT0 Reception interrupt request of MFS channel 3 0 0 read-only IRQ14MON IRQ14 Batch Read Register 0x4C 32 read-only 0x00000000 0x0000000F MFSINT3 Status interrupt request of MFS channel 11 3 3 read-only MFSINT2 Transmission interrupt request of MFS channel 11 2 2 read-only MFSINT1 Status interrupt request of MFS channel 3 1 1 read-only MFSINT0 Transmission interrupt request of MFS channel 3 0 0 read-only IRQ15MON IRQ15 Batch Read Register 0x50 32 read-only 0x00000000 0x00000003 MFSINT1 Reception interrupt request of MFS channel 12 1 1 read-only MFSINT0 Reception interrupt request of MFS channel 4 0 0 read-only IRQ16MON IRQ16 Batch Read Register 0x54 32 read-only 0x00000000 0x0000000F MFSINT3 Status interrupt request of MFS channel 12 3 3 read-only MFSINT2 Transmission interrupt request of MFS channel 12 2 2 read-only MFSINT1 Status interrupt request of MFS channel 4 1 1 read-only MFSINT0 Transmission interrupt request of MFS channel 4 0 0 read-only IRQ17MON IRQ17 Batch Read Register 0x58 32 read-only 0x00000000 0x00000003 MFSINT1 Reception interrupt request of MFS channel 13 1 1 read-only MFSINT0 Reception interrupt request of MFS channel 5 0 0 read-only IRQ18MON IRQ18 Batch Read Register 0x5C 32 read-only 0x00000000 0x0000000F MFSINT3 Status interrupt request of MFS channel 13 3 3 read-only MFSINT2 Transmission interrupt request of MFS channel 13 2 2 read-only MFSINT1 Status interrupt request of MFS channel 5 1 1 read-only MFSINT0 Transmission interrupt request of MFS channel 5 0 0 read-only IRQ19MON IRQ19 Batch Read Register 0x60 32 read-only 0x00000000 0x00000013 DMAINT Interrupt request of DMAC ch.0 4 4 read-only MFSINT1 Reception interrupt request of MFS channel 14 1 1 read-only MFSINT0 Reception interrupt request of MFS channel 6 0 0 read-only IRQ20MON IRQ20 Batch Read Register 0x64 32 read-only 0x00000000 0x0000001F DMAINT Interrupt request of DMAC ch.1 4 4 read-only MFSINT3 Status interrupt request of MFS channel 14 3 3 read-only MFSINT2 Transmission interrupt request of MFS channel 14 2 2 read-only MFSINT1 Status interrupt request of MFS channel 6 1 1 read-only MFSINT0 Transmission interrupt request of MFS channel 6 0 0 read-only IRQ21MON IRQ21 Batch Read Register 0x68 32 read-only 0x00000000 0x00000013 DMAINT Interrupt request of DMAC ch.2 4 4 read-only MFSINT1 Reception interrupt request of MFS channel 15 1 1 read-only MFSINT0 Reception interrupt request of MFS channel 7 0 0 read-only IRQ22MON IRQ22 Batch Read Register 0x6C 32 read-only 0x00000000 0x0000001F DMAINT Interrupt request of DMAC ch.3 4 4 read-only MFSINT3 Status interrupt request of MFS channel 15 3 3 read-only MFSINT2 Transmission interrupt request of MFS channel 15 2 2 read-only MFSINT1 Status interrupt request of MFS channel 7 1 1 read-only MFSINT0 Transmission interrupt request of MFS channel 7 0 0 read-only IRQ23MON IRQ23 Batch Read Register 0x70 32 read-only 0x00000000 0x000001FF PPGINT8 Interrupt request of PPG ch.20 8 8 read-only PPGINT7 Interrupt request of PPG ch.18 7 7 read-only PPGINT6 Interrupt request of PPG ch.16 6 6 read-only PPGINT5 Interrupt request of PPG ch.12 5 5 read-only PPGINT4 Interrupt request of PPG ch.10 4 4 read-only PPGINT3 Interrupt request of PPG ch.8 3 3 read-only PPGINT2 Interrupt request of PPG ch.4 2 2 read-only PPGINT1 Interrupt request of PPG ch.2 1 1 read-only PPGINT0 Interrupt request of PPG ch.0 0 0 read-only IRQ24MON IRQ24 Batch Read Register 0x74 32 read-only 0x00000000 0x00000037 RTCINT RTC interrupt request 5 5 read-only WCINT Watch counter interrupt request 4 4 read-only MPLLINT Stabilization wait completion interrupt request for main PLL oscillation 2 2 read-only SOSCINT Stabilization wait completion interrupt request for sub-clock oscillation 1 1 read-only MOSCINT Stabilization wait completion interrupt request for main clock oscillation 0 0 read-only IRQ25MON IRQ25 Batch Read Register 0x78 32 read-only 0x00000000 0x0000001F ADCINT4 Range comparison result interrupt request in the A/D converter unit 0 4 4 read-only ADCINT3 Conversion result comparison interrupt request in the A/D converter unit 0 3 3 read-only ADCINT2 FIFO overrun interrupt request in the A/D converter unit 0 2 2 read-only ADCINT1 Scan conversion interrupt request in the A/D converter unit 0 1 1 read-only ADCINT0 Priority conversion interrupt request in the A/D converter unit 0 0 0 read-only IRQ26MON IRQ26 Batch Read Register 0x7C 32 read-only 0x00000000 0x0000001F ADCINT4 Range comparison result interrupt request in the A/D converter unit 1 4 4 read-only ADCINT3 Conversion result comparison interrupt request in the A/D converter unit 1 3 3 read-only ADCINT2 FIFO overrun interrupt request in the A/D converter unit 1 2 2 read-only ADCINT1 Scan conversion interrupt request in the A/D converter unit 1 1 1 read-only ADCINT0 Priority conversion interrupt request in the A/D converter unit 1 0 0 read-only IRQ27MON IRQ27 Batch Read Register 0x80 32 read-only 0x00000000 0x0000003F LCDCINT Interrupt request for LCD controller 5 5 read-only ADCINT4 Range comparison result interrupt request in the A/D converter unit 2 4 4 read-only ADCINT3 Conversion result comparison interrupt request in the A/D converter unit 2 3 3 read-only ADCINT2 FIFO overrun interrupt request in the A/D converter unit 2 2 2 read-only ADCINT1 Scan conversion interrupt request in the A/D converter unit 2 1 1 read-only ADCINT0 Priority conversion interrupt request in the A/D converter unit 2 0 0 read-only IRQ28MON IRQ28 Batch Read Register 0x84 32 read-only 0x00000000 0x0003FFFF FRT2INT5 Zero detection interrupt request of the free run timer ch.2 in the MFT unit 2 17 17 read-only FRT2INT4 Zero detection interrupt request of the free run timer ch.1 in the MFT unit 2 16 16 read-only FRT2INT3 Zero detection interrupt request of the free run timer ch.0 in the MFT unit 2 15 15 read-only FRT2INT2 Peak value detection interrupt request of the free run timer ch.2 in the MFT unit 2 14 14 read-only FRT2INT1 Peak value detection interrupt request of the free run timer ch.1 in the MFT unit 2 13 13 read-only FRT2INT0 Peak value detection interrupt request of the free run timer ch.0 in the MFT unit 2 12 12 read-only FRT1INT5 Zero detection interrupt request of the free run timer ch.2 in the MFT unit 1 11 11 read-only FRT1INT4 Zero detection interrupt request of the free run timer ch.1 in the MFT unit 1 10 10 read-only FRT1INT3 Zero detection interrupt request of the free run timer ch.0 in the MFT unit 1 9 9 read-only FRT1INT2 Peak value detection interrupt request of the free run timer ch.2 in the MFT unit 1 8 8 read-only FRT1INT1 Peak value detection interrupt request of the free run timer ch.1 in the MFT unit 1 7 7 read-only FRT1INT0 Peak value detection interrupt request of the free run timer ch.0 in the MFT unit 1 6 6 read-only FRT0INT5 Zero detection interrupt request of the free run timer ch.2 in the MFT unit 0 5 5 read-only FRT0INT4 Zero detection interrupt request of the free run timer ch.1 in the MFT unit 0 4 4 read-only FRT0INT3 Zero detection interrupt request of the free run timer ch.0 in the MFT unit 0 3 3 read-only FRT0INT2 Peak value detection interrupt request of the free run timer ch.2 in the MFT unit 0 2 2 read-only FRT0INT1 Peak value detection interrupt request of the free run timer ch.1 in the MFT unit 0 1 1 read-only FRT0INT0 Peak value detection interrupt request of the free run timer ch.0 in the MFT unit 0 0 0 read-only IRQ29MON IRQ29 Batch Read Register 0x88 32 read-only 0x00000000 0x00000FFF ICU2INT3 Interrupt request of the input capture ch.3 in the MFT unit 2 11 11 read-only ICU2INT2 Interrupt request of the input capture ch.2 in the MFT unit 2 10 10 read-only ICU2INT1 Interrupt request of the input capture ch.1 in the MFT unit 2 9 9 read-only ICU2INT0 Interrupt request of the input capture ch.0 in the MFT unit 2 8 8 read-only ICU1INT3 Interrupt request of the input capture ch.3 in the MFT unit 1 7 7 read-only ICU1INT2 Interrupt request of the input capture ch.2 in the MFT unit 1 6 6 read-only ICU1INT1 Interrupt request of the input capture ch.1 in the MFT unit 1 5 5 read-only ICU1INT0 Interrupt request of the input capture ch.0 in the MFT unit 1 4 4 read-only ICU0INT3 Interrupt request of the input capture ch.3 in the MFT unit 0 3 3 read-only ICU0INT2 Interrupt request of the input capture ch.2 in the MFT unit 0 2 2 read-only ICU0INT1 Interrupt request of the input capture ch.1 in the MFT unit 0 1 1 read-only ICU0INT0 Interrupt request of the input capture ch.0 in the MFT unit 0 0 0 read-only IRQ30MON IRQ30 Batch Read Register 0x8C 32 read-only 0x00000000 0x0003FFFF OCU2INT5 Interrupt request of the output compare ch.5 in the MFT unit 2 17 17 read-only OCU2INT4 Interrupt request of the output compare ch.4 in the MFT unit 2 16 16 read-only OCU2INT3 Interrupt request of the output compare ch.3 in the MFT unit 2 15 15 read-only OCU2INT2 Interrupt request of the output compare ch.2 in the MFT unit 2 14 14 read-only OCU2INT1 Interrupt request of the output compare ch.1 in the MFT unit 2 13 13 read-only OCU2INT0 Interrupt request of the output compare ch.0 in the MFT unit 2 12 12 read-only OCU1INT5 Interrupt request of the output compare ch.5 in the MFT unit 1 11 11 read-only OCU1INT4 Interrupt request of the output compare ch.4 in the MFT unit 1 10 10 read-only OCU1INT3 Interrupt request of the output compare ch.3 in the MFT unit 1 9 9 read-only OCU1INT2 Interrupt request of the output compare ch.2 in the MFT unit 1 8 8 read-only OCU1INT1 Interrupt request of the output compare ch.1 in the MFT unit 1 7 7 read-only OCU1INT0 Interrupt request of the output compare ch.0 in the MFT unit 1 6 6 read-only OCU0INT5 Interrupt request of the output compare ch.5 in the MFT unit 0 5 5 read-only OCU0INT4 Interrupt request of the output compare ch.4 in the MFT unit 0 4 4 read-only OCU0INT3 Interrupt request of the output compare ch.3 in the MFT unit 0 3 3 read-only OCU0INT2 Interrupt request of the output compare ch.2 in the MFT unit 0 2 2 read-only OCU0INT1 Interrupt request of the output compare ch.1 in the MFT unit 0 1 1 read-only OCU0INT0 Interrupt request of the output compare ch.0 in the MFT unit 0 0 0 read-only IRQ31MON IRQ31 Batch Read Register 0x90 32 read-only 0x00000000 0x0800FFFF FLASHINT RDY/HANG interrupt request for f lash memory 27 27 read-only BTINT15 IRQ1 interrupt request of the base timer ch.7 15 15 read-only BTINT14 IRQ0 interrupt request of the base timer ch.7 14 14 read-only BTINT13 IRQ1 interrupt request of the base timer ch.6 13 13 read-only BTINT12 IRQ0 interrupt request of the base timer ch.6 12 12 read-only BTINT11 IRQ1 interrupt request of the base timer ch.5 11 11 read-only BTINT10 IRQ0 interrupt request of the base timer ch.5 10 10 read-only BTINT9 IRQ1 interrupt request of the base timer ch.4 9 9 read-only BTINT8 IRQ0 interrupt request of the base timer ch.4 8 8 read-only BTINT7 IRQ1 interrupt request of the base timer ch.3 7 7 read-only BTINT6 IRQ0 interrupt request of the base timer ch.3 6 6 read-only BTINT5 IRQ1 interrupt request of the base timer ch.2 5 5 read-only BTINT4 IRQ0 interrupt request of the base timer ch.2 4 4 read-only BTINT3 IRQ1 interrupt request of the base timer ch.1 3 3 read-only BTINT2 IRQ0 interrupt request of the base timer ch.1 2 2 read-only BTINT1 IRQ1 interrupt request of the base timer ch.0 1 1 read-only BTINT0 IRQ0 interrupt request of the base timer ch.0 0 0 read-only RCINTSEL0 Interrupt Factor Selection Register 0 0x210 32 read-write 0x0 0xFFFFFFFF INTSEL3 Select the interrupt factor for the interrupt vector No.22 24 31 read-write INTSEL2 Select the interrupt factor for the interrupt vector No.21 16 23 read-write INTSEL1 Select the interrupt factor for the interrupt vector No.20 8 15 read-write INTSEL0 Select the interrupt factor for the interrupt vector No.19 0 7 read-write RCINTSEL1 Interrupt Factor Selection Register 1 0x214 32 read-write 0x0 0xFFFFFFFF INTSEL7 Select the interrupt factor for the interrupt vector No.26 24 31 read-write INTSEL6 Select the interrupt factor for the interrupt vector No.25 16 23 read-write INTSEL5 Select the interrupt factor for the interrupt vector No.24 8 15 read-write INTSEL4 Select the interrupt factor for the interrupt vector No.23 0 7 read-write GPIO I/O Port Registers GPIO 0x40033000 0x0 0x40 registers 0x100 0x40 registers 0x200 0x40 registers 0x300 0x40 registers 0x400 0x40 registers 0x500 0x4 registers 0x580 0x4 registers 0x600 0x2C registers 0x630 0x1C registers 0x654 0x8 registers 0x700 0x40 registers 0x900 0x40 registers PFR0 Port Function Setting Register 0 0x0 32 read-write 0x0000000A 0x0000801F P0F Bit15 of PFR0 15 15 read-write P04 Bit4 of PFR0 4 4 read-write P03 Bit3 of PFR0 3 3 read-write P02 Bit2 of PFR0 2 2 read-write P01 Bit1 of PFR0 1 1 read-write P00 Bit0 of PFR0 0 0 read-write PFR1 Port Function Setting Register 1 0x4 32 read-write 0x00000000 0x0000003F P15 Bit5 of PFR1 5 5 read-write P14 Bit4 of PFR1 4 4 read-write P13 Bit3 of PFR1 3 3 read-write P12 Bit2 of PFR1 2 2 read-write P11 Bit1 of PFR1 1 1 read-write P10 Bit0 of PFR1 0 0 read-write PFR2 Port Function Setting Register 2 0x8 32 read-write 0x00000000 0x0000000E P23 Bit3 of PFR2 3 3 read-write P22 Bit2 of PFR2 2 2 read-write P21 Bit1 of PFR2 1 1 read-write PFR3 Port Function Setting Register 3 0xC 32 read-write 0x00000000 0x0000FE00 P3F Bit15 of PFR3 15 15 read-write P3E Bit14 of PFR3 14 14 read-write P3D Bit13 of PFR3 13 13 read-write P3C Bit12 of PFR3 12 12 read-write P3B Bit11 of PFR3 11 11 read-write P3A Bit10 of PFR3 10 10 read-write P39 Bit9 of PFR3 9 9 read-write PFR4 Port Function Setting Register 4 0x10 32 read-write 0x00000000 0x000006C0 P4A Bit10 of PFR4 10 10 read-write P49 Bit9 of PFR4 9 9 read-write P47 Bit7 of PFR4 7 7 read-write P46 Bit6 of PFR4 6 6 read-write PFR5 Port Function Setting Register 5 0x14 32 read-write 0x00000000 0x00000007 P52 Bit2 of PFR5 2 2 read-write P51 Bit1 of PFR5 1 1 read-write P50 Bit0 of PFR5 0 0 read-write PFR6 Port Function Setting Register 6 0x18 32 read-write 0x00000000 0x00000003 P61 Bit1 of PFR6 1 1 read-write P60 Bit0 of PFR6 0 0 read-write PFR8 Port Function Setting Register 8 0x20 32 read-write 0x00000000 0x00000007 P82 Bit2 of PFR8 2 2 read-write P81 Bit1 of PFR8 1 1 read-write P80 Bit0 of PFR8 0 0 read-write PFRE Port Function Setting Register E 0x38 32 read-write 0x00000000 0x0000000D PE3 Bit3 of PFRE 3 3 read-write PE2 Bit2 of PFRE 2 2 read-write PE0 Bit0 of PFRE 0 0 read-write PCR0 Pull-up Setting Register 0 0x100 PCR1 Pull-up Setting Register 1 0x104 PCR2 Pull-up Setting Register 2 0x108 PCR3 Pull-up Setting Register 3 0x10C PCR4 Pull-up Setting Register 4 0x110 PCR5 Pull-up Setting Register 5 0x114 PCR6 Pull-up Setting Register 6 0x118 PCR8 Pull-up Setting Register 8 0x120 PCRE Pull-up Setting Register E 0x138 DDR0 Port input/output Direction Setting Register 0 0x200 32 read-write 0x00000000 0x0000801F P0F Bit15 of DDR0 15 15 read-write P04 Bit4 of DDR0 4 4 read-write P03 Bit3 of DDR0 3 3 read-write P02 Bit2 of DDR0 2 2 read-write P01 Bit1 of DDR0 1 1 read-write P00 Bit0 of DDR0 0 0 read-write DDR1 Port input/output Direction Setting Register 1 0x204 DDR2 Port input/output Direction Setting Register 2 0x208 DDR3 Port input/output Direction Setting Register 3 0x20C DDR4 Port input/output Direction Setting Register 4 0x210 DDR5 Port input/output Direction Setting Register 5 0x214 DDR6 Port input/output Direction Setting Register 6 0x218 DDR8 Port input/output Direction Setting Register 8 0x220 DDRE Port input/output Direction Setting Register E 0x238 PDIR0 Port Input Data Register 0 0x300 32 read-only 0x00000000 0x0000801F P0F Bit15 of PDIR0 15 15 read-only P04 Bit4 of PDIR0 4 4 read-only P03 Bit3 of PDIR0 3 3 read-only P02 Bit2 of PDIR0 2 2 read-only P01 Bit1 of PDIR0 1 1 read-only P00 Bit0 of PDIR0 0 0 read-only PDIR1 Port Input Data Register 1 0x304 32 read-only 0x00000000 0x0000003F P15 Bit5 of PDIR1 5 5 read-only P14 Bit4 of PDIR1 4 4 read-only P13 Bit3 of PDIR1 3 3 read-only P12 Bit2 of PDIR1 2 2 read-only P11 Bit1 of PDIR1 1 1 read-only P10 Bit0 of PDIR1 0 0 read-only PDIR2 Port Input Data Register 2 0x308 32 read-only 0x00000000 0x0000000E P23 Bit3 of PDIR2 3 3 read-only P22 Bit2 of PDIR2 2 2 read-only P21 Bit1 of PDIR2 1 1 read-only PDIR3 Port Input Data Register 3 0x30C 32 read-only 0x00000000 0x0000FE00 P3F Bit15 of PDIR3 15 15 read-only P3E Bit14 of PDIR3 14 14 read-only P3D Bit13 of PDIR3 13 13 read-only P3C Bit12 of PDIR3 12 12 read-only P3B Bit11 of PDIR3 11 11 read-only P3A Bit10 of PDIR3 10 10 read-only P39 Bit9 of PDIR3 9 9 read-only PDIR4 Port Input Data Register 4 0x310 32 read-only 0x00000000 0x000006C0 P4A Bit10 of PDIR4 10 10 read-only P49 Bit9 of PDIR4 9 9 read-only P47 Bit7 of PDIR4 7 7 read-only P46 Bit6 of PDIR4 6 6 read-only PDIR5 Port Input Data Register 5 0x314 32 read-only 0x00000000 0x00000007 P52 Bit2 of PDIR5 2 2 read-only P51 Bit1 of PDIR5 1 1 read-only P50 Bit0 of PDIR5 0 0 read-only PDIR6 Port Input Data Register 6 0x318 32 read-only 0x00000000 0x00000003 P61 Bit1 of PDIR6 1 1 read-only P60 Bit0 of PDIR6 0 0 read-only PDIR8 Port Input Data Register 8 0x320 32 read-only 0x00000000 0x00000007 P82 Bit2 of PDIR8 2 2 read-only P81 Bit1 of PDIR8 1 1 read-only P80 Bit0 of PDIR8 0 0 read-only PDIRE Port Input Data Register E 0x338 32 read-only 0x00000000 0x0000000D PE3 Bit3 of PDIRE 3 3 read-only PE2 Bit2 of PDIRE 2 2 read-only PE0 Bit0 of PDIRE 0 0 read-only PDOR0 Port Output Data Register 0 0x400 PDOR1 Port Output Data Register 1 0x404 PDOR2 Port Output Data Register 2 0x408 PDOR3 Port Output Data Register 3 0x40C PDOR4 Port Output Data Register 4 0x410 PDOR5 Port Output Data Register 5 0x414 PDOR6 Port Output Data Register 6 0x418 PDOR8 Port Output Data Register 8 0x420 PDORE Port Output Data Register E 0x438 ADE Analog Input Setting Register 0x500 32 read-write 0xFFFFFFFF 0xFFFFFFFF AN31 Analog Input Ch.31 Setting Register 31 31 read-write AN30 Analog Input Ch.30 Setting Register 30 30 read-write AN29 Analog Input Ch.29 Setting Register 29 29 read-write AN28 Analog Input Ch.28 Setting Register 28 28 read-write AN27 Analog Input Ch.27 Setting Register 27 27 read-write AN26 Analog Input Ch.26 Setting Register 26 26 read-write AN25 Analog Input Ch.25 Setting Register 25 25 read-write AN24 Analog Input Ch.24 Setting Register 24 24 read-write AN23 Analog Input Ch.23 Setting Register 23 23 read-write AN22 Analog Input Ch.22 Setting Register 22 22 read-write AN21 Analog Input Ch.21 Setting Register 21 21 read-write AN20 Analog Input Ch.20 Setting Register 20 20 read-write AN19 Analog Input Ch.19 Setting Register 19 19 read-write AN18 Analog Input Ch.18 Setting Register 18 18 read-write AN17 Analog Input Ch.17 Setting Register 17 17 read-write AN16 Analog Input Ch.16 Setting Register 16 16 read-write AN15 Analog Input Ch.15 Setting Register 15 15 read-write AN14 Analog Input Ch.14 Setting Register 14 14 read-write AN13 Analog Input Ch.13 Setting Register 13 13 read-write AN12 Analog Input Ch.12 Setting Register 12 12 read-write AN11 Analog Input Ch.11 Setting Register 11 11 read-write AN10 Analog Input Ch.10 Setting Register 10 10 read-write AN09 Analog Input Ch.9 Setting Register 9 9 read-write AN08 Analog Input Ch.8 Setting Register 8 8 read-write AN07 Analog Input Ch.7 Setting Register 7 7 read-write AN06 Analog Input Ch.6 Setting Register 6 6 read-write AN05 Analog Input Ch.5 Setting Register 5 5 read-write AN04 Analog Input Ch.4 Setting Register 4 4 read-write AN03 Analog Input Ch.3 Setting Register 3 3 read-write AN02 Analog Input Ch.2 Setting Register 2 2 read-write AN01 Analog Input Ch.1 Setting Register 1 1 read-write AN00 Analog Input Ch.0 Setting Register 0 0 read-write SPSR Special Port Setting Register 0x580 32 read-write 0x00000005 0x0000000F MAINXC Main Clock (Oscillation) Pin Setting Register 2 3 read-write SUBXC Sub Clock (Oscillation) Pin Setting Register 0 1 read-write EPFR00 Extended Pin Function Setting Register 00 0x600 32 read-write 0x00010000 0x000100F7 SWDEN Serial Wire Debug Function Select bit 16 16 read-write SUBOUTE Sub clock divide output function select bit 6 7 read-write RTCCOE RTC clock output select bit 4 5 read-write CROUTE Internal high-speed CR Oscillation Output Function Select bit 1 2 read-write NMIS NMIX Function Select bit 0 0 read-write EPFR01 Extended Pin Function Setting Register 01 0x604 32 read-write 0x00000000 0xFFFF1FFF IC03S IC03 Input Select bits 29 31 read-write IC02S IC02 Input Select bits 26 28 read-write IC01S IC01 Input Select bits 23 25 read-write IC00S IC00 Input Select bits 20 22 read-write FRCK0S FRCK0 Input Select bits 18 19 read-write DTTI0S DTTIX0 Input Select bits 16 17 read-write DTTI0C DTTIX0 Function Select bit 12 12 read-write RTO05E RTO05 Output Select bits 10 11 read-write RTO04E RTO04 Output Select bits 8 9 read-write RTO03E RTO03 Output Select bits 6 7 read-write RTO02E RTO02 Output Select bits 4 5 read-write RTO01E RTO01 Output Select bits 2 3 read-write RTO00E RTO00 Output Select bits 0 1 read-write EPFR02 Extended Pin Function Setting Register 02 0x608 32 read-write 0x00000000 0xFFFF3FFF IC13S IC13 Input Select bits 29 31 read-write IC12S IC12 Input Select bits 26 28 read-write IC11S IC11 Input Select bits 23 25 read-write IC10S IC10 Input Select bits 20 22 read-write FRCK1S FRCK1 Input Select bits 18 19 read-write DTTI1S DTTIX1 Input Select bits 16 17 read-write IGTRG0 IGTRG0 Input Select bit 13 13 read-write DTTI1C DTTIX1 Function Select bit 12 12 read-write RTO15E RTO15 Output Select bits 10 11 read-write RTO14E RTO14 Output Select bits 8 9 read-write RTO13E RTO13 Output Select bits 6 7 read-write RTO12E RTO12 Output Select bits 4 5 read-write RTO11E RTO11 Output Select bits 2 3 read-write RTO10E RTO10 Output Select bits 0 1 read-write EPFR03 Extended Pin Function Setting Register 03 0x60C 32 read-write 0x00000000 0xFFFF1FFF IC23S IC23 Input Select bits 29 31 read-write IC22S IC22 Input Select bits 26 28 read-write IC21S IC21 Input Select bits 23 25 read-write IC20S IC20 Input Select bits 20 22 read-write FRCK2S FRCK2 Input Select bits 18 19 read-write DTTI2S DTTIX2 Input Select bits 16 17 read-write DTTI2C DTTIX2 Function Select bit 12 12 read-write RTO25E RTO25 Output Select bits 10 11 read-write RTO24E RTO24 Output Select bits 8 9 read-write RTO23E RTO23 Output Select bits 6 7 read-write RTO22E RTO22 Output Select bits 4 5 read-write RTO21E RTO21 Output Select bits 2 3 read-write RTO20E RTO20 Output Select bits 0 1 read-write EPFR04 Extended Pin Function Setting Register 04 0x610 32 read-write 0x00000000 0x3F3C3F7C TIOB3S TIOB3 Input Select bits 28 29 read-write TIOA3E TIOA3 Output Select bits 26 27 read-write TIOA3S TIOA3 Input Select bits 24 25 read-write TIOB2S TIOB2 Input Select bits 20 21 read-write TIOA2E TIOA2 Output Select bits 18 19 read-write TIOB1S TIOB1 Input Select bits 12 13 read-write TIOA1E TIOA1 Output Select bits 10 11 read-write TIOA1S TIOA1 Input Select bits 8 9 read-write TIOB0S TIOB0 Input Select bits 4 6 read-write TIOA0E TIOA0 Output Select bits 2 3 read-write EPFR05 Extended Pin Function Setting Register 05 0x614 32 read-write 0x00000000 0x3F3C3F3C TIOB7S TIOB7 Input Select bits 28 29 read-write TIOA7E TIOA7 Output Select bits 26 27 read-write TIOA7S TIOA7 Input Select bits 24 25 read-write TIOB6S TIOB6 Input Select bits 20 21 read-write TIOA6E TIOA6 Output Select bits 18 19 read-write TIOB5S TIOB5 Input Select bits 12 13 read-write TIOA5E TIOA5 Output Select bits 10 11 read-write TIOA5S TIOA5 Input Select bits 8 9 read-write TIOB4S TIOB4 Input Select bits 4 5 read-write TIOA4E TIOA4 Output Select bits 2 3 read-write EPFR06 Extended Pin Function Setting Register 06 0x618 32 read-write 0x00000000 0xFFFFFFFF EINT15S External Interrupt 15 Input Select bits 30 31 read-write EINT14S External Interrupt 14 Input Select bits 28 29 read-write EINT13S External Interrupt 13 Input Select bits 26 27 read-write EINT12S External Interrupt 12 Input Select bits 24 25 read-write EINT11S External Interrupt 11 Input Select bits 22 23 read-write EINT10S External Interrupt 10 Input Select bits 20 21 read-write EINT09S External Interrupt 09 Input Select bits 18 19 read-write EINT08S External Interrupt 08 Input Select bits 16 17 read-write EINT07S External Interrupt 07 Input Select bits 14 15 read-write EINT06S External Interrupt 06 Input Select bits 12 13 read-write EINT05S External Interrupt 05 Input Select bits 10 11 read-write EINT04S External Interrupt 04 Input Select bits 8 9 read-write EINT03S External Interrupt 03 Input Select bits 6 7 read-write EINT02S External Interrupt 02 Input Select bits 4 5 read-write EINT01S External Interrupt 01 Input Select bits 2 3 read-write EINT00S External Interrupt 00 Input Select bits 0 1 read-write EPFR07 Extended Pin Function Setting Register 07 0x61C 32 read-write 0x00000000 0x0FFFFFF0 SCK3B SCK3 Input/Output Select bits 26 27 read-write SOT3B SOT3 Input/Output Select bits 24 25 read-write SIN3S SIN3 Input Select bits 22 23 read-write SCK2B SCK2 Input/Output Select bits 20 21 read-write SOT2B SOT2 Input/Output Select bits 18 19 read-write SIN2S SIN2 Input Select bits 16 17 read-write SCK1B SCK1 Input/Output Select bits 14 15 read-write SOT1B SOT1 Input/Output Select bits 12 13 read-write SIN1S SIN1 Input Select bits 10 11 read-write SCK0B SCK0 Input/Output Select bits 8 9 read-write SOT0B SOT0 Input/Output Select bits 6 7 read-write SIN0S SIN0 Input Select bits 4 5 read-write EPFR08 Extended Pin Function Setting Register 08 0x620 32 read-write 0x00000000 0x0FFFFFFF SCK7B SCK7 Input/Output Select bits 26 27 read-write SOT7B SOT7 Input/Output Select bits 24 25 read-write SIN7S SIN7 Input Select bits 22 23 read-write SCK6B SCK6 Input/Output Select bits 20 21 read-write SOT6B SOT6 Input/Output Select bits 18 19 read-write SIN6S SIN6 Input Select bits 16 17 read-write SCK5B SCK5 Input/Output Select bits 14 15 read-write SOT5B SOT5 Input/Output Select bits 12 13 read-write SIN5S SIN5 Input Select bits 10 11 read-write SCK4B SCK4 Input/Output Select bits 8 9 read-write SOT4B SOT4 Input/Output Select bits 6 7 read-write SIN4S SIN4 Input Select bits 4 5 read-write CTS4S CTS4 Input Select bits 2 3 read-write RTS4E RTS4 Output Select bits 0 1 read-write EPFR09 Extended Pin Function Setting Register 09 0x624 32 read-write 0x00000000 0xFFFFFFFF CTX1E CTX1E Output Select bits 30 31 read-write CRX1S CRX1S Input Select bits 28 29 read-write CTX0E CTX0E Output Select bits 26 27 read-write CRX0S CRX0S Input Select bits 24 25 read-write ADTRG2S ADTRG2 Input Select bits 20 23 read-write ADTRG1S ADTRG1 Input Select bits 16 19 read-write ADTRG0S ADTRG0 Input Select bits 12 15 read-write QZIN1S QZIN1S Input Select bits 10 11 read-write QBIN1S QBIN1S Input Select bits 8 9 read-write QAIN1S QAIN1S Input Select bits 6 7 read-write QZIN0S QZIN0S Input Select bits 4 5 read-write QBIN0S QBIN0S Input Select bits 2 3 read-write QAIN0S QAIN0S Input Select bits 0 1 read-write EPFR12 Extended Pin Function Setting Register 12 0x630 32 read-write 0x00000000 0x3F3C3F3C TIOB11S TIOB11 Input Select bits 28 29 read-write TIOA11E TIOA11 Output Select bits 26 27 read-write TIOA11S TIOA11 Input Select bits 24 25 read-write TIOB10S TIOB10 Input Select bits 20 21 read-write TIOA10E TIOA10 Output Select bits 18 19 read-write TIOB9S TIOB9 Input Select bits 12 13 read-write TIOA9E TIOA9 Output Select bits 10 11 read-write TIOA9S TIOA9 Input Select bits 8 9 read-write TIOB8S TIOB8 Input Select bits 4 5 read-write TIOA8E TIOA8 Output Select bits 2 3 read-write EPFR13 Extended Pin Function Setting Register 13 0x634 32 read-write 0x00000000 0x3F3C3F3C TIOB15S TIOB15 Input Select bits 28 29 read-write TIOA15E TIOA15 Output Select bits 26 27 read-write TIOA15S TIOA15 Input Select bits 24 25 read-write TIOB14S TIOB14 Input Select bits 20 21 read-write TIOA14E TIOA14 Output Select bits 18 19 read-write TIOB13S TIOB13 Input Select bits 12 13 read-write TIOA13E TIOA13 Output Select bits 10 11 read-write TIOA13S TIOA13 Input Select bits 8 9 read-write TIOB12S TIOB12 Input Select bits 4 5 read-write TIOA12E TIOA12 Output Select bits 2 3 read-write EPFR14 Extended Pin Function Setting Register 14 0x638 32 read-write 0x00000000 0x0000003F QZIN2S QPRC-ch.2 ZIN Input Pin bits 4 5 read-write QBIN2S QPRC-ch.2 BIN Input Pin bits 2 3 read-write QAIN2S QPRC-ch.2 AIN Input Pin bits 0 1 read-write EPFR15 Extended Pin Function Setting Register 15 0x63C 32 read-write 0x00000000 0xFFFFFFFF EINT31S External Interrupt 31 Input Select bits 30 31 read-write EINT30S External Interrupt 30 Input Select bits 28 29 read-write EINT29S External Interrupt 29 Input Select bits 26 27 read-write EINT28S External Interrupt 28 Input Select bits 24 25 read-write EINT27S External Interrupt 27 Input Select bits 22 23 read-write EINT26S External Interrupt 26 Input Select bits 20 21 read-write EINT25S External Interrupt 25 Input Select bits 18 19 read-write EINT24S External Interrupt 24 Input Select bits 16 17 read-write EINT23S External Interrupt 23 Input Select bits 14 15 read-write EINT22S External Interrupt 22 Input Select bits 12 13 read-write EINT21S External Interrupt 21 Input Select bits 10 11 read-write EINT20S External Interrupt 20 Input Select bits 8 9 read-write EINT19S External Interrupt 19 Input Select bits 6 7 read-write EINT18S External Interrupt 18 Input Select bits 4 5 read-write EINT17S External Interrupt 17 Input Select bits 2 3 read-write EINT16S External Interrupt 16 Input Select bits 0 1 read-write EPFR16 Extended Pin Function Setting Register 16 0x640 32 read-write 0x00000000 0x0FFFFFF0 SCK11B SCK11 Input/Output Select bits 26 27 read-write SOT11B SOT11 Input/Output Select bits 24 25 read-write SIN11S SIN11 Input Select bits 22 23 read-write SCK10B SCK10 Input/Output Select bits 20 21 read-write SOT10B SOT10 Input/Output Select bits 18 19 read-write SIN10S SIN10 Input Select bits 16 17 read-write SCK9B SCK9 Input/Output Select bits 14 15 read-write SOT9B SOT9 Input/Output Select bits 12 13 read-write SIN9S SIN9 Input Select bits 10 11 read-write SCK8B SCK8 Input/Output Select bits 8 9 read-write SOT8B SOT8 Input/Output Select bits 6 7 read-write SIN8S SIN8 Input Select bits 4 5 read-write EPFR17 Extended Pin Function Setting Register 17 0x644 32 read-write 0x00000000 0x0FFFFFF0 SCK15B SCK15 Input/Output Select bits 26 27 read-write SOT15B SOT15 Input/Output Select bits 24 25 read-write SIN15S SIN15 Input Select bits 22 23 read-write SCK14B SCK14 Input/Output Select bits 20 21 read-write SOT14B SOT14 Input/Output Select bits 18 19 read-write SIN14S SIN14 Input Select bits 16 17 read-write SCK13B SCK13 Input/Output Select bits 14 15 read-write SOT13B SOT13 Input/Output Select bits 12 13 read-write SIN13S SIN13 Input Select bits 10 11 read-write SCK12B SCK12 Input/Output Select bits 8 9 read-write SOT12B SOT12 Input/Output Select bits 6 7 read-write SIN12S SIN12 Input Select bits 4 5 read-write EPFR18 Extended Pin Function Setting Register 18 0x648 32 read-write 0x00000000 0x0000000F CECR1B CEC1 input/output selection bits 2 3 read-write CECR0B CEC0 input/output selection bits 0 1 read-write EPFR21 Extended Pin Function Setting Register 21 0x654 32 read-write 0x00000000 0x00000007 QZIN0S QPRC-ch.0 ZIN Input Pin bits 2 2 read-write QBIN0S QPRC-ch.0 BIN Input Pin bits 1 1 read-write QAIN0S QPRC-ch.0 AIN Input Pin bits 0 0 read-write EPFR22 Extended Pin Function Setting Register 22 0x658 32 read-write 0x00000000 0x0000F0F0 SCS31E SCS31 Output Select bits 14 15 read-write SCS30B SCS30 Input/Output Select bits 12 13 read-write SCS11E SCS11 Output Select bits 6 7 read-write SCS10B SCS10 Input/Output Select bits 4 5 read-write PZR0 Port Pseudo Open Drain Setting Register 0 0x700 PZR1 Port Pseudo Open Drain Setting Register 1 0x704 PZR2 Port Pseudo Open Drain Setting Register 2 0x708 PZR3 Port Pseudo Open Drain Setting Register 3 0x70C PZR4 Port Pseudo Open Drain Setting Register 4 0x710 PZR5 Port Pseudo Open Drain Setting Register 5 0x714 PZR6 Port Pseudo Open Drain Setting Register 6 0x718 PZR8 Port Pseudo Open Drain Setting Register 8 0x720 PZRE Port Pseudo Open Drain Setting Register E 0x738 FPOER0 Fast GPIO Output Enable Register 0 0x900 32 write-only 0x00000000 0x0000801F P0F Bit15 of FPOER0 15 15 write-only P04 Bit4 of FPOER0 4 4 write-only P03 Bit3 of FPOER0 3 3 write-only P02 Bit2 of FPOER0 2 2 write-only P01 Bit1 of FPOER0 1 1 write-only P00 Bit0 of FPOER0 0 0 write-only FPOER1 Fast GPIO Output Enable Register 1 0x904 32 write-only 0x00000000 0x0000003F P15 Bit5 of FPOER1 5 5 write-only P14 Bit4 of FPOER1 4 4 write-only P13 Bit3 of FPOER1 3 3 write-only P12 Bit2 of FPOER1 2 2 write-only P11 Bit1 of FPOER1 1 1 write-only P10 Bit0 of FPOER1 0 0 write-only FPOER2 Fast GPIO Output Enable Register 2 0x908 32 write-only 0x00000000 0x0000000E P23 Bit3 of FPOER2 3 3 write-only P22 Bit2 of FPOER2 2 2 write-only P21 Bit1 of FPOER2 1 1 write-only FPOER3 Fast GPIO Output Enable Register 3 0x90C 32 write-only 0x00000000 0x0000FE00 P3F Bit15 of FPOER3 15 15 write-only P3E Bit14 of FPOER3 14 14 write-only P3D Bit13 of FPOER3 13 13 write-only P3C Bit12 of FPOER3 12 12 write-only P3B Bit11 of FPOER3 11 11 write-only P3A Bit10 of FPOER3 10 10 write-only P39 Bit9 of FPOER3 9 9 write-only FPOER4 Fast GPIO Output Enable Register 4 0x910 32 write-only 0x00000000 0x000006C0 P4A Bit10 of FPOER4 10 10 write-only P49 Bit9 of FPOER4 9 9 write-only P47 Bit7 of FPOER4 7 7 write-only P46 Bit6 of FPOER4 6 6 write-only FPOER5 Fast GPIO Output Enable Register 5 0x914 32 write-only 0x00000000 0x00000007 P52 Bit2 of FPOER5 2 2 write-only P51 Bit1 of FPOER5 1 1 write-only P50 Bit0 of FPOER5 0 0 write-only FPOER6 Fast GPIO Output Enable Register 6 0x918 32 write-only 0x00000000 0x00000003 P61 Bit1 of FPOER6 1 1 write-only P60 Bit0 of FPOER6 0 0 write-only FPOER8 Fast GPIO Output Enable Register 8 0x920 32 write-only 0x00000000 0x00000007 P82 Bit2 of FPOER8 2 2 write-only P81 Bit1 of FPOER8 1 1 write-only P80 Bit0 of FPOER8 0 0 write-only FPOERE Fast GPIO Output Enable Register E 0x938 32 write-only 0x00000000 0x0000000D PE3 Bit3 of FPOERE 3 3 write-only PE2 Bit2 of FPOERE 2 2 write-only PE0 Bit0 of FPOERE 0 0 write-only LVD Low-voltage Detection LVD 0x40035000 0x0 0x2 registers 0x4 0x1 registers 0x8 0x1 registers 0xC 0x4 registers 0x10 0x1 registers LVD 2 LVD_CTL Low-voltage Detection Voltage Control Register 0x0 16 read-write 0x800C 0xFCFC LVDRE Low-voltage detection reset operation enable bit 15 15 read-write SVHR Low-voltage detection reset voltage setting bits 10 14 read-write LVDIE Low-voltage detection interrupt enable bit 7 7 read-write SVHI Low-voltage detection interrupt voltage setting bits 2 6 read-write LVD_STR Low-voltage Detection Interrupt Factor Register 0x4 8 read-only 0x00 0x80 LVDIR Low-voltage detection interrupt factor bit 7 7 read-only LVD_CLR Low-voltage Detection Interrupt Factor Clear Register 0x8 8 read-write 0x80 0x80 LVDCL Low-voltage detection interrupt factor clear bit 7 7 read-write LVD_RLR Low-voltage Detection Voltage Protection Register 0xC 32 read-write 0x00000001 0xFFFFFFFF LVDLCK Low-voltage Detection Voltage Control Register protection bits 0 31 read-write LVD_STR2 Low-voltage Detection Circuit Status Register 0x10 8 read-only 0x40 0xC0 LVDIRDY Low-voltage detection interrupt status flag 7 7 read-only LVDRRDY Low-voltage detection reset status flag 6 6 read-only DS Low Power Consumption Mode Registers DS 0x40035100 0x0 0x1 registers 0x4 0x1 registers 0x700 0x1 registers 0x704 0x1 registers 0x708 0x2 registers 0x70C 0x2 registers 0x710 0x1 registers 0x714 0x1 registers 0x800 0x4 registers 0x804 0x4 registers 0x808 0x4 registers 0x80C 0x4 registers REG_CTL Sub Oscillation Circuit Power Supply Control Register 0x0 8 read-write 0x04 0x06 ISUBSEL Sub oscillation circuit current setting bits 1 2 read-write RCK_CTL Sub Clock Control Register 0x4 8 read-write 0x01 0x03 CECCKE CEC clock control bit 1 1 read-write RTCCKE RTC clock control bit 0 0 read-write PMD_CTL RTC Mode Control Register 0x700 8 read-write 0x00 0x01 RTCE RTC mode control bit 0 0 read-write WRFSR Deep Standby Return Factor Register 1 0x704 8 read-only 0x00 0x03 WLVDH Low-voltage detection reset return bit 1 1 read-only WINITX INITX pin input reset return bit 0 0 read-only WIFSR Deep Standby Return Factor Register 2 0x708 16 read-only 0x0000 0x03FF WCEC1I CEC ch.1 interrupt return bit 9 9 read-only WCEC0I CEC ch.0 interrupt return bit 8 8 read-only WUI5 WKUP5 pin input return bit 7 7 read-only WUI4 WKUP4 pin input return bit 6 6 read-only WUI3 WKUP3 pin input return bit 5 5 read-only WUI2 WKUP2 pin input return bit 4 4 read-only WUI1 WKUP1 pin input return bit 3 3 read-only WUI0 WKUP0 pin input return bit 2 2 read-only WLVDI LVD interrupt return bit 1 1 read-only WRTCI RTC interrupt return bit 0 0 read-only WIER Deep Standby Return Enable Register 0x70C 16 read-write 0x0000 0x03FB WCEC1E HDMI-CEC/ Remote Control Reception ch.1 interrupt return enable bit 9 9 read-write WCEC0E HDMI-CEC/ Remote Control Reception ch.0 interrupt return enable bit 8 8 read-write WUI5E WKUP5 pin input return enable bit 7 7 read-write WUI4E WKUP4 pin input return enable bit 6 6 read-write WUI3E WKUP3 pin input return enable bit 5 5 read-write WUI2E WKUP2 pin input return enable bit 4 4 read-write WUI1E WKUP1 pin input return enable bit 3 3 read-write WLVDE LVD interrupt return enable bit 1 1 read-write WRTCE RTC interrupt return enable bit 0 0 read-write WILVR WKUP Pin Input Level Register 0x710 8 read-write 0x00 0x1F WUI5LV WKUP5 pin input level select bit 4 4 read-write WUI4LV WKUP4 pin input level select bit 3 3 read-write WUI3LV WKUP3 pin input level select bit 2 2 read-write WUI2LV WKUP2 pin input level select bit 1 1 read-write WUI1LV WKUP1 pin input level select bit 0 0 read-write DSRAMR Deep Standby RAM Retention Register 0x714 8 read-write 0x00 0x03 SRAMR On-chip SRAM retention control bits 0 1 read-write BUR01 Backup Register 01 0x800 8 read-write 0x00 0xFF BUR02 Backup Register 02 0x801 8 read-write 0x00 0xFF BUR03 Backup Register 03 0x802 8 read-write 0x00 0xFF BUR04 Backup Register 04 0x803 8 read-write 0x00 0xFF BUR05 Backup Register 05 0x804 8 read-write 0x00 0xFF BUR06 Backup Register 06 0x805 8 read-write 0x00 0xFF BUR07 Backup Register 07 0x806 8 read-write 0x00 0xFF BUR08 Backup Register 08 0x807 8 read-write 0x00 0xFF BUR09 Backup Register 09 0x808 8 read-write 0x00 0xFF BUR10 Backup Register 10 0x809 8 read-write 0x00 0xFF BUR11 Backup Register 11 0x80A 8 read-write 0x00 0xFF BUR12 Backup Register 12 0x80B 8 read-write 0x00 0xFF BUR13 Backup Register 13 0x80C 8 read-write 0x00 0xFF BUR14 Backup Register 14 0x80D 8 read-write 0x00 0xFF BUR15 Backup Register 15 0x80E 8 read-write 0x00 0xFF BUR16 Backup Register 16 0x80F 8 read-write 0x00 0xFF MFS0 Multi-function Serial Interface 0 MFS0 0x40038000 0x0 0x2 registers 0x4 0x2 registers 0x8 0x2 registers 0xC 0x2 registers 0x10 0x2 registers 0x14 0x2 registers 0x18 0x2 registers 0x1C 0x2 registers 0x20 0x2 registers 0x24 0x2 registers 0x28 0x2 registers 0x2C 0x2 registers 0x30 0x2 registers 0x34 0x2 registers 0x38 0x1 registers 0x3C 0x2 registers 0x40 0x2 registers MFS0RX 7 MFS0TX 8 UART_SCR Serial Control Register UART 0x1 8 read-write 0x00 0x9F UPCL Programmable Clear bit 7 7 read-write RIE Received interrupt enable bit 4 4 read-write TIE Transmit interrupt enable bit 3 3 read-write TBIE Transmit bus idle interrupt enable bit 2 2 read-write RXE Received operation enable bit 1 1 read-write TXE Transmission operation enable bit 0 0 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write 0x00 0xED MD Operation mode set bit 5 7 read-write SBL Stop bit length select bit 3 3 read-write BDS Transfer direction select bit 2 2 read-write SOE Serial data output enable bit 0 0 read-write UART_SSR Serial Status Register UART 0x5 8 read-write 0x03 0xBF REC Received error flag clear bit 7 7 read-write PE Parity error flag bit (only functions in operation mode 0) 5 5 read-only FRE Framing error flag bit 4 4 read-only ORE Overrun error flag bit 3 3 read-only RDRF Received data full flag bit 2 2 read-only TDRE Transmit data empty flag bit 1 1 read-only TBI Transmit bus idle flag 0 0 read-only UART_ESCR Extended Communication Control Register UART 0x4 8 read-write 0x00 0xFF FLWEN Flow control enable bit 7 7 read-write ESBL Extension stop bit length select bit 6 6 read-write INV Inverted serial data format bit 5 5 read-write PEN Parity enable bit (only functions in operation mode 0) 4 4 read-write P Parity select bit (only functions in operation mode 0) 3 3 read-write L Data length select bit 0 2 read-write UART_RDR Received Data Register UART 0x8 16 read-only 0x0000 0x01FF D Data 0 8 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only 0x01FF 0x01FF D Data 0 8 write-only UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write 0x0000 0xFFFF EXT External clock select bit 15 15 read-write BGR1 Baud Rate Generator Register 1 8 14 read-write BGR0 Baud Rate Generator Register 0 0 7 read-write UART_FCR1 FIFO Control Register 1 UART 0x15 8 read-write 0x04 0x1F FLSTE Re-transmission data lost detect enable bit 4 4 read-write FRIIE Received FIFO idle detection enable bit 3 3 read-write FDRQ Transmit FIFO data request bit 2 2 read-write FTIE Transmit FIFO interrupt enable bit 1 1 read-write FSEL FIFO select bit 0 0 read-write UART_FCR0 FIFO Control Register 0 UART 0x14 8 read-write 0x00 0x7F FLST FIFO re-transmit data lost flag bit 6 6 read-only FLD FIFO pointer reload bit 5 5 read-write FSET FIFO pointer save bit 4 4 read-write FCL2 FIFO2 reset bit 3 3 read-write FCL1 FIFO1 reset bit 2 2 read-write FE2 FIFO2 operation enable bit 1 1 read-write FE1 FIFO1 operation enable bit 0 0 read-write UART_FBYTE1 FIFO Byte Register 1 UART 0x18 8 read-write 0x00 0xFF UART_FBYTE2 FIFO Byte Register 2 UART 0x19 8 read-write 0x00 0xFF CSIO_SCR Serial Control Register CSIO 0x1 8 read-write 0x00 0xFF UPCL Programmable clear bit 7 7 read-write MS Master/Slave function select bit 6 6 read-write SPI SPI corresponding bit 5 5 read-write RIE Received interrupt enable bit 4 4 read-write TIE Transmit interrupt enable bit 3 3 read-write TBIE Transmit bus idle interrupt enable bit 2 2 read-write RXE Data received enable bit 1 1 read-write TXE Data transmission enable bit 0 0 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write 0x00 0xEF MD Operation mode set bits 5 7 read-write SCINV Serial clock invert bit 3 3 read-write BDS Transfer direction select bit 2 2 read-write SCKE Master mode serial clock output enable bit 1 1 read-write SOE Serial data output enable bit 0 0 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write 0x03 0x9F REC Received error flag clear bit 7 7 read-write ORE Overrun error flag bit 3 3 read-only RDRF Received data full flag bit 2 2 read-only TDRE Transmit data empty flag bit 1 1 read-only TBI Transmit bus idle flag bit 0 0 read-only CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write 0x00 0xFF SOP Serial output pin set bit 7 7 read-write L3 Bit3 of Data length select bits 6 6 read-write CSFE Serial Chip Select Format enable bit 5 5 read-write WT Data transmit/received wait select bits 3 4 read-write L Bit0-2 of Data length select bits 0 2 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only 0x0000 0xFFFF D Data 0 15 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only 0xFFFF 0xFFFF D Data 0 15 write-only CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write 0x0000 0x7FFF BGR1 Baud Rate Generator Register 1 8 14 read-write BGR0 Baud Rate Generator Register 0 0 7 read-write CSIO_FCR1 FIFO Control Register 1 CSIO 0x15 8 read-write 0x04 0x1F FLSTE Re-transmission data lost detect enable bit 4 4 read-write FRIIE Received FIFO idle detection enable bit 3 3 read-write FDRQ Transmit FIFO data request bit 2 2 read-write FTIE Transmit FIFO interrupt enable bit 1 1 read-write FSEL FIFO select bit 0 0 read-write CSIO_FCR0 FIFO Control Register 0 CSIO 0x14 8 read-write 0x00 0x7F FLST FIFO re-transmit data lost flag bit 6 6 read-only FLD FIFO pointer reload bit 5 5 read-write FSET FIFO pointer save bit 4 4 read-write FCL2 FIFO2 reset bit 3 3 read-write FCL1 FIFO1 reset bit 2 2 read-write FE2 FIFO2 operation enable bit 1 1 read-write FE1 FIFO1 operation enable bit 0 0 read-write CSIO_FBYTE1 FIFO Byte Register 1 CSIO 0x18 8 read-write 0x00 0xFF CSIO_FBYTE2 FIFO Byte Register 2 CSIO 0x19 8 read-write 0x00 0xFF CSIO_SCSTR0 Serial Chip Select Timing Register 0 CSIO 0x1C 8 read-write 0x00 0xFF CSHD Serial Chip Select Hold Delay bits 0 7 read-write CSIO_SCSTR1 Serial Chip Select Timing Register 1 CSIO 0x1D 8 read-write 0x00 0xFF CSSU Serial Chip Select Setup Delay bits 0 7 read-write CSIO_SCSTR2 Serial Chip Select Timing Registers 2/3 CSIO 0x20 16 read-write 0x0000 0xFFFF CSDS Serial Chip Deselect bits 0 15 read-write CSIO_SACSR Serial Support Control Register CSIO 0x24 16 read-write 0x0000 0x39DF TBEEN Transfer Byte Error Enable bit 13 13 read-write CSEIE Chip Select Error Interupt Enable bit 12 12 read-write CSE Chip Select Error Flag 11 11 read-write TINT Timer Interrupt Flag 8 8 read-write TINTE Timer Interrupt Enable bit 7 7 read-write TSYNE Synchronous Transmission Enable bit 6 6 read-write TDIV Timer Operation Clock Division bit 1 4 read-write TMRE Serial Timer Enable bit 0 0 read-write CSIO_STMR Serial Timer Register CSIO 0x28 16 read-only 0x0000 0xFFFF TM Timer Data bits 0 15 read-only CSIO_STMCR Serial Timer Comparison Register CSIO 0x2C 16 read-write 0x0000 0xFFFF TC Compare bits 0 15 read-write CSIO_SCSCR Serial Chip Select Control Status Register CSIO 0x30 16 read-write 0x0020 0xFFFF SST Serial Chip Select Active Start bit 14 15 read-write SED Serial Chip Select Active End bit 12 13 read-write SCD Serial Chip Select Active Display bit 10 11 read-write SCAM Serial Chip Select Active Hold bit 9 9 read-write CDIV Serial Chip Select Timing Operation Clock Division bit 6 8 read-write CSLVL Serial Chip Select Level Setting bit 5 5 read-write CSEN3 Serial Chip Select Enable bit 4 4 read-write CSEN2 Serial Chip Select Enable bit 3 3 read-write CSEN1 Serial Chip Select Enable bit 2 2 read-write CSEN0 Serial Chip Select Enable bit 1 1 read-write CSOE Serial Chip Select Output Enable bit 0 0 read-write CSIO_SCSFR0 Serial Chip Select Format Register 0 CSIO 0x34 8 read-write 0x80 0xFF CS1CSLVL Serial Chip Select 1 Level Setting bit 7 7 read-write CS1SCINV Serial Clock Invert bit of Serial Chip Select 1 6 6 read-write CS1SPI SPI corresponding bit of Serial Chip Select 1 5 5 read-write CS1BDS Transfer direction select bit of Serial Chip Select 1 4 4 read-write CS1L Data length select bits of Serial Chip Select 1 0 3 read-write CSIO_SCSFR1 Serial Chip Select Format Register 1 CSIO 0x35 8 read-write 0x80 0xFF CS2CSLVL Serial Chip Select 2 Level Setting bit 7 7 read-write CS2SCINV Serial Clock Invert bit of Serial Chip Select 2 6 6 read-write CS2SPI SPI corresponding bit of Serial Chip Select 2 5 5 read-write CS2BDS Transfer direction select bit of Serial Chip Select 2 4 4 read-write CS2L Data length select bits of Serial Chip Select 2 0 3 read-write CSIO_SCSFR2 Serial Chip Select Format Register 0 CSIO 0x38 8 read-write 0x80 0xFF CS0CSLVL Serial Chip Select 0 Level Setting bit 7 7 read-write CS0SCINV Serial Clock Invert bit of Serial Chip Select 0 6 6 read-write CS0SPI SPI corresponding bit of Serial Chip Select 0 5 5 read-write CS0BDS Transfer direction select bit of Serial Chip Select 0 4 4 read-write CS0L Data length select bits of Serial Chip Select 0 0 3 read-write CSIO_TBYTE0 Transfer Byte Register 0 CSIO 0x3C 8 read-write 0x00 0xFF CSIO_TBYTE1 Transfer Byte Register 1 CSIO 0x3D 8 read-write 0x00 0xFF CSIO_TBYTE2 Transfer Byte Register 2 CSIO 0x40 8 read-write 0x00 0xFF CSIO_TBYTE3 Transfer Byte Register 3 CSIO 0x41 8 read-write 0x00 0xFF LIN_SCR Serial Control Register LIN 0x1 8 read-write 0x00 0xFF UPCL Programmable clear bit 7 7 read-write MS Master/Slave function select bit 6 6 read-write LBR LIN Break Field setting bit (valid in master mode only) 5 5 read-write RIE Received interrupt enable bit 4 4 read-write TIE Transmit interrupt enable bit 3 3 read-write TBIE Transmit bus idle interrupt enable bit 2 2 read-write RXE Data reception enable bit 1 1 read-write TXE Data transmission enable bit 0 0 read-write LIN_SMR Serial Mode Register LIN 0x0 8 read-write 0x00 0xE9 MD Operation mode setting bits 5 7 read-write SBL Stop bit length select bit 3 3 read-write SOE Serial data output enable bit 0 0 read-write LIN_SSR Serial Status Register LIN 0x5 8 read-write 0x03 0xBF REC Received Error flag clear bit 7 7 read-write LBD LIN Break field detection flag bit 5 5 read-write FRE Framing error flag bit 4 4 read-only ORE Overrun error flag bit 3 3 read-only RDRF Received data full flag bit 2 2 read-only TDRE Transmit data empty flag bit 1 1 read-only TBI Transmit bus idle flag bit 0 0 read-only LIN_ESCR Extended Communication Control Register LIN 0x4 8 read-write 0x00 0x5F ESBL Extended stop bit length select bit 6 6 read-write LBIE LIN Break field detect interrupt enable bit 4 4 read-write LBL LIN Break field length select bits (valid in master mode only) 2 3 read-write DEL LIN Break delimiter length select bits (valid in master mode only) 0 1 read-write LIN_RDR Received Data Register LIN 0x8 16 read-only 0x0000 0x00FF D Data 0 7 read-only LIN_TDR Transmit Data Register LIN 0x8 16 write-only 0x00FF 0x00FF D Data 0 7 write-only LIN_BGR Baud Rate Generator Registers LIN 0xC 16 read-write 0x0000 0xFFFF EXT External clock select bit 15 15 read-write BGR1 Baud Rate Generator Registers 1 8 14 read-write BGR0 Baud Rate Generator Registers 0 0 7 read-write LIN_FCR1 FIFO Control Register 1 LIN 0x15 8 read-write 0x04 0x1F FLSTE Re-transmission data lost detect enable bit 4 4 read-write FRIIE Received FIFO idle detection enable bit 3 3 read-write FDRQ Transmit FIFO data request bit 2 2 read-write FTIE Transmit FIFO interrupt enable bit 1 1 read-write FSEL FIFO select bit 0 0 read-write LIN_FCR0 FIFO Control Register 0 LIN 0x14 8 read-write 0x00 0x7F FLST FIFO re-transmit data lost flag bit 6 6 read-only FLD FIFO pointer reload bit 5 5 read-write FSET FIFO pointer save bit 4 4 read-write FCL2 FIFO2 reset bit 3 3 read-write FCL1 FIFO1 reset bit 2 2 read-write FE2 FIFO2 operation enable bit 1 1 read-write FE1 FIFO1 operation enable bit 0 0 read-write LIN_FBYTE1 FIFO Byte Register 1 LIN 0x18 8 read-write 0x00 0xFF LIN_FBYTE2 FIFO Byte Register 2 LIN 0x19 8 read-write 0x00 0xFF I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write 0x00 0xFF MSS Master/slave select bit 7 7 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 6 read-write ACKE Data byte acknowledge enable bit 5 5 read-write WSEL Wait selection bit 4 4 read-write CNDE Condition detection interrupt enable bit 3 3 read-write INTE Interrupt enable bit 2 2 read-write BER Bus error flag bit 1 1 read-only INT Interrupt flag bit 0 0 read-write I2C_SMR Serial Mode Register I2C 0x0 8 read-write 0x00 0xEC MD Operation mode set bits 5 7 read-write RIE Received interrupt enable bit 3 3 read-write TIE Transmit interrupt enable bit 2 2 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write 0x00 0xFF FBT First byte bit 7 7 read-only RACK Acknowledge flag bit 6 6 read-only RSA Reserved address detection bit 5 5 read-only TRX Data direction bit 4 4 read-only AL Arbitration lost bit 3 3 read-only RSC Iteration start condition check bit 2 2 read-write SPC Stop condition check bit 1 1 read-write BB Bus state bit 0 0 read-only I2C_SSR Serial Status Register I2C 0x5 8 read-write 0x03 0xFF REC Received error flag clear bit 7 7 read-write TSET Transmit empty flag set bit 6 6 read-write DMA DMA mode enable bit 5 5 read-write TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 4 read-write ORE Overrun error flag bit 3 3 read-only RDRF Received data full flag bit 2 2 read-only TDRE Transmit data empty flag bit 1 1 read-only TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 0 read-only I2C_RDR Received Data Register I2C 0x8 16 read-only 0x0000 0x00FF D Data 0 7 read-only I2C_TDR Transmit Data Register I2C 0x8 16 write-only 0x00FF 0x00FF D Data 0 7 write-only I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write 0x0000 0x7FFF BGR1 Baud Rate Generator Register 1 8 14 read-write BGR0 Baud Rate Generator Register 0 0 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write 0x7F 0xFF EN I2C interface operation enable bit 7 7 read-write SM Slave address mask bits 0 6 read-write I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write 0x00 0xFF SAEN Slave address enable bit 7 7 read-write SA 7-bit slave address 0 6 read-write I2C_FCR1 FIFO Control Register 1 I2C 0x15 8 read-write 0x04 0x1F FLSTE Re-transmission data lost detect enable bit 4 4 read-write FRIIE Received FIFO idle detection enable bit 3 3 read-write FDRQ Transmit FIFO data request bit 2 2 read-write FTIE Transmit FIFO interrupt enable bit 1 1 read-write FSEL FIFO select bit 0 0 read-write I2C_FCR0 FIFO Control Register 0 I2C 0x14 8 read-write 0x00 0x7F FLST FIFO re-transmit data lost flag bit 6 6 read-only FLD FIFO pointer reload bit 5 5 read-write FSET FIFO pointer save bit 4 4 read-write FCL2 FIFO2 reset bit 3 3 read-write FCL1 FIFO1 reset bit 2 2 read-write FE2 FIFO2 operation enable bit 1 1 read-write FE1 FIFO1 operation enable bit 0 0 read-write I2C_FBYTE1 FIFO Byte Register 1 I2C 0x18 8 read-write 0x0000 0xFFFF I2C_FBYTE2 FIFO Byte Register 2 I2C 0x19 8 read-write 0x0000 0xFFFF I2C_NFCR Noise Filter Control Register I2C 0x1C 8 read-write 0x00 0x1F NFT Noise Filter Time Select bits 0 4 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write 0x0C 0x3F SDAS SDA status bit 5 5 read-only SCLS SCL status bit 4 4 read-only SDAC SDA output control bit 3 3 read-write SCLC SCL output control bit 2 2 read-write SOCE Serial output enabled bit 1 1 read-write BEC Bus error control bit 0 0 read-write MFS1 0x40038100 MFS1RX 9 MFS1TX 10 MFS3 0x40038300 MFS3RX 13 MFS3TX 14 CRC CRC Registers CRC 0x40039000 0x0 0x1 registers 0x4 0x4 registers 0x8 0x4 registers 0xC 0x4 registers CRCCR CRC Control Register 0x0 8 read-write 0x00 0x7F FXOR Final XOR control bit 6 6 read-write CRCLSF CRC result bit-order setting bit 5 5 read-write CRCLTE CRC result byte-order setting bit 4 4 read-write LSBFST Bit-order setting bit 3 3 read-write LTLEND Byte-order setting bit 2 2 read-write CRC32 CRC mode selection bit 1 1 read-write INIT Initialization bit 0 0 read-write CRCINIT Initial Value Register 0x4 32 read-write 0xFFFFFFFF 0xFFFFFFFF D Initial value bits 0 31 read-write CRCIN Input Data Register 0x8 32 read-write 0x00000000 0xFFFFFFFF D Input data bits 0 31 read-write CRCR CRC Register 0xC 32 read-only 0xFFFFFFFF 0xFFFFFFFF D CRC bits 0 31 read-only WC Watch Counter WC 0x4003A000 0x0 0x3 registers 0x10 0x2 registers 0x14 0x1 registers OSC_PLL_WC_RTC 24 WCRD Watch Counter Read Register 0x0 8 read-only 0x00 0x3F CTR Counter read bits 0 5 read-only WCRL Watch Counter Reload Register 0x1 8 read-write 0x00 0x3F RLC Counter reload value setting bits 0 5 read-write WCCR Watch Counter Control Register 0x2 8 read-write 0x00 0xCF WCEN Watch counter operation enable bit 7 7 read-write WCOP Watch counter operating state flag 6 6 read-only CS Count clock select bits 2 3 read-write WCIE Interrupt request enable bit 1 1 read-write WCIF Interrupt request flag bit 0 0 read-write CLK_SEL Clock Selection Register 0x10 16 read-write 0x0000 0x0703 SEL_OUT Output clock selection bit 8 10 read-write SEL_IN Input clock selection bit 0 1 read-write CLK_EN Division Clock Enable Register 0x14 8 read-write 0x00 0x03 CLK_EN_R Division clock enable read bit 1 1 read-write CLK_EN Division clock enable bit 0 0 read-write RTC REAL-TIME CLOCK RTC 0x4003B000 0x0 0x13 registers 0x15 0x3 registers 0x19 0x2 registers 0x1C 0x4 registers 0x20 0x2 registers 0x24 0x3 registers 0x28 0x2 registers 0x2C 0x1 registers 0x30 0x1 registers OSC_PLL_WC_RTC 24 WTCR1 Control Register 1 0x0 32 read-write 0x00000000 0xFFFF1F7D INTCRIE Year/month/date/hour/minute/second/day of the week counter value read completion interrupt enable bit 31 31 read-write INTERIE Time rewrite error interrupt enable bit 30 30 read-write INTALIE Alarm interrupt enable bit 29 29 read-write INTTMIE Timer interrupt enable bit 28 28 read-write INTHIE 1-hour interrupt enable bit 27 27 read-write INTMIE 1-minute interrupt enable bit 26 26 read-write INTSIE 1-second interrupt enable bit 25 25 read-write INTSSIE 0.5-second interrupt enable bit 24 24 read-write INTCRI Year/month/date/hour/minute/second/day of the week counter value read completion interrupt flag bit 23 23 read-write INTERI Time rewrite error interrupt flag bit 22 22 read-write INTALI Alarm interrupt flag bit 21 21 read-write INTTMI Timer interrupt flag bit 20 20 read-write INTHI 1-hour interrupt flag bit 19 19 read-write INTMI 1-minute interrupt flag bit 18 18 read-write INTSI 1-second interrupt flag bit 17 17 read-write INTSSI 0.5-second interrupt flag bit 16 16 read-write YEN Alarm year register enable bit 12 12 read-write MOEN Alarm month register enable bit 11 11 read-write DEN Alarm date register enable bit 10 10 read-write HEN Alarm hour register enable bit 9 9 read-write MIEN Alarm minute register enable bit 8 8 read-write BUSY Busy bit 6 6 read-only SCRST Sub second generation/1-second generation counter reset bit 5 5 read-write SCST 1-second clock output stop bit 4 4 read-write SRST RTC reset bit 3 3 read-write RUN RTC count block operation bit 2 2 read-only ST Start bit 0 0 read-write WTCR2 Control Register 2 0x4 32 read-write 0x00000000 0x00000701 TMRUN Timer counter operation bit 10 10 read-only TMEN Timer counter control bit 9 9 read-write TMST Timer counter start bit 8 8 read-write CREAD Year/month/date/hour/minute/second/day of the week counter value read control bit 0 0 read-write WTBR Counter Cycle Setting Register 0x8 32 read-write 0x00000000 0x00FFFFFF BR23 Bit23 of WTBR 23 23 read-write BR22 Bit22 of WTBR 22 22 read-write BR21 Bit21 of WTBR 21 21 read-write BR20 Bit20 of WTBR 20 20 read-write BR19 Bit19 of WTBR 19 19 read-write BR18 Bit18 of WTBR 18 18 read-write BR17 Bit17 of WTBR 17 17 read-write BR16 Bit16 of WTBR 16 16 read-write BR15 Bit15 of WTBR 15 15 read-write BR14 Bit14 of WTBR 14 14 read-write BR13 Bit13 of WTBR 13 13 read-write BR12 Bit12 of WTBR 12 12 read-write BR11 Bit11 of WTBR 11 11 read-write BR10 Bit10 of WTBR 10 10 read-write BR9 Bit9 of WTBR 9 9 read-write BR8 Bit8 of WTBR 8 8 read-write BR7 Bit7 of WTBR 7 7 read-write BR6 Bit6 of WTBR 6 6 read-write BR5 Bit5 of WTBR 5 5 read-write BR4 Bit4 of WTBR 4 4 read-write BR3 Bit3 of WTBR 3 3 read-write BR2 Bit2 of WTBR 2 2 read-write BR1 Bit1 of WTBR 1 1 read-write BR0 Bit0 of WTBR 0 0 read-write WTDR Date Register 0xF 8 read-write 0x00 0x3F TD The second digit of the date 4 5 read-write D The first digit of the date 0 3 read-write WTHR Hour register 0xE 8 read-write 0x00 0x3F TH The second digit of the hour 4 5 read-write H The first digit of the hour 0 3 read-write WTMIR Minute Register 0xD 8 read-write 0x00 0x7F TMI The second digit of the minute 4 6 read-write MI The first digit of the minute 0 3 read-write WTSR Second Register 0xC 8 read-write 0x00 0x7F TS The second digit of the second 4 6 read-write S The first digit of the second 0 3 read-write WTYR Year Register 0x12 8 read-write 0x00 0xFF TY The second digit of the year 4 7 read-write Y The first digit of the year 0 3 read-write WTMOR Month Register 0x11 8 read-write 0x00 0x1F TMO0 The second digit in the month 4 4 read-write MO The first digit of the month 0 3 read-write WTDW Day of the Week Register 0x10 8 read-write 0x00 0x07 DW Day of the week 0 2 read-write ALDR Alarm Date Register 0x17 8 read-write 0x00 0x3F TAD The second digit of the alarm-set date 4 5 read-write AD The first digit of the alarm-set date 0 3 read-write ALHR Alarm Hour Register 0x16 8 read-write 0x00 0x3F TAH The second digit of the alarm-set hour 4 5 read-write AH The first digit of the alarm-set hour 0 3 read-write ALMIR Alarm Minute Register 0x15 8 read-write 0x00 0x7F TAMI The second digit of the alarm-set minute 4 6 read-write AMI The first digit of the alarm-set minute 0 3 read-write ALYR Alarm Years Register 0x1A 8 read-write 0x00 0xFF TAY The second digit of the alarm-set year 4 7 read-write AY The first digit of the alarm-set year 0 3 read-write ALMOR Alarm Month Register 0x19 8 read-write 0x00 0x1F TAMO0 The second digit of the alarm-set month 4 4 read-write AMO The first digit of the alarm-set month 0 3 read-write WTTR Timer Setting Register 0x1C 32 read-write 0x00000000 0x0003FFFF TM Timer setting register 0 17 read-write WTCLKS Clock Selection Register 0x20 8 read-write 0x00 0x01 WTCLKS Input clock selection bit 0 0 read-write WTCLKM Selection Clock Status Register 0x21 8 read-only 0x00 0x03 WTCLKM Clock selection status bits 0 1 read-only WTCAL Frequency Correction Value Setting Register 0x24 16 read-write 0x0000 0x03FF WTCAL Frequency correction value setting bits 0 9 read-write WTCALEN Frequency Correction Enable Register 0x26 8 read-write 0x00 0x01 WTCALEN Frequency correction enable bit 0 0 read-write WTDIV Divider Ratio Setting Register 0x28 8 read-write 0x00 0x0F WTDIV Divider ratio setting bits 0 3 read-write WTDIVEN Divider Output Enable Register 0x29 8 read-write 0x00 0x03 WTDIVRDY Divider status bit 1 1 read-only WTDIVEN Divider enable bit 0 0 read-write WTCALPRD Frequency Correction Cycle Setting Register 0x2C 8 read-write 0x13 0x3F WTCALPRD Frequency correction value setting bits 0 5 read-write WTCOSEL RTCCO Output Selection Register 0x30 8 read-write 0x00 0x01 WTCOSEL RTCCO output selection bit 0 0 read-write LSCRP Low-speed CR Prescaler Register LSCRP 0x4003C000 0x0 0x1 registers LCR_PRSLD Low-speed CR Prescaler Control Register 0x0 8 read-write 0x00 0x3F LCR_PRSLD Low-speed CR Prescaler Load 0 5 read-write PCG Peripheral Clock Gating Registers PCG 0x4003C100 0x0 0x4 registers 0x4 0x4 registers 0x10 0x4 registers 0x14 0x4 registers 0x20 0x4 registers 0x24 0x4 registers CKEN0 Peripheral Function Clock Control Register 0 0x0 32 read-write 0x110FFFFF 0x110FFFFF GIOCK Software clock control of GPIO/Fast GPIO function 28 28 read-write DMACK Supplying and gating settings of DMAC operation clock 24 24 read-write ADCCK3 Settings for operation clock supplying and gating to A/D converter unit 3 19 19 read-write ADCCK2 Settings for operation clock supplying and gating to A/D converter unit 2 18 18 read-write ADCCK1 Settings for operation clock supplying and gating to A/D converter unit 1 17 17 read-write ADCCK0 Settings for operation clock supplying and gating to A/D converter unit 0 16 16 read-write MFSCK15 Settings for operation clock supply and gating to multi-function serial interface ch.15 15 15 read-write MFSCK14 Settings for operation clock supply and gating to multi-function serial interface ch.14 14 14 read-write MFSCK13 Settings for operation clock supply and gating to multi-function serial interface ch.13 13 13 read-write MFSCK12 Settings for operation clock supply and gating to multi-function serial interface ch.12 12 12 read-write MFSCK11 Settings for operation clock supply and gating to multi-function serial interface ch.11 11 11 read-write MFSCK10 Settings for operation clock supply and gating to multi-function serial interface ch.10 10 10 read-write MFSCK9 Settings for operation clock supply and gating to multi-function serial interface ch.9 9 9 read-write MFSCK8 Settings for operation clock supply and gating to multi-function serial interface ch.8 8 8 read-write MFSCK7 Settings for operation clock supply and gating to multi-function serial interface ch.7 7 7 read-write MFSCK6 Settings for operation clock supply and gating to multi-function serial interface ch.6 6 6 read-write MFSCK5 Settings for operation clock supply and gating to multi-function serial interface ch.5 5 5 read-write MFSCK4 Settings for operation clock supply and gating to multi-function serial interface ch.4 4 4 read-write MFSCK3 Settings for operation clock supply and gating to multi-function serial interface ch.3 3 3 read-write MFSCK2 Settings for operation clock supply and gating to multi-function serial interface ch.2 2 2 read-write MFSCK1 Settings for operation clock supply and gating to multi-function serial interface ch.1 1 1 read-write MFSCK0 Settings for operation clock supply and gating to multi-function serial interface ch.0 0 0 read-write MRST0 Peripheral Function Reset Control Register 0 0x4 32 read-write 0x00000000 0x010FFFFF DMARST Reset control of DMAC 24 24 read-write ADCRST3 Reset control of A/D converter unit 3 19 19 read-write ADCRST2 Reset control of A/D converter unit 2 18 18 read-write ADCRST1 Reset control of A/D converter unit 1 17 17 read-write ADCRST0 Reset control of A/D converter unit 0 16 16 read-write MFSRST15 Control of software reset of multi-function serial interface ch.15 15 15 read-write MFSRST14 Control of software reset of multi-function serial interface ch.14 14 14 read-write MFSRST13 Control of software reset of multi-function serial interface ch.13 13 13 read-write MFSRST12 Control of software reset of multi-function serial interface ch.12 12 12 read-write MFSRST11 Control of software reset of multi-function serial interface ch.11 11 11 read-write MFSRST10 Control of software reset of multi-function serial interface ch.10 10 10 read-write MFSRST9 Control of software reset of multi-function serial interface ch.9 9 9 read-write MFSRST8 Control of software reset of multi-function serial interface ch.8 8 8 read-write MFSRST7 Control of software reset of multi-function serial interface ch.7 7 7 read-write MFSRST6 Control of software reset of multi-function serial interface ch.6 6 6 read-write MFSRST5 Control of software reset of multi-function serial interface ch.5 5 5 read-write MFSRST4 Control of software reset of multi-function serial interface ch.4 4 4 read-write MFSRST3 Control of software reset of multi-function serial interface ch.3 3 3 read-write MFSRST2 Control of software reset of multi-function serial interface ch.2 2 2 read-write MFSRST1 Control of software reset of multi-function serial interface ch.1 1 1 read-write MFSRST0 Control of software reset of multi-function serial interface ch.0 0 0 read-write CKEN1 Peripheral Function Clock Control Register 1 0x10 32 read-write 0x000F0F0F 0x000F0F0F QDUCK3 Settings for operation clock supply and gating of quad counter unit 3 19 19 read-write QDUCK2 Settings for operation clock supply and gating of quad counter unit 2 18 18 read-write QDUCK1 Settings for operation clock supply and gating of quad counter unit 1 17 17 read-write QDUCK0 Settings for operation clock supply and gating of quad counter unit 0 16 16 read-write MFTCK3 Settings for operation clock supply and gating of multi-function timer 3 and PPG 24/26/28/30 11 11 read-write MFTCK2 Settings for operation clock supply and gating of multi-function timer 2 and PPG 16/18/20/22 10 10 read-write MFTCK1 Settings for operation clock supply and gating of multi-function timer 1 and PPG 8/10/12/14 9 9 read-write MFTCK0 Settings for operation clock supply and gating of multi-function timer 0 and PPG 0/2/4/6 8 8 read-write BTMCK3 Settings operation clock supply and gating to base timer 12/13/14/15 3 3 read-write BTMCK2 Settings operation clock supply and gating to base timer 8/9/10/11 2 2 read-write BTMCK1 Settings operation clock supply and gating to base timer 4/5/6/7 1 1 read-write BTMCK0 Settings operation clock supply and gating to base timer 0/1/2/3 0 0 read-write MRST1 Peripheral Function Reset Control Register 1 0x14 32 read-write 0x00000000 0x000F0F0F QDURST3 Reset control of quad counter unit 3 19 19 read-write QDURST2 Reset control of quad counter unit 2 18 18 read-write QDURST1 Reset control of quad counter unit 1 17 17 read-write QDURST0 Reset control of quad counter unit 0 16 16 read-write MFTRST3 Control of multi-function timer 3 and PPG 24/26/28/30 reset control 11 11 read-write MFTRST2 Control of multi-function timer 2 and PPG 16/18/20/22 reset control 10 10 read-write MFTRST1 Control of multi-function timer 1 and PPG 8/10/12/14 reset control 9 9 read-write MFTRST0 Control of multi-function timer 0 and PPG 0/2/4/6 reset control 8 8 read-write BTMRST3 Reset control of base timer 12/13/14/15 3 3 read-write BTMRST2 Reset control of base timer 8/9/10/11 2 2 read-write BTMRST1 Reset control of base timer 4/5/6/7 1 1 read-write BTMRST0 Reset control of base timer 0/1/2/3 0 0 read-write CKEN2 Peripheral Function Clock Control Register 2 0x20 32 read-write 0x00000000 0x00000030 CANCK1 Peripheral Function Clock Control Register 2 5 5 read-write CANCK0 $ 4 4 read-write MRST2 Peripheral Function Reset Control Register 2 0x24 32 read-write 0x00000000 0x00000030 CANRST1 Peripheral Function Reset Control Register 2 5 5 read-write CANRST0 $ 4 4 read-write DMAC DMAC Registers DMAC 0x40060000 0x0 0x4 registers 0x10 0x80 registers DMAC0 19 DMAC1 20 DMACR Entire DMAC Configuration Register 0x0 32 read-write 0x00000000 0xDF000000 DE DMA Enable (all-channel operation enable bit) 31 31 read-write DS DMA Stop 30 30 read-write PR Priority Rotation 28 28 read-write DH DMA Halt (All-channel pause bit) 24 27 read-write DMACA0 Configuration A Register 0x10 32 read-write 0x00000000 0xFF8FFFFF EB Enable bit (individual-channel operation enable bit) 31 31 read-write PB Pause bit (individual-channel pause bit) 30 30 read-write ST Software Trigger 29 29 read-write IS Input Select 23 28 read-write BC Block Count 16 19 read-write TC Transfer Count 0 15 read-write DMACB0 Configuration B Register 0x14 32 read-write 0x00000000 0x3FFF0001 MS Mode Select 28 29 read-write TW Transfer Width 26 27 read-write FS Fixed Source 25 25 read-write FD Fixed Destination 24 24 read-write RC Reload Count (BC/TC reload) 23 23 read-write RS Reload Source 22 22 read-write RD Reload Destination 21 21 read-write EI Error Interrupt (unsuccessful transfer completion interrupt enable) 20 20 read-write CI Completion Interrupt (successful transfer completion interrupt enable) 19 19 read-write SS Stop Status (stop status notification) 16 18 read-write EM Enable bit Mask (EB bit clear mask) 0 0 read-write DMACSA0 Transfer Source Address Register 0 0x18 32 read-write 0x00000000 0xFFFFFFFF DMACDA0 Transfer Destination Address Register 0 0x1C 32 read-write 0x00000000 0xFFFFFFFF DMACA1 Configuration A Register 1 0x20 DMACB1 Configuration B Register 1 0x24 DMACSA1 Transfer Source Address Register 1 0x28 DMACDA1 Transfer Destination Address Register 1 0x2C DMACA2 Configuration A Register 2 0x30 DMACB2 Configuration B Register 2 0x34 DMACSA2 Transfer Source Address Register 2 0x38 DMACDA2 Transfer Destination Address Register 2 0x3C DMACA3 Configuration A Register 3 0x40 DMACB3 Configuration B Register 3 0x44 DMACSA3 Transfer Source Address Register 3 0x48 DMACDA3 Transfer Destination Address Register 3 0x4C DMACA4 Configuration A Register 4 0x50 DMACB4 Configuration B Register 4 0x54 DMACSA4 Transfer Source Address Register 4 0x58 DMACDA4 Transfer Destination Address Register 4 0x5C DMACA5 Configuration A Register 5 0x60 DMACB5 Configuration B Register 5 0x64 DMACSA5 Transfer Source Address Register 5 0x68 DMACDA5 Transfer Destination Address Register 5 0x6C DMACA6 Configuration A Register 6 0x70 DMACB6 Configuration B Register 6 0x74 DMACSA6 Transfer Source Address Register 6 0x78 DMACDA6 Transfer Destination Address Register 6 0x7C DMACA7 Configuration A Register 7 0x80 DMACB7 Configuration B Register 7 0x84 DMACSA7 Transfer Source Address Register 7 0x88 DMACDA7 Transfer Destination Address Register 7 0x8C MTB_DWT Micro Trace Buffer Data Watchpoint and Trace Registers MTB_DWT 0xF0001000 0x0 0x4 registers 0x4 0x4 registers 0x8 0x4 registers 0x10 0x4 registers 0x14 0x4 registers 0x18 0x4 registers 0x20 0x1 registers 0xFD0 0x4 registers 0xFD4 0x4 registers 0xFD8 0x4 registers 0xFDC 0x4 registers 0xFE0 0x4 registers 0xFE4 0x4 registers 0xFE8 0x4 registers 0xFEC 0x4 registers 0xFF0 0x4 registers 0xFF4 0x4 registers 0xFF8 0x4 registers 0xFFC 0x4 registers CMP_ADDR_START MTB_DWT Address Compare Start trace Register 0x0 32 read-write 0x00000000 0xFFFFFFFF ADCMP_STA MTB_DWT address comparison start trace bits 0 31 read-write CMP_DATA_START MTB_DWT Data Compare Start trace Register 0x4 32 read-write 0x00000000 0xFFFFFFFF DTCMP_STA MTB_DWT data comparison start trace bits 0 31 read-write CMP_MASK_START MTB_DWT Mask Data Compare Start Trace Register 0x8 32 read-write 0x00000000 0xFFFFFFFF MSK_STA MTB_DWT data compare start trace register mask bits 0 31 read-write CMP_ADDR_STOP MTB_DWT Address Compare Stop trace Register 0x10 32 read-write 0x00000000 0xFFFFFFFF ADCMP_STO MTB_DWT address comparison stop trace bits 0 31 read-write CMP_DATA_STOP MTB_DWT Data Compare Stop trace Register 0x14 32 read-write 0x00000000 0xFFFFFFFF DTCMP_STO MTB_DWT data comparison stop trace bits 0 31 read-write CMP_MASK_STOP MTB_DWT Mask Data Compare Stop Trace Register 0x18 32 read-write 0x00000000 0xFFFFFFFF MSK_STO MTB_DWT data compare stop trace register mask bits 0 31 read-write FCT MTB_DWT Function Register 0x20 8 read-write 0x00 0xFF DSTP Data size stop bits 6 7 read-write DSTA Data size start bits 4 5 read-write STPEN Enable MTB_DWT stop MTB function bits 2 3 read-write STAEN Enable MTB_DWT start MTB function bits 0 1 read-write PID4 Peripheral ID4 Register 0xFD0 32 read-only 0x00000000 0xFFFFFFFF PERID Peripheral ID bits 0 31 read-only PID5 Peripheral ID5 Register 0xFD4 32 read-only 0x00000000 0xFFFFFFFF PERID Peripheral ID bits 0 31 read-only PID6 Peripheral ID6 Register 0xFD8 32 read-only 0x00000000 0xFFFFFFFF PERID Peripheral ID bits 0 31 read-only PID7 Peripheral ID7 Register 0xFDC 32 read-only 0x00000000 0xFFFFFFFF PERID Peripheral ID bits 0 31 read-only PID0 Peripheral ID0 Register 0xFE0 32 read-only 0x00000016 0xFFFFFFFF PERID Peripheral ID bits 0 31 read-only PID1 Peripheral ID1 Register 0xFE4 32 read-only 0x00000048 0xFFFFFFFF PERID Peripheral ID bits 0 31 read-only PID2 Peripheral ID2 Register 0xFE8 32 read-only 0x00000008 0xFFFFFFFF PERID Peripheral ID bits 0 31 read-only PID3 Peripheral ID3 Register 0xFEC 32 read-only 0x00000000 0xFFFFFFFF PERID Peripheral ID bits 0 31 read-only CID0 Component ID0 Register 0xFF0 32 read-only 0x0000000D 0xFFFFFFFF CPNTID Component ID bits 0 31 read-only CID1 Component ID1 Register 0xFF4 32 read-only 0x00000090 0xFFFFFFFF CPNTID Component ID bits 0 31 read-only CID2 Component ID2 Register 0xFF8 32 read-only 0x00000005 0xFFFFFFFF CPNTID Component ID bits 0 31 read-only CID3 Component ID3 Register 0xFFC 32 read-only 0x000000B1 0xFFFFFFFF CPNTID Component ID bits 0 31 read-only FASTIO Fast GPIO Registers FASTIO 0xF8000000 0x0 0x100 registers FPDIR0 Fast GPIO Input Data Register 0 0x0 32 read-only 0x00000000 0x0000801F P0F Bit15 of FPDIR0 15 15 read-only P04 Bit4 of FPDIR0 4 4 read-only P03 Bit3 of FPDIR0 3 3 read-only P02 Bit2 of FPDIR0 2 2 read-only P01 Bit1 of FPDIR0 1 1 read-only P00 Bit0 of FPDIR0 0 0 read-only FPDIR1 Fast GPIO Input Data Register 1 0x4 32 read-only 0x00000000 0x0000003F P15 Bit5 of FPDIR1 5 5 read-only P14 Bit4 of FPDIR1 4 4 read-only P13 Bit3 of FPDIR1 3 3 read-only P12 Bit2 of FPDIR1 2 2 read-only P11 Bit1 of FPDIR1 1 1 read-only P10 Bit0 of FPDIR1 0 0 read-only FPDIR2 Fast GPIO Input Data Register 2 0x8 32 read-only 0x00000000 0x0000000E P23 Bit3 of FPDIR2 3 3 read-only P22 Bit2 of FPDIR2 2 2 read-only P21 Bit1 of FPDIR2 1 1 read-only FPDIR3 Fast GPIO Input Data Register 3 0xC 32 read-only 0x00000000 0x0000FE00 P3F Bit15 of FPDIR3 15 15 read-only P3E Bit14 of FPDIR3 14 14 read-only P3D Bit13 of FPDIR3 13 13 read-only P3C Bit12 of FPDIR3 12 12 read-only P3B Bit11 of FPDIR3 11 11 read-only P3A Bit10 of FPDIR3 10 10 read-only P39 Bit9 of FPDIR3 9 9 read-only FPDIR4 Fast GPIO Input Data Register 4 0x10 32 read-only 0x00000000 0x000006C0 P4A Bit10 of FPDIR4 10 10 read-only P49 Bit9 of FPDIR4 9 9 read-only P47 Bit7 of FPDIR4 7 7 read-only P46 Bit6 of FPDIR4 6 6 read-only FPDIR5 Fast GPIO Input Data Register 5 0x14 32 read-only 0x00000000 0x00000007 P52 Bit2 of FPDIR5 2 2 read-only P51 Bit1 of FPDIR5 1 1 read-only P50 Bit0 of FPDIR5 0 0 read-only FPDIR6 Fast GPIO Input Data Register 6 0x18 32 read-only 0x00000000 0x00000003 P61 Bit1 of FPDIR6 1 1 read-only P60 Bit0 of FPDIR6 0 0 read-only FPDIR8 Fast GPIO Input Data Register 8 0x20 32 read-only 0x00000000 0x00000007 P82 Bit2 of FPDIR8 2 2 read-only P81 Bit1 of FPDIR8 1 1 read-only P80 Bit0 of FPDIR8 0 0 read-only FPDIRE Fast GPIO Input Data Register E 0x38 32 read-only 0x00000000 0x0000000D PE3 Bit3 of FPDIRE 3 3 read-only PE2 Bit2 of FPDIRE 2 2 read-only PE0 Bit0 of FPDIRE 0 0 read-only FPDOR0 Fast GPIO Output Data Register 0 0x40 32 read-write 0x00000000 0x0000801F P0F Bit15 of FPDOR0 15 15 read-write P04 Bit4 of FPDOR0 4 4 read-write P03 Bit3 of FPDOR0 3 3 read-write P02 Bit2 of FPDOR0 2 2 read-write P01 Bit1 of FPDOR0 1 1 read-write P00 Bit0 of FPDOR0 0 0 read-write FPDOR1 Fast GPIO Output Data Register 1 0x44 32 read-write 0x00000000 0x0000003F P15 Bit5 of FPDOR1 5 5 read-write P14 Bit4 of FPDOR1 4 4 read-write P13 Bit3 of FPDOR1 3 3 read-write P12 Bit2 of FPDOR1 2 2 read-write P11 Bit1 of FPDOR1 1 1 read-write P10 Bit0 of FPDOR1 0 0 read-write FPDOR2 Fast GPIO Output Data Register 2 0x48 32 read-write 0x00000000 0x0000000E P23 Bit3 of FPDOR2 3 3 read-write P22 Bit2 of FPDOR2 2 2 read-write P21 Bit1 of FPDOR2 1 1 read-write FPDOR3 Fast GPIO Output Data Register 3 0x4C 32 read-write 0x00000000 0x0000FE00 P3F Bit15 of FPDOR3 15 15 read-write P3E Bit14 of FPDOR3 14 14 read-write P3D Bit13 of FPDOR3 13 13 read-write P3C Bit12 of FPDOR3 12 12 read-write P3B Bit11 of FPDOR3 11 11 read-write P3A Bit10 of FPDOR3 10 10 read-write P39 Bit9 of FPDOR3 9 9 read-write FPDOR4 Fast GPIO Output Data Register 4 0x50 32 read-write 0x00000000 0x000006C0 P4A Bit10 of FPDOR4 10 10 read-write P49 Bit9 of FPDOR4 9 9 read-write P47 Bit7 of FPDOR4 7 7 read-write P46 Bit6 of FPDOR4 6 6 read-write FPDOR5 Fast GPIO Output Data Register 5 0x54 32 read-write 0x00000000 0x00000007 P52 Bit2 of FPDOR5 2 2 read-write P51 Bit1 of FPDOR5 1 1 read-write P50 Bit0 of FPDOR5 0 0 read-write FPDOR6 Fast GPIO Output Data Register 6 0x58 32 read-write 0x00000000 0x00000003 P61 Bit1 of FPDOR6 1 1 read-write P60 Bit0 of FPDOR6 0 0 read-write FPDOR8 Fast GPIO Output Data Register 8 0x60 32 read-write 0x00000000 0x00000007 P82 Bit2 of FPDOR8 2 2 read-write P81 Bit1 of FPDOR8 1 1 read-write P80 Bit0 of FPDOR8 0 0 read-write FPDORE Fast GPIO Output Data Register E 0x78 32 read-write 0x00000000 0x0000000D PE3 Bit3 of FPDORE 3 3 read-write PE2 Bit2 of FPDORE 2 2 read-write PE0 Bit0 of FPDORE 0 0 read-write M_FPDIR0 Mirror Fast GPIO Input Data Register 0 0x80 32 read-only 0x00000000 0x000000FF P22 Bit7 of M_FPDIR0 7 7 read-only P23 Bit6 of M_FPDIR0 6 6 read-only P15 Bit5 of M_FPDIR0 5 5 read-only P14 Bit4 of M_FPDIR0 4 4 read-only P13 Bit3 of M_FPDIR0 3 3 read-only P12 Bit2 of M_FPDIR0 2 2 read-only P11 Bit1 of M_FPDIR0 1 1 read-only P10 Bit0 of M_FPDIR0 0 0 read-only M_FPDIR1 Mirror Fast GPIO Input Data Register 1 0x84 32 read-only 0x00000000 0x000000FF P47 Bit7 of M_FPDIR1 7 7 read-only P46 Bit6 of M_FPDIR1 6 6 read-only P3F Bit5 of M_FPDIR1 5 5 read-only P3E Bit4 of M_FPDIR1 4 4 read-only P3D Bit3 of M_FPDIR1 3 3 read-only P3C Bit2 of M_FPDIR1 2 2 read-only P3B Bit1 of M_FPDIR1 1 1 read-only P3A Bit0 of M_FPDIR1 0 0 read-only M_FPDOR0 Mirror Fast GPIO Output Data Register 0 0xC0 32 read-write 0x00000000 0x000000FF P22 Bit7 of M_FPDOR0 7 7 read-write P23 Bit6 of M_FPDOR0 6 6 read-write P15 Bit5 of M_FPDOR0 5 5 read-write P14 Bit4 of M_FPDOR0 4 4 read-write P13 Bit3 of M_FPDOR0 3 3 read-write P12 Bit2 of M_FPDOR0 2 2 read-write P11 Bit1 of M_FPDOR0 1 1 read-write P10 Bit0 of M_FPDOR0 0 0 read-write M_FPDOR1 Mirror Fast GPIO Output Data Register 1 0xC4 32 read-write 0x00000000 0x000000FF P47 Bit7 of M_FPDOR1 7 7 read-write P46 Bit6 of M_FPDOR1 6 6 read-write P3F Bit5 of M_FPDOR1 5 5 read-write P3E Bit4 of M_FPDOR1 4 4 read-write P3D Bit3 of M_FPDOR1 3 3 read-write P3C Bit2 of M_FPDOR1 2 2 read-write P3B Bit1 of M_FPDOR1 1 1 read-write P3A Bit0 of M_FPDOR1 0 0 read-write