Freescale Semiconductor, Inc. Freescale Kinetis_V MKV11Z7 1.6 MKV11Z7 Freescale Microcontroller Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. 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CM0PLUS r0p0 little false false false true 2 false 8 32 FTFA_FlashConfig Flash configuration field NV_ 0x400 0 0xE registers BACKKEY3 Backdoor Comparison Key 3. 0 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY2 Backdoor Comparison Key 2. 0x1 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY1 Backdoor Comparison Key 1. 0x2 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY0 Backdoor Comparison Key 0. 0x3 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY7 Backdoor Comparison Key 7. 0x4 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY6 Backdoor Comparison Key 6. 0x5 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY5 Backdoor Comparison Key 5. 0x6 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY4 Backdoor Comparison Key 4. 0x7 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only FPROT3 Non-volatile P-Flash Protection 1 - Low Register 0x8 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FPROT2 Non-volatile P-Flash Protection 1 - High Register 0x9 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FPROT1 Non-volatile P-Flash Protection 0 - Low Register 0xA 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FPROT0 Non-volatile P-Flash Protection 0 - High Register 0xB 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FSEC Non-volatile Flash Security Register 0xC 8 read-only 0xFF 0xFF SEC Flash Security 0 2 read-only 10 MCU security status is unsecure #10 11 MCU security status is secure #11 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 10 Freescale factory access denied #10 11 Freescale factory access granted #11 MEEN no description available 4 2 read-only 10 Mass erase is disabled #10 11 Mass erase is enabled #11 KEYEN Backdoor Key Security Enable 6 2 read-only 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 FOPT Non-volatile Flash Option Register 0xD 8 read-only 0xFF 0xFF LPBOOT0 no description available 0 1 read-only 00 Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. #0 01 Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. #1 NMI_DIS no description available 2 1 read-only 00 NMI interrupts are always blocked #0 01 NMI_b pin/interrupts reset default to enabled #1 RESET_PIN_CFG no description available 3 1 read-only 00 RESET pin is disabled following a POR and cannot be enabled as reset function #0 01 RESET_b pin is dedicated #1 LPBOOT1 no description available 4 1 read-only 00 Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. #0 01 Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. #1 FAST_INIT no description available 5 1 read-only 00 Slower initialization #0 01 Fast Initialization #1 DMA Enhanced direct memory access controller DMA_ 0x40008000 0 0x1100 registers DMA0_DMA4 0 DMA1_DMA5 1 DMA2_DMA6 2 DMA3_DMA7 3 DMA_Error 4 CR Control Register 0 32 read-write 0 0xFFFFFFFF EDBG Enable Debug 1 1 read-write 0 When in debug mode, the DMA continues to operate. #0 1 When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. #1 ERCA Enable Round Robin Channel Arbitration 2 1 read-write 0 Fixed priority arbitration is used for channel selection . #0 1 Round robin arbitration is used for channel selection . #1 HOE Halt On Error 4 1 read-write 0 Normal operation #0 1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. #1 HALT Halt DMA Operations 5 1 read-write 0 Normal operation #0 1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. #1 CLM Continuous Link Mode 6 1 read-write 0 A minor loop channel link made to itself goes through channel arbitration before being activated again. #0 1 A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. #1 EMLM Enable Minor Loop Mapping 7 1 read-write 0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. #0 1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. #1 ECX Error Cancel Transfer 16 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. #1 CX Cancel Transfer 17 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. #1 ACTIVE DMA Active Status 31 1 read-only 0 eDMA is idle. #0 1 eDMA is executing a channel. #1 ES Error Status Register 0x4 32 read-only 0 0xFFFFFFFF DBE Destination Bus Error 0 1 read-only 0 No destination bus error #0 1 The last recorded error was a bus error on a destination write #1 SBE Source Bus Error 1 1 read-only 0 No source bus error #0 1 The last recorded error was a bus error on a source read #1 SGE Scatter/Gather Configuration Error 2 1 read-only 0 No scatter/gather configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. #1 NCE NBYTES/CITER Configuration Error 3 1 read-only 0 No NBYTES/CITER configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] #1 DOE Destination Offset Error 4 1 read-only 0 No destination offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. #1 DAE Destination Address Error 5 1 read-only 0 No destination address configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. #1 SOE Source Offset Error 6 1 read-only 0 No source offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. #1 SAE Source Address Error 7 1 read-only 0 No source address configuration error. #0 1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. #1 ERRCHN Error Channel Number or Canceled Channel Number 8 3 read-only CPE Channel Priority Error 14 1 read-only 0 No channel priority error #0 1 The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique. #1 ECX Transfer Canceled 16 1 read-only 0 No canceled transfers #0 1 The last recorded entry was a canceled transfer by the error cancel transfer input #1 VLD Logical OR of all ERR status bits 31 1 read-only 0 No ERR bits are set. #0 1 At least one ERR bit is set indicating a valid error exists that has not been cleared. #1 ERQ Enable Request Register 0xC 32 read-write 0 0xFFFFFFFF ERQ0 Enable DMA Request 0 0 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ1 Enable DMA Request 1 1 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ2 Enable DMA Request 2 2 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ3 Enable DMA Request 3 3 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ4 Enable DMA Request 4 4 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ5 Enable DMA Request 5 5 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ6 Enable DMA Request 6 6 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ7 Enable DMA Request 7 7 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 EEI Enable Error Interrupt Register 0x14 32 read-write 0 0xFFFFFFFF EEI0 Enable Error Interrupt 0 0 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI1 Enable Error Interrupt 1 1 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI2 Enable Error Interrupt 2 2 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI3 Enable Error Interrupt 3 3 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI4 Enable Error Interrupt 4 4 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI5 Enable Error Interrupt 5 5 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI6 Enable Error Interrupt 6 6 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI7 Enable Error Interrupt 7 7 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 CEEI Clear Enable Error Interrupt Register 0x18 8 write-only 0 0xFF CEEI Clear Enable Error Interrupt 0 3 write-only CAEE Clear All Enable Error Interrupts 6 1 write-only 0 Clear only the EEI bit specified in the CEEI field #0 1 Clear all bits in EEI #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SEEI Set Enable Error Interrupt Register 0x19 8 write-only 0 0xFF SEEI Set Enable Error Interrupt 0 3 write-only SAEE Sets All Enable Error Interrupts 6 1 write-only 0 Set only the EEI bit specified in the SEEI field. #0 1 Sets all bits in EEI #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERQ Clear Enable Request Register 0x1A 8 write-only 0 0xFF CERQ Clear Enable Request 0 3 write-only CAER Clear All Enable Requests 6 1 write-only 0 Clear only the ERQ bit specified in the CERQ field #0 1 Clear all bits in ERQ #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SERQ Set Enable Request Register 0x1B 8 write-only 0 0xFF SERQ Set Enable Request 0 3 write-only SAER Set All Enable Requests 6 1 write-only 0 Set only the ERQ bit specified in the SERQ field #0 1 Set all bits in ERQ #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CDNE Clear DONE Status Bit Register 0x1C 8 write-only 0 0xFF CDNE Clear DONE Bit 0 3 write-only CADN Clears All DONE Bits 6 1 write-only 0 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field #0 1 Clears all bits in TCDn_CSR[DONE] #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SSRT Set START Bit Register 0x1D 8 write-only 0 0xFF SSRT Set START Bit 0 3 write-only SAST Set All START Bits (activates all channels) 6 1 write-only 0 Set only the TCDn_CSR[START] bit specified in the SSRT field #0 1 Set all bits in TCDn_CSR[START] #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERR Clear Error Register 0x1E 8 write-only 0 0xFF CERR Clear Error Indicator 0 3 write-only CAEI Clear All Error Indicators 6 1 write-only 0 Clear only the ERR bit specified in the CERR field #0 1 Clear all bits in ERR #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CINT Clear Interrupt Request Register 0x1F 8 write-only 0 0xFF CINT Clear Interrupt Request 0 3 write-only CAIR Clear All Interrupt Requests 6 1 write-only 0 Clear only the INT bit specified in the CINT field #0 1 Clear all bits in INT #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 INT Interrupt Request Register 0x24 32 read-write 0 0xFFFFFFFF INT0 Interrupt Request 0 0 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT1 Interrupt Request 1 1 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT2 Interrupt Request 2 2 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT3 Interrupt Request 3 3 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT4 Interrupt Request 4 4 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT5 Interrupt Request 5 5 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT6 Interrupt Request 6 6 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT7 Interrupt Request 7 7 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 ERR Error Register 0x2C 32 read-write 0 0xFFFFFFFF ERR0 Error In Channel 0 0 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR1 Error In Channel 1 1 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR2 Error In Channel 2 2 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR3 Error In Channel 3 3 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR4 Error In Channel 4 4 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR5 Error In Channel 5 5 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR6 Error In Channel 6 6 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR7 Error In Channel 7 7 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 HRS Hardware Request Status Register 0x34 32 read-only 0 0xFFFFFFFF HRS0 Hardware Request Status Channel 0 0 1 read-only 0 A hardware service request for channel 0 is not present #0 1 A hardware service request for channel 0 is present #1 HRS1 Hardware Request Status Channel 1 1 1 read-only 0 A hardware service request for channel 1 is not present #0 1 A hardware service request for channel 1 is present #1 HRS2 Hardware Request Status Channel 2 2 1 read-only 0 A hardware service request for channel 2 is not present #0 1 A hardware service request for channel 2 is present #1 HRS3 Hardware Request Status Channel 3 3 1 read-only 0 A hardware service request for channel 3 is not present #0 1 A hardware service request for channel 3 is present #1 HRS4 Hardware Request Status Channel 4 4 1 read-only 0 A hardware service request for channel 4 is not present #0 1 A hardware service request for channel 4 is present #1 HRS5 Hardware Request Status Channel 5 5 1 read-only 0 A hardware service request for channel 5 is not present #0 1 A hardware service request for channel 5 is present #1 HRS6 Hardware Request Status Channel 6 6 1 read-only 0 A hardware service request for channel 6 is not present #0 1 A hardware service request for channel 6 is present #1 HRS7 Hardware Request Status Channel 7 7 1 read-only 0 A hardware service request for channel 7 is not present #0 1 A hardware service request for channel 7 is present #1 EARS Enable Asynchronous Request in Stop Register 0x44 32 read-write 0 0xFFFFFFFF EDREQ_0 Enable asynchronous DMA request in stop mode for channel 0. 0 1 read-write 0 Disable asynchronous DMA request for channel 0. #0 1 Enable asynchronous DMA request for channel 0. #1 EDREQ_1 Enable asynchronous DMA request in stop mode for channel 1. 1 1 read-write 0 Disable asynchronous DMA request for channel 1 #0 1 Enable asynchronous DMA request for channel 1. #1 EDREQ_2 Enable asynchronous DMA request in stop mode for channel 2. 2 1 read-write 0 Disable asynchronous DMA request for channel 2. #0 1 Enable asynchronous DMA request for channel 2. #1 EDREQ_3 Enable asynchronous DMA request in stop mode for channel 3. 3 1 read-write 0 Disable asynchronous DMA request for channel 3. #0 1 Enable asynchronous DMA request for channel 3. #1 EDREQ_4 Enable asynchronous DMA request in stop mode for channel 4 4 1 read-write 0 Disable asynchronous DMA request for channel 4. #0 1 Enable asynchronous DMA request for channel 4. #1 EDREQ_5 Enable asynchronous DMA request in stop mode for channel 5 5 1 read-write 0 Disable asynchronous DMA request for channel 5. #0 1 Enable asynchronous DMA request for channel 5. #1 EDREQ_6 Enable asynchronous DMA request in stop mode for channel 6 6 1 read-write 0 Disable asynchronous DMA request for channel 6. #0 1 Enable asynchronous DMA request for channel 6. #1 EDREQ_7 Enable asynchronous DMA request in stop mode for channel 7 7 1 read-write 0 Disable asynchronous DMA request for channel 7. #0 1 Enable asynchronous DMA request for channel 7. #1 8 0x1 3,2,1,0,7,6,5,4 DCHPRI%s Channel n Priority Register 0x100 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 3 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 8 0x20 0,1,2,3,4,5,6,7 TCD%s_SADDR TCD Source Address 0x1000 32 read-write 0 0 SADDR Source Address 0 32 read-write 8 0x20 0,1,2,3,4,5,6,7 TCD%s_SOFF TCD Signed Source Address Offset 0x1004 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write 8 0x20 0,1,2,3,4,5,6,7 TCD%s_ATTR TCD Transfer Attributes 0x1006 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 101 32-byte #101 SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 8 0x20 0,1,2,3,4,5,6,7 TCD%s_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write 8 0x20 0,1,2,3,4,5,6,7 TCD%s_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 8 0x20 0,1,2,3,4,5,6,7 TCD%s_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 8 0x20 0,1,2,3,4,5,6,7 TCD%s_SLAST TCD Last Source Address Adjustment 0x100C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write 8 0x20 0,1,2,3,4,5,6,7 TCD%s_DADDR TCD Destination Address 0x1010 32 read-write 0 0 DADDR Destination Address 0 32 read-write 8 0x20 0,1,2,3,4,5,6,7 TCD%s_DOFF TCD Signed Destination Address Offset 0x1014 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write 8 0x20 0,1,2,3,4,5,6,7 TCD%s_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1016 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 8 0x20 0,1,2,3,4,5,6,7 TCD%s_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1016 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 3 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 8 0x20 0,1,2,3,4,5,6,7 TCD%s_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1018 32 read-write 0 0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write 8 0x20 0,1,2,3,4,5,6,7 TCD%s_CSR TCD Control and Status 0x101C 16 read-write 0 0 START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 ACTIVE Channel Active 6 1 read-write DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 3 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 8 0x20 0,1,2,3,4,5,6,7 TCD%s_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x101E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 8 0x20 0,1,2,3,4,5,6,7 TCD%s_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x101E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 3 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 FTFA Flash Memory Interface FTFA_ 0x40020000 0 0x2C registers FTFA 5 FSTAT Flash Status Register 0 8 read-write 0 0xFF MGSTAT0 Memory Controller Command Completion Status Flag 0 1 read-only FPVIOL Flash Protection Violation Flag 4 1 read-write 0 No protection violation detected #0 1 Protection violation detected #1 ACCERR Flash Access Error Flag 5 1 read-write 0 No access error detected #0 1 Access error detected #1 RDCOLERR Flash Read Collision Error Flag 6 1 read-write 0 No collision error detected #0 1 Collision error detected #1 CCIF Command Complete Interrupt Flag 7 1 read-write 0 Flash command in progress #0 1 Flash command has completed #1 FCNFG Flash Configuration Register 0x1 8 read-write 0 0xFF ERSSUSP Erase Suspend 4 1 read-write 0 No suspend requested #0 1 Suspend the current Erase Flash Sector command execution. #1 ERSAREQ Erase All Request 5 1 read-only 0 No request or request complete #0 1 Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state. #1 RDCOLLIE Read Collision Error Interrupt Enable 6 1 read-write 0 Read collision error interrupt disabled #0 1 Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]). #1 CCIE Command Complete Interrupt Enable 7 1 read-write 0 Command complete interrupt disabled #0 1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. #1 FSEC Flash Security Register 0x2 8 read-only 0 0 SEC Flash Security 0 2 read-only 00 MCU security status is secure. #00 01 MCU security status is secure. #01 10 MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.) #10 11 MCU security status is secure. #11 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 00 Freescale factory access granted #00 01 Freescale factory access denied #01 10 Freescale factory access denied #10 11 Freescale factory access granted #11 MEEN Mass Erase Enable 4 2 read-only 00 Mass erase is enabled #00 01 Mass erase is enabled #01 10 Mass erase is disabled #10 11 Mass erase is enabled #11 KEYEN Backdoor Key Security Enable 6 2 read-only 00 Backdoor key access disabled #00 01 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) #01 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 FOPT Flash Option Register 0x3 8 read-only 0 0 OPT Nonvolatile Option 0 8 read-only 12 0x1 3,2,1,0,7,6,5,4,B,A,9,8 FCCOB%s Flash Common Command Object Registers 0x4 8 read-write 0 0xFF CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write 4 0x1 3,2,1,0 FPROT%s Program Flash Protection Registers 0x10 8 read-write 0 0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 8 0x1 H3,H2,H1,H0,L3,L2,L1,L0 XACC%s Execute-only Access Registers 0x18 8 read-only 0 0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 8 0x1 H3,H2,H1,H0,L3,L2,L1,L0 SACC%s Supervisor-only Access Registers 0x20 8 read-only 0 0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 FACSS Flash Access Segment Size Register 0x28 8 read-only 0 0 SGSIZE Segment Size 0 8 read-only FACSN Flash Access Segment Number Register 0x2B 8 read-only 0 0 NUMSG Number of Segments Indicator 0 8 read-only 100000 Program flash memory is divided into 32 segments (64 Kbytes, 128 Kbytes) #100000 101000 Program flash memory is divided into 40 segments (160 Kbytes) #101000 1000000 Program flash memory is divided into 64 segments (256 Kbytes, 512 Kbytes) #1000000 DMAMUX DMA channel multiplexor DMAMUX_ 0x40021000 0 0x8 registers 8 0x1 0,1,2,3,4,5,6,7 CHCFG%s Channel Configuration register 0 8 read-write 0 0xFF SOURCE DMA Channel Source (Slot) 0 6 read-write ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 CAN0 Flex Controller Area Network module CAN0_ 0x40024000 0 0x8C0 registers CAN0 14 MCR Module Configuration Register 0 32 read-write 0xD890000F 0xFFFFFFFF MAXMB Number Of The Last Message Buffer 0 7 read-write IDAM ID Acceptance Mode 8 2 read-write 00 Format A: One full ID (standard and extended) per ID Filter Table element. #00 01 Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. #01 10 Format C: Four partial 8-bit Standard IDs per ID Filter Table element. #10 11 Format D: All frames rejected. #11 AEN Abort Enable 12 1 read-write 0 Abort disabled. #0 1 Abort enabled. #1 LPRIOEN Local Priority Enable 13 1 read-write 0 Local Priority disabled. #0 1 Local Priority enabled. #1 DMA DMA Enable 15 1 read-write 0 DMA feature for RX FIFO disabled. #0 1 DMA feature for RX FIFO enabled. #1 IRMQ Individual Rx Masking And Queue Enable 16 1 read-write 0 Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. #0 1 Individual Rx masking and queue feature are enabled. #1 SRXDIS Self Reception Disable 17 1 read-write 0 Self reception enabled. #0 1 Self reception disabled. #1 DOZE Doze Mode Enable 18 1 read-write 0 FlexCAN is not enabled to enter low-power mode when Doze mode is requested. #0 1 FlexCAN is enabled to enter low-power mode when Doze mode is requested. #1 WAKSRC Wake Up Source 19 1 read-write 0 FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. #0 1 FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. #1 LPMACK Low-Power Mode Acknowledge 20 1 read-only 0 FlexCAN is not in a low-power mode. #0 1 FlexCAN is in a low-power mode. #1 WRNEN Warning Interrupt Enable 21 1 read-write 0 TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. #0 1 TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. #1 SLFWAK Self Wake Up 22 1 read-write 0 FlexCAN Self Wake Up feature is disabled. #0 1 FlexCAN Self Wake Up feature is enabled. #1 SUPV Supervisor Mode 23 1 read-write 0 FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. #0 1 FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location. #1 FRZACK Freeze Mode Acknowledge 24 1 read-only 0 FlexCAN not in Freeze mode, prescaler running. #0 1 FlexCAN in Freeze mode, prescaler stopped. #1 SOFTRST Soft Reset 25 1 read-write 0 No reset request. #0 1 Resets the registers affected by soft reset. #1 WAKMSK Wake Up Interrupt Mask 26 1 read-write 0 Wake Up Interrupt is disabled. #0 1 Wake Up Interrupt is enabled. #1 NOTRDY FlexCAN Not Ready 27 1 read-only 0 FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. #0 1 FlexCAN module is either in Disable mode, Doze mode , Stop mode or Freeze mode. #1 HALT Halt FlexCAN 28 1 read-write 0 No Freeze mode request. #0 1 Enters Freeze mode if the FRZ bit is asserted. #1 RFEN Rx FIFO Enable 29 1 read-write 0 Rx FIFO not enabled. #0 1 Rx FIFO enabled. #1 FRZ Freeze Enable 30 1 read-write 0 Not enabled to enter Freeze mode. #0 1 Enabled to enter Freeze mode. #1 MDIS Module Disable 31 1 read-write 0 Enable the FlexCAN module. #0 1 Disable the FlexCAN module. #1 CTRL1 Control 1 register 0x4 32 read-write 0 0xFFFFFFFF PROPSEG Propagation Segment 0 3 read-write LOM Listen-Only Mode 3 1 read-write 0 Listen-Only mode is deactivated. #0 1 FlexCAN module operates in Listen-Only mode. #1 LBUF Lowest Buffer Transmitted First 4 1 read-write 0 Buffer with highest priority is transmitted first. #0 1 Lowest number buffer is transmitted first. #1 TSYN Timer Sync 5 1 read-write 0 Timer Sync feature disabled #0 1 Timer Sync feature enabled #1 BOFFREC Bus Off Recovery 6 1 read-write 0 Automatic recovering from Bus Off state enabled. #0 1 Automatic recovering from Bus Off state disabled. #1 SMP CAN Bit Sampling 7 1 read-write 0 Just one sample is used to determine the bit value. #0 1 Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used. #1 RWRNMSK Rx Warning Interrupt Mask 10 1 read-write 0 Rx Warning Interrupt disabled. #0 1 Rx Warning Interrupt enabled. #1 TWRNMSK Tx Warning Interrupt Mask 11 1 read-write 0 Tx Warning Interrupt disabled. #0 1 Tx Warning Interrupt enabled. #1 LPB Loop Back Mode 12 1 read-write 0 Loop Back disabled. #0 1 Loop Back enabled. #1 CLKSRC CAN Engine Clock Source 13 1 read-write 0 The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. #0 1 The CAN engine clock source is the peripheral clock. #1 ERRMSK Error Interrupt Mask 14 1 read-write 0 Error interrupt disabled. #0 1 Error interrupt enabled. #1 BOFFMSK Bus Off Interrupt Mask 15 1 read-write 0 Bus Off interrupt disabled. #0 1 Bus Off interrupt enabled. #1 PSEG2 Phase Segment 2 16 3 read-write PSEG1 Phase Segment 1 19 3 read-write RJW Resync Jump Width 22 2 read-write PRESDIV Prescaler Division Factor 24 8 read-write TIMER Free Running Timer 0x8 32 read-write 0 0xFFFFFFFF TIMER Timer Value 0 16 read-write RXMGMASK Rx Mailboxes Global Mask Register 0x10 32 read-write 0 0 MG Rx Mailboxes Global Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RX14MASK Rx 14 Mask register 0x14 32 read-write 0 0 RX14M Rx Buffer 14 Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RX15MASK Rx 15 Mask register 0x18 32 read-write 0 0 RX15M Rx Buffer 15 Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 ECR Error Counter 0x1C 32 read-write 0 0xFFFFFFFF TXERRCNT Transmit Error Counter 0 8 read-write RXERRCNT Receive Error Counter 8 8 read-write ESR1 Error and Status 1 register 0x20 32 read-write 0 0xFFFFFFFF WAKINT Wake-Up Interrupt 0 1 read-write 0 No such occurrence. #0 1 Indicates a recessive to dominant transition was received on the CAN bus. #1 ERRINT Error Interrupt 1 1 read-write 0 No such occurrence. #0 1 Indicates setting of any Error Bit in the Error and Status Register. #1 BOFFINT Bus Off Interrupt 2 1 read-write 0 No such occurrence. #0 1 FlexCAN module entered Bus Off state. #1 RX FlexCAN In Reception 3 1 read-only 0 FlexCAN is not receiving a message. #0 1 FlexCAN is receiving a message. #1 FLTCONF Fault Confinement State 4 2 read-only 00 Error Active #00 01 Error Passive #01 1x Bus Off #1x TX FlexCAN In Transmission 6 1 read-only 0 FlexCAN is not transmitting a message. #0 1 FlexCAN is transmitting a message. #1 IDLE This bit indicates when CAN bus is in IDLE state 7 1 read-only 0 No such occurrence. #0 1 CAN bus is now IDLE. #1 RXWRN Rx Error Warning 8 1 read-only 0 No such occurrence. #0 1 RXERRCNT is greater than or equal to 96. #1 TXWRN TX Error Warning 9 1 read-only 0 No such occurrence. #0 1 TXERRCNT is greater than or equal to 96. #1 STFERR Stuffing Error 10 1 read-only 0 No such occurrence. #0 1 A Stuffing Error occurred since last read of this register. #1 FRMERR Form Error 11 1 read-only 0 No such occurrence. #0 1 A Form Error occurred since last read of this register. #1 CRCERR Cyclic Redundancy Check Error 12 1 read-only 0 No such occurrence. #0 1 A CRC error occurred since last read of this register. #1 ACKERR Acknowledge Error 13 1 read-only 0 No such occurrence. #0 1 An ACK error occurred since last read of this register. #1 BIT0ERR Bit0 Error 14 1 read-only 0 No such occurrence. #0 1 At least one bit sent as dominant is received as recessive. #1 BIT1ERR Bit1 Error 15 1 read-only 0 No such occurrence. #0 1 At least one bit sent as recessive is received as dominant. #1 RWRNINT Rx Warning Interrupt Flag 16 1 read-write 0 No such occurrence. #0 1 The Rx error counter transitioned from less than 96 to greater than or equal to 96. #1 TWRNINT Tx Warning Interrupt Flag 17 1 read-write 0 No such occurrence. #0 1 The Tx error counter transitioned from less than 96 to greater than or equal to 96. #1 SYNCH CAN Synchronization Status 18 1 read-only 0 FlexCAN is not synchronized to the CAN bus. #0 1 FlexCAN is synchronized to the CAN bus. #1 BOFFDONEINT Bus Off Done Interrupt 19 1 read-write 0 No such occurrence. #0 1 FlexCAN module has completed Bus Off process. #1 ERROVR Error Overrun bit 21 1 read-write 0 Overrun has not occurred. #0 1 Overrun has occured. #1 IMASK1 Interrupt Masks 1 register 0x28 32 read-write 0 0xFFFFFFFF BUF31TO0M Buffer MB i Mask 0 32 read-write 0 The corresponding buffer Interrupt is disabled. #0 1 The corresponding buffer Interrupt is enabled. #1 IFLAG1 Interrupt Flags 1 register 0x30 32 read-write 0 0xFFFFFFFF BUF0I Buffer MB0 Interrupt Or Clear FIFO bit 0 1 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. #0 1 The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. #1 BUF4TO1I Buffer MB i Interrupt Or "reserved" 1 4 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. #0000 1 The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. #0001 BUF5I Buffer MB5 Interrupt Or "Frames available in Rx FIFO" 5 1 read-write 0 No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 #0 1 MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled. #1 BUF6I Buffer MB6 Interrupt Or "Rx FIFO Warning" 6 1 read-write 0 No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 #0 1 MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1 #1 BUF7I Buffer MB7 Interrupt Or "Rx FIFO Overflow" 7 1 read-write 0 No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 #0 1 MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1 #1 BUF31TO8I Buffer MBi Interrupt 8 24 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception. #0 1 The corresponding buffer has successfully completed transmission or reception. #1 CTRL2 Control 2 register 0x34 32 read-write 0xB00000 0xFFFFFFFF EACEN Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 16 1 read-write 0 Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. #0 1 Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. #1 RRS Remote Request Storing 17 1 read-write 0 Remote Response Frame is generated. #0 1 Remote Request Frame is stored. #1 MRP Mailboxes Reception Priority 18 1 read-write 0 Matching starts from Rx FIFO and continues on Mailboxes. #0 1 Matching starts from Mailboxes and continues on Rx FIFO. #1 TASD Tx Arbitration Start Delay 19 5 read-write RFFN Number Of Rx FIFO Filters 24 4 read-write BOFFDONEMSK Bus Off Done Interrupt Mask 30 1 read-write 0 Bus Off Done interrupt disabled. #0 1 Bus Off Done interrupt enabled. #1 ESR2 Error and Status 2 register 0x38 32 read-only 0 0xFFFFFFFF IMB Inactive Mailbox 13 1 read-only 0 If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. #0 1 If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. #1 VPS Valid Priority Status 14 1 read-only 0 Contents of IMB and LPTM are invalid. #0 1 Contents of IMB and LPTM are valid. #1 LPTM Lowest Priority Tx Mailbox 16 7 read-only CRCR CRC Register 0x44 32 read-only 0 0xFFFFFFFF TXCRC Transmitted CRC value 0 15 read-only MBCRC CRC Mailbox 16 7 read-only RXFGMASK Rx FIFO Global Mask register 0x48 32 read-write 0 0 FGM Rx FIFO Global Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXFIR Rx FIFO Information Register 0x4C 32 read-only 0 0 IDHIT Identifier Acceptance Filter Hit Indicator 0 9 read-only CBT CAN Bit Timing Register 0x50 32 read-write 0 0xFFFFFFFF EPSEG2 Extended Phase Segment 2 0 5 read-write EPSEG1 Extended Phase Segment 1 5 5 read-write EPROPSEG Extended Propagation Segment 10 6 read-write ERJW Extended Resync Jump Width 16 4 read-write EPRESDIV Extended Prescaler Division Factor 21 10 read-write BTF Bit Timing Format Enable 31 1 read-write 0 Extended bit time definitions disabled. #0 1 Extended bit time definitions enabled. #1 CS0 Message Buffer 0 CS Register 0x80 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ID0 Message Buffer 0 ID Register 0x84 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD00 Message Buffer 0 WORD0 Register 0x88 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD10 Message Buffer 0 WORD1 Register 0x8C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS1 Message Buffer 1 CS Register 0x90 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ID1 Message Buffer 1 ID Register 0x94 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD01 Message Buffer 1 WORD0 Register 0x98 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD11 Message Buffer 1 WORD1 Register 0x9C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS2 Message Buffer 2 CS Register 0xA0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ID2 Message Buffer 2 ID Register 0xA4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD02 Message Buffer 2 WORD0 Register 0xA8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD12 Message Buffer 2 WORD1 Register 0xAC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS3 Message Buffer 3 CS Register 0xB0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ID3 Message Buffer 3 ID Register 0xB4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD03 Message Buffer 3 WORD0 Register 0xB8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD13 Message Buffer 3 WORD1 Register 0xBC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS4 Message Buffer 4 CS Register 0xC0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ID4 Message Buffer 4 ID Register 0xC4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD04 Message Buffer 4 WORD0 Register 0xC8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD14 Message Buffer 4 WORD1 Register 0xCC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS5 Message Buffer 5 CS Register 0xD0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ID5 Message Buffer 5 ID Register 0xD4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD05 Message Buffer 5 WORD0 Register 0xD8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD15 Message Buffer 5 WORD1 Register 0xDC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS6 Message Buffer 6 CS Register 0xE0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ID6 Message Buffer 6 ID Register 0xE4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD06 Message Buffer 6 WORD0 Register 0xE8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD16 Message Buffer 6 WORD1 Register 0xEC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS7 Message Buffer 7 CS Register 0xF0 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ID7 Message Buffer 7 ID Register 0xF4 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD07 Message Buffer 7 WORD0 Register 0xF8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD17 Message Buffer 7 WORD1 Register 0xFC 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS8 Message Buffer 8 CS Register 0x100 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ID8 Message Buffer 8 ID Register 0x104 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD08 Message Buffer 8 WORD0 Register 0x108 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD18 Message Buffer 8 WORD1 Register 0x10C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS9 Message Buffer 9 CS Register 0x110 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ID9 Message Buffer 9 ID Register 0x114 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD09 Message Buffer 9 WORD0 Register 0x118 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD19 Message Buffer 9 WORD1 Register 0x11C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS10 Message Buffer 10 CS Register 0x120 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ID10 Message Buffer 10 ID Register 0x124 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD010 Message Buffer 10 WORD0 Register 0x128 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD110 Message Buffer 10 WORD1 Register 0x12C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS11 Message Buffer 11 CS Register 0x130 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ID11 Message Buffer 11 ID Register 0x134 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD011 Message Buffer 11 WORD0 Register 0x138 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD111 Message Buffer 11 WORD1 Register 0x13C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS12 Message Buffer 12 CS Register 0x140 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ID12 Message Buffer 12 ID Register 0x144 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD012 Message Buffer 12 WORD0 Register 0x148 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD112 Message Buffer 12 WORD1 Register 0x14C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS13 Message Buffer 13 CS Register 0x150 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ID13 Message Buffer 13 ID Register 0x154 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD013 Message Buffer 13 WORD0 Register 0x158 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD113 Message Buffer 13 WORD1 Register 0x15C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS14 Message Buffer 14 CS Register 0x160 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ID14 Message Buffer 14 ID Register 0x164 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD014 Message Buffer 14 WORD0 Register 0x168 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD114 Message Buffer 14 WORD1 Register 0x16C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write CS15 Message Buffer 15 CS Register 0x170 32 read-write 0 0xFFFFFFFF TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write CODE Reserved 24 4 read-write ID15 Message Buffer 15 ID Register 0x174 32 read-write 0 0xFFFFFFFF EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write WORD015 Message Buffer 15 WORD0 Register 0x178 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write WORD115 Message Buffer 15 WORD1 Register 0x17C 32 read-write 0 0xFFFFFFFF DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write 16 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 RXIMR%s Rx Individual Mask Registers 0x880 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 FTM0 FlexTimer Module FTM FTM0_ 0x40038000 0 0x9C registers FTM0 17 SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD Modulo Value 0 16 read-write 6 0x8 0,1,2,3,4,5 C%sSC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 6 0x8 0,1,2,3,4,5 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT Initial Value Of The FTM Counter 0 16 read-write STATUS Capture And Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write 0 TPM compatibility. Free running counter and synchronization compatible with TPM. #0 1 Free running counter and synchronization are different from TPM behavior. #1 INIT Initialize The Channels Output 1 1 read-write WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 DEADTIME Deadtime Insertion Control 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF NUMTOF TOF Frequency 0 5 read-write BDMMODE BDM Mode 6 2 read-write GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 SWRSTCNT FTM counter synchronization is activated by the software trigger. 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWWRBUF MOD, CNTIN, and CV registers synchronization is activated by the software trigger. 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOM Output mask synchronization is activated by the software trigger. 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWINVC Inverting control synchronization is activated by the software trigger. 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWSOC Software output control synchronization is activated by the software trigger. 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 HWRSTCNT FTM counter synchronization is activated by a hardware trigger. 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWWRBUF MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger. 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 HWOM Output mask synchronization is activated by a hardware trigger. 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWINVC Inverting control synchronization is activated by a hardware trigger. 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWSOC Software output control synchronization is activated by a hardware trigger. 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 FTM1 FlexTimer Module FTM FTM1_ 0x40039000 0 0x9C registers FTM1 18 SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD Modulo Value 0 16 read-write 2 0x8 0,1 C%sSC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 2 0x8 0,1 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT Initial Value Of The FTM Counter 0 16 read-write STATUS Capture And Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write 0 TPM compatibility. Free running counter and synchronization compatible with TPM. #0 1 Free running counter and synchronization are different from TPM behavior. #1 INIT Initialize The Channels Output 1 1 read-write WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 DEADTIME Deadtime Insertion Control 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF NUMTOF TOF Frequency 0 5 read-write BDMMODE BDM Mode 6 2 read-write GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 SWRSTCNT FTM counter synchronization is activated by the software trigger. 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWWRBUF MOD, CNTIN, and CV registers synchronization is activated by the software trigger. 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOM Output mask synchronization is activated by the software trigger. 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWINVC Inverting control synchronization is activated by the software trigger. 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWSOC Software output control synchronization is activated by the software trigger. 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 HWRSTCNT FTM counter synchronization is activated by a hardware trigger. 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWWRBUF MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger. 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 HWOM Output mask synchronization is activated by a hardware trigger. 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWINVC Inverting control synchronization is activated by a hardware trigger. 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWSOC Software output control synchronization is activated by a hardware trigger. 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 FTM2 FlexTimer Module FTM FTM2_ 0x4003A000 0 0x9C registers FTM2 19 SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD Modulo Value 0 16 read-write 2 0x8 0,1 C%sSC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 2 0x8 0,1 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT Initial Value Of The FTM Counter 0 16 read-write STATUS Capture And Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write 0 TPM compatibility. Free running counter and synchronization compatible with TPM. #0 1 Free running counter and synchronization are different from TPM behavior. #1 INIT Initialize The Channels Output 1 1 read-write WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 DEADTIME Deadtime Insertion Control 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF NUMTOF TOF Frequency 0 5 read-write BDMMODE BDM Mode 6 2 read-write GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 SWRSTCNT FTM counter synchronization is activated by the software trigger. 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWWRBUF MOD, CNTIN, and CV registers synchronization is activated by the software trigger. 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOM Output mask synchronization is activated by the software trigger. 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWINVC Inverting control synchronization is activated by the software trigger. 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWSOC Software output control synchronization is activated by the software trigger. 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 HWRSTCNT FTM counter synchronization is activated by a hardware trigger. 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWWRBUF MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger. 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 HWOM Output mask synchronization is activated by a hardware trigger. 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWINVC Inverting control synchronization is activated by a hardware trigger. 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWSOC Software output control synchronization is activated by a hardware trigger. 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 FTM3 FlexTimer Module FTM FTM3_ 0x40026000 0 0x9C registers FTM3 22 SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD Modulo Value 0 16 read-write 6 0x8 0,1,2,3,4,5 C%sSC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 6 0x8 0,1,2,3,4,5 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT Initial Value Of The FTM Counter 0 16 read-write STATUS Capture And Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write 0 TPM compatibility. Free running counter and synchronization compatible with TPM. #0 1 Free running counter and synchronization are different from TPM behavior. #1 INIT Initialize The Channels Output 1 1 read-write WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 DEADTIME Deadtime Insertion Control 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF NUMTOF TOF Frequency 0 5 read-write BDMMODE BDM Mode 6 2 read-write GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 SWRSTCNT FTM counter synchronization is activated by the software trigger. 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWWRBUF MOD, CNTIN, and CV registers synchronization is activated by the software trigger. 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOM Output mask synchronization is activated by the software trigger. 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWINVC Inverting control synchronization is activated by the software trigger. 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWSOC Software output control synchronization is activated by the software trigger. 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 HWRSTCNT FTM counter synchronization is activated by a hardware trigger. 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWWRBUF MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger. 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 HWOM Output mask synchronization is activated by a hardware trigger. 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWINVC Inverting control synchronization is activated by a hardware trigger. 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWSOC Software output control synchronization is activated by a hardware trigger. 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 FTM4 FlexTimer Module FTM FTM4_ 0x40027000 0 0x9C registers FTM4 24 SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD Modulo Value 0 16 read-write 2 0x8 0,1 C%sSC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 2 0x8 0,1 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT Initial Value Of The FTM Counter 0 16 read-write STATUS Capture And Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write 0 TPM compatibility. Free running counter and synchronization compatible with TPM. #0 1 Free running counter and synchronization are different from TPM behavior. #1 INIT Initialize The Channels Output 1 1 read-write WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 DEADTIME Deadtime Insertion Control 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF NUMTOF TOF Frequency 0 5 read-write BDMMODE BDM Mode 6 2 read-write GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 SWRSTCNT FTM counter synchronization is activated by the software trigger. 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWWRBUF MOD, CNTIN, and CV registers synchronization is activated by the software trigger. 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOM Output mask synchronization is activated by the software trigger. 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWINVC Inverting control synchronization is activated by the software trigger. 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWSOC Software output control synchronization is activated by the software trigger. 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 HWRSTCNT FTM counter synchronization is activated by a hardware trigger. 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWWRBUF MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger. 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 HWOM Output mask synchronization is activated by a hardware trigger. 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWINVC Inverting control synchronization is activated by a hardware trigger. 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWSOC Software output control synchronization is activated by a hardware trigger. 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 FTM5 FlexTimer Module FTM FTM5_ 0x40028000 0 0x9C registers FTM5 26 SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD Modulo Value 0 16 read-write 2 0x8 0,1 C%sSC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 2 0x8 0,1 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT Initial Value Of The FTM Counter 0 16 read-write STATUS Capture And Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write 0 TPM compatibility. Free running counter and synchronization compatible with TPM. #0 1 Free running counter and synchronization are different from TPM behavior. #1 INIT Initialize The Channels Output 1 1 read-write WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 DEADTIME Deadtime Insertion Control 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF NUMTOF TOF Frequency 0 5 read-write BDMMODE BDM Mode 6 2 read-write GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 SWRSTCNT FTM counter synchronization is activated by the software trigger. 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWWRBUF MOD, CNTIN, and CV registers synchronization is activated by the software trigger. 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOM Output mask synchronization is activated by the software trigger. 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWINVC Inverting control synchronization is activated by the software trigger. 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWSOC Software output control synchronization is activated by the software trigger. 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 HWRSTCNT FTM counter synchronization is activated by a hardware trigger. 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWWRBUF MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger. 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 HWOM Output mask synchronization is activated by a hardware trigger. 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWINVC Inverting control synchronization is activated by a hardware trigger. 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWSOC Software output control synchronization is activated by a hardware trigger. 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 SPI0 Serial Peripheral Interface SPI0_ 0x4002C000 0 0x140 registers SPI0 10 MCR Module Configuration Register 0 32 read-write 0x4001 0xFFFFFFFF HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 SMPL_PT Sample Point 8 2 read-write 00 0 protocol clock cycles between SCK edge and SIN sample #00 01 1 protocol clock cycle between SCK edge and SIN sample #01 10 2 protocol clock cycles between SCK edge and SIN sample #10 CLR_RXF CLR_RXF 10 1 write-only 0 Do not clear the RX FIFO counter. #0 1 Clear the RX FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the TX FIFO counter. #0 1 Clear the TX FIFO counter. #1 DIS_RXF Disable Receive FIFO 12 1 read-write 0 RX FIFO is enabled. #0 1 RX FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 TX FIFO is enabled. #0 1 TX FIFO is disabled. #1 MDIS Module Disable 14 1 read-write 0 Enables the module clocks. #0 1 Allows external logic to disable the module clocks. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on the module. #0 1 Doze mode disables the module. #1 PCSIS Peripheral Chip Select x Inactive State 16 5 read-write 0 The inactive state of PCSx is low. #00000 1 The inactive state of PCSx is high. #00001 ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 MTFE Modified Transfer Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in Debug mode. #0 1 Halt serial transfers in Debug mode. #1 DCONF SPI Configuration. 28 2 read-only 00 SPI #00 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 Enables Slave mode #0 1 Enables Master mode #1 TCR Transfer Count Register 0x8 32 read-write 0 0xFFFFFFFF SPI_TCNT SPI Transfer Counter 16 16 read-write 2 0x4 0,1 CTAR%s Clock and Transfer Attributes Register (In Master Mode) SPI0 0xC 32 read-write 0x78000000 0xFFFFFFFF BR Baud Rate Scaler 0 4 read-write DT Delay After Transfer Scaler 4 4 read-write ASC After SCK Delay Scaler 8 4 read-write CSSCK PCS to SCK Delay Scaler 12 4 read-write PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 CTAR_SLAVE Clock and Transfer Attributes Register (In Slave Mode) SPI0 0xC 32 read-write 0x78000000 0xFFFFFFFF CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write SR Status Register 0x2C 32 read-write 0x2000000 0xFFFFFFFF POPNXTPTR Pop Next Pointer 0 4 read-only RXCTR RX FIFO Counter 4 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXCTR TX FIFO Counter 12 4 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 RX FIFO is empty. #0 1 RX FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 TX FIFO is full. #0 1 TX FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No TX FIFO underflow. #0 1 TX FIFO underflow has occurred. #1 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 TXRXS TX and RX Status 30 1 read-write 0 Transmit and receive operations are disabled (The module is in Stopped state). #0 1 Transmit and receive operations are enabled (The module is in Running state). #1 TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 RSER DMA/Interrupt Request Select and Enable Register 0x30 32 read-write 0 0xFFFFFFFF RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled. #0 1 RFDF interrupt or DMA requests are enabled. #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 EOQF_RE Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 PUSHR PUSH TX FIFO Register In Master Mode SPI0 0x34 32 read-write 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-write PCS Select which PCS signals are to be asserted for the transfer 16 5 read-write 0 Negate the PCS[x] signal. #00000 1 Assert the PCS[x] signal. #00001 CTCNT Clear Transfer Counter 26 1 read-write 0 Do not clear the TCR[TCNT] field. #0 1 Clear the TCR[TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 CTAS Clock and Transfer Attributes Select 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 PUSHR_SLAVE PUSH TX FIFO Register In Slave Mode SPI0 0x34 32 read-write 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-write POPR POP RX FIFO Register 0x38 32 read-only 0 0xFFFFFFFF RXDATA Received Data 0 32 read-only 4 0x4 0,1,2,3 TXFR%s Transmit FIFO Registers 0x3C 32 read-only 0 0xFFFFFFFF TXDATA Transmit Data 0 16 read-only TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only 4 0x4 0,1,2,3 RXFR%s Receive FIFO Registers 0x7C 32 read-only 0 0xFFFFFFFF RXDATA Receive Data 0 32 read-only SREX Status Register Extended 0x13C 32 read-only 0 0xFFFFFFFF CMDNXTPTR Command Next Pointer 0 4 read-only CMDCTR CMD FIFO Counter 4 5 read-only TXCTR4 TX FIFO Counter[4] 11 1 read-only RXCTR4 RX FIFO Counter[4] 14 1 read-only PDB0 Programmable Delay Block PDB PDB0_ 0x40036000 0 0x19C registers PDB0_PDB1 29 SC Status and Control register 0 32 read-write 0 0xFFFFFFFF LDOK Load OK 0 1 read-write CONT Continuous Mode Enable 1 1 read-write 0 PDB operation in One-Shot mode #0 1 PDB operation in Continuous mode #1 MULT Multiplication Factor Select for Prescaler 2 2 read-write 00 Multiplication factor is 1. #00 01 Multiplication factor is 10. #01 10 Multiplication factor is 20. #10 11 Multiplication factor is 40. #11 PDBIE PDB Interrupt Enable 5 1 read-write 0 PDB interrupt disabled. #0 1 PDB interrupt enabled. #1 PDBIF PDB Interrupt Flag 6 1 read-write PDBEN PDB Enable 7 1 read-write 0 PDB disabled. Counter is off. #0 1 PDB enabled. #1 TRGSEL Trigger Input Source Select 8 4 read-write 0000 Trigger-In 0 is selected. #0000 0001 Trigger-In 1 is selected. #0001 0010 Trigger-In 2 is selected. #0010 0011 Trigger-In 3 is selected. #0011 0100 Trigger-In 4 is selected. #0100 0101 Trigger-In 5 is selected. #0101 0110 Trigger-In 6 is selected. #0110 0111 Trigger-In 7 is selected. #0111 1000 Trigger-In 8 is selected. #1000 1001 Trigger-In 9 is selected. #1001 1010 Trigger-In 10 is selected. #1010 1011 Trigger-In 11 is selected. #1011 1100 Trigger-In 12 is selected. #1100 1101 Trigger-In 13 is selected. #1101 1110 Trigger-In 14 is selected. #1110 1111 Software trigger is selected. #1111 PRESCALER Prescaler Divider Select 12 3 read-write 000 Counting uses the peripheral clock divided by multiplication factor selected by MULT. #000 001 Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT. #001 010 Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT. #010 011 Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT. #011 100 Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT. #100 101 Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT. #101 110 Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT. #110 111 Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT. #111 DMAEN DMA Enable 15 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 SWTRIG Software Trigger 16 1 write-only PDBEIE PDB Sequence Error Interrupt Enable 17 1 read-write 0 PDB sequence error interrupt disabled. #0 1 PDB sequence error interrupt enabled. #1 LDMOD Load Mode Select 18 2 read-write 00 The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK. #00 01 The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK. #01 10 The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK. #10 11 The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK. #11 MOD Modulus register 0x4 32 read-write 0xFFFF 0xFFFFFFFF MOD PDB Modulus 0 16 read-write CNT Counter register 0x8 32 read-only 0 0xFFFFFFFF CNT PDB Counter 0 16 read-only IDLY Interrupt Delay register 0xC 32 read-write 0xFFFF 0xFFFFFFFF IDLY PDB Interrupt Delay 0 16 read-write 2 0x28 0,1 CH%sC1 Channel n Control register 1 0x10 32 read-write 0 0xFFFFFFFF EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 BB PDB Channel Pre-Trigger Back-to-Back Operation Enable 16 8 read-write 0 PDB channel's corresponding pre-trigger back-to-back operation disabled. #0 1 PDB channel's corresponding pre-trigger back-to-back operation enabled. #1 2 0x28 0,1 CH%sS Channel n Status register 0x14 32 read-write 0 0xFFFFFFFF ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. #1 CF PDB Channel Flags 16 8 read-write 2 0x28 0,1 CH%sDLY0 Channel n Delay 0 register 0x18 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write 2 0x28 0,1 CH%sDLY1 Channel n Delay 1 register 0x1C 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write DACINTC DAC Interval Trigger n Control register 0x150 32 read-write 0 0xFFFFFFFF TOE DAC Interval Trigger Enable 0 1 read-write 0 DAC interval trigger disabled. #0 1 DAC interval trigger enabled. #1 EXT DAC External Trigger Input Enable 1 1 read-write 0 DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger. #1 DACINT DAC Interval n register 0x154 32 read-write 0 0xFFFFFFFF INT DAC Interval 0 16 read-write POEN Pulse-Out n Enable register 0x190 32 read-write 0 0xFFFFFFFF POEN PDB Pulse-Out Enable 0 8 read-write 0 PDB Pulse-Out disabled #0 1 PDB Pulse-Out enabled #1 2 0x4 0,1 PO%sDLY Pulse-Out n Delay register 0x194 32 read-write 0 0xFFFFFFFF DLY2 PDB Pulse-Out Delay 2 0 16 read-write DLY1 PDB Pulse-Out Delay 1 16 16 read-write PDB1 Programmable Delay Block PDB PDB1_ 0x40031000 0 0x19C registers PDB0_PDB1 29 SC Status and Control register 0 32 read-write 0 0xFFFFFFFF LDOK Load OK 0 1 read-write CONT Continuous Mode Enable 1 1 read-write 0 PDB operation in One-Shot mode #0 1 PDB operation in Continuous mode #1 MULT Multiplication Factor Select for Prescaler 2 2 read-write 00 Multiplication factor is 1. #00 01 Multiplication factor is 10. #01 10 Multiplication factor is 20. #10 11 Multiplication factor is 40. #11 PDBIE PDB Interrupt Enable 5 1 read-write 0 PDB interrupt disabled. #0 1 PDB interrupt enabled. #1 PDBIF PDB Interrupt Flag 6 1 read-write PDBEN PDB Enable 7 1 read-write 0 PDB disabled. Counter is off. #0 1 PDB enabled. #1 TRGSEL Trigger Input Source Select 8 4 read-write 0000 Trigger-In 0 is selected. #0000 0001 Trigger-In 1 is selected. #0001 0010 Trigger-In 2 is selected. #0010 0011 Trigger-In 3 is selected. #0011 0100 Trigger-In 4 is selected. #0100 0101 Trigger-In 5 is selected. #0101 0110 Trigger-In 6 is selected. #0110 0111 Trigger-In 7 is selected. #0111 1000 Trigger-In 8 is selected. #1000 1001 Trigger-In 9 is selected. #1001 1010 Trigger-In 10 is selected. #1010 1011 Trigger-In 11 is selected. #1011 1100 Trigger-In 12 is selected. #1100 1101 Trigger-In 13 is selected. #1101 1110 Trigger-In 14 is selected. #1110 1111 Software trigger is selected. #1111 PRESCALER Prescaler Divider Select 12 3 read-write 000 Counting uses the peripheral clock divided by multiplication factor selected by MULT. #000 001 Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT. #001 010 Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT. #010 011 Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT. #011 100 Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT. #100 101 Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT. #101 110 Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT. #110 111 Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT. #111 DMAEN DMA Enable 15 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 SWTRIG Software Trigger 16 1 write-only PDBEIE PDB Sequence Error Interrupt Enable 17 1 read-write 0 PDB sequence error interrupt disabled. #0 1 PDB sequence error interrupt enabled. #1 LDMOD Load Mode Select 18 2 read-write 00 The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK. #00 01 The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK. #01 10 The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK. #10 11 The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK. #11 MOD Modulus register 0x4 32 read-write 0xFFFF 0xFFFFFFFF MOD PDB Modulus 0 16 read-write CNT Counter register 0x8 32 read-only 0 0xFFFFFFFF CNT PDB Counter 0 16 read-only IDLY Interrupt Delay register 0xC 32 read-write 0xFFFF 0xFFFFFFFF IDLY PDB Interrupt Delay 0 16 read-write 2 0x28 0,1 CH%sC1 Channel n Control register 1 0x10 32 read-write 0 0xFFFFFFFF EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 BB PDB Channel Pre-Trigger Back-to-Back Operation Enable 16 8 read-write 0 PDB channel's corresponding pre-trigger back-to-back operation disabled. #0 1 PDB channel's corresponding pre-trigger back-to-back operation enabled. #1 2 0x28 0,1 CH%sS Channel n Status register 0x14 32 read-write 0 0xFFFFFFFF ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. #1 CF PDB Channel Flags 16 8 read-write 2 0x28 0,1 CH%sDLY0 Channel n Delay 0 register 0x18 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write 2 0x28 0,1 CH%sDLY1 Channel n Delay 1 register 0x1C 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write DACINTC DAC Interval Trigger n Control register 0x150 32 read-write 0 0xFFFFFFFF TOE DAC Interval Trigger Enable 0 1 read-write 0 DAC interval trigger disabled. #0 1 DAC interval trigger enabled. #1 EXT DAC External Trigger Input Enable 1 1 read-write 0 DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger. #1 DACINT DAC Interval n register 0x154 32 read-write 0 0xFFFFFFFF INT DAC Interval 0 16 read-write POEN Pulse-Out n Enable register 0x190 32 read-write 0 0xFFFFFFFF POEN PDB Pulse-Out Enable 0 8 read-write 0 PDB Pulse-Out disabled #0 1 PDB Pulse-Out enabled #1 2 0x4 0,1 PO%sDLY Pulse-Out n Delay register 0x194 32 read-write 0 0xFFFFFFFF DLY2 PDB Pulse-Out Delay 2 0 16 read-write DLY1 PDB Pulse-Out Delay 1 16 16 read-write CRC Cyclic Redundancy Check CRC_ 0x40032000 0 0xC registers DATA CRC Data register CRC 0 32 read-write 0xFFFFFFFF 0xFFFFFFFF LL CRC Low Lower Byte 0 8 read-write LU CRC Low Upper Byte 8 8 read-write HL CRC High Lower Byte 16 8 read-write HU CRC High Upper Byte 24 8 read-write DATAL CRC_DATAL register. CRC 0 16 read-write 0xFFFF 0xFFFF DATAL DATAL stores the lower 16 bits of the 16/32 bit CRC 0 16 read-write DATALL CRC_DATALL register. CRC 0 8 read-write 0xFF 0xFF DATALL CRCLL stores the first 8 bits of the 32 bit DATA 0 8 read-write DATALU CRC_DATALU register. 0x1 8 read-write 0xFF 0xFF DATALU DATALL stores the second 8 bits of the 32 bit CRC 0 8 read-write DATAH CRC_DATAH register. CRC 0x2 16 read-write 0xFFFF 0xFFFF DATAH DATAH stores the high 16 bits of the 16/32 bit CRC 0 16 read-write DATAHL CRC_DATAHL register. CRC 0x2 8 read-write 0xFF 0xFF DATAHL DATAHL stores the third 8 bits of the 32 bit CRC 0 8 read-write DATAHU CRC_DATAHU register. 0x3 8 read-write 0xFF 0xFF DATAHU DATAHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write GPOLY CRC Polynomial register CRC 0x4 32 read-write 0x1021 0xFFFFFFFF LOW Low Polynominal Half-word 0 16 read-write HIGH High Polynominal Half-word 16 16 read-write GPOLYL CRC_GPOLYL register. CRC 0x4 16 read-write 0xFFFF 0xFFFF GPOLYL POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value 0 16 read-write GPOLYLL CRC_GPOLYLL register. CRC 0x4 8 read-write 0xFF 0xFF GPOLYLL POLYLL stores the first 8 bits of the 32 bit CRC 0 8 read-write GPOLYLU CRC_GPOLYLU register. 0x5 8 read-write 0xFF 0xFF GPOLYLU POLYLL stores the second 8 bits of the 32 bit CRC 0 8 read-write GPOLYH CRC_GPOLYH register. CRC 0x6 16 read-write 0xFFFF 0xFFFF GPOLYH POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value 0 16 read-write GPOLYHL CRC_GPOLYHL register. CRC 0x6 8 read-write 0xFF 0xFF GPOLYHL POLYHL stores the third 8 bits of the 32 bit CRC 0 8 read-write GPOLYHU CRC_GPOLYHU register. 0x7 8 read-write 0xFF 0xFF GPOLYHU POLYHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write CTRL CRC Control register 0x8 32 read-write 0 0xFFFFFFFF TCRC Width of CRC protocol. 24 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 WAS Write CRC Data Register As Seed 25 1 read-write 0 Writes to the CRC data register are data values. #0 1 Writes to the CRC data register are seed values. #1 FXOR Complement Read Of CRC Data Register 26 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of the CRC Data register. #1 TOTR Type Of Transpose For Read 28 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOT Type Of Transpose For Writes 30 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 CTRLHU CRC_CTRLHU register. 0xB 8 read-write 0 0xFF TCRC no description available 0 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 WAS no description available 1 1 read-write 0 Writes to CRC data register are data values. #0 1 Writes to CRC data reguster are seed values. #1 FXOR no description available 2 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of CRC data register. #1 TOTR no description available 4 2 read-write 00 No Transposition. #00 01 Bits in bytes are transposed, bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOT no description available 6 2 read-write 00 No Transposition. #00 01 Bits in bytes are transposed, bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 ADC0 Analog-to-Digital Converter ADC ADC0_ 0x4003B000 0 0x70 registers ADC0 15 2 0x4 A,B SC1%s ADC Status and Control Registers 1 0 32 read-write 0x1F 0xFFFFFFFF ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11010 When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11101 When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. #11101 11110 When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. #11110 11111 Module is disabled. #11111 DIFF Differential Mode Enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 AIEN Interrupt Enable 6 1 read-write 0 Conversion complete interrupt is disabled. #0 1 Conversion complete interrupt is enabled. #1 COCO Conversion Complete Flag 7 1 read-only 0 Conversion is not completed. #0 1 Conversion is completed. #1 CFG1 ADC Configuration Register 1 0x8 32 read-write 0 0xFFFFFFFF ADICLK Input Clock Select 0 2 read-write 00 Bus clock #00 01 Bus clock divided by 2(BUSCLK/2) #01 10 Alternate clock (ALTCLK) #10 11 Asynchronous clock (ADACK) #11 MODE Conversion mode selection 2 2 read-write 00 When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. #00 01 When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output. #01 10 When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output #10 11 When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output #11 ADLSMP Sample Time Configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 ADIV Clock Divide Select 5 2 read-write 00 The divide ratio is 1 and the clock rate is input clock. #00 01 The divide ratio is 2 and the clock rate is (input clock)/2. #01 10 The divide ratio is 4 and the clock rate is (input clock)/4. #10 11 The divide ratio is 8 and the clock rate is (input clock)/8. #11 ADLPC Low-Power Configuration 7 1 read-write 0 Normal power configuration. #0 1 Low-power configuration. The power is reduced at the expense of maximum clock speed. #1 CFG2 ADC Configuration Register 2 0xC 32 read-write 0 0xFFFFFFFF ADLSTS Long Sample Time Select 0 2 read-write 00 Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. #00 01 12 extra ADCK cycles; 16 ADCK cycles total sample time. #01 10 6 extra ADCK cycles; 10 ADCK cycles total sample time. #10 11 2 extra ADCK cycles; 6 ADCK cycles total sample time. #11 ADHSC High-Speed Configuration 2 1 read-write 0 Normal conversion sequence selected. #0 1 High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. #1 ADACKEN Asynchronous Clock Output Enable 3 1 read-write 0 Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. #0 1 Asynchronous clock and clock output is enabled regardless of the state of the ADC. #1 2 0x4 A,B R%s ADC Data Result Register 0x10 32 read-only 0 0xFFFFFFFF D Data result 0 16 read-only 2 0x4 1,2 CV%s Compare Value Registers 0x18 32 read-write 0 0xFFFFFFFF CV Compare Value. 0 16 read-write SC2 Status and Control Register 2 0x20 32 read-write 0 0xFFFFFFFF REFSEL Voltage Reference Selection 0 2 read-write 00 Default voltage reference pin pair, that is, external pins VREFH and VREFL #00 01 Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU #01 DMAEN DMA Enable 2 1 read-write 0 DMA is disabled. #0 1 DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted. #1 ACREN Compare Function Range Enable 3 1 read-write 0 Range function disabled. Only CV1 is compared. #0 1 Range function enabled. Both CV1 and CV2 are compared. #1 ACFGT Compare Function Greater Than Enable 4 1 read-write 0 Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. #0 1 Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2. #1 ACFE Compare Function Enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ADTRG Conversion Trigger Select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 ADACT Conversion Active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 SC3 Status and Control Register 3 0x24 32 read-write 0 0xFFFFFFFF AVGS Hardware Average Select 0 2 read-write 00 4 samples averaged. #00 01 8 samples averaged. #01 10 16 samples averaged. #10 11 32 samples averaged. #11 AVGE Hardware Average Enable 2 1 read-write 0 Hardware average function disabled. #0 1 Hardware average function enabled. #1 ADCO Continuous Conversion Enable 3 1 read-write 0 One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. #0 1 Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. #1 CALF Calibration Failed Flag 6 1 read-write 0 Calibration completed normally. #0 1 Calibration failed. ADC accuracy specifications are not guaranteed. #1 CAL Calibration 7 1 read-write OFS ADC Offset Correction Register 0x28 32 read-write 0x4 0xFFFFFFFF OFS Offset Error Correction Value 0 16 read-write PG ADC Plus-Side Gain Register 0x2C 32 read-write 0x8200 0xFFFFFFFF PG Plus-Side Gain 0 16 read-write MG ADC Minus-Side Gain Register 0x30 32 read-write 0x8200 0xFFFFFFFF MG Minus-Side Gain 0 16 read-write CLPD ADC Plus-Side General Calibration Value Register 0x34 32 read-write 0xA 0xFFFFFFFF CLPD Calibration Value 0 6 read-write CLPS ADC Plus-Side General Calibration Value Register 0x38 32 read-write 0x20 0xFFFFFFFF CLPS Calibration Value 0 6 read-write CLP4 ADC Plus-Side General Calibration Value Register 0x3C 32 read-write 0x200 0xFFFFFFFF CLP4 Calibration Value 0 10 read-write CLP3 ADC Plus-Side General Calibration Value Register 0x40 32 read-write 0x100 0xFFFFFFFF CLP3 Calibration Value 0 9 read-write CLP2 ADC Plus-Side General Calibration Value Register 0x44 32 read-write 0x80 0xFFFFFFFF CLP2 Calibration Value 0 8 read-write CLP1 ADC Plus-Side General Calibration Value Register 0x48 32 read-write 0x40 0xFFFFFFFF CLP1 Calibration Value 0 7 read-write CLP0 ADC Plus-Side General Calibration Value Register 0x4C 32 read-write 0x20 0xFFFFFFFF CLP0 Calibration Value 0 6 read-write CLMD ADC Minus-Side General Calibration Value Register 0x54 32 read-write 0xA 0xFFFFFFFF CLMD Calibration Value 0 6 read-write CLMS ADC Minus-Side General Calibration Value Register 0x58 32 read-write 0x20 0xFFFFFFFF CLMS Calibration Value 0 6 read-write CLM4 ADC Minus-Side General Calibration Value Register 0x5C 32 read-write 0x200 0xFFFFFFFF CLM4 Calibration Value 0 10 read-write CLM3 ADC Minus-Side General Calibration Value Register 0x60 32 read-write 0x100 0xFFFFFFFF CLM3 Calibration Value 0 9 read-write CLM2 ADC Minus-Side General Calibration Value Register 0x64 32 read-write 0x80 0xFFFFFFFF CLM2 Calibration Value 0 8 read-write CLM1 ADC Minus-Side General Calibration Value Register 0x68 32 read-write 0x40 0xFFFFFFFF CLM1 Calibration Value 0 7 read-write CLM0 ADC Minus-Side General Calibration Value Register 0x6C 32 read-write 0x20 0xFFFFFFFF CLM0 Calibration Value 0 6 read-write ADC1 Analog-to-Digital Converter ADC ADC1_ 0x4003C000 0 0x70 registers ADC1 16 2 0x4 A,B SC1%s ADC Status and Control Registers 1 0 32 read-write 0x1F 0xFFFFFFFF ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11010 When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11101 When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. #11101 11110 When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. #11110 11111 Module is disabled. #11111 DIFF Differential Mode Enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 AIEN Interrupt Enable 6 1 read-write 0 Conversion complete interrupt is disabled. #0 1 Conversion complete interrupt is enabled. #1 COCO Conversion Complete Flag 7 1 read-only 0 Conversion is not completed. #0 1 Conversion is completed. #1 CFG1 ADC Configuration Register 1 0x8 32 read-write 0 0xFFFFFFFF ADICLK Input Clock Select 0 2 read-write 00 Bus clock #00 01 Bus clock divided by 2(BUSCLK/2) #01 10 Alternate clock (ALTCLK) #10 11 Asynchronous clock (ADACK) #11 MODE Conversion mode selection 2 2 read-write 00 When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. #00 01 When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output. #01 10 When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output #10 11 When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output #11 ADLSMP Sample Time Configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 ADIV Clock Divide Select 5 2 read-write 00 The divide ratio is 1 and the clock rate is input clock. #00 01 The divide ratio is 2 and the clock rate is (input clock)/2. #01 10 The divide ratio is 4 and the clock rate is (input clock)/4. #10 11 The divide ratio is 8 and the clock rate is (input clock)/8. #11 ADLPC Low-Power Configuration 7 1 read-write 0 Normal power configuration. #0 1 Low-power configuration. The power is reduced at the expense of maximum clock speed. #1 CFG2 ADC Configuration Register 2 0xC 32 read-write 0 0xFFFFFFFF ADLSTS Long Sample Time Select 0 2 read-write 00 Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. #00 01 12 extra ADCK cycles; 16 ADCK cycles total sample time. #01 10 6 extra ADCK cycles; 10 ADCK cycles total sample time. #10 11 2 extra ADCK cycles; 6 ADCK cycles total sample time. #11 ADHSC High-Speed Configuration 2 1 read-write 0 Normal conversion sequence selected. #0 1 High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. #1 ADACKEN Asynchronous Clock Output Enable 3 1 read-write 0 Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. #0 1 Asynchronous clock and clock output is enabled regardless of the state of the ADC. #1 2 0x4 A,B R%s ADC Data Result Register 0x10 32 read-only 0 0xFFFFFFFF D Data result 0 16 read-only 2 0x4 1,2 CV%s Compare Value Registers 0x18 32 read-write 0 0xFFFFFFFF CV Compare Value. 0 16 read-write SC2 Status and Control Register 2 0x20 32 read-write 0 0xFFFFFFFF REFSEL Voltage Reference Selection 0 2 read-write 00 Default voltage reference pin pair, that is, external pins VREFH and VREFL #00 01 Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU #01 DMAEN DMA Enable 2 1 read-write 0 DMA is disabled. #0 1 DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted. #1 ACREN Compare Function Range Enable 3 1 read-write 0 Range function disabled. Only CV1 is compared. #0 1 Range function enabled. Both CV1 and CV2 are compared. #1 ACFGT Compare Function Greater Than Enable 4 1 read-write 0 Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. #0 1 Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2. #1 ACFE Compare Function Enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ADTRG Conversion Trigger Select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 ADACT Conversion Active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 SC3 Status and Control Register 3 0x24 32 read-write 0 0xFFFFFFFF AVGS Hardware Average Select 0 2 read-write 00 4 samples averaged. #00 01 8 samples averaged. #01 10 16 samples averaged. #10 11 32 samples averaged. #11 AVGE Hardware Average Enable 2 1 read-write 0 Hardware average function disabled. #0 1 Hardware average function enabled. #1 ADCO Continuous Conversion Enable 3 1 read-write 0 One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. #0 1 Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. #1 CALF Calibration Failed Flag 6 1 read-write 0 Calibration completed normally. #0 1 Calibration failed. ADC accuracy specifications are not guaranteed. #1 CAL Calibration 7 1 read-write OFS ADC Offset Correction Register 0x28 32 read-write 0x4 0xFFFFFFFF OFS Offset Error Correction Value 0 16 read-write PG ADC Plus-Side Gain Register 0x2C 32 read-write 0x8200 0xFFFFFFFF PG Plus-Side Gain 0 16 read-write MG ADC Minus-Side Gain Register 0x30 32 read-write 0x8200 0xFFFFFFFF MG Minus-Side Gain 0 16 read-write CLPD ADC Plus-Side General Calibration Value Register 0x34 32 read-write 0xA 0xFFFFFFFF CLPD Calibration Value 0 6 read-write CLPS ADC Plus-Side General Calibration Value Register 0x38 32 read-write 0x20 0xFFFFFFFF CLPS Calibration Value 0 6 read-write CLP4 ADC Plus-Side General Calibration Value Register 0x3C 32 read-write 0x200 0xFFFFFFFF CLP4 Calibration Value 0 10 read-write CLP3 ADC Plus-Side General Calibration Value Register 0x40 32 read-write 0x100 0xFFFFFFFF CLP3 Calibration Value 0 9 read-write CLP2 ADC Plus-Side General Calibration Value Register 0x44 32 read-write 0x80 0xFFFFFFFF CLP2 Calibration Value 0 8 read-write CLP1 ADC Plus-Side General Calibration Value Register 0x48 32 read-write 0x40 0xFFFFFFFF CLP1 Calibration Value 0 7 read-write CLP0 ADC Plus-Side General Calibration Value Register 0x4C 32 read-write 0x20 0xFFFFFFFF CLP0 Calibration Value 0 6 read-write CLMD ADC Minus-Side General Calibration Value Register 0x54 32 read-write 0xA 0xFFFFFFFF CLMD Calibration Value 0 6 read-write CLMS ADC Minus-Side General Calibration Value Register 0x58 32 read-write 0x20 0xFFFFFFFF CLMS Calibration Value 0 6 read-write CLM4 ADC Minus-Side General Calibration Value Register 0x5C 32 read-write 0x200 0xFFFFFFFF CLM4 Calibration Value 0 10 read-write CLM3 ADC Minus-Side General Calibration Value Register 0x60 32 read-write 0x100 0xFFFFFFFF CLM3 Calibration Value 0 9 read-write CLM2 ADC Minus-Side General Calibration Value Register 0x64 32 read-write 0x80 0xFFFFFFFF CLM2 Calibration Value 0 8 read-write CLM1 ADC Minus-Side General Calibration Value Register 0x68 32 read-write 0x40 0xFFFFFFFF CLM1 Calibration Value 0 7 read-write CLM0 ADC Minus-Side General Calibration Value Register 0x6C 32 read-write 0x20 0xFFFFFFFF CLM0 Calibration Value 0 6 read-write DAC0 12-Bit Digital-to-Analog Converter DAC0_ 0x4003F000 0 0x24 registers DAC0 25 2 0x2 0,1 DAT%sL DAC Data Low Register 0 8 read-write 0 0xFF DATA0 DATA0 0 8 read-write 2 0x2 0,1 DAT%sH DAC Data High Register 0x1 8 read-write 0 0xFF DATA1 DATA1 0 4 read-write SR DAC Status Register 0x20 8 read-write 0x6 0xFF DACBFRPBF DAC Buffer Read Pointer Bottom Position Flag 0 1 read-write 0 The DAC buffer read pointer is not equal to C2[DACBFUP]. #0 1 The DAC buffer read pointer is equal to C2[DACBFUP]. #1 DACBFRPTF DAC Buffer Read Pointer Top Position Flag 1 1 read-write 0 The DAC buffer read pointer is not zero. #0 1 The DAC buffer read pointer is zero. #1 DACBFWMF DAC Buffer Watermark Flag 2 1 read-write 0 The DAC buffer read pointer has not reached the watermark level. #0 1 The DAC buffer read pointer has reached the watermark level. #1 C0 DAC Control Register 0x21 8 read-write 0 0xFF DACBBIEN DAC Buffer Read Pointer Bottom Flag Interrupt Enable 0 1 read-write 0 The DAC buffer read pointer bottom flag interrupt is disabled. #0 1 The DAC buffer read pointer bottom flag interrupt is enabled. #1 DACBTIEN DAC Buffer Read Pointer Top Flag Interrupt Enable 1 1 read-write 0 The DAC buffer read pointer top flag interrupt is disabled. #0 1 The DAC buffer read pointer top flag interrupt is enabled. #1 DACBWIEN DAC Buffer Watermark Interrupt Enable 2 1 read-write 0 The DAC buffer watermark interrupt is disabled. #0 1 The DAC buffer watermark interrupt is enabled. #1 LPEN DAC Low Power Control 3 1 read-write 0 High-Power mode #0 1 Low-Power mode #1 DACSWTRG DAC Software Trigger 4 1 write-only 0 The DAC soft trigger is not valid. #0 1 The DAC soft trigger is valid. #1 DACTRGSEL DAC Trigger Select 5 1 read-write 0 The DAC hardware trigger is selected. #0 1 The DAC software trigger is selected. #1 DACRFS DAC Reference Select 6 1 read-write 0 The DAC selects DACREF_1 as the reference voltage. #0 1 The DAC selects DACREF_2 as the reference voltage. #1 DACEN DAC Enable 7 1 read-write 0 The DAC system is disabled. #0 1 The DAC system is enabled. #1 C1 DAC Control Register 1 0x22 8 read-write 0 0xFF DACBFEN DAC Buffer Enable 0 1 read-write 0 Buffer read pointer is disabled. The converted data is always the first word of the buffer. #0 1 Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. #1 DACBFMD DAC Buffer Work Mode Select 2 1 read-write 0 Normal mode #0 1 One-Time Scan mode #1 DMAEN DMA Enable Select 7 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time. #1 C2 DAC Control Register 2 0x23 8 read-write 0x1 0xFF DACBFUP DAC Buffer Upper Limit 0 1 read-write DACBFRP DAC Buffer Read Pointer 4 1 read-write LPTMR0 Low Power Timer LPTMR0_ 0x40040000 0 0x10 registers LPTMR0 28 CSR Low Power Timer Control Status Register 0 32 read-write 0 0xFFFFFFFF TEN Timer Enable 0 1 read-write 0 LPTMR is disabled and internal logic is reset. #0 1 LPTMR is enabled. #1 TMS Timer Mode Select 1 1 read-write 0 Time Counter mode. #0 1 Pulse Counter mode. #1 TFC Timer Free-Running Counter 2 1 read-write 0 CNR is reset whenever TCF is set. #0 1 CNR is reset on overflow. #1 TPP Timer Pin Polarity 3 1 read-write 0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. #0 1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. #1 TPS Timer Pin Select 4 2 read-write 00 Pulse counter input 0 is selected. #00 01 Pulse counter input 1 is selected. #01 10 Pulse counter input 2 is selected. #10 11 Pulse counter input 3 is selected. #11 TIE Timer Interrupt Enable 6 1 read-write 0 Timer interrupt disabled. #0 1 Timer interrupt enabled. #1 TCF Timer Compare Flag 7 1 read-write 0 The value of CNR is not equal to CMR and increments. #0 1 The value of CNR is equal to CMR and increments. #1 PSR Low Power Timer Prescale Register 0x4 32 read-write 0 0xFFFFFFFF PCS Prescaler Clock Select 0 2 read-write 00 Prescaler/glitch filter clock 0 selected. #00 01 Prescaler/glitch filter clock 1 selected. #01 10 Prescaler/glitch filter clock 2 selected. #10 11 Prescaler/glitch filter clock 3 selected. #11 PBYP Prescaler Bypass 2 1 read-write 0 Prescaler/glitch filter is enabled. #0 1 Prescaler/glitch filter is bypassed. #1 PRESCALE Prescale Value 3 4 read-write 0000 Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. #0000 0001 Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. #0001 0010 Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. #0010 0011 Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. #0011 0100 Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. #0100 0101 Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. #0101 0110 Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. #0110 0111 Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. #0111 1000 Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. #1000 1001 Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. #1001 1010 Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. #1010 1011 Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. #1011 1100 Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. #1100 1101 Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. #1101 1110 Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. #1110 1111 Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. #1111 CMR Low Power Timer Compare Register 0x8 32 read-write 0 0xFFFFFFFF COMPARE Compare Value 0 16 read-write CNR Low Power Timer Counter Register 0xC 32 read-write 0 0xFFFFFFFF COUNTER Counter Value 0 16 read-write SIM System Integration Module SIM_ 0x40047000 0 0x1104 registers SOPT1 System Options Register 1 0 32 read-write 0 0xFFFFFFFF OSC32KSEL 32K Oscillator Clock Select 18 2 read-write 00 System oscillator (OSC32KCLK) #00 11 LPO 1 kHz #11 SOPT2 System Options Register 2 0x1004 32 read-write 0 0xFFFFFFFF CLKOUTSEL CLKOUT Select 5 3 read-write 010 Bus clock #010 011 LPO clock (1 kHz) #011 100 MCGIRCLK #100 110 OSCERCLK #110 FTMFFCLKSEL FTM Fixed Frequency Clock Select 24 2 read-write 00 MCGFFCLK #00 01 MCGIRCLK #01 10 OSCERCLK #10 11 MCGFFCLK #11 SOPT4 System Options Register 4 0x100C 32 read-write 0 0xFFFFFFFF FTM0FLT0 FTM0 Fault 0 Select 0 1 read-write 0 FTM0_FLT0 pin #0 1 CMP0 out #1 FTM0FLT1 FTM0 Fault 1 Select 1 1 read-write 0 FTM0_FLT1 pin #0 1 CMP1 out #1 FTM1FLT0 FTM1 Fault 0 Select 2 1 read-write 0 FTM1_FLT0 pin #0 1 CMP0 out #1 FTM2FLT0 FTM2 Fault 0 Select 3 1 read-write 0 FTM2_FLT0 pin #0 1 CMP0 out #1 FTM0TRG0SRC FlexTimer 0 Hardware Trigger 0 Source Select 7 1 read-write 0 CMP0 output drives FTM0 hardware trigger 0 #0 1 FTM1 channel match drives FTM0 hardware trigger 0 #1 FTM0TRG1SRC FlexTimer 0 Hardware Trigger 1 Source Select 8 1 read-write 0 PDB0 channel 1 trigger drives FTM0 hardware trigger 1 #0 1 FTM2 channel match drives FTM0 hardware trigger 1 #1 FTM0TRG2SRC FlexTimer 0 Hardware Trigger 2 Source Select 9 1 read-write 0 CMP0 output drives FTM0 hardware trigger 2 #0 1 CMP1 output drives FTM0 hardware trigger 2 #1 FTM1TRG0SRC FlexTimer 1 Hardware Trigger 0 Source Select 10 1 read-write 0 CMP0 output drives FTM1 hardware trigger 0 #0 1 FTM0 channel match drives FTM1 hardware trigger 0 #1 FTM1TRG1SRC FlexTimer 1 Hardware Trigger 1 Source Select 11 1 read-write 0 PDB0 channel 1 trigger drives FTM1 hardware trigger 1 #0 1 FTM2 channel match drives FTM1 hardware trigger 1 #1 FTM1TRG2SRC FlexTimer 1 Hardware Trigger 2 Source Select 12 1 read-write 0 CMP0 output drives FTM1 hardware trigger 2 #0 1 CMP1 output drives FTM1 hardware trigger 2 #1 FTM2TRG0SRC FlexTimer 2 Hardware Trigger 0 Source Select 13 1 read-write 0 CMP0 output drives FTM2 hardware trigger 0 #0 1 FTM0 channel match drives FTM2 hardware trigger 0 #1 FTM2TRG1SRC FlexTimer 2 Hardware Trigger 1 Source Select 14 1 read-write 0 PDB0 output trigger 1 drives FTM2 hardware trigger 1 #0 1 FTM1 channel match drives FTM2 hardware trigger 1 #1 FTM2TRG2SRC FlexTimer 2 Hardware Trigger 2 Source Select 15 1 read-write 0 CMP0 output drives FTM2 hardware trigger 2 #0 1 CMP1 output drives FTM2 hardware trigger 2 #1 FTM1CH0SRC FTM1 Channel 0 Input Capture Source Select 18 2 read-write 00 FTM1_CH0 signal #00 01 CMP0 output #01 10 CMP1 output #10 FTM2CH0SRC FTM2 Channel 0 Input Capture Source Select 20 2 read-write 00 FTM2_CH0 signal #00 01 CMP0 output #01 10 CMP1 output #10 FTM2CH1SRC FTM2 Channel 1 Input Capture Source Select 22 1 read-write 0 FTM2_CH1 pin is fed to FTM2 CH1 #0 1 FTM2_CH1 pin XOR FTM2_CH0 pin XOR FTM1_CH1 pin is fed to FTM2 CH1 If this field is set, then the three input pins feed FTM2 channel 1 input capture. In this case, FTM1 channel 1 cannot be used for input capture of FTM1, as it has no pin. FTM1 channel1 can be used for Output Compare mode of FTM1, though without an output. #1 FTM0CLKSEL FTM0 External Clock Pin Select 24 2 read-write 00 FTM0 external clock driven by FTM_CLKIN0 pin #00 01 FTM0 external clock driven by FTM_CLKIN1 pin #01 10 FTM0 external clock driven by FTM_CLKIN2 pin #10 FTM1CLKSEL FTM1 External Clock Pin Select 26 2 read-write 00 FTM1 external clock driven by FTM_CLKIN0 pin #00 01 FTM1 external clock driven by FTM_CLKIN1 pin #01 10 FTM1 external clock driven by FTM_CLKIN2 pin #10 FTM2CLKSEL FTM2 External Clock Pin Select 28 2 read-write 00 FTM2 external clock driven by FTM_CLKIN0 pin #00 01 FTM2 external clock driven by FTM_CLKIN1 pin #01 10 FTM2 external clock driven by FTM_CLKIN2 pin #10 SOPT5 System Options Register 5 0x1010 32 read-write 0 0xFFFFFFFF UART0TXSRC UART 0 Transmit Data Source Select 0 2 read-write 00 UART0_TX pin #00 01 UART0_TX pin modulated with FTM1 channel 0 output #01 10 UART0_TX pin modulated with FTM2 channel 0 output #10 UART0RXSRC UART 0 Receive Data Source Select 2 2 read-write 00 UART0_RX pin #00 01 CMP0 #01 10 CMP1 #10 UART1TXSRC UART 1 Transmit Data Source Select 4 2 read-write 00 UART1_TX pin #00 01 UART1_TX pin modulated with FTM1 channel 0 output #01 10 UART1_TX pin modulated with FTM2 channel 0 output #10 UART1RXSRC UART 1 Receive Data Source Select 6 2 read-write 00 UART1_RX pin #00 01 CMP0 #01 10 CMP1 #10 UART0ODE UART0 Open Drain Enable 16 1 read-write 0 Open drain is disabled on UART0 #0 1 Open drain is enabled on UART0 #1 UART1ODE UART1 Open Drain Enable 17 1 read-write 0 Open drain is disabled on UART1 #0 1 Open drain is enabled on UART1 #1 SOPT6 Systems Option Register 6 0x1014 32 read-write 0 0xFFFFFFFF FTM3FLT0 FTM3 Fault 0 Select 0 1 read-write 0 FTM3_FLT0 pin #0 1 CMP0 out #1 FTM4FLT0 FTM4 Fault 0 Select 2 1 read-write 0 FTM4_FLT0 pin #0 1 CMP0 out #1 FTM5FLT0 FTM5 Fault 0 Select 3 1 read-write 0 FTM5_FLT0 pin #0 1 CMP0 out #1 FTM3TRG0SRC FlexTimer 3 Hardware Trigger 0 Source Select 7 1 read-write 0 CMP0 output drives FTM3 hardware trigger 0 #0 1 FTM5 channel match drives FTM3 hardware trigger 0 #1 FTM3TRG1SRC FlexTimer 3 Hardware Trigger 1 Source Select 8 1 read-write 0 PDB1 output drives FTM3 hardware trigger 1 #0 1 FTM4 channel match drives FTM3 hardware trigger 1 #1 FTM3TRG2SRC FlexTimer 3 Hardware Trigger 2 Source Select 9 1 read-write 0 CMP0 output drives FTM3 hardware trigger 2 #0 1 CMP1 output drives FTM3 hardware trigger 2 #1 FTM4TRG0SRC FlexTimer 4 Hardware Trigger 0 Source Select 10 1 read-write 0 CMP0 output drives FTM4 hardware trigger 0 #0 1 FTM3 channel match drives FTM4 hardware trigger 0 #1 FTM4TRG1SRC FlexTimer 4 Hardware Trigger 1 Source Select 11 1 read-write 0 PDB1 output trigger 1 drives FTM4 hardware trigger 1 #0 1 FTM5 channel match drives FTM4 hardware trigger 1 #1 FTM4TRG2SRC FlexTimer 4 Hardware Trigger 2 Source Select 12 1 read-write 0 CMP0 output drives FTM4 hardware trigger 2 #0 1 CMP1 output drives FTM4 hardware trigger 2 #1 FTM5TRG0SRC FlexTimer 5 Hardware Trigger 0 Source Select 13 1 read-write 0 CMP0 output drives FTM5 hardware trigger 0 #0 1 FTM3 channel match drives FTM5 hardware trigger 0 #1 FTM5TRG1SRC FlexTimer 5 Hardware Trigger 1 Source Select 14 1 read-write 0 PDB1 output trigger 1 drives FTM5 hardware trigger 1 #0 1 FTM4 channel match drives FTM5 hardware trigger 1 #1 FTM5TRG2SRC FlexTimer 5 Hardware Trigger 2 Source Select 15 1 read-write 0 CMP0 output drives FTM5 hardware trigger 2 #0 1 CMP1 output drives FTM5 hardware trigger 2 #1 FTM4CH0SRC FTM4 channel 0 input capture source select 18 2 read-write 00 FTM4_CH0 signal #00 01 CMP0 output #01 10 CMP1 output #10 FTM5CH0SRC FTM5 channel 0 input capture source select 20 2 read-write 00 FTM5_CH0 signal #00 01 CMP0 output #01 10 CMP1 output #10 FTM3CLKSEL FTM3 External Clock Pin Select 24 2 read-write 00 FTM3 external clock driven by FTM_CLKIN0 pin #00 01 FTM3 external clock driven by FTM_CLKIN1 pin #01 10 FTM3 external clock driven by FTM_CLKIN2 pin #10 FTM4CLKSEL FTM4 External Clock Pin Select 26 2 read-write 00 FTM4 external clock driven by FTM_CLKIN0 pin #00 01 FTM4 external clock driven by FTM_CLKIN1 pin #01 10 FTM4 external clock driven by FTM_CLKIN2 pin #10 FTM5CLKSEL FTM5 External Clock Pin Select 28 2 read-write 00 FTM5 external clock driven by FTM_CLKIN0 pin #00 01 FTM5 external clock driven by FTM_CLKIN1 pin #01 10 FTM5 external clock driven by FTM_CLKIN2 pin #10 SOPT7 System Options Register 7 0x1018 32 read-write 0 0xFFFFFFFF ADC0TRGSEL ADC0 Trigger Select 0 4 read-write 0000 External trigger pin input (PDB_EXTRG0) #0000 0001 CMP0 output #0001 0010 CMP1 output #0010 0011 External trigger pin input (PDB_EXTRG1) #0011 0100 DMA channel 0 transfer last write complete #0100 0101 DMA channel 1 transfer last write complete #0101 0110 DMA channel 2 transfer last write complete #0110 0111 DMA channel 3 transfer last write complete #0111 1000 FTM0 intialtrig or external trig output #1000 1001 FTM1 intial trig or external trig output #1001 1010 FTM2 intial trig or external trig output #1010 1011 FTM3 intial trig or external trig output #1011 1100 FTM4 intial trig or external trig output #1100 1101 FTM5 intial trig or external trig output #1101 1110 LPTMR0 trigger #1110 ADC0PRETRGSEL ADC0 Pre-trigger Select 4 1 read-write 0 Pre-trigger A for ADC0. Clearing this field will result in ADHWTSA=1 and ADHWTSB=0. #0 1 Pre-trigger B for ADC0. Setting this bit will result in ADHWTSA=0 and ADHWTSB=1. #1 ADC0ALTTRGEN Enable alternative conversion triggers for ADC0. 6 2 read-write 00 PDB0 CH0 triggers ADC0 #00 01 PDB1 CH0 triggers ADC0 #01 10 Alt trigger source as per ADC0TRGSEL #10 11 PDB0 CH0 OR PDB1 CH0 trigger ADC0 #11 ADC1TRGSEL ADC1 Trigger Select 8 4 read-write 0000 External trigger pin input (PDB_EXTRG0) #0000 0001 CMP0 output #0001 0010 CMP1 output #0010 0011 External trigger pin input (PDB_EXTRG1) #0011 0100 DMA channel 0 transfer last write complete #0100 0101 DMA channel 1 transfer last write complete #0101 0110 DMA channel 2 transfer last write complete #0110 0111 DMA channel 3 transfer last write complete #0111 1000 FTM0 intialtrig or external trig output #1000 1001 FTM1 intial trig or external trig output #1001 1010 FTM2 intial trig or external trig output #1010 1011 FTM3 intial trig or external trig output #1011 1100 FTM4 intial trig or external trig output #1100 1101 FTM5 intial trig or external trig output #1101 1110 LPTMR0 trigger #1110 ADC1PRETRGSEL ADC1 Pre-trigger Select 12 1 read-write 0 Pre-trigger A for ADC1. Clearing this field will result in ADHWTSA=1 and ADHWTSB=0. #0 1 Pre-trigger B for ADC1. Setting this bit will result in ADHWTSA=0 and ADHWTSB=1. #1 ADC1ALTTRGEN Enable alternative conversion triggers for ADC1. 14 2 read-write 00 PDB0 CH1 triggers ADC1 #00 01 PDB1 CH1 triggers ADC1 #01 10 Alt trigger source ADC1TRGSEL #10 11 PDB0 CH1 OR PDB1 CH1 trigger ADC1 #11 ADC0ALTCLKSRC ADC0 ALT Clock Source Select 24 2 read-write 00 OUTDIV5 output #00 01 MCGIRCLK #01 10 OSCERCLK #10 ADC1ALTCLKSRC ADC1 ALT Clock Source Select 26 2 read-write 00 OUTDIV5 output #00 01 MCGIRCLK #01 10 OSCERCLK #10 SOPT8 System Options Register 8 0x101C 32 read-write 0 0xFFFFFFFF FTM0SYNCBIT FlexTimer 0 Hardware Trigger 0 configure by software 0 1 read-write 0 No effect to FTM0; this allow the hardware trigger options to function as expected. See SOPT4[FTM0TRG0SRC]. #0 1 If TRIG0 enabled, this refreshes the FTM0CNTIN and all buffered registers of the FTM0 (must write 0 first then write 1); this masks the hardware trigger. #1 FTM1SYNCBIT FlexTimer 1 Hardware Trigger 0 configure by software 1 1 read-write 0 No effect to FTM1; this allows the hardware trigger options to function as expected. See SOPT4[FTM1TRG0SRC]. #0 1 If TRIG0 enabled, this refreshes the FTM1CNTIN and all buffered registers of the FTM1 (must write 0 first then write 1); this masks the hardware trigger. #1 FTM2SYNCBIT FlexTimer 2 Hardware Trigger 0 configure by software 2 1 read-write 0 No effect to FTM2; this allows the hardware trigger options to function as expected. See SOPT4[FTM2TRG0SRC]. #0 1 If TRIG0 is enabled, this refreshes the FTM2CNTIN and all buffered registers of the FTM2 (must write 0 first then write 1); this masks the hardware trigger. #1 FTM3SYNCBIT FlexTimer 3 Hardware Trigger 0 configure by software 3 1 read-write 0 No effect to FTM3; this allows the hardware trigger options to function as expected. See SOPT6[FTM3TRG0SRC]. #0 1 If TRIG0 is enabled, this refreshes the FTM3CNTIN and allbuffered registers of the FTM3 (must write 0 first then write 1); this masks the hardware trigger. #1 FTM4SYNCBIT FlexTimer 4 Hardware Trigger 0 configure by software 4 1 read-write 0 No effect to FTM4; this allows the hardware trigger options to function as expected. See SOPT6[FTM4TRG0SRC]. #0 1 If TRIG0 is enabled, this refreshes the FTM4CNTIN and allbuffered registers of the FTM4 (must write 0 first then write 1); this masks the hardware trigger. #1 FTM5SYNCBIT FlexTimer 5 Hardware Trigger 0 configure by software 5 1 read-write 0 No effect on FTM5; this allows the hardware trigger options to function as expected. See SOPT6[FTM5TRG0SRC]. #0 1 If TRIG0 is enabled, this refreshes the FTM5CNTIN and allbuffered registers of the FTM5 (must write 0 first then write 1); this masks the hardware trigger. #1 CARRIER_SELECT0 Carrier frequency selection for FTM0/2 output channel 8 2 read-write 00 FTM1_CH1 output provides the carrier signal for Timer Modulation mode #00 01 LPTMR0 prescaler output provides the carrier signal for Timer Modulation mode #01 10 FTM5_CH1 output provides the carrier signal for Timer Modulation mode #10 FTM0OCH0SRC FTM0 channel 0 output PWM/OCMP mode source select 16 1 read-write 0 FTM0CH0 pin is the output of FTM0 channel 0 PWM/OCMP #0 1 FTM0CH0 pin is the output of FTM0 channel 0 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0 #1 FTM0OCH1SRC FTM0 channel 1 output PWM/OCMP mode source select 17 1 read-write 0 FTM0CH1 pin is the output of FTM0 channel 1 PWM/OCMP #0 1 FTM0CH1 pin is the output of FTM0 channel 1 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0 #1 FTM0OCH2SRC FTM0 channel 2 output PWM/OCMP mode source select 18 1 read-write 0 FTM0CH2 pin is the output of FTM0 channel 2 PWM/OCMP #0 1 FTM0CH2 pin is the output of FTM0 channel 2 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0 #1 FTM0OCH3SRC FTM0 channel 3 output PWM/OCMP mode source select 19 1 read-write 0 FTM0CH3 pin is the output of FTM0 channel 3 PWM/OCMP #0 1 FTM0CH3 pin is the output of FTM0 channel 3 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0 #1 FTM0OCH4SRC FTM0 channel 4 output PWM/OCMP mode source select 20 1 read-write 0 FTM0CH4 pin is the output of FTM0 channel 4 PWM/OCMP #0 1 FTM0CH4 pin is the output of FTM0 channel 4 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0 #1 FTM0OCH5SRC FTM0 channel 5 output PWM/OCMP mode source select 21 1 read-write 0 FTM0CH5 pin is the output of FTM0 channel 5 PWM/OCMP #0 1 FTM0CH5 pin is the output of FTM0 channel 5 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0 #1 FTM2OCH0SRC FTM2 channel 0 output PWM/OCMP mode source select 22 1 read-write 0 FTM2CH0 pin is the output of FTM2 channel 0 PWM/OCMP #0 1 FTM2CH0 pin is the output of FTM2 channel 0 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0 #1 FTM2OCH1SRC FTM2 channel 1 output PWM/OCMP mode source select 23 1 read-write 0 FTM2CH1 pin is the output of FTM2 channel 1 PWM/OCMP #0 1 FTM2CH1 pin is the output of FTM2 channel 1 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0 #1 SOPT9 System Options Register 9 0x1020 32 read-write 0 0xFFFFFFFF CARRIER_SELECT1 Carrier frequency selection for FTM3/4 output channel 8 2 read-write 00 FTM1_CH1 output provides the carrier signal for Timer Modulation mode #00 01 LPTMR0 prescaler output provides the carrier signal for Timer Modulation mode #01 10 FTM5_CH1 output provides the carrier signal for Timer Modulation mode #10 FTM3OCH0SRC FTM3 channel 0 output PWM/OCMP mode source select 16 1 read-write 0 FTM3CH0 pin is the output of FTM3 channel 0 PWM/OCMP #0 1 FTM3CH0 pin is the output of FTM3 channel 0 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT1 #1 FTM3OCH1SRC FTM3 channel 1 output PWM/OCMP mode source select 17 1 read-write 0 FTM3CH1 pin is the output of FTM3 channel 1 PWM/OCMP #0 1 FTM3CH1 pin is the output of FTM3 channel 1 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT1 #1 FTM3OCH2SRC FTM3 channel 2 output PWM/OCMP mode source select 18 1 read-write 0 FTM3CH2 pin is the output of FTM3 channel 2 PWM/OCMP #0 1 FTM3CH2 pin is the output of FTM3 channel 2 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT1 #1 FTM3OCH3SRC FTM3 channel 3 output PWM/OCMP mode source select 19 1 read-write 0 FTM3CH3 pin is the output of FTM3 channel 3 PWM/OCMP #0 1 FTM3CH3 pin is the output of FTM3 channel 3 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT1 #1 FTM3OCH4SRC FTM3 channel 4 output PWM/OCMP mode source select 20 1 read-write 0 FTM3CH4 pin is the output of FTM3 channel 4 PWM/OCMP #0 1 FTM3CH4 pin is the output of FTM3 channel 4 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT1 #1 FTM3OCH5SRC FTM3 channel 5 output PWM/OCMP mode source select 21 1 read-write 0 FTM3CH5 pin is the output of FTM3 channel 5 PWM/OCMP #0 1 FTM3CH5 pin is the output of FTM3 channel 5 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT1 #1 FTM4OCH0SRC FTM4 channel 0 output PWM/OCMP mode source select 22 1 read-write 0 FTM4CH0 pin is the output of FTM4 channel 0 PWM/OCMP #0 1 FTM4CH0 pin is the output of FTM4 channel 0 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT1 #1 FTM4OCH1SRC FTM4 channel 1 output PWM/OCMP mode source select 23 1 read-write 0 FTM4CH1 pin is the output of FTM4 channel 1 PWM/OCMP #0 1 FTM4CH1 pin is the output of FTM4 channel 1 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT1 #1 SDID System Device Identification Register 0x1024 32 read-only 0x10000000 0xF0000070 PINID Pincount identification 0 4 read-only 0010 32-pin #0010 0100 48-pin #0100 0101 64-pin #0101 DIEID Device die number 7 5 read-only REVID Device revision number 12 4 read-only SRAMSIZE Specifies the size of the System SRAM. 16 4 read-only 0101 16 KB #0101 SERIERID Series ID 20 4 read-only 0110 V-family - Motor control #0110 SUBFAMID V Sub-family ID 24 4 read-only 0000 MKV10xxxx #0000 0001 MKV11xxxx #0001 FAMID V-Family ID 28 4 read-only 0001 MKV1xZx #0001 SCGC4 System Clock Gating Control Register 4 0x1034 32 read-write 0xF0000030 0xFFFFFFFF EWM EWM Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 I2C0 I2C0 Clock Gate Control 6 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART0 UART0 Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART1 UART1 Clock Gate Control 11 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CMP Comparator Clock Gate Control 19 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC5 System Clock Gating Control Register 5 0x1038 32 read-write 0x40180 0xFFFFFFFF LPTMR Low Power Timer Clock Gate Control 0 1 read-write 0 Access disabled #0 1 Access enabled #1 PORTA Port A Clock Gate Control 9 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTB Port B Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTC Port C Clock Gate Control 11 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTD Port D Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTE Port E Clock Gate Control 13 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC6 System Clock Gating Control Register 6 0x103C 32 read-write 0x1 0xFFFFFFFF FTF Flash Memory Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 DMAMUX DMA Mux Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FLEXCAN0 FLEXCAN0 Clock Gate Control 4 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM3 FTM3 Clock Gate Control 6 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM4 FTM4 Clock Gate Control 7 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM5 FTM5 Clock Gate Control 8 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI0 SPI0 Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PDB1 PDB1 Clock Gate Control 17 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CRC CRC Clock Gate Control 18 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PDB0 PDB0 Clock Gate Control 22 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM0 FTM0 Clock Gate Control 24 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM1 FTM1 Clock Gate Control 25 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM2 FTM2 Clock Gate Control 26 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ADC0 ADC0 Clock Gate Control 27 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ADC1 ADC1 Clock Gate Control 28 1 read-write 0 Clock disabled #0 1 Clock enabled #1 DAC0 DAC0 Clock Gate Control 31 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC7 System Clock Gating Control Register 7 0x1040 32 read-write 0x100 0xFFFFFFFF DMA DMA Clock Gate Control 8 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CLKDIV1 System Clock Divider Register 1 0x1044 32 read-write 0x11000 0xFFFFFFFF OUTDIV5 Clock 5 Output Divider Value 12 3 read-write 000 Divide-by-1 #000 001 Divide-by-2 #001 010 Divide-by-3 #010 011 Divide-by-4 #011 100 Divide-by-5 #100 101 Divide-by-6 #101 110 Divide-by-7 #110 111 Divide-by-8 #111 OUTDIV5EN OUTDIV5 Divider Control 15 1 read-write 0 OUTDIV5 disabled #0 1 OUTDIV5 enabled #1 OUTDIV4 Clock 4 Output Divider Value 16 3 read-write 000 Divide-by-1. #000 001 Divide-by-2. #001 010 Divide-by-3. #010 011 Divide-by-4. #011 100 Divide-by-5. #100 101 Divide-by-6. #101 110 Divide-by-7. #110 111 Divide-by-8. #111 OUTDIV1 Clock 1 Output Divider Value 28 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 FCFG1 Flash Configuration Register 1 0x104C 32 read-write 0 0xF0FFFFFF FLASHDIS Flash Disable 0 1 read-write 0 Flash is enabled #0 1 Flash is disabled #1 FLASHDOZE Flash Doze 1 1 read-write 0 Flash remains enabled during Doze mode #0 1 Flash is disabled for the duration of Doze mode #1 PFSIZE Program Flash Size 24 4 read-only 0000 8 KB of program flash memory, 0.25 KB protection region #0000 0001 16 KB of program flash memory, 0.5 KB protection region #0001 0011 32 KB of program flash memory, 1 KB protection region #0011 0101 64 KB of program flash memory, 2 KB protection region #0101 0111 128 KB of program flash memory, 4 KB protection region #0111 1001 256 KB of program flash memory, 4 KB protection region #1001 1111 32 KB of program flash memory, 1 KB protection region #1111 FCFG2 Flash Configuration Register 2 0x1050 32 read-only 0x800000 0x80FFFFFF MAXADDR Max address block 24 7 read-only UIDMH Unique Identification Register Mid-High 0x1058 32 read-only 0 0 UID Unique Identification 0 16 read-only UIDML Unique Identification Register Mid Low 0x105C 32 read-only 0 0 UID Unique Identification 0 32 read-only UIDL Unique Identification Register Low 0x1060 32 read-only 0 0 UID Unique Identification 0 32 read-only WDOGC WDOG Control Register 0x1100 32 read-write 0 0xFFFFFFFF WDOGCLKS WDOG Clock Select 1 1 read-write 0 Internal 1 kHz clock is source to WDOG #0 1 MCGIRCLK is source to WDOG #1 PORTA Pin Control and Interrupts PORT PORTA_ 0x40049000 0 0xA4 registers PORTA 30 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0x702 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PORTB Pin Control and Interrupts PORT PORTB_ 0x4004A000 0 0xA4 registers PORTB_PORTC_PORTD_PORTE 31 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PORTC Pin Control and Interrupts PORT PORTC_ 0x4004B000 0 0xA4 registers PORTB_PORTC_PORTD_PORTE 31 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PORTD Pin Control and Interrupts PORT PORTD_ 0x4004C000 0 0xA4 registers PORTB_PORTC_PORTD_PORTE 31 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PORTE Pin Control and Interrupts PORT PORTE_ 0x4004D000 0 0xA4 registers PORTB_PORTC_PORTD_PORTE 31 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0x1 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 WDOG Generation 2008 Watchdog Timer WDOG_ 0x40052000 0 0x18 registers WDOG_EWM 23 STCTRLH Watchdog Status and Control Register High 0 16 read-write 0x1D3 0xFFFF WDOGEN Enables or disables the WDOG's operation 0 1 read-write 0 WDOG is disabled. #0 1 WDOG is enabled. #1 CLKSRC Selects clock source for the WDOG timer and other internal timing operations. 1 1 read-write 0 WDOG clock sourced from LPO . #0 1 WDOG clock sourced from alternate clock source. #1 IRQRSTEN Used to enable the debug breadcrumbs feature 2 1 read-write 0 WDOG time-out generates reset only. #0 1 WDOG time-out initially generates an interrupt. After WCT, it generates a reset. #1 WINEN Enables Windowing mode. 3 1 read-write 0 Windowing mode is disabled. #0 1 Windowing mode is enabled. #1 ALLOWUPDATE Enables updates to watchdog write-once registers, after the reset-triggered initial configuration window (WCT) closes, through unlock sequence 4 1 read-write 0 No further updates allowed to WDOG write-once registers. #0 1 WDOG write-once registers can be unlocked for updating. #1 DBGEN Enables or disables WDOG in Debug mode. 5 1 read-write 0 WDOG is disabled in CPU Debug mode. #0 1 WDOG is enabled in CPU Debug mode. #1 STOPEN Enables or disables WDOG in Stop mode. 6 1 read-write 0 WDOG is disabled in CPU Stop mode. #0 1 WDOG is enabled in CPU Stop mode. #1 WAITEN Enables or disables WDOG in Wait mode. 7 1 read-write 0 WDOG is disabled in CPU Wait mode. #0 1 WDOG is enabled in CPU Wait mode. #1 TESTWDOG Puts the watchdog in the functional test mode 10 1 read-write TESTSEL Effective only if TESTWDOG is set. Selects the test to be run on the watchdog timer. 11 1 read-write 0 Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test. #0 1 Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing. #1 BYTESEL This 2-bit field selects the byte to be tested when the watchdog is in the byte test mode. 12 2 read-write 00 Byte 0 selected #00 01 Byte 1 selected #01 10 Byte 2 selected #10 11 Byte 3 selected #11 DISTESTWDOG Allows the WDOG's functional test mode to be disabled permanently 14 1 read-write 0 WDOG functional test mode is not disabled. #0 1 WDOG functional test mode is disabled permanently until reset. #1 STCTRLL Watchdog Status and Control Register Low 0x2 16 read-write 0x1 0xFFFF INTFLG Interrupt flag 15 1 read-write TOVALH Watchdog Time-out Value Register High 0x4 16 read-write 0x4C 0xFFFF TOVALHIGH Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer 0 16 read-write TOVALL Watchdog Time-out Value Register Low 0x6 16 read-write 0x4B4C 0xFFFF TOVALLOW Defines the lower 16 bits of the 32-bit time-out value for the watchdog timer 0 16 read-write WINH Watchdog Window Register High 0x8 16 read-write 0 0xFFFF WINHIGH Defines the upper 16 bits of the 32-bit window for the windowed mode of operation of the watchdog 0 16 read-write WINL Watchdog Window Register Low 0xA 16 read-write 0x10 0xFFFF WINLOW Defines the lower 16 bits of the 32-bit window for the windowed mode of operation of the watchdog 0 16 read-write REFRESH Watchdog Refresh register 0xC 16 read-write 0xB480 0xFFFF WDOGREFRESH Watchdog refresh register 0 16 read-write UNLOCK Watchdog Unlock register 0xE 16 read-write 0xD928 0xFFFF WDOGUNLOCK Writing the unlock sequence values to this register to makes the watchdog write-once registers writable again 0 16 read-write TMROUTH Watchdog Timer Output Register High 0x10 16 read-write 0 0xFFFF TIMEROUTHIGH Shows the value of the upper 16 bits of the watchdog timer. 0 16 read-write TMROUTL Watchdog Timer Output Register Low 0x12 16 read-write 0 0xFFFF TIMEROUTLOW Shows the value of the lower 16 bits of the watchdog timer. 0 16 read-write RSTCNT Watchdog Reset Count register 0x14 16 read-write 0 0xFFFF RSTCNT Counts the number of times the watchdog resets the system 0 16 read-write PRESC Watchdog Prescaler register 0x16 16 read-write 0x400 0xFFFF PRESCVAL 3-bit prescaler for the watchdog clock source 8 3 read-write EWM External Watchdog Monitor EWM_ 0x40061000 0 0x6 registers WDOG_EWM 23 CTRL Control Register 0 8 read-write 0 0xFF EWMEN EWM enable. 0 1 read-write ASSIN EWM_in's Assertion State Select. 1 1 read-write INEN Input Enable. 2 1 read-write INTEN Interrupt Enable. 3 1 read-write SERV Service Register 0x1 8 write-only 0 0xFF SERVICE The EWM service mechanism requires the CPU to write two values to the SERV register: a first data byte of 0xB4, followed by a second data byte of 0x2C 0 8 write-only CMPL Compare Low Register 0x2 8 read-write 0 0xFF COMPAREL To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) minimum service time is required 0 8 read-write CMPH Compare High Register 0x3 8 read-write 0xFF 0xFF COMPAREH To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) maximum service time is required 0 8 read-write CLKCTRL Clock Control Register 0x4 8 read-write 0 0xFF CLKSEL EWM has 4 possible low power clock sources for running EWM counter 0 2 read-write CLKPRESCALER Clock Prescaler Register 0x5 8 read-write 0 0xFF CLK_DIV Selected low power clock source for running the EWM counter can be prescaled as below 0 8 read-write MCG Multipurpose Clock Generator module MCG_ 0x40064000 0 0xC registers MCG 27 C1 MCG Control 1 Register 0 8 read-write 0x4 0xFF IREFSTEN Internal Reference Stop Enable 0 1 read-write 0 Internal reference clock is disabled in Stop mode. #0 1 Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. #1 IRCLKEN Internal Reference Clock Enable 1 1 read-write 0 MCGIRCLK inactive. #0 1 MCGIRCLK active. #1 IREFS Internal Reference Select 2 1 read-write 0 External reference clock is selected. #0 1 The slow internal reference clock is selected. #1 FRDIV FLL External Reference Divider 3 3 read-write 000 If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. #000 001 If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. #001 010 If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. #010 011 If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. #011 100 If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. #100 101 If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. #101 110 If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . #110 111 If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 . #111 CLKS Clock Source Select 6 2 read-write 00 Encoding 0 - Output of FLL is selected. #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 11 Encoding 3 - Reserved. #11 C2 MCG Control 2 Register 0x1 8 read-write 0x80 0xFF IRCS Internal Reference Clock Select 0 1 read-write 0 Slow internal reference clock selected. #0 1 Fast internal reference clock selected. #1 LP Low Power Select 1 1 read-write 0 FLL is not disabled in bypass modes. #0 1 FLL is disabled in bypass modes (lower power) #1 EREFS External Reference Select 2 1 read-write 0 External reference clock requested. #0 1 Oscillator requested. #1 HGO High Gain Oscillator Select 3 1 read-write 0 Configure crystal oscillator for low-power operation. #0 1 Configure crystal oscillator for high-gain operation. #1 RANGE Frequency Range Select 4 2 read-write 00 Encoding 0 - Low frequency range selected for the crystal oscillator . #00 01 Encoding 1 - High frequency range selected for the crystal oscillator . #01 FCFTRIM Fast Internal Reference Clock Fine Trim 6 1 read-write LOCRE0 Loss of Clock Reset Enable 7 1 read-write 0 Interrupt request is generated on a loss of OSC0 external reference clock. #0 1 Generate a reset request on a loss of OSC0 external reference clock. #1 C3 MCG Control 3 Register 0x2 8 read-write 0 0 SCTRIM Slow Internal Reference Clock Trim Setting 0 8 read-write C4 MCG Control 4 Register 0x3 8 read-write 0 0xE0 SCFTRIM Slow Internal Reference Clock Fine Trim 0 1 read-write FCTRIM Fast Internal Reference Clock Trim Setting 1 4 read-write DRST_DRS DCO Range Select 5 2 read-write 00 Encoding 0 - Low range (reset default). #00 01 Encoding 1 - Mid range. #01 10 Encoding 2 - Mid-high range. #10 11 Encoding 3 - High range. #11 DMX32 DCO Maximum Frequency with 32.768 kHz Reference 7 1 read-write 0 DCO has a default range of 25%. #0 1 DCO is fine-tuned for maximum frequency with 32.768 kHz reference. #1 C6 MCG Control 6 Register 0x5 8 read-write 0 0xFF CME Clock Monitor Enable 5 1 read-write 0 External clock monitor is disabled. #0 1 Generate a reset request on loss of external clock. #1 S MCG Status Register 0x6 8 read-only 0x10 0xFF IRCST Internal Reference Clock Status 0 1 read-only 0 Source of internal reference clock is the slow clock (32 kHz IRC). #0 1 Source of internal reference clock is the fast clock (4 MHz IRC). #1 OSCINIT0 OSC Initialization 1 1 read-only CLKST Clock Mode Status 2 2 read-only 00 Encoding 0 - Output of the FLL is selected (reset default). #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 IREFST Internal Reference Status 4 1 read-only 0 Source of FLL reference clock is the external reference clock. #0 1 Source of FLL reference clock is the internal reference clock. #1 SC MCG Status and Control Register 0x8 8 read-write 0x2 0xFF LOCS0 OSC0 Loss of Clock Status 0 1 read-write 0 Loss of OSC0 has not occurred. #0 1 Loss of OSC0 has occurred. #1 FCRDIV Fast Clock Internal Reference Divider 1 3 read-write 000 Divide Factor is 1 #000 001 Divide Factor is 2. #001 010 Divide Factor is 4. #010 011 Divide Factor is 8. #011 100 Divide Factor is 16 #100 101 Divide Factor is 32 #101 110 Divide Factor is 64 #110 111 Divide Factor is 128. #111 FLTPRSRV FLL Filter Preserve Enable 4 1 read-write 0 FLL filter and FLL frequency will reset on changes to currect clock mode. #0 1 Fll filter and FLL frequency retain their previous values during new clock mode change. #1 ATMF Automatic Trim Machine Fail Flag 5 1 read-write 0 Automatic Trim Machine completed normally. #0 1 Automatic Trim Machine failed. #1 ATMS Automatic Trim Machine Select 6 1 read-write 0 32 kHz Internal Reference Clock selected. #0 1 4 MHz Internal Reference Clock selected. #1 ATME Automatic Trim Machine Enable 7 1 read-write 0 Auto Trim Machine disabled. #0 1 Auto Trim Machine enabled. #1 ATCVH MCG Auto Trim Compare Value High Register 0xA 8 read-write 0 0xFF ATCVH ATM Compare Value High 0 8 read-write ATCVL MCG Auto Trim Compare Value Low Register 0xB 8 read-write 0 0xFF ATCVL ATM Compare Value Low 0 8 read-write OSC0 Oscillator OSC0_ 0x40065000 0 0x1 registers CR OSC Control Register 0 8 read-write 0 0xFF SC16P Oscillator 16 pF Capacitor Load Configure 0 1 read-write 0 Disable the selection. #0 1 Add 16 pF capacitor to the oscillator load. #1 SC8P Oscillator 8 pF Capacitor Load Configure 1 1 read-write 0 Disable the selection. #0 1 Add 8 pF capacitor to the oscillator load. #1 SC4P Oscillator 4 pF Capacitor Load Configure 2 1 read-write 0 Disable the selection. #0 1 Add 4 pF capacitor to the oscillator load. #1 SC2P Oscillator 2 pF Capacitor Load Configure 3 1 read-write 0 Disable the selection. #0 1 Add 2 pF capacitor to the oscillator load. #1 EREFSTEN External Reference Stop Enable 5 1 read-write 0 External reference clock is disabled in Stop mode. #0 1 External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. #1 ERCLKEN External Reference Enable 7 1 read-write 0 External reference clock is inactive. #0 1 External reference clock is enabled. #1 I2C0 Inter-Integrated Circuit I2C0_ 0x40066000 0 0xC registers I2C0 8 A1 I2C Address Register 1 0 8 read-write 0 0xFF AD Address 1 7 read-write F I2C Frequency Divider register 0x1 8 read-write 0 0xFF ICR ClockRate 0 6 read-write MULT Multiplier Factor 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 C1 I2C Control Register 1 0x2 8 read-write 0 0xFF DMAEN DMA Enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 RSTA Repeat START 2 1 write-only TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 S I2C Status register 0x3 8 read-write 0x80 0xFF RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 D I2C Data I/O register 0x4 8 read-write 0 0xFF DATA Data 0 8 read-write C2 I2C Control Register 2 0x5 8 read-write 0 0xFF AD Slave Address 0 3 read-write RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 HDRS High Drive Select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 FLT I2C Programmable Input Glitch Filter Register 0x6 8 read-write 0 0xFF FLT I2C Programmable Filter Factor 0 4 read-write 0 No filter/bypass #0000 STARTF I2C Bus Start Detect Flag 4 1 read-write 0 No start happens on I2C bus #0 1 Start detected on I2C bus #1 SSIE I2C Bus Stop or Start Interrupt Enable 5 1 read-write 0 Stop or start detection interrupt is disabled #0 1 Stop or start detection interrupt is enabled #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. #0 1 Stop holdoff is enabled. #1 RA I2C Range Address register 0x7 8 read-write 0 0xFF RAD Range Slave Address 1 7 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write 0 0xFF SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the I2C module clock / 64 #0 1 Timeout counter counts at the frequency of the I2C module clock #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. #1 A2 I2C Address Register 2 0x9 8 read-write 0xC2 0xFF SAD SMBus Address 1 7 read-write SLTH I2C SCL Low Timeout Register High 0xA 8 read-write 0 0xFF SSLT SSLT[15:8] 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write 0 0xFF SSLT SSLT[7:0] 0 8 read-write UART0 Serial Communication Interface UART UART0_ 0x4006A000 0 0x17 registers UART0 12 BDH UART Baud Rate Registers: High 0 8 read-write 0 0xFF SBR UART Baud Rate Bits 0 5 read-write SBNS Stop Bit Number Select 5 1 read-write 0 Data frame consists of a single stop bit. #0 1 Data frame consists of two stop bits. #1 RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 LBKDIE LIN Break Detect Interrupt Enable 7 1 read-write 0 LBKDIF interrupt requests disabled. #0 1 LBKDIF interrupt requests enabled. #1 BDL UART Baud Rate Registers: Low 0x1 8 read-write 0x4 0xFF SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write 0 0xFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 C2 UART Control Register 2 0x3 8 read-write 0 0xFF SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 S1 UART Status Register 1 0x4 8 read-only 0xC0 0xFF PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write 0 0xFF RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character detection is disabled. #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 C3 UART Control Register 3 0x6 8 read-write 0 0xFF PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 T8 Transmit Bit 8 6 1 read-write R8 Received Bit 8 7 1 read-only D UART Data Register 0x7 8 read-write 0 0xFF RT Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register 0 8 read-write MA1 UART Match Address Registers 1 0x8 8 read-write 0 0xFF MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write 0 0xFF MA Match Address 0 8 read-write C4 UART Control Register 4 0xA 8 read-write 0 0xFF BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. #1 C5 UART Control Register 5 0xB 8 read-write 0 0xFF RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 ED UART Extended Data Register 0xC 8 read-only 0 0xFF PARITYE The current received dataword contained in D and C3[R8] was received with a parity error. 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 NOISY The current received dataword contained in D and C3[R8] was received with noise. 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 MODEM UART Modem Register 0xD 8 read-write 0 0xFF TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) Ensure that C2[TE] is asserted before assertion of this bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. See Hardware flow control #1 PFIFO UART FIFO Parameters 0x10 8 read-write 0 0xFF RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 CFIFO UART FIFO Control Register 0x11 8 read-write 0 0xFF RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 RXOFE Receive FIFO Overflow Interrupt Enable 2 1 read-write 0 RXOF flag does not generate an interrupt to the host. #0 1 RXOF flag generates an interrupt to the host. #1 RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 SFIFO UART FIFO Status Register 0x12 8 read-write 0xC0 0xFF RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 RXOF Receiver Buffer Overflow Flag 2 1 read-write 0 No receive buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer overflow has occurred since the last time the flag was cleared. #1 RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write 0 0xFF TXWATER Transmit Watermark 0 8 read-write TCFIFO UART FIFO Transmit Count 0x14 8 read-only 0 0xFF TXCOUNT Transmit Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write 0x1 0xFF RXWATER Receive Watermark 0 8 read-write RCFIFO UART FIFO Receive Count 0x16 8 read-only 0 0xFF RXCOUNT Receive Counter 0 8 read-only UART1 Serial Communication Interface UART UART1_ 0x4006B000 0 0x17 registers UART1 13 BDH UART Baud Rate Registers: High 0 8 read-write 0 0xFF SBR UART Baud Rate Bits 0 5 read-write SBNS Stop Bit Number Select 5 1 read-write 0 Data frame consists of a single stop bit. #0 1 Data frame consists of two stop bits. #1 RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 LBKDIE LIN Break Detect Interrupt Enable 7 1 read-write 0 LBKDIF interrupt requests disabled. #0 1 LBKDIF interrupt requests enabled. #1 BDL UART Baud Rate Registers: Low 0x1 8 read-write 0x4 0xFF SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write 0 0xFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 C2 UART Control Register 2 0x3 8 read-write 0 0xFF SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 S1 UART Status Register 1 0x4 8 read-only 0xC0 0xFF PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write 0 0xFF RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character detection is disabled. #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 C3 UART Control Register 3 0x6 8 read-write 0 0xFF PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 T8 Transmit Bit 8 6 1 read-write R8 Received Bit 8 7 1 read-only D UART Data Register 0x7 8 read-write 0 0xFF RT Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register 0 8 read-write MA1 UART Match Address Registers 1 0x8 8 read-write 0 0xFF MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write 0 0xFF MA Match Address 0 8 read-write C4 UART Control Register 4 0xA 8 read-write 0 0xFF BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. #1 C5 UART Control Register 5 0xB 8 read-write 0 0xFF RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 ED UART Extended Data Register 0xC 8 read-only 0 0xFF PARITYE The current received dataword contained in D and C3[R8] was received with a parity error. 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 NOISY The current received dataword contained in D and C3[R8] was received with noise. 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 MODEM UART Modem Register 0xD 8 read-write 0 0xFF TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) Ensure that C2[TE] is asserted before assertion of this bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. See Hardware flow control #1 PFIFO UART FIFO Parameters 0x10 8 read-write 0 0xFF RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 CFIFO UART FIFO Control Register 0x11 8 read-write 0 0xFF RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 RXOFE Receive FIFO Overflow Interrupt Enable 2 1 read-write 0 RXOF flag does not generate an interrupt to the host. #0 1 RXOF flag generates an interrupt to the host. #1 RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 SFIFO UART FIFO Status Register 0x12 8 read-write 0xC0 0xFF RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 RXOF Receiver Buffer Overflow Flag 2 1 read-write 0 No receive buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer overflow has occurred since the last time the flag was cleared. #1 RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write 0 0xFF TXWATER Transmit Watermark 0 8 read-write TCFIFO UART FIFO Transmit Count 0x14 8 read-only 0 0xFF TXCOUNT Transmit Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write 0x1 0xFF RXWATER Receive Watermark 0 8 read-write RCFIFO UART FIFO Receive Count 0x16 8 read-only 0 0xFF RXCOUNT Receive Counter 0 8 read-only CMP0 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP CMP0_ 0x40073000 0 0x6 registers CMP0 20 CR0 CMP Control Register 0 0 8 read-write 0 0xFF HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. #000 001 One sample must agree. The comparator output is simply sampled. #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 CR1 CMP Control Register 1 0x1 8 read-write 0 0xFF EN Comparator Module Enable 0 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. #0 1 CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. #1 COS Comparator Output Select 2 1 read-write 0 Set the filtered comparator output (CMPO) to equal COUT. #0 1 Set the unfiltered comparator output (CMPO) to equal COUTA. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 PMODE Power Mode Select 4 1 read-write 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 TRIGM Trigger Mode Enable 5 1 read-write 0 Trigger mode is disabled. #0 1 Trigger mode is enabled. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 SE Sample Enable 7 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 FPR CMP Filter Period Register 0x2 8 read-write 0 0xFF FILT_PER Filter Sample Period 0 8 read-write SCR CMP Status and Control Register 0x3 8 read-write 0 0xFF COUT Analog Comparator Output 0 1 read-only CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling-edge on COUT has not been detected. #0 1 Falling-edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising-edge on COUT has not been detected. #0 1 Rising-edge on COUT has occurred. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 DMAEN DMA Enable Control 6 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 DACCR DAC Control Register 0x4 8 read-write 0 0xFF VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference. #0 1 Vin2 is selected as resistor ladder network supply reference. #1 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 MUXCR MUX Control Register 0x5 8 read-write 0 0xFF MSEL Minus Input Mux Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input Mux Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 CMP1 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP CMP1_ 0x40073008 0 0x6 registers CMP1 21 CR0 CMP Control Register 0 0 8 read-write 0 0xFF HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. #000 001 One sample must agree. The comparator output is simply sampled. #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 CR1 CMP Control Register 1 0x1 8 read-write 0 0xFF EN Comparator Module Enable 0 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. #0 1 CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. #1 COS Comparator Output Select 2 1 read-write 0 Set the filtered comparator output (CMPO) to equal COUT. #0 1 Set the unfiltered comparator output (CMPO) to equal COUTA. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 PMODE Power Mode Select 4 1 read-write 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 TRIGM Trigger Mode Enable 5 1 read-write 0 Trigger mode is disabled. #0 1 Trigger mode is enabled. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 SE Sample Enable 7 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 FPR CMP Filter Period Register 0x2 8 read-write 0 0xFF FILT_PER Filter Sample Period 0 8 read-write SCR CMP Status and Control Register 0x3 8 read-write 0 0xFF COUT Analog Comparator Output 0 1 read-only CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling-edge on COUT has not been detected. #0 1 Falling-edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising-edge on COUT has not been detected. #0 1 Rising-edge on COUT has occurred. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 DMAEN DMA Enable Control 6 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 DACCR DAC Control Register 0x4 8 read-write 0 0xFF VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference. #0 1 Vin2 is selected as resistor ladder network supply reference. #1 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 MUXCR MUX Control Register 0x5 8 read-write 0 0xFF MSEL Minus Input Mux Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input Mux Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 LLWU Low leakage wakeup unit LLWU_ 0x4007C000 0 0x10 registers LLWU 7 PE1 LLWU Pin Enable 1 register 0 8 read-write 0 0xFF WUPE0 Wakeup Pin Enable For LLWU_P0 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE1 Wakeup Pin Enable For LLWU_P1 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE2 Wakeup Pin Enable For LLWU_P2 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE3 Wakeup Pin Enable For LLWU_P3 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE2 LLWU Pin Enable 2 register 0x1 8 read-write 0 0xFF WUPE4 Wakeup Pin Enable For LLWU_P4 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE5 Wakeup Pin Enable For LLWU_P5 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE6 Wakeup Pin Enable For LLWU_P6 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE7 Wakeup Pin Enable For LLWU_P7 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE3 LLWU Pin Enable 3 register 0x2 8 read-write 0 0xFF WUPE8 Wakeup Pin Enable For LLWU_P8 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE9 Wakeup Pin Enable For LLWU_P9 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE10 Wakeup Pin Enable For LLWU_P10 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE11 Wakeup Pin Enable For LLWU_P11 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE4 LLWU Pin Enable 4 register 0x3 8 read-write 0 0xFF WUPE12 Wakeup Pin Enable For LLWU_P12 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE13 Wakeup Pin Enable For LLWU_P13 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE14 Wakeup Pin Enable For LLWU_P14 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE15 Wakeup Pin Enable For LLWU_P15 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE5 LLWU Pin Enable 5 register 0x4 8 read-write 0 0xFF WUPE16 Wakeup Pin Enable For LLWU_P16 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE17 Wakeup Pin Enable For LLWU_P17 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE18 Wakeup Pin Enable For LLWU_P18 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE19 Wakeup Pin Enable For LLWU_P19 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE6 LLWU Pin Enable 6 register 0x5 8 read-write 0 0xFF WUPE20 Wakeup Pin Enable For LLWU_P20 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE21 Wakeup Pin Enable For LLWU_P21 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE22 Wakeup Pin Enable For LLWU_P22 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE23 Wakeup Pin Enable For LLWU_P23 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE7 LLWU Pin Enable 7 register 0x6 8 read-write 0 0xFF WUPE24 Wakeup Pin Enable For LLWU_P24 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE25 Wakeup Pin Enable For LLWU_P25 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE26 Wakeup Pin Enable For LLWU_P26 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE27 Wakeup Pin Enable For LLWU_P27 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE8 LLWU Pin Enable 8 register 0x7 8 read-write 0 0xFF WUPE28 Wakeup Pin Enable For LLWU_P28 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE29 Wakeup Pin Enable For LLWU_P29 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE30 Wakeup Pin Enable For LLWU_P30 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE31 Wakeup Pin Enable For LLWU_P31 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 ME LLWU Module Enable register 0x8 8 read-write 0 0xFF WUME0 Wakeup Module Enable For Module 0 0 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME1 Wakeup Module Enable for Module 1 1 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME2 Wakeup Module Enable For Module 2 2 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME3 Wakeup Module Enable For Module 3 3 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME4 Wakeup Module Enable For Module 4 4 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME5 Wakeup Module Enable For Module 5 5 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME6 Wakeup Module Enable For Module 6 6 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME7 Wakeup Module Enable For Module 7 7 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 PF1 LLWU Pin Flag 1 register 0x9 8 read-write 0 0xFF WUF0 Wakeup Flag For LLWU_P0 0 1 read-write 0 LLWU_P0 input was not a wakeup source #0 1 LLWU_P0 input was a wakeup source #1 WUF1 Wakeup Flag For LLWU_P1 1 1 read-write 0 LLWU_P1 input was not a wakeup source #0 1 LLWU_P1 input was a wakeup source #1 WUF2 Wakeup Flag For LLWU_P2 2 1 read-write 0 LLWU_P2 input was not a wakeup source #0 1 LLWU_P2 input was a wakeup source #1 WUF3 Wakeup Flag For LLWU_P3 3 1 read-write 0 LLWU_P3 input was not a wakeup source #0 1 LLWU_P3 input was a wakeup source #1 WUF4 Wakeup Flag For LLWU_P4 4 1 read-write 0 LLWU_P4 input was not a wakeup source #0 1 LLWU_P4 input was a wakeup source #1 WUF5 Wakeup Flag For LLWU_P5 5 1 read-write 0 LLWU_P5 input was not a wakeup source #0 1 LLWU_P5 input was a wakeup source #1 WUF6 Wakeup Flag For LLWU_P6 6 1 read-write 0 LLWU_P6 input was not a wakeup source #0 1 LLWU_P6 input was a wakeup source #1 WUF7 Wakeup Flag For LLWU_P7 7 1 read-write 0 LLWU_P7 input was not a wakeup source #0 1 LLWU_P7 input was a wakeup source #1 PF2 LLWU Pin Flag 2 register 0xA 8 read-write 0 0xFF WUF8 Wakeup Flag For LLWU_P8 0 1 read-write 0 LLWU_P8 input was not a wakeup source #0 1 LLWU_P8 input was a wakeup source #1 WUF9 Wakeup Flag For LLWU_P9 1 1 read-write 0 LLWU_P9 input was not a wakeup source #0 1 LLWU_P9 input was a wakeup source #1 WUF10 Wakeup Flag For LLWU_P10 2 1 read-write 0 LLWU_P10 input was not a wakeup source #0 1 LLWU_P10 input was a wakeup source #1 WUF11 Wakeup Flag For LLWU_P11 3 1 read-write 0 LLWU_P11 input was not a wakeup source #0 1 LLWU_P11 input was a wakeup source #1 WUF12 Wakeup Flag For LLWU_P12 4 1 read-write 0 LLWU_P12 input was not a wakeup source #0 1 LLWU_P12 input was a wakeup source #1 WUF13 Wakeup Flag For LLWU_P13 5 1 read-write 0 LLWU_P13 input was not a wakeup source #0 1 LLWU_P13 input was a wakeup source #1 WUF14 Wakeup Flag For LLWU_P14 6 1 read-write 0 LLWU_P14 input was not a wakeup source #0 1 LLWU_P14 input was a wakeup source #1 WUF15 Wakeup Flag For LLWU_P15 7 1 read-write 0 LLWU_P15 input was not a wakeup source #0 1 LLWU_P15 input was a wakeup source #1 PF3 LLWU Pin Flag 3 register 0xB 8 read-write 0 0xFF WUF16 Wakeup Flag For LLWU_P16 0 1 read-write 0 LLWU_P16 input was not a wakeup source #0 1 LLWU_P16 input was a wakeup source #1 WUF17 Wakeup Flag For LLWU_P17 1 1 read-write 0 LLWU_P17 input was not a wakeup source #0 1 LLWU_P17 input was a wakeup source #1 WUF18 Wakeup Flag For LLWU_P18 2 1 read-write 0 LLWU_P18 input was not a wakeup source #0 1 LLWU_P18 input was a wakeup source #1 WUF19 Wakeup Flag For LLWU_P19 3 1 read-write 0 LLWU_P19 input was not a wakeup source #0 1 LLWU_P19 input was a wakeup source #1 WUF20 Wakeup Flag For LLWU_P20 4 1 read-write 0 LLWU_P20 input was not a wakeup source #0 1 LLWU_P20 input was a wakeup source #1 WUF21 Wakeup Flag For LLWU_P21 5 1 read-write 0 LLWU_P21 input was not a wakeup source #0 1 LLWU_P21 input was a wakeup source #1 WUF22 Wakeup Flag For LLWU_P22 6 1 read-write 0 LLWU_P22 input was not a wakeup source #0 1 LLWU_P22 input was a wakeup source #1 WUF23 Wakeup Flag For LLWU_P23 7 1 read-write 0 LLWU_P23 input was not a wakeup source #0 1 LLWU_P23 input was a wakeup source #1 PF4 LLWU Pin Flag 4 register 0xC 8 read-write 0 0xFF WUF24 Wakeup Flag For LLWU_P24 0 1 read-write 0 LLWU_P24 input was not a wakeup source #0 1 LLWU_P24 input was a wakeup source #1 WUF25 Wakeup Flag For LLWU_P25 1 1 read-write 0 LLWU_P25 input was not a wakeup source #0 1 LLWU_P25 input was a wakeup source #1 WUF26 Wakeup Flag For LLWU_P26 2 1 read-write 0 LLWU_P26 input was not a wakeup source #0 1 LLWU_P26 input was a wakeup source #1 WUF27 Wakeup Flag For LLWU_P27 3 1 read-write 0 LLWU_P27 input was not a wakeup source #0 1 LLWU_P27 input was a wakeup source #1 WUF28 Wakeup Flag For LLWU_P28 4 1 read-write 0 LLWU_P28 input was not a wakeup source #0 1 LLWU_P28 input was a wakeup source #1 WUF29 Wakeup Flag For LLWU_P29 5 1 read-write 0 LLWU_P29 input was not a wakeup source #0 1 LLWU_P29 input was a wakeup source #1 WUF30 Wakeup Flag For LLWU_P30 6 1 read-write 0 LLWU_P30 input was not a wakeup source #0 1 LLWU_P30 input was a wakeup source #1 WUF31 Wakeup Flag For LLWU_P31 7 1 read-write 0 LLWU_P31 input was not a wakeup source #0 1 LLWU_P31 input was a wakeup source #1 MF5 LLWU Module Flag 5 register 0xD 8 read-only 0 0xFF MWUF0 Wakeup flag For module 0 0 1 read-only 0 Module 0 input was not a wakeup source #0 1 Module 0 input was a wakeup source #1 MWUF1 Wakeup flag For module 1 1 1 read-only 0 Module 1 input was not a wakeup source #0 1 Module 1 input was a wakeup source #1 MWUF2 Wakeup flag For module 2 2 1 read-only 0 Module 2 input was not a wakeup source #0 1 Module 2 input was a wakeup source #1 MWUF3 Wakeup flag For module 3 3 1 read-only 0 Module 3 input was not a wakeup source #0 1 Module 3 input was a wakeup source #1 MWUF4 Wakeup flag For module 4 4 1 read-only 0 Module 4 input was not a wakeup source #0 1 Module 4 input was a wakeup source #1 MWUF5 Wakeup flag For module 5 5 1 read-only 0 Module 5 input was not a wakeup source #0 1 Module 5 input was a wakeup source #1 MWUF6 Wakeup flag For module 6 6 1 read-only 0 Module 6 input was not a wakeup source #0 1 Module 6 input was a wakeup source #1 MWUF7 Wakeup flag For module 7 7 1 read-only 0 Module 7 input was not a wakeup source #0 1 Module 7 input was a wakeup source #1 FILT1 LLWU Pin Filter 1 register 0xE 8 read-write 0 0xFF FILTSEL Filter Pin Select 0 5 read-write 00000 Select LLWU_P0 for filter #00000 11111 Select LLWU_P31 for filter #11111 FILTE Digital Filter On External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 1 was not a wakeup source #0 1 Pin Filter 1 was a wakeup source #1 FILT2 LLWU Pin Filter 2 register 0xF 8 read-write 0 0xFF FILTSEL Filter Pin Select 0 5 read-write 00000 Select LLWU_P0 for filter #00000 11111 Select LLWU_P31 for filter #11111 FILTE Digital Filter On External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 2 was not a wakeup source #0 1 Pin Filter 2 was a wakeup source #1 PMC Power Management Controller PMC_ 0x4007D000 0 0x3 registers LVD_LVW 6 LVDSC1 Low Voltage Detect Status And Control 1 register 0 8 read-write 0x10 0xFF LVDV Low-Voltage Detect Voltage Select 0 2 read-write 00 Low trip point selected (V LVD = V LVDL ) #00 01 High trip point selected (V LVD = V LVDH ) #01 LVDRE Low-Voltage Detect Reset Enable 4 1 read-write 0 LVDF does not generate hardware resets #0 1 Force an MCU reset when LVDF = 1 #1 LVDIE Low-Voltage Detect Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVDF = 1 #1 LVDACK Low-Voltage Detect Acknowledge 6 1 write-only LVDF Low-Voltage Detect Flag 7 1 read-only 0 Low-voltage event not detected #0 1 Low-voltage event detected #1 LVDSC2 Low Voltage Detect Status And Control 2 register 0x1 8 read-write 0 0xFF LVWV Low-Voltage Warning Voltage Select 0 2 read-write 00 Low trip point selected (VLVW = VLVW1) #00 01 Mid 1 trip point selected (VLVW = VLVW2) #01 10 Mid 2 trip point selected (VLVW = VLVW3) #10 11 High trip point selected (VLVW = VLVW4) #11 LVWIE Low-Voltage Warning Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVWF = 1 #1 LVWACK Low-Voltage Warning Acknowledge 6 1 write-only LVWF Low-Voltage Warning Flag 7 1 read-only 0 Low-voltage warning event not detected #0 1 Low-voltage warning event detected #1 REGSC Regulator Status And Control register 0x2 8 read-write 0x4 0xFF BGBE Bandgap Buffer Enable 0 1 read-write 0 Bandgap buffer not enabled #0 1 Bandgap buffer enabled #1 REGONS Regulator In Run Regulation Status 2 1 read-only 0 Regulator is in stop regulation or in transition to/from it #0 1 Regulator is in run regulation #1 ACKISO Acknowledge Isolation 3 1 read-write 0 Peripherals and I/O pads are in normal run state. #0 1 Certain peripherals and I/O pads are in an isolated and latched state. #1 BGEN Bandgap Enable In VLPx Operation 4 1 read-write 0 Bandgap voltage reference is disabled in VLPx , and VLLSx modes. #0 1 Bandgap voltage reference is enabled in VLPx , and VLLSx modes. #1 SMC System Mode Controller SMC_ 0x4007E000 0 0x4 registers PMPROT Power Mode Protection register 0 8 read-write 0 0xFF AVLLS Allow Very-Low-Leakage Stop Mode 1 1 read-write 0 Any VLLSx mode is not allowed #0 1 Any VLLSx mode is allowed #1 AVLP Allow Very-Low-Power Modes 5 1 read-write 0 VLPR, VLPW, and VLPS are not allowed. #0 1 VLPR, VLPW, and VLPS are allowed. #1 PMCTRL Power Mode Control register 0x1 8 read-write 0 0xFF STOPM Stop Mode Control 0 3 read-write 000 Normal Stop (STOP) #000 010 Very-Low-Power Stop (VLPS) #010 100 Very-Low-Leakage Stop (VLLSx) #100 110 Reseved #110 STOPA Stop Aborted 3 1 read-only 0 The previous stop mode entry was successsful. #0 1 The previous stop mode entry was aborted. #1 RUNM Run Mode Control 5 2 read-write 00 Normal Run mode (RUN) #00 10 Very-Low-Power Run mode (VLPR) #10 STOPCTRL Stop Control Register 0x2 8 read-write 0x3 0xFF VLLSM VLLS Mode Control 0 3 read-write 000 VLLS0 #000 001 VLLS1 #001 011 VLLS3 #011 PORPO POR Power Option 5 1 read-write 0 POR detect circuit is enabled in VLLS0 #0 1 POR detect circuit is disabled in VLLS0 #1 PSTOPO Partial Stop Option 6 2 read-write 00 STOP - Normal Stop mode #00 01 PSTOP1 - Partial Stop with both system and bus clocks disabled #01 10 PSTOP2 - Partial Stop with system clock disabled and bus clock enabled #10 PMSTAT Power Mode Status register 0x3 8 read-only 0x1 0xFF PMSTAT Power Mode Status 0 8 read-only RCM Reset Control Module RCM_ 0x4007F000 0 0x6 registers SRS0 System Reset Status Register 0 0 8 read-only 0x82 0xFF WAKEUP Low Leakage Wakeup Reset 0 1 read-only 0 Reset not caused by LLWU module wakeup source #0 1 Reset caused by LLWU module wakeup source #1 LVD Low-Voltage Detect Reset 1 1 read-only 0 Reset not caused by LVD trip or POR #0 1 Reset caused by LVD trip or POR #1 LOC Loss-of-Clock Reset 2 1 read-only 0 Reset not caused by a loss of external clock. #0 1 Reset caused by a loss of external clock. #1 WDOG Watchdog 5 1 read-only 0 Reset not caused by watchdog timeout #0 1 Reset caused by watchdog timeout #1 PIN External Reset Pin 6 1 read-only 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 POR Power-On Reset 7 1 read-only 0 Reset not caused by POR #0 1 Reset caused by POR #1 SRS1 System Reset Status Register 1 0x1 8 read-only 0 0xFF LOCKUP Core Lockup 1 1 read-only 0 Reset not caused by core LOCKUP event #0 1 Reset caused by core LOCKUP event #1 SW Software 2 1 read-only 0 Reset not caused by software setting of SYSRESETREQ bit #0 1 Reset caused by software setting of SYSRESETREQ bit #1 MDM_AP MDM-AP System Reset Request 3 1 read-only 0 Reset not caused by host debugger system setting of the System Reset Request bit #0 1 Reset caused by host debugger system setting of the System Reset Request bit #1 SACKERR Stop Mode Acknowledge Error Reset 5 1 read-only 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode #0 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode #1 RPFC Reset Pin Filter Control register 0x4 8 read-write 0 0xFF RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes 0 2 read-write 00 All filtering disabled #00 01 Bus clock filter enabled for normal operation #01 10 LPO clock filter enabled for normal operation #10 RSTFLTSS Reset Pin Filter Select in Stop Mode 2 1 read-write 0 All filtering disabled #0 1 LPO clock filter enabled #1 RPFW Reset Pin Filter Width register 0x5 8 read-write 0 0xFF RSTFLTSEL Reset Pin Filter Bus Clock Select 0 5 read-write 00000 Bus clock filter count is 1 #00000 00001 Bus clock filter count is 2 #00001 00010 Bus clock filter count is 3 #00010 00011 Bus clock filter count is 4 #00011 00100 Bus clock filter count is 5 #00100 00101 Bus clock filter count is 6 #00101 00110 Bus clock filter count is 7 #00110 00111 Bus clock filter count is 8 #00111 01000 Bus clock filter count is 9 #01000 01001 Bus clock filter count is 10 #01001 01010 Bus clock filter count is 11 #01010 01011 Bus clock filter count is 12 #01011 01100 Bus clock filter count is 13 #01100 01101 Bus clock filter count is 14 #01101 01110 Bus clock filter count is 15 #01110 01111 Bus clock filter count is 16 #01111 10000 Bus clock filter count is 17 #10000 10001 Bus clock filter count is 18 #10001 10010 Bus clock filter count is 19 #10010 10011 Bus clock filter count is 20 #10011 10100 Bus clock filter count is 21 #10100 10101 Bus clock filter count is 22 #10101 10110 Bus clock filter count is 23 #10110 10111 Bus clock filter count is 24 #10111 11000 Bus clock filter count is 25 #11000 11001 Bus clock filter count is 26 #11001 11010 Bus clock filter count is 27 #11010 11011 Bus clock filter count is 28 #11011 11100 Bus clock filter count is 29 #11100 11101 Bus clock filter count is 30 #11101 11110 Bus clock filter count is 31 #11110 11111 Bus clock filter count is 32 #11111 GPIOA General Purpose Input/Output GPIO GPIOA_ 0x400FF000 0 0x18 registers PORTA 30 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOB General Purpose Input/Output GPIO GPIOB_ 0x400FF040 0 0x18 registers PORTB_PORTC_PORTD_PORTE 31 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOC General Purpose Input/Output GPIO GPIOC_ 0x400FF080 0 0x18 registers PORTB_PORTC_PORTD_PORTE 31 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOD General Purpose Input/Output GPIO GPIOD_ 0x400FF0C0 0 0x18 registers PORTB_PORTC_PORTD_PORTE 31 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOE General Purpose Input/Output GPIO GPIOE_ 0x400FF100 0 0x18 registers PORTB_PORTC_PORTD_PORTE 31 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 MTB Micro Trace Buffer MTB_ 0xF0000000 0 0x1000 registers POSITION MTB Position Register 0 32 read-write 0 0x3 WRAP WRAP 2 1 read-write POINTER Trace Packet Address Pointer[28:0] 3 29 read-write MASTER MTB Master Register 0x4 32 read-write 0x80 0xFFFFFFE0 MASK Mask 0 5 read-write TSTARTEN Trace Start Input Enable 5 1 read-write TSTOPEN Trace Stop Input Enable 6 1 read-write SFRWPRIV Special Function Register Write Privilege 7 1 read-write RAMPRIV RAM Privilege 8 1 read-write HALTREQ Halt Request 9 1 read-write EN Main Trace Enable 31 1 read-write FLOW MTB Flow Register 0x8 32 read-write 0 0x4 AUTOSTOP AUTOSTOP 0 1 read-write AUTOHALT AUTOHALT 1 1 read-write WATERMARK WATERMARK[28:0] 3 29 read-write BASE MTB Base Register 0xC 32 read-only 0 0 BASEADDR BASEADDR 0 32 read-only MODECTRL Integration Mode Control Register 0xF00 32 read-only 0 0xFFFFFFFF MODECTRL MODECTRL 0 32 read-only TAGSET Claim TAG Set Register 0xFA0 32 read-only 0 0xFFFFFFFF TAGSET TAGSET 0 32 read-only TAGCLEAR Claim TAG Clear Register 0xFA4 32 read-only 0 0xFFFFFFFF TAGCLEAR TAGCLEAR 0 32 read-only LOCKACCESS Lock Access Register 0xFB0 32 read-only 0 0xFFFFFFFF LOCKACCESS Hardwired to 0x0000_0000 0 32 read-only LOCKSTAT Lock Status Register 0xFB4 32 read-only 0 0xFFFFFFFF LOCKSTAT LOCKSTAT 0 32 read-only AUTHSTAT Authentication Status Register 0xFB8 32 read-only 0 0xFFFFFFFF BIT0 Connected to DBGEN. 0 1 read-only BIT1 BIT1 1 1 read-only BIT2 BIT2 2 1 read-only BIT3 BIT3 3 1 read-only DEVICEARCH Device Architecture Register 0xFBC 32 read-only 0x47700A31 0xFFFFFFFF DEVICEARCH DEVICEARCH 0 32 read-only DEVICECFG Device Configuration Register 0xFC8 32 read-only 0 0xFFFFFFFF DEVICECFG DEVICECFG 0 32 read-only DEVICETYPID Device Type Identifier Register 0xFCC 32 read-only 0x31 0xFFFFFFFF DEVICETYPID DEVICETYPID 0 32 read-only 8 0x4 4,5,6,7,0,1,2,3 PERIPHID%s Peripheral ID Register 0xFD0 32 read-only 0 0 PERIPHID PERIPHID 0 32 read-only 4 0x4 0,1,2,3 COMPID%s Component ID Register 0xFF0 32 read-only 0 0 COMPID Component ID 0 32 read-only MTBDWT MTB data watchpoint and trace MTBDWT_ 0xF0001000 0 0x1000 registers CTRL MTB DWT Control Register 0 32 read-only 0x2F000000 0xFFFFFFFF DWTCFGCTRL DWT configuration controls 0 28 read-only NUMCMP Number of comparators 28 4 read-only 2 0x10 0,1 COMP%s MTB_DWT Comparator Register 0x20 32 read-write 0 0xFFFFFFFF COMP Reference value for comparison 0 32 read-write 2 0x10 0,1 MASK%s MTB_DWT Comparator Mask Register 0x24 32 read-write 0 0xFFFFFFFF MASK MASK 0 5 read-write FCT0 MTB_DWT Comparator Function Register 0 0x28 32 read-write 0 0xFFFFFFFF FUNCTION Function 0 4 read-write 0000 Disabled. #0000 0100 Instruction fetch. #0100 0101 Data operand read. #0101 0110 Data operand write. #0110 0111 Data operand (read + write). #0111 DATAVMATCH Data Value Match 8 1 read-write 0 Perform address comparison. #0 1 Perform data value comparison. #1 DATAVSIZE Data Value Size 10 2 read-write 00 Byte. #00 01 Halfword. #01 10 Word. #10 11 Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. #11 DATAVADDR0 Data Value Address 0 12 4 read-write MATCHED Comparator match 24 1 read-only 0 No match. #0 1 Match occurred. #1 FCT1 MTB_DWT Comparator Function Register 1 0x38 32 read-write 0 0xFFFFFFFF FUNCTION Function 0 4 read-write 0000 Disabled. #0000 0100 Instruction fetch. #0100 0101 Data operand read. #0101 0110 Data operand write. #0110 0111 Data operand (read + write). #0111 MATCHED Comparator match 24 1 read-only 0 No match. #0 1 Match occurred. #1 TBCTRL MTB_DWT Trace Buffer Control Register 0x200 32 read-write 0x20000000 0xFFFFFFFF ACOMP0 Action based on Comparator 0 match 0 1 read-write 0 Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED]. #0 1 Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED]. #1 ACOMP1 Action based on Comparator 1 match 1 1 read-write 0 Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED]. #0 1 Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED]. #1 NUMCOMP Number of Comparators 28 4 read-only DEVICECFG Device Configuration Register 0xFC8 32 read-only 0 0xFFFFFFFF DEVICECFG DEVICECFG 0 32 read-only DEVICETYPID Device Type Identifier Register 0xFCC 32 read-only 0x4 0xFFFFFFFF DEVICETYPID DEVICETYPID 0 32 read-only 8 0x4 4,5,6,7,0,1,2,3 PERIPHID%s Peripheral ID Register 0xFD0 32 read-only 0 0 PERIPHID PERIPHID 0 32 read-only 4 0x4 0,1,2,3 COMPID%s Component ID Register 0xFF0 32 read-only 0 0 COMPID Component ID 0 32 read-only ROM System ROM ROM_ 0xF0002000 0 0x1000 registers 3 0x4 0,1,2 ENTRY%s Entry 0 32 read-only 0 0 ENTRY ENTRY 0 32 read-only TABLEMARK End of Table Marker Register 0xC 32 read-only 0 0xFFFFFFFF MARK MARK 0 32 read-only SYSACCESS System Access Register 0xFCC 32 read-only 0x1 0xFFFFFFFF SYSACCESS SYSACCESS 0 32 read-only 8 0x4 4,5,6,7,0,1,2,3 PERIPHID%s Peripheral ID Register 0xFD0 32 read-only 0 0 PERIPHID PERIPHID 0 32 read-only 4 0x4 0,1,2,3 COMPID%s Component ID Register 0xFF0 32 read-only 0 0 COMPID Component ID 0 32 read-only MCM Core Platform Miscellaneous Control Module MCM_ 0xF0003000 0x8 0x3C registers PLASC Crossbar Switch (AXBS) Slave Configuration 0x8 16 read-only 0x7 0xFFFF ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 8 read-only 0 A bus slave connection to AXBS input port n is absent. #0 1 A bus slave connection to AXBS input port n is present. #1 PLAMC Crossbar Switch (AXBS) Master Configuration 0xA 16 read-only 0x5 0xFFFF AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 8 read-only 0 A bus master connection to AXBS input port n is absent #0 1 A bus master connection to AXBS input port n is present #1 PLACR Platform Control Register 0xC 32 read-write 0 0xFFFFFFFF ARB Arbitration select 9 1 read-write 0 Fixed-priority arbitration for the crossbar masters #0 1 Round-robin arbitration for the crossbar masters #1 CFCC Clear Flash Controller Cache 10 1 write-only DFCDA Disable Flash Controller Data Caching 11 1 read-write 0 Enable flash controller data caching #0 1 Disable flash controller data caching. #1 DFCIC Disable Flash Controller Instruction Caching 12 1 read-write 0 Enable flash controller instruction caching. #0 1 Disable flash controller instruction caching. #1 DFCC Disable Flash Controller Cache 13 1 read-write 0 Enable flash controller cache. #0 1 Disable flash controller cache. #1 EFDS Enable Flash Data Speculation 14 1 read-write 0 Disable flash data speculation. #0 1 Enable flash data speculation. #1 DFCS Disable Flash Controller Speculation 15 1 read-write 0 Enable flash controller speculation. #0 1 Disable flash controller speculation. #1 ESFC Enable Stalling Flash Controller 16 1 read-write 0 Disable stalling flash controller when flash is busy. #0 1 Enable stalling flash controller when flash is busy. #1 CPO Compute Operation Control Register 0x40 32 read-write 0 0xFFFFFFFF CPOREQ Compute Operation Request 0 1 read-write 0 Request is cleared. #0 1 Request Compute Operation. #1 CPOACK Compute Operation Acknowledge 1 1 read-only 0 Compute operation entry has not completed or compute operation exit has completed. #0 1 Compute operation entry has completed or compute operation exit has not completed. #1 CPOWOI Compute Operation Wake-up on Interrupt 2 1 read-write 0 No effect. #0 1 When set, the CPOREQ is cleared on any interrupt or exception vector fetch. #1 MMDVSQ Divide and Square Root MMDVSQ_ 0xF0004000 0 0x14 registers DEND Dividend Register 0 32 read-write 0 0 DIVIDEND Dividend 0 32 read-write DSOR Divisor Register 0x4 32 read-write 0 0 DIVISOR Divisor 0 32 read-write CSR Control/Status Register 0x8 32 read-write 0 0x9FFFFFFF SRT Start 0 1 write-only 0 No operation initiated #0 1 If CSR[DFS] = 1, then initiate a divide calculation, else ignore #1 USGN Unsigned calculation 1 1 read-write 0 Perform a signed divide #0 1 Perform an unsigned divide #1 REM REMainder calculation 2 1 read-write 0 Return the quotient in the RES for the divide calculation #0 1 Return the remainder in the RES for the divide calculation #1 DZE Divide-by-Zero-Enable 3 1 read-write 0 Reads of the RES register return the register contents #0 1 If CSR[DZ] = 1, an attempted read of RES register is error terminated to signal a divide-by-zero, else the register contents are returned #1 DZ Divide-by-Zero 4 1 read-only 0 The last divide operation had a non-zero divisor, that is, DSOR != 0 #0 1 The last divide operation had a zero divisor, that is, DSOR = 0 #1 DFS Disable Fast Start 5 1 read-write 0 A divide operation is initiated by a write to the DSOR register #0 1 A divide operation is initiated by a write to the CSR register with CSR[SRT] = 1 #1 SQRT SQUARE ROOT 29 1 read-only 0 Current or last MMDVSQ operation was not a square root #0 1 Current or last MMDVSQ operation was a square root #1 DIV DIVIDE 30 1 read-only 0 Current or last MMDVSQ operation was not a divide #0 1 Current or last MMDVSQ operation was a divide #1 BUSY BUSY 31 1 read-only 0 MMDVSQ is idle #0 1 MMDVSQ is busy performing a divide or square root calculation #1 RES Result Register 0xC 32 read-write 0 0 RESULT Result 0 32 read-write RCND Radicand Register 0x10 32 read-write 0 0 RADICAND Radicand 0 32 read-write FGPIOA General Purpose Input/Output FGPIO FGPIOA_ 0xF8000000 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 FGPIOB General Purpose Input/Output FGPIO FGPIOB_ 0xF8000040 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 FGPIOC General Purpose Input/Output FGPIO FGPIOC_ 0xF8000080 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 FGPIOD General Purpose Input/Output FGPIO FGPIOD_ 0xF80000C0 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 FGPIOE General Purpose Input/Output FGPIO FGPIOE_ 0xF8000100 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1