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Freescale Kinetis_L MKL14Z4 1.6 MKL14Z4 Freescale Microcontroller Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. 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CM0PLUS r0p0 little false false false true 2 false 8 32 FTFA_FlashConfig Flash configuration field NV_ 0x400 0 0xE registers BACKKEY3 Backdoor Comparison Key 3. 0 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY2 Backdoor Comparison Key 2. 0x1 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY1 Backdoor Comparison Key 1. 0x2 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY0 Backdoor Comparison Key 0. 0x3 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY7 Backdoor Comparison Key 7. 0x4 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY6 Backdoor Comparison Key 6. 0x5 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY5 Backdoor Comparison Key 5. 0x6 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY4 Backdoor Comparison Key 4. 0x7 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only FPROT3 Non-volatile P-Flash Protection 1 - Low Register 0x8 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FPROT2 Non-volatile P-Flash Protection 1 - High Register 0x9 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FPROT1 Non-volatile P-Flash Protection 0 - Low Register 0xA 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FPROT0 Non-volatile P-Flash Protection 0 - High Register 0xB 8 read-only 0xFF 0xFF PROT P-Flash Region Protect 0 8 read-only FSEC Non-volatile Flash Security Register 0xC 8 read-only 0xFF 0xFF SEC Flash Security 0 2 read-only 10 MCU security status is unsecure #10 11 MCU security status is secure #11 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 10 Freescale factory access denied #10 11 Freescale factory access granted #11 MEEN no description available 4 2 read-only 10 Mass erase is disabled #10 11 Mass erase is enabled #11 KEYEN Backdoor Key Security Enable 6 2 read-only 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 FOPT Non-volatile Flash Option Register 0xD 8 read-only 0xFF 0xFF LPBOOT0 no description available 0 1 read-only 00 Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. #0 01 Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. #1 NMI_DIS no description available 2 1 read-only 00 NMI interrupts are always blocked #0 01 NMI_b pin/interrupts reset default to enabled #1 RESET_PIN_CFG no description available 3 1 read-only 00 RESET pin is disabled following a POR and cannot be enabled as reset function #0 01 RESET_b pin is dedicated #1 LPBOOT1 no description available 4 1 read-only 00 Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. #0 01 Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. #1 FAST_INIT no description available 5 1 read-only 00 Slower initialization #0 01 Fast Initialization #1 DMA DMA Controller DMA_ 0x40008000 0x100 0x40 registers DMA0 0 DMA1 1 DMA2 2 DMA3 3 SAR0 Source Address Register 0x100 32 read-write 0 0xFFFFFFFF SAR Each SAR contains the byte address used by the DMA controller to read data 0 32 read-write DAR0 Destination Address Register 0x104 32 read-write 0 0xFFFFFFFF DAR Each DAR contains the byte address used by the DMA controller to write data 0 32 read-write DSR_BCR0 DMA Status Register / Byte Count Register 0x108 32 read-write 0 0xFFFFFFFF BCR This field contains the number of bytes yet to be transferred for a given block 0 24 read-write DONE Transactions done 24 1 read-write 0 DMA transfer is not yet complete. Writing a 0 has no effect. #0 1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits. #1 BSY Busy 25 1 read-only 0 DMA channel is inactive. Cleared when the DMA has finished the last transaction. #0 1 BSY is set the first time the channel is enabled after a transfer is initiated. #1 REQ Request 26 1 read-only 0 No request is pending or the channel is currently active. Cleared when the channel is selected. #0 1 The DMA channel has a transfer remaining and the channel is not selected. #1 BED Bus error on destination 28 1 read-only 0 No bus error occurred. #0 1 The DMA channel terminated with a bus error during the write portion of a transfer. #1 BES Bus error on source 29 1 read-only 0 No bus error occurred. #0 1 The DMA channel terminated with a bus error during the read portion of a transfer. #1 CE Configuration error 30 1 read-only 0 No configuration error exists. #0 1 A configuration error has occurred. #1 DSR0 DMA_DSR0 register. 0x10B 8 read-write 0 0xFF DCR0 DMA Control Register 0x10C 32 read-write 0 0xFFFFFFFF LCH2 Link channel 2 0 2 read-write 00 DMA Channel 0 #00 01 DMA Channel 1 #01 10 DMA Channel 2 #10 11 DMA Channel 3 #11 LCH1 Link channel 1 2 2 read-write 00 DMA Channel 0 #00 01 DMA Channel 1 #01 10 DMA Channel 2 #10 11 DMA Channel 3 #11 LINKCC Link channel control 4 2 read-write 00 No channel-to-channel linking #00 01 Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to zero #01 10 Perform a link to channel LCH1 after each cycle-steal transfer #10 11 Perform a link to channel LCH1 after the BCR decrements to zero #11 D_REQ Disable request 7 1 read-write 0 ERQ bit is not affected. #0 1 ERQ bit is cleared when the BCR is exhausted. #1 DMOD Destination address modulo 8 4 read-write 0000 Buffer disabled #0000 0001 Circular buffer size is 16 bytes #0001 0010 Circular buffer size is 32 bytes #0010 0011 Circular buffer size is 64 bytes #0011 0100 Circular buffer size is 128 bytes #0100 0101 Circular buffer size is 256 bytes #0101 0110 Circular buffer size is 512 bytes #0110 0111 Circular buffer size is 1 KB #0111 1000 Circular buffer size is 2 KB #1000 1001 Circular buffer size is 4 KB #1001 1010 Circular buffer size is 8 KB #1010 1011 Circular buffer size is 16 KB #1011 1100 Circular buffer size is 32 KB #1100 1101 Circular buffer size is 64 KB #1101 1110 Circular buffer size is 128 KB #1110 1111 Circular buffer size is 256 KB #1111 SMOD Source address modulo 12 4 read-write 0000 Buffer disabled #0000 0001 Circular buffer size is 16 bytes #0001 0010 Circular buffer size is 32 bytes #0010 0011 Circular buffer size is 64 bytes #0011 0100 Circular buffer size is 128 bytes #0100 0101 Circular buffer size is 256 bytes #0101 0110 Circular buffer size is 512 bytes #0110 0111 Circular buffer size is 1 KB #0111 1000 Circular buffer size is 2 KB #1000 1001 Circular buffer size is 4 KB #1001 1010 Circular buffer size is 8 KB #1010 1011 Circular buffer size is 16 KB #1011 1100 Circular buffer size is 32 KB #1100 1101 Circular buffer size is 64 KB #1101 1110 Circular buffer size is 128 KB #1110 1111 Circular buffer size is 256 KB #1111 START Start transfer 16 1 write-only 0 DMA inactive #0 1 The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0. #1 DSIZE Destination size 17 2 read-write 00 32-bit #00 01 8-bit #01 10 16-bit #10 11 Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) #11 DINC Destination increment 19 1 read-write 0 No change to the DAR after a successful transfer. #0 1 The DAR increments by 1, 2, 4 depending upon the size of the transfer. #1 SSIZE Source size 20 2 read-write 00 32-bit #00 01 8-bit #01 10 16-bit #10 11 Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) #11 SINC Source increment 22 1 read-write 0 No change to SAR after a successful transfer. #0 1 The SAR increments by 1, 2, 4 as determined by the transfer size. #1 EADREQ Enable asynchronous DMA requests 23 1 read-write 0 Disabled #0 1 Enabled #1 AA Auto-align 28 1 read-write 0 Auto-align disabled #0 1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC. #1 CS Cycle steal 29 1 read-write 0 DMA continuously makes read/write transfers until the BCR decrements to 0. #0 1 Forces a single read/write transfer per request. #1 ERQ Enable peripheral request 30 1 read-write 0 Peripheral request is ignored. #0 1 Enables peripheral request, defined by the appropriate REQC[DMACn] field, to initiate transfer. A software-initiated request (setting the START bit) is always enabled. #1 EINT Enable interrupt on completion of transfer 31 1 read-write 0 No interrupt is generated. #0 1 Interrupt signal is enabled. #1 SAR1 Source Address Register 0x110 32 read-write 0 0xFFFFFFFF SAR Each SAR contains the byte address used by the DMA controller to read data 0 32 read-write DAR1 Destination Address Register 0x114 32 read-write 0 0xFFFFFFFF DAR Each DAR contains the byte address used by the DMA controller to write data 0 32 read-write DSR_BCR1 DMA Status Register / Byte Count Register 0x118 32 read-write 0 0xFFFFFFFF BCR This field contains the number of bytes yet to be transferred for a given block 0 24 read-write DONE Transactions done 24 1 read-write 0 DMA transfer is not yet complete. Writing a 0 has no effect. #0 1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits. #1 BSY Busy 25 1 read-only 0 DMA channel is inactive. Cleared when the DMA has finished the last transaction. #0 1 BSY is set the first time the channel is enabled after a transfer is initiated. #1 REQ Request 26 1 read-only 0 No request is pending or the channel is currently active. Cleared when the channel is selected. #0 1 The DMA channel has a transfer remaining and the channel is not selected. #1 BED Bus error on destination 28 1 read-only 0 No bus error occurred. #0 1 The DMA channel terminated with a bus error during the write portion of a transfer. #1 BES Bus error on source 29 1 read-only 0 No bus error occurred. #0 1 The DMA channel terminated with a bus error during the read portion of a transfer. #1 CE Configuration error 30 1 read-only 0 No configuration error exists. #0 1 A configuration error has occurred. #1 DSR1 DMA_DSR1 register. 0x11B 8 read-write 0 0xFF DCR1 DMA Control Register 0x11C 32 read-write 0 0xFFFFFFFF LCH2 Link channel 2 0 2 read-write 00 DMA Channel 0 #00 01 DMA Channel 1 #01 10 DMA Channel 2 #10 11 DMA Channel 3 #11 LCH1 Link channel 1 2 2 read-write 00 DMA Channel 0 #00 01 DMA Channel 1 #01 10 DMA Channel 2 #10 11 DMA Channel 3 #11 LINKCC Link channel control 4 2 read-write 00 No channel-to-channel linking #00 01 Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to zero #01 10 Perform a link to channel LCH1 after each cycle-steal transfer #10 11 Perform a link to channel LCH1 after the BCR decrements to zero #11 D_REQ Disable request 7 1 read-write 0 ERQ bit is not affected. #0 1 ERQ bit is cleared when the BCR is exhausted. #1 DMOD Destination address modulo 8 4 read-write 0000 Buffer disabled #0000 0001 Circular buffer size is 16 bytes #0001 0010 Circular buffer size is 32 bytes #0010 0011 Circular buffer size is 64 bytes #0011 0100 Circular buffer size is 128 bytes #0100 0101 Circular buffer size is 256 bytes #0101 0110 Circular buffer size is 512 bytes #0110 0111 Circular buffer size is 1 KB #0111 1000 Circular buffer size is 2 KB #1000 1001 Circular buffer size is 4 KB #1001 1010 Circular buffer size is 8 KB #1010 1011 Circular buffer size is 16 KB #1011 1100 Circular buffer size is 32 KB #1100 1101 Circular buffer size is 64 KB #1101 1110 Circular buffer size is 128 KB #1110 1111 Circular buffer size is 256 KB #1111 SMOD Source address modulo 12 4 read-write 0000 Buffer disabled #0000 0001 Circular buffer size is 16 bytes #0001 0010 Circular buffer size is 32 bytes #0010 0011 Circular buffer size is 64 bytes #0011 0100 Circular buffer size is 128 bytes #0100 0101 Circular buffer size is 256 bytes #0101 0110 Circular buffer size is 512 bytes #0110 0111 Circular buffer size is 1 KB #0111 1000 Circular buffer size is 2 KB #1000 1001 Circular buffer size is 4 KB #1001 1010 Circular buffer size is 8 KB #1010 1011 Circular buffer size is 16 KB #1011 1100 Circular buffer size is 32 KB #1100 1101 Circular buffer size is 64 KB #1101 1110 Circular buffer size is 128 KB #1110 1111 Circular buffer size is 256 KB #1111 START Start transfer 16 1 write-only 0 DMA inactive #0 1 The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0. #1 DSIZE Destination size 17 2 read-write 00 32-bit #00 01 8-bit #01 10 16-bit #10 11 Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) #11 DINC Destination increment 19 1 read-write 0 No change to the DAR after a successful transfer. #0 1 The DAR increments by 1, 2, 4 depending upon the size of the transfer. #1 SSIZE Source size 20 2 read-write 00 32-bit #00 01 8-bit #01 10 16-bit #10 11 Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) #11 SINC Source increment 22 1 read-write 0 No change to SAR after a successful transfer. #0 1 The SAR increments by 1, 2, 4 as determined by the transfer size. #1 EADREQ Enable asynchronous DMA requests 23 1 read-write 0 Disabled #0 1 Enabled #1 AA Auto-align 28 1 read-write 0 Auto-align disabled #0 1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC. #1 CS Cycle steal 29 1 read-write 0 DMA continuously makes read/write transfers until the BCR decrements to 0. #0 1 Forces a single read/write transfer per request. #1 ERQ Enable peripheral request 30 1 read-write 0 Peripheral request is ignored. #0 1 Enables peripheral request, defined by the appropriate REQC[DMACn] field, to initiate transfer. A software-initiated request (setting the START bit) is always enabled. #1 EINT Enable interrupt on completion of transfer 31 1 read-write 0 No interrupt is generated. #0 1 Interrupt signal is enabled. #1 SAR2 Source Address Register 0x120 32 read-write 0 0xFFFFFFFF SAR Each SAR contains the byte address used by the DMA controller to read data 0 32 read-write DAR2 Destination Address Register 0x124 32 read-write 0 0xFFFFFFFF DAR Each DAR contains the byte address used by the DMA controller to write data 0 32 read-write DSR_BCR2 DMA Status Register / Byte Count Register 0x128 32 read-write 0 0xFFFFFFFF BCR This field contains the number of bytes yet to be transferred for a given block 0 24 read-write DONE Transactions done 24 1 read-write 0 DMA transfer is not yet complete. Writing a 0 has no effect. #0 1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits. #1 BSY Busy 25 1 read-only 0 DMA channel is inactive. Cleared when the DMA has finished the last transaction. #0 1 BSY is set the first time the channel is enabled after a transfer is initiated. #1 REQ Request 26 1 read-only 0 No request is pending or the channel is currently active. Cleared when the channel is selected. #0 1 The DMA channel has a transfer remaining and the channel is not selected. #1 BED Bus error on destination 28 1 read-only 0 No bus error occurred. #0 1 The DMA channel terminated with a bus error during the write portion of a transfer. #1 BES Bus error on source 29 1 read-only 0 No bus error occurred. #0 1 The DMA channel terminated with a bus error during the read portion of a transfer. #1 CE Configuration error 30 1 read-only 0 No configuration error exists. #0 1 A configuration error has occurred. #1 DSR2 DMA_DSR2 register. 0x12B 8 read-write 0 0xFF DCR2 DMA Control Register 0x12C 32 read-write 0 0xFFFFFFFF LCH2 Link channel 2 0 2 read-write 00 DMA Channel 0 #00 01 DMA Channel 1 #01 10 DMA Channel 2 #10 11 DMA Channel 3 #11 LCH1 Link channel 1 2 2 read-write 00 DMA Channel 0 #00 01 DMA Channel 1 #01 10 DMA Channel 2 #10 11 DMA Channel 3 #11 LINKCC Link channel control 4 2 read-write 00 No channel-to-channel linking #00 01 Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to zero #01 10 Perform a link to channel LCH1 after each cycle-steal transfer #10 11 Perform a link to channel LCH1 after the BCR decrements to zero #11 D_REQ Disable request 7 1 read-write 0 ERQ bit is not affected. #0 1 ERQ bit is cleared when the BCR is exhausted. #1 DMOD Destination address modulo 8 4 read-write 0000 Buffer disabled #0000 0001 Circular buffer size is 16 bytes #0001 0010 Circular buffer size is 32 bytes #0010 0011 Circular buffer size is 64 bytes #0011 0100 Circular buffer size is 128 bytes #0100 0101 Circular buffer size is 256 bytes #0101 0110 Circular buffer size is 512 bytes #0110 0111 Circular buffer size is 1 KB #0111 1000 Circular buffer size is 2 KB #1000 1001 Circular buffer size is 4 KB #1001 1010 Circular buffer size is 8 KB #1010 1011 Circular buffer size is 16 KB #1011 1100 Circular buffer size is 32 KB #1100 1101 Circular buffer size is 64 KB #1101 1110 Circular buffer size is 128 KB #1110 1111 Circular buffer size is 256 KB #1111 SMOD Source address modulo 12 4 read-write 0000 Buffer disabled #0000 0001 Circular buffer size is 16 bytes #0001 0010 Circular buffer size is 32 bytes #0010 0011 Circular buffer size is 64 bytes #0011 0100 Circular buffer size is 128 bytes #0100 0101 Circular buffer size is 256 bytes #0101 0110 Circular buffer size is 512 bytes #0110 0111 Circular buffer size is 1 KB #0111 1000 Circular buffer size is 2 KB #1000 1001 Circular buffer size is 4 KB #1001 1010 Circular buffer size is 8 KB #1010 1011 Circular buffer size is 16 KB #1011 1100 Circular buffer size is 32 KB #1100 1101 Circular buffer size is 64 KB #1101 1110 Circular buffer size is 128 KB #1110 1111 Circular buffer size is 256 KB #1111 START Start transfer 16 1 write-only 0 DMA inactive #0 1 The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0. #1 DSIZE Destination size 17 2 read-write 00 32-bit #00 01 8-bit #01 10 16-bit #10 11 Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) #11 DINC Destination increment 19 1 read-write 0 No change to the DAR after a successful transfer. #0 1 The DAR increments by 1, 2, 4 depending upon the size of the transfer. #1 SSIZE Source size 20 2 read-write 00 32-bit #00 01 8-bit #01 10 16-bit #10 11 Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) #11 SINC Source increment 22 1 read-write 0 No change to SAR after a successful transfer. #0 1 The SAR increments by 1, 2, 4 as determined by the transfer size. #1 EADREQ Enable asynchronous DMA requests 23 1 read-write 0 Disabled #0 1 Enabled #1 AA Auto-align 28 1 read-write 0 Auto-align disabled #0 1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC. #1 CS Cycle steal 29 1 read-write 0 DMA continuously makes read/write transfers until the BCR decrements to 0. #0 1 Forces a single read/write transfer per request. #1 ERQ Enable peripheral request 30 1 read-write 0 Peripheral request is ignored. #0 1 Enables peripheral request, defined by the appropriate REQC[DMACn] field, to initiate transfer. A software-initiated request (setting the START bit) is always enabled. #1 EINT Enable interrupt on completion of transfer 31 1 read-write 0 No interrupt is generated. #0 1 Interrupt signal is enabled. #1 SAR3 Source Address Register 0x130 32 read-write 0 0xFFFFFFFF SAR Each SAR contains the byte address used by the DMA controller to read data 0 32 read-write DAR3 Destination Address Register 0x134 32 read-write 0 0xFFFFFFFF DAR Each DAR contains the byte address used by the DMA controller to write data 0 32 read-write DSR_BCR3 DMA Status Register / Byte Count Register 0x138 32 read-write 0 0xFFFFFFFF BCR This field contains the number of bytes yet to be transferred for a given block 0 24 read-write DONE Transactions done 24 1 read-write 0 DMA transfer is not yet complete. Writing a 0 has no effect. #0 1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits. #1 BSY Busy 25 1 read-only 0 DMA channel is inactive. Cleared when the DMA has finished the last transaction. #0 1 BSY is set the first time the channel is enabled after a transfer is initiated. #1 REQ Request 26 1 read-only 0 No request is pending or the channel is currently active. Cleared when the channel is selected. #0 1 The DMA channel has a transfer remaining and the channel is not selected. #1 BED Bus error on destination 28 1 read-only 0 No bus error occurred. #0 1 The DMA channel terminated with a bus error during the write portion of a transfer. #1 BES Bus error on source 29 1 read-only 0 No bus error occurred. #0 1 The DMA channel terminated with a bus error during the read portion of a transfer. #1 CE Configuration error 30 1 read-only 0 No configuration error exists. #0 1 A configuration error has occurred. #1 DSR3 DMA_DSR3 register. 0x13B 8 read-write 0 0xFF DCR3 DMA Control Register 0x13C 32 read-write 0 0xFFFFFFFF LCH2 Link channel 2 0 2 read-write 00 DMA Channel 0 #00 01 DMA Channel 1 #01 10 DMA Channel 2 #10 11 DMA Channel 3 #11 LCH1 Link channel 1 2 2 read-write 00 DMA Channel 0 #00 01 DMA Channel 1 #01 10 DMA Channel 2 #10 11 DMA Channel 3 #11 LINKCC Link channel control 4 2 read-write 00 No channel-to-channel linking #00 01 Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to zero #01 10 Perform a link to channel LCH1 after each cycle-steal transfer #10 11 Perform a link to channel LCH1 after the BCR decrements to zero #11 D_REQ Disable request 7 1 read-write 0 ERQ bit is not affected. #0 1 ERQ bit is cleared when the BCR is exhausted. #1 DMOD Destination address modulo 8 4 read-write 0000 Buffer disabled #0000 0001 Circular buffer size is 16 bytes #0001 0010 Circular buffer size is 32 bytes #0010 0011 Circular buffer size is 64 bytes #0011 0100 Circular buffer size is 128 bytes #0100 0101 Circular buffer size is 256 bytes #0101 0110 Circular buffer size is 512 bytes #0110 0111 Circular buffer size is 1 KB #0111 1000 Circular buffer size is 2 KB #1000 1001 Circular buffer size is 4 KB #1001 1010 Circular buffer size is 8 KB #1010 1011 Circular buffer size is 16 KB #1011 1100 Circular buffer size is 32 KB #1100 1101 Circular buffer size is 64 KB #1101 1110 Circular buffer size is 128 KB #1110 1111 Circular buffer size is 256 KB #1111 SMOD Source address modulo 12 4 read-write 0000 Buffer disabled #0000 0001 Circular buffer size is 16 bytes #0001 0010 Circular buffer size is 32 bytes #0010 0011 Circular buffer size is 64 bytes #0011 0100 Circular buffer size is 128 bytes #0100 0101 Circular buffer size is 256 bytes #0101 0110 Circular buffer size is 512 bytes #0110 0111 Circular buffer size is 1 KB #0111 1000 Circular buffer size is 2 KB #1000 1001 Circular buffer size is 4 KB #1001 1010 Circular buffer size is 8 KB #1010 1011 Circular buffer size is 16 KB #1011 1100 Circular buffer size is 32 KB #1100 1101 Circular buffer size is 64 KB #1101 1110 Circular buffer size is 128 KB #1110 1111 Circular buffer size is 256 KB #1111 START Start transfer 16 1 write-only 0 DMA inactive #0 1 The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0. #1 DSIZE Destination size 17 2 read-write 00 32-bit #00 01 8-bit #01 10 16-bit #10 11 Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) #11 DINC Destination increment 19 1 read-write 0 No change to the DAR after a successful transfer. #0 1 The DAR increments by 1, 2, 4 depending upon the size of the transfer. #1 SSIZE Source size 20 2 read-write 00 32-bit #00 01 8-bit #01 10 16-bit #10 11 Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) #11 SINC Source increment 22 1 read-write 0 No change to SAR after a successful transfer. #0 1 The SAR increments by 1, 2, 4 as determined by the transfer size. #1 EADREQ Enable asynchronous DMA requests 23 1 read-write 0 Disabled #0 1 Enabled #1 AA Auto-align 28 1 read-write 0 Auto-align disabled #0 1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC. #1 CS Cycle steal 29 1 read-write 0 DMA continuously makes read/write transfers until the BCR decrements to 0. #0 1 Forces a single read/write transfer per request. #1 ERQ Enable peripheral request 30 1 read-write 0 Peripheral request is ignored. #0 1 Enables peripheral request, defined by the appropriate REQC[DMACn] field, to initiate transfer. A software-initiated request (setting the START bit) is always enabled. #1 EINT Enable interrupt on completion of transfer 31 1 read-write 0 No interrupt is generated. #0 1 Interrupt signal is enabled. #1 FTFA Flash Memory Interface FTFA_ 0x40020000 0 0x14 registers FTFA 5 FSTAT Flash Status Register 0 8 read-write 0 0xFF MGSTAT0 Memory Controller Command Completion Status Flag 0 1 read-only FPVIOL Flash Protection Violation Flag 4 1 read-write 0 No protection violation detected #0 1 Protection violation detected #1 ACCERR Flash Access Error Flag 5 1 read-write 0 No access error detected #0 1 Access error detected #1 RDCOLERR Flash Read Collision Error Flag 6 1 read-write 0 No collision error detected #0 1 Collision error detected #1 CCIF Command Complete Interrupt Flag 7 1 read-write 0 Flash command in progress #0 1 Flash command has completed #1 FCNFG Flash Configuration Register 0x1 8 read-write 0 0xFF ERSSUSP Erase Suspend 4 1 read-write 0 No suspend requested #0 1 Suspend the current Erase Flash Sector command execution. #1 ERSAREQ Erase All Request 5 1 read-only 0 No request or request complete #0 1 Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state. #1 RDCOLLIE Read Collision Error Interrupt Enable 6 1 read-write 0 Read collision error interrupt disabled #0 1 Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]). #1 CCIE Command Complete Interrupt Enable 7 1 read-write 0 Command complete interrupt disabled #0 1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. #1 FSEC Flash Security Register 0x2 8 read-only 0 0 SEC Flash Security 0 2 read-only 00 MCU security status is secure #00 01 MCU security status is secure #01 10 MCU security status is unsecure (The standard shipping condition of the flash memory module is unsecure.) #10 11 MCU security status is secure #11 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 00 Freescale factory access granted #00 01 Freescale factory access denied #01 10 Freescale factory access denied #10 11 Freescale factory access granted #11 MEEN Mass Erase Enable Bits 4 2 read-only 00 Mass erase is enabled #00 01 Mass erase is enabled #01 10 Mass erase is disabled #10 11 Mass erase is enabled #11 KEYEN Backdoor Key Security Enable 6 2 read-only 00 Backdoor key access disabled #00 01 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) #01 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 FOPT Flash Option Register 0x3 8 read-only 0 0 OPT Nonvolatile Option 0 8 read-only 12 0x1 3,2,1,0,7,6,5,4,B,A,9,8 FCCOB%s Flash Common Command Object Registers 0x4 8 read-write 0 0xFF CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write 4 0x1 3,2,1,0 FPROT%s Program Flash Protection Registers 0x10 8 read-write 0 0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 DMAMUX0 DMA channel multiplexor DMAMUX0_ 0x40021000 0 0x4 registers 4 0x1 0,1,2,3 CHCFG%s Channel Configuration register 0 8 read-write 0 0xFF SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in Periodic Trigger mode. #1 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 PIT Periodic Interrupt Timer PIT_ 0x40037000 0 0x120 registers PIT 22 MCR PIT Module Control Register 0 32 read-write 0x2 0xFFFFFFFF FRZ Freeze 0 1 read-write 0 Timers continue to run in Debug mode. #0 1 Timers are stopped in Debug mode. #1 MDIS Module Disable - (PIT section) 1 1 read-write 0 Clock for standard PIT timers is enabled. #0 1 Clock for standard PIT timers is disabled. #1 LTMR64H PIT Upper Lifetime Timer Register 0xE0 32 read-only 0 0xFFFFFFFF LTH Life Timer value 0 32 read-only LTMR64L PIT Lower Lifetime Timer Register 0xE4 32 read-only 0 0xFFFFFFFF LTL Life Timer value 0 32 read-only 2 0x10 0,1 LDVAL%s Timer Load Value Register 0x100 32 read-write 0 0xFFFFFFFF TSV Timer Start Value 0 32 read-write 2 0x10 0,1 CVAL%s Current Timer Value Register 0x104 32 read-only 0 0xFFFFFFFF TVL Current Timer Value 0 32 read-only 2 0x10 0,1 TCTRL%s Timer Control Register 0x108 32 read-write 0 0xFFFFFFFF TEN Timer Enable 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is enabled. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 CHN Chain Mode 2 1 read-write 0 Timer is not chained. #0 1 Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. #1 2 0x10 0,1 TFLG%s Timer Flag Register 0x10C 32 read-write 0 0xFFFFFFFF TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 TPM0 Timer/PWM Module TPM TPM0_ 0x40038000 0 0x88 registers TPM0 17 SC Status and Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CMOD Clock Mode Selection 3 2 read-write 00 LPTPM counter is disabled #00 01 LPTPM counter increments on every LPTPM counter clock #01 10 LPTPM counter increments on rising edge of LPTPM_EXTCLK synchronized to the LPTPM counter clock #10 CPWMS Center-aligned PWM Select 5 1 read-write 0 LPTPM counter operates in up counting mode. #0 1 LPTPM counter operates in up-down counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling or DMA request. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-write 0 LPTPM counter has not overflowed. #0 1 LPTPM counter has overflowed. #1 DMA DMA Enable 8 1 read-write 0 Disables DMA transfers. #0 1 Enables DMA transfers. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter value 0 16 read-write MOD Modulo 0x8 32 read-write 0xFFFF 0xFFFFFFFF MOD Modulo value 0 16 read-write 6 0x8 0,1,2,3,4,5 C%sSC Channel (n) Status and Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 6 0x8 0,1,2,3,4,5 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write STATUS Capture and Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 TOF Timer Overflow Flag 8 1 read-write 0 LPTPM counter has not overflowed. #0 1 LPTPM counter has overflowed. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF DOZEEN Doze Enable 5 1 read-write 0 Internal LPTPM counter continues in Doze mode. #0 1 Internal LPTPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. #1 DBGMODE Debug Mode 6 2 read-write 00 LPTPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. #00 11 LPTPM counter continues in debug mode. #11 GTBEEN Global time base enable 9 1 read-write 0 All channels use the internally generated LPTPM counter as their timebase #0 1 All channels use an externally generated global timebase as their timebase #1 CSOT Counter Start on Trigger 16 1 read-write 0 LPTPM counter starts to increment immediately, once it is enabled. #0 1 LPTPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. #1 CSOO Counter Stop On Overflow 17 1 read-write 0 LPTPM counter continues incrementing or decrementing after overflow #0 1 LPTPM counter stops incrementing or decrementing after overflow. #1 CROT Counter Reload On Trigger 18 1 read-write 0 Counter is not reloaded due to a rising edge on the selected input trigger #0 1 Counter is reloaded when a rising edge is detected on the selected input trigger #1 TRGSEL Trigger Select 24 4 read-write TPM1 Timer/PWM Module TPM TPM1_ 0x40039000 0 0x88 registers TPM1 18 SC Status and Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CMOD Clock Mode Selection 3 2 read-write 00 LPTPM counter is disabled #00 01 LPTPM counter increments on every LPTPM counter clock #01 10 LPTPM counter increments on rising edge of LPTPM_EXTCLK synchronized to the LPTPM counter clock #10 CPWMS Center-aligned PWM Select 5 1 read-write 0 LPTPM counter operates in up counting mode. #0 1 LPTPM counter operates in up-down counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling or DMA request. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-write 0 LPTPM counter has not overflowed. #0 1 LPTPM counter has overflowed. #1 DMA DMA Enable 8 1 read-write 0 Disables DMA transfers. #0 1 Enables DMA transfers. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter value 0 16 read-write MOD Modulo 0x8 32 read-write 0xFFFF 0xFFFFFFFF MOD Modulo value 0 16 read-write 2 0x8 0,1 C%sSC Channel (n) Status and Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 2 0x8 0,1 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write STATUS Capture and Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 TOF Timer Overflow Flag 8 1 read-write 0 LPTPM counter has not overflowed. #0 1 LPTPM counter has overflowed. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF DOZEEN Doze Enable 5 1 read-write 0 Internal LPTPM counter continues in Doze mode. #0 1 Internal LPTPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. #1 DBGMODE Debug Mode 6 2 read-write 00 LPTPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. #00 11 LPTPM counter continues in debug mode. #11 GTBEEN Global time base enable 9 1 read-write 0 All channels use the internally generated LPTPM counter as their timebase #0 1 All channels use an externally generated global timebase as their timebase #1 CSOT Counter Start on Trigger 16 1 read-write 0 LPTPM counter starts to increment immediately, once it is enabled. #0 1 LPTPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. #1 CSOO Counter Stop On Overflow 17 1 read-write 0 LPTPM counter continues incrementing or decrementing after overflow #0 1 LPTPM counter stops incrementing or decrementing after overflow. #1 CROT Counter Reload On Trigger 18 1 read-write 0 Counter is not reloaded due to a rising edge on the selected input trigger #0 1 Counter is reloaded when a rising edge is detected on the selected input trigger #1 TRGSEL Trigger Select 24 4 read-write TPM2 Timer/PWM Module TPM TPM2_ 0x4003A000 0 0x88 registers TPM2 19 SC Status and Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CMOD Clock Mode Selection 3 2 read-write 00 LPTPM counter is disabled #00 01 LPTPM counter increments on every LPTPM counter clock #01 10 LPTPM counter increments on rising edge of LPTPM_EXTCLK synchronized to the LPTPM counter clock #10 CPWMS Center-aligned PWM Select 5 1 read-write 0 LPTPM counter operates in up counting mode. #0 1 LPTPM counter operates in up-down counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling or DMA request. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-write 0 LPTPM counter has not overflowed. #0 1 LPTPM counter has overflowed. #1 DMA DMA Enable 8 1 read-write 0 Disables DMA transfers. #0 1 Enables DMA transfers. #1 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter value 0 16 read-write MOD Modulo 0x8 32 read-write 0xFFFF 0xFFFFFFFF MOD Modulo value 0 16 read-write 2 0x8 0,1 C%sSC Channel (n) Status and Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 2 0x8 0,1 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write STATUS Capture and Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 TOF Timer Overflow Flag 8 1 read-write 0 LPTPM counter has not overflowed. #0 1 LPTPM counter has overflowed. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF DOZEEN Doze Enable 5 1 read-write 0 Internal LPTPM counter continues in Doze mode. #0 1 Internal LPTPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. #1 DBGMODE Debug Mode 6 2 read-write 00 LPTPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. #00 11 LPTPM counter continues in debug mode. #11 GTBEEN Global time base enable 9 1 read-write 0 All channels use the internally generated LPTPM counter as their timebase #0 1 All channels use an externally generated global timebase as their timebase #1 CSOT Counter Start on Trigger 16 1 read-write 0 LPTPM counter starts to increment immediately, once it is enabled. #0 1 LPTPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. #1 CSOO Counter Stop On Overflow 17 1 read-write 0 LPTPM counter continues incrementing or decrementing after overflow #0 1 LPTPM counter stops incrementing or decrementing after overflow. #1 CROT Counter Reload On Trigger 18 1 read-write 0 Counter is not reloaded due to a rising edge on the selected input trigger #0 1 Counter is reloaded when a rising edge is detected on the selected input trigger #1 TRGSEL Trigger Select 24 4 read-write ADC0 Analog-to-Digital Converter ADC0_ 0x4003B000 0 0x50 registers ADC0 15 2 0x4 A,B SC1%s ADC Status and Control Registers 1 0 32 read-write 0x1F 0xFFFFFFFF ADCH Input channel select 0 5 read-write 00000 AD0 is selected as input. #00000 00001 AD1 is selected as input. #00001 00010 AD2 is selected as input. #00010 00011 AD3 is selected as input. #00011 00100 AD4 is selected as input. #00100 00101 AD5 is selected as input. #00101 00110 AD6 is selected as input. #00110 00111 AD7 is selected as input. #00111 01000 AD8 is selected as input. #01000 01001 AD9 is selected as input. #01001 01010 AD10 is selected as input. #01010 01011 AD11 is selected as input. #01011 01100 AD12 is selected as input. #01100 01101 AD13 is selected as input. #01101 01110 AD14 is selected as input. #01110 01111 AD15 is selected as input. #01111 10000 AD16 is selected as input. #10000 10001 AD17 is selected as input. #10001 10010 AD18 is selected as input. #10010 10011 AD19 is selected as input. #10011 10100 AD20 is selected as input. #10100 10101 AD21 is selected as input. #10101 10110 AD22 is selected as input. #10110 10111 AD23 is selected as input. #10111 11010 Temp Sensor (single-ended) is selected as input. #11010 11011 Bandgap (single-ended) is selected as input. #11011 11101 VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]. #11101 11110 VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]. #11110 11111 Module is disabled. #11111 AIEN Interrupt Enable 6 1 read-write 0 Conversion complete interrupt is disabled. #0 1 Conversion complete interrupt is enabled. #1 COCO Conversion Complete Flag 7 1 read-only 0 Conversion is not completed. #0 1 Conversion is completed. #1 CFG1 ADC Configuration Register 1 0x8 32 read-write 0 0xFFFFFFFF ADICLK Input Clock Select 0 2 read-write 00 Bus clock #00 01 (Bus clock)/2 #01 10 Alternate clock (ALTCLK) #10 11 Asynchronous clock (ADACK) #11 MODE Conversion mode selection 2 2 read-write 00 It is single-ended 8-bit conversion. #00 01 It is single-ended 12-bit conversion . #01 10 It is single-ended 10-bit conversion . #10 11 Reserved. Do not set the bitfield to this value. #11 ADLSMP Sample time configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 ADIV Clock Divide Select 5 2 read-write 00 The divide ratio is 1 and the clock rate is input clock. #00 01 The divide ratio is 2 and the clock rate is (input clock)/2. #01 10 The divide ratio is 4 and the clock rate is (input clock)/4. #10 11 The divide ratio is 8 and the clock rate is (input clock)/8. #11 ADLPC Low-Power Configuration 7 1 read-write 0 Normal power configuration. #0 1 Low-power configuration. The power is reduced at the expense of maximum clock speed. #1 CFG2 ADC Configuration Register 2 0xC 32 read-write 0 0xFFFFFFFF ADLSTS Long Sample Time Select 0 2 read-write 00 Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. #00 01 12 extra ADCK cycles; 16 ADCK cycles total sample time. #01 10 6 extra ADCK cycles; 10 ADCK cycles total sample time. #10 11 2 extra ADCK cycles; 6 ADCK cycles total sample time. #11 ADHSC High-Speed Configuration 2 1 read-write 0 Normal conversion sequence selected. #0 1 High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. #1 ADACKEN Asynchronous Clock Output Enable 3 1 read-write 0 Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. #0 1 Asynchronous clock and clock output is enabled regardless of the state of the ADC. #1 MUXSEL ADC Mux Select 4 1 read-write 0 ADxxa channels are selected. #0 1 ADxxb channels are selected. #1 2 0x4 A,B R%s ADC Data Result Register 0x10 32 read-only 0 0xFFFFFFFF D Data result 0 16 read-only 2 0x4 1,2 CV%s Compare Value Registers 0x18 32 read-write 0 0xFFFFFFFF CV Compare Value. 0 16 read-write SC2 Status and Control Register 2 0x20 32 read-write 0 0xFFFFFFFF REFSEL Voltage Reference Selection 0 2 read-write 00 Default voltage reference pin pair, that is, external pins VREFH and VREFL #00 01 Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU #01 DMAEN DMA Enable 2 1 read-write 0 DMA is disabled. #0 1 DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted. #1 ACREN Compare Function Range Enable 3 1 read-write 0 Range function disabled. Only CV1 is compared. #0 1 Range function enabled. Both CV1 and CV2 are compared. #1 ACFGT Compare Function Greater Than Enable 4 1 read-write 0 Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. #0 1 Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2. #1 ACFE Compare Function Enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ADTRG Conversion Trigger Select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 ADACT Conversion Active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 SC3 Status and Control Register 3 0x24 32 read-write 0 0xFFFFFFFF AVGS Hardware Average Select 0 2 read-write 00 4 samples averaged. #00 01 8 samples averaged. #01 10 16 samples averaged. #10 11 32 samples averaged. #11 AVGE Hardware Average Enable 2 1 read-write 0 Hardware average function disabled. #0 1 Hardware average function enabled. #1 ADCO Continuous Conversion Enable 3 1 read-write 0 One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. #0 1 Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. #1 CALF Calibration Failed Flag 6 1 read-write 0 Calibration completed normally. #0 1 Calibration failed. ADC accuracy specifications are not guaranteed. #1 CAL Calibration 7 1 read-write OFS ADC Offset Correction Register 0x28 32 read-write 0x4 0xFFFFFFFF OFS Offset Error Correction Value 0 16 read-write PG ADC Plus-Side Gain Register 0x2C 32 read-write 0x8200 0xFFFFFFFF PG Plus-Side Gain 0 16 read-write CLPD ADC Plus-Side General Calibration Value Register 0x34 32 read-write 0xA 0xFFFFFFFF CLPD Calibration Value 0 6 read-write CLPS ADC Plus-Side General Calibration Value Register 0x38 32 read-write 0x20 0xFFFFFFFF CLPS Calibration Value 0 6 read-write CLP4 ADC Plus-Side General Calibration Value Register 0x3C 32 read-write 0x200 0xFFFFFFFF CLP4 Calibration Value 0 10 read-write CLP3 ADC Plus-Side General Calibration Value Register 0x40 32 read-write 0x100 0xFFFFFFFF CLP3 Calibration Value 0 9 read-write CLP2 ADC Plus-Side General Calibration Value Register 0x44 32 read-write 0x80 0xFFFFFFFF CLP2 Calibration Value 0 8 read-write CLP1 ADC Plus-Side General Calibration Value Register 0x48 32 read-write 0x40 0xFFFFFFFF CLP1 Calibration Value 0 7 read-write CLP0 ADC Plus-Side General Calibration Value Register 0x4C 32 read-write 0x20 0xFFFFFFFF CLP0 Calibration Value 0 6 read-write RTC Secure Real Time Clock RTC_ 0x4003D000 0 0x20 registers RTC 20 RTC_Seconds 21 TSR RTC Time Seconds Register 0 32 read-write 0 0xFFFFFFFF TSR Time Seconds Register 0 32 read-write TPR RTC Time Prescaler Register 0x4 32 read-write 0 0xFFFFFFFF TPR Time Prescaler Register 0 16 read-write TAR RTC Time Alarm Register 0x8 32 read-write 0 0xFFFFFFFF TAR Time Alarm Register 0 32 read-write TCR RTC Time Compensation Register 0xC 32 read-write 0 0xFFFFFFFF TCR Time Compensation Register 0 8 read-write 10000000 Time Prescaler Register overflows every 32896 clock cycles. #10000000 11111111 Time Prescaler Register overflows every 32769 clock cycles. #11111111 0 Time Prescaler Register overflows every 32768 clock cycles. #0 1 Time Prescaler Register overflows every 32767 clock cycles. #1 1111111 Time Prescaler Register overflows every 32641 clock cycles. #1111111 CIR Compensation Interval Register 8 8 read-write TCV Time Compensation Value 16 8 read-only CIC Compensation Interval Counter 24 8 read-only CR RTC Control Register 0x10 32 read-write 0 0xFFFFFFFF SWR Software Reset 0 1 read-write 0 No effect. #0 1 Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it. #1 WPE Wakeup Pin Enable 1 1 read-write 0 Wakeup pin is disabled. #0 1 Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on. #1 SUP Supervisor Access 2 1 read-write 0 Non-supervisor mode write accesses are not supported and generate a bus error. #0 1 Non-supervisor mode write accesses are supported. #1 UM Update Mode 3 1 read-write 0 Registers cannot be written when locked. #0 1 Registers can be written when locked under limited conditions. #1 OSCE Oscillator Enable 8 1 read-write 0 32.768 kHz oscillator is disabled. #0 1 32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize. #1 CLKO Clock Output 9 1 read-write 0 The 32 kHz clock is output to other peripherals. #0 1 The 32 kHz clock is not output to other peripherals. #1 SC16P Oscillator 16pF Load Configure 10 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC8P Oscillator 8pF Load Configure 11 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC4P Oscillator 4pF Load Configure 12 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC2P Oscillator 2pF Load Configure 13 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SR RTC Status Register 0x14 32 read-write 0x1 0xFFFFFFFF TIF Time Invalid Flag 0 1 read-only 0 Time is valid. #0 1 Time is invalid and time counter is read as zero. #1 TOF Time Overflow Flag 1 1 read-only 0 Time overflow has not occurred. #0 1 Time overflow has occurred and time counter is read as zero. #1 TAF Time Alarm Flag 2 1 read-only 0 Time alarm has not occurred. #0 1 Time alarm has occurred. #1 TCE Time Counter Enable 4 1 read-write 0 Time counter is disabled. #0 1 Time counter is enabled. #1 LR RTC Lock Register 0x18 32 read-write 0xFF 0xFFFFFFFF TCL Time Compensation Lock 3 1 read-write 0 Time Compensation Register is locked and writes are ignored. #0 1 Time Compensation Register is not locked and writes complete as normal. #1 CRL Control Register Lock 4 1 read-write 0 Control Register is locked and writes are ignored. #0 1 Control Register is not locked and writes complete as normal. #1 SRL Status Register Lock 5 1 read-write 0 Status Register is locked and writes are ignored. #0 1 Status Register is not locked and writes complete as normal. #1 LRL Lock Register Lock 6 1 read-write 0 Lock Register is locked and writes are ignored. #0 1 Lock Register is not locked and writes complete as normal. #1 IER RTC Interrupt Enable Register 0x1C 32 read-write 0x7 0xFFFFFFFF TIIE Time Invalid Interrupt Enable 0 1 read-write 0 Time invalid flag does not generate an interrupt. #0 1 Time invalid flag does generate an interrupt. #1 TOIE Time Overflow Interrupt Enable 1 1 read-write 0 Time overflow flag does not generate an interrupt. #0 1 Time overflow flag does generate an interrupt. #1 TAIE Time Alarm Interrupt Enable 2 1 read-write 0 Time alarm flag does not generate an interrupt. #0 1 Time alarm flag does generate an interrupt. #1 TSIE Time Seconds Interrupt Enable 4 1 read-write 0 Seconds interrupt is disabled. #0 1 Seconds interrupt is enabled. #1 WPON Wakeup Pin On 7 1 read-write 0 No effect. #0 1 If the wakeup pin is enabled, then the wakeup pin will assert. #1 LPTMR0 Low Power Timer LPTMR0_ 0x40040000 0 0x10 registers LPTMR0 28 CSR Low Power Timer Control Status Register 0 32 read-write 0 0xFFFFFFFF TEN Timer Enable 0 1 read-write 0 LPTMR is disabled and internal logic is reset. #0 1 LPTMR is enabled. #1 TMS Timer Mode Select 1 1 read-write 0 Time Counter mode. #0 1 Pulse Counter mode. #1 TFC Timer Free-Running Counter 2 1 read-write 0 CNR is reset whenever TCF is set. #0 1 CNR is reset on overflow. #1 TPP Timer Pin Polarity 3 1 read-write 0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. #0 1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. #1 TPS Timer Pin Select 4 2 read-write 00 Pulse counter input 0 is selected. #00 01 Pulse counter input 1 is selected. #01 10 Pulse counter input 2 is selected. #10 11 Pulse counter input 3 is selected. #11 TIE Timer Interrupt Enable 6 1 read-write 0 Timer interrupt disabled. #0 1 Timer interrupt enabled. #1 TCF Timer Compare Flag 7 1 read-write 0 The value of CNR is not equal to CMR and increments. #0 1 The value of CNR is equal to CMR and increments. #1 PSR Low Power Timer Prescale Register 0x4 32 read-write 0 0xFFFFFFFF PCS Prescaler Clock Select 0 2 read-write 00 Prescaler/glitch filter clock 0 selected. #00 01 Prescaler/glitch filter clock 1 selected. #01 10 Prescaler/glitch filter clock 2 selected. #10 11 Prescaler/glitch filter clock 3 selected. #11 PBYP Prescaler Bypass 2 1 read-write 0 Prescaler/glitch filter is enabled. #0 1 Prescaler/glitch filter is bypassed. #1 PRESCALE Prescale Value 3 4 read-write 0000 Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. #0000 0001 Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. #0001 0010 Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. #0010 0011 Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. #0011 0100 Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. #0100 0101 Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. #0101 0110 Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. #0110 0111 Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. #0111 1000 Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. #1000 1001 Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. #1001 1010 Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. #1010 1011 Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. #1011 1100 Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. #1100 1101 Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. #1101 1110 Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. #1110 1111 Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. #1111 CMR Low Power Timer Compare Register 0x8 32 read-write 0 0xFFFFFFFF COMPARE Compare Value 0 16 read-write CNR Low Power Timer Counter Register 0xC 32 read-write 0 0xFFFFFFFF COUNTER Counter Value 0 16 read-write SIM System Integration Module SIM_ 0x40047000 0 0x1108 registers SOPT1 System Options Register 1 0 32 read-write 0 0xFFFFFFFF OSC32KSEL 32K oscillator clock select 18 2 read-write 00 System oscillator (OSC32KCLK) #00 10 RTC_CLKIN #10 11 LPO 1kHz #11 SOPT1CFG SOPT1 Configuration Register 0x4 32 read-only 0 0xFFFFFFFF SOPT2 System Options Register 2 0x1004 32 read-write 0 0xFFFFFFFF RTCCLKOUTSEL RTC clock out select 4 1 read-write 0 RTC 1 Hz clock is output on the RTC_CLKOUT pin. #0 1 OSCERCLK clock is output on the RTC_CLKOUT pin. #1 CLKOUTSEL CLKOUT select 5 3 read-write 010 Bus clock #010 011 LPO clock (1 kHz) #011 100 MCGIRCLK #100 110 OSCERCLK #110 PLLFLLSEL PLL/FLL clock select 16 1 read-write 0 MCGFLLCLK clock #0 1 MCGPLLCLK clock with fixed divide by two #1 TPMSRC TPM clock source select 24 2 read-write 00 Clock disabled #00 01 MCGFLLCLK clock #01 10 OSCERCLK clock #10 11 MCGIRCLK clock #11 UART0SRC UART0 clock source select 26 2 read-write 00 Clock disabled #00 01 MCGFLLCLK clock #01 10 OSCERCLK clock #10 11 MCGIRCLK clock #11 SOPT4 System Options Register 4 0x100C 32 read-write 0 0xFFFFFFFF TPM1CH0SRC TPM1 channel 0 input capture source select 18 1 read-write 0 TPM1_CH0 signal #0 1 CMP0 output #1 TPM2CH0SRC TPM2 channel 0 input capture source select 20 1 read-write 0 TPM2_CH0 signal #0 1 CMP0 output #1 TPM0CLKSEL TPM0 External Clock Pin Select 24 1 read-write 0 TPM0 external clock driven by TPM_CLKIN0 pin. #0 1 TPM0 external clock driven by TPM_CLKIN1 pin. #1 TPM1CLKSEL TPM1 External Clock Pin Select 25 1 read-write 0 TPM1 external clock driven by TPM_CLKIN0 pin. #0 1 TPM1 external clock driven by TPM_CLKIN1 pin. #1 TPM2CLKSEL TPM2 External Clock Pin Select 26 1 read-write 0 TPM2 external clock driven by TPM_CLKIN0 pin. #0 1 TPM2 external clock driven by TPM_CLKIN1 pin. #1 SOPT5 System Options Register 5 0x1010 32 read-write 0 0xFFFFFFFF UART0TXSRC UART0 transmit data source select 0 2 read-write 00 UART0_TX pin #00 01 UART0_TX pin modulated with TPM1 channel 0 output #01 10 UART0_TX pin modulated with TPM2 channel 0 output #10 UART0RXSRC UART0 receive data source select 2 1 read-write 0 UART0_RX pin #0 1 CMP0 output #1 UART1TXSRC UART1 transmit data source select 4 2 read-write 00 UART1_TX pin #00 01 UART1_TX pin modulated with TPM1 channel 0 output #01 10 UART1_TX pin modulated with TPM2 channel 0 output #10 UART1RXSRC UART1 receive data source select 6 1 read-write 0 UART1_RX pin #0 1 CMP0 output #1 UART0ODE UART0 Open Drain Enable 16 1 read-write 0 Open drain is disabled on UART0 #0 1 Open drain is enabled on UART0 #1 UART1ODE UART1 Open Drain Enable 17 1 read-write 0 Open drain is disabled on UART1 #0 1 Open drain is enabled on UART1 #1 UART2ODE UART2 Open Drain Enable 18 1 read-write 0 Open drain is disabled on UART2 #0 1 Open drain is enabled on UART2 #1 SOPT7 System Options Register 7 0x1018 32 read-write 0 0xFFFFFFFF ADC0TRGSEL ADC0 trigger select 0 4 read-write 0000 External trigger pin input (EXTRG_IN) #0000 0001 CMP0 output #0001 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 1000 TPM0 overflow #1000 1001 TPM1 overflow #1001 1010 TPM2 overflow #1010 1100 RTC alarm #1100 1101 RTC seconds #1101 1110 LPTMR0 trigger #1110 ADC0PRETRGSEL ADC0 pretrigger select 4 1 read-write 0 Pre-trigger A #0 1 Pre-trigger B #1 ADC0ALTTRGEN ADC0 alternate trigger enable 7 1 read-write 0 TPM1 channel 0 (A) and channel 1 (B) triggers selected for ADC0. #0 1 Alternate trigger selected for ADC0. #1 SDID System Device Identification Register 0x1024 32 read-only 0x100480 0xFFFFFFFF PINID Pincount identification 0 4 read-only 0000 16-pin #0000 0001 24-pin #0001 0010 32-pin #0010 0100 48-pin #0100 0101 64-pin #0101 0110 80-pin #0110 1000 100-pin #1000 DIEID Device die number 7 5 read-only REVID Device revision number 12 4 read-only SRAMSIZE System SRAM Size 16 4 read-only 0000 0.5 KB #0000 0001 1 KB #0001 0010 2 KB #0010 0011 4 KB #0011 0100 8 KB #0100 0101 16 KB #0101 0110 32 KB #0110 0111 64 KB #0111 SERIESID Kinetis Series ID 20 4 read-only 0001 KL family #0001 SUBFAMID Kinetis Sub-Family ID 24 4 read-only 0010 KLx2 Subfamily (low end) #0010 0100 KLx4 Subfamily (basic analog) #0100 0101 KLx5 Subfamily (advanced analog) #0101 0110 KLx6 Subfamily (advanced analog with I2S) #0110 FAMID Kinetis family ID 28 4 read-only 0000 KL0x Family (low end) #0000 0001 KL1x Family (basic) #0001 0010 KL2x Family (USB) #0010 0011 KL3x Family (Segment LCD) #0011 0100 KL4x Family (USB and Segment LCD) #0100 SCGC4 System Clock Gating Control Register 4 0x1034 32 read-write 0xF0000030 0xFFFFFFFF I2C0 I2C0 Clock Gate Control 6 1 read-write 0 Clock disabled #0 1 Clock enabled #1 I2C1 I2C1 Clock Gate Control 7 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART0 UART0 Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART1 UART1 Clock Gate Control 11 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART2 UART2 Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CMP Comparator Clock Gate Control 19 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI0 SPI0 Clock Gate Control 22 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI1 SPI1 Clock Gate Control 23 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC5 System Clock Gating Control Register 5 0x1038 32 read-write 0x180 0xFFFFFFFF LPTMR Low Power Timer Access Control 0 1 read-write 0 Access disabled #0 1 Access enabled #1 PORTA Port A Clock Gate Control 9 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTB Port B Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTC Port C Clock Gate Control 11 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTD Port D Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTE Port E Clock Gate Control 13 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC6 System Clock Gating Control Register 6 0x103C 32 read-write 0x1 0xFFFFFFFF FTF Flash Memory Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 DMAMUX DMA Mux Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PIT PIT Clock Gate Control 23 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TPM0 TPM0 Clock Gate Control 24 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TPM1 TPM1 Clock Gate Control 25 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TPM2 TPM2 Clock Gate Control 26 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ADC0 ADC0 Clock Gate Control 27 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RTC RTC Access Control 29 1 read-write 0 Access and interrupts disabled #0 1 Access and interrupts enabled #1 SCGC7 System Clock Gating Control Register 7 0x1040 32 read-write 0x100 0xFFFFFFFF DMA DMA Clock Gate Control 8 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CLKDIV1 System Clock Divider Register 1 0x1044 32 read-write 0x10000 0xFFFFFFFF OUTDIV4 Clock 4 output divider value 16 3 read-write 000 Divide-by-1. #000 001 Divide-by-2. #001 010 Divide-by-3. #010 011 Divide-by-4. #011 100 Divide-by-5. #100 101 Divide-by-6. #101 110 Divide-by-7. #110 111 Divide-by-8. #111 OUTDIV1 Clock 1 output divider value 28 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 FCFG1 Flash Configuration Register 1 0x104C 32 read-write 0xF000000 0xFFFFFFFF FLASHDIS Flash Disable 0 1 read-write 0 Flash is enabled #0 1 Flash is disabled #1 FLASHDOZE Flash Doze 1 1 read-write 0 Flash remains enabled during Doze mode #0 1 Flash is disabled for the duration of Doze mode #1 PFSIZE Program flash size 24 4 read-only 0000 8 KB of program flash memory, 0.25 KB protection region #0000 0001 16 KB of program flash memory, 0.5 KB protection region #0001 0011 32 KB of program flash memory, 1 KB protection region #0011 0101 64 KB of program flash memory, 2 KB protection region #0101 0111 128 KB of program flash memory, 4 KB protection region #0111 1001 256 KB of program flash memory, 8 KB protection region #1001 1111 128 KB of program flash memory, 4 KB protection region #1111 FCFG2 Flash Configuration Register 2 0x1050 32 read-only 0x7F800000 0xFFFFFFFF MAXADDR0 Max address block 24 7 read-only UIDMH Unique Identification Register Mid-High 0x1058 32 read-only 0 0xFFFFFFFF UID Unique Identification 0 16 read-only UIDML Unique Identification Register Mid Low 0x105C 32 read-only 0 0xFFFFFFFF UID Unique Identification 0 32 read-only UIDL Unique Identification Register Low 0x1060 32 read-only 0 0xFFFFFFFF UID Unique Identification 0 32 read-only COPC COP Control Register 0x1100 32 read-write 0xC 0xFFFFFFFF COPW COP windowed mode 0 1 read-write 0 Normal mode #0 1 Windowed mode #1 COPCLKS COP Clock Select 1 1 read-write 0 Internal 1 kHz clock is source to COP #0 1 Bus clock is source to COP #1 COPT COP Watchdog Timeout 2 2 read-write 00 COP disabled #00 01 COP timeout after 2^5 LPO cycles or 213 bus clock cycles #01 10 COP timeout after 2^8 LPO cycles or 216 bus clock cycles #10 11 COP timeout after 2^10 LPO cycles or 218 bus clock cycles #11 SRVCOP Service COP Register 0x1104 32 write-only 0 0xFFFFFFFF SRVCOP Sevice COP Register 0 8 write-only PORTA Pin Control and Interrupts PORT PORTA_ 0x40049000 0 0xA4 registers PORTA 30 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0x706 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA request disabled. #0000 0001 DMA request on rising edge. #0001 0010 DMA request on falling edge. #0010 0011 DMA request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PORTB Pin Control and Interrupts PORT PORTB_ 0x4004A000 0 0xA4 registers 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA request disabled. #0000 0001 DMA request on rising edge. #0001 0010 DMA request on falling edge. #0010 0011 DMA request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PORTC Pin Control and Interrupts PORT PORTC_ 0x4004B000 0 0xA4 registers 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA request disabled. #0000 0001 DMA request on rising edge. #0001 0010 DMA request on falling edge. #0010 0011 DMA request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PORTD Pin Control and Interrupts PORT PORTD_ 0x4004C000 0 0xA4 registers PORTD 31 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA request disabled. #0000 0001 DMA request on rising edge. #0001 0010 DMA request on falling edge. #0010 0011 DMA request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PORTE Pin Control and Interrupts PORT PORTE_ 0x4004D000 0 0xA4 registers 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0x5 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA request disabled. #0000 0001 DMA request on rising edge. #0001 0010 DMA request on falling edge. #0010 0011 DMA request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MCG Multipurpose Clock Generator module MCG_ 0x40064000 0 0x10 registers MCG 27 C1 MCG Control 1 Register 0 8 read-write 0x4 0xFF IREFSTEN Internal Reference Stop Enable 0 1 read-write 0 Internal reference clock is disabled in Stop mode. #0 1 Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. #1 IRCLKEN Internal Reference Clock Enable 1 1 read-write 0 MCGIRCLK inactive. #0 1 MCGIRCLK active. #1 IREFS Internal Reference Select 2 1 read-write 0 External reference clock is selected. #0 1 The slow internal reference clock is selected. #1 FRDIV FLL External Reference Divider 3 3 read-write 000 If RANGE 0 = 0 , Divide Factor is 1; for all other RANGE 0 values, Divide Factor is 32. #000 001 If RANGE 0 = 0 , Divide Factor is 2; for all other RANGE 0 values, Divide Factor is 64. #001 010 If RANGE 0 = 0 , Divide Factor is 4; for all other RANGE 0 values, Divide Factor is 128. #010 011 If RANGE 0 = 0 , Divide Factor is 8; for all other RANGE 0 values, Divide Factor is 256. #011 100 If RANGE 0 = 0 , Divide Factor is 16; for all other RANGE 0 values, Divide Factor is 512. #100 101 If RANGE 0 = 0 , Divide Factor is 32; for all other RANGE 0 values, Divide Factor is 1024. #101 110 If RANGE 0 = 0 , Divide Factor is 64; for all other RANGE 0 values, Divide Factor is 1280 . #110 111 If RANGE 0 = 0 , Divide Factor is 128; for all other RANGE 0 values, Divide Factor is 1536 . #111 CLKS Clock Source Select 6 2 read-write 00 Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit). #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 11 Encoding 3 - Reserved. #11 C2 MCG Control 2 Register 0x1 8 read-write 0x80 0xFF IRCS Internal Reference Clock Select 0 1 read-write 0 Slow internal reference clock selected. #0 1 Fast internal reference clock selected. #1 LP Low Power Select 1 1 read-write 0 FLL or PLL is not disabled in bypass modes. #0 1 FLL or PLL is disabled in bypass modes (lower power) #1 EREFS0 External Reference Select 2 1 read-write 0 External reference clock requested. #0 1 Oscillator requested. #1 HGO0 High Gain Oscillator Select 3 1 read-write 0 Configure crystal oscillator for low-power operation. #0 1 Configure crystal oscillator for high-gain operation. #1 RANGE0 Frequency Range Select 4 2 read-write 00 Encoding 0 - Low frequency range selected for the crystal oscillator . #00 01 Encoding 1 - High frequency range selected for the crystal oscillator . #01 LOCRE0 Loss of Clock Reset Enable 7 1 read-write 0 Interrupt request is generated on a loss of OSC0 external reference clock. #0 1 Generate a reset request on a loss of OSC0 external reference clock. #1 C3 MCG Control 3 Register 0x2 8 read-write 0 0 SCTRIM Slow Internal Reference Clock Trim Setting 0 8 read-write C4 MCG Control 4 Register 0x3 8 read-write 0 0xE0 SCFTRIM Slow Internal Reference Clock Fine Trim 0 1 read-write FCTRIM Fast Internal Reference Clock Trim Setting 1 4 read-write DRST_DRS DCO Range Select 5 2 read-write 00 Encoding 0 - Low range (reset default). #00 01 Encoding 1 - Mid range. #01 10 Encoding 2 - Mid-high range. #10 11 Encoding 3 - High range. #11 DMX32 DCO Maximum Frequency with 32.768 kHz Reference 7 1 read-write 0 DCO has a default range of 25%. #0 1 DCO is fine-tuned for maximum frequency with 32.768 kHz reference. #1 C5 MCG Control 5 Register 0x4 8 read-write 0 0xFF PRDIV0 PLL External Reference Divider 0 5 read-write PLLSTEN0 PLL Stop Enable 5 1 read-write 0 MCGPLLCLK is disabled in any of the Stop modes. #0 1 MCGPLLCLK is enabled if system is in Normal Stop mode. #1 PLLCLKEN0 PLL Clock Enable 6 1 read-write 0 MCGPLLCLK is inactive. #0 1 MCGPLLCLK is active. #1 C6 MCG Control 6 Register 0x5 8 read-write 0 0xFF VDIV0 VCO 0 Divider 0 5 read-write CME0 Clock Monitor Enable 5 1 read-write 0 External clock monitor is disabled for OSC0. #0 1 External clock monitor is enabled for OSC0. #1 PLLS PLL Select 6 1 read-write 0 FLL is selected. #0 1 PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 2-4 MHz prior to setting the PLLS bit). #1 LOLIE0 Loss of Lock Interrrupt Enable 7 1 read-write 0 No interrupt request is generated on loss of lock. #0 1 Generate an interrupt request on loss of lock. #1 S MCG Status Register 0x6 8 read-write 0x10 0xFF IRCST Internal Reference Clock Status 0 1 read-only 0 Source of internal reference clock is the slow clock (32 kHz IRC). #0 1 Source of internal reference clock is the fast clock (4 MHz IRC). #1 OSCINIT0 OSC Initialization 1 1 read-only CLKST Clock Mode Status 2 2 read-only 00 Encoding 0 - Output of the FLL is selected (reset default). #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 11 Encoding 3 - Output of the PLL is selected. #11 IREFST Internal Reference Status 4 1 read-only 0 Source of FLL reference clock is the external reference clock. #0 1 Source of FLL reference clock is the internal reference clock. #1 PLLST PLL Select Status 5 1 read-only 0 Source of PLLS clock is FLL clock. #0 1 Source of PLLS clock is PLL output clock. #1 LOCK0 Lock Status 6 1 read-only 0 PLL is currently unlocked. #0 1 PLL is currently locked. #1 LOLS0 Loss of Lock Status 7 1 read-write 0 PLL has not lost lock since LOLS 0 was last cleared. #0 1 PLL has lost lock since LOLS 0 was last cleared. #1 SC MCG Status and Control Register 0x8 8 read-write 0x2 0xFF LOCS0 OSC0 Loss of Clock Status 0 1 read-write 0 Loss of OSC0 has not occurred. #0 1 Loss of OSC0 has occurred. #1 FCRDIV Fast Clock Internal Reference Divider 1 3 read-write 000 Divide Factor is 1 #000 001 Divide Factor is 2. #001 010 Divide Factor is 4. #010 011 Divide Factor is 8. #011 100 Divide Factor is 16 #100 101 Divide Factor is 32 #101 110 Divide Factor is 64 #110 111 Divide Factor is 128. #111 FLTPRSRV FLL Filter Preserve Enable 4 1 read-write 0 FLL filter and FLL frequency will reset on changes to currect clock mode. #0 1 Fll filter and FLL frequency retain their previous values during new clock mode change. #1 ATMF Automatic Trim Machine Fail Flag 5 1 read-write 0 Automatic Trim Machine completed normally. #0 1 Automatic Trim Machine failed. #1 ATMS Automatic Trim Machine Select 6 1 read-write 0 32 kHz Internal Reference Clock selected. #0 1 4 MHz Internal Reference Clock selected. #1 ATME Automatic Trim Machine Enable 7 1 read-write 0 Auto Trim Machine disabled. #0 1 Auto Trim Machine enabled. #1 ATCVH MCG Auto Trim Compare Value High Register 0xA 8 read-write 0 0xFF ATCVH ATM Compare Value High 0 8 read-write ATCVL MCG Auto Trim Compare Value Low Register 0xB 8 read-write 0 0xFF ATCVL ATM Compare Value Low 0 8 read-write C7 MCG Control 7 Register 0xC 8 read-only 0 0xFF C8 MCG Control 8 Register 0xD 8 read-write 0x80 0xFF LOLRE PLL Loss of Lock Reset Enable 6 1 read-write 0 Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request. #0 1 Generate a reset request on a PLL loss of lock indication. #1 C9 MCG Control 9 Register 0xE 8 read-only 0 0xFF C10 MCG Control 10 Register 0xF 8 read-only 0 0xFF OSC0 Oscillator OSC0_ 0x40065000 0 0x1 registers CR OSC Control Register 0 8 read-write 0 0xFF SC16P Oscillator 16 pF Capacitor Load Configure 0 1 read-write 0 Disable the selection. #0 1 Add 16 pF capacitor to the oscillator load. #1 SC8P Oscillator 8 pF Capacitor Load Configure 1 1 read-write 0 Disable the selection. #0 1 Add 8 pF capacitor to the oscillator load. #1 SC4P Oscillator 4 pF Capacitor Load Configure 2 1 read-write 0 Disable the selection. #0 1 Add 4 pF capacitor to the oscillator load. #1 SC2P Oscillator 2 pF Capacitor Load Configure 3 1 read-write 0 Disable the selection. #0 1 Add 2 pF capacitor to the oscillator load. #1 EREFSTEN External Reference Stop Enable 5 1 read-write 0 External reference clock is disabled in Stop mode. #0 1 External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. #1 ERCLKEN External Reference Enable 7 1 read-write 0 External reference clock is inactive. #0 1 External reference clock is enabled. #1 I2C0 Inter-Integrated Circuit I2C I2C0_ 0x40066000 0 0xC registers I2C0 8 A1 I2C Address Register 1 0 8 read-write 0 0xFF AD Address 1 7 read-write F I2C Frequency Divider register 0x1 8 read-write 0 0xFF ICR ClockRate 0 6 read-write MULT The MULT bits define the multiplier factor mul 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 C1 I2C Control Register 1 0x2 8 read-write 0 0xFF DMAEN DMA Enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled and the following conditions trigger the DMA request: While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from master to slave, then it is not required to check the SRW. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 RSTA Repeat START 2 1 write-only TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 S I2C Status register 0x3 8 read-write 0x80 0xFF RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 D I2C Data I/O register 0x4 8 read-write 0 0xFF DATA Data 0 8 read-write C2 I2C Control Register 2 0x5 8 read-write 0 0xFF AD Slave Address 0 3 read-write RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 HDRS High Drive Select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 FLT I2C Programmable Input Glitch Filter register 0x6 8 read-write 0 0xFF FLT I2C Programmable Filter Factor 0 5 read-write 0 No filter/bypass #00000 STOPIE I2C Bus Stop Interrupt Enable 5 1 read-write 0 Stop detection interrupt is disabled #0 1 Stop detection interrupt is enabled #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. #0 1 Stop holdoff is enabled. #1 RA I2C Range Address register 0x7 8 read-write 0 0xFF RAD Range Slave Address 1 7 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write 0 0xFF SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the bus clock / 64 #0 1 Timeout counter counts at the frequency of the bus clock #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. #1 A2 I2C Address Register 2 0x9 8 read-write 0xC2 0xFF SAD SMBus Address 1 7 read-write SLTH I2C SCL Low Timeout Register High 0xA 8 read-write 0 0xFF SSLT Most significant byte of SCL low timeout value that determines the timeout period of SCL low. 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write 0 0xFF SSLT Least significant byte of SCL low timeout value that determines the timeout period of SCL low. 0 8 read-write I2C1 Inter-Integrated Circuit I2C I2C1_ 0x40067000 0 0xC registers I2C1 9 A1 I2C Address Register 1 0 8 read-write 0 0xFF AD Address 1 7 read-write F I2C Frequency Divider register 0x1 8 read-write 0 0xFF ICR ClockRate 0 6 read-write MULT The MULT bits define the multiplier factor mul 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 C1 I2C Control Register 1 0x2 8 read-write 0 0xFF DMAEN DMA Enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled and the following conditions trigger the DMA request: While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from master to slave, then it is not required to check the SRW. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 RSTA Repeat START 2 1 write-only TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 S I2C Status register 0x3 8 read-write 0x80 0xFF RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 D I2C Data I/O register 0x4 8 read-write 0 0xFF DATA Data 0 8 read-write C2 I2C Control Register 2 0x5 8 read-write 0 0xFF AD Slave Address 0 3 read-write RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 HDRS High Drive Select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 FLT I2C Programmable Input Glitch Filter register 0x6 8 read-write 0 0xFF FLT I2C Programmable Filter Factor 0 5 read-write 0 No filter/bypass #00000 STOPIE I2C Bus Stop Interrupt Enable 5 1 read-write 0 Stop detection interrupt is disabled #0 1 Stop detection interrupt is enabled #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. #0 1 Stop holdoff is enabled. #1 RA I2C Range Address register 0x7 8 read-write 0 0xFF RAD Range Slave Address 1 7 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write 0 0xFF SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the bus clock / 64 #0 1 Timeout counter counts at the frequency of the bus clock #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. #1 A2 I2C Address Register 2 0x9 8 read-write 0xC2 0xFF SAD SMBus Address 1 7 read-write SLTH I2C SCL Low Timeout Register High 0xA 8 read-write 0 0xFF SSLT Most significant byte of SCL low timeout value that determines the timeout period of SCL low. 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write 0 0xFF SSLT Least significant byte of SCL low timeout value that determines the timeout period of SCL low. 0 8 read-write UART0 Universal Asynchronous Receiver/Transmitter UART0_ 0x4006A000 0 0xC registers UART0 12 BDH UART Baud Rate Register High 0 8 read-write 0 0xFF SBR Baud Rate Modulo Divisor. 0 5 read-write SBNS Stop Bit Number Select 5 1 read-write 0 One stop bit. #0 1 Two stop bit. #1 RXEDGIE RX Input Active Edge Interrupt Enable (for RXEDGIF) 6 1 read-write 0 Hardware interrupts from UART _S2[RXEDGIF] disabled (use polling). #0 1 Hardware interrupt requested when UART _S2[RXEDGIF] flag is 1. #1 LBKDIE LIN Break Detect Interrupt Enable (for LBKDIF) 7 1 read-write 0 Hardware interrupts from UART _S2[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when UART _S2[LBKDIF] flag is 1. #1 BDL UART Baud Rate Register Low 0x1 8 read-write 0x4 0xFF SBR Baud Rate Modulo Divisor 0 8 read-write C1 UART Control Register 1 0x2 8 read-write 0 0xFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle-line wakeup. #0 1 Address-mark wakeup. #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Receiver and transmitter use 8-bit data characters. #0 1 Receiver and transmitter use 9-bit data characters. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the UART _RX pins. #0 1 Single-wire UART mode where the UART _TX pin is connected to the transmitter output and receiver input. #1 DOZEEN Doze Enable 6 1 read-write 0 UART is enabled in Wait mode. #0 1 UART is disabled in Wait mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - UART _RX and UART _TX use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) UART _RX pin is not used by UART . #1 C2 UART Control Register 2 0x3 8 read-write 0 0xFF SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal UART receiver operation. #0 1 UART receiver in standby waiting for wakeup condition. #1 RE Receiver Enable 2 1 read-write 0 Receiver disabled. #0 1 Receiver enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter disabled. #0 1 Transmitter enabled. #1 ILIE Idle Line Interrupt Enable for IDLE 4 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 RIE Receiver Interrupt Enable for RDRF 5 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 TCIE Transmission Complete Interrupt Enable for TC 6 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TIE Transmit Interrupt Enable for TDRE 7 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 S1 UART Status Register 1 0x4 8 read-write 0xC0 0xFF PF Parity Error Flag 0 1 read-write 0 No parity error. #0 1 Parity error. #1 FE Framing Error Flag 1 1 read-write 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 NF Noise Flag 2 1 read-write 0 No noise detected. #0 1 Noise detected in the received character in UART _D. #1 OR Receiver Overrun Flag 3 1 read-write 0 No overrun. #0 1 Receive overrun (new UART data lost). #1 IDLE Idle Line Flag 4 1 read-write 0 No idle line detected. #0 1 Idle line was detected. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 Receive data buffer empty. #0 1 Receive data buffer full. #1 TC Transmission Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 Transmit data buffer full. #0 1 Transmit data buffer empty. #1 S2 UART Status Register 2 0x5 8 read-write 0 0xFF RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle waiting for a start bit. #0 1 UART receiver active ( UART _RXD input not idle). #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1). #1 BRK13 Break Character Generation Length 2 1 read-write 0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1). #1 RWUID Receive Wake Up Idle Detect 3 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 MSBF MSB First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M], C1[PE] and C4[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE]. #1 RXEDGIF UART _RX Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 C3 UART Control Register 3 0x6 8 read-write 0 0xFF PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupts disabled; use polling. #0 1 Hardware interrupt requested when FE is set. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupts disabled; use polling. #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 3 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 TXINV Transmit Data Inversion 4 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 TXDIR UART _TX Pin Direction in Single-Wire Mode 5 1 read-write 0 UART _TXD pin is an input in single-wire mode. #0 1 UART _TXD pin is an output in single-wire mode. #1 R9T8 Receive Bit 9 / Transmit Bit 8 6 1 read-write R8T9 Receive Bit 8 / Transmit Bit 9 7 1 read-write D UART Data Register 0x7 8 read-write 0 0xFF R0T0 Read receive data buffer 0 or write transmit data buffer 0. 0 1 read-write R1T1 Read receive data buffer 1 or write transmit data buffer 1. 1 1 read-write R2T2 Read receive data buffer 2 or write transmit data buffer 2. 2 1 read-write R3T3 Read receive data buffer 3 or write transmit data buffer 3. 3 1 read-write R4T4 Read receive data buffer 4 or write transmit data buffer 4. 4 1 read-write R5T5 Read receive data buffer 5 or write transmit data buffer 5. 5 1 read-write R6T6 Read receive data buffer 6 or write transmit data buffer 6. 6 1 read-write R7T7 Read receive data buffer 7 or write transmit data buffer 7. 7 1 read-write MA1 UART Match Address Registers 1 0x8 8 read-write 0 0xFF MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write 0 0xFF MA Match Address 0 8 read-write C4 UART Control Register 4 0xA 8 read-write 0xF 0xFF OSR Over Sampling Ratio 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 Receiver and transmitter use 8-bit or 9-bit data characters. #0 1 Receiver and transmitter use 10-bit data characters. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. #1 C5 UART Control Register 5 0xB 8 read-write 0 0xFF RESYNCDIS Resynchronization Disable 0 1 read-write 0 Resynchronization during received data word is supported #0 1 Resynchronization during received data word is disabled #1 BOTHEDGE Both Edge Sampling 1 1 read-write 0 Receiver samples input data using the rising edge of the baud rate clock. #0 1 Receiver samples input data using the rising and falling edge of the baud rate clock. #1 RDMAE Receiver Full DMA Enable 5 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDMAE Transmitter DMA Enable 7 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 UART1 Universal Asynchronous Receiver/Transmitter (UART) UART UART1_ 0x4006B000 0 0x9 registers UART1 13 BDH UART Baud Rate Register: High 0 8 read-write 0 0xFF SBR Baud Rate Modulo Divisor. 0 5 read-write SBNS Stop Bit Number Select 5 1 read-write 0 One stop bit. #0 1 Two stop bit. #1 RXEDGIE RxD Input Active Edge Interrupt Enable (for RXEDGIF) 6 1 read-write 0 Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling). #0 1 Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1. #1 LBKDIE LIN Break Detect Interrupt Enable (for LBKDIF) 7 1 read-write 0 Hardware interrupts from UART_S2[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when UART_S2[LBKDIF] flag is 1. #1 BDL UART Baud Rate Register: Low 0x1 8 read-write 0x4 0xFF SBR Baud Rate Modulo Divisor 0 8 read-write C1 UART Control Register 1 0x2 8 read-write 0 0xFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle-line wakeup. #0 1 Address-mark wakeup. #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Normal - start + 8 data bits (lsb first) + stop. #0 1 Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins. #0 1 Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clocks continue to run in wait mode so the UART can be the source of an interrupt that wakes up the CPU. #0 1 UART clocks freeze while CPU is in wait mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - RxD and TxD use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART. #1 C2 UART Control Register 2 0x3 8 read-write 0 0xFF SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal UART receiver operation. #0 1 UART receiver in standby waiting for wakeup condition. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 ILIE Idle Line Interrupt Enable for IDLE 4 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 RIE Receiver Interrupt Enable for RDRF 5 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 TCIE Transmission Complete Interrupt Enable for TC 6 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TIE Transmit Interrupt Enable for TDRE 7 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 S1 UART Status Register 1 0x4 8 read-only 0xC0 0xFF PF Parity Error Flag 0 1 read-only 0 No parity error. #0 1 Parity error. #1 FE Framing Error Flag 1 1 read-only 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 NF Noise Flag 2 1 read-only 0 No noise detected. #0 1 Noise detected in the received character in UART_D. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun. #0 1 Receive overrun (new UART data lost). #1 IDLE Idle Line Flag 4 1 read-only 0 No idle line detected. #0 1 Idle line was detected. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 Receive data register empty. #0 1 Receive data register full. #1 TC Transmission Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 Transmit data register (buffer) full. #0 1 Transmit data register (buffer) empty. #1 S2 UART Status Register 2 0x5 8 read-write 0 0xFF RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle waiting for a start bit. #0 1 UART receiver active (RxD input not idle). #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1). #0 1 Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 13 (if M = 1, SBNS = 1). #1 BRK13 Break Character Generation Length 2 1 read-write 0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1). #0 1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1). #1 RWUID Receive Wake Up Idle Detect 3 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 C3 UART Control Register 3 0x6 8 read-write 0 0xFF PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupts disabled; use polling). #0 1 Hardware interrupt requested when FE is set. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupts disabled; use polling). #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 3 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 TXINV Transmit Data Inversion 4 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 TXDIR TxD Pin Direction in Single-Wire Mode 5 1 read-write 0 TxD pin is an input in single-wire mode. #0 1 TxD pin is an output in single-wire mode. #1 T8 Ninth Data Bit for Transmitter 6 1 read-write R8 Ninth Data Bit for Receiver 7 1 read-only D UART Data Register 0x7 8 read-write 0 0xFF R0T0 Read receive data buffer 0 or write transmit data buffer 0. 0 1 read-write R1T1 Read receive data buffer 1 or write transmit data buffer 1. 1 1 read-write R2T2 Read receive data buffer 2 or write transmit data buffer 2. 2 1 read-write R3T3 Read receive data buffer 3 or write transmit data buffer 3. 3 1 read-write R4T4 Read receive data buffer 4 or write transmit data buffer 4. 4 1 read-write R5T5 Read receive data buffer 5 or write transmit data buffer 5. 5 1 read-write R6T6 Read receive data buffer 6 or write transmit data buffer 6. 6 1 read-write R7T7 Read receive data buffer 7 or write transmit data buffer 7. 7 1 read-write C4 UART Control Register 4 0x8 8 read-write 0 0xFF RDMAS Receiver Full DMA Select 5 1 read-write 0 If RIE is set and the RDRF flag is set, the RDRF interrupt request signal is asserted to request interrupt service. #0 1 If RIE is set and the RDRF flag is set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If TIE is set and the TDRE flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If TIE is set and the TDRE flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 UART2 Universal Asynchronous Receiver/Transmitter (UART) UART UART2_ 0x4006C000 0 0x9 registers UART2 14 BDH UART Baud Rate Register: High 0 8 read-write 0 0xFF SBR Baud Rate Modulo Divisor. 0 5 read-write SBNS Stop Bit Number Select 5 1 read-write 0 One stop bit. #0 1 Two stop bit. #1 RXEDGIE RxD Input Active Edge Interrupt Enable (for RXEDGIF) 6 1 read-write 0 Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling). #0 1 Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1. #1 LBKDIE LIN Break Detect Interrupt Enable (for LBKDIF) 7 1 read-write 0 Hardware interrupts from UART_S2[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when UART_S2[LBKDIF] flag is 1. #1 BDL UART Baud Rate Register: Low 0x1 8 read-write 0x4 0xFF SBR Baud Rate Modulo Divisor 0 8 read-write C1 UART Control Register 1 0x2 8 read-write 0 0xFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle-line wakeup. #0 1 Address-mark wakeup. #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Normal - start + 8 data bits (lsb first) + stop. #0 1 Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins. #0 1 Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clocks continue to run in wait mode so the UART can be the source of an interrupt that wakes up the CPU. #0 1 UART clocks freeze while CPU is in wait mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - RxD and TxD use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART. #1 C2 UART Control Register 2 0x3 8 read-write 0 0xFF SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal UART receiver operation. #0 1 UART receiver in standby waiting for wakeup condition. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 ILIE Idle Line Interrupt Enable for IDLE 4 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 RIE Receiver Interrupt Enable for RDRF 5 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 TCIE Transmission Complete Interrupt Enable for TC 6 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TIE Transmit Interrupt Enable for TDRE 7 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 S1 UART Status Register 1 0x4 8 read-only 0xC0 0xFF PF Parity Error Flag 0 1 read-only 0 No parity error. #0 1 Parity error. #1 FE Framing Error Flag 1 1 read-only 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 NF Noise Flag 2 1 read-only 0 No noise detected. #0 1 Noise detected in the received character in UART_D. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun. #0 1 Receive overrun (new UART data lost). #1 IDLE Idle Line Flag 4 1 read-only 0 No idle line detected. #0 1 Idle line was detected. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 Receive data register empty. #0 1 Receive data register full. #1 TC Transmission Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 Transmit data register (buffer) full. #0 1 Transmit data register (buffer) empty. #1 S2 UART Status Register 2 0x5 8 read-write 0 0xFF RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle waiting for a start bit. #0 1 UART receiver active (RxD input not idle). #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1). #0 1 Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 13 (if M = 1, SBNS = 1). #1 BRK13 Break Character Generation Length 2 1 read-write 0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1). #0 1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1). #1 RWUID Receive Wake Up Idle Detect 3 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 C3 UART Control Register 3 0x6 8 read-write 0 0xFF PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupts disabled; use polling). #0 1 Hardware interrupt requested when FE is set. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupts disabled; use polling). #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 3 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 TXINV Transmit Data Inversion 4 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 TXDIR TxD Pin Direction in Single-Wire Mode 5 1 read-write 0 TxD pin is an input in single-wire mode. #0 1 TxD pin is an output in single-wire mode. #1 T8 Ninth Data Bit for Transmitter 6 1 read-write R8 Ninth Data Bit for Receiver 7 1 read-only D UART Data Register 0x7 8 read-write 0 0xFF R0T0 Read receive data buffer 0 or write transmit data buffer 0. 0 1 read-write R1T1 Read receive data buffer 1 or write transmit data buffer 1. 1 1 read-write R2T2 Read receive data buffer 2 or write transmit data buffer 2. 2 1 read-write R3T3 Read receive data buffer 3 or write transmit data buffer 3. 3 1 read-write R4T4 Read receive data buffer 4 or write transmit data buffer 4. 4 1 read-write R5T5 Read receive data buffer 5 or write transmit data buffer 5. 5 1 read-write R6T6 Read receive data buffer 6 or write transmit data buffer 6. 6 1 read-write R7T7 Read receive data buffer 7 or write transmit data buffer 7. 7 1 read-write C4 UART Control Register 4 0x8 8 read-write 0 0xFF RDMAS Receiver Full DMA Select 5 1 read-write 0 If RIE is set and the RDRF flag is set, the RDRF interrupt request signal is asserted to request interrupt service. #0 1 If RIE is set and the RDRF flag is set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If TIE is set and the TDRE flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If TIE is set and the TDRE flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 CMP0 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP0_ 0x40073000 0 0x6 registers CMP0 16 CR0 CMP Control Register 0 0 8 read-write 0 0xFF HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. #000 001 One sample must agree. The comparator output is simply sampled. #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 CR1 CMP Control Register 1 0x1 8 read-write 0 0xFF EN Comparator Module Enable 0 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. #0 1 CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. #1 COS Comparator Output Select 2 1 read-write 0 Set the filtered comparator output (CMPO) to equal COUT. #0 1 Set the unfiltered comparator output (CMPO) to equal COUTA. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 PMODE Power Mode Select 4 1 read-write 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 TRIGM Trigger Mode Enable 5 1 read-write 0 Trigger mode is disabled. #0 1 Trigger mode is enabled. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 SE Sample Enable 7 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 FPR CMP Filter Period Register 0x2 8 read-write 0 0xFF FILT_PER Filter Sample Period 0 8 read-write SCR CMP Status and Control Register 0x3 8 read-write 0 0xFF COUT Analog Comparator Output 0 1 read-only CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling-edge on COUT has not been detected. #0 1 Falling-edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising-edge on COUT has not been detected. #0 1 Rising-edge on COUT has occurred. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 DMAEN DMA Enable Control 6 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 DACCR DAC Control Register 0x4 8 read-write 0 0xFF VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 V is selected as resistor ladder network supply reference V. in1 in #0 1 V is selected as resistor ladder network supply reference V. in2 in #1 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 MUXCR MUX Control Register 0x5 8 read-write 0 0xFF MSEL Minus Input Mux Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input Mux Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSTM Pass Through Mode Enable 7 1 read-write 0 Pass Through Mode is disabled. #0 1 Pass Through Mode is enabled. #1 SPI0 Serial Peripheral Interface SPI SPI0_ 0x40076000 0 0x8 registers SPI0 10 C1 SPI control register 1 0 8 read-write 0x4 0xFF LSBFE LSB first (shifter direction) 0 1 read-write 0 SPI serial data transfers start with most significant bit #0 1 SPI serial data transfers start with least significant bit #1 SSOE Slave select output enable 1 1 read-write 0 When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input. #0 1 When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input. #1 CPHA Clock phase 2 1 read-write 0 First edge on SPSCK occurs at the middle of the first cycle of a data transfer #0 1 First edge on SPSCK occurs at the start of the first cycle of a data transfer #1 CPOL Clock polarity 3 1 read-write 0 Active-high SPI clock (idles low) #0 1 Active-low SPI clock (idles high) #1 MSTR Master/slave mode select 4 1 read-write 0 SPI module configured as a slave SPI device #0 1 SPI module configured as a master SPI device #1 SPTIE SPI transmit interrupt enable 5 1 read-write 0 Interrupts from SPTEF inhibited (use polling) #0 1 When SPTEF is 1, hardware interrupt requested #1 SPE SPI system enable 6 1 read-write 0 SPI system inactive #0 1 SPI system enabled #1 SPIE SPI interrupt enable: for SPRF and MODF 7 1 read-write 0 Interrupts from SPRF and MODF are inhibited-use polling #0 1 Request a hardware interrupt when SPRF or MODF is 1 #1 C2 SPI control register 2 0x1 8 read-write 0 0xFF SPC0 SPI pin control 0 0 1 read-write 0 SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in. #0 1 SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI. #1 SPISWAI SPI stop in wait mode 1 1 read-write 0 SPI clocks continue to operate in wait mode #0 1 SPI clocks stop when the MCU enters wait mode #1 RXDMAE Receive DMA enable 2 1 read-write 0 DMA request for receive is disabled and interrupt from SPRF is allowed #0 1 DMA request for receive is enabled and interrupt from SPRF is disabled #1 BIDIROE Bidirectional mode output enable 3 1 read-write 0 Output driver disabled so SPI data I/O pin acts as an input #0 1 SPI I/O pin enabled as an output #1 MODFEN Master mode-fault function enable 4 1 read-write 0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI #0 1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output #1 TXDMAE Transmit DMA enable 5 1 read-write 0 DMA request for transmit is disabled and interrupt from SPTEF is allowed #0 1 DMA request for transmit is enabled and interrupt from SPTEF is disabled #1 SPMIE SPI match interrupt enable 7 1 read-write 0 Interrupts from SPMF inhibited (use polling) #0 1 When SPMF is 1, requests a hardware interrupt #1 BR SPI baud rate register 0x2 8 read-write 0 0xFF SPR SPI baud rate divisor 0 4 read-write 0000 Baud rate divisor is 2 #0000 0001 Baud rate divisor is 4 #0001 0010 Baud rate divisor is 8 #0010 0011 Baud rate divisor is 16 #0011 0100 Baud rate divisor is 32 #0100 0101 Baud rate divisor is 64 #0101 0110 Baud rate divisor is 128 #0110 0111 Baud rate divisor is 256 #0111 1000 Baud rate divisor is 512 #1000 SPPR SPI baud rate prescale divisor 4 3 read-write 000 Baud rate prescaler divisor is 1 #000 001 Baud rate prescaler divisor is 2 #001 010 Baud rate prescaler divisor is 3 #010 011 Baud rate prescaler divisor is 4 #011 100 Baud rate prescaler divisor is 5 #100 101 Baud rate prescaler divisor is 6 #101 110 Baud rate prescaler divisor is 7 #110 111 Baud rate prescaler divisor is 8 #111 S SPI status register 0x3 8 read-write 0x20 0xFF MODF Master mode fault flag 4 1 read-only 0 No mode fault error #0 1 Mode fault error detected #1 SPTEF SPI transmit buffer empty flag 5 1 read-only 0 SPI transmit buffer not empty #0 1 SPI transmit buffer empty #1 SPMF SPI match flag 6 1 read-write 0 Value in the receive data buffer does not match the value in the M register #0 1 Value in the receive data buffer matches the value in the M register #1 SPRF SPI read buffer full flag 7 1 read-only 0 No data available in the receive data buffer #0 1 Data available in the receive data buffer #1 D SPI data register 0x5 8 read-write 0 0xFF Bits Data (low byte) 0 8 read-write M SPI match register 0x7 8 read-write 0 0xFF Bits Hardware compare value (low byte) 0 8 read-write SPI1 Serial Peripheral Interface SPI SPI1_ 0x40077000 0 0x8 registers SPI1 11 C1 SPI control register 1 0 8 read-write 0x4 0xFF LSBFE LSB first (shifter direction) 0 1 read-write 0 SPI serial data transfers start with most significant bit #0 1 SPI serial data transfers start with least significant bit #1 SSOE Slave select output enable 1 1 read-write 0 When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input. #0 1 When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input. #1 CPHA Clock phase 2 1 read-write 0 First edge on SPSCK occurs at the middle of the first cycle of a data transfer #0 1 First edge on SPSCK occurs at the start of the first cycle of a data transfer #1 CPOL Clock polarity 3 1 read-write 0 Active-high SPI clock (idles low) #0 1 Active-low SPI clock (idles high) #1 MSTR Master/slave mode select 4 1 read-write 0 SPI module configured as a slave SPI device #0 1 SPI module configured as a master SPI device #1 SPTIE SPI transmit interrupt enable 5 1 read-write 0 Interrupts from SPTEF inhibited (use polling) #0 1 When SPTEF is 1, hardware interrupt requested #1 SPE SPI system enable 6 1 read-write 0 SPI system inactive #0 1 SPI system enabled #1 SPIE SPI interrupt enable: for SPRF and MODF 7 1 read-write 0 Interrupts from SPRF and MODF are inhibited-use polling #0 1 Request a hardware interrupt when SPRF or MODF is 1 #1 C2 SPI control register 2 0x1 8 read-write 0 0xFF SPC0 SPI pin control 0 0 1 read-write 0 SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in. #0 1 SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI. #1 SPISWAI SPI stop in wait mode 1 1 read-write 0 SPI clocks continue to operate in wait mode #0 1 SPI clocks stop when the MCU enters wait mode #1 RXDMAE Receive DMA enable 2 1 read-write 0 DMA request for receive is disabled and interrupt from SPRF is allowed #0 1 DMA request for receive is enabled and interrupt from SPRF is disabled #1 BIDIROE Bidirectional mode output enable 3 1 read-write 0 Output driver disabled so SPI data I/O pin acts as an input #0 1 SPI I/O pin enabled as an output #1 MODFEN Master mode-fault function enable 4 1 read-write 0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI #0 1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output #1 TXDMAE Transmit DMA enable 5 1 read-write 0 DMA request for transmit is disabled and interrupt from SPTEF is allowed #0 1 DMA request for transmit is enabled and interrupt from SPTEF is disabled #1 SPMIE SPI match interrupt enable 7 1 read-write 0 Interrupts from SPMF inhibited (use polling) #0 1 When SPMF is 1, requests a hardware interrupt #1 BR SPI baud rate register 0x2 8 read-write 0 0xFF SPR SPI baud rate divisor 0 4 read-write 0000 Baud rate divisor is 2 #0000 0001 Baud rate divisor is 4 #0001 0010 Baud rate divisor is 8 #0010 0011 Baud rate divisor is 16 #0011 0100 Baud rate divisor is 32 #0100 0101 Baud rate divisor is 64 #0101 0110 Baud rate divisor is 128 #0110 0111 Baud rate divisor is 256 #0111 1000 Baud rate divisor is 512 #1000 SPPR SPI baud rate prescale divisor 4 3 read-write 000 Baud rate prescaler divisor is 1 #000 001 Baud rate prescaler divisor is 2 #001 010 Baud rate prescaler divisor is 3 #010 011 Baud rate prescaler divisor is 4 #011 100 Baud rate prescaler divisor is 5 #100 101 Baud rate prescaler divisor is 6 #101 110 Baud rate prescaler divisor is 7 #110 111 Baud rate prescaler divisor is 8 #111 S SPI status register 0x3 8 read-write 0x20 0xFF MODF Master mode fault flag 4 1 read-only 0 No mode fault error #0 1 Mode fault error detected #1 SPTEF SPI transmit buffer empty flag 5 1 read-only 0 SPI transmit buffer not empty #0 1 SPI transmit buffer empty #1 SPMF SPI match flag 6 1 read-write 0 Value in the receive data buffer does not match the value in the M register #0 1 Value in the receive data buffer matches the value in the M register #1 SPRF SPI read buffer full flag 7 1 read-only 0 No data available in the receive data buffer #0 1 Data available in the receive data buffer #1 D SPI data register 0x5 8 read-write 0 0xFF Bits Data (low byte) 0 8 read-write M SPI match register 0x7 8 read-write 0 0xFF Bits Hardware compare value (low byte) 0 8 read-write LLWU Low leakage wakeup unit LLWU_ 0x4007C000 0 0xA registers LLWU 7 PE1 LLWU Pin Enable 1 register 0 8 read-write 0 0xFF WUPE0 Wakeup Pin Enable For LLWU_P0 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE1 Wakeup Pin Enable For LLWU_P1 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE2 Wakeup Pin Enable For LLWU_P2 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE3 Wakeup Pin Enable For LLWU_P3 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE2 LLWU Pin Enable 2 register 0x1 8 read-write 0 0xFF WUPE4 Wakeup Pin Enable For LLWU_P4 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE5 Wakeup Pin Enable For LLWU_P5 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE6 Wakeup Pin Enable For LLWU_P6 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE7 Wakeup Pin Enable For LLWU_P7 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE3 LLWU Pin Enable 3 register 0x2 8 read-write 0 0xFF WUPE8 Wakeup Pin Enable For LLWU_P8 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE9 Wakeup Pin Enable For LLWU_P9 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE10 Wakeup Pin Enable For LLWU_P10 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE11 Wakeup Pin Enable For LLWU_P11 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE4 LLWU Pin Enable 4 register 0x3 8 read-write 0 0xFF WUPE12 Wakeup Pin Enable For LLWU_P12 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE13 Wakeup Pin Enable For LLWU_P13 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE14 Wakeup Pin Enable For LLWU_P14 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE15 Wakeup Pin Enable For LLWU_P15 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 ME LLWU Module Enable register 0x4 8 read-write 0 0xFF WUME0 Wakeup Module Enable For Module 0 0 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME1 Wakeup Module Enable for Module 1 1 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME2 Wakeup Module Enable For Module 2 2 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME3 Wakeup Module Enable For Module 3 3 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME4 Wakeup Module Enable For Module 4 4 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME5 Wakeup Module Enable For Module 5 5 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME6 Wakeup Module Enable For Module 6 6 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME7 Wakeup Module Enable For Module 7 7 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 F1 LLWU Flag 1 register 0x5 8 read-write 0 0xFF WUF0 Wakeup Flag For LLWU_P0 0 1 read-write 0 LLWU_P0 input was not a wakeup source #0 1 LLWU_P0 input was a wakeup source #1 WUF1 Wakeup Flag For LLWU_P1 1 1 read-write 0 LLWU_P1 input was not a wakeup source #0 1 LLWU_P1 input was a wakeup source #1 WUF2 Wakeup Flag For LLWU_P2 2 1 read-write 0 LLWU_P2 input was not a wakeup source #0 1 LLWU_P2 input was a wakeup source #1 WUF3 Wakeup Flag For LLWU_P3 3 1 read-write 0 LLWU_P3 input was not a wakeup source #0 1 LLWU_P3 input was a wakeup source #1 WUF4 Wakeup Flag For LLWU_P4 4 1 read-write 0 LLWU_P4 input was not a wakeup source #0 1 LLWU_P4 input was a wakeup source #1 WUF5 Wakeup Flag For LLWU_P5 5 1 read-write 0 LLWU_P5 input was not a wakeup source #0 1 LLWU_P5 input was a wakeup source #1 WUF6 Wakeup Flag For LLWU_P6 6 1 read-write 0 LLWU_P6 input was not a wakeup source #0 1 LLWU_P6 input was a wakeup source #1 WUF7 Wakeup Flag For LLWU_P7 7 1 read-write 0 LLWU_P7 input was not a wakeup source #0 1 LLWU_P7 input was a wakeup source #1 F2 LLWU Flag 2 register 0x6 8 read-write 0 0xFF WUF8 Wakeup Flag For LLWU_P8 0 1 read-write 0 LLWU_P8 input was not a wakeup source #0 1 LLWU_P8 input was a wakeup source #1 WUF9 Wakeup Flag For LLWU_P9 1 1 read-write 0 LLWU_P9 input was not a wakeup source #0 1 LLWU_P9 input was a wakeup source #1 WUF10 Wakeup Flag For LLWU_P10 2 1 read-write 0 LLWU_P10 input was not a wakeup source #0 1 LLWU_P10 input was a wakeup source #1 WUF11 Wakeup Flag For LLWU_P11 3 1 read-write 0 LLWU_P11 input was not a wakeup source #0 1 LLWU_P11 input was a wakeup source #1 WUF12 Wakeup Flag For LLWU_P12 4 1 read-write 0 LLWU_P12 input was not a wakeup source #0 1 LLWU_P12 input was a wakeup source #1 WUF13 Wakeup Flag For LLWU_P13 5 1 read-write 0 LLWU_P13 input was not a wakeup source #0 1 LLWU_P13 input was a wakeup source #1 WUF14 Wakeup Flag For LLWU_P14 6 1 read-write 0 LLWU_P14 input was not a wakeup source #0 1 LLWU_P14 input was a wakeup source #1 WUF15 Wakeup Flag For LLWU_P15 7 1 read-write 0 LLWU_P15 input was not a wakeup source #0 1 LLWU_P15 input was a wakeup source #1 F3 LLWU Flag 3 register 0x7 8 read-only 0 0xFF MWUF0 Wakeup flag For module 0 0 1 read-only 0 Module 0 input was not a wakeup source #0 1 Module 0 input was a wakeup source #1 MWUF1 Wakeup flag For module 1 1 1 read-only 0 Module 1 input was not a wakeup source #0 1 Module 1 input was a wakeup source #1 MWUF2 Wakeup flag For module 2 2 1 read-only 0 Module 2 input was not a wakeup source #0 1 Module 2 input was a wakeup source #1 MWUF3 Wakeup flag For module 3 3 1 read-only 0 Module 3 input was not a wakeup source #0 1 Module 3 input was a wakeup source #1 MWUF4 Wakeup flag For module 4 4 1 read-only 0 Module 4 input was not a wakeup source #0 1 Module 4 input was a wakeup source #1 MWUF5 Wakeup flag For module 5 5 1 read-only 0 Module 5 input was not a wakeup source #0 1 Module 5 input was a wakeup source #1 MWUF6 Wakeup flag For module 6 6 1 read-only 0 Module 6 input was not a wakeup source #0 1 Module 6 input was a wakeup source #1 MWUF7 Wakeup flag For module 7 7 1 read-only 0 Module 7 input was not a wakeup source #0 1 Module 7 input was a wakeup source #1 FILT1 LLWU Pin Filter 1 register 0x8 8 read-write 0 0xFF FILTSEL Filter Pin Select 0 4 read-write 0000 Select LLWU_P0 for filter #0000 1111 Select LLWU_P15 for filter #1111 FILTE Digital Filter On External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 1 was not a wakeup source #0 1 Pin Filter 1 was a wakeup source #1 FILT2 LLWU Pin Filter 2 register 0x9 8 read-write 0 0xFF FILTSEL Filter Pin Select 0 4 read-write 0000 Select LLWU_P0 for filter #0000 1111 Select LLWU_P15 for filter #1111 FILTE Digital Filter On External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 2 was not a wakeup source #0 1 Pin Filter 2 was a wakeup source #1 PMC Power Management Controller PMC_ 0x4007D000 0 0x3 registers LVD_LVW 6 LVDSC1 Low Voltage Detect Status And Control 1 register 0 8 read-write 0x10 0xFF LVDV Low-Voltage Detect Voltage Select 0 2 read-write 00 Low trip point selected (V LVD = V LVDL ) #00 01 High trip point selected (V LVD = V LVDH ) #01 LVDRE Low-Voltage Detect Reset Enable 4 1 read-write 0 LVDF does not generate hardware resets #0 1 Force an MCU reset when LVDF = 1 #1 LVDIE Low-Voltage Detect Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVDF = 1 #1 LVDACK Low-Voltage Detect Acknowledge 6 1 write-only LVDF Low-Voltage Detect Flag 7 1 read-only 0 Low-voltage event not detected #0 1 Low-voltage event detected #1 LVDSC2 Low Voltage Detect Status And Control 2 register 0x1 8 read-write 0 0xFF LVWV Low-Voltage Warning Voltage Select 0 2 read-write 00 Low trip point selected (VLVW = VLVW1) #00 01 Mid 1 trip point selected (VLVW = VLVW2) #01 10 Mid 2 trip point selected (VLVW = VLVW3) #10 11 High trip point selected (VLVW = VLVW4) #11 LVWIE Low-Voltage Warning Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVWF = 1 #1 LVWACK Low-Voltage Warning Acknowledge 6 1 write-only LVWF Low-Voltage Warning Flag 7 1 read-only 0 Low-voltage warning event not detected #0 1 Low-voltage warning event detected #1 REGSC Regulator Status And Control register 0x2 8 read-write 0x4 0xFF BGBE Bandgap Buffer Enable 0 1 read-write 0 Bandgap buffer not enabled #0 1 Bandgap buffer enabled #1 REGONS Regulator In Run Regulation Status 2 1 read-only 0 Regulator is in stop regulation or in transition to/from it #0 1 Regulator is in run regulation #1 ACKISO Acknowledge Isolation 3 1 read-write 0 Peripherals and I/O pads are in normal run state #0 1 Certain peripherals and I/O pads are in an isolated and latched state #1 BGEN Bandgap Enable In VLPx Operation 4 1 read-write 0 Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes #0 1 Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes #1 SMC System Mode Controller SMC_ 0x4007E000 0 0x4 registers PMPROT Power Mode Protection register 0 8 read-write 0 0xFF AVLLS Allow Very-Low-Leakage Stop Mode 1 1 read-write 0 Any VLLSx mode is not allowed #0 1 Any VLLSx mode is allowed #1 ALLS Allow Low-Leakage Stop Mode 3 1 read-write 0 LLS is not allowed #0 1 LLS is allowed #1 AVLP Allow Very-Low-Power Modes 5 1 read-write 0 VLPR, VLPW and VLPS are not allowed #0 1 VLPR, VLPW and VLPS are allowed #1 PMCTRL Power Mode Control register 0x1 8 read-write 0 0xFF STOPM Stop Mode Control 0 3 read-write 000 Normal Stop (STOP) #000 010 Very-Low-Power Stop (VLPS) #010 011 Low-Leakage Stop (LLS) #011 100 Very-Low-Leakage Stop (VLLSx) #100 110 Reseved #110 STOPA Stop Aborted 3 1 read-only 0 The previous stop mode entry was successsful. #0 1 The previous stop mode entry was aborted. #1 RUNM Run Mode Control 5 2 read-write 00 Normal Run mode (RUN) #00 10 Very-Low-Power Run mode (VLPR) #10 VLLSCTRL VLLS Control register 0x2 8 read-write 0x3 0xFF VLLSM VLLS Mode Control 0 3 read-write 000 VLLS0 #000 001 VLLS1 #001 010 VLLS2 #010 011 VLLS3 #011 PORPO POR Power Option 5 1 read-write 0 POR detect circuit is enabled in VLLS0 #0 1 POR detect circuit is disabled in VLLS0 #1 PMSTAT Power Mode Status register 0x3 8 read-only 0x1 0xFF PMSTAT When debug is enabled, the PMSTAT will not update to STOP or VLPS 0 7 read-only RCM Reset Control Module RCM_ 0x4007F000 0 0x6 registers SRS0 System Reset Status Register 0 0 8 read-only 0x82 0xFF WAKEUP Low Leakage Wakeup Reset 0 1 read-only 0 Reset not caused by LLWU module wakeup source #0 1 Reset caused by LLWU module wakeup source #1 LVD Low-Voltage Detect Reset 1 1 read-only 0 Reset not caused by LVD trip or POR #0 1 Reset caused by LVD trip or POR #1 LOC Loss-of-Clock Reset 2 1 read-only 0 Reset not caused by a loss of external clock. #0 1 Reset caused by a loss of external clock. #1 LOL Loss-of-Lock Reset 3 1 read-only 0 Reset not caused by a loss of lock in the PLL #0 1 Reset caused by a loss of lock in the PLL #1 WDOG Watchdog 5 1 read-only 0 Reset not caused by watchdog timeout #0 1 Reset caused by watchdog timeout #1 PIN External Reset Pin 6 1 read-only 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 POR Power-On Reset 7 1 read-only 0 Reset not caused by POR #0 1 Reset caused by POR #1 SRS1 System Reset Status Register 1 0x1 8 read-only 0 0xFF LOCKUP Core Lockup 1 1 read-only 0 Reset not caused by core LOCKUP event #0 1 Reset caused by core LOCKUP event #1 SW Software 2 1 read-only 0 Reset not caused by software setting of SYSRESETREQ bit #0 1 Reset caused by software setting of SYSRESETREQ bit #1 MDM_AP MDM-AP System Reset Request 3 1 read-only 0 Reset not caused by host debugger system setting of the System Reset Request bit #0 1 Reset caused by host debugger system setting of the System Reset Request bit #1 SACKERR Stop Mode Acknowledge Error Reset 5 1 read-only 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode #0 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode #1 RPFC Reset Pin Filter Control register 0x4 8 read-write 0 0xFF RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes 0 2 read-write 00 All filtering disabled #00 01 Bus clock filter enabled for normal operation #01 10 LPO clock filter enabled for normal operation #10 RSTFLTSS Reset Pin Filter Select in Stop Mode 2 1 read-write 0 All filtering disabled #0 1 LPO clock filter enabled #1 RPFW Reset Pin Filter Width register 0x5 8 read-write 0 0xFF RSTFLTSEL Reset Pin Filter Bus Clock Select 0 5 read-write 00000 Bus clock filter count is 1 #00000 00001 Bus clock filter count is 2 #00001 00010 Bus clock filter count is 3 #00010 00011 Bus clock filter count is 4 #00011 00100 Bus clock filter count is 5 #00100 00101 Bus clock filter count is 6 #00101 00110 Bus clock filter count is 7 #00110 00111 Bus clock filter count is 8 #00111 01000 Bus clock filter count is 9 #01000 01001 Bus clock filter count is 10 #01001 01010 Bus clock filter count is 11 #01010 01011 Bus clock filter count is 12 #01011 01100 Bus clock filter count is 13 #01100 01101 Bus clock filter count is 14 #01101 01110 Bus clock filter count is 15 #01110 01111 Bus clock filter count is 16 #01111 10000 Bus clock filter count is 17 #10000 10001 Bus clock filter count is 18 #10001 10010 Bus clock filter count is 19 #10010 10011 Bus clock filter count is 20 #10011 10100 Bus clock filter count is 21 #10100 10101 Bus clock filter count is 22 #10101 10110 Bus clock filter count is 23 #10110 10111 Bus clock filter count is 24 #10111 11000 Bus clock filter count is 25 #11000 11001 Bus clock filter count is 26 #11001 11010 Bus clock filter count is 27 #11010 11011 Bus clock filter count is 28 #11011 11100 Bus clock filter count is 29 #11100 11101 Bus clock filter count is 30 #11101 11110 Bus clock filter count is 31 #11110 11111 Bus clock filter count is 32 #11111 GPIOA General Purpose Input/Output GPIO GPIOA_ 0x400FF000 0 0x18 registers PORTA 30 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOB General Purpose Input/Output GPIO GPIOB_ 0x400FF040 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOC General Purpose Input/Output GPIO GPIOC_ 0x400FF080 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOD General Purpose Input/Output GPIO GPIOD_ 0x400FF0C0 0 0x18 registers PORTD 31 PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 GPIOE General Purpose Input/Output GPIO GPIOE_ 0x400FF100 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 MTB Micro Trace Buffer MTB_ 0xF0000000 0 0x1000 registers POSITION MTB Position Register 0 32 read-write 0 0x3 WRAP This bit is set to 1 automatically when the POINTER value wraps as determined by the MTB_MASTER[MASK] bit in the MASTER Trace Control Register 2 1 read-write POINTER Trace Packet Address Pointer 3 29 read-write MASTER MTB Master Register 0x4 32 read-write 0x80 0xFFFFFFFF MASK Mask 0 5 read-write TSTARTEN Trace start input enable 5 1 read-write TSTOPEN Trace stop input enable 6 1 read-write SFRWPRIV Special Function Register Write Privilege bit 7 1 read-write RAMPRIV RAM privilege bit 8 1 read-write HALTREQ Halt request bit 9 1 read-write EN Main trace enable bit 31 1 read-write FLOW MTB Flow Register 0x8 32 read-write 0 0x4 AUTOSTOP If this bit is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then the MTB_MASTER[EN] bit is automatically set to 0 0 1 read-write AUTOHALT If this bit is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then the MTB_MASTER[HALTREQ] bit is automatically set to 1 1 1 read-write WATERMARK WATERMARK value 3 29 read-write BASE MTB Base Register 0xC 32 read-only 0 0 BASEADDR This value is defined with a hardwired signal and the expression: 0x2000_0000 - (RAM_Size/4) 0 32 read-only MODECTRL Integration Mode Control Register 0xF00 32 read-only 0 0xFFFFFFFF MODECTRL Hardwired to 0x0000_0000 0 32 read-only TAGSET Claim TAG Set Register 0xFA0 32 read-only 0 0xFFFFFFFF TAGSET Hardwired to 0x0000_0000 0 32 read-only TAGCLEAR Claim TAG Clear Register 0xFA4 32 read-only 0 0xFFFFFFFF TAGCLEAR Hardwired to 0x0000_0000 0 32 read-only LOCKACCESS Lock Access Register 0xFB0 32 read-only 0 0xFFFFFFFF LOCKACCESS Hardwired to 0x0000_0000 0 32 read-only LOCKSTAT Lock Status Register 0xFB4 32 read-only 0 0xFFFFFFFF LOCKSTAT Hardwired to 0x0000_0000 0 32 read-only AUTHSTAT Authentication Status Register 0xFB8 32 read-only 0 0xFFFFFFFF BIT0 Connected to DBGEN. 0 1 read-only BIT1 Hardwired to 1. 1 1 read-only BIT2 Connected to NIDEN or DBGEN signal. 2 1 read-only BIT3 Hardwired to 1. 3 1 read-only DEVICEARCH Device Architecture Register 0xFBC 32 read-only 0x47700A31 0xFFFFFFFF DEVICEARCH Hardwired to 0x4770_0A31. 0 32 read-only DEVICECFG Device Configuration Register 0xFC8 32 read-only 0 0xFFFFFFFF DEVICECFG Hardwired to 0x0000_0000. 0 32 read-only DEVICETYPID Device Type Identifier Register 0xFCC 32 read-only 0x31 0xFFFFFFFF DEVICETYPID Hardwired to 0x0000_0031. 0 32 read-only 8 0x4 4,5,6,7,0,1,2,3 PERIPHID%s Peripheral ID Register 0xFD0 32 read-only 0 0 PERIPHID Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000 0 32 read-only 4 0x4 0,1,2,3 COMPID%s Component ID Register 0xFF0 32 read-only 0 0 COMPID Component ID 0 32 read-only MTBDWT MTB data watchpoint and trace MTBDWT_ 0xF0001000 0 0x1000 registers CTRL MTB DWT Control Register 0 32 read-only 0x2F000000 0xFFFFFFFF DWTCFGCTRL DWT configuration controls 0 28 read-only NUMCMP Number of comparators 28 4 read-only 2 0x10 0,1 COMP%s MTB_DWT Comparator Register 0x20 32 read-write 0 0xFFFFFFFF COMP Reference value for comparison 0 32 read-write 2 0x10 0,1 MASK%s MTB_DWT Comparator Mask Register 0x24 32 read-write 0 0xFFFFFFFF MASK MASK 0 5 read-write FCT0 MTB_DWT Comparator Function Register 0 0x28 32 read-write 0 0xFFFFFFFF FUNCTION Function 0 4 read-write 0000 Disabled. #0000 0100 Instruction fetch. #0100 0101 Data operand read. #0101 0110 Data operand write. #0110 0111 Data operand (read + write). #0111 DATAVMATCH Data Value Match 8 1 read-write 0 Perform address comparison. #0 1 Perform data value comparison. #1 DATAVSIZE Data Value Size 10 2 read-write 00 Byte. #00 01 Halfword. #01 10 Word. #10 11 Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. #11 DATAVADDR0 Data Value Address 0 12 4 read-write MATCHED Comparator match 24 1 read-only 0 No match. #0 1 Match occurred. #1 FCT1 MTB_DWT Comparator Function Register 1 0x38 32 read-write 0 0xFFFFFFFF FUNCTION Function 0 4 read-write 0000 Disabled. #0000 0100 Instruction fetch. #0100 0101 Data operand read. #0101 0110 Data operand write. #0110 0111 Data operand (read + write). #0111 MATCHED Comparator match 24 1 read-only 0 No match. #0 1 Match occurred. #1 TBCTRL MTB_DWT Trace Buffer Control Register 0x200 32 read-write 0x20000000 0xFFFFFFFF ACOMP0 Action based on Comparator 0 match 0 1 read-write 0 Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED]. #0 1 Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED]. #1 ACOMP1 Action based on Comparator 1 match 1 1 read-write 0 Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED]. #0 1 Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED]. #1 NUMCOMP Number of Comparators 28 4 read-only DEVICECFG Device Configuration Register 0xFC8 32 read-only 0 0xFFFFFFFF DEVICECFG Hardwired to 0x0000_0000. 0 32 read-only DEVICETYPID Device Type Identifier Register 0xFCC 32 read-only 0x4 0xFFFFFFFF DEVICETYPID Hardwired to 0x0000_0004. 0 32 read-only 8 0x4 4,5,6,7,0,1,2,3 PERIPHID%s Peripheral ID Register 0xFD0 32 read-only 0 0 PERIPHID Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the others to 0x0000_0000. 0 32 read-only 4 0x4 0,1,2,3 COMPID%s Component ID Register 0xFF0 32 read-only 0 0 COMPID Component ID 0 32 read-only ROM System ROM ROM_ 0xF0002000 0 0x1000 registers 3 0x4 0,1,2 ENTRY%s Entry 0 32 read-only 0 0 ENTRY ENTRY 0 32 read-only TABLEMARK End of Table Marker Register 0xC 32 read-only 0 0xFFFFFFFF MARK Hardwired to 0x0000_0000 0 32 read-only SYSACCESS System Access Register 0xFCC 32 read-only 0x1 0xFFFFFFFF SYSACCESS Hardwired to 0x0000_0001 0 32 read-only 8 0x4 4,5,6,7,0,1,2,3 PERIPHID%s Peripheral ID Register 0xFD0 32 read-only 0 0 PERIPHID Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the others to 0x0000_0000. 0 32 read-only 4 0x4 0,1,2,3 COMPID%s Component ID Register 0xFF0 32 read-only 0 0 COMPID Component ID 0 32 read-only MCM Core Platform Miscellaneous Control Module MCM_ 0xF0003000 0x8 0x3C registers PLASC Crossbar Switch (AXBS) Slave Configuration 0x8 16 read-only 0x7 0xFFFF ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 8 read-only 0 A bus slave connection to AXBS input port n is absent #0 1 A bus slave connection to AXBS input port n is present #1 PLAMC Crossbar Switch (AXBS) Master Configuration 0xA 16 read-only 0xD 0xFFFF AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 8 read-only 0 A bus master connection to AXBS input port n is absent #0 1 A bus master connection to AXBS input port n is present #1 PLACR Platform Control Register 0xC 32 read-write 0 0xFFFFFFFF ARB Arbitration select 9 1 read-write 0 Fixed-priority arbitration for the crossbar masters #0 1 Round-robin arbitration for the crossbar masters #1 CFCC Clear Flash Controller Cache 10 1 write-only DFCDA Disable Flash Controller Data Caching 11 1 read-write 0 Enable flash controller data caching #0 1 Disable flash controller data caching. #1 DFCIC Disable Flash Controller Instruction Caching 12 1 read-write 0 Enable flash controller instruction caching. #0 1 Disable flash controller instruction caching. #1 DFCC Disable Flash Controller Cache 13 1 read-write 0 Enable flash controller cache. #0 1 Disable flash controller cache. #1 EFDS Enable Flash Data Speculation 14 1 read-write 0 Disable flash data speculation. #0 1 Enable flash data speculation. #1 DFCS Disable Flash Controller Speculation 15 1 read-write 0 Enable flash controller speculation. #0 1 Disable flash controller speculation. #1 ESFC Enable Stalling Flash Controller 16 1 read-write 0 Disable stalling flash controller when flash is busy. #0 1 Enable stalling flash controller when flash is busy. #1 CPO Compute Operation Control Register 0x40 32 read-write 0 0xFFFFFFFF CPOREQ Compute Operation request 0 1 read-write 0 Request is cleared. #0 1 Request Compute Operation. #1 CPOACK Compute Operation acknowledge 1 1 read-only 0 Compute operation entry has not completed or compute operation exit has completed. #0 1 Compute operation entry has completed or compute operation exit has not completed. #1 CPOWOI Compute Operation wakeup on interrupt 2 1 read-write 0 No effect. #0 1 When set, the CPOREQ is cleared on any interrupt or exception vector fetch. #1 FGPIOA General Purpose Input/Output FGPIO FGPIOA_ 0xF80FF000 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 FGPIOB General Purpose Input/Output FGPIO FGPIOB_ 0xF80FF040 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 FGPIOC General Purpose Input/Output FGPIO FGPIOC_ 0xF80FF080 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 FGPIOD General Purpose Input/Output FGPIO FGPIOD_ 0xF80FF0C0 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 FGPIOE General Purpose Input/Output FGPIO FGPIOE_ 0xF80FF100 0 0x18 registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1