ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32-S2 ESP32 S-Series 18 32-bit MCU & 2.4 GHz Wi-Fi Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. Xtensa LX7 r0p0 little false false 0 false 32 32 0x00000000 0xFFFFFFFF AES AES (Advanced Encryption Standard) Accelerator AES 0x6003A000 0x0 0xBC registers AES 56 8 0x4 KEY_%s AES key register %s 0x0 0x20 KEY Stores AES keys. 0 32 read-write 4 0x4 TEXT_IN_%s Source data register %s 0x20 0x20 TEXT_IN Stores the source data when the AES Accelerator operates in the Typical AES working mode. 0 32 read-write 4 0x4 TEXT_OUT_%s Result data register %s 0x30 0x20 TEXT_OUT Stores the result data when the AES Accelerator operates in the Typical AES working mode. 0 32 read-write MODE AES working mode configuration register 0x40 0x20 MODE Defines the operation type of the AES Accelerator operating under the Typical AES working mode. & 0x0(AES_EN_128): AES-EN-128 # 0x1(AES_EN_192): AES-EN-192 # 0x2(AES_EN_256): AES-EN-256 # 0x4(AES_DE_128): AES-DE-128 # 0x5(AES_DE_192): AES-DE-192 # 0x6(AES_DE_256): AES-DE-256 & 0 3 read-write ENDIAN Endian configuration register 0x44 0x20 ENDIAN Defines the endianness of input and output texts. & [1:0] key endian # [3:2] text_in endian or in_stream endian # [5:4] text_out endian or out_stream endian # & 0 6 read-write TRIGGER Operation start controlling register 0x48 0x20 TRIGGER Set this bit to 1 to start AES operation. 0 1 write-only STATE Operation status register 0x4C 0x20 STATE Stores the working status of the AES Accelerator. For details, see Table 3 for Typical AES working mode and Table 9 for DMA AES working mode. For typical AES; 0 = idle; 1 = busy. For DMA-AES; 0 = idle; 1 = busy; 2 = calculation_done. 0 2 read-only 4 0x4 IV_%s initialization vector 0x50 0x20 IV This register stores the %sth 32-bit piece of 128-bit initialization vector 0 32 read-write 4 0x4 H_%s GCM hash subkey 0x60 0x20 H GCM hash subkey 0 32 read-only 4 0x4 J0_%s J0 0x70 0x20 J0 This register stores the %sth 32-bit piece of 128-bit J0 0 32 read-write 4 0x4 T0_%s T0 0x80 0x20 T0 This register stores the %sth 32-bit piece of 128-bit T0 0 32 read-only DMA_ENABLE DMA enable register 0x90 0x20 DMA_ENABLE Defines the working mode of the AES Accelerator. For details, see Table 1. 1'h0: typical AES operation 1'h1: DMA-AES operation 0 1 read-write BLOCK_MODE Block operation type register 0x94 0x20 BLOCK_MODE Defines the operation type of the AES Accelerator operating under the DMA-AES working mode. For details, see Table 8. & 3'h0(BLOCK_MODE_ECB): ECB # 3'h1(BLOCK_MODE_CBC): CBC # 3'h2(BLOCK_MODE_OFB): OFB # 3'h3(BLOCK_MODE_CTR): CTR # 3'h4(BLOCK_MODE_CFB8): CFB-8 # 3'h5(BLOCK_MODE_CFB128): CFB-128 # 3'h6(BLOCK_MODE_GCM): GCM & 0 3 read-write BLOCK_NUM Block number configuration register 0x98 0x20 BLOCK_NUM Stores the Block Number of plaintext or cipertext when the AES Accelerator operates under the DMA-AES working mode. For details, see Section 1.5.4. 0 32 read-write INC_SEL Standard incrementing function register 0x9C 0x20 INC_SEL Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC 32 or INC 128 . 0 1 read-write AAD_BLOCK_NUM AAD block number configuration register 0xA0 0x20 AAD_BLOCK_NUM Stores the ADD Block Number for the GCM operation. 0 32 read-write REMAINDER_BIT_NUM Remainder bit number of plaintext/ciphertext 0xA4 0x20 REMAINDER_BIT_NUM Stores the Remainder Bit Number for the GCM operation. 0 7 read-write CONTINUE_OP Operation continue controlling register 0xA8 0x20 CONTINUE_OP Set this bit to 1 to continue AES operation. 0 1 write-only INT_CLR DMA-AES interrupt clear register 0xAC 0x20 INT_CLR Set this bit to 1 to clear AES interrupt. 0 1 write-only INT_ENA DMA-AES interrupt enable register 0xB0 0x20 INT_ENA Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. 0 1 read-write DATE Version control register 0xB4 0x20 0x20190514 DATE Version control register 0 30 read-write DMA_EXIT Operation exit controlling register 0xB8 0x20 DMA_EXIT Set this bit to 1 to exit AES operation. This register is only effective for DMA-AES operation. 0 1 write-only APB_SARADC SAR (Successive Approximation Register) Analog-to-Digital Converter APB_SARADC 0x3F440000 0x0 0x68 registers APB_ADC 89 CTRL DIG ADC common configuration 0x0 0x20 0x407F8240 START_FORCE 0: select FSM to start SAR ADC. 1: select software to start SAR ADC. 0 1 read-write START Start SAR ADC by software. 1 1 read-write WORK_MODE 0: single-channel scan mode. 1: double-channel scan mode. 2: alternate-channel scan mode. 3 2 read-write SAR_SEL 0: select SAR ADC1. 1: select SAR ADC2, only work for single-channel scan mode. 5 1 read-write SAR_CLK_GATED SAR clock gate enable bit. 6 1 read-write SAR_CLK_DIV SAR clock divider 7 8 read-write SAR1_PATT_LEN 0 ~ 15 means length 1 ~ 16 15 4 read-write SAR2_PATT_LEN 0 ~ 15 means length 1 ~ 16 19 4 read-write SAR1_PATT_P_CLEAR Clear the pointer of pattern table for DIG ADC1 CTRL. 23 1 read-write SAR2_PATT_P_CLEAR Clear the pointer of pattern table for DIG ADC2 CTRL. 24 1 read-write DATA_SAR_SEL 1: sar_sel will be coded to the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits. 25 1 read-write DATA_TO_I2S 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix 26 1 read-write XPD_SAR_FORCE Force option to xpd sar blocks. 27 2 read-write WAIT_ARB_CYCLE Wait arbit signal stable after sar_done. 30 2 read-write CTRL2 DIG ADC common configuration 0x4 0x20 0x0000A1FE MEAS_NUM_LIMIT Enable limit times of SAR ADC sample. 0 1 read-write MAX_MEAS_NUM Set maximum conversion number. 1 8 read-write SAR1_INV 1: data to DIG ADC1 CTRL is inverted, otherwise not. 9 1 read-write SAR2_INV 1: data to DIG ADC2 CTRL is inverted, otherwise not. 10 1 read-write TIMER_SEL 1: select saradc timer 0: i2s_ws trigger 11 1 read-write TIMER_TARGET Set SAR ADC timer target. 12 12 read-write TIMER_EN Enable SAR ADC timer trigger. 24 1 read-write FSM digital adc control register 0x8 0x20 0x02000000 SAMPLE_NUM sample number 16 8 read-write SAMPLE_CYCLE sample cycles 24 8 read-write FSM_WAIT configure saradc fsm internal parameter base on test 0xC 0x20 0x00FF0808 XPD_WAIT xpd wait 0 8 read-write RSTB_WAIT reset time 8 8 read-write STANDBY_WAIT standby wait 16 8 read-write SAR1_STATUS digital adc1 status 0x10 0x20 SAR1_STATUS digital adc1 status 0 32 read-only SAR2_STATUS digital adc2 status 0x14 0x20 SAR2_STATUS digital adc2 status 0 32 read-only SAR1_PATT_TAB1 item 0 ~ 3 for pattern table 1 (each item one byte) 0x18 0x20 0x0F0F0F0F SAR1_PATT_TAB1 item 0 ~ 3 for pattern table 1 (each item one byte) 0 32 read-write SAR1_PATT_TAB2 Item 4 ~ 7 for pattern table 1 (each item one byte) 0x1C 0x20 0x0F0F0F0F SAR1_PATT_TAB2 Item 4 ~ 7 for pattern table 1 (each item one byte) 0 32 read-write SAR1_PATT_TAB3 Item 8 ~ 11 for pattern table 1 (each item one byte) 0x20 0x20 0x0F0F0F0F SAR1_PATT_TAB3 Item 8 ~ 11 for pattern table 1 (each item one byte) 0 32 read-write SAR1_PATT_TAB4 Item 12 ~ 15 for pattern table 1 (each item one byte) 0x24 0x20 0x0F0F0F0F SAR1_PATT_TAB4 Item 12 ~ 15 for pattern table 1 (each item one byte) 0 32 read-write SAR2_PATT_TAB1 item 0 ~ 3 for pattern table 2 (each item one byte) 0x28 0x20 0x0F0F0F0F SAR2_PATT_TAB1 item 0 ~ 3 for pattern table 2 (each item one byte) 0 32 read-write SAR2_PATT_TAB2 Item 4 ~ 7 for pattern table 2 (each item one byte) 0x2C 0x20 0x0F0F0F0F SAR2_PATT_TAB2 Item 4 ~ 7 for pattern table 2 (each item one byte) 0 32 read-write SAR2_PATT_TAB3 Item 8 ~ 11 for pattern table 2 (each item one byte) 0x30 0x20 0x0F0F0F0F SAR2_PATT_TAB3 Item 8 ~ 11 for pattern table 2 (each item one byte) 0 32 read-write SAR2_PATT_TAB4 Item 12 ~ 15 for pattern table 2 (each item one byte) 0x34 0x20 0x0F0F0F0F SAR2_PATT_TAB4 Item 12 ~ 15 for pattern table 2 (each item one byte) 0 32 read-write ARB_CTRL Configure the settings of DIG ADC2 arbiter 0x38 0x20 0x00000900 ADC_ARB_APB_FORCE ADC2 arbiter forces to enable DIG ADC2 CTRL. 2 1 read-write ADC_ARB_RTC_FORCE ADC2 arbiter forces to enable RTC ADC2 CTRL. 3 1 read-write ADC_ARB_WIFI_FORCE ADC2 arbiter forces to enable PWDET/PKDET CTRL. 4 1 read-write ADC_ARB_GRANT_FORCE ADC2 arbiter force grant. 5 1 read-write ADC_ARB_APB_PRIORITY Set DIG ADC2 CTRL priority. 6 2 read-write ADC_ARB_RTC_PRIORITY Set RTC ADC2 CTRL priority. 8 2 read-write ADC_ARB_WIFI_PRIORITY Set PWDET/PKDET CTRL priority. 10 2 read-write ADC_ARB_FIX_PRIORITY ADC2 arbiter uses fixed priority. 12 1 read-write FILTER_CTRL Configure the settings of DIG ADC2 filter 0x3C 0x20 0x20400000 ADC2_FILTER_RESET Reset ADC2 filter. 0 1 read-write ADC1_FILTER_RESET Reset ADC1 filter. 1 1 read-write ADC2_FILTER_FACTOR Set filter factor for DIG ADC2 CRTL. 16 7 read-write ADC1_FILTER_FACTOR Set filter factor for DIG ADC1 CRTL. 23 7 read-write ADC2_FILTER_EN Enable DIG ADC2 CRTL filter. 30 1 read-write ADC1_FILTER_EN Enable DIG ADC1 CRTL filter. 31 1 read-write FILTER_STATUS Data status of DIG ADC2 filter 0x40 0x20 ADC2_FILTER_DATA ADC2 filter data. 0 16 read-only ADC1_FILTER_DATA ADC1 filter data. 16 16 read-only THRES_CTRL Configure monitor threshold for DIG ADC2 0x44 0x20 CLK_EN Clock gate enable. 0 1 read-write ADC2_THRES_MODE 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA < threshold, generate interrupt. 2 1 read-write ADC1_THRES_MODE 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA < threshold, generate interrupt. 3 1 read-write ADC2_THRES ADC2 threshold. 4 13 read-write ADC1_THRES ADC1 threshold. 17 13 read-write ADC2_THRES_EN Enable ADC2 threshold monitor. 30 1 read-write ADC1_THRES_EN Enable ADC1 threshold monitor. 31 1 read-write INT_ENA Enable DIG ADC interrupts 0x48 0x20 ADC2_THRES_INT_ENA Enable bit of APB_SARADC_ADC2_THRES_INT interrupt. 28 1 read-write ADC1_THRES_INT_ENA Enable bit of APB_SARADC_ADC1_THRES_INT interrupt. 29 1 read-write ADC2_DONE_INT_ENA Enable bit of APB_SARADC_ADC2_DONE_INT interrupt. 30 1 read-write ADC1_DONE_INT_ENA Enable bit of APB_SARADC_ADC1_DONE_INT interrupt. 31 1 read-write INT_RAW DIG ADC interrupt raw bits 0x4C 0x20 ADC2_THRES_INT_RAW Raw bit of APB_SARADC_ADC2_THRES_INT interrupt. 28 1 read-only ADC1_THRES_INT_RAW Raw bit of APB_SARADC_ADC1_THRES_INT interrupt. 29 1 read-only ADC2_DONE_INT_RAW Raw bit of APB_SARADC_ADC2_DONE_INT interrupt. 30 1 read-only ADC1_DONE_INT_RAW Raw bit of APB_SARADC_ADC1_DONE_INT interrupt. 31 1 read-only INT_ST DIG ADC interrupt status 0x50 0x20 ADC2_THRES_INT_ST Status of APB_SARADC_ADC2_THRES_INT interrupt. 28 1 read-only ADC1_THRES_INT_ST Status of APB_SARADC_ADC1_THRES_INT interrupt. 29 1 read-only ADC2_DONE_INT_ST Status of APB_SARADC_ADC2_DONE_INT interrupt. 30 1 read-only ADC1_DONE_INT_ST Status of APB_SARADC_ADC1_DONE_INT interrupt. 31 1 read-only INT_CLR Clear DIG ADC interrupts 0x54 0x20 ADC2_THRES_INT_CLR Clear bit of APB_SARADC_ADC2_THRES_INT interrupt. 28 1 write-only ADC1_THRES_INT_CLR Clear bit of APB_SARADC_ADC1_THRES_INT interrupt. 29 1 write-only ADC2_DONE_INT_CLR Clear bit of APB_SARADC_ADC2_DONE_INT interrupt. 30 1 write-only ADC1_DONE_INT_CLR Clear bit of APB_SARADC_ADC1_DONE_INT interrupt. 31 1 write-only DMA_CONF Configure digital ADC DMA path 0x58 0x20 0x000000FF APB_ADC_EOF_NUM Generate dma_in_suc_eof when sample cnt = spi_eof_num. 0 16 read-write APB_ADC_RESET_FSM Reset DIG ADC CTRL status. 30 1 read-write APB_ADC_TRANS Set this bit, DIG ADC CTRL uses SPI DMA. 31 1 read-write CLKM_CONF Configure DIG ADC clock 0x5C 0x20 0x00000004 CLKM_DIV_NUM Integral DIG_ADC clock divider value 0 8 read-write CLKM_DIV_B Fractional clock divider numerator value 8 6 read-write CLKM_DIV_A Fractional clock divider denominator value 14 6 read-write CLK_SEL 1: select APLL. 2: select APB_CLK. Other values: disable clock. 21 2 read-write APB_DAC_CTRL Configure DAC settings 0x60 0x20 0x00002064 DAC_TIMER_TARGET Set DAC timer target. 0 12 read-write DAC_TIMER_EN Enable read dac data. 12 1 read-write APB_DAC_ALTER_MODE Enable DAC alter mode. 13 1 read-write APB_DAC_TRANS Enable DMA_DAC. 14 1 read-write DAC_RESET_FIFO Reset DIG DAC FIFO. 15 1 read-write APB_DAC_RST Reset DIG DAC by software. 16 1 read-write APB_CTRL_DATE Version control register 0x3FC 0x20 0x01907162 APB_CTRL_DATE Version control register 0 32 read-write BB BB Peripheral BB 0x3F41D000 0x0 0x4 registers BBPD_CTRL Baseband control register 0x54 0x20 DC_EST_FORCE_PD 0 1 read-write DC_EST_FORCE_PU 1 1 read-write FFT_FORCE_PD 2 1 read-write FFT_FORCE_PU 3 1 read-write DEDICATED_GPIO DEDICATED_GPIO Peripheral DEDIC_GPIO 0x3F4CF000 0x0 0x30 registers DEDICATED_GPIO 27 OUT_DRT Dedicated GPIO directive output register 0x0 0x20 VLAUE This register is used to configure directive output value of 8-channel dedicated GPIO. 0 8 write-only OUT_MSK Dedicated GPIO mask output register 0x4 0x20 OUT_VALUE This register is used to configure updated output value of 8-channel dedicated GPIO. 0 8 write-only OUT_MSK This register is used to configure channels which would be updated. 1: corresponding channel's output would be updated. 8 8 write-only OUT_IDV Dedicated GPIO individual output register 0x8 0x20 CH0 Configure channel 0 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value. 0 2 write-only CH1 Configure channel 1 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value. 2 2 write-only CH2 Configure channel 2 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value. 4 2 write-only CH3 Configure channel 3 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value. 6 2 write-only CH4 Configure channel 4 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value. 8 2 write-only CH5 Configure channel 5 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value. 10 2 write-only CH6 Configure channel 6 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value. 12 2 write-only CH7 Configure channel 7 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value. 14 2 write-only OUT_SCAN Dedicated GPIO output status register 0xC 0x20 OUT_STATUS GPIO out value configured by DEDIC_GPIO_OUT_DRT_REG, DEDIC_GPIO_OUT_MSK_REG, DEDIC_GPIO_OUT_IDV_REG. 0 8 read-only OUT_CPU Dedicated GPIO output mode selection register 0x10 0x20 SEL0 Select GPIO out value configured by registers or CPU instructions for channel 0. 0: Configured by registers. 1: configured by CPU instructions. 0 1 read-write SEL1 Select GPIO out value configured by registers or CPU instructions for channel 1. 0: Configured by registers. 1: configured by CPU instructions. 1 1 read-write SEL2 Select GPIO out value configured by registers or CPU instructions for channel 2. 0: Configured by registers. 1: configured by CPU instructions. 2 1 read-write SEL3 Select GPIO out value configured by registers or CPU instructions for channel 3. 0: Configured by registers. 1: configured by CPU instructions. 3 1 read-write SEL4 Select GPIO out value configured by registers or CPU instructions for channel 4. 0: Configured by registers. 1: configured by CPU instructions. 4 1 read-write SEL5 Select GPIO out value configured by registers or CPU instructions for channel 5. 0: Configured by registers. 1: configured by CPU instructions. 5 1 read-write SEL6 Select GPIO out value configured by registers or CPU instructions for channel 6. 0: Configured by registers. 1: configured by CPU instructions. 6 1 read-write SEL7 Select GPIO out value configured by registers or CPU instructions for channel 7. 0: Configured by registers. 1: configured by CPU instructions. 7 1 read-write IN_DLY Dedicated GPIO input delay configuration register 0x14 0x20 CH0 Configure GPIO0 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay. 0 2 read-write CH1 Configure GPIO1 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay. 2 2 read-write CH2 Configure GPIO2 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay. 4 2 read-write CH3 Configure GPIO3 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay. 6 2 read-write CH4 Configure GPIO4 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay. 8 2 read-write CH5 Configure GPIO5 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay. 10 2 read-write CH6 Configure GPIO6 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay. 12 2 read-write CH7 Configure GPIO7 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay. 14 2 read-write IN_SCAN Dedicated GPIO input status register 0x18 0x20 IN_STATUS GPIO input value after configured by DEDIC_GPIO_IN_DLY_REG. 0 8 read-only INTR_RCGN Dedicated GPIO interrupts generation mode register 0x1C 0x20 INTR_MODE_CH0 Configure channel 0 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger. 0 3 read-write INTR_MODE_CH1 Configure channel 1 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger. 3 3 read-write INTR_MODE_CH2 Configure channel 2 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger. 6 3 read-write INTR_MODE_CH3 Configure channel 3 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger. 9 3 read-write INTR_MODE_CH4 Configure channel 4 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger. 12 3 read-write INTR_MODE_CH5 Configure channel 5 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger. 15 3 read-write INTR_MODE_CH6 Configure channel 6 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger. 18 3 read-write INTR_MODE_CH7 Configure channel 7 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger. 21 3 read-write INTR_RAW Raw interrupt status 0x20 0x20 GPIO0 This interrupt raw bit turns to high level when dedicated GPIO0 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. 0 1 read-only GPIO1 This interrupt raw bit turns to high level when dedicated GPIO1 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. 1 1 read-only GPIO2 This interrupt raw bit turns to high level when dedicated GPIO2 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. 2 1 read-only GPIO3 This interrupt raw bit turns to high level when dedicated GPIO3 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. 3 1 read-only GPIO4 This interrupt raw bit turns to high level when dedicated GPIO4 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. 4 1 read-only GPIO5 This interrupt raw bit turns to high level when dedicated GPIO5 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. 5 1 read-only GPIO6 This interrupt raw bit turns to high level when dedicated GPIO6 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. 6 1 read-only GPIO7 This interrupt raw bit turns to high level when dedicated GPIO7 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. 7 1 read-only INTR_RLS Interrupt enable bits 0x24 0x20 GPIO0_INT_ENA The enable bit for DEDIC_GPIO0_INT_ST register. 0 1 read-write GPIO1_INT_ENA The enable bit for DEDIC_GPIO1_INT_ST register. 1 1 read-write GPIO2_INT_ENA The enable bit for DEDIC_GPIO2_INT_ST register. 2 1 read-write GPIO3_INT_ENA The enable bit for DEDIC_GPIO3_INT_ST register. 3 1 read-write GPIO4_INT_ENA The enable bit for DEDIC_GPIO4_INT_ST register. 4 1 read-write GPIO5_INT_ENA The enable bit for DEDIC_GPIO5_INT_ST register. 5 1 read-write GPIO6_INT_ENA The enable bit for DEDIC_GPIO6_INT_ST register. 6 1 read-write GPIO7_INT_ENA The enable bit for DEDIC_GPIO7_INT_ST register. 7 1 read-write INTR_ST Masked interrupt status 0x28 0x20 GPIO0_INT_ST This is the status bit for DEDIC_GPIO0_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. 0 1 read-only GPIO1_INT_ST This is the status bit for DEDIC_GPIO1_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. 1 1 read-only GPIO2_INT_ST This is the status bit for DEDIC_GPIO2_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. 2 1 read-only GPIO3_INT_ST This is the status bit for DEDIC_GPIO3_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. 3 1 read-only GPIO4_INT_ST This is the status bit for DEDIC_GPIO4_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. 4 1 read-only GPIO5_INT_ST This is the status bit for DEDIC_GPIO5_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. 5 1 read-only GPIO6_INT_ST This is the status bit for DEDIC_GPIO6_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. 6 1 read-only GPIO7_INT_ST This is the status bit for DEDIC_GPIO7_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. 7 1 read-only INTR_CLR Interrupt clear bits 0x2C 0x20 GPIO0_INT_CLR Set this bit to clear the DEDIC_GPIO0_INT_RAW interrupt. 0 1 write-only GPIO1_INT_CLR Set this bit to clear the DEDIC_GPIO1_INT_RAW interrupt. 1 1 write-only GPIO2_INT_CLR Set this bit to clear the DEDIC_GPIO2_INT_RAW interrupt. 2 1 write-only GPIO3_INT_CLR Set this bit to clear the DEDIC_GPIO3_INT_RAW interrupt. 3 1 write-only GPIO4_INT_CLR Set this bit to clear the DEDIC_GPIO4_INT_RAW interrupt. 4 1 write-only GPIO5_INT_CLR Set this bit to clear the DEDIC_GPIO5_INT_RAW interrupt. 5 1 write-only GPIO6_INT_CLR Set this bit to clear the DEDIC_GPIO6_INT_RAW interrupt. 6 1 write-only GPIO7_INT_CLR Set this bit to clear the DEDIC_GPIO7_INT_RAW interrupt. 7 1 write-only DS Digital Signature DS 0x6003D000 0x0 0xA5C registers 1584 0x1 C_MEM[%s] memory C 0x0 0x8 4 0x4 IV_%s IV block data. 0x630 0x20 IV IV block data. 0 32 write-only 512 0x1 X_MEM[%s] memory X 0x800 0x8 512 0x1 Z_MEM[%s] memory Z 0xA00 0x8 SET_START Activates the DS peripheral 0xE00 0x20 SET_START Write 1 to this register to activate the DS peripheral. 0 1 write-only SET_ME Starts DS operation 0xE04 0x20 SET_ME Write 1 to this register to start DS operation. 0 1 write-only SET_FINISH Ends DS operation 0xE08 0x20 SET_FINISH Write 1 to this register to end DS operation. 0 1 write-only QUERY_BUSY Status of the DS 0xE0C 0x20 QUERY_BUSY 1: The DS peripheral is busy. 0: The DS peripheral is idle. 0 1 read-only QUERY_KEY_WRONG Checks the reason why DS_KEY is not ready. 0xE10 0x20 QUERY_KEY_WRONG 1-15: HMAC was activated, but the DS peripheral did not successfully receive the DS_KEY value from the HMAC peripheral. The biggest value is 15. 0: HMAC is not activated. 0 4 read-only QUERY_CHECK Queries DS check result 0xE14 0x20 MD_ERROR 1: MD check fails. 0: MD check passes. 0 1 read-only PADDING_BAD 1: The padding check fails. 0: The padding check passes. 1 1 read-only DATE Version control register 0xE20 0x20 0x20190418 DATE Version control register. 0 30 read-write EFUSE eFuse Controller EFUSE 0x3F41A000 0x0 0x1D0 registers EFUSE 46 8 0x4 PGM_DATA%s Register %s that stores data to be programmed. 0x0 0x20 PGM_DATA The content of the %sth 32-bit data to be programmed. 0 32 read-write 3 0x4 PGM_CHECK_VALUE%s Register %s that stores the RS code to be programmed. 0x20 0x20 PGM_RS_DATA The content of the %sth 32-bit RS code to be programmed. 0 32 read-write RD_WR_DIS Register 0 of BLOCK0. 0x2C 0x20 WR_DIS Disables programming of individual eFuses. 0 32 read-only RD_REPEAT_DATA0 Register 1 of BLOCK0. 0x30 0x20 RD_DIS Disables software reading from individual eFuse blocks (BLOCK4-10). 0 7 read-only DIS_RTC_RAM_BOOT Reserved. 7 1 read-only DIS_ICACHE Set this bit to disable Icache. 8 1 read-only DIS_DCACHE Set this bit to disable Dcache. 9 1 read-only DIS_DOWNLOAD_ICACHE Disables Icache when SoC is in Download mode. 10 1 read-only DIS_DOWNLOAD_DCACHE Disables Dcache when SoC is in Download mode. 11 1 read-only DIS_FORCE_DOWNLOAD Set this bit to disable the function that forces chip into download mode. 12 1 read-only DIS_USB Set this bit to disable USB OTG function. 13 1 read-only DIS_CAN Set this bit to disable the TWAI Controller function. 14 1 read-only DIS_BOOT_REMAP Disables capability to Remap RAM to ROM address space. 15 1 read-only RPT4_RESERVED5 Reserved (used for four backups method). 16 1 read-only SOFT_DIS_JTAG Software disables JTAG. When software disabled, JTAG can be activated temporarily by HMAC peripheral. 17 1 read-only HARD_DIS_JTAG Hardware disables JTAG permanently. 18 1 read-only DIS_DOWNLOAD_MANUAL_ENCRYPT Disables flash encryption when in download boot modes. 19 1 read-only USB_DREFH Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse. 20 2 read-only USB_DREFL Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse. 22 2 read-only USB_EXCHG_PINS Set this bit to exchange USB D+ and D- pins. 24 1 read-only EXT_PHY_ENABLE Set this bit to enable external USB PHY. 25 1 read-only USB_FORCE_NOPERSIST If set, forces USB BVALID to 1. 26 1 read-only RPT4_RESERVED0 Reserved (used for four backups method). 27 2 read-only VDD_SPI_MODECURLIM SPI regulator switches current limit mode. 29 1 read-only VDD_SPI_DREFH SPI regulator high voltage reference. 30 2 read-only RD_REPEAT_DATA1 Register 2 of BLOCK0. 0x34 0x20 VDD_SPI_DREFM SPI regulator medium voltage reference. 0 2 read-only VDD_SPI_DREFL SPI regulator low voltage reference. 2 2 read-only VDD_SPI_XPD If VDD_SPI_FORCE is 1, this value determines if the VDD_SPI regulator is powered on. 4 1 read-only VDD_SPI_TIEH If VDD_SPI_FORCE is 1, determines VDD_SPI voltage. 0: VDD_SPI connects to 1.8 V LDO. 1: VDD_SPI connects to VDD_RTC_IO. 5 1 read-only VDD_SPI_FORCE Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO. 6 1 read-only VDD_SPI_EN_INIT Set SPI regulator to 0 to configure init[1:0]=0. 7 1 read-only VDD_SPI_ENCURLIM Set SPI regulator to 1 to enable output current limit. 8 1 read-only VDD_SPI_DCURLIM Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d). 9 3 read-only VDD_SPI_INIT Adds resistor from LDO output to ground. 0: no resistance. 1: 6 K. 2: 4 K. 3: 2 K. 12 2 read-only VDD_SPI_DCAP Prevents SPI regulator from overshoot. 14 2 read-only WDT_DELAY_SEL Selects RTC watchdog timeout threshold at startup. 0: 40,000 slow clock cycles. 1: 80,000 slow clock cycles. 2: 160,000 slow clock cycles. 3: 320,000 slow clock cycles. 16 2 read-only SPI_BOOT_CRYPT_CNT Enables encryption and decryption, when an SPI boot mode is set. Feature is enabled 1 or 3 bits are set in the eFuse, disabled otherwise. 18 3 read-only SECURE_BOOT_KEY_REVOKE0 If set, revokes use of secure boot key digest 0. 21 1 read-only SECURE_BOOT_KEY_REVOKE1 If set, revokes use of secure boot key digest 1. 22 1 read-only SECURE_BOOT_KEY_REVOKE2 If set, revokes use of secure boot key digest 2. 23 1 read-only KEY_PURPOSE_0 Purpose of KEY0. Refer to Table Key Purpose Values. 24 4 read-only KEY_PURPOSE_1 Purpose of KEY1. Refer to Table Key Purpose Values. 28 4 read-only RD_REPEAT_DATA2 Register 3 of BLOCK0. 0x38 0x20 KEY_PURPOSE_2 Purpose of KEY2. Refer to Table Key Purpose Values. 0 4 read-only KEY_PURPOSE_3 Purpose of KEY3. Refer to Table Key Purpose Values. 4 4 read-only KEY_PURPOSE_4 Purpose of KEY4. Refer to Table Key Purpose Values. 8 4 read-only KEY_PURPOSE_5 Purpose of KEY5. Refer to Table Key Purpose Values. 12 4 read-only KEY_PURPOSE_6 Purpose of KEY6. Refer to Table Key Purpose Values. 16 4 read-only SECURE_BOOT_EN Set this bit to enable secure boot. 20 1 read-only SECURE_BOOT_AGGRESSIVE_REVOKE Set this bit to enable aggressive secure boot key revocation mode. 21 1 read-only RPT4_RESERVED1 Reserved (used for four backups method). 22 6 read-only FLASH_TPUW Configures flash startup delay after SoC power-up, in unit of (ms/2). When the value is 15, delay is 7.5 ms. 28 4 read-only RD_REPEAT_DATA3 Register 4 of BLOCK0. 0x3C 0x20 DIS_DOWNLOAD_MODE Set this bit to disable all download boot modes. 0 1 read-only DIS_LEGACY_SPI_BOOT Set this bit to disable Legacy SPI boot mode. 1 1 read-only UART_PRINT_CHANNEL Selects the default UART for printing boot messages. 0: UART0. 1: UART1. 2 1 read-only RPT4_RESERVED3 Reserved (used for four backups method). 3 1 read-only DIS_USB_DOWNLOAD_MODE Set this bit to disable use of USB OTG in UART download boot mode. 4 1 read-only ENABLE_SECURITY_DOWNLOAD Set this bit to enable secure UART download mode (read/write flash only). 5 1 read-only UART_PRINT_CONTROL Set the default UART boot message output mode. 00: Enabled. 01: Enable when GPIO46 is low at reset. 10: Enable when GPIO46 is high at reset. 11: Disabled. 6 2 read-only PIN_POWER_SELECTION Set default power supply for GPIO33-GPIO37, set when SPI flash is initialized. 0: VDD3P3_CPU. 1: VDD_SPI. 8 1 read-only FLASH_TYPE SPI flash type. 0: maximum four data lines, 1: eight data lines. 9 1 read-only FORCE_SEND_RESUME If set, forces ROM code to send an SPI flash resume command during SPI boot. 10 1 read-only SECURE_VERSION Secure version (used by ESP-IDF anti-rollback feature). 11 16 read-only RPT4_RESERVED2 Reserved (used for four backups method). 27 5 read-only RD_REPEAT_DATA4 Register 5 of BLOCK0. 0x40 0x20 RPT4_RESERVED4 Reserved (used for four backups method). 0 24 read-only RD_MAC_SPI_SYS_0 Register 0 of BLOCK1. 0x44 0x20 MAC_0 Stores the low 32 bits of MAC address. 0 32 read-only RD_MAC_SPI_SYS_1 Register 1 of BLOCK1. 0x48 0x20 MAC_1 Stores the high 16 bits of MAC address. 0 16 read-only SPI_PAD_CONF_0 Stores the zeroth part of SPI_PAD_CONF. 16 16 read-only RD_MAC_SPI_SYS_2 Register 2 of BLOCK1. 0x4C 0x20 SPI_PAD_CONF_1 Stores the first part of SPI_PAD_CONF. 0 32 read-only RD_MAC_SPI_SYS_3 Register 3 of BLOCK1. 0x50 0x20 SPI_PAD_CONF_2 Stores the second part of SPI_PAD_CONF. 0 18 read-only SYS_DATA_PART0_0 Stores the zeroth part of the zeroth part of system data. 18 14 read-only RD_MAC_SPI_SYS_4 Register 4 of BLOCK1. 0x54 0x20 SYS_DATA_PART0_1 Stores the fist part of the zeroth part of system data. 0 32 read-only RD_MAC_SPI_SYS_5 Register 5 of BLOCK1. 0x58 0x20 SYS_DATA_PART0_2 Stores the second part of the zeroth part of system data. 0 32 read-only 8 0x4 RD_SYS_DATA_PART1_%s Register %s of BLOCK2 (system). 0x5C 0x20 SYS_DATA_PART1 Stores the %sth 32 bits of the first part of system data. 0 32 read-only 8 0x4 RD_USR_DATA%s Register %s of BLOCK3 (user). 0x7C 0x20 USR_DATA Stores the %sth 32 bits of BLOCK3 (user). 0 32 read-only 8 0x4 RD_KEY0_DATA%s Register %s of BLOCK4 (KEY0). 0x9C 0x20 KEY0_DATA Stores the %sth 32 bits of KEY0. 0 32 read-only 8 0x4 RD_KEY1_DATA%s Register %s of BLOCK5 (KEY1). 0xBC 0x20 KEY1_DATA Stores the %sth 32 bits of KEY1. 0 32 read-only 8 0x4 RD_KEY2_DATA%s Register %s of BLOCK6 (KEY2). 0xDC 0x20 KEY2_DATA Stores the %sth 32 bits of KEY2. 0 32 read-only 8 0x4 RD_KEY3_DATA%s Register %s of BLOCK7 (KEY3). 0xFC 0x20 KEY3_DATA Stores the %sth 32 bits of KEY3. 0 32 read-only 8 0x4 RD_KEY4_DATA%s Register %s of BLOCK8 (KEY4). 0x11C 0x20 KEY4_DATA Stores the %sth 32 bits of KEY4. 0 32 read-only 8 0x4 RD_KEY5_DATA%s Register %s of BLOCK9 (KEY5). 0x13C 0x20 KEY5_DATA Stores the %sth 32 bits of KEY5. 0 32 read-only 8 0x4 RD_SYS_DATA_PART2_%s Register %s of BLOCK10 (system). 0x15C 0x20 SYS_DATA_PART2 Stores the %sth 32 bits of the 2nd part of system data. 0 32 read-only RD_REPEAT_ERR0 Programming error record register 0 of BLOCK0. 0x17C 0x20 RD_DIS_ERR Any bit equal to 1 denotes a programming error in EFUSE_RD_DIS. 0 7 read-only DIS_RTC_RAM_BOOT_ERR Any bit equal to 1 denotes a programming error in EFUSE_DIS_RTC_RAM_BOOT. 7 1 read-only DIS_ICACHE_ERR Any bit equal to 1 denotes a programming error in EFUSE_DIS_ICACHE. 8 1 read-only DIS_DCACHE_ERR Any bit equal to 1 denotes a programming error in EFUSE_DIS_DCACHE. 9 1 read-only DIS_DOWNLOAD_ICACHE_ERR Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_ICACHE. 10 1 read-only DIS_DOWNLOAD_DCACHE_ERR Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_DCACHE. 11 1 read-only DIS_FORCE_DOWNLOAD_ERR Any bit equal to 1 denotes a programming error in EFUSE_DIS_FORCE_DOWNLOAD. 12 1 read-only DIS_USB_ERR Any bit equal to 1 denotes a programming error in EFUSE_DIS_USB. 13 1 read-only DIS_CAN_ERR Any bit equal to 1 denotes a programming error in EFUSE_DIS_CAN. 14 1 read-only DIS_BOOT_REMAP_ERR Any bit equal to 1 denotes a programming error in EFUSE_DIS_BOOT_REMAP. 15 1 read-only RPT4_RESERVED5_ERR Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED5. 16 1 read-only SOFT_DIS_JTAG_ERR Any bit equal to 1 denotes a programming error in EFUSE_SOFT_DIS_JTAG. 17 1 read-only HARD_DIS_JTAG_ERR Any bit equal to 1 denotes a programming error in EFUSE_HARD_DIS_JTAG. 18 1 read-only DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT. 19 1 read-only USB_DREFH_ERR Any bit equal to 1 denotes a programming error in EFUSE_USB_DREFH. 20 2 read-only USB_DREFL_ERR Any bit equal to 1 denotes a programming error in EFUSE_USB_DREFL. 22 2 read-only USB_EXCHG_PINS_ERR Any bit equal to 1 denotes a programming error in EFUSE_USB_EXCHG_PINS. 24 1 read-only EXT_PHY_ENABLE_ERR Any bit equal to 1 denotes a programming error in EFUSE_EXT_PHY_ENABLE. 25 1 read-only USB_FORCE_NOPERSIST_ERR Any bit equal to 1 denotes a programming error in EFUSE_USB_FORCE_NOPERSIST. 26 1 read-only RPT4_RESERVED0_ERR Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED0. 27 2 read-only VDD_SPI_MODECURLIM_ERR Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_MODECURLIM. 29 1 read-only VDD_SPI_DREFH_ERR Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFH. 30 2 read-only RD_REPEAT_ERR1 Programming error record register 1 of BLOCK0. 0x180 0x20 VDD_SPI_DREFM_ERR Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFM. 0 2 read-only VDD_SPI_DREFL_ERR Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFL. 2 2 read-only VDD_SPI_XPD_ERR Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_XPD. 4 1 read-only VDD_SPI_TIEH_ERR Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_TIEH. 5 1 read-only VDD_SPI_FORCE_ERR Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_FORCE. 6 1 read-only VDD_SPI_EN_INIT_ERR Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_EN_INIT. 7 1 read-only VDD_SPI_ENCURLIM_ERR Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_ENCURLIM. 8 1 read-only VDD_SPI_DCURLIM_ERR Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DCURLIM. 9 3 read-only VDD_SPI_INIT_ERR Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_INIT. 12 2 read-only VDD_SPI_DCAP_ERR Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DCAP. 14 2 read-only WDT_DELAY_SEL_ERR Any bit equal to 1 denotes a programming error in EFUSE_WDT_DELAY_SEL. 16 2 read-only SPI_BOOT_CRYPT_CNT_ERR Any bit equal to 1 denotes a programming error in EFUSE_SPI_BOOT_CRYPT_CNT. 18 3 read-only SECURE_BOOT_KEY_REVOKE0_ERR Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE0. 21 1 read-only SECURE_BOOT_KEY_REVOKE1_ERR Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE1. 22 1 read-only SECURE_BOOT_KEY_REVOKE2_ERR Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE2. 23 1 read-only KEY_PURPOSE_0_ERR Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_0. 24 4 read-only KEY_PURPOSE_1_ERR Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_1. 28 4 read-only RD_REPEAT_ERR2 Programming error record register 2 of BLOCK0. 0x184 0x20 KEY_PURPOSE_2_ERR Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_2. 0 4 read-only KEY_PURPOSE_3_ERR Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_3. 4 4 read-only KEY_PURPOSE_4_ERR Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_4. 8 4 read-only KEY_PURPOSE_5_ERR Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_5. 12 4 read-only KEY_PURPOSE_6_ERR Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_6. 16 4 read-only SECURE_BOOT_EN_ERR Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_EN. 20 1 read-only SECURE_BOOT_AGGRESSIVE_REVOKE_ERR Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE. 21 1 read-only RPT4_RESERVED1_ERR Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED1. 22 6 read-only FLASH_TPUW_ERR Any bit equal to 1 denotes a programming error in EFUSE_FLASH_TPUW. 28 4 read-only RD_REPEAT_ERR3 Programming error record register 3 of BLOCK0. 0x188 0x20 DIS_DOWNLOAD_MODE_ERR Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_MODE. 0 1 read-only DIS_LEGACY_SPI_BOOT_ERR Any bit equal to 1 denotes a programming error in EFUSE_DIS_LEGACY_SPI_BOOT. 1 1 read-only UART_PRINT_CHANNEL_ERR Any bit equal to 1 denotes a programming error in EFUSE_UART_PRINT_CHANNEL. 2 1 read-only RPT4_RESERVED3_ERR Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED3. 3 1 read-only DIS_USB_DOWNLOAD_MODE_ERR Any bit equal to 1 denotes a programming error in EFUSE_DIS_USB_DOWNLOAD_MODE. 4 1 read-only ENABLE_SECURITY_DOWNLOAD_ERR Any bit equal to 1 denotes a programming error in EFUSE_ENABLE_SECURITY_DOWNLOAD. 5 1 read-only UART_PRINT_CONTROL_ERR Any bit equal to 1 denotes a programming error in EFUSE_UART_PRINT_CONTROL. 6 2 read-only PIN_POWER_SELECTION_ERR Any bit equal to 1 denotes a programming error in EFUSE_PIN_POWER_SELECTION. 8 1 read-only FLASH_TYPE_ERR Any bit equal to 1 denotes a programming error in EFUSE_FLASH_TYPE. 9 1 read-only FORCE_SEND_RESUME_ERR Any bit equal to 1 denotes a programming error in EFUSE_FORCE_SEND_RESUME. 10 1 read-only SECURE_VERSION_ERR Any bit equal to 1 denotes a programming error in EFUSE_SECURE_VERSION. 11 16 read-only RPT4_RESERVED2_ERR Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED2. 27 5 read-only RD_REPEAT_ERR4 Programming error record register 4 of BLOCK0. 0x190 0x20 RPT4_RESERVED4_ERR If any bit in RPT4_RESERVED4 is 1, there is a programming error in EFUSE_RPT4_RESERVED4. 0 24 read-only RD_RS_ERR0 Programming error record register 0 of BLOCK1-10. 0x1C0 0x20 MAC_SPI_8M_ERR_NUM The value of this signal means the number of error bytes in BLOCK1. 0 3 read-only MAC_SPI_8M_FAIL 0: Means no failure and that the data of BLOCK1 is reliable. 1: Means that programming BLOCK1 data failed and the number of error bytes is over 5. 3 1 read-only SYS_PART1_NUM The value of this signal means the number of error bytes in BLOCK2. 4 3 read-only SYS_PART1_FAIL 0: Means no failure and that the data of BLOCK2 is reliable. 1: Means that programming BLOCK2 data failed and the number of error bytes is over 5. 7 1 read-only USR_DATA_ERR_NUM The value of this signal means the number of error bytes in BLOCK3. 8 3 read-only USR_DATA_FAIL 0: Means no failure and that the data of BLOCK3 is reliable. 1: Means that programming BLOCK3 data failed and the number of error bytes is over 5. 11 1 read-only KEY0_ERR_NUM The value of this signal means the number of error bytes in KEY0. 12 3 read-only KEY0_FAIL 0: Means no failure and that the data of KEY0 is reliable. 1: Means that programming KEY0 failed and the number of error bytes is over 5. 15 1 read-only KEY1_ERR_NUM The value of this signal means the number of error bytes in KEY1. 16 3 read-only KEY1_FAIL 0: Means no failure and that the data of KEY1 is reliable. 1: Means that programming KEY1 failed and the number of error bytes is over 5. 19 1 read-only KEY2_ERR_NUM The value of this signal means the number of error bytes in KEY2. 20 3 read-only KEY2_FAIL 0: Means no failure and that the data of KEY2 is reliable. 1: Means that programming KEY2 failed and the number of error bytes is over 5. 23 1 read-only KEY3_ERR_NUM The value of this signal means the number of error bytes in KEY3. 24 3 read-only KEY3_FAIL 0: Means no failure and that the data of KEY3 is reliable. 1: Means that programming KEY3 failed and the number of error bytes is over 5. 27 1 read-only KEY4_ERR_NUM The value of this signal means the number of error bytes in KEY4. 28 3 read-only KEY4_FAIL 0: Means no failure and that the data of KEY4 is reliable. 1: Means that programming KEY4 failed and the number of error bytes is over 5. 31 1 read-only RD_RS_ERR1 Programming error record register 1 of BLOCK1-10. 0x1C4 0x20 KEY5_ERR_NUM The value of this signal means the number of error bytes in KEY5. 0 3 read-only KEY5_FAIL 0: Means no failure and that the data of KEY5 is reliable. 1: Means that programming user data failed and the number of error bytes is over 5. 3 1 read-only SYS_PART2_ERR_NUM The value of this signal means the number of error bytes in BLOCK10. 4 3 read-only SYS_PART2_FAIL 0: Means no failure and that the data of BLOCK10 is reliable. 1: Means that programming BLOCK10 data failed and the number of error bytes is over 5. 7 1 read-only CLK eFuse clock configuration register. 0x1C8 0x20 0x00000002 EFUSE_MEM_FORCE_PD If set, forces eFuse SRAM into power-saving mode. 0 1 read-write MEM_CLK_FORCE_ON If set, forces to activate clock signal of eFuse SRAM. 1 1 read-write EFUSE_MEM_FORCE_PU If set, forces eFuse SRAM into working mode. 2 1 read-write EN If set, forces to enable clock signal of eFuse memory. 16 1 read-write CONF eFuse operation mode configuration register. 0x1CC 0x20 OP_CODE 0x5A5A: Operate programming command. 0x5AA5: Operate read command. 0 16 read-write STATUS eFuse status register. 0x1D0 0x20 STATE Indicates the state of the eFuse state machine. 0 4 read-only OTP_LOAD_SW The value of OTP_LOAD_SW. 4 1 read-only OTP_VDDQ_C_SYNC2 The value of OTP_VDDQ_C_SYNC2. 5 1 read-only OTP_STROBE_SW The value of OTP_STROBE_SW. 6 1 read-only OTP_CSB_SW The value of OTP_CSB_SW. 7 1 read-only OTP_PGENB_SW The value of OTP_PGENB_SW. 8 1 read-only OTP_VDDQ_IS_SW The value of OTP_VDDQ_IS_SW. 9 1 read-only REPEAT_ERR_CNT Indicates the number of error bits during programming BLOCK0. 10 8 read-only CMD eFuse command register. 0x1D4 0x20 READ_CMD Set this bit to send read command. 0 1 read-write PGM_CMD Set this bit to send programming command. 1 1 read-write BLK_NUM The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively. 2 4 read-write INT_RAW eFuse raw interrupt register. 0x1D8 0x20 READ_DONE_INT_RAW The raw bit signal for read_done interrupt. 0 1 read-only PGM_DONE_INT_RAW The raw bit signal for pgm_done interrupt. 1 1 read-only INT_ST eFuse interrupt status register. 0x1DC 0x20 READ_DONE_INT_ST The status signal for read_done interrupt. 0 1 read-only PGM_DONE_INT_ST The status signal for pgm_done interrupt. 1 1 read-only INT_ENA eFuse interrupt enable register. 0x1E0 0x20 READ_DONE_INT_ENA The enable signal for read_done interrupt. 0 1 read-write PGM_DONE_INT_ENA The enable signal for pgm_done interrupt. 1 1 read-write INT_CLR eFuse interrupt clear register. 0x1E4 0x20 READ_DONE_INT_CLR The clear signal for read_done interrupt. 0 1 write-only PGM_DONE_INT_CLR The clear signal for pgm_done interrupt. 1 1 write-only DAC_CONF Controls the eFuse programming voltage. 0x1E8 0x20 0x0001FE1C DAC_CLK_DIV Controls the division factor of the rising clock of the programming voltage. 0 8 read-write DAC_CLK_PAD_SEL Don't care. 8 1 read-write DAC_NUM Controls the rising period of the programming voltage. 9 8 read-write OE_CLR Reduces the power supply of the programming voltage. 17 1 read-write RD_TIM_CONF Configures read timing parameters. 0x1EC 0x20 0x12010101 THR_A Configures the hold time of read operation. 0 8 read-write TRD Configures the length of pulse of read operation. 8 8 read-write TSUR_A Configures the setup time of read operation. 16 8 read-write READ_INIT_NUM Configures the initial read time of eFuse. 24 8 read-write WR_TIM_CONF0 Configuration register 0 of eFuse programming timing parameters. 0x1F0 0x20 0x00C80101 THP_A Configures the hold time of programming operation. 0 8 read-write TPGM_INACTIVE Configures the length of pulse during programming 0 to eFuse. 8 8 read-write TPGM Configures the length of pulse during programming 1 to eFuse. 16 16 read-write WR_TIM_CONF1 Configuration register 1 of eFuse programming timing parameters. 0x1F4 0x20 0x00288001 TSUP_A Configures the setup time of programming operation. 0 8 read-write PWR_ON_NUM Configures the power up time for VDDQ. 8 16 read-write WR_TIM_CONF2 Configuration register 2 of eFuse programming timing parameters. 0x1F8 0x20 0x00000190 PWR_OFF_NUM Configures the power outage time for VDDQ. 0 16 read-write DATE Version control register. 0x1FC 0x20 0x19081100 DATE Version control register. 0 32 read-write EXTMEM External Memory EXTMEM 0x61800000 0x0 0x140 registers PRO_DCACHE_CTRL register description 0x0 0x20 0x00000100 PRO_DCACHE_ENABLE The bit is used to activate the data cache. 0: disable, 1: enable 0 1 read-write PRO_DCACHE_SETSIZE_MODE The bit is used to configure cache memory size.0: 8KB, 1: 16KB 2 1 read-write PRO_DCACHE_BLOCKSIZE_MODE The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes 3 1 read-write PRO_DCACHE_INVALIDATE_ENA The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. 8 1 read-write PRO_DCACHE_INVALIDATE_DONE The bit is used to indicate invalidate operation is finished. 9 1 read-only PRO_DCACHE_FLUSH_ENA The bit is used to enable flush operation. It will be cleared by hardware after flush operation done. 10 1 read-write PRO_DCACHE_FLUSH_DONE The bit is used to indicate flush operation is finished. 11 1 read-only PRO_DCACHE_CLEAN_ENA The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. 12 1 read-write PRO_DCACHE_CLEAN_DONE The bit is used to indicate clean operation is finished. 13 1 read-only PRO_DCACHE_LOCK0_EN The bit is used to enable pre-lock operation which is combined with PRO_DCACHE_LOCK0_ADDR_REG and PRO_DCACHE_LOCK0_SIZE_REG. 14 1 read-write PRO_DCACHE_LOCK1_EN The bit is used to enable pre-lock operation which is combined with PRO_DCACHE_LOCK1_ADDR_REG and PRO_DCACHE_LOCK1_SIZE_REG. 15 1 read-write PRO_DCACHE_AUTOLOAD_ENA The bit is used to enable and disable conditional-preload operation. It is combined with pre_dcache_autoload_done. 1: enable, 0: disable. 18 1 read-write PRO_DCACHE_AUTOLOAD_DONE The bit is used to indicate conditional-preload operation is finished. 19 1 read-only PRO_DCACHE_PRELOAD_ENA The bit is used to enable preload operation. It will be cleared by hardware after preload operation done. 20 1 read-write PRO_DCACHE_PRELOAD_DONE The bit is used to indicate preload operation is finished. 21 1 read-only PRO_DCACHE_UNLOCK_ENA The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. 22 1 read-write PRO_DCACHE_UNLOCK_DONE The bit is used to indicate unlock operation is finished. 23 1 read-only PRO_DCACHE_LOCK_ENA The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. 24 1 read-write PRO_DCACHE_LOCK_DONE The bit is used to indicate lock operation is finished. 25 1 read-only PRO_DCACHE_CTRL1 register description 0x4 0x20 0x00000007 PRO_DCACHE_MASK_BUS0 The bit is used to disable dbus0, 0: enable, 1: disable 0 1 read-write PRO_DCACHE_MASK_BUS1 The bit is used to disable dbus1, 0: enable, 1: disable 1 1 read-write PRO_DCACHE_MASK_BUS2 The bit is used to disable dbus2, 0: enable, 1: disable 2 1 read-write PRO_DCACHE_TAG_POWER_CTRL register description 0x8 0x20 0x00000005 PRO_DCACHE_TAG_MEM_FORCE_ON The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating. 0 1 read-write PRO_DCACHE_TAG_MEM_FORCE_PD The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down 1 1 read-write PRO_DCACHE_TAG_MEM_FORCE_PU The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power up 2 1 read-write PRO_DCACHE_LOCK0_ADDR register description 0xC 0x20 PRO_DCACHE_LOCK0_ADDR The bits are used to configure the first start virtual address of data locking, which is combined with PRO_DCACHE_LOCK0_SIZE_REG 0 32 read-write PRO_DCACHE_LOCK0_SIZE register description 0x10 0x20 PRO_DCACHE_LOCK0_SIZE The bits are used to configure the first length of data locking, which is combined with PRO_DCACHE_LOCK0_ADDR_REG 0 16 read-write PRO_DCACHE_LOCK1_ADDR register description 0x14 0x20 PRO_DCACHE_LOCK1_ADDR The bits are used to configure the second start virtual address of data locking, which is combined with PRO_DCACHE_LOCK1_SIZE_REG 0 32 read-write PRO_DCACHE_LOCK1_SIZE register description 0x18 0x20 PRO_DCACHE_LOCK1_SIZE The bits are used to configure the second length of data locking, which is combined with PRO_DCACHE_LOCK1_ADDR_REG 0 16 read-write PRO_DCACHE_MEM_SYNC0 register description 0x1C 0x20 PRO_DCACHE_MEMSYNC_ADDR The bits are used to configure the start virtual address for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if the address is validate. The auto operations will be issued if the address is invalidate. It should be combined with PRO_DCACHE_MEM_SYNC1. 0 32 read-write PRO_DCACHE_MEM_SYNC1 register description 0x20 0x20 PRO_DCACHE_MEMSYNC_SIZE The bits are used to configure the length for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if it is validate. The auto operations will be issued if it is invalidate. It should be combined with PRO_DCACHE_MEM_SYNC0. 0 19 read-write PRO_DCACHE_PRELOAD_ADDR register description 0x24 0x20 PRO_DCACHE_PRELOAD_ADDR The bits are used to configure the start virtual address for manual pre-load operation. It should be combined with PRO_DCACHE_PRELOAD_SIZE_REG. 0 32 read-write PRO_DCACHE_PRELOAD_SIZE register description 0x28 0x20 0x00000200 PRO_DCACHE_PRELOAD_SIZE The bits are used to configure the length for manual pre-load operation. It should be combined with PRO_DCACHE_PRELOAD_ADDR_REG.. 0 10 read-write PRO_DCACHE_PRELOAD_ORDER The bits are used to configure the direction of manual pre-load operation. 1: descending, 0: ascending. 10 1 read-write PRO_DCACHE_AUTOLOAD_CFG register description 0x2C 0x20 PRO_DCACHE_AUTOLOAD_MODE Reserved. 0 1 read-write PRO_DCACHE_AUTOLOAD_STEP Reserved. 1 2 read-write PRO_DCACHE_AUTOLOAD_ORDER The bits are used to configure the direction of conditional pre-load operation. 1: descending, 0: ascending. 3 1 read-write PRO_DCACHE_AUTOLOAD_RQST The bits are used to configure trigger conditions for conditional pre-load. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit. 4 2 read-write PRO_DCACHE_AUTOLOAD_SIZE The bits are used to configure the numbers of the cache block for the issuing conditional pre-load operation. 6 2 read-write PRO_DCACHE_AUTOLOAD_SCT0_ENA The bits are used to enable the second section for conditional pre-load operation. 8 1 read-write PRO_DCACHE_AUTOLOAD_SCT1_ENA The bits are used to enable the first section for conditional pre-load operation. 9 1 read-write PRO_DCACHE_AUTOLOAD_SECTION0_ADDR register description 0x30 0x20 PRO_DCACHE_AUTOLOAD_SCT0_ADDR The bits are used to configure the start virtual address of the first section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct0_ena. 0 32 read-write PRO_DCACHE_AUTOLOAD_SECTION0_SIZE register description 0x34 0x20 0x00008000 PRO_DCACHE_AUTOLOAD_SCT0_SIZE The bits are used to configure the length of the first section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct0_ena. 0 24 read-write PRO_DCACHE_AUTOLOAD_SECTION1_ADDR register description 0x38 0x20 PRO_DCACHE_AUTOLOAD_SCT1_ADDR The bits are used to configure the start virtual address of the second section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct1_ena. 0 32 read-write PRO_DCACHE_AUTOLOAD_SECTION1_SIZE register description 0x3C 0x20 0x00008000 PRO_DCACHE_AUTOLOAD_SCT1_SIZE The bits are used to configure the length of the second section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct1_ena. 0 24 read-write PRO_ICACHE_CTRL register description 0x40 0x20 0x00000100 PRO_ICACHE_ENABLE The bit is used to activate the data cache. 0: disable, 1: enable 0 1 read-write PRO_ICACHE_SETSIZE_MODE The bit is used to configure cache memory size.0: 8KB, 1: 16KB 2 1 read-write PRO_ICACHE_BLOCKSIZE_MODE The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes 3 1 read-write PRO_ICACHE_INVALIDATE_ENA The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. 8 1 read-write PRO_ICACHE_INVALIDATE_DONE The bit is used to indicate invalidate operation is finished. 9 1 read-only PRO_ICACHE_LOCK0_EN The bit is used to enable pre-lock operation which is combined with PRO_ICACHE_LOCK0_ADDR_REG and PRO_ICACHE_LOCK0_SIZE_REG. 14 1 read-write PRO_ICACHE_LOCK1_EN The bit is used to enable pre-lock operation which is combined with PRO_ICACHE_LOCK1_ADDR_REG and PRO_ICACHE_LOCK1_SIZE_REG. 15 1 read-write PRO_ICACHE_AUTOLOAD_ENA The bit is used to enable and disable conditional-preload operation. It is combined with pre_dcache_autoload_done. 1: enable, 0: disable. 18 1 read-write PRO_ICACHE_AUTOLOAD_DONE The bit is used to indicate conditional-preload operation is finished. 19 1 read-only PRO_ICACHE_PRELOAD_ENA The bit is used to enable preload operation. It will be cleared by hardware after preload operation done. 20 1 read-write PRO_ICACHE_PRELOAD_DONE The bit is used to indicate preload operation is finished. 21 1 read-only PRO_ICACHE_UNLOCK_ENA The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. 22 1 read-write PRO_ICACHE_UNLOCK_DONE The bit is used to indicate unlock operation is finished. 23 1 read-only PRO_ICACHE_LOCK_ENA The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. 24 1 read-write PRO_ICACHE_LOCK_DONE The bit is used to indicate lock operation is finished. 25 1 read-only PRO_ICACHE_CTRL1 register description 0x44 0x20 0x00000007 PRO_ICACHE_MASK_BUS0 The bit is used to disable ibus0, 0: enable, 1: disable 0 1 read-write PRO_ICACHE_MASK_BUS1 The bit is used to disable ibus1, 0: enable, 1: disable 1 1 read-write PRO_ICACHE_MASK_BUS2 The bit is used to disable ibus2, 0: enable, 1: disable 2 1 read-write PRO_ICACHE_TAG_POWER_CTRL register description 0x48 0x20 0x00000005 PRO_ICACHE_TAG_MEM_FORCE_ON The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating. 0 1 read-write PRO_ICACHE_TAG_MEM_FORCE_PD The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down 1 1 read-write PRO_ICACHE_TAG_MEM_FORCE_PU The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power up 2 1 read-write PRO_ICACHE_LOCK0_ADDR register description 0x4C 0x20 PRO_ICACHE_LOCK0_ADDR The bits are used to configure the first start virtual address of data locking, which is combined with PRO_ICACHE_LOCK0_SIZE_REG 0 32 read-write PRO_ICACHE_LOCK0_SIZE register description 0x50 0x20 PRO_ICACHE_LOCK0_SIZE The bits are used to configure the first length of data locking, which is combined with PRO_ICACHE_LOCK0_ADDR_REG 0 16 read-write PRO_ICACHE_LOCK1_ADDR register description 0x54 0x20 PRO_ICACHE_LOCK1_ADDR The bits are used to configure the second start virtual address of data locking, which is combined with PRO_ICACHE_LOCK1_SIZE_REG 0 32 read-write PRO_ICACHE_LOCK1_SIZE register description 0x58 0x20 PRO_ICACHE_LOCK1_SIZE The bits are used to configure the second length of data locking, which is combined with PRO_ICACHE_LOCK1_ADDR_REG 0 16 read-write PRO_ICACHE_MEM_SYNC0 register description 0x5C 0x20 PRO_ICACHE_MEMSYNC_ADDR The bits are used to configure the start virtual address for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if the address is validate. The auto operations will be issued if the address is invalidate. It should be combined with PRO_ICACHE_MEM_SYNC1. 0 32 read-write PRO_ICACHE_MEM_SYNC1 register description 0x60 0x20 PRO_ICACHE_MEMSYNC_SIZE The bits are used to configure the length for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if it is validate. The auto operations will be issued if it is invalidate. It should be combined with PRO_ICACHE_MEM_SYNC0. 0 19 read-write PRO_ICACHE_PRELOAD_ADDR register description 0x64 0x20 PRO_ICACHE_PRELOAD_ADDR The bits are used to configure the start virtual address for manual pre-load operation. It should be combined with PRO_ICACHE_PRELOAD_SIZE_REG. 0 32 read-write PRO_ICACHE_PRELOAD_SIZE register description 0x68 0x20 0x00000200 PRO_ICACHE_PRELOAD_SIZE The bits are used to configure the length for manual pre-load operation. It should be combined with PRO_ICACHE_PRELOAD_ADDR_REG.. 0 10 read-write PRO_ICACHE_PRELOAD_ORDER The bits are used to configure the direction of manual pre-load operation. 1: descending, 0: ascending. 10 1 read-write PRO_ICACHE_AUTOLOAD_CFG register description 0x6C 0x20 PRO_ICACHE_AUTOLOAD_MODE Reserved. 0 1 read-write PRO_ICACHE_AUTOLOAD_STEP Reserved. 1 2 read-write PRO_ICACHE_AUTOLOAD_ORDER The bits are used to configure the direction of conditional pre-load operation. 1: descending, 0: ascending. 3 1 read-write PRO_ICACHE_AUTOLOAD_RQST The bits are used to configure trigger conditions for conditional pre-load. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit. 4 2 read-write PRO_ICACHE_AUTOLOAD_SIZE The bits are used to configure the numbers of the cache block for the issuing conditional pre-load operation. 6 2 read-write PRO_ICACHE_AUTOLOAD_SCT0_ENA The bits are used to enable the second section for conditional pre-load operation. 8 1 read-write PRO_ICACHE_AUTOLOAD_SCT1_ENA The bits are used to enable the first section for conditional pre-load operation. 9 1 read-write PRO_ICACHE_AUTOLOAD_SECTION0_ADDR register description 0x70 0x20 PRO_ICACHE_AUTOLOAD_SCT0_ADDR The bits are used to configure the start virtual address of the first section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct0_ena. 0 32 read-write PRO_ICACHE_AUTOLOAD_SECTION0_SIZE register description 0x74 0x20 0x00008000 PRO_ICACHE_AUTOLOAD_SCT0_SIZE The bits are used to configure the length of the first section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct0_ena. 0 24 read-write PRO_ICACHE_AUTOLOAD_SECTION1_ADDR register description 0x78 0x20 PRO_ICACHE_AUTOLOAD_SCT1_ADDR The bits are used to configure the start virtual address of the second section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct1_ena. 0 32 read-write PRO_ICACHE_AUTOLOAD_SECTION1_SIZE register description 0x7C 0x20 0x00008000 PRO_ICACHE_AUTOLOAD_SCT1_SIZE The bits are used to configure the length of the second section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct1_ena. 0 24 read-write IC_PRELOAD_CNT register description 0x80 0x20 IC_PRELOAD_CNT The bits are used to count the number of issued pre-load which include manual pre-load and conditional pre-load. 0 16 read-only IC_PRELOAD_MISS_CNT register description 0x84 0x20 IC_PRELOAD_MISS_CNT The bits are used to count the number of missed pre-load which include manual pre-load and conditional pre-load. 0 16 read-only IBUS2_ABANDON_CNT register description 0x88 0x20 IBUS2_ABANDON_CNT The bits are used to count the number of the abandoned ibus2 access. 0 16 read-only IBUS1_ABANDON_CNT register description 0x8C 0x20 IBUS1_ABANDON_CNT The bits are used to count the number of the abandoned ibus1 access. 0 16 read-only IBUS0_ABANDON_CNT register description 0x90 0x20 IBUS0_ABANDON_CNT The bits are used to count the number of the abandoned ibus0 access. 0 16 read-only IBUS2_ACS_MISS_CNT register description 0x94 0x20 IBUS2_ACS_MISS_CNT The bits are used to count the number of the cache miss caused by ibus2 access. 0 32 read-only IBUS1_ACS_MISS_CNT register description 0x98 0x20 IBUS1_ACS_MISS_CNT The bits are used to count the number of the cache miss caused by ibus1 access. 0 32 read-only IBUS0_ACS_MISS_CNT register description 0x9C 0x20 IBUS0_ACS_MISS_CNT The bits are used to count the number of the cache miss caused by ibus0 access. 0 32 read-only IBUS2_ACS_CNT register description 0xA0 0x20 IBUS2_ACS_CNT The bits are used to count the number of ibus2 access icache. 0 32 read-only IBUS1_ACS_CNT register description 0xA4 0x20 IBUS1_ACS_CNT The bits are used to count the number of ibus1 access icache. 0 32 read-only IBUS0_ACS_CNT register description 0xA8 0x20 IBUS0_ACS_CNT The bits are used to count the number of ibus0 access icache. 0 32 read-only DC_PRELOAD_CNT register description 0xAC 0x20 DC_PRELOAD_CNT The bits are used to count the number of issued pre-load which include manual pre-load and conditional pre-load. 0 16 read-only DC_PRELOAD_EVICT_CNT register description 0xB0 0x20 DC_PRELOAD_EVICT_CNT The bits are used to count the number of cache evictions by pre-load which include manual pre-load and conditional pre-load. 0 16 read-only DC_PRELOAD_MISS_CNT register description 0xB4 0x20 DC_PRELOAD_MISS_CNT The bits are used to count the number of missed pre-load which include manual pre-load and conditional pre-load. 0 16 read-only DBUS2_ABANDON_CNT register description 0xB8 0x20 DBUS2_ABANDON_CNT The bits are used to count the number of the abandoned dbus2 access. 0 16 read-only DBUS1_ABANDON_CNT register description 0xBC 0x20 DBUS1_ABANDON_CNT The bits are used to count the number of the abandoned dbus1 access. 0 16 read-only DBUS0_ABANDON_CNT register description 0xC0 0x20 DBUS0_ABANDON_CNT The bits are used to count the number of the abandoned dbus0 access. 0 16 read-only DBUS2_ACS_WB_CNT register description 0xC4 0x20 DBUS2_ACS_WB_CNT The bits are used to count the number of cache evictions by dbus2 access cache. 0 20 read-only DBUS1_ACS_WB_CNT register description 0xC8 0x20 DBUS1_ACS_WB_CNT The bits are used to count the number of cache evictions by dbus1 access cache. 0 20 read-only DBUS0_ACS_WB_CNT register description 0xCC 0x20 DBUS0_ACS_WB_CNT The bits are used to count the number of cache evictions by dbus0 access cache. 0 20 read-only DBUS2_ACS_MISS_CNT register description 0xD0 0x20 DBUS2_ACS_MISS_CNT The bits are used to count the number of the cache miss caused by dbus2 access. 0 32 read-only DBUS1_ACS_MISS_CNT register description 0xD4 0x20 DBUS1_ACS_MISS_CNT The bits are used to count the number of the cache miss caused by dbus1 access. 0 32 read-only DBUS0_ACS_MISS_CNT register description 0xD8 0x20 DBUS0_ACS_MISS_CNT The bits are used to count the number of the cache miss caused by dbus0 access. 0 32 read-only DBUS2_ACS_CNT register description 0xDC 0x20 DBUS2_ACS_CNT The bits are used to count the number of dbus2 access dcache. 0 32 read-only DBUS1_ACS_CNT register description 0xE0 0x20 DBUS1_ACS_CNT The bits are used to count the number of dbus1 access dcache. 0 32 read-only DBUS0_ACS_CNT register description 0xE4 0x20 DBUS0_ACS_CNT The bits are used to count the number of dbus0 access dcache. 0 32 read-only CACHE_DBG_INT_ENA register description 0xE8 0x20 0x00000001 CACHE_DBG_EN The bit is used to activate the cache track function. 1: enable, 0: disable. 0 1 read-write IBUS_ACS_MSK_IC_INT_ENA The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access. 2 1 read-write IBUS_CNT_OVF_INT_ENA The bit is used to enable interrupt by ibus counter overflow. 3 1 read-write IC_SYNC_SIZE_FAULT_INT_ENA The bit is used to enable interrupt by manual sync configurations fault. 4 1 read-write IC_PRELOAD_SIZE_FAULT_INT_ENA The bit is used to enable interrupt by manual pre-load configurations fault. 5 1 read-write ICACHE_REJECT_INT_ENA The bit is used to enable interrupt by authentication fail. 6 1 read-write ICACHE_SET_PRELOAD_ILG_INT_ENA The bit is used to enable interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations. 7 1 read-write ICACHE_SET_SYNC_ILG_INT_ENA The bit is used to enable interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations. 8 1 read-write ICACHE_SET_LOCK_ILG_INT_ENA The bit is used to enable interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations. 9 1 read-write DBUS_ACS_MSK_DC_INT_ENA The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access. 10 1 read-write DBUS_CNT_OVF_INT_ENA The bit is used to enable interrupt by dbus counter overflow. 11 1 read-write DC_SYNC_SIZE_FAULT_INT_ENA The bit is used to enable interrupt by manual sync configurations fault. 12 1 read-write DC_PRELOAD_SIZE_FAULT_INT_ENA The bit is used to enable interrupt by manual pre-load configurations fault. 13 1 read-write DCACHE_WRITE_FLASH_INT_ENA The bit is used to enable interrupt by dcache trying to write flash. 14 1 read-write DCACHE_REJECT_INT_ENA The bit is used to enable interrupt by authentication fail. 15 1 read-write DCACHE_SET_PRELOAD_ILG_INT_ENA The bit is used to enable interrupt by illegal writing preload registers of dcache while dcache is busy to issue lock,sync and pre-load operations. 16 1 read-write DCACHE_SET_SYNC_ILG_INT_ENA The bit is used to enable interrupt by illegal writing sync registers of dcache while dcache is busy to issue lock,sync and pre-load operations. 17 1 read-write DCACHE_SET_LOCK_ILG_INT_ENA The bit is used to enable interrupt by illegal writing lock registers of dcache while dcache is busy to issue lock,sync or pre-load operations. 18 1 read-write MMU_ENTRY_FAULT_INT_ENA The bit is used to enable interrupt by mmu entry fault. 19 1 read-write CACHE_DBG_INT_CLR register description 0xEC 0x20 IBUS_ACS_MSK_IC_INT_CLR The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access. 0 1 write-only IBUS_CNT_OVF_INT_CLR The bit is used to clear interrupt by ibus counter overflow. 1 1 write-only IC_SYNC_SIZE_FAULT_INT_CLR The bit is used to clear interrupt by manual sync configurations fault. 2 1 write-only IC_PRELOAD_SIZE_FAULT_INT_CLR The bit is used to clear interrupt by manual pre-load configurations fault. 3 1 write-only ICACHE_REJECT_INT_CLR The bit is used to clear interrupt by authentication fail. 4 1 write-only ICACHE_SET_ILG_INT_CLR The bit is used to clear interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations. 5 1 write-only DBUS_ACS_MSK_DC_INT_CLR The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access. 6 1 write-only DBUS_CNT_OVF_INT_CLR The bit is used to clear interrupt by dbus counter overflow. 7 1 write-only DC_SYNC_SIZE_FAULT_INT_CLR The bit is used to clear interrupt by manual sync configurations fault. 8 1 write-only DC_PRELOAD_SIZE_FAULT_INT_CLR The bit is used to clear interrupt by manual pre-load configurations fault. 9 1 write-only DCACHE_WRITE_FLASH_INT_CLR The bit is used to clear interrupt by dcache trying to write flash. 10 1 write-only DCACHE_REJECT_INT_CLR The bit is used to clear interrupt by authentication fail. 11 1 write-only DCACHE_SET_ILG_INT_CLR The bit is used to clear interrupt by illegal writing lock registers of dcache while dcache is busy to issue lock,sync or pre-load operations. 12 1 write-only MMU_ENTRY_FAULT_INT_CLR The bit is used to clear interrupt by mmu entry fault. 13 1 write-only CACHE_DBG_STATUS0 register description 0xF0 0x20 IBUS0_ACS_MSK_ICACHE_ST The bit is used to indicate interrupt by cpu access icache while the ibus0 is disabled or icache is disabled which include speculative access. 0 1 read-only IBUS1_ACS_MSK_ICACHE_ST The bit is used to indicate interrupt by cpu access icache while the ibus1 is disabled or icache is disabled which include speculative access. 1 1 read-only IBUS2_ACS_MSK_ICACHE_ST The bit is used to indicate interrupt by cpu access icache while the ibus2 is disabled or icache is disabled which include speculative access. 2 1 read-only IBUS0_ACS_CNT_OVF_ST The bit is used to indicate interrupt by ibus0 counter overflow. 4 1 read-only IBUS1_ACS_CNT_OVF_ST The bit is used to indicate interrupt by ibus1 counter overflow. 5 1 read-only IBUS2_ACS_CNT_OVF_ST The bit is used to indicate interrupt by ibus2 counter overflow. 6 1 read-only IBUS0_ACS_MISS_CNT_OVF_ST The bit is used to indicate interrupt by ibus0 miss counter overflow. 8 1 read-only IBUS1_ACS_MISS_CNT_OVF_ST The bit is used to indicate interrupt by ibus1 miss counter overflow. 9 1 read-only IBUS2_ACS_MISS_CNT_OVF_ST The bit is used to indicate interrupt by ibus2 miss counter overflow. 10 1 read-only IBUS0_ABANDON_CNT_OVF_ST The bit is used to indicate interrupt by ibus0 abandon counter overflow. 12 1 read-only IBUS1_ABANDON_CNT_OVF_ST The bit is used to indicate interrupt by ibus1 abandon counter overflow. 13 1 read-only IBUS2_ABANDON_CNT_OVF_ST The bit is used to indicate interrupt by ibus2 abandon counter overflow. 14 1 read-only IC_PRELOAD_MISS_CNT_OVF_ST The bit is used to indicate interrupt by pre-load miss counter overflow. 16 1 read-only IC_PRELOAD_CNT_OVF_ST The bit is used to indicate interrupt by pre-load counter overflow. 18 1 read-only IC_SYNC_SIZE_FAULT_ST The bit is used to indicate interrupt by manual sync configurations fault. 19 1 read-only IC_PRELOAD_SIZE_FAULT_ST The bit is used to indicate interrupt by manual pre-load configurations fault. 20 1 read-only ICACHE_REJECT_ST The bit is used to indicate interrupt by authentication fail. 21 1 read-only ICACHE_SET_PRELOAD_ILG_ST The bit is used to indicate interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations. 22 1 read-only ICACHE_SET_SYNC_ILG_ST The bit is used to indicate interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations. 23 1 read-only ICACHE_SET_LOCK_ILG_ST The bit is used to indicate interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations. 24 1 read-only CACHE_DBG_STATUS1 register description 0xF4 0x20 DBUS0_ACS_MSK_DCACHE_ST The bit is used to indicate interrupt by cpu access dcache while the dbus0 is disabled or dcache is disabled which include speculative access. 0 1 read-only DBUS1_ACS_MSK_DCACHE_ST The bit is used to indicate interrupt by cpu access dcache while the dbus1 is disabled or dcache is disabled which include speculative access. 1 1 read-only DBUS2_ACS_MSK_DCACHE_ST The bit is used to indicate interrupt by cpu access dcache while the dbus2 is disabled or dcache is disabled which include speculative access. 2 1 read-only DBUS0_ACS_CNT_OVF_ST The bit is used to indicate interrupt by dbus0 counter overflow. 4 1 read-only DBUS1_ACS_CNT_OVF_ST The bit is used to indicate interrupt by dbus1 counter overflow. 5 1 read-only DBUS2_ACS_CNT_OVF_ST The bit is used to indicate interrupt by dbus2 counter overflow. 6 1 read-only DBUS0_ACS_MISS_CNT_OVF_ST The bit is used to indicate interrupt by dbus0 miss counter overflow. 8 1 read-only DBUS1_ACS_MISS_CNT_OVF_ST The bit is used to indicate interrupt by dbus1 miss counter overflow. 9 1 read-only DBUS2_ACS_MISS_CNT_OVF_ST The bit is used to indicate interrupt by dbus2 miss counter overflow. 10 1 read-only DBUS0_ACS_WB_CNT_OVF_ST The bit is used to indicate interrupt by dbus0 eviction counter overflow. 12 1 read-only DBUS1_ACS_WB_CNT_OVF_ST The bit is used to indicate interrupt by dbus1 eviction counter overflow. 13 1 read-only DBUS2_ACS_WB_CNT_OVF_ST The bit is used to indicate interrupt by dbus2 eviction counter overflow. 14 1 read-only DBUS0_ABANDON_CNT_OVF_ST The bit is used to indicate interrupt by dbus0 abandon counter overflow. 16 1 read-only DBUS1_ABANDON_CNT_OVF_ST The bit is used to indicate interrupt by dbus1 abandon counter overflow. 17 1 read-only DBUS2_ABANDON_CNT_OVF_ST The bit is used to indicate interrupt by dbus2 abandon counter overflow. 18 1 read-only DC_PRELOAD_MISS_CNT_OVF_ST The bit is used to indicate interrupt by pre-load miss counter overflow. 20 1 read-only DC_PRELOAD_EVICT_CNT_OVF_ST The bit is used to indicate interrupt by pre-load eviction counter overflow. 21 1 read-only DC_PRELOAD_CNT_OVF_ST The bit is used to indicate interrupt by pre-load counter overflow. 22 1 read-only DC_SYNC_SIZE_FAULT_ST The bit is used to indicate interrupt by manual sync configurations fault. 23 1 read-only DC_PRELOAD_SIZE_FAULT_ST The bit is used to indicate interrupt by manual pre-load configurations fault. 24 1 read-only DCACHE_WRITE_FLASH_ST The bit is used to indicate interrupt by dcache trying to write flash. 25 1 read-only DCACHE_REJECT_ST The bit is used to indicate interrupt by authentication fail. 26 1 read-only DCACHE_SET_PRELOAD_ILG_ST The bit is used to indicate interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations. 27 1 read-only DCACHE_SET_SYNC_ILG_ST The bit is used to indicate interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations. 28 1 read-only DCACHE_SET_LOCK_ILG_ST The bit is used to indicate interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations. 29 1 read-only MMU_ENTRY_FAULT_ST The bit is used to indicate interrupt by mmu entry fault. 30 1 read-only PRO_CACHE_ACS_CNT_CLR register description 0xF8 0x20 PRO_DCACHE_ACS_CNT_CLR The bit is used to clear dcache counter which include DC_PRELOAD_CNT_REG, DC_PRELOAD_EVICT_CNT_REG, DC_PRELOAD_MISS_CNT_REG, DBUS0-2_ABANDON_CNT_REG, DBUS0-2_ACS_WB_CNT_REG, DBUS0-2_ACS_MISS_CNT_REG and DBUS0-2_ACS_CNT_REG. 0 1 write-only PRO_ICACHE_ACS_CNT_CLR The bit is used to clear icache counter which include IC_PRELOAD_CNT_REG, IC_PRELOAD_MISS_CNT_REG, IBUS0-2_ABANDON_CNT_REG, IBUS0-2_ACS_MISS_CNT_REG and IBUS0-2_ACS_CNT_REG. 1 1 write-only PRO_DCACHE_REJECT_ST register description 0xFC 0x20 PRO_DCACHE_TAG_ATTR The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. 0 3 read-only PRO_DCACHE_CPU_ATTR The bits are used to indicate the attribute of CPU access dcache when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. 3 3 read-only PRO_DCACHE_REJECT_VADDR register description 0x100 0x20 PRO_DCACHE_CPU_VADDR The bits are used to indicate the virtual address of CPU access dcache when authentication fail. 0 32 read-only PRO_ICACHE_REJECT_ST register description 0x104 0x20 PRO_ICACHE_TAG_ATTR The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. 0 3 read-only PRO_ICACHE_CPU_ATTR The bits are used to indicate the attribute of CPU access icache when authentication fail. 0: invalidate, 1: execute-able, 2: read-able 3 3 read-only PRO_ICACHE_REJECT_VADDR register description 0x108 0x20 PRO_ICACHE_CPU_VADDR The bits are used to indicate the virtual address of CPU access icache when authentication fail. 0 32 read-only PRO_CACHE_MMU_FAULT_CONTENT register description 0x10C 0x20 PRO_CACHE_MMU_FAULT_CONTENT The bits are used to indicate the content of mmu entry which cause mmu fault.. 0 17 read-only PRO_CACHE_MMU_FAULT_CODE The bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: flush, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx 17 3 read-only PRO_CACHE_MMU_FAULT_VADDR register description 0x110 0x20 PRO_CACHE_MMU_FAULT_VADDR The bits are used to indicate the virtual address which cause mmu fault.. 0 32 read-only PRO_CACHE_WRAP_AROUND_CTRL register description 0x114 0x20 PRO_CACHE_FLASH_WRAP_AROUND The bit is used to enable wrap around mode when read data from flash. 0 1 read-write PRO_CACHE_SRAM_RD_WRAP_AROUND The bit is used to enable wrap around mode when read data from spiram. 1 1 read-write PRO_CACHE_MMU_POWER_CTRL register description 0x118 0x20 0x00000005 PRO_CACHE_MMU_MEM_FORCE_ON The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable 0 1 read-write PRO_CACHE_MMU_MEM_FORCE_PD The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down 1 1 read-write PRO_CACHE_MMU_MEM_FORCE_PU The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up 2 1 read-write PRO_CACHE_STATE register description 0x11C 0x20 PRO_ICACHE_STATE The bit is used to indicate icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state 0 12 read-only PRO_DCACHE_STATE The bit is used to indicate dcache main fsm is in idle state or not. 1: in idle state, 0: not in idle state 12 12 read-only CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE register description 0x120 0x20 RECORD_DISABLE_DB_ENCRYPT Reserved. 0 1 read-write RECORD_DISABLE_G0CB_DECRYPT Reserved. 1 1 read-write CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON register description 0x124 0x20 0x00000007 CLK_FORCE_ON_DB_ENCRYPT The bit is used to close clock gating of encrypt clock. 1: close gating, 0: open clock gating. 0 1 read-write CLK_FORCE_ON_G0CB_DECRYPT The bit is used to close clock gating of decrypt clock. 1: close gating, 0: open clock gating. 1 1 read-write CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT The bit is used to close clock gating of encrypt and decrypt clock. 1: close gating, 0: open clock gating. 2 1 read-write CACHE_BRIDGE_ARBITER_CTRL register description 0x128 0x20 ALLOC_WB_HOLD_ARBITER Reserved. 0 1 read-write CACHE_PRELOAD_INT_CTRL register description 0x12C 0x20 PRO_ICACHE_PRELOAD_INT_ST The bit is used to indicate the interrupt by icache pre-load done. 0 1 read-only PRO_ICACHE_PRELOAD_INT_ENA The bit is used to enable the interrupt by icache pre-load done. 1 1 read-write PRO_ICACHE_PRELOAD_INT_CLR The bit is used to clear the interrupt by icache pre-load done. 2 1 write-only PRO_DCACHE_PRELOAD_INT_ST The bit is used to indicate the interrupt by dcache pre-load done. 3 1 read-only PRO_DCACHE_PRELOAD_INT_ENA The bit is used to enable the interrupt by dcache pre-load done. 4 1 read-write PRO_DCACHE_PRELOAD_INT_CLR The bit is used to clear the interrupt by dcache pre-load done. 5 1 write-only CACHE_SYNC_INT_CTRL register description 0x130 0x20 PRO_ICACHE_SYNC_INT_ST The bit is used to indicate the interrupt by icache sync done. 0 1 read-only PRO_ICACHE_SYNC_INT_ENA The bit is used to enable the interrupt by icache sync done. 1 1 read-write PRO_ICACHE_SYNC_INT_CLR The bit is used to clear the interrupt by icache sync done. 2 1 write-only PRO_DCACHE_SYNC_INT_ST The bit is used to indicate the interrupt by dcache sync done. 3 1 read-only PRO_DCACHE_SYNC_INT_ENA The bit is used to enable the interrupt by dcache sync done. 4 1 read-write PRO_DCACHE_SYNC_INT_CLR The bit is used to clear the interrupt by dcache sync done. 5 1 write-only CACHE_CONF_MISC register description 0x134 0x20 0x00000003 PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT The bit is used to disable checking mmu entry fault by preload operation. 0 1 read-write PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT The bit is used to disable checking mmu entry fault by sync operation. 1 1 read-write CLOCK_GATE register description 0x138 0x20 0x00000001 CLK_EN Reserved. 0 1 read-write PRO_EXTMEM_REG_DATE register description 0x3FC 0x20 0x01904180 PRO_EXTMEM_REG_DATE Reserved. 0 28 read-write GPIO General Purpose Input/Output GPIO 0x3F404000 0x0 0x634 registers GPIO 23 GPIO_NMI 24 GPIO_INTR_2 25 GPIO_NMI_2 26 BT_SELECT GPIO bit select register 0x0 0x20 BT_SEL Reserved 0 32 read-write OUT GPIO0 ~ 31 output register 0x4 0x20 DATA_ORIG GPIO0 ~ 31 output value in simple GPIO output mode. The values of bit0 ~ bit31 correspond to the output value of GPIO0 ~ GPIO31 respectively. Bit22 ~ bit25 are invalid. 0 32 read-write OUT_W1TS GPIO0 ~ 31 output bit set register 0x8 0x20 OUT_W1TS GPIO0 ~ 31 output set register. If the value 1 is written to a bit here, the corre- sponding bit in GPIO_OUT_REG will be set to 1. Recommended operation: use this register to set GPIO_OUT_REG. 0 32 write-only OUT_W1TC GPIO0 ~ 31 output bit clear register 0xC 0x20 OUT_W1TC GPIO0 ~ 31 output clear register. If the value 1 is written to a bit here, the cor- responding bit in GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear GPIO_OUT_REG. 0 32 write-only OUT1 GPIO32 ~ 53 output register 0x10 0x20 DATA_ORIG GPIO32 ~ 53 output value in simple GPIO output mode. The values of bit0 ~ bit13 correspond to GPIO32 ~ GPIO45. Bit14 ~ bit21 are invalid. 0 22 read-write OUT1_W1TS GPIO32 ~ 53 output bit set register 0x14 0x20 OUT1_W1TS GPIO32 ~ 53 output value set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_OUT1_REG will be set to 1. Recommended operation: use this register to set GPIO_OUT1_REG. 0 22 write-only OUT1_W1TC GPIO32 ~ 53 output bit clear register 0x18 0x20 OUT1_W1TC GPIO32 ~ 53 output value clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_OUT1_REG will be cleared. Recommended operation: use this register to clear GPIO_OUT1_REG. 0 22 write-only SDIO_SELECT GPIO SDIO selection register 0x1C 0x20 SDIO_SEL Reserved 0 8 read-write ENABLE GPIO0 ~ 31 output enable register 0x20 0x20 DATA GPIO0~31 output enable register. 0 32 read-write ENABLE_W1TS GPIO0 ~ 31 output enable bit set register 0x24 0x20 ENABLE_W1TS GPIO0 ~ 31 output enable set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set GPIO_ENABLE_REG. 0 32 write-only ENABLE_W1TC GPIO0 ~ 31 output enable bit clear register 0x28 0x20 ENABLE_W1TC GPIO0 ~ 31 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE_REG will be cleared. Recommended operation: use this register to clear GPIO_ENABLE_REG. 0 32 write-only ENABLE1 GPIO32 ~ 53 output enable register 0x2C 0x20 DATA GPIO32~53 output enable register. 0 22 read-write ENABLE1_W1TS GPIO32 ~ 53 output enable bit set register 0x30 0x20 ENABLE1_W1TS GPIO32 ~ 53 output enable set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE1_REG will be set to 1. Recommended operation: use this register to set GPIO_ENABLE1_REG. 0 22 write-only ENABLE1_W1TC GPIO32 ~ 53 output enable bit clear register 0x34 0x20 ENABLE1_W1TC GPIO32 ~ 53 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE1_REG will be cleared. Recommended operation: use this register to clear GPIO_ENABLE1_REG. 0 22 write-only STRAP Bootstrap pin value register 0x38 0x20 STRAPPING GPIO strapping values: bit4 ~ bit2 correspond to stripping pins GPIO45, GPIO0, and GPIO46 respectively. 0 16 read-only IN GPIO0 ~ 31 input register 0x3C 0x20 DATA_NEXT GPIO0 ~ 31 input value. Each bit represents a pad input value, 1 for high level and 0 for low level. 0 32 read-write IN1 GPIO32 ~ 53 input register 0x40 0x20 IN_DATA1_NEXT GPIO32 ~ 53 input value. Each bit represents a pad input value. 0 22 read-only STATUS GPIO0 ~ 31 interrupt status register 0x44 0x20 INTERRUPT GPIO0 ~ 31 interrupt status register. 0 32 read-write STATUS_W1TS GPIO0 ~ 31 interrupt status bit set register 0x48 0x20 STATUS_W1TS GPIO0 ~ 31 interrupt status set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS_INTERRUPT will be set to 1. Recommended operation: use this register to set GPIO_STATUS_INTERRUPT. 0 32 write-only STATUS_W1TC GPIO0 ~ 31 interrupt status bit clear register 0x4C 0x20 STATUS_W1TC GPIO0 ~ 31 interrupt status clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS_INTERRUPT will be cleared. Recommended operation: use this register to clear GPIO_STATUS_INTERRUPT. 0 32 write-only STATUS1 GPIO32 ~ 53 interrupt status register 0x50 0x20 INTERRUPT GPIO32 ~ 53 interrupt status register. 0 22 read-write STATUS1_W1TS GPIO32 ~ 53 interrupt status bit set register 0x54 0x20 STATUS1_W1TS GPIO32 ~ 53 interrupt status set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS1_REG will be set to 1. Recommended operation: use this register to set GPIO_STATUS1_REG. 0 22 write-only STATUS1_W1TC GPIO32 ~ 53 interrupt status bit clear register 0x58 0x20 STATUS1_W1TC GPIO32 ~ 53 interrupt status clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS1_REG will be cleared. Recommended operation: use this register to clear GPIO_STATUS1_REG. 0 22 write-only PCPU_INT GPIO0 ~ 31 PRO_CPU interrupt status register 0x5C 0x20 PROCPU_INT GPIO0 ~ 31 PRO_CPU interrupt status. This interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high) enable signal (bit13 of GPIO_PINn_REG). 0 32 read-only PCPU_NMI_INT GPIO0 ~ 31 PRO_CPU non-maskable interrupt status register 0x60 0x20 PROCPU_NMI_INT GPIO0 ~ 31 PRO_CPU non-maskable interrupt status. This interrupt sta- tus is corresponding to the bit in GPIO_STATUS_REG when assert (high) enable signal (bit 14 of GPIO_PINn_REG). 0 32 read-only CPUSDIO_INT GPIO0 ~ 31 CPU SDIO interrupt status register 0x64 0x20 SDIO_INT GPIO0~31 CPU SDIO interrupt status. 0 32 read-only PCPU_INT1 GPIO32 ~ 53 PRO_CPU interrupt status register 0x68 0x20 PROCPU1_INT GPIO32 ~ 53 PRO_CPU interrupt status. This interrupt status is corresponding to the bit in GPIO_STATUS1_REG when assert (high) enable signal (bit 13 of GPIO_PINn_REG). 0 22 read-only PCPU_NMI_INT1 GPIO32 ~ 53 PRO_CPU non-maskable interrupt status register 0x6C 0x20 PROCPU_NMI1_INT GPIO32 ~ 53 PRO_CPU non-maskable interrupt status. This interrupt status is corresponding to bit in GPIO_STATUS1_REG when assert (high) enable signal (bit 14 of GPIO_PINn_REG). 0 22 read-only CPUSDIO_INT1 GPIO32 ~ 53 CPU SDIO interrupt status register 0x70 0x20 SDIO1_INT GPIO32~53 CPU SDIO interrupt status. 0 22 read-only 54 0x4 PIN%s Configuration for GPIO pin %s 0x74 0x20 SYNC2_BYPASS For the second stage synchronization, GPIO input data can be syn- chronized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge. 0 2 read-write PAD_DRIVER Pad driver selection. 0: normal output; 1: open drain output.. 2 1 read-write SYNC1_BYPASS For the first stage synchronization, GPIO input data can be synchro- nized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge. 3 2 read-write INT_TYPE Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level trigger; 5: high level trigger. (R/W) 7 3 read-write WAKEUP_ENABLE GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. 10 1 read-write CONFIG Reserved 11 2 read-write INT_ENA Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU non-maskable interrupt enabled. 13 5 read-write STATUS_NEXT GPIO0 ~ 31 interrupt source register 0x14C 0x20 STATUS_INTERRUPT_NEXT Interrupt source signal of GPIO0 ~ 31, could be rising edge interrupt, falling edge interrupt, level sensitive interrupt and any edge interrupt. 0 32 read-only STATUS_NEXT1 GPIO32 ~ 53 interrupt source register 0x150 0x20 STATUS1_INTERRUPT_NEXT Interrupt source signal of GPIO32 ~ 53. 0 22 read-only 256 0x4 FUNC%s_IN_SEL_CFG Peripheral function %s input selection register 0x154 0x20 IN_SEL Selection control for peripheral input signal m, selects a pad from the 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a constantly high input or 0x3C for a constantly low input. 0 6 read-write IN_INV_SEL Invert the input value. 1: invert enabled; 0: invert disabled. 6 1 read-write SEL Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals directly to peripheral configured in IO_MUX. 7 1 read-write 54 0x4 FUNC%s_OUT_SEL_CFG Peripheral output selection for GPIO %s 0x554 0x20 0x00000100 OUT_SEL Selection control for GPIO output n. If a value s (0<=s<256) is written to this field, the peripheral output signal s will be connected to GPIO output n. If a value 256 is written to this field, bit n of GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be selected as the output value and output enable. 0 9 read-write INV_SEL 0: Do not invert the output value; 1: Invert the output value. 9 1 read-write OEN_SEL 0: Use output enable signal from peripheral; 1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG. 10 1 read-write OEN_INV_SEL 0: Do not invert the output enable signal; 1: Invert the output enable signal. 11 1 read-write CLOCK_GATE GPIO clock gating register 0x62C 0x20 0x00000001 CLK_EN Clock gating enable bit. If set to 1, the clock is free running. 0 1 read-write REG_DATE Version control register 0x6FC 0x20 0x01905061 DATE Version control register 0 28 read-write GPIO_SD Sigma-Delta Modulation GPIOSD 0x3F404F00 0x0 0x2C registers 8 0x4 SIGMADELTA%s Duty-cycle configuration register of SDM%s 0x0 0x20 0x0000FF00 SD_IN This field is used to configure the duty cycle of sigma delta modulation output. 0 8 read-write SD_PRESCALE This field is used to set a divider value to divide APB clock. 8 8 read-write SIGMADELTA_CG Clock gating configuration register 0x20 0x20 CLK_EN Clock enable bit of configuration registers for sigma delta modulation. 31 1 read-write SIGMADELTA_MISC MISC register 0x24 0x20 FUNCTION_CLK_EN Clock enable bit of sigma delta modulation. 30 1 read-write SPI_SWAP Reserved. 31 1 read-write SIGMADELTA_VERSION Version control register 0x28 0x20 0x01802260 GPIO_SD_DATE Version control register. 0 28 read-write HMAC HMAC (Hash-based Message Authentication Code) Accelerator HMAC 0x6003E000 0x0 0x9C registers SET_START HMAC start control register 0x40 0x20 SET_START Set this bit to enable HMAC. 0 1 write-only SET_PARA_PURPOSE HMAC parameter configuration register 0x44 0x20 PURPOSE_SET Set hmac purpose. 0 4 write-only SET_PARA_KEY HMAC key configuration register 0x48 0x20 KEY_SET Select hmac key. 0 3 write-only SET_PARA_FINISH HMAC configuration completion register 0x4C 0x20 SET_PARA_END Set this bit to finish HMAC configuration. 0 1 write-only SET_MESSAGE_ONE HMAC one message control register 0x50 0x20 SET_TEXT_ONE Call SHA to calculate one message block. 0 1 write-only SET_MESSAGE_ING HMAC message continue register 0x54 0x20 SET_TEXT_ING Set this bit to show there are still some message blocks to be processed. 0 1 write-only SET_MESSAGE_END HMAC message end register 0x58 0x20 SET_TEXT_END Set this bit to start hardware padding. 0 1 write-only SET_RESULT_FINISH HMAC read result completion register 0x5C 0x20 SET_RESULT_END Set this bit to end upstream and clear the calculation result. 0 1 write-only SET_INVALIDATE_JTAG Invalidate JTAG result register 0x60 0x20 SET_INVALIDATE_JTAG Set this bit to clear calculation results in JTAG re-enable function under downstream mode. 0 1 write-only SET_INVALIDATE_DS Invalidate digital signature result register 0x64 0x20 SET_INVALIDATE_DS Set this bit to clear calculation results in DS function under downstream mode. 0 1 write-only QUERY_ERROR The matching result between key and purpose user configured 0x68 0x20 QUERY_CHECK Hmac error status. 0: hmac key and purpose match. 1: error. 0 1 read-only QUERY_BUSY The busy state of HMAC module 0x6C 0x20 BUSY_STATE The state of Hmac. 1'b0: idle. 1'b1: busy. 0 1 read-only 16 0x4 WR_MESSAGE_%s Message register %s 0x80 0x20 WDATA Store the %sth 32-bit of message. 0 32 write-only 8 0x4 RD_RESULT_%s Hash result register %s 0xC0 0x20 RDATA Read the %sth 32-bit of hash result. 0 32 read-only SET_MESSAGE_PAD Software padding register 0xF0 0x20 SET_TEXT_PAD Set this bit to let software do padding job. 0 1 write-only ONE_BLOCK One block message register. 0xF4 0x20 SET_ONE_BLOCK Set this bit to show no padding is required. 0 1 write-only DATE Version control register 0xF8 0x20 0x20190402 DATE Version control register. 0 30 read-write I2C0 I2C (Inter-Integrated Circuit) Controller 0 I2C 0x3F413000 0x0 0xA8 registers I2C_EXT0 52 SCL_LOW_PERIOD Configures the low level width of the SCL clock 0x0 0x20 SCL_LOW_PERIOD This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. 0 14 read-write CTR Transmission setting 0x4 0x20 0x00000A0B SDA_FORCE_OUT 0: direct output. 1: open drain output. 0 1 read-write SCL_FORCE_OUT 0: direct output. 1: open drain output. 1 1 read-write SAMPLE_SCL_LEVEL This register is used to select the sample mode. 1: sample SDA data on the SCL low level. 0: sample SDA data on the SCL high level. 2 1 read-write RX_FULL_ACK_LEVEL This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. 3 1 read-write MS_MODE Set this bit to configure the module as an I2C Master. Clear this bit to configure the module as an I2C Slave. 4 1 read-write TRANS_START Set this bit to start sending the data in TX FIFO. 5 1 read-write TX_LSB_FIRST This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit. 0: send data from the most significant bit. 6 1 read-write RX_LSB_FIRST This bit is used to control the storage mode for received data. 1: receive data from the least significant bit. 0: receive data from the most significant bit. 7 1 read-write CLK_EN Reserved. 8 1 read-write ARBITRATION_EN This is the enable bit for I2C bus arbitration function. 9 1 read-write FSM_RST This register is used to reset the SCL_FSM. 10 1 read-write REF_ALWAYS_ON This register is used to control the REF_TICK. 11 1 read-write SR Describe I2C work status 0x8 0x20 RESP_REC The received ACK value in master mode or slave mode. 0: ACK. 1: NACK. 0 1 read-only SLAVE_RW When in slave mode, 1: master reads from slave. 0: master writes to slave. 1 1 read-only TIME_OUT When the I2C controller takes more than I2C_TIME_OUT clocks to receive a data bit, this field changes to 1. 2 1 read-only ARB_LOST When the I2C controller loses control of SCL line, this register changes to 1. 3 1 read-only BUS_BUSY 1: the I2C bus is busy transferring data. 0: the I2C bus is in idle state. 4 1 read-only SLAVE_ADDRESSED When configured as an I2C Slave, and the address sent by the master is equal to the address of the slave, then this bit will be of high level. 5 1 read-only BYTE_TRANS This field changes to 1 when one byte is transferred. 6 1 read-only RXFIFO_CNT This field represents the amount of data needed to be sent. 8 6 read-only STRETCH_CAUSE The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C TX FIFO is empty in slave mode. 2: stretching SCL low when I2C RX FIFO is full in slave mode. 14 2 read-only TXFIFO_CNT This field stores the amount of received data in RAM. 18 6 read-only SCL_MAIN_STATE_LAST This field indicates the states of the I2C module state machine. 0: Idle. 1: Address shift. 2: ACK address. 3: RX data. 4: TX data. 5: Send ACK. 6: Wait ACK 24 3 read-only SCL_STATE_LAST This field indicates the states of the state machine used to produce SCL. 0: Idle. 1: Start. 2: Negative edge. 3: Low. 4: Positive edge. 5: High. 6: Stop 28 3 read-only TO Setting time out control for receiving data 0xC 0x20 TIME_OUT_VALUE This register is used to configure the timeout for receiving a data bit in APB clock cycles. 0 24 read-write TIME_OUT_EN This is the enable bit for time out control. 24 1 read-write SLAVE_ADDR Local slave address setting 0x10 0x20 SLAVE_ADDR When configured as an I2C Slave, this field is used to configure the slave address. 0 15 read-write ADDR_10BIT_EN This field is used to enable the slave 10-bit addressing mode in master mode. 31 1 read-write FIFO_ST FIFO status register 0x14 0x20 RXFIFO_START_ADDR This is the offset address of the last received data, as described in I2C_NONFIFO_RX_THRES. 0 5 read-only RXFIFO_END_ADDR This is the offset address of the last received data, as described in I2C_NONFIFO_RX_THRES. This value refreshes when an I2C_RXFIFO_UDF_INT or I2C_TRANS_COMPLETE_INT interrupt is generated. 5 5 read-only TXFIFO_START_ADDR This is the offset address of the first sent data, as described in I2C_NONFIFO_TX_THRES. 10 5 read-only TXFIFO_END_ADDR This is the offset address of the last sent data, as described in I2C_NONFIFO_TX_THRES. The value refreshes when an I2C_TXFIFO_OVF_INT or I2C_TRANS_COMPLETE_INT interrupt is generated. 15 5 read-only RX_UPDATE Write 0 or 1 to I2C_RX_UPDATE to update the value of I2C_RXFIFO_END_ADDR and I2C_RXFIFO_START_ADDR. 20 1 write-only TX_UPDATE Write 0 or 1 to I2C_TX_UPDATE to update the value of I2C_TXFIFO_END_ADDR and I2C_TXFIFO_START_ADDR. 21 1 write-only SLAVE_RW_POINT The received data in I2C slave mode. 22 8 read-only FIFO_CONF FIFO configuration register 0x18 0x20 0x0555408B RXFIFO_WM_THRHD The water mark threshold of RX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0], I2C_RXFIFO_WM_INT_RAW bit will be valid. 0 5 read-write TXFIFO_WM_THRHD The water mark threshold of TX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and TX FIFO counter is smaller than I2C_TXFIFO_WM_THRHD[4:0], I2C_TXFIFO_WM_INT_RAW bit will be valid. 5 5 read-write NONFIFO_EN Set this bit to enable APB non-FIFO mode. 10 1 read-write FIFO_ADDR_CFG_EN When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. 11 1 read-write RX_FIFO_RST Set this bit to reset RX FIFO. 12 1 read-write TX_FIFO_RST Set this bit to reset TX FIFO. 13 1 read-write NONFIFO_RX_THRES When I2C receives more than I2C_NONFIFO_RX_THRES bytes of data, it will generate an I2C_RXFIFO_UDF_INT interrupt and update the current offset address of the received data. 14 6 read-write NONFIFO_TX_THRES When I2C sends more than I2C_NONFIFO_TX_THRES bytes of data, it will generate an I2C_TXFIFO_OVF_INT interrupt and update the current offset address of the sent data. 20 6 read-write FIFO_PRT_EN The control enable bit of FIFO pointer in non-FIFO mode. This bit controls the valid bits and the interrupts of TX/RX FIFO overflow, underflow, full and empty. 26 1 read-write DATA RX FIFO read data 0x1C 0x20 FIFO_RDATA The value of RX FIFO read data. 0 8 read-write INT_RAW Raw interrupt status 0x20 0x20 RXFIFO_WM_INT_RAW The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. 0 1 read-only TXFIFO_WM_INT_RAW The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. 1 1 read-only RXFIFO_OVF_INT_RAW The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. 2 1 read-only END_DETECT_INT_RAW The raw interrupt bit for the I2C_END_DETECT_INT interrupt. 3 1 read-only BYTE_TRANS_DONE_INT_RAW The raw interrupt bit for the I2C_END_DETECT_INT interrupt. 4 1 read-only ARBITRATION_LOST_INT_RAW The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. 5 1 read-only MST_TXFIFO_UDF_INT_RAW The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. 6 1 read-only TRANS_COMPLETE_INT_RAW The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. 7 1 read-only TIME_OUT_INT_RAW The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. 8 1 read-only TRANS_START_INT_RAW The raw interrupt bit for the I2C_TRANS_START_INT interrupt. 9 1 read-only NACK_INT_RAW The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. 10 1 read-only TXFIFO_OVF_INT_RAW The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. 11 1 read-only RXFIFO_UDF_INT_RAW The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. 12 1 read-only SCL_ST_TO_INT_RAW The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. 13 1 read-only SCL_MAIN_ST_TO_INT_RAW The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. 14 1 read-only DET_START_INT_RAW The raw interrupt bit for I2C_DET_START_INT interrupt. 15 1 read-only SLAVE_STRETCH_INT_RAW The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. 16 1 read-only INT_CLR Interrupt clear bits 0x24 0x20 RXFIFO_WM_INT_CLR Set this bit to clear I2C_RXFIFO_WM_INT interrupt. 0 1 write-only TXFIFO_WM_INT_CLR Set this bit to clear I2C_TXFIFO_WM_INT interrupt. 1 1 write-only RXFIFO_OVF_INT_CLR Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. 2 1 write-only END_DETECT_INT_CLR Set this bit to clear the I2C_END_DETECT_INT interrupt. 3 1 write-only BYTE_TRANS_DONE_INT_CLR Set this bit to clear the I2C_END_DETECT_INT interrupt. 4 1 write-only ARBITRATION_LOST_INT_CLR Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. 5 1 write-only MST_TXFIFO_UDF_INT_CLR Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. 6 1 write-only TRANS_COMPLETE_INT_CLR Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. 7 1 write-only TIME_OUT_INT_CLR Set this bit to clear the I2C_TIME_OUT_INT interrupt. 8 1 write-only TRANS_START_INT_CLR Set this bit to clear the I2C_TRANS_START_INT interrupt. 9 1 write-only NACK_INT_CLR Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. 10 1 write-only TXFIFO_OVF_INT_CLR Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. 11 1 write-only RXFIFO_UDF_INT_CLR Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. 12 1 write-only SCL_ST_TO_INT_CLR Set this bit to clear I2C_SCL_ST_TO_INT interrupt. 13 1 write-only SCL_MAIN_ST_TO_INT_CLR Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. 14 1 write-only DET_START_INT_CLR Set this bit to clear I2C_DET_START_INT interrupt. 15 1 write-only SLAVE_STRETCH_INT_CLR Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. 16 1 write-only INT_ENA Interrupt enable bits 0x28 0x20 RXFIFO_WM_INT_ENA The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. 0 1 read-write TXFIFO_WM_INT_ENA The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. 1 1 read-write RXFIFO_OVF_INT_ENA The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. 2 1 read-write END_DETECT_INT_ENA The raw interrupt bit for the I2C_END_DETECT_INT interrupt. 3 1 read-write BYTE_TRANS_DONE_INT_ENA The raw interrupt bit for the I2C_END_DETECT_INT interrupt. 4 1 read-write ARBITRATION_LOST_INT_ENA The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. 5 1 read-write MST_TXFIFO_UDF_INT_ENA The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. 6 1 read-write TRANS_COMPLETE_INT_ENA The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. 7 1 read-write TIME_OUT_INT_ENA The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. 8 1 read-write TRANS_START_INT_ENA The raw interrupt bit for the I2C_TRANS_START_INT interrupt. 9 1 read-write NACK_INT_ENA The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. 10 1 read-write TXFIFO_OVF_INT_ENA The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. 11 1 read-write RXFIFO_UDF_INT_ENA The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. 12 1 read-write SCL_ST_TO_INT_ENA The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. 13 1 read-write SCL_MAIN_ST_TO_INT_ENA The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. 14 1 read-write DET_START_INT_ENA The raw interrupt bit for I2C_DET_START_INT interrupt. 15 1 read-write SLAVE_STRETCH_INT_ENA The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. 16 1 read-write INT_STATUS Status of captured I2C communication events 0x2C 0x20 RXFIFO_WM_INT_ST The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. 0 1 read-only TXFIFO_WM_INT_ST The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. 1 1 read-only RXFIFO_OVF_INT_ST The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. 2 1 read-only END_DETECT_INT_ST The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. 3 1 read-only BYTE_TRANS_DONE_INT_ST The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. 4 1 read-only ARBITRATION_LOST_INT_ST The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. 5 1 read-only MST_TXFIFO_UDF_INT_ST The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. 6 1 read-only TRANS_COMPLETE_INT_ST The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. 7 1 read-only TIME_OUT_INT_ST The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. 8 1 read-only TRANS_START_INT_ST The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. 9 1 read-only NACK_INT_ST The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. 10 1 read-only TXFIFO_OVF_INT_ST The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. 11 1 read-only RXFIFO_UDF_INT_ST The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. 12 1 read-only SCL_ST_TO_INT_ST The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. 13 1 read-only SCL_MAIN_ST_TO_INT_ST The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. 14 1 read-only DET_START_INT_ST The masked interrupt status bit for I2C_DET_START_INT interrupt. 15 1 read-only SLAVE_STRETCH_INT_ST The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. 16 1 read-only SDA_HOLD Configures the hold time after a negative SCL edge 0x30 0x20 TIME This register is used to configure the interval between changing the SDA output level and the falling edge of SCL, in I2C module clock cycles. 0 10 read-write SDA_SAMPLE Configures the sample time after a positive SCL edge 0x34 0x20 TIME This register is used to configure the interval between the rising edge of SCL and the level sampling time of SDA, in I2C module clock cycles. 0 10 read-write SCL_HIGH_PERIOD Configures the high level width of the SCL clock 0x38 0x20 SCL_HIGH_PERIOD This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles. 0 14 read-write SCL_WAIT_HIGH_PERIOD This register is used to configure for the SCL_FSM's waiting period for SCL to go high in master mode, in I2C module clock cycles. 14 14 read-write SCL_START_HOLD Configures the interval between pulling SDA low and pulling SCL low when the master generates a START condition 0x40 0x20 0x00000008 TIME This register is used to configure interval between pulling SDA low and pulling SCL low when the master generates a START condition, in I2C module clock cycles. 0 10 read-write SCL_RSTART_SETUP Configures the interval between the positive edge of SCL and the negative edge of SDA 0x44 0x20 0x00000008 TIME This register is used to configure the interval between the positive edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. 0 10 read-write SCL_STOP_HOLD Configures the delay after the SCL clock edge for a stop condition 0x48 0x20 TIME This register is used to configure the delay after the STOP condition, in I2C module clock cycles. 0 14 read-write SCL_STOP_SETUP Configures the delay between the SDA and SCL positive edge for a stop condition 0x4C 0x20 TIME This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles. 0 10 read-write SCL_FILTER_CFG SCL filter configuration register 0x50 0x20 0x00000010 SCL_FILTER_THRES When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse. 0 4 read-write SCL_FILTER_EN This is the filter enable bit for SCL. 4 1 read-write SDA_FILTER_CFG SDA filter configuration register 0x54 0x20 0x00000010 SDA_FILTER_THRES When a pulse on the SDA input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse. 0 4 read-write SDA_FILTER_EN This is the filter enable bit for SDA. 4 1 read-write 16 0x4 0-15 COMD%s I2C command register %s 0x58 0x20 COMMAND This is the content of command 0. It consists of three parts: op_code is the command, 0: RSTART. 1: WRITE. 2: READ. 3: STOP. 4: END. byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. 0 14 read-write COMMAND_DONE When command 0 is done in I2C Master mode, this bit changes to high level. 31 1 read-write SCL_ST_TIME_OUT SCL status time out register 0x98 0x20 0x00000100 SCL_ST_TO The threshold value of SCL_FSM state unchanged period. 0 24 read-write SCL_MAIN_ST_TIME_OUT SCL main status time out register 0x9C 0x20 0x00000100 SCL_MAIN_ST_TO The threshold value of SCL_MAIN_FSM state unchanged period. 0 24 read-write SCL_SP_CONF Power configuration register 0xA0 0x20 SCL_RST_SLV_EN When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to I2C_SCL_RST_SLV_NUM[4:0]. 0 1 read-write SCL_RST_SLV_NUM Configure the pulses of SCL generated in I2C master mode. Valid when I2C_SCL_RST_SLV_EN is 1. 1 5 read-write SCL_PD_EN The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set I2C_SCL_FORCE_OUT and I2C_SCL_PD_EN to 1 to stretch SCL low. 6 1 read-write SDA_PD_EN The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set I2C_SDA_FORCE_OUT and I2C_SDA_PD_EN to 1 to stretch SDA low. 7 1 read-write SCL_STRETCH_CONF Set SCL stretch of I2C slave 0xA4 0x20 STRETCH_PROTECT_NUM Configure the period of I2C slave stretching SCL line. 0 10 read-write SLAVE_SCL_STRETCH_EN The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The stretch cause can be seen in I2C_STRETCH_CAUSE. 10 1 read-write SLAVE_SCL_STRETCH_CLR Set this bit to clear the I2C slave SCL stretch function. 11 1 write-only DATE Version control register 0xF8 0x20 0x19052000 DATE This is the the version control register. 0 32 read-write I2C1 I2C (Inter-Integrated Circuit) Controller 1 0x3F427000 I2C_EXT1 53 I2S0 I2S (Inter-IC Sound) Controller 0 I2S 0x3F40F000 0x0 0x88 registers I2S0 35 I2S1 36 CONF I2S configuration register 0x8 0x20 0x000C0300 TX_RESET Set this bit to reset transmitter. 0 1 write-only RX_RESET Set this bit to reset receiver. 1 1 write-only TX_FIFO_RESET Set this bit to reset TX FIFO. 2 1 write-only RX_FIFO_RESET Set this bit to reset RX FIFO. 3 1 write-only TX_START Set this bit to start transmitting data. 4 1 read-write RX_START Set this bit to start receiving data. 5 1 read-write TX_SLAVE_MOD Set this bit to enable slave transmitter mode. 6 1 read-write RX_SLAVE_MOD Set this bit to enable slave receiver mode. 7 1 read-write TX_RIGHT_FIRST Set this bit to transmit right channel data first. 8 1 read-write RX_RIGHT_FIRST Set this bit to receive right channel data first. 9 1 read-write TX_MSB_SHIFT Set this bit to enable transmitter in Phillips standard mode. 10 1 read-write RX_MSB_SHIFT Set this bit to enable receiver in Phillips standard mode. 11 1 read-write TX_SHORT_SYNC Set this bit to enable transmitter in PCM standard mode. 12 1 read-write RX_SHORT_SYNC Set this bit to enable receiver in PCM standard mode. 13 1 read-write TX_MONO Set this bit to enable transmitter in mono mode. 14 1 read-write RX_MONO Set this bit to enable receiver in mono mode. 15 1 read-write TX_MSB_RIGHT Set this bit to place right channel data at the MSB in TX FIFO. 16 1 read-write RX_MSB_RIGHT Set this bit to place right channel data at the MSB in RX FIFO. 17 1 read-write TX_LSB_FIRST_DMA 1:the data in DMA/APB transform from low bits. 0:the data from DMA/APB transform from high bits. 18 1 read-write RX_LSB_FIRST_DMA 1:the data in DMA/APB transform from low bits. 0:the data from DMA/APB transform from high bits. 19 1 read-write SIG_LOOPBACK Enable signal loopback mode with transmitter module and receiver module sharing the same WS and BCK signals. 20 1 read-write TX_FIFO_RESET_ST I2S TX FIFO reset status. 1: I2S_TX_FIFO_RESET is not completed. 0: I2S_TX_FIFO_RESET is completed. 21 1 read-only RX_FIFO_RESET_ST I2S RX FIFO reset status. 1: I2S_RX_FIFO_RESET is not completed. 0: I2S_RX_FIFO_RESET is completed. 22 1 read-only TX_RESET_ST I2S TX reset status. 1: I2S_TX_RESET is not completed. 0: I2S_TX_RESET is completed. 23 1 read-only TX_DMA_EQUAL 1: Data in left channel is equal to data in right channel. 0: Data in left channel is not equal to data in right channel. 24 1 read-write RX_DMA_EQUAL 1: Data in left channel is equal to data in right channel. 0: Data in left channel is not equal to data in right channel. 25 1 read-write PRE_REQ_EN Set this bit to enable I2S to prepare data earlier. 26 1 read-write TX_BIG_ENDIAN I2S TX byte endianness. 27 1 read-write RX_BIG_ENDIAN I2S RX byte endianness. 28 1 read-write RX_RESET_ST I2S RX reset status. 1: I2S_RX_RESET is not completed. 0: I2S_RX_RESET is completed. 29 1 read-only INT_RAW Raw interrupt status 0xC 0x20 RX_TAKE_DATA_INT_RAW The raw interrupt status bit for I2S_RX_TAKE_DATA_INT interrupt. 0 1 read-only TX_PUT_DATA_INT_RAW The raw interrupt status bit for I2S_TX_PUT_DATA_INT interrupt. 1 1 read-only RX_WFULL_INT_RAW The raw interrupt status bit for I2S_RX_WFULL_INT interrupt. 2 1 read-only RX_REMPTY_INT_RAW The raw interrupt status bit for I2S_RX_REMPTY_INT interrupt. 3 1 read-only TX_WFULL_INT_RAW The raw interrupt status bit for I2S_TX_WFULL_INT interrupt. 4 1 read-only TX_REMPTY_INT_RAW The raw interrupt status bit for I2S_TX_REMPTY_INT interrupt. 5 1 read-only RX_HUNG_INT_RAW The raw interrupt status bit for I2S_RX_HUNG_INT interrupt. 6 1 read-only TX_HUNG_INT_RAW The raw interrupt status bit for I2S_TX_HUNG_INT interrupt. 7 1 read-only IN_DONE_INT_RAW The raw interrupt status bit for I2S_IN_DONE_INT interrupt. 8 1 read-only IN_SUC_EOF_INT_RAW The raw interrupt status bit for I2S_IN_SUC_EOF_INT interrupt. 9 1 read-only IN_ERR_EOF_INT_RAW Reserved. 10 1 read-only OUT_DONE_INT_RAW The raw interrupt status bit for I2S_OUT_DONE_INT interrupt. 11 1 read-only OUT_EOF_INT_RAW The raw interrupt status bit for I2S_OUT_EOF_INT interrupt. 12 1 read-only IN_DSCR_ERR_INT_RAW The raw interrupt status bit for I2S_IN_DSCR_ERR_INT interrupt. 13 1 read-only OUT_DSCR_ERR_INT_RAW The raw interrupt status bit for I2S_OUT_DSCR_ERR_INT interrupt. 14 1 read-only IN_DSCR_EMPTY_INT_RAW The raw interrupt status bit for I2S_IN_DSCR_EMPTY_INT interrupt. 15 1 read-only OUT_TOTAL_EOF_INT_RAW The raw interrupt status bit for I2S_OUT_TOTAL_EOF_INT interrupt. 16 1 read-only V_SYNC_INT_RAW The raw interrupt status bit for I2S_V_SYNC_INT interrupt. 17 1 read-only INT_ST Masked interrupt status 0x10 0x20 RX_TAKE_DATA_INT_ST The masked interrupt status bit for I2S_RX_TAKE_DATA_INT interrupt. 0 1 read-only TX_PUT_DATA_INT_ST The masked interrupt status bit for I2S_TX_PUT_DATA_INT interrupt. 1 1 read-only RX_WFULL_INT_ST The masked interrupt status bit for I2S_RX_WFULL_INT interrupt. 2 1 read-only RX_REMPTY_INT_ST The masked interrupt status bit for I2S_RX_REMPTY_INT interrupt. 3 1 read-only TX_WFULL_INT_ST The masked interrupt status bit for I2S_TX_WFULL_INT interrupt. 4 1 read-only TX_REMPTY_INT_ST The masked interrupt status bit for I2S_TX_REMPTY_INT interrupt. 5 1 read-only RX_HUNG_INT_ST The masked interrupt status bit for I2S_RX_HUNG_INT interrupt. 6 1 read-only TX_HUNG_INT_ST The masked interrupt status bit for I2S_TX_HUNG_INT interrupt. 7 1 read-only IN_DONE_INT_ST The masked interrupt status bit for I2S_IN_DONE_INT interrupt. 8 1 read-only IN_SUC_EOF_INT_ST The masked interrupt status bit for I2S_IN_SUC_EOF_INT interrupt. 9 1 read-only IN_ERR_EOF_INT_ST Reserved. 10 1 read-only OUT_DONE_INT_ST The masked interrupt status bit for I2S_OUT_DONE_INT interrupt. 11 1 read-only OUT_EOF_INT_ST The masked interrupt status bit for I2S_OUT_EOF_INT interrupt. 12 1 read-only IN_DSCR_ERR_INT_ST The masked interrupt status bit for I2S_IN_DSCR_ERR_INT interrupt. 13 1 read-only OUT_DSCR_ERR_INT_ST The masked interrupt status bit for I2S_OUT_DSCR_ERR_INT interrupt. 14 1 read-only IN_DSCR_EMPTY_INT_ST The masked interrupt status bit for I2S_IN_DSCR_EMPTY_INT interrupt. 15 1 read-only OUT_TOTAL_EOF_INT_ST The masked interrupt status bit for I2S_OUT_TOTAL_EOF_INT interrupt. 16 1 read-only V_SYNC_INT_ST The masked interrupt status bit for I2S_V_SYNC_INT interrupt. 17 1 read-only INT_ENA Interrupt enable bits 0x14 0x20 RX_TAKE_DATA_INT_ENA The interrupt enable bit for I2S_RX_TAKE_DATA_INT interrupt. 0 1 read-write TX_PUT_DATA_INT_ENA The interrupt enable bit for I2S_TX_PUT_DATA_INT interrupt. 1 1 read-write RX_WFULL_INT_ENA The interrupt enable bit for I2S_RX_WFULL_INT interrupt. 2 1 read-write RX_REMPTY_INT_ENA The interrupt enable bit for I2S_RX_REMPTY_INT interrupt. 3 1 read-write TX_WFULL_INT_ENA The interrupt enable bit for I2S_TX_WFULL_INT interrupt. 4 1 read-write TX_REMPTY_INT_ENA The interrupt enable bit for I2S_TX_REMPTY_INT interrupt. 5 1 read-write RX_HUNG_INT_ENA The interrupt enable bit for I2S_RX_HUNG_INT interrupt. 6 1 read-write TX_HUNG_INT_ENA The interrupt enable bit for I2S_TX_HUNG_INT interrupt. 7 1 read-write IN_DONE_INT_ENA The interrupt enable bit for I2S_IN_DONE_INT interrupt. 8 1 read-write IN_SUC_EOF_INT_ENA The interrupt enable bit for I2S_IN_SUC_EOF_INT interrupt. 9 1 read-write IN_ERR_EOF_INT_ENA Reserved. 10 1 read-write OUT_DONE_INT_ENA The interrupt enable bit for I2S_OUT_DONE_INT interrupt. 11 1 read-write OUT_EOF_INT_ENA The interrupt enable bit for I2S_OUT_EOF_INT interrupt. 12 1 read-write IN_DSCR_ERR_INT_ENA The interrupt enable bit for I2S_IN_DSCR_ERR_INT interrupt. 13 1 read-write OUT_DSCR_ERR_INT_ENA The interrupt enable bit for I2S_OUT_DSCR_ERR_INT interrupt. 14 1 read-write IN_DSCR_EMPTY_INT_ENA The interrupt enable bit for I2S_IN_DSCR_EMPTY_INT interrupt. 15 1 read-write OUT_TOTAL_EOF_INT_ENA The interrupt enable bit for I2S_OUT_TOTAL_EOF_INT interrupt. 16 1 read-write V_SYNC_INT_ENA The interrupt enable bit for I2S_V_SYNC_INT interrupt. 17 1 read-write INT_CLR Interrupt clear bits 0x18 0x20 TAKE_DATA_INT_CLR Set this bit to clear I2S_RX_TAKE_DATA_INT interrupt. 0 1 write-only PUT_DATA_INT_CLR Set this bit to clear I2S_TX_PUT_DATA_INT interrupt. 1 1 write-only RX_WFULL_INT_CLR Set this bit to clear I2S_RX_WFULL_INT interrupt. 2 1 write-only RX_REMPTY_INT_CLR Set this bit to clear I2S_RX_REMPTY_INT interrupt. 3 1 write-only TX_WFULL_INT_CLR Set this bit to clear I2S_TX_WFULL_INT interrupt. 4 1 write-only TX_REMPTY_INT_CLR Set this bit to clear I2S_TX_REMPTY_INT interrupt. 5 1 write-only RX_HUNG_INT_CLR Set this bit to clear I2S_RX_HUNG_INT interrupt. 6 1 write-only TX_HUNG_INT_CLR Set this bit to clear I2S_TX_HUNG_INT interrupt. 7 1 write-only IN_DONE_INT_CLR Set this bit to clear I2S_IN_DONE_INT interrupt. 8 1 write-only IN_SUC_EOF_INT_CLR Set this bit to clear I2S_IN_SUC_EOF_INT interrupt. 9 1 write-only IN_ERR_EOF_INT_CLR Reserved. 10 1 write-only OUT_DONE_INT_CLR Set this bit to clear I2S_OUT_DONE_INT interrupt. 11 1 write-only OUT_EOF_INT_CLR Set this bit to clear I2S_OUT_EOF_INT interrupt. 12 1 write-only IN_DSCR_ERR_INT_CLR Set this bit to clear I2S_IN_DSCR_ERR_INT interrupt. 13 1 write-only OUT_DSCR_ERR_INT_CLR Set this bit to clear I2S_OUT_DSCR_ERR_INT interrupt. 14 1 write-only IN_DSCR_EMPTY_INT_CLR Set this bit to clear I2S_IN_DSCR_EMPTY_INT interrupt. 15 1 write-only OUT_TOTAL_EOF_INT_CLR Set this bit to clear I2S_OUT_TOTAL_EOF_INT interrupt. 16 1 write-only V_SYNC_INT_CLR Set this bit to clear I2S_V_SYNC_INT interrupt. 17 1 write-only TIMING I2S timing register 0x1C 0x20 TX_BCK_IN_DELAY Number of delay cycles for BCK signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles. 0 2 read-write TX_WS_IN_DELAY Number of delay cycles for WS signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles. 2 2 read-write RX_BCK_IN_DELAY Number of delay cycles for BCK signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles. 4 2 read-write RX_WS_IN_DELAY Number of delay cycles for WS signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles. 6 2 read-write RX_SD_IN_DELAY Number of delay cycles for SD signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles. 8 2 read-write TX_BCK_OUT_DELAY Number of delay cycles for BCK signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles. 10 2 read-write TX_WS_OUT_DELAY Number of delay cycles for WS signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles. 12 2 read-write TX_SD_OUT_DELAY Number of delay cycles for SD signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles. 14 2 read-write RX_WS_OUT_DELAY Number of delay cycles for WS signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles. 16 2 read-write RX_BCK_OUT_DELAY Number of delay cycles for BCK signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles. 18 2 read-write TX_DSYNC_SW Set this bit to synchronize signals into the transmitter by two flip-flop synchronizer. 0: the signals will be firstly clocked by rising clock edge , then clocked by falling clock edge. 1: the signals will be firstly clocked by falling clock edge, then clocked by rising clock edge. 20 1 read-write RX_DSYNC_SW Set this bit to synchronize signals into the receiver by two flip-flop synchronizer. 0: the signals will be clocked by rising clock edge firstly, then clocked by falling clock edge. 1: the signals will be clocked by falling clock edge firstly, then clocked by rising clock edge. 21 1 read-write DATA_ENABLE_DELAY Number of delay cycles for data valid flag based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles. 22 2 read-write TX_BCK_IN_INV Set this bit to invert BCK signal input to the slave transmitter. 24 1 read-write FIFO_CONF I2S FIFO configuration register 0x20 0x20 0x00001820 RX_DATA_NUM I2S_RX_TAKE_DATA_INT is triggered when the left and right channel data number in RX FIFO is larger than the value of I2S_RX_DATA_NUM[5:0]. (RX FIFO is almost full threshold.) 0 6 read-write TX_DATA_NUM I2S_TX_PUT_DATA_INT is triggered when the left and right channel data number in TX FIFO is smaller than the value of I2S_TX_DATA_NUM[5:0]. (TX FIFO is almost empty threshold.) 6 6 read-write DSCR_EN Set this bit to enable I2S DMA mode. 12 1 read-write TX_FIFO_MOD Transmitter FIFO mode configuration bits 13 3 read-write RX_FIFO_MOD Receiver FIFO mode configuration bits 16 3 read-write TX_FIFO_MOD_FORCE_EN The bit should always be set to 1 19 1 read-write RX_FIFO_MOD_FORCE_EN The bit should always be set to 1 20 1 read-write RX_FIFO_SYNC force write back rx data to memory 21 1 read-write RX_24MSB_EN Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo 22 1 read-write TX_24MSB_EN Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo 23 1 read-write RXEOF_NUM I2S DMA RX EOF data length 0x24 0x20 0x00000040 RX_EOF_NUM The length of data to be received. It will trigger I2S_IN_SUC_EOF_INT. 0 32 read-write CONF_SIGLE_DATA Constant single channel data 0x28 0x20 SIGLE_DATA The right channel or left channel transmits constant value stored in this register according to I2S_TX_CHAN_MOD and I2S_TX_MSB_RIGHT. 0 32 read-write CONF_CHAN I2S channel configuration register 0x2C 0x20 TX_CHAN_MOD I2S transmitter channel mode configuration bits. 0 3 read-write RX_CHAN_MOD I2S receiver channel mode configuration bits. 3 2 read-write OUT_LINK I2S DMA TX configuration register 0x30 0x20 OUTLINK_ADDR The address of first outlink descriptor. 0 20 read-write OUTLINK_STOP Set this bit to stop outlink descriptor. 28 1 read-write OUTLINK_START Set this bit to start outlink descriptor. 29 1 read-write OUTLINK_RESTART Set this bit to restart outlink descriptor. 30 1 read-write OUTLINK_PARK 31 1 read-only IN_LINK I2S DMA RX configuration register 0x34 0x20 INLINK_ADDR The address of first inlink descriptor. 0 20 read-write INLINK_STOP Set this bit to stop inlink descriptor. 28 1 read-write INLINK_START Set this bit to start inlink descriptor. 29 1 read-write INLINK_RESTART Set this bit to restart inlink descriptor. 30 1 read-write INLINK_PARK 31 1 read-only OUT_EOF_DES_ADDR Address of outlink descriptor that produces EOF 0x38 0x20 OUT_EOF_DES_ADDR The address of outlink descriptor that produces EOF. 0 32 read-only IN_EOF_DES_ADDR Address of inlink descriptor that produces EOF 0x3C 0x20 IN_SUC_EOF_DES_ADDR The address of inlink descriptor that produces EOF. 0 32 read-only OUT_EOF_BFR_DES_ADDR Address of buffer relative to the outlink descriptor that produces EOF 0x40 0x20 OUT_EOF_BFR_DES_ADDR The address of buffer relative to the outlink descriptor that produces EOF. 0 32 read-only INLINK_DSCR Address of current inlink descriptor 0x48 0x20 INLINK_DSCR The address of current inlink descriptor. 0 32 read-only INLINK_DSCR_BF0 Address of next inlink descriptor 0x4C 0x20 INLINK_DSCR_BF0 The address of next inlink descriptor. 0 32 read-only INLINK_DSCR_BF1 Address of next inlink data buffer 0x50 0x20 INLINK_DSCR_BF1 The address of next inlink data buffer. 0 32 read-only OUTLINK_DSCR Address of current outlink descriptor 0x54 0x20 OUTLINK_DSCR The address of current outlink descriptor. 0 32 read-only OUTLINK_DSCR_BF0 Address of next outlink descriptor 0x58 0x20 OUTLINK_DSCR_BF0 The address of next outlink descriptor. 0 32 read-only OUTLINK_DSCR_BF1 Address of next outlink data buffer 0x5C 0x20 OUTLINK_DSCR_BF1 The address of next outlink data buffer. 0 32 read-only LC_CONF I2S DMA configuration register 0x60 0x20 0x00000100 IN_RST Set this bit to reset in-DMA FSM. Set this bit before the DMA configuration. 0 1 read-write OUT_RST Set this bit to reset out-DMA FSM. Set this bit before the DMA configuration. 1 1 read-write AHBM_FIFO_RST Set this bit to reset AHB interface cmdFIFO of DMA. Set this bit before the DMA configuration. 2 1 read-write AHBM_RST Set this bit to reset AHB interface of DMA. Set this bit before the DMA configuration. 3 1 read-write OUT_LOOP_TEST Set this bit to loop test inlink. 4 1 read-write IN_LOOP_TEST Set this bit to loop test outlink. 5 1 read-write OUT_AUTO_WRBACK Set this bit to enable outlink-written-back automatically when out buffer is transmitted done. 6 1 read-write OUT_NO_RESTART_CLR Reserved. 7 1 read-write OUT_EOF_MODE DMA out EOF flag generation mode. 1: When DMA has popped all data from the FIFO. 0: When AHB has pushed all data to the FIFO. 8 1 read-write OUTDSCR_BURST_EN DMA outlink descriptor transfer mode configuration bit. 1: Prepare outlink descriptor with burst mode. 0: Prepare outlink descriptor with byte mode. 9 1 read-write INDSCR_BURST_EN DMA inlink descriptor transfer mode configuration bit. 1: Prepare inlink descriptor with burst mode. 0: Prepare inlink descriptor with byte mode. 10 1 read-write OUT_DATA_BURST_EN Transmitter data transfer mode configuration bit. 1: Prepare out data with burst mode. 0: Prepare out data with byte mode. 11 1 read-write CHECK_OWNER Set this bit to enable check owner bit by hardware. 12 1 read-write MEM_TRANS_EN Reserved. 13 1 read-write EXT_MEM_BK_SIZE DMA access external memory block size. 0: 16 bytes. 1: 32 bytes. 2: 64 bytes. 3: reserved. 14 2 read-write OUTFIFO_PUSH APB out FIFO mode register 0x64 0x20 OUTFIFO_WDATA APB out FIFO write data. 0 9 read-write OUTFIFO_PUSH APB out FIFO push. 16 1 read-write INFIFO_POP APB in FIFO mode register 0x68 0x20 INFIFO_RDATA APB in FIFO read data. 0 12 read-only INFIFO_POP APB in FIFO pop. 16 1 read-write LC_STATE0 I2S DMA TX status 0x6C 0x20 OUTLINK_DSCR_ADDR I2S DMA out descriptor address. 0 18 read-only OUT_DSCR_STATE I2S DMA out descriptor state. 18 2 read-only OUT_STATE I2S DMA out data state. 20 3 read-only OUTFIFO_CNT The remains of I2S DMA outfifo data. 23 7 read-only OUT_FULL I2S DMA outfifo is full. 30 1 read-only OUT_EMPTY I2S DMA outfifo is empty. 31 1 read-only LC_STATE1 I2S DMA RX status 0x70 0x20 INLINK_DSCR_ADDR I2S DMA in descriptor address. 0 18 read-only IN_DSCR_STATE I2S DMA in descriptor state. 18 2 read-only IN_STATE I2S DMA in data state. 20 3 read-only INFIFO_CNT_DEBUG The remains of I2S DMA infifo data. 23 7 read-only IN_FULL I2S DMA infifo is full. 30 1 read-only IN_EMPTY I2S DMA infifo is empty. 31 1 read-only LC_HUNG_CONF I2S Hung configuration register 0x74 0x20 0x00000810 LC_FIFO_TIMEOUT I2S_TX_HUNG_INT interrupt or I2S_RX_HUNG_INT interrupt will be triggered when FIFO hung counter is equal to this value. 0 8 read-write LC_FIFO_TIMEOUT_SHIFT The bits are used to set the tick counter threshold. The tick counter is clocked by APB_CLK. The tick counter threshold is 88000/2^I2S_LC_FIFO_TIMEOUT_SHIFT. The tick counter is reset when it reaches the threshold. 8 3 read-write LC_FIFO_TIMEOUT_ENA The enable bit for FIFO timeout. 11 1 read-write CONF1 I2S configuration register 1 0xA0 0x20 0x00000089 TX_PCM_CONF Compress/Decompress module configuration bits. 0: decompress transmitted data 1:compress transmitted data 0 3 read-write TX_PCM_BYPASS Set this bit to bypass Compress/Decompress module for transmitted data. 3 1 read-write RX_PCM_CONF Compress/Decompress module configuration bits. 0: decompress received data 1:compress received data 4 3 read-write RX_PCM_BYPASS Set this bit to bypass Compress/Decompress module for received data. 7 1 read-write TX_STOP_EN Set this bit to stop the output of BCK signal and WS signal when TX FIFO is empty. 8 1 read-write TX_ZEROS_RM_EN Reserved. 9 1 read-write PD_CONF I2S power-down configuration register 0xA4 0x20 0x0000002A FIFO_FORCE_PD Force FIFO power-down. 0 1 read-write FIFO_FORCE_PU Force FIFO power-up. 1 1 read-write PLC_MEM_FORCE_PD Force I2S memory power-down. 2 1 read-write PLC_MEM_FORCE_PU Force I2S memory power-up. 3 1 read-write DMA_RAM_FORCE_PD Force DMA FIFO power-down. 4 1 read-write DMA_RAM_FORCE_PU Force DMA FIFO power-up. 5 1 read-write DMA_RAM_CLK_FO Set this bit to force on DMA RAM clock. 6 1 read-write CONF2 I2S configuration register 2 0xA8 0x20 CAMERA_EN Set this bit to enable camera mode. 0 1 read-write LCD_TX_WRX2_EN LCD WR double for one datum. 1 1 read-write LCD_TX_SDX2_EN Set this bit to duplicate data pairs (Frame Form 2) in LCD mode. 2 1 read-write DATA_ENABLE_TEST_EN for debug camera mode enable 3 1 read-write DATA_ENABLE for debug camera mode enable 4 1 read-write LCD_EN Set this bit to enable LCD mode. 5 1 read-write EXT_ADC_START_EN Set this bit to enable the function that ADC mode is triggered by external signal. 6 1 read-write INTER_VALID_EN Set this bit to enable camera VGA reducing-resolution mode: only receive two consecutive cycle data in four consecutive clocks. 7 1 read-write CAM_SYNC_FIFO_RESET Set this bit to reset FIFO in camera mode. 8 1 read-write CAM_CLK_LOOPBACK Set this bit to loopback PCLK from I2S0I_WS_out. 9 1 read-write VSYNC_FILTER_EN Set this bit to enable I2S VSYNC filter function. 10 1 read-write VSYNC_FILTER_THRES Configure the I2S VSYNC filter threshold value. 11 3 read-write CLKM_CONF I2S module clock configuration register 0xAC 0x20 0x00000004 CLKM_DIV_NUM Integral I2S clock divider value. 0 8 read-write CLKM_DIV_B Fractional clock divider numerator value. 8 6 read-write CLKM_DIV_A Fractional clock divider denominator value. 14 6 read-write CLK_EN Set this bit to enable clock gate. 20 1 read-write CLK_SEL Set this bit to select I2S module clock source. 0: No clock. 1: APLL_CLK. 2: PLL_160M_CLK. 3: No clock. 21 2 read-write SAMPLE_RATE_CONF I2S sample rate register 0xB0 0x20 0x00410186 TX_BCK_DIV_NUM Bit clock configuration bits in transmitter mode. 0 6 read-write RX_BCK_DIV_NUM Bit clock configuration bits in receiver mode. 6 6 read-write TX_BITS_MOD Set the bits to configure bit length of I2S transmitter channel, the value of which can only be 8, 16, 24 and 32. 12 6 read-write RX_BITS_MOD Set the bits to configure bit length of I2S receiver channel, the value of which can only be 8, 16, 24 and 32. 18 6 read-write STATE I2S TX status register 0xBC 0x20 0x00000001 TX_IDLE 1: I2S TX is in idle state. 0: I2S TX is at work. 0 1 read-only DATE Version control register 0xFC 0x20 0x19052500 DATE Version control register 0 32 read-write INTERRUPT_CORE0 Interrupt Controller (Core 0) INTERRUPT_CORE0 0x3F4C2000 0x0 0x190 registers WIFI_MAC 0 WIFI_NMI 1 WIFI_PWR 2 WIFI_BB 3 BT_MAC 4 BT_BB 5 BT_BB_NMI 6 RWBT 7 RWBLE 8 RWBT_NMI 9 RWBLE_NMI 10 SLC0 11 SLC1 12 FROM_CPU_INTR0 28 FROM_CPU_INTR1 29 FROM_CPU_INTR2 30 FROM_CPU_INTR3 31 SDIO_HOST 40 WDT 59 CACHE_IA 70 ICACHE_PRELOAD 87 DCACHE_PRELOAD 88 CPU_PERI_ERR 91 APB_PERI_ERR 92 DCACHE_SYNC 93 ICACHE_SYNC 94 PRO_MAC_INTR_MAP MAC_INTR interrupt configuration register 0x0 0x20 0x00000010 PRO_MAC_INTR_MAP This register is used to map MAC_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_MAC_NMI_MAP MAC_NMI interrupt configuration register 0x4 0x20 0x00000010 PRO_MAC_NMI_MAP This register is used to map MAC_NMI interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_PWR_INTR_MAP PWR_INTR interrupt configuration register 0x8 0x20 0x00000010 PRO_PWR_INTR_MAP This register is used to map PWR_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_BB_INT_MAP BB_INT interrupt configuration register 0xC 0x20 0x00000010 PRO_BB_INT_MAP This register is used to map BB_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_BT_MAC_INT_MAP BT_MAC_INT interrupt configuration register 0x10 0x20 0x00000010 PRO_BT_MAC_INT_MAP This register is used to map BT_MAC_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_BT_BB_INT_MAP BT_BB_INT interrupt configuration register 0x14 0x20 0x00000010 PRO_BT_BB_INT_MAP This register is used to map BT_BB_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_BT_BB_NMI_MAP BT_BB_NMI interrupt configuration register 0x18 0x20 0x00000010 PRO_BT_BB_NMI_MAP This register is used to map BT_BB_NMI interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_RWBT_IRQ_MAP RWBT_IRQ interrupt configuration register 0x1C 0x20 0x00000010 PRO_RWBT_IRQ_MAP This register is used to map RWBT_IRQ interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_RWBLE_IRQ_MAP RWBLE_IRQ interrupt configuration register 0x20 0x20 0x00000010 PRO_RWBLE_IRQ_MAP This register is used to map RWBLE_IRQ interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_RWBT_NMI_MAP RWBT_NMI interrupt configuration register 0x24 0x20 0x00000010 PRO_RWBT_NMI_MAP This register is used to map RWBT_NMI interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_RWBLE_NMI_MAP RWBLE_NMI interrupt configuration register 0x28 0x20 0x00000010 PRO_RWBLE_NMI_MAP This register is used to map RWBLE_NMI interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_SLC0_INTR_MAP SLC0_INTR interrupt configuration register 0x2C 0x20 0x00000010 PRO_SLC0_INTR_MAP This register is used to map SLC0_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_SLC1_INTR_MAP SLC1_INTR interrupt configuration register 0x30 0x20 0x00000010 PRO_SLC1_INTR_MAP This register is used to map SLC1_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_UHCI0_INTR_MAP UHCI0_INTR interrupt configuration register 0x34 0x20 0x00000010 PRO_UHCI0_INTR_MAP This register is used to map UHCI0_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_UHCI1_INTR_MAP UHCI1_INTR interrupt configuration register 0x38 0x20 0x00000010 PRO_UHCI1_INTR_MAP This register is used to map UHCI1_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_TG_T0_LEVEL_INT_MAP TG_T0_LEVEL_INT interrupt configuration register 0x3C 0x20 0x00000010 PRO_TG_T0_LEVEL_INT_MAP This register is used to map TG_T0_LEVEL_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_TG_T1_LEVEL_INT_MAP TG_T1_LEVEL_INT interrupt configuration register 0x40 0x20 0x00000010 PRO_TG_T1_LEVEL_INT_MAP This register is used to map TG_T1_LEVEL_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_TG_WDT_LEVEL_INT_MAP TG_WDT_LEVEL_INT interrupt configuration register 0x44 0x20 0x00000010 PRO_TG_WDT_LEVEL_INT_MAP This register is used to map TG_WDT_LEVEL_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_TG_LACT_LEVEL_INT_MAP TG_LACT_LEVEL_INT interrupt configuration register 0x48 0x20 0x00000010 PRO_TG_LACT_LEVEL_INT_MAP This register is used to map TG_LACT_LEVEL_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_TG1_T0_LEVEL_INT_MAP TG1_T0_LEVEL_INT interrupt configuration register 0x4C 0x20 0x00000010 PRO_TG1_T0_LEVEL_INT_MAP This register is used to map TG1_T0_LEVEL_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_TG1_T1_LEVEL_INT_MAP TG1_T1_LEVEL_INT interrupt configuration register 0x50 0x20 0x00000010 PRO_TG1_T1_LEVEL_INT_MAP This register is used to map TG1_T1_LEVEL_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_TG1_WDT_LEVEL_INT_MAP TG1_WDT_LEVEL_INT interrupt configuration register 0x54 0x20 0x00000010 PRO_TG1_WDT_LEVEL_INT_MAP This register is used to map TG1_WDT_LEVEL_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_TG1_LACT_LEVEL_INT_MAP TG1_LACT_LEVEL_INT interrupt configuration register 0x58 0x20 0x00000010 PRO_TG1_LACT_LEVEL_INT_MAP This register is used to map TG1_LACT_LEVEL_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_GPIO_INTERRUPT_PRO_MAP GPIO_INTERRUPT_PRO interrupt configuration register 0x5C 0x20 0x00000010 PRO_GPIO_INTERRUPT_PRO_MAP This register is used to map GPIO_INTERRUPT_PRO interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_GPIO_INTERRUPT_PRO_NMI_MAP GPIO_INTERRUPT_PRO_NMI interrupt configuration register 0x60 0x20 0x00000010 PRO_GPIO_INTERRUPT_PRO_NMI_MAP This register is used to map GPIO_INTERRUPT_PRO_NMI interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_GPIO_INTERRUPT_APP_MAP GPIO_INTERRUPT_APP interrupt configuration register 0x64 0x20 0x00000010 PRO_GPIO_INTERRUPT_APP_MAP This register is used to map GPIO_INTERRUPT_APP interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_GPIO_INTERRUPT_APP_NMI_MAP GPIO_INTERRUPT_APP_NMI interrupt configuration register 0x68 0x20 0x00000010 PRO_GPIO_INTERRUPT_APP_NMI_MAP This register is used to map GPIO_INTERRUPT_APP_NMI interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_DEDICATED_GPIO_IN_INTR_MAP DEDICATED_GPIO_IN_INTR interrupt configuration register 0x6C 0x20 0x00000010 PRO_DEDICATED_GPIO_IN_INTR_MAP This register is used to map DEDICATED_GPIO_IN_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_CPU_INTR_FROM_CPU_0_MAP CPU_INTR_FROM_CPU_0 interrupt configuration register 0x70 0x20 0x00000010 PRO_CPU_INTR_FROM_CPU_0_MAP This register is used to map CPU_INTR_FROM_CPU_0 interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_CPU_INTR_FROM_CPU_1_MAP CPU_INTR_FROM_CPU_1 interrupt configuration register 0x74 0x20 0x00000010 PRO_CPU_INTR_FROM_CPU_1_MAP This register is used to map CPU_INTR_FROM_CPU_1 interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_CPU_INTR_FROM_CPU_2_MAP CPU_INTR_FROM_CPU_2 interrupt configuration register 0x78 0x20 0x00000010 PRO_CPU_INTR_FROM_CPU_2_MAP This register is used to map CPU_INTR_FROM_CPU_2 interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_CPU_INTR_FROM_CPU_3_MAP CPU_INTR_FROM_CPU_3 interrupt configuration register 0x7C 0x20 0x00000010 PRO_CPU_INTR_FROM_CPU_3_MAP This register is used to map CPU_INTR_FROM_CPU_3 interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_SPI_INTR_1_MAP SPI_INTR_1 interrupt configuration register 0x80 0x20 0x00000010 PRO_SPI_INTR_1_MAP This register is used to map SPI_INTR_1 interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_SPI_INTR_2_MAP SPI_INTR_2 interrupt configuration register 0x84 0x20 0x00000010 PRO_SPI_INTR_2_MAP This register is used to map SPI_INTR_2 interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_SPI_INTR_3_MAP SPI_INTR_3 interrupt configuration register 0x88 0x20 0x00000010 PRO_SPI_INTR_3_MAP This register is used to map SPI_INTR_3 interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_I2S0_INT_MAP I2S0_INT interrupt configuration register 0x8C 0x20 0x00000010 PRO_I2S0_INT_MAP This register is used to map I2S0_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_I2S1_INT_MAP I2S1_INT interrupt configuration register 0x90 0x20 0x00000010 PRO_I2S1_INT_MAP This register is used to map I2S1_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_UART_INTR_MAP UART_INT interrupt configuration register 0x94 0x20 0x00000010 PRO_UART_INTR_MAP This register is used to map UART_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_UART1_INTR_MAP UART1_INT interrupt configuration register 0x98 0x20 0x00000010 PRO_UART1_INTR_MAP This register is used to map UART1_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_UART2_INTR_MAP UART2_INT interrupt configuration register 0x9C 0x20 0x00000010 PRO_UART2_INTR_MAP This register is used to map UART2_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_SDIO_HOST_INTERRUPT_MAP SDIO_HOST_INTERRUPT configuration register 0xA0 0x20 0x00000010 PRO_SDIO_HOST_INTERRUPT_MAP This register is used to map SDIO_HOST_INTERRUPT signal to one of the CPU interrupts. 0 5 read-write PRO_PWM0_INTR_MAP PWM0_INTR interrupt configuration register 0xA4 0x20 0x00000010 PRO_PWM0_INTR_MAP This register is used to map PWM0_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_PWM1_INTR_MAP PWM1_INTR interrupt configuration register 0xA8 0x20 0x00000010 PRO_PWM1_INTR_MAP This register is used to map PWM1_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_PWM2_INTR_MAP PWM2_INTR interrupt configuration register 0xAC 0x20 0x00000010 PRO_PWM2_INTR_MAP This register is used to map PWM2_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_PWM3_INTR_MAP PWM3_INTR interrupt configuration register 0xB0 0x20 0x00000010 PRO_PWM3_INTR_MAP This register is used to map PWM3_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_LEDC_INT_MAP LEDC_INTR interrupt configuration register 0xB4 0x20 0x00000010 PRO_LEDC_INT_MAP This register is used to map LEDC_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_EFUSE_INT_MAP EFUSE_INT interrupt configuration register 0xB8 0x20 0x00000010 PRO_EFUSE_INT_MAP This register is used to map EFUSE_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_CAN_INT_MAP CAN_INT interrupt configuration register 0xBC 0x20 0x00000010 PRO_CAN_INT_MAP This register is used to map CAN_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_USB_INTR_MAP USB_INT interrupt configuration register 0xC0 0x20 0x00000010 PRO_USB_INTR_MAP This register is used to map USB_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_RTC_CORE_INTR_MAP RTC_CORE_INTR interrupt configuration register 0xC4 0x20 0x00000010 PRO_RTC_CORE_INTR_MAP This register is used to map RTC_CORE_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_RMT_INTR_MAP RMT_INTR interrupt configuration register 0xC8 0x20 0x00000010 PRO_RMT_INTR_MAP This register is used to map RMT_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_PCNT_INTR_MAP PCNT_INTR interrupt configuration register 0xCC 0x20 0x00000010 PRO_PCNT_INTR_MAP This register is used to map PCNT_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_I2C_EXT0_INTR_MAP I2C_EXT0_INTR interrupt configuration register 0xD0 0x20 0x00000010 PRO_I2C_EXT0_INTR_MAP This register is used to map I2C_EXT0_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_I2C_EXT1_INTR_MAP I2C_EXT1_INTR interrupt configuration register 0xD4 0x20 0x00000010 PRO_I2C_EXT1_INTR_MAP This register is used to map I2C_EXT1_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_RSA_INTR_MAP RSA_INTR interrupt configuration register 0xD8 0x20 0x00000010 PRO_RSA_INTR_MAP This register is used to map RSA_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_SHA_INTR_MAP SHA_INTR interrupt configuration register 0xDC 0x20 0x00000010 PRO_SHA_INTR_MAP This register is used to map SHA_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_AES_INTR_MAP AES_INTR interrupt configuration register 0xE0 0x20 0x00000010 PRO_AES_INTR_MAP This register is used to map AES_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_SPI2_DMA_INT_MAP SPI2_DMA_INT interrupt configuration register 0xE4 0x20 0x00000010 PRO_SPI2_DMA_INT_MAP This register is used to map AES_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_SPI3_DMA_INT_MAP SPI3_DMA_INT interrupt configuration register 0xE8 0x20 0x00000010 PRO_SPI3_DMA_INT_MAP This register is used to map SPI3_DMA_INT dma interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_WDG_INT_MAP WDG_INT interrupt configuration register 0xEC 0x20 0x00000010 PRO_WDG_INT_MAP This register is used to map WDG_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_TIMER_INT1_MAP TIMER_INT1 interrupt configuration register 0xF0 0x20 0x00000010 PRO_TIMER_INT1_MAP This register is used to map TIMER_INT1 interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_TIMER_INT2_MAP TIMER_INT2 interrupt configuration register 0xF4 0x20 0x00000010 PRO_TIMER_INT2_MAP This register is used to map TIMER_INT2 interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_TG_T0_EDGE_INT_MAP TG_T0_EDGE_INT interrupt configuration register 0xF8 0x20 0x00000010 PRO_TG_T0_EDGE_INT_MAP This register is used to map TG_T0_EDGE_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_TG_T1_EDGE_INT_MAP TG_T1_EDGE_INT interrupt configuration register 0xFC 0x20 0x00000010 PRO_TG_T1_EDGE_INT_MAP This register is used to map TG_T1_EDGE_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_TG_WDT_EDGE_INT_MAP TG_WDT_EDGE_INT interrupt configuration register 0x100 0x20 0x00000010 PRO_TG_WDT_EDGE_INT_MAP This register is used to map TG_WDT_EDGE_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_TG_LACT_EDGE_INT_MAP TG_LACT_EDGE_INT interrupt configuration register 0x104 0x20 0x00000010 PRO_TG_LACT_EDGE_INT_MAP This register is used to map TG_LACT_EDGE_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_TG1_T0_EDGE_INT_MAP TG1_T0_EDGE_INT interrupt configuration register 0x108 0x20 0x00000010 PRO_TG1_T0_EDGE_INT_MAP This register is used to map TG1_T0_EDGE_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_TG1_T1_EDGE_INT_MAP TG1_T1_EDGE_INT interrupt configuration register 0x10C 0x20 0x00000010 PRO_TG1_T1_EDGE_INT_MAP This register is used to map TG1_T1_EDGE_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_TG1_WDT_EDGE_INT_MAP TG1_WDT_EDGE_INT interrupt configuration register 0x110 0x20 0x00000010 PRO_TG1_WDT_EDGE_INT_MAP This register is used to map TG1_WDT_EDGE_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_TG1_LACT_EDGE_INT_MAP TG1_LACT_EDGE_INT interrupt configuration register 0x114 0x20 0x00000010 PRO_TG1_LACT_EDGE_INT_MAP This register is used to map TG1_LACT_EDGE_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_CACHE_IA_INT_MAP CACHE_IA_INT interrupt configuration register 0x118 0x20 0x00000010 PRO_CACHE_IA_INT_MAP This register is used to map CACHE_IA_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_SYSTIMER_TARGET0_INT_MAP SYSTIMER_TARGET0_INT interrupt configuration register 0x11C 0x20 0x00000010 PRO_SYSTIMER_TARGET0_INT_MAP This register is used to map SYSTIMER_TARGET0_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_SYSTIMER_TARGET1_INT_MAP SYSTIMER_TARGET1_INT interrupt configuration register 0x120 0x20 0x00000010 PRO_SYSTIMER_TARGET1_INT_MAP This register is used to map SYSTIMER_TARGET1_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_SYSTIMER_TARGET2_INT_MAP SYSTIMER_TARGET2_INT interrupt configuration register 0x124 0x20 0x00000010 PRO_SYSTIMER_TARGET2_INT_MAP This register is used to map SYSTIMER_TARGET2_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_ASSIST_DEBUG_INTR_MAP ASSIST_DEBUG_INTR interrupt configuration register 0x128 0x20 0x00000010 PRO_ASSIST_DEBUG_INTR_MAP This register is used to map ASSIST_DEBUG_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_PMS_PRO_IRAM0_ILG_INTR_MAP PMS_PRO_IRAM0_ILG interrupt configuration register 0x12C 0x20 0x00000010 PRO_PMS_PRO_IRAM0_ILG_INTR_MAP This register is used to map PMS_PRO_IRAM0_ILG interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_PMS_PRO_DRAM0_ILG_INTR_MAP PMS_PRO_DRAM0_ILG interrupt configuration register 0x130 0x20 0x00000010 PRO_PMS_PRO_DRAM0_ILG_INTR_MAP This register is used to map PMS_PRO_DRAM0_ILG interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_PMS_PRO_DPORT_ILG_INTR_MAP PMS_PRO_DPORT_ILG interrupt configuration register 0x134 0x20 0x00000010 PRO_PMS_PRO_DPORT_ILG_INTR_MAP This register is used to map PMS_PRO_DPORT_ILG interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_PMS_PRO_AHB_ILG_INTR_MAP PMS_PRO_AHB_ILG interrupt configuration register 0x138 0x20 0x00000010 PRO_PMS_PRO_AHB_ILG_INTR_MAP This register is used to map PMS_PRO_AHB_ILG interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_PMS_PRO_CACHE_ILG_INTR_MAP PMS_PRO_CACHE_ILG interrupt configuration register 0x13C 0x20 0x00000010 PRO_PMS_PRO_CACHE_ILG_INTR_MAP This register is used to map PMS_PRO_CACHE_ILG interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_PMS_DMA_APB_I_ILG_INTR_MAP PMS_DMA_APB_I_ILG interrupt configuration register 0x140 0x20 0x00000010 PRO_PMS_DMA_APB_I_ILG_INTR_MAP This register is used to map PMS_DMA_APB_I_ILG interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_PMS_DMA_RX_I_ILG_INTR_MAP PMS_DMA_RX_I_ILG interrupt configuration register 0x144 0x20 0x00000010 PRO_PMS_DMA_RX_I_ILG_INTR_MAP This register is used to map PMS_DMA_RX_I_ILG interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_PMS_DMA_TX_I_ILG_INTR_MAP PMS_DMA_TX_I_ILG interrupt configuration register 0x148 0x20 0x00000010 PRO_PMS_DMA_TX_I_ILG_INTR_MAP This register is used to map PMS_DMA_TX_I_ILG interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_SPI_MEM_REJECT_INTR_MAP SPI_MEM_REJECT_INTR interrupt configuration register 0x14C 0x20 0x00000010 PRO_SPI_MEM_REJECT_INTR_MAP This register is used to map SPI_MEM_REJECT_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_DMA_COPY_INTR_MAP DMA_COPY_INTR interrupt configuration register 0x150 0x20 0x00000010 PRO_DMA_COPY_INTR_MAP This register is used to map DMA_COPY_INTR interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_SPI4_DMA_INT_MAP SPI4_DMA_INT interrupt configuration register 0x154 0x20 0x00000010 PRO_SPI4_DMA_INT_MAP This register is used to map SPI4_DMA_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_SPI_INTR_4_MAP SPI_INTR_4 interrupt configuration register 0x158 0x20 0x00000010 PRO_SPI_INTR_4_MAP This register is used to map SPI_INTR_4 interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_DCACHE_PRELOAD_INT_MAP DCACHE_PRELOAD_INT interrupt configuration register 0x15C 0x20 0x00000010 PRO_DCACHE_PRELOAD_INT_MAP This register is used to map DCACHE_PRELOAD_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_ICACHE_PRELOAD_INT_MAP ICACHE_PRELOAD_INT interrupt configuration register 0x160 0x20 0x00000010 PRO_ICACHE_PRELOAD_INT_MAP This register is used to map ICACHE_PRELOAD_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_APB_ADC_INT_MAP APB_ADC_INT interrupt configuration register 0x164 0x20 0x00000010 PRO_APB_ADC_INT_MAP This register is used to map APB_ADC_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_CRYPTO_DMA_INT_MAP CRYPTO_DMA_INT interrupt configuration register 0x168 0x20 0x00000010 PRO_CRYPTO_DMA_INT_MAP This register is used to map CRYPTO_DMA_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_CPU_PERI_ERROR_INT_MAP CPU_PERI_ERROR_INT interrupt configuration register 0x16C 0x20 0x00000010 PRO_CPU_PERI_ERROR_INT_MAP This register is used to map CPU_PERI_ERROR_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_APB_PERI_ERROR_INT_MAP APB_PERI_ERROR_INT interrupt configuration register 0x170 0x20 0x00000010 PRO_APB_PERI_ERROR_INT_MAP This register is used to map APB_PERI_ERROR_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_DCACHE_SYNC_INT_MAP DCACHE_SYNC_INT interrupt configuration register 0x174 0x20 0x00000010 PRO_DCACHE_SYNC_INT_MAP This register is used to map DCACHE_SYNC_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_ICACHE_SYNC_INT_MAP ICACHE_SYNC_INT interrupt configuration register 0x178 0x20 0x00000010 PRO_ICACHE_SYNC_INT_MAP This register is used to map ICACHE_SYNC_INT interrupt signal to one of the CPU interrupts. 0 5 read-write PRO_INTR_STATUS_0 Interrupt status register 0 0x17C 0x20 PRO_INTR_STATUS_0 This register stores the status of the first 32 input interrupt sources. 0 32 read-only PRO_INTR_STATUS_1 Interrupt status register 1 0x180 0x20 PRO_INTR_STATUS_1 This register stores the status of the second 32 input interrupt sources. 0 32 read-only PRO_INTR_STATUS_2 Interrupt status register 2 0x184 0x20 PRO_INTR_STATUS_2 This register stores the status of the last 31 input interrupt sources. 0 32 read-only CLOCK_GATE NMI interrupt signals mask register 0x188 0x20 0x00000001 CLK_EN This bit is used to enable or disable the clock of interrupt matrix. 1: enable the clock. 0: disable the clock. 0 1 read-write PRO_NMI_MASK_HW This bit is used to disable all NMI interrupt signals to CPU. 1 1 read-write REG_DATE Version control register 0xFFC 0x20 0x01904180 INTERRUPT_REG_DATE This is the version register. 0 28 read-write IO_MUX Input/Output Multiplexer IO_MUX 0x3F409000 0x0 0xB4 registers PIN_CTRL Clock output configuration register 0x0 0x20 0x000027FF PIN_CLK_OUT1 Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT1. 15: disabled. 0 4 read-write PIN_CLK_OUT2 Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT2. 15: disabled. 4 4 read-write PIN_CLK_OUT3 Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT3. 15: disabled. 8 4 read-write SWITCH_PRT_NUM IO pin power switch delay, delay unit is one APB clock. 12 3 read-write PAD_POWER_CTRL Select power voltage for GPIO33 ~ GPIO37. 1: select VDD_SPI 1.8 V. 0: select VDD3P3_CPU 3.3 V. 15 1 read-write GPIO0 Configuration register for pin GPIO0 0x4 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO1 Configuration register for pin GPIO1 0x8 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO2 Configuration register for pin GPIO2 0xC 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO3 Configuration register for pin GPIO3 0x10 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO4 Configuration register for pin GPIO4 0x14 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO5 Configuration register for pin GPIO5 0x18 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO6 Configuration register for pin GPIO6 0x1C 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO7 Configuration register for pin GPIO7 0x20 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO8 Configuration register for pin GPIO8 0x24 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO9 Configuration register for pin GPIO9 0x28 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO10 Configuration register for pin GPIO10 0x2C 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO11 Configuration register for pin GPIO11 0x30 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO12 Configuration register for pin GPIO12 0x34 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO13 Configuration register for pin GPIO13 0x38 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO14 Configuration register for pin GPIO14 0x3C 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO19 Configuration register for pin GPIO19 0x50 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO20 Configuration register for pin GPIO20 0x54 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO21 Configuration register for pin GPIO21 0x58 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO33 Configuration register for pin GPIO33 0x88 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO34 Configuration register for pin GPIO34 0x8C 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO35 Configuration register for pin GPIO35 0x90 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO36 Configuration register for pin GPIO36 0x94 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO37 Configuration register for pin GPIO37 0x98 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO38 Configuration register for pin GPIO38 0x9C 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO45 Configuration register for pin GPIO45 0xB8 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO46 Configuration register for pin GPIO46 0xBC 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write DATE Version control register 0xFC 0x20 0x01907160 VERSION Version control register 0 28 read-write GPIO15 Configuration register for pin GPIO15 0x40 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO16 Configuration register for pin GPIO16 0x44 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO17 Configuration register for pin GPIO17 0x48 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO18 Configuration register for pin GPIO18 0x4C 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO26 Configuration register for pin GPIO26 0x6C 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO27 Configuration register for pin GPIO27 0x70 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO28 Configuration register for pin GPIO28 0x74 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO29 Configuration register for pin GPIO29 0x78 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO30 Configuration register for pin GPIO30 0x7C 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO31 Configuration register for pin GPIO31 0x80 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO32 Configuration register for pin GPIO32 0x84 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO39 Configuration register for pin GPIO39 0xA0 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO40 Configuration register for pin GPIO40 0xA4 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO41 Configuration register for pin GPIO41 0xA8 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO42 Configuration register for pin GPIO42 0xAC 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO43 Configuration register for pin GPIO43 0xB0 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write GPIO44 Configuration register for pin GPIO44 0xB4 0x20 0x00000B00 MCU_OE Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. 4 1 read-write FUN_WPD Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pin. 1: Input enabled. 0: Input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. 15 1 read-write LEDC LED Control PWM (Pulse Width Modulation) LEDC 0x3F419000 0x0 0xD8 registers LEDC 45 TIMER1 60 TIMER2 61 8 0x14 CH%s_CONF0 Configuration register 0 for channel %s 0x0 0x20 TIMER_SEL This field is used to select one of timers for channel %s. 0: select timer 0. 1: select timer 1. 2: select timer 2. 3: select timer 3. 0 2 read-write SIG_OUT_EN Set this bit to enable signal output on channel %s. 2 1 read-write IDLE_LV This bit is used to control the output value when channel %s is inactive. 3 1 read-write PARA_UP This bit is used to update register LEDC_CH%s_HPOINT and LEDC_CH%s_DUTY for channel %s. 4 1 write-only OVF_NUM This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. 5 10 read-write OVF_CNT_EN This bit is used to enable the ovf_cnt of channel %s. 15 1 read-write OVF_CNT_RESET Set this bit to reset the ovf_cnt of channel %s. 16 1 write-only OVF_CNT_RESET_ST This is the status bit of LEDC_OVF_CNT_RESET_CH%s. 17 1 read-only 8 0x14 CH%s_HPOINT High point register for channel %s 0x4 0x20 HPOINT The output value changes to high when the selected timers has reached the value specified by this register. 0 14 read-write 8 0x14 CH%s_DUTY Initial duty cycle for channel %s 0x8 0x20 DUTY This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint. 0 19 read-write 8 0x14 CH%s_CONF1 Configuration register 1 for channel %s 0xC 0x20 0x40000000 DUTY_SCALE This register is used to configure the changing step scale of duty on channel %s. 0 10 read-write DUTY_CYCLE The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s. 10 10 read-write DUTY_NUM This register is used to control the number of times the duty cycle will be changed. 20 10 read-write DUTY_INC This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase. 0: Decrease. 30 1 read-write DUTY_START Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. 31 1 read-write 8 0x14 CH%s_DUTY_R Current duty cycle for channel %s 0x10 0x20 DUTY_R This register stores the current duty of output signal on channel %s. 0 19 read-only 4 0x8 TIMER%s_CONF Timer %s configuration 0xA0 0x20 0x00800000 DUTY_RES This register is used to control the range of the counter in timer %s. 0 4 read-write CLK_DIV This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part. 4 18 read-write PAUSE This bit is used to suspend the counter in timer %s. 22 1 read-write RST This bit is used to reset timer %s. The counter will show 0 after reset. 23 1 read-write TICK_SEL This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. 0: LEDC_PWM_CLK. 1: REF_TICK. 24 1 read-write PARA_UP Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. 25 1 write-only 4 0x8 TIMER%s_VALUE Timer %s current counter value 0xA4 0x20 CNT This register stores the current counter value of timer %s. 0 14 read-only INT_RAW Raw interrupt status 0xC0 0x20 TIMER0_OVF_INT_RAW Triggered when the timer0 has reached its maximum counter value. 0 1 read-only TIMER1_OVF_INT_RAW Triggered when the timer1 has reached its maximum counter value. 1 1 read-only TIMER2_OVF_INT_RAW Triggered when the timer2 has reached its maximum counter value. 2 1 read-only TIMER3_OVF_INT_RAW Triggered when the timer3 has reached its maximum counter value. 3 1 read-only DUTY_CHNG_END_CH0_INT_RAW Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. 4 1 read-only DUTY_CHNG_END_CH1_INT_RAW Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. 5 1 read-only DUTY_CHNG_END_CH2_INT_RAW Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. 6 1 read-only DUTY_CHNG_END_CH3_INT_RAW Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. 7 1 read-only DUTY_CHNG_END_CH4_INT_RAW Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. 8 1 read-only DUTY_CHNG_END_CH5_INT_RAW Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. 9 1 read-only DUTY_CHNG_END_CH6_INT_RAW Interrupt raw bit for channel 6. Triggered when the gradual change of duty has finished. 10 1 read-only DUTY_CHNG_END_CH7_INT_RAW Interrupt raw bit for channel 7. Triggered when the gradual change of duty has finished. 11 1 read-only OVF_CNT_CH0_INT_RAW Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. 12 1 read-only OVF_CNT_CH1_INT_RAW Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. 13 1 read-only OVF_CNT_CH2_INT_RAW Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. 14 1 read-only OVF_CNT_CH3_INT_RAW Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. 15 1 read-only OVF_CNT_CH4_INT_RAW Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. 16 1 read-only OVF_CNT_CH5_INT_RAW Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. 17 1 read-only OVF_CNT_CH6_INT_RAW Interrupt raw bit for channel 6. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. 18 1 read-only OVF_CNT_CH7_INT_RAW Interrupt raw bit for channel 7. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. 19 1 read-only INT_ST Masked interrupt status 0xC4 0x20 TIMER0_OVF_INT_ST This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. 0 1 read-only TIMER1_OVF_INT_ST This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. 1 1 read-only TIMER2_OVF_INT_ST This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. 2 1 read-only TIMER3_OVF_INT_ST This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. 3 1 read-only DUTY_CHNG_END_CH0_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1. 4 1 read-only DUTY_CHNG_END_CH1_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1. 5 1 read-only DUTY_CHNG_END_CH2_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1. 6 1 read-only DUTY_CHNG_END_CH3_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1. 7 1 read-only DUTY_CHNG_END_CH4_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1. 8 1 read-only DUTY_CHNG_END_CH5_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1. 9 1 read-only DUTY_CHNG_END_CH6_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt when LEDC_DUTY_CHNG_END_CH6_INT_ENAIS set to 1. 10 1 read-only DUTY_CHNG_END_CH7_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt when LEDC_DUTY_CHNG_END_CH7_INT_ENAIS set to 1. 11 1 read-only OVF_CNT_CH0_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. 12 1 read-only OVF_CNT_CH1_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. 13 1 read-only OVF_CNT_CH2_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. 14 1 read-only OVF_CNT_CH3_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. 15 1 read-only OVF_CNT_CH4_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. 16 1 read-only OVF_CNT_CH5_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. 17 1 read-only OVF_CNT_CH6_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH6_INT interrupt when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. 18 1 read-only OVF_CNT_CH7_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH7_INT interrupt when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. 19 1 read-only INT_ENA Interrupt enable bits 0xC8 0x20 TIMER0_OVF_INT_ENA The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. 0 1 read-write TIMER1_OVF_INT_ENA The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. 1 1 read-write TIMER2_OVF_INT_ENA The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. 2 1 read-write TIMER3_OVF_INT_ENA The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. 3 1 read-write DUTY_CHNG_END_CH0_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. 4 1 read-write DUTY_CHNG_END_CH1_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. 5 1 read-write DUTY_CHNG_END_CH2_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. 6 1 read-write DUTY_CHNG_END_CH3_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. 7 1 read-write DUTY_CHNG_END_CH4_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. 8 1 read-write DUTY_CHNG_END_CH5_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. 9 1 read-write DUTY_CHNG_END_CH6_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt. 10 1 read-write DUTY_CHNG_END_CH7_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt. 11 1 read-write OVF_CNT_CH0_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. 12 1 read-write OVF_CNT_CH1_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. 13 1 read-write OVF_CNT_CH2_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. 14 1 read-write OVF_CNT_CH3_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. 15 1 read-write OVF_CNT_CH4_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. 16 1 read-write OVF_CNT_CH5_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. 17 1 read-write OVF_CNT_CH6_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH6_INT interrupt. 18 1 read-write OVF_CNT_CH7_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH7_INT interrupt. 19 1 read-write INT_CLR Interrupt clear bits 0xCC 0x20 TIMER0_OVF_INT_CLR Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. 0 1 write-only TIMER1_OVF_INT_CLR Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. 1 1 write-only TIMER2_OVF_INT_CLR Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. 2 1 write-only TIMER3_OVF_INT_CLR Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. 3 1 write-only DUTY_CHNG_END_CH0_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. 4 1 write-only DUTY_CHNG_END_CH1_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. 5 1 write-only DUTY_CHNG_END_CH2_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. 6 1 write-only DUTY_CHNG_END_CH3_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. 7 1 write-only DUTY_CHNG_END_CH4_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. 8 1 write-only DUTY_CHNG_END_CH5_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. 9 1 write-only DUTY_CHNG_END_CH6_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH6_INT interrupt. 10 1 write-only DUTY_CHNG_END_CH7_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH7_INT interrupt. 11 1 write-only OVF_CNT_CH0_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. 12 1 write-only OVF_CNT_CH1_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. 13 1 write-only OVF_CNT_CH2_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. 14 1 write-only OVF_CNT_CH3_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. 15 1 write-only OVF_CNT_CH4_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. 16 1 write-only OVF_CNT_CH5_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. 17 1 write-only OVF_CNT_CH6_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH6_INT interrupt. 18 1 write-only OVF_CNT_CH7_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH7_INT interrupt. 19 1 write-only CONF Global ledc configuration register 0xD0 0x20 APB_CLK_SEL This bit is used to select clock source for the 4 timers . 1: APB_CLK. 2: RTC8M_CLK. 3: XTAL_CLK. 0 2 read-write CLK_EN This bit is used to control clock. 1: Force clock on for register. 0: Support clock only when application writes registers. 31 1 read-write DATE Version control register 0xFC 0x20 0x19072601 DATE This is the version control register. 0 32 read-write PCNT Pulse Count Controller PCNT 0x3F417000 0x0 0x68 registers PCNT 51 4 0xC U%s_CONF0 Configuration register 0 for unit %s 0x0 0x20 0x00003C10 FILTER_THRES This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled. 0 10 read-write FILTER_EN This is the enable bit for unit %s's input filter. 10 1 read-write THR_ZERO_EN This is the enable bit for unit %s's zero comparator. 11 1 read-write THR_H_LIM_EN This is the enable bit for unit %s's thr_h_lim comparator. 12 1 read-write THR_L_LIM_EN This is the enable bit for unit %s's thr_l_lim comparator. 13 1 read-write THR_THRES0_EN This is the enable bit for unit %s's thres0 comparator. 14 1 read-write THR_THRES1_EN This is the enable bit for unit %s's thres1 comparator. 15 1 read-write CH0_NEG_MODE This register sets the behavior when the signal input of channel 0 detects a negative edge. 1: Increase the counter. 2: Decrease the counter. 0, 3: No effect on counter. 16 2 read-write CH0_POS_MODE This register sets the behavior when the signal input of channel 0 detects a positive edge. 1: Increase the counter. 2: Decrease the counter. 0, 3: No effect on counter. 18 2 read-write CH0_HCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification. 20 2 read-write CH0_LCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification. 22 2 read-write CH1_NEG_MODE This register sets the behavior when the signal input of channel 1 detects a negative edge. 1: Increment the counter. 2: Decrement the counter. 0, 3: No effect on counter. 24 2 read-write CH1_POS_MODE This register sets the behavior when the signal input of channel 1 detects a positive edge. 1: Increment the counter. 2: Decrement the counter. 0, 3: No effect on counter. 26 2 read-write CH1_HCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification. 28 2 read-write CH1_LCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification. 30 2 read-write 4 0xC U%s_CONF1 Configuration register 1 for unit %s 0x4 0x20 CNT_THRES0 This register is used to configure the thres0 value for unit %s. 0 16 read-write CNT_THRES1 This register is used to configure the thres1 value for unit %s. 16 16 read-write 4 0xC U%s_CONF2 Configuration register 2 for unit %s 0x8 0x20 CNT_H_LIM This register is used to configure the thr_h_lim value for unit %s. 0 16 read-write CNT_L_LIM This register is used to configure the thr_l_lim value for unit %s. 16 16 read-write 4 0x4 U%s_CNT Counter value for unit %s 0x30 0x20 CNT This register stores the current pulse count value for unit %s. 0 16 read-only INT_RAW Interrupt raw status register 0x40 0x20 CNT_THR_EVENT_U0 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-only CNT_THR_EVENT_U1 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-only CNT_THR_EVENT_U2 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-only CNT_THR_EVENT_U3 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 read-only INT_ST Interrupt status register 0x44 0x20 CNT_THR_EVENT_U0 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-only CNT_THR_EVENT_U1 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-only CNT_THR_EVENT_U2 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-only CNT_THR_EVENT_U3 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 read-only INT_ENA Interrupt enable register 0x48 0x20 CNT_THR_EVENT_U0 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-write CNT_THR_EVENT_U1 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-write CNT_THR_EVENT_U2 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-write CNT_THR_EVENT_U3 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 read-write INT_CLR Interrupt clear register 0x4C 0x20 CNT_THR_EVENT_U0 Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 write-only CNT_THR_EVENT_U1 Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 write-only CNT_THR_EVENT_U2 Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 write-only CNT_THR_EVENT_U3 Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 write-only 4 0x4 U%s_STATUS PNCT UNIT%s status register 0x50 0x20 ZERO_MODE The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. 0 2 read-only THRES1 The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others. 2 1 read-only THRES0 The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others. 3 1 read-only L_LIM The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others. 4 1 read-only H_LIM The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others. 5 1 read-only ZERO The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others. 6 1 read-only CTRL Control register for all counters 0x60 0x20 0x00000055 CNT_RST_U0 Set this bit to clear unit 0's counter. 0 1 read-write CNT_PAUSE_U0 Set this bit to freeze unit 1's counter. 1 1 read-write CNT_RST_U1 Set this bit to clear unit 2's counter. 2 1 read-write CNT_PAUSE_U1 Set this bit to freeze unit 3's counter. 3 1 read-write CNT_RST_U2 Set this bit to clear unit 4's counter. 4 1 read-write CNT_PAUSE_U2 Set this bit to freeze unit 5's counter. 5 1 read-write CNT_RST_U3 Set this bit to clear unit 6's counter. 6 1 read-write CNT_PAUSE_U3 Set this bit to freeze unit 7's counter. 7 1 read-write CLK_EN The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application 16 1 read-write DATE PCNT version control register 0xFC 0x20 0x19072601 DATE This is the PCNT version control register. 0 32 read-write PMS Permissions Controller PMS 0x3F4C1000 0x0 0x10C registers PMS_PRO_IRAM0_ILG 75 PMS_PRO_DRAM0_ILG 76 PMS_PRO_DPORT_ILG 77 PMS_PRO_AHB_ILG 78 PMS_PRO_CACHE_ILG 79 PMS_DMA_APB_I_ILG 80 PMS_DMA_RX_I_ILG 81 PMS_DMA_TX_I_ILG 82 SDIO_0 SDIO permission control register 0. 0x0 0x20 SDIO_LOCK Lock register. Setting to 1 locks SDIO permission control registers. 0 1 read-write SDIO_1 SDIO permission control register 1. 0x4 0x20 SDIO_DISABLE Setting to 1 disables the SDIO function. 0 1 read-write MAC_DUMP_0 MAC dump permission control register 0. 0x8 0x20 MAC_DUMP_LOCK Lock register. Setting to 1 locks MAC dump permission control registers. 0 1 read-write MAC_DUMP_1 MAC dump permission control register 1. 0xC 0x20 0x000000E4 MAC_DUMP_CONNECT Configure MAC dump connection. 0 12 read-write PRO_IRAM0_0 IBUS permission control register 0. 0x10 0x20 PRO_IRAM0_LOCK Lock register. Setting to 1 locks IBUS permission control registers. 0 1 read-write PRO_IRAM0_1 IBUS permission control register 1. 0x14 0x20 0x00000FFF PRO_IRAM0_SRAM_0_F Setting to 1 grants IBUS permission to fetch SRAM Block 0. 0 1 read-write PRO_IRAM0_SRAM_0_R Setting to 1 grants IBUS permission to read SRAM Block 0. 1 1 read-write PRO_IRAM0_SRAM_0_W Setting to 1 grants IBUS permission to write SRAM Block 0. 2 1 read-write PRO_IRAM0_SRAM_1_F Setting to 1 grants IBUS permission to fetch SRAM Block 1. 3 1 read-write PRO_IRAM0_SRAM_1_R Setting to 1 grants IBUS permission to read SRAM Block 1. 4 1 read-write PRO_IRAM0_SRAM_1_W Setting to 1 grants IBUS permission to write SRAM Block 1. 5 1 read-write PRO_IRAM0_SRAM_2_F Setting to 1 grants IBUS permission to fetch SRAM Block 2. 6 1 read-write PRO_IRAM0_SRAM_2_R Setting to 1 grants IBUS permission to read SRAM Block 2. 7 1 read-write PRO_IRAM0_SRAM_2_W Setting to 1 grants IBUS permission to write SRAM Block 2. 8 1 read-write PRO_IRAM0_SRAM_3_F Setting to 1 grants IBUS permission to fetch SRAM Block 3. 9 1 read-write PRO_IRAM0_SRAM_3_R Setting to 1 grants IBUS permission to read SRAM Block 3. 10 1 read-write PRO_IRAM0_SRAM_3_W Setting to 1 grants IBUS permission to write SRAM Block 3. 11 1 read-write PRO_IRAM0_2 IBUS permission control register 2. 0x18 0x20 0x007E0000 PRO_IRAM0_SRAM_4_SPLTADDR Configure the split address of SRAM Block 4-21 for IBUS access. 0 17 read-write PRO_IRAM0_SRAM_4_L_F Setting to 1 grants IBUS permission to fetch SRAM Block 4-21 low address region. 17 1 read-write PRO_IRAM0_SRAM_4_L_R Setting to 1 grants IBUS permission to read SRAM Block 4-21 low address region. 18 1 read-write PRO_IRAM0_SRAM_4_L_W Setting to 1 grants IBUS permission to write SRAM Block 4-21 low address region. 19 1 read-write PRO_IRAM0_SRAM_4_H_F Setting to 1 grants IBUS permission to fetch SRAM Block 4-21 high address region. 20 1 read-write PRO_IRAM0_SRAM_4_H_R Setting to 1 grants IBUS permission to read SRAM Block 4-21 high address region. 21 1 read-write PRO_IRAM0_SRAM_4_H_W Setting to 1 grants IBUS permission to write SRAM Block 4-21 high address region. 22 1 read-write PRO_IRAM0_3 IBUS permission control register 3. 0x1C 0x20 0x0001F800 PRO_IRAM0_RTCFAST_SPLTADDR Configure the split address of RTC FAST for IBUS access. 0 11 read-write PRO_IRAM0_RTCFAST_L_F Setting to 1 grants IBUS permission to fetch RTC FAST low address region. 11 1 read-write PRO_IRAM0_RTCFAST_L_R Setting to 1 grants IBUS permission to read RTC FAST low address region. 12 1 read-write PRO_IRAM0_RTCFAST_L_W Setting to 1 grants IBUS permission to write RTC FAST low address region. 13 1 read-write PRO_IRAM0_RTCFAST_H_F Setting to 1 grants IBUS permission to fetch RTC FAST high address region. 14 1 read-write PRO_IRAM0_RTCFAST_H_R Setting to 1 grants IBUS permission to read RTC FAST high address region. 15 1 read-write PRO_IRAM0_RTCFAST_H_W Setting to 1 grants IBUS permission to write RTC FAST high address region. 16 1 read-write PRO_IRAM0_4 IBUS permission control register 4. 0x20 0x20 PRO_IRAM0_ILG_CLR The clear signal for IBUS access interrupt. 0 1 read-write PRO_IRAM0_ILG_EN The enable signal for IBUS access interrupt. 1 1 read-write PRO_IRAM0_ILG_INTR IBUS access interrupt signal. 2 1 read-only PRO_IRAM0_5 IBUS status register. 0x24 0x20 PRO_IRAM0_ILG_ST Record the illegitimate information of IBUS. [21:2]: store the bits [21:2] of IBUS address. [1]: 1 means data access, 0 means instruction access. [0]: 1 means write operation, 0 means read operation. 0 22 read-only PRO_DRAM0_0 DBUS permission control register 0. 0x28 0x20 PRO_DRAM0_LOCK Lock register. Setting to 1 locks DBUS0 permission control registers. 0 1 read-write PRO_DRAM0_1 DBUS permission control register 1. 0x2C 0x20 0x1E0000FF PRO_DRAM0_SRAM_0_R Setting to 1 grants DBUS0 permission to read SRAM Block 0. 0 1 read-write PRO_DRAM0_SRAM_0_W Setting to 1 grants DBUS0 permission to write SRAM Block 0. 1 1 read-write PRO_DRAM0_SRAM_1_R Setting to 1 grants DBUS0 permission to read SRAM Block 1. 2 1 read-write PRO_DRAM0_SRAM_1_W Setting to 1 grants DBUS0 permission to write SRAM Block 1. 3 1 read-write PRO_DRAM0_SRAM_2_R Setting to 1 grants DBUS0 permission to read SRAM Block 2. 4 1 read-write PRO_DRAM0_SRAM_2_W Setting to 1 grants DBUS0 permission to write SRAM Block 2. 5 1 read-write PRO_DRAM0_SRAM_3_R Setting to 1 grants DBUS0 permission to read SRAM Block 3. 6 1 read-write PRO_DRAM0_SRAM_3_W Setting to 1 grants DBUS0 permission to write SRAM Block 3. 7 1 read-write PRO_DRAM0_SRAM_4_SPLTADDR Configure the split address of SRAM Block 4-21 for DBUS0 access. 8 17 read-write PRO_DRAM0_SRAM_4_L_R Setting to 1 grants DBUS0 permission to read SRAM Block 4-21 low address region. 25 1 read-write PRO_DRAM0_SRAM_4_L_W Setting to 1 grants DBUS0 permission to write SRAM Block 4-21 low address region. 26 1 read-write PRO_DRAM0_SRAM_4_H_R Setting to 1 grants DBUS0 permission to read SRAM Block 4-21 high address region. 27 1 read-write PRO_DRAM0_SRAM_4_H_W Setting to 1 grants DBUS0 permission to write SRAM Block 4-21 high address region. 28 1 read-write PRO_DRAM0_2 DBUS permission control register 2. 0x30 0x20 0x00007800 PRO_DRAM0_RTCFAST_SPLTADDR Configure the split address of RTC FAST for DBUS0 access. 0 11 read-write PRO_DRAM0_RTCFAST_L_R Setting to 1 grants DBUS0 permission to read RTC FAST low address region. 11 1 read-write PRO_DRAM0_RTCFAST_L_W Setting to 1 grants DBUS0 permission to write RTC FAST low address region. 12 1 read-write PRO_DRAM0_RTCFAST_H_R Setting to 1 grants DBUS0 permission to read RTC FAST high address region. 13 1 read-write PRO_DRAM0_RTCFAST_H_W Setting to 1 grants DBUS0 permission to write RTC FAST high address region. 14 1 read-write PRO_DRAM0_3 DBUS permission control register 3. 0x34 0x20 PRO_DRAM0_ILG_CLR The clear signal for DBUS0 access interrupt. 0 1 read-write PRO_DRAM0_ILG_EN The enable signal for DBUS0 access interrupt. 1 1 read-write PRO_DRAM0_ILG_INTR DBUS0 access interrupt signal. 2 1 read-only PRO_DRAM0_4 DBUS status register. 0x38 0x20 PRO_DRAM0_ILG_ST Record the illegitimate information of DBUS. [25:6]: store the bits [21:2] of DBUS address. [5]: 1 means atomic access, 0 means nonatomic access. [4]: 1 means write operation, 0 means read operation. [3:0]: DBUS0 bus byte enables. 0 26 read-only PRO_DPORT_0 PeriBus1 permission control register 0. 0x3C 0x20 PRO_DPORT_LOCK Lock register. Setting to 1 locks PeriBus1 permission control registers. 0 1 read-write PRO_DPORT_1 PeriBus1 permission control register 1. 0x40 0x20 0x0000F000 PRO_DPORT_APB_PERIPHERAL_FORBID Setting to 1 denies PeriBus1 bus???s access to APB peripheral. 0 1 read-write PRO_DPORT_RTCSLOW_SPLTADDR Configure the split address of RTC FAST for PeriBus1 access. 1 11 read-write PRO_DPORT_RTCSLOW_L_R Setting to 1 grants PeriBus1 permission to read RTC FAST low address region. 12 1 read-write PRO_DPORT_RTCSLOW_L_W Setting to 1 grants PeriBus1 permission to write RTC FAST low address region. 13 1 read-write PRO_DPORT_RTCSLOW_H_R Setting to 1 grants PeriBus1 permission to read RTC FAST high address region. 14 1 read-write PRO_DPORT_RTCSLOW_H_W Setting to 1 grants PeriBus1 permission to write RTC FAST high address region. 15 1 read-write PRO_DPORT_RESERVE_FIFO_VALID Configure whether to enable read protection for user-configured FIFO address. 16 4 read-write PRO_DPORT_2 PeriBus1 permission control register 2. 0x44 0x20 PRO_DPORT_RESERVE_FIFO_0 Configure read-protection address 0. 0 18 read-write PRO_DPORT_3 PeriBus1 permission control register 3. 0x48 0x20 PRO_DPORT_RESERVE_FIFO_1 Configure read-protection address 1. 0 18 read-write PRO_DPORT_4 PeriBus1 permission control register 4. 0x4C 0x20 PRO_DPORT_RESERVE_FIFO_2 Configure read-protection address 2. 0 18 read-write PRO_DPORT_5 PeriBus1 permission control register 5. 0x50 0x20 PRO_DPORT_RESERVE_FIFO_3 Configure read-protection address 3. 0 18 read-write PRO_DPORT_6 PeriBus1 permission control register 6. 0x54 0x20 PRO_DPORT_ILG_CLR The clear signal for PeriBus1 access interrupt. 0 1 read-write PRO_DPORT_ILG_EN The enable signal for PeriBus1 access interrupt. 1 1 read-write PRO_DPORT_ILG_INTR PeriBus1 access interrupt signal. 2 1 read-only PRO_DPORT_7 PeriBus1 status register. 0x58 0x20 PRO_DPORT_ILG_ST Record the illegitimate information of PeriBus1. [25:6]: store the bits [21:2] of PeriBus1 address. [5]: 1 means atomic access, 0 means nonatomic access. [4]: if bits [31:22] of PeriBus1 address are 0xfd, then the bit value is 1, otherwise it is 0. [3:0]: PeriBus1 byte enables. 0 26 read-only PRO_AHB_0 PeriBus2 permission control register 0. 0x5C 0x20 PRO_AHB_LOCK Lock register. Setting to 1 locks PeriBus2 permission control registers. 0 1 read-write PRO_AHB_1 PeriBus2 permission control register 1. 0x60 0x20 0x0001F800 PRO_AHB_RTCSLOW_0_SPLTADDR Configure the split address of RTCSlow_0 for PeriBus2 access. 0 11 read-write PRO_AHB_RTCSLOW_0_L_F Setting to 1 grants PeriBus2 permission to fetch RTCSlow_0 low address region. 11 1 read-write PRO_AHB_RTCSLOW_0_L_R Setting to 1 grants PeriBus2 permission to read RTCSlow_0 low address region. 12 1 read-write PRO_AHB_RTCSLOW_0_L_W Setting to 1 grants PeriBus2 permission to write RTCSlow_0 low address region. 13 1 read-write PRO_AHB_RTCSLOW_0_H_F Setting to 1 grants PeriBus2 permission to fetch RTCSlow_0 high address region. 14 1 read-write PRO_AHB_RTCSLOW_0_H_R Setting to 1 grants PeriBus2 permission to read RTCSlow_0 high address region. 15 1 read-write PRO_AHB_RTCSLOW_0_H_W Setting to 1 grants PeriBus2 permission to write RTCSlow_0 high address region. 16 1 read-write PRO_AHB_2 PeriBus2 permission control register 2. 0x64 0x20 0x0001F800 PRO_AHB_RTCSLOW_1_SPLTADDR Configure the split address of RTCSlow_1 for PeriBus2 access. 0 11 read-write PRO_AHB_RTCSLOW_1_L_F Setting to 1 grants PeriBus2 permission to fetch RTCSlow_1 low address region. 11 1 read-write PRO_AHB_RTCSLOW_1_L_R Setting to 1 grants PeriBus2 permission to read RTCSlow_1 low address region. 12 1 read-write PRO_AHB_RTCSLOW_1_L_W Setting to 1 grants PeriBus2 permission to write RTCSlow_1 low address region. 13 1 read-write PRO_AHB_RTCSLOW_1_H_F Setting to 1 grants PeriBus2 permission to fetch RTCSlow_1 high address region. 14 1 read-write PRO_AHB_RTCSLOW_1_H_R Setting to 1 grants PeriBus2 permission to read RTCSlow_1 high address region. 15 1 read-write PRO_AHB_RTCSLOW_1_H_W Setting to 1 grants PeriBus2 permission to write RTCSlow_1 high address region. 16 1 read-write PRO_AHB_3 PeriBus2 permission control register 3. 0x68 0x20 PRO_AHB_ILG_CLR The clear signal for PeriBus2 access interrupt. 0 1 read-write PRO_AHB_ILG_EN The enable signal for PeriBus2 access interrupt. 1 1 read-write PRO_AHB_ILG_INTR PeriBus2 access interrupt signal. 2 1 read-only PRO_AHB_4 PeriBus2 status register. 0x6C 0x20 PRO_AHB_ILG_ST Record the illegitimate information of PeriBus2. [31:2]: store the bits [31:2] of PeriBus2 address. [1]: 1 means data access, 0 means instruction access. [0]: 1 means write operation, 0 means read operation. 0 32 read-only PRO_TRACE_0 Trace memory permission control register 0. 0x70 0x20 PRO_TRACE_LOCK Lock register. Setting to 1 locks trace function permission control registers. 0 1 read-write PRO_TRACE_1 Trace memory permission control register 1. 0x74 0x20 PRO_TRACE_DISABLE Setting to 1 disables the trace memory function. 0 1 read-write PRO_CACHE_0 Cache permission control register 0. 0x78 0x20 PRO_CACHE_LOCK Lock register. Setting to 1 locks cache permission control registers. 0 1 read-write PRO_CACHE_1 Cache permission control register 1. 0x7C 0x20 PRO_CACHE_CONNECT Configure which SRAM Block will be occupied by Icache or Dcache. 0 16 read-write PRO_CACHE_2 Cache permission control register 2. 0x80 0x20 PRO_CACHE_ILG_CLR The clear signal for cache access interrupt. 0 1 read-write PRO_CACHE_ILG_EN The enable signal for cache access interrupt. 1 1 read-write PRO_CACHE_ILG_INTR Cache access interrupt signal. 2 1 read-only PRO_CACHE_3 Icache status register. 0x84 0x20 PRO_CACHE_ILG_ST_I Record the illegitimate information of ICache to access memory. [16]: access enable, active low. [15:4]: store the bits [11:0] of address. [3:0]: Icache bus write byte enables, active low. 0 17 read-only PRO_CACHE_4 Dcache status register. 0x88 0x20 PRO_CACHE_ILG_ST_D Record the illegitimate information of Dcache to access memory. [16]: access enable, active low. [15:4]: store the bits [11:0] of address. [3:0]: Dcache bus write byte enables, active low. 0 17 read-only DMA_APB_I_0 Internal DMA permission control register 0. 0x8C 0x20 DMA_APB_I_LOCK Lock register. Setting to 1 locks internal DMA permission control registers. 0 1 read-write DMA_APB_I_1 Internal DMA permission control register 1. 0x90 0x20 0x1E0000FF DMA_APB_I_SRAM_0_R Setting to 1 grants internal DMA permission to read SRAM Block 0. 0 1 read-write DMA_APB_I_SRAM_0_W Setting to 1 grants internal DMA permission to write SRAM Block 0. 1 1 read-write DMA_APB_I_SRAM_1_R Setting to 1 grants internal DMA permission to read SRAM Block 1. 2 1 read-write DMA_APB_I_SRAM_1_W Setting to 1 grants internal DMA permission to write SRAM Block 1. 3 1 read-write DMA_APB_I_SRAM_2_R Setting to 1 grants internal DMA permission to read SRAM Block 2. 4 1 read-write DMA_APB_I_SRAM_2_W Setting to 1 grants internal DMA permission to write SRAM Block 2. 5 1 read-write DMA_APB_I_SRAM_3_R Setting to 1 grants internal DMA permission to read SRAM Block 3. 6 1 read-write DMA_APB_I_SRAM_3_W Setting to 1 grants internal DMA permission to write SRAM Block 3. 7 1 read-write DMA_APB_I_SRAM_4_SPLTADDR Configure the split address of SRAM Block 4-21 for internal DMA access. 8 17 read-write DMA_APB_I_SRAM_4_L_R Setting to 1 grants internal DMA permission to read SRAM Block 4-21 low address region. 25 1 read-write DMA_APB_I_SRAM_4_L_W Setting to 1 grants internal DMA permission to write SRAM Block 4-21 low address region. 26 1 read-write DMA_APB_I_SRAM_4_H_R Setting to 1 grants internal DMA permission to read SRAM Block 4-21 high address region. 27 1 read-write DMA_APB_I_SRAM_4_H_W Setting to 1 grants internal DMA permission to write SRAM Block 4-21 high address region. 28 1 read-write DMA_APB_I_2 Internal DMA permission control register 2. 0x94 0x20 DMA_APB_I_ILG_CLR The clear signal for internal DMA access interrupt. 0 1 read-write DMA_APB_I_ILG_EN The enable signal for internal DMA access interrupt. 1 1 read-write DMA_APB_I_ILG_INTR Internal DMA access interrupt signal. 2 1 read-only DMA_APB_I_3 Internal DMA status register. 0x98 0x20 DMA_APB_I_ILG_ST Record the illegitimate information of Internal DMA. [22:6]: store the bits [18:2] of address. [5]: if bits [31:19] of address are 0x7ff, then the bit value is 1, otherwise it is 0. [4]: 1 means write operation, 0 means read operation. [3:0]: Internal DMA bus byte enables. 0 23 read-only DMA_RX_I_0 RX Copy DMA permission control register 0. 0x9C 0x20 DMA_RX_I_LOCK Lock register. Setting to 1 locks RX Copy DMA permission control registers. 0 1 read-write DMA_RX_I_1 RX Copy DMA permission control register 1. 0xA0 0x20 0x1E0000FF DMA_RX_I_SRAM_0_R Setting to 1 grants RX Copy DMA permission to read SRAM Block 0. 0 1 read-write DMA_RX_I_SRAM_0_W Setting to 1 grants RX Copy DMA permission to write SRAM Block 0. 1 1 read-write DMA_RX_I_SRAM_1_R Setting to 1 grants RX Copy DMA permission to read SRAM Block 1. 2 1 read-write DMA_RX_I_SRAM_1_W Setting to 1 grants RX Copy DMA permission to write SRAM Block 1. 3 1 read-write DMA_RX_I_SRAM_2_R Setting to 1 grants RX Copy DMA permission to read SRAM Block 2. 4 1 read-write DMA_RX_I_SRAM_2_W Setting to 1 grants RX Copy DMA permission to write SRAM Block 2. 5 1 read-write DMA_RX_I_SRAM_3_R Setting to 1 grants RX Copy DMA permission to read SRAM Block 3. 6 1 read-write DMA_RX_I_SRAM_3_W Setting to 1 grants RX Copy DMA permission to write SRAM Block 3. 7 1 read-write DMA_RX_I_SRAM_4_SPLTADDR Configure the split address of SRAM Block 4-21 for RX Copy DMA access. 8 17 read-write DMA_RX_I_SRAM_4_L_R Setting to 1 grants RX Copy DMA permission to read SRAM Block 4-21 low address region. 25 1 read-write DMA_RX_I_SRAM_4_L_W Setting to 1 grants RX Copy DMA permission to write SRAM Block 4-21 low address region. 26 1 read-write DMA_RX_I_SRAM_4_H_R Setting to 1 grants RX Copy DMA permission to read SRAM Block 4-21 high address region. 27 1 read-write DMA_RX_I_SRAM_4_H_W Setting to 1 grants RX Copy DMA permission to write SRAM Block 4~21 high address region. 28 1 read-write DMA_RX_I_2 RX Copy DMA permission control register 2. 0xA4 0x20 DMA_RX_I_ILG_CLR The clear signal for RX Copy DMA access interrupt. 0 1 read-write DMA_RX_I_ILG_EN The enable signal for RX Copy DMA access interrupt. 1 1 read-write DMA_RX_I_ILG_INTR RX Copy DMA access interrupt signal. 2 1 read-only DMA_RX_I_3 RX Copy DMA status register. 0xA8 0x20 DMA_RX_I_ILG_ST Record the illegitimate information of RX Copy DMA. [22:6]: store the bits [18:2] of address. [5]: if bits [31:19] of address are 0x7ff, then the bit value is 1, otherwise it is 0. [4]: 1 means write operation, 0 means read operation. [3:0]: RX Copy DMA bus byte enables. 0 23 read-only DMA_TX_I_0 TX Copy DMA permission control register 0. 0xAC 0x20 DMA_TX_I_LOCK Lock register. Setting to 1 locks TX Copy DMA permission control registers. 0 1 read-write DMA_TX_I_1 TX Copy DMA permission control register 1. 0xB0 0x20 0x1E0000FF DMA_TX_I_SRAM_0_R Setting to 1 grants TX Copy DMA permission to read SRAM Block 0. 0 1 read-write DMA_TX_I_SRAM_0_W Setting to 1 grants TX Copy DMA permission to write SRAM Block 0. 1 1 read-write DMA_TX_I_SRAM_1_R Setting to 1 grants TX Copy DMA permission to read SRAM Block 1. 2 1 read-write DMA_TX_I_SRAM_1_W Setting to 1 grants TX Copy DMA permission to write SRAM Block 1. 3 1 read-write DMA_TX_I_SRAM_2_R Setting to 1 grants TX Copy DMA permission to read SRAM Block 2. 4 1 read-write DMA_TX_I_SRAM_2_W Setting to 1 grants TX Copy DMA permission to write SRAM Block 2. 5 1 read-write DMA_TX_I_SRAM_3_R Setting to 1 grants TX Copy DMA permission to read SRAM Block 3. 6 1 read-write DMA_TX_I_SRAM_3_W Setting to 1 grants TX Copy DMA permission to write SRAM Block 3. 7 1 read-write DMA_TX_I_SRAM_4_SPLTADDR Configure the split address of SRAM Block 4-21 for TX Copy DMA access. 8 17 read-write DMA_TX_I_SRAM_4_L_R Setting to 1 grants TX Copy DMA permission to read SRAM Block 4-21 low address region. 25 1 read-write DMA_TX_I_SRAM_4_L_W Setting to 1 grants TX Copy DMA permission to write SRAM Block 4-21 low address region. 26 1 read-write DMA_TX_I_SRAM_4_H_R Setting to 1 grants TX Copy DMA permission to read SRAM Block 4-21 high address region. 27 1 read-write DMA_TX_I_SRAM_4_H_W Setting to 1 grants TX Copy DMA permission to write SRAM Block 4-21 high address region. 28 1 read-write DMA_TX_I_2 TX Copy DMA permission control register 2. 0xB4 0x20 DMA_TX_I_ILG_CLR The clear signal for TX Copy DMA access interrupt. 0 1 read-write DMA_TX_I_ILG_EN The enable signal for TX Copy DMA access interrupt. 1 1 read-write DMA_TX_I_ILG_INTR TX Copy DMA access interrupt signal. 2 1 read-only DMA_TX_I_3 TX Copy DMA status register. 0xB8 0x20 DMA_TX_I_ILG_ST Record the illegitimate information of TX Copy DMA. [22:6]: store the bits [18:2] of address. [5]: if bits [31:19] of address are 0x7ff, then the bit value is 1, otherwise it is 0. [4]: 1 means write operation, 0 means read operation. [3:0]: TX Copy DMA bus byte enables. 0 23 read-only PRO_BOOT_LOCATION_0 Boot permission control register 0. 0xBC 0x20 PRO_BOOT_LOCATION_LOCK Lock register. Setting to 1 locks boot remap permission control registers. 0 1 read-write PRO_BOOT_LOCATION_1 Boot permission control register 1. 0xC0 0x20 PRO_BOOT_REMAP If set to 1, enable boot remap function. 0 1 read-write CACHE_SOURCE_0 Cache access permission control register 0. 0xC4 0x20 CACHE_SOURCE_LOCK Lock register. Setting to 1 locks cache access permission control registers. 0 1 read-write CACHE_SOURCE_1 Cache access permission control register 1. 0xC8 0x20 PRO_CACHE_I_SOURCE_PRO_IRAM1 xx 0 1 read-write PRO_CACHE_I_SOURCE_PRO_IROM0 xx 1 1 read-write PRO_CACHE_I_SOURCE_PRO_DROM0 xx 2 1 read-write PRO_CACHE_D_SOURCE_PRO_DRAM0 xx 3 1 read-write PRO_CACHE_D_SOURCE_PRO_DPORT xx 4 1 read-write PRO_CACHE_D_SOURCE_PRO_DROM0 xx 5 1 read-write APB_PERIPHERAL_0 Peripheral access permission control register 0. 0xCC 0x20 APB_PERIPHERAL_LOCK Lock register. Setting to 1 locks TX Copy DMA permission control registers. 0 1 read-write APB_PERIPHERAL_1 Peripheral access permission control register 1. 0xD0 0x20 0x00000001 APB_PERIPHERAL_SPLIT_BURST Setting to 1 splits the data phase of the last access and the address phase of following access. 0 1 read-write OCCUPY_0 Occupy permission control register 0. 0xD4 0x20 OCCUPY_LOCK Lock register. Setting to 1 locks occupy permission control registers. 0 1 read-write OCCUPY_1 Occupy permission control register 1. 0xD8 0x20 OCCUPY_CACHE Configure whether SRAM Block 0-3 is used as cache memory. 0 4 read-write OCCUPY_2 Occupy permission control register 2. 0xDC 0x20 OCCUPY_MAC_DUMP Configure whether SRAM Block 18-21 is used as mac dump. 0 4 read-write OCCUPY_3 Occupy permission control register 3. 0xE0 0x20 OCCUPY_PRO_TRACE Configure one block of SRAM Block 4-21 is used as trace memory. 0 18 read-write CACHE_TAG_ACCESS_0 Cache tag permission control register 0. 0xE4 0x20 CACHE_TAG_ACCESS_LOCK Lock register. Setting to 1 locks cache tag permission control registers. 0 1 read-write CACHE_TAG_ACCESS_1 Cache tag permission control register 1. 0xE8 0x20 PRO_I_TAG_RD_ACS Setting to 1 permits read access to Icache tag memory. 0 1 read-write PRO_I_TAG_WR_ACS Setting to 1 permits write access to Icache tag memory. 1 1 read-write PRO_D_TAG_RD_ACS Setting to 1 permits read access to Dcache tag memory. 2 1 read-write PRO_D_TAG_WR_ACS Setting to 1 permits write access to Dcache tag memory. 3 1 read-write CACHE_MMU_ACCESS_0 Cache MMU permission control register 0. 0xEC 0x20 CACHE_MMU_ACCESS_LOCK Lock register. Setting to 1 locks cache MMU permission control registers. 0 1 read-write CACHE_MMU_ACCESS_1 Cache MMU permission control register 1. 0xF0 0x20 0x00000003 PRO_MMU_RD_ACS Setting to 1 permits read access to MMU memory. 0 1 read-write PRO_MMU_WR_ACS Setting to 1 permits write access to MMU memory. 1 1 read-write APB_PERIPHERAL_INTR PeribBus2 permission control register. 0xF4 0x20 APB_PERI_BYTE_ERROR_CLR The clear signal for APB peripheral interrupt. 0 1 read-write APB_PERI_BYTE_ERROR_EN The enable signal for APB peripheral access interrupt. 1 1 read-write APB_PERI_BYTE_ERROR_INTR APB peripheral access interrupt signal. 2 1 read-only APB_PERIPHERAL_STATUS PeribBus2 peripheral access status register. 0xF8 0x20 APB_PERI_BYTE_ERROR_ADDR Record the illegitimate address of APB peripheral. 0 32 read-only CPU_PERIPHERAL_INTR PeribBus1 permission control register. 0xFC 0x20 CPU_PERI_BYTE_ERROR_CLR The clear signal for CPU peripheral access interrupt. 0 1 read-write CPU_PERI_BYTE_ERROR_EN The enable signal for CPU peripheral access interrupt. 1 1 read-write CPU_PERI_BYTE_ERROR_INTR CPU peripheral access interrupt signal. 2 1 read-only CPU_PERIPHERAL_STATUS PeribBus1 peripheral access status register. 0x100 0x20 CPU_PERI_BYTE_ERROR_ADDR Record the illegitimate address of CPU peripheral. 0 32 read-only CLOCK_GATE Clock gate register of permission control. 0x104 0x20 0x00000001 CLK_EN Enable the clock of permission control module when set to 1. 0 1 read-write DATE Version control register. 0xFFC 0x20 0x01905090 DATE Version control register. 0 28 read-write RMT Remote Control RMT 0x3F416000 0x0 0xA0 registers RMT 50 4 0x4 CH%sDATA The read and write data register for CHANNEL%s by apb fifo access. 0x0 0x20 DATA The read and write data register for CHANNEL%s by apb fifo access. 0 32 read-write 4 0x8 CH%sCONF0 Channel %s configure register 0 0x10 0x20 0x39100002 DIV_CNT This register is used to configure the divider for clock of CHANNEL%s. 0 8 read-write IDLE_THRES When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished. 8 16 read-write MEM_SIZE This register is used to configure the maximum size of memory allocated to CHANNEL%s. 24 3 read-write CARRIER_EFF_EN 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1. 27 1 read-write CARRIER_EN This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. 28 1 read-write CARRIER_OUT_LV This bit is used to configure the position of carrier wave for CHANNEL%s. 1'h0: add carrier wave on low level. 1'h1: add carrier wave on high level. 29 1 read-write 4 0x8 CH%sCONF1 Channel %s configure register 1 0x14 0x20 0x00000F20 TX_START Set this bit to start sending data on CHANNEL%s. 0 1 read-write RX_EN Set this bit to enable receiver to receive data on CHANNEL%s. 1 1 read-write MEM_WR_RST Set this bit to reset write ram address for CHANNEL%s by accessing receiver. 2 1 write-only MEM_RD_RST Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. 3 1 write-only APB_MEM_RST Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. 4 1 write-only MEM_OWNER This register marks the ownership of CHANNEL%s's ram block. 1'h1: Receiver is using the ram. 1'h0: Transmitter is using the ram. 5 1 read-write TX_CONTI_MODE Set this bit to restart transmission from the first data to the last data in CHANNEL%s. 6 1 read-write RX_FILTER_EN This is the receive filter's enable bit for CHANNEL%s. 7 1 read-write RX_FILTER_THRES Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). 8 8 read-write CHK_RX_CARRIER_EN Set this bit to enable memory loop read mode when carrier modulation is enabled for channel %s. 16 1 read-write REF_ALWAYS_ON This bit is used to select the base clock for CHANNEL%s. 1'h1: clk_apb 1'h0:clk_ref 17 1 read-write IDLE_OUT_LV This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. 18 1 read-write IDLE_OUT_EN This is the output enable-control bit for CHANNEL%s in IDLE state. 19 1 read-write TX_STOP Set this bit to stop the transmitter of CHANNEL%s sending data out. 20 1 read-write 4 0x4 CH%sSTATUS Channel %s status register 0x30 0x20 MEM_WADDR_EX This register records the memory address offset when receiver of CHANNEL%s is using the RAM. 0 9 read-only MEM_RADDR_EX This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. 10 9 read-only STATE This register records the FSM status of CHANNEL%s. 20 3 read-only MEM_OWNER_ERR This status bit will be set when the ownership of memory block is wrong. 23 1 read-only MEM_FULL This status bit will be set if the receiver receives more data than the memory size. 24 1 read-only MEM_EMPTY This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. 25 1 read-only APB_MEM_WR_ERR This status bit will be set if the offset address out of memory size when writes via APB bus. 26 1 read-only APB_MEM_RD_ERR This status bit will be set if the offset address out of memory size when reads via APB bus. 27 1 read-only 4 0x4 CH%sADDR Channel %s address register 0x40 0x20 APB_MEM_WADDR This register records the memory address offset when writes RAM over APB bus. 0 9 read-only APB_MEM_RADDR This register records the memory address offset when reads RAM over APB bus. 10 9 read-only INT_RAW Raw interrupt status 0x50 0x20 4 0x3 0-3 CH%s_TX_END The interrupt raw bit for CHANNEL%s. Triggered when transmission done. 0 1 read-only 4 0x3 0-3 CH%s_RX_END The interrupt raw bit for CHANNEL%s. Triggered when reception done. 1 1 read-only 4 0x3 0-3 CH%s_ERR The interrupt raw bit for CHANNEL%s. Triggered when error occurs. 2 1 read-only 4 0x1 0-3 CH%s_TX_THR_EVENT The interrupt raw bit for CHANNEL%s. Triggered when transmitter sent more data than configured value. 12 1 read-only 4 0x1 0-3 CH%s_TX_LOOP The interrupt raw bit for CHANNEL%s. Triggered when the loop count reaches the configured threshold value. 16 1 read-only INT_ST Masked interrupt status 0x54 0x20 4 0x3 0-3 CH%s_TX_END The masked interrupt status bit for CH%s_TX_END_INT. 0 1 read-only 4 0x3 0-3 CH%s_RX_END The masked interrupt status bit for CH%s_RX_END_INT. 1 1 read-only 4 0x3 0-3 CH%s_ERR The masked interrupt status bit for CH%s_ERR_INT. 2 1 read-only 4 0x1 0-3 CH%s_TX_THR_EVENT The masked interrupt status bit for CH%s_TX_THR_EVENT_INT. 12 1 read-only 4 0x1 0-3 CH%s_TX_LOOP The masked interrupt status bit for CH%s_TX_LOOP_INT. 16 1 read-only INT_ENA Interrupt enable bits 0x58 0x20 4 0x3 0-3 CH%s_TX_END The interrupt enabled bit for CH%s_TX_END_INT. 0 1 read-write 4 0x3 0-3 CH%s_RX_END The interrupt enabled bit for CH%s_RX_END_INT. 1 1 read-write 4 0x3 0-3 CH%s_ERR The interrupt enabled bit for CH%s_ERR_INT. 2 1 read-write 4 0x1 0-3 CH%s_TX_THR_EVENT The interrupt enabled bit for CH%s_TX_THR_EVENT_INT. 12 1 read-write 4 0x1 0-3 CH%s_TX_LOOP The interrupt enabled bit for CH%s_TX_LOOP_INT. 16 1 read-write INT_CLR Interrupt clear bits 0x5C 0x20 4 0x3 0-3 CH%s_TX_END Set this bit to clear the CH%s_TX_END_INT interrupt. 0 1 write-only 4 0x3 0-3 CH%s_RX_END Set this bit to clear the CH%s_RX_END_INT interrupt. 1 1 write-only 4 0x3 0-3 CH%s_ERR Set this bit to clear the CH%s_ERR_INT interrupt. 2 1 write-only 4 0x1 0-3 CH%s_TX_THR_EVENT Set this bit to clear the CH%s_TX_THR_EVENT_INT interrupt. 12 1 write-only 4 0x1 0-3 CH%s_TX_LOOP Set this bit to clear the CH%s_TX_LOOP_INT interrupt. 16 1 write-only 4 0x4 CH%sCARRIER_DUTY Channel %s duty cycle configuration register 0x60 0x20 0x00400040 CARRIER_LOW This register is used to configure carrier wave 's low level clock period for CHANNEL%s. 0 16 read-write CARRIER_HIGH This register is used to configure carrier wave 's high level clock period for CHANNEL%s. 16 16 read-write 4 0x4 CH%s_TX_LIM Channel %s Tx event configuration register 0x70 0x20 0x00000080 TX_LIM This register is used to configure the maximum entries that CHANNEL%s can send out. 0 9 read-write TX_LOOP_NUM This register is used to configure the maximum loop count when tx_conti_mode is valid. 9 10 read-write TX_LOOP_CNT_EN This register is the enabled bit for loop count. 19 1 read-write LOOP_COUNT_RESET This register is used to reset the loop count when tx_conti_mode is valid. 20 1 write-only APB_CONF RMT apb configuration register 0x80 0x20 0x00000004 APB_FIFO_MASK 1'h1: access memory directly. 1'h0: access memory by FIFO. 0 1 read-write MEM_TX_WRAP_EN This is the enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size. 1 1 read-write MEM_CLK_FORCE_ON Set this bit to enable the clock for RMT memory. 2 1 read-write MEM_FORCE_PD Set this bit to power down RMT memory. 3 1 read-write MEM_FORCE_PU 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode. 4 1 read-write CLK_EN RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers 31 1 read-write TX_SIM RMT TX synchronous register 0x84 0x20 CH0 Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. 0 1 read-write CH1 Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. 1 1 read-write CH2 Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels. 2 1 read-write CH3 Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels. 3 1 read-write EN This register is used to enable multiple of channels to start sending data synchronously. 4 1 read-write REF_CNT_RST RMT clock divider reset register 0x88 0x20 CH0 This register is used to reset the clock divider of CHANNEL0. 0 1 read-write CH1 This register is used to reset the clock divider of CHANNEL1. 1 1 read-write CH2 This register is used to reset the clock divider of CHANNEL2. 2 1 read-write CH3 This register is used to reset the clock divider of CHANNEL3. 3 1 read-write 4 0x4 CH%s_RX_CARRIER_RM Channel %s carrier remove register 0x8C 0x20 CARRIER_LOW_THRES The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. 0 16 read-write CARRIER_HIGH_THRES The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. 16 16 read-write DATE RMT version register 0xFC 0x20 0x19072601 DATE This is the version register. 0 32 read-write RNG Hardware Random Number Generator RNG 0x60035000 0x0 0x4 registers DATA Random number data 0x110 0x20 read-only RSA RSA (Rivest Shamir Adleman) Accelerator RSA 0x6003C000 0x0 0x34 registers RSA 54 M_PRIME Register to store M' 0x800 0x20 M_PRIME Stores M'. 0 32 read-write MODE RSA length mode 0x804 0x20 MODE Stores the mode of modular exponentiation. 0 7 read-write CLEAN RSA clean register 0x808 0x20 CLEAN The content of this bit is 1 when memories complete initialization. 0 1 read-only MODEXP_START Modular exponentiation starting bit 0x80C 0x20 MODEXP_START Set this bit to 1 to start the modular exponentiation. 0 1 write-only MODMULT_START Modular multiplication starting bit 0x810 0x20 MODMULT_START Set this bit to 1 to start the modular multiplication. 0 1 write-only MULT_START Normal multiplication starting bit 0x814 0x20 MULT_START Set this bit to 1 to start the multiplication. 0 1 write-only IDLE RSA idle register 0x818 0x20 IDLE The content of this bit is 1 when the RSA accelerator is idle. 0 1 read-only CLEAR_INTERRUPT RSA clear interrupt register 0x81C 0x20 CLEAR_INTERRUPT Set this bit to 1 to clear the RSA interrupts. 0 1 write-only CONSTANT_TIME The constant_time option 0x820 0x20 0x00000001 CONSTANT_TIME Set this bit to 0 to enable the acceleration option of constant_time for modular exponentiation. Set to 1 to disable the acceleration (by default). 0 1 read-write SEARCH_ENABLE The search option 0x824 0x20 SEARCH_ENABLE Set this bit to 1 to enable the acceleration option of search for modular exponentiation. Set to 0 to disable the acceleration (by default). 0 1 read-write SEARCH_POS The search position 0x828 0x20 SEARCH_POS Is used to configure the starting address when the acceleration option of search is used. 0 12 read-write INTERRUPT_ENA RSA interrupt enable register 0x82C 0x20 0x00000001 INTERRUPT_ENA Set this bit to 1 to enable the RSA interrupt. This option is enabled by default. 0 1 read-write DATE Version control register 0x830 0x20 0x20190425 DATE Version control register. 0 30 read-write 512 0x1 M_MEM[%s] Represents M 0x0 0x8 write-only 512 0x1 Z_MEM[%s] Represents Z 0x200 0x8 read-write 512 0x1 Y_MEM[%s] Represents Y 0x400 0x8 write-only 512 0x1 X_MEM[%s] Represents X 0x600 0x8 write-only RTC_IO Low-power Input/Output RTCIO 0x3F408400 0x0 0xF0 registers RTC_GPIO_OUT RTC GPIO output register 0x0 0x20 GPIO_OUT_DATA GPIO0 ~ 21 output register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. 10 22 read-write RTC_GPIO_OUT_W1TS RTC GPIO output bit set register 0x4 0x20 GPIO_OUT_DATA_W1TS GPIO0 ~ 21 output set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_OUT_REG. 10 22 write-only RTC_GPIO_OUT_W1TC RTC GPIO output bit clear register 0x8 0x20 GPIO_OUT_DATA_W1TC GPIO0 ~ 21 output clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_OUT_REG. 10 22 write-only RTC_GPIO_ENABLE RTC GPIO output enable register 0xC 0x20 REG_RTCIO_REG_GPIO_ENABLE GPIO0 ~ 21 output enable. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. If the bit is set to 1, it means this GPIO pad is output. 10 22 read-write RTC_GPIO_ENABLE_W1TS RTC GPIO output enable bit set register 0x10 0x20 REG_RTCIO_REG_GPIO_ENABLE_W1TS GPIO0 ~ 21 output enable set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_ENABLE_REG. 10 22 write-only ENABLE_W1TC RTC GPIO output enable bit clear register 0x14 0x20 ENABLE_W1TC GPIO0 ~ 21 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_ENABLE_REG. 10 22 write-only RTC_GPIO_STATUS RTC GPIO interrupt status register 0x18 0x20 GPIO_STATUS_INT GPIO0 ~ 21 interrupt status register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. This register should be used together with RTCIO_RTC_GPIO_PINn_INT_TYPE in RTCIO_RTC_GPIO_PINn_REG. 0: no interrupt; 1: corresponding interrupt. 10 22 read-write RTC_GPIO_STATUS_W1TS RTC GPIO interrupt status bit set register 0x1C 0x20 GPIO_STATUS_INT_W1TS GPIO0 ~ 21 interrupt set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be set to 1. Recommended operation: use this register to set RTCIO_GPIO_STATUS_INT. 10 22 write-only RTC_GPIO_STATUS_W1TC RTC GPIO interrupt status bit clear register 0x20 0x20 GPIO_STATUS_INT_W1TC GPIO0 ~ 21 interrupt clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be cleared. Recommended operation: use this register to clear RTCIO_GPIO_STATUS_INT. 10 22 write-only RTC_GPIO_IN RTC GPIO input register 0x24 0x20 GPIO_IN_NEXT GPIO0 ~ 21 input value. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. Each bit represents a pad input value, 1 for high level, and 0 for low level. 10 22 read-only 22 0x4 PIN%s RTC configuration for pin %s 0x28 0x20 PAD_DRIVER Pad driver selection. 0: normal output. 1: open drain. 2 1 read-write GPIO_PIN_INT_TYPE GPIO interrupt type selection. 0: GPIO interrupt disabled. 1: rising edge trigger. 2: falling edge trigger. 3: any edge trigger. 4: low level trigger. 5: high level trigger. 7 3 read-write GPIO_PIN_WAKEUP_ENABLE GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. 10 1 read-write RTC_DEBUG_SEL RTC debug select register 0x80 0x20 RTC_DEBUG_SEL0 0 5 read-write RTC_DEBUG_SEL1 5 5 read-write RTC_DEBUG_SEL2 10 5 read-write RTC_DEBUG_SEL3 15 5 read-write RTC_DEBUG_SEL4 20 5 read-write RTC_DEBUG_12M_NO_GATING 25 1 read-write 15 0x4 TOUCH_PAD%s Touch pad %s configuration register 0x84 0x20 0x52000000 FUN_IE Input enable in normal execution. 13 1 read-write SLP_OE Output enable in sleep mode. 14 1 read-write SLP_IE Input enable in sleep mode. 15 1 read-write SLP_SEL 0: no sleep mode. 1: enable sleep mode. 16 1 read-write FUN_SEL Function selection. 17 2 read-write MUX_SEL Connect the RTC pad input to digital pad input. 0 is available. 19 1 read-write XPD Touch sensor power on. 20 1 read-write TIE_OPT The tie option of touch sensor. 0: tie low. 1: tie high. 21 1 read-write START Start touch sensor. 22 1 read-write DAC Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. 23 3 read-write RUE Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 27 1 read-write RDE Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 28 1 read-write DRV Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 29 2 read-write XTAL_32P_PAD 32KHz crystal P-pad configuration register 0xC0 0x20 0x40000000 X32P_FUN_IE Input enable in normal execution. 13 1 read-write X32P_SLP_OE output enable in sleep mode. 14 1 read-write X32P_SLP_IE input enable in sleep mode. 15 1 read-write X32P_SLP_SEL 1: enable sleep mode. 0: no sleep mode. 16 1 read-write X32P_FUN_SEL Function selection. 17 2 read-write X32P_MUX_SEL 1: use RTC GPIO. 0: use digital GPIO. 19 1 read-write X32P_RUE Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 27 1 read-write X32P_RDE Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 28 1 read-write X32P_DRV Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 29 2 read-write XTAL_32N_PAD 32KHz crystal N-pad configuration register 0xC4 0x20 0x40000000 X32N_FUN_IE Input enable in normal execution. 13 1 read-write X32N_SLP_OE Output enable in sleep mode. 14 1 read-write X32N_SLP_IE Input enable in sleep mode. 15 1 read-write X32N_SLP_SEL 1: enable sleep mode. 0: no sleep mode. 16 1 read-write X32N_FUN_SEL Function selection. 17 2 read-write X32N_MUX_SEL 1: use RTC GPIO. 0: use digital GPIO. 19 1 read-write X32N_RUE Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 27 1 read-write X32N_RDE Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 28 1 read-write X32N_DRV Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 29 2 read-write PAD_DAC1 DAC1 configuration register 0xC8 0x20 0x40000000 PDAC1_DAC Configure DAC_1 output when RTCIO_PDAC1_DAC_XPD_FORCE is set to 1. 3 8 read-write PDAC1_XPD_DAC When RTCIO_PDAC1_DAC_XPD_FORCE is set to 1, 1: enable DAC_1 output. 0: disable DAC_1 output. 11 1 read-write PDAC1_DAC_XPD_FORCE 1: use RTCIO_PDAC1_XPD_DAC to control DAC_1 output. 0: use SAR ADC FSM to control DAC_1 output. 12 1 read-write PDAC1_FUN_IE Input enable in normal execution. 13 1 read-write PDAC1_SLP_OE Output enable in sleep mode 14 1 read-write PDAC1_SLP_IE Input enable in sleep mode 15 1 read-write PDAC1_SLP_SEL 1: enable sleep mode. 0: no sleep mode 16 1 read-write PDAC1_FUN_SEL DAC_1 function selection. 17 2 read-write PDAC1_MUX_SEL 1: use RTC GPIO. 0: use digital GPIO 19 1 read-write PDAC1_RUE Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 27 1 read-write PDAC1_RDE Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 28 1 read-write PDAC1_DRV Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 29 2 read-write PAD_DAC2 DAC2 configuration register 0xCC 0x20 0x40000000 PDAC2_DAC Configure DAC_2 output when RTCIO_PDAC2_DAC_XPD_FORCE is set to 1. 3 8 read-write PDAC2_XPD_DAC When RTCIO_PDAC2_DAC_XPD_FORCE is set to 1, 1: enable DAC_2 output. 0: disable DAC_2 output. 11 1 read-write PDAC2_DAC_XPD_FORCE 1: use RTCIO_PDAC2_XPD_DAC to control DAC_2 output. 0: use SAR ADC FSM to control DAC_2 output. 12 1 read-write PDAC2_FUN_IE Input enable in normal execution. 13 1 read-write PDAC2_SLP_OE Output enable in sleep mode. 14 1 read-write PDAC2_SLP_IE Input enable in sleep mode. 15 1 read-write PDAC2_SLP_SEL 1: enable sleep mode. 0: no sleep mode. 16 1 read-write PDAC2_FUN_SEL DAC_2 function selection. 17 2 read-write PDAC2_MUX_SEL 1: use RTC GPIO. 0: use digital GPIO. 19 1 read-write PDAC2_RUE Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 27 1 read-write PDAC2_RDE Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 28 1 read-write PDAC2_DRV Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 29 2 read-write RTC_PAD19 Touch pad 19 configuration register 0xD0 0x20 0x50000000 FUN_IE Input enable in normal execution. 13 1 read-write SLP_OE Output enable in sleep mode. 14 1 read-write SLP_IE Input enable in sleep mode. 15 1 read-write SLP_SEL 1: enable sleep mode. 0: no sleep mode 16 1 read-write FUN_SEL Function selection. 17 2 read-write MUX_SEL 1: use RTC GPIO. 0: use digital GPIO. 19 1 read-write RUE Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 27 1 read-write RDE Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 28 1 read-write DRV Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 29 2 read-write RTC_PAD20 Touch pad 20 configuration register 0xD4 0x20 0x50000000 FUN_IE Input enable in normal execution. 13 1 read-write SLP_OE Output enable in sleep mode. 14 1 read-write SLP_IE Input enable in sleep mode. 15 1 read-write SLP_SEL 1: enable sleep mode. 0: no sleep mode. 16 1 read-write FUN_SEL Function selection. 17 2 read-write MUX_SEL 1: use RTC GPIO. 0: use digital GPIO. 19 1 read-write RUE Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 27 1 read-write RDE Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 28 1 read-write DRV Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 29 2 read-write RTC_PAD21 Touch pad 21 configuration register 0xD8 0x20 0x50000000 FUN_IE Input enable in normal execution. 13 1 read-write SLP_OE Output enable in sleep mode. 14 1 read-write SLP_IE Input enable in sleep mode. 15 1 read-write SLP_SEL 1: enable sleep mode. 0: no sleep mode. 16 1 read-write FUN_SEL Function selection. 17 2 read-write MUX_SEL 1: use RTC GPIO. 0: use digital GPIO. 19 1 read-write RUE Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 27 1 read-write RDE Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 28 1 read-write DRV Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 29 2 read-write EXT_WAKEUP0 External wake up configuration register 0xDC 0x20 SEL GPIO[0-17] can be used to wake up the chip when the chip is in the sleep mode. This register prompts the pad source to wake up the chip when the latter is indeep/light sleep mode. 0: select GPIO0; 1: select GPIO2, etc 27 5 read-write XTL_EXT_CTR Crystal power down enable GPIO source 0xE0 0x20 SEL Select the external crystal power down enable source to get into sleep mode. 0: select GPIO0. 1: select GPIO1, etc. The input value on this pin XOR RTC_CNTL_EXT_XTL_CONF_REG[30] is the crystal power down enable signal. 27 5 read-write SAR_I2C_IO RTC I2C pad selection 0xE4 0x20 SAR_DEBUG_BIT_SEL 23 5 read-write SAR_I2C_SCL_SEL Selects a pad the RTC I2C SCL signal connects to. 0: use TOUCH PAD0. 1: use TOUCH PAD2. 28 2 read-write SAR_I2C_SDA_SEL Selects a pad the RTC I2C SDA signal connects to. 0: use TOUCH PAD1. 1: use TOUCH PAD3. 30 2 read-write RTC_IO_TOUCH_CTRL Touch control register 0xE8 0x20 IO_TOUCH_BUFSEL 0 4 read-write IO_TOUCH_BUFMODE 4 1 read-write RTC_IO_DATE Version control register 0x1FC 0x20 0x01903170 IO_DATE Version control register 0 28 read-write RTC_CNTL Real-Time Clock Control RTC_CNTL 0x3F408000 0x0 0x138 registers RTC_CORE 49 OPTIONS0 Sets the power options of crystal and PLL clocks, and initiates reset by software 0x0 0x20 0x1C002000 SW_STALL_APPCPU_C0 {reg_sw_stall_appcpu_c1[5:0] , reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU 0 2 read-write SW_STALL_PROCPU_C0 When RTC_CNTL_REG_SW_STALL_PROCPU_C1 is configured to 0x21, setting this bit to 0x2 stalls the CPU by SW. 2 2 read-write SW_APPCPU_RST APP CPU SW reset. (Note, we don’t have APP CPU for ESP32-S2) 4 1 write-only SW_PROCPU_RST Set this bit to reset the CPU by SW. 5 1 write-only BB_I2C_FORCE_PD Set this bit to FPD BB_I2C. 6 1 read-write BB_I2C_FORCE_PU Set this bit to FPU BB_I2C. 7 1 read-write BBPLL_I2C_FORCE_PD Set this bit to FPD BB_PLL _I2C. 8 1 read-write BBPLL_I2C_FORCE_PU Set this bit to FPU BB_PLL _I2C. 9 1 read-write BBPLL_FORCE_PD Set this bit to FPD BB_PLL. 10 1 read-write BBPLL_FORCE_PU Set this bit to FPU BB_PLL. 11 1 read-write XTL_FORCE_PD Set this bit to FPD the crystal oscillator. 12 1 read-write XTL_FORCE_PU Set this bit to FPU the crystal oscillator. 13 1 read-write XTL_FORCE_ISO 23 1 read-write PLL_FORCE_ISO 24 1 read-write ANALOG_FORCE_ISO 25 1 read-write XTL_FORCE_NOISO 26 1 read-write PLL_FORCE_NOISO 27 1 read-write ANALOG_FORCE_NOISO 28 1 read-write DG_WRAP_FORCE_RST Set this bit to force reset the digital system in deep-sleep. 29 1 read-write DG_WRAP_FORCE_NORST Set this bit to disable force reset to digital system in deep-sleep. 30 1 read-write SW_SYS_RST Set this bit to reset the system via SW. 31 1 write-only SLP_TIMER0 RTC timer threshold register 0 0x4 0x20 SLP_VAL_LO Sets the lower 32 bits of the trigger threshold for the RTC timer. 0 32 read-write SLP_TIMER1 RTC timer threshold register 1 0x8 0x20 SLP_VAL_HI Sets the higher 16 bits of the trigger threshold for the RTC timer. 0 16 read-write MAIN_TIMER_ALARM_EN Sets this bit to enable the timer alarm. 16 1 write-only TIME_UPDATE RTC timer update control register 0xC 0x20 TIMER_SYS_STALL Selects the triggering condition for the RTC timer. See details in Table 1-2. 27 1 read-write TIMER_XTL_OFF Selects the triggering condition for the RTC timer. See details in Table 1-2. 28 1 read-write TIMER_SYS_RST Selects the triggering condition for the RTC timer. See details in Table 1-2. 29 1 read-write TIME_UPDATE Selects the triggering condition for the RTC timer. See details in Table 1-2. 31 1 write-only TIME_LOW0 Stores the lower 32 bits of RTC timer 0. 0x10 0x20 TIMER_VALUE0_LOW Stores the lower 32 bits of RTC timer 0. 0 32 read-only TIME_HIGH0 Stores the higher 16 bits of RTC timer 0 0x14 0x20 TIMER_VALUE0_HIGH Stores the higher 16 bits of RTC timer 0. 0 16 read-only STATE0 Configures the sleep / reject / wakeup state 0x18 0x20 SW_CPU_INT Sends a SW RTC interrupt to CPU. 0 1 write-only SLP_REJECT_CAUSE_CLR Clears the RTC reject-to-sleep cause. 1 1 write-only APB2RTC_BRIDGE_SEL 1: APB to RTC using bridge 0: APB to RTC using sync 22 1 read-write SDIO_ACTIVE_IND Indicates the SDIO is active. 28 1 read-only SLP_WAKEUP Sleep wakeup bit. 29 1 read-write SLP_REJECT Sleep reject bit. 30 1 read-write SLEEP_EN Sends the chip to sleep. 31 1 read-write TIMER1 Configures CPU stall options 0x1C 0x20 0x28140403 CPU_STALL_EN Enables CPU stalling. 0 1 read-write CPU_STALL_WAIT Sets the CPU stall waiting cycle (using the RTC fast clock). 1 5 read-write CK8M_WAIT Sets the 8 MHz clock waiting (using the RTC slow clock). 6 8 read-write XTL_BUF_WAIT Sets the XTAL waiting cycle (using the RTC slow clock). 14 10 read-write PLL_BUF_WAIT Sets the PLL waiting cycle (using the RTC slow clock). 24 8 read-write TIMER2 Configures RTC slow clock and touch controller 0x20 0x20 0x01080000 ULPCP_TOUCH_START_WAIT Sets the waiting cycle (using the RTC slow clock) before the ULP co-processor / touch controller start to work. 15 9 read-write MIN_TIME_CK8M_OFF Sets the minimal cycle for 8 MHz clock (using the RTC slow clock) when powered down. 24 8 read-write TIMER3 configure some wait time for power on 0x24 0x20 0x14160A08 WIFI_WAIT_TIMER 0 9 read-write WIFI_POWERUP_TIMER 9 7 read-write ROM_RAM_WAIT_TIMER 16 9 read-write ROM_RAM_POWERUP_TIMER 25 7 read-write TIMER4 configure some wait time for power on 0x28 0x20 0x10200A08 WAIT_TIMER 0 9 read-write POWERUP_TIMER 9 7 read-write DG_WRAP_WAIT_TIMER 16 9 read-write DG_WRAP_POWERUP_TIMER 25 7 read-write TIMER5 Configures the minimal sleep cycles 0x2C 0x20 0x12148000 MIN_SLP_VAL Sets the minimal sleep cycles (using the RTC slow clock). 8 8 read-write RTCMEM_WAIT_TIMER 16 9 read-write RTCMEM_POWERUP_TIMER 25 7 read-write TIMER6 Configure minimal sleep cycles register 0x30 0x20 0x10200000 DG_DCDC_WAIT_TIMER 16 9 read-write DG_DCDC_POWERUP_TIMER 25 7 read-write ANA_CONF Configures the power options for I2C and PLLA 0x34 0x20 0x00A40000 I2C_RESET_POR_FORCE_PD SLEEP_I2CPOR force pd 18 1 read-write I2C_RESET_POR_FORCE_PU SLEEP_I2CPOR force pu 19 1 read-write GLITCH_RST_EN Set this bit to enable a reset when the system detects a glitch. 20 1 read-write SAR_I2C_FORCE_PD Sets this bit to FPD the SAR_I2C. 21 1 read-write SAR_I2C_FORCE_PU Sets this bit to FPU the SAR_I2C. 22 1 read-write PLLA_FORCE_PD Sets this bit to FPD the PLLA. 23 1 read-write PLLA_FORCE_PU Sets this bit to FPU the PLLA. 24 1 read-write BBPLL_CAL_SLP_START start BBPLL calibration during sleep 25 1 read-write PVTMON_PU 1: PVTMON power up , otherwise power down 26 1 read-write TXRF_I2C_PU 1: TXRF_I2C power up , otherwise power down 27 1 read-write RFRX_PBUS_PU 1: RFRX_PBUS power up , otherwise power down 28 1 read-write CKGEN_I2C_PU 1: CKGEN_I2C power up , otherwise power down 30 1 read-write PLL_I2C_PU 1. PLL_I2C power up ,otherwise power down 31 1 read-write RESET_STATE Indicates the CPU reset source. For more information about the reset cause, please refer to Table \ref{table:resetreasons} in Chapter \ref{module:ResetandClock} \textit{\nameref{module:ResetandClock}}. 0x38 0x20 0x00003000 RESET_CAUSE_PROCPU Stores the CPU reset cause. 0 6 read-only RESET_CAUSE_APPCPU reset cause of APP CPU 6 6 read-only APPCPU_STAT_VECTOR_SEL APP CPU state vector sel 12 1 read-write PROCPU_STAT_VECTOR_SEL Selects the CPU state vector. 13 1 read-write WAKEUP_STATE Wakeup bitmap enabling register 0x3C 0x20 0x00060000 WAKEUP_ENA Enables the wakeup bitmap. 15 17 read-write INT_ENA_RTC RTC interrupt enabling register 0x40 0x20 SLP_WAKEUP_INT_ENA Enables interruption when the chip wakes up from sleep. 0 1 read-write SLP_REJECT_INT_ENA Enables interruption when the chip rejects to go to sleep. 1 1 read-write SDIO_IDLE_INT_ENA Enables interruption when the SDIO idles. 2 1 read-write WDT_INT_ENA Enables the RTC watchdog interrupt. 3 1 read-write TOUCH_SCAN_DONE_INT_ENA Enables interruption upon the completion of a touch scanning. 4 1 read-write ULP_CP_INT_ENA Enables the ULP co-processor interrupt. 5 1 read-write TOUCH_DONE_INT_ENA Enables interruption upon the completion of a single touch. 6 1 read-write TOUCH_ACTIVE_INT_ENA Enables interruption when a touch is detected. 7 1 read-write TOUCH_INACTIVE_INT_ENA Enables interruption when a touch is released. 8 1 read-write BROWN_OUT_INT_ENA Enables the brown out interrupt. 9 1 read-write MAIN_TIMER_INT_ENA Enables the RTC main timer interrupt. 10 1 read-write SARADC1_INT_ENA Enables the SAR ADC 1 interrupt. 11 1 read-write TSENS_INT_ENA Enables the touch sensor interrupt. 12 1 read-write COCPU_INT_ENA Enables the ULP-RISCV interrupt. 13 1 read-write SARADC2_INT_ENA Enables the SAR ADC 2 interrupt. 14 1 read-write SWD_INT_ENA Enables the super watchdog interrupt. 15 1 read-write XTAL32K_DEAD_INT_ENA Enables interruption when the 32 kHz crystal is dead. 16 1 read-write COCPU_TRAP_INT_ENA Enables interruption when the ULP-RISCV is trapped. 17 1 read-write TOUCH_TIMEOUT_INT_ENA Enables interruption when touch sensor times out. 18 1 read-write GLITCH_DET_INT_ENA Enables interruption when a glitch is detected. 19 1 read-write INT_RAW_RTC RTC interrupt raw register 0x44 0x20 SLP_WAKEUP_INT_RAW Stores the raw interrupt triggered when the chip wakes up from sleep. 0 1 read-only SLP_REJECT_INT_RAW Stores the raw interrupt triggered when the chip rejects to go to sleep. 1 1 read-only SDIO_IDLE_INT_RAW Stores the raw interrupt triggered when the SDIO idles. 2 1 read-only WDT_INT_RAW Stores the raw RTC watchdog interrupt. 3 1 read-only TOUCH_SCAN_DONE_INT_RAW Stores the raw interrupt triggered upon the completion of a touch scanning. 4 1 read-only ULP_CP_INT_RAW Stores the raw ULP co-processor interrupt. 5 1 read-only TOUCH_DONE_INT_RAW Stores the raw interrupt triggered upon the completion of a single touch. 6 1 read-only TOUCH_ACTIVE_INT_RAW Stores the raw interrupt triggered when a touch is detected. 7 1 read-only TOUCH_INACTIVE_INT_RAW Stores the raw interrupt triggered when a touch is released. 8 1 read-only BROWN_OUT_INT_RAW Stores the raw brown out interrupt. 9 1 read-only MAIN_TIMER_INT_RAW Stores the raw RTC main timer interrupt. 10 1 read-only SARADC1_INT_RAW Stores the raw SAR ADC 1 interrupt. 11 1 read-only TSENS_INT_RAW Stores the raw touch sensor interrupt. 12 1 read-only COCPU_INT_RAW Stores the raw ULP-RISCV interrupt. 13 1 read-only SARADC2_INT_RAW Stores the raw SAR ADC 2 interrupt. 14 1 read-only SWD_INT_RAW Stores the raw super watchdog interrupt. 15 1 read-only XTAL32K_DEAD_INT_RAW Stores the raw interrupt triggered when the 32 kHz crystal is dead. 16 1 read-only COCPU_TRAP_INT_RAW Stores the raw interrupt triggered when the ULP-RISCV is trapped. 17 1 read-only TOUCH_TIMEOUT_INT_RAW Stores the raw interrupt triggered when touch sensor times out. 18 1 read-only GLITCH_DET_INT_RAW Stores the raw interrupt triggered when a glitch is detected. 19 1 read-only INT_ST_RTC RTC interrupt state register 0x48 0x20 SLP_WAKEUP_INT_ST Stores the status of the interrupt triggered when the chip wakes up from sleep. 0 1 read-only SLP_REJECT_INT_ST Stores the status of the interrupt triggered when the chip rejects to go to sleep. 1 1 read-only SDIO_IDLE_INT_ST Stores the status of the interrupt triggered when the SDIO idles. 2 1 read-only WDT_INT_ST Stores the status of the RTC watchdog interrupt. 3 1 read-only TOUCH_SCAN_DONE_INT_ST Stores the status of the interrupt triggered upon the completion of a touch scanning. 4 1 read-only ULP_CP_INT_ST Stores the status of the ULP co-processor interrupt. 5 1 read-only TOUCH_DONE_INT_ST Stores the status of the interrupt triggered upon the completion of a single touch. 6 1 read-only TOUCH_ACTIVE_INT_ST Stores the status of the interrupt triggered when a touch is detected. 7 1 read-only TOUCH_INACTIVE_INT_ST Stores the status of the interrupt triggered when a touch is released. 8 1 read-only BROWN_OUT_INT_ST Stores the status of the brown out interrupt. 9 1 read-only MAIN_TIMER_INT_ST Stores the status of the RTC main timer interrupt. 10 1 read-only SARADC1_INT_ST Stores the status of the SAR ADC 1 interrupt. 11 1 read-only TSENS_INT_ST Stores the status of the touch sensor interrupt. 12 1 read-only COCPU_INT_ST Stores the status of the ULP-RISCV interrupt. 13 1 read-only SARADC2_INT_ST Stores the status of the SAR ADC 2 interrupt. 14 1 read-only SWD_INT_ST Stores the status of the super watchdog interrupt. 15 1 read-only XTAL32K_DEAD_INT_ST Stores the status of the interrupt triggered when the 32 kHz crystal is dead. 16 1 read-only COCPU_TRAP_INT_ST Stores the status of the interrupt triggered when the ULP-RISCV is trapped. 17 1 read-only TOUCH_TIMEOUT_INT_ST Stores the status of the interrupt triggered when touch sensor times out. 18 1 read-only GLITCH_DET_INT_ST Stores the status of the interrupt triggered when a glitch is detected. 19 1 read-only INT_CLR_RTC RTC interrupt clear register 0x4C 0x20 SLP_WAKEUP_INT_CLR Clears the interrupt triggered when the chip wakes up from sleep. 0 1 write-only SLP_REJECT_INT_CLR Clears the interrupt triggered when the chip rejects to go to sleep. 1 1 write-only SDIO_IDLE_INT_CLR Clears the interrupt triggered when the SDIO idles. 2 1 write-only WDT_INT_CLR Enables the RTC watchdog interrupt. 3 1 write-only TOUCH_SCAN_DONE_INT_CLR Clears the interrupt triggered upon the completion of a touch scanning. 4 1 write-only ULP_CP_INT_CLR Enables the ULP co-processor interrupt. 5 1 write-only TOUCH_DONE_INT_CLR Clears the interrupt triggered upon the completion of a single touch. 6 1 write-only TOUCH_ACTIVE_INT_CLR Clears the interrupt triggered when a touch is detected. 7 1 write-only TOUCH_INACTIVE_INT_CLR Clears the interrupt triggered when a touch is released. 8 1 write-only BROWN_OUT_INT_CLR Clears the brown out interrupt. 9 1 write-only MAIN_TIMER_INT_CLR Clears the RTC main timer interrupt. 10 1 write-only SARADC1_INT_CLR Clears the SAR ADC 1 interrupt. 11 1 write-only TSENS_INT_CLR Clears the touch sensor interrupt. 12 1 write-only COCPU_INT_CLR Clears the ULP-RISCV interrupt. 13 1 write-only SARADC2_INT_CLR Clears the SAR ADC 2 interrupt. 14 1 write-only SWD_INT_CLR Clears the super watchdog interrupt. 15 1 write-only XTAL32K_DEAD_INT_CLR Clears the interrupt triggered when the 32 kHz crystal is dead. 16 1 write-only COCPU_TRAP_INT_CLR Clears the interrupt triggered when the ULP-RISCV is trapped. 17 1 write-only TOUCH_TIMEOUT_INT_CLR Clears the interrupt triggered when touch sensor times out. 18 1 write-only GLITCH_DET_INT_CLR Clears the interrupt triggered when a glitch is detected. 19 1 write-only STORE0 Reservation register 0 0x50 0x20 SCRATCH0 Reservation register 0 0 32 read-write STORE1 Reservation register 1 0x54 0x20 SCRATCH1 Reservation register 1 0 32 read-write STORE2 Reservation register 2 0x58 0x20 SCRATCH2 Reservation register 2 0 32 read-write STORE3 Reservation register 3 0x5C 0x20 SCRATCH3 Reservation register 3 0 32 read-write EXT_XTL_CONF 32 kHz crystal oscillator configuration register 0x60 0x20 0x00066C80 XTAL32K_WDT_EN Set this bit to enable the 32 kHz crystal watchdog. 0 1 read-write XTAL32K_WDT_CLK_FO Set this bit to FPU the 32 kHz crystal watchdog clock. 1 1 read-write XTAL32K_WDT_RESET Set this bit to reset the 32 kHz crystal watchdog by SW. 2 1 read-write XTAL32K_EXT_CLK_FO Set this bit to FPU the external clock of 32 kHz crystal. 3 1 read-write XTAL32K_AUTO_BACKUP Set this bit to switch to the backup clock when the 32 kHz crystal is dead. 4 1 read-write XTAL32K_AUTO_RESTART Set this bit to restart the 32 kHz crystal automatically when the 32 kHz crystal is dead. 5 1 read-write XTAL32K_AUTO_RETURN Set this bit to switch back to 32 kHz crystal when the 32 kHz crystal is restarted. 6 1 read-write XTAL32K_XPD_FORCE Set 1 to allow the software to FPD the 32 kHz crystal. Set 0 to allow the FSM to FPD the 32 kHz crystal. (R/W) 7 1 read-write ENCKINIT_XTAL_32K Applies an internal clock to help the 32 kHz crystal to start. 8 1 read-write DBUF_XTAL_32K 0: single-end buffer 1: differential buffer 9 1 read-write DGM_XTAL_32K xtal_32k gm control 10 3 read-write DRES_XTAL_32K DRES_XTAL_32K 13 3 read-write XPD_XTAL_32K XPD_XTAL_32K 16 1 read-write DAC_XTAL_32K DAC_XTAL_32K 17 3 read-write WDT_STATE Stores the status of the 32 kHz watchdog. 20 3 read-only XTAL32K_GPIO_SEL Selects the 32 kHz crystal clock. 0: selects the external 32 kHz clock. 1: selects clock from the RTC GPIO X32P_C. 23 1 read-write XTL_EXT_CTR_LV 0: powers down XTAL at high level 1: powers down XTAL at low level 30 1 read-write XTL_EXT_CTR_EN Enables the GPIO to power down the crystal oscillator. 31 1 read-write EXT_WAKEUP_CONF GPIO wakeup configuration register 0x64 0x20 GPIO_WAKEUP_FILTER Set this bit to enable the GPIO wakeup event filter. 29 1 read-write EXT_WAKEUP0_LV 0: external wakeup 0 at low level 1: external wakeup 0 at high level 30 1 read-write EXT_WAKEUP1_LV 0: external wakeup 1 at low level 1: external wakeup 1 at high level 31 1 read-write SLP_REJECT_CONF Configures sleep / reject options 0x68 0x20 SLEEP_REJECT_ENA Set this bit to enable reject-to-sleep. 13 17 read-write LIGHT_SLP_REJECT_EN Set this bit to enable reject-to-light-sleep. 30 1 read-write DEEP_SLP_REJECT_EN Set this bit to enable reject-to-deep-sleep. 31 1 read-write CPU_PERIOD_CONF CPU sel option 0x6C 0x20 CPUSEL_CONF CPU sel option 29 1 read-write CPUPERIOD_SEL 30 2 read-write SDIO_ACT_CONF configure sdio active register 0x70 0x20 SDIO_ACT_DNUM configure sdio act dnum 22 10 read-write CLK_CONF RTC clock configuration register 0x74 0x20 0x01583218 CK8M_DIV_SEL_VLD Synchronizes the reg_ck8m_div_sel. Not that you have to invalidate the bus before switching clock, and validate the new clock. 3 1 read-write CK8M_DIV Set the CK8M_D256_OUT divider. 00: divided by 128 01: divided by 256 10: divided by 512 11: divided by 1024. 4 2 read-write ENB_CK8M Set this bit to disable CK8M and CK8M_D256_OUT. 6 1 read-write ENB_CK8M_DIV Selects the CK8M_D256_OUT. 1: CK8M 0: CK8M divided by 256. 7 1 read-write DIG_XTAL32K_EN Set this bit to enable CK_XTAL_32K clock for the digital core. 8 1 read-write DIG_CLK8M_D256_EN Set this bit to enable CK8M_D256_OUT clock for the digital core. 9 1 read-write DIG_CLK8M_EN Set this bit to enable 8 MHz clock for the digital core. 10 1 read-write CK8M_DIV_SEL Stores the 8 MHz divider, which is reg_ck8m_div_sel + 1 12 3 read-write XTAL_FORCE_NOGATING Set this bit to force no gating to crystal during sleep 15 1 read-write CK8M_FORCE_NOGATING Set this bit to disable force gating to 8 MHz crystal during sleep. 16 1 read-write CK8M_DFREQ CK8M_DFREQ 17 8 read-write CK8M_FORCE_PD Set this bit to FPD the 8 MHz clock. 25 1 read-write CK8M_FORCE_PU Set this bit to FPU the 8 MHz clock. 26 1 read-write FAST_CLK_RTC_SEL Set this bit to select the RTC fast clock. 0: XTAL div 4, 1: CK8M. 29 1 read-write ANA_CLK_RTC_SEL Set this bit to select the RTC slow clock. 0: 90K rtc_clk 1: 32k XTAL 2: 8md256. 30 2 read-write SLOW_CLK_CONF RTC slow clock configuration register 0x78 0x20 0x00400000 ANA_CLK_DIV_VLD Synchronizes the reg_rtc_ana_clk_div bus. Note that you have to invalidate the bus before switching clock, and validate the new clock. 22 1 read-write ANA_CLK_DIV Set the rtc_clk divider. 23 8 read-write SLOW_CLK_NEXT_EDGE 31 1 read-write SDIO_CONF configure vddsdio register 0x7C 0x20 0x02B0BE0A SDIO_TIMER_TARGET timer count to apply reg_sdio_dcap after sdio power on 0 8 read-write SDIO_DTHDRV Tieh = 1 mode drive ability. Initially set to 0 to limit charge current set to 3 after several us. 9 2 read-write SDIO_DCAP ability to prevent LDO from overshoot 11 2 read-write SDIO_INITI add resistor from ldo output to ground. 0: no res 1: 6k 2: 4k 3: 2k 13 2 read-write SDIO_EN_INITI 0 to set init[1:0]=0 15 1 read-write SDIO_DCURLIM tune current limit threshold when tieh = 0. About 800mA/(8+d) 16 3 read-write SDIO_MODECURLIM select current limit mode 19 1 read-write SDIO_ENCURLIM enable current limit 20 1 read-write SDIO_REG_PD_EN power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 21 1 read-write SDIO_FORCE 1: use SW option to control SDIO_REG 0: use state machine 22 1 read-write SDIO_TIEH SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 23 1 read-write REG1P8_READY read only register for REG1P8_READY 24 1 read-only DREFL_SDIO SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 25 2 read-write DREFM_SDIO SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 27 2 read-write DREFH_SDIO SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 29 2 read-write XPD_SDIO SW option for XPD_VOOSDIO. Only active when reg_sdio_force = 1 31 1 read-write BIAS_CONF configure power register 0x80 0x20 0x00010800 BIAS_BUF_IDLE open bias buf when system in active 10 1 read-write BIAS_BUF_WAKE open bias buf when rtc in wakeup 11 1 read-write BIAS_BUF_DEEP_SLP open bias buf when rtc in deep sleep 12 1 read-write BIAS_BUF_MONITOR open bias buf when rtc in monitor state 13 1 read-write PD_CUR_DEEP_SLP xpd cur when rtc in sleep_state 14 1 read-write PD_CUR_MONITOR xpd cur when rtc in monitor state 15 1 read-write BIAS_SLEEP_DEEP_SLP bias_sleep when rtc in sleep_state 16 1 read-write BIAS_SLEEP_MONITOR bias_sleep when rtc in monitor state 17 1 read-write DBG_ATTEN_DEEP_SLP DBG_ATTEN when rtc in sleep state 18 4 read-write DBG_ATTEN_MONITOR DBG_ATTEN when rtc in monitor state 22 4 read-write ENB_SCK_XTAL ENB_SCK_XTAL 26 1 read-write INC_HEARTBEAT_REFRESH INC_HEARTBEAT_REFRESH 27 1 read-write DEC_HEARTBEAT_PERIOD DEC_HEARTBEAT_PERIOD 28 1 read-write INC_HEARTBEAT_PERIOD INC_HEARTBEAT_PERIOD 29 1 read-write DEC_HEARTBEAT_WIDTH DEC_HEARTBEAT_WIDTH 30 1 read-write RST_BIAS_I2C 31 1 read-write REG RTC/DIG regulator configuration register 0x84 0x20 0xA9002400 DIG_REG_DBIAS_SLP Configures the regulation factor for the digital system voltage regulator when the CPU is in sleep status. 8 3 read-write DIG_REG_DBIAS_WAK Configures the regulation factor for the digital system voltage regulator when the CPU is in active status. 11 3 read-write SCK_DCAP Configures the frequency of the RTC clocks. 14 8 read-write DBIAS_SLP Configures the regulation factor for the low-power voltage regulator when the CPU is in sleep status. 22 3 read-write DBIAS_WAK Configures the regulation factor for the low-power voltage regulator when the CPU is in active status. 25 3 read-write DBOOST_FORCE_PD RTC_DBOOST force power down 28 1 read-write DBOOST_FORCE_PU RTC_DBOOST force power up 29 1 read-write REGULATOR_FORCE_PD Set this bit to FPD the RTC_REG, which means decreasing its voltage to 0.8 V or lower. 30 1 read-write REGULATOR_FORCE_PU Set this bit to FPU the RTC_REG. 31 1 read-write PWC RTC power configuraiton register 0x88 0x20 0x00012925 FASTMEM_FORCE_NOISO Set this bit to disable the force isolation to the RTC fast memory. 0 1 read-write FASTMEM_FORCE_ISO Set this bit to force isolate the RTC fast memory. 1 1 read-write SLOWMEM_FORCE_NOISO Set this bit to disable the force isolation to the RTC slow memory. 2 1 read-write SLOWMEM_FORCE_ISO Set this bit to force isolate the RTC slow memory. 3 1 read-write FORCE_ISO Set this bit to force isolate the RTC peripherals. 4 1 read-write FORCE_NOISO Set this bit to disable the force isolation to the RTC peripherals. 5 1 read-write FASTMEM_FOLW_CPU Set 1 to FPD the RTC fast memory when the CPU is powered down. Set 0 to FPD the RTC fast memory when the RTC main state machine is powered down. 6 1 read-write FASTMEM_FORCE_LPD Set this bit to force not retain the RTC fast memory. 7 1 read-write FASTMEM_FORCE_LPU Set this bit to force retain the RTC fast memory. 8 1 read-write SLOWMEM_FOLW_CPU Set 1 to FPD the RTC slow memory when the CPU is powered down. Set 0 to FPD the RTC slow memory when the RTC main state machine is powered down. 9 1 read-write SLOWMEM_FORCE_LPD Set this bit to force not retain the RTC slow memory. 10 1 read-write SLOWMEM_FORCE_LPU Set this bit to force retain the RTC slow memory. 11 1 read-write FASTMEM_FORCE_PD Set this bit to FPD the RTC fast memory. 12 1 read-write FASTMEM_FORCE_PU Set this bit to FPU the RTC fast memory. 13 1 read-write FASTMEM_PD_EN Set this bit to enable PD for the RTC fast memory in sleep. 14 1 read-write SLOWMEM_FORCE_PD Set this bit to FPD the RTC slow memory. 15 1 read-write SLOWMEM_FORCE_PU Set this bit to FPU the RTC slow memory. 16 1 read-write SLOWMEM_PD_EN Set this bit to enable PD for the RTC slow memory in sleep. 17 1 read-write FORCE_PD Set this bit to FPD the RTC peripherals. 18 1 read-write FORCE_PU Set this bit to FPU the RTC peripherals. 19 1 read-write PD_EN Set this bit to enable PD for the RTC peripherals in sleep. 20 1 read-write PAD_FORCE_HOLD Set this bit the force hold the RTC GPIOs. 21 1 read-write DIG_PWC Digital system power configuraiton register 0x8C 0x20 0x00555550 LSLP_MEM_FORCE_PD Set this bit to FPD the memories in the digital system in sleep. 3 1 read-write LSLP_MEM_FORCE_PU Set this bit to FPU the memories in the digital system. 4 1 read-write ROM0_FORCE_PD ROM force power down 5 1 read-write ROM0_FORCE_PU ROM force power up 6 1 read-write INTER_RAM0_FORCE_PD internal SRAM 0 force power down 7 1 read-write INTER_RAM0_FORCE_PU internal SRAM 0 force power up 8 1 read-write INTER_RAM1_FORCE_PD internal SRAM 1 force power down 9 1 read-write INTER_RAM1_FORCE_PU internal SRAM 1 force power up 10 1 read-write INTER_RAM2_FORCE_PD internal SRAM 2 force power down 11 1 read-write INTER_RAM2_FORCE_PU internal SRAM 2 force power up 12 1 read-write INTER_RAM3_FORCE_PD internal SRAM 3 force power down 13 1 read-write INTER_RAM3_FORCE_PU internal SRAM 3 force power up 14 1 read-write INTER_RAM4_FORCE_PD internal SRAM 4 force power down 15 1 read-write INTER_RAM4_FORCE_PU internal SRAM 4 force power up 16 1 read-write WIFI_FORCE_PD Set this bit to FPD the Wi-Fi circuit. 17 1 read-write WIFI_FORCE_PU Set this bit to FPU the Wi-Fi circuit. 18 1 read-write DG_WRAP_FORCE_PD Set this bit to FPD the digital system. 19 1 read-write DG_WRAP_FORCE_PU Set this bit to FPD the DC-DC convertor in the digital system. 20 1 read-write DG_DCDC_FORCE_PD Set this bit to FPD the DC-DC convertor in the digital system. 21 1 read-write DG_DCDC_FORCE_PU Set this bit to FPU the DC-DC convertor in the digital system. 22 1 read-write DG_DCDC_PD_EN Set this bit to enable PD for the DC-DC convertor in the digital system. 23 1 read-write ROM0_PD_EN enable power down ROM in sleep 24 1 read-write INTER_RAM0_PD_EN enable power down internal SRAM 0 in sleep 25 1 read-write INTER_RAM1_PD_EN enable power down internal SRAM 1 in sleep 26 1 read-write INTER_RAM2_PD_EN enable power down internal SRAM 2 in sleep 27 1 read-write INTER_RAM3_PD_EN enable power down internal SRAM 3 in sleep 28 1 read-write INTER_RAM4_PD_EN enable power down internal SRAM 4 in sleep 29 1 read-write WIFI_PD_EN Set this bit to enable PD for the Wi-Fi circuit in sleep. 30 1 read-write DG_WRAP_PD_EN Set this bit to enable PD for the digital system in sleep. 31 1 read-write DIG_ISO Digital system ISO configuration register 0x90 0x20 0xAAAA5000 FORCE_OFF 7 1 read-write FORCE_ON 8 1 read-write DG_PAD_AUTOHOLD Indicates the auto-hold status of the digital GPIOs. 9 1 read-only CLR_DG_PAD_AUTOHOLD Se this bit to clear the auto-hold enabler for the digital GPIOs. 10 1 write-only DG_PAD_AUTOHOLD_EN Se this bit to allow the digital GPIOs to enter the autohold status. 11 1 read-write DG_PAD_FORCE_NOISO Set this bit to disable the force isolation to the digital GPIOs. 12 1 read-write DG_PAD_FORCE_ISO Set this bit to force isolate the digital GPIOs. 13 1 read-write DG_PAD_FORCE_UNHOLD Set this bit the force unhold the digital GPIOs. 14 1 read-write DG_PAD_FORCE_HOLD Set this bit the force hold the digital GPIOs. 15 1 read-write ROM0_FORCE_ISO ROM force ISO 16 1 read-write ROM0_FORCE_NOISO ROM force no ISO 17 1 read-write INTER_RAM0_FORCE_ISO internal SRAM 0 force ISO 18 1 read-write INTER_RAM0_FORCE_NOISO internal SRAM 0 force no ISO 19 1 read-write INTER_RAM1_FORCE_ISO internal SRAM 1 force ISO 20 1 read-write INTER_RAM1_FORCE_NOISO internal SRAM 1 force no ISO 21 1 read-write INTER_RAM2_FORCE_ISO internal SRAM 2 force ISO 22 1 read-write INTER_RAM2_FORCE_NOISO internal SRAM 2 force no ISO 23 1 read-write INTER_RAM3_FORCE_ISO internal SRAM 3 force ISO 24 1 read-write INTER_RAM3_FORCE_NOISO internal SRAM 3 force no ISO 25 1 read-write INTER_RAM4_FORCE_ISO internal SRAM 4 force ISO 26 1 read-write INTER_RAM4_FORCE_NOISO internal SRAM 4 force no ISO 27 1 read-write WIFI_FORCE_ISO Set this bit to force isolate the Wi-Fi circuits. 28 1 read-write WIFI_FORCE_NOISO Set this bit to disable the force isolation to the Wi-Fi circuits. 29 1 read-write DG_WRAP_FORCE_ISO Set this bit to force isolate the digital system. 30 1 read-write DG_WRAP_FORCE_NOISO Set this bit to disable the force isolation to the digital system. 31 1 read-write WDTCONFIG0 RTC watchdog configuration register 0x94 0x20 0x00013214 WDT_CHIP_RESET_WIDTH chip reset siginal pulse width 0 8 read-write WDT_CHIP_RESET_EN wdt reset whole chip enable 8 1 read-write WDT_PAUSE_IN_SLP Set this bit to pause the watchdog in sleep. 9 1 read-write WDT_APPCPU_RESET_EN enable WDT reset APP CPU 10 1 read-write WDT_PROCPU_RESET_EN Set this bit to allow the watchdog to be able to reset CPU. 11 1 read-write WDT_FLASHBOOT_MOD_EN Set this bit to enable watchdog when the chip boots from flash. 12 1 read-write WDT_SYS_RESET_LENGTH Sets the length of the system reset counter. 13 3 read-write WDT_CPU_RESET_LENGTH Sets the length of the CPU reset counter. 16 3 read-write WDT_STG3 1: enable at the interrupt stage 2: enable at the CPU stage 3: enable at the system stage 4: enable at the system and RTC stage. 19 3 read-write WDT_STG2 1: enable at the interrupt stage 2: enable at the CPU stage 3: enable at the system stage 4: enable at the system and RTC stage. 22 3 read-write WDT_STG1 1: enable at the interrupt stage 2: enable at the CPU stage 3: enable at the system stage 4: enable at the system and RTC stage. 25 3 read-write WDT_STG0 1: enable at the interrupt stage 2: enable at the CPU stage 3: enable at the system stage 4: enable at the system and RTC stage. 28 3 read-write WDT_EN Set this bit to enable the RTC watchdog. 31 1 read-write WDTCONFIG1 Configures the hold time of RTC watchdog at level 1 0x98 0x20 0x00030D40 WDT_STG0_HOLD Configures the hold time of RTC watchdog at level 1. 0 32 read-write WDTCONFIG2 Configures the hold time of RTC watchdog at level 2 0x9C 0x20 0x00013880 WDT_STG1_HOLD Configures the hold time of RTC watchdog at level 2. 0 32 read-write WDTCONFIG3 Configures the hold time of RTC watchdog at level 3 0xA0 0x20 0x00000FFF WDT_STG2_HOLD Configures the hold time of RTC watchdog at level 3. 0 32 read-write WDTCONFIG4 Configures the hold time of RTC watchdog at level 4 0xA4 0x20 0x00000FFF WDT_STG3_HOLD Configures the hold time of RTC watchdog at level 4. 0 32 read-write WDTFEED RTC watchdog SW feed configuration register 0xA8 0x20 WDT_FEED Set 1 to feed the RTC watchdog. 31 1 write-only WDTWPROTECT RTC watchdog write protection configuration register 0xAC 0x20 0x50D83AA1 WDT_WKEY Sets the write protection key of the watchdog. 0 32 read-write SWD_CONF Super watchdog configuration register 0xB0 0x20 0x04B00000 SWD_RESET_FLAG Indicates the super watchdog reset flag. 0 1 read-only SWD_FEED_INT Receiving this interrupt leads to feeding the super watchdog via SW. 1 1 read-only SWD_SIGNAL_WIDTH Adjusts the signal width sent to the super watchdog. 18 10 read-write SWD_RST_FLAG_CLR Set to reset the super watchdog reset flag. 28 1 write-only SWD_FEED Set to feed the super watchdog via SW. 29 1 write-only SWD_DISABLE Set this bit to disable super watchdog. 30 1 read-write SWD_AUTO_FEED_EN Set this bit to enable automatic watchdog feeding upon interrupts. 31 1 read-write SWD_WPROTECT Super watchdog write protection configuration register 0xB4 0x20 0x8F1D312A SWD_WKEY Sets the write protection key of the super watchdog. 0 32 read-write SW_CPU_STALL CPU stall configuration register 0xB8 0x20 SW_STALL_APPCPU_C1 {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU 20 6 read-write SW_STALL_PROCPU_C1 Set this bit to allow the SW to be able to send the CPU into stalling. 26 6 read-write STORE4 Reservation register 4 0xBC 0x20 SCRATCH4 Reservation register 4. 0 32 read-write STORE5 Reservation register 5 0xC0 0x20 SCRATCH5 Reservation register 5. 0 32 read-write STORE6 Reservation register 6 0xC4 0x20 SCRATCH6 Reservation register 6. 0 32 read-write STORE7 Reservation register 7 0xC8 0x20 SCRATCH7 Reservation register 7. 0 32 read-write LOW_POWER_ST RTC main state machine status register 0xCC 0x20 XPD_ROM0 rom0 power down 0 1 read-only XPD_DIG_DCDC External DCDC power down 2 1 read-only PERI_ISO rtc peripheral iso 3 1 read-only XPD_RTC_PERI rtc peripheral power down 4 1 read-only WIFI_ISO wifi iso 5 1 read-only XPD_WIFI wifi wrap power down 6 1 read-only DIG_ISO digital wrap iso 7 1 read-only XPD_DIG digital wrap power down 8 1 read-only TOUCH_STATE_START touch should start to work 9 1 read-only TOUCH_STATE_SWITCH touch is about to working. Switch rtc main state 10 1 read-only TOUCH_STATE_SLP touch is in sleep state 11 1 read-only TOUCH_STATE_DONE touch is done 12 1 read-only COCPU_STATE_START ulp/cocpu should start to work 13 1 read-only COCPU_STATE_SWITCH ulp/cocpu is about to working. Switch rtc main state 14 1 read-only COCPU_STATE_SLP ulp/cocpu is in sleep state 15 1 read-only COCPU_STATE_DONE ulp/cocpu is done 16 1 read-only MAIN_STATE_XTAL_ISO no use any more 17 1 read-only MAIN_STATE_PLL_ON rtc main state machine is in states that pll should be running 18 1 read-only RDY_FOR_WAKEUP Indicates the RTC is ready to be triggered by any wakeup source. 19 1 read-only MAIN_STATE_WAIT_END rtc main state machine has been waited for some cycles 20 1 read-only IN_WAKEUP_STATE rtc main state machine is in the states of wakeup process 21 1 read-only IN_LOW_POWER_STATE rtc main state machine is in the states of low power 22 1 read-only MAIN_STATE_IN_WAIT_8M rtc main state machine is in wait 8m state 23 1 read-only MAIN_STATE_IN_WAIT_PLL rtc main state machine is in wait pll state 24 1 read-only MAIN_STATE_IN_WAIT_XTL rtc main state machine is in wait xtal state 25 1 read-only MAIN_STATE_IN_SLP rtc main state machine is in sleep state 26 1 read-only MAIN_STATE_IN_IDLE rtc main state machine is in idle state 27 1 read-only MAIN_STATE rtc main state machine status 28 4 read-only DIAG0 debug register 0xD0 0x20 LOW_POWER_DIAG1 0 32 read-only PAD_HOLD Configures the hold options for RTC GPIOs 0xD4 0x20 TOUCH_PAD0_HOLD Sets the touch GPIO 0 to hold. 0 1 read-write TOUCH_PAD1_HOLD Sets the touch GPIO 1 to hold. 1 1 read-write TOUCH_PAD2_HOLD Sets the touch GPIO 2 to hold. 2 1 read-write TOUCH_PAD3_HOLD Sets the touch GPIO 3 to hold. 3 1 read-write TOUCH_PAD4_HOLD Sets the touch GPIO 4 to hold. 4 1 read-write TOUCH_PAD5_HOLD Sets the touch GPIO 5 to hold. 5 1 read-write TOUCH_PAD6_HOLD Sets the touch GPIO 6 to hold. 6 1 read-write TOUCH_PAD7_HOLD Sets the touch GPIO 7 to hold. 7 1 read-write TOUCH_PAD8_HOLD Sets the touch GPIO 8 to hold. 8 1 read-write TOUCH_PAD9_HOLD Sets the touch GPIO 9 to hold. 9 1 read-write TOUCH_PAD10_HOLD Sets the touch GPIO 10 to hold. 10 1 read-write TOUCH_PAD11_HOLD Sets the touch GPIO 11 to hold. 11 1 read-write TOUCH_PAD12_HOLD Sets the touch GPIO 12 to hold. 12 1 read-write TOUCH_PAD13_HOLD Sets the touch GPIO 13 to hold. 13 1 read-write TOUCH_PAD14_HOLD Sets the touch GPIO 14 to hold. 14 1 read-write X32P_HOLD Sets the x32p to hold. 15 1 read-write X32N_HOLD Sets the x32n to hold. 16 1 read-write PDAC1_HOLD Sets the pdac1 to hold. 17 1 read-write PDAC2_HOLD Sets the pdac2 to hold. 18 1 read-write PAD19_HOLD Sets the RTG GPIO 19 to hold. 19 1 read-write PAD20_HOLD Sets the RTG GPIO 20 to hold. 20 1 read-write PAD21_HOLD Sets the RTG GPIO 21 to hold. 21 1 read-write DIG_PAD_HOLD Configures the hold option for digital GPIOs 0xD8 0x20 DIG_PAD_HOLD Set GPIO 21 to GPIO 45 to hold. (See bitmap to locate any GPIO). 0 32 read-write EXT_WAKEUP1 EXT1 wakeup configuration register 0xDC 0x20 SEL Selects a RTC GPIO to be the EXT1 wakeup source. 0 22 read-write STATUS_CLR Clears the EXT1 wakeup status. 22 1 write-only EXT_WAKEUP1_STATUS EXT1 wakeup source register 0xE0 0x20 EXT_WAKEUP1_STATUS Indicates the EXT1 wakeup status. 0 22 read-only BROWN_OUT Brownout configuration register 0xE4 0x20 0x03FF2FF1 BROWN_OUT2_ENA Enables the brown_out2 to initiate a chip reset. 0 1 read-write INT_WAIT Configures the waiting cycle before sending an interrupt. 4 10 read-write CLOSE_FLASH_ENA Set this bit to enable PD the flash when a brown-out happens. 14 1 read-write PD_RF_ENA Set this bit to enable PD the RF circuits when a brown-out happens. 15 1 read-write RST_WAIT Configures the waiting cycle before the reset after a brown-out. 16 10 read-write RST_ENA Enables to reset brown-out. 26 1 read-write RST_SEL Selects the reset type when a brown-out happens. 1: chip reset 0: system reset. 27 1 read-write CNT_CLR Clears the brown-out counter. 29 1 write-only ENA Set this bit to enable brown-out detection. 30 1 read-write DET Indicates the status of the brown-out signal. 31 1 read-only TIME_LOW1 Stores the lower 32 bits of RTC timer 1 0xE8 0x20 TIMER_VALUE1_LOW Stores the lower 32 bits of RTC timer 1. 0 32 read-only TIME_HIGH1 Stores the higher 16 bits of RTC timer 1 0xEC 0x20 TIMER_VALUE1_HIGH Stores the higher 16 bits of RTC timer. 0 16 read-only XTAL32K_CLK_FACTOR Configures the divider factor for the backup clock of 32 kHz crystal oscillator 0xF0 0x20 XTAL32K_CLK_FACTOR Configures the divider factor for the 32 kHz crystal oscillator. 0 32 read-write XTAL32K_CONF 32 kHz crystal oscillator configuration register 0xF4 0x20 0x0FF00000 XTAL32K_RETURN_WAIT Defines the waiting cycles before returning to the normal 32 kHz crystal oscillator. 0 4 read-write XTAL32K_RESTART_WAIT Defines the maximum waiting cycle before restarting the 32 kHz crystal oscillator. 4 16 read-write XTAL32K_WDT_TIMEOUT Defines the maximum waiting period for clock detection. If no clock is detected after this period, the 32 kHz crystal oscillator can be regarded as dead. 20 8 read-write XTAL32K_STABLE_THRES Defines the maximum allowed restarting period, within which the 32 kHz crystal oscillator can be regarded as stable. 28 4 read-write ULP_CP_TIMER Configure coprocessor timer 0xF8 0x20 ULP_CP_PC_INIT ULP coprocessor PC initial address 0 11 read-write ULP_CP_GPIO_WAKEUP_ENA Enable the option of ULP coprocessor woken up by RTC GPIO 29 1 read-write ULP_CP_GPIO_WAKEUP_CLR Disable the option of ULP coprocessor woken up by RTC GPIO 30 1 write-only ULP_CP_SLP_TIMER_EN ULP coprocessor timer enable bit. 0: Disable hardware Timer. 1: Enable hardware timer 31 1 read-write ULP_CP_CTRL ULP-FSM configuration register 0xFC 0x20 0x00100200 ULP_CP_MEM_ADDR_INIT 0 11 read-write ULP_CP_MEM_ADDR_SIZE 11 11 read-write ULP_CP_MEM_OFFSET_CLR 22 1 write-only ULP_CP_CLK_FO ULP-FSM clock force on 28 1 read-write ULP_CP_RESET ULP-FSM clock software reset 29 1 read-write ULP_CP_FORCE_START_TOP Write 1 to start ULP-FSM by software 30 1 read-write ULP_CP_START_TOP Write 1 to start ULP-FSM 31 1 read-write COCPU_CTRL ULP-RISCV configuration register 0x100 0x20 0x008A0810 COCPU_CLK_FO ULP-RISCV clock force on 0 1 read-write COCPU_START_2_RESET_DIS Time from ULP-RISCV startup to pull down reset 1 6 read-write COCPU_START_2_INTR_EN Time from ULP-RISCV startup to send out RISCV_START_INT interrupt 7 6 read-write COCPU_SHUT Shut down ULP-RISCV 13 1 read-write COCPU_SHUT_2_CLK_DIS Time from shut down ULP-RISCV to disable clock 14 8 read-write COCPU_SHUT_RESET_EN This bit is used to reset ULP-RISCV 22 1 read-write COCPU_SEL 0: select ULP-RISCV. 1: select ULP-FSM 23 1 read-write COCPU_DONE_FORCE 0: select ULP-FSM DONE signal. 1: select ULP-RISCV DONE signal 24 1 read-write COCPU_DONE DONE signal. Write 1 to this bit, ULP-RISCV will go to HALT and the timer starts counting 25 1 read-write COCPU_SW_INT_TRIGGER Trigger ULP-RISCV register interrupt 26 1 write-only TOUCH_CTRL1 Touch control register 0x104 0x20 0x10000100 TOUCH_SLEEP_CYCLES Set sleep cycles for touch timer. 0 16 read-write TOUCH_MEAS_NUM Configure measurement length (in 8 MHz), i.e., charge/discharge times. 16 16 read-write TOUCH_CTRL2 Touch control register 0x108 0x20 0x000840CC TOUCH_DRANGE TOUCH attenuation. 2 2 read-write TOUCH_DREFL TOUCH reference voltage low. 0: 0.5 V 1: 0.6 V 2: 0.7 V 3: 0.8 V. 4 2 read-write TOUCH_DREFH TOUCH reference voltage high. 0: 2.4 V 1: 2.5 V 2: 2.6 V 3: 2.7 V. 6 2 read-write TOUCH_XPD_BIAS TOUCH BIAS power switch. 8 1 read-write TOUCH_REFC Touch pad 0 reference capacitance. 9 3 read-write TOUCH_DBIAS 0: Use bandgap bias. 1: Use self bias. 12 1 read-write TOUCH_SLP_TIMER_EN Touch timer enable bit. 13 1 read-write TOUCH_START_FSM_EN 0: TOUCH_START and TOUCH_XPD are controlled by soft- ware. 1: TOUCH_START and TOUCH_XPD are controlled by the Touch FSM. 14 1 read-write TOUCH_START_EN 1: Start the Touch FSM, only valid when RTC_CNTL_TOUCH_START_FORCE = 1. 15 1 read-write TOUCH_START_FORCE 0: Start the Touch FSM by timer. 1: Start Touch FSM by software. 16 1 read-write TOUCH_XPD_WAIT The waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD. 17 8 read-write TOUCH_SLP_CYC_DIV When a touch pad is active, sleep cycle could be divided by this number. 25 2 read-write TOUCH_TIMER_FORCE_DONE Force touch timer done. 27 2 read-write TOUCH_RESET Reset TOUCH FSM via software. 29 1 read-write TOUCH_CLK_FO Touch clock force on. 30 1 read-write TOUCH_CLKGATE_EN Touch clock enable bit. 31 1 read-write TOUCH_SCAN_CTRL Configure touch scan settings 0x10C 0x20 0xF0000102 TOUCH_DENOISE_RES Denoise resolution. 0: 12-bit; 1: 10-bit; 2: 8-bit; 3: 4-bit. 0 2 read-write TOUCH_DENOISE_EN Touch pad 0 will be used to denoise. 2 1 read-write TOUCH_INACTIVE_CONNECTION Inactive touch pads connect to 0: HighZ, 1: GND. 8 1 read-write TOUCH_SHIELD_PAD_EN Touch pad 14 will be used as shield_pad. 9 1 read-write TOUCH_SCAN_PAD_MAP Pad enable map for touch scan mode. 10 15 read-write TOUCH_BUFDRV Touch 14 buffer driver strength. 25 3 read-write TOUCH_OUT_RING Select out one pad as guard_ring. 28 4 read-write TOUCH_SLP_THRES Configure the settings of touch sleep pad 0x110 0x20 0x78000000 TOUCH_SLP_TH Set the threshold for touch sleep pad. 0 22 read-write TOUCH_SLP_APPROACH_EN Enable the proximity mode of touch sleep pad. 26 1 read-write TOUCH_SLP_PAD Select sleep pad. 27 5 read-write TOUCH_APPROACH Configure touch approach settings 0x114 0x20 0x50000000 TOUCH_SLP_CHANNEL_CLR Clear touch sleep channel. 23 1 write-only MEAS_TIME Set the total measurement times for the pads in proximity mode. Range: 0 – 255. 24 8 read-write TOUCH_FILTER_CTRL Configure touch filter settings 0x118 0x20 0x96AA8800 TOUCH_SMOOTH_LVL 0: Raw data. 1: IIR1/2. 2: IIR1/4. 3: IIR1/8. 9 2 read-write TOUCH_JITTER_STEP Touch jitter step. Range: 0 – 15. 11 4 read-write TOUCH_NEG_NOISE_LIMIT Negative threshold counter limit. 15 4 read-write TOUCH_NEG_NOISE_THRES Negative noise threshold. 19 2 read-write TOUCH_NOISE_THRES Active noise threshold. 21 2 read-write TOUCH_HYSTERESIS Touch hysteresis. 23 2 read-write TOUCH_DEBOUNCE Debounce counter. 25 3 read-write TOUCH_FILTER_MODE Set filter mode. 0: IIR 1/2; 1: IIR 1/4; 2: IIR 1/8; 3: IIR 1/16; 4: IIR 1/32; 5: IIR 1/64; 6: IIR 1/128; 7: Jitter. 28 3 read-write TOUCH_FILTER_EN Enable touch filter. 31 1 read-write USB_CONF configure usb control register 0x11C 0x20 USB_VREFH 0 2 read-write USB_VREFL 2 2 read-write USB_VREF_OVERRIDE 4 1 read-write USB_PAD_PULL_OVERRIDE 5 1 read-write USB_DP_PULLUP 6 1 read-write USB_DP_PULLDOWN 7 1 read-write USB_DM_PULLUP 8 1 read-write USB_DM_PULLDOWN 9 1 read-write USB_PULLUP_VALUE 10 1 read-write USB_PAD_ENABLE_OVERRIDE 11 1 read-write USB_PAD_ENABLE 12 1 read-write USB_TXM 13 1 read-write USB_TXP 14 1 read-write USB_TX_EN 15 1 read-write USB_TX_EN_OVERRIDE 16 1 read-write USB_RESET_DISABLE 17 1 read-write IO_MUX_RESET_DISABLE 18 1 read-write TOUCH_TIMEOUT_CTRL Configure touch timeout settings 0x120 0x20 0x007FFFFF TOUCH_TIMEOUT_NUM Set touch timeout threshold. 0 22 read-write TOUCH_TIMEOUT_EN Enable touch timeout. 22 1 read-write SLP_REJECT_CAUSE Stores the reject-to-sleep cause. 0x124 0x20 REJECT_CAUSE Stores the reject-to-sleep cause. 0 17 read-only OPTIONS1 RTC option register 0x128 0x20 FORCE_DOWNLOAD_BOOT Set this bit to force the chip to boot from the download mode. 0 1 read-write SLP_WAKEUP_CAUSE Stores the sleep-to-wakeup cause. 0x12C 0x20 WAKEUP_CAUSE Stores the wakeup cause. 0 17 read-only ULP_CP_TIMER_1 Configure sleep cycle of the timer 0x130 0x20 0x0000C800 ULP_CP_TIMER_SLP_CYCLE Set sleep cycles for ULP coprocessor timer 8 24 read-write DATE 0x138 0x20 0x01906191 CNTL_DATE 0 28 read-write RTC_I2C Low-power I2C (Inter-Integrated Circuit) Controller RTC_I2C 0x3F408C00 0x0 0x7C registers SCL_LOW Configure the low level width of SCL 0x0 0x20 0x00000100 PERIOD This register is used to configure how many clock cycles SCL remains low. 0 20 read-write CTRL Transmission setting 0x4 0x20 SDA_FORCE_OUT SDA output mode. 0: open drain. 1: push pull. 0 1 read-write SCL_FORCE_OUT SCL output mode. 0: open drain. 1: push pull. 1 1 read-write MS_MODE Set this bit to configure RTC I²C as a master. 2 1 read-write TRANS_START Set this bit to 1, RTC I2C starts sending data. 3 1 read-write TX_LSB_FIRST This bit is used to control the sending mode. 0: send data from the most significant bit. 1: send data from the least significant bit. 4 1 read-write RX_LSB_FIRST This bit is used to control the storage mode for received data. 0: receive data from the most significant bit. 1: receive data from the least significant bit. 5 1 read-write CLK_GATE_EN RTC I²C controller clock gate. 29 1 read-write RESET RTC I²C software reset. 30 1 read-write CLK_EN rtc i2c reg clk gating 31 1 read-write STATUS RTC I2C status 0x8 0x20 ACK_REC The received ACK value. 0: ACK. 1: NACK. 0 1 read-only SLAVE_RW 0: master writes to slave. 1: master reads from slave. 1 1 read-only ARB_LOST When the RTC I2C loses control of SCL line, the register changes to 1. 2 1 read-only BUS_BUSY 0: RTC I2C bus is in idle state. 1: RTC I2C bus is busy transferring data. 3 1 read-only SLAVE_ADDRESSED When the address sent by the master matches the address of the slave, then this bit will be set. 4 1 read-only BYTE_TRANS This field changes to 1 when one byte is transferred. 5 1 read-only OP_CNT Indicate which operation is working. 6 2 read-only SHIFT shifter content 16 8 read-only SCL_MAIN_STATE_LAST i2c last main status 24 3 read-only SCL_STATE_LAST scl last status 28 3 read-only TO Configure RTC I2C timeout 0xC 0x20 0x00010000 TIME_OUT Timeout threshold 0 20 read-write SLAVE_ADDR Configure slave address 0x10 0x20 SLAVE_ADDR slave address 0 15 read-write ADDR_10BIT_EN This field is used to enable the slave 10-bit addressing mode. 31 1 read-write SCL_HIGH Configure the high level width of SCL 0x14 0x20 0x00000100 PERIOD This register is used to configure how many cycles SCL remains high. 0 20 read-write SDA_DUTY Configure the SDA hold time after a negative SCL edge 0x18 0x20 0x00000010 NUM The number of clock cycles between the SDA switch and the falling edge of SCL. 0 20 read-write SCL_START_PERIOD Configure the delay between the SDA and SCL negative edge for a start condition 0x1C 0x20 0x00000008 SCL_START_PERIOD Number of clock cycles to wait after generating a start condition. 0 20 read-write SCL_STOP_PERIOD Configure the delay between SDA and SCL positive edge for a stop condition 0x20 0x20 0x00000008 SCL_STOP_PERIOD Number of clock cycles to wait before generating a stop condition. 0 20 read-write INT_CLR Clear RTC I2C interrupt 0x24 0x20 SLAVE_TRAN_COMP_INT_CLR RTC_I2C_SLAVE_TRAN_COMP_INT interrupt clear bit 0 1 write-only ARBITRATION_LOST_INT_CLR RTC_I2C_ARBITRATION_LOST_INT interrupt clear bit 1 1 write-only MASTER_TRAN_COMP_INT_CLR RTC_I2C_MASTER_TRAN_COMP_INT interrupt clear bit 2 1 write-only TRANS_COMPLETE_INT_CLR RTC_I2C_TRANS_COMPLETE_INT interrupt clear bit 3 1 write-only TIME_OUT_INT_CLR RTC_I2C_TIME_OUT_INT interrupt clear bit 4 1 write-only ACK_ERR_INT_CLR RTC_I2C_ACK_ERR_INT interrupt clear bit 5 1 write-only RX_DATA_INT_CLR RTC_I2C_RX_DATA_INT interrupt clear bit 6 1 write-only TX_DATA_INT_CLR RTC_I2C_TX_DATA_INT interrupt clear bit 7 1 write-only DETECT_START_INT_CLR RTC_I2C_DETECT_START_INT interrupt clear bit 8 1 write-only INT_RAW RTC I2C raw interrupt 0x28 0x20 SLAVE_TRAN_COMP_INT_RAW RTC_I2C_SLAVE_TRAN_COMP_INT interrupt raw bit 0 1 read-only ARBITRATION_LOST_INT_RAW RTC_I2C_ARBITRATION_LOST_INT interrupt raw bit 1 1 read-only MASTER_TRAN_COMP_INT_RAW RTC_I2C_MASTER_TRAN_COMP_INT interrupt raw bit 2 1 read-only TRANS_COMPLETE_INT_RAW RTC_I2C_TRANS_COMPLETE_INT interrupt raw bit 3 1 read-only TIME_OUT_INT_RAW RTC_I2C_TIME_OUT_INT interrupt raw bit 4 1 read-only ACK_ERR_INT_RAW RTC_I2C_ACK_ERR_INT interrupt raw bit 5 1 read-only RX_DATA_INT_RAW RTC_I2C_RX_DATA_INT interrupt raw bit 6 1 read-only TX_DATA_INT_RAW RTC_I2C_TX_DATA_INT interrupt raw bit 7 1 read-only DETECT_START_INT_RAW RTC_I2C_DETECT_START_INT interrupt raw bit 8 1 read-only INT_ST RTC I2C interrupt status 0x2C 0x20 SLAVE_TRAN_COMP_INT_ST RTC_I2C_SLAVE_TRAN_COMP_INT interrupt status bit 0 1 read-only ARBITRATION_LOST_INT_ST RTC_I2C_ARBITRATION_LOST_INT interrupt status bit 1 1 read-only MASTER_TRAN_COMP_INT_ST RTC_I2C_MASTER_TRAN_COMP_INT interrupt status bit 2 1 read-only TRANS_COMPLETE_INT_ST RTC_I2C_TRANS_COMPLETE_INT interrupt status bit 3 1 read-only TIME_OUT_INT_ST RTC_I2C_TIME_OUT_INT interrupt status bit 4 1 read-only ACK_ERR_INT_ST RTC_I2C_ACK_ERR_INT interrupt status bit 5 1 read-only RX_DATA_INT_ST RTC_I2C_RX_DATA_INT interrupt status bit 6 1 read-only TX_DATA_INT_ST RTC_I2C_TX_DATA_INT interrupt status bit 7 1 read-only DETECT_START_INT_ST RTC_I2C_DETECT_START_INT interrupt status bit 8 1 read-only INT_ENA Enable RTC I2C interrupt 0x30 0x20 SLAVE_TRAN_COMP_INT_ENA RTC_I2C_SLAVE_TRAN_COMP_INT interrupt enable bit 0 1 read-write ARBITRATION_LOST_INT_ENA RTC_I2C_ARBITRATION_LOST_INT interrupt enable bit 1 1 read-write MASTER_TRAN_COMP_INT_ENA RTC_I2C_MASTER_TRAN_COMP_INT interrupt enable bit 2 1 read-write TRANS_COMPLETE_INT_ENA RTC_I2C_TRANS_COMPLETE_INT interrupt enable bit 3 1 read-write TIME_OUT_INT_ENA RTC_I2C_TIME_OUT_INT interrupt enable bit 4 1 read-write ACK_ERR_INT_ENA RTC_I2C_ACK_ERR_INT interrupt enable bit 5 1 read-write RX_DATA_INT_ENA RTC_I2C_RX_DATA_INT interrupt enable bit 6 1 read-write TX_DATA_INT_ENA RTC_I2C_TX_DATA_INT interrupt enable bit 7 1 read-write DETECT_START_INT_ENA RTC_I2C_DETECT_START_INT interrupt enable bit 8 1 read-write DATA RTC I2C read data 0x34 0x20 RDATA Data received 0 8 read-only SLAVE_TX_DATA The data sent by slave 8 8 read-write DONE RTC I2C transmission is done. 31 1 read-only 16 0x4 0-15 CMD%s RTC I2C Command %s 0x38 0x20 0x00000903 COMMAND Content of command 0. For more information, please refer to the register I2C_COMD0_REG in Chapter I²C Controller 0 14 read-write COMMAND_DONE When command 0 is done, this bit changes to 1. 31 1 read-only DATE Version control register 0xFC 0x20 0x01905310 DATE Version control register 0 28 read-write SENS SENS Peripheral SENS 0x3F408800 0x0 0x110 registers SAR_READER1_CTRL RTC ADC1 data and sampling control 0x0 0x20 0x20040002 SAR1_CLK_DIV Clock divider. 0 8 read-write SAR1_CLK_GATED 18 1 read-write SAR1_SAMPLE_NUM 19 8 read-write SAR1_DATA_INV Invert SAR ADC1 data. 28 1 read-write SAR1_INT_EN Enable SAR ADC1 to send out interrupt. 29 1 read-write SAR_READER1_STATUS saradc1 status for debug 0x4 0x20 SAR1_READER_STATUS 0 32 read-only SAR_MEAS1_CTRL1 Configure RTC ADC1 controller 0x8 0x20 RTC_SARADC_RESET SAR ADC software reset. 22 1 read-write RTC_SARADC_CLKGATE_EN Enable bit of SAR ADC clock gate. 23 1 read-write FORCE_XPD_AMP 24 2 read-write AMP_RST_FB_FORCE 26 2 read-write AMP_SHORT_REF_FORCE 28 2 read-write AMP_SHORT_REF_GND_FORCE 30 2 read-write SAR_MEAS1_CTRL2 Control RTC ADC1 conversion and status 0xC 0x20 MEAS1_DATA_SAR SAR ADC1 data 0 16 read-only MEAS1_DONE_SAR Indicate SAR ADC1 conversion is done. 16 1 read-only MEAS1_START_SAR SAR ADC1 controller (in RTC) starts conversion, active only when SENS_MEAS1_START_FORCE = 1. 17 1 read-write MEAS1_START_FORCE 1: SAR ADC1 controller (in RTC) is started by software. 0: SAR ADC1 controller is started by ULP coprocessor. 18 1 read-write SAR1_EN_PAD SAR ADC1 pad enable bitmap, active only when SENS_SAR1_EN_PAD_FORCE = 1. 19 12 read-write SAR1_EN_PAD_FORCE 1: SAR ADC1 pad enable bitmap is controlled by software. 0: SAR ADC1 pad enable bitmap is controlled by ULP coprocessor. 31 1 read-write SAR_MEAS1_MUX Select the controller for SAR ADC1 0x10 0x20 SAR1_DIG_FORCE 1: SAR ADC1 controlled by DIG ADC1 CTRL 31 1 read-write SAR_ATTEN1 Configure SAR ADC1 attenuation 0x14 0x20 0xFFFFFFFF SAR1_ATTEN 2-bit attenuation for each pad. [1:0] is used for channel 0, [3:2] is used for channel 1, etc. 0 32 read-write SAR_AMP_CTRL1 AMP control 0x18 0x20 0x000A000A SAR_AMP_WAIT1 0 16 read-write SAR_AMP_WAIT2 16 16 read-write SAR_AMP_CTRL2 AMP control 0x1C 0x20 0x000A0000 SAR1_DAC_XPD_FSM_IDLE 0 1 read-write XPD_SAR_AMP_FSM_IDLE 1 1 read-write AMP_RST_FB_FSM_IDLE 2 1 read-write AMP_SHORT_REF_FSM_IDLE 3 1 read-write AMP_SHORT_REF_GND_FSM_IDLE 4 1 read-write XPD_SAR_FSM_IDLE 5 1 read-write SAR_RSTB_FSM_IDLE 6 1 read-write SAR_AMP_WAIT3 16 16 read-write SAR_AMP_CTRL3 AMP control register 0x20 0x20 0x007338F3 SAR1_DAC_XPD_FSM Control of DAC. 4’b0010: disable DAC. 4’b0000: power up DAC by FSM. 4’b0011: power up DAC by software. 0 4 read-write XPD_SAR_AMP_FSM 4 4 read-write AMP_RST_FB_FSM 8 4 read-write AMP_SHORT_REF_FSM 12 4 read-write AMP_SHORT_REF_GND_FSM 16 4 read-write XPD_SAR_FSM 20 4 read-write SAR_RSTB_FSM 24 4 read-write SAR_READER2_CTRL RTC ADC2 data and sampling control 0x24 0x20 0x40050002 SAR2_CLK_DIV clock divider 0 8 read-write SAR2_WAIT_ARB_CYCLE wait arbit stable after sar_done 16 2 read-write SAR2_CLK_GATED 18 1 read-write SAR2_SAMPLE_NUM 19 8 read-write SAR2_DATA_INV Invert SAR ADC2 data 29 1 read-write SAR2_INT_EN enable saradc2 to send out interrupt 30 1 read-write SAR_READER2_STATUS saradc2 status for debug 0x28 0x20 SAR2_READER_STATUS 0 32 read-only SAR_MEAS2_CTRL1 configure rtc saradc2 0x2C 0x20 0x07020200 SAR2_CNTL_STATE saradc2_cntl_fsm 0 3 read-only SAR2_PWDET_CAL_EN rtc control pwdet enable 3 1 read-write SAR2_PKDET_CAL_EN rtc control pkdet enable 4 1 read-write SAR2_EN_TEST SAR2_EN_TEST 5 1 read-write SAR2_RSTB_FORCE 6 2 read-write SAR2_STANDBY_WAIT 8 8 read-write SAR2_RSTB_WAIT 16 8 read-write SAR2_XPD_WAIT 24 8 read-write SAR_MEAS2_CTRL2 Control RTC ADC2 conversion and status 0x30 0x20 MEAS2_DATA_SAR SAR ADC2 data. 0 16 read-only MEAS2_DONE_SAR Indicate SAR ADC2 conversion is done. 16 1 read-only MEAS2_START_SAR SAR ADC2 controller (in RTC) starts conversion, active only when SENS_MEAS2_START_FORCE = 1. 17 1 read-write MEAS2_START_FORCE 1: SAR ADC2 controller (in RTC) is started by software. 0: SAR ADC2 controller is started by ULP coprocessor. 18 1 read-write SAR2_EN_PAD SAR ADC2 pad enable bitmap, active only whenSENS_SAR2_EN_PAD_FORCE = 1. 19 12 read-write SAR2_EN_PAD_FORCE 1: SAR ADC2 pad enable bitmap is controlled by software. 0: SAR ADC2 pad enable bitmap is controlled by ULP coprocessor. 31 1 read-write SAR_MEAS2_MUX Select the controller for SAR ADC2 0x34 0x20 SAR2_PWDET_CCT SAR2_PWDET_CCT, PA power detector capacitance tuning. 28 3 read-write SAR2_RTC_FORCE In sleep, force to use RTC to control ADC. 31 1 read-write SAR_ATTEN2 Configure SAR ADC2 attenuation 0x38 0x20 0xFFFFFFFF SAR2_ATTEN 2-bit attenuation for each pad. [1:0] is used for channel 0, [3:2] is used for channel 1, etc. 0 32 read-write SAR_POWER_XPD_SAR configure saradc’s power by sw 0x3C 0x20 FORCE_XPD_SAR 29 2 read-write SARCLK_EN 31 1 read-write SAR_SLAVE_ADDR1 Configure slave addresses 0-1 of RTC I2C 0x40 0x20 I2C_SLAVE_ADDR1 RTC I2C slave address 1 0 11 read-write I2C_SLAVE_ADDR0 RTC I2C slave address 0 11 11 read-write MEAS_STATUS 22 8 read-only SAR_SLAVE_ADDR2 Configure slave addresses 2-3 of RTC I2C 0x44 0x20 I2C_SLAVE_ADDR3 RTC I2C slave address 3 0 11 read-write I2C_SLAVE_ADDR2 RTC I2C slave address 2 11 11 read-write SAR_SLAVE_ADDR3 Configure slave addresses 4-5 of RTC I2C 0x48 0x20 I2C_SLAVE_ADDR5 RTC I2C slave address 5 0 11 read-write I2C_SLAVE_ADDR4 RTC I2C slave address 4 11 11 read-write SAR_SLAVE_ADDR4 Configure slave addresses 6-7 of RTC I2C 0x4C 0x20 I2C_SLAVE_ADDR7 RTC I2C slave address 7 0 11 read-write I2C_SLAVE_ADDR6 RTC I2C slave address 6 11 11 read-write SAR_TSENS_CTRL Temperature sensor data control 0x50 0x20 0x00019000 TSENS_OUT Temperature sensor data out. 0 8 read-only TSENS_READY Indicate temperature sensor out ready. 8 1 read-only TSENS_INT_EN Enable temperature sensor to send out interrupt. 12 1 read-write TSENS_IN_INV Invert temperature sensor data. 13 1 read-write TSENS_CLK_DIV Temperature sensor clock divider. 14 8 read-write TSENS_POWER_UP Temperature sensor power up. 22 1 read-write TSENS_POWER_UP_FORCE 1: dump out and power up controlled by software. 0: by FSM. 23 1 read-write TSENS_DUMP_OUT Temperature sensor dump out only active when SENS_TSENS_POWER_UP_FORCE = 1. 24 1 read-write SAR_TSENS_CTRL2 Temperature sensor control 0x54 0x20 0x00004002 TSENS_XPD_WAIT 0 12 read-write TSENS_XPD_FORCE 12 2 read-write TSENS_CLK_INV 14 1 read-write TSENS_CLKGATE_EN Enable temperature sensor clock. 15 1 read-write TSENS_RESET Reset temperature sensor. 16 1 read-write SAR_I2C_CTRL Configure RTC I2C transmission 0x58 0x20 SAR_I2C_CTRL RTC I2C control data. Active only when SENS_SAR_I2C_START_FORCE = 1. 0 28 read-write SAR_I2C_START Start RTC I2C. Active only when SENS_SAR_I2C_START_FORCE = 1 28 1 read-write SAR_I2C_START_FORCE 0: RTC I2C started by FSM. 1: RTC I2C started by software. 29 1 read-write SAR_TOUCH_CONF Touch sensor configuration register 0x5C 0x20 0xFFF07FFF TOUCH_OUTEN Enable touch controller output. 0 15 read-write TOUCH_STATUS_CLR Clear all touch active status. 15 1 write-only TOUCH_DATA_SEL 0 and 1: touch_raw_data; 2: base_line; 3: touch_smooth_data. 16 2 read-write TOUCH_DENOISE_END Touch denoise done. 18 1 read-only TOUCH_UNIT_END Indicate the completion of sampling. 19 1 read-only TOUCH_APPROACH_PAD2 Indicate which pad is selected as proximity pad2 20 4 read-write TOUCH_APPROACH_PAD1 Indicate which pad is selected as proximity pad1 24 4 read-write TOUCH_APPROACH_PAD0 Indicate which pad is selected as proximity pad0 28 4 read-write SAR_TOUCH_THRES1 Finger threshold for touch pad 1 0x60 0x20 TOUCH_OUT_TH1 Finger threshold for touch pad 1 0 22 read-write SAR_TOUCH_THRES2 Finger threshold for touch pad 2 0x64 0x20 TOUCH_OUT_TH2 Finger threshold for touch pad 2 0 22 read-write SAR_TOUCH_THRES3 Finger threshold for touch pad 3 0x68 0x20 TOUCH_OUT_TH3 Finger threshold for touch pad 3 0 22 read-write SAR_TOUCH_THRES4 Finger threshold for touch pad 4 0x6C 0x20 TOUCH_OUT_TH4 Finger threshold for touch pad 4 0 22 read-write SAR_TOUCH_THRES5 Finger threshold for touch pad 5 0x70 0x20 TOUCH_OUT_TH5 Finger threshold for touch pad 5 0 22 read-write SAR_TOUCH_THRES6 Finger threshold for touch pad 6 0x74 0x20 TOUCH_OUT_TH6 Finger threshold for touch pad 6 0 22 read-write SAR_TOUCH_THRES7 Finger threshold for touch pad 7 0x78 0x20 TOUCH_OUT_TH7 Finger threshold for touch pad 7 0 22 read-write SAR_TOUCH_THRES8 Finger threshold for touch pad 8 0x7C 0x20 TOUCH_OUT_TH8 Finger threshold for touch pad 8 0 22 read-write SAR_TOUCH_THRES9 Finger threshold for touch pad 9 0x80 0x20 TOUCH_OUT_TH9 Finger threshold for touch pad 9 0 22 read-write SAR_TOUCH_THRES10 Finger threshold for touch pad 10 0x84 0x20 TOUCH_OUT_TH10 Finger threshold for touch pad 10 0 22 read-write SAR_TOUCH_THRES11 Finger threshold for touch pad 11 0x88 0x20 TOUCH_OUT_TH11 Finger threshold for touch pad 11 0 22 read-write SAR_TOUCH_THRES12 Finger threshold for touch pad 12 0x8C 0x20 TOUCH_OUT_TH12 Finger threshold for touch pad 12 0 22 read-write SAR_TOUCH_THRES13 Finger threshold for touch pad 13 0x90 0x20 TOUCH_OUT_TH13 Finger threshold for touch pad 13 0 22 read-write SAR_TOUCH_THRES14 Finger threshold for touch pad 14 0x94 0x20 TOUCH_OUT_TH14 Finger threshold for touch pad 14 0 22 read-write SAR_TOUCH_CHN_ST Touch channel status register 0xD4 0x20 TOUCH_PAD_ACTIVE Touch active status 0 15 read-only TOUCH_CHANNEL_CLR Clear touch channel 15 15 write-only TOUCH_MEAS_DONE Signal flag that indicates one touch pad is done. 31 1 read-only SAR_TOUCH_STATUS0 Status of touch controller 0xD8 0x20 TOUCH_DENOISE_DATA Denoise measure value from touch sensor 0. 0 22 read-only TOUCH_SCAN_CURR Current pad in scan status 22 4 read-only SAR_TOUCH_STATUS1 Touch pad 1 status 0xDC 0x20 TOUCH_PAD1_DATA The data of touch pad 1, depending on the setting of SENS_TOUCH_DATA_SEL. 0 22 read-only TOUCH_PAD1_DEBOUNCE Touch pad 1 debounce value. 29 3 read-only SAR_TOUCH_STATUS2 Touch pad 2 status 0xE0 0x20 TOUCH_PAD2_DATA The data of touch pad 2, depending on the setting of SENS_TOUCH_DATA_SEL. 0 22 read-only TOUCH_PAD2_DEBOUNCE Touch pad 2 debounce value. 29 3 read-only SAR_TOUCH_STATUS3 Touch pad 3 status 0xE4 0x20 TOUCH_PAD3_DATA The data of touch pad 3, depending on the setting of SENS_TOUCH_DATA_SEL. 0 22 read-only TOUCH_PAD3_DEBOUNCE Touch pad 3 debounce value. 29 3 read-only SAR_TOUCH_STATUS4 Touch pad 4 status 0xE8 0x20 TOUCH_PAD4_DATA The data of touch pad 4, depending on the setting of SENS_TOUCH_DATA_SEL. 0 22 read-only TOUCH_PAD4_DEBOUNCE Touch pad 4 debounce value. 29 3 read-only SAR_TOUCH_STATUS5 Touch pad 5 status 0xEC 0x20 TOUCH_PAD5_DATA The data of touch pad 5, depending on the setting of SENS_TOUCH_DATA_SEL. 0 22 read-only TOUCH_PAD5_DEBOUNCE Touch pad 5 debounce value. 29 3 read-only SAR_TOUCH_STATUS6 Touch pad 6 status 0xF0 0x20 TOUCH_PAD6_DATA The data of touch pad 6, depending on the setting of SENS_TOUCH_DATA_SEL. 0 22 read-only TOUCH_PAD6_DEBOUNCE Touch pad 6 debounce value. 29 3 read-only SAR_TOUCH_STATUS7 Touch pad 7 status 0xF4 0x20 TOUCH_PAD7_DATA The data of touch pad 7, depending on the setting of SENS_TOUCH_DATA_SEL. 0 22 read-only TOUCH_PAD7_DEBOUNCE Touch pad 7 debounce value. 29 3 read-only SAR_TOUCH_STATUS8 Touch pad 8 status 0xF8 0x20 TOUCH_PAD8_DATA The data of touch pad 8, depending on the setting of SENS_TOUCH_DATA_SEL. 0 22 read-only TOUCH_PAD8_DEBOUNCE Touch pad 8 debounce value. 29 3 read-only SAR_TOUCH_STATUS9 Touch pad 9 status 0xFC 0x20 TOUCH_PAD9_DATA The data of touch pad 9, depending on the setting of SENS_TOUCH_DATA_SEL. 0 22 read-only TOUCH_PAD9_DEBOUNCE Touch pad 9 debounce value. 29 3 read-only SAR_TOUCH_STATUS10 Touch pad 10 status 0x100 0x20 TOUCH_PAD10_DATA The data of touch pad 10, depending on the setting of SENS_TOUCH_DATA_SEL. 0 22 read-only TOUCH_PAD10_DEBOUNCE Touch pad 10 debounce value. 29 3 read-only SAR_TOUCH_STATUS11 Touch pad 11 status 0x104 0x20 TOUCH_PAD11_DATA The data of touch pad 11, depending on the setting of SENS_TOUCH_DATA_SEL. 0 22 read-only TOUCH_PAD11_DEBOUNCE Touch pad 11 debounce value. 29 3 read-only SAR_TOUCH_STATUS12 Touch pad 12 status 0x108 0x20 TOUCH_PAD12_DATA The data of touch pad 12, depending on the setting of SENS_TOUCH_DATA_SEL. 0 22 read-only TOUCH_PAD12_DEBOUNCE Touch pad 12 debounce value. 29 3 read-only SAR_TOUCH_STATUS13 Touch pad 13 status 0x10C 0x20 TOUCH_PAD13_DATA The data of touch pad 13, depending on the setting of SENS_TOUCH_DATA_SEL. 0 22 read-only TOUCH_PAD13_DEBOUNCE Touch pad 13 debounce value. 29 3 read-only SAR_TOUCH_STATUS14 Touch pad 14 status 0x110 0x20 TOUCH_PAD14_DATA The data of touch pad 14, depending on the setting of SENS_TOUCH_DATA_SEL. 0 22 read-only TOUCH_PAD14_DEBOUNCE Touch pad 14 debounce value. 29 3 read-only SAR_TOUCH_STATUS15 Touch sleep pad status 0x114 0x20 TOUCH_SLP_DATA The data of touch sleep pad, depending on the setting of SENS_TOUCH_DATA_SEL. 0 22 read-only TOUCH_SLP_DEBOUNCE Touch sleep pad debouce value. 29 3 read-only SAR_TOUCH_STATUS16 Touch approach count status 0x118 0x20 TOUCH_APPROACH_PAD2_CNT Count status of proximity pad 2. 0 8 read-only TOUCH_APPROACH_PAD1_CNT Count status of proximity pad 1. 8 8 read-only TOUCH_APPROACH_PAD0_CNT Count status of proximity pad 0. 16 8 read-only TOUCH_SLP_APPROACH_CNT Count status of sleep pad in proximity mode. 24 8 read-only SAR_DAC_CTRL1 DAC control 0x11C 0x20 SW_FSTEP Frequency step for CW generator can be used to adjust the frequency. 0 16 read-write SW_TONE_EN 0: disable CW generator. 1: enable CW generator. 16 1 read-write DEBUG_BIT_SEL 17 5 read-write DAC_DIG_FORCE 0: DAC1 and DAC2 do not use DMA. 1: DAC1 and DAC2 use DMA. 22 1 read-write DAC_CLK_FORCE_LOW 1: force PDAC_CLK to low 23 1 read-write DAC_CLK_FORCE_HIGH 1: force PDAC_CLK to high 24 1 read-write DAC_CLK_INV 1: invert PDAC_CLK. 25 1 read-write DAC_RESET Reset DAC by software. 26 1 read-write DAC_CLKGATE_EN DAC clock gate enable bit. 27 1 read-write SAR_DAC_CTRL2 DAC output control 0x120 0x20 0x03000000 DAC_DC1 DC offset for DAC1 CW generator. 0 8 read-write DAC_DC2 DC offset for DAC2 CW generator. 8 8 read-write DAC_SCALE1 DAC1 scaling. 00: no scale. 01: scale to 1/2. 10: scale to 1/4. 11: scale to 1/8. 16 2 read-write DAC_SCALE2 DAC2 scaling. 00: no scale. 01: scale to 1/2. 10: scale to 1/4. 11: scale to 1/8. 18 2 read-write DAC_INV1 Invert DAC1. 00: do not invert any bits. 01: invert all bits. 10: invert MSB. 11: invert all bits except MSB. 20 2 read-write DAC_INV2 Invert DAC2. 00: do not invert any bits. 01: invert all bits. 10: invert MSB. 11: invert all bits except MSB. 22 2 read-write DAC_CW_EN1 1: select CW generator as source for PDAC1_DAC. 0: select register RT- CIO_PDAC1_DAC as source for PDAC1_DAC. 24 1 read-write DAC_CW_EN2 1: select CW generator as source for PDAC2_DAC. 0: select register RT- CIO_PDAC2_DAC as source for PDAC2_DAC. 25 1 read-write SAR_COCPU_STATE ULP-RISCV status 0x124 0x20 COCPU_DBG_TRIGGER Trigger ULP-RISCV debug registers 25 1 write-only COCPU_CLK_EN Check ULP-RISCV whether clk on 26 1 read-only COCPU_RESET_N Check ULP-RISCV whether in reset state 27 1 read-only COCPU_EOI Check ULP-RISCV whether in interrupt state 28 1 read-only COCPU_TRAP Check ULP-RISCV whether in trap state 29 1 read-only COCPU_EBREAK Check ULP-RISCV whether in ebreak 30 1 read-only SAR_COCPU_INT_RAW Interrupt raw bit of ULP-RISCV 0x128 0x20 COCPU_TOUCH_DONE_INT_RAW TOUCH_DONE_INT interrupt raw bit 0 1 read-only COCPU_TOUCH_INACTIVE_INT_RAW TOUCH_INACTIVE_INT interrupt raw bit 1 1 read-only COCPU_TOUCH_ACTIVE_INT_RAW TOUCH_ACTIVE_INT interrupt raw bit 2 1 read-only COCPU_SARADC1_INT_RAW SARADC1_DONE_INT interrupt raw bit 3 1 read-only COCPU_SARADC2_INT_RAW SARADC2_DONE_INT interrupt raw bit 4 1 read-only COCPU_TSENS_INT_RAW TSENS_DONE_INT interrupt raw bit 5 1 read-only COCPU_START_INT_RAW RISCV_START_INT interrupt raw bit 6 1 read-only COCPU_SW_INT_RAW SW_INT interrupt raw bit 7 1 read-only COCPU_SWD_INT_RAW SWD_INT interrupt raw bit 8 1 read-only SAR_COCPU_INT_ENA Interrupt enable bit of ULP-RISCV 0x12C 0x20 COCPU_TOUCH_DONE_INT_ENA TOUCH_DONE_INT interrupt enable bit 0 1 read-write COCPU_TOUCH_INACTIVE_INT_ENA TOUCH_INACTIVE_INT interrupt enable bit 1 1 read-write COCPU_TOUCH_ACTIVE_INT_ENA TOUCH_ACTIVE_INT interrupt enable bit 2 1 read-write COCPU_SARADC1_INT_ENA SARADC1_DONE_INT interrupt enable bit 3 1 read-write COCPU_SARADC2_INT_ENA SARADC2_DONE_INT interrupt enable bit 4 1 read-write COCPU_TSENS_INT_ENA TSENS_DONE_INT interrupt enable bit 5 1 read-write COCPU_START_INT_ENA RISCV_START_INT interrupt enable bit 6 1 read-write COCPU_SW_INT_ENA SW_INT interrupt enable bit 7 1 read-write COCPU_SWD_INT_ENA SWD_INT interrupt enable bit 8 1 read-write SAR_COCPU_INT_ST Interrupt status bit of ULP-RISCV 0x130 0x20 COCPU_TOUCH_DONE_INT_ST TOUCH_DONE_INT interrupt status bit 0 1 read-only COCPU_TOUCH_INACTIVE_INT_ST TOUCH_INACTIVE_INT interrupt status bit 1 1 read-only COCPU_TOUCH_ACTIVE_INT_ST TOUCH_ACTIVE_INT interrupt status bit 2 1 read-only COCPU_SARADC1_INT_ST SARADC1_DONE_INT interrupt status bit 3 1 read-only COCPU_SARADC2_INT_ST SARADC2_DONE_INT interrupt status bit 4 1 read-only COCPU_TSENS_INT_ST TSENS_DONE_INT interrupt status bit 5 1 read-only COCPU_START_INT_ST RISCV_START_INT interrupt status bit 6 1 read-only COCPU_SW_INT_ST SW_INT interrupt status bit 7 1 read-only COCPU_SWD_INT_ST SWD_INT interrupt status bit 8 1 read-only SAR_COCPU_INT_CLR Interrupt clear bit of ULP-RISCV 0x134 0x20 COCPU_TOUCH_DONE_INT_CLR TOUCH_DONE_INT interrupt clear bit 0 1 write-only COCPU_TOUCH_INACTIVE_INT_CLR TOUCH_INACTIVE_INT interrupt clear bit 1 1 write-only COCPU_TOUCH_ACTIVE_INT_CLR TOUCH_ACTIVE_INT interrupt clear bit 2 1 write-only COCPU_SARADC1_INT_CLR SARADC1_DONE_INT interrupt clear bit 3 1 write-only COCPU_SARADC2_INT_CLR SARADC2_DONE_INT interrupt clear bit 4 1 write-only COCPU_TSENS_INT_CLR TSENS_DONE_INT interrupt clear bit 5 1 write-only COCPU_START_INT_CLR RISCV_START_INT interrupt clear bit 6 1 write-only COCPU_SW_INT_CLR SW_INT interrupt clear bit 7 1 write-only COCPU_SWD_INT_CLR SWD_INT interrupt clear bit 8 1 write-only SAR_COCPU_DEBUG ULP-RISCV debug register 0x138 0x20 COCPU_PC ULP-RISCV Program counter 0 13 read-only COCPU_MEM_VLD ULP-RISCV memory valid output 13 1 read-only COCPU_MEM_RDY ULP-RISCV memory ready input 14 1 read-only COCPU_MEM_WEN ULP-RISCV memory write enable output 15 4 read-only COCPU_MEM_ADDR ULP-RISCV memory address output 19 13 read-only SAR_HALL_CTRL hall control 0x13C 0x20 0xA0000000 XPD_HALL Power on hall sensor and connect to VP and VN 28 1 read-write XPD_HALL_FORCE 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor 29 1 read-write HALL_PHASE Reverse phase of hall sensor 30 1 read-write HALL_PHASE_FORCE 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor 31 1 read-write SAR_NOUSE sar nouse 0x140 0x20 SAR_NOUSE sar nouse 0 32 read-write SAR_IO_MUX_CONF Configure and reset IO MUX 0x144 0x20 IOMUX_RESET Reset IO MUX by software 30 1 read-write IOMUX_CLK_GATE_EN IO MUX clock gate enable bit 31 1 read-write SARDATE Version Control Register 0x148 0x20 0x01906140 SAR_DATE Version Control Register 0 28 read-write SHA SHA (Secure Hash Algorithm) Accelerator SHA 0x6003B000 0x0 0xF0 registers SHA 55 MODE Defines the algorithm of SHA accelerator 0x0 0x20 MODE Defines the SHA algorithm. 0 3 read-write T_STRING String content register for calculating initial Hash Value (only effective for SHA-512/t) 0x4 0x20 T_STRING Defines t_string for calculating the initial Hash value for SHA-512/t. 0 32 read-write T_LENGTH String length register for calculating initial Hash Value (only effective for SHA-512/t) 0x8 0x20 T_LENGTH Defines t_length for calculating the initial Hash value for SHA-512/t. 0 6 read-write DMA_BLOCK_NUM Block number register (only effective for DMA-SHA) 0xC 0x20 DMA_BLOCK_NUM Defines the DMA-SHA block number. 0 6 read-write START Starts the SHA accelerator for Typical SHA operation 0x10 0x20 START Write 1 to start Typical SHA calculation. 0 1 write-only CONTINUE Continues SHA operation (only effective in Typical SHA mode) 0x14 0x20 CONTINUE_OP Write 1 to continue Typical SHA calculation. 0 1 write-only BUSY Indicates if SHA Accelerator is busy or not 0x18 0x20 STATE Indicates the states of SHA accelerator. 1'h0: idle 1'h1: busy 0 1 read-only DMA_START Starts the SHA accelerator for DMA-SHA operation 0x1C 0x20 DMA_START Write 1 to start DMA-SHA calculation. 0 1 write-only DMA_CONTINUE Continues SHA operation (only effective in DMA-SHA mode) 0x20 0x20 DMA_CONTINUE Write 1 to continue DMA-SHA calculation. 0 1 write-only INT_CLEAR DMA-SHA interrupt clear register 0x24 0x20 CLEAR_INTERRUPT Clears DMA-SHA interrupt. 0 1 write-only INT_ENA DMA-SHA interrupt enable register 0x28 0x20 INTERRUPT_ENA Enables DMA-SHA interrupt. 0 1 read-write DATE Version control register 0x2C 0x20 0x20190402 DATE Version control register. 0 30 read-write 16 0x4 H_MEM%s Hash value 0x40 0x20 H Stores the %sth 32-bit piece of the Hash value. 0 32 read-write 32 0x4 M_MEM%s Message 0x80 0x20 M Stores the %sth 32-bit piece of the message. 0 32 read-write SPI0 SPI (Serial Peripheral Interface) Controller 0 SPI 0x3F403000 0x0 0x108 registers SPI0_REJECT_CACHE 83 CMD Command control register 0x0 0x20 CONF_BITLEN Define the spi_clk cycles of SPI_CONF state. Can be configured in CONF state. 0 23 read-write USR User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. 24 1 read-write ADDR Address value 0x4 0x20 USR_ADDR_VALUE [31:8]:address to slave, [7:0]:Reserved. Can be configured in CONF state. 0 32 read-write CTRL SPI control register 0x8 0x20 0x002C0000 EXT_HOLD_EN Set the bit to hold spi. The bit is combined with SPI_USR_PREP_HOLD,SPI_USR_CMD_HOLD,SPI_USR_ADDR_HOLD,SPI_USR_DUMMY_HOLD,SPI_USR_DIN_HOLD,SPI_USR_DOUT_HOLD and SPI_USR_HOLD_POL. Can be configured in CONF state. 2 1 read-write DUMMY_OUT In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state. 3 1 read-write FADDR_DUAL Apply 2-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state. 5 1 read-write FADDR_QUAD Apply 4-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state. 6 1 read-write FADDR_OCT Apply 8-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state. 7 1 read-write FCMD_DUAL Apply 2-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state. 8 1 read-write FCMD_QUAD Apply 4-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state. 9 1 read-write FCMD_OCT Apply 8-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state. 10 1 read-write FREAD_DUAL In the read operations, read-data phase is in 2-bit mode. 1: enable 0: disable. Can be configured in CONF state. 14 1 read-write FREAD_QUAD In the read operations read-data phase is in 4-bit mode. 1: enable 0: disable. Can be configured in CONF state. 15 1 read-write FREAD_OCT In the read operations read-data phase is in 8-bit mode. 1: enable 0: disable. Can be configured in CONF state. 16 1 read-write Q_POL The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. 18 1 read-write D_POL The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. 19 1 read-write WP Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. 21 1 read-write RD_BIT_ORDER In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. 25 1 read-write WR_BIT_ORDER In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. 26 1 read-write CTRL1 SPI control register 1 0xC 0x20 0x00004010 CLK_MODE SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. 0 2 read-write CLK_MODE_13 {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. 2 1 read-write RSCK_DATA_OUT It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge 3 1 read-write W16_17_WR_ENA 1:SPI_BUF16~SPI_BUF17 can be written 0:SPI_BUF16~SPI_BUF17 can not be written. Can be configured in CONF state. 4 1 read-write CS_HOLD_DELAY SPI cs signal is delayed by spi clock cycles. Can be configured in CONF state. 14 6 read-write CTRL2 SPI control register 2 0x10 0x20 0x00002000 CS_SETUP_TIME (cycles+1) of prepare phase by spi clock this bits are combined with SPI_CS_SETUP bit. Can be configured in CONF state. 0 13 read-write CS_HOLD_TIME delay cycles of cs pin by spi clock this bits are combined with SPI_CS_HOLD bit. Can be configured in CONF state. 13 13 read-write CS_DELAY_MODE spi_cs signal is delayed by spi_clk . 0: zero 1: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by half cycle else delayed by one cycle 2: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by one cycle, else delayed by half cycle 3: delayed one cycle. Can be configured in CONF state. 26 3 read-write CS_DELAY_NUM spi_cs signal is delayed by system clock cycles. Can be configured in CONF state. 29 2 read-write CLOCK SPI clock control register 0x14 0x20 0x80003043 CLKCNT_L In the master mode it must be equal to SPI_CLKCNT_N. In the slave mode it must be 0. Can be configured in CONF state. 0 6 read-write CLKCNT_H In the master mode it must be floor((SPI_CLKCNT_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. 6 6 read-write CLKCNT_N In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(SPI_CLKDIV_PRE+1)/(SPI_CLKCNT_N+1). Can be configured in CONF state. 12 6 read-write CLKDIV_PRE In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. 18 13 read-write CLK_EQU_SYSCLK In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. 31 1 read-write USER SPI USER control register 0x18 0x20 0x800000C0 DOUTDIN Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. 0 1 read-write QPI_MODE Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. 3 1 read-write OPI_MODE Just for master mode. 1: spi controller is in OPI mode (all in 8-bit mode). 0: others. Can be configured in CONF state. 4 1 read-write TSCK_I_EDGE In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. 5 1 read-write CS_HOLD spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. 6 1 read-write CS_SETUP spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. 7 1 read-write RSCK_I_EDGE In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. 8 1 read-write CK_OUT_EDGE the bit combined with SPI_DOUT_MODE register to set mosi signal delay mode. Can be configured in CONF state. 9 1 read-write RD_BYTE_ORDER In read-data (MISO) phase 1: big-endian 0: little_endian. Can be configured in CONF state. 10 1 read-write WR_BYTE_ORDER In command address write-data (MOSI) phases 1: big-endian 0: litte_endian. Can be configured in CONF state. 11 1 read-write FWRITE_DUAL In the write operations read-data phase is in 2-bit mode. Can be configured in CONF state. 12 1 read-write FWRITE_QUAD In the write operations read-data phase is in 4-bit mode. Can be configured in CONF state. 13 1 read-write FWRITE_OCT In the write operations read-data phase is in 8-bit mode. Can be configured in CONF state. 14 1 read-write USR_CONF_NXT 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. 15 1 read-write SIO Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. 16 1 read-write USR_HOLD_POL It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low. Can be configured in CONF state. 17 1 read-write USR_DOUT_HOLD spi is hold at data out state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. 18 1 read-write USR_DIN_HOLD spi is hold at data in state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. 19 1 read-write USR_DUMMY_HOLD spi is hold at dummy state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. 20 1 read-write USR_ADDR_HOLD spi is hold at address state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. 21 1 read-write USR_CMD_HOLD spi is hold at command state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. 22 1 read-write USR_PREP_HOLD spi is hold at prepare state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. 23 1 read-write USR_MISO_HIGHPART read-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state. 24 1 read-write USR_MOSI_HIGHPART write-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state. 25 1 read-write USR_DUMMY_IDLE spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. 26 1 read-write USR_MOSI This bit enable the write-data phase of an operation. Can be configured in CONF state. 27 1 read-write USR_MISO This bit enable the read-data phase of an operation. Can be configured in CONF state. 28 1 read-write USR_DUMMY This bit enable the dummy phase of an operation. Can be configured in CONF state. 29 1 read-write USR_ADDR This bit enable the address phase of an operation. Can be configured in CONF state. 30 1 read-write USR_COMMAND This bit enable the command phase of an operation. Can be configured in CONF state. 31 1 read-write USER1 SPI USER control register 1 0x1C 0x20 0xB8000007 USR_DUMMY_CYCLELEN The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. 0 8 read-write USR_ADDR_BITLEN The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. 27 5 read-write USER2 SPI USER control register 2 0x20 0x20 0x70000000 USR_COMMAND_VALUE The value of command. Can be configured in CONF state. 0 16 read-write USR_COMMAND_BITLEN The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. 28 4 read-write MOSI_DLEN MOSI length 0x24 0x20 USR_MOSI_DBITLEN The length in bits of write-data. The register value shall be (bit_num-1). Can be configured in CONF state. 0 23 read-write MISO_DLEN MISO length 0x28 0x20 USR_MISO_DBITLEN The length in bits of read-data. The register value shall be (bit_num-1). Can be configured in CONF state. 0 23 read-write MISC SPI misc register 0x2C 0x20 0x0000003E CS0_DIS SPI CS0 pin enable, 1: disable CS0, 0: SPI_CS0 signal is from/to CS0 pin. Can be configured in CONF state. 0 1 read-write CS1_DIS SPI CS1 pin enable, 1: disable CS1, 0: SPI_CS1 signal is from/to CS1 pin. Can be configured in CONF state. 1 1 read-write CS2_DIS SPI CS2 pin enable, 1: disable CS2, 0: SPI_CS2 signal is from/to CS2 pin. Can be configured in CONF state. 2 1 read-write CS3_DIS SPI CS3 pin enable, 1: disable CS3, 0: SPI_CS3 signal is from/to CS3 pin. Can be configured in CONF state. 3 1 read-write CS4_DIS SPI CS4 pin enable, 1: disable CS4, 0: SPI_CS4 signal is from/to CS4 pin. Can be configured in CONF state. 4 1 read-write CS5_DIS SPI CS5 pin enable, 1: disable CS5, 0: SPI_CS5 signal is from/to CS5 pin. Can be configured in CONF state. 5 1 read-write CK_DIS 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. 6 1 read-write MASTER_CS_POL In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ SPI_MASTER_CS_POL. Can be configured in CONF state. 7 6 read-write CLK_DATA_DTR_EN 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. 16 1 read-write DATA_DTR_EN 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. 17 1 read-write ADDR_DTR_EN 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. 18 1 read-write CMD_DTR_EN 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. 19 1 read-write CD_DATA_SET 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_DOUT or SPI_DIN state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state. 20 1 read-write CD_DUMMY_SET 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_DUMMY state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state. 21 1 read-write CD_ADDR_SET 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_SEND_ADDR state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state. 22 1 read-write SLAVE_CS_POL spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. 23 1 read-write DQS_IDLE_EDGE The default value of spi_dqs. Can be configured in CONF state. 24 1 read-write CD_CMD_SET 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_SEND_CMD state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state. 25 1 read-write CD_IDLE_EDGE The default value of spi_cd. Can be configured in CONF state. 26 1 read-write CK_IDLE_EDGE 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. 29 1 read-write CS_KEEP_ACTIVE spi cs line keep low when the bit is set. Can be configured in CONF state. 30 1 read-write QUAD_DIN_PIN_SWAP 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state. 31 1 read-write SLAVE SPI slave control register 0x30 0x20 0x00000200 TRANS_DONE The interrupt raw bit for the completion of any operation in both the master mode and the slave mode. Can not be changed by CONF_buf. 4 1 read-write INT_RD_BUF_DONE_EN SPI_SLV_RD_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state. 5 1 read-write INT_WR_BUF_DONE_EN SPI_SLV_WR_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state. 6 1 read-write INT_RD_DMA_DONE_EN SPI_SLV_RD_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state. 7 1 read-write INT_WR_DMA_DONE_EN SPI_SLV_WR_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state. 8 1 read-write INT_TRANS_DONE_EN SPI_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state. 9 1 read-write INT_DMA_SEG_TRANS_EN SPI_DMA_SEG_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state. 10 1 read-write SEG_MAGIC_ERR_INT_EN 1: Enable seg magic value error interrupt. 0: Others. Can be configured in CONF state. 11 1 read-write TRANS_CNT The operations counter in both the master mode and the slave mode. 23 4 read-only TRANS_DONE_AUTO_CLR_EN SPI_TRANS_DONE auto clear enable, clear it 3 apb cycles after the pos edge of SPI_TRANS_DONE. 0:disable. 1: enable. Can be configured in CONF state. 29 1 read-write MODE Set SPI work mode. 1: slave mode 0: master mode. 30 1 read-write SOFT_RESET Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. 31 1 read-write SLAVE1 SPI slave control register 1 0x34 0x20 SLV_ADDR_ERR_CLR 1: Clear SPI_SLV_ADDR_ERR. 0: not valid. Can be changed by CONF_buf. 10 1 read-write SLV_CMD_ERR_CLR 1: Clear SPI_SLV_CMD_ERR. 0: not valid. Can be changed by CONF_buf. 11 1 read-write SLV_NO_QPI_EN 1: spi slave QPI mode is not supported. 0: spi slave QPI mode is supported. 12 1 read-write SLV_ADDR_ERR 1: The address value of the last SPI transfer is not supported by SPI slave. 0: The address value is supported or no address value is received. 13 1 read-only SLV_CMD_ERR 1: The command value of the last SPI transfer is not supported by SPI slave. 0: The command value is supported or no command value is received. 14 1 read-only SLV_WR_DMA_DONE The interrupt raw bit for the completion of dma write operation in the slave mode. Can not be changed by CONF_buf. 15 1 read-write SLV_LAST_COMMAND In the slave mode it is the value of command. 16 8 read-write SLV_LAST_ADDR In the slave mode it is the value of address. 24 8 read-write SLV_WRBUF_DLEN SPI slave Wr_BUF interrupt and CONF control register 0x38 0x20 0xD8000000 SLV_WR_BUF_DONE The interrupt raw bit for the completion of write-buffer operation in the slave mode. Can not be changed by CONF_buf. 24 1 read-write CONF_BASE_BITLEN The basic spi_clk cycles of CONF state. The real cycle length of CONF state, if SPI_USR_CONF is enabled, is SPI_CONF_BASE_BITLEN[6:0] + SPI_CONF_BITLEN[23:0]. 25 7 read-write SLV_RDBUF_DLEN SPI magic error and slave control register 0x3C 0x20 SLV_DMA_RD_BYTELEN In the slave mode it is the length in bytes for read operations. The register value shall be byte_num. 0 20 read-write SLV_RD_BUF_DONE The interrupt raw bit for the completion of read-buffer operation in the slave mode. Can not be changed by CONF_buf. 24 1 read-write SEG_MAGIC_ERR 1: The recent magic value in CONF buffer is not right in master DMA seg-trans mode. 0: others. 25 1 read-write SLV_RD_BYTE SPI interrupt control register 0x40 0x20 0x0A000000 SLV_DATA_BYTELEN The full-duplex or half-duplex data byte length of the last SPI transfer in slave mode. In half-duplex mode, this value is controlled by bits [23:20]. 0 20 read-write SLV_RDDMA_BYTELEN_EN 1: SPI_SLV_DATA_BYTELEN stores data byte length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others 20 1 read-write SLV_WRDMA_BYTELEN_EN 1: SPI_SLV_DATA_BYTELEN stores data byte length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others 21 1 read-write SLV_RDBUF_BYTELEN_EN 1: SPI_SLV_DATA_BYTELEN stores data byte length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others 22 1 read-write SLV_WRBUF_BYTELEN_EN 1: SPI_SLV_DATA_BYTELEN stores data byte length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others 23 1 read-write DMA_SEG_MAGIC_VALUE The magic value of BM table in master DMA seg-trans. 24 4 read-write SLV_RD_DMA_DONE The interrupt raw bit for the completion of Rd-DMA operation in the slave mode. Can not be changed by CONF_buf. 30 1 read-write USR_CONF 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. 31 1 read-write FSM SPI master status and DMA read byte control register 0x44 0x20 ST The status of spi state machine. 0: idle state, 1: preparation state, 2: send command state, 3: send data state, 4: red data state, 5:write data state, 6: wait state, 7: done state. 0 4 read-only MST_DMA_RD_BYTELEN Define the master DMA read byte length in non seg-conf-trans or seg-conf-trans mode. Invalid when SPI_RX_EOF_EN is 0. Can be configured in CONF state.. 12 20 read-write HOLD SPI hold register 0x48 0x20 INT_HOLD_ENA This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set, if the other SPI is busy, the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase. Can be configured in CONF state. 0 2 read-write VAL spi hold output value, which should be used with SPI_HOLD_OUT_EN. Can be configured in CONF state. 2 1 read-write OUT_EN Enable set spi output hold value to spi_hold_reg. It can be used to hold spi state machine with SPI_EXT_HOLD_EN and other usr hold signals. Can be configured in CONF state. 3 1 read-write OUT_TIME set the hold cycles of output spi_hold signal when SPI_HOLD_OUT_EN is enable. Can be configured in CONF state. 4 3 read-write DMA_SEG_TRANS_DONE 1: spi master DMA full-duplex/half-duplex seg-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-trans is not ended or not occurred. Can not be changed by CONF_buf. 7 1 read-write DMA_CONF SPI DMA control register 0x4C 0x20 0x00000200 IN_RST The bit is used to reset in dma fsm and in data fifo pointer. 2 1 read-write OUT_RST The bit is used to reset out dma fsm and out data fifo pointer. 3 1 read-write AHBM_FIFO_RST Reset spi dma ahb master fifo pointer. 4 1 read-write AHBM_RST Reset spi dma ahb master. 5 1 read-write IN_LOOP_TEST Set bit to test in link. 6 1 read-write OUT_LOOP_TEST Set bit to test out link. 7 1 read-write OUT_AUTO_WRBACK when the bit is set, DMA continue to use the next inlink node when the length of inlink is 0. 8 1 read-write OUT_EOF_MODE out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo. 9 1 read-write OUTDSCR_BURST_EN read descriptor use burst mode when read data for memory. 10 1 read-write INDSCR_BURST_EN read descriptor use burst mode when write data to memory. 11 1 read-write OUT_DATA_BURST_EN spi dma read data from memory in burst mode. 12 1 read-write MEM_TRANS_EN 1: Internal memory data transfer enable bit. Send SPI DMA RX buffer data to SPI DMA TX buffer. 0: Disable this function. 13 1 read-write DMA_RX_STOP spi dma read data stop when in continue tx/rx mode. 14 1 read-write DMA_TX_STOP spi dma write data stop when in continue tx/rx mode. 15 1 read-write DMA_CONTINUE spi dma continue tx/rx data. 16 1 read-write SLV_LAST_SEG_POP_CLR 1: Clear spi_slv_seg_frt_pop_mask. 0 : others 17 1 read-write DMA_SLV_SEG_TRANS_EN Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. 18 1 read-write SLV_RX_SEG_TRANS_CLR_EN 1: spi_dma_infifo_full_vld is cleared by spi slave CMD5. 0: spi_dma_infifo_full_vld is cleared by SPI_TRANS_DONE. 19 1 read-write SLV_TX_SEG_TRANS_CLR_EN 1: spi_dma_outfifo_empty_vld is cleared by spi slave CMD6. 0: spi_dma_outfifo_empty_vld is cleared by SPI_TRANS_DONE. 20 1 read-write RX_EOF_EN 1: SPI_IN_SUC_EOF_INT_RAW is set when the number of dma pushed data bytes is equal to the value of SPI_SLV_DMA_RD_BYTELEN[19:0]/ SPI_MST_DMA_RD_BYTELEN[19:0] in spi dma transition. 0: SPI_IN_SUC_EOF_INT_RAW is set by SPI_TRANS_DONE in non-seg-trans or SPI_DMA_SEG_TRANS_DONE in seg-trans. 21 1 read-write DMA_INFIFO_FULL_CLR 1:Clear spi_dma_infifo_full_vld. 0: Do not control it. 22 1 read-write DMA_OUTFIFO_EMPTY_CLR 1:Clear spi_dma_outfifo_empty_vld. 0: Do not control it. 23 1 read-write EXT_MEM_BK_SIZE Select the external memory block size. 26 2 read-write DMA_SEG_TRANS_CLR 1: End slave seg-trans, which acts as 0x05 command. 2 or more end seg-trans signals will induce error in DMA RX. 0: others. Will be cleared in 1 APB CLK cycles by hardware.. 28 1 read-write DMA_OUT_LINK SPI DMA TX link configuration 0x50 0x20 OUTLINK_ADDR The address of the first outlink descriptor. 0 20 read-write OUTLINK_STOP Set the bit to stop to use outlink descriptor. 28 1 read-write OUTLINK_START Set the bit to start to use outlink descriptor. 29 1 read-write OUTLINK_RESTART Set the bit to mount on new outlink descriptors. 30 1 read-write DMA_TX_ENA spi dma write data status bit. 31 1 read-write DMA_IN_LINK SPI DMA RX link configuration 0x54 0x20 INLINK_ADDR The address of the first inlink descriptor. 0 20 read-write INLINK_AUTO_RET when the bit is set, the inlink descriptor returns to the first link node when a packet is error. 20 1 read-write INLINK_STOP Set the bit to stop to use inlink descriptor. 28 1 read-write INLINK_START Set the bit to start to use inlink descriptor. 29 1 read-write INLINK_RESTART Set the bit to mount on new inlink descriptors. 30 1 read-write DMA_RX_ENA SPI DMA read data status bit. 31 1 read-write DMA_INT_ENA SPI DMA interrupt enable register 0x58 0x20 INLINK_DSCR_EMPTY_INT_ENA The enable bit for lack of enough inlink descriptors. Can be configured in CONF state. 0 1 read-write OUTLINK_DSCR_ERROR_INT_ENA The enable bit for outlink descriptor error. Can be configured in CONF state. 1 1 read-write INLINK_DSCR_ERROR_INT_ENA The enable bit for inlink descriptor error. Can be configured in CONF state. 2 1 read-write IN_DONE_INT_ENA The enable bit for completing usage of a inlink descriptor. Can be configured in CONF state. 3 1 read-write IN_ERR_EOF_INT_ENA The enable bit for receiving error. Can be configured in CONF state. 4 1 read-write IN_SUC_EOF_INT_ENA The enable bit for completing receiving all the packets from host. Can be configured in CONF state. 5 1 read-write OUT_DONE_INT_ENA The enable bit for completing usage of a outlink descriptor . Can be configured in CONF state. 6 1 read-write OUT_EOF_INT_ENA The enable bit for sending a packet to host done. Can be configured in CONF state. 7 1 read-write OUT_TOTAL_EOF_INT_ENA The enable bit for sending all the packets to host done. Can be configured in CONF state. 8 1 read-write INFIFO_FULL_ERR_INT_ENA The enable bit for infifo full error interrupt. 9 1 read-write OUTFIFO_EMPTY_ERR_INT_ENA The enable bit for outfifo empty error interrupt. 10 1 read-write SLV_CMD6_INT_ENA The enable bit for SPI slave CMD6 interrupt. 11 1 read-write SLV_CMD7_INT_ENA The enable bit for SPI slave CMD7 interrupt. 12 1 read-write SLV_CMD8_INT_ENA The enable bit for SPI slave CMD8 interrupt. 13 1 read-write SLV_CMD9_INT_ENA The enable bit for SPI slave CMD9 interrupt. 14 1 read-write SLV_CMDA_INT_ENA The enable bit for SPI slave CMDA interrupt. 15 1 read-write DMA_INT_RAW SPI DMA interrupt raw register 0x5C 0x20 INLINK_DSCR_EMPTY_INT_RAW The raw bit for lack of enough inlink descriptors. Can be configured in CONF state. 0 1 read-only OUTLINK_DSCR_ERROR_INT_RAW The raw bit for outlink descriptor error. Can be configured in CONF state. 1 1 read-only INLINK_DSCR_ERROR_INT_RAW The raw bit for inlink descriptor error. Can be configured in CONF state. 2 1 read-only IN_DONE_INT_RAW The raw bit for completing usage of a inlink descriptor. Can be configured in CONF state. 3 1 read-only IN_ERR_EOF_INT_RAW The raw bit for receiving error. Can be configured in CONF state. 4 1 read-only IN_SUC_EOF_INT_RAW The raw bit for completing receiving all the packets from host. Can be configured in CONF state. 5 1 read-only OUT_DONE_INT_RAW The raw bit for completing usage of a outlink descriptor. Can be configured in CONF state. 6 1 read-only OUT_EOF_INT_RAW The raw bit for sending a packet to host done. Can be configured in CONF state. 7 1 read-only OUT_TOTAL_EOF_INT_RAW The raw bit for sending all the packets to host done. Can be configured in CONF state. 8 1 read-only INFIFO_FULL_ERR_INT_RAW 1:SPI_DMA_INFIFO_FULL and spi_push_data_prep are valid, which means that DMA Rx buffer is full but push is valid. 0: Others. Can not be changed by CONF_buf. 9 1 read-only OUTFIFO_EMPTY_ERR_INT_RAW 1:SPI_DMA_OUTFIFO_EMPTY and spi_pop_data_prep are valid, which means that there is no data to pop but pop is valid. 0: Others. Can not be changed by CONF_buf. 10 1 read-only SLV_CMD6_INT_RAW The raw bit for SPI slave CMD6 interrupt. 11 1 read-write SLV_CMD7_INT_RAW The raw bit for SPI slave CMD7 interrupt. 12 1 read-write SLV_CMD8_INT_RAW The raw bit for SPI slave CMD8 interrupt. 13 1 read-write SLV_CMD9_INT_RAW The raw bit for SPI slave CMD9 interrupt. 14 1 read-write SLV_CMDA_INT_RAW The raw bit for SPI slave CMDA interrupt. 15 1 read-write DMA_INT_ST SPI DMA interrupt status register 0x60 0x20 INLINK_DSCR_EMPTY_INT_ST The status bit for lack of enough inlink descriptors. 0 1 read-only OUTLINK_DSCR_ERROR_INT_ST The status bit for outlink descriptor error. 1 1 read-only INLINK_DSCR_ERROR_INT_ST The status bit for inlink descriptor error. 2 1 read-only IN_DONE_INT_ST The status bit for completing usage of a inlink descriptor. 3 1 read-only IN_ERR_EOF_INT_ST The status bit for receiving error. 4 1 read-only IN_SUC_EOF_INT_ST The status bit for completing receiving all the packets from host. 5 1 read-only OUT_DONE_INT_ST The status bit for completing usage of a outlink descriptor. 6 1 read-only OUT_EOF_INT_ST The status bit for sending a packet to host done. 7 1 read-only OUT_TOTAL_EOF_INT_ST The status bit for sending all the packets to host done. 8 1 read-only INFIFO_FULL_ERR_INT_ST The status bit for infifo full error. 9 1 read-only OUTFIFO_EMPTY_ERR_INT_ST The status bit for outfifo empty error. 10 1 read-only SLV_CMD6_INT_ST The status bit for SPI slave CMD6 interrupt. 11 1 read-write SLV_CMD7_INT_ST The status bit for SPI slave CMD7 interrupt. 12 1 read-write SLV_CMD8_INT_ST The status bit for SPI slave CMD8 interrupt. 13 1 read-write SLV_CMD9_INT_ST The status bit for SPI slave CMD9 interrupt. 14 1 read-write SLV_CMDA_INT_ST The status bit for SPI slave CMDA interrupt. 15 1 read-write DMA_INT_CLR SPI DMA interrupt clear register 0x64 0x20 INLINK_DSCR_EMPTY_INT_CLR The clear bit for lack of enough inlink descriptors. Can be configured in CONF state. 0 1 read-write OUTLINK_DSCR_ERROR_INT_CLR The clear bit for outlink descriptor error. Can be configured in CONF state. 1 1 read-write INLINK_DSCR_ERROR_INT_CLR The clear bit for inlink descriptor error. Can be configured in CONF state. 2 1 read-write IN_DONE_INT_CLR The clear bit for completing usage of a inlink descriptor. Can be configured in CONF state. 3 1 read-write IN_ERR_EOF_INT_CLR The clear bit for receiving error. Can be configured in CONF state. 4 1 read-write IN_SUC_EOF_INT_CLR The clear bit for completing receiving all the packets from host. Can be configured in CONF state. 5 1 read-write OUT_DONE_INT_CLR The clear bit for completing usage of a outlink descriptor. Can be configured in CONF state. 6 1 read-write OUT_EOF_INT_CLR The clear bit for sending a packet to host done. Can be configured in CONF state. 7 1 read-write OUT_TOTAL_EOF_INT_CLR The clear bit for sending all the packets to host done. Can be configured in CONF state. 8 1 read-write INFIFO_FULL_ERR_INT_CLR 1: Clear SPI_INFIFO_FULL_ERR_INT_RAW. 0: not valid. Can be changed by CONF_buf. 9 1 read-write OUTFIFO_EMPTY_ERR_INT_CLR 1: Clear SPI_OUTFIFO_EMPTY_ERR_INT_RAW signal. 0: not valid. Can be changed by CONF_buf. 10 1 read-write SLV_CMD6_INT_CLR The clear bit for SPI slave CMD6 interrupt. 11 1 read-write SLV_CMD7_INT_CLR The clear bit for SPI slave CMD7 interrupt. 12 1 read-write SLV_CMD8_INT_CLR The clear bit for SPI slave CMD8 interrupt. 13 1 read-write SLV_CMD9_INT_CLR The clear bit for SPI slave CMD9 interrupt. 14 1 read-write SLV_CMDA_INT_CLR The clear bit for SPI slave CMDA interrupt. 15 1 read-write IN_ERR_EOF_DES_ADDR The latest SPI DMA RX descriptor address receiving error 0x68 0x20 DMA_IN_ERR_EOF_DES_ADDR The inlink descriptor address when spi dma produce receiving error. 0 32 read-only IN_SUC_EOF_DES_ADDR The latest SPI DMA eof RX descriptor address 0x6C 0x20 DMA_IN_SUC_EOF_DES_ADDR The last inlink descriptor address when spi dma produce from_suc_eof. 0 32 read-only INLINK_DSCR Current SPI DMA RX descriptor pointer 0x70 0x20 DMA_INLINK_DSCR The content of current in descriptor pointer. 0 32 read-only INLINK_DSCR_BF0 Next SPI DMA RX descriptor pointer 0x74 0x20 DMA_INLINK_DSCR_BF0 The content of next in descriptor pointer. 0 32 read-only INLINK_DSCR_BF1 Current SPI DMA RX buffer pointer 0x78 0x20 DMA_INLINK_DSCR_BF1 The content of current in descriptor data buffer pointer. 0 32 read-only OUT_EOF_BFR_DES_ADDR The latest SPI DMA eof TX buffer address 0x7C 0x20 DMA_OUT_EOF_BFR_DES_ADDR The address of buffer relative to the outlink descriptor that produce eof. 0 32 read-only OUT_EOF_DES_ADDR The latest SPI DMA eof TX descriptor address 0x80 0x20 DMA_OUT_EOF_DES_ADDR The last outlink descriptor address when spi dma produce to_eof. 0 32 read-only OUTLINK_DSCR Current SPI DMA TX descriptor pointer 0x84 0x20 DMA_OUTLINK_DSCR The content of current out descriptor pointer. 0 32 read-only OUTLINK_DSCR_BF0 Next SPI DMA TX descriptor pointer 0x88 0x20 DMA_OUTLINK_DSCR_BF0 The content of next out descriptor pointer. 0 32 read-only OUTLINK_DSCR_BF1 Current SPI DMA TX buffer pointer 0x8C 0x20 DMA_OUTLINK_DSCR_BF1 The content of current out descriptor data buffer pointer. 0 32 read-only DMA_OUTSTATUS SPI DMA TX status 0x90 0x20 0x80000000 DMA_OUTDSCR_ADDR SPI dma out descriptor address. 0 18 read-only DMA_OUTDSCR_STATE SPI dma out descriptor state. 18 2 read-only DMA_OUT_STATE SPI dma out data state. 20 3 read-only DMA_OUTFIFO_CNT The remains of SPI dma outfifo data. 23 7 read-only DMA_OUTFIFO_FULL SPI dma outfifo is full. 30 1 read-only DMA_OUTFIFO_EMPTY SPI dma outfifo is empty. 31 1 read-only DMA_INSTATUS SPI DMA RX status 0x94 0x20 0x80000000 DMA_INDSCR_ADDR SPI dma in descriptor address. 0 18 read-only DMA_INDSCR_STATE SPI dma in descriptor state. 18 2 read-only DMA_IN_STATE SPI dma in data state. 20 3 read-only DMA_INFIFO_CNT The remains of SPI dma infifo data. 23 7 read-only DMA_INFIFO_FULL SPI dma infifo is full. 30 1 read-only DMA_INFIFO_EMPTY SPI dma infifo is empty. 31 1 read-only W0 Data buffer 0 0x98 0x20 BUF0 32 bits data buffer 0, transferred in the unit of byte. Byte addressable in slave half-duplex mode. 0 32 read-write W1 Data buffer 1 0x9C 0x20 BUF1 32 bits data buffer 1, transferred in the unit of byte. Byte addressable in slave half-duplex mode. 0 32 read-write W2 Data buffer 2 0xA0 0x20 BUF2 32 bits data buffer 2, transferred in the unit of byte. Byte addressable in slave half-duplex mode. 0 32 read-write W3 Data buffer 3 0xA4 0x20 BUF3 32 bits data buffer 3, transferred in the unit of byte. Byte addressable in slave half-duplex mode. 0 32 read-write W4 Data buffer 4 0xA8 0x20 BUF4 32 bits data buffer 4, transferred in the unit of byte. Byte addressable in slave half-duplex mode. 0 32 read-write W5 Data buffer 5 0xAC 0x20 BUF5 32 bits data buffer 5, transferred in the unit of byte. Byte addressable in slave half-duplex mode. 0 32 read-write W6 Data buffer 6 0xB0 0x20 BUF6 32 bits data buffer 6, transferred in the unit of byte. Byte addressable in slave half-duplex mode. 0 32 read-write W7 Data buffer 7 0xB4 0x20 BUF7 32 bits data buffer 7, transferred in the unit of byte. Byte addressable in slave half-duplex mode. 0 32 read-write W8 Data buffer 8 0xB8 0x20 BUF8 32 bits data buffer 8, transferred in the unit of byte. Byte addressable in slave half-duplex mode. 0 32 read-write W9 Data buffer 9 0xBC 0x20 BUF9 32 bits data buffer 9, transferred in the unit of byte. Byte addressable in slave half-duplex mode. 0 32 read-write W10 Data buffer 10 0xC0 0x20 BUF10 32 bits data buffer 10, transferred in the unit of byte. Byte addressable in slave half-duplex mode. 0 32 read-write W11 Data buffer 11 0xC4 0x20 BUF11 32 bits data buffer 11, transferred in the unit of byte. Byte addressable in slave half-duplex mode. 0 32 read-write W12 Data buffer 12 0xC8 0x20 BUF12 32 bits data buffer 12, transferred in the unit of byte. Byte addressable in slave half-duplex mode. 0 32 read-write W13 Data buffer 13 0xCC 0x20 BUF13 32 bits data buffer 13, transferred in the unit of byte. Byte addressable in slave half-duplex mode. 0 32 read-write W14 Data buffer 14 0xD0 0x20 BUF14 32 bits data buffer 14, transferred in the unit of byte. Byte addressable in slave half-duplex mode. 0 32 read-write W15 Data buffer 15 0xD4 0x20 BUF15 32 bits data buffer 15, transferred in the unit of byte. Byte addressable in slave half-duplex mode. 0 32 read-write W16 Data buffer 16 0xD8 0x20 BUF16 32 bits data buffer 16, transferred in the unit of byte. Byte addressable in slave half-duplex mode. 0 32 read-write W17 Data buffer 17 0xDC 0x20 BUF17 32 bits data buffer 17, transferred in the unit of byte. Byte addressable in slave half-duplex mode. 0 32 read-write DIN_MODE SPI input delay mode configuration 0xE0 0x20 DIN0_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 0 3 read-write DIN1_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 3 3 read-write DIN2_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 6 3 read-write DIN3_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 9 3 read-write DIN4_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 12 3 read-write DIN5_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 15 3 read-write DIN6_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 18 3 read-write DIN7_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 21 3 read-write TIMING_CLK_ENA 1:enable hclk in spi_timing.v. 0: disable it. Can be configured in CONF state. 24 1 read-write DIN_NUM SPI input delay number configuration 0xE4 0x20 DIN0_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 0 2 read-write DIN1_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 2 2 read-write DIN2_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 4 2 read-write DIN3_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 6 2 read-write DIN4_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 8 2 read-write DIN5_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 10 2 read-write DIN6_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 12 2 read-write DIN7_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 14 2 read-write DOUT_MODE SPI output delay mode configuration 0xE8 0x20 DOUT0_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. 0 3 read-write DOUT1_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. 3 3 read-write DOUT2_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. 6 3 read-write DOUT3_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. 9 3 read-write DOUT4_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. 12 3 read-write DOUT5_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. 15 3 read-write DOUT6_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. 18 3 read-write DOUT7_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. 21 3 read-write DOUT_NUM SPI output delay number configuration 0xEC 0x20 DOUT0_NUM the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 0 2 read-write DOUT1_NUM the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 2 2 read-write DOUT2_NUM the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 4 2 read-write DOUT3_NUM the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 6 2 read-write DOUT4_NUM the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 8 2 read-write DOUT5_NUM the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 10 2 read-write DOUT6_NUM the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 12 2 read-write DOUT7_NUM the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 14 2 read-write LCD_CTRL LCD frame control register 0xF0 0x20 LCD_HB_FRONT It is the horizontal blank front porch of a frame. Can be configured in CONF state. 0 11 read-write LCD_VA_HEIGHT It is the vertical active height of a frame. Can be configured in CONF state. 11 10 read-write LCD_VT_HEIGHT It is the vertical total height of a frame. Can be configured in CONF state. 21 10 read-write LCD_MODE_EN 1: Enable LCD mode output vsync, hsync, de. 0: Disable. Can be configured in CONF state. 31 1 read-write LCD_CTRL1 LCD frame control1 register 0xF4 0x20 LCD_VB_FRONT It is the vertical blank front porch of a frame. Can be configured in CONF state. 0 8 read-write LCD_HA_WIDTH It is the horizontal active width of a frame. Can be configured in CONF state. 8 12 read-write LCD_HT_WIDTH It is the horizontal total width of a frame. Can be configured in CONF state. 20 12 read-write LCD_CTRL2 LCD frame control2 register 0xF8 0x20 0x00010001 LCD_VSYNC_WIDTH It is the position of spi_vsync active pulse in a line. Can be configured in CONF state. 0 7 read-write VSYNC_IDLE_POL It is the idle value of spi_vsync. Can be configured in CONF state. 7 1 read-write LCD_HSYNC_WIDTH It is the position of spi_hsync active pulse in a line. Can be configured in CONF state. 16 7 read-write HSYNC_IDLE_POL It is the idle value of spi_hsync. Can be configured in CONF state. 23 1 read-write LCD_HSYNC_POSITION It is the position of spi_hsync active pulse in a line. Can be configured in CONF state. 24 8 read-write LCD_D_MODE LCD delay number 0xFC 0x20 D_DQS_MODE the output spi_dqs is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. 0 3 read-write D_CD_MODE the output spi_cd is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. 3 3 read-write D_DE_MODE the output spi_de is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. 6 3 read-write D_HSYNC_MODE the output spi_hsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. 9 3 read-write D_VSYNC_MODE the output spi_vsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. 12 3 read-write DE_IDLE_POL It is the idle value of spi_de. 15 1 read-write HS_BLANK_EN 1: The pulse of spi_hsync is out in vertical blanking lines in seg-trans or one trans. 0: spi_hsync pulse is valid only in active region lines in seg-trans. 16 1 read-write LCD_D_NUM LCD delay mode 0x100 0x20 D_DQS_NUM the output spi_dqs is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 0 2 read-write D_CD_NUM the output spi_cd is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 2 2 read-write D_DE_NUM the output spi_de is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 4 2 read-write D_HSYNC_NUM the output spi_hsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 6 2 read-write D_VSYNC_NUM the output spi_vsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 8 2 read-write REG_DATE SPI version control 0x3FC 0x20 0x01907240 DATE SPI register version. 0 28 read-write SPI1 SPI (Serial Peripheral Interface) Controller 1 0x3F402000 SPI1 32 SPI2 SPI (Serial Peripheral Interface) Controller 2 0x3F424000 SPI2 33 SPI2_DMA 57 SPI3 SPI (Serial Peripheral Interface) Controller 3 0x3F425000 SPI3 34 SPI3_DMA 58 SPI4 SPI (Serial Peripheral Interface) Controller 4 0x3F437000 SPI4_DMA 85 SPI4 86 SYSCON SYSCON Peripheral SYSCON 0x3F426000 0x0 0xA0 registers SYSCLK_CONF 0x0 0x20 CLK_320M_EN 10 1 read-write CLK_EN 11 1 read-write RST_TICK_CNT 12 1 read-write TICK_CONF 0x4 0x20 0x00010727 XTAL_TICK_NUM 0 8 read-write CK8M_TICK_NUM 8 8 read-write TICK_ENABLE 16 1 read-write CLK_OUT_EN 0x8 0x20 0x000007FF CLK20_OEN 0 1 read-write CLK22_OEN 1 1 read-write CLK44_OEN 2 1 read-write CLK_BB_OEN 3 1 read-write CLK80_OEN 4 1 read-write CLK160_OEN 5 1 read-write CLK_320M_OEN 6 1 read-write CLK_ADC_INF_OEN 7 1 read-write CLK_DAC_CPU_OEN 8 1 read-write CLK40X_BB_OEN 9 1 read-write CLK_XTAL_OEN 10 1 read-write HOST_INF_SEL 0xC 0x20 PERI_IO_SWAP 0 8 read-write EXT_MEM_PMS_LOCK 0x10 0x20 EXT_MEM_PMS_LOCK 0 1 read-write FLASH_ACE0_ATTR 0x14 0x20 0x00000007 FLASH_ACE0_ATTR 0 3 read-write FLASH_ACE1_ATTR 0x18 0x20 0x00000007 FLASH_ACE1_ATTR 0 3 read-write FLASH_ACE2_ATTR 0x1C 0x20 0x00000007 FLASH_ACE2_ATTR 0 3 read-write FLASH_ACE3_ATTR 0x20 0x20 0x00000007 FLASH_ACE3_ATTR 0 3 read-write FLASH_ACE0_ADDR 0x24 0x20 S 0 32 read-write FLASH_ACE1_ADDR 0x28 0x20 0x10000000 S 0 32 read-write FLASH_ACE2_ADDR 0x2C 0x20 0x20000000 S 0 32 read-write FLASH_ACE3_ADDR 0x30 0x20 0x30000000 S 0 32 read-write FLASH_ACE0_SIZE 0x34 0x20 0x00001000 FLASH_ACE0_SIZE 0 16 read-write FLASH_ACE1_SIZE 0x38 0x20 0x00001000 FLASH_ACE1_SIZE 0 16 read-write FLASH_ACE2_SIZE 0x3C 0x20 0x00001000 FLASH_ACE2_SIZE 0 16 read-write FLASH_ACE3_SIZE 0x40 0x20 0x00001000 FLASH_ACE3_SIZE 0 16 read-write SRAM_ACE0_ATTR 0x44 0x20 0x00000007 SRAM_ACE0_ATTR 0 3 read-write SRAM_ACE1_ATTR 0x48 0x20 0x00000007 SRAM_ACE1_ATTR 0 3 read-write SRAM_ACE2_ATTR 0x4C 0x20 0x00000007 SRAM_ACE2_ATTR 0 3 read-write SRAM_ACE3_ATTR 0x50 0x20 0x00000007 SRAM_ACE3_ATTR 0 3 read-write SRAM_ACE0_ADDR 0x54 0x20 S 0 32 read-write SRAM_ACE1_ADDR 0x58 0x20 0x10000000 S 0 32 read-write SRAM_ACE2_ADDR 0x5C 0x20 0x20000000 S 0 32 read-write SRAM_ACE3_ADDR 0x60 0x20 0x30000000 S 0 32 read-write SRAM_ACE0_SIZE 0x64 0x20 0x00001000 SRAM_ACE0_SIZE 0 16 read-write SRAM_ACE1_SIZE 0x68 0x20 0x00001000 SRAM_ACE1_SIZE 0 16 read-write SRAM_ACE2_SIZE 0x6C 0x20 0x00001000 SRAM_ACE2_SIZE 0 16 read-write SRAM_ACE3_SIZE 0x70 0x20 0x00001000 SRAM_ACE3_SIZE 0 16 read-write SPI_MEM_PMS_CTRL 0x74 0x20 SPI_MEM_REJECT_INT 0 1 read-only SPI_MEM_REJECT_CLR 1 1 write-only SPI_MEM_REJECT_CDE 2 5 read-only SPI_MEM_REJECT_ADDR 0x78 0x20 SPI_MEM_REJECT_ADDR 0 32 read-only SDIO_CTRL 0x7C 0x20 SDIO_WIN_ACCESS_EN 0 1 read-write REDCY_SIG0 0x80 0x20 REDCY_SIG0 0 31 read-write REDCY_ANDOR 31 1 read-only REDCY_SIG1 0x84 0x20 REDCY_SIG1 0 31 read-write REDCY_NANDOR 31 1 read-only WIFI_BB_CFG 0x88 0x20 WIFI_BB_CFG 0 32 read-write WIFI_BB_CFG_2 0x8C 0x20 WIFI_BB_CFG_2 0 32 read-write WIFI_CLK_EN 0x90 0x20 0xFFFCE030 WIFI_CLK_EN 0 32 read-write WIFI_RST_EN 0x94 0x20 0xFFFCE030 WIFI_RST 0 32 read-write FRONT_END_MEM_PD 0x98 0x20 0x00000015 AGC_MEM_FORCE_PU 0 1 read-write AGC_MEM_FORCE_PD 1 1 read-write PBUS_MEM_FORCE_PU 2 1 read-write PBUS_MEM_FORCE_PD 3 1 read-write DC_MEM_FORCE_PU 4 1 read-write DC_MEM_FORCE_PD 5 1 read-write DATE 0x3FC 0x20 0x01907010 DATE 0 32 read-write SYSTEM System Configuration Registers SYSTEM 0x3F4C0000 0x0 0x94 registers ROM_CTRL_0 System ROM configuration register 0 0x0 0x20 0x00000003 ROM_FO This field is used to force on clock gate of internal ROM. 0 2 read-write ROM_CTRL_1 System ROM configuration register 1 0x4 0x20 0x0000000C ROM_FORCE_PD This field is used to power down internal ROM. 0 2 read-write ROM_FORCE_PU This field is used to power up internal ROM. 2 2 read-write SRAM_CTRL_0 System SRAM configuration register 0 0x8 0x20 0x003FFFFF SRAM_FO This field is used to force on clock gate of internal SRAM. 0 22 read-write SRAM_CTRL_1 System SRAM configuration register 1 0xC 0x20 SRAM_FORCE_PD This field is used to power down internal SRAM. 0 22 read-write CPU_PERI_CLK_EN CPU peripheral clock enable register 0x10 0x20 CLK_EN_DEDICATED_GPIO Set this bit to enable clock of DEDICATED GPIO module. 7 1 read-write CPU_PERI_RST_EN CPU peripheral reset register 0x14 0x20 0x00000080 RST_EN_DEDICATED_GPIO Set this bit to reset DEDICATED GPIO module. 7 1 read-write CPU_PER_CONF CPU peripheral clock configuration register 0x18 0x20 0x0000000C CPUPERIOD_SEL This field is used to select the clock frequency of CPU or CPU period. 0 2 read-write PLL_FREQ_SEL This field is used to select the PLL clock frequency based on CPU period. 2 1 read-write CPU_WAIT_MODE_FORCE_ON Set this bit to force on CPU wait mode. In this mode, the clock gate of CPU is turned off until any interrupts happen. This mode could also be force on via WAITI instruction. 3 1 read-write CPU_WAITI_DELAY_NUM Sets the number of delay cycles to enter CPU wait mode after a WAITI instruction. 4 4 read-write JTAG_CTRL_0 JTAG configuration register 0 0x1C 0x20 CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 Stores the 0 to 31 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. 0 32 write-only JTAG_CTRL_1 JTAG configuration register 1 0x20 0x20 CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 Stores the 32 to 63 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. 0 32 write-only JTAG_CTRL_2 JTAG configuration register 2 0x24 0x20 CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 Stores the 64 to 95 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. 0 32 write-only JTAG_CTRL_3 JTAG configuration register 3 0x28 0x20 CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 Stores the 96 to 127 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. 0 32 write-only JTAG_CTRL_4 JTAG configuration register 4 0x2C 0x20 CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 Stores the 128 to 159 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. 0 32 write-only JTAG_CTRL_5 JTAG configuration register 5 0x30 0x20 CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 Stores the 160 to 191 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. 0 32 write-only JTAG_CTRL_6 JTAG configuration register 6 0x34 0x20 CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 Stores the 192 to 223 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. 0 32 write-only JTAG_CTRL_7 JTAG configuration register 7 0x38 0x20 CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 Stores the 0 to 224 bits of the 255 bits register used to cancel the temporary disable of eFuse to JTAG. 0 32 write-only MEM_PD_MASK Memory power-related controlling register (under low-sleep) 0x3C 0x20 0x00000001 LSLP_MEM_PD_MASK Set this bit to allow the memory to work as usual when the chip enters the light-sleep state. 0 1 read-write PERIP_CLK_EN0 System peripheral clock (for hardware accelerators) enable register 0x40 0x20 0xF9C1E06F TIMERS_CLK_EN Set this bit to enable clock of timers. 0 1 read-write SPI01_CLK_EN Set this bit to enable clock of SPI0 and SPI1. 1 1 read-write UART_CLK_EN Set this bit to enable clock of UART0. 2 1 read-write WDG_CLK_EN Set this bit to enable clock of WDG. 3 1 read-write I2S0_CLK_EN Set this bit to enable clock of I2S0. 4 1 read-write UART1_CLK_EN Set this bit to enable clock of UART1. 5 1 read-write SPI2_CLK_EN Set this bit to enable clock of SPI2. 6 1 read-write I2C_EXT0_CLK_EN Set this bit to enable clock of I2C EXT0. 7 1 read-write UHCI0_CLK_EN Set this bit to enable clock of UHCI0. 8 1 read-write RMT_CLK_EN Set this bit to enable clock of remote controller. 9 1 read-write PCNT_CLK_EN Set this bit to enable clock of pulse count. 10 1 read-write LEDC_CLK_EN Set this bit to enable clock of LED PWM. 11 1 read-write UHCI1_CLK_EN Set this bit to enable clock of UHCI1. 12 1 read-write TIMERGROUP_CLK_EN Set this bit to enable clock of timer group0. 13 1 read-write EFUSE_CLK_EN Set this bit to enable clock of eFuse. 14 1 read-write TIMERGROUP1_CLK_EN Set this bit to enable clock of timer group1. 15 1 read-write SPI3_CLK_EN Set this bit to enable clock of SPI3. 16 1 read-write PWM0_CLK_EN Set this bit to enable clock of PWM0. 17 1 read-write I2C_EXT1_CLK_EN Set this bit to enable clock of I2C EXT1. 18 1 read-write TWAI_CLK_EN Set this bit to enable clock of CAN. 19 1 read-write PWM1_CLK_EN Set this bit to enable clock of PWM1. 20 1 read-write I2S1_CLK_EN Set this bit to enable clock of I2S1. 21 1 read-write SPI2_DMA_CLK_EN Set this bit to enable clock of SPI2 DMA. 22 1 read-write USB_CLK_EN Set this bit to enable clock of USB. 23 1 read-write UART_MEM_CLK_EN Set this bit to enable clock of UART memory. 24 1 read-write PWM2_CLK_EN Set this bit to enable clock of PWM2. 25 1 read-write PWM3_CLK_EN Set this bit to enable clock of PWM3. 26 1 read-write SPI3_DMA_CLK_EN Set this bit to enable clock of SPI3 DMA. 27 1 read-write APB_SARADC_CLK_EN Set this bit to enable clock of SAR ADC. 28 1 read-write SYSTIMER_CLK_EN Set this bit to enable clock of system timer. 29 1 read-write ADC2_ARB_CLK_EN Set this bit to enable clock of aribiter of ADC2. 30 1 read-write SPI4_CLK_EN Set this bit to enable clock of SPI4. 31 1 read-write PERIP_CLK_EN1 System peripheral clock (for hardware accelerators) enable register 1 0x44 0x20 CRYPTO_AES_CLK_EN Set this bit to enable clock of cryptography AES. 1 1 read-write CRYPTO_SHA_CLK_EN Set this bit to enable clock of cryptography SHA. 2 1 read-write CRYPTO_RSA_CLK_EN Set this bit to enable clock of cryptography RSA. 3 1 read-write CRYPTO_DS_CLK_EN Set this bit to enable clock of cryptography Digital Signature. 4 1 read-write CRYPTO_HMAC_CLK_EN Set this bit to enable clock of cryptography HMAC. 5 1 read-write CRYPTO_DMA_CLK_EN Set this bit to enable clock of cryptography DMA. 6 1 read-write PERIP_RST_EN0 System peripheral (hardware accelerators) reset register 0 0x48 0x20 TIMERS_RST Set this bit to reset timers. 0 1 read-write SPI01_RST Set this bit to reset SPI0 and SPI1. 1 1 read-write UART_RST Set this bit to reset UART0. 2 1 read-write WDG_RST Set this bit to reset WDG. 3 1 read-write I2S0_RST Set this bit to reset I2S0. 4 1 read-write UART1_RST Set this bit to reset UART1. 5 1 read-write SPI2_RST Set this bit to reset SPI2. 6 1 read-write I2C_EXT0_RST Set this bit to reset I2C EXT0. 7 1 read-write UHCI0_RST Set this bit to reset UHCI0. 8 1 read-write RMT_RST Set this bit to reset remote controller. 9 1 read-write PCNT_RST Set this bit to reset pulse count. 10 1 read-write LEDC_RST Set this bit to reset LED PWM. 11 1 read-write UHCI1_RST Set this bit to reset UHCI1. 12 1 read-write TIMERGROUP_RST Set this bit to reset timer group0. 13 1 read-write EFUSE_RST Set this bit to reset eFuse. 14 1 read-write TIMERGROUP1_RST Set this bit to reset timer group1. 15 1 read-write SPI3_RST Set this bit to reset SPI3. 16 1 read-write PWM0_RST Set this bit to reset PWM0. 17 1 read-write I2C_EXT1_RST Set this bit to reset I2C EXT1. 18 1 read-write TWAI_RST Set this bit to reset CAN. 19 1 read-write PWM1_RST Set this bit to reset PWM1. 20 1 read-write I2S1_RST Set this bit to reset I2S1. 21 1 read-write SPI2_DMA_RST Set this bit to reset SPI2 DMA. 22 1 read-write USB_RST Set this bit to reset USB. 23 1 read-write UART_MEM_RST Set this bit to reset UART memory. 24 1 read-write PWM2_RST Set this bit to reset PWM2. 25 1 read-write PWM3_RST Set this bit to reset PWM3. 26 1 read-write SPI3_DMA_RST Set this bit to reset SPI3 DMA. 27 1 read-write APB_SARADC_RST Set this bit to reset SAR ADC. 28 1 read-write SYSTIMER_RST Set this bit to reset system timer. 29 1 read-write ADC2_ARB_RST Set this bit to reset aribiter of ADC2. 30 1 read-write SPI4_RST Set this bit to reset SPI4. 31 1 read-write PERIP_RST_EN1 System peripheral (hardware accelerators) reset register 1 0x4C 0x20 0x0000007E CRYPTO_AES_RST Set this bit to reset cryptography AES. 1 1 read-write CRYPTO_SHA_RST Set this bit to reset cryptography SHA. 2 1 read-write CRYPTO_RSA_RST Set this bit to reset cryptography RSA. 3 1 read-write CRYPTO_DS_RST Set this bit to reset cryptography digital signature. 4 1 read-write CRYPTO_HMAC_RST Set this bit to reset cryptography HMAC. 5 1 read-write CRYPTO_DMA_RST Set this bit to reset cryptography DMA. 6 1 read-write LPCK_DIV_INT Low power clock divider integer register 0x50 0x20 0x000000FF LPCK_DIV_NUM This field is used to set the integer number of the divider value. 0 12 read-write BT_LPCK_DIV_FRAC Divider fraction configuration register for low-power clock 0x54 0x20 0x02000000 LPCLK_SEL_RTC_SLOW Set this bit to select RTC slow clock as the low power clock. 24 1 read-write LPCLK_SEL_8M Set this bit to select 8m clock as the low power clock. 25 1 read-write LPCLK_SEL_XTAL Set this bit to select xtal clock as the low power clock. 26 1 read-write LPCLK_SEL_XTAL32K Set this bit to select xtal32k clock as the low power clock. 27 1 read-write LPCLK_RTC_EN Set this bit to enable the RTC low power clock. 28 1 read-write CPU_INTR_FROM_CPU_0 CPU interrupt controlling register 0 0x58 0x20 CPU_INTR_FROM_CPU_0 Set this bit to generate CPU interrupt 0. This bit needs to be reset by software in the ISR process. 0 1 read-write CPU_INTR_FROM_CPU_1 CPU interrupt controlling register 1 0x5C 0x20 CPU_INTR_FROM_CPU_1 Set this bit to generate CPU interrupt 1. This bit needs to be reset by software in the ISR process. 0 1 read-write CPU_INTR_FROM_CPU_2 CPU interrupt controlling register 2 0x60 0x20 CPU_INTR_FROM_CPU_2 Set this bit to generate CPU interrupt 2. This bit needs to be reset by software in the ISR process. 0 1 read-write CPU_INTR_FROM_CPU_3 CPU interrupt controlling register 3 0x64 0x20 CPU_INTR_FROM_CPU_3 Set this bit to generate CPU interrupt 3. This bit needs to be reset by software in the ISR process. 0 1 read-write RSA_PD_CTRL RSA memory remapping register 0x68 0x20 0x00000001 RSA_MEM_PD Set this bit to power down RSA memory. This bit has the lowest priority. When Digital Signature occupies the RSA, this bit is invalid. 0 1 read-write RSA_MEM_FORCE_PU Set this bit to force power up RSA memory. This bit has the second highest priority. 1 1 read-write RSA_MEM_FORCE_PD Set this bit to force power down RSA memory. This bit has the highest priority. 2 1 read-write BUSTOEXTMEM_ENA EDMA enable register 0x6C 0x20 0x00000001 BUSTOEXTMEM_ENA Set this bit to enable bus to EDMA. 0 1 read-write CACHE_CONTROL Cache control register 0x70 0x20 0x00000003 PRO_ICACHE_CLK_ON Set this bit to enable clock of i-cache. 0 1 read-write PRO_DCACHE_CLK_ON Set this bit to enable clock of d-cache. 1 1 read-write PRO_CACHE_RESET Set this bit to reset cache. 2 1 read-write EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL External memory encrypt and decrypt controlling register 0x74 0x20 ENABLE_SPI_MANUAL_ENCRYPT Set this bit to enable Manual Encryption under SPI Boot mode. 0 1 read-write ENABLE_DOWNLOAD_DB_ENCRYPT Set this bit to enable Auto Encryption under Download Boot mode. 1 1 read-write ENABLE_DOWNLOAD_G0CB_DECRYPT Set this bit to enable Auto Decryption under Download Boot mode. 2 1 read-write ENABLE_DOWNLOAD_MANUAL_ENCRYPT Set this bit to enable Manual Encryption under Download Boot mode. 3 1 read-write RTC_FASTMEM_CONFIG RTC fast memory configuration register 0x78 0x20 0x7FF00000 RTC_MEM_CRC_START Set this bit to start the CRC of RTC memory. 8 1 read-write RTC_MEM_CRC_ADDR This field is used to set address of RTC memory for CRC. 9 11 read-write RTC_MEM_CRC_LEN This field is used to set length of RTC memory for CRC based on start address. 20 11 read-write RTC_MEM_CRC_FINISH This bit stores the status of RTC memory CRC. High level means finished while low level means not finished. 31 1 read-only RTC_FASTMEM_CRC RTC fast memory CRC controlling register 0x7C 0x20 RTC_MEM_CRC_RES This field stores the CRC result of RTC memory. 0 32 read-only Redundant_ECO_Ctrl Redundant ECO control register 0x80 0x20 REDUNDANT_ECO_DRIVE The redundant ECO drive bit to avoid optimization in circuits. 0 1 read-write REDUNDANT_ECO_RESULT The redundant ECO result bit to avoid optimization in circuits. 1 1 read-only CLOCK_GATE Clock gate control register 0x84 0x20 0x00000001 CLK_EN Set this bit to enable clock of this module. 0 1 read-write SRAM_CTRL_2 System SRAM configuration register 2 0x88 0x20 0x003FFFFF SRAM_FORCE_PU This field is used to power up internal SRAM. 0 22 read-write SYSCLK_CONF SoC clock configuration register 0x8C 0x20 0x00000001 PRE_DIV_CNT This field is used to set the count of prescaler of XTAL\_CLK. 0 10 read-write SOC_CLK_SEL This field is used to select SOC clock. 10 2 read-write CLK_XTAL_FREQ This field is used to read XTAL frequency in MHz. 12 7 read-only CLK_DIV_EN Not used, extends from ESP32. 19 1 read-only DATE Version control register 0xFFC 0x20 0x01908020 DATE Version control register. 0 28 read-write SYSTIMER System Timer SYSTIMER 0x3F423000 0x0 0x54 registers SYSTIMER_TARGET0 71 SYSTIMER_TARGET1 72 SYSTIMER_TARGET2 73 CONF Configure system timer clock 0x0 0x20 CLK_FO System timer clock force enable. 0 1 read-write CLK_EN Register clock enable. 31 1 read-write LOAD Load value to system timer 0x4 0x20 TIMER_LOAD Set this bit to 1, the value stored in SYSTIMER_TIMER_LOAD_HI and in SYSTIMER_TIMER_LOAD_LO will be loaded to system timer 31 1 write-only LOAD_HI High 32 bits to be loaded to system timer 0x8 0x20 TIMER_LOAD_HI The value to be loaded into system timer, high 32 bits. 0 32 read-write LOAD_LO Low 32 bits to be loaded to system timer 0xC 0x20 TIMER_LOAD_LO The value to be loaded into system timer, low 32 bits. 0 32 read-write STEP System timer accumulation step 0x10 0x20 0x00000450 TIMER_XTAL_STEP Set system timer increment step when using XTAL_CLK. 0 10 read-write TIMER_PLL_STEP Set system timer increment step when using PLL_CLK 10 10 read-write TARGET0_HI System timer target 0, high 32 bits 0x14 0x20 TIMER_TARGET0_HI System timer target 0, high 32 bits. 0 32 read-write TARGET0_LO System timer target 0, low 32 bits 0x18 0x20 TIMER_TARGET0_LO System timer target 0, low 32 bits. 0 32 read-write TARGET1_HI System timer target 1, high 32 bits 0x1C 0x20 TIMER_TARGET1_HI System timer target 1, high 32 bits. 0 32 read-write TARGET1_LO System timer target 1, low 32 bits 0x20 0x20 TIMER_TARGET1_LO System timer target 1, low 32 bits. 0 32 read-write TARGET2_HI System timer target 2, high 32 bits 0x24 0x20 TIMER_TARGET2_HI System timer target 2, high 32 bits. 0 32 read-write TARGET2_LO System timer target 2, low 32 bits 0x28 0x20 TIMER_TARGET2_LO System timer target 2, low 32 bits. 0 32 read-write TARGET0_CONF Configure work mode for system timer target 0 0x2C 0x20 TARGET0_PERIOD Set alarm period for system timer target 0, only valid in periodic alarms mode. 0 30 read-write TARGET0_PERIOD_MODE Set work mode for system timer target 0. 0: work in a timedelay alarm mode; 1: work in periodic alarms mode. 30 1 read-write TARGET0_WORK_EN System timer target 0 work enable. 31 1 read-write TARGET1_CONF Configure work mode for system timer target 1 0x30 0x20 TARGET1_PERIOD Set alarm period for system timer target 1, only valid in periodic alarms mode. 0 30 read-write TARGET1_PERIOD_MODE Set work mode for system timer target 1. 0: work in a timedelay alarm mode; 1: work in periodic alarms mode. 30 1 read-write TARGET1_WORK_EN System timer target 1 work enable. 31 1 read-write TARGET2_CONF Configure work mode for system timer target 2 0x34 0x20 TARGET2_PERIOD Set alarm period for system timer target 2, only valid in periodic alarms mode. 0 30 read-write TARGET2_PERIOD_MODE Set work mode for system timer target 2. 0: work in a timedelay alarm mode; 1: work in periodic alarms mode. 30 1 read-write TARGET2_WORK_EN System timer target 2 work enable. 31 1 read-write UNIT0_OP Read out system timer value 0x38 0x20 TIMER_UNIT0_VALUE_VALID Check if it is valid to read out timer value from registers. 0: Not ready to read timer value from registers; 1: Ready to read timer value from registers 30 1 read-only TIMER_UNIT0_UPDATE Update system timer value to registers. 31 1 write-only UNIT0_VALUE_HI System timer value, high 32 bits 0x3C 0x20 TIMER_VALUE_HI System timer value, high 32 bits. 0 32 read-only UNIT0_VALUE_LO System timer value, low 32 bits 0x40 0x20 TIMER_VALUE_LO System timer value, low 32 bits. 0 32 read-only INT_ENA System timer interrupt enable 0x44 0x20 TARGET0_INT_ENA Interrupt enable bit of system timer target 0. 0 1 read-write TARGET1_INT_ENA Interrupt enable bit of system timer target 1. 1 1 read-write TARGET2_INT_ENA Interrupt enable bit of system timer target 2. 2 1 read-write INT_RAW System timer interrupt raw 0x48 0x20 INT0_RAW Interrupt raw bit of system timer target 0. 0 1 read-only INT1_RAW Interrupt raw bit of system timer target 1. 1 1 read-only INT2_RAW Interrupt raw bit of system timer target 2. 2 1 read-only INT_CLR System timer interrupt clear 0x4C 0x20 TARGET0_INT_CLR Interrupt clear bit of system timer target 0. 0 1 write-only TARGET1_INT_CLR Interrupt clear bit of system timer target 1. 1 1 write-only TARGET2_INT_CLR Interrupt clear bit of system timer target 2. 2 1 write-only DATE Version control register 0xFC 0x20 0x01807160 DATE Version control register 0 32 read-write TIMG0 Timer Group 0 TIMG 0x3F41F000 0x0 0xB4 registers TG0_T0_LEVEL 15 TG0_T1_LEVEL 16 TG0_WDT_LEVEL 17 TG0_LACT_LEVEL 18 TG0_T0_EDGE 62 TG0_T1_EDGE 63 TG0_WDT_EDGE 64 TG0_LACT_EDGE 65 2 0x24 T%sCONFIG Timer %s configuration register 0x0 0x20 0x60002000 USE_XTAL 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. 9 1 read-write ALARM_EN When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs. 10 1 read-write LEVEL_INT_EN When set, an alarm will generate a level type interrupt. 11 1 read-write EDGE_INT_EN When set, an alarm will generate an edge type interrupt. 12 1 read-write DIVIDER Timer %s clock (T%s_clk) prescaler value. 13 16 read-write AUTORELOAD When set, timer %s auto-reload at alarm is enabled. 29 1 read-write INCREASE When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement. 30 1 read-write EN When set, the timer %s time-base counter is enabled. 31 1 read-write 2 0x24 T%sLO Timer %s current value, low 32 bits 0x4 0x20 LO After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter of timer %s can be read here. 0 32 read-only 2 0x24 T%sHI Timer %s current value, high 32 bits 0x8 0x20 HI After writing to TIMG_T%sUPDATE_REG, the high 32 bits of the time-base counter of timer %s can be read here. 0 32 read-only 2 0x24 T%sUPDATE Write to copy current timer value to TIMG_T%sLO_REG or TIMGn_T%sHI_REG 0xC 0x20 UPDATE After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. 31 1 read-write 2 0x24 T%sALARMLO Timer %s alarm value, low 32 bits 0x10 0x20 ALARM_LO Timer %s alarm trigger time-base counter value, low 32 bits. 0 32 read-write 2 0x24 T%sALARMHI Timer %s alarm value, high bits 0x14 0x20 ALARM_HI Timer %s alarm trigger time-base counter value, high 32 bits. 0 32 read-write 2 0x24 T%sLOADLO Timer %s reload value, low 32 bits 0x18 0x20 LOAD_LO Low 32 bits of the value that a reload will load onto timer %s time-base counter. 0 32 read-write 2 0x24 T%sLOADHI Timer %s reload value, high 32 bits 0x1C 0x20 LOAD_HI High 32 bits of the value that a reload will load onto timer %s time-base counter. 0 32 read-write 2 0x24 T%sLOAD Write to reload timer from TIMG_T%sLOADLO_REG or TIMG_T%sLOADHI_REG 0x20 0x20 LOAD Write any value to trigger a timer %s time-base counter reload. 0 32 write-only WDTCONFIG0 Watchdog timer configuration register 0x48 0x20 0x0004C000 WDT_APPCPU_RESET_EN Reserved. 12 1 read-write WDT_PROCPU_RESET_EN WDT reset CPU enable. 13 1 read-write WDT_FLASHBOOT_MOD_EN When set, Flash boot protection is enabled. 14 1 read-write WDT_SYS_RESET_LENGTH System reset signal length selection. 0: 100 ns. 1: 200 ns. 2: 300 ns. 3: 400 ns. 4: 500 ns. 5: 800 ns. 6: 1.6 us. 7: 3.2 us. 15 3 read-write WDT_CPU_RESET_LENGTH CPU reset signal length selection. 0: 100 ns. 1: 200 ns. 2: 300 ns. 3: 400 ns. 4: 500 ns. 5: 800 ns. 6: 1.6 us. 7: 3.2 us. 18 3 read-write WDT_LEVEL_INT_EN When set, a level type interrupt will occur at the timeout of a stage configured to generate an interrupt. 21 1 read-write WDT_EDGE_INT_EN When set, an edge type interrupt will occur at the timeout of a stage configured to generate an interrupt. 22 1 read-write WDT_STG3 Stage 3 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system. 23 2 read-write WDT_STG2 Stage 2 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system. 25 2 read-write WDT_STG1 Stage 1 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system. 27 2 read-write WDT_STG0 Stage 0 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system. 29 2 read-write WDT_EN When set, MWDT is enabled. 31 1 read-write WDTCONFIG1 Watchdog timer prescaler register 0x4C 0x20 0x00010000 WDT_CLK_PRESCALE MWDT clock prescaler value. MWDT clock period = 12.5 ns * TIMG_WDT_CLK_PRESCALE. 16 16 read-write WDTCONFIG2 Watchdog timer stage 0 timeout value 0x50 0x20 0x018CBA80 WDT_STG0_HOLD Stage 0 timeout value, in MWDT clock cycles. 0 32 read-write WDTCONFIG3 Watchdog timer stage 1 timeout value 0x54 0x20 0x07FFFFFF WDT_STG1_HOLD Stage 1 timeout value, in MWDT clock cycles. 0 32 read-write WDTCONFIG4 Watchdog timer stage 2 timeout value 0x58 0x20 0x000FFFFF WDT_STG2_HOLD Stage 2 timeout value, in MWDT clock cycles. 0 32 read-write WDTCONFIG5 Watchdog timer stage 3 timeout value 0x5C 0x20 0x000FFFFF WDT_STG3_HOLD Stage 3 timeout value, in MWDT clock cycles. 0 32 read-write WDTFEED Write to feed the watchdog timer 0x60 0x20 WDT_FEED Write any value to feed the MWDT. 0 32 write-only WDTWPROTECT Watchdog write protect register 0x64 0x20 0x50D83AA1 WDT_WKEY If the register contains a different value than its reset value, write protection is enabled. 0 32 read-write RTCCALICFG RTC calibration configuration register 0x68 0x20 0x00013000 RTC_CALI_START_CYCLING When set, periodic calibration is enabled. 12 1 read-write RTC_CALI_CLK_SEL Used to select the clock to be calibrated. 0: RTC_CLK. 1: RTC20M_D256_CLK. 2: XTAL32K_CLK. 13 2 read-write RTC_CALI_RDY Set this bit to mark the completion of calibration. 15 1 read-only RTC_CALI_MAX Calibration time, in cycles of the clock to be calibrated. 16 15 read-write RTC_CALI_START Set this bit to starts calibration. 31 1 read-write RTCCALICFG1 RTC calibration configuration register 1 0x6C 0x20 RTC_CALI_CYCLING_DATA_VLD Periodic calibration valid signal. 0 1 read-only RTC_CALI_VALUE Calibration value when cycles of clock to be calibrated reach TIMG_RTC_CALI_MAX, in unit of XTAL_CLK clock cycles. 7 25 read-only LACTCONFIG LACT configuration register 0x70 0x20 0x60002300 LACT_USE_REFTICK Reserved. 6 1 read-write LACT_RTC_ONLY Reserved. 7 1 read-write LACT_CPST_EN Reserved. 8 1 read-write LACT_LAC_EN Reserved. 9 1 read-write LACT_ALARM_EN Reserved. 10 1 read-write LACT_LEVEL_INT_EN Reserved. 11 1 read-write LACT_EDGE_INT_EN Reserved. 12 1 read-write LACT_DIVIDER Reserved. 13 16 read-write LACT_AUTORELOAD Reserved. 29 1 read-write LACT_INCREASE Reserved. 30 1 read-write LACT_EN Reserved. 31 1 read-write LACTRTC LACT RTC register 0x74 0x20 LACT_RTC_STEP_LEN Reserved. 6 26 read-write LACTLO LACT low register 0x78 0x20 LACT_LO Reserved. 0 32 read-only LACTHI LACT high register 0x7C 0x20 LACT_HI Reserved. 0 32 read-only LACTUPDATE LACT update register 0x80 0x20 LACT_UPDATE Reserved. 0 32 write-only LACTALARMLO LACT alarm low register 0x84 0x20 LACT_ALARM_LO Reserved. 0 32 read-write LACTALARMHI LACT alarm high register 0x88 0x20 LACT_ALARM_HI Reserved. 0 32 read-write LACTLOADLO LACT load low register 0x8C 0x20 LACT_LOAD_LO Reserved. 0 32 read-write LACTLOADHI Timer LACT load high register 0x90 0x20 LACT_LOAD_HI Reserved. 0 32 read-write LACTLOAD Timer LACT load register 0x94 0x20 LACT_LOAD Reserved. 0 32 write-only INT_ENA_TIMERS Interrupt enable bits 0x98 0x20 T0_INT_ENA The interrupt enable bit for the TIMG_T0_INT interrupt. 0 1 read-write T1_INT_ENA The interrupt enable bit for the TIMG_T1_INT interrupt. 1 1 read-write WDT_INT_ENA The interrupt enable bit for the TIMG_WDT_INT interrupt. 2 1 read-write LACT_INT_ENA The interrupt enable bit for the TIMG_LACT_INT interrupt. 3 1 read-write INT_RAW_TIMERS Raw interrupt status 0x9C 0x20 T0_INT_RAW The raw interrupt status bit for the TIMG_T0_INT interrupt. 0 1 read-only T1_INT_RAW The raw interrupt status bit for the TIMG_T1_INT interrupt. 1 1 read-only WDT_INT_RAW The raw interrupt status bit for the TIMG_WDT_INT interrupt. 2 1 read-only LACT_INT_RAW The raw interrupt status bit for the TIMG_LACT_INT interrupt. 3 1 read-only INT_ST_TIMERS Masked interrupt status 0xA0 0x20 T0_INT_ST The masked interrupt status bit for the TIMG_T0_INT interrupt. 0 1 read-only T1_INT_ST The masked interrupt status bit for the TIMG_T1_INT interrupt. 1 1 read-only WDT_INT_ST The masked interrupt status bit for the TIMG_WDT_INT interrupt. 2 1 read-only LACT_INT_ST The masked interrupt status bit for the TIMG_LACT_INT interrupt. 3 1 read-only INT_CLR_TIMERS Interrupt clear bits 0xA4 0x20 T0_INT_CLR Set this bit to clear the TIMG_T0_INT interrupt. 0 1 write-only T1_INT_CLR Set this bit to clear the TIMG_T1_INT interrupt. 1 1 write-only WDT_INT_CLR Set this bit to clear the TIMG_WDT_INT interrupt. 2 1 write-only LACT_INT_CLR Set this bit to clear the TIMG_LACT_INT interrupt. 3 1 write-only RTCCALICFG2 Timer group calibration register 0xA8 0x20 0xFFFFFF98 RTC_CALI_TIMEOUT RTC calibration timeout indicator 0 1 read-only RTC_CALI_TIMEOUT_RST_CNT Cycles that release calibration timeout reset 3 4 read-write RTC_CALI_TIMEOUT_THRES Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered. 7 25 read-write TIMERS_DATE Version control register 0xF8 0x20 0x01907261 TIMERS_DATE Version control register. 0 28 read-write REGCLK Timer group clock gate register 0xFC 0x20 CLK_EN Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software. 31 1 read-write TIMG1 Timer Group 1 0x3F420000 TG1_T0_LEVEL 19 TG1_T1_LEVEL 20 TG1_WDT_LEVEL 21 TG1_LACT_LEVEL 22 TG1_T0_EDGE 66 TG1_T1_EDGE 67 TG1_WDT_EDGE 68 TG1_LACT_EDGE 69 TWAI0 Two-Wire Automotive Interface TWAI 0x3F42B000 0x0 0x6C registers TWAI0 47 MODE Mode Register 0x0 0x20 0x00000001 RESET_MODE This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode. 0 1 read-write LISTEN_ONLY_MODE 1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter. 1 1 read-write SELF_TEST_MODE 1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command. 2 1 read-write RX_FILTER_MODE This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode. 3 1 read-write CMD Command Register 0x4 0x20 TX_REQ Set the bit to 1 to allow the driving nodes start transmission. 0 1 write-only ABORT_TX Set the bit to 1 to cancel a pending transmission request. 1 1 write-only RELEASE_BUF Set the bit to 1 to release the RX buffer. 2 1 write-only CLR_OVERRUN Set the bit to 1 to clear the data overrun status bit. 3 1 write-only SELF_RX_REQ Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously. 4 1 write-only STATUS Status register 0x8 0x20 RX_BUF_ST 1: The data in the RX buffer is not empty, with at least one received data packet. 0 1 read-only OVERRUN_ST 1: The RX FIFO is full and data overrun has occurred. 1 1 read-only TX_BUF_ST 1: The TX buffer is empty, the CPU may write a message into it. 2 1 read-only TX_COMPLETE 1: The TWAI controller has successfully received a packet from the bus. 3 1 read-only RX_ST 1: The TWAI Controller is receiving a message from the bus. 4 1 read-only TX_ST 1: The TWAI Controller is transmitting a message to the bus. 5 1 read-only ERR_ST 1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG. 6 1 read-only BUS_OFF_ST 1: In bus-off status, the TWAI Controller is no longer involved in bus activities. 7 1 read-only MISS_ST This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete 8 1 read-only INT_RAW Interrupt Register 0xC 0x20 RX_INT_ST Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO. 0 1 read-only TX_INT_ST Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute. 1 1 read-only ERR_WARN_INT_ST Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0). 2 1 read-only OVERRUN_INT_ST Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO. 3 1 read-only ERR_PASSIVE_INT_ST Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters. 5 1 read-only ARB_LOST_INT_ST Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated. 6 1 read-only BUS_ERR_INT_ST Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus. 7 1 read-only INT_ENA Interrupt Enable Register 0x10 0x20 RX_INT_ENA Set this bit to 1 to enable receive interrupt. 0 1 read-write TX_INT_ENA Set this bit to 1 to enable transmit interrupt. 1 1 read-write ERR_WARN_INT_ENA Set this bit to 1 to enable error warning interrupt. 2 1 read-write OVERRUN_INT_ENA Set this bit to 1 to enable data overrun interrupt. 3 1 read-write ERR_PASSIVE_INT_ENA Set this bit to 1 to enable error passive interrupt. 5 1 read-write ARB_LOST_INT_ENA Set this bit to 1 to enable arbitration lost interrupt. 6 1 read-write BUS_ERR_INT_ENA Set this bit to 1 to enable error interrupt. 7 1 read-write BUS_TIMING_0 Bus Timing Register 0 0x18 0x20 BAUD_PRESC Baud Rate Prescaler, determines the frequency dividing ratio. 0 14 read-write SYNC_JUMP_WIDTH Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. 14 2 read-write BUS_TIMING_1 Bus Timing Register 1 0x1C 0x20 TIME_SEG1 The width of PBS1. 0 4 read-write TIME_SEG2 The width of PBS2. 4 3 read-write TIME_SAMP The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times 7 1 read-write ARB_LOST_CAP Arbitration Lost Capture Register 0x2C 0x20 ARB_LOST_CAP This register contains information about the bit position of lost arbitration. 0 5 read-only ERR_CODE_CAP Error Code Capture Register 0x30 0x20 ECC_SEGMENT This register contains information about the location of errors, see Table 181 for details. 0 5 read-only ECC_DIRECTION This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message 5 1 read-only ECC_TYPE This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error 6 2 read-only ERR_WARNING_LIMIT Error Warning Limit Register 0x34 0x20 0x00000060 ERR_WARNING_LIMIT Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid). 0 8 read-write RX_ERR_CNT Receive Error Counter Register 0x38 0x20 RX_ERR_CNT The RX error counter register, reflects value changes under reception status. 0 8 read-write TX_ERR_CNT Transmit Error Counter Register 0x3C 0x20 TX_ERR_CNT The TX error counter register, reflects value changes under transmission status. 0 8 read-write DATA_0 Data register 0 0x40 0x20 TX_BYTE_0 In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode. 0 8 read-write DATA_1 Data register 1 0x44 0x20 TX_BYTE_1 In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode. 0 8 read-write DATA_2 Data register 2 0x48 0x20 TX_BYTE_2 In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode. 0 8 read-write DATA_3 Data register 3 0x4C 0x20 TX_BYTE_3 In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode. 0 8 read-write DATA_4 Data register 4 0x50 0x20 TX_BYTE_4 In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode. 0 8 read-write DATA_5 Data register 5 0x54 0x20 TX_BYTE_5 In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode. 0 8 read-write DATA_6 Data register 6 0x58 0x20 TX_BYTE_6 In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode. 0 8 read-write DATA_7 Data register 7 0x5C 0x20 TX_BYTE_7 In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode. 0 8 read-write DATA_8 Data register 8 0x60 0x20 TX_BYTE_8 Stored the 8th byte information of the data to be transmitted under operating mode. 0 8 read-write DATA_9 Data register 9 0x64 0x20 TX_BYTE_9 Stored the 9th byte information of the data to be transmitted under operating mode. 0 8 read-write DATA_10 Data register 10 0x68 0x20 TX_BYTE_10 Stored the 10th byte information of the data to be transmitted under operating mode. 0 8 read-write DATA_11 Data register 11 0x6C 0x20 TX_BYTE_11 Stored the 11th byte information of the data to be transmitted under operating mode. 0 8 read-write DATA_12 Data register 12 0x70 0x20 TX_BYTE_12 Stored the 12th byte information of the data to be transmitted under operating mode. 0 8 read-write RX_MESSAGE_CNT Receive Message Counter Register 0x74 0x20 RX_MESSAGE_COUNTER This register reflects the number of messages available within the RX FIFO. 0 7 read-only CLOCK_DIVIDER Clock Divider register 0x7C 0x20 CD These bits are used to configure frequency dividing coefficients of the external CLKOUT pin. 0 8 read-write CLOCK_OFF This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin 8 1 read-write UART0 UART (Universal Asynchronous Receiver-Transmitter) Controller 0 UART 0x3F400000 0x0 0x7C registers UART0 37 FIFO FIFO data register 0x0 0x20 RXFIFO_RD_BYTE UART 0 accesses FIFO via this register. 0 8 read-write INT_RAW Raw interrupt status 0x4 0x20 RXFIFO_FULL_INT_RAW This interrupt raw bit turns to high level when the receiver receives more data than what UART_RXFIFO_FULL_THRHD specifies. 0 1 read-only TXFIFO_EMPTY_INT_RAW This interrupt raw bit turns to high level when the amount of data in TX FIFO is less than what UART_TXFIFO_EMPTY_THRHD specifies. 1 1 read-only PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when the receiver detects a parity error in the data. 2 1 read-only FRM_ERR_INT_RAW This interrupt raw bit turns to high level when the receiver detects a data frame error. 3 1 read-only RXFIFO_OVF_INT_RAW This interrupt raw bit turns to high level when the receiver receives more data than the capacity of RX FIFO. 4 1 read-only DSR_CHG_INT_RAW This interrupt raw bit turns to high level when the receiver detects the edge change of DSRn signal. 5 1 read-only CTS_CHG_INT_RAW This interrupt raw bit turns to high level when the receiver detects the edge change of CTSn signal. 6 1 read-only BRK_DET_INT_RAW This interrupt raw bit turns to high level when the receiver detects a 0 after the stop bit. 7 1 read-only RXFIFO_TOUT_INT_RAW This interrupt raw bit turns to high level when the receiver takes more time than UART_RX_TOUT_THRHD to receive a byte. 8 1 read-only SW_XON_INT_RAW This interrupt raw bit turns to high level when the receiver receives an XON character and UART_SW_FLOW_CON_EN is set to 1. 9 1 read-only SW_XOFF_INT_RAW This interrupt raw bit turns to high level when the receiver receives an XOFF character and UART_SW_FLOW_CON_EN is set to 1. 10 1 read-only GLITCH_DET_INT_RAW This interrupt raw bit turns to high level when the receiver detects a glitch in the middle of a start bit. 11 1 read-only TX_BRK_DONE_INT_RAW This interrupt raw bit turns to high level when the transmitter completes sending NULL characters, after all data in TX FIFO are sent. 12 1 read-only TX_BRK_IDLE_DONE_INT_RAW This interrupt raw bit turns to high level when the transmitter has kept the shortest duration after sending the last data. 13 1 read-only TX_DONE_INT_RAW This interrupt raw bit turns to high level when the transmitter has sent out all data in FIFO. 14 1 read-only RS485_PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when the receiver detects a parity error from the echo of the transmitter in RS485 mode. 15 1 read-only RS485_FRM_ERR_INT_RAW This interrupt raw bit turns to high level when the receiver detects a data frame error from the echo of the transmitter in RS485 mode. 16 1 read-only RS485_CLASH_INT_RAW This interrupt raw bit turns to high level when a collision is detected between the transmitter and the receiver in RS485 mode. 17 1 read-only AT_CMD_CHAR_DET_INT_RAW This interrupt raw bit turns to high level when the receiver detects the configured UART_AT_CMD CHAR. 18 1 read-only WAKEUP_INT_RAW This interrupt raw bit turns to high level when input RXD edge changes more times than what UART_ACTIVE_THRESHOLD specifies in Light-sleep mode. 19 1 read-only INT_ST Masked interrupt status 0x8 0x20 RXFIFO_FULL_INT_ST This is the status bit for UART_RXFIFO_FULL_INT when UART_RXFIFO_FULL_INT_ENA is set to 1. 0 1 read-only TXFIFO_EMPTY_INT_ST This is the status bit for UART_TXFIFO_EMPTY_INT when UART_TXFIFO_EMPTY_INT_ENA is set to 1. 1 1 read-only PARITY_ERR_INT_ST This is the status bit for UART_PARITY_ERR_INT when UART_PARITY_ERR_INT_ENA is set to 1. 2 1 read-only FRM_ERR_INT_ST This is the status bit for UART_FRM_ERR_INT when UART_FRM_ERR_INT_ENA is set to 1. 3 1 read-only RXFIFO_OVF_INT_ST This is the status bit for UART_RXFIFO_OVF_INT when UART_RXFIFO_OVF_INT_ENA is set to 1. 4 1 read-only DSR_CHG_INT_ST This is the status bit for UART_DSR_CHG_INT when UART_DSR_CHG_INT_ENA is set to 1. 5 1 read-only CTS_CHG_INT_ST This is the status bit for UART_CTS_CHG_INT when UART_CTS_CHG_INT_ENA is set to 1. 6 1 read-only BRK_DET_INT_ST This is the status bit for UART_BRK_DET_INT when UART_BRK_DET_INT_ENA is set to 1. 7 1 read-only RXFIFO_TOUT_INT_ST This is the status bit for UART_RXFIFO_TOUT_INT when UART_RXFIFO_TOUT_INT_ENA is set to 1. 8 1 read-only SW_XON_INT_ST This is the status bit for UART_SW_XON_INT when UART_SW_XON_INT_ENA is set to 1. 9 1 read-only SW_XOFF_INT_ST This is the status bit for UART_SW_XOFF_INT when UART_SW_XOFF_INT_ENA is set to 1. 10 1 read-only GLITCH_DET_INT_ST This is the status bit for UART_GLITCH_DET_INT when UART_GLITCH_DET_INT_ENA is set to 1. 11 1 read-only TX_BRK_DONE_INT_ST This is the status bit for UART_TX_BRK_DONE_INT when UART_TX_BRK_DONE_INT_ENA is set to 1. 12 1 read-only TX_BRK_IDLE_DONE_INT_ST This is the status bit for UART_TX_BRK_IDLE_DONE_INT when UART_TX_BRK_IDLE_DONE_INT_ENA is set to 1. 13 1 read-only TX_DONE_INT_ST This is the status bit for UART_TX_DONE_INT when UART_TX_DONE_INT_ENA is set to 1. 14 1 read-only RS485_PARITY_ERR_INT_ST This is the status bit for UART_RS485_PARITY_ERR_INT when UART_RS485_PARITY_INT_ENA is set to 1. 15 1 read-only RS485_FRM_ERR_INT_ST This is the status bit for UART_RS485_FRM_ERR_INT when UART_RS485_FRM_ERR_INT_ENA is set to 1. 16 1 read-only RS485_CLASH_INT_ST This is the status bit for UART_RS485_CLASH_INT when UART_RS485_CLASH_INT_ENA is set to 1. 17 1 read-only AT_CMD_CHAR_DET_INT_ST This is the status bit for UART_AT_CMD_CHAR_DET_INT when UART_AT_CMD_CHAR_DET_INT_ENA is set to 1. 18 1 read-only WAKEUP_INT_ST This is the status bit for UART_WAKEUP_INT when UART_WAKEUP_INT_ENA is set to 1. 19 1 read-only INT_ENA Interrupt enable bits 0xC 0x20 RXFIFO_FULL_INT_ENA This is the enable bit for UART_RXFIFO_FULL_INT. 0 1 read-write TXFIFO_EMPTY_INT_ENA This is the enable bit for UART_TXFIFO_EMPTY_INT. 1 1 read-write PARITY_ERR_INT_ENA This is the enable bit for UART_PARITY_ERR_INT. 2 1 read-write FRM_ERR_INT_ENA This is the enable bit for UART_FRM_ERR_INT. 3 1 read-write RXFIFO_OVF_INT_ENA This is the enable bit for UART_RXFIFO_OVF_INT. 4 1 read-write DSR_CHG_INT_ENA This is the enable bit for UART_DSR_CHG_INT. 5 1 read-write CTS_CHG_INT_ENA This is the enable bit for UART_CTS_CHG_INT. 6 1 read-write BRK_DET_INT_ENA This is the enable bit for UART_BRK_DET_INT. 7 1 read-write RXFIFO_TOUT_INT_ENA This is the enable bit for UART_RXFIFO_TOUT_INT. 8 1 read-write SW_XON_INT_ENA This is the enable bit for UART_SW_XON_INT. 9 1 read-write SW_XOFF_INT_ENA This is the enable bit for UART_SW_XOFF_INT. 10 1 read-write GLITCH_DET_INT_ENA This is the enable bit for UART_GLITCH_DET_INT. 11 1 read-write TX_BRK_DONE_INT_ENA This is the enable bit for UART_TX_BRK_DONE_INT. 12 1 read-write TX_BRK_IDLE_DONE_INT_ENA This is the enable bit for UART_TX_BRK_IDLE_DONE_INT. 13 1 read-write TX_DONE_INT_ENA This is the enable bit for UART_TX_DONE_INT. 14 1 read-write RS485_PARITY_ERR_INT_ENA This is the enable bit for UART_RS485_PARITY_ERR_INT. 15 1 read-write RS485_FRM_ERR_INT_ENA This is the enable bit for UART_RS485_PARITY_ERR_INT. 16 1 read-write RS485_CLASH_INT_ENA This is the enable bit for UART_RS485_CLASH_INT. 17 1 read-write AT_CMD_CHAR_DET_INT_ENA This is the enable bit for UART_AT_CMD_CHAR_DET_INT. 18 1 read-write WAKEUP_INT_ENA This is the enable bit for UART_WAKEUP_INT. 19 1 read-write INT_CLR Interrupt clear bits 0x10 0x20 RXFIFO_FULL_INT_CLR Set this bit to clear UART_THE RXFIFO_FULL_INT interrupt. 0 1 write-only TXFIFO_EMPTY_INT_CLR Set this bit to clear UART_TXFIFO_EMPTY_INT interrupt. 1 1 write-only PARITY_ERR_INT_CLR Set this bit to clear UART_PARITY_ERR_INT interrupt. 2 1 write-only FRM_ERR_INT_CLR Set this bit to clear UART_FRM_ERR_INT interrupt. 3 1 write-only RXFIFO_OVF_INT_CLR Set this bit to clear UART_UART_RXFIFO_OVF_INT interrupt. 4 1 write-only DSR_CHG_INT_CLR Set this bit to clear UART_DSR_CHG_INT interrupt. 5 1 write-only CTS_CHG_INT_CLR Set this bit to clear UART_CTS_CHG_INT interrupt. 6 1 write-only BRK_DET_INT_CLR Set this bit to clear UART_BRK_DET_INT interrupt. 7 1 write-only RXFIFO_TOUT_INT_CLR Set this bit to clear UART_RXFIFO_TOUT_INT interrupt. 8 1 write-only SW_XON_INT_CLR Set this bit to clear UART_SW_XON_INT interrupt. 9 1 write-only SW_XOFF_INT_CLR Set this bit to clear UART_SW_XOFF_INT interrupt. 10 1 write-only GLITCH_DET_INT_CLR Set this bit to clear UART_GLITCH_DET_INT interrupt. 11 1 write-only TX_BRK_DONE_INT_CLR Set this bit to clear UART_TX_BRK_DONE_INT interrupt. 12 1 write-only TX_BRK_IDLE_DONE_INT_CLR Set this bit to clear UART_TX_BRK_IDLE_DONE_INT interrupt. 13 1 write-only TX_DONE_INT_CLR Set this bit to clear UART_TX_DONE_INT interrupt. 14 1 write-only RS485_PARITY_ERR_INT_CLR Set this bit to clear UART_RS485_PARITY_ERR_INT interrupt. 15 1 write-only RS485_FRM_ERR_INT_CLR Set this bit to clear UART_RS485_FRM_ERR_INT interrupt. 16 1 write-only RS485_CLASH_INT_CLR Set this bit to clear UART_RS485_CLASH_INT interrupt. 17 1 write-only AT_CMD_CHAR_DET_INT_CLR Set this bit to clear UART_AT_CMD_CHAR_DET_INT interrupt. 18 1 write-only WAKEUP_INT_CLR Set this bit to clear UART_WAKEUP_INT interrupt. 19 1 write-only CLKDIV Clock divider configuration 0x14 0x20 0x000002B6 CLKDIV The integral part of the frequency divisor. 0 20 read-write FRAG The fractional part of the frequency divisor. 20 4 read-write AUTOBAUD Autobaud configuration register 0x18 0x20 0x00001000 EN This is the enable bit for baud rate detection. 0 1 read-write GLITCH_FILT When input pulse width is lower than this value, the pulse is ignored. This register is used in autobaud detection. 8 8 read-write STATUS UART status register 0x1C 0x20 RXFIFO_CNT Stores the number of valid data bytes in RX FIFO. 0 10 read-only DSRN This register represents the level of the internal UART DSR signal. 13 1 read-only CTSN This register represents the level of the internal UART CTS signal. 14 1 read-only RXD This register represents the level of the internal UART RXD signal. 15 1 read-only TXFIFO_CNT Stores the number of data bytes in TX FIFO. 16 10 read-only DTRN This bit represents the level of the internal UART DTR signal. 29 1 read-only RTSN This bit represents the level of the internal UART RTS signal. 30 1 read-only TXD This bit represents the level of the internal UART TXD signal. 31 1 read-only CONF0 Configuration register 0 0x20 0x20 0x1800001C PARITY This register is used to configure the parity check mode. 0: even. 1: odd. 0 1 read-write PARITY_EN Set this bit to enable UART parity check. 1 1 read-write BIT_NUM This register is used to set the length of data. 0: 5 bits. 1: 6 bits. 2: 7 bits. 3: 8 bits. 2 2 read-write STOP_BIT_NUM This register is used to set the length of stop bit. 1: 1 bit. 2: 1.5 bits. 3: 2 bits. 4 2 read-write SW_RTS This register is used to configure the software RTS signal which is used in software flow control. 6 1 read-write SW_DTR This register is used to configure the software DTR signal which is used in software flow control. 7 1 read-write TXD_BRK Set this bit to enable the transmitter to send NULL characters when the process of sending data is done. 8 1 read-write IRDA_DPLX Set this bit to enable IrDA loopback mode. 9 1 read-write IRDA_TX_EN This is the start enable bit for IrDA transmitter. 10 1 read-write IRDA_WCTL 1: The IrDA transmitter's 11th bit is the same as 10th bit. 0: Set IrDA transmitter's 11th bit to 0. 11 1 read-write IRDA_TX_INV Set this bit to invert the level of IrDA transmitter. 12 1 read-write IRDA_RX_INV Set this bit to invert the level of IrDA receiver. 13 1 read-write LOOPBACK Set this bit to enable UART loopback test mode. 14 1 read-write TX_FLOW_EN Set this bit to enable flow control function for the transmitter. 15 1 read-write IRDA_EN Set this bit to enable IrDA protocol. 16 1 read-write RXFIFO_RST Set this bit to reset the UART RX FIFO. 17 1 read-write TXFIFO_RST Set this bit to reset the UART TX FIFO. 18 1 read-write RXD_INV Set this bit to invert the level of UART RXD signal. 19 1 read-write CTS_INV Set this bit to invert the level of UART CTS signal. 20 1 read-write DSR_INV Set this bit to invert the level of UART DSR signal. 21 1 read-write TXD_INV Set this bit to invert the level of UART TXD signal. 22 1 read-write RTS_INV Set this bit to invert the level of UART RTS signal. 23 1 read-write DTR_INV Set this bit to invert the level of UART DTR signal. 24 1 read-write CLK_EN 1: Force clock on for registers. 0: Support clock only when application writes registers. 25 1 read-write ERR_WR_MASK 1: The receiver stops storing data into FIFO when data is wrong. 0: The receiver stores the data even if the received data is wrong. 26 1 read-write TICK_REF_ALWAYS_ON This register is used to select the clock. 1: APB_CLK. 0: REF_TICK. 27 1 read-write MEM_CLK_EN The signal to enable UART RAM clock gating. 1: UART RAM powers on, the data of which can be read and written. 0: UART RAM powers down. 28 1 read-write CONF1 Configuration register 1 0x24 0x20 0x0000C060 RXFIFO_FULL_THRHD An UART_RXFIFO_FULL_INT interrupt is generated when the receiver receives more data than this register’s value. 0 9 read-write TXFIFO_EMPTY_THRHD An UART_TXFIFO_EMPTY_INT interrupt is generated when the number of data bytes in TX FIFO is less than this register's value. 9 9 read-write RX_TOUT_FLOW_DIS Set this bit to stop accumulating idle_cnt when hardware flow control works. 29 1 read-write RX_FLOW_EN This is the flow enable bit for UART receiver. 1: Choose software flow control with configuring sw_rts signal. 0: Disable software flow control. 30 1 read-write RX_TOUT_EN This is the enable bit for UART receiver's timeout function. 31 1 read-write LOWPULSE Autobaud minimum low pulse duration register 0x28 0x20 0x000FFFFF MIN_CNT This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate detection. 0 20 read-only HIGHPULSE Autobaud minimum high pulse duration register 0x2C 0x20 0x000FFFFF MIN_CNT This register stores the value of the maximum duration time for the high level pulse. It is used in baud rate detection. 0 20 read-only RXD_CNT Autobaud edge change count register 0x30 0x20 RXD_EDGE_CNT This register stores the count of RXD edge change. It is used in baud rate detection. As baud rate registers UART_REG_LOWPULSE_MIN_CNT, UART_REG_HIGHPULSE_MIN_CNT, UART_REG_POSEDGE_MIN_CNT, and UART_REG_NEGEDGE_MIN_CNT always record the minimal value, UART_REG_RXD_EDGE_CNT indicates the statistic number of RXD edge to find out the minimal value for these baud rate registers. 0 10 read-only FLOW_CONF Software flow control configuration 0x34 0x20 SW_FLOW_CON_EN Set this bit to enable software flow control. When UART receives flow control characters XON or XOFF, which can be configured by UART_XON_CHAR or UART_XOFF_CHAR respectively, UART_SW_XON_INT or UART_SW_XOFF_INT interrupts can be triggered if enabled. 0 1 read-write XONOFF_DEL Set this bit to remove flow control characters from the received data. 1 1 read-write FORCE_XON Set this bit to force the transmitter to send data. 2 1 read-write FORCE_XOFF Set this bit to stop the transmitter from sending data. 3 1 read-write SEND_XON Set this bit to send an XON character. This bit is cleared by hardware automatically. 4 1 read-write SEND_XOFF Set this bit to send an XOFF character. This bit is cleared by hardware automatically. 5 1 read-write SLEEP_CONF Sleep mode configuration 0x38 0x20 0x000000F0 ACTIVE_THRESHOLD The UART is activated from Light-sleep mode when the input RXD edge changes more times than this register's value. 0 10 read-write SWFC_CONF0 Software flow control character configuration 0x3C 0x20 0x000026E0 XOFF_THRESHOLD When the number of data bytes in RX FIFO is more than this register's value with UART_SW_FLOW_CON_EN set to 1, the transmitter sends an XOFF character. 0 9 read-write XOFF_CHAR This register stores the XOFF flow control character. 9 8 read-write SWFC_CONF1 Software flow-control character configuration 0x40 0x20 0x00002200 XON_THRESHOLD When the number of data bytes in RX FIFO is less than this register's value with UART_SW_FLOW_CON_EN set to 1, the transmitter sends an XON character. 0 9 read-write XON_CHAR This register stores the XON flow control character. 9 8 read-write IDLE_CONF Frame end idle time configuration 0x44 0x20 0x00A40100 RX_IDLE_THRHD A frame end signal is generated when the receiver takes more time to receive one byte data than this register's value, in the unit of bit time (the time it takes to transfer one bit). 0 10 read-write TX_IDLE_NUM This register is used to configure the duration time between transfers, in the unit of bit time (the time it takes to transfer one bit). 10 10 read-write TX_BRK_NUM This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when UART_TXD_BRK is set to 1. 20 8 read-write RS485_CONF RS485 mode configuration 0x48 0x20 RS485_EN Set this bit to choose RS485 mode. 0 1 read-write DL0_EN Set this bit to delay the stop bit by 1 bit. 1 1 read-write DL1_EN Set this bit to delay the stop bit by 1 bit. 2 1 read-write RS485TX_RX_EN Set this bit to enable the receiver could receive data when the transmitter is transmitting data in RS485 mode. 3 1 read-write RS485RXBY_TX_EN 1: enable RS485 transmitter to send data when RS485 receiver line is busy. 0: RS485 transmitter should not send data when its receiver is busy. 4 1 read-write RS485_RX_DLY_NUM This register is used to delay the receiver's internal data signal. 5 1 read-write RS485_TX_DLY_NUM This register is used to delay the transmitter's internal data signal. 6 4 read-write AT_CMD_PRECNT Pre-sequence timing configuration 0x4C 0x20 0x00000901 PRE_IDLE_NUM This register is used to configure the idle duration time before the first AT_CMD is received by the receiver. It will not take the next data received as AT_CMD character when the duration is less than this register's value. 0 16 read-write AT_CMD_POSTCNT Post-sequence timing configuration 0x50 0x20 0x00000901 POST_IDLE_NUM This register is used to configure the duration time between the last AT_CMD and the next data. It will not take the previous data as AT_CMD character when the duration is less than this register's value. 0 16 read-write AT_CMD_GAPTOUT Timeout configuration 0x54 0x20 0x0000000B RX_GAP_TOUT This register is used to configure the duration time between the AT_CMD characters. It will not take the data as continuous AT_CMD characters when the duration time is less than this register's value. 0 16 read-write AT_CMD_CHAR AT escape sequence selection configuration 0x58 0x20 0x0000032B AT_CMD_CHAR This register is used to configure the content of AT_CMD character. 0 8 read-write CHAR_NUM This register is used to configure the number of continuous AT_CMD characters received by the receiver. 8 8 read-write MEM_CONF UART threshold and allocation configuration 0x5C 0x20 0x000A0012 RX_SIZE This register is used to configure the amount of RAM allocated for RX FIFO. The default number is 128 bytes. 1 3 read-write TX_SIZE This register is used to configure the amount of RAM allocated for TX FIFO. The default number is 128 bytes. 4 3 read-write RX_FLOW_THRHD This register is used to configure the maximum amount of data bytes that can be received when hardware flow control works. 7 9 read-write RX_TOUT_THRHD This register is used to configure the threshold time that the receiver takes to receive one byte, in the unit of bit time (the time it takes to transfer one bit). The UART_RXFIFO_TOUT_INT interrupt will be triggered when the receiver takes more time to receive one byte with UART RX_TOUT_EN set to 1. 16 10 read-write MEM_FORCE_PD Set this bit to force power down UART RAM. 26 1 read-write MEM_FORCE_PU Set this bit to force power up UART RAM. 27 1 read-write MEM_TX_STATUS TX FIFO write and read offset address 0x60 0x20 APB_TX_WADDR This register stores the offset address in TX FIFO when software writes TX FIFO via APB. 0 10 read-only TX_RADDR This register stores the offset address in TX FIFO when TX FSM reads data via Tx_FIFO_Ctrl. 11 10 read-only MEM_RX_STATUS RX FIFO write and read offset address 0x64 0x20 APB_RX_RADDR This register stores the offset address in RX_FIFO when software reads data from RX FIFO via APB. 0 10 read-only RX_WADDR This register stores the offset address in RX FIFO when Rx_FIFO_Ctrl writes RX FIFO. 11 10 read-only FSM_STATUS UART transmitter and receiver status 0x68 0x20 ST_URX_OUT This is the status register of the receiver. 0 4 read-only ST_UTX_OUT This is the status register of the transmitter. 4 4 read-only POSPULSE Autobaud high pulse register 0x6C 0x20 0x000FFFFF POSEDGE_MIN_CNT This register stores the minimal input clock count between two positive edges. It is used in baud rate detection. 0 20 read-only NEGPULSE Autobaud low pulse register 0x70 0x20 0x000FFFFF NEGEDGE_MIN_CNT This register stores the minimal input clock count between two negative edges. It is used in baud rate detection. 0 20 read-only DATE UART version control register 0x74 0x20 0x18082800 DATE This is the version control register. 0 32 read-write ID UART ID register 0x78 0x20 0x00000500 ID This register is used to configure the UART_ID. 0 32 read-write UART1 UART (Universal Asynchronous Receiver-Transmitter) Controller 1 0x3F410000 UART1 38 UART2 39 UHCI0 Universal Host Controller Interface 0 UHCI 0x3F414000 0x0 0xBC registers UHCI0 13 UHCI1 14 CONF0 UHCI configuration register 0x0 0x20 0x00370100 IN_RST Set this bit to reset in DMA FSM. 0 1 read-write OUT_RST Set this bit to reset out DMA FSM. 1 1 read-write AHBM_FIFO_RST Set this bit to reset AHB interface cmdFIFO of DMA. 2 1 read-write AHBM_RST Set this bit to reset AHB interface of DMA. 3 1 read-write IN_LOOP_TEST Reserved. 4 1 read-write OUT_LOOP_TEST Reserved. 5 1 read-write OUT_AUTO_WRBACK Set this bit to enable automatic outlink writeback when all the data in TX FIFO has been transmitted. 6 1 read-write OUT_NO_RESTART_CLR Reserved. 7 1 read-write OUT_EOF_MODE This register is used to specify the generation mode of UHCI_OUT_EOF_INT interrupt. 1: When DMA has popped all data from FIFO. 0: When AHB has pushed all data to FIFO. 8 1 read-write UART0_CE Set this bit to link up UHCI and UART0. 9 1 read-write UART1_CE Set this bit to link up UHCI and UART1. 10 1 read-write OUTDSCR_BURST_EN This register is used to specify DMA transmit descriptor transfer mode. 1: burst mode. 0: byte mode. 12 1 read-write INDSCR_BURST_EN This register is used to specify DMA receive descriptor transfer mode. 1: burst mode. 0: byte mode. 13 1 read-write MEM_TRANS_EN 1: UHCI transmitted data would be write back into DMA INFIFO. 15 1 read-write SEPER_EN Set this bit to separate the data frame using a special character. 16 1 read-write HEAD_EN Set this bit to encode the data packet with a formatting header. 17 1 read-write CRC_REC_EN Set this bit to enable UHCI to receive the 16 bit CRC. 18 1 read-write UART_IDLE_EOF_EN If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state. 19 1 read-write LEN_EOF_EN If this bit is set to 1, UHCI decoder stops receiving payload data when the number of received data bytes has reached the specified value. The value is payload length indicated by UCHI packet header when UHCI_HEAD_EN is 1 or the value is a configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder stops receiving payload data upon receiving 0xC0. 20 1 read-write ENCODE_CRC_EN Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to the end of the payload. 21 1 read-write CLK_EN 1: Force clock on for registers. 0: Support clock only when application writes registers. 22 1 read-write UART_RX_BRK_EOF_EN If this bit is set to 1, UHCI stops receiving payload data when a NULL frame is received by UART. 23 1 read-write INT_RAW Raw interrupt status 0x4 0x20 RX_START_INT_RAW This is the interrupt raw bit for UHCI_RX_START_INT interrupt. The interrupt is triggered when a separator has been sent. 0 1 read-only TX_START_INT_RAW This is the interrupt raw bit for UHCI_TX_START_INT interrupt. The interrupt is triggered when DMA detects a separator. 1 1 read-only RX_HUNG_INT_RAW This is the interrupt raw bit for UHCI_RX_HUNG_INT interrupt. The interrupt is triggered when DMA takes more time to receive data than the configure value. 2 1 read-only TX_HUNG_INT_RAW This is the interrupt raw bit for UHCI_TX_HUNG_INT interrupt. The interrupt is triggered when DMA takes more time to read data from RAM than the configured value. 3 1 read-only IN_DONE_INT_RAW This is the interrupt raw bit for UHCI_IN_DONE_INT interrupt. The interrupt is triggered when an receive descriptor is completed. 4 1 read-only IN_SUC_EOF_INT_RAW This is the interrupt raw bit for UHCI_IN_SUC_EOF_INT interrupt. The interrupt is triggered when a data packet has been received successfully. 5 1 read-only IN_ERR_EOF_INT_RAW This is the interrupt raw bit for UHCI_IN_ERR_EOF_INT interrupt. The interrupt is triggered when there are some errors in EOF in the receive descriptor. 6 1 read-only OUT_DONE_INT_RAW This is the interrupt raw bit for UHCI_OUT_DONE_INT interrupt. The interrupt is triggered when an transmit descriptor is completed. 7 1 read-only OUT_EOF_INT_RAW This is the interrupt raw bit for UHCI_OUT_EOF_INT interrupt. The interrupt is triggered when the current descriptor's EOF bit is 1. 8 1 read-only IN_DSCR_ERR_INT_RAW This is the interrupt raw bit for UHCI_IN_DSCR_ERR_INT interrupt. The interrupt is triggered when there are some errors in the receive descriptor. 9 1 read-only OUT_DSCR_ERR_INT_RAW This is the interrupt raw bit for UHCI_OUT_DSCR_ERR_INT interrupt. The interrupt is triggered when there are some errors in the transmit descriptor. 10 1 read-only IN_DSCR_EMPTY_INT_RAW This is the interrupt raw bit for UHCI_IN_DSCR_EMPTY_INT interrupt. The interrupt is triggered when there are not enough inlinks for DMA. 11 1 read-only OUTLINK_EOF_ERR_INT_RAW This is the interrupt raw bit for UHCI_OUTLINK_EOF_ERR_INT interrupt. The interrupt is triggered when there are some errors in EOF in the transmit descriptor. 12 1 read-only OUT_TOTAL_EOF_INT_RAW This is the interrupt raw bit for UHCI_OUT_TOTAL_EOF_INT interrupt. The interrupt is triggered when all data in the last buffer address has been sent out. 13 1 read-only SEND_S_REG_Q_INT_RAW This is the interrupt raw bit for UHCI_SEND_S_REG_Q_INT interrupt. The interrupt is triggered when DMA has sent out a short packet using single_send mode. 14 1 read-only SEND_A_REG_Q_INT_RAW This is the interrupt raw bit for UHCI_SEND_A_REG_Q_INT interrupt. The interrupt is triggered when DMA has sent out a short packet using always_send mode. 15 1 read-only DMA_INFIFO_FULL_WM_INT_RAW This is the interrupt raw bit for UHCI_DMA_INFIFO_FULL_WM_INT interrupt. The interrupt is triggered when the number of data bytes in DMA RX FIFO has reached the configured threshold value. 16 1 read-only INT_ST Masked interrupt status 0x8 0x20 RX_START_INT_ST This is the masked interrupt bit for UHCI_RX_START_INT interrupt when UHCI_RX_START_INT_ENA is set to 1. 0 1 read-only TX_START_INT_ST This is the masked interrupt bit for UHCI_TX_START_INT interrupt when UHCI_TX_START_INT_ENA is set to 1. 1 1 read-only RX_HUNG_INT_ST This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when UHCI_RX_HUNG_INT_ENA is set to 1. 2 1 read-only TX_HUNG_INT_ST This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when UHCI_TX_HUNG_INT_ENA is set to 1. 3 1 read-only IN_DONE_INT_ST This is the masked interrupt bit for UHCI_IN_DONE_INT interrupt when UHCI_IN_DONE_INT_ENA is set to 1. 4 1 read-only IN_SUC_EOF_INT_ST This is the masked interrupt bit for UHCI_IN_SUC_EOF_INT interrupt when UHCI_IN_SUC_EOF_INT_ENA is set to 1. 5 1 read-only IN_ERR_EOF_INT_ST This is the masked interrupt bit for UHCI_IN_ERR_EOF_INT interrupt when UHCI_IN_ERR_EOF_INT_ENA is set to 1. 6 1 read-only OUT_DONE_INT_ST This is the masked interrupt bit for UHCI_OUT_DONE_INT interrupt when UHCI_OUT_DONE_INT_ENA is set to 1. 7 1 read-only OUT_EOF_INT_ST This is the masked interrupt bit for UHCI_OUT_EOF_INT interrupt when UHCI_OUT_EOF_INT_ENA is set to 1. 8 1 read-only IN_DSCR_ERR_INT_ST This is the masked interrupt bit for UHCI_IN_DSCR_ERR_INT interrupt when UHCI_IN_DSCR_ERR_INT is set to 1. 9 1 read-only OUT_DSCR_ERR_INT_ST This is the masked interrupt bit for UHCI_OUT_DSCR_ERR_INT interrupt when UHCI_OUT_DSCR_ERR_INT_ENA is set to 1. 10 1 read-only IN_DSCR_EMPTY_INT_ST This is the masked interrupt bit for UHCI_IN_DSCR_EMPTY_INT interrupt when UHCI_IN_DSCR_EMPTY_INT_ENA is set to 1. 11 1 read-only OUTLINK_EOF_ERR_INT_ST This is the masked interrupt bit for UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA is set to 1. 12 1 read-only OUT_TOTAL_EOF_INT_ST This is the masked interrupt bit for UHCI_OUT_TOTAL_EOF_INT interrupt when UHCI_OUT_TOTAL_EOF_INT_ENA is set to 1. 13 1 read-only SEND_S_REG_Q_INT_ST This is the masked interrupt bit for UHCI_SEND_S_REG_Q_INT interrupt when UHCI_SEND_S_REG_Q_INT_ENA is set to 1. 14 1 read-only SEND_A_REG_Q_INT_ST This is the masked interrupt bit for UHCI_SEND_A_REG_Q_INT interrupt when UHCI_SEND_A_REG_Q_INT_ENA is set to 1. 15 1 read-only DMA_INFIFO_FULL_WM_INT_ST This is the masked interrupt bit for UHCI_DMA_INFIFO_FULL_WM_INT INTERRUPT when UHCI_DMA_INFIFO_FULL_WM_INT_ENA is set to 1. 16 1 read-only INT_ENA Interrupt enable bits 0xC 0x20 RX_START_INT_ENA This is the interrupt enable bit for UHCI_RX_START_INT interrupt. 0 1 read-write TX_START_INT_ENA This is the interrupt enable bit for UHCI_TX_START_INT interrupt. 1 1 read-write RX_HUNG_INT_ENA This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt. 2 1 read-write TX_HUNG_INT_ENA This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt. 3 1 read-write IN_DONE_INT_ENA This is the interrupt enable bit for UHCI_IN_DONE_INT interrupt. 4 1 read-write IN_SUC_EOF_INT_ENA This is the interrupt enable bit for UHCI_IN_SUC_EOF_INT interrupt. 5 1 read-write IN_ERR_EOF_INT_ENA This is the interrupt enable bit for UHCI_IN_ERR_EOF_INT interrupt. 6 1 read-write OUT_DONE_INT_ENA This is the interrupt enable bit for UHCI_OUT_DONE_INT interrupt. 7 1 read-write OUT_EOF_INT_ENA This is the interrupt enable bit for UHCI_OUT_EOF_INT interrupt. 8 1 read-write IN_DSCR_ERR_INT_ENA This is the interrupt enable bit for UHCI_IN_DSCR_ERR_INT interrupt. 9 1 read-write OUT_DSCR_ERR_INT_ENA This is the interrupt enable bit for UHCI_OUT_DSCR_ERR_INT interrupt. 10 1 read-write IN_DSCR_EMPTY_INT_ENA This is the interrupt enable bit for UHCI_IN_DSCR_EMPTY_INT interrupt. 11 1 read-write OUTLINK_EOF_ERR_INT_ENA This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt. 12 1 read-write OUT_TOTAL_EOF_INT_ENA This is the interrupt enable bit for UHCI_OUT_TOTAL_EOF_INT interrupt. 13 1 read-write SEND_S_REG_Q_INT_ENA This is the interrupt enable bit for UHCI_SEND_S_REG_Q_INT interrupt. 14 1 read-write SEND_A_REG_Q_INT_ENA This is the interrupt enable bit for UHCI_SEND_A_REG_Q_INT interrupt. 15 1 read-write DMA_INFIFO_FULL_WM_INT_ENA This is the interrupt enable bit for UHCI_DMA_INFIFO_FULL_WM_INT interrupt. 16 1 read-write INT_CLR Interrupt clear bits 0x10 0x20 RX_START_INT_CLR Set this bit to clear UHCI_RX_START_INT interrupt. 0 1 write-only TX_START_INT_CLR Set this bit to clear UHCI_TX_START_INT interrupt. 1 1 write-only RX_HUNG_INT_CLR Set this bit to clear UHCI_RX_HUNG_INT interrupt. 2 1 write-only TX_HUNG_INT_CLR Set this bit to clear UHCI_TX_HUNG_INT interrupt. 3 1 write-only IN_DONE_INT_CLR Set this bit to clear UHCI_IN_DONE_INT interrupt. 4 1 write-only IN_SUC_EOF_INT_CLR Set this bit to clear UHCI_IN_SUC_EOF_INT interrupt. 5 1 write-only IN_ERR_EOF_INT_CLR Set this bit to clear UHCI_IN_ERR_EOF_INT interrupt. 6 1 write-only OUT_DONE_INT_CLR Set this bit to clear UHCI_OUT_DONE_INT interrupt. 7 1 write-only OUT_EOF_INT_CLR Set this bit to clear UHCI_OUT_EOF_INT interrupt. 8 1 write-only IN_DSCR_ERR_INT_CLR Set this bit to clear UHCI_IN_DSCR_ERR_INT interrupt. 9 1 write-only OUT_DSCR_ERR_INT_CLR Set this bit to clear UHCI_OUT_DSCR_ERR_INT interrupt. 10 1 write-only IN_DSCR_EMPTY_INT_CLR Set this bit to clear UHCI_IN_DSCR_EMPTY_INT interrupt. 11 1 write-only OUTLINK_EOF_ERR_INT_CLR Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt. 12 1 write-only OUT_TOTAL_EOF_INT_CLR Set this bit to clear UHCI_OUT_TOTAL_EOF_INT interrupt. 13 1 write-only SEND_S_REG_Q_INT_CLR Set this bit to clear UHCI_SEND_S_REG_Q_INT interrupt. 14 1 write-only SEND_A_REG_Q_INT_CLR Set this bit to clear UHCI_SEND_A_REG_Q_INT interrupt. 15 1 write-only DMA_INFIFO_FULL_WM_INT_CLR Set this bit to clear UHCI_DMA_INFIFO_FULL_WM_INT interrupt. 16 1 write-only DMA_OUT_STATUS DMA data-output status register 0x14 0x20 0x00000002 OUT_FULL 1: DMA TX FIFO is full. 0 1 read-only OUT_EMPTY 1: DMA TX FIFO is empty. 1 1 read-only DMA_OUT_PUSH Push control register of TX FIFO 0x18 0x20 OUTFIFO_WDATA This is the data that need to be pushed into TX FIFO. 0 9 read-write OUTFIFO_PUSH Set this bit to push data into TX FIFO. 16 1 read-write DMA_IN_STATUS UHCI data-input status register 0x1C 0x20 0x00000002 IN_FULL Data-input FIFO full signal. 0 1 read-only IN_EMPTY Data-input FIFO empty signal. 1 1 read-only RX_ERR_CAUSE This register indicates the error type when DMA has received a packet with error. 3'b001: Checksum error in the HCI packet; 3'b010: Sequence number error in the HCI packet; 3'b011: CRC bit error in the HCI packet; 3'b100: 0xC0 is found but the received HCI packet is not end; 3'b101: 0xC0 is not found when the HCI packet has been received; 3'b110: CRC check error. 4 3 read-only DMA_IN_POP Pop control register of RX FIFO 0x20 0x20 INFIFO_RDATA This register stores the data popping from RX FIFO. 0 12 read-only INFIFO_POP Set this bit to pop data from RX FIFO. 16 1 read-write DMA_OUT_LINK Link descriptor address and control 0x24 0x20 OUTLINK_ADDR This register is used to specify the least significant 20 bits of the first transmit descriptor's address. 0 20 read-write OUTLINK_STOP Set this bit to stop dealing with the transmit descriptor. 28 1 read-write OUTLINK_START Set this bit to start a new transmit descriptor. 29 1 read-write OUTLINK_RESTART Set this bit to restart the transmit descriptor from the last address. 30 1 read-write OUTLINK_PARK 1: the transmit descriptor's FSM is in idle state. 0: the transmit descriptor's FSM is working. 31 1 read-only DMA_IN_LINK Link descriptor address and control 0x28 0x20 0x00100000 INLINK_ADDR This register is used to specify the least significant 20 bits of the first receive descriptor's address. 0 20 read-write INLINK_AUTO_RET This is the enable bit to return to current receive descriptor's address, when there are some errors in current packet. 20 1 read-write INLINK_STOP Set this bit to stop dealing with the receive descriptors. 28 1 read-write INLINK_START Set this bit to start dealing with the receive descriptors. 29 1 read-write INLINK_RESTART Set this bit to restart new receive descriptors. 30 1 read-write INLINK_PARK 1: the receive descriptor's FSM is in idle state. 0: the receive descriptor's FSM is working. 31 1 read-only CONF1 UHCI configuration register 0x2C 0x20 0x00000033 CHECK_SUM_EN This is the enable bit to check header checksum when UHCI receives a data packet. 0 1 read-write CHECK_SEQ_EN This is the enable bit to check sequence number when UHCI receives a data packet. 1 1 read-write CRC_DISABLE Set this bit to support CRC calculation. Data Integrity check present bit in UHCI packet frame should be 1. 2 1 read-write SAVE_HEAD Set this bit to save the packet header when UHCI receives a data packet. 3 1 read-write TX_CHECK_SUM_RE Set this bit to encode the data packet with a checksum. 4 1 read-write TX_ACK_NUM_RE Set this bit to encode the data packet with an acknowledgement when a reliable packet is to be transmit. 5 1 read-write CHECK_OWNER 1: Check the link list descriptor when link list owner is DMA controller; 0: Always check link list descriptor. 6 1 read-write WAIT_SW_START The UHCI encoder will jump to ST_SW_WAIT status if this register is set to 1. 7 1 read-write SW_START If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1. 8 1 read-write DMA_INFIFO_FULL_THRS This field is used to generate the UHCI_DMA_INFIFO_FULL_WM_INT interrupt when the counter value of DMA RX FIFO exceeds the value of the register. 9 12 read-write STATE0 UHCI decoder status register 0x30 0x20 INLINK_DSCR_ADDR This register stores the current receive descriptor's address. 0 18 read-only IN_DSCR_STATE Reserved. 18 2 read-only IN_STATE Reserved. 20 3 read-only INFIFO_CNT_DEBUG This register stores the number of data bytes in RX FIFO. 23 5 read-only DECODE_STATE UHCI decoder status. 28 3 read-only STATE1 UHCI encoder status register 0x34 0x20 OUTLINK_DSCR_ADDR This register stores the current transmit descriptor's address. 0 18 read-only OUT_DSCR_STATE Reserved. 18 2 read-only OUT_STATE Reserved. 20 3 read-only OUTFIFO_CNT This register stores the number of data bytes in TX FIFO. 23 5 read-only ENCODE_STATE UHCI encoder status. 28 3 read-only DMA_OUT_EOF_DES_ADDR Outlink descriptor address when EOF occurs 0x38 0x20 OUT_EOF_DES_ADDR This register stores the address of the transmit descriptor when the EOF bit in this descriptor is 1. 0 32 read-only DMA_IN_SUC_EOF_DES_ADDR Inlink descriptor address when EOF occurs 0x3C 0x20 IN_SUC_EOF_DES_ADDR This register stores the address of the receive descriptor when received successful EOF. 0 32 read-only DMA_IN_ERR_EOF_DES_ADDR Inlink descriptor address when errors occur 0x40 0x20 IN_ERR_EOF_DES_ADDR This register stores the address of the receive descriptor when there are some errors in this descriptor. 0 32 read-only DMA_OUT_EOF_BFR_DES_ADDR Outlink descriptor address before the last transmit descriptor 0x44 0x20 OUT_EOF_BFR_DES_ADDR This register stores the address of the transmit descriptor before the last transmit descriptor. 0 32 read-only AHB_TEST AHB test register 0x48 0x20 AHB_TESTMODE Reserved. 0 3 read-write AHB_TESTADDR Reserved. 4 2 read-write DMA_IN_DSCR The third word of the next receive descriptor 0x4C 0x20 INLINK_DSCR This register stores the third word of the next receive descriptor. 0 32 read-only DMA_IN_DSCR_BF0 The third word of current receive descriptor 0x50 0x20 INLINK_DSCR_BF0 This register stores the third word of the current receive descriptor. 0 32 read-only DMA_OUT_DSCR The third word of the next transmit descriptor 0x58 0x20 OUTLINK_DSCR This register stores the third word of the next transmit descriptor. 0 32 read-only DMA_OUT_DSCR_BF0 The third word of current transmit descriptor 0x5C 0x20 OUTLINK_DSCR_BF0 This register stores the third word of the current transmit descriptor. 0 32 read-only ESCAPE_CONF Escape character configuration 0x64 0x20 0x00000033 TX_C0_ESC_EN Set this bit to decode character 0xC0 when DMA receives data. 0 1 read-write TX_DB_ESC_EN Set this bit to decode character 0xDB when DMA receives data. 1 1 read-write TX_11_ESC_EN Set this bit to decode flow control character 0x11 when DMA receives data. 2 1 read-write TX_13_ESC_EN Set this bit to decode flow control character 0x13 when DMA receives data. 3 1 read-write RX_C0_ESC_EN Set this bit to replace 0xC0 by special characters when DMA sends data. 4 1 read-write RX_DB_ESC_EN Set this bit to replace 0xDB by special characters when DMA sends data. 5 1 read-write RX_11_ESC_EN Set this bit to replace flow control character 0x11 by special characters when DMA sends data. 6 1 read-write RX_13_ESC_EN Set this bit to replace flow control character 0x13 by special characters when DMA sends data. 7 1 read-write HUNG_CONF Timeout configuration 0x68 0x20 0x00810810 TXFIFO_TIMEOUT This register stores the timeout value. UHCI produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data. 0 8 read-write TXFIFO_TIMEOUT_SHIFT This register is used to configure the maximum tick count. 8 3 read-write TXFIFO_TIMEOUT_ENA This is the enable bit for TX FIFO receive timeout. 11 1 read-write RXFIFO_TIMEOUT This register stores the timeout value. UHCI produce the UHCI_RX_HUNG_INT interrupt when DMA takes more time to read data from RAM. 12 8 read-write RXFIFO_TIMEOUT_SHIFT This register is used to configure the maximum tick count. 20 3 read-write RXFIFO_TIMEOUT_ENA This is the enable bit for DMA send timeout. 23 1 read-write RX_HEAD UHCI packet header register 0x70 0x20 RX_HEAD This register stores the header of the current received packet. 0 32 read-only QUICK_SENT UHCI quick_sent configuration register 0x74 0x20 SINGLE_SEND_NUM This register is used to specify the single_send mode. 0 3 read-write SINGLE_SEND_EN Set this bit to enable single_send mode to send short packets. 3 1 read-write ALWAYS_SEND_NUM This register is used to specify the always_send mode. 4 3 read-write ALWAYS_SEND_EN Set this bit to enable always_send mode to send short packets. 7 1 read-write Q0_WORD0 Q0_WORD0 quick_sent register 0x78 0x20 SEND_Q0_WORD0 This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 32 read-write Q0_WORD1 Q0_WORD1 quick_sent register 0x7C 0x20 SEND_Q0_WORD1 This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 32 read-write Q1_WORD0 Q1_WORD0 quick_sent register 0x80 0x20 SEND_Q1_WORD0 This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 32 read-write Q1_WORD1 Q1_WORD1 quick_sent register 0x84 0x20 SEND_Q1_WORD1 This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 32 read-write Q2_WORD0 Q2_WORD0 quick_sent register 0x88 0x20 SEND_Q2_WORD0 This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 32 read-write Q2_WORD1 Q2_WORD1 quick_sent register 0x8C 0x20 SEND_Q2_WORD1 This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 32 read-write Q3_WORD0 Q3_WORD0 quick_sent register 0x90 0x20 SEND_Q3_WORD0 This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 32 read-write Q3_WORD1 Q3_WORD1 quick_sent register 0x94 0x20 SEND_Q3_WORD1 This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 32 read-write Q4_WORD0 Q4_WORD0 quick_sent register 0x98 0x20 SEND_Q4_WORD0 This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 32 read-write Q4_WORD1 Q4_WORD1 quick_sent register 0x9C 0x20 SEND_Q4_WORD1 This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 32 read-write Q5_WORD0 Q5_WORD0 quick_sent register 0xA0 0x20 SEND_Q5_WORD0 This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 32 read-write Q5_WORD1 Q5_WORD1 quick_sent register 0xA4 0x20 SEND_Q5_WORD1 This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 32 read-write Q6_WORD0 Q6_WORD0 quick_sent register 0xA8 0x20 SEND_Q6_WORD0 This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 32 read-write Q6_WORD1 Q6_WORD1 quick_sent register 0xAC 0x20 SEND_Q6_WORD1 This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. 0 32 read-write ESC_CONF0 Escape sequence configuration register 0 0xB0 0x20 0x00DCDBC0 SEPER_CHAR This register is used to define separators to encode data packets. The default value is 0xC0. 0 8 read-write SEPER_ESC_CHAR0 This register is used to define the first character of SLIP escape sequence. The default value is 0xDB. 8 8 read-write SEPER_ESC_CHAR1 This register is used to define the second character of SLIP escape sequence. The default value is 0xDC. 16 8 read-write ESC_CONF1 Escape sequence configuration register 1 0xB4 0x20 0x00DDDBDB ESC_SEQ0 This register is used to define a character that need to be encoded. The default value is 0xDB that used as the first character of SLIP escape sequence. 0 8 read-write ESC_SEQ0_CHAR0 This register is used to define the first character of SLIP escape sequence. The default value is 0xDB. 8 8 read-write ESC_SEQ0_CHAR1 This register is used to define the second character of SLIP escape sequence. The default value is 0xDD. 16 8 read-write ESC_CONF2 Escape sequence configuration register 2 0xB8 0x20 0x00DEDB11 ESC_SEQ1 This register is used to define a character that need to be encoded. The default value is 0x11 that used as a flow control character. 0 8 read-write ESC_SEQ1_CHAR0 This register is used to define the first character of SLIP escape sequence. The default value is 0xDB. 8 8 read-write ESC_SEQ1_CHAR1 This register is used to define the second character of SLIP escape sequence. The default value is 0xDE. 16 8 read-write ESC_CONF3 Escape sequence configuration register 3 0xBC 0x20 0x00DFDB13 ESC_SEQ2 This register is used to define a character that need to be decoded. The default value is 0x13 that used as a flow control character. 0 8 read-write ESC_SEQ2_CHAR0 This register is used to define the first character of SLIP escape sequence. The default value is 0xDB. 8 8 read-write ESC_SEQ2_CHAR1 This register is used to define the second character of SLIP escape sequence. The default value is 0xDF. 16 8 read-write PKT_THRES Configure register for packet length 0xC0 0x20 0x00000080 PKT_THRS This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0. 0 13 read-write DATE UHCI version control register 0xFC 0x20 0x18073001 DATE This is the version control register. 0 32 read-write USB0 USB OTG (On-The-Go) USB 0x60080000 0x0 0x2A0 registers USB 48 GOTGCTL 0x0 0x20 SESREQSCS 0 1 read-only SESREQ 1 1 read-write VBVALIDOVEN 2 1 read-write VBVALIDOVVAL 3 1 read-write AVALIDOVEN 4 1 read-write AVALIDOVVAL 5 1 read-write BVALIDOVEN 6 1 read-write BVALIDOVVAL 7 1 read-write HSTNEGSCS 8 1 read-only HNPREQ 9 1 read-write HSTSETHNPEN 10 1 read-write DEVHNPEN 11 1 read-write EHEN 12 1 read-write DBNCEFLTRBYPASS 15 1 read-write CONIDSTS 16 1 read-only DBNCTIME 17 1 read-only ASESVLD 18 1 read-only BSESVLD 19 1 read-only OTGVER 20 1 read-write CURMOD 21 1 read-only GOTGINT 0x4 0x20 SESENDDET 2 1 read-write SESREQSUCSTSCHNG 8 1 read-write HSTNEGSUCSTSCHNG 9 1 read-write HSTNEGDET 17 1 read-write ADEVTOUTCHG 18 1 read-write DBNCEDONE 19 1 read-write GAHBCFG 0x8 0x20 GLBLLNTRMSK 0 1 read-write HBSTLEN 1 4 read-write DMAEN 5 1 read-write NPTXFEMPLVL 7 1 read-write PTXFEMPLVL 8 1 read-write REMMEMSUPP 21 1 read-write NOTIALLDMAWRIT 22 1 read-write AHBSINGLE 23 1 read-write INVDESCENDIANESS 24 1 read-write GUSBCFG 0xC 0x20 0x00001440 TOUTCAL 0 3 read-write PHYIF 3 1 read-write ULPI_UTMI_SEL 4 1 read-only FSINTF 5 1 read-write PHYSEL 6 1 read-only SRPCAP 8 1 read-write HNPCAP 9 1 read-write USBTRDTIM 10 4 read-write TERMSELDLPULSE 22 1 read-write TXENDDELAY 28 1 read-write FORCEHSTMODE 29 1 read-write FORCEDEVMODE 30 1 read-write CORRUPTTXPKT 31 1 read-write GRSTCTL 0x10 0x20 CSFTRST 0 1 read-write PIUFSSFTRST 1 1 read-write FRMCNTRRST 2 1 read-write RXFFLSH 4 1 read-write TXFFLSH 5 1 read-write TXFNUM 6 5 read-write DMAREQ 30 1 read-only AHBIDLE 31 1 read-only GINTSTS 0x14 0x20 CURMOD_INT 0 1 read-only MODEMIS 1 1 read-write OTGINT 2 1 read-only SOF 3 1 read-write RXFLVI 4 1 read-only NPTXFEMP 5 1 read-only GINNAKEFF 6 1 read-only GOUTNAKEFF 7 1 read-only ERLYSUSP 10 1 read-write USBSUSP 11 1 read-write USBRST 12 1 read-write ENUMDONE 13 1 read-write ISOOUTDROP 14 1 read-write EOPF 15 1 read-write EPMIS 17 1 read-write IEPINT 18 1 read-only OEPINT 19 1 read-only INCOMPISOIN 20 1 read-write INCOMPIP 21 1 read-write FETSUSP 22 1 read-write RESETDET 23 1 read-write PRTLNT 24 1 read-only HCHLNT 25 1 read-only PTXFEMP 26 1 read-only CONIDSTSCHNG 28 1 read-write DISCONNINT 29 1 read-write SESSREQINT 30 1 read-write WKUPINT 31 1 read-write GINTMSK 0x18 0x20 MODEMISMSK 1 1 read-write OTGINTMSK 2 1 read-write SOFMSK 3 1 read-write RXFLVIMSK 4 1 read-write NPTXFEMPMSK 5 1 read-write GINNAKEFFMSK 6 1 read-write GOUTNACKEFFMSK 7 1 read-write ERLYSUSPMSK 10 1 read-write USBSUSPMSK 11 1 read-write USBRSTMSK 12 1 read-write ENUMDONEMSK 13 1 read-write ISOOUTDROPMSK 14 1 read-write EOPFMSK 15 1 read-write EPMISMSK 17 1 read-write IEPINTMSK 18 1 read-write OEPINTMSK 19 1 read-write INCOMPISOINMSK 20 1 read-write INCOMPIPMSK 21 1 read-write FETSUSPMSK 22 1 read-write RESETDETMSK 23 1 read-write PRTLNTMSK 24 1 read-write HCHINTMSK 25 1 read-write PTXFEMPMSK 26 1 read-write CONIDSTSCHNGMSK 28 1 read-write DISCONNINTMSK 29 1 read-write SESSREQINTMSK 30 1 read-write WKUPINTMSK 31 1 read-write GRXSTSR 0x1C 0x20 G_CHNUM 0 4 read-only G_BCNT 4 11 read-only G_DPID 15 2 read-only G_PKTSTS 17 4 read-only G_FN 21 4 read-only GRXSTSP 0x20 0x20 CHNUM 0 4 read-only BCNT 4 11 read-only DPID 15 2 read-only PKTSTS 17 4 read-only FN 21 4 read-only GRXFSIZ 0x24 0x20 0x00000100 RXFDEP 0 16 read-write GNPTXFSIZ 0x28 0x20 0x01000100 NPTXFSTADDR 0 16 read-write NPTXFDEP 16 16 read-write GNPTXSTS 0x2C 0x20 0x00040100 NPTXFSPCAVAIL 0 16 read-only NPTXQSPCAVAIL 16 4 read-only NPTXQTOP 24 7 read-only GSNPSID 0x40 0x20 0x4F54400A SYNOPSYSID 0 32 read-only GHWCFG1 0x44 0x20 EPDIR 0 32 read-only GHWCFG2 0x48 0x20 0x224DD930 OTGMODE 0 3 read-only OTGARCH 3 2 read-only SINGPNT 5 1 read-only HSPHYTYPE 6 2 read-only FSPHYTYPE 8 2 read-only NUMDEVEPS 10 4 read-only NUMHSTCHNL 14 4 read-only PERIOSUPPORT 18 1 read-only DYNFIFOSIZING 19 1 read-only MULTIPROCINTRPT 20 1 read-only NPTXQDEPTH 22 2 read-only PTXQDEPTH 24 2 read-only TKNQDEPTH 26 5 read-only OTG_ENABLE_IC_USB 31 1 read-only GHWCFG3 0x4C 0x20 0x010004B5 XFERSIZEWIDTH 0 4 read-only PKTSIZEWIDTH 4 3 read-only OTGEN 7 1 read-only I2CINTSEL 8 1 read-only VNDCTLSUPT 9 1 read-only OPTFEATURE 10 1 read-only RSTTYPE 11 1 read-only ADPSUPPORT 12 1 read-only HSICMODE 13 1 read-only BCSUPPORT 14 1 read-only LPMMODE 15 1 read-only DFIFODEPTH 16 16 read-only GHWCFG4 0x50 0x20 0xD3F0A030 G_NUMDEVPERIOEPS 0 4 read-only G_PARTIALPWRDN 4 1 read-only G_AHBFREQ 5 1 read-only G_HIBERNATION 6 1 read-only G_EXTENDEDHIBERNATION 7 1 read-only G_ACGSUPT 12 1 read-only G_ENHANCEDLPMSUPT 13 1 read-only G_PHYDATAWIDTH 14 2 read-only G_NUMCTLEPS 16 4 read-only G_IDDQFLTR 20 1 read-only G_VBUSVALIDFLTR 21 1 read-only G_AVALIDFLTR 22 1 read-only G_BVALIDFLTR 23 1 read-only G_SESSENDFLTR 24 1 read-only G_DEDFIFOMODE 25 1 read-only G_INEPS 26 4 read-only G_DESCDMAENABLED 30 1 read-only G_DESCDMA 31 1 read-only GDFIFOCFG 0x5C 0x20 GDFIFOCFG 0 16 read-write EPINFOBASEADDR 16 16 read-write HPTXFSIZ 0x100 0x20 0x10000200 PTXFSTADDR 0 16 read-write PTXFSIZE 16 16 read-write DIEPTXF1 0x104 0x20 0x10000200 INEP1TXFSTADDR 0 16 read-write INEP1TXFDEP 16 16 read-write DIEPTXF2 0x108 0x20 0x10000200 INEP2TXFSTADDR 0 16 read-write INEP2TXFDEP 16 16 read-write DIEPTXF3 0x10C 0x20 0x10000200 INEP3TXFSTADDR 0 16 read-write INEP3TXFDEP 16 16 read-write DIEPTXF4 0x110 0x20 0x10000200 INEP4TXFSTADDR 0 16 read-write INEP4TXFDEP 16 16 read-write HCFG 0x400 0x20 H_FSLSPCLKSEL 0 2 read-write H_FSLSSUPP 2 1 read-write H_ENA32KHZS 7 1 read-write H_DESCDMA 23 1 read-write H_FRLISTEN 24 2 read-write H_PERSCHEDENA 26 1 read-write H_MODECHTIMEN 31 1 read-write HFIR 0x404 0x20 0x000017D7 FRINT 0 16 read-write HFIRRLDCTRL 16 1 read-write HFNUM 0x408 0x20 0x00003FFF FRNUM 0 14 read-only FRREM 16 16 read-only HPTXSTS 0x410 0x20 0x00080100 PTXFSPCAVAIL 0 16 read-only PTXQSPCAVAIL 16 5 read-only PTXQTOP 24 8 read-only HAINT 0x414 0x20 HAINT 0 8 read-only HAINTMSK 0x418 0x20 HAINTMSK 0 8 read-write HFLBADDR 0x41C 0x20 HFLBADDR 0 32 read-write HPRT 0x440 0x20 PRTCONNSTS 0 1 read-only PRTCONNDET 1 1 read-write PRTENA 2 1 read-write PRTENCHNG 3 1 read-write PRTOVRCURRACT 4 1 read-only PRTOVRCURRCHNG 5 1 read-write PRTRES 6 1 read-write PRTSUSP 7 1 read-write PRTRST 8 1 read-write PRTLNSTS 10 2 read-only PRTPWR 12 1 read-write PRTTSTCTL 13 4 read-write PRTSPD 17 2 read-only HCCHAR0 0x500 0x20 H_MPS0 0 11 read-write H_EPNUM0 11 4 read-write H_EPDIR0 15 1 read-write H_LSPDDEV0 17 1 read-write H_EPTYPE0 18 2 read-write H_EC0 21 1 read-write H_DEVADDR0 22 7 read-write H_ODDFRM0 29 1 read-write H_CHDIS0 30 1 read-write H_CHENA0 31 1 read-write HCINT0 0x508 0x20 H_XFERCOMPL0 0 1 read-write H_CHHLTD0 1 1 read-write H_AHBERR0 2 1 read-write H_STALL0 3 1 read-write H_NACK0 4 1 read-write H_ACK0 5 1 read-write H_NYET0 6 1 read-write H_XACTERR0 7 1 read-write H_BBLERR0 8 1 read-write H_FRMOVRUN0 9 1 read-write H_DATATGLERR0 10 1 read-write H_BNAINTR0 11 1 read-write H_XCS_XACT_ERR0 12 1 read-write H_DESC_LST_ROLLINTR0 13 1 read-write HCINTMSK0 0x50C 0x20 H_XFERCOMPLMSK0 0 1 read-write H_CHHLTDMSK0 1 1 read-write H_AHBERRMSK0 2 1 read-write H_STALLMSK0 3 1 read-write H_NAKMSK0 4 1 read-write H_ACKMSK0 5 1 read-write H_NYETMSK0 6 1 read-write H_XACTERRMSK0 7 1 read-write H_BBLERRMSK0 8 1 read-write H_FRMOVRUNMSK0 9 1 read-write H_DATATGLERRMSK0 10 1 read-write H_BNAINTRMSK0 11 1 read-write H_DESC_LST_ROLLINTRMSK0 13 1 read-write HCTSIZ0 0x510 0x20 H_XFERSIZE0 0 19 read-write H_PKTCNT0 19 10 read-write H_PID0 29 2 read-write H_DOPNG0 31 1 read-write HCDMA0 0x514 0x20 H_DMAADDR0 0 32 read-write HCDMAB0 0x51C 0x20 H_HCDMAB0 0 32 read-only HCCHAR1 0x520 0x20 H_MPS1 0 11 read-write H_EPNUM1 11 4 read-write H_EPDIR1 15 1 read-write H_LSPDDEV1 17 1 read-write H_EPTYPE1 18 2 read-write H_EC1 21 1 read-write H_DEVADDR1 22 7 read-write H_ODDFRM1 29 1 read-write H_CHDIS1 30 1 read-write H_CHENA1 31 1 read-write HCINT1 0x528 0x20 H_XFERCOMPL1 0 1 read-write H_CHHLTD1 1 1 read-write H_AHBERR1 2 1 read-write H_STALL1 3 1 read-write H_NACK1 4 1 read-write H_ACK1 5 1 read-write H_NYET1 6 1 read-write H_XACTERR1 7 1 read-write H_BBLERR1 8 1 read-write H_FRMOVRUN1 9 1 read-write H_DATATGLERR1 10 1 read-write H_BNAINTR1 11 1 read-write H_XCS_XACT_ERR1 12 1 read-write H_DESC_LST_ROLLINTR1 13 1 read-write HCINTMSK1 0x52C 0x20 H_XFERCOMPLMSK1 0 1 read-write H_CHHLTDMSK1 1 1 read-write H_AHBERRMSK1 2 1 read-write H_STALLMSK1 3 1 read-write H_NAKMSK1 4 1 read-write H_ACKMSK1 5 1 read-write H_NYETMSK1 6 1 read-write H_XACTERRMSK1 7 1 read-write H_BBLERRMSK1 8 1 read-write H_FRMOVRUNMSK1 9 1 read-write H_DATATGLERRMSK1 10 1 read-write H_BNAINTRMSK1 11 1 read-write H_DESC_LST_ROLLINTRMSK1 13 1 read-write HCTSIZ1 0x530 0x20 H_XFERSIZE1 0 19 read-write H_PKTCNT1 19 10 read-write H_PID1 29 2 read-write H_DOPNG1 31 1 read-write HCDMA1 0x534 0x20 H_DMAADDR1 0 32 read-write HCDMAB1 0x53C 0x20 H_HCDMAB1 0 32 read-only HCCHAR2 0x540 0x20 H_MPS2 0 11 read-write H_EPNUM2 11 4 read-write H_EPDIR2 15 1 read-write H_LSPDDEV2 17 1 read-write H_EPTYPE2 18 2 read-write H_EC2 21 1 read-write H_DEVADDR2 22 7 read-write H_ODDFRM2 29 1 read-write H_CHDIS2 30 1 read-write H_CHENA2 31 1 read-write HCINT2 0x548 0x20 H_XFERCOMPL2 0 1 read-write H_CHHLTD2 1 1 read-write H_AHBERR2 2 1 read-write H_STALL2 3 1 read-write H_NACK2 4 1 read-write H_ACK2 5 1 read-write H_NYET2 6 1 read-write H_XACTERR2 7 1 read-write H_BBLERR2 8 1 read-write H_FRMOVRUN2 9 1 read-write H_DATATGLERR2 10 1 read-write H_BNAINTR2 11 1 read-write H_XCS_XACT_ERR2 12 1 read-write H_DESC_LST_ROLLINTR2 13 1 read-write HCINTMSK2 0x54C 0x20 H_XFERCOMPLMSK2 0 1 read-write H_CHHLTDMSK2 1 1 read-write H_AHBERRMSK2 2 1 read-write H_STALLMSK2 3 1 read-write H_NAKMSK2 4 1 read-write H_ACKMSK2 5 1 read-write H_NYETMSK2 6 1 read-write H_XACTERRMSK2 7 1 read-write H_BBLERRMSK2 8 1 read-write H_FRMOVRUNMSK2 9 1 read-write H_DATATGLERRMSK2 10 1 read-write H_BNAINTRMSK2 11 1 read-write H_DESC_LST_ROLLINTRMSK2 13 1 read-write HCTSIZ2 0x550 0x20 H_XFERSIZE2 0 19 read-write H_PKTCNT2 19 10 read-write H_PID2 29 2 read-write H_DOPNG2 31 1 read-write HCDMA2 0x554 0x20 H_DMAADDR2 0 32 read-write HCDMAB2 0x55C 0x20 H_HCDMAB2 0 32 read-only HCCHAR3 0x560 0x20 H_MPS3 0 11 read-write H_EPNUM3 11 4 read-write H_EPDIR3 15 1 read-write H_LSPDDEV3 17 1 read-write H_EPTYPE3 18 2 read-write H_EC3 21 1 read-write H_DEVADDR3 22 7 read-write H_ODDFRM3 29 1 read-write H_CHDIS3 30 1 read-write H_CHENA3 31 1 read-write HCINT3 0x568 0x20 H_XFERCOMPL3 0 1 read-write H_CHHLTD3 1 1 read-write H_AHBERR3 2 1 read-write H_STALL3 3 1 read-write H_NACK3 4 1 read-write H_ACK3 5 1 read-write H_NYET3 6 1 read-write H_XACTERR3 7 1 read-write H_BBLERR3 8 1 read-write H_FRMOVRUN3 9 1 read-write H_DATATGLERR3 10 1 read-write H_BNAINTR3 11 1 read-write H_XCS_XACT_ERR3 12 1 read-write H_DESC_LST_ROLLINTR3 13 1 read-write HCINTMSK3 0x56C 0x20 H_XFERCOMPLMSK3 0 1 read-write H_CHHLTDMSK3 1 1 read-write H_AHBERRMSK3 2 1 read-write H_STALLMSK3 3 1 read-write H_NAKMSK3 4 1 read-write H_ACKMSK3 5 1 read-write H_NYETMSK3 6 1 read-write H_XACTERRMSK3 7 1 read-write H_BBLERRMSK3 8 1 read-write H_FRMOVRUNMSK3 9 1 read-write H_DATATGLERRMSK3 10 1 read-write H_BNAINTRMSK3 11 1 read-write H_DESC_LST_ROLLINTRMSK3 13 1 read-write HCTSIZ3 0x570 0x20 H_XFERSIZE3 0 19 read-write H_PKTCNT3 19 10 read-write H_PID3 29 2 read-write H_DOPNG3 31 1 read-write HCDMA3 0x574 0x20 H_DMAADDR3 0 32 read-write HCDMAB3 0x57C 0x20 H_HCDMAB3 0 32 read-only HCCHAR4 0x580 0x20 H_MPS4 0 11 read-write H_EPNUM4 11 4 read-write H_EPDIR4 15 1 read-write H_LSPDDEV4 17 1 read-write H_EPTYPE4 18 2 read-write H_EC4 21 1 read-write H_DEVADDR4 22 7 read-write H_ODDFRM4 29 1 read-write H_CHDIS4 30 1 read-write H_CHENA4 31 1 read-write HCINT4 0x588 0x20 H_XFERCOMPL4 0 1 read-write H_CHHLTD4 1 1 read-write H_AHBERR4 2 1 read-write H_STALL4 3 1 read-write H_NACK4 4 1 read-write H_ACK4 5 1 read-write H_NYET4 6 1 read-write H_XACTERR4 7 1 read-write H_BBLERR4 8 1 read-write H_FRMOVRUN4 9 1 read-write H_DATATGLERR4 10 1 read-write H_BNAINTR4 11 1 read-write H_XCS_XACT_ERR4 12 1 read-write H_DESC_LST_ROLLINTR4 13 1 read-write HCINTMSK4 0x58C 0x20 H_XFERCOMPLMSK4 0 1 read-write H_CHHLTDMSK4 1 1 read-write H_AHBERRMSK4 2 1 read-write H_STALLMSK4 3 1 read-write H_NAKMSK4 4 1 read-write H_ACKMSK4 5 1 read-write H_NYETMSK4 6 1 read-write H_XACTERRMSK4 7 1 read-write H_BBLERRMSK4 8 1 read-write H_FRMOVRUNMSK4 9 1 read-write H_DATATGLERRMSK4 10 1 read-write H_BNAINTRMSK4 11 1 read-write H_DESC_LST_ROLLINTRMSK4 13 1 read-write HCTSIZ4 0x590 0x20 H_XFERSIZE4 0 19 read-write H_PKTCNT4 19 10 read-write H_PID4 29 2 read-write H_DOPNG4 31 1 read-write HCDMA4 0x594 0x20 H_DMAADDR4 0 32 read-write HCDMAB4 0x59C 0x20 H_HCDMAB4 0 32 read-only HCCHAR5 0x5A0 0x20 H_MPS5 0 11 read-write H_EPNUM5 11 4 read-write H_EPDIR5 15 1 read-write H_LSPDDEV5 17 1 read-write H_EPTYPE5 18 2 read-write H_EC5 21 1 read-write H_DEVADDR5 22 7 read-write H_ODDFRM5 29 1 read-write H_CHDIS5 30 1 read-write H_CHENA5 31 1 read-write HCINT5 0x5A8 0x20 H_XFERCOMPL5 0 1 read-write H_CHHLTD5 1 1 read-write H_AHBERR5 2 1 read-write H_STALL5 3 1 read-write H_NACK5 4 1 read-write H_ACK5 5 1 read-write H_NYET5 6 1 read-write H_XACTERR5 7 1 read-write H_BBLERR5 8 1 read-write H_FRMOVRUN5 9 1 read-write H_DATATGLERR5 10 1 read-write H_BNAINTR5 11 1 read-write H_XCS_XACT_ERR5 12 1 read-write H_DESC_LST_ROLLINTR5 13 1 read-write HCINTMSK5 0x5AC 0x20 H_XFERCOMPLMSK5 0 1 read-write H_CHHLTDMSK5 1 1 read-write H_AHBERRMSK5 2 1 read-write H_STALLMSK5 3 1 read-write H_NAKMSK5 4 1 read-write H_ACKMSK5 5 1 read-write H_NYETMSK5 6 1 read-write H_XACTERRMSK5 7 1 read-write H_BBLERRMSK5 8 1 read-write H_FRMOVRUNMSK5 9 1 read-write H_DATATGLERRMSK5 10 1 read-write H_BNAINTRMSK5 11 1 read-write H_DESC_LST_ROLLINTRMSK5 13 1 read-write HCTSIZ5 0x5B0 0x20 H_XFERSIZE5 0 19 read-write H_PKTCNT5 19 10 read-write H_PID5 29 2 read-write H_DOPNG5 31 1 read-write HCDMA5 0x5B4 0x20 H_DMAADDR5 0 32 read-write HCDMAB5 0x5BC 0x20 H_HCDMAB5 0 32 read-only HCCHAR6 0x5C0 0x20 H_MPS6 0 11 read-write H_EPNUM6 11 4 read-write H_EPDIR6 15 1 read-write H_LSPDDEV6 17 1 read-write H_EPTYPE6 18 2 read-write H_EC6 21 1 read-write H_DEVADDR6 22 7 read-write H_ODDFRM6 29 1 read-write H_CHDIS6 30 1 read-write H_CHENA6 31 1 read-write HCINT6 0x5C8 0x20 H_XFERCOMPL6 0 1 read-write H_CHHLTD6 1 1 read-write H_AHBERR6 2 1 read-write H_STALL6 3 1 read-write H_NACK6 4 1 read-write H_ACK6 5 1 read-write H_NYET6 6 1 read-write H_XACTERR6 7 1 read-write H_BBLERR6 8 1 read-write H_FRMOVRUN6 9 1 read-write H_DATATGLERR6 10 1 read-write H_BNAINTR6 11 1 read-write H_XCS_XACT_ERR6 12 1 read-write H_DESC_LST_ROLLINTR6 13 1 read-write HCINTMSK6 0x5CC 0x20 H_XFERCOMPLMSK6 0 1 read-write H_CHHLTDMSK6 1 1 read-write H_AHBERRMSK6 2 1 read-write H_STALLMSK6 3 1 read-write H_NAKMSK6 4 1 read-write H_ACKMSK6 5 1 read-write H_NYETMSK6 6 1 read-write H_XACTERRMSK6 7 1 read-write H_BBLERRMSK6 8 1 read-write H_FRMOVRUNMSK6 9 1 read-write H_DATATGLERRMSK6 10 1 read-write H_BNAINTRMSK6 11 1 read-write H_DESC_LST_ROLLINTRMSK6 13 1 read-write HCTSIZ6 0x5D0 0x20 H_XFERSIZE6 0 19 read-write H_PKTCNT6 19 10 read-write H_PID6 29 2 read-write H_DOPNG6 31 1 read-write HCDMA6 0x5D4 0x20 H_DMAADDR6 0 32 read-write HCDMAB6 0x5DC 0x20 H_HCDMAB6 0 32 read-only HCCHAR7 0x5E0 0x20 H_MPS7 0 11 read-write H_EPNUM7 11 4 read-write H_EPDIR7 15 1 read-write H_LSPDDEV7 17 1 read-write H_EPTYPE7 18 2 read-write H_EC7 21 1 read-write H_DEVADDR7 22 7 read-write H_ODDFRM7 29 1 read-write H_CHDIS7 30 1 read-write H_CHENA7 31 1 read-write HCINT7 0x5E8 0x20 H_XFERCOMPL7 0 1 read-write H_CHHLTD7 1 1 read-write H_AHBERR7 2 1 read-write H_STALL7 3 1 read-write H_NACK7 4 1 read-write H_ACK7 5 1 read-write H_NYET7 6 1 read-write H_XACTERR7 7 1 read-write H_BBLERR7 8 1 read-write H_FRMOVRUN7 9 1 read-write H_DATATGLERR7 10 1 read-write H_BNAINTR7 11 1 read-write H_XCS_XACT_ERR7 12 1 read-write H_DESC_LST_ROLLINTR7 13 1 read-write HCINTMSK7 0x5EC 0x20 H_XFERCOMPLMSK7 0 1 read-write H_CHHLTDMSK7 1 1 read-write H_AHBERRMSK7 2 1 read-write H_STALLMSK7 3 1 read-write H_NAKMSK7 4 1 read-write H_ACKMSK7 5 1 read-write H_NYETMSK7 6 1 read-write H_XACTERRMSK7 7 1 read-write H_BBLERRMSK7 8 1 read-write H_FRMOVRUNMSK7 9 1 read-write H_DATATGLERRMSK7 10 1 read-write H_BNAINTRMSK7 11 1 read-write H_DESC_LST_ROLLINTRMSK7 13 1 read-write HCTSIZ7 0x5F0 0x20 H_XFERSIZE7 0 19 read-write H_PKTCNT7 19 10 read-write H_PID7 29 2 read-write H_DOPNG7 31 1 read-write HCDMA7 0x5F4 0x20 H_DMAADDR7 0 32 read-write HCDMAB7 0x5FC 0x20 H_HCDMAB7 0 32 read-only DCFG 0x800 0x20 0x08100000 NZSTSOUTHSHK 2 1 read-write ENA32KHZSUSP 3 1 read-write DEVADDR 4 7 read-write PERFRLINT 11 2 read-write ENDEVOUTNAK 13 1 read-write XCVRDLY 14 1 read-write ERRATICINTMSK 15 1 read-write EPMISCNT 18 5 read-write DESCDMA 23 1 read-write PERSCHINTVL 24 2 read-write RESVALID 26 6 read-write DCTL 0x804 0x20 0x00002000 RMTWKUPSIG 0 1 read-write SFTDISCON 1 1 read-write GNPINNAKSTS 2 1 read-only GOUTNAKSTS 3 1 read-only TSTCTL 4 3 read-write SGNPINNAK 7 1 write-only CGNPINNAK 8 1 write-only SGOUTNAK 9 1 write-only CGOUTNAK 10 1 write-only PWRONPRGDONE 11 1 read-write GMC 13 2 read-write IGNRFRMNUM 15 1 read-write NAKONBBLE 16 1 read-write ENCOUNTONBNA 17 1 read-write DEEPSLEEPBESLREJECT 18 1 read-write DSTS 0x808 0x20 0x00000002 SUSPSTS 0 1 read-only ENUMSPD 1 2 read-only ERRTICERR 3 1 read-only SOFFN 8 14 read-only DEVLNSTS 22 2 read-only DIEPMSK 0x810 0x20 DI_XFERCOMPLMSK 0 1 read-write DI_EPDISBLDMSK 1 1 read-write DI_AHBERMSK 2 1 read-write TIMEOUTMSK 3 1 read-write INTKNTXFEMPMSK 4 1 read-write INTKNEPMISMSK 5 1 read-write INEPNAKEFFMSK 6 1 read-write TXFIFOUNDRNMSK 8 1 read-write BNAININTRMSK 9 1 read-write DI_NAKMSK 13 1 read-write DOEPMSK 0x814 0x20 XFERCOMPLMSK 0 1 read-write EPDISBLDMSK 1 1 read-write AHBERMSK 2 1 read-write SETUPMSK 3 1 read-write OUTTKNEPDISMSK 4 1 read-write STSPHSERCVDMSK 5 1 read-write BACK2BACKSETUP 6 1 read-write OUTPKTERRMSK 8 1 read-write BNAOUTINTRMSK 9 1 read-write BBLEERRMSK 12 1 read-write NAKMSK 13 1 read-write NYETMSK 14 1 read-write DAINT 0x818 0x20 INEPINT0 0 1 read-only INEPINT1 1 1 read-only INEPINT2 2 1 read-only INEPINT3 3 1 read-only INEPINT4 4 1 read-only INEPINT5 5 1 read-only INEPINT6 6 1 read-only OUTEPINT0 16 1 read-only OUTEPINT1 17 1 read-only OUTEPINT2 18 1 read-only OUTEPINT3 19 1 read-only OUTEPINT4 20 1 read-only OUTEPINT5 21 1 read-only OUTEPINT6 22 1 read-only DAINTMSK 0x81C 0x20 INEPMSK0 0 1 read-write INEPMSK1 1 1 read-write INEPMSK2 2 1 read-write INEPMSK3 3 1 read-write INEPMSK4 4 1 read-write INEPMSK5 5 1 read-write INEPMSK6 6 1 read-write OUTEPMSK0 16 1 read-write OUTEPMSK1 17 1 read-write OUTEPMSK2 18 1 read-write OUTEPMSK3 19 1 read-write OUTEPMSK4 20 1 read-write OUTEPMSK5 21 1 read-write OUTEPMSK6 22 1 read-write DVBUSDIS 0x828 0x20 0x000017D7 DVBUSDIS 0 16 read-write DVBUSPULSE 0x82C 0x20 0x000005B8 DVBUSPULSE 0 12 read-write DTHRCTL 0x830 0x20 0x08020020 NONISOTHREN 0 1 read-write ISOTHREN 1 1 read-write TXTHRLEN 2 9 read-write AHBTHRRATIO 11 2 read-write RXTHREN 16 1 read-write RXTHRLEN 17 9 read-write ARBPRKEN 27 1 read-write DIEPEMPMSK 0x834 0x20 D_INEPTXFEMPMSK 0 16 read-write DIEPCTL0 0x900 0x20 0x00008000 D_MPS0 0 2 read-write D_USBACTEP0 15 1 read-only D_NAKSTS0 17 1 read-only D_EPTYPE0 18 2 read-only D_STALL0 21 1 read-write D_TXFNUM0 22 4 read-write D_CNAK0 26 1 write-only DI_SNAK0 27 1 write-only D_EPDIS0 30 1 read-write D_EPENA0 31 1 read-write DIEPINT0 0x908 0x20 D_XFERCOMPL0 0 1 read-write D_EPDISBLD0 1 1 read-write D_AHBERR0 2 1 read-write D_TIMEOUT0 3 1 read-write D_INTKNTXFEMP0 4 1 read-write D_INTKNEPMIS0 5 1 read-write D_INEPNAKEFF0 6 1 read-write D_TXFEMP0 7 1 read-only D_TXFIFOUNDRN0 8 1 read-write D_BNAINTR0 9 1 read-write D_PKTDRPSTS0 11 1 read-write D_BBLEERR0 12 1 read-write D_NAKINTRPT0 13 1 read-write D_NYETINTRPT0 14 1 read-write DIEPTSIZ0 0x910 0x20 D_XFERSIZE0 0 7 read-write D_PKTCNT0 19 2 read-write DIEPDMA0 0x914 0x20 D_DMAADDR0 0 32 read-write DTXFSTS0 0x918 0x20 D_INEPTXFSPCAVAIL0 0 16 read-only DIEPDMAB0 0x91C 0x20 D_DMABUFFERADDR0 0 32 read-only DIEPCTL1 0x920 0x20 0x00008000 D_MPS1 0 2 read-write D_USBACTEP1 15 1 read-only D_NAKSTS1 17 1 read-only D_EPTYPE1 18 2 read-only D_STALL1 21 1 read-write D_TXFNUM1 22 4 read-write D_CNAK1 26 1 write-only DI_SNAK1 27 1 write-only DI_SETD0PID1 28 1 write-only DI_SETD1PID1 29 1 write-only D_EPDIS1 30 1 read-write D_EPENA1 31 1 read-write DIEPINT1 0x928 0x20 D_XFERCOMPL1 0 1 read-write D_EPDISBLD1 1 1 read-write D_AHBERR1 2 1 read-write D_TIMEOUT1 3 1 read-write D_INTKNTXFEMP1 4 1 read-write D_INTKNEPMIS1 5 1 read-write D_INEPNAKEFF1 6 1 read-write D_TXFEMP1 7 1 read-only D_TXFIFOUNDRN1 8 1 read-write D_BNAINTR1 9 1 read-write D_PKTDRPSTS1 11 1 read-write D_BBLEERR1 12 1 read-write D_NAKINTRPT1 13 1 read-write D_NYETINTRPT1 14 1 read-write DIEPTSIZ1 0x930 0x20 D_XFERSIZE1 0 7 read-write D_PKTCNT1 19 2 read-write DIEPDMA1 0x934 0x20 D_DMAADDR1 0 32 read-write DTXFSTS1 0x938 0x20 D_INEPTXFSPCAVAIL1 0 16 read-only DIEPDMAB1 0x93C 0x20 D_DMABUFFERADDR1 0 32 read-only DIEPCTL2 0x940 0x20 0x00008000 D_MPS2 0 2 read-write D_USBACTEP2 15 1 read-only D_NAKSTS2 17 1 read-only D_EPTYPE2 18 2 read-only D_STALL2 21 1 read-write D_TXFNUM2 22 4 read-write D_CNAK2 26 1 write-only DI_SNAK2 27 1 write-only DI_SETD0PID2 28 1 write-only DI_SETD1PID2 29 1 write-only D_EPDIS2 30 1 read-write D_EPENA2 31 1 read-write DIEPINT2 0x948 0x20 D_XFERCOMPL2 0 1 read-write D_EPDISBLD2 1 1 read-write D_AHBERR2 2 1 read-write D_TIMEOUT2 3 1 read-write D_INTKNTXFEMP2 4 1 read-write D_INTKNEPMIS2 5 1 read-write D_INEPNAKEFF2 6 1 read-write D_TXFEMP2 7 1 read-only D_TXFIFOUNDRN2 8 1 read-write D_BNAINTR2 9 1 read-write D_PKTDRPSTS2 11 1 read-write D_BBLEERR2 12 1 read-write D_NAKINTRPT2 13 1 read-write D_NYETINTRPT2 14 1 read-write DIEPTSIZ2 0x950 0x20 D_XFERSIZE2 0 7 read-write D_PKTCNT2 19 2 read-write DIEPDMA2 0x954 0x20 D_DMAADDR2 0 32 read-write DTXFSTS2 0x958 0x20 D_INEPTXFSPCAVAIL2 0 16 read-only DIEPDMAB2 0x95C 0x20 D_DMABUFFERADDR2 0 32 read-only DIEPCTL3 0x960 0x20 0x00008000 DI_MPS3 0 2 read-write DI_USBACTEP3 15 1 read-only DI_NAKSTS3 17 1 read-only DI_EPTYPE3 18 2 read-only DI_STALL3 21 1 read-write DI_TXFNUM3 22 4 read-write DI_CNAK3 26 1 write-only DI_SNAK3 27 1 write-only DI_SETD0PID3 28 1 write-only DI_SETD1PID3 29 1 write-only DI_EPDIS3 30 1 read-write DI_EPENA3 31 1 read-write DIEPINT3 0x968 0x20 D_XFERCOMPL3 0 1 read-write D_EPDISBLD3 1 1 read-write D_AHBERR3 2 1 read-write D_TIMEOUT3 3 1 read-write D_INTKNTXFEMP3 4 1 read-write D_INTKNEPMIS3 5 1 read-write D_INEPNAKEFF3 6 1 read-write D_TXFEMP3 7 1 read-only D_TXFIFOUNDRN3 8 1 read-write D_BNAINTR3 9 1 read-write D_PKTDRPSTS3 11 1 read-write D_BBLEERR3 12 1 read-write D_NAKINTRPT3 13 1 read-write D_NYETINTRPT3 14 1 read-write DIEPTSIZ3 0x970 0x20 D_XFERSIZE3 0 7 read-write D_PKTCNT3 19 2 read-write DIEPDMA3 0x974 0x20 D_DMAADDR3 0 32 read-write DTXFSTS3 0x978 0x20 D_INEPTXFSPCAVAIL3 0 16 read-only DIEPDMAB3 0x97C 0x20 D_DMABUFFERADDR3 0 32 read-only DIEPCTL4 0x980 0x20 0x00008000 D_MPS4 0 2 read-write D_USBACTEP4 15 1 read-only D_NAKSTS4 17 1 read-only D_EPTYPE4 18 2 read-only D_STALL4 21 1 read-write D_TXFNUM4 22 4 read-write D_CNAK4 26 1 write-only DI_SNAK4 27 1 write-only DI_SETD0PID4 28 1 write-only DI_SETD1PID4 29 1 write-only D_EPDIS4 30 1 read-write D_EPENA4 31 1 read-write DIEPINT4 0x988 0x20 D_XFERCOMPL4 0 1 read-write D_EPDISBLD4 1 1 read-write D_AHBERR4 2 1 read-write D_TIMEOUT4 3 1 read-write D_INTKNTXFEMP4 4 1 read-write D_INTKNEPMIS4 5 1 read-write D_INEPNAKEFF4 6 1 read-write D_TXFEMP4 7 1 read-only D_TXFIFOUNDRN4 8 1 read-write D_BNAINTR4 9 1 read-write D_PKTDRPSTS4 11 1 read-write D_BBLEERR4 12 1 read-write D_NAKINTRPT4 13 1 read-write D_NYETINTRPT4 14 1 read-write DIEPTSIZ4 0x990 0x20 D_XFERSIZE4 0 7 read-write D_PKTCNT4 19 2 read-write DIEPDMA4 0x994 0x20 D_DMAADDR4 0 32 read-write DTXFSTS4 0x998 0x20 D_INEPTXFSPCAVAIL4 0 16 read-only DIEPDMAB4 0x99C 0x20 D_DMABUFFERADDR4 0 32 read-only DIEPCTL5 0x9A0 0x20 0x00008000 DI_MPS5 0 2 read-write DI_USBACTEP5 15 1 read-only DI_NAKSTS5 17 1 read-only DI_EPTYPE5 18 2 read-only DI_STALL5 21 1 read-write DI_TXFNUM5 22 4 read-write DI_CNAK5 26 1 write-only DI_SNAK5 27 1 write-only DI_SETD0PID5 28 1 write-only DI_SETD1PID5 29 1 write-only DI_EPDIS5 30 1 read-write DI_EPENA5 31 1 read-write DIEPINT5 0x9A8 0x20 D_XFERCOMPL5 0 1 read-write D_EPDISBLD5 1 1 read-write D_AHBERR5 2 1 read-write D_TIMEOUT5 3 1 read-write D_INTKNTXFEMP5 4 1 read-write D_INTKNEPMIS5 5 1 read-write D_INEPNAKEFF5 6 1 read-write D_TXFEMP5 7 1 read-only D_TXFIFOUNDRN5 8 1 read-write D_BNAINTR5 9 1 read-write D_PKTDRPSTS5 11 1 read-write D_BBLEERR5 12 1 read-write D_NAKINTRPT5 13 1 read-write D_NYETINTRPT5 14 1 read-write DIEPTSIZ5 0x9B0 0x20 D_XFERSIZE5 0 7 read-write D_PKTCNT5 19 2 read-write DIEPDMA5 0x9B4 0x20 D_DMAADDR5 0 32 read-write DTXFSTS5 0x9B8 0x20 D_INEPTXFSPCAVAIL5 0 16 read-only DIEPDMAB5 0x9BC 0x20 D_DMABUFFERADDR5 0 32 read-only DIEPCTL6 0x9C0 0x20 0x00008000 D_MPS6 0 2 read-write D_USBACTEP6 15 1 read-only D_NAKSTS6 17 1 read-only D_EPTYPE6 18 2 read-only D_STALL6 21 1 read-write D_TXFNUM6 22 4 read-write D_CNAK6 26 1 write-only DI_SNAK6 27 1 write-only DI_SETD0PID6 28 1 write-only DI_SETD1PID6 29 1 write-only D_EPDIS6 30 1 read-write D_EPENA6 31 1 read-write DIEPINT6 0x9C8 0x20 D_XFERCOMPL6 0 1 read-write D_EPDISBLD6 1 1 read-write D_AHBERR6 2 1 read-write D_TIMEOUT6 3 1 read-write D_INTKNTXFEMP6 4 1 read-write D_INTKNEPMIS6 5 1 read-write D_INEPNAKEFF6 6 1 read-write D_TXFEMP6 7 1 read-only D_TXFIFOUNDRN6 8 1 read-write D_BNAINTR6 9 1 read-write D_PKTDRPSTS6 11 1 read-write D_BBLEERR6 12 1 read-write D_NAKINTRPT6 13 1 read-write D_NYETINTRPT6 14 1 read-write DIEPTSIZ6 0x9D0 0x20 D_XFERSIZE6 0 7 read-write D_PKTCNT6 19 2 read-write DIEPDMA6 0x9D4 0x20 D_DMAADDR6 0 32 read-write DTXFSTS6 0x9D8 0x20 D_INEPTXFSPCAVAIL6 0 16 read-only DIEPDMAB6 0x9DC 0x20 D_DMABUFFERADDR6 0 32 read-only DOEPCTL0 0xB00 0x20 0x00008000 MPS0 0 2 read-only USBACTEP0 15 1 read-only NAKSTS0 17 1 read-only EPTYPE0 18 2 read-only SNP0 20 1 read-write STALL0 21 1 read-write CNAK0 26 1 write-only DO_SNAK0 27 1 write-only EPDIS0 30 1 read-only EPENA0 31 1 read-write DOEPINT0 0xB08 0x20 XFERCOMPL0 0 1 read-write EPDISBLD0 1 1 read-write AHBERR0 2 1 read-write SETUP0 3 1 read-write OUTTKNEPDIS0 4 1 read-write STSPHSERCVD0 5 1 read-write BACK2BACKSETUP0 6 1 read-write OUTPKTERR0 8 1 read-write BNAINTR0 9 1 read-write PKTDRPSTS0 11 1 read-write BBLEERR0 12 1 read-write NAKINTRPT0 13 1 read-write NYEPINTRPT0 14 1 read-write STUPPKTRCVD0 15 1 read-write DOEPTSIZ0 0xB10 0x20 XFERSIZE0 0 7 read-write PKTCNT0 19 1 read-write SUPCNT0 29 2 read-write DOEPDMA0 0xB14 0x20 DMAADDR0 0 32 read-write DOEPDMAB0 0xB1C 0x20 DMABUFFERADDR0 0 32 read-write DOEPCTL1 0xB20 0x20 0x00008000 MPS1 0 11 read-only USBACTEP1 15 1 read-only NAKSTS1 17 1 read-only EPTYPE1 18 2 read-only SNP1 20 1 read-write STALL1 21 1 read-write CNAK1 26 1 write-only DO_SNAK1 27 1 write-only DO_SETD0PID1 28 1 write-only DO_SETD1PID1 29 1 write-only EPDIS1 30 1 read-only EPENA1 31 1 read-write DOEPINT1 0xB28 0x20 XFERCOMPL1 0 1 read-write EPDISBLD1 1 1 read-write AHBERR1 2 1 read-write SETUP1 3 1 read-write OUTTKNEPDIS1 4 1 read-write STSPHSERCVD1 5 1 read-write BACK2BACKSETUP1 6 1 read-write OUTPKTERR1 8 1 read-write BNAINTR1 9 1 read-write PKTDRPSTS1 11 1 read-write BBLEERR1 12 1 read-write NAKINTRPT1 13 1 read-write NYEPINTRPT1 14 1 read-write STUPPKTRCVD1 15 1 read-write DOEPTSIZ1 0xB30 0x20 XFERSIZE1 0 7 read-write PKTCNT1 19 1 read-write SUPCNT1 29 2 read-write DOEPDMA1 0xB34 0x20 DMAADDR1 0 32 read-write DOEPDMAB1 0xB3C 0x20 DMABUFFERADDR1 0 32 read-write DOEPCTL2 0xB40 0x20 0x00008000 MPS2 0 11 read-only USBACTEP2 15 1 read-only NAKSTS2 17 1 read-only EPTYPE2 18 2 read-only SNP2 20 1 read-write STALL2 21 1 read-write CNAK2 26 1 write-only DO_SNAK2 27 1 write-only DO_SETD0PID2 28 1 write-only DO_SETD1PID2 29 1 write-only EPDIS2 30 1 read-only EPENA2 31 1 read-write DOEPINT2 0xB48 0x20 XFERCOMPL2 0 1 read-write EPDISBLD2 1 1 read-write AHBERR2 2 1 read-write SETUP2 3 1 read-write OUTTKNEPDIS2 4 1 read-write STSPHSERCVD2 5 1 read-write BACK2BACKSETUP2 6 1 read-write OUTPKTERR2 8 1 read-write BNAINTR2 9 1 read-write PKTDRPSTS2 11 1 read-write BBLEERR2 12 1 read-write NAKINTRPT2 13 1 read-write NYEPINTRPT2 14 1 read-write STUPPKTRCVD2 15 1 read-write DOEPTSIZ2 0xB50 0x20 XFERSIZE2 0 7 read-write PKTCNT2 19 1 read-write SUPCNT2 29 2 read-write DOEPDMA2 0xB54 0x20 DMAADDR2 0 32 read-write DOEPDMAB2 0xB5C 0x20 DMABUFFERADDR2 0 32 read-write DOEPCTL3 0xB60 0x20 0x00008000 MPS3 0 11 read-only USBACTEP3 15 1 read-only NAKSTS3 17 1 read-only EPTYPE3 18 2 read-only SNP3 20 1 read-write STALL3 21 1 read-write CNAK3 26 1 write-only DO_SNAK3 27 1 write-only DO_SETD0PID3 28 1 write-only DO_SETD1PID3 29 1 write-only EPDIS3 30 1 read-only EPENA3 31 1 read-write DOEPINT3 0xB68 0x20 XFERCOMPL3 0 1 read-write EPDISBLD3 1 1 read-write AHBERR3 2 1 read-write SETUP3 3 1 read-write OUTTKNEPDIS3 4 1 read-write STSPHSERCVD3 5 1 read-write BACK2BACKSETUP3 6 1 read-write OUTPKTERR3 8 1 read-write BNAINTR3 9 1 read-write PKTDRPSTS3 11 1 read-write BBLEERR3 12 1 read-write NAKINTRPT3 13 1 read-write NYEPINTRPT3 14 1 read-write STUPPKTRCVD3 15 1 read-write DOEPTSIZ3 0xB70 0x20 XFERSIZE3 0 7 read-write PKTCNT3 19 1 read-write SUPCNT3 29 2 read-write DOEPDMA3 0xB74 0x20 DMAADDR3 0 32 read-write DOEPDMAB3 0xB7C 0x20 DMABUFFERADDR3 0 32 read-write DOEPCTL4 0xB80 0x20 0x00008000 MPS4 0 11 read-only USBACTEP4 15 1 read-only NAKSTS4 17 1 read-only EPTYPE4 18 2 read-only SNP4 20 1 read-write STALL4 21 1 read-write CNAK4 26 1 write-only DO_SNAK4 27 1 write-only DO_SETD0PID4 28 1 write-only DO_SETD1PID4 29 1 write-only EPDIS4 30 1 read-only EPENA4 31 1 read-write DOEPINT4 0xB88 0x20 XFERCOMPL4 0 1 read-write EPDISBLD4 1 1 read-write AHBERR4 2 1 read-write SETUP4 3 1 read-write OUTTKNEPDIS4 4 1 read-write STSPHSERCVD4 5 1 read-write BACK2BACKSETUP4 6 1 read-write OUTPKTERR4 8 1 read-write BNAINTR4 9 1 read-write PKTDRPSTS4 11 1 read-write BBLEERR4 12 1 read-write NAKINTRPT4 13 1 read-write NYEPINTRPT4 14 1 read-write STUPPKTRCVD4 15 1 read-write DOEPTSIZ4 0xB90 0x20 XFERSIZE4 0 7 read-write PKTCNT4 19 1 read-write SUPCNT4 29 2 read-write DOEPDMA4 0xB94 0x20 DMAADDR4 0 32 read-write DOEPDMAB4 0xB9C 0x20 DMABUFFERADDR4 0 32 read-write DOEPCTL5 0xBA0 0x20 0x00008000 MPS5 0 11 read-only USBACTEP5 15 1 read-only NAKSTS5 17 1 read-only EPTYPE5 18 2 read-only SNP5 20 1 read-write STALL5 21 1 read-write CNAK5 26 1 write-only DO_SNAK5 27 1 write-only DO_SETD0PID5 28 1 write-only DO_SETD1PID5 29 1 write-only EPDIS5 30 1 read-only EPENA5 31 1 read-write DOEPINT5 0xBA8 0x20 XFERCOMPL5 0 1 read-write EPDISBLD5 1 1 read-write AHBERR5 2 1 read-write SETUP5 3 1 read-write OUTTKNEPDIS5 4 1 read-write STSPHSERCVD5 5 1 read-write BACK2BACKSETUP5 6 1 read-write OUTPKTERR5 8 1 read-write BNAINTR5 9 1 read-write PKTDRPSTS5 11 1 read-write BBLEERR5 12 1 read-write NAKINTRPT5 13 1 read-write NYEPINTRPT5 14 1 read-write STUPPKTRCVD5 15 1 read-write DOEPTSIZ5 0xBB0 0x20 XFERSIZE5 0 7 read-write PKTCNT5 19 1 read-write SUPCNT5 29 2 read-write DOEPDMA5 0xBB4 0x20 DMAADDR5 0 32 read-write DOEPDMAB5 0xBBC 0x20 DMABUFFERADDR5 0 32 read-write DOEPCTL6 0xBC0 0x20 0x00008000 MPS6 0 11 read-only USBACTEP6 15 1 read-only NAKSTS6 17 1 read-only EPTYPE6 18 2 read-only SNP6 20 1 read-write STALL6 21 1 read-write CNAK6 26 1 write-only DO_SNAK6 27 1 write-only DO_SETD0PID6 28 1 write-only DO_SETD1PID6 29 1 write-only EPDIS6 30 1 read-only EPENA6 31 1 read-write DOEPINT6 0xBC8 0x20 XFERCOMPL6 0 1 read-write EPDISBLD6 1 1 read-write AHBERR6 2 1 read-write SETUP6 3 1 read-write OUTTKNEPDIS6 4 1 read-write STSPHSERCVD6 5 1 read-write BACK2BACKSETUP6 6 1 read-write OUTPKTERR6 8 1 read-write BNAINTR6 9 1 read-write PKTDRPSTS6 11 1 read-write BBLEERR6 12 1 read-write NAKINTRPT6 13 1 read-write NYEPINTRPT6 14 1 read-write STUPPKTRCVD6 15 1 read-write DOEPTSIZ6 0xBD0 0x20 XFERSIZE6 0 7 read-write PKTCNT6 19 1 read-write SUPCNT6 29 2 read-write DOEPDMA6 0xBD4 0x20 DMAADDR6 0 32 read-write DOEPDMAB6 0xBDC 0x20 DMABUFFERADDR6 0 32 read-write PCGCCTL 0xE00 0x20 STOPPCLK 0 1 read-write GATEHCLK 1 1 read-write PWRCLMP 2 1 read-write RSTPDWNMODULE 3 1 read-write PHYSLEEP 6 1 read-only L1SUSPENDED 7 1 read-only RESETAFTERSUSP 8 1 read-write USB_WRAP USB_WRAP Peripheral USB_WRAP 0x3F439000 0x0 0xC registers OTG_CONF USB OTG Wrapper Configure Register 0x0 0x20 0x001C0000 SRP_SESSEND_OVERRIDE This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input. 1'b1: the signal is controlled by the software. 0 1 read-write SRP_SESSEND_VALUE Software over-ride value of srp session end signal. 1 1 read-write PHY_SEL Select internal external PHY. 1'b0: Select internal PHY. 1'b1: Select external PHY. 2 1 read-write DFIFO_FORCE_PD Force the dfifo to go into low power mode. The data in dfifo will not lost. 3 1 read-write DBNCE_FLTR_BYPASS Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals 4 1 read-write EXCHG_PINS_OVERRIDE Enable software controlle USB D+ D- exchange 5 1 read-write EXCHG_PINS USB D+ D- exchange. 1'b0: don't change. 1'b1: exchange D+ D- 6 1 read-write VREFH Control single-end input high threshold,1.76V to 2V, step 80mV 7 2 read-write VREFL Control single-end input low threshold,0.8V to 1.04V, step 80mV 9 2 read-write VREF_OVERRIDE Enable software controlle input threshold 11 1 read-write PAD_PULL_OVERRIDE Enable software controlle USB D+ D- pullup pulldown 12 1 read-write DP_PULLUP Controlle USB D+ pullup 13 1 read-write DP_PULLDOWN Controlle USB D+ pulldown 14 1 read-write DM_PULLUP Controlle USB D+ pullup 15 1 read-write DM_PULLDOWN Controlle USB D+ pulldown 16 1 read-write PULLUP_VALUE Controlle pullup value. 1'b0: typical value is 2.4K. 1'b1: typical value is 1.2K. 17 1 read-write USB_PAD_ENABLE Enable USB pad function 18 1 read-write AHB_CLK_FORCE_ON Force ahb clock always on 19 1 read-write PHY_CLK_FORCE_ON Force phy clock always on 20 1 read-write PHY_TX_EDGE_SEL Select phy tx signal output clock edge. 1'b0: negedge. 1'b1: posedge. 21 1 read-write DFIFO_FORCE_PU Disable the dfifo to go into low power mode. The data in dfifo will not lost. 22 1 read-write CLK_EN Disable auto clock gating of CSR registers 31 1 read-write TEST_CONF USB Internal PHY Testing Register 0x4 0x20 TEST_ENABLE Enable test of the USB pad 0 1 read-write TEST_USB_OE USB pad oen in test 1 1 read-write TEST_TX_DP USB D+ tx value in test 2 1 read-write TEST_TX_DM USB D- tx value in test 3 1 read-write TEST_RX_RCV USB differential rx value in test 4 1 read-only TEST_RX_DP USB D+ rx value in test 5 1 read-only TEST_RX_DM USB D- rx value in test 6 1 read-only DATE Version Control Register 0x3FC 0x20 0x02102010 USB_WRAP_DATE Date register 0 32 read-write XTS_AES XTS-AES-128 Flash Encryption XTS_AES 0x6003A100 0x0 0x60 registers 16 0x4 PLAIN_%s Plaintext register %s 0x100 0x20 PLAIN This register stores %sth 32-bit piece of plaintext. 0 32 read-write LINESIZE Configures the size of target memory space 0x140 0x20 LINESIZE Configures the data size of a single encryption. 0: 128 bits. 1: 256 bits. 2: 512 bits. 0 2 read-write DESTINATION Configures the type of the external memory 0x144 0x20 DESTINATION Configures the type of the external memory. Currently, it must be set to 0, as the Manual Encryption block only supports flash encryption. Errors may occur if users write 1. 0: flash. 1: external RAM. 0 1 read-write PHYSICAL_ADDRESS Physical address 0x148 0x20 PHYSICAL_ADDRESS Physical address. 0 30 read-write TRIGGER Activates AES algorithm 0x14C 0x20 TRIGGER Set to enable manual encryption. 0 1 write-only RELEASE Release control 0x150 0x20 RELEASE Set to grant SPI1 access to encrypted result. 0 1 write-only DESTROY Destroys control 0x154 0x20 DESTROY Set to destroy encrypted result. 0 1 write-only STATE Status register 0x158 0x20 STATE Indicates the status of the Manual Encryption block. 0x0 (XTS_AES_IDLE): idle. 0x1 (XTS_AES_BUSY): busy with encryption. 0x2 (XTS_AES_DONE): encryption is completed, but the encrypted result is not accessible to SPI. 0X3 (XTS_AES_RELEASE): encrypted result is accessible to SPI. 0 2 read-only DATE Version control register 0x15C 0x20 0x20190514 DATE Version control register. 0 30 read-only