Keil ArteryTek AT32F402xx_v2 AT32F402 1.0 ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 216MHz, etc. ARM Limited (ARM) is supplying this software for use with Cortex-M\n processor based microcontroller, but can be equally used for other\n suitable processor architectures. This file can be freely distributed.\n Modifications to this file shall be clearly marked.\n \n THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. CM4 r0p1 little false true 4 false 8 32 32 read-write 0x00000000 0xFFFFFFFF PWC Power control PWC 0x40007000 0x0 0x400 registers CTRL CTRL Power control register (PWC_CTRL) 0x0 0x20 read-write 0x00000000 VRSEL Voltage regulator state select when deepsleep mode 0 1 LPSEL Low power mode select when Cortex-M4F sleepdeep 1 1 CLSWEF Clear SWEF flag 2 1 CLSEF Clear SEF flag 3 1 PVMEN Power voltage monitoring enable 4 1 PVMSEL Power voltage monitoring boundary select 5 3 BPWEN Battery powered domain write enable 8 1 CTRLSTS CTRLSTS Power control and status register (PWC_CTRLSTS) 0x4 0x20 0x00000000 SWEF Standby wake-up event flag 0 1 read-only SEF Standby mode entry flag 1 1 read-only PVMOF Power voltage monitoring output flag 2 1 read-only SWPEN1 Standby wake-up pin 1 enable 8 1 read-write SWPEN2 Standby wake-up pin 2 enable 9 1 read-write SWPEN6 Standby wake-up pin 6 enable 13 1 read-write LDOOV LDOOV LDO output voltage register 0x10 0x20 0x00000012 LDOOVSEL LDO output voltage select 0 2 read-write VREXLPEN Voltage regulator extra low power mode enable 4 1 read-write CRM Clock and reset management CRM 0x40023800 0x0 0x400 registers CRM CRM global interrupt 5 CTRL CTRL Clock control register 0x0 0x20 0x00000083 HICKEN High speed internal clock enable 0 1 read-write HICKSTBL High speed internal clock ready flag 1 1 read-only HICKTRIM High speed internal clock trimming 2 6 read-write HICKCAL High speed internal clock calibration 8 8 read-only HEXTEN High speed exernal crystal enable 16 1 read-write HEXTSTBL High speed exernal crystal ready flag 17 1 read-only HEXTBYPS High speed exernal crystal bypass 18 1 read-write CFDEN Clock failure detection enable 19 1 read-write PLLEN PLL enable 24 1 read-write PLLSTBL PLL clock ready flag 25 1 read-only PLLUSTBL PLLU clock ready flag 26 1 read-only PLLCFG PLLCFG PLL configuration register (CRM_PLLCFG) 0x4 0x20 0x00033002 PLL_MS PLL pre-division 0 4 read-write PLL_NS PLL frequency multiplication factor 6 9 read-write PLL_FP PLLP post-division 16 4 read-write PLL_FU PLLU post-division 20 3 read-write PLLU_EN PLLU enable 29 1 read-write PLLRCS PLL reference clock select 30 1 read-write CFG CFG Clock configuration register(CRM_CFG) 0x8 0x20 0x00000000 SCLKSEL System clock select 0 2 read-write SCLKSTS System Clock select Status 2 2 read-only AHBDIV AHB division 4 4 read-write APB1DIV APB1 division 10 3 read-write APB2DIV APB2 division 13 3 read-write ERTCDIV HEXT division for ERTC clock 16 5 read-write I2S5CLKSEL I2S clock select 22 2 read-write CLKOUTDIV1 Clock output division1 27 3 read-write CLKOUT_SEL1 Clock output selection1 30 2 read-write CLKINT CLKINT Clock interrupt register (CRM_CLKINT) 0xC 0x20 0x00000000 LICKSTBLF LICK ready interrupt flag 0 1 read-only LEXTSTBLF LEXT ready interrupt flag 1 1 read-only HICKSTBLF HICK ready interrupt flag 2 1 read-only HEXTSTBLF HEXT ready interrupt flag 3 1 read-only PLLSTBLF PLL ready interrupt flag 4 1 read-only CFDF Clock failure detection interrupt flag 7 1 read-only LICKSTBLIEN LICK ready interrupt enable 8 1 read-write LEXTSTBLIEN LEXT ready interrupt enable 9 1 read-write HICKSTBLIEN HICK ready interrupt enable 10 1 read-write HEXTSTBLIEN HEXT ready interrupt enable 11 1 read-write PLLSTBLIEN PLL ready interrupt enable 12 1 read-write LICKSTBLFC LICK ready interrupt clear 16 1 write-only LEXTSTBLFC LEXT ready interrupt clear 17 1 write-only HICKSTBLFC HICK ready interrupt clear 18 1 write-only HEXTSTBLFC HEXT ready interrupt clear 19 1 write-only PLLSTBLFC PLL ready interrupt clear 20 1 write-only CFDFC Clock failure detection interrupt clear 23 1 write-only AHBRST1 AHBRST1 AHB peripheral reset register1 (CRM_AHBRST1) 0x10 0x20 read-write 0x000000000 GPIOARST IO port A reset 0 1 GPIOBRST IO port B reset 1 1 GPIOCRST IO port C reset 2 1 GPIODRST IO port D reset 3 1 GPIOFRST IO port F reset 5 1 CRCRST CRC reset 12 1 DMA1RST DMA1 reset 22 1 DMA2RST DMA2 reset 24 1 OTGHSRST OTGHS interface reset 29 1 AHBRST2 AHBRST2 AHB peripheral reset register 2 (CRM_AHBRST2) 0x14 0x20 read-write 0x00000000 OTGFS1RST OTGFS1 reset 7 1 AHBRST3 AHBRST3 AHB peripheral reset register 3 (CRM_AHBRST3) 0x18 0x20 read-write 0x00000000 QSPI1RST QSPI1 reset 1 1 APB1RST APB1RST APB1 peripheral reset register (CRM_APB1RST) 0x20 0x20 read-write 0x00000000 TMR2RST Timer2 reset 0 1 TMR3RST Timer3 reset 1 1 TMR4RST Timer4 reset 2 1 TMR6RST Timer6 reset 4 1 TMR7RST Timer7 reset 5 1 TMR13RST Timer13 reset 7 1 TMR14RST Timer14 reset 8 1 WWDTRST Window watchdog reset 11 1 SPI2RST SPI2 reset 14 1 SPI3RST SPI3 reset 15 1 USART2RST USART2 reset 17 1 USART3RST USART3 reset 18 1 USART4RST USART4 reset 19 1 USART5RST USART5 reset 20 1 I2C1RST I2C1 reset 21 1 I2C2RST I2C2 reset 22 1 I2C3RST I2C3 reset 23 1 CAN1RST CAN1 reset 25 1 PWCRST PWC reset 28 1 UART7RST UART7 reset 30 1 UART8RST UART8 reset 31 1 APB2RST APB2RST APB2 peripheral reset register (CRM_APB2RST) 0x24 0x20 read-write 0x00000000 TMR1RST Timer1 reset 0 1 USART1RST USART1 reset 4 1 USART6RST USART6 reset 5 1 ADCRST ADC reset 8 1 SPI1RST SPI1 reset 12 1 SCFGRST SCFG reset 14 1 TMR9RST Timer9 reset 16 1 TMR10RST Timer10 reset 17 1 TMR11RST Timer 11 reset 18 1 I2S5RST I2S5 reset 20 1 ACCRST ACC reset 29 1 OTGHSPHYRST OTGHS phy reset 31 1 AHBEN1 AHBEN1 AHB Peripheral Clock enable register 1 (CRM_AHBEN1) 0x30 0x20 read-write 0x00000000 GPIOAEN IO A clock enable 0 1 GPIOBEN IO B clock enable 1 1 GPIOCEN IO C clock enable 2 1 GPIODEN IO D clock enable 3 1 GPIOFEN IO F clock enable 5 1 CRCEN CRC clock enable 12 1 DMA1EN DMA1 clock enable 22 1 DMA2EN DMA2 clock enable 24 1 OTGHSEN OTGHS clock enable 29 1 AHBEN2 AHBEN2 AHB peripheral clock enable register 2 (CRM_AHBEN2) 0x34 0x20 read-write 0x00000000 OTGFS1EN OTGFS1 clock enable 7 1 AHBEN3 AHBEN3 AHB peripheral clock enable register 3 (CRM_AHBEN3) 0x38 0x20 read-write 0x00000000 QSPI1EN QSPI1 clock enable 1 1 APB1EN APB1EN APB1 peripheral clock enable register (CRM_APB1EN) 0x40 0x20 read-write 0x00000000 TMR2EN Timer2 clock enable 0 1 TMR3EN Timer3 clock enable 1 1 TMR4EN Timer4 clock enable 2 1 TMR6EN Timer6 clock enable 4 1 TMR7EN Timer7 clock enable 5 1 TMR13EN Timer13 clock enable 7 1 TMR14EN Timer14 clock enable 8 1 WWDTEN WWDT clock enable 11 1 SPI2EN SPI2 clock enable 14 1 SPI3EN SPI3 clock enable 15 1 USART2EN USART2 clock enable 17 1 USART3EN USART3 clock enable 18 1 USART4EN USART4 clock enable 19 1 USART5EN USART5 clock enable 20 1 I2C1EN I2C1 clock enable 21 1 I2C2EN I2C2 clock enable 22 1 I2C3EN I2C3 clock enable 23 1 CAN1EN CAN1 clock enable 25 1 PWCEN PWC clock enable 28 1 UART7EN UART7 clock enable 30 1 UART8EN UART8 clock enable 31 1 APB2EN APB2EN APB2 peripheral clock enable register (CRM_APB2EN) 0x44 0x20 read-write 0x00000000 TMR1EN Timer1 clock enable 0 1 USART1EN USART1 clock enable 4 1 USART6EN USART6 clock enable 5 1 ADC1EN ADC1 clock enable 8 1 SPI1EN SPI1 clock enable 12 1 SCFGEN SCFG clock enable 14 1 TMR9EN Timer9 clock enable 16 1 TMR10EN Timer10 clock enable 17 1 TMR11EN Timer11 clock enable 18 1 I2S5EN I2S5 clock enable 20 1 ACCEN ACC clock enable 29 1 AHBLPEN1 AHBLPEN1 AHB Low-power Peripheral Clock enable register 1 (CRM_AHBLPEN1) 0x50 0x20 read-write 0x3E6390FF GPIOALPEN IO A clock enable during sleep mode 0 1 GPIOBLPEN IO B clock enable during sleep mode 1 1 GPIOCLPEN IO C clock enable during sleep mode 2 1 GPIODLPEN IO D clock enable during sleep mode 3 1 GPIOFLPEN IO F clock enable during sleep mode 5 1 CRCLPEN CRC clock enable during sleep mode 12 1 FLASHLPEN Flash clock enable during sleep mode 15 1 SRAMLPEN SRAM clock enable during sleep mode 16 1 DMA1LPEN DMA1 clock enable during sleep mode 22 1 DMA2LPEN DMA2 clock enable during sleep mode 24 1 OTGHSLPEN OTGHS clock enable during sleep mode 29 1 AHBLPEN2 AHBLPEN2 AHB peripheral Low-power clock enable register 2 (CRM_AHBLPEN2) 0x54 0x20 read-write 0x00008081 OTGFS1LPEN OTGFS1 clock enable during sleep mode 7 1 AHBLPEN3 AHBLPEN3 AHB peripheral Low-power clock enable register 3 (CRM_AHBLPEN3) 0x58 0x20 read-write 0x0000C003 QSPI1LPEN QSPI1 clock enable during sleep mode 1 1 APB1LPEN APB1LPEN APB1 peripheral Low-power clock enable register (CRM_APB1LPEN) 0x60 0x20 read-write 0xF6FEE9FF TMR2LPEN Timer2 clock enable during sleep mode 0 1 TMR3LPEN Timer3 clock enable during sleep mode 1 1 TMR4LPEN Timer4 clock enable during sleep mode 2 1 TMR6LPEN Timer6 clock enable during sleep mode 4 1 TMR7LPEN Timer7 clock enable during sleep mode 5 1 TMR13LPEN Timer13 clock enable during sleep mode 7 1 TMR14LPEN Timer14 clock enable during sleep mode 8 1 WWDTLPEN WWDT clock enable during sleep mode 11 1 SPI2LPEN SPI2 clock enable during sleep mode 14 1 SPI3LPEN SPI3 clock enable during sleep mode 15 1 USART2LPEN USART2 clock enable during sleep mode 17 1 USART3LPEN USART3 clock enable during sleep mode 18 1 USART4LPEN USART4 clock enable during sleep mode 19 1 USART5LPEN USART5 clock enable during sleep mode 20 1 I2C1CPEN I2C1 clock enable during sleep mode 21 1 I2C2CPEN I2C2 clock enable during sleep mode 22 1 I2C3CPEN I2C3 clock enable during sleep mode 23 1 CAN1LPEN CAN1 clock enable during sleep mode 25 1 PWCLPEN PWC clock enable during sleep mode 28 1 UART7LPEN UART7 clock enable during sleep mode 30 1 UART8LPEN UART8 clock enable during sleep mode 31 1 APB2LPEN APB2LPEN APB2 peripheral Low-power clock enable register (CRM_APB2LPEN) 0x64 0x20 read-write 0x20177733 TMR1LPEN Timer1 clock enable during sleep mode 0 1 USART1LPEN USART1 clock enable during sleep mode 4 1 USART6LPEN USART6 clock enable during sleep mode 5 1 SPI1LPEN SPI1 clock enable during sleep mode 12 1 SCFGLPEN SCFG clock enable during sleep mode 14 1 TMR9LPEN Timer9 clock enable during sleep mode 16 1 TMR10LPEN Timer10 clock enable during sleep mode 17 1 TMR11LPEN Timer11 clock enable during sleep mode 18 1 I2S5LPEN I2S5 clock enable during sleep mode 20 1 ACCLPEN ACC clock enable during sleep mode 29 1 OTGHSPHYLPEN OTGHS phy clock enable during sleep mode 31 1 BPDC BPDC Battery powered domain control register (CRM_BPDC) 0x70 0x20 0x00000000 LEXTEN Low speed external crystal enable 0 1 read-write LEXTSTBL Low speed external crystal ready 1 1 read-only LEXTBYPS Low speed external crystal bypass 2 1 read-write ERTCSEL ERTC clock source selection 8 2 read-write ERTCEN ERTC clock enable 15 1 read-write BPDRST Battery powered domain software reset 16 1 read-write CTRLSTS CTRLSTS Control/status register (CRM_CTRLSTS) 0x74 0x20 0x0C000000 LICKEN Low speed internal clock enable 0 1 read-write LICKSTBL Low speed internal clock ready 1 1 read-only RSTFC Reset reset flag 24 1 read-write NRSTF PIN reset flag 26 1 read-write PORRSTF POR/LVR reset flag 27 1 read-write SWRSTF Software reset flag 28 1 read-write WDTRSTF Watchdog timer reset flag 29 1 read-write WWDTRSTF Window watchdog timer reset flag 30 1 read-write LPRSTF Low-power reset flag 31 1 read-write OTGHS OTGHS OTGHS register 0x78 0x20 0x00000000 USBHS_PHY12_SEL USBHS phy12 select value 3 2 read-write MISC1 MISC1 Miscellaneous register1 0xA0 0x20 0x00000000 HICKCAL_KEY HICKCAL write key value 0 8 read-write HICKDIV HICK 6 divider selection 12 1 read-write HICK_TO_SCLK HICK to system clock 14 1 read-write CLKOUT_SEL2 Clock output select2 16 4 read-write CLKOUTDIV2 Clock output division2 28 4 read-write MISC2 MISC2 Miscellaneous register2 0xA4 0x20 0x0000000D AUTO_STEP_EN AUTO_STEP_EN 4 2 read-write PLLU_USB48_SEL USB clock source select 10 1 read-write HICK_TO_SCLK_DIV HICK as system clock frequency division 16 3 read-write HEXT_TO_SCLK_DIV HEXT as system clock frequency division 19 3 read-write GPIOA General purpose I/Os GPIO 0x40020000 0x0 0x400 registers CFGR CFGR GPIO configuration register 0x0 0x20 read-write 0x00000000 IOMC15 GPIOx pin 15 mode configurate 30 2 IOMC14 GPIOx pin 14 mode configurate 28 2 IOMC13 GPIOx pin 13 mode configurate 26 2 IOMC12 GPIOx pin 12 mode configurate 24 2 IOMC11 GPIOx pin 11 mode configurate 22 2 IOMC10 GPIOx pin 10 mode configurate 20 2 IOMC9 GPIOx pin 9 mode configurate 18 2 IOMC8 GPIOx pin 8 mode configurate 16 2 IOMC7 GPIOx pin 7 mode configurate 14 2 IOMC6 GPIOx pin 6 mode configurate 12 2 IOMC5 GPIOx pin 5 mode configurate 10 2 IOMC4 GPIOx pin 4 mode configurate 8 2 IOMC3 GPIOx pin 3 mode configurate 6 2 IOMC2 GPIOx pin 2 mode configurate 4 2 IOMC1 GPIOx pin 1 mode configurate 2 2 IOMC0 GPIOx pin 0 mode configurate 0 2 OMODE OMODE GPIO output mode register 0x4 0x20 read-write 0x00000000 OM15 GPIOx pin 15 outpu mode configurate 15 1 OM14 GPIOx pin 14 outpu mode configurate 14 1 OM13 GPIOx pin 13 outpu mode configurate 13 1 OM12 GPIOx pin 12 outpu mode configurate 12 1 OM11 GPIOx pin 11 outpu mode configurate 11 1 OM10 GPIOx pin 10 outpu mode configurate 10 1 OM9 GPIOx pin 9 outpu mode configurate 9 1 OM8 GPIOx pin 8 outpu mode configurate 8 1 OM7 GPIOx pin 7 outpu mode configurate 7 1 OM6 GPIOx pin 6 outpu mode configurate 6 1 OM5 GPIOx pin 5 outpu mode configurate 5 1 OM4 GPIOx pin 4 outpu mode configurate 4 1 OM3 GPIOx pin 3 outpu mode configurate 3 1 OM2 GPIOx pin 2 outpu mode configurate 2 1 OM1 GPIOx pin 1 outpu mode configurate 1 1 OM0 GPIOx pin 0 outpu mode configurate 0 1 ODRVR ODRVR GPIO drive capability register 0x8 0x20 read-write 0x00000000 ODRV15 GPIOx pin 15 output drive capability 30 2 ODRV14 GPIOx pin 14 output drive capability 28 2 ODRV13 GPIOx pin 13 output drive capability 26 2 ODRV12 GPIOx pin 12 output drive capability 24 2 ODRV11 GPIOx pin 11 output drive capability 22 2 ODRV10 GPIOx pin 10 output drive capability 20 2 ODRV9 GPIOx pin 9 output drive capability 18 2 ODRV8 GPIOx pin 8 output drive capability 16 2 ODRV7 GPIOx pin 7 output drive capability 14 2 ODRV6 GPIOx pin 6 output drive capability 12 2 ODRV5 GPIOx pin 5 output drive capability 10 2 ODRV4 GPIOx pin 4 output drive capability 8 2 ODRV3 GPIOx pin 3 output drive capability 6 2 ODRV2 GPIOx pin 2 output drive capability 4 2 ODRV1 GPIOx pin 1 output drive capability 2 2 ODRV0 GPIOx pin 0 output drive capability 0 2 PULL PULL GPIO pull-up/pull-down register 0xC 0x20 read-write 0x00000000 PULL15 GPIOx pin 15 pull configuration 30 2 PULL14 GPIOx pin 14 pull configuration 28 2 PULL13 GPIOx pin 13 pull configuration 26 2 PULL12 GPIOx pin 12 pull configuration 24 2 PULL11 GPIOx pin 11 pull configuration 22 2 PULL10 GPIOx pin 10 pull configuration 20 2 PULL9 GPIOx pin 9 pull configuration 18 2 PULL8 GPIOx pin 8 pull configuration 16 2 PULL7 GPIOx pin 7 pull configuration 14 2 PULL6 GPIOx pin 6 pull configuration 12 2 PULL5 GPIOx pin 5 pull configuration 10 2 PULL4 GPIOx pin 4 pull configuration 8 2 PULL3 GPIOx pin 3 pull configuration 6 2 PULL2 GPIOx pin 2 pull configuration 4 2 PULL1 GPIOx pin 1 pull configuration 2 2 PULL0 GPIOx pin 0 pull configuration 0 2 IDT IDT GPIO input data register 0x10 0x20 read-only 0x00000000 IDT0 Port input data 0 1 IDT1 Port input data 1 1 IDT2 Port input data 2 1 IDT3 Port input data 3 1 IDT4 Port input data 4 1 IDT5 Port input data 5 1 IDT6 Port input data 6 1 IDT7 Port input data 7 1 IDT8 Port input data 8 1 IDT9 Port input data 9 1 IDT10 Port input data 10 1 IDT11 Port input data 11 1 IDT12 Port input data 12 1 IDT13 Port input data 13 1 IDT14 Port input data 14 1 IDT15 Port input data 15 1 ODT ODT GPIO output data register 0x14 0x20 read-write 0x00000000 ODT0 Port output data 0 1 ODT1 Port output data 1 1 ODT2 Port output data 2 1 ODT3 Port output data 3 1 ODT4 Port output data 4 1 ODT5 Port output data 5 1 ODT6 Port output data 6 1 ODT7 Port output data 7 1 ODT8 Port output data 8 1 ODT9 Port output data 9 1 ODT10 Port output data 10 1 ODT11 Port output data 11 1 ODT12 Port output data 12 1 ODT13 Port output data 13 1 ODT14 Port output data 14 1 ODT15 Port output data 15 1 SCR SCR Port bit set/clear register 0x18 0x20 write-only 0x00000000 IOSB0 Set bit 0 0 1 IOSB1 Set bit 1 1 1 IOSB2 Set bit 1 2 1 IOSB3 Set bit 3 3 1 IOSB4 Set bit 4 4 1 IOSB5 Set bit 5 5 1 IOSB6 Set bit 6 6 1 IOSB7 Set bit 7 7 1 IOSB8 Set bit 8 8 1 IOSB9 Set bit 9 9 1 IOSB10 Set bit 10 10 1 IOSB11 Set bit 11 11 1 IOSB12 Set bit 12 12 1 IOSB13 Set bit 13 13 1 IOSB14 Set bit 14 14 1 IOSB15 Set bit 15 15 1 IOCB0 Clear bit 0 16 1 IOCB1 Clear bit 1 17 1 IOCB2 Clear bit 2 18 1 IOCB3 Clear bit 3 19 1 IOCB4 Clear bit 4 20 1 IOCB5 Clear bit 5 21 1 IOCB6 Clear bit 6 22 1 IOCB7 Clear bit 7 23 1 IOCB8 Clear bit 8 24 1 IOCB9 Clear bit 9 25 1 IOCB10 Clear bit 10 26 1 IOCB11 Clear bit 11 27 1 IOCB12 Clear bit 12 28 1 IOCB13 Clear bit 13 29 1 IOCB14 Clear bit 14 30 1 IOCB15 Clear bit 15 31 1 WPR WPR Port write protect register 0x1C 0x20 read-write 0x00000000 WPEN0 Write protect enable 0 0 1 WPEN1 Write protect enable 1 1 1 WPEN2 Write protect enable 2 2 1 WPEN3 Write protect enable 3 3 1 WPEN4 Write protect enable 4 4 1 WPEN5 Write protect enable 5 5 1 WPEN6 Write protect enable 6 6 1 WPEN7 Write protect enable 7 7 1 WPEN8 Write protect enable 8 8 1 WPEN9 Write protect enable 9 9 1 WPEN10 Write protect enable 10 10 1 WPEN11 Write protect enable 11 11 1 WPEN12 Write protect enable 12 12 1 WPEN13 Write protect enable 13 13 1 WPEN14 Write protect enable 14 14 1 WPEN15 Write protect enable 15 15 1 WPSEQ Write protect sequence 16 1 MUXL MUXL GPIO muxing function low register 0x20 0x20 read-write 0x00000000 MUXL7 GPIOx pin 7 muxing 28 4 MUXL6 GPIOx pin 6 muxing 24 4 MUXL5 GPIOx pin 5 muxing 20 4 MUXL4 GPIOx pin 4 muxing 16 4 MUXL3 GPIOx pin 3 muxing 12 4 MUXL2 GPIOx pin 2 muxing 8 4 MUXL1 GPIOx pin 1 muxing 4 4 MUXL0 GPIOx pin 0 muxing 0 4 MUXH MUXH GPIO muxing function high register 0x24 0x20 read-write 0x00000000 MUXH15 GPIOx pin 15 muxing 28 4 MUXH14 GPIOx pin 14 muxing 24 4 MUXH13 GPIOx pin 13 muxing 20 4 MUXH12 GPIOx pin 12 muxing 16 4 MUXH11 GPIOx pin 11 muxing 12 4 MUXH10 GPIOx pin 10 muxing 8 4 MUXH9 GPIOx pin 9 muxing 4 4 MUXH8 GPIOx pin 8 muxing 0 4 CLR CLR GPIO bit reset register 0x28 0x20 write-only 0x00000000 IOCB0 Clear bit 0 0 1 IOCB1 Clear bit 1 1 1 IOCB2 Clear bit 1 2 1 IOCB3 Clear bit 3 3 1 IOCB4 Clear bit 4 4 1 IOCB5 Clear bit 5 5 1 IOCB6 Clear bit 6 6 1 IOCB7 Clear bit 7 7 1 IOCB8 Clear bit 8 8 1 IOCB9 Clear bit 9 9 1 IOCB10 Clear bit 10 10 1 IOCB11 Clear bit 11 11 1 IOCB12 Clear bit 12 12 1 IOCB13 Clear bit 13 13 1 IOCB14 Clear bit 14 14 1 IOCB15 Clear bit 15 15 1 TOGR TOGR GPIO bit toggle register 0x2C 0x20 write-only 0x00000000 IOTB0 toggle bit 0 0 1 IOTB1 toggle bit 1 1 1 IOTB2 toggle bit 2 2 1 IOTB3 toggle bit 3 3 1 IOTB4 toggle bit 4 4 1 IOTB5 toggle bit 5 5 1 IOTB6 toggle bit 6 6 1 IOTB7 toggle bit 7 7 1 IOTB8 toggle bit 8 8 1 IOTB9 toggle bit 9 9 1 IOTB10 toggle bit 10 10 1 IOTB11 toggle bit 11 11 1 IOTB12 toggle bit 12 12 1 IOTB13 toggle bit 13 13 1 IOTB14 toggle bit 14 14 1 IOTB15 toggle bit 15 15 1 HDRV HDRV Huge current driver 0x3C 0x20 read-write 0x00000000 HDRV0 Port x driver bit y 0 1 HDRV1 Port x driver bit y 1 1 HDRV2 Port x driver bit y 2 1 HDRV3 Port x driver bit y 3 1 HDRV4 Port x driver bit y 4 1 HDRV5 Port x driver bit y 5 1 HDRV6 Port x driver bit y 6 1 HDRV7 Port x driver bit y 7 1 HDRV8 Port x driver bit y 8 1 HDRV9 Port x driver bit y 9 1 HDRV10 Port x driver bit y 10 1 HDRV11 Port x driver bit y 11 1 HDRV12 Port x driver bit y 12 1 HDRV13 Port x driver bit y 13 1 HDRV14 Port x driver bit y 14 1 HDRV15 Port x driver bit y 15 1 GPIOB 0x40020400 GPIOC 0x40020800 GPIOD 0x40020C00 GPIOF 0x40021400 EXINT EXINT EXINT 0x40013C00 0x0 0x400 registers EXINT0 EXINT Line0 interrupt 6 EXINT1 EXINT Line1 interrupt 7 EXINT2 EXINT Line2 interrupt 8 EXINT3 EXINT Line3 interrupt 9 EXINT4 EXINT Line4 interrupt 10 EXINT9_5 EXINT Line[9:5] interrupts 23 EXINT15_10 EXINT Line[15:10] interrupts 40 PVM PVM interrupt connect to EXINT line16 1 ERTCALARM ERTC Alarm interrupt connect to EXINT line17 41 OTGFS1_WKUP OTGFS1_WKUP interrupt connect to EXINT line18 42 OTGHS_WKUP OTGHS_WKUP interrupt connect to EXINT line20 76 TAMPER Tamper interrupt connect to EXINT line21 2 ERTC_WKUP ERTC Global interrupt connect to EXINT line22 3 INTEN INTEN Interrupt enable register 0x0 0x20 read-write 0x00000000 INTEN0 Interrupt enable or disable on line 0 0 1 INTEN1 Interrupt enable or disable on line 1 1 1 INTEN2 Interrupt enable or disable on line 2 2 1 INTEN3 Interrupt enable or disable on line 3 3 1 INTEN4 Interrupt enable or disable on line 4 4 1 INTEN5 Interrupt enable or disable on line 5 5 1 INTEN6 Interrupt enable or disable on line 6 6 1 INTEN7 Interrupt enable or disable on line 7 7 1 INTEN8 Interrupt enable or disable on line 8 8 1 INTEN9 Interrupt enable or disable on line 9 9 1 INTEN10 Interrupt enable or disable on line 10 10 1 INTEN11 Interrupt enable or disable on line 11 11 1 INTEN12 Interrupt enable or disable on line 12 12 1 INTEN13 Interrupt enable or disable on line 13 13 1 INTEN14 Interrupt enable or disable on line 14 14 1 INTEN15 Interrupt enable or disable on line 15 15 1 INTEN16 Interrupt enable or disable on line 16 16 1 INTEN17 Interrupt enable or disable on line 17 17 1 INTEN18 Interrupt enable or disable on line 18 18 1 INTEN19 Interrupt enable or disable on line 19 19 1 INTEN20 Interrupt enable or disable on line 20 20 1 INTEN21 Interrupt enable or disable on line 21 21 1 INTEN22 Interrupt enable or disable on line 22 22 1 EVTEN EVTEN Event enable register 0x4 0x20 read-write 0x00000000 EVTEN0 Event enable or disable on line 0 0 1 EVTEN1 Event enable or disable on line 1 1 1 EVTEN2 Event enable or disable on line 2 2 1 EVTEN3 Event enable or disable on line 3 3 1 EVTEN4 Event enable or disable on line 4 4 1 EVTEN5 Event enable or disable on line 5 5 1 EVTEN6 Event enable or disable on line 6 6 1 EVTEN7 Event enable or disable on line 7 7 1 EVTEN8 Event enable or disable on line 8 8 1 EVTEN9 Event enable or disable on line 9 9 1 EVTEN10 Event enable or disable on line 10 10 1 EVTEN11 Event enable or disable on line 11 11 1 EVTEN12 Event enable or disable on line 12 12 1 EVTEN13 Event enable or disable on line 13 13 1 EVTEN14 Event enable or disable on line 14 14 1 EVTEN15 Event enable or disable on line 15 15 1 EVTEN16 Event enable or disable on line 16 16 1 EVTEN17 Event enable or disable on line 17 17 1 EVTEN18 Event enable or disable on line 18 18 1 EVTEN19 Event enable or disable on line 19 19 1 EVTEN20 Event enable or disable on line 20 20 1 EVTEN21 Event enable or disable on line 21 21 1 EVTEN22 Event enable or disable on line 22 22 1 POLCFG1 POLCFG1 Rising polarity configuration register 0x8 0x20 read-write 0x00000000 RP0 Rising polarity configuration bit of line 0 0 1 RP1 Rising polarity configuration bit of line 1 1 1 RP2 Rising polarity configuration bit of line 2 2 1 RP3 Rising polarity configuration bit of line 3 3 1 RP4 Rising polarity configuration bit of line 4 4 1 RP5 Rising polarity configuration bit of line 5 5 1 RP6 Rising polarity configuration bit of linee 6 6 1 RP7 Rising polarity configuration bit of line 7 7 1 RP8 Rising polarity configuration bit of line 8 8 1 RP9 Rising polarity configuration bit of line 9 9 1 RP10 Rising polarity configuration bit of line 10 10 1 RP11 Rising polarity configuration bit of line 11 11 1 RP12 Rising polarity configuration bit of line 12 12 1 RP13 Rising polarity configuration bit of line 13 13 1 RP14 Rising polarity configuration bit of line 14 14 1 RP15 Rising polarity configuration bit of line 15 15 1 RP16 Rising polarity configuration bit of line 16 16 1 RP17 Rising polarity configuration bit of line 17 17 1 RP18 Rising polarity configuration bit of line 18 18 1 RP19 Rising polarity configuration bit of line 19 19 1 RP20 Rising polarity configuration bit of line 20 20 1 RP21 Rising polarity configuration bit of line 21 21 1 RP22 Rising polarity configuration bit of line 22 22 1 POLCFG2 POLCFG2 Falling polarity configuration register 0xC 0x20 read-write 0x00000000 FP0 Falling polarity event configuration bit of line 0 0 1 FP1 Falling polarity event configuration bit of line 1 1 1 FP2 Falling polarity event configuration bit of line 2 2 1 FP3 Falling polarity event configuration bit of line 3 3 1 FP4 Falling polarity event configuration bit of line 4 4 1 FP5 Falling polarity event configuration bit of line 5 5 1 FP6 Falling polarity event configuration bit of line 6 6 1 FP7 Falling polarity event configuration bit of line 7 7 1 FP8 Falling polarity event configuration bit of line 8 8 1 FP9 Falling polarity event configuration bit of line 9 9 1 FP10 Falling polarity event configuration bit of line 10 10 1 FP11 Falling polarity event configuration bit of line 11 11 1 FP12 Falling polarity event configuration bit of line 12 12 1 FP13 Falling polarity event configuration bit of line 13 13 1 FP14 Falling polarity event configuration bit of line 14 14 1 FP15 Falling polarity event configuration bit of line 15 15 1 FP16 Falling polarity event configuration bit of line 16 16 1 FP17 Falling polarity event configuration bit of line 17 17 1 FP18 Falling polarity event configuration bit of line 18 18 1 FP19 Falling polarity event configuration bit of line 19 19 1 FP20 Falling polarity event configuration bit of line 20 20 1 FP21 Falling polarity event configuration bit of line 21 21 1 FP22 Falling polarity event configuration bit of line 22 22 1 SWTRG SWTRG Software triggle register 0x10 0x20 read-write 0x00000000 SWT0 Software triggle on line 0 0 1 SWT1 Software triggle on line 1 1 1 SWT2 Software triggle on line 2 2 1 SWT3 Software triggle on line 3 3 1 SWT4 Software triggle on line 4 4 1 SWT5 Software triggle on line 5 5 1 SWT6 Software triggle on line 6 6 1 SWT7 Software triggle on line 7 7 1 SWT8 Software triggle on line 8 8 1 SWT9 Software triggle on line 9 9 1 SWT10 Software triggle on line 10 10 1 SWT11 Software triggle on line 11 11 1 SWT12 Software triggle on line 12 12 1 SWT13 Software triggle on line 13 13 1 SWT14 Software triggle on line 14 14 1 SWT15 Software triggle on line 15 15 1 SWT16 Software triggle on line 16 16 1 SWT17 Software triggle on line 17 17 1 SWT18 Software triggle on line 18 18 1 SWT19 Software triggle on line 19 19 1 SWT20 Software triggle on line 20 20 1 SWT21 Software triggle on line 21 21 1 SWT22 Software triggle on line 22 22 1 INTSTS INTSTS Interrupt status register 0x14 0x20 read-write 0x00000000 LINE0 Line 0 state bit 0 1 LINE1 Line 1 state bit 1 1 LINE2 Line 2 state bit 2 1 LINE3 Line 3 state bit 3 1 LINE4 Line 4 state bit 4 1 LINE5 Line 5 state bit 5 1 LINE6 Line 6 state bit 6 1 LINE7 Line 7 state bit 7 1 LINE8 Line 8 state bit 8 1 LINE9 Line 9 state bit 9 1 LINE10 Line 10 state bit 10 1 LINE11 Line 11 state bit 11 1 LINE12 Line 12 state bit 12 1 LINE13 Line 13 state bit 13 1 LINE14 Line 14 state bit 14 1 LINE15 Line 15 state bit 15 1 LINE16 Line 16 state bit 16 1 LINE17 Line 17 state bit 17 1 LINE18 Line 18 state bit 18 1 LINE19 Line 19 state bit 19 1 LINE20 Line 20 state bit 20 1 LINE21 Line 21 state bit 21 1 LINE22 Line 22 state bit 22 1 DMA1 DMA controller DMA 0x40026000 0x0 0x200 registers DMA1_Channel1 DMA1 Channel1 global interrupt 11 DMA1_Channel2 DMA1 Channel2 global interrupt 12 DMA1_Channel3 DMA1 Channel3 global interrupt 13 DMA1_Channel4 DMA1 Channel4 global interrupt 14 DMA1_Channel5 DMA1 Channel5 global interrupt 15 DMA1_Channel6 DMA1 Channel6 global interrupt 16 DMA1_Channel7 DMA1 Channel7 global interrupt 17 STS STS DMA interrupt status register (DMA_STS) 0x0 0x20 read-only 0x00000000 GF1 Channel 1 Global event flag 0 1 FDTF1 Channel 1 full data transfer event flag 1 1 HDTF1 Channel 1 half data transfer event flag 2 1 DTERRF1 Channel 1 data transfer error event flag 3 1 GF2 Channel 2 Global event flag 4 1 FDTF2 Channel 2 full data transfer event flag 5 1 HDTF2 Channel 2 half data transfer event flag 6 1 DTERRF2 Channel 2 data transfer error event flag 7 1 GF3 Channel 3 Global event flag 8 1 FDTF3 Channel 3 full data transfer event flag 9 1 HDTF3 Channel 3 half data transfer event flag 10 1 DTERRF3 Channel 3 data transfer error event flag 11 1 GF4 Channel 4 Global event flag 12 1 FDTF4 Channel 4 full data transfer event flag 13 1 HDTF4 Channel 4 half data transfer event flag 14 1 DTERRF4 Channel 4 data transfer error event flag 15 1 GF5 Channel 5 Global event flag 16 1 FDTF5 Channel 5 full data transfer event flag 17 1 HDTF5 Channel 5 half data transfer event flag 18 1 DTERRF5 Channel 5 data transfer error event flag 19 1 GF6 Channel 6 Global event flag 20 1 FDTF6 Channel 6 full data transfer event flag 21 1 HDTF6 Channel 6 half data transfer event flag 22 1 DTERRF6 Channel 6 data transfer error event flag 23 1 GF7 Channel 7 Global event flag 24 1 FDTF7 Channel 7 full data transfer event flag 25 1 HDTF7 Channel 7 half data transfer event flag 26 1 DTERRF7 Channel 7 data transfer error event flag 27 1 CLR CLR DMA interrupt flag clear register (DMA_CLR) 0x4 0x20 read-write 0x00000000 GFC1 Channel 1 Global flag clear 0 1 GFC2 Channel 2 Global flag clear 4 1 GFC3 Channel 3 Global flag clear 8 1 GFC4 Channel 4 Global flag clear 12 1 GFC5 Channel 5 Global flag clear 16 1 GFC6 Channel 6 Global flag clear 20 1 GFC7 Channel 7 Global flag clear 24 1 FDTFC1 Channel 1 full data transfer flag clear 1 1 FDTFC2 Channel 2 full data transfer flag clear 5 1 FDTFC3 Channel 3 full data transfer flag clear 9 1 FDTFC4 Channel 4 full data transfer flag clear 13 1 FDTFC5 Channel 5 full data transfer flag clear 17 1 FDTFC6 Channel 6 full data transfer flag clear 21 1 FDTFC7 Channel 7 full data transfer flag clear 25 1 HDTFC1 Channel 1 half data transfer flag clear 2 1 HDTFC2 Channel 2 half data transfer flag clear 6 1 HDTFC3 Channel 3 half data transfer flag clear 10 1 HDTFC4 Channel 4 half data transfer flag clear 14 1 HDTFC5 Channel 5 half data transfer flag clear 18 1 HDTFC6 Channel 6 half data transfer flag clear 22 1 HDTFC7 Channel 7 half data transfer flag clear 26 1 DTERRFC1 Channel 1 data transfer error flag clear 3 1 DTERRFC2 Channel 2 data transfer error flag clear 7 1 DTERRFC3 Channel 3 data transfer error flag clear 11 1 DTERRFC4 Channel 4 data transfer error flag clear 15 1 DTERRFC5 Channel 5 data transfer error flag clear 19 1 DTERRFC6 Channel 6 data transfer error flag clear 23 1 DTERRFC7 Channel 7 data transfer error flag clear 27 1 C1CTRL C1CTRL DMA channel configuration register(DMA_C1CTRL) 0x8 0x20 read-write 0x00000000 CHEN Channel enable 0 1 FDTIEN Transfer complete interrupt enable 1 1 HDTIEN Half transfer interrupt enable 2 1 DTERRIEN Transfer error interrupt enable 3 1 DTD Data transfer direction 4 1 LM Loop mode 5 1 PINCM Peripheral increment mode 6 1 MINCM Memory increment mode 7 1 PWIDTH Peripheral data bit width 8 2 MWIDTH Memory data bit width 10 2 CHPL Channel Priority level 12 2 M2M Memory to memory mode 14 1 C1DTCNT C1DTCNT DMA channel 1 number of data to transfer register 0xC 0x20 read-write 0x00000000 CNT Number of data to transfer 0 16 C1PADDR C1PADDR DMA channel 1 peripheral base address register 0x10 0x20 read-write 0x00000000 PADDR Peripheral address 0 32 C1MADDR C1MADDR DMA channel 1 memory base address register 0x14 0x20 read-write 0x00000000 MADDR Memory address 0 32 C2CTRL C2CTRL DMA channel configuration register (DMA_C2CTRL) 0x1C 0x20 read-write 0x00000000 CHEN Channel enable 0 1 FDTIEN Transfer complete interrupt enable 1 1 HDTIEN Half transfer interrupt enable 2 1 DTERRIEN Transfer error interrupt enable 3 1 DTD Data transfer direction 4 1 LM Loop mode 5 1 PINCM Peripheral increment mode 6 1 MINCM Memory increment mode 7 1 PWIDTH Peripheral data bit width 8 2 MWIDTH Memory data bit width 10 2 CHPL Channel Priority level 12 2 M2M Memory to memory mode 14 1 C2DTCNT C2DTCNT DMA channel 2 number of data to transferregister 0x20 0x20 read-write 0x00000000 CNT Number of data to transfer 0 16 C2PADDR C2PADDR DMA channel 2 peripheral base address register 0x24 0x20 read-write 0x00000000 PADDR Peripheral address 0 32 C2MADDR C2MADDR DMA channel 2 memory base address register 0x28 0x20 read-write 0x00000000 MADDR Memory address 0 32 C3CTRL C3CTRL DMA channel configuration register (DMA_C3CTRL) 0x30 0x20 read-write 0x00000000 CHEN Channel enable 0 1 FDTIEN Transfer complete interrupt enable 1 1 HDTIEN Half transfer interrupt enable 2 1 DTERRIEN Transfer error interrupt enable 3 1 DTD Data transfer direction 4 1 LM Loop mode 5 1 PINCM Peripheral increment mode 6 1 MINCM Memory increment mode 7 1 PWIDTH Peripheral data bit width 8 2 MWIDTH Memory data bit width 10 2 CHPL Channel Priority level 12 2 M2M Memory to memory mode 14 1 C3DTCNT C3DTCNT DMA channel 3 number of data to transfer register 0x34 0x20 read-write 0x00000000 CNT Number of data to transfer 0 16 C3PADDR C3PADDR DMA channel 3 peripheral base address register 0x38 0x20 read-write 0x00000000 PADDR Peripheral address 0 32 C3MADDR C3MADDR DMA channel 3 memory base address register 0x3C 0x20 read-write 0x00000000 MADDR Memory address 0 32 C4CTRL C4CTRL DMA channel configuration register (DMA_C4CTRL) 0x44 0x20 read-write 0x00000000 CHEN Channel enable 0 1 FDTIEN Transfer complete interrupt enable 1 1 HDTIEN Half transfer interrupt enable 2 1 DTERRIEN Transfer error interrupt enable 3 1 DTD Data transfer direction 4 1 LM Loop mode 5 1 PINCM Peripheral increment mode 6 1 MINCM Memory increment mode 7 1 PWIDTH Peripheral data bit width 8 2 MWIDTH Memory data bit width 10 2 CHPL Channel Priority level 12 2 M2M Memory to memory mode 14 1 C4DTCNT C4DTCNT DMA channel 4 number of data to transfer register 0x48 0x20 read-write 0x00000000 CNT Number of data to transfer 0 16 C4PADDR C4PADDR DMA channel 4 peripheral base address register 0x4C 0x20 read-write 0x00000000 PADDR Peripheral address 0 32 C4MADDR C4MADDR DMA channel 4 memory base address register 0x50 0x20 read-write 0x00000000 MADDR Memory address 0 32 C5CTRL C5CTRL DMA channel configuration register (DMA_C5CTRL) 0x58 0x20 read-write 0x00000000 CHEN Channel enable 0 1 FDTIEN Transfer complete interrupt enable 1 1 HDTIEN Half transfer interrupt enable 2 1 DTERRIEN Transfer error interrupt enable 3 1 DTD Data transfer direction 4 1 LM Loop mode 5 1 PINCM Peripheral increment mode 6 1 MINCM Memory increment mode 7 1 PWIDTH Peripheral data bit width 8 2 MWIDTH Memory data bit width 10 2 CHPL Channel Priority level 12 2 M2M Memory to memory mode 14 1 C5DTCNT C5DTCNT DMA channel 5 number of data to transfer register 0x5C 0x20 read-write 0x00000000 CNT Number of data to transfer 0 16 C5PADDR C5PADDR DMA channel 5 peripheral base address register 0x60 0x20 read-write 0x00000000 PADDR Peripheral address 0 32 C5MADDR C5MADDR DMA channel 5 memory base address register 0x64 0x20 read-write 0x00000000 MADDR Memory address 0 32 C6CTRL C6CTRL DMA channel configuration register(DMA_C6CTRL) 0x6C 0x20 read-write 0x00000000 CHEN Channel enable 0 1 FDTIEN Transfer complete interrupt enable 1 1 HDTIEN Half transfer interrupt enable 2 1 DTERRIEN Transfer error interrupt enable 3 1 DTD Data transfer direction 4 1 LM Loop mode 5 1 PINCM Peripheral increment mode 6 1 MINCM Memory increment mode 7 1 PWIDTH Peripheral data bit width 8 2 MWIDTH Memory data bit width 10 2 CHPL Channel Priority level 12 2 M2M Memory to memory mode 14 1 C6DTCNT C6DTCNT DMA channel 6 number of data to transfer register 0x70 0x20 read-write 0x00000000 CNT Number of data to transfer 0 16 C6PADDR C6PADDR DMA channel 6 peripheral address base register 0x74 0x20 read-write 0x00000000 PADDR Peripheral address 0 32 C6MADDR C6MADDR DMA channel 6 memory address base register 0x78 0x20 read-write 0x00000000 MADDR Memory address 0 32 C7CTRL C7CTRL DMA channel configuration register(DMA_C7CTRL) 0x80 0x20 read-write 0x00000000 CHEN Channel enable 0 1 FDTIEN Transfer complete interrupt enable 1 1 HDTIEN Half transfer interrupt enable 2 1 DTERRIEN Transfer error interrupt enable 3 1 DTD Data transfer direction 4 1 LM Loop mode 5 1 PINCM Peripheral increment mode 6 1 MINCM Memory increment mode 7 1 PWIDTH Peripheral data bit width 8 2 MWIDTH Memory data bit width 10 2 CHPL Channel Priority level 12 2 M2M Memory to memory mode 14 1 C7DTCNT C7DTCNT DMA channel 7 number of data to transfer register 0x84 0x20 read-write 0x00000000 CNT Number of data to transfer 0 16 C7PADDR C7PADDR DMA channel 7 peripheral base address register 0x88 0x20 read-write 0x00000000 PADDR Peripheral address 0 32 C7MADDR C7MADDR DMA channel 7 memory base address register 0x8C 0x20 read-write 0x00000000 MADDR Memory address 0 32 DMA_MUXSEL DMA_MUXSEL DMAMUX Table Selection 0x100 0x20 0x00000000 TBL_SEL Multiplexer Table Select 0 1 read-write MUXC1CTRL MUXC1CTRL Channel 1 Configuration Register 0x104 0x20 0x00000000 REQSEL DMA request select 0 7 read-write SYNCOVIEN Synchronization overrun interrupt enable 8 1 read-write EVTGEN Event generation enable 9 1 read-write SYNCEN Synchroniztion enable 16 1 read-write SYNCPOL Synchronization polarity 17 2 read-write REQCNT Number of DMA requests 19 5 read-write SYNCSEL Synchronization Identification 24 5 read-write MUXC2CTRL MUXC2CTRL Channel 2 Configuration Register 0x108 0x20 0x00000000 REQSEL DMA request select 0 7 read-write SYNCOVIEN Synchronization overrun interrupt enable 8 1 read-write EVTGEN Event generation enable 9 1 read-write SYNCEN Synchroniztion enable 16 1 read-write SYNCPOL Synchronization polarity 17 2 read-write REQCNT Number of DMA requests 19 5 read-write SYNCSEL Synchronization Identification 24 5 read-write MUXC3CTRL MUXC3CTRL Channel 3 Configuration Register 0x10C 0x20 0x00000000 REQSEL DMA request select 0 7 read-write SYNCOVIEN Synchronization overrun interrupt enable 8 1 read-write EVTGEN Event generation enable 9 1 read-write SYNCEN Synchroniztion enable 16 1 read-write SYNCPOL Synchronization polarity 17 2 read-write REQCNT Number of DMA requests 19 5 read-write SYNCSEL Synchronization Identification 24 5 read-write MUXC4CTRL MUXC4CTRL Channel 4 Configuration Register 0x110 0x20 0x00000000 REQSEL DMA request select 0 7 read-write SYNCOVIEN Synchronization overrun interrupt enable 8 1 read-write EVTGEN Event generation enable 9 1 read-write SYNCEN Synchroniztion enable 16 1 read-write SYNCPOL Synchronization polarity 17 2 read-write REQCNT Number of DMA requests 19 5 read-write SYNCSEL Synchronization Identification 24 5 read-write MUXC5CTRL MUXC5CTRL Channel 5 Configuration Register 0x114 0x20 0x00000000 REQSEL DMA request select 0 7 read-write SYNCOVIEN Synchronization overrun interrupt enable 8 1 read-write EVTGEN Event generation enable 9 1 read-write SYNCEN Synchroniztion enable 16 1 read-write SYNCPOL Synchronization polarity 17 2 read-write REQCNT Number of DMA requests 19 5 read-write SYNCSEL Synchronization Identification 24 5 read-write MUXC6CTRL MUXC6CTRL Channel 6 Configuration Register 0x118 0x20 0x00000000 REQSEL DMA request select 0 7 read-write SYNCOVIEN Synchronization overrun interrupt enable 8 1 read-write EVTGEN Event generation enable 9 1 read-write SYNCEN Synchroniztion enable 16 1 read-write SYNCPOL Synchronization polarity 17 2 read-write REQCNT Number of DMA requests 19 5 read-write SYNCSEL Synchronization Identification 24 5 read-write MUXC7CTRL MUXC7CTRL Channel 7 Configuration Register 0x11C 0x20 0x00000000 REQSEL DMA request select 0 7 read-write SYNCOVIEN Synchronization overrun interrupt enable 8 1 read-write EVTGEN Event generation enable 9 1 read-write SYNCEN Synchroniztion enable 16 1 read-write SYNCPOL Synchronization polarity 17 2 read-write REQCNT Number of DMA requests 19 5 read-write SYNCSEL Synchronization Identification 24 5 read-write MUXG1CTRL MUXG1CTRL Generator 1 Configuration Register 0x120 0x20 0x00000000 SIGSEL Signal select 0 5 read-write TRGOVIEN Trigger overrun interrupt enable 8 1 read-write GEN DMA request generator enable 16 1 read-write GPOL DMA request generator trigger polarity 17 2 read-write GREQCNT Number of DMA requests to be generated 19 5 read-write MUXG2CTRL MUXG2CTRL Generator 2 Configuration Register 0x124 0x20 0x00000000 SIGSEL Signal select 0 5 read-write TRGOVIEN Trigger overrun interrupt enable 8 1 read-write GEN DMA request generator enable 16 1 read-write GPOL DMA request generator trigger polarity 17 2 read-write GREQCNT Number of DMA requests to be generated 19 5 read-write MUXG3CTRL MUXG3CTRL Generator 3 Configuration Register 0x128 0x20 0x00000000 SIGSEL Signal select 0 5 read-write TRGOVIEN Trigger overrun interrupt enable 8 1 read-write GEN DMA request generator enable 16 1 read-write GPOL DMA request generator trigger polarity 17 2 read-write GREQCNT Number of DMA requests to be generated 19 5 read-write MUXG4CTRL MUXG4CTRL Generator 4 Configuration Register 0x12C 0x20 0x00000000 SIGSEL Signal select 0 5 read-write TRGOVIEN Trigger overrun interrupt enable 8 1 read-write GEN DMA request generator enable 16 1 read-write GPOL DMA request generator trigger polarity 17 2 read-write GREQCNT Number of DMA requests to be generated 19 5 read-write MUXSYNCSTS MUXSYNCSTS Channel Interrupt Status Register 0x130 0x20 0x00000000 SYNCOVF1 Synchronizaton overrun interrupt flag 0 1 read-only SYNCOVF2 Synchronizaton overrun interrupt flag 1 1 read-only SYNCOVF3 Synchronizaton overrun interrupt flag 2 1 read-only SYNCOVF4 Synchronizaton overrun interrupt flag 3 1 read-only SYNCOVF5 Synchronizaton overrun interrupt flag 4 1 read-only SYNCOVF6 Synchronizaton overrun interrupt flag 5 1 read-only SYNCOVF7 Synchronizaton overrun interrupt flag 6 1 read-only MUXSYNCCLR MUXSYNCCLR Channel Interrupt Clear Flag Register 0x134 0x20 0x00000000 SYNCOVFC1 Clear synchronizaton overrun interrupt flag 0 1 read-write SYNCOVFC2 Clear synchronizaton overrun interrupt flag 1 1 read-write SYNCOVFC3 Clear synchronizaton overrun interrupt flag 2 1 read-write SYNCOVFC4 Clear synchronizaton overrun interrupt flag 3 1 read-write SYNCOVFC5 Clear synchronizaton overrun interrupt flag 4 1 read-write SYNCOVFC6 Clear synchronizaton overrun interrupt flag 5 1 read-write SYNCOVFC7 Clear synchronizaton overrun interrupt flag 6 1 read-write MUXGSTS MUXGSTS Generator Interrupt Status Register 0x138 0x20 0x00000000 TRGOVF1 Trigger overrun interrupt flag 0 1 read-write TRGOVF2 Trigger overrun interrupt flag 1 1 read-write TRGOVF3 Trigger overrun interrupt flag 2 1 read-write TRGOVF4 Trigger overrun interrupt flag 3 1 read-write MUXGCLR MUXGCLR Generator Interrupt Clear Flag Register 0x13C 0x20 0x00000000 TRGOVFC1 Clear trigger overrun interrupt flag 0 1 read-write TRGOVFC2 Clear trigger overrun interrupt flag 1 1 read-write TRGOVFC3 Clear trigger overrun interrupt flag 2 1 read-write TRGOVFC4 Clear trigger overrun interrupt flag 3 1 read-write DMA2 0x40026400 SDIO1 Secure digital input/output interface SDIO 0x4002C400 0x0 0x400 registers SDIO1 SDIO1 global interrupt 49 PWRCTRL PWRCTRL Bits 1:0 = PWRCTRL: Power supply control bits 0x0 0x20 read-write 0x00000000 PS Power switch 0 2 CLKCTRL CLKCTRL SD clock control register (SDIO_CLKCTRL) 0x4 0x20 read-write 0x00000000 CLKDIV Clock division 0 8 CLKOEN Clock output enable 8 1 PWRSVEN Power saving mode enable 9 1 BYPSEN Clock divider bypass enable bit 10 1 BUSWS Bus width selection 11 2 CLKEDS SDIO_CK edge selection bit 13 1 HFCEN Hardware flow control enable 14 1 CLKDIV98 Clock divide factor bit9 and bit8 15 2 ARGU ARGU Bits 31:0 = : Command argument 0x8 0x20 read-write 0x00000000 ARGU Command argument 0 32 CMDCTRL CMDCTRL SDIO command control register (SDIO_CMDCTRL) 0xC 0x20 read-write 0x00000000 CMDIDX CMDIDX 0 6 RSPWT Wait for response 6 2 INTWT CCSM wait for interrupt 8 1 PNDWT CCSM wait for end of transfer 9 1 CCSMEN Command channel state machine 10 1 IOSUSP SD I/O suspend command 11 1 RSPCMD RSPCMD SDIO command register 0x10 0x20 read-only 0x00000000 RSPCMD RSPCMD 0 6 RSP1 RSP1 Bits 31:0 = CARDSTATUS1 0x14 0x20 read-only 0x00000000 CARDSTS1 CARDSTATUS1 0 32 RSP2 RSP2 Bits 31:0 = CARDSTATUS2 0x18 0x20 read-only 0x00000000 CARDSTS2 CARDSTATUS2 0 32 RSP3 RSP3 Bits 31:0 = CARDSTATUS3 0x1C 0x20 read-only 0x00000000 CARDSTS2 CARDSTATUS3 0 32 RSP4 RSP4 Bits 31:0 = CARDSTATUS4 0x20 0x20 read-only 0x00000000 CARDSTS2 CARDSTATUS4 0 32 DTTMR DTTMR Bits 31:0 = TIMEOUT: Data timeout period 0x24 0x20 read-write 0x00000000 TIMEOUT Data timeout period 0 32 DTLEN DTLEN Bits 24:0 = DATALENGTH: Data length value 0x28 0x20 read-write 0x00000000 DTLEN Data length value 0 25 DTCTRL DTCTRL SDIO data control register (SDIO_DCTRL) 0x2C 0x20 read-write 0x00000000 TFREN DTEN 0 1 TFRDIR DTDIR 1 1 TFRMODE DTMODE 2 1 DMAEN DMAEN 3 1 BLKSIZE DBLOCKSIZE 4 4 RDWTSTART PWSTART 8 1 RDWTSTOP PWSTOP 9 1 RDWTMODE RWMOD 10 1 IOEN SD I/O function enable 11 1 DTCNT DTCNT Bits 24:0 = DATACOUNT: Data count value 0x30 0x20 read-only 0x00000000 CNT Data count value 0 25 STS STS SDIO status register (SDIO_STA) 0x34 0x20 read-only 0x00000000 CMDFAIL Command crc fail 0 1 DTFAIL Data crc fail 1 1 CMDTIMEOUT Command timeout 2 1 DTTIMEOUT Data timeout 3 1 TXERRU Tx under run error 4 1 RXERRO Rx over run error 5 1 CMDRSPCMPL Command response complete 6 1 CMDCMPL Command sent 7 1 DTCMPL Data sent 8 1 SBITERR Start bit error 9 1 DTBLKCMPL Data block sent 10 1 DOCMD Command transfer in progress 11 1 DOTX Data transmit in progress 12 1 DORX Data receive in progress 13 1 TXBUFH Tx buffer half empty 14 1 RXBUFH Rx buffer half empty 15 1 TXBUFF Tx buffer full 16 1 RXBUFF Rx buffer full 17 1 TXBUFE Tx buffer empty 18 1 RXBUFE Rx buffer empty 19 1 TXBUF Tx data vaild 20 1 RXBUF Rx data vaild 21 1 IOIF SD I/O interrupt 22 1 INTCLR INTCLR SDIO interrupt clear register (SDIO_INTCLR) 0x38 0x20 read-write 0x00000000 CMDFAIL Command crc fail flag clear 0 1 DTFAIL Data crc fail flag clear 1 1 CMDTIMEOUT Command timeout flag clear 2 1 DTTIMEOUT Data timeout flag clear 3 1 TXERRU Tx under run error flag clear 4 1 RXERRU Rx over run error flag clear 5 1 CMDRSPCMPL Command response complete flag clear 6 1 CMDCMPL Command sent flag clear 7 1 DTCMPL Data sent flag clear 8 1 SBITERR Start bit error flag clear 9 1 DTBLKCMPL Data block sent clear 10 1 IOIF SD I/O interrupt flag clear 22 1 INTEN INTEN SDIO mask register (SDIO_MASK) 0x3C 0x20 read-write 0x00000000 CMDFAILIEN Command crc fail interrupt enable 0 1 DTFAILIEN Data crc fail interrupt enable 1 1 CMDTIMEOUTIEN Command timeout interrupt enable 2 1 DTTIMEOUTIEN Data timeout interrupt enable 3 1 TXERRUIEN Tx under run interrupt enable 4 1 RXERRUIEN Rx over run interrupt enable 5 1 CMDRSPCMPLIEN Command response complete interrupt enable 6 1 CMDCMPLIEN Command sent complete interrupt enable 7 1 DTCMPLIEN Data sent complete interrupt enable 8 1 SBITERRIEN Start bit error interrupt enable 9 1 DTBLKCMPLIEN Data block sent complete interrupt enable 10 1 DOCMDIEN Command acting interrupt enable 11 1 DOTXIEN Data transmit acting interrupt enable 12 1 DORXIEN Data receive acting interrupt enable 13 1 TXBUFHIEN Tx buffer half empty interrupt enable 14 1 RXBUFHIEN Rx buffer half empty interrupt enable 15 1 TXBUFFIEN Tx buffer full interrupt enable 16 1 RXBUFFIEN Rx buffer full interrupt enable 17 1 TXBUFEIEN Tx buffer empty interrupt enable 18 1 RXBUFEIEN Rx buffer empty interrupt enable 19 1 TXBUFIEN Tx buffer data vaild interrupt enable 20 1 RXBUFIEN Rx buffer data vaild interrupt enable 21 1 IOIFIEN SD I/O interrupt enable 22 1 BUFCNT BUFCNT Bits 23:0 = BUFCOUNT: Remaining number of words to be written to or read from the FIFO 0x48 0x20 read-only 0x00000000 CNT FIF0COUNT 0 24 BUF BUF bits 31:0 = Buffer Data: Receive and transmit buffer data 0x80 0x20 read-write 0x00000000 DT Buffer data 0 32 SDIO2 0x50061000 SDIO2 SDIO2 global interrupt 102 ERTC Real-time clock ERTC 0x40002800 0x0 0x400 registers TIME TIME time register 0x0 0x20 read-write 0x00000000 AMPM AM/PM notation 22 1 HT Hour tens 20 2 HU Hour units 16 4 MT Minute tens 12 3 MU Minute units 8 4 ST Second tens 4 3 SU Second units 0 4 DATE DATE date register 0x4 0x20 read-write 0x00002101 YT Year tens 20 4 YU Year units 16 4 WK Week 13 3 MT Month tens 12 1 MU Month units 8 4 DT Date tens 4 2 DU Date units 0 4 CTRL CTRL control register 0x8 0x20 read-write 0x00000000 CALOEN Calibration output enable 23 1 OUTSEL Output source selection 21 2 OUTP Output polarity 20 1 CALOSEL Calibration output selection 19 1 BPR Battery power domain data register 18 1 DEC1H Decrease 1 hour 17 1 ADD1H Add 1 hour 16 1 TSIEN Timestamp interrupt enable 15 1 WATIEN Wakeup timer interrupt enable 14 1 ALBIEN Alarm B interrupt enable 13 1 ALAIEN Alarm A interrupt enable 12 1 TSEN Timestamp enable 11 1 WATEN Wakeup timer enable 10 1 ALBEN Alarm B enable 9 1 ALAEN Alarm A enable 8 1 CCALEN Coarse calibration enable 7 1 HM Hour mode 6 1 DREN Date/time register direct read enable 5 1 RCDEN Reference clock detection enable 4 1 TSEDG Timestamp trigger edge 3 1 WATCLK Wakeup timer clock selection 0 3 STS STS initialization and status register 0xC 0x20 0x00000007 ALAWF Alarm A register allows write flag 0 1 read-only ALBWF Alarm B register allows write flag 1 1 read-only WATWF Wakeup timer register allows write flag 2 1 read-only TADJF Time adjustment flag 3 1 read-write INITF Calendar initialization flag 4 1 read-only UPDF Calendar update flag 5 1 read-write IMF Enter initialization mode flag 6 1 read-only IMEN Initialization mode enable 7 1 read-write ALAF Alarm A flag 8 1 read-write ALBF Alarm B flag 9 1 read-write WATF Wakeup timer flag 10 1 read-write TSF Timestamp flag 11 1 read-write TSOF Timestamp overflow flag 12 1 read-write TP1F Tamper detection 1 flag 13 1 read-write TP2F Tamper detection 2 flag 14 1 read-write CALUPDF Calibration value update completed flag 16 1 read-only DIV DIV Diveder register 0x10 0x20 read-write 0x007F00FF DIVA Diveder A 16 7 DIVB Diveder B 0 15 WAT WAT Wakeup timer register 0x14 0x20 read-write 0x0000FFFF VAL Wakeup timer reload value 0 16 CCAL CCAL Calibration register 0x18 0x20 read-write 0x00000000 CALDIR Calibration direction 7 1 CALVAL Calibration value 0 5 ALA ALA Alarm A register 0x1C 0x20 read-write 0x00000000 MASK4 Date/week mask 31 1 WKSEL Date/week mode select 30 1 DT Date tens 28 2 DU Date units 24 4 MASK3 Hours mask 23 1 AMPM AM/PM 22 1 HT Hour tens 20 2 HU Hour units 16 4 MASK2 Minutes mask 15 1 MT Minute tens 12 3 MU Minute units 8 4 MASK1 Seconds mask 7 1 ST Second tens 4 3 SU Second units 0 4 ALB ALB Alarm B register 0x20 0x20 read-write 0x00000000 MASK4 Date/week mask 31 1 WKSEL Date/week mode select 30 1 DT Date tens 28 2 DU Date units 24 4 MASK3 Hours mask 23 1 AMPM AM/PM 22 1 HT Hour tens 20 2 HU Hour units 16 4 MASK2 Minutes mask 15 1 MT Minute tens 12 3 MU Minute units 8 4 MASK1 Seconds mask 7 1 ST Second tens 4 3 SU Second units 0 4 WP WP write protection register 0x24 0x20 write-only 0x00000000 CMD Command register 0 8 SBS SBS sub second register 0x28 0x20 read-only 0x00000000 SBS Sub second value 0 16 TADJ TADJ time adjust register 0x2C 0x20 write-only 0x00000000 ADD1S Add 1 second 31 1 DECSBS Decrease sub-second value 0 15 TSTM TSTM time stamp time register 0x30 0x20 read-only 0x00000000 AMPM AMPM 22 1 HT Hour tens 20 2 HU Hour units 16 4 MT Minute tens 12 3 MU Minute units 8 4 ST Second tens 4 3 SU Second units 0 4 TSDT TSDT timestamp date register 0x34 0x20 read-only 0x00000000 WK Week 13 3 MT Month tens 12 1 MU Month units 8 4 DT Date tens 4 2 DU Date units 0 4 TSSBS TSSBS timestamp sub second register 0x38 0x20 read-only 0x00000000 SBS Sub second value 0 16 SCAL SCAL calibration register 0x3C 0x20 read-write 0x00000000 ADD Add ERTC clock 15 1 CAL8 8-second calibration period 14 1 CAL16 16 second calibration period 13 1 DEC Decrease ERTC clock 0 9 TAMP TAMP tamper and alternate function configuration register 0x40 0x20 read-write 0x00000000 OUTTYPE Output type 18 1 TSPIN Time stamp detection pin selection 17 1 TP1PIN Tamper detection pin selection 16 1 TPPU Tamper detection pull-up 15 1 TPPR Tamper detection pre-charge time 13 2 TPFLT Tamper detection filter time 11 2 TPFREQ Tamper detection frequency 8 3 TPTSEN Tamper detection timestamp enable 7 1 TP2EDG Tamper detection 2 valid edge 4 1 TP2EN Tamper detection 2 enable 3 1 TPIEN Tamper detection interrupt enable 2 1 TP1EDG Tamper detection 1 valid edge 1 1 TP1EN Tamper detection 1 enable 0 1 ALASBS ALASBS alarm A sub second register 0x44 0x20 read-write 0x00000000 SBSMSK Sub-second mask 24 4 SBS Sub-seconds value 0 15 ALBSBS ALBSBS alarm B sub second register 0x48 0x20 read-write 0x00000000 SBSMSK Sub-second mask 24 4 SBS Sub-seconds value 0 15 BPR1DT BPR1DT Battery powered domain register 0x50 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR2DT BPR2DT Battery powered domain register 0x54 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR3DT BPR3DT Battery powered domain register 0x58 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR4DT BPR4DT Battery powered domain register 0x5C 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR5DT BPR5DT Battery powered domain register 0x60 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR6DT BPR6DT Battery powered domain register 0x64 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR7DT BPR7DT Battery powered domain register 0x68 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR8DT BPR8DT Battery powered domain register 0x6C 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR9DT BPR9DT Battery powered domain register 0x70 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR10DT BPR10DT Battery powered domain register 0x74 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR11DT BPR11DT Battery powered domain register 0x78 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR12DT BPR12DT Battery powered domain register 0x7C 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR13DT BPR13DT Battery powered domain register 0x80 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR14DT BPR14DT Battery powered domain register 0x84 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR15DT BPR15DT Battery powered domain register 0x88 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR16DT BPR16DT Battery powered domain register 0x8C 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR17DT BPR17DT Battery powered domain register 0x90 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR18DT BPR18DT Battery powered domain register 0x94 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR19DT BPR19DT Battery powered domain register 0x98 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 BPR20DT BPR20DT Battery powered domain register 0x9C 0x20 read-write 0x00000000 DT Battery powered domain data 0 32 WDT Watchdog WDT 0x40003000 0x0 0x400 registers CMD CMD Command register 0x0 0x20 write-only 0x00000000 CMD Command register 0 16 DIV DIV Division register 0x4 0x20 read-write 0x00000000 DIV Division divider 0 3 RLD RLD Reload register 0x8 0x20 read-write 0x00000FFF RLD Reload value 0 12 STS STS Status register 0xC 0x20 read-only 0x00000000 DIVF Division value update complete flag 0 1 RLDF Reload value update complete flag 1 1 WINF Window value update complete flag 2 1 WIN WIN Window register 0x10 0x20 read-write 0x00000FFF WIN Window value 0 12 WWDT Window watchdog WWDT 0x40002C00 0x0 0x400 registers WWDT Window Watchdog interrupt 0 CTRL CTRL Control register 0x0 0x20 read-write 0x0000007F CNT Decrement counter 0 7 WWDTEN Window watchdog enable 7 1 CFG CFG Configuration register 0x4 0x20 read-write 0x0000007F WIN Window value 0 7 DIV Clock division value 7 2 RLDIEN Reload counter interrupt 9 1 STS STS Status register 0x8 0x20 read-write 0x00000000 RLDF Reload counter interrupt flag 0 1 TMR1 Advanced timer TIMER 0x40010000 0x0 0x400 registers TMR1_BRK_TMR9 TMR1 brake interrupt and TMR9 global interrupt 24 TMR1_OVF_TMR10 TMR1 overflow interrupt and TMR10 global interrupt 25 TMR1_TRG_HALL_TMR11 TMR1 trigger and HALL interrupts and TMR11 global interrupt 26 TMR1_CH TMR1 channel interrupt 27 CTRL1 CTRL1 Control register 1 0x0 0x20 read-write 0x0000 CLKDIV Clock divider 8 2 PRBEN Period buffer enable 7 1 TWCMSEL Two-way count mode selection 5 2 OWCDIR One-way count direction 4 1 OCMEN One cycle mode enable 3 1 OVFS Overflow event source 2 1 OVFEN Overflow event enable 1 1 TMREN TMR enable 0 1 CTRL2 CTRL2 Control register 2 0x4 0x20 read-write 0x0000 TRGOUT2EN TRGOUT2 enable 31 1 C4IOS Channel 4 idle output state 14 1 C3CIOS Channel 3 complementary idle output state 13 1 C3IOS Channel 3 idle output state 12 1 C2CIOS Channel 2 complementary idle output state 11 1 C2IOS Channel 2 idle output state 10 1 C1CIOS Channel 1 complementary idle output state 9 1 C1IOS Channel 1 idle output state 8 1 C1INSEL C1IN selection 7 1 PTOS Primary TMR output selection 4 3 DRS DMA request source 3 1 CCFS Channel control bit flash select 2 1 CBCTRL Channel buffer control 0 1 STCTRL STCTRL Subordinate TMR control register 0x8 0x20 read-write 0x0000 ESP External signal polarity 15 1 ECMBEN External clock mode B enable 14 1 ESDIV External signal divider 12 2 ESF External signal filter 8 4 STS Subordinate TMR synchronization 7 1 STIS Subordinate TMR input selection 4 3 SMSEL Subordinate TMR mode selection 0 3 IDEN IDEN Interrupt/DMA enable register 0xC 0x20 read-write 0x0000 TDEN Trigger DMA request enable 14 1 HALLDE HALL DMA request enable 13 1 C4DEN Channel 4 DMA request enable 12 1 C3DEN Channel 3 DMA request enable 11 1 C2DEN Channel 2 DMA request enable 10 1 C1DEN Channel 1 DMA request enable 9 1 OVFDEN Overflow DMA request enable 8 1 BRKIE Brake interrupt enable 7 1 TIEN Trigger interrupt enable 6 1 HALLIEN HALL interrupt enable 5 1 C4IEN Channel 4 interrupt enable 4 1 C3IEN Channel 3 interrupt enable 3 1 C2IEN Channel 2 interrupt enable 2 1 C1IEN Channel 1 interrupt enable 1 1 OVFIEN Overflow interrupt enable 0 1 ISTS ISTS Interrupt status register 0x10 0x20 read-write 0x0000 C4RF Channel 4 recapture flag 12 1 C3RF Channel 3 recapture flag 11 1 C2RF Channel 2 recapture flag 10 1 C1RF Channel 1 recapture flag 9 1 BRKIF Brake interrupt flag 7 1 TRGIF Trigger interrupt flag 6 1 HALLIF HALL interrupt flag 5 1 C4IF Channel 4 interrupt flag 4 1 C3IF Channel 3 interrupt flag 3 1 C2IF Channel 2 interrupt flag 2 1 C1IF Channel 1 interrupt flag 1 1 OVFIF Overflow interrupt flag 0 1 SWEVT SWEVT Software event register 0x14 0x20 read-write 0x0000 BRKSWTR Brake event triggered by software 7 1 TRGSWTR Trigger event triggered by software 6 1 HALLSWTR HALL event triggered by software 5 1 C4SWTR Channel 4 event triggered by software 4 1 C3SWTR Channel 3 event triggered by software 3 1 C2SWTR Channel 2 event triggered by software 2 1 C1SWTR Channel 1 event triggered by software 1 1 OVFSWTR Overflow event triggered by software 0 1 CM1_OUTPUT CM1_OUTPUT Channel output mode register 0x18 0x20 read-write 0x00000000 C2OSEN Channel 2 output switch enable 15 1 C2OCTRL Channel 2 output control 12 3 C2OBEN Channel 2 output buffer enable 11 1 C2OIEN Channel 2 output immediately enable 10 1 C2C Channel 2 configure 8 2 C1OSEN Channel 1 output switch enable 7 1 C1OCTRL Channel 1 output control 4 3 C1OBEN Channel 1 output buffer enable 3 1 C1OIEN Channel 1 output immediately enable 2 1 C1C Channel 1 configure 0 2 CM1_INPUT CM1_INPUT Channel input mode register 1 CM1_OUTPUT 0x18 0x20 read-write 0x00000000 C2DF Channel 2 digital filter 12 4 C2IDIV Channel 2 input divider 10 2 C2C Channel 2 configure 8 2 C1DF Channel 1 digital filter 4 4 C1IDIV Channel 1 input divider 2 2 C1C Channel 1 configure 0 2 CM2_OUTPUT CM2_OUTPUT Channel output mode register 2 0x1C 0x20 read-write 0x00000000 C4OSEN Channel 4 output switch enable 15 1 C4OCTRL Channel 4 output control 12 3 C4OBEN Channel 4 output buffer enable 11 1 C4OIEN Channel 4 output immediately enable 10 1 C4C Channel 4 configure 8 2 C3OSEN Channel 3 output switch enable 7 1 C3OCTRL Channel 3 output control 4 3 C3OBEN Channel 3 output buffer enable 3 1 C3OIEN Channel 3 output immediately enable 2 1 C3C Channel 3 configure 0 2 CM2_INPUT CM2_INPUT Channel input mode register 2 CM2_OUTPUT 0x1C 0x20 read-write 0x00000000 C4DF Channel 4 digital filter 12 4 C4IDIV Channel 4 input divider 10 2 C4C Channel 4 configure 8 2 C3DF Channel 3 digital filter 4 4 C3IDIV Channel 3 input divider 2 2 C3C Channel 3 configure 0 2 CCTRL CCTRL Channel control register 0x20 0x20 read-write 0x0000 C4P Channel 4 Polarity 13 1 C4EN Channel 4 enable 12 1 C3CP Channel 3 complementary polarity 11 1 C3CEN Channel 3 complementary enable 10 1 C3P Channel 3 Polarity 9 1 C3EN Channel 3 enable 8 1 C2CP Channel 2 complementary polarity 7 1 C2CEN Channel 2 complementary enable 6 1 C2P Channel 2 Polarity 5 1 C2EN Channel 2 enable 4 1 C1CP Channel 1 complementary polarity 3 1 C1CEN Channel 1 complementary enable 2 1 C1P Channel 1 Polarity 1 1 C1EN Channel 1 enable 0 1 CVAL CVAL Counter value 0x24 0x20 read-write 0x00000000 CVAL Counter value 0 16 DIV DIV Divider value 0x28 0x20 read-write 0x0000 DIV Divider value 0 16 PR PR Period value 0x2C 0x20 read-write 0x00000000 PR Period value 0 16 RPR RPR Repetition of period value 0x30 0x20 read-write 0x0000 RPR Repetition of period value 0 16 C1DT C1DT Channel 1 data register 0x34 0x20 read-write 0x00000000 C1DT Channel 1 data register 0 16 C2DT C2DT Channel 2 data register 0x38 0x20 read-write 0x00000000 C2DT Channel 2 data register 0 16 C3DT C3DT Channel 3 data register 0x3C 0x20 read-write 0x00000000 C3DT Channel 3 data register 0 16 C4DT C4DT Channel 4 data register 0x40 0x20 read-write 0x00000000 C4DT Channel 4 data register 0 16 BRK BRK Brake register 0x44 0x20 read-write 0x0000 BKF Brake input filter 16 4 OEN Output enable 15 1 AOEN Automatic output enable 14 1 BRKV Brake input validity 13 1 BRKEN Brake enable 12 1 FCSOEN Frozen channel status when holistic output enable 11 1 FCSODIS Frozen channel status when holistic output disable 10 1 WPC Write protected configuration 8 2 DTC Dead-time configuration 0 8 DMACTRL DMACTRL DMA control register 0x48 0x20 read-write 0x0000 DTB DMA transfer bytes 8 5 ADDR DMA transfer address offset 0 5 DMADT DMADT DMA data register 0x4C 0x20 read-write 0x0000 DMADT DMA data register 0 16 CM3_OUTPUT CM3_OUTPUT Channel output mode register 0x70 0x20 read-write 0x00000000 C5OSEN Channel 5 output switch enable 7 1 C5OCTRL Channel 5 output control 4 3 C5OBEN Channel 5 output buffer enable 3 1 C5OIEN Channel 5 output immediately enable 2 1 C5DT C5DT Channel 5 data register 0x74 0x20 read-write 0x00000000 C5DT Channel 5 data register 0 16 TMR2 General purpose timer TIMER 0x40000000 0x0 0x400 registers TMR2 TMR2 global interrupt 28 CTRL1 CTRL1 Control register 1 0x0 0x20 read-write 0x0000 PMEN Plus Mode Enable 10 1 CLKDIV Clock divider 8 2 PRBEN Period buffer enable 7 1 TWCMSEL Two-way count mode selection 5 2 OWCDIR One-way count direction 4 1 OCMEN One cycle mode enable 3 1 OVFS Overflow event source 2 1 OVFEN Overflow event enable 1 1 TMREN TMR enable 0 1 CTRL2 CTRL2 Control register 2 0x4 0x20 read-write 0x0000 C1INSEL C1IN selection 7 1 PTOS Primary TMR output selection 4 3 DRS DMA request source 3 1 STCTRL STCTRL Subordinate TMR control register 0x8 0x20 read-write 0x0000 ESP External signal polarity 15 1 ECMBEN External clock mode B enable 14 1 ESDIV External signal divider 12 2 ESF External signal filter 8 4 STS Subordinate TMR synchronization 7 1 STIS Subordinate TMR input selection 4 3 SMSEL Subordinate TMR mode selection 0 3 IDEN IDEN Interrupt/DMA enable register 0xC 0x20 read-write 0x0000 TDEN Trigger DMA request enable 14 1 C4DEN Channel 4 DMA request enable 12 1 C3DEN Channel 3 DMA request enable 11 1 C2DEN Channel 2 DMA request enable 10 1 C1DEN Channel 1 DMA request enable 9 1 OVFDEN Overflow DMA request enable 8 1 TIEN Trigger interrupt enable 6 1 C4IEN Channel 4 interrupt enable 4 1 C3IEN Channel 3 interrupt enable 3 1 C2IEN Channel 2 interrupt enable 2 1 C1IEN Channel 1 interrupt enable 1 1 OVFIEN Overflow interrupt enable 0 1 ISTS ISTS Interrupt status register 0x10 0x20 read-write 0x0000 C4RF Channel 4 recapture flag 12 1 C3RF Channel 3 recapture flag 11 1 C2RF Channel 2 recapture flag 10 1 C1RF Channel 1 recapture flag 9 1 TRGIF Trigger interrupt flag 6 1 C4IF Channel 4 interrupt flag 4 1 C3IF Channel 3 interrupt flag 3 1 C2IF Channel 2 interrupt flag 2 1 C1IF Channel 1 interrupt flag 1 1 OVFIF Overflow interrupt flag 0 1 SWEVT SWEVT Software event register 0x14 0x20 read-write 0x0000 TRGSWTR Trigger event triggered by software 6 1 C4SWTR Channel 4 event triggered by software 4 1 C3SWTR Channel 3 event triggered by software 3 1 C2SWTR Channel 2 event triggered by software 2 1 C1SWTR Channel 1 event triggered by software 1 1 OVFSWTR Overflow event triggered by software 0 1 CM1_OUTPUT CM1_OUTPUT Channel output mode register 0x18 0x20 read-write 0x00000000 C2OSEN Channel 2 output switch enable 15 1 C2OCTRL Channel 2 output control 12 3 C2OBEN Channel 2 output buffer enable 11 1 C2OIEN Channel 2 output immediately enable 10 1 C2C Channel 2 configure 8 2 C1OSEN Channel 1 output switch enable 7 1 C1OCTRL Channel 1 output control 4 3 C1OBEN Channel 1 output buffer enable 3 1 C1OIEN Channel 1 output immediately enable 2 1 C1C Channel 1 configure 0 2 CM1_INPUT CM1_INPUT Channel input mode register 1 CM1_OUTPUT 0x18 0x20 read-write 0x00000000 C2DF Channel 2 digital filter 12 4 C2IDIV Channel 2 input divider 10 2 C2C Channel 2 configure 8 2 C1DF Channel 1 digital filter 4 4 C1IDIV Channel 1 input divider 2 2 C1C Channel 1 configure 0 2 CM2_OUTPUT CM2_OUTPUT Channel output mode register 2 0x1C 0x20 read-write 0x00000000 C4OSEN Channel 4 output switch enable 15 1 C4OCTRL Channel 4 output control 12 3 C4OBEN Channel 4 output buffer enable 11 1 C4OIEN Channel 4 output immediately enable 10 1 C4C Channel 4 configure 8 2 C3OSEN Channel 3 output switch enable 7 1 C3OCTRL Channel 3 output control 4 3 C3OBEN Channel 3 output buffer enable 3 1 C3OIEN Channel 3 output immediately enable 2 1 C3C Channel 3 configure 0 2 CM2_INPUT CM2_INPUT Channel input mode register 2 CM2_OUTPUT 0x1C 0x20 read-write 0x00000000 C4DF Channel 4 digital filter 12 4 C4IDIV Channel 4 input divider 10 2 C4C Channel 4 configure 8 2 C3DF Channel 3 digital filter 4 4 C3IDIV Channel 3 input divider 2 2 C3C Channel 3 configure 0 2 CCTRL CCTRL Channel control register 0x20 0x20 read-write 0x0000 C4P Channel 4 Polarity 13 1 C4EN Channel 4 enable 12 1 C3P Channel 3 Polarity 9 1 C3EN Channel 3 enable 8 1 C2P Channel 2 Polarity 5 1 C2EN Channel 2 enable 4 1 C1P Channel 1 Polarity 1 1 C1EN Channel 1 enable 0 1 CVAL CVAL Counter value 0x24 0x20 read-write 0x00000000 CVAL Counter value 0 32 DIV DIV Divider value 0x28 0x20 read-write 0x0000 DIV Divider value 0 16 PR PR Period value 0x2C 0x20 read-write 0x00000000 PR Period value 0 32 C1DT C1DT Channel 1 data register 0x34 0x20 read-write 0x00000000 C1DT Channel 1 data register 0 32 C2DT C2DT Channel 2 data register 0x38 0x20 read-write 0x00000000 C2DT Channel 2 data register 0 32 C3DT C3DT Channel 3 data register 0x3C 0x20 read-write 0x00000000 C3DT Channel 3 data register 0 32 C4DT C4DT Channel 4 data register 0x40 0x20 read-write 0x00000000 C4DT Channel 4 data register 0 32 DMACTRL DMACTRL DMA control register 0x48 0x20 read-write 0x0000 DTB DMA transfer bytes 8 5 ADDR DMA transfer address offset 0 5 DMADT DMADT DMA data register 0x4C 0x20 read-write 0x0000 DMADT DMA data register 0 16 RMP RMP TMR2 input remap register 0x50 0x20 read-write 0x0000 TMR2_IS1_IRMP TMR2 internal selection 3 remap 10 2 TMR3 General purpose timer TIMER 0x40000400 0x0 0x400 registers TMR3 TMR3 global interrupt 29 CTRL1 CTRL1 Control register 1 0x0 0x20 read-write 0x0000 CLKDIV Clock divider 8 2 PRBEN Period buffer enable 7 1 TWCMSEL Two-way count mode selection 5 2 OWCDIR One-way count direction 4 1 OCMEN One cycle mode enable 3 1 OVFS Overflow event source 2 1 OVFEN Overflow event enable 1 1 TMREN TMR enable 0 1 CTRL2 CTRL2 Control register 2 0x4 0x20 read-write 0x0000 C1INSEL C1IN selection 7 1 PTOS Primary TMR output selection 4 3 DRS DMA request source 3 1 STCTRL STCTRL Subordinate TMR control register 0x8 0x20 read-write 0x0000 ESP External signal polarity 15 1 ECMBEN External clock mode B enable 14 1 ESDIV External signal divider 12 2 ESF External signal filter 8 4 STS Subordinate TMR synchronization 7 1 STIS Subordinate TMR input selection 4 3 SMSEL Subordinate TMR mode selection 0 3 IDEN IDEN Interrupt/DMA enable register 0xC 0x20 read-write 0x0000 TDEN Trigger DMA request enable 14 1 C4DEN Channel 4 DMA request enable 12 1 C3DEN Channel 3 DMA request enable 11 1 C2DEN Channel 2 DMA request enable 10 1 C1DEN Channel 1 DMA request enable 9 1 OVFDEN Overflow DMA request enable 8 1 TIEN Trigger interrupt enable 6 1 C4IEN Channel 4 interrupt enable 4 1 C3IEN Channel 3 interrupt enable 3 1 C2IEN Channel 2 interrupt enable 2 1 C1IEN Channel 1 interrupt enable 1 1 OVFIEN Overflow interrupt enable 0 1 ISTS ISTS Interrupt status register 0x10 0x20 read-write 0x0000 C4RF Channel 4 recapture flag 12 1 C3RF Channel 3 recapture flag 11 1 C2RF Channel 2 recapture flag 10 1 C1RF Channel 1 recapture flag 9 1 TRGIF Trigger interrupt flag 6 1 C4IF Channel 4 interrupt flag 4 1 C3IF Channel 3 interrupt flag 3 1 C2IF Channel 2 interrupt flag 2 1 C1IF Channel 1 interrupt flag 1 1 OVFIF Overflow interrupt flag 0 1 SWEVT SWEVT Software event register 0x14 0x20 read-write 0x0000 TRGSWTR Trigger event triggered by software 6 1 C4SWTR Channel 4 event triggered by software 4 1 C3SWTR Channel 3 event triggered by software 3 1 C2SWTR Channel 2 event triggered by software 2 1 C1SWTR Channel 1 event triggered by software 1 1 OVFSWTR Overflow event triggered by software 0 1 CM1_OUTPUT CM1_OUTPUT Channel output mode register 0x18 0x20 read-write 0x00000000 C2OSEN Channel 2 output switch enable 15 1 C2OCTRL Channel 2 output control 12 3 C2OBEN Channel 2 output buffer enable 11 1 C2OIEN Channel 2 output immediately enable 10 1 C2C Channel 2 configure 8 2 C1OSEN Channel 1 output switch enable 7 1 C1OCTRL Channel 1 output control 4 3 C1OBEN Channel 1 output buffer enable 3 1 C1OIEN Channel 1 output immediately enable 2 1 C1C Channel 1 configure 0 2 CM1_INPUT CM1_INPUT Channel input mode register 1 CM1_OUTPUT 0x18 0x20 read-write 0x00000000 C2DF Channel 2 digital filter 12 4 C2IDIV Channel 2 input divider 10 2 C2C Channel 2 configure 8 2 C1DF Channel 1 digital filter 4 4 C1IDIV Channel 1 input divider 2 2 C1C Channel 1 configure 0 2 CM2_OUTPUT CM2_OUTPUT Channel output mode register 2 0x1C 0x20 read-write 0x00000000 C4OSEN Channel 4 output switch enable 15 1 C4OCTRL Channel 4 output control 12 3 C4OBEN Channel 4 output buffer enable 11 1 C4OIEN Channel 4 output immediately enable 10 1 C4C Channel 4 configure 8 2 C3OSEN Channel 3 output switch enable 7 1 C3OCTRL Channel 3 output control 4 3 C3OBEN Channel 3 output buffer enable 3 1 C3OIEN Channel 3 output immediately enable 2 1 C3C Channel 3 configure 0 2 CM2_INPUT CM2_INPUT Channel input mode register 2 CM2_OUTPUT 0x1C 0x20 read-write 0x00000000 C4DF Channel 4 digital filter 12 4 C4IDIV Channel 4 input divider 10 2 C4C Channel 4 configure 8 2 C3DF Channel 3 digital filter 4 4 C3IDIV Channel 3 input divider 2 2 C3C Channel 3 configure 0 2 CCTRL CCTRL Channel control register 0x20 0x20 read-write 0x0000 C4P Channel 4 Polarity 13 1 C4EN Channel 4 enable 12 1 C3P Channel 3 Polarity 9 1 C3EN Channel 3 enable 8 1 C2P Channel 2 Polarity 5 1 C2EN Channel 2 enable 4 1 C1P Channel 1 Polarity 1 1 C1EN Channel 1 enable 0 1 CVAL CVAL Counter value 0x24 0x20 read-write 0x00000000 CVAL Counter value 0 16 DIV DIV Divider value 0x28 0x20 read-write 0x0000 DIV Divider value 0 16 PR PR Period value 0x2C 0x20 read-write 0x00000000 PR Period value 0 16 C1DT C1DT Channel 1 data register 0x34 0x20 read-write 0x00000000 C1DT Channel 1 data register 0 16 C2DT C2DT Channel 2 data register 0x38 0x20 read-write 0x00000000 C2DT Channel 2 data register 0 16 C3DT C3DT Channel 3 data register 0x3C 0x20 read-write 0x00000000 C3DT Channel 3 data register 0 16 C4DT C4DT Channel 4 data register 0x40 0x20 read-write 0x00000000 C4DT Channel 4 data register 0 16 DMACTRL DMACTRL DMA control register 0x48 0x20 read-write 0x0000 DTB DMA transfer bytes 8 5 ADDR DMA transfer address offset 0 5 DMADT DMADT DMA data register 0x4C 0x20 read-write 0x0000 DMADT DMA data register 0 16 TMR4 0x40000800 TMR4 TMR4 global interrupt 30 TMR9 General purpose timer TIMER 0x40014000 0x0 0x400 registers CTRL1 CTRL1 Control register 1 0x0 0x20 read-write 0x0000 CLKDIV Clock divider 8 2 PRBEN Period buffer enable 7 1 TWCMSEL Two-way count mode selection 5 2 OWCDIR One-way count direction 4 1 OCMEN One cycle mode enable 3 1 OVFS Overflow event source 2 1 OVFEN Overflow event enable 1 1 TMREN TMR enable 0 1 CTRL2 CTRL2 Control register 2 0x4 0x20 read-write 0x0000 C2CIOS Channel 2 complementary idle output state 11 1 C2IOS Channel 2 idle output state 10 1 C1CIOS Channel 1 complementary idle output state 9 1 C1IOS Channel 1 idle output state 8 1 PTOS Primary TMR output selection 4 3 DRS DMA request source 3 1 CCFS Channel control bit flash select 2 1 CBCTRL Channel buffer control 0 1 STCTRL STCTRL Subordinate TMR control register 0x8 0x20 read-write 0x0000 STS Subordinate TMR synchronization 7 1 STIS Subordinate TMR input selection 4 3 SMSEL Subordinate TMR mode selection 0 3 IDEN IDEN Interrupt/DMA enable register 0xC 0x20 read-write 0x0000 TDEN Trigger DMA request enable 14 1 HALLDE HALL DMA request enable 13 1 C2DEN Channel 2 DMA request enable 10 1 C1DEN Channel 1 DMA request enable 9 1 OVFDEN Overflow DMA request enable 8 1 BRKIE Brake interrupt enable 7 1 TIEN Trigger interrupt enable 6 1 HALLIEN HALL interrupt enable 5 1 C2IEN Channel 2 interrupt enable 2 1 C1IEN Channel 1 interrupt enable 1 1 OVFIEN Overflow interrupt enable 0 1 ISTS ISTS Interrupt status register 0x10 0x20 read-write 0x0000 C2RF Channel 2 recapture flag 10 1 C1RF Channel 1 recapture flag 9 1 BRKIF Brake interrupt flag 7 1 TRGIF Trigger interrupt flag 6 1 C2IF Channel 2 interrupt flag 2 1 C1IF Channel 1 interrupt flag 1 1 OVFIF Overflow interrupt flag 0 1 SWEVT SWEVT Software event register 0x14 0x20 read-write 0x0000 BRKSWTR Brake event triggered by software 7 1 TRGSWTR Trigger event triggered by software 6 1 HALLSWTR HALL event triggered by software 5 1 C2SWTR Channel 2 event triggered by software 2 1 C1SWTR Channel 1 event triggered by software 1 1 OVFSWTR Overflow event triggered by software 0 1 CM1_OUTPUT CM1_OUTPUT Channel output mode register 0x18 0x20 read-write 0x00000000 C2OCTRL Channel 2 output control 12 3 C2OBEN Channel 2 output buffer enable 11 1 C2OIEN Channel 2 output immediately enable 10 1 C2C Channel 2 configure 8 2 C1OCTRL Channel 1 output control 4 3 C1OBEN Channel 1 output buffer enable 3 1 C1OIEN Channel 1 output immediately enable 2 1 C1C Channel 1 configure 0 2 CM1_INPUT CM1_INPUT Channel input mode register 1 CM1_OUTPUT 0x18 0x20 read-write 0x00000000 C2DF Channel 2 digital filter 12 4 C2IDIV Channel 2 input divider 10 2 C2C Channel 2 configure 8 2 C1DF Channel 1 digital filter 4 4 C1IDIV Channel 1 input divider 2 2 C1C Channel 1 configure 0 2 CCTRL CCTRL Channel control register 0x20 0x20 read-write 0x0000 C2CP Channel 2 complementary polarity 7 1 C2CEN Channel 2 complementary enable 6 1 C2P Channel 2 Polarity 5 1 C2EN Channel 2 enable 4 1 C1CP Channel 1 complementary polarity 3 1 C1CEN Channel 1 complementary enable 2 1 C1P Channel 1 Polarity 1 1 C1EN Channel 1 enable 0 1 CVAL CVAL Counter value 0x24 0x20 read-write 0x00000000 CVAL Counter value 0 16 DIV DIV Divider value 0x28 0x20 read-write 0x0000 DIV Divider value 0 16 PR PR Period value 0x2C 0x20 read-write 0x00000000 PR Period value 0 16 RPR RPR Repetition of period value 0x30 0x20 read-write 0x0000 RPR Repetition of period value 0 8 C1DT C1DT Channel 1 data register 0x34 0x20 read-write 0x00000000 C1DT Channel 1 data register 0 16 C2DT C2DT Channel 2 data register 0x38 0x20 read-write 0x00000000 C2DT Channel 2 data register 0 16 BRK BRK Brake register 0x44 0x20 read-write 0x0000 BKF Brake input filter 16 4 OEN Output enable 15 1 AOEN Automatic output enable 14 1 BRKV Brake input validity 13 1 BRKEN Brake enable 12 1 FCSOEN Frozen channel status when holistic output enable 11 1 FCSODIS Frozen channel status when holistic output disable 10 1 WPC Write protected configuration 8 2 DTC Dead-time configuration 0 8 DMACTRL DMACTRL DMA control register 0x48 0x20 read-write 0x0000 DTB DMA transfer bytes 8 5 ADDR DMA transfer address offset 0 5 DMADT DMADT DMA data register 0x4C 0x20 read-write 0x0000 DMADT DMA data register 0 16 TMR10 General purpose timer TIMER 0x40014400 0x0 0x400 registers TMR1_OVF_TMR10 TMR1 overflow interrupt and TMR10 global interrupt 25 CTRL1 CTRL1 Control register 1 0x0 0x20 read-write 0x0000 CLKDIV Clock divider 8 2 PRBEN Period buffer enable 7 1 TWCMSEL Two-way count mode selection 5 2 OWCDIR One-way count direction 4 1 OCMEN One cycle mode enable 3 1 OVFS Overflow event source 2 1 OVFEN Overflow event enable 1 1 TMREN TMR enable 0 1 CTRL2 CTRL2 Control register 2 0x4 0x20 read-write 0x0000 C1CIOS Channel 1 complementary idle output state 9 1 C1IOS Channel 1 idle output state 8 1 PTOS Primary TMR output selection 4 3 DRS DMA request source 3 1 CCFS Channel control bit flash select 2 1 CBCTRL Channel buffer control 0 1 IDEN IDEN Interrupt/DMA enable register 0xC 0x20 read-write 0x0000 C1DEN Channel 1 DMA request enable 9 1 OVFDEN Overflow DMA request enable 8 1 BRKIE Brake interrupt enable 7 1 HALLIEN HALL interrupt enable 5 1 C1IEN Channel 1 interrupt enable 1 1 OVFIEN Overflow interrupt enable 0 1 ISTS ISTS Interrupt status register 0x10 0x20 read-write 0x0000 C1RF Channel 1 recapture flag 9 1 BRKIF Brake interrupt flag 7 1 HALLIF HALL interrupt flag 5 1 C1IF Channel 1 interrupt flag 1 1 OVFIF Overflow interrupt flag 0 1 SWEVT SWEVT Software event register 0x14 0x20 read-write 0x0000 BRKSWTR Brake event triggered by software 7 1 HALLSWTR HALL event triggered by software 5 1 C1SWTR Channel 1 event triggered by software 1 1 OVFSWTR Overflow event triggered by software 0 1 CM1_OUTPUT CM1_OUTPUT Channel output mode register 0x18 0x20 read-write 0x00000000 C1OCTRL Channel 1 output control 4 3 C1OBEN Channel 1 output buffer enable 3 1 C1OIEN Channel 1 output immediately enable 2 1 C1C Channel 1 configure 0 2 CM1_INPUT CM1_INPUT Channel input mode register 1 CM1_OUTPUT 0x18 0x20 read-write 0x00000000 C1DF Channel 1 digital filter 4 4 C1IDIV Channel 1 input divider 2 2 C1C Channel 1 configure 0 2 CCTRL CCTRL Channel control register 0x20 0x20 read-write 0x0000 C1CP Channel 1 complementary polarity 3 1 C1CEN Channel 1 complementary enable 2 1 C1P Channel 1 Polarity 1 1 C1EN Channel 1 enable 0 1 CVAL CVAL Counter value 0x24 0x20 read-write 0x00000000 CVAL Counter value 0 16 DIV DIV Divider value 0x28 0x20 read-write 0x0000 DIV Divider value 0 16 PR PR Period value 0x2C 0x20 read-write 0x00000000 PR Period value 0 16 RPR RPR Repetition of period value 0x30 0x20 read-write 0x0000 RPR Repetition of period value 0 8 C1DT C1DT Channel 1 data register 0x34 0x20 read-write 0x00000000 C1DT Channel 1 data register 0 16 BRK BRK Brake register 0x44 0x20 read-write 0x0000 BKF Brake input filter 16 4 OEN Output enable 15 1 AOEN Automatic output enable 14 1 BRKV Brake input validity 13 1 BRKEN Brake enable 12 1 FCSOEN Frozen channel status when holistic output enable 11 1 FCSODIS Frozen channel status when holistic output disable 10 1 WPC Write protected configuration 8 2 DTC Dead-time configuration 0 8 DMACTRL DMACTRL DMA control register 0x48 0x20 read-write 0x0000 DTB DMA transfer bytes 8 5 ADDR DMA transfer address offset 0 5 DMADT DMADT DMA data register 0x4C 0x20 read-write 0x0000 DMADT DMA data register 0 16 TMR11 0x40014800 TMR1_TRG_HALL_TMR11 TMR1 trigger and HALL interrupts and TMR11 global interrupt 26 TMR13 0x40001C00 TMR14 0x40002000 RMP RMP TMR14 channel 1 input remap 0x50 0x20 read-write 0x00000000 TMR14_CH1_IRMP TMR14 channel 1 input remap 6 2 TMR6 Basic timer TIMER 0x40001000 0x0 0x400 registers TMR6 TMR6 global interrupt 54 CTRL1 CTRL1 Control register 1 0x0 0x20 read-write 0x0000 PRBEN Period buffer enable 7 1 OCMEN One cycle mode enable 3 1 OVFS Overflow event source 2 1 OVFEN Overflow event enable 1 1 TMREN TMR enable 0 1 CTRL2 CTRL2 Control register 2 0x4 0x20 read-write 0x0000 PTOS Primary TMR output selection 4 3 IDEN IDEN Interrupt/DMA enable register 0xC 0x20 read-write 0x0000 OVFDEN Overflow DMA request enable 8 1 OVFIEN Overflow interrupt enable 0 1 ISTS ISTS Interrupt status register 0x10 0x20 read-write 0x0000 OVFIF Overflow interrupt flag 0 1 SWEVT SWEVT Software event register 0x14 0x20 read-write 0x0000 OVFSWTR Overflow event triggered by software 0 1 CVAL CVAL Counter value 0x24 0x20 read-write 0x00000000 CVAL Counter value 0 16 DIV DIV Divider value 0x28 0x20 read-write 0x0000 DIV Divider value 0 16 PR PR Period value 0x2C 0x20 read-write 0x00000000 PR Period value 0 16 TMR7 0x40001400 TMR7 TMR7 global interrupt 55 ACC HSI Auto Clock Calibration ACC 0x40017400 0x0 0x400 registers STS STS status register 0x0 0x20 0x0000 RSLOST Reference Signal Lost read-write 1 1 CALRDY Internal high-speed clock calibration ready read-write 0 1 CTRL1 CTRL1 control register 1 0x04 0x20 0x0100 STEP STEP read-write 8 4 CALRDYIEN CALRDY interrupt enable read-write 5 1 EIEN RSLOST error interrupt enable read-write 4 1 ENTRIM Enable trim read-write 1 1 CALON Calibration on read-write 0 1 CTRL2 CTRL2 control register 2 0x08 0x20 0x2080 HICKTWK Internal high-speed auto clock trimming read-only 8 6 HICKCAL Internal high-speed auto clock calibration read-only 0 8 C1 C1 compare value 1 0x0C 0x20 0x1F2C C1 Compare 1 read-write 0 16 C2 C2 compare value 2 0x10 0x20 0x1F40 C2 Compare 2 read-write 0 16 C3 C3 compare value 3 0x14 0x20 0x1F54 C3 Compare 3 read-write 0 16 I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EVT I2C1 event interrupt 31 I2C1_ERR I2C1 error interrupt 32 CTRL1 CTRL1 Control register 1 0x0 0x20 0x00000000 I2CEN I2C peripheral enable 0 1 read-write TDIEN Transmit data interrupt enable 1 1 read-write RDIEN Receive data interrupt enable 2 1 read-write ADDRIEN Address match interrupt enable 3 1 read-write ACKFAILIEN Acknowledge fail interrupt enable 4 1 read-write STOPIEN Stop generation complete interrupt enable 5 1 read-write TDCIEN Transfer data complete interrupt enable 6 1 read-write ERRIEN Error interrupts enable 7 1 read-write DFLT Digital filter value 8 4 read-write DMATEN DMA Transmit data request enable 14 1 read-write DMAREN DMA receive data request enable 15 1 read-write SCTRL Slave receiving data control 16 1 read-write STRETCH Clock stretching mode 17 1 read-write GCAEN General call address enable 19 1 read-write HADDREN SMBus host address enable 20 1 read-write DEVADDREN SMBus device default address enable 21 1 read-write SMBALERT SMBus alert enable / pin set 22 1 read-write PECEN PEC calculation enable 23 1 read-write CTRL2 CTRL2 Control register 2 0x4 0x20 read-write 0x00000000 PECTEN Request PEC transmission enable 26 1 ASTOPEN Automatically send stop condition enable 25 1 RLDEN Send data reload mode enable 24 1 CNT Transmit data counter 16 8 NACKEN Not acknowledge enable 15 1 GENSTOP Generate stop condition 14 1 GENSTART Generate start condition 13 1 READH10 10-bit address header read enable 12 1 ADDR10 Host send 10-bit address mode enable 11 1 DIR Master data transmission direction 10 1 SADDR Slave address 0 10 OADDR1 OADDR1 Own address register 1 0x8 0x20 read-write 0x00000000 ADDR1 Interface address 0 10 ADDR1MODE Own Address mode 10 1 ADDR1EN Own address 1 enable 15 1 OADDR2 OADDR2 Own address register 2 0xC 0x20 read-write 0x00000000 ADDR2 Own address 2 1 7 ADDR2MASK Own address 2-bit mask 8 3 ADDR2EN Own address 2 enable 15 1 CLKCTRL CLKCTRL Clock contorl register 0x10 0x20 read-write 0x00000000 SCLL SCL low level 0 8 SCLH SCL high level 8 8 SDAD SDA output delay 16 4 SCLD SCL output delay 20 4 DIVH High 4 bits of clock divider value 24 4 DIVL Low 4 bits of clock divider value 28 4 TIMEOUT TIMEOUT Timeout register 0x14 0x20 read-write 0x00000000 TOTIME Clock timeout detection time 0 12 TOMOED Clock timeout detection mode 12 1 TOEN Detect clock low/high timeout enable 15 1 EXTTIME Cumulative clock low extend timeout value 16 12 EXTEN Cumulative clock low extend timeout enable 31 1 STS STS Interrupt and Status register 0x18 0x20 0x00000001 ADDR Slave address matching value 17 7 read-only SDIR Slave data transmit direction 16 1 read-only BUSYF Bus busy 15 1 read-only ALERTF SMBus alert flag 13 1 read-only TMOUT SMBus timeout flag 12 1 read-only PECERR PEC receive error flag 11 1 read-only OUF Overflow or underflow flag 10 1 read-only ARLOST Arbitration lost flag 9 1 read-only BUSERR Bus error flag 8 1 read-only TCRLD Transmission is complete, waiting to load data 7 1 read-only TDC Transmit data complete flag 6 1 read-only STOPF Stop condition generation complete flag 5 1 read-only ACKFAIL Acknowledge failure flag 4 1 read-only ADDRF 0~7 bit address match flag 3 1 read-only RDBF Receive data buffer full flag 2 1 read-only TDIS Send interrupt status 1 1 read-write TDBE Transmit data buffer empty flag 0 1 read-write CLR CLR Interrupt clear register 0x1C 0x20 write-only 0x00000000 ALERTC Clear SMBus alert flag 13 1 TMOUTC Clear SMBus timeout flag 12 1 PECERRC Clear PEC receive error flag 11 1 OUFC Clear overload / underload flag 10 1 ARLOSTC Clear arbitration lost flag 9 1 BUSERRC Clear bus error flag 8 1 STOPC Clear stop condition generation complete flag 5 1 ACKFAILC Clear acknowledge failure flag 4 1 ADDRC Clear 0~7 bit address match flag 3 1 PEC PEC PEC register 0x20 0x20 read-only 0x00000000 PECVAL PEC value 0 8 RXDT RXDT Receive data register 0x24 0x20 read-only 0x00000000 DT Receive data register 0 8 TXDT TXDT Transmit data register 0x28 0x20 read-write 0x00000000 DT Transmit data register 0 8 I2C2 0x40005800 I2C2_EVT I2C2 event interrupt 33 I2C2_ERR I2C2 error interrupt 34 I2C3 0x40005C00 I2C3_EVT I2C3 event interrupt 72 I2C3_ERR I2C3 error interrupt 73 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 35 CTRL1 CTRL1 control register 1 0x0 0x20 read-write 0x0000 SLBEN Single line bidirectional half-duplex enable 15 1 SLBTD Single line bidirectional half-duplex transmission direction 14 1 CCEN CRC calculation enable 13 1 NTC Next transmission CRC 12 1 FBN frame bit num 11 1 ORA Only receive active 10 1 SWCSEN Software CS enable 9 1 SWCSIL Software CS internal level 8 1 LTF LSB transmit first 7 1 SPIEN SPI enable 6 1 MDIV2_0 Master clock frequency division bit2-0 3 3 MSTEN Master enable 2 1 CLKPOL Clock polarity 1 1 CLKPHA Clock phase 0 1 CTRL2 CTRL2 control register 2 0x4 0x20 read-write 0x0000 MDIV3EN Master clock frequency3 division enable 9 1 MDIV3 Master clock frequency division bit3 8 1 TDBEIE Transmit data buffer empty interrupt enable 7 1 RDBFIE Receive data buffer full interrupt enable 6 1 ERRIE Error interrupt enable 5 1 TIEN TI mode enable 4 1 HWCSOE Hardware CS output enable 2 1 DMATEN DMA transmit enable 1 1 DMAREN DMA receive enable 0 1 STS STS status register 0x8 0x20 0x0002 CSPAS CS pulse abnormal setting fiag 8 1 read-write BF Busy flag 7 1 read-only ROERR Receiver overflow error 6 1 read-only MMERR Master mode error 5 1 read-only CCERR CRC calculation error 4 1 read-write TUERR Transmitter underload error 3 1 read-only ACS Audio channel state 2 1 read-only TDBE Transmit data buffer empty 1 1 read-only RDBF Receive data buffer full 0 1 read-only DT DT data register 0xC 0x20 read-write 0x0000 DT Data value 0 16 CPOLY CPOLY CRC polynomial register 0x10 0x20 read-write 0x0007 CPOLY CRC polynomial 0 16 RCRC RCRC Receive CRC register 0x14 0x20 read-only 0x0000 RCRC Receive CRC 0 16 TCRC TCRC Transmit CRC register 0x18 0x20 read-only 0x0000 TCRC Transmit CRC 0 16 I2SCTRL I2SCTRL I2S control register 0x1C 0x20 read-write 0x0000 I2SMSEL I2S mode select 11 1 I2SEN I2S Enable 10 1 OPERSEL I2S operation select 8 2 PCMFSSEL PCM frame synchronization select 7 1 STDSEL I2S standard select 4 2 I2SCLKPOL I2S clock polarity 3 1 I2SDBN I2S data bit num 1 2 I2SCBN I2S channel bit num 0 1 I2SCLK I2SCLK I2S clock register 0x20 0x20 read-write 00000010 I2SDIV9_8 I2S division bit9 and bit8 10 2 I2SMCLKOE I2S master clock output enable 9 1 I2SODD Odd result for I2S division 8 1 I2SDIV7_0 I2S division bit7 to bit0 0 8 SPI2 0x40003800 SPI2 SPI2 global interrupt 36 SPI3 0x40003C00 SPI3 SPI3 global interrupt 51 I2SF5 Serial peripheral interface SPI 0x40015000 0x0 0x400 registers I2SF5 I2SF5 global interrupt 85 CTRL2 CTRL2 control register 2 0x4 0x20 read-write 0x0000 TDBEIE Transmit data buffer empty interrupt enable 7 1 RDBFIE Receive data buffer full interrupt enable 6 1 ERRIE Error interrupt enable 5 1 DMATEN DMA transmit enable 1 1 DMAREN DMA receive enable 0 1 STS STS status register 0x8 0x20 0x0002 CSPAS CS pulse abnormal setting fiag 8 1 read-write BF Busy flag 7 1 read-only ROERR Receiver overflow error 6 1 read-only TUERR Transmitter underload error 3 1 read-only ACS Audio channel state 2 1 read-only TDBE Transmit data buffer empty 1 1 read-only RDBF Receive data buffer full 0 1 read-only DT DT data register 0xC 0x20 read-write 0x0000 DT Data value 0 16 I2SCTRL I2SCTRL I2S control register 0x1C 0x20 read-write 0x0000 I2SFDUPEN I2S full duplex mode enable 13 1 I2SEN I2S Enable 10 1 OPERSEL I2S operation select 8 2 PCMFSSEL PCM frame synchronization select 7 1 STDSEL I2S standard select 4 2 I2SCLKPOL I2S clock polarity 3 1 I2SDBN I2S data bit num 1 2 I2SCBN I2S channel bit num 0 1 I2SCLK I2SCLK I2S clock register 0x20 0x20 read-write 00000010 I2SDIV9_8 I2S division bit9 and bit8 10 2 I2SMCLKOE I2S master clock output enable 9 1 I2SODD Odd result for I2S division 8 1 I2SDIV7_0 I2S division bit7 to bit0 0 8 MISC1 MISC1 MISC1 register 0x30 0x20 read-write 00000000 I2SFPCMCKSEL I2S PCM clock edge select 0 1 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40011000 0x0 0x400 registers USART1 USART1 global interrupt 37 STS STS Status register 0x0 0x20 0x00C0 CMDF Character match detection flag 17 1 read-write RTODF Reiceiver time out detection flag 11 1 read-write CTSCF CTS change flag 9 1 read-write BFF Break frame flag 8 1 read-write TDBE Transmit data buffer empty 7 1 read-only TDC Transmit data complete 6 1 read-write RDBF Receive data buffer full 5 1 read-write IDLEF IDLE flag 4 1 read-only ROERR Receiver overflow error 3 1 read-only NERR Noise error 2 1 read-only FERR Framing error 1 1 read-only PERR Parity error 0 1 read-only DT DT Data register 0x4 0x20 read-write 0x00000000 DT Data value 0 9 BAUDR BAUDR Baud rate register 0x8 0x20 read-write 0x0000 DIV Division 0 16 CTRL1 CTRL1 Control register 1 0xC 0x20 read-write 0x0000 DBN1 high bit for Data bit num 28 1 RTODEN Receiver time out detection enable 27 1 RETODIE Receiver time out detection interrupt enable 26 1 TSDT transmit start delay time 21 5 TCDT transmit complete delay time 16 5 CMDIE Character match detection interrupt enable 14 1 UEN USART enable 13 1 DBN0 low bit for Data bit num 12 1 WUM Wake up mode 11 1 PEN Parity enable 10 1 PSEL Parity selection 9 1 PERRIEN PERR interrupt enable 8 1 TDBEIEN TDBE interrupt enable 7 1 TDCIEN TDC interrupt enable 6 1 RDBFIEN RDBF interrupt enable 5 1 IDLEIEN IDLE interrupt enable 4 1 TEN Transmitter enable 3 1 REN Receiver enable 2 1 RM Receiver mute 1 1 SBF Send break frame 0 1 CTRL2 CTRL2 Control register 2 0x10 0x20 read-write 0x0000 IDH bit 7-4 for usart identification 28 4 MTF MSB transmit first 19 1 DTREV DT register polarity reverse 18 1 TXREV TX polarity reverse 17 1 RXREV RX polarity reverse 16 1 TRPSWAP Transmit receive pin swap 15 1 LINEN LIN mode enable 14 1 STOPBN STOP bit num 12 2 CLKEN Clock enable 11 1 CLKPOL Clock polarity 10 1 CLKPHA Clock phase 9 1 LBCP Last bit clock pulse 8 1 BFIEN Break frame interrupt enable 6 1 BFBN Break frame bit num 5 1 IDBN Identification bit num 4 1 IDL bit 3-0 for usart identification 0 4 CTRL3 CTRL3 Control register 3 0x14 0x20 read-write 0x0000 DEP DE polarity selection 15 1 RS485EN RS485 enable 14 1 CTSCFIEN CTSCF interrupt enable 10 1 CTSEN CTS enable 9 1 RTSEN RTS enable 8 1 DMATEN DMA transmitter enable 7 1 DMAREN DMA receiver enable 6 1 SCMEN Smartcard mode enable 5 1 SCNACKEN Smartcard NACK enable 4 1 SLBEN Single line bidirectional half-duplex enable 3 1 IRDALP IrDA low-power mode 2 1 IRDAEN IrDA enable 1 1 ERRIEN Error interrupt enable 0 1 GDIV GDIV Guard time and division register 0x18 0x20 read-write 0x0000 SCGT Smart card guard time value 8 8 ISDIV IrDA/smartcard division value 0 8 RTOV RTOV Receiver time out value register 0x1C 0x20 read-write 0x0000 RTOV Receiver time out value 0 24 IFC IFC Interruption flag clear register 0x20 0x20 read-write 0x0000 CMDFC Character match detection flag clear 17 1 RTODFC Receiver time out detection flag clear 11 1 USART2 0x40004400 USART2 USART2 global interrupt 38 USART3 0x40004800 USART3 USART3 global interrupt 39 USART4 0x40004C00 USART4 USART4 global interrupt 52 USART5 0x40005000 USART5 USART5 global interrupt 53 USART6 0x40011400 USART6 USART6 global interrupt 71 UART7 Universal asynchronous receiver transmitter 0x40007800 UART7 UART7 global interrupt 82 UART8 Universal asynchronous receiver transmitter 0x40007C00 UART8 UART8 global interrupt 83 ADC1 Analog to digital converter ADC 0x40012000 0x0 0x100 registers ADC ADC1 global interrupt 18 STS STS status register 0x0 0x20 read-write 0x00000000 OCCS Ordinary channel conversion start flag 4 1 PCCS Preempted channel conversion start flag 3 1 PCCE Preempted channels conversion end flag 2 1 CCE Channels conversion end flag 1 1 VMOR Voltage monitoring out of range flag 0 1 CTRL1 CTRL1 control register 1 0x4 0x20 read-write 0x00000000 OCVMEN Voltage monitoring enable on ordinary channels 23 1 PCVMEN Voltage monitoring enable on preempted channels 22 1 OCPCNT Partitioned mode conversion count of ordinary channels 13 3 PCPEN Partitioned mode enable on preempted channels 12 1 OCPEN Partitioned mode enable on ordinary channels 11 1 PCAUTOEN Preempted group automatic conversion enable after ordinary group 10 1 VMSGEN Voltage monitoring enable on a single channel 9 1 SQEN Sequence mode enable 8 1 PCCEIEN Conversion end interrupt enable for preempted channels 7 1 VMORIEN Voltage monitoring out of range interrupt enable 6 1 CCEIEN Channel conversion end interrupt enable 5 1 VMCSEL Voltage monitoring channel select 0 5 CTRL2 CTRL2 control register 2 0x8 0x20 read-write 0x00000000 ITSRVEN Internal temperature sensor and VINTRV enable 23 1 OCSWTRG Conversion trigger by software of ordinary channels 22 1 PCSWTRG Conversion trigger by software of preempted channels 21 1 OCTEN Trigger mode enable for ordinary channels conversion 20 1 OCTESEL Low bit of trigger event select for ordinary channels conversion 17 3 PCTEN Trigger mode enable for preempted channels conversion 15 1 PCTESEL Low bit of trigger event select for preempted channels conversion 12 3 DTALIGN Data alignment 11 1 OCDMAEN DMA transfer enable of ordinary channels 8 1 ADCALINIT initialize A/D calibration 3 1 ADCAL A/D Calibration 2 1 RPEN Repeat mode enable 1 1 ADCEN A/D converter enable 0 1 SPT1 SPT1 sample time register 1 0xC 0x20 read-write 0x00000000 CSPT17 Selection sample time of channel ADC_IN17 21 3 CSPT16 Selection sample time of channel ADC_IN16 18 3 CSPT15 Selection sample time of channel ADC_IN15 15 3 CSPT14 Selection sample time of channel ADC_IN14 12 3 CSPT13 Selection sample time of channel ADC_IN13 9 3 CSPT12 Selection sample time of channel ADC_IN12 6 3 CSPT11 Selection sample time of channel ADC_IN11 3 3 CSPT10 Selection sample time of channel ADC_IN10 0 3 SPT2 SPT2 sample time register 2 0x10 0x20 read-write 0x00000000 CSPT9 Selection sample time of channel ADC_IN9 27 3 CSPT8 Selection sample time of channel ADC_IN8 24 3 CSPT7 Selection sample time of channel ADC_IN7 21 3 CSPT6 Selection sample time of channel ADC_IN6 18 3 CSPT5 Selection sample time of channel ADC_IN5 15 3 CSPT4 Selection sample time of channel ADC_IN4 12 3 CSPT3 Selection sample time of channel ADC_IN3 9 3 CSPT2 Selection sample time of channel ADC_IN2 6 3 CSPT1 Selection sample time of channel ADC_IN1 3 3 CSPT0 Selection sample time of channel ADC_IN0 0 3 PCDTO1 PCDTO1 Preempted channel 1 data offset register 0x14 0x20 read-write 0x00000000 PCDTO1 Data offset for Preempted channel 1 0 12 PCDTO2 PCDTO2 Preempted channel 2 data offset register 0x18 0x20 read-write 0x00000000 PCDTO2 Data offset for Preempted channel 2 0 12 PCDTO3 PCDTO3 Preempted channel 3 data offset register 0x1C 0x20 read-write 0x00000000 PCDTO3 Data offset for Preempted channel 3 0 12 PCDTO4 PCDTO4 Preempted channel 4 data offset register 0x20 0x20 read-write 0x00000000 PCDTO4 Data offset for Preempted channel 4 0 12 VMHB VMHB Voltage monitoring high boundary register 0x24 0x20 read-write 0x00000FFF VMHB Voltage monitoring high boundary 0 12 VMLB VMLB Voltage monitoring low boundary register 0x28 0x20 read-write 0x00000000 VMLB Voltage monitoring low boundary 0 12 OSQ1 OSQ1 Ordinary sequence register 1 0x2C 0x20 read-write 0x00000000 OCLEN Ordinary conversion sequence length 20 4 OSN16 Number of 16th conversion in ordinary sequence 15 5 OSN15 Number of 15th conversion in ordinary sequence 10 5 OSN14 Number of 14th conversion in ordinary sequence 5 5 OSN13 Number of 13th conversion in ordinary sequence 0 5 OSQ2 OSQ2 Ordinary sequence register 2 0x30 0x20 read-write 0x00000000 OSN12 Number of 12th conversion in ordinary sequence 25 5 OSN11 Number of 11th conversion in ordinary sequence 20 5 OSN10 Number of 10th conversion in ordinary sequence 15 5 OSN9 Number of 8th conversion in ordinary sequence 10 5 OSN8 Number of 7th conversion in ordinary sequence 5 5 OSN7 Number of 13th conversion in ordinary sequence 0 5 OSQ3 OSQ3 Ordinary sequence register 3 0x34 0x20 read-write 0x00000000 OSN6 Number of 6th conversion in ordinary sequence 25 5 OSN5 Number of 5th conversion in ordinary sequence 20 5 OSN4 Number of 4th conversion in ordinary sequence 15 5 OSN3 number of 3rd conversion in ordinary sequence 10 5 OSN2 Number of 2nd conversion in ordinary sequence 5 5 OSN1 Number of 1st conversion in ordinary sequence 0 5 PSQ PSQ Preempted sequence register 0x38 0x20 read-write 0x00000000 PCLEN Preempted conversion sequence length 20 2 PSN4 Number of 4th conversion in Preempted sequence 15 5 PSN3 Number of 3rd conversion in Preempted sequence 10 5 PSN2 Number of 2nd conversion in Preempted sequence 5 5 PSN1 Number of 1st conversion in Preempted sequence 0 5 PDT1 PDT1 Preempted data register 1 0x3C 0x20 read-only 0x00000000 PDT1 Preempted data 0 16 PDT2 PDT2 Preempted data register 2 0x40 0x20 read-only 0x00000000 PDT2 Preempted data 0 16 PDT3 PDT3 Preempted data register 3 0x44 0x20 read-only 0x00000000 PDT3 Preempted data 0 16 PDT4 PDT4 Preempted data register 4 0x48 0x20 read-only 0x00000000 PDT4 Preempted data 0 16 ODT ODT Ordinary data register 0x4C 0x20 read-only 0x00000000 ODT Conversion data of ordinary channel 0 16 OVSP OVSP oversampling register 0x80 0x20 read-write 0x00000000 OOSRSEL Ordinary oversampling recovery mode select 10 1 OOSTREN Ordinary oversampling trigger mode enable 9 1 OSSSEL Oversampling shift select 5 4 OSRSEL Oversampling ratio select 2 3 POSEN Preempted oversampling enable 1 1 OOSEN Ordinary oversampling enable 0 1 ADCCOM ADC common area ADC 0x40012300 0x0 0x100 registers CCTRL CCTRL Common control register 0x4 0x20 read-write 0x00000000 ADCDIV ADC division 16 4 CAN1 Can controller area network CAN 0x40006400 0x0 0x400 registers CAN1_TX CAN1 TX interrupt 19 CAN1_RX0 CAN1 RX0 interrupt 20 CAN_RX1 CAN1 RX1 interrupt 21 CAN_SE CAN1 SE interrupt 22 MCTRL MCTRL Main control register 0x0 0x20 read-write 0x00010002 PTD Prohibit transmission when debug 16 1 SPRST Software partial reset 15 1 TTCEN Time triggered communication mode enable 7 1 AEBOEN Automatic exit bus-off enable 6 1 AEDEN Automatic exit doze mode enable 5 1 PRSFEN Prohibit retransmission when sending fails enable 4 1 MDRSEL Message discarding rule select when overflow 3 1 MMSSR Multiple message sending sequence rule 2 1 DZEN Doze mode enable 1 1 FZEN Freeze mode enable 0 1 MSTS MSTS Main status register 0x4 0x20 0x00000C02 REALRX Real time level of RX pin 11 1 read-only LSAMPRX Last sample level of RX pin 10 1 read-only CURS Currently receiving status 9 1 read-only CUSS Currently sending status 8 1 read-only EDZIF Enter doze mode interrupt flag 4 1 read-write QDZIF Quit doze mode interrupt flag 3 1 read-write EOIF Error occur Interrupt flag 2 1 read-write DZC Doze mode confirm 1 1 read-only FZC Freeze mode confirm 0 1 read-only TSTS TSTS Transmit status register 0x8 0x20 0x1C000000 TM2LPF Transmit mailbox 2 lowest priority flag 31 1 read-only TM1LPF Transmit mailbox 1 lowest priority flag 30 1 read-only TM0LPF Transmit mailbox 0 lowest priority flag 29 1 read-only TM2EF Transmit mailbox 2 empty flag 28 1 read-only TM1EF Transmit mailbox 1 empty flag 27 1 read-only TM0EF Transmit mailbox 0 empty flag 26 1 read-only TMNR Transmit Mailbox number record 24 2 read-only TM2CT Transmit mailbox 2 cancel transmission 23 1 read-write TM2TEF Transmit mailbox 2 transmission error flag 19 1 read-write TM2ALF Transmit mailbox 2 arbitration lost flag 18 1 read-write TM2TSF Transmit mailbox 2 transmission success flag 17 1 read-write TM2TCF transmit mailbox 2 transmission complete flag 16 1 read-write TM1CT Transmit mailbox 1 cancel transmission 15 1 read-write TM1TEF Transmit mailbox 1 transmission error flag 11 1 read-write TM1ALF Transmit mailbox 1 arbitration lost flag 10 1 read-write TM1TSF Transmit mailbox 1 transmission success flag 9 1 read-write TM1TCF Transmit mailbox 1 transmission complete flag 8 1 read-write TM0CT Transmit mailbox 0 cancel transmission 7 1 read-write TM0TEF Transmit mailbox 0 transmission error flag 3 1 read-write TM0ALF Transmit mailbox 0 arbitration lost flag 2 1 read-write TM0TSF Transmit mailbox 0 transmission success flag 1 1 read-write TM0TCF Transmit mailbox 0 transmission complete flag 0 1 read-write RF0 RF0 Receive FIFO 0 register 0xC 0x20 0x00000000 RF0R Receive FIFO 0 release 5 1 read-write RF0OF Receive FIFO 0 overflow flag 4 1 read-write RF0FF Receive FIFO 0 full flag 3 1 read-write RF0MN Receive FIFO 0 message num 0 2 read-only RF1 RF1 Receive FIFO 1 register 0x10 0x20 0x00000000 RF1R Receive FIFO 1 release 5 1 read-write RF1OF Receive FIFO 1 overflow flag 4 1 read-write RF1FF Receive FIFO 1 full flag 3 1 read-write RF1MN Receive FIFO 1 message num 0 2 read-only INTEN INTEN Interrupt enable register 0x14 0x20 read-write 0x00000000 EDZIEN Enter doze mode interrupt enable 17 1 QDZIEN Quit doze mode interrupt enable 16 1 EOIEN Error occur interrupt enable 15 1 ETRIEN Error type record interrupt enable 11 1 BOIEN Bus-off interrupt enable 10 1 EPIEN Error passive interrupt enable 9 1 EAIEN Error active interrupt enable 8 1 RF1OIEN Receive FIFO 1 overflow interrupt enable 6 1 RF1FIEN Receive FIFO 1 full interrupt enable 5 1 RF1MIEN FIFO 1 receive message interrupt enable 4 1 RF0OIEN Receive FIFO 0 overflow interrupt enable 3 1 RF0FIEN Receive FIFO 0 full interrupt enable 2 1 RF0MIEN FIFO 0 receive message interrupt enable 1 1 TCIEN Transmission complete interrupt enable 0 1 ESTS ESTS Error status register 0x18 0x20 0x00000000 REC Receive error counter 24 8 read-only TEC Transmit error counter 16 8 read-only ETR Error type record 4 3 read-write BOF Bus-off flag 2 1 read-only EPF Error passive flag 1 1 read-only EAF Error active flag 0 1 read-only BTMG BTMG Bit timing register 0x1C 0x20 read-write 0x00000000 LOEN Listen-Only mode 31 1 LBEN Loop back mode 30 1 RSAW Resynchronization adjust width 24 2 BTS2 Bit time segment 2 20 3 BTS1 Bit time segment 1 16 4 BRDIV Baud rate division 0 12 TMI0 TMI0 Transmit mailbox 0 identifier register 0x180 0x20 read-write 0x00000000 TMSID Transmit mailbox standard identifier or extended identifier high bytes 21 11 TMEID Ttransmit mailbox extended identifier 3 18 TMIDSEL Transmit mailbox identifier type select 2 1 TMFRSEL Transmit mailbox frame type select 1 1 TMSR Transmit mailbox send request 0 1 TMC0 TMC0 Transmit mailbox 0 data length and time stamp register 0x184 0x20 read-write 0x00000000 TMTS Transmit mailbox time stamp 16 16 TMTSTEN Transmit mailbox time stamp transmit enable 8 1 TMDTBL Transmit mailbox data byte length 0 4 TMDTL0 TMDTL0 Transmit mailbox 0 low byte data register 0x188 0x20 read-write 0x00000000 TMDT3 Transmit mailbox data byte 3 24 8 TMDT2 Transmit mailbox data byte 2 16 8 TMDT1 Transmit mailbox data byte 1 8 8 TMDT0 Transmit mailbox data byte 0 0 8 TMDTH0 TMDTH0 Transmit mailbox 0 high byte data register 0x18C 0x20 read-write 0x00000000 TMDT7 Transmit mailbox data byte 7 24 8 TMDT6 Transmit mailbox data byte 6 16 8 TMDT5 Transmit mailbox data byte 5 8 8 TMDT4 Transmit mailbox data byte 4 0 8 TMI1 TMI1 Transmit mailbox 1 identifier register 0x190 0x20 read-write 0x00000000 TMSID Transmit mailbox standard identifier or extended identifier high bytes 21 11 TMEID Ttransmit mailbox extended identifier 3 18 TMIDSEL Transmit mailbox identifier type select 2 1 TMFRSEL Transmit mailbox frame type select 1 1 TMSR Transmit mailbox send request 0 1 TMC1 TMC1 Transmit mailbox 1 data length and time stamp register 0x194 0x20 read-write 0x00000000 TMTS Transmit mailbox time stamp 16 16 TMTSTEN Transmit mailbox time stamp transmit enable 8 1 TMDTBL Transmit mailbox data byte length 0 4 TMDTL1 TMDTL1 Transmit mailbox 1 low byte data register 0x198 0x20 read-write 0x00000000 TMDT3 Transmit mailbox data byte 3 24 8 TMDT2 Transmit mailbox data byte 2 16 8 TMDT1 Transmit mailbox data byte 1 8 8 TMDT0 Transmit mailbox data byte 0 0 8 TMDTH1 TMDTH1 Transmit mailbox 1 high byte data register 0x19C 0x20 read-write 0x00000000 TMDT7 Transmit mailbox data byte 7 24 8 TMDT6 Transmit mailbox data byte 6 16 8 TMDT5 Transmit mailbox data byte 5 8 8 TMDT4 Transmit mailbox data byte 4 0 8 TMI2 TMI2 Transmit mailbox 2 identifier register 0x1A0 0x20 read-write 0x00000000 TMSID Transmit mailbox standard identifier or extended identifier high bytes 21 11 TMEID Ttransmit mailbox extended identifier 3 18 TMIDSEL Transmit mailbox identifier type select 2 1 TMFRSEL Transmit mailbox frame type select 1 1 TMSR Transmit mailbox send request 0 1 TMC2 TMC2 Transmit mailbox 2 data length and time stamp register 0x1A4 0x20 read-write 0x00000000 TMTS Transmit mailbox time stamp 16 16 TMTSTEN Transmit mailbox time stamp transmit enable 8 1 TMDTBL Transmit mailbox data byte length 0 4 TMDTL2 TMDTL2 Transmit mailbox 2 low byte data register 0x1A8 0x20 read-write 0x00000000 TMDT3 Transmit mailbox data byte 3 24 8 TMDT2 Transmit mailbox data byte 2 16 8 TMDT1 Transmit mailbox data byte 1 8 8 TMDT0 Transmit mailbox data byte 0 0 8 TMDTH2 TMDTH2 Transmit mailbox 2 high byte data register 0x1AC 0x20 read-write 0x00000000 TMDT7 Transmit mailbox data byte 7 24 8 TMDT6 Transmit mailbox data byte 6 16 8 TMDT5 Transmit mailbox data byte 5 8 8 TMDT4 Transmit mailbox data byte 4 0 8 RFI0 RFI0 Receive FIFO 0 register 0x1B0 0x20 read-only 0x00000000 RFSID Receive FIFO standard identifier or receive FIFO extended identifier 21 11 RFEID Receive FIFO extended identifier 3 18 RFIDI Receive FIFO identifier type indication 2 1 RFFRI Receive FIFO frame type indication 1 1 RFC0 RFC0 Receive FIFO 0 data length and time stamp register 0x1B4 0x20 read-only 0x00000000 RFTS Receive FIFO time stamp 16 16 RFFMN Receive FIFO filter match number 8 8 RFDTL Receive FIFO data length 0 4 RFDTL0 RFDTL0 Receive FIFO 0 low byte data register 0x1B8 0x20 read-only 0x00000000 RFDT3 Receive FIFO data byte 3 24 8 RFDT2 Receive FIFO data byte 2 16 8 RFDT1 Receive FIFO data byte 1 8 8 RFDT0 Receive FIFO data byte 0 0 8 RFDTH0 RFDTH0 Receive FIFO 0 high byte data register 0x1BC 0x20 read-only 0x00000000 RFDT7 Receive FIFO data byte 7 24 8 RFDT6 Receive FIFO data byte 6 16 8 RFDT5 Receive FIFO data byte 5 8 8 RFDT4 Receive FIFO data byte 4 0 8 RFI1 RFI1 Receive FIFO 1 register 0x1C0 0x20 read-only 0x00000000 RFSID Receive FIFO standard identifier or receive FIFO extended identifier 21 11 RFEID Receive FIFO extended identifier 3 18 RFIDI Receive FIFO identifier type indication 2 1 RFFRI Receive FIFO frame type indication 1 1 RFC1 RFC1 Receive FIFO 1 data length and time stamp register 0x1C4 0x20 read-only 0x00000000 RFTS Receive FIFO time stamp 16 16 RFFMN Receive FIFO filter match number 8 8 RFDTL Receive FIFO data length 0 4 RFDTL1 RFDTL1 Receive FIFO 1 low byte data register 0x1C8 0x20 read-only 0x00000000 RFDT3 Receive FIFO data byte 3 24 8 RFDT2 Receive FIFO data byte 2 16 8 RFDT1 Receive FIFO data byte 1 8 8 RFDT0 Receive FIFO data byte 0 0 8 RFDTH1 RFDTH1 Receive FIFO 1 high byte data register 0x1CC 0x20 read-only 0x00000000 RFDT7 Receive FIFO data byte 7 24 8 RFDT6 Receive FIFO data byte 6 16 8 RFDT5 Receive FIFO data byte 5 8 8 RFDT4 Receive FIFO data byte 4 0 8 FCTRL FCTRL Filter control register 0x200 0x20 read-write 0x00000000 FCS Filters configure switch 0 1 FMCFG FMCFG Filter mode config register 0x204 0x20 read-write 0x00000000 FMSEL0 Filter mode select 0 1 FMSEL1 Filter mode select 1 1 FMSEL2 Filter mode select 2 1 FMSEL3 Filter mode select 3 1 FMSEL4 Filter mode select 4 1 FMSEL5 Filter mode select 5 1 FMSEL6 Filter mode select 6 1 FMSEL7 Filter mode select 7 1 FMSEL8 Filter mode select 8 1 FMSEL9 Filter mode select 9 1 FMSEL10 Filter mode select 10 1 FMSEL11 Filter mode select 11 1 FMSEL12 Filter mode select 12 1 FMSEL13 Filter mode select 13 1 FBWCFG FBWCFG Filter bit width config register 0x20C 0x20 read-write 0x00000000 FBWSEL0 Filter bit width select 0 1 FBWSEL1 Filter bit width select 1 1 FBWSEL2 Filter bit width select 2 1 FBWSEL3 Filter bit width select 3 1 FBWSEL4 Filter bit width select 4 1 FBWSEL5 Filter bit width select 5 1 FBWSEL6 Filter bit width select 6 1 FBWSEL7 Filter bit width select 7 1 FBWSEL8 Filter bit width select 8 1 FBWSEL9 Filter bit width select 9 1 FBWSEL10 Filter bit width select 10 1 FBWSEL11 Filter bit width select 11 1 FBWSEL12 Filter bit width select 12 1 FBWSEL13 Filter bit width select 13 1 FRF FRF Filter related FIFO register 0x214 0x20 read-write 0x00000000 FRFSEL0 Filter relation FIFO select 0 1 FRFSEL1 Filter relation FIFO select 1 1 FRFSEL2 Filter relation FIFO select 2 1 FRFSEL3 Filter relation FIFO select 3 1 FRFSEL4 Filter relation FIFO select 4 1 FRFSEL5 Filter relation FIFO select 5 1 FRFSEL6 Filter relation FIFO select 6 1 FRFSEL7 Filter relation FIFO select 7 1 FRFSEL8 Filter relation FIFO select 8 1 FRFSEL9 Filter relation FIFO select 9 1 FRFSEL10 Filter relation FIFO select 10 1 FRFSEL11 Filter relation FIFO select 11 1 FRFSEL12 Filter relation FIFO select 12 1 FRFSEL13 Filter relation FIFO select 13 1 FACFG FACFG Filter activate configuration register 0x21C 0x20 read-write 0x00000000 FAEN0 Filter activate enable 0 1 FAEN1 Filter activate enable 1 1 FAEN2 Filter activate enable 2 1 FAEN3 Filter activate enable 3 1 FAEN4 Filter activate enable 4 1 FAEN5 Filter activate enable 5 1 FAEN6 Filter activate enable 6 1 FAEN7 Filter activate enable 7 1 FAEN8 Filter activate enable 8 1 FAEN9 Filter activate enable 9 1 FAEN10 Filter activate enable 10 1 FAEN11 Filter activate enable 11 1 FAEN12 Filter activate enable 12 1 FAEN13 Filter activate enable 13 1 F0FB1 F0FB1 Filter bank 0 filtrate bit register 1 0x240 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F0FB2 F0FB2 Filter bank 0 filtrate bit register 2 0x244 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F1FB1 F1FB1 Filter bank 1 filtrate bit register 1 0x248 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F1FB2 F1FB2 Filter bank 1 filtrate bit register 2 0x24C 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F2FB1 F2FB1 Filter bank 2 filtrate bit register 1 0x250 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F2FB2 F2FB2 Filter bank 2 filtrate bit register 2 0x254 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F3FB1 F3FB1 Filter bank 3 filtrate bit register 1 0x258 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F3FB2 F3FB2 Filter bank 3 filtrate bit register 2 0x25C 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F4FB1 F4FB1 Filter bank 4 filtrate bit register 1 0x260 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F4FB2 F4FB2 Filter bank 4 filtrate bit register 2 0x264 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F5FB1 F5FB1 Filter bank 5 filtrate bit register 1 0x268 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F5FB2 F5FB2 Filter bank 5 filtrate bit register 2 0x26C 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F6FB1 F6FB1 Filter bank 6 filtrate bit register 1 0x270 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F6FB2 F6FB2 Filter bank 6 filtrate bit register 2 0x274 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F7FB1 F7FB1 Filter bank 7 filtrate bit register 1 0x278 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F7FB2 F7FB2 Filter bank 7 filtrate bit register 2 0x27C 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F8FB1 F8FB1 Filter bank 8 filtrate bit register 1 0x280 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F8FB2 F8FB2 Filter bank 8 filtrate bit register 2 0x284 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F9FB1 F9FB1 Filter bank 9 filtrate bit register 1 0x288 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F9FB2 F9FB2 Filter bank 9 filtrate bit register 2 0x28C 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F10FB1 F10FB1 Filter bank 10 filtrate bit register 1 0x290 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F10FB2 F10FB2 Filter bank 10 filtrate bit register 2 0x294 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F11FB1 F11FB1 Filter bank 11 filtrate bit register 1 0x298 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F11FB2 F11FB2 Filter bank 11 filtrate bit register 2 0x29C 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F12FB1 F12FB1 Filter bank 12 filtrate bit register 1 0x2A0 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F12FB2 F12FB2 Filter bank 12 filtrate bit register 2 0x2A4 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F13FB1 F13FB1 Filter bank 13 filtrate bit register 1 0x2A8 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 F13FB2 F13FB2 Filter bank 13 filtrate bit register 2 0x2AC 0x20 read-write 0x00000000 FFDB0 Filter data bit 0 1 FFDB1 Filter data bit 1 1 FFDB2 Filter data bit 2 1 FFDB3 Filter data bit 3 1 FFDB4 Filter data bit 4 1 FFDB5 Filter data bit 5 1 FFDB6 Filter data bit 6 1 FFDB7 Filter data bit 7 1 FFDB8 Filter data bit 8 1 FFDB9 Filter data bit 9 1 FFDB10 Filter data bit 10 1 FFDB11 Filter data bit 11 1 FFDB12 Filter data bit 12 1 FFDB13 Filter data bit 13 1 FFDB14 Filter data bit 14 1 FFDB15 Filter data bit 15 1 FFDB16 Filter data bit 16 1 FFDB17 Filter data bit 17 1 FFDB18 Filter data bit 18 1 FFDB19 Filter data bit 19 1 FFDB20 Filter data bit 20 1 FFDB21 Filter data bit 21 1 FFDB22 Filter data bit 22 1 FFDB23 Filter data bit 23 1 FFDB24 Filter data bit 24 1 FFDB25 Filter data bit 25 1 FFDB26 Filter data bit 26 1 FFDB27 Filter data bit 27 1 FFDB28 Filter data bit 28 1 FFDB29 Filter data bit 29 1 FFDB30 Filter data bit 30 1 FFDB31 Filter data bit 31 1 DEBUG Debug support DEBUG 0xE0042000 0x0 0x400 registers IDCODE IDCODE DEBUG IDCODE 0x0 0x20 read-only 0x0 PID Product ID 0 32 CTRL CTRL DEBUG CTRL 0x4 0x20 read-write 0x0 SLEEP_DEBUG SLEEP_DEBUG 0 1 DEEPSLEEP_DEBUG DEEPSLEEP_DEBUG 1 1 STANDBY_DEBUG STANDBY_DEBUG 2 1 APB1_PAUSE APB1_PAUSE DEBUG APB1 PAUSE 0x8 0x20 read-write 0x0 TMR2_PAUSE TMR2_PAUSE 0 1 TMR3_PAUSE TMR3_PAUSE 1 1 TMR4_PAUSE TMR4_PAUSE 2 1 TMR6_PAUSE TMR6_PAUSE 4 1 TMR7_PAUSE TMR7_PAUSE 5 1 TMR13_PAUSE TMR13_PAUSE 7 1 TMR14_PAUSE TMR14_PAUSE 8 1 ERTC_PAUSE ERTC_PAUSE 10 1 WWDT_PAUSE WWDT_PAUSE 11 1 WDT_PAUSE WDT_PAUSE 12 1 ERTC512_PAUSE ERTC512_PAUSE 15 1 I2C1_SMBUS_TIMEOUT I2C1_SMBUS_TIMEOUT 24 1 CAN1_PAUSE CAN1_PAUSE 25 1 I2C2_SMBUS_TIMEOUT I2C2_SMBUS_TIMEOUT 27 1 I2C3_SMBUS_TIMEOUT I2C3_SMBUS_TIMEOUT 28 1 APB2_PAUSE APB2_PAUSE DEBUG APB2 PAUSE 0xC 0x20 read-write 0x0 TMR1_PAUSE TMR1_PAUSE 0 1 TMR9_PAUSE TMR9_PAUSE 16 1 TMR10_PAUSE TMR10_PAUSE 17 1 TMR11_PAUSE TMR11_PAUSE 18 1 CRC CRC calculation unit CRC 0x40023000 0x0 0x400 registers DT DT Data register 0x0 0x20 read-write 0xFFFFFFFF DT Data Register 0 32 CDT CDT Common data register 0x4 0x20 read-write 0x00000000 CDT Common Data 0 1 CTRL CTRL Control register 0x8 0x20 read-write 0x00000000 RST Reset bit 0 1 POLY_SIZE Polynomial size 3 2 REVID Reverse input data 5 2 REVOD Reverse output data 7 1 IDT IDT Initial data register 0x10 0x20 read-write 0xFFFFFFFF IDT Initial Data 0 32 POLY POLY Polynomial coefficient register 0x14 0x20 read-write 0x04C11DB7 POLY polynomial coefficient 0 32 FLASH Flash memory controler FLASH 0x40023C00 0x0 0x400 registers FLASH Flash global interrupt 4 PSR PSR Performance selection register 0x0 0x20 0x00000030 WTCYC Wait cycle 0 3 read-write PFT_EN Prefetch enable 4 1 read-write PFT_ENF Prefetch enabled flag 5 1 read-only PFT_EN2 Prefetch enable 2 6 1 read-write PFT_ENF2 Prefetch enabled flag 2 7 1 read-only PFT_LAT_DIS Prefetch latency disable 8 1 read-write UNLOCK UNLOCK Unlock register 0x4 0x20 write-only 0x00000000 UKVAL Unlock key value 0 32 USD_UNLOCK USD_UNLOCK USD unlock register 0x8 0x20 write-only 0x00000000 USD_UKVAL User system data Unlock key value 0 32 STS STS Status register 0xC 0x20 0x00000000 ODF Operate done flag 5 1 read-write EPPERR Erase/program protection error 4 1 read-write PRGMERR program error 2 1 read-write OBF Operate busy flag 0 1 read-only CTRL CTRL Control register 0x10 0x20 read-write 0x00020080 FPRGM Flash program 0 1 SECERS Sector erase 1 1 BANKERS Bank erase 2 1 USDPRGM User system data program 4 1 USDERS User system data erase 5 1 ERSTR Erasing start 6 1 OPLK Operation lock 7 1 USDULKS User system data unlock success 9 1 ERRIE Error interrupt enable 10 1 ODFIE Operation done flag interrupt enable 12 1 ADDR ADDR Address register 0x14 0x20 write-only 0x00000000 FA Flash Address 0 32 USD USD User system data register 0x1C 0x20 read-only 0x03FFFFFC USDERR User system data error 0 1 FAP FLASH access protection 1 1 nWDT_ATO_EN WDT auto enable 2 1 nDEPSLP_RST Deepsleep reset 3 1 nSTDBY_RST Standby reset 4 1 nBOOT1 boot1 6 1 nDEPSLP_WDT Deepsleep wdt stop count 7 1 nSTDBY_WDT Standby wdt stop count 8 1 nRAM_PRT_CHK SRAM parity check 9 1 USER_D0 User data 0 10 8 USER_D1 User data 1 18 8 FAP_HL FAP high level 26 1 EPPS EPPS Erase/program protection status register 0x20 0x20 read-only 0xFFFFFFFF EPPS Erase/program protection status 0 32 SLIB_STS0 SLIB_STS0 sLib status 0 register 0x74 0x20 0x00000000 BTM_AP_ENF Boot memory store application code enabled flag 0 1 EM_SLIB_ENF Extension memory sLib enabled flag 2 1 SLIB_ENF sLib enabled flag 3 1 EM_SLIB_INST_SS Extension memory sLib instruction start sector 16 8 SLIB_STS1 SLIB_STS1 sLib status 1 register 0x78 0x20 0x00000000 SLIB_SS sLib start sector 0 11 SLIB_INST_SS sLib instruction start sector 11 11 SLIB_ES sLib end sector 22 10 SLIB_PWD_CLR SLIB_PWD_CLR SLIB password clear register 0x7C 0x20 0x00000000 write-only SLIB_PCLR_VAL sLib password clear value 0 32 SLIB_MISC_STS SLIB_MISC_STS sLib misc status register 0x80 0x20 0x01000000 SLIB_PWD_ERR sLib password error 0 1 read-only SLIB_PWD_OK sLib password ok 1 1 read-only SLIB_ULKF sLib unlock flag 2 1 read-only CRC_ADDR CRC_ADDR Flash CRC data start address register 0x84 0x20 write-only 0x00000000 CRC_ADDR CRC address 0 32 CRC_CTRL CRC_CTRL Flash CRC controll register 0x88 0x20 0x00000000 CRC_SN CRC sector numbler 0 16 read-write CRC_STRT CRC start 16 1 write-only CRC_CHKR CRC_CHKR FLASH CRC check result register 0x8C 0x20 read-only 0x00000000 FCRC_OUT CRC32 verification result of flash user code or SLIB code 0 32 SLIB_SET_PWD SLIB_SET_PWD sLib password setting register 0x160 0x20 write-only 0x00000000 SLIB_PSET_VAL sLib password setting val 0 32 SLIB_SET_RANGE SLIB_SET_RANGE Configure sLib range register 0x164 0x20 write-only 0x00000000 SLIB_SS_SET sLib start sector setting 0 11 SLIB_ISS_SET sLib instruction start sector setting 11 11 SLIB_ES_SET sLib end sector setting 22 10 EM_SLIB_SET EM_SLIB_SET Extension momery slib set register 0x168 0x20 write-only 0x00000000 EM_SLIB_SET Extension memory sLib setting 0 16 EM_SLIB_ISS_SET Extension memory sLib instruction start sector setting 16 8 BTM_MODE_SET BTM_MODE_SET Boot memory mode setting register 0x16C 0x20 write-only 0x00000000 BTM_MODE_SET Boot memory mode setting 0 8 SLIB_UNLOCK SLIB_UNLOCK sLib unlock register 0x170 0x20 write-only 0x00000000 SLIB_UKVAL sLib unlock key value 0 32 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E000 0x0 0x1001 registers ICTR ICTR Interrupt Controller Type Register 0x4 0x20 read-only 0x00000000 INTLINESNUM Total number of interrupt lines in groups 0 4 STIR STIR Software Triggered Interrupt Register 0xF00 0x20 write-only 0x00000000 INTID interrupt to be triggered 0 9 ISER0 ISER0 Interrupt Set-Enable Register 0x100 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER1 ISER1 Interrupt Set-Enable Register 0x104 0x20 read-write 0x00000000 SETENA SETENA 0 32 ICER0 ICER0 Interrupt Clear-Enable Register 0x180 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER1 ICER1 Interrupt Clear-Enable Register 0x184 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ISPR0 ISPR0 Interrupt Set-Pending Register 0x200 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR1 ISPR1 Interrupt Set-Pending Register 0x204 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ICPR0 ICPR0 Interrupt Clear-Pending Register 0x280 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR1 ICPR1 Interrupt Clear-Pending Register 0x284 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 IABR0 IABR0 Interrupt Active Bit Register 0x300 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR1 IABR1 Interrupt Active Bit Register 0x304 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IPR0 IPR0 Interrupt Priority Register 0x400 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR1 IPR1 Interrupt Priority Register 0x404 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR2 IPR2 Interrupt Priority Register 0x408 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR3 IPR3 Interrupt Priority Register 0x40C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR4 IPR4 Interrupt Priority Register 0x410 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR5 IPR5 Interrupt Priority Register 0x414 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR6 IPR6 Interrupt Priority Register 0x418 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR7 IPR7 Interrupt Priority Register 0x41C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR8 IPR8 Interrupt Priority Register 0x420 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR9 IPR9 Interrupt Priority Register 0x424 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR10 IPR10 Interrupt Priority Register 0x428 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR11 IPR11 Interrupt Priority Register 0x42C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR12 IPR12 Interrupt Priority Register 0x430 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR13 IPR13 Interrupt Priority Register 0x434 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR14 IPR14 Interrupt Priority Register 0x438 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 DVP Digital video parallel interface DVP 0x50050000 0x0 0x400 registers DVP DVP global interrupt 78 CTRL CTRL Control register 0x0 0x20 0x0000 LCDS Line capture/drop selection 20 1 read-write LCDC Line capture/drop control 19 1 read-write PCDS Pixel capture/drop selection 18 1 read-write PCDC Basic pixel capture/drop control 16 2 read-write ENA DVP enable 14 1 read-write PDL Pixel data length 10 2 read-write BFRC Basic frame rate control 8 2 read-write VSP Vertical synchronization polarity 7 1 read-write HSP Horizontal synchronization polarity 6 1 read-write CKP Pixel clock polarity 5 1 read-write SM synchronization mode 4 1 read-write JPEG JPEG format 3 1 read-write CRP Cropping function enable 2 1 read-write CFM Capture fire mode 1 1 read-write CAP Capture function enable 0 1 read-write STS STS status register 0x4 0x20 read-only 0x0000 OFNE Output FIFO Non-empty 2 1 VSYN Vertical synchronization status 1 1 HSYN Horizontal synchronization status 0 1 ESTS ESTS Event status register 0x8 0x20 read-only 0x0000 HSES Horizontal synchronization event status 4 1 VSES Vertical synchronization event status 3 1 ESEES Embedded synchronization error event status 2 1 OVRES Data FIFO overrun event status 1 1 CFDES Capture frame done event status 0 1 IENA IENA interrupt enable register 0xC 0x20 read-write 0x0000 HSIE Horizontal synchronization interrupt enable 4 1 VSIE Vertical synchronization interrupt enablee 3 1 ESEIE Embedded synchronization error interrupt enable 2 1 OVRIE Data FIFO overrun interrupt enable 1 1 CFDIE Capture frame done interrupt enable 0 1 ISTS ISTS Interrupt status register 0x10 0x20 read-only 0x0000 HSIS Horizontal synchronization interrupt status 4 1 VSIS Vertical synchronization interrupt status 3 1 ESEIS Embedded synchronization error interrupt status 2 1 OVRIS Data FIFO overrun interrupt status 1 1 CFDIS Capture frame done interrupt status 0 1 ICLR ICLR Interrupt clear register 0x14 0x20 write-only 0x0000 HSIC Horizontal synchronization interrupt clear 4 1 VSIC Vertical synchronization interrupt clear 3 1 ESEIC Embedded synchronization error interrupt clear 2 1 OVRIC Data FIFO overrun interrupt clear 1 1 CFDIC Capture frame done interrupt clear 0 1 SCR SCR Synchronization code register 0x18 0x20 read-write 0x0000 FMEC Frame end code 24 8 LNEC Line end code 16 8 LNSC Line start code 8 8 FMSC Frame start code 0 8 SUR SUR Synchronization unmask register 0x1C 0x20 read-write 0x0000 FMEU Frame end unmask 24 8 LNEU Line end unmask 16 8 LNSU Line start unmask 8 8 FMSU Frame start unmask 0 8 CWST CWST Crop window start 0x20 0x20 read-write 0x0000 CVSTR Cropping window vertical start line 16 13 CHSTR Cropping window horizontal start pixel 0 14 CWSZ CWSZ Crop window size 0x24 0x20 read-write 0x0000 CVNUM Cropping window vertical line number 16 14 CHNUM Cropping window horizontal pixel number 0 14 DT DT Data register 0x28 0x20 read-only 0x0000 DT Data Port 0 32 ACTRL ACTRL Advanced Control register 0x40 0x20 read-write 0x0000 VSEID Vertical synchonization event and interrupt definition 17 1 HSEID Horizontal synchonization event and interrupt definition 16 1 DMABT DMA burst transfer configuration 12 1 IDUS Input data un-used setting 10 1 IDUN Input data un-used number 8 2 EFDM Enhanced function data format management 6 1 EFDF Enhanced function data format 4 2 PCDES Basic pixel capture/drop extended selection 3 1 MIBE Monochrome image binarization enable 2 1 EFRCE Enhanced frame rate control enable 1 1 EISRE Enhanced image scaling resize enable 0 1 HSCF HSCF Horizontal scaling control flow 0x48 0x20 read-write 0x0000 HSRTF Horizontal scaling resize target factor 16 13 HSRSF Horizontal scaling resize source factor 0 13 VSCF VSCF Vertical scaling control flow 0x4C 0x20 read-write 0x0000 VSRTF Vertical scaling resize target factor 16 13 VSRSF Vertical scaling resize source factor 0 13 FRF FRF Frame rate flow 0x50 0x20 read-write 0x0000 EFRCTF Enhanced frame rate control target factor 8 5 EFRCSF Enhanced frame rate contorl source factor 0 5 BTH BTH Binarization threshold 0x54 0x20 read-write 0x0000 MIBTHD Monochrome image binarization threshold 0 8 USB_OTGFS_GLOBAL USB on-the-go full speed USB_OTGFS 0x50000000 0x0 0x400 registers OTGFS USB On The Go FS global interrupt 67 GOTGCTL GOTGCTL OTGFS control and status register (OTGFS_GOTGCTL) 0x0 0x20 0x00000800 CONIDSTS Connector ID status 16 1 read-only CURMOD Current Mode of Operation 21 1 read-only GOTGINT GOTGINT OTGFS interrupt register (OTGFS_GOTGINT) 0x4 0x20 0x00000000 SESENDDET VBUS is deasserted 2 1 read-write GAHBCFG GAHBCFG OTGFS AHB configuration register (OTGFS_GAHBCFG) 0x8 0x20 read-write 0x00000000 GLBINTMSK Global interrupt mask 0 1 NPTXFEMPLVL Non-Periodic TxFIFO empty level 7 1 PTXFEMPLVL Periodic TxFIFO empty level 8 1 GUSBCFG GUSBCFG USB configuration register (OTGFS_GUSBCFG) 0xC 0x20 0x00000A00 TOUTCAL FS timeout calibration 0 3 read-write USBTRDTIM USB turnaround time 10 4 read-write FHSTMODE Force host mode 29 1 read-write FDEVMODE Force device mode 30 1 read-write COTXPKT Corrupt Tx packet 31 1 read-write GRSTCTL GRSTCTL OTGFS reset register (OTGFS_GRSTCTL) 0x10 0x20 0x20000000 CSFTRST Core soft reset 0 1 read-write PIUSFTRST PIU FS Dedicated Controller Soft Reset 1 1 read-write FRMCNTRST Host frame counter reset 2 1 read-write RXFFLSH RxFIFO flush 4 1 read-write TXFFLSH TxFIFO flush 5 1 read-write TXFNUM TxFIFO number 6 5 read-write AHBIDLE AHB master idle 31 1 read-only GINTSTS GINTSTS OTGFS core interrupt register (OTGFS_GINTSTS) 0x14 0x20 0x04000020 CURMOD Current mode of operation 0 1 read-only MODEMIS Mode mismatch interrupt 1 1 read-write OTGINT OTG interrupt 2 1 read-only SOF Start of frame 3 1 read-write RXFLVL RxFIFO non-empty 4 1 read-only NPTXFEMP Non-periodic TxFIFO empty 5 1 read-only GINNAKEFF Global IN non-periodic NAK effective 6 1 read-only GOUTNAKEFF Global OUT NAK effective 7 1 read-only ERLYSUSP Early suspend 10 1 read-write USBSUSP USB suspend 11 1 read-write USBRST USB reset 12 1 read-write ENUMDONE Enumeration done 13 1 read-write ISOOUTDROP Isochronous OUT packet dropped interrupt 14 1 read-write EOPF End of periodic frame interrupt 15 1 read-write IEPTINT IN endpoint interrupt 18 1 read-only OEPTINT OUT endpoint interrupt 19 1 read-only INCOMPISOIN Incomplete isochronous IN transfer 20 1 read-write INCOMPIP_INCOMPISOOUT Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) 21 1 read-write PRTINT Host port interrupt 24 1 read-only HCHINT Host channels interrupt 25 1 read-only PTXFEMP Periodic TxFIFO empty 26 1 read-only CONIDSCHG Connector ID status change 28 1 read-write DISCONINT Disconnect detected interrupt 29 1 read-write WKUPINT Resume/remote wakeup detected interrupt 31 1 read-write GINTMSK GINTMSK OTG_FS interrupt mask register (OTG_FS_GINTMSK) 0x18 0x20 0x00000000 MODEMISMSK Mode mismatch interrupt mask 1 1 read-write OTGINTMSK OTG interrupt mask 2 1 read-write SOFMSK Start of frame mask 3 1 read-write RXFLVLMSK Receive FIFO non-empty mask 4 1 read-write NPTXFEMPMSK Non-periodic TxFIFO empty mask 5 1 read-write GINNAKEFFMSK Global non-periodic IN NAK effective mask 6 1 read-write GOUTNAKEFFMSK Global OUT NAK effective mask 7 1 read-write ERLYSUSPMSK Early suspend mask 10 1 read-write USBSUSPMSK USB suspend mask 11 1 read-write USBRSTMSK USB reset mask 12 1 read-write ENUMDONEMSK Enumeration done mask 13 1 read-write ISOOUTDROPMSK Isochronous OUT packet dropped interrupt mask 14 1 read-write EOPFMSK End of periodic frame interrupt mask 15 1 read-write IEPTINTMSK IN endpoints interrupt mask 18 1 read-write OEPTINTMSK OUT endpoints interrupt mask 19 1 read-write INCOMISOINMSK Incomplete isochronous IN transfer mask 20 1 read-write INCOMPIP_INCOMPISOOUTMSK Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) 21 1 read-write PRTINTMSK Host port interrupt mask 24 1 read-write HCHINTMSK Host channels interrupt mask 25 1 read-write PTXFEMPMSK Periodic TxFIFO empty mask 26 1 read-write CONIDSCHGMSK Connector ID status change mask 28 1 read-write DISCONINTMSK Disconnect detected interrupt mask 29 1 read-write WKUPINTMSK Resume/remote wakeup detected interrupt mask 31 1 read-write GRXSTSR_Device GRXSTSR_Device OTGFS Receive status debug read(Device mode) 0x1C 0x20 read-only 0x00000000 EPTNUM Endpoint number 0 4 BCNT Byte count 4 11 DPID Data PID 15 2 PKTSTS Packet status 17 4 FN Frame number 21 4 GRXSTSR_Host GRXSTSR_Host OTGFS Receive status debug read(Host mode) GRXSTSR_Device 0x1C 0x20 read-only 0x00000000 CHNUM Channel number 0 4 BCNT Byte count 4 11 DPID Data PID 15 2 PKTSTS Packet status 17 4 GRXFSIZ GRXFSIZ OTGFS Receive FIFO size register (OTGFS_GRXFSIZ) 0x24 0x20 read-write 0x00000200 RXFDEP RxFIFO depth 0 16 DIEPTXF0 DIEPTXF0 IN Endpoint TxFIFO 0 transmit FIFO size register (Device mode) 0x28 0x20 read-write 0x00000200 INEPT0TXSTADDR Endpoint 0 transmit RAM start address 0 16 INEPT0TXDEP Endpoint 0 TxFIFO depth 16 16 GNPTXFSIZ GNPTXFSIZ OTGFS non-periodic transmit FIFO size register (Host mode) DIEPTXF0 0x28 0x20 read-write 0x00000200 NPTXFSTADDR Non-periodic Transmit RAM Start address 0 16 NPTXFDEP Non-periodic TxFIFO depth 16 16 GNPTXSTS GNPTXSTS OTGFS non-periodic transmit FIFO/queue status register (OTGFS_GNPTXSTS) 0x2C 0x20 read-only 0x00080200 NPTXFSPCAVAIL Non-periodic TxFIFO space available 0 16 NPTXQSPCAVAIL Non-periodic transmit request queue space available 16 8 NPTXQTOP Top of the non-periodic transmit request queue 24 7 GCCFG GCCFG OTGFS general core configuration register (OTGFS_GCCFG) 0x38 0x20 read-write 0x00000000 PWRDOWN Power down 16 1 LP_MODE Low power mode 17 1 SOFOUTEN SOF output enable 20 1 VBUSIG VBUS Ignored 21 1 GUID GUID Product ID register 0x3C 0x20 read-write 0x00001000 USERID Product ID field 0 32 HPTXFSIZ HPTXFSIZ OTGFS Host periodic transmit FIFO size register (OTGFS_HPTXFSIZ) 0x100 0x20 read-write 0x02000600 PTXFSTADDR Host periodic TxFIFO start address 0 16 PTXFSIZE Host periodic TxFIFO depth 16 16 DIEPTXF1 DIEPTXF1 OTGFS device IN endpoint transmit FIFO size register (OTGFS_DIEPTXF1) 0x104 0x20 read-write 0x02000400 INEPTXFSTADDR IN endpoint FIFO1 transmit RAM start address 0 16 INEPTXFDEP IN endpoint TxFIFO depth 16 16 DIEPTXF2 DIEPTXF2 OTGFS device IN endpoint transmit FIFO size register (OTGFS_DIEPTXF2) 0x108 0x20 read-write 0x02000400 INEPTXFSTADDR IN endpoint FIFO2 transmit RAM start address 0 16 INEPTXFDEP IN endpoint TxFIFO depth 16 16 DIEPTXF3 DIEPTXF3 OTGFS device IN endpoint transmit FIFO size register (OTGFS_DIEPTXF3) 0x10C 0x20 read-write 0x02000400 INEPTXFSTADDR IN endpoint FIFO3 transmit RAM start address 0 16 INEPTXFDEP IN endpoint TxFIFO depth 16 16 DIEPTXF4 DIEPTXF4 OTGFS device IN endpoint transmit FIFO size register (OTGFS_DIEPTXF4) 0x110 0x20 read-write 0x02000400 INEPTXFSTADDR IN endpoint FIFO4 transmit RAM start address 0 16 INEPTXFDEP IN endpoint TxFIFO depth 16 16 DIEPTXF5 DIEPTXF5 OTGFS device IN endpoint transmit FIFO size register (OTGFS_DIEPTXF5) 0x114 0x20 read-write 0x02000400 INEPTXFSTADDR IN endpoint FIFO5 transmit RAM start address 0 16 INEPTXFDEP IN endpoint TxFIFO depth 16 16 DIEPTXF6 DIEPTXF6 OTGFS device IN endpoint transmit FIFO size register (OTGFS_DIEPTXF6) 0x118 0x20 read-write 0x02000400 INEPTXFSTADDR IN endpoint FIFO6 transmit RAM start address 0 16 INEPTXFDEP IN endpoint TxFIFO depth 16 16 DIEPTXF7 DIEPTXF7 OTGFS device IN endpoint transmit FIFO size register (OTGFS_DIEPTXF7) 0x11C 0x20 read-write 0x02000400 INEPTXFSTADDR IN endpoint FIFO7 transmit RAM start address 0 16 INEPTXFDEP IN endpoint TxFIFO depth 16 16 USB_OTG1_HOST USB on the go full speed USB_OTGFS 0x50000400 0x0 0x400 registers HCFG HCFG OTGFS host configuration register (OTGFS_HCFG) 0x0 0x20 0x00000000 FSLSPCLKSEL FS/LS PHY clock select 0 2 read-write FSLSSUPP FS- and LS-only support 2 1 read-only HFIR HFIR OTGFS Host frame interval register 0x4 0x20 read-write 0x0000EA60 FRINT Frame interval 0 16 HFNUM HFNUM OTGFS host frame number/frame time remaining register (OTGFS_HFNUM) 0x8 0x20 read-only 0x00003FFF FRNUM Frame number 0 16 FTREM Frame time remaining 16 16 HPTXSTS HPTXSTS OTGFS_Host periodic transmit FIFO/queue status register (OTGFS_HPTXSTS) 0x10 0x20 0x00080100 PTXFSPCAVAIL Periodic transmit data FIFO space available 0 16 read-write PTXQSPCAVAIL Periodic transmit request queue space available 16 8 read-only PTXQTOP Top of the periodic transmit request queue 24 8 read-only HAINT HAINT OTGFS Host all channels interrupt register 0x14 0x20 read-only 0x00000000 HAINT Channel interrupts 0 16 HAINTMSK HAINTMSK OTGFS host all channels interrupt mask register 0x18 0x20 read-write 0x00000000 HAINTMSK Channel interrupt mask 0 16 HPRT HPRT OTGFS host port control and status register (OTGFS_HPRT) 0x40 0x20 0x00000000 PRTCONSTS Port connect status 0 1 read-only PRTCONDET Port connect detected 1 1 read-write PRTENA Port enable 2 1 read-write PRTENCHNG Port enable/disable change 3 1 read-write PRTOVRCACT Port overcurrent active 4 1 read-only PRTOVRCCHNG Port overcurrent change 5 1 read-write PRTRES Port resume 6 1 read-write PRTSUSP Port suspend 7 1 read-write PRTRST Port reset 8 1 read-write PRTLNSTS Port line status 10 2 read-only PRTPWR Port power 12 1 read-write PRTTSTCTL Port test control 13 4 read-write PRTSPD Port speed 17 2 read-only HCCHAR0 HCCHAR0 OTGFS host channel-0 characteristics register (OTGFS_HCCHAR0) 0x100 0x20 read-write 0x00000000 MPS Maximum packet size 0 11 EPTNUM Endpoint number 11 4 EPTDIR Endpoint direction 15 1 LSPDDEV Low-speed device 17 1 EPTYPE Endpoint type 18 2 MC Multicount 20 2 DEVADDR Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR1 HCCHAR1 OTGFS host channel-1 characteristics register (OTGFS_HCCHAR1) 0x120 0x20 read-write 0x00000000 MPS Maximum packet size 0 11 EPTNUM Endpoint number 11 4 EPTDIR Endpoint direction 15 1 LSPDDEV Low-speed device 17 1 EPTYPE Endpoint type 18 2 MC Multicount 20 2 DEVADDR Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR2 HCCHAR2 OTGFS host channel-2 characteristics register (OTGFS_HCCHAR2) 0x140 0x20 read-write 0x00000000 MPS Maximum packet size 0 11 EPTNUM Endpoint number 11 4 EPTDIR Endpoint direction 15 1 LSPDDEV Low-speed device 17 1 EPTYPE Endpoint type 18 2 MC Multicount 20 2 DEVADDR Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR3 HCCHAR3 OTGFS host channel-3 characteristics register (OTGFS_HCCHAR3) 0x160 0x20 read-write 0x00000000 MPS Maximum packet size 0 11 EPTNUM Endpoint number 11 4 EPTDIR Endpoint direction 15 1 LSPDDEV Low-speed device 17 1 EPTYPE Endpoint type 18 2 MC Multicount 20 2 DEVADDR Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR4 HCCHAR4 OTGFS host channel-4 characteristics register (OTGFS_HCCHAR4) 0x180 0x20 read-write 0x00000000 MPS Maximum packet size 0 11 EPTNUM Endpoint number 11 4 EPTDIR Endpoint direction 15 1 LSPDDEV Low-speed device 17 1 EPTYPE Endpoint type 18 2 MC Multicount 20 2 DEVADDR Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR5 HCCHAR5 OTGFS host channel-5 characteristics register (OTGFS_HCCHAR5) 0x1A0 0x20 read-write 0x00000000 MPS Maximum packet size 0 11 EPTNUM Endpoint number 11 4 EPTDIR Endpoint direction 15 1 LSPDDEV Low-speed device 17 1 EPTYPE Endpoint type 18 2 MC Multicount 20 2 DEVADDR Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR6 HCCHAR6 OTGFS host channel-6 characteristics register (OTGFS_HCCHAR6) 0x1C0 0x20 read-write 0x00000000 MPS Maximum packet size 0 11 EPTNUM Endpoint number 11 4 EPTDIR Endpoint direction 15 1 LSPDDEV Low-speed device 17 1 EPTYPE Endpoint type 18 2 MC Multicount 20 2 DEVADDR Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR7 HCCHAR7 OTGFS host channel-7 characteristics register (OTGFS_HCCHAR7) 0x1E0 0x20 read-write 0x00000000 MPS Maximum packet size 0 11 EPTNUM Endpoint number 11 4 EPTDIR Endpoint direction 15 1 LSPDDEV Low-speed device 17 1 EPTYPE Endpoint type 18 2 MC Multicount 20 2 DEVADDR Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR8 HCCHAR8 OTGFS host channel-8 characteristics register (OTGFS_HCCHAR8) 0x200 0x20 read-write 0x00000000 MPS Maximum packet size 0 11 EPTNUM Endpoint number 11 4 EPTDIR Endpoint direction 15 1 LSPDDEV Low-speed device 17 1 EPTYPE Endpoint type 18 2 MC Multicount 20 2 DEVADDR Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR9 HCCHAR9 OTGFS host channel-9 characteristics register (OTGFS_HCCHAR9) 0x220 0x20 read-write 0x00000000 MPS Maximum packet size 0 11 EPTNUM Endpoint number 11 4 EPTDIR Endpoint direction 15 1 LSPDDEV Low-speed device 17 1 EPTYPE Endpoint type 18 2 MC Multicount 20 2 DEVADDR Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR10 HCCHAR10 OTGFS host channel-10 characteristics register (OTGFS_HCCHAR10) 0x240 0x20 read-write 0x00000000 MPS Maximum packet size 0 11 EPTNUM Endpoint number 11 4 EPTDIR Endpoint direction 15 1 LSPDDEV Low-speed device 17 1 EPTYPE Endpoint type 18 2 MC Multicount 20 2 DEVADDR Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR11 HCCHAR11 OTGFS host channel-7 characteristics register (OTGFS_HCCHAR11) 0x260 0x20 read-write 0x00000000 MPS Maximum packet size 0 11 EPTNUM Endpoint number 11 4 EPTDIR Endpoint direction 15 1 LSPDDEV Low-speed device 17 1 EPTYPE Endpoint type 18 2 MC Multicount 20 2 DEVADDR Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR12 HCCHAR12 OTGFS host channel-12 characteristics register (OTGFS_HCCHAR12) 0x280 0x20 read-write 0x00000000 MPS Maximum packet size 0 11 EPTNUM Endpoint number 11 4 EPTDIR Endpoint direction 15 1 LSPDDEV Low-speed device 17 1 EPTYPE Endpoint type 18 2 MC Multicount 20 2 DEVADDR Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR13 HCCHAR13 OTGFS host channel-13 characteristics register (OTGFS_HCCHAR13) 0x2A0 0x20 read-write 0x00000000 MPS Maximum packet size 0 11 EPTNUM Endpoint number 11 4 EPTDIR Endpoint direction 15 1 LSPDDEV Low-speed device 17 1 EPTYPE Endpoint type 18 2 MC Multicount 20 2 DEVADDR Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR14 HCCHAR14 OTGFS host channel-14 characteristics register (OTGFS_HCCHAR14) 0x2C0 0x20 read-write 0x00000000 MPS Maximum packet size 0 11 EPTNUM Endpoint number 11 4 EPTDIR Endpoint direction 15 1 LSPDDEV Low-speed device 17 1 EPTYPE Endpoint type 18 2 MC Multicount 20 2 DEVADDR Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR15 HCCHAR15 OTGFS host channel-15 characteristics register (OTGFS_HCCHAR15) 0x2E0 0x20 read-write 0x00000000 MPS Maximum packet size 0 11 EPTNUM Endpoint number 11 4 EPTDIR Endpoint direction 15 1 LSPDDEV Low-speed device 17 1 EPTYPE Endpoint type 18 2 MC Multicount 20 2 DEVADDR Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCINT0 HCINT0 OTGFS host channel-0 interrupt register (OTGFS_HCINT0) 0x108 0x20 read-write 0x00000000 XFERC Transfer completed 0 1 CHHLTD Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 XACTERR Transaction error 7 1 BBLERR Babble error 8 1 FRMOVRUN Frame overrun 9 1 DTGLERR Data toggle error 10 1 HCINT1 HCINT1 OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1) 0x128 0x20 read-write 0x00000000 XFERC Transfer completed 0 1 CHHLTD Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 XACTERR Transaction error 7 1 BBLERR Babble error 8 1 FRMOVRUN Frame overrun 9 1 DTGLERR Data toggle error 10 1 HCINT2 HCINT2 OTGFS host channel-2 interrupt register (OTGFS_HCINT2) 0x148 0x20 read-write 0x00000000 XFERC Transfer completed 0 1 CHHLTD Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 XACTERR Transaction error 7 1 BBLERR Babble error 8 1 FRMOVRUN Frame overrun 9 1 DTGLERR Data toggle error 10 1 HCINT3 HCINT3 OTGFS host channel-3 interrupt register (OTGFS_HCINT3) 0x168 0x20 read-write 0x00000000 XFERC Transfer completed 0 1 CHHLTD Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 XACTERR Transaction error 7 1 BBLERR Babble error 8 1 FRMOVRUN Frame overrun 9 1 DTGLERR Data toggle error 10 1 HCINT4 HCINT4 OTGFS host channel-4 interrupt register (OTGFS_HCINT4) 0x188 0x20 read-write 0x00000000 XFERC Transfer completed 0 1 CHHLTD Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 XACTERR Transaction error 7 1 BBLERR Babble error 8 1 FRMOVRUN Frame overrun 9 1 DTGLERR Data toggle error 10 1 HCINT5 HCINT5 OTGFS host channel-5 interrupt register (OTGFS_HCINT5) 0x1A8 0x20 read-write 0x00000000 XFERC Transfer completed 0 1 CHHLTD Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 XACTERR Transaction error 7 1 BBLERR Babble error 8 1 FRMOVRUN Frame overrun 9 1 DTGLERR Data toggle error 10 1 HCINT6 HCINT6 OTGFS host channel-6 interrupt register (OTGFS_HCINT6) 0x1C8 0x20 read-write 0x00000000 XFERC Transfer completed 0 1 CHHLTD Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 XACTERR Transaction error 7 1 BBLERR Babble error 8 1 FRMOVRUN Frame overrun 9 1 DTGLERR Data toggle error 10 1 HCINT7 HCINT7 OTGFS host channel-7 interrupt register (OTGFS_HCINT7) 0x1E8 0x20 read-write 0x00000000 XFERC Transfer completed 0 1 CHHLTD Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 XACTERR Transaction error 7 1 BBLERR Babble error 8 1 FRMOVRUN Frame overrun 9 1 DTGLERR Data toggle error 10 1 HCINT8 HCINT8 OTGFS host channel-8 interrupt register (OTGFS_HCINT8) 0x208 0x20 read-write 0x00000000 XFERC Transfer completed 0 1 CHHLTD Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 XACTERR Transaction error 7 1 BBLERR Babble error 8 1 FRMOVRUN Frame overrun 9 1 DTGLERR Data toggle error 10 1 HCINT9 HCINT9 OTGFS host channel-9 interrupt register (OTGFS_HCINT9) 0x228 0x20 read-write 0x00000000 XFERC Transfer completed 0 1 CHHLTD Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 XACTERR Transaction error 7 1 BBLERR Babble error 8 1 FRMOVRUN Frame overrun 9 1 DTGLERR Data toggle error 10 1 HCINT10 HCINT10 OTGFS host channel-10 interrupt register (OTGFS_HCINT10) 0x248 0x20 read-write 0x00000000 XFERC Transfer completed 0 1 CHHLTD Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 XACTERR Transaction error 7 1 BBLERR Babble error 8 1 FRMOVRUN Frame overrun 9 1 DTGLERR Data toggle error 10 1 HCINT11 HCINT11 OTGFS host channel-11 interrupt register (OTGFS_HCINT11) 0x268 0x20 read-write 0x00000000 XFERC Transfer completed 0 1 CHHLTD Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 XACTERR Transaction error 7 1 BBLERR Babble error 8 1 FRMOVRUN Frame overrun 9 1 DTGLERR Data toggle error 10 1 HCINT12 HCINT12 OTGFS host channel-12 interrupt register (OTGFS_HCINT12) 0x288 0x20 read-write 0x00000000 XFERC Transfer completed 0 1 CHHLTD Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 XACTERR Transaction error 7 1 BBLERR Babble error 8 1 FRMOVRUN Frame overrun 9 1 DTGLERR Data toggle error 10 1 HCINT13 HCINT13 OTGFS host channel-13 interrupt register (OTGFS_HCINT13) 0x2A8 0x20 read-write 0x00000000 XFERC Transfer completed 0 1 CHHLTD Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 XACTERR Transaction error 7 1 BBLERR Babble error 8 1 FRMOVRUN Frame overrun 9 1 DTGLERR Data toggle error 10 1 HCINT14 HCINT14 OTGFS host channel-14 interrupt register (OTGFS_HCINT14) 0x2C8 0x20 read-write 0x00000000 XFERC Transfer completed 0 1 CHHLTD Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 XACTERR Transaction error 7 1 BBLERR Babble error 8 1 FRMOVRUN Frame overrun 9 1 DTGLERR Data toggle error 10 1 HCINT15 HCINT15 OTGFS host channel-15 interrupt register (OTGFS_HCINT15) 0x2E8 0x20 read-write 0x00000000 XFERC Transfer completed 0 1 CHHLTD Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 XACTERR Transaction error 7 1 BBLERR Babble error 8 1 FRMOVRUN Frame overrun 9 1 DTGLERR Data toggle error 10 1 HCINTMSK0 HCINTMSK0 OTGFS host channel-0 mask register (OTGFS_HCINTMSK0) 0x10C 0x20 read-write 0x00000000 XFERCMSK Transfer completed mask 0 1 CHHLTDMSK Channel halted mask 1 1 STALLMSK STALL response received interrupt mask 3 1 NAKMSK NAK response received interrupt mask 4 1 ACKMSK ACK response received/transmitted interrupt mask 5 1 XACTERRMSK Transaction error mask 7 1 BBLERRMSK Babble error mask 8 1 FRMOVRUNMSK Frame overrun mask 9 1 DTGLERRMSK Data toggle error mask 10 1 HCINTMSK1 HCINTMSK1 OTGFS host channel-1 mask register (OTGFS_HCINTMSK1) 0x12C 0x20 read-write 0x00000000 XFERCMSK Transfer completed mask 0 1 CHHLTDMSK Channel halted mask 1 1 STALLMSK STALL response received interrupt mask 3 1 NAKMSK NAK response received interrupt mask 4 1 ACKMSK ACK response received/transmitted interrupt mask 5 1 XACTERRMSK Transaction error mask 7 1 BBLERRMSK Babble error mask 8 1 FRMOVRUNMSK Frame overrun mask 9 1 DTGLERRMSK Data toggle error mask 10 1 HCINTMSK2 HCINTMSK2 OTGFS host channel-2 mask register (OTGFS_HCINTMSK2) 0x14C 0x20 read-write 0x00000000 XFERCMSK Transfer completed mask 0 1 CHHLTDMSK Channel halted mask 1 1 STALLMSK STALL response received interrupt mask 3 1 NAKMSK NAK response received interrupt mask 4 1 ACKMSK ACK response received/transmitted interrupt mask 5 1 XACTERRMSK Transaction error mask 7 1 BBLERRMSK Babble error mask 8 1 FRMOVRUNMSK Frame overrun mask 9 1 DTGLERRMSK Data toggle error mask 10 1 HCINTMSK3 HCINTMSK3 OTGFS host channel-3 mask register (OTGFS_HCINTMSK3) 0x16C 0x20 read-write 0x00000000 XFERCMSK Transfer completed mask 0 1 CHHLTDMSK Channel halted mask 1 1 STALLMSK STALL response received interrupt mask 3 1 NAKMSK NAK response received interrupt mask 4 1 ACKMSK ACK response received/transmitted interrupt mask 5 1 XACTERRMSK Transaction error mask 7 1 BBLERRMSK Babble error mask 8 1 FRMOVRUNMSK Frame overrun mask 9 1 DTGLERRMSK Data toggle error mask 10 1 HCINTMSK4 HCINTMSK4 OTGFS host channel-4 mask register (OTGFS_HCINTMSK4) 0x18C 0x20 read-write 0x00000000 XFERCMSK Transfer completed mask 0 1 CHHLTDMSK Channel halted mask 1 1 STALLMSK STALL response received interrupt mask 3 1 NAKMSK NAK response received interrupt mask 4 1 ACKMSK ACK response received/transmitted interrupt mask 5 1 XACTERRMSK Transaction error mask 7 1 BBLERRMSK Babble error mask 8 1 FRMOVRUNMSK Frame overrun mask 9 1 DTGLERRMSK Data toggle error mask 10 1 HCINTMSK5 HCINTMSK5 OTGFS host channel-5 mask register (OTGFS_HCINTMSK5) 0x1AC 0x20 read-write 0x00000000 XFERCMSK Transfer completed mask 0 1 CHHLTDMSK Channel halted mask 1 1 STALLMSK STALL response received interrupt mask 3 1 NAKMSK NAK response received interrupt mask 4 1 ACKMSK ACK response received/transmitted interrupt mask 5 1 XACTERRMSK Transaction error mask 7 1 BBLERRMSK Babble error mask 8 1 FRMOVRUNMSK Frame overrun mask 9 1 DTGLERRMSK Data toggle error mask 10 1 HCINTMSK6 HCINTMSK6 OTGFS host channel-6 mask register (OTGFS_HCINTMSK6) 0x1CC 0x20 read-write 0x00000000 XFERCMSK Transfer completed mask 0 1 CHHLTDMSK Channel halted mask 1 1 STALLMSK STALL response received interrupt mask 3 1 NAKMSK NAK response received interrupt mask 4 1 ACKMSK ACK response received/transmitted interrupt mask 5 1 XACTERRMSK Transaction error mask 7 1 BBLERRMSK Babble error mask 8 1 FRMOVRUNMSK Frame overrun mask 9 1 DTGLERRMSK Data toggle error mask 10 1 HCINTMSK7 HCINTMSK7 OTGFS host channel-7 mask register (OTGFS_HCINTMSK7) 0x1EC 0x20 read-write 0x00000000 XFERCMSK Transfer completed mask 0 1 CHHLTDMSK Channel halted mask 1 1 STALLMSK STALL response received interrupt mask 3 1 NAKMSK NAK response received interrupt mask 4 1 ACKMSK ACK response received/transmitted interrupt mask 5 1 XACTERRMSK Transaction error mask 7 1 BBLERRMSK Babble error mask 8 1 FRMOVRUNMSK Frame overrun mask 9 1 DTGLERRMSK Data toggle error mask 10 1 HCINTMSK8 HCINTMSK8 OTGFS host channel-8 mask register (OTGFS_HCINTMSK8) 0x20C 0x20 read-write 0x00000000 XFERCMSK Transfer completed mask 0 1 CHHLTDMSK Channel halted mask 1 1 STALLMSK STALL response received interrupt mask 3 1 NAKMSK NAK response received interrupt mask 4 1 ACKMSK ACK response received/transmitted interrupt mask 5 1 XACTERRMSK Transaction error mask 7 1 BBLERRMSK Babble error mask 8 1 FRMOVRUNMSK Frame overrun mask 9 1 DTGLERRMSK Data toggle error mask 10 1 HCINTMSK9 HCINTMSK9 OTGFS host channel-9 mask register (OTGFS_HCINTMSK9) 0x22C 0x20 read-write 0x00000000 XFERCMSK Transfer completed mask 0 1 CHHLTDMSK Channel halted mask 1 1 STALLMSK STALL response received interrupt mask 3 1 NAKMSK NAK response received interrupt mask 4 1 ACKMSK ACK response received/transmitted interrupt mask 5 1 XACTERRMSK Transaction error mask 7 1 BBLERRMSK Babble error mask 8 1 FRMOVRUNMSK Frame overrun mask 9 1 DTGLERRMSK Data toggle error mask 10 1 HCINTMSK10 HCINTMSK10 OTGFS host channel-10 mask register (OTGFS_HCINTMSK10) 0x24C 0x20 read-write 0x00000000 XFERCMSK Transfer completed mask 0 1 CHHLTDMSK Channel halted mask 1 1 STALLMSK STALL response received interrupt mask 3 1 NAKMSK NAK response received interrupt mask 4 1 ACKMSK ACK response received/transmitted interrupt mask 5 1 XACTERRMSK Transaction error mask 7 1 BBLERRMSK Babble error mask 8 1 FRMOVRUNMSK Frame overrun mask 9 1 DTGLERRMSK Data toggle error mask 10 1 HCINTMSK11 HCINTMSK11 OTGFS host channel-11 mask register (OTGFS_HCINTMSK11) 0x26C 0x20 read-write 0x00000000 XFERCMSK Transfer completed mask 0 1 CHHLTDMSK Channel halted mask 1 1 STALLMSK STALL response received interrupt mask 3 1 NAKMSK NAK response received interrupt mask 4 1 ACKMSK ACK response received/transmitted interrupt mask 5 1 XACTERRMSK Transaction error mask 7 1 BBLERRMSK Babble error mask 8 1 FRMOVRUNMSK Frame overrun mask 9 1 DTGLERRMSK Data toggle error mask 10 1 HCINTMSK12 HCINTMSK12 OTGFS host channel-12 mask register (OTGFS_HCINTMSK12) 0x28C 0x20 read-write 0x00000000 XFERCMSK Transfer completed mask 0 1 CHHLTDMSK Channel halted mask 1 1 STALLMSK STALL response received interrupt mask 3 1 NAKMSK NAK response received interrupt mask 4 1 ACKMSK ACK response received/transmitted interrupt mask 5 1 XACTERRMSK Transaction error mask 7 1 BBLERRMSK Babble error mask 8 1 FRMOVRUNMSK Frame overrun mask 9 1 DTGLERRMSK Data toggle error mask 10 1 HCINTMSK13 HCINTMSK13 OTGFS host channel-13 mask register (OTGFS_HCINTMSK13) 0x2AC 0x20 read-write 0x00000000 XFERCMSK Transfer completed mask 0 1 CHHLTDMSK Channel halted mask 1 1 STALLMSK STALL response received interrupt mask 3 1 NAKMSK NAK response received interrupt mask 4 1 ACKMSK ACK response received/transmitted interrupt mask 5 1 XACTERRMSK Transaction error mask 7 1 BBLERRMSK Babble error mask 8 1 FRMOVRUNMSK Frame overrun mask 9 1 DTGLERRMSK Data toggle error mask 10 1 HCINTMSK14 HCINTMSK14 OTGFS host channel-14 mask register (OTGFS_HCINTMSK14) 0x2CC 0x20 read-write 0x00000000 XFERCMSK Transfer completed mask 0 1 CHHLTDMSK Channel halted mask 1 1 STALLMSK STALL response received interrupt mask 3 1 NAKMSK NAK response received interrupt mask 4 1 ACKMSK ACK response received/transmitted interrupt mask 5 1 XACTERRMSK Transaction error mask 7 1 BBLERRMSK Babble error mask 8 1 FRMOVRUNMSK Frame overrun mask 9 1 DTGLERRMSK Data toggle error mask 10 1 HCINTMSK15 HCINTMSK15 OTGFS host channel-15 mask register (OTGFS_HCINTMSK15) 0x2EC 0x20 read-write 0x00000000 XFERCMSK Transfer completed mask 0 1 CHHLTDMSK Channel halted mask 1 1 STALLMSK STALL response received interrupt mask 3 1 NAKMSK NAK response received interrupt mask 4 1 ACKMSK ACK response received/transmitted interrupt mask 5 1 XACTERRMSK Transaction error mask 7 1 BBLERRMSK Babble error mask 8 1 FRMOVRUNMSK Frame overrun mask 9 1 DTGLERRMSK Data toggle error mask 10 1 HCTSIZ0 HCTSIZ0 OTGFS host channel-0 transfer size register 0x110 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 PID PID 29 2 HCTSIZ1 HCTSIZ1 OTGFS host channel-1 transfer size register 0x130 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 PID PID 29 2 HCTSIZ2 HCTSIZ2 OTGFS host channel-2 transfer size register 0x150 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 PID PID 29 2 HCTSIZ3 HCTSIZ3 OTGFS host channel-3 transfer size register 0x170 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 PID PID 29 2 HCTSIZ4 HCTSIZ4 OTGFS host channel-4 transfer size register 0x190 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 PID PID 29 2 HCTSIZ5 HCTSIZ5 OTGFS host channel-5 transfer size register 0x1B0 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 PID PID 29 2 HCTSIZ6 HCTSIZ6 OTGFS host channel-6 transfer size register 0x1D0 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 PID PID 29 2 HCTSIZ7 HCTSIZ7 OTGFS host channel-7 transfer size register 0x1F0 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 PID PID 29 2 HCTSIZ8 HCTSIZ8 OTGFS host channel-8 transfer size register 0x210 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 PID PID 29 2 HCTSIZ9 HCTSIZ9 OTGFS host channel-9 transfer size register 0x230 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 PID PID 29 2 HCTSIZ10 HCTSIZ10 OTGFS host channel-10 transfer size register 0x250 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 PID PID 29 2 HCTSIZ11 HCTSIZ11 OTGFS host channel-11 transfer size register 0x270 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 PID PID 29 2 HCTSIZ12 HCTSIZ12 OTGFS host channel-12 transfer size register 0x290 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 PID PID 29 2 HCTSIZ13 HCTSIZ13 OTGFS host channel-13 transfer size register 0x2B0 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 PID PID 29 2 HCTSIZ14 HCTSIZ14 OTGFS host channel-14 transfer size register 0x2D0 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 PID PID 29 2 HCTSIZ15 HCTSIZ15 OTGFS host channel-15 transfer size register 0x2F0 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 PID PID 29 2 USB_OTG1_DEVICE USB on the go full speed USB_OTGFS 0x50000800 0x0 0x400 registers DCFG DCFG OTGFS device configuration register (OTGFS_DCFG) 0x0 0x20 read-write 0x02200000 DEVSPD Device speed 0 2 NZSTSOUTHSHK Non-zero-length status OUT handshake 2 1 DEVADDR Device address 4 7 PERFRINT Periodic frame interval 11 2 DCTL DCTL OTGFS device control register (OTGFS_DCTL) 0x4 0x20 0x00000000 RWKUPSIG Remote wakeup signaling 0 1 read-write SFTDISCON Soft disconnect 1 1 read-write GNPINNAKSTS Global IN NAK status 2 1 read-only GOUTNAKSTS Global OUT NAK status 3 1 read-only TSTCTL Test control 4 3 read-write SGNPINNAK Set global IN NAK 7 1 read-write CGNPINNAK Clear global IN NAK 8 1 read-write SGOUTNAK Set global OUT NAK 9 1 read-write CGOUTNAK Clear global OUT NAK 10 1 read-write PWROPRGDNE Power-on programming done 11 1 read-write DSTS DSTS OTGFS device status register (OTGFS_DSTS) 0x8 0x20 read-only 0x00000010 SUSPSTS Suspend status 0 1 ENUMSPD Enumerated speed 1 2 ETICERR Erratic error 3 1 SOFFN Frame number of the received SOF 8 14 DIEPMSK DIEPMSK OTGFS device IN endpoint common interrupt mask register (OTGFS_DIEPMSK) 0x10 0x20 read-write 0x00000000 XFERCMSK Transfer completed interrupt mask 0 1 EPTDISMSK Endpoint disabled interrupt mask 1 1 TIMEOUTMSK Timeout condition mask (Non-isochronous endpoints) 3 1 INTKNTXFEMPMSK IN token received when TxFIFO empty mask 4 1 INTKNEPTMISMSK IN token received with EP mismatch mask 5 1 INEPTNAKMSK IN endpoint NAK effective mask 6 1 TXFIFOUDRMSK FIFO underrun mask 8 1 BNAINMSK BNA interrupt mask 9 1 DOEPMSK DOEPMSK OTGFS device OUT endpoint common interrupt mask register (OTGFS_DOEPMSK) 0x14 0x20 read-write 0x00000000 XFERCMSK Transfer completed interrupt mask 0 1 EPTDISMSK Endpoint disabled interrupt mask 1 1 SETUPMSK SETUP phase done mask 3 1 OUTTEPDMSK OUT token received when endpoint disabled mask 4 1 B2BSETUPMSK Back-to-back SETUP packets received mask 6 1 OUTPERRMSK OUT packet error mask 8 1 BNAOUTMSK BNA interrupt mask 9 1 DAINT DAINT OTGFS device all endpoints interrupt register (OTGFS_DAINT) 0x18 0x20 read-only 0x00000000 INEPTINT IN endpoint interrupt bits 0 16 OUTEPTINT OUT endpoint interrupt bits 16 16 DAINTMSK DAINTMSK OTGFS all endpoints interrupt mask register (OTGFS_DAINTMSK) 0x1C 0x20 read-write 0x00000000 INEPTMSK IN EP interrupt mask bits 0 16 OUTEPTMSK OUT endpoint interrupt bits 16 16 DIEPEMPMSK DIEPEMPMSK OTGFS device IN endpoint FIFO empty interrupt mask register 0x34 0x20 read-write 0x00000000 INEPTXFEMSK IN EP Tx FIFO empty interrupt mask bits 0 16 DIEPCTL0 DIEPCTL0 OTGFS device control IN endpoint 0 control register (OTGFS_DIEPCTL0) 0x100 0x20 0x00000000 MPS Maximum packet size 0 2 read-write USBACEPT USB active endpoint 15 1 read-only NAKSTS NAK status 17 1 read-only EPTYPE Endpoint type 18 2 read-only STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only EPTDIS Endpoint disable 30 1 read-only EPTENA Endpoint enable 31 1 read-only DIEPCTL1 DIEPCTL1 OTGFS device IN endpoint-1 control register 0x120 0x20 0x00000000 MPS Maximum packet size 0 11 read-write USBACEPT USB active endpoint 15 1 read-write DPID Endpoint Data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYPE Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SETD0PID Set DATA0 PID 28 1 write-only SETD1PID Set DATA1 PID 29 1 write-only EPTDIS Endpoint disable 30 1 read-write EPTENA Endpoint enable 31 1 read-write DIEPCTL2 DIEPCTL2 OTGFS device IN endpoint-2 control register 0x140 0x20 0x00000000 MPS Maximum packet size 0 11 read-write USBACEPT USB active endpoint 15 1 read-write DPID Endpoint Data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYPE Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SETD0PID Set DATA0 PID 28 1 write-only SETD1PID Set DATA1 PID 29 1 write-only EPTDIS Endpoint disable 30 1 read-write EPTENA Endpoint enable 31 1 read-write DIEPCTL3 DIEPCTL3 OTGFS device IN endpoint-3 control register 0x160 0x20 0x00000000 MPS Maximum packet size 0 11 read-write USBACEPT USB active endpoint 15 1 read-write DPID Endpoint Data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYPE Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SETD0PID Set DATA0 PID 28 1 write-only SETD1PID Set DATA1 PID 29 1 write-only EPTDIS Endpoint disable 30 1 read-write EPTENA Endpoint enable 31 1 read-write DIEPCTL4 DIEPCTL4 OTGFS device IN endpoint-4 control register 0x180 0x20 0x00000000 MPS Maximum packet size 0 11 read-write USBACEPT USB active endpoint 15 1 read-write DPID Endpoint Data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYPE Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SETD0PID Set DATA0 PID 28 1 write-only SETD1PID Set DATA1 PID 29 1 write-only EPTDIS Endpoint disable 30 1 read-write EPTENA Endpoint enable 31 1 read-write DIEPCTL5 DIEPCTL5 OTGFS device IN endpoint-5 control register 0x1A0 0x20 0x00000000 MPS Maximum packet size 0 11 read-write USBACEPT USB active endpoint 15 1 read-write DPID Endpoint Data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYPE Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SETD0PID Set DATA0 PID 28 1 write-only SETD1PID Set DATA1 PID 29 1 write-only EPTDIS Endpoint disable 30 1 read-write EPTENA Endpoint enable 31 1 read-write DIEPCTL6 DIEPCTL6 OTGFS device IN endpoint-6 control register 0x1C0 0x20 0x00000000 MPS Maximum packet size 0 11 read-write USBACEPT USB active endpoint 15 1 read-write DPID Endpoint Data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYPE Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SETD0PID Set DATA0 PID 28 1 write-only SETD1PID Set DATA1 PID 29 1 write-only EPTDIS Endpoint disable 30 1 read-write EPTENA Endpoint enable 31 1 read-write DIEPCTL7 DIEPCTL7 OTGFS device IN endpoint-7 control register 0x1E0 0x20 0x00000000 MPS Maximum packet size 0 11 read-write USBACEPT USB active endpoint 15 1 read-write DPID Endpoint Data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYPE Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SETD0PID Set DATA0 PID 28 1 write-only SETD1PID Set DATA1 PID 29 1 write-only EPTDIS Endpoint disable 30 1 read-write EPTENA Endpoint enable 31 1 read-write DOEPCTL0 DOEPCTL0 OTGFS device OUT endpoint-0 control register 0x300 0x20 0x00008000 MPS Maximum packet size 0 2 read-only USBACEPT USB active endpoint 15 1 read-only NAKSTS NAK status 17 1 read-only EPTYPE Endpoint type 18 2 read-only SNP Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only EPTDIS Endpoint disable 30 1 read-write EPTENA Endpoint enable 31 1 read-write DOEPCTL1 DOEPCTL1 OTGFS device OUT endpoint-1 control register 0x320 0x20 0x00000000 MPS Maximum packet size 0 11 read-write USBACEPT USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYPE Endpoint type 18 2 read-write SNP Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only EPTDIS Endpoint disable 30 1 read-write EPTENA Endpoint enable 31 1 read-write DOEPCTL2 DOEPCTL2 OTGFS device OUT endpoint-2 control register 0x340 0x20 0x00000000 MPS Maximum packet size 0 11 read-write USBACEPT USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYPE Endpoint type 18 2 read-write SNP Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only EPTDIS Endpoint disable 30 1 read-write EPTENA Endpoint enable 31 1 read-write DOEPCTL3 DOEPCTL3 OTGFS device OUT endpoint-3 control register 0x360 0x20 0x00000000 MPS Maximum packet size 0 11 read-write USBACEPT USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYPE Endpoint type 18 2 read-write SNP Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only EPTDIS Endpoint disable 30 1 read-write EPTENA Endpoint enable 31 1 read-write DOEPCTL4 DOEPCTL4 OTGFS device OUT endpoint-4 control register 0x380 0x20 0x00000000 MPS Maximum packet size 0 11 read-write USBACEPT USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYPE Endpoint type 18 2 read-write SNP Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only EPTDIS Endpoint disable 30 1 read-write EPTENA Endpoint enable 31 1 read-write DOEPCTL5 DOEPCTL5 OTGFS device OUT endpoint-5 control register 0x3A0 0x20 0x00000000 MPS Maximum packet size 0 11 read-write USBACEPT USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYPE Endpoint type 18 2 read-write SNP Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only EPTDIS Endpoint disable 30 1 read-write EPTENA Endpoint enable 31 1 read-write DOEPCTL6 DOEPCTL6 OTGFS device OUT endpoint-6 control register 0x3C0 0x20 0x00000000 MPS Maximum packet size 0 11 read-write USBACEPT USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYPE Endpoint type 18 2 read-write SNP Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only EPTDIS Endpoint disable 30 1 read-write EPTENA Endpoint enable 31 1 read-write DOEPCTL7 DOEPCTL7 OTGFS device OUT endpoint-7 control register 0x3E0 0x20 0x00000000 MPS Maximum packet size 0 11 read-write USBACEPT USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYPE Endpoint type 18 2 read-write SNP Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only EPTDIS Endpoint disable 30 1 read-write EPTENA Endpoint enable 31 1 read-write DIEPINT0 DIEPINT0 OTGFS device IN endpoint-0 interrupt register 0x108 0x20 0x00000080 XFERC Transfer completed interrupt 0 1 read-write EPTDISD Endpoint disabled interrupt 1 1 read-write TIMEOUT Timeout condition 3 1 read-write INTKNTXFEMP IN token received when TxFIFO is empty 4 1 read-write INEPTNAK IN endpoint NAK effective 6 1 read-write TXFEMP Transmit FIFO empty 7 1 read-only DIEPINT1 DIEPINT1 OTGFS device IN endpoint-1 interrupt register 0x128 0x20 0x00000080 XFERC Transfer completed interrupt 0 1 read-write EPTDISD Endpoint disabled interrupt 1 1 read-write TIMEOUT Timeout condition 3 1 read-write INTKNTXFEMP IN token received when TxFIFO is empty 4 1 read-write INEPTNAK IN endpoint NAK effective 6 1 read-write TXFEMP Transmit FIFO empty 7 1 read-only DIEPINT2 DIEPINT2 OTGFS device IN endpoint-2 interrupt register 0x148 0x20 0x00000080 XFERC Transfer completed interrupt 0 1 read-write EPTDISD Endpoint disabled interrupt 1 1 read-write TIMEOUT Timeout condition 3 1 read-write INTKNTXFEMP IN token received when TxFIFO is empty 4 1 read-write INEPTNAK IN endpoint NAK effective 6 1 read-write TXFEMP Transmit FIFO empty 7 1 read-only DIEPINT3 DIEPINT3 OTGFS device IN endpoint-3 interrupt register 0x168 0x20 0x00000080 XFERC Transfer completed interrupt 0 1 read-write EPTDISD Endpoint disabled interrupt 1 1 read-write TIMEOUT Timeout condition 3 1 read-write INTKNTXFEMP IN token received when TxFIFO is empty 4 1 read-write INEPTNAK IN endpoint NAK effective 6 1 read-write TXFEMP Transmit FIFO empty 7 1 read-only DIEPINT4 DIEPINT4 OTGFS device IN endpoint-4 interrupt register 0x188 0x20 0x00000080 XFERC Transfer completed interrupt 0 1 read-write EPTDISD Endpoint disabled interrupt 1 1 read-write TIMEOUT Timeout condition 3 1 read-write INTKNTXFEMP IN token received when TxFIFO is empty 4 1 read-write INEPTNAK IN endpoint NAK effective 6 1 read-write TXFEMP Transmit FIFO empty 7 1 read-only DIEPINT5 DIEPINT5 OTGFS device IN endpoint-5 interrupt register 0x1A8 0x20 0x00000080 XFERC Transfer completed interrupt 0 1 read-write EPTDISD Endpoint disabled interrupt 1 1 read-write TIMEOUT Timeout condition 3 1 read-write INTKNTXFEMP IN token received when TxFIFO is empty 4 1 read-write INEPTNAK IN endpoint NAK effective 6 1 read-write TXFEMP Transmit FIFO empty 7 1 read-only DIEPINT6 DIEPINT6 OTGFS device IN endpoint-6 interrupt register 0x1C8 0x20 0x00000080 XFERC Transfer completed interrupt 0 1 read-write EPTDISD Endpoint disabled interrupt 1 1 read-write TIMEOUT Timeout condition 3 1 read-write INTKNTXFEMP IN token received when TxFIFO is empty 4 1 read-write INEPTNAK IN endpoint NAK effective 6 1 read-write TXFEMP Transmit FIFO empty 7 1 read-only DIEPINT7 DIEPINT7 OTGFS device IN endpoint-7 interrupt register 0x1E8 0x20 0x00000080 XFERC Transfer completed interrupt 0 1 read-write EPTDISD Endpoint disabled interrupt 1 1 read-write TIMEOUT Timeout condition 3 1 read-write INTKNTXFEMP IN token received when TxFIFO is empty 4 1 read-write INEPTNAK IN endpoint NAK effective 6 1 read-write TXFEMP Transmit FIFO empty 7 1 read-only DOEPINT0 DOEPINT0 OTGFS device OUT endpoint-0 interrupt register 0x308 0x20 read-write 0x00000080 XFERC Transfer completed interrupt 0 1 EPTDISD Endpoint disabled interrupt 1 1 SETUP SETUP phase done 3 1 OUTTEPD OUT token received when endpoint disabled 4 1 B2BSTUP Back-to-back SETUP packets received 6 1 DOEPINT1 DOEPINT1 OTGFS device OUT endpoint-1 interrupt register 0x328 0x20 read-write 0x00000080 XFERC Transfer completed interrupt 0 1 EPTDISD Endpoint disabled interrupt 1 1 SETUP SETUP phase done 3 1 OUTTEPD OUT token received when endpoint disabled 4 1 B2BSTUP Back-to-back SETUP packets received 6 1 DOEPINT2 DOEPINT2 OTGFS device OUT endpoint-2 interrupt register 0x348 0x20 read-write 0x00000080 XFERC Transfer completed interrupt 0 1 EPTDISD Endpoint disabled interrupt 1 1 SETUP SETUP phase done 3 1 OUTTEPD OUT token received when endpoint disabled 4 1 B2BSTUP Back-to-back SETUP packets received 6 1 DOEPINT3 DOEPINT3 OTGFS device OUT endpoint-3 interrupt register 0x368 0x20 read-write 0x00000080 XFERC Transfer completed interrupt 0 1 EPTDISD Endpoint disabled interrupt 1 1 SETUP SETUP phase done 3 1 OUTTEPD OUT token received when endpoint disabled 4 1 B2BSTUP Back-to-back SETUP packets received 6 1 DOEPINT4 DOEPINT4 OTGFS device OUT endpoint-4 interrupt register 0x388 0x20 read-write 0x00000080 XFERC Transfer completed interrupt 0 1 EPTDISD Endpoint disabled interrupt 1 1 SETUP SETUP phase done 3 1 OUTTEPD OUT token received when endpoint disabled 4 1 B2BSTUP Back-to-back SETUP packets received 6 1 DOEPINT5 DOEPINT5 OTGFS device OUT endpoint-5 interrupt register 0x3A8 0x20 read-write 0x00000080 XFERC Transfer completed interrupt 0 1 EPTDISD Endpoint disabled interrupt 1 1 SETUP SETUP phase done 3 1 OUTTEPD OUT token received when endpoint disabled 4 1 B2BSTUP Back-to-back SETUP packets received 6 1 DOEPINT6 DOEPINT6 OTGFS device OUT endpoint-6 interrupt register 0x3C8 0x20 read-write 0x00000080 XFERC Transfer completed interrupt 0 1 EPTDISD Endpoint disabled interrupt 1 1 SETUP SETUP phase done 3 1 OUTTEPD OUT token received when endpoint disabled 4 1 B2BSTUP Back-to-back SETUP packets received 6 1 DOEPINT7 DOEPINT7 OTGFS device OUT endpoint-7 interrupt register 0x3E8 0x20 read-write 0x00000080 XFERC Transfer completed interrupt 0 1 EPTDISD Endpoint disabled interrupt 1 1 SETUP SETUP phase done 3 1 OUTTEPD OUT token received when endpoint disabled 4 1 B2BSTUP Back-to-back SETUP packets received 6 1 DIEPTSIZ0 DIEPTSIZ0 OTGFS device IN endpoint-0 transfer size register 0x110 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 7 PKTCNT Packet count 19 2 DOEPTSIZ0 DOEPTSIZ0 OTGFS device OUT endpoint-0 transfer size register 0x310 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 7 PKTCNT Packet count 19 1 SETUPCNT SETUP packet count 29 2 DIEPTSIZ1 DIEPTSIZ1 OTGFS device IN endpoint-1 transfer size register 0x130 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 MC Multi count 29 2 DIEPTSIZ2 DIEPTSIZ2 OTGFS device IN endpoint-2 transfer size register 0x150 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 MC Multi count 29 2 DIEPTSIZ3 DIEPTSIZ3 OTG device IN endpoint-3 transfer size register 0x170 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 MC Multi count 29 2 DIEPTSIZ4 DIEPTSIZ4 OTG device IN endpoint-4 transfer size register 0x190 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 MC Multi count 29 2 DIEPTSIZ5 DIEPTSIZ5 OTG device IN endpoint-5 transfer size register 0x1B0 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 MC Multi count 29 2 DIEPTSIZ6 DIEPTSIZ6 OTG device IN endpoint-6 transfer size register 0x1D0 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 MC Multi count 29 2 DIEPTSIZ7 DIEPTSIZ7 OTG device IN endpoint-7 transfer size register 0x1F0 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 MC Multi count 29 2 DTXFSTS0 DTXFSTS0 OTGFS device IN endpoint-0 transmit FIFO status register 0x118 0x20 read-only 0x00000000 INEPTXFSAV IN endpoint TxFIFO space available 0 16 DTXFSTS1 DTXFSTS1 OTGFS device IN endpoint-1 transmit FIFO status register 0x138 0x20 read-only 0x00000000 INEPTXFSAV IN endpoint TxFIFO space available 0 16 DTXFSTS2 DTXFSTS2 OTGFS device IN endpoint-2 transmit FIFO status register 0x158 0x20 read-only 0x00000000 INEPTXFSAV IN endpoint TxFIFO space available 0 16 DTXFSTS3 DTXFSTS3 OTGFS device IN endpoint-3 transmit FIFO status register 0x178 0x20 read-only 0x00000000 INEPTXFSAV IN endpoint TxFIFO space available 0 16 DTXFSTS4 DTXFSTS4 OTGFS device IN endpoint-4 transmit FIFO status register 0x198 0x20 read-only 0x00000000 INEPTXFSAV IN endpoint TxFIFO space available 0 16 DTXFSTS5 DTXFSTS5 OTGFS device IN endpoint-5 transmit FIFO status register 0x1B8 0x20 read-only 0x00000000 INEPTXFSAV IN endpoint TxFIFO space available 0 16 DTXFSTS6 DTXFSTS6 OTGFS device IN endpoint-6 transmit FIFO status register 0x1D8 0x20 read-only 0x00000000 INEPTXFSAV IN endpoint TxFIFO space available 0 16 DTXFSTS7 DTXFSTS7 OTGFS device IN endpoint-7 transmit FIFO status register 0x1F8 0x20 read-only 0x00000000 INEPTXFSAV IN endpoint TxFIFO space available 0 16 DOEPTSIZ1 DOEPTSIZ1 OTGFS device OUT endpoint-1 transfer size register 0x330 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 RXDPID Received data PID 29 2 DOEPTSIZ2 DOEPTSIZ2 OTGFS device OUT endpoint-2 transfer size register 0x350 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 RXDPID Received data PID 29 2 DOEPTSIZ3 DOEPTSIZ3 OTGFS device OUT endpoint-3 transfer size register 0x370 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 RXDPID Received data PID 29 2 DOEPTSIZ4 DOEPTSIZ4 OTGFS device OUT endpoint-4 transfer size register 0x390 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 RXDPID Received data PID 29 2 DOEPTSIZ5 DOEPTSIZ5 OTGFS device OUT endpoint-5 transfer size register 0x3B0 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 RXDPID Received data PID 29 2 DOEPTSIZ6 DOEPTSIZ6 OTGFS device OUT endpoint-6 transfer size register 0x3D0 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 RXDPID Received data PID 29 2 DOEPTSIZ7 DOEPTSIZ7 OTGFS device OUT endpoint-7 transfer size register 0x3F0 0x20 read-write 0x00000000 XFERSIZE Transfer size 0 19 PKTCNT Packet count 19 10 RXDPID Received data PID 29 2 USB_OTG1_PWRCLK USB on the go full speed USB_OTGFS 0x50000E00 0x0 0x400 registers PCGCCTL PCGCCTL OTGFS power and clock gating control register (OTGFS_PCGCCTL) 0x0 0x20 0x00000000 STOPPCLK Stop PHY clock 0 1 read-write SUSPENDM PHY Suspended 4 1 read-only SCFG System configuration controller SCFG 0x40013800 0x0 0x400 registers CFG1 CFG1 configuration register 1 0x0 0x20 read-write 0x00000000 MEM_MAP_SEL Memory address mapping selection bits 0 3 IR_POL IR output polarity selection 5 1 IR_SRC_SEL IR signal source selection 6 2 CFG2 CFG2 configuration register 2 0x4 0x20 read-write 0x00000000 LOCKUP_LK CM4F LOCKUP bit enable 0 1 SRAM_OPERR_LK SRAM odd parity error lock enable 1 1 PVM_LK PVM lock enable 2 1 SRAM_OPERR_STS SRAM odd parity error status 8 1 I2S_FD I2S full duplex config 30 2 EXINTC1 EXINTC1 external interrupt configuration register 1 0x8 0x20 read-write 0x0000 EXINT3 EXINT 3 configuration bits 12 4 EXINT2 EXINT 2 configuration bits 8 4 EXINT1 EXINT 1 configuration bits 4 4 EXINT0 EXINT 0 configuration bits 0 4 EXINTC2 EXINTC2 external interrupt configuration register 2 0xC 0x20 read-write 0x0000 EXINT7 EXINT 7 configuration bits 12 4 EXINT6 EXINT 6 configuration bits 8 4 EXINT5 EXINT 5 configuration bits 4 4 EXINT4 EXINT 4 configuration bits 0 4 EXINTC3 EXINTC3 external interrupt configuration register 3 0x10 0x20 read-write 0x0000 EXINT11 EXINT 11 configuration bits 12 4 EXINT10 EXINT 10 configuration bits 8 4 EXINT9 EXINT 9 configuration bits 4 4 EXINT8 EXINT 8 configuration bits 0 4 EXINTC4 EXINTC4 external interrupt configuration register 4 0x14 0x20 read-write 0x0000 EXINT15 EXINT 15 configuration bits 12 4 EXINT14 EXINT 14 configuration bits 8 4 EXINT13 EXINT 13 configuration bits 4 4 EXINT12 EXINT 12 configuration bits 0 4 UHDRV UHDRV Ultra high drive register 0x2C 0x20 read-write 0x0000 PB10_UH PB10 ultra high sourcing/sinking strength 2 1 PB9_UH PB9 ultra high sourcing/sinking strength 1 1 PB3_UH PB3 ultra high sourcing/sinking strength 0 1 QSPI1 Quad SPI Controller QSPI 0xA0001000 0x0 0x400 registers QSPI1 QSPI1 global interrupt 92 CMD_W0 CMD_W0 Command word 0 0x0 0x20 read-write 0x00000000 SPIADR SPI flash address 0 32 CMD_W1 CMD_W1 Command word 1 0x4 0x20 read-write 0x01000003 ADRLEN SPI address length 0 3 DUM2 Second dummy state cycle 16 8 INSLEN Instruction code length 24 2 PEMEN Perfrmance enhance mode enable 28 1 CMD_W2 CMD_W2 Command word 2 0x8 0x20 read-write 0x01000003 DCNT Read write data counter 0 32 CMD_W3 CMD_W3 Command word 3 0xC 0x20 read-write 0x00000000 WEN Write data enable 1 1 RSTSEN Read spi status enable 2 1 RSTSC Read spi status configure 3 1 OPMODE SPI operate mode 5 3 PEMOPC Performance enhance mode operate code 16 8 INSC Instruction code 24 8 CTRL CTRL Control register 0x10 0x20 read-write 0x00000000 CLKDIV SPI clock divider 0 3 SCKMODE Sckout mode 4 1 XIPIDLE XIP port idle status 7 1 ABORT Abort instruction 8 1 BUSY Busy bit of spi status 16 3 XIPRCMDF XIP read command flush 19 1 XIPSEL XIP port selection 20 1 KEYEN encryption key enable 21 1 FIFOSTS FIFOSTS FIFO Status register 0x18 0x20 read-only 0x00000001 TXFIFORDY TxFIFO ready status 0 1 RXFIFORDY RxFIFO ready status 1 1 CTRL2 CTRL2 control register 2 0x20 0x20 read-write 0x00000001 DMAEN DMA handshake enable 0 1 CMDIE Command complete interrupt enable 1 1 TXFIFOTHOD TxFIFO thod 8 2 RXFIFOTHOD RxFIFO thod 12 2 CMDSTS CMDSTS CMD status register 0x24 0x20 read-only 0x00000000 CMDSTS Command complete status 0 1 RSTS RSTS SPI read status register 0x28 0x20 read-only 0x00000000 SPISTS SPI read status 0 8 FSIZE FSIZE SPI flash size 0x2C 0x20 read-write 0x00000000 SPIFSIZE SPI flash size 0 32 XIP_CMD_W0 XIP_CMD_W0 XIP command word 0 0x30 0x20 read-write 0x00000000 XIPR_DUM2 XIP read second dummy cycle 0 8 XIPR_OPMODE XIP read operate mode 8 3 XIPR_ADRLEN XIP read address length 11 1 XIPR_INSC XIP read instruction code 12 8 XIP_CMD_W1 XIP_CMD_W1 XIP command word 1 0x34 0x20 read-write 0x00000000 XIPW_DUM2 XIP write second dummy cycle 0 8 XIPW_OPMODE XIP write operate mode 8 3 XIPW_ADRLEN XIP write address length 11 1 XIPW_INSC XIP write instruction code 12 8 XIP_CMD_W2 XIP_CMD_W2 XIP command word 2 0x38 0x20 read-write 0x00000000 XIPR_DCNT XIP read data counter 0 5 XIPR_TCNT XIP continue read cycle counter 8 7 XIPR_SEL XIP read continue mode select 15 1 XIPW_DCNT XIP write data counter 16 5 XIPW_TCNT XIP continue write cycle counter 24 7 XIPW_SEL XIP write continue mode select 31 1 XIP_CMD_W3 XIP_CMD_W3 XIP command word 3 0x3C 0x20 read-write 0x00000000 BYPASSC Bypass cache function 0 1 CSTS Cache status 3 1 REV REV Revision 0x50 0x20 read-write 0x00010500 REVISION Revision number 0 31 DT DT 32/16/8 bit data port register 0x100 0x20 read-write 0x00000000