ARM Ltd. ARM CMSDK_CM3 ARM Cortex M3 1.0 ARM 32-bit Cortex-M3 based device ARM Limited (ARM) is supplying this software for use with Cortex-M\n processor based microcontroller, but can be equally used for other\n suitable processor architectures. This file can be freely distributed.\n Modifications to this file shall be clearly marked.\n \n THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. CM3 r2p1 little true false 3 false 8 32 32 read-write 0x00000000 0xFFFFFFFF TIMER0 1.0 Timer 0 TIMER 0x40000000 32 read-write 0 0x10 registers TIMER0 Timer 0 Interrupt 8 CTRL Control Register 0x000 ENABLE Enable [0:0] Disable Timer is disabled 0 Enable Timer is enabled 1 EXTIN External Input as Enable [1:1] Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 EXTCLK External Clock Enable [2:2] Disable External Clock s disabled 0 Enable External Clock is enabled 1 INTEN Interrupt Enable [3:3] Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 VALUE Current Timer Counter Value 0x004 RELOAD Counter Reload Value 0x008 INTSTATUS Timer Interrupt status register 0x00C read-only INTCLEAR Timer Interrupt clear register INTSTATUS 0x00C write-only oneToClear TIMER1 0x40001000 TIMER1 Timer 1 Interrupt 9 DUALTIMER 1.0 Dual Timer DUALTIMER 0x40002000 32 read-write 0 0x3C registers DUALTIMER Dual Timer Interrupt 10 TIMER1LOAD Timer 1 Load Register 0x000 0x00000000 TIMER1VALUE Timer 1 Value Register 0x004 0xFFFFFFFF read-only TIMER1CONTROL Timer 1 Control Register 0x008 0x20 OneShotCount Selects one-shot or wrapping counter mode. 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerSize Selects 16-bit or 32- bit counter operation. 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TimerPre Timer prescale bits. 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 InterruptEnable Interrupt Enable bit. 5 1 Disable Interrupt is disabled. 0 Enable Interrupt is enabled. 1 TimerMode Timer Mode bit. 6 1 Free-Running Free-Running timer mode. 0 Periodic Periodic timer mode. 1 TimerEnable Timer Enable Enable bit. 7 1 Disable Timer is disabled. 0 Enable Timer is enabled. 1 TIMER1INTCLR Timer 1 Interrupt Clear Register 0x00C 0x00000000 write-only INT Interrupt 0 1 oneToClear TIMER1RIS Timer 1 Raw Interrupt Status Register 0x010 0x0 read-only RIS Raw Timer Interrupt 0 1 TIMER1MIS Timer 1 Mask Interrupt Status Register 0x014 0x0 read-only MIS Masked Timer Interrupt 0 1 TIMER1BGLOAD Timer 1 Background Load Register 0x018 0x00000000 TIMER2LOAD Timer 2 Load Register 0x020 0x00000000 TIMER2VALUE Timer 2 Value Register 0x024 0xFFFFFFFF read-only TIMER2CONTROL Timer 2 Control Register 0x028 0x20 OneShotCount Selects one-shot or wrapping counter mode. 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerSize Selects 16-bit or 32- bit counter operation. 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TimerPre Timer prescale bits. 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 InterruptEnable Interrupt Enable bit. 5 1 Disable Interrupt is disabled. 0 Enable Interrupt is enabled. 1 TimerMode Timer Mode bit. 6 1 Free-Running Free-Running timer mode. 0 Periodic Periodic timer mode. 1 TimerEnable Timer Enable Enable bit. 7 1 Disable Timer is disabled. 0 Enable Timer is enabled. 1 TIMER2INTCLR Timer 2 Interrupt Clear Register 0x02C 0x00000000 write-only INT Interrupt 0 1 oneToClear TIMER2RIS Timer 2 Raw Interrupt Status Register 0x030 0x0 read-only RIS Raw Timer Interrupt 0 1 TIMER2MIS Timer 2 Mask Interrupt Status Register 0x034 0x0 read-only MIS Masked Timer Interrupt 0 1 TIMER2BGLOAD Timer 2 Background Load Register 0x038 0x00000000 UART0 1.0 UART 0 UART 0x40004000 32 read-write 0 0x14 registers UART0_RX UART 0 Receive Interrupt 0 UART0_TX UART 0 Transmit Interrupt 1 DATA Recieve and Transmit Data Value 0x000 8 STATE UART Status Register 0x004 RXOV RX Buffer Overun (write 1 to clear) [3:3] oneToClear TXOV TX Buffer Overun (write 1 to clear) [2:2] oneToClear RXBF RX Buffer Full [1:1] read-only TXBF TX Buffer Full [0:0] read-only CTRL UART Control Register 0x008 HSTX High Speed Test Mode for TX only [6:6] Disable Disabled 0 Enable Enabled 1 RVOVINT RX Overrun Interrupt Enable [5:5] Disable Disabled 0 Enable Enabled 1 TXOVINT TX Overrun Interrupt Enable [4:4] Disable Disabled 0 Enable Enabled 1 RXINT RX Interrupt Enable [3:3] Disable Disabled 0 Enable Enabled 1 TXINT TX Interrupt Enable [2:2] Disable Disabled 0 Enable Enabled 1 RXEN RX Enable [1:1] Disable Disabled 0 Enable Enabled 1 TXEN TX Enable [0:0] Disable Disabled 0 Enable Enabled 1 INTSTATUS UART Interrupt Status Register 0x00C read-only RXOV RX Overrun Interrupt [3:3] TXOV TX Overrun Interrupt [2:2] RXINT RX Interrupt [1:1] TXINT TX Interrupt [0:0] INTCLEAR UART Interrupt CLEAR Register INTSTATUS 0x00C write-only RXOV RX Overrun Interrupt [3:3] oneToClear TXOV TX Overrun Interrupt [2:2] oneToClear RXINT RX Interrupt [1:1] oneToClear TXINT TX Interrupt [0:0] oneToClear BAUDDIV Baudrate Divider 0x010 UART1 0x40005000 UART1_RX UART 1 Receive Interrupt 2 UART1_TX UART 1 Transmit Interrupt 3 UART2 0x40006000 UART2_RX UART 1 Receive Interrupt 4 UART2_TX UART 2 Transmit Interrupt 5 UART3 0x40007000 UART3_RX UART 3 Receive Interrupt 18 UART3_TX UART 3 Transmit Interrupt 19 UART4 0x40009000 UART4_RX UART 4 Receive Interrupt 20 UART4_TX UART 4 Transmit Interrupt 21 GPIO0 1.0 general-purpose I/O GPIO 0x40010000 32 read-write 0 0x3C registers GPIO0 GPIO 0 combined interrupt 6 DATA Data Register 0x000 DATAOUT Data Output Register 0x004 OUTENSET Ouptut enable set Register 0x010 OUTENCLR Ouptut enable clear Register 0x014 ALTFUNCSET Alternate function set Register 0x018 ALTFUNCCLR Alternate function clear Register 0x01C INTENSET Interrupt enable set Register 0x020 INTENCLR Interrupt enable clear Register 0x024 INTTYPESET Interrupt type set Register 0x028 INTTYPECLR Interrupt type clear Register 0x02C INTPOLSET Polarity-level, edge interrupt configuration set Register 0x030 INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x034 INTSTATUS Interrupt Status Register 0x038 read-only INTCLEAR Interrupt CLEAR Register INTSTATUS 0x038 write-only oneToClear GPIO1 0x40011000 GPIO1 GPIO 1 combined interrupt 7 SPI 1.0 SPI SPI 0x40027000 16 read-write 0 64 registers SPI Combined SPI 0, SPI 1 Interrupt 11 SPSTAT SPI Status 0 SPDAT SPI Data 2 SPCLK SPI Clock Configuration 4 SPCON SPI Configuration 6 SPEN [0:0] SSDIS [1:1] MSTRS [2:2] CPOL [3:3] CPHA [4:4] SPR1 [5:5] SPR0 [6:6] WDT Watchdog Timer 0x40008000 0 0xC04 registers WDT Watchdog Interrupt 0 WDOGLOAD Watchdog Load Register 0x000 0xFFFFFFFF WDOGVALUE Watchdog Value Register 0x004 0xFFFFFFFF read-only WDOGCONTROL Watchdog Control Register 0x008 0x20 INTEN Enable the interrupt event 0 1 Disable Disable Watchdog interrupt 0 Enable ENable Watchdog interrupt. 1 RESEN Enable watchdog reset output 1 1 Disable Disable Watchdog reset 0 Enable ENable Watchdog reset 1 WDOGINTCLR Watchdog Interrupt Clear Register 0x00C 0x00000000 write-only INT Interrupt 0 1 oneToClear WDOGRIS Watchdog Raw Interrupt Status Register 0x010 0x0 read-only RIS Raw watchdog Interrupt 0 1 WDOGMIS Watchdog Mask Interrupt Status Register 0x014 0x0 read-only MIS Masked Watchdog Interrupt 0 1 WDOGLOCK Watchdog Lock Register 0xC00 0x00000000 FPGAIO FPGA System Control I/O 0x40028000 0 0x100 registers LED LED Connections 0x000 32 0x0 LED0 [0:0] Off LED is off 0 On LED is on 1 LED1 [1:1] Off LED is off 0 On LED is on 1 BUTTON Button Connections 0x008 32 0x0 BUTTON0 [0:0] Off BUTTON is off 0 On BUTTON is on 1 BUTTON1 [1:1] Off BUTTON is off 0 On BUTTON is on 1 CLK1HZ 1Hz Up Counter 0x010 32 read-only 0x0 CLK100HZ 100Hz Up Counter 0x014 32 read-only 0x0 COUNTER Cycle up counter 0x018 32 read-write 0x0 PRESCALER Reload value for prescaler counter 0x01C 32 read-write 0x0 PSCNTR Prescale Counter 0x020 32 read-write 0x0 MISC Misc. Control 0x04C 32 read-write 0x0 SHIELD1_SPI_nCS [9:9] SHIELD0_SPI_nCS [8:8] ADC_SPI_nCS [7:7] CLCD_BL_CTRL [6:6] CLCD_RD [5:5] CLCD_RS [4:4] CLCD_RESET [3:3] SPI_nSS [1:1] CLCD_CS [0:0] SCC Serial Communication Controller 0x4002F000 0 0x1000 registers CFG_REG0 0x000 32 read-write 0x0 REMAP 1 = REMAP Block RAM to ZBT [0:0] CFG_REG1 0x004 32 read-write 0x0 MCC_LED7 MCC LEDs: 0 = OFF 1 = ON [7:7] Off LED is off 0 On LED is on 1 MCC_LED6 MCC LEDs: 0 = OFF 1 = ON [6:6] Off LED is off 0 On LED is on 1 MCC_LED5 MCC LEDs: 0 = OFF 1 = ON [5:5] Off LED is off 0 On LED is on 1 MCC_LED4 MCC LEDs: 0 = OFF 1 = ON [4:4] Off LED is off 0 On LED is on 1 MCC_LED3 MCC LEDs: 0 = OFF 1 = ON [3:3] Off LED is off 0 On LED is on 1 MCC_LED2 MCC LEDs: 0 = OFF 1 = ON [2:2] Off LED is off 0 On LED is on 1 MCC_LED1 MCC LEDs: 0 = OFF 1 = ON [1:1] Off LED is off 0 On LED is on 1 MCC_LED0 MCC LEDs: 0 = OFF 1 = ON [0:0] Off LED is off 0 On LED is on 1 CFG_REG2 0x008 32 read-only 0x0 CFG_REG3 0x00C 32 read-only 0x0 MCC_SWITCHE7 MCC SWITCHES: 0 = OFF 1 = ON [7:7] Off Switch is off 0 On Switch is on 1 MCC_SWITCHE6 MCC SWITCHES: 0 = OFF 1 = ON [6:6] Off Switch is off 0 On Switch is on 1 MCC_SWITCHE5 MCC SWITCHES: 0 = OFF 1 = ON [5:5] Off Switch is off 0 On Switch is on 1 MCC_SWITCHE4 MCC SWITCHES: 0 = OFF 1 = ON [4:4] Off Switch is off 0 On Switch is on 1 MCC_SWITCHE3 MCC SWITCHES: 0 = OFF 1 = ON [3:3] Off Switch is off 0 On Switch is on 1 MCC_SWITCHE2 MCC SWITCHES: 0 = OFF 1 = ON [2:2] Off Switch is off 0 On Switch is on 1 MCC_SWITCHE1 MCC SWITCHES: 0 = OFF 1 = ON [1:1] Off Switch is off 0 On Switch is on 1 MCC_SWITCHE0 MCC SWITCHES: 0 = OFF 1 = ON [0:0] Off Switch is off 0 On Switch is on 1 CFG_REG4 0x010 32 read-only 0x0 BRDREV Board Revision [3:0] CFG_REG5 0x014 32 read-write 0x0 DEBUG Debug: 0 = Serial Wire Debug 1 = JTAG [5:5] CFG_REG6 0x018 32 read-only 0x0 CFG_REG7 0x01C 32 read-only 0x0 SYS_CFGDATA_RTN 0x0A0 32 read-write 0x0 SYS_CFGDATA_OUT 0x0A4 32 read-write 0x0 SYS_CFGCTRL 0x0A8 32 read-write 0x0 START Start: generates interrupt on write to this bit [31:31] RW_ACCESS Read/Write Access [30:30] RFUNCVAL Function Value [25:20] DEVICE Device (value of 0/1/2 for supported clocks [11:0] SYS_CFGSTAT 0x0AC 32 read-write 0x0 ERROR Error Flag [1:1] COMPLETE Complete Flag [0:0] DLL DLL Lock Register 0x100 32 read-write 0x0 LOCKED_MASKED Error Flag [31:24] LOCK_UNLOCK Complete Flag [23:16] LOCKED Complete Flag [0:0] AID 0xFF8 32 read-only 0x0 FPGA_BUILD FPGA Build Number [31:24] MPS2_REV V2M-MPS2 target Board Revision (A=0,B=1,C=2) [23:20] NUM_CFG_REG Number of SCC configuration register [7:0] ID 0xFFC 32 read-only 0x0 IMPLEMENTER_ID Implementer ID: 0x41 = ARM [31:24] APP_NOTE_VAR Application note IP variant number [23:20] IP_ARCH IP Architecture: 0x4 = AHB [19:16] PRI_NUM Primary Part Number: 383 = AN383 [11:4] APP_REV Application note IP revision number [3:0]