Texas Instruments ti.com MSP432E411Y MSP432E4 3.200 ARM Cortex-M4 MSP432E4 Device \n Software License Agreement\n \n Texas Instruments (TI) is supplying this software for use solely and\n exclusively on TI's microcontroller products. The software is owned by\n TI and/or its suppliers, and is protected under applicable copyright\n laws. You may not combine this software with "viral" open-source\n software in order to form a larger program.\n \n THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.\n NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT\n NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY\n CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL\n DAMAGES, FOR ANY REASON WHATSOEVER.\n \n CM4 r1p2 little false true 3 false 8 32 32 read-write 0 0 WATCHDOG0 Register map for WATCHDOG0 peripheral WATCHDOG WATCHDOG0 0x40000000 0 0x00001000 registers WATCHDOG018 LOAD Watchdog Load 0x00000000 WDT_LOAD Watchdog Load Value [31:0] VALUE Watchdog Value 0x00000004 WDT_VALUE Watchdog Value [31:0] CTL Watchdog Control 0x00000008 WDT_CTL_INTEN Watchdog Interrupt Enable [0:0] WDT_CTL_RESEN Watchdog Reset Enable [1:1] WDT_CTL_INTTYPE Watchdog Interrupt Type [2:2] WDT_CTL_WRC Write Complete [31:31] ICR Watchdog Interrupt Clear 0x0000000C write-only WDT_ICR Watchdog Interrupt Clear [31:0] write-only RIS Watchdog Raw Interrupt Status 0x00000010 WDT_RIS_WDTRIS Watchdog Raw Interrupt Status [0:0] MIS Watchdog Masked Interrupt Status 0x00000014 WDT_MIS_WDTMIS Watchdog Masked Interrupt Status [0:0] TEST Watchdog Test 0x00000418 WDT_TEST_STALL Watchdog Stall Enable [8:8] LOCK Watchdog Lock 0x00000C00 WDT_LOCK Watchdog Lock [31:0] WDT_LOCK_UNLOCKED Unlocked 0x0 WDT_LOCK_LOCKED Locked 0x1 WATCHDOG1 WATCHDOG1 0x40001000 SSI0 Register map for SSI0 peripheral SSI SSI0 0x40008000 0 0x00001000 registers SSI07 CR0 SSI Control 0 0x00000000 SSI_CR0_DSS SSI Data Size Select [3:0] SSI_CR0_DSS_4 4-bit data 0x3 SSI_CR0_DSS_5 5-bit data 0x4 SSI_CR0_DSS_6 6-bit data 0x5 SSI_CR0_DSS_7 7-bit data 0x6 SSI_CR0_DSS_8 8-bit data 0x7 SSI_CR0_DSS_9 9-bit data 0x8 SSI_CR0_DSS_10 10-bit data 0x9 SSI_CR0_DSS_11 11-bit data 0xa SSI_CR0_DSS_12 12-bit data 0xb SSI_CR0_DSS_13 13-bit data 0xc SSI_CR0_DSS_14 14-bit data 0xd SSI_CR0_DSS_15 15-bit data 0xe SSI_CR0_DSS_16 16-bit data 0xf SSI_CR0_FRF SSI Frame Format Select [5:4] SSI_CR0_FRF_MOTO Freescale SPI Frame Format 0x0 SSI_CR0_FRF_TI Synchronous Serial Frame Format 0x1 SSI_CR0_SPO SSI Serial Clock Polarity [6:6] SSI_CR0_SPH SSI Serial Clock Phase [7:7] SSI_CR0_SCR SSI Serial Clock Rate [15:8] CR1 SSI Control 1 0x00000004 SSI_CR1_LBM SSI Loopback Mode [0:0] SSI_CR1_SSE SSI Synchronous Serial Port Enable [1:1] SSI_CR1_MS SSI Master/Slave Select [2:2] SSI_CR1_EOT End of Transmission [4:4] SSI_CR1_MODE SSI Mode [7:6] SSI_CR1_MODE_LEGACY Legacy SSI mode 0x0 SSI_CR1_MODE_BI Bi-SSI mode 0x1 SSI_CR1_MODE_QUAD Quad-SSI Mode 0x2 SSI_CR1_MODE_ADVANCED Advanced SSI Mode with 8-bit packet size 0x3 SSI_CR1_DIR SSI Direction of Operation [8:8] SSI_CR1_HSCLKEN High Speed Clock Enable [9:9] SSI_CR1_FSSHLDFRM FSS Hold Frame [10:10] SSI_CR1_EOM Stop Frame (End of Message) [11:11] DR SSI Data 0x00000008 SSI_DR_DATA SSI Receive/Transmit Data [15:0] SR SSI Status 0x0000000C SSI_SR_TFE SSI Transmit FIFO Empty [0:0] SSI_SR_TNF SSI Transmit FIFO Not Full [1:1] SSI_SR_RNE SSI Receive FIFO Not Empty [2:2] SSI_SR_RFF SSI Receive FIFO Full [3:3] SSI_SR_BSY SSI Busy Bit [4:4] CPSR SSI Clock Prescale 0x00000010 SSI_CPSR_CPSDVSR SSI Clock Prescale Divisor [7:0] IM SSI Interrupt Mask 0x00000014 SSI_IM_RORIM SSI Receive Overrun Interrupt Mask [0:0] SSI_IM_RTIM SSI Receive Time-Out Interrupt Mask [1:1] SSI_IM_RXIM SSI Receive FIFO Interrupt Mask [2:2] SSI_IM_TXIM SSI Transmit FIFO Interrupt Mask [3:3] SSI_IM_DMARXIM SSI Receive DMA Interrupt Mask [4:4] SSI_IM_DMATXIM SSI Transmit DMA Interrupt Mask [5:5] SSI_IM_EOTIM End of Transmit Interrupt Mask [6:6] RIS SSI Raw Interrupt Status 0x00000018 SSI_RIS_RORRIS SSI Receive Overrun Raw Interrupt Status [0:0] SSI_RIS_RTRIS SSI Receive Time-Out Raw Interrupt Status [1:1] SSI_RIS_RXRIS SSI Receive FIFO Raw Interrupt Status [2:2] SSI_RIS_TXRIS SSI Transmit FIFO Raw Interrupt Status [3:3] SSI_RIS_DMARXRIS SSI Receive DMA Raw Interrupt Status [4:4] SSI_RIS_DMATXRIS SSI Transmit DMA Raw Interrupt Status [5:5] SSI_RIS_EOTRIS End of Transmit Raw Interrupt Status [6:6] MIS SSI Masked Interrupt Status 0x0000001C SSI_MIS_RORMIS SSI Receive Overrun Masked Interrupt Status [0:0] SSI_MIS_RTMIS SSI Receive Time-Out Masked Interrupt Status [1:1] SSI_MIS_RXMIS SSI Receive FIFO Masked Interrupt Status [2:2] SSI_MIS_TXMIS SSI Transmit FIFO Masked Interrupt Status [3:3] SSI_MIS_DMARXMIS SSI Receive DMA Masked Interrupt Status [4:4] SSI_MIS_DMATXMIS SSI Transmit DMA Masked Interrupt Status [5:5] SSI_MIS_EOTMIS End of Transmit Masked Interrupt Status [6:6] ICR SSI Interrupt Clear 0x00000020 write-only SSI_ICR_RORIC SSI Receive Overrun Interrupt Clear [0:0] write-only SSI_ICR_RTIC SSI Receive Time-Out Interrupt Clear [1:1] write-only SSI_ICR_DMARXIC SSI Receive DMA Interrupt Clear [4:4] write-only SSI_ICR_DMATXIC SSI Transmit DMA Interrupt Clear [5:5] write-only SSI_ICR_EOTIC End of Transmit Interrupt Clear [6:6] write-only DMACTL SSI DMA Control 0x00000024 SSI_DMACTL_RXDMAE Receive DMA Enable [0:0] SSI_DMACTL_TXDMAE Transmit DMA Enable [1:1] PP SSI Peripheral Properties 0x00000FC0 SSI_PP_HSCLK High Speed Capability [0:0] SSI_PP_MODE Mode of Operation [2:1] SSI_PP_MODE_LEGACY Legacy SSI mode 0x0 SSI_PP_MODE_ADVBI Legacy mode, Advanced SSI mode and Bi-SSI mode enabled 0x1 SSI_PP_MODE_ADVBIQUAD Legacy mode, Advanced mode, Bi-SSI and Quad-SSI mode enabled 0x2 SSI_PP_FSSHLDFRM FSS Hold Frame Capability [3:3] CC SSI Clock Configuration 0x00000FC8 SSI_CC_CS SSI Baud Clock Source [3:0] SSI_CC_CS_SYSPLL System clock (based on clock source and divisor factor) 0x0 SSI_CC_CS_PIOSC PIOSC 0x5 SSI1 SSI1 0x40009000 SSI134 SSI2 SSI2 0x4000A000 SSI254 SSI3 SSI3 0x4000B000 SSI355 UART0 Register map for UART0 peripheral UART UART0 0x4000C000 0 0x00001000 registers UART05 DR UART Data 0x00000000 UART_DR_DATA Data Transmitted or Received [7:0] UART_DR_FE UART Framing Error [8:8] UART_DR_PE UART Parity Error [9:9] UART_DR_BE UART Break Error [10:10] UART_DR_OE UART Overrun Error [11:11] RSR UART Receive Status/Error Clear 0x00000004 UART_RSR_FE UART Framing Error [0:0] UART_RSR_PE UART Parity Error [1:1] UART_RSR_BE UART Break Error [2:2] UART_RSR_OE UART Overrun Error [3:3] ECR UART Receive Status/Error Clear UART_ALT 0x00000004 UART_ECR_DATA Error Clear [7:0] FR UART Flag 0x00000018 UART_FR_CTS Clear To Send [0:0] UART_FR_DSR Data Set Ready [1:1] UART_FR_DCD Data Carrier Detect [2:2] UART_FR_BUSY UART Busy [3:3] UART_FR_RXFE UART Receive FIFO Empty [4:4] UART_FR_TXFF UART Transmit FIFO Full [5:5] UART_FR_RXFF UART Receive FIFO Full [6:6] UART_FR_TXFE UART Transmit FIFO Empty [7:7] UART_FR_RI Ring Indicator [8:8] ILPR UART IrDA Low-Power Register 0x00000020 UART_ILPR_ILPDVSR IrDA Low-Power Divisor [7:0] IBRD UART Integer Baud-Rate Divisor 0x00000024 UART_IBRD_DIVINT Integer Baud-Rate Divisor [15:0] FBRD UART Fractional Baud-Rate Divisor 0x00000028 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor [5:0] LCRH UART Line Control 0x0000002C UART_LCRH_BRK UART Send Break [0:0] UART_LCRH_PEN UART Parity Enable [1:1] UART_LCRH_EPS UART Even Parity Select [2:2] UART_LCRH_STP2 UART Two Stop Bits Select [3:3] UART_LCRH_FEN UART Enable FIFOs [4:4] UART_LCRH_WLEN UART Word Length [6:5] UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 UART_LCRH_SPS UART Stick Parity Select [7:7] CTL UART Control 0x00000030 UART_CTL_UARTEN UART Enable [0:0] UART_CTL_SIREN UART SIR Enable [1:1] UART_CTL_SIRLP UART SIR Low-Power Mode [2:2] UART_CTL_SMART ISO 7816 Smart Card Support [3:3] UART_CTL_EOT End of Transmission [4:4] UART_CTL_HSE High-Speed Enable [5:5] UART_CTL_LBE UART Loop Back Enable [7:7] UART_CTL_TXE UART Transmit Enable [8:8] UART_CTL_RXE UART Receive Enable [9:9] UART_CTL_DTR Data Terminal Ready [10:10] UART_CTL_RTS Request to Send [11:11] UART_CTL_RTSEN Enable Request to Send [14:14] UART_CTL_CTSEN Enable Clear To Send [15:15] IFLS UART Interrupt FIFO Level Select 0x00000034 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select [2:0] UART_IFLS_TX1_8 TX FIFO <= 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO <= 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO <= 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO <= 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO <= 7/8 full 0x4 UART_IFLS_RX UART Receive Interrupt FIFO Level Select [5:3] UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 IM UART Interrupt Mask 0x00000038 UART_IM_RIMIM UART Ring Indicator Modem Interrupt Mask [0:0] UART_IM_CTSMIM UART Clear to Send Modem Interrupt Mask [1:1] UART_IM_DCDMIM UART Data Carrier Detect Modem Interrupt Mask [2:2] UART_IM_DSRMIM UART Data Set Ready Modem Interrupt Mask [3:3] UART_IM_RXIM UART Receive Interrupt Mask [4:4] UART_IM_TXIM UART Transmit Interrupt Mask [5:5] UART_IM_RTIM UART Receive Time-Out Interrupt Mask [6:6] UART_IM_FEIM UART Framing Error Interrupt Mask [7:7] UART_IM_PEIM UART Parity Error Interrupt Mask [8:8] UART_IM_BEIM UART Break Error Interrupt Mask [9:9] UART_IM_OEIM UART Overrun Error Interrupt Mask [10:10] UART_IM_EOTIM End of Transmission Interrupt Mask [11:11] UART_IM_9BITIM 9-Bit Mode Interrupt Mask [12:12] UART_IM_DMARXIM Receive DMA Interrupt Mask [16:16] UART_IM_DMATXIM Transmit DMA Interrupt Mask [17:17] RIS UART Raw Interrupt Status 0x0000003C UART_RIS_RIRIS UART Ring Indicator Modem Raw Interrupt Status [0:0] UART_RIS_CTSRIS UART Clear to Send Modem Raw Interrupt Status [1:1] UART_RIS_DCDRIS UART Data Carrier Detect Modem Raw Interrupt Status [2:2] UART_RIS_DSRRIS UART Data Set Ready Modem Raw Interrupt Status [3:3] UART_RIS_RXRIS UART Receive Raw Interrupt Status [4:4] UART_RIS_TXRIS UART Transmit Raw Interrupt Status [5:5] UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status [6:6] UART_RIS_FERIS UART Framing Error Raw Interrupt Status [7:7] UART_RIS_PERIS UART Parity Error Raw Interrupt Status [8:8] UART_RIS_BERIS UART Break Error Raw Interrupt Status [9:9] UART_RIS_OERIS UART Overrun Error Raw Interrupt Status [10:10] UART_RIS_EOTRIS End of Transmission Raw Interrupt Status [11:11] UART_RIS_9BITRIS 9-Bit Mode Raw Interrupt Status [12:12] UART_RIS_DMARXRIS Receive DMA Raw Interrupt Status [16:16] UART_RIS_DMATXRIS Transmit DMA Raw Interrupt Status [17:17] MIS UART Masked Interrupt Status 0x00000040 UART_MIS_RIMIS UART Ring Indicator Modem Masked Interrupt Status [0:0] UART_MIS_CTSMIS UART Clear to Send Modem Masked Interrupt Status [1:1] UART_MIS_DCDMIS UART Data Carrier Detect Modem Masked Interrupt Status [2:2] UART_MIS_DSRMIS UART Data Set Ready Modem Masked Interrupt Status [3:3] UART_MIS_RXMIS UART Receive Masked Interrupt Status [4:4] UART_MIS_TXMIS UART Transmit Masked Interrupt Status [5:5] UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status [6:6] UART_MIS_FEMIS UART Framing Error Masked Interrupt Status [7:7] UART_MIS_PEMIS UART Parity Error Masked Interrupt Status [8:8] UART_MIS_BEMIS UART Break Error Masked Interrupt Status [9:9] UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status [10:10] UART_MIS_EOTMIS End of Transmission Masked Interrupt Status [11:11] UART_MIS_9BITMIS 9-Bit Mode Masked Interrupt Status [12:12] UART_MIS_DMARXMIS Receive DMA Masked Interrupt Status [16:16] UART_MIS_DMATXMIS Transmit DMA Masked Interrupt Status [17:17] ICR UART Interrupt Clear 0x00000044 write-only UART_ICR_RIMIC UART Ring Indicator Modem Interrupt Clear [0:0] write-only UART_ICR_CTSMIC UART Clear to Send Modem Interrupt Clear [1:1] write-only UART_ICR_DCDMIC UART Data Carrier Detect Modem Interrupt Clear [2:2] write-only UART_ICR_DSRMIC UART Data Set Ready Modem Interrupt Clear [3:3] write-only UART_ICR_RXIC Receive Interrupt Clear [4:4] write-only UART_ICR_TXIC Transmit Interrupt Clear [5:5] write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear [6:6] write-only UART_ICR_FEIC Framing Error Interrupt Clear [7:7] write-only UART_ICR_PEIC Parity Error Interrupt Clear [8:8] write-only UART_ICR_BEIC Break Error Interrupt Clear [9:9] write-only UART_ICR_OEIC Overrun Error Interrupt Clear [10:10] write-only UART_ICR_EOTIC End of Transmission Interrupt Clear [11:11] write-only UART_ICR_9BITIC 9-Bit Mode Interrupt Clear [12:12] write-only UART_ICR_DMARXIC Receive DMA Interrupt Clear [16:16] write-only UART_ICR_DMATXIC Transmit DMA Interrupt Clear [17:17] write-only DMACTL UART DMA Control 0x00000048 UART_DMACTL_RXDMAE Receive DMA Enable [0:0] UART_DMACTL_TXDMAE Transmit DMA Enable [1:1] UART_DMACTL_DMAERR DMA on Error [2:2] _9BITADDR UART 9-Bit Self Address 0x000000A4 UART_9BITADDR_ADDR Self Address for 9-Bit Mode [7:0] UART_9BITADDR_9BITEN Enable 9-Bit Mode [15:15] _9BITAMASK UART 9-Bit Self Address Mask 0x000000A8 UART_9BITAMASK_MASK Self Address Mask for 9-Bit Mode [7:0] PP UART Peripheral Properties 0x00000FC0 UART_PP_SC Smart Card Support [0:0] UART_PP_NB 9-Bit Support [1:1] UART_PP_MS Modem Support [2:2] UART_PP_MSE Modem Support Extended [3:3] CC UART Clock Configuration 0x00000FC8 UART_CC_CS UART Baud Clock Source [3:0] UART_CC_CS_SYSCLK System clock (based on clock source and divisor factor) 0x0 UART_CC_CS_PIOSC PIOSC 0x5 UART1 UART1 0x4000D000 UART16 UART2 UART2 0x4000E000 UART233 UART3 UART3 0x4000F000 UART356 UART4 UART4 0x40010000 UART457 UART5 UART5 0x40011000 UART558 UART6 UART6 0x40012000 UART659 UART7 UART7 0x40013000 UART760 I2C0 Register map for I2C0 peripheral I2C I2C0 0x40020000 0 0x00001000 registers I2C08 MSA I2C Master Slave Address 0x00000000 I2C_MSA_RS Receive not send [0:0] I2C_MSA_SA I2C Slave Address [7:1] MCS I2C Master Control/Status 0x00000004 I2C_MCS_RUN I2C Master Enable [0:0] I2C_MCS_START Generate START [1:1] I2C_MCS_ADRACK Acknowledge Address [2:2] I2C_MCS_ACK Data Acknowledge Enable [3:3] I2C_MCS_ARBLST Arbitration Lost [4:4] I2C_MCS_IDLE I2C Idle [5:5] I2C_MCS_BURST Burst Enable [6:6] I2C_MCS_CLKTO Clock Timeout Error [7:7] I2C_MCS_ACTDMATX DMA TX Active Status [30:30] I2C_MCS_ACTDMARX DMA RX Active Status [31:31] MCS I2C Master Control/Status I2C0_ALT 0x00000004 I2C_MCS_BUSY I2C Busy [0:0] I2C_MCS_ERROR Error [1:1] I2C_MCS_STOP Generate STOP [2:2] I2C_MCS_DATACK Acknowledge Data [3:3] I2C_MCS_HS High-Speed Enable [4:4] I2C_MCS_QCMD Quick Command [5:5] I2C_MCS_BUSBSY Bus Busy [6:6] MDR I2C Master Data 0x00000008 I2C_MDR_DATA This byte contains the data transferred during a transaction [7:0] MTPR I2C Master Timer Period 0x0000000C I2C_MTPR_TPR Timer Period [6:0] I2C_MTPR_HS High-Speed Enable [7:7] I2C_MTPR_PULSEL Glitch Suppression Pulse Width [18:16] I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 MIMR I2C Master Interrupt Mask 0x00000010 I2C_MIMR_IM Master Interrupt Mask [0:0] I2C_MIMR_CLKIM Clock Timeout Interrupt Mask [1:1] I2C_MIMR_DMARXIM Receive DMA Interrupt Mask [2:2] I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask [3:3] I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask [4:4] I2C_MIMR_STARTIM START Detection Interrupt Mask [5:5] I2C_MIMR_STOPIM STOP Detection Interrupt Mask [6:6] I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask [7:7] I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask [8:8] I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask [9:9] I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask [10:10] I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask [11:11] MRIS I2C Master Raw Interrupt Status 0x00000014 I2C_MRIS_RIS Master Raw Interrupt Status [0:0] I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status [1:1] I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status [2:2] I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status [3:3] I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status [4:4] I2C_MRIS_STARTRIS START Detection Raw Interrupt Status [5:5] I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status [6:6] I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status [7:7] I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status [8:8] I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status [9:9] I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status [10:10] I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status [11:11] MMIS I2C Master Masked Interrupt Status 0x00000018 I2C_MMIS_MIS Masked Interrupt Status [0:0] I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status [1:1] I2C_MMIS_DMARXMIS Receive DMA Interrupt Status [2:2] I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status [3:3] I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask [4:4] I2C_MMIS_STARTMIS START Detection Interrupt Mask [5:5] I2C_MMIS_STOPMIS STOP Detection Interrupt Mask [6:6] I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask [7:7] I2C_MMIS_TXMIS Transmit Request Interrupt Mask [8:8] I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask [9:9] I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask [10:10] I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask [11:11] MICR I2C Master Interrupt Clear 0x0000001C write-only I2C_MICR_IC Master Interrupt Clear [0:0] write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear [1:1] write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear [2:2] write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear [3:3] write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear [4:4] write-only I2C_MICR_STARTIC START Detection Interrupt Clear [5:5] write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear [6:6] write-only I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear [7:7] write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear [8:8] write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear [9:9] write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear [10:10] write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear [11:11] write-only MCR I2C Master Configuration 0x00000020 I2C_MCR_LPBK I2C Loopback [0:0] I2C_MCR_MFE I2C Master Function Enable [4:4] I2C_MCR_SFE I2C Slave Function Enable [5:5] MCLKOCNT I2C Master Clock Low Timeout Count 0x00000024 I2C_MCLKOCNT_CNTL I2C Master Count [7:0] MBMON I2C Master Bus Monitor 0x0000002C I2C_MBMON_SCL I2C SCL Status [0:0] I2C_MBMON_SDA I2C SDA Status [1:1] MBLEN I2C Master Burst Length 0x00000030 I2C_MBLEN_CNTL I2C Burst Length [7:0] MBCNT I2C Master Burst Count 0x00000034 I2C_MBCNT_CNTL I2C Master Burst Count [7:0] SOAR I2C Slave Own Address 0x00000800 I2C_SOAR_OAR I2C Slave Own Address [6:0] SCSR I2C Slave Control/Status 0x00000804 I2C_SCSR_RREQ Receive Request [0:0] I2C_SCSR_TXFIFO TX FIFO Enable [1:1] I2C_SCSR_FBR First Byte Received [2:2] I2C_SCSR_OAR2SEL OAR2 Address Matched [3:3] I2C_SCSR_QCMDST Quick Command Status [4:4] I2C_SCSR_QCMDRW Quick Command Read / Write [5:5] I2C_SCSR_ACTDMATX DMA TX Active Status [30:30] I2C_SCSR_ACTDMARX DMA RX Active Status [31:31] SCSR I2C Slave Control/Status I2C0_ALT 0x00000804 I2C_SCSR_DA Device Active [0:0] I2C_SCSR_TREQ Transmit Request [1:1] I2C_SCSR_RXFIFO RX FIFO Enable [2:2] SDR I2C Slave Data 0x00000808 I2C_SDR_DATA Data for Transfer [7:0] SIMR I2C Slave Interrupt Mask 0x0000080C I2C_SIMR_DATAIM Data Interrupt Mask [0:0] I2C_SIMR_STARTIM Start Condition Interrupt Mask [1:1] I2C_SIMR_STOPIM Stop Condition Interrupt Mask [2:2] I2C_SIMR_DMARXIM Receive DMA Interrupt Mask [3:3] I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask [4:4] I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask [5:5] I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask [6:6] I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask [7:7] I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask [8:8] SRIS I2C Slave Raw Interrupt Status 0x00000810 I2C_SRIS_DATARIS Data Raw Interrupt Status [0:0] I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status [1:1] I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status [2:2] I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status [3:3] I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status [4:4] I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status [5:5] I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status [6:6] I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status [7:7] I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status [8:8] SMIS I2C Slave Masked Interrupt Status 0x00000814 I2C_SMIS_DATAMIS Data Masked Interrupt Status [0:0] I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status [1:1] I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status [2:2] I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status [3:3] I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status [4:4] I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask [5:5] I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask [6:6] I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask [7:7] I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask [8:8] SICR I2C Slave Interrupt Clear 0x00000818 write-only I2C_SICR_DATAIC Data Interrupt Clear [0:0] write-only I2C_SICR_STARTIC Start Condition Interrupt Clear [1:1] write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear [2:2] write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear [3:3] write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear [4:4] write-only I2C_SICR_TXIC Transmit Request Interrupt Mask [5:5] write-only I2C_SICR_RXIC Receive Request Interrupt Mask [6:6] write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask [7:7] write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask [8:8] write-only SOAR2 I2C Slave Own Address 2 0x0000081C I2C_SOAR2_OAR2 I2C Slave Own Address 2 [6:0] I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable [7:7] SACKCTL I2C Slave ACK Control 0x00000820 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable [0:0] I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value [1:1] FIFODATA I2C FIFO Data 0x00000F00 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte [7:0] FIFOCTL I2C FIFO Control 0x00000F04 I2C_FIFOCTL_TXTRIG TX FIFO Trigger [2:0] I2C_FIFOCTL_DMATXENA DMA TX Channel Enable [13:13] I2C_FIFOCTL_TXFLUSH TX FIFO Flush [14:14] I2C_FIFOCTL_TXASGNMT TX Control Assignment [15:15] I2C_FIFOCTL_RXTRIG RX FIFO Trigger [18:16] I2C_FIFOCTL_DMARXENA DMA RX Channel Enable [29:29] I2C_FIFOCTL_RXFLUSH RX FIFO Flush [30:30] I2C_FIFOCTL_RXASGNMT RX Control Assignment [31:31] FIFOSTATUS I2C FIFO Status 0x00000F08 I2C_FIFOSTATUS_TXFE TX FIFO Empty [0:0] I2C_FIFOSTATUS_TXFF TX FIFO Full [1:1] I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level [2:2] I2C_FIFOSTATUS_RXFE RX FIFO Empty [16:16] I2C_FIFOSTATUS_RXFF RX FIFO Full [17:17] I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level [18:18] PP I2C Peripheral Properties 0x00000FC0 I2C_PP_HS High-Speed Capable [0:0] PC I2C Peripheral Configuration 0x00000FC4 I2C_PC_HS High-Speed Capable [0:0] I2C1 I2C1 0x40021000 I2C137 I2C2 I2C2 0x40022000 I2C261 I2C3 I2C3 0x40023000 I2C362 PWM0 Register map for PWM0 peripheral PWM PWM0 0x40028000 0 0x00001000 registers PWM0_010 PWM0_111 PWM0_212 PWM0_343 PWM0_FAULT9 CTL PWM Master Control 0x00000000 PWM_CTL_GLOBALSYNC0 Update PWM Generator 0 [0:0] PWM_CTL_GLOBALSYNC1 Update PWM Generator 1 [1:1] PWM_CTL_GLOBALSYNC2 Update PWM Generator 2 [2:2] PWM_CTL_GLOBALSYNC3 Update PWM Generator 3 [3:3] SYNC PWM Time Base Sync 0x00000004 PWM_SYNC_SYNC0 Reset Generator 0 Counter [0:0] PWM_SYNC_SYNC1 Reset Generator 1 Counter [1:1] PWM_SYNC_SYNC2 Reset Generator 2 Counter [2:2] PWM_SYNC_SYNC3 Reset Generator 3 Counter [3:3] ENABLE PWM Output Enable 0x00000008 PWM_ENABLE_PWM0EN MnPWM0 Output Enable [0:0] PWM_ENABLE_PWM1EN MnPWM1 Output Enable [1:1] PWM_ENABLE_PWM2EN MnPWM2 Output Enable [2:2] PWM_ENABLE_PWM3EN MnPWM3 Output Enable [3:3] PWM_ENABLE_PWM4EN MnPWM4 Output Enable [4:4] PWM_ENABLE_PWM5EN MnPWM5 Output Enable [5:5] PWM_ENABLE_PWM6EN MnPWM6 Output Enable [6:6] PWM_ENABLE_PWM7EN MnPWM7 Output Enable [7:7] INVERT PWM Output Inversion 0x0000000C PWM_INVERT_PWM0INV Invert MnPWM0 Signal [0:0] PWM_INVERT_PWM1INV Invert MnPWM1 Signal [1:1] PWM_INVERT_PWM2INV Invert MnPWM2 Signal [2:2] PWM_INVERT_PWM3INV Invert MnPWM3 Signal [3:3] PWM_INVERT_PWM4INV Invert MnPWM4 Signal [4:4] PWM_INVERT_PWM5INV Invert MnPWM5 Signal [5:5] PWM_INVERT_PWM6INV Invert MnPWM6 Signal [6:6] PWM_INVERT_PWM7INV Invert MnPWM7 Signal [7:7] FAULT PWM Output Fault 0x00000010 PWM_FAULT_FAULT0 MnPWM0 Fault [0:0] PWM_FAULT_FAULT1 MnPWM1 Fault [1:1] PWM_FAULT_FAULT2 MnPWM2 Fault [2:2] PWM_FAULT_FAULT3 MnPWM3 Fault [3:3] PWM_FAULT_FAULT4 MnPWM4 Fault [4:4] PWM_FAULT_FAULT5 MnPWM5 Fault [5:5] PWM_FAULT_FAULT6 MnPWM6 Fault [6:6] PWM_FAULT_FAULT7 MnPWM7 Fault [7:7] INTEN PWM Interrupt Enable 0x00000014 PWM_INTEN_INTPWM0 PWM0 Interrupt Enable [0:0] PWM_INTEN_INTPWM1 PWM1 Interrupt Enable [1:1] PWM_INTEN_INTPWM2 PWM2 Interrupt Enable [2:2] PWM_INTEN_INTPWM3 PWM3 Interrupt Enable [3:3] PWM_INTEN_INTFAULT0 Interrupt Fault 0 [16:16] PWM_INTEN_INTFAULT1 Interrupt Fault 1 [17:17] PWM_INTEN_INTFAULT2 Interrupt Fault 2 [18:18] PWM_INTEN_INTFAULT3 Interrupt Fault 3 [19:19] RIS PWM Raw Interrupt Status 0x00000018 PWM_RIS_INTPWM0 PWM0 Interrupt Asserted [0:0] PWM_RIS_INTPWM1 PWM1 Interrupt Asserted [1:1] PWM_RIS_INTPWM2 PWM2 Interrupt Asserted [2:2] PWM_RIS_INTPWM3 PWM3 Interrupt Asserted [3:3] PWM_RIS_INTFAULT0 Interrupt Fault PWM 0 [16:16] PWM_RIS_INTFAULT1 Interrupt Fault PWM 1 [17:17] PWM_RIS_INTFAULT2 Interrupt Fault PWM 2 [18:18] PWM_RIS_INTFAULT3 Interrupt Fault PWM 3 [19:19] ISC PWM Interrupt Status and Clear 0x0000001C PWM_ISC_INTPWM0 PWM0 Interrupt Status [0:0] PWM_ISC_INTPWM1 PWM1 Interrupt Status [1:1] PWM_ISC_INTPWM2 PWM2 Interrupt Status [2:2] PWM_ISC_INTPWM3 PWM3 Interrupt Status [3:3] PWM_ISC_INTFAULT0 FAULT0 Interrupt Asserted [16:16] PWM_ISC_INTFAULT1 FAULT1 Interrupt Asserted [17:17] PWM_ISC_INTFAULT2 FAULT2 Interrupt Asserted [18:18] PWM_ISC_INTFAULT3 FAULT3 Interrupt Asserted [19:19] STATUS PWM Status 0x00000020 PWM_STATUS_FAULT0 Generator 0 Fault Status [0:0] PWM_STATUS_FAULT1 Generator 1 Fault Status [1:1] PWM_STATUS_FAULT2 Generator 2 Fault Status [2:2] PWM_STATUS_FAULT3 Generator 3 Fault Status [3:3] FAULTVAL PWM Fault Condition Value 0x00000024 PWM_FAULTVAL_PWM0 MnPWM0 Fault Value [0:0] PWM_FAULTVAL_PWM1 MnPWM1 Fault Value [1:1] PWM_FAULTVAL_PWM2 MnPWM2 Fault Value [2:2] PWM_FAULTVAL_PWM3 MnPWM3 Fault Value [3:3] PWM_FAULTVAL_PWM4 MnPWM4 Fault Value [4:4] PWM_FAULTVAL_PWM5 MnPWM5 Fault Value [5:5] PWM_FAULTVAL_PWM6 MnPWM6 Fault Value [6:6] PWM_FAULTVAL_PWM7 MnPWM7 Fault Value [7:7] ENUPD PWM Enable Update 0x00000028 PWM_ENUPD_ENUPD0 MnPWM0 Enable Update Mode [1:0] PWM_ENUPD_ENUPD0_IMM Immediate 0x0 PWM_ENUPD_ENUPD0_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD0_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD1 MnPWM1 Enable Update Mode [3:2] PWM_ENUPD_ENUPD1_IMM Immediate 0x0 PWM_ENUPD_ENUPD1_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD1_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD2 MnPWM2 Enable Update Mode [5:4] PWM_ENUPD_ENUPD2_IMM Immediate 0x0 PWM_ENUPD_ENUPD2_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD2_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD3 MnPWM3 Enable Update Mode [7:6] PWM_ENUPD_ENUPD3_IMM Immediate 0x0 PWM_ENUPD_ENUPD3_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD3_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD4 MnPWM4 Enable Update Mode [9:8] PWM_ENUPD_ENUPD4_IMM Immediate 0x0 PWM_ENUPD_ENUPD4_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD4_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD5 MnPWM5 Enable Update Mode [11:10] PWM_ENUPD_ENUPD5_IMM Immediate 0x0 PWM_ENUPD_ENUPD5_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD5_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD6 MnPWM6 Enable Update Mode [13:12] PWM_ENUPD_ENUPD6_IMM Immediate 0x0 PWM_ENUPD_ENUPD6_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD6_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD7 MnPWM7 Enable Update Mode [15:14] PWM_ENUPD_ENUPD7_IMM Immediate 0x0 PWM_ENUPD_ENUPD7_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD7_GSYNC Globally Synchronized 0x3 _0_CTL PWM0 Control 0x00000040 PWM_0_CTL_ENABLE PWM Block Enable [0:0] PWM_0_CTL_MODE Counter Mode [1:1] PWM_0_CTL_DEBUG Debug Mode [2:2] PWM_0_CTL_LOADUPD Load Register Update Mode [3:3] PWM_0_CTL_CMPAUPD Comparator A Update Mode [4:4] PWM_0_CTL_CMPBUPD Comparator B Update Mode [5:5] PWM_0_CTL_GENAUPD PWMnGENA Update Mode [7:6] PWM_0_CTL_GENAUPD_I Immediate 0x0 PWM_0_CTL_GENAUPD_LS Locally Synchronized 0x2 PWM_0_CTL_GENAUPD_GS Globally Synchronized 0x3 PWM_0_CTL_GENBUPD PWMnGENB Update Mode [9:8] PWM_0_CTL_GENBUPD_I Immediate 0x0 PWM_0_CTL_GENBUPD_LS Locally Synchronized 0x2 PWM_0_CTL_GENBUPD_GS Globally Synchronized 0x3 PWM_0_CTL_DBCTLUPD PWMnDBCTL Update Mode [11:10] PWM_0_CTL_DBCTLUPD_I Immediate 0x0 PWM_0_CTL_DBCTLUPD_LS Locally Synchronized 0x2 PWM_0_CTL_DBCTLUPD_GS Globally Synchronized 0x3 PWM_0_CTL_DBRISEUPD PWMnDBRISE Update Mode [13:12] PWM_0_CTL_DBRISEUPD_I Immediate 0x0 PWM_0_CTL_DBRISEUPD_LS Locally Synchronized 0x2 PWM_0_CTL_DBRISEUPD_GS Globally Synchronized 0x3 PWM_0_CTL_DBFALLUPD PWMnDBFALL Update Mode [15:14] PWM_0_CTL_DBFALLUPD_I Immediate 0x0 PWM_0_CTL_DBFALLUPD_LS Locally Synchronized 0x2 PWM_0_CTL_DBFALLUPD_GS Globally Synchronized 0x3 PWM_0_CTL_FLTSRC Fault Condition Source [16:16] PWM_0_CTL_MINFLTPER Minimum Fault Period [17:17] PWM_0_CTL_LATCH Latch Fault Input [18:18] _0_INTEN PWM0 Interrupt and Trigger Enable 0x00000044 PWM_0_INTEN_INTCNTZERO Interrupt for Counter=0 [0:0] PWM_0_INTEN_INTCNTLOAD Interrupt for Counter=PWMnLOAD [1:1] PWM_0_INTEN_INTCMPAU Interrupt for Counter=PWMnCMPA Up [2:2] PWM_0_INTEN_INTCMPAD Interrupt for Counter=PWMnCMPA Down [3:3] PWM_0_INTEN_INTCMPBU Interrupt for Counter=PWMnCMPB Up [4:4] PWM_0_INTEN_INTCMPBD Interrupt for Counter=PWMnCMPB Down [5:5] PWM_0_INTEN_TRCNTZERO Trigger for Counter=0 [8:8] PWM_0_INTEN_TRCNTLOAD Trigger for Counter=PWMnLOAD [9:9] PWM_0_INTEN_TRCMPAU Trigger for Counter=PWMnCMPA Up [10:10] PWM_0_INTEN_TRCMPAD Trigger for Counter=PWMnCMPA Down [11:11] PWM_0_INTEN_TRCMPBU Trigger for Counter=PWMnCMPB Up [12:12] PWM_0_INTEN_TRCMPBD Trigger for Counter=PWMnCMPB Down [13:13] _0_RIS PWM0 Raw Interrupt Status 0x00000048 PWM_0_RIS_INTCNTZERO Counter=0 Interrupt Status [0:0] PWM_0_RIS_INTCNTLOAD Counter=Load Interrupt Status [1:1] PWM_0_RIS_INTCMPAU Comparator A Up Interrupt Status [2:2] PWM_0_RIS_INTCMPAD Comparator A Down Interrupt Status [3:3] PWM_0_RIS_INTCMPBU Comparator B Up Interrupt Status [4:4] PWM_0_RIS_INTCMPBD Comparator B Down Interrupt Status [5:5] _0_ISC PWM0 Interrupt Status and Clear 0x0000004C PWM_0_ISC_INTCNTZERO Counter=0 Interrupt [0:0] PWM_0_ISC_INTCNTLOAD Counter=Load Interrupt [1:1] PWM_0_ISC_INTCMPAU Comparator A Up Interrupt [2:2] PWM_0_ISC_INTCMPAD Comparator A Down Interrupt [3:3] PWM_0_ISC_INTCMPBU Comparator B Up Interrupt [4:4] PWM_0_ISC_INTCMPBD Comparator B Down Interrupt [5:5] _0_LOAD PWM0 Load 0x00000050 PWM_0_LOAD Counter Load Value [15:0] _0_COUNT PWM0 Counter 0x00000054 PWM_0_COUNT Counter Value [15:0] _0_CMPA PWM0 Compare A 0x00000058 PWM_0_CMPA Comparator A Value [15:0] _0_CMPB PWM0 Compare B 0x0000005C PWM_0_CMPB Comparator B Value [15:0] _0_GENA PWM0 Generator A Control 0x00000060 PWM_0_GENA_ACTZERO Action for Counter=0 [1:0] PWM_0_GENA_ACTZERO_NONE Do nothing 0x0 PWM_0_GENA_ACTZERO_INV Invert pwmA 0x1 PWM_0_GENA_ACTZERO_ZERO Drive pwmA Low 0x2 PWM_0_GENA_ACTZERO_ONE Drive pwmA High 0x3 PWM_0_GENA_ACTLOAD Action for Counter=LOAD [3:2] PWM_0_GENA_ACTLOAD_NONE Do nothing 0x0 PWM_0_GENA_ACTLOAD_INV Invert pwmA 0x1 PWM_0_GENA_ACTLOAD_ZERO Drive pwmA Low 0x2 PWM_0_GENA_ACTLOAD_ONE Drive pwmA High 0x3 PWM_0_GENA_ACTCMPAU Action for Comparator A Up [5:4] PWM_0_GENA_ACTCMPAU_NONE Do nothing 0x0 PWM_0_GENA_ACTCMPAU_INV Invert pwmA 0x1 PWM_0_GENA_ACTCMPAU_ZERO Drive pwmA Low 0x2 PWM_0_GENA_ACTCMPAU_ONE Drive pwmA High 0x3 PWM_0_GENA_ACTCMPAD Action for Comparator A Down [7:6] PWM_0_GENA_ACTCMPAD_NONE Do nothing 0x0 PWM_0_GENA_ACTCMPAD_INV Invert pwmA 0x1 PWM_0_GENA_ACTCMPAD_ZERO Drive pwmA Low 0x2 PWM_0_GENA_ACTCMPAD_ONE Drive pwmA High 0x3 PWM_0_GENA_ACTCMPBU Action for Comparator B Up [9:8] PWM_0_GENA_ACTCMPBU_NONE Do nothing 0x0 PWM_0_GENA_ACTCMPBU_INV Invert pwmA 0x1 PWM_0_GENA_ACTCMPBU_ZERO Drive pwmA Low 0x2 PWM_0_GENA_ACTCMPBU_ONE Drive pwmA High 0x3 PWM_0_GENA_ACTCMPBD Action for Comparator B Down [11:10] PWM_0_GENA_ACTCMPBD_NONE Do nothing 0x0 PWM_0_GENA_ACTCMPBD_INV Invert pwmA 0x1 PWM_0_GENA_ACTCMPBD_ZERO Drive pwmA Low 0x2 PWM_0_GENA_ACTCMPBD_ONE Drive pwmA High 0x3 _0_GENB PWM0 Generator B Control 0x00000064 PWM_0_GENB_ACTZERO Action for Counter=0 [1:0] PWM_0_GENB_ACTZERO_NONE Do nothing 0x0 PWM_0_GENB_ACTZERO_INV Invert pwmB 0x1 PWM_0_GENB_ACTZERO_ZERO Drive pwmB Low 0x2 PWM_0_GENB_ACTZERO_ONE Drive pwmB High 0x3 PWM_0_GENB_ACTLOAD Action for Counter=LOAD [3:2] PWM_0_GENB_ACTLOAD_NONE Do nothing 0x0 PWM_0_GENB_ACTLOAD_INV Invert pwmB 0x1 PWM_0_GENB_ACTLOAD_ZERO Drive pwmB Low 0x2 PWM_0_GENB_ACTLOAD_ONE Drive pwmB High 0x3 PWM_0_GENB_ACTCMPAU Action for Comparator A Up [5:4] PWM_0_GENB_ACTCMPAU_NONE Do nothing 0x0 PWM_0_GENB_ACTCMPAU_INV Invert pwmB 0x1 PWM_0_GENB_ACTCMPAU_ZERO Drive pwmB Low 0x2 PWM_0_GENB_ACTCMPAU_ONE Drive pwmB High 0x3 PWM_0_GENB_ACTCMPAD Action for Comparator A Down [7:6] PWM_0_GENB_ACTCMPAD_NONE Do nothing 0x0 PWM_0_GENB_ACTCMPAD_INV Invert pwmB 0x1 PWM_0_GENB_ACTCMPAD_ZERO Drive pwmB Low 0x2 PWM_0_GENB_ACTCMPAD_ONE Drive pwmB High 0x3 PWM_0_GENB_ACTCMPBU Action for Comparator B Up [9:8] PWM_0_GENB_ACTCMPBU_NONE Do nothing 0x0 PWM_0_GENB_ACTCMPBU_INV Invert pwmB 0x1 PWM_0_GENB_ACTCMPBU_ZERO Drive pwmB Low 0x2 PWM_0_GENB_ACTCMPBU_ONE Drive pwmB High 0x3 PWM_0_GENB_ACTCMPBD Action for Comparator B Down [11:10] PWM_0_GENB_ACTCMPBD_NONE Do nothing 0x0 PWM_0_GENB_ACTCMPBD_INV Invert pwmB 0x1 PWM_0_GENB_ACTCMPBD_ZERO Drive pwmB Low 0x2 PWM_0_GENB_ACTCMPBD_ONE Drive pwmB High 0x3 _0_DBCTL PWM0 Dead-Band Control 0x00000068 PWM_0_DBCTL_ENABLE Dead-Band Generator Enable [0:0] _0_DBRISE PWM0 Dead-Band Rising-Edge Delay 0x0000006C PWM_0_DBRISE_DELAY Dead-Band Rise Delay [11:0] _0_DBFALL PWM0 Dead-Band Falling-Edge-Delay 0x00000070 PWM_0_DBFALL_DELAY Dead-Band Fall Delay [11:0] _0_FLTSRC0 PWM0 Fault Source 0 0x00000074 PWM_0_FLTSRC0_FAULT0 Fault0 Input [0:0] PWM_0_FLTSRC0_FAULT1 Fault1 Input [1:1] PWM_0_FLTSRC0_FAULT2 Fault2 Input [2:2] PWM_0_FLTSRC0_FAULT3 Fault3 Input [3:3] _0_FLTSRC1 PWM0 Fault Source 1 0x00000078 PWM_0_FLTSRC1_DCMP0 Digital Comparator 0 [0:0] PWM_0_FLTSRC1_DCMP1 Digital Comparator 1 [1:1] PWM_0_FLTSRC1_DCMP2 Digital Comparator 2 [2:2] PWM_0_FLTSRC1_DCMP3 Digital Comparator 3 [3:3] PWM_0_FLTSRC1_DCMP4 Digital Comparator 4 [4:4] PWM_0_FLTSRC1_DCMP5 Digital Comparator 5 [5:5] PWM_0_FLTSRC1_DCMP6 Digital Comparator 6 [6:6] PWM_0_FLTSRC1_DCMP7 Digital Comparator 7 [7:7] _0_MINFLTPER PWM0 Minimum Fault Period 0x0000007C PWM_0_MINFLTPER Minimum Fault Period [15:0] _1_CTL PWM1 Control 0x00000080 PWM_1_CTL_ENABLE PWM Block Enable [0:0] PWM_1_CTL_MODE Counter Mode [1:1] PWM_1_CTL_DEBUG Debug Mode [2:2] PWM_1_CTL_LOADUPD Load Register Update Mode [3:3] PWM_1_CTL_CMPAUPD Comparator A Update Mode [4:4] PWM_1_CTL_CMPBUPD Comparator B Update Mode [5:5] PWM_1_CTL_GENAUPD PWMnGENA Update Mode [7:6] PWM_1_CTL_GENAUPD_I Immediate 0x0 PWM_1_CTL_GENAUPD_LS Locally Synchronized 0x2 PWM_1_CTL_GENAUPD_GS Globally Synchronized 0x3 PWM_1_CTL_GENBUPD PWMnGENB Update Mode [9:8] PWM_1_CTL_GENBUPD_I Immediate 0x0 PWM_1_CTL_GENBUPD_LS Locally Synchronized 0x2 PWM_1_CTL_GENBUPD_GS Globally Synchronized 0x3 PWM_1_CTL_DBCTLUPD PWMnDBCTL Update Mode [11:10] PWM_1_CTL_DBCTLUPD_I Immediate 0x0 PWM_1_CTL_DBCTLUPD_LS Locally Synchronized 0x2 PWM_1_CTL_DBCTLUPD_GS Globally Synchronized 0x3 PWM_1_CTL_DBRISEUPD PWMnDBRISE Update Mode [13:12] PWM_1_CTL_DBRISEUPD_I Immediate 0x0 PWM_1_CTL_DBRISEUPD_LS Locally Synchronized 0x2 PWM_1_CTL_DBRISEUPD_GS Globally Synchronized 0x3 PWM_1_CTL_DBFALLUPD PWMnDBFALL Update Mode [15:14] PWM_1_CTL_DBFALLUPD_I Immediate 0x0 PWM_1_CTL_DBFALLUPD_LS Locally Synchronized 0x2 PWM_1_CTL_DBFALLUPD_GS Globally Synchronized 0x3 PWM_1_CTL_FLTSRC Fault Condition Source [16:16] PWM_1_CTL_MINFLTPER Minimum Fault Period [17:17] PWM_1_CTL_LATCH Latch Fault Input [18:18] _1_INTEN PWM1 Interrupt and Trigger Enable 0x00000084 PWM_1_INTEN_INTCNTZERO Interrupt for Counter=0 [0:0] PWM_1_INTEN_INTCNTLOAD Interrupt for Counter=PWMnLOAD [1:1] PWM_1_INTEN_INTCMPAU Interrupt for Counter=PWMnCMPA Up [2:2] PWM_1_INTEN_INTCMPAD Interrupt for Counter=PWMnCMPA Down [3:3] PWM_1_INTEN_INTCMPBU Interrupt for Counter=PWMnCMPB Up [4:4] PWM_1_INTEN_INTCMPBD Interrupt for Counter=PWMnCMPB Down [5:5] PWM_1_INTEN_TRCNTZERO Trigger for Counter=0 [8:8] PWM_1_INTEN_TRCNTLOAD Trigger for Counter=PWMnLOAD [9:9] PWM_1_INTEN_TRCMPAU Trigger for Counter=PWMnCMPA Up [10:10] PWM_1_INTEN_TRCMPAD Trigger for Counter=PWMnCMPA Down [11:11] PWM_1_INTEN_TRCMPBU Trigger for Counter=PWMnCMPB Up [12:12] PWM_1_INTEN_TRCMPBD Trigger for Counter=PWMnCMPB Down [13:13] _1_RIS PWM1 Raw Interrupt Status 0x00000088 PWM_1_RIS_INTCNTZERO Counter=0 Interrupt Status [0:0] PWM_1_RIS_INTCNTLOAD Counter=Load Interrupt Status [1:1] PWM_1_RIS_INTCMPAU Comparator A Up Interrupt Status [2:2] PWM_1_RIS_INTCMPAD Comparator A Down Interrupt Status [3:3] PWM_1_RIS_INTCMPBU Comparator B Up Interrupt Status [4:4] PWM_1_RIS_INTCMPBD Comparator B Down Interrupt Status [5:5] _1_ISC PWM1 Interrupt Status and Clear 0x0000008C PWM_1_ISC_INTCNTZERO Counter=0 Interrupt [0:0] PWM_1_ISC_INTCNTLOAD Counter=Load Interrupt [1:1] PWM_1_ISC_INTCMPAU Comparator A Up Interrupt [2:2] PWM_1_ISC_INTCMPAD Comparator A Down Interrupt [3:3] PWM_1_ISC_INTCMPBU Comparator B Up Interrupt [4:4] PWM_1_ISC_INTCMPBD Comparator B Down Interrupt [5:5] _1_LOAD PWM1 Load 0x00000090 PWM_1_LOAD_LOAD Counter Load Value [15:0] _1_COUNT PWM1 Counter 0x00000094 PWM_1_COUNT_COUNT Counter Value [15:0] _1_CMPA PWM1 Compare A 0x00000098 PWM_1_CMPA_COMPA Comparator A Value [15:0] _1_CMPB PWM1 Compare B 0x0000009C PWM_1_CMPB_COMPB Comparator B Value [15:0] _1_GENA PWM1 Generator A Control 0x000000A0 PWM_1_GENA_ACTZERO Action for Counter=0 [1:0] PWM_1_GENA_ACTZERO_NONE Do nothing 0x0 PWM_1_GENA_ACTZERO_INV Invert pwmA 0x1 PWM_1_GENA_ACTZERO_ZERO Drive pwmA Low 0x2 PWM_1_GENA_ACTZERO_ONE Drive pwmA High 0x3 PWM_1_GENA_ACTLOAD Action for Counter=LOAD [3:2] PWM_1_GENA_ACTLOAD_NONE Do nothing 0x0 PWM_1_GENA_ACTLOAD_INV Invert pwmA 0x1 PWM_1_GENA_ACTLOAD_ZERO Drive pwmA Low 0x2 PWM_1_GENA_ACTLOAD_ONE Drive pwmA High 0x3 PWM_1_GENA_ACTCMPAU Action for Comparator A Up [5:4] PWM_1_GENA_ACTCMPAU_NONE Do nothing 0x0 PWM_1_GENA_ACTCMPAU_INV Invert pwmA 0x1 PWM_1_GENA_ACTCMPAU_ZERO Drive pwmA Low 0x2 PWM_1_GENA_ACTCMPAU_ONE Drive pwmA High 0x3 PWM_1_GENA_ACTCMPAD Action for Comparator A Down [7:6] PWM_1_GENA_ACTCMPAD_NONE Do nothing 0x0 PWM_1_GENA_ACTCMPAD_INV Invert pwmA 0x1 PWM_1_GENA_ACTCMPAD_ZERO Drive pwmA Low 0x2 PWM_1_GENA_ACTCMPAD_ONE Drive pwmA High 0x3 PWM_1_GENA_ACTCMPBU Action for Comparator B Up [9:8] PWM_1_GENA_ACTCMPBU_NONE Do nothing 0x0 PWM_1_GENA_ACTCMPBU_INV Invert pwmA 0x1 PWM_1_GENA_ACTCMPBU_ZERO Drive pwmA Low 0x2 PWM_1_GENA_ACTCMPBU_ONE Drive pwmA High 0x3 PWM_1_GENA_ACTCMPBD Action for Comparator B Down [11:10] PWM_1_GENA_ACTCMPBD_NONE Do nothing 0x0 PWM_1_GENA_ACTCMPBD_INV Invert pwmA 0x1 PWM_1_GENA_ACTCMPBD_ZERO Drive pwmA Low 0x2 PWM_1_GENA_ACTCMPBD_ONE Drive pwmA High 0x3 _1_GENB PWM1 Generator B Control 0x000000A4 PWM_1_GENB_ACTZERO Action for Counter=0 [1:0] PWM_1_GENB_ACTZERO_NONE Do nothing 0x0 PWM_1_GENB_ACTZERO_INV Invert pwmB 0x1 PWM_1_GENB_ACTZERO_ZERO Drive pwmB Low 0x2 PWM_1_GENB_ACTZERO_ONE Drive pwmB High 0x3 PWM_1_GENB_ACTLOAD Action for Counter=LOAD [3:2] PWM_1_GENB_ACTLOAD_NONE Do nothing 0x0 PWM_1_GENB_ACTLOAD_INV Invert pwmB 0x1 PWM_1_GENB_ACTLOAD_ZERO Drive pwmB Low 0x2 PWM_1_GENB_ACTLOAD_ONE Drive pwmB High 0x3 PWM_1_GENB_ACTCMPAU Action for Comparator A Up [5:4] PWM_1_GENB_ACTCMPAU_NONE Do nothing 0x0 PWM_1_GENB_ACTCMPAU_INV Invert pwmB 0x1 PWM_1_GENB_ACTCMPAU_ZERO Drive pwmB Low 0x2 PWM_1_GENB_ACTCMPAU_ONE Drive pwmB High 0x3 PWM_1_GENB_ACTCMPAD Action for Comparator A Down [7:6] PWM_1_GENB_ACTCMPAD_NONE Do nothing 0x0 PWM_1_GENB_ACTCMPAD_INV Invert pwmB 0x1 PWM_1_GENB_ACTCMPAD_ZERO Drive pwmB Low 0x2 PWM_1_GENB_ACTCMPAD_ONE Drive pwmB High 0x3 PWM_1_GENB_ACTCMPBU Action for Comparator B Up [9:8] PWM_1_GENB_ACTCMPBU_NONE Do nothing 0x0 PWM_1_GENB_ACTCMPBU_INV Invert pwmB 0x1 PWM_1_GENB_ACTCMPBU_ZERO Drive pwmB Low 0x2 PWM_1_GENB_ACTCMPBU_ONE Drive pwmB High 0x3 PWM_1_GENB_ACTCMPBD Action for Comparator B Down [11:10] PWM_1_GENB_ACTCMPBD_NONE Do nothing 0x0 PWM_1_GENB_ACTCMPBD_INV Invert pwmB 0x1 PWM_1_GENB_ACTCMPBD_ZERO Drive pwmB Low 0x2 PWM_1_GENB_ACTCMPBD_ONE Drive pwmB High 0x3 _1_DBCTL PWM1 Dead-Band Control 0x000000A8 PWM_1_DBCTL_ENABLE Dead-Band Generator Enable [0:0] _1_DBRISE PWM1 Dead-Band Rising-Edge Delay 0x000000AC PWM_1_DBRISE_RISEDELAY Dead-Band Rise Delay [11:0] _1_DBFALL PWM1 Dead-Band Falling-Edge-Delay 0x000000B0 PWM_1_DBFALL_FALLDELAY Dead-Band Fall Delay [11:0] _1_FLTSRC0 PWM1 Fault Source 0 0x000000B4 PWM_1_FLTSRC0_FAULT0 Fault0 Input [0:0] PWM_1_FLTSRC0_FAULT1 Fault1 Input [1:1] PWM_1_FLTSRC0_FAULT2 Fault2 Input [2:2] PWM_1_FLTSRC0_FAULT3 Fault3 Input [3:3] _1_FLTSRC1 PWM1 Fault Source 1 0x000000B8 PWM_1_FLTSRC1_DCMP0 Digital Comparator 0 [0:0] PWM_1_FLTSRC1_DCMP1 Digital Comparator 1 [1:1] PWM_1_FLTSRC1_DCMP2 Digital Comparator 2 [2:2] PWM_1_FLTSRC1_DCMP3 Digital Comparator 3 [3:3] PWM_1_FLTSRC1_DCMP4 Digital Comparator 4 [4:4] PWM_1_FLTSRC1_DCMP5 Digital Comparator 5 [5:5] PWM_1_FLTSRC1_DCMP6 Digital Comparator 6 [6:6] PWM_1_FLTSRC1_DCMP7 Digital Comparator 7 [7:7] _1_MINFLTPER PWM1 Minimum Fault Period 0x000000BC PWM_1_MINFLTPER_MFP Minimum Fault Period [15:0] _2_CTL PWM2 Control 0x000000C0 PWM_2_CTL_ENABLE PWM Block Enable [0:0] PWM_2_CTL_MODE Counter Mode [1:1] PWM_2_CTL_DEBUG Debug Mode [2:2] PWM_2_CTL_LOADUPD Load Register Update Mode [3:3] PWM_2_CTL_CMPAUPD Comparator A Update Mode [4:4] PWM_2_CTL_CMPBUPD Comparator B Update Mode [5:5] PWM_2_CTL_GENAUPD PWMnGENA Update Mode [7:6] PWM_2_CTL_GENAUPD_I Immediate 0x0 PWM_2_CTL_GENAUPD_LS Locally Synchronized 0x2 PWM_2_CTL_GENAUPD_GS Globally Synchronized 0x3 PWM_2_CTL_GENBUPD PWMnGENB Update Mode [9:8] PWM_2_CTL_GENBUPD_I Immediate 0x0 PWM_2_CTL_GENBUPD_LS Locally Synchronized 0x2 PWM_2_CTL_GENBUPD_GS Globally Synchronized 0x3 PWM_2_CTL_DBCTLUPD PWMnDBCTL Update Mode [11:10] PWM_2_CTL_DBCTLUPD_I Immediate 0x0 PWM_2_CTL_DBCTLUPD_LS Locally Synchronized 0x2 PWM_2_CTL_DBCTLUPD_GS Globally Synchronized 0x3 PWM_2_CTL_DBRISEUPD PWMnDBRISE Update Mode [13:12] PWM_2_CTL_DBRISEUPD_I Immediate 0x0 PWM_2_CTL_DBRISEUPD_LS Locally Synchronized 0x2 PWM_2_CTL_DBRISEUPD_GS Globally Synchronized 0x3 PWM_2_CTL_DBFALLUPD PWMnDBFALL Update Mode [15:14] PWM_2_CTL_DBFALLUPD_I Immediate 0x0 PWM_2_CTL_DBFALLUPD_LS Locally Synchronized 0x2 PWM_2_CTL_DBFALLUPD_GS Globally Synchronized 0x3 PWM_2_CTL_FLTSRC Fault Condition Source [16:16] PWM_2_CTL_MINFLTPER Minimum Fault Period [17:17] PWM_2_CTL_LATCH Latch Fault Input [18:18] _2_INTEN PWM2 Interrupt and Trigger Enable 0x000000C4 PWM_2_INTEN_INTCNTZERO Interrupt for Counter=0 [0:0] PWM_2_INTEN_INTCNTLOAD Interrupt for Counter=PWMnLOAD [1:1] PWM_2_INTEN_INTCMPAU Interrupt for Counter=PWMnCMPA Up [2:2] PWM_2_INTEN_INTCMPAD Interrupt for Counter=PWMnCMPA Down [3:3] PWM_2_INTEN_INTCMPBU Interrupt for Counter=PWMnCMPB Up [4:4] PWM_2_INTEN_INTCMPBD Interrupt for Counter=PWMnCMPB Down [5:5] PWM_2_INTEN_TRCNTZERO Trigger for Counter=0 [8:8] PWM_2_INTEN_TRCNTLOAD Trigger for Counter=PWMnLOAD [9:9] PWM_2_INTEN_TRCMPAU Trigger for Counter=PWMnCMPA Up [10:10] PWM_2_INTEN_TRCMPAD Trigger for Counter=PWMnCMPA Down [11:11] PWM_2_INTEN_TRCMPBU Trigger for Counter=PWMnCMPB Up [12:12] PWM_2_INTEN_TRCMPBD Trigger for Counter=PWMnCMPB Down [13:13] _2_RIS PWM2 Raw Interrupt Status 0x000000C8 PWM_2_RIS_INTCNTZERO Counter=0 Interrupt Status [0:0] PWM_2_RIS_INTCNTLOAD Counter=Load Interrupt Status [1:1] PWM_2_RIS_INTCMPAU Comparator A Up Interrupt Status [2:2] PWM_2_RIS_INTCMPAD Comparator A Down Interrupt Status [3:3] PWM_2_RIS_INTCMPBU Comparator B Up Interrupt Status [4:4] PWM_2_RIS_INTCMPBD Comparator B Down Interrupt Status [5:5] _2_ISC PWM2 Interrupt Status and Clear 0x000000CC PWM_2_ISC_INTCNTZERO Counter=0 Interrupt [0:0] PWM_2_ISC_INTCNTLOAD Counter=Load Interrupt [1:1] PWM_2_ISC_INTCMPAU Comparator A Up Interrupt [2:2] PWM_2_ISC_INTCMPAD Comparator A Down Interrupt [3:3] PWM_2_ISC_INTCMPBU Comparator B Up Interrupt [4:4] PWM_2_ISC_INTCMPBD Comparator B Down Interrupt [5:5] _2_LOAD PWM2 Load 0x000000D0 PWM_2_LOAD_LOAD Counter Load Value [15:0] _2_COUNT PWM2 Counter 0x000000D4 PWM_2_COUNT_COUNT Counter Value [15:0] _2_CMPA PWM2 Compare A 0x000000D8 PWM_2_CMPA_COMPA Comparator A Value [15:0] _2_CMPB PWM2 Compare B 0x000000DC PWM_2_CMPB_COMPB Comparator B Value [15:0] _2_GENA PWM2 Generator A Control 0x000000E0 PWM_2_GENA_ACTZERO Action for Counter=0 [1:0] PWM_2_GENA_ACTZERO_NONE Do nothing 0x0 PWM_2_GENA_ACTZERO_INV Invert pwmA 0x1 PWM_2_GENA_ACTZERO_ZERO Drive pwmA Low 0x2 PWM_2_GENA_ACTZERO_ONE Drive pwmA High 0x3 PWM_2_GENA_ACTLOAD Action for Counter=LOAD [3:2] PWM_2_GENA_ACTLOAD_NONE Do nothing 0x0 PWM_2_GENA_ACTLOAD_INV Invert pwmA 0x1 PWM_2_GENA_ACTLOAD_ZERO Drive pwmA Low 0x2 PWM_2_GENA_ACTLOAD_ONE Drive pwmA High 0x3 PWM_2_GENA_ACTCMPAU Action for Comparator A Up [5:4] PWM_2_GENA_ACTCMPAU_NONE Do nothing 0x0 PWM_2_GENA_ACTCMPAU_INV Invert pwmA 0x1 PWM_2_GENA_ACTCMPAU_ZERO Drive pwmA Low 0x2 PWM_2_GENA_ACTCMPAU_ONE Drive pwmA High 0x3 PWM_2_GENA_ACTCMPAD Action for Comparator A Down [7:6] PWM_2_GENA_ACTCMPAD_NONE Do nothing 0x0 PWM_2_GENA_ACTCMPAD_INV Invert pwmA 0x1 PWM_2_GENA_ACTCMPAD_ZERO Drive pwmA Low 0x2 PWM_2_GENA_ACTCMPAD_ONE Drive pwmA High 0x3 PWM_2_GENA_ACTCMPBU Action for Comparator B Up [9:8] PWM_2_GENA_ACTCMPBU_NONE Do nothing 0x0 PWM_2_GENA_ACTCMPBU_INV Invert pwmA 0x1 PWM_2_GENA_ACTCMPBU_ZERO Drive pwmA Low 0x2 PWM_2_GENA_ACTCMPBU_ONE Drive pwmA High 0x3 PWM_2_GENA_ACTCMPBD Action for Comparator B Down [11:10] PWM_2_GENA_ACTCMPBD_NONE Do nothing 0x0 PWM_2_GENA_ACTCMPBD_INV Invert pwmA 0x1 PWM_2_GENA_ACTCMPBD_ZERO Drive pwmA Low 0x2 PWM_2_GENA_ACTCMPBD_ONE Drive pwmA High 0x3 _2_GENB PWM2 Generator B Control 0x000000E4 PWM_2_GENB_ACTZERO Action for Counter=0 [1:0] PWM_2_GENB_ACTZERO_NONE Do nothing 0x0 PWM_2_GENB_ACTZERO_INV Invert pwmB 0x1 PWM_2_GENB_ACTZERO_ZERO Drive pwmB Low 0x2 PWM_2_GENB_ACTZERO_ONE Drive pwmB High 0x3 PWM_2_GENB_ACTLOAD Action for Counter=LOAD [3:2] PWM_2_GENB_ACTLOAD_NONE Do nothing 0x0 PWM_2_GENB_ACTLOAD_INV Invert pwmB 0x1 PWM_2_GENB_ACTLOAD_ZERO Drive pwmB Low 0x2 PWM_2_GENB_ACTLOAD_ONE Drive pwmB High 0x3 PWM_2_GENB_ACTCMPAU Action for Comparator A Up [5:4] PWM_2_GENB_ACTCMPAU_NONE Do nothing 0x0 PWM_2_GENB_ACTCMPAU_INV Invert pwmB 0x1 PWM_2_GENB_ACTCMPAU_ZERO Drive pwmB Low 0x2 PWM_2_GENB_ACTCMPAU_ONE Drive pwmB High 0x3 PWM_2_GENB_ACTCMPAD Action for Comparator A Down [7:6] PWM_2_GENB_ACTCMPAD_NONE Do nothing 0x0 PWM_2_GENB_ACTCMPAD_INV Invert pwmB 0x1 PWM_2_GENB_ACTCMPAD_ZERO Drive pwmB Low 0x2 PWM_2_GENB_ACTCMPAD_ONE Drive pwmB High 0x3 PWM_2_GENB_ACTCMPBU Action for Comparator B Up [9:8] PWM_2_GENB_ACTCMPBU_NONE Do nothing 0x0 PWM_2_GENB_ACTCMPBU_INV Invert pwmB 0x1 PWM_2_GENB_ACTCMPBU_ZERO Drive pwmB Low 0x2 PWM_2_GENB_ACTCMPBU_ONE Drive pwmB High 0x3 PWM_2_GENB_ACTCMPBD Action for Comparator B Down [11:10] PWM_2_GENB_ACTCMPBD_NONE Do nothing 0x0 PWM_2_GENB_ACTCMPBD_INV Invert pwmB 0x1 PWM_2_GENB_ACTCMPBD_ZERO Drive pwmB Low 0x2 PWM_2_GENB_ACTCMPBD_ONE Drive pwmB High 0x3 _2_DBCTL PWM2 Dead-Band Control 0x000000E8 PWM_2_DBCTL_ENABLE Dead-Band Generator Enable [0:0] _2_DBRISE PWM2 Dead-Band Rising-Edge Delay 0x000000EC PWM_2_DBRISE_RISEDELAY Dead-Band Rise Delay [11:0] _2_DBFALL PWM2 Dead-Band Falling-Edge-Delay 0x000000F0 PWM_2_DBFALL_FALLDELAY Dead-Band Fall Delay [11:0] _2_FLTSRC0 PWM2 Fault Source 0 0x000000F4 PWM_2_FLTSRC0_FAULT0 Fault0 Input [0:0] PWM_2_FLTSRC0_FAULT1 Fault1 Input [1:1] PWM_2_FLTSRC0_FAULT2 Fault2 Input [2:2] PWM_2_FLTSRC0_FAULT3 Fault3 Input [3:3] _2_FLTSRC1 PWM2 Fault Source 1 0x000000F8 PWM_2_FLTSRC1_DCMP0 Digital Comparator 0 [0:0] PWM_2_FLTSRC1_DCMP1 Digital Comparator 1 [1:1] PWM_2_FLTSRC1_DCMP2 Digital Comparator 2 [2:2] PWM_2_FLTSRC1_DCMP3 Digital Comparator 3 [3:3] PWM_2_FLTSRC1_DCMP4 Digital Comparator 4 [4:4] PWM_2_FLTSRC1_DCMP5 Digital Comparator 5 [5:5] PWM_2_FLTSRC1_DCMP6 Digital Comparator 6 [6:6] PWM_2_FLTSRC1_DCMP7 Digital Comparator 7 [7:7] _2_MINFLTPER PWM2 Minimum Fault Period 0x000000FC PWM_2_MINFLTPER_MFP Minimum Fault Period [15:0] _3_CTL PWM3 Control 0x00000100 PWM_3_CTL_ENABLE PWM Block Enable [0:0] PWM_3_CTL_MODE Counter Mode [1:1] PWM_3_CTL_DEBUG Debug Mode [2:2] PWM_3_CTL_LOADUPD Load Register Update Mode [3:3] PWM_3_CTL_CMPAUPD Comparator A Update Mode [4:4] PWM_3_CTL_CMPBUPD Comparator B Update Mode [5:5] PWM_3_CTL_GENAUPD PWMnGENA Update Mode [7:6] PWM_3_CTL_GENAUPD_I Immediate 0x0 PWM_3_CTL_GENAUPD_LS Locally Synchronized 0x2 PWM_3_CTL_GENAUPD_GS Globally Synchronized 0x3 PWM_3_CTL_GENBUPD PWMnGENB Update Mode [9:8] PWM_3_CTL_GENBUPD_I Immediate 0x0 PWM_3_CTL_GENBUPD_LS Locally Synchronized 0x2 PWM_3_CTL_GENBUPD_GS Globally Synchronized 0x3 PWM_3_CTL_DBCTLUPD PWMnDBCTL Update Mode [11:10] PWM_3_CTL_DBCTLUPD_I Immediate 0x0 PWM_3_CTL_DBCTLUPD_LS Locally Synchronized 0x2 PWM_3_CTL_DBCTLUPD_GS Globally Synchronized 0x3 PWM_3_CTL_DBRISEUPD PWMnDBRISE Update Mode [13:12] PWM_3_CTL_DBRISEUPD_I Immediate 0x0 PWM_3_CTL_DBRISEUPD_LS Locally Synchronized 0x2 PWM_3_CTL_DBRISEUPD_GS Globally Synchronized 0x3 PWM_3_CTL_DBFALLUPD PWMnDBFALL Update Mode [15:14] PWM_3_CTL_DBFALLUPD_I Immediate 0x0 PWM_3_CTL_DBFALLUPD_LS Locally Synchronized 0x2 PWM_3_CTL_DBFALLUPD_GS Globally Synchronized 0x3 PWM_3_CTL_FLTSRC Fault Condition Source [16:16] PWM_3_CTL_MINFLTPER Minimum Fault Period [17:17] PWM_3_CTL_LATCH Latch Fault Input [18:18] _3_INTEN PWM3 Interrupt and Trigger Enable 0x00000104 PWM_3_INTEN_INTCNTZERO Interrupt for Counter=0 [0:0] PWM_3_INTEN_INTCNTLOAD Interrupt for Counter=PWMnLOAD [1:1] PWM_3_INTEN_INTCMPAU Interrupt for Counter=PWMnCMPA Up [2:2] PWM_3_INTEN_INTCMPAD Interrupt for Counter=PWMnCMPA Down [3:3] PWM_3_INTEN_INTCMPBU Interrupt for Counter=PWMnCMPB Up [4:4] PWM_3_INTEN_INTCMPBD Interrupt for Counter=PWMnCMPB Down [5:5] PWM_3_INTEN_TRCNTZERO Trigger for Counter=0 [8:8] PWM_3_INTEN_TRCNTLOAD Trigger for Counter=PWMnLOAD [9:9] PWM_3_INTEN_TRCMPAU Trigger for Counter=PWMnCMPA Up [10:10] PWM_3_INTEN_TRCMPAD Trigger for Counter=PWMnCMPA Down [11:11] PWM_3_INTEN_TRCMPBU Trigger for Counter=PWMnCMPB Up [12:12] PWM_3_INTEN_TRCMPBD Trigger for Counter=PWMnCMPB Down [13:13] _3_RIS PWM3 Raw Interrupt Status 0x00000108 PWM_3_RIS_INTCNTZERO Counter=0 Interrupt Status [0:0] PWM_3_RIS_INTCNTLOAD Counter=Load Interrupt Status [1:1] PWM_3_RIS_INTCMPAU Comparator A Up Interrupt Status [2:2] PWM_3_RIS_INTCMPAD Comparator A Down Interrupt Status [3:3] PWM_3_RIS_INTCMPBU Comparator B Up Interrupt Status [4:4] PWM_3_RIS_INTCMPBD Comparator B Down Interrupt Status [5:5] _3_ISC PWM3 Interrupt Status and Clear 0x0000010C PWM_3_ISC_INTCNTZERO Counter=0 Interrupt [0:0] PWM_3_ISC_INTCNTLOAD Counter=Load Interrupt [1:1] PWM_3_ISC_INTCMPAU Comparator A Up Interrupt [2:2] PWM_3_ISC_INTCMPAD Comparator A Down Interrupt [3:3] PWM_3_ISC_INTCMPBU Comparator B Up Interrupt [4:4] PWM_3_ISC_INTCMPBD Comparator B Down Interrupt [5:5] _3_LOAD PWM3 Load 0x00000110 PWM_3_LOAD_LOAD Counter Load Value [15:0] _3_COUNT PWM3 Counter 0x00000114 PWM_3_COUNT_COUNT Counter Value [15:0] _3_CMPA PWM3 Compare A 0x00000118 PWM_3_CMPA_COMPA Comparator A Value [15:0] _3_CMPB PWM3 Compare B 0x0000011C PWM_3_CMPB_COMPB Comparator B Value [15:0] _3_GENA PWM3 Generator A Control 0x00000120 PWM_3_GENA_ACTZERO Action for Counter=0 [1:0] PWM_3_GENA_ACTZERO_NONE Do nothing 0x0 PWM_3_GENA_ACTZERO_INV Invert pwmA 0x1 PWM_3_GENA_ACTZERO_ZERO Drive pwmA Low 0x2 PWM_3_GENA_ACTZERO_ONE Drive pwmA High 0x3 PWM_3_GENA_ACTLOAD Action for Counter=LOAD [3:2] PWM_3_GENA_ACTLOAD_NONE Do nothing 0x0 PWM_3_GENA_ACTLOAD_INV Invert pwmA 0x1 PWM_3_GENA_ACTLOAD_ZERO Drive pwmA Low 0x2 PWM_3_GENA_ACTLOAD_ONE Drive pwmA High 0x3 PWM_3_GENA_ACTCMPAU Action for Comparator A Up [5:4] PWM_3_GENA_ACTCMPAU_NONE Do nothing 0x0 PWM_3_GENA_ACTCMPAU_INV Invert pwmA 0x1 PWM_3_GENA_ACTCMPAU_ZERO Drive pwmA Low 0x2 PWM_3_GENA_ACTCMPAU_ONE Drive pwmA High 0x3 PWM_3_GENA_ACTCMPAD Action for Comparator A Down [7:6] PWM_3_GENA_ACTCMPAD_NONE Do nothing 0x0 PWM_3_GENA_ACTCMPAD_INV Invert pwmA 0x1 PWM_3_GENA_ACTCMPAD_ZERO Drive pwmA Low 0x2 PWM_3_GENA_ACTCMPAD_ONE Drive pwmA High 0x3 PWM_3_GENA_ACTCMPBU Action for Comparator B Up [9:8] PWM_3_GENA_ACTCMPBU_NONE Do nothing 0x0 PWM_3_GENA_ACTCMPBU_INV Invert pwmA 0x1 PWM_3_GENA_ACTCMPBU_ZERO Drive pwmA Low 0x2 PWM_3_GENA_ACTCMPBU_ONE Drive pwmA High 0x3 PWM_3_GENA_ACTCMPBD Action for Comparator B Down [11:10] PWM_3_GENA_ACTCMPBD_NONE Do nothing 0x0 PWM_3_GENA_ACTCMPBD_INV Invert pwmA 0x1 PWM_3_GENA_ACTCMPBD_ZERO Drive pwmA Low 0x2 PWM_3_GENA_ACTCMPBD_ONE Drive pwmA High 0x3 _3_GENB PWM3 Generator B Control 0x00000124 PWM_3_GENB_ACTZERO Action for Counter=0 [1:0] PWM_3_GENB_ACTZERO_NONE Do nothing 0x0 PWM_3_GENB_ACTZERO_INV Invert pwmB 0x1 PWM_3_GENB_ACTZERO_ZERO Drive pwmB Low 0x2 PWM_3_GENB_ACTZERO_ONE Drive pwmB High 0x3 PWM_3_GENB_ACTLOAD Action for Counter=LOAD [3:2] PWM_3_GENB_ACTLOAD_NONE Do nothing 0x0 PWM_3_GENB_ACTLOAD_INV Invert pwmB 0x1 PWM_3_GENB_ACTLOAD_ZERO Drive pwmB Low 0x2 PWM_3_GENB_ACTLOAD_ONE Drive pwmB High 0x3 PWM_3_GENB_ACTCMPAU Action for Comparator A Up [5:4] PWM_3_GENB_ACTCMPAU_NONE Do nothing 0x0 PWM_3_GENB_ACTCMPAU_INV Invert pwmB 0x1 PWM_3_GENB_ACTCMPAU_ZERO Drive pwmB Low 0x2 PWM_3_GENB_ACTCMPAU_ONE Drive pwmB High 0x3 PWM_3_GENB_ACTCMPAD Action for Comparator A Down [7:6] PWM_3_GENB_ACTCMPAD_NONE Do nothing 0x0 PWM_3_GENB_ACTCMPAD_INV Invert pwmB 0x1 PWM_3_GENB_ACTCMPAD_ZERO Drive pwmB Low 0x2 PWM_3_GENB_ACTCMPAD_ONE Drive pwmB High 0x3 PWM_3_GENB_ACTCMPBU Action for Comparator B Up [9:8] PWM_3_GENB_ACTCMPBU_NONE Do nothing 0x0 PWM_3_GENB_ACTCMPBU_INV Invert pwmB 0x1 PWM_3_GENB_ACTCMPBU_ZERO Drive pwmB Low 0x2 PWM_3_GENB_ACTCMPBU_ONE Drive pwmB High 0x3 PWM_3_GENB_ACTCMPBD Action for Comparator B Down [11:10] PWM_3_GENB_ACTCMPBD_NONE Do nothing 0x0 PWM_3_GENB_ACTCMPBD_INV Invert pwmB 0x1 PWM_3_GENB_ACTCMPBD_ZERO Drive pwmB Low 0x2 PWM_3_GENB_ACTCMPBD_ONE Drive pwmB High 0x3 _3_DBCTL PWM3 Dead-Band Control 0x00000128 PWM_3_DBCTL_ENABLE Dead-Band Generator Enable [0:0] _3_DBRISE PWM3 Dead-Band Rising-Edge Delay 0x0000012C PWM_3_DBRISE_RISEDELAY Dead-Band Rise Delay [11:0] _3_DBFALL PWM3 Dead-Band Falling-Edge-Delay 0x00000130 PWM_3_DBFALL_FALLDELAY Dead-Band Fall Delay [11:0] _3_FLTSRC0 PWM3 Fault Source 0 0x00000134 PWM_3_FLTSRC0_FAULT0 Fault0 Input [0:0] PWM_3_FLTSRC0_FAULT1 Fault1 Input [1:1] PWM_3_FLTSRC0_FAULT2 Fault2 Input [2:2] PWM_3_FLTSRC0_FAULT3 Fault3 Input [3:3] _3_FLTSRC1 PWM3 Fault Source 1 0x00000138 PWM_3_FLTSRC1_DCMP0 Digital Comparator 0 [0:0] PWM_3_FLTSRC1_DCMP1 Digital Comparator 1 [1:1] PWM_3_FLTSRC1_DCMP2 Digital Comparator 2 [2:2] PWM_3_FLTSRC1_DCMP3 Digital Comparator 3 [3:3] PWM_3_FLTSRC1_DCMP4 Digital Comparator 4 [4:4] PWM_3_FLTSRC1_DCMP5 Digital Comparator 5 [5:5] PWM_3_FLTSRC1_DCMP6 Digital Comparator 6 [6:6] PWM_3_FLTSRC1_DCMP7 Digital Comparator 7 [7:7] _3_MINFLTPER PWM3 Minimum Fault Period 0x0000013C PWM_3_MINFLTPER_MFP Minimum Fault Period [15:0] _0_FLTSEN PWM0 Fault Pin Logic Sense 0x00000800 PWM_0_FLTSEN_FAULT0 Fault0 Sense [0:0] PWM_0_FLTSEN_FAULT1 Fault1 Sense [1:1] PWM_0_FLTSEN_FAULT2 Fault2 Sense [2:2] PWM_0_FLTSEN_FAULT3 Fault3 Sense [3:3] _0_FLTSTAT0 PWM0 Fault Status 0 0x00000804 read-only PWM_0_FLTSTAT0_FAULT0 Fault Input 0 [0:0] read-only PWM_0_FLTSTAT0_FAULT1 Fault Input 1 [1:1] read-only PWM_0_FLTSTAT0_FAULT2 Fault Input 2 [2:2] read-only PWM_0_FLTSTAT0_FAULT3 Fault Input 3 [3:3] read-only _0_FLTSTAT1 PWM0 Fault Status 1 0x00000808 read-only PWM_0_FLTSTAT1_DCMP0 Digital Comparator 0 Trigger [0:0] read-only PWM_0_FLTSTAT1_DCMP1 Digital Comparator 1 Trigger [1:1] read-only PWM_0_FLTSTAT1_DCMP2 Digital Comparator 2 Trigger [2:2] read-only PWM_0_FLTSTAT1_DCMP3 Digital Comparator 3 Trigger [3:3] read-only PWM_0_FLTSTAT1_DCMP4 Digital Comparator 4 Trigger [4:4] read-only PWM_0_FLTSTAT1_DCMP5 Digital Comparator 5 Trigger [5:5] read-only PWM_0_FLTSTAT1_DCMP6 Digital Comparator 6 Trigger [6:6] read-only PWM_0_FLTSTAT1_DCMP7 Digital Comparator 7 Trigger [7:7] read-only _1_FLTSEN PWM1 Fault Pin Logic Sense 0x00000880 PWM_1_FLTSEN_FAULT0 Fault0 Sense [0:0] PWM_1_FLTSEN_FAULT1 Fault1 Sense [1:1] PWM_1_FLTSEN_FAULT2 Fault2 Sense [2:2] PWM_1_FLTSEN_FAULT3 Fault3 Sense [3:3] _1_FLTSTAT0 PWM1 Fault Status 0 0x00000884 read-only PWM_1_FLTSTAT0_FAULT0 Fault Input 0 [0:0] read-only PWM_1_FLTSTAT0_FAULT1 Fault Input 1 [1:1] read-only PWM_1_FLTSTAT0_FAULT2 Fault Input 2 [2:2] read-only PWM_1_FLTSTAT0_FAULT3 Fault Input 3 [3:3] read-only _1_FLTSTAT1 PWM1 Fault Status 1 0x00000888 read-only PWM_1_FLTSTAT1_DCMP0 Digital Comparator 0 Trigger [0:0] read-only PWM_1_FLTSTAT1_DCMP1 Digital Comparator 1 Trigger [1:1] read-only PWM_1_FLTSTAT1_DCMP2 Digital Comparator 2 Trigger [2:2] read-only PWM_1_FLTSTAT1_DCMP3 Digital Comparator 3 Trigger [3:3] read-only PWM_1_FLTSTAT1_DCMP4 Digital Comparator 4 Trigger [4:4] read-only PWM_1_FLTSTAT1_DCMP5 Digital Comparator 5 Trigger [5:5] read-only PWM_1_FLTSTAT1_DCMP6 Digital Comparator 6 Trigger [6:6] read-only PWM_1_FLTSTAT1_DCMP7 Digital Comparator 7 Trigger [7:7] read-only _2_FLTSEN PWM2 Fault Pin Logic Sense 0x00000900 PWM_2_FLTSEN_FAULT0 Fault0 Sense [0:0] PWM_2_FLTSEN_FAULT1 Fault1 Sense [1:1] PWM_2_FLTSEN_FAULT2 Fault2 Sense [2:2] PWM_2_FLTSEN_FAULT3 Fault3 Sense [3:3] _2_FLTSTAT0 PWM2 Fault Status 0 0x00000904 read-only PWM_2_FLTSTAT0_FAULT0 Fault Input 0 [0:0] read-only PWM_2_FLTSTAT0_FAULT1 Fault Input 1 [1:1] read-only PWM_2_FLTSTAT0_FAULT2 Fault Input 2 [2:2] read-only PWM_2_FLTSTAT0_FAULT3 Fault Input 3 [3:3] read-only _2_FLTSTAT1 PWM2 Fault Status 1 0x00000908 read-only PWM_2_FLTSTAT1_DCMP0 Digital Comparator 0 Trigger [0:0] read-only PWM_2_FLTSTAT1_DCMP1 Digital Comparator 1 Trigger [1:1] read-only PWM_2_FLTSTAT1_DCMP2 Digital Comparator 2 Trigger [2:2] read-only PWM_2_FLTSTAT1_DCMP3 Digital Comparator 3 Trigger [3:3] read-only PWM_2_FLTSTAT1_DCMP4 Digital Comparator 4 Trigger [4:4] read-only PWM_2_FLTSTAT1_DCMP5 Digital Comparator 5 Trigger [5:5] read-only PWM_2_FLTSTAT1_DCMP6 Digital Comparator 6 Trigger [6:6] read-only PWM_2_FLTSTAT1_DCMP7 Digital Comparator 7 Trigger [7:7] read-only _3_FLTSEN PWM3 Fault Pin Logic Sense 0x00000980 PWM_3_FLTSEN_FAULT0 Fault0 Sense [0:0] PWM_3_FLTSEN_FAULT1 Fault1 Sense [1:1] PWM_3_FLTSEN_FAULT2 Fault2 Sense [2:2] PWM_3_FLTSEN_FAULT3 Fault3 Sense [3:3] _3_FLTSTAT0 PWM3 Fault Status 0 0x00000984 read-only PWM_3_FLTSTAT0_FAULT0 Fault Input 0 [0:0] read-only PWM_3_FLTSTAT0_FAULT1 Fault Input 1 [1:1] read-only PWM_3_FLTSTAT0_FAULT2 Fault Input 2 [2:2] read-only PWM_3_FLTSTAT0_FAULT3 Fault Input 3 [3:3] read-only _3_FLTSTAT1 PWM3 Fault Status 1 0x00000988 read-only PWM_3_FLTSTAT1_DCMP0 Digital Comparator 0 Trigger [0:0] read-only PWM_3_FLTSTAT1_DCMP1 Digital Comparator 1 Trigger [1:1] read-only PWM_3_FLTSTAT1_DCMP2 Digital Comparator 2 Trigger [2:2] read-only PWM_3_FLTSTAT1_DCMP3 Digital Comparator 3 Trigger [3:3] read-only PWM_3_FLTSTAT1_DCMP4 Digital Comparator 4 Trigger [4:4] read-only PWM_3_FLTSTAT1_DCMP5 Digital Comparator 5 Trigger [5:5] read-only PWM_3_FLTSTAT1_DCMP6 Digital Comparator 6 Trigger [6:6] read-only PWM_3_FLTSTAT1_DCMP7 Digital Comparator 7 Trigger [7:7] read-only PP PWM Peripheral Properties 0x00000FC0 PWM_PP_GCNT Generators [3:0] PWM_PP_FCNT Fault Inputs (per PWM unit) [7:4] PWM_PP_ESYNC Extended Synchronization [8:8] PWM_PP_EFAULT Extended Fault [9:9] PWM_PP_ONE One-Shot Mode [10:10] CC PWM Clock Configuration 0x00000FC8 PWM_CC_PWMDIV PWM Clock Divider [2:0] PWM_CC_PWMDIV_2 /2 0x0 PWM_CC_PWMDIV_4 /4 0x1 PWM_CC_PWMDIV_8 /8 0x2 PWM_CC_PWMDIV_16 /16 0x3 PWM_CC_PWMDIV_32 /32 0x4 PWM_CC_PWMDIV_64 /64 0x5 PWM_CC_USEPWM Use PWM Clock Divisor [8:8] QEI0 Register map for QEI0 peripheral QEI QEI0 0x4002C000 0 0x00001000 registers QEI013 CTL QEI Control 0x00000000 QEI_CTL_ENABLE Enable QEI [0:0] QEI_CTL_SWAP Swap Signals [1:1] QEI_CTL_SIGMODE Signal Mode [2:2] QEI_CTL_CAPMODE Capture Mode [3:3] QEI_CTL_RESMODE Reset Mode [4:4] QEI_CTL_VELEN Capture Velocity [5:5] QEI_CTL_VELDIV Predivide Velocity [8:6] QEI_CTL_VELDIV_1 QEI clock /1 0x0 QEI_CTL_VELDIV_2 QEI clock /2 0x1 QEI_CTL_VELDIV_4 QEI clock /4 0x2 QEI_CTL_VELDIV_8 QEI clock /8 0x3 QEI_CTL_VELDIV_16 QEI clock /16 0x4 QEI_CTL_VELDIV_32 QEI clock /32 0x5 QEI_CTL_VELDIV_64 QEI clock /64 0x6 QEI_CTL_VELDIV_128 QEI clock /128 0x7 QEI_CTL_INVA Invert PhA [9:9] QEI_CTL_INVB Invert PhB [10:10] QEI_CTL_INVI Invert Index Pulse [11:11] QEI_CTL_STALLEN Stall QEI [12:12] QEI_CTL_FILTEN Enable Input Filter [13:13] QEI_CTL_FILTCNT Input Filter Prescale Count [19:16] STAT QEI Status 0x00000004 QEI_STAT_ERROR Error Detected [0:0] QEI_STAT_DIRECTION Direction of Rotation [1:1] POS QEI Position 0x00000008 QEI_POS Current Position Integrator Value [31:0] MAXPOS QEI Maximum Position 0x0000000C QEI_MAXPOS Maximum Position Integrator Value [31:0] LOAD QEI Timer Load 0x00000010 QEI_LOAD Velocity Timer Load Value [31:0] TIME QEI Timer 0x00000014 QEI_TIME Velocity Timer Current Value [31:0] COUNT QEI Velocity Counter 0x00000018 QEI_COUNT Velocity Pulse Count [31:0] SPEED QEI Velocity 0x0000001C QEI_SPEED Velocity [31:0] INTEN QEI Interrupt Enable 0x00000020 QEI_INTEN_INDEX Index Pulse Detected Interrupt Enable [0:0] QEI_INTEN_TIMER Timer Expires Interrupt Enable [1:1] QEI_INTEN_DIR Direction Change Interrupt Enable [2:2] QEI_INTEN_ERROR Phase Error Interrupt Enable [3:3] RIS QEI Raw Interrupt Status 0x00000024 QEI_RIS_INDEX Index Pulse Asserted [0:0] QEI_RIS_TIMER Velocity Timer Expired [1:1] QEI_RIS_DIR Direction Change Detected [2:2] QEI_RIS_ERROR Phase Error Detected [3:3] ISC QEI Interrupt Status and Clear 0x00000028 QEI_ISC_INDEX Index Pulse Interrupt [0:0] QEI_ISC_TIMER Velocity Timer Expired Interrupt [1:1] QEI_ISC_DIR Direction Change Interrupt [2:2] QEI_ISC_ERROR Phase Error Interrupt [3:3] TIMER0 Register map for TIMER0 peripheral TIMER TIMER0 0x40030000 0 0x00001000 registers TIMER0A19 TIMER0B20 CFG GPTM Configuration 0x00000000 TIMER_CFG GPTM Configuration [2:0] TIMER_CFG_32_BIT_TIMER For a 16/32-bit timer, this value selects the 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT For a 16/32-bit timer, this value selects the 16-bit timer configuration 0x4 TAMR GPTM Timer A Mode 0x00000004 TIMER_TAMR_TAMR GPTM Timer A Mode [1:0] TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TACMR GPTM Timer A Capture Mode [2:2] TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select [3:3] TIMER_TAMR_TACDIR GPTM Timer A Count Direction [4:4] TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable [5:5] TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger [6:6] TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode [7:7] TIMER_TAMR_TAILD GPTM Timer A Interval Load Write [8:8] TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable [9:9] TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update [10:10] TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation [11:11] TIMER_TAMR_TACINTD One-shot/Periodic Interrupt Disable [12:12] TIMER_TAMR_TCACT Timer Compare Action Select [15:13] TIMER_TAMR_TCACT_NONE Disable compare operations 0x0 TIMER_TAMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TAMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TAMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TAMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TAMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TAMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TAMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TBMR GPTM Timer B Mode 0x00000008 TIMER_TBMR_TBMR GPTM Timer B Mode [1:0] TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode [2:2] TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select [3:3] TIMER_TBMR_TBCDIR GPTM Timer B Count Direction [4:4] TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable [5:5] TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger [6:6] TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode [7:7] TIMER_TBMR_TBILD GPTM Timer B Interval Load Write [8:8] TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable [9:9] TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update [10:10] TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation [11:11] TIMER_TBMR_TBCINTD One-Shot/Periodic Interrupt Disable [12:12] TIMER_TBMR_TCACT Timer Compare Action Select [15:13] TIMER_TBMR_TCACT_NONE Disable compare operations 0x0 TIMER_TBMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TBMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TBMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TBMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TBMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TBMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TBMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 CTL GPTM Control 0x0000000C TIMER_CTL_TAEN GPTM Timer A Enable [0:0] TIMER_CTL_TASTALL GPTM Timer A Stall Enable [1:1] TIMER_CTL_TAEVENT GPTM Timer A Event Mode [3:2] TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_RTCEN GPTM RTC Stall Enable [4:4] TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable [5:5] TIMER_CTL_TAPWML GPTM Timer A PWM Output Level [6:6] TIMER_CTL_TBEN GPTM Timer B Enable [8:8] TIMER_CTL_TBSTALL GPTM Timer B Stall Enable [9:9] TIMER_CTL_TBEVENT GPTM Timer B Event Mode [11:10] TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable [13:13] TIMER_CTL_TBPWML GPTM Timer B PWM Output Level [14:14] SYNC GPTM Synchronize 0x00000010 TIMER_SYNC_SYNCT0 Synchronize GPTM Timer 0 [1:0] TIMER_SYNC_SYNCT0_NONE GPTM0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM Timer 1 [3:2] TIMER_SYNC_SYNCT1_NONE GPTM1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM Timer 2 [5:4] TIMER_SYNC_SYNCT2_NONE GPTM2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM Timer 3 [7:6] TIMER_SYNC_SYNCT3_NONE GPTM3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM Timer 4 [9:8] TIMER_SYNC_SYNCT4_NONE GPTM4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM Timer 5 [11:10] TIMER_SYNC_SYNCT5_NONE GPTM5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM5 is triggered 0x3 TIMER_SYNC_SYNCT6 Synchronize GPTM Timer 6 [13:12] TIMER_SYNC_SYNCT6_NONE GPTM6 is not affected 0x0 TIMER_SYNC_SYNCT6_TA A timeout event for Timer A of GPTM6 is triggered 0x1 TIMER_SYNC_SYNCT6_TB A timeout event for Timer B of GPTM6 is triggered 0x2 TIMER_SYNC_SYNCT6_TATB A timeout event for both Timer A and Timer B of GPTM6 is triggered 0x3 TIMER_SYNC_SYNCT7 Synchronize GPTM Timer 7 [15:14] TIMER_SYNC_SYNCT7_NONE GPT7 is not affected 0x0 TIMER_SYNC_SYNCT7_TA A timeout event for Timer A of GPTM7 is triggered 0x1 TIMER_SYNC_SYNCT7_TB A timeout event for Timer B of GPTM7 is triggered 0x2 TIMER_SYNC_SYNCT7_TATB A timeout event for both Timer A and Timer B of GPTM7 is triggered 0x3 IMR GPTM Interrupt Mask 0x00000018 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask [0:0] TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask [1:1] TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask [2:2] TIMER_IMR_RTCIM GPTM RTC Interrupt Mask [3:3] TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask [4:4] TIMER_IMR_DMAAIM GPTM Timer A DMA Done Interrupt Mask [5:5] TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask [8:8] TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask [9:9] TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask [10:10] TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask [11:11] TIMER_IMR_DMABIM GPTM Timer B DMA Done Interrupt Mask [13:13] RIS GPTM Raw Interrupt Status 0x0000001C TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt [0:0] TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt [1:1] TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt [2:2] TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt [3:3] TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt [4:4] TIMER_RIS_DMAARIS GPTM Timer A DMA Done Raw Interrupt Status [5:5] TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt [8:8] TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt [9:9] TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt [10:10] TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt [11:11] TIMER_RIS_DMABRIS GPTM Timer B DMA Done Raw Interrupt Status [13:13] MIS GPTM Masked Interrupt Status 0x00000020 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt [0:0] TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt [1:1] TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt [2:2] TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt [3:3] TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt [4:4] TIMER_MIS_DMAAMIS GPTM Timer A DMA Done Masked Interrupt [5:5] TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt [8:8] TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt [9:9] TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt [10:10] TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt [11:11] TIMER_MIS_DMABMIS GPTM Timer B DMA Done Masked Interrupt [13:13] ICR GPTM Interrupt Clear 0x00000024 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt [0:0] write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear [1:1] write-only TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear [2:2] write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear [3:3] write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear [4:4] write-only TIMER_ICR_DMAAINT GPTM Timer A DMA Done Interrupt Clear [5:5] write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear [8:8] write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear [9:9] write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear [10:10] write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear [11:11] write-only TIMER_ICR_DMABINT GPTM Timer B DMA Done Interrupt Clear [13:13] write-only TAILR GPTM Timer A Interval Load 0x00000028 TBILR GPTM Timer B Interval Load 0x0000002C TAMATCHR GPTM Timer A Match 0x00000030 TBMATCHR GPTM Timer B Match 0x00000034 TAPR GPTM Timer A Prescale 0x00000038 TIMER_TAPR_TAPSR GPTM Timer A Prescale [7:0] TBPR GPTM Timer B Prescale 0x0000003C TIMER_TBPR_TBPSR GPTM Timer B Prescale [7:0] TAPMR GPTM TimerA Prescale Match 0x00000040 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match [7:0] TBPMR GPTM TimerB Prescale Match 0x00000044 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match [7:0] TAR GPTM Timer A 0x00000048 TBR GPTM Timer B 0x0000004C TAV GPTM Timer A Value 0x00000050 TBV GPTM Timer B Value 0x00000054 RTCPD GPTM RTC Predivide 0x00000058 TIMER_RTCPD_RTCPD RTC Predivide Counter Value [15:0] TAPS GPTM Timer A Prescale Snapshot 0x0000005C TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot [15:0] TBPS GPTM Timer B Prescale Snapshot 0x00000060 TIMER_TBPS_PSS GPTM Timer A Prescaler Value [15:0] TAPV GPTM Timer A Prescale Value 0x00000064 TBPV GPTM Timer B Prescale Value 0x00000068 DMAEV GPTM DMA Event 0x0000006C TIMER_DMAEV_TATODMAEN GPTM A Time-Out Event DMA Trigger Enable [0:0] TIMER_DMAEV_CAMDMAEN GPTM A Capture Match Event DMA Trigger Enable [1:1] TIMER_DMAEV_CAEDMAEN GPTM A Capture Event DMA Trigger Enable [2:2] TIMER_DMAEV_RTCDMAEN GPTM A RTC Match Event DMA Trigger Enable [3:3] TIMER_DMAEV_TAMDMAEN GPTM A Mode Match Event DMA Trigger Enable [4:4] TIMER_DMAEV_TBTODMAEN GPTM B Time-Out Event DMA Trigger Enable [8:8] TIMER_DMAEV_CBMDMAEN GPTM B Capture Match Event DMA Trigger Enable [9:9] TIMER_DMAEV_CBEDMAEN GPTM B Capture Event DMA Trigger Enable [10:10] TIMER_DMAEV_TBMDMAEN GPTM B Mode Match Event DMA Trigger Enable [11:11] ADCEV GPTM ADC Event 0x00000070 TIMER_ADCEV_TATOADCEN GPTM A Time-Out Event ADC Trigger Enable [0:0] TIMER_ADCEV_CAMADCEN GPTM A Capture Match Event ADC Trigger Enable [1:1] TIMER_ADCEV_CAEADCEN GPTM A Capture Event ADC Trigger Enable [2:2] TIMER_ADCEV_RTCADCEN GPTM RTC Match Event ADC Trigger Enable [3:3] TIMER_ADCEV_TAMADCEN GPTM A Mode Match Event ADC Trigger Enable [4:4] TIMER_ADCEV_TBTOADCEN GPTM B Time-Out Event ADC Trigger Enable [8:8] TIMER_ADCEV_CBMADCEN GPTM B Capture Match Event ADC Trigger Enable [9:9] TIMER_ADCEV_CBEADCEN GPTM B Capture Event ADC Trigger Enable [10:10] TIMER_ADCEV_TBMADCEN GPTM B Mode Match Event ADC Trigger Enable [11:11] PP GPTM Peripheral Properties 0x00000FC0 TIMER_PP_SIZE Count Size [3:0] TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 TIMER_PP_CHAIN Chain with Other Timers [4:4] TIMER_PP_SYNCCNT Synchronize Start [5:5] TIMER1 TIMER1 0x40031000 TIMER1A21 TIMER1B22 TIMER2 TIMER2 0x40032000 TIMER2A23 TIMER2B24 TIMER3 TIMER3 0x40033000 TIMER3A35 TIMER3B36 TIMER4 TIMER4 0x40034000 TIMER4A63 TIMER4B64 TIMER5 TIMER5 0x40035000 TIMER5A65 TIMER5B66 ADC0 Register map for ADC0 peripheral ADC ADC0 0x40038000 0 0x00001000 registers ADC0SS014 ADC0SS115 ADC0SS216 ADC0SS317 ACTSS ADC Active Sample Sequencer 0x00000000 ADC_ACTSS_ASEN0 ADC SS0 Enable [0:0] ADC_ACTSS_ASEN1 ADC SS1 Enable [1:1] ADC_ACTSS_ASEN2 ADC SS2 Enable [2:2] ADC_ACTSS_ASEN3 ADC SS3 Enable [3:3] ADC_ACTSS_ADEN0 ADC SS1 DMA Enable [8:8] ADC_ACTSS_ADEN1 ADC SS1 DMA Enable [9:9] ADC_ACTSS_ADEN2 ADC SS2 DMA Enable [10:10] ADC_ACTSS_ADEN3 ADC SS3 DMA Enable [11:11] ADC_ACTSS_BUSY ADC Busy [16:16] RIS ADC Raw Interrupt Status 0x00000004 ADC_RIS_INR0 SS0 Raw Interrupt Status [0:0] ADC_RIS_INR1 SS1 Raw Interrupt Status [1:1] ADC_RIS_INR2 SS2 Raw Interrupt Status [2:2] ADC_RIS_INR3 SS3 Raw Interrupt Status [3:3] ADC_RIS_DMAINR0 SS0 DMA Raw Interrupt Status [8:8] ADC_RIS_DMAINR1 SS1 DMA Raw Interrupt Status [9:9] ADC_RIS_DMAINR2 SS2 DMA Raw Interrupt Status [10:10] ADC_RIS_DMAINR3 SS3 DMA Raw Interrupt Status [11:11] ADC_RIS_INRDC Digital Comparator Raw Interrupt Status [16:16] IM ADC Interrupt Mask 0x00000008 ADC_IM_MASK0 SS0 Interrupt Mask [0:0] ADC_IM_MASK1 SS1 Interrupt Mask [1:1] ADC_IM_MASK2 SS2 Interrupt Mask [2:2] ADC_IM_MASK3 SS3 Interrupt Mask [3:3] ADC_IM_DMAMASK0 SS0 DMA Interrupt Mask [8:8] ADC_IM_DMAMASK1 SS1 DMA Interrupt Mask [9:9] ADC_IM_DMAMASK2 SS2 DMA Interrupt Mask [10:10] ADC_IM_DMAMASK3 SS3 DMA Interrupt Mask [11:11] ADC_IM_DCONSS0 Digital Comparator Interrupt on SS0 [16:16] ADC_IM_DCONSS1 Digital Comparator Interrupt on SS1 [17:17] ADC_IM_DCONSS2 Digital Comparator Interrupt on SS2 [18:18] ADC_IM_DCONSS3 Digital Comparator Interrupt on SS3 [19:19] ISC ADC Interrupt Status and Clear 0x0000000C ADC_ISC_IN0 SS0 Interrupt Status and Clear [0:0] ADC_ISC_IN1 SS1 Interrupt Status and Clear [1:1] ADC_ISC_IN2 SS2 Interrupt Status and Clear [2:2] ADC_ISC_IN3 SS3 Interrupt Status and Clear [3:3] ADC_ISC_DMAIN0 SS0 DMA Interrupt Status and Clear [8:8] ADC_ISC_DMAIN1 SS1 DMA Interrupt Status and Clear [9:9] ADC_ISC_DMAIN2 SS2 DMA Interrupt Status and Clear [10:10] ADC_ISC_DMAIN3 SS3 DMA Interrupt Status and Clear [11:11] ADC_ISC_DCINSS0 Digital Comparator Interrupt Status on SS0 [16:16] ADC_ISC_DCINSS1 Digital Comparator Interrupt Status on SS1 [17:17] ADC_ISC_DCINSS2 Digital Comparator Interrupt Status on SS2 [18:18] ADC_ISC_DCINSS3 Digital Comparator Interrupt Status on SS3 [19:19] OSTAT ADC Overflow Status 0x00000010 ADC_OSTAT_OV0 SS0 FIFO Overflow [0:0] ADC_OSTAT_OV1 SS1 FIFO Overflow [1:1] ADC_OSTAT_OV2 SS2 FIFO Overflow [2:2] ADC_OSTAT_OV3 SS3 FIFO Overflow [3:3] EMUX ADC Event Multiplexer Select 0x00000014 ADC_EMUX_EM0 SS0 Trigger Select [3:0] ADC_EMUX_EM0_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM0_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM0_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM0_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM0_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM0_TIMER Timer 0x5 ADC_EMUX_EM0_PWM0 PWM generator 0 0x6 ADC_EMUX_EM0_PWM1 PWM generator 1 0x7 ADC_EMUX_EM0_PWM2 PWM generator 2 0x8 ADC_EMUX_EM0_PWM3 PWM generator 3 0x9 ADC_EMUX_EM0_NEVER Never Trigger 0xe ADC_EMUX_EM0_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM1 SS1 Trigger Select [7:4] ADC_EMUX_EM1_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM1_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM1_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM1_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM1_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM1_TIMER Timer 0x5 ADC_EMUX_EM1_PWM0 PWM generator 0 0x6 ADC_EMUX_EM1_PWM1 PWM generator 1 0x7 ADC_EMUX_EM1_PWM2 PWM generator 2 0x8 ADC_EMUX_EM1_PWM3 PWM generator 3 0x9 ADC_EMUX_EM1_NEVER Never Trigger 0xe ADC_EMUX_EM1_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM2 SS2 Trigger Select [11:8] ADC_EMUX_EM2_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM2_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM2_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM2_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM2_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM2_TIMER Timer 0x5 ADC_EMUX_EM2_PWM0 PWM generator 0 0x6 ADC_EMUX_EM2_PWM1 PWM generator 1 0x7 ADC_EMUX_EM2_PWM2 PWM generator 2 0x8 ADC_EMUX_EM2_PWM3 PWM generator 3 0x9 ADC_EMUX_EM2_NEVER Never Trigger 0xe ADC_EMUX_EM2_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM3 SS3 Trigger Select [15:12] ADC_EMUX_EM3_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM3_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM3_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM3_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM3_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM3_TIMER Timer 0x5 ADC_EMUX_EM3_PWM0 PWM generator 0 0x6 ADC_EMUX_EM3_PWM1 PWM generator 1 0x7 ADC_EMUX_EM3_PWM2 PWM generator 2 0x8 ADC_EMUX_EM3_PWM3 PWM generator 3 0x9 ADC_EMUX_EM3_NEVER Never Trigger 0xe ADC_EMUX_EM3_ALWAYS Always (continuously sample) 0xf USTAT ADC Underflow Status 0x00000018 ADC_USTAT_UV0 SS0 FIFO Underflow [0:0] ADC_USTAT_UV1 SS1 FIFO Underflow [1:1] ADC_USTAT_UV2 SS2 FIFO Underflow [2:2] ADC_USTAT_UV3 SS3 FIFO Underflow [3:3] TSSEL ADC Trigger Source Select 0x0000001C ADC_TSSEL_PS0 Generator 0 PWM Module Trigger Select [5:4] ADC_TSSEL_PS0_0 Use Generator 0 (and its trigger) in PWM module 0 0x0 ADC_TSSEL_PS1 Generator 1 PWM Module Trigger Select [13:12] ADC_TSSEL_PS1_0 Use Generator 1 (and its trigger) in PWM module 0 0x0 ADC_TSSEL_PS2 Generator 2 PWM Module Trigger Select [21:20] ADC_TSSEL_PS2_0 Use Generator 2 (and its trigger) in PWM module 0 0x0 ADC_TSSEL_PS3 Generator 3 PWM Module Trigger Select [29:28] ADC_TSSEL_PS3_0 Use Generator 3 (and its trigger) in PWM module 0 0x0 SSPRI ADC Sample Sequencer Priority 0x00000020 ADC_SSPRI_SS0 SS0 Priority [1:0] ADC_SSPRI_SS1 SS1 Priority [5:4] ADC_SSPRI_SS2 SS2 Priority [9:8] ADC_SSPRI_SS3 SS3 Priority [13:12] SPC ADC Sample Phase Control 0x00000024 ADC_SPC_PHASE Phase Difference [3:0] ADC_SPC_PHASE_0 ADC sample lags by 0.0 0x0 ADC_SPC_PHASE_22_5 ADC sample lags by 22.5 0x1 ADC_SPC_PHASE_45 ADC sample lags by 45.0 0x2 ADC_SPC_PHASE_67_5 ADC sample lags by 67.5 0x3 ADC_SPC_PHASE_90 ADC sample lags by 90.0 0x4 ADC_SPC_PHASE_112_5 ADC sample lags by 112.5 0x5 ADC_SPC_PHASE_135 ADC sample lags by 135.0 0x6 ADC_SPC_PHASE_157_5 ADC sample lags by 157.5 0x7 ADC_SPC_PHASE_180 ADC sample lags by 180.0 0x8 ADC_SPC_PHASE_202_5 ADC sample lags by 202.5 0x9 ADC_SPC_PHASE_225 ADC sample lags by 225.0 0xa ADC_SPC_PHASE_247_5 ADC sample lags by 247.5 0xb ADC_SPC_PHASE_270 ADC sample lags by 270.0 0xc ADC_SPC_PHASE_292_5 ADC sample lags by 292.5 0xd ADC_SPC_PHASE_315 ADC sample lags by 315.0 0xe ADC_SPC_PHASE_337_5 ADC sample lags by 337.5 0xf PSSI ADC Processor Sample Sequence Initiate 0x00000028 ADC_PSSI_SS0 SS0 Initiate [0:0] ADC_PSSI_SS1 SS1 Initiate [1:1] ADC_PSSI_SS2 SS2 Initiate [2:2] ADC_PSSI_SS3 SS3 Initiate [3:3] ADC_PSSI_SYNCWAIT Synchronize Wait [27:27] ADC_PSSI_GSYNC Global Synchronize [31:31] SAC ADC Sample Averaging Control 0x00000030 ADC_SAC_AVG Hardware Averaging Control [2:0] ADC_SAC_AVG_OFF No hardware oversampling 0x0 ADC_SAC_AVG_2X 2x hardware oversampling 0x1 ADC_SAC_AVG_4X 4x hardware oversampling 0x2 ADC_SAC_AVG_8X 8x hardware oversampling 0x3 ADC_SAC_AVG_16X 16x hardware oversampling 0x4 ADC_SAC_AVG_32X 32x hardware oversampling 0x5 ADC_SAC_AVG_64X 64x hardware oversampling 0x6 DCISC ADC Digital Comparator Interrupt Status and Clear 0x00000034 ADC_DCISC_DCINT0 Digital Comparator 0 Interrupt Status and Clear [0:0] ADC_DCISC_DCINT1 Digital Comparator 1 Interrupt Status and Clear [1:1] ADC_DCISC_DCINT2 Digital Comparator 2 Interrupt Status and Clear [2:2] ADC_DCISC_DCINT3 Digital Comparator 3 Interrupt Status and Clear [3:3] ADC_DCISC_DCINT4 Digital Comparator 4 Interrupt Status and Clear [4:4] ADC_DCISC_DCINT5 Digital Comparator 5 Interrupt Status and Clear [5:5] ADC_DCISC_DCINT6 Digital Comparator 6 Interrupt Status and Clear [6:6] ADC_DCISC_DCINT7 Digital Comparator 7 Interrupt Status and Clear [7:7] CTL ADC Control 0x00000038 ADC_CTL_VREF Voltage Reference Select [0:0] ADC_CTL_VREF_INTERNAL VDDA and GNDA are the voltage references 0x0 ADC_CTL_VREF_EXT_3V The external VREFA+ and VREFA- inputs are the voltage references 0x1 ADC_CTL_DITHER Dither Mode Enable [6:6] SSMUX0 ADC Sample Sequence Input Multiplexer Select 0 0x00000040 ADC_SSMUX0_MUX0 1st Sample Input Select [3:0] ADC_SSMUX0_MUX1 2nd Sample Input Select [7:4] ADC_SSMUX0_MUX2 3rd Sample Input Select [11:8] ADC_SSMUX0_MUX3 4th Sample Input Select [15:12] ADC_SSMUX0_MUX4 5th Sample Input Select [19:16] ADC_SSMUX0_MUX5 6th Sample Input Select [23:20] ADC_SSMUX0_MUX6 7th Sample Input Select [27:24] ADC_SSMUX0_MUX7 8th Sample Input Select [31:28] SSCTL0 ADC Sample Sequence Control 0 0x00000044 ADC_SSCTL0_D0 1st Sample Differential Input Select [0:0] ADC_SSCTL0_END0 1st Sample is End of Sequence [1:1] ADC_SSCTL0_IE0 1st Sample Interrupt Enable [2:2] ADC_SSCTL0_TS0 1st Sample Temp Sensor Select [3:3] ADC_SSCTL0_D1 2nd Sample Differential Input Select [4:4] ADC_SSCTL0_END1 2nd Sample is End of Sequence [5:5] ADC_SSCTL0_IE1 2nd Sample Interrupt Enable [6:6] ADC_SSCTL0_TS1 2nd Sample Temp Sensor Select [7:7] ADC_SSCTL0_D2 3rd Sample Differential Input Select [8:8] ADC_SSCTL0_END2 3rd Sample is End of Sequence [9:9] ADC_SSCTL0_IE2 3rd Sample Interrupt Enable [10:10] ADC_SSCTL0_TS2 3rd Sample Temp Sensor Select [11:11] ADC_SSCTL0_D3 4th Sample Differential Input Select [12:12] ADC_SSCTL0_END3 4th Sample is End of Sequence [13:13] ADC_SSCTL0_IE3 4th Sample Interrupt Enable [14:14] ADC_SSCTL0_TS3 4th Sample Temp Sensor Select [15:15] ADC_SSCTL0_D4 5th Sample Differential Input Select [16:16] ADC_SSCTL0_END4 5th Sample is End of Sequence [17:17] ADC_SSCTL0_IE4 5th Sample Interrupt Enable [18:18] ADC_SSCTL0_TS4 5th Sample Temp Sensor Select [19:19] ADC_SSCTL0_D5 6th Sample Differential Input Select [20:20] ADC_SSCTL0_END5 6th Sample is End of Sequence [21:21] ADC_SSCTL0_IE5 6th Sample Interrupt Enable [22:22] ADC_SSCTL0_TS5 6th Sample Temp Sensor Select [23:23] ADC_SSCTL0_D6 7th Sample Differential Input Select [24:24] ADC_SSCTL0_END6 7th Sample is End of Sequence [25:25] ADC_SSCTL0_IE6 7th Sample Interrupt Enable [26:26] ADC_SSCTL0_TS6 7th Sample Temp Sensor Select [27:27] ADC_SSCTL0_D7 8th Sample Differential Input Select [28:28] ADC_SSCTL0_END7 8th Sample is End of Sequence [29:29] ADC_SSCTL0_IE7 8th Sample Interrupt Enable [30:30] ADC_SSCTL0_TS7 8th Sample Temp Sensor Select [31:31] SSFIFO0 ADC Sample Sequence Result FIFO 0 0x00000048 ADC_SSFIFO0_DATA Conversion Result Data [11:0] SSFSTAT0 ADC Sample Sequence FIFO 0 Status 0x0000004C ADC_SSFSTAT0_TPTR FIFO Tail Pointer [3:0] ADC_SSFSTAT0_HPTR FIFO Head Pointer [7:4] ADC_SSFSTAT0_EMPTY FIFO Empty [8:8] ADC_SSFSTAT0_FULL FIFO Full [12:12] SSOP0 ADC Sample Sequence 0 Operation 0x00000050 ADC_SSOP0_S0DCOP Sample 0 Digital Comparator Operation [0:0] ADC_SSOP0_S1DCOP Sample 1 Digital Comparator Operation [4:4] ADC_SSOP0_S2DCOP Sample 2 Digital Comparator Operation [8:8] ADC_SSOP0_S3DCOP Sample 3 Digital Comparator Operation [12:12] ADC_SSOP0_S4DCOP Sample 4 Digital Comparator Operation [16:16] ADC_SSOP0_S5DCOP Sample 5 Digital Comparator Operation [20:20] ADC_SSOP0_S6DCOP Sample 6 Digital Comparator Operation [24:24] ADC_SSOP0_S7DCOP Sample 7 Digital Comparator Operation [28:28] SSDC0 ADC Sample Sequence 0 Digital Comparator Select 0x00000054 ADC_SSDC0_S0DCSEL Sample 0 Digital Comparator Select [3:0] ADC_SSDC0_S1DCSEL Sample 1 Digital Comparator Select [7:4] ADC_SSDC0_S2DCSEL Sample 2 Digital Comparator Select [11:8] ADC_SSDC0_S3DCSEL Sample 3 Digital Comparator Select [15:12] ADC_SSDC0_S4DCSEL Sample 4 Digital Comparator Select [19:16] ADC_SSDC0_S5DCSEL Sample 5 Digital Comparator Select [23:20] ADC_SSDC0_S6DCSEL Sample 6 Digital Comparator Select [27:24] ADC_SSDC0_S7DCSEL Sample 7 Digital Comparator Select [31:28] SSEMUX0 ADC Sample Sequence Extended Input Multiplexer Select 0 0x00000058 ADC_SSEMUX0_EMUX0 1st Sample Input Select (Upper Bit) [0:0] ADC_SSEMUX0_EMUX1 2th Sample Input Select (Upper Bit) [4:4] ADC_SSEMUX0_EMUX2 3rd Sample Input Select (Upper Bit) [8:8] ADC_SSEMUX0_EMUX3 4th Sample Input Select (Upper Bit) [12:12] ADC_SSEMUX0_EMUX4 5th Sample Input Select (Upper Bit) [16:16] ADC_SSEMUX0_EMUX5 6th Sample Input Select (Upper Bit) [20:20] ADC_SSEMUX0_EMUX6 7th Sample Input Select (Upper Bit) [24:24] ADC_SSEMUX0_EMUX7 8th Sample Input Select (Upper Bit) [28:28] SSTSH0 ADC Sample Sequence 0 Sample and Hold Time 0x0000005C ADC_SSTSH0_TSH0 1st Sample and Hold Period Select [3:0] ADC_SSTSH0_TSH1 2nd Sample and Hold Period Select [7:4] ADC_SSTSH0_TSH2 3rd Sample and Hold Period Select [11:8] ADC_SSTSH0_TSH3 4th Sample and Hold Period Select [15:12] ADC_SSTSH0_TSH4 5th Sample and Hold Period Select [19:16] ADC_SSTSH0_TSH5 6th Sample and Hold Period Select [23:20] ADC_SSTSH0_TSH6 7th Sample and Hold Period Select [27:24] ADC_SSTSH0_TSH7 8th Sample and Hold Period Select [31:28] SSMUX1 ADC Sample Sequence Input Multiplexer Select 1 0x00000060 ADC_SSMUX1_MUX0 1st Sample Input Select [3:0] ADC_SSMUX1_MUX1 2nd Sample Input Select [7:4] ADC_SSMUX1_MUX2 3rd Sample Input Select [11:8] ADC_SSMUX1_MUX3 4th Sample Input Select [15:12] SSCTL1 ADC Sample Sequence Control 1 0x00000064 ADC_SSCTL1_D0 1st Sample Differential Input Select [0:0] ADC_SSCTL1_END0 1st Sample is End of Sequence [1:1] ADC_SSCTL1_IE0 1st Sample Interrupt Enable [2:2] ADC_SSCTL1_TS0 1st Sample Temp Sensor Select [3:3] ADC_SSCTL1_D1 2nd Sample Differential Input Select [4:4] ADC_SSCTL1_END1 2nd Sample is End of Sequence [5:5] ADC_SSCTL1_IE1 2nd Sample Interrupt Enable [6:6] ADC_SSCTL1_TS1 2nd Sample Temp Sensor Select [7:7] ADC_SSCTL1_D2 3rd Sample Differential Input Select [8:8] ADC_SSCTL1_END2 3rd Sample is End of Sequence [9:9] ADC_SSCTL1_IE2 3rd Sample Interrupt Enable [10:10] ADC_SSCTL1_TS2 3rd Sample Temp Sensor Select [11:11] ADC_SSCTL1_D3 4th Sample Differential Input Select [12:12] ADC_SSCTL1_END3 4th Sample is End of Sequence [13:13] ADC_SSCTL1_IE3 4th Sample Interrupt Enable [14:14] ADC_SSCTL1_TS3 4th Sample Temp Sensor Select [15:15] SSFIFO1 ADC Sample Sequence Result FIFO 1 0x00000068 ADC_SSFIFO1_DATA Conversion Result Data [11:0] SSFSTAT1 ADC Sample Sequence FIFO 1 Status 0x0000006C ADC_SSFSTAT1_TPTR FIFO Tail Pointer [3:0] ADC_SSFSTAT1_HPTR FIFO Head Pointer [7:4] ADC_SSFSTAT1_EMPTY FIFO Empty [8:8] ADC_SSFSTAT1_FULL FIFO Full [12:12] SSOP1 ADC Sample Sequence 1 Operation 0x00000070 ADC_SSOP1_S0DCOP Sample 0 Digital Comparator Operation [0:0] ADC_SSOP1_S1DCOP Sample 1 Digital Comparator Operation [4:4] ADC_SSOP1_S2DCOP Sample 2 Digital Comparator Operation [8:8] ADC_SSOP1_S3DCOP Sample 3 Digital Comparator Operation [12:12] SSDC1 ADC Sample Sequence 1 Digital Comparator Select 0x00000074 ADC_SSDC1_S0DCSEL Sample 0 Digital Comparator Select [3:0] ADC_SSDC1_S1DCSEL Sample 1 Digital Comparator Select [7:4] ADC_SSDC1_S2DCSEL Sample 2 Digital Comparator Select [11:8] ADC_SSDC1_S3DCSEL Sample 3 Digital Comparator Select [15:12] SSEMUX1 ADC Sample Sequence Extended Input Multiplexer Select 1 0x00000078 ADC_SSEMUX1_EMUX0 1st Sample Input Select (Upper Bit) [0:0] ADC_SSEMUX1_EMUX1 2th Sample Input Select (Upper Bit) [4:4] ADC_SSEMUX1_EMUX2 3rd Sample Input Select (Upper Bit) [8:8] ADC_SSEMUX1_EMUX3 4th Sample Input Select (Upper Bit) [12:12] SSTSH1 ADC Sample Sequence 1 Sample and Hold Time 0x0000007C ADC_SSTSH1_TSH0 1st Sample and Hold Period Select [3:0] ADC_SSTSH1_TSH1 2nd Sample and Hold Period Select [7:4] ADC_SSTSH1_TSH2 3rd Sample and Hold Period Select [11:8] ADC_SSTSH1_TSH3 4th Sample and Hold Period Select [15:12] SSMUX2 ADC Sample Sequence Input Multiplexer Select 2 0x00000080 ADC_SSMUX2_MUX0 1st Sample Input Select [3:0] ADC_SSMUX2_MUX1 2nd Sample Input Select [7:4] ADC_SSMUX2_MUX2 3rd Sample Input Select [11:8] ADC_SSMUX2_MUX3 4th Sample Input Select [15:12] SSCTL2 ADC Sample Sequence Control 2 0x00000084 ADC_SSCTL2_D0 1st Sample Differential Input Select [0:0] ADC_SSCTL2_END0 1st Sample is End of Sequence [1:1] ADC_SSCTL2_IE0 1st Sample Interrupt Enable [2:2] ADC_SSCTL2_TS0 1st Sample Temp Sensor Select [3:3] ADC_SSCTL2_D1 2nd Sample Differential Input Select [4:4] ADC_SSCTL2_END1 2nd Sample is End of Sequence [5:5] ADC_SSCTL2_IE1 2nd Sample Interrupt Enable [6:6] ADC_SSCTL2_TS1 2nd Sample Temp Sensor Select [7:7] ADC_SSCTL2_D2 3rd Sample Differential Input Select [8:8] ADC_SSCTL2_END2 3rd Sample is End of Sequence [9:9] ADC_SSCTL2_IE2 3rd Sample Interrupt Enable [10:10] ADC_SSCTL2_TS2 3rd Sample Temp Sensor Select [11:11] ADC_SSCTL2_D3 4th Sample Differential Input Select [12:12] ADC_SSCTL2_END3 4th Sample is End of Sequence [13:13] ADC_SSCTL2_IE3 4th Sample Interrupt Enable [14:14] ADC_SSCTL2_TS3 4th Sample Temp Sensor Select [15:15] SSFIFO2 ADC Sample Sequence Result FIFO 2 0x00000088 ADC_SSFIFO2_DATA Conversion Result Data [11:0] SSFSTAT2 ADC Sample Sequence FIFO 2 Status 0x0000008C ADC_SSFSTAT2_TPTR FIFO Tail Pointer [3:0] ADC_SSFSTAT2_HPTR FIFO Head Pointer [7:4] ADC_SSFSTAT2_EMPTY FIFO Empty [8:8] ADC_SSFSTAT2_FULL FIFO Full [12:12] SSOP2 ADC Sample Sequence 2 Operation 0x00000090 ADC_SSOP2_S0DCOP Sample 0 Digital Comparator Operation [0:0] ADC_SSOP2_S1DCOP Sample 1 Digital Comparator Operation [4:4] ADC_SSOP2_S2DCOP Sample 2 Digital Comparator Operation [8:8] ADC_SSOP2_S3DCOP Sample 3 Digital Comparator Operation [12:12] SSDC2 ADC Sample Sequence 2 Digital Comparator Select 0x00000094 ADC_SSDC2_S0DCSEL Sample 0 Digital Comparator Select [3:0] ADC_SSDC2_S1DCSEL Sample 1 Digital Comparator Select [7:4] ADC_SSDC2_S2DCSEL Sample 2 Digital Comparator Select [11:8] ADC_SSDC2_S3DCSEL Sample 3 Digital Comparator Select [15:12] SSEMUX2 ADC Sample Sequence Extended Input Multiplexer Select 2 0x00000098 ADC_SSEMUX2_EMUX0 1st Sample Input Select (Upper Bit) [0:0] ADC_SSEMUX2_EMUX1 2th Sample Input Select (Upper Bit) [4:4] ADC_SSEMUX2_EMUX2 3rd Sample Input Select (Upper Bit) [8:8] ADC_SSEMUX2_EMUX3 4th Sample Input Select (Upper Bit) [12:12] SSTSH2 ADC Sample Sequence 2 Sample and Hold Time 0x0000009C ADC_SSTSH2_TSH0 1st Sample and Hold Period Select [3:0] ADC_SSTSH2_TSH1 2nd Sample and Hold Period Select [7:4] ADC_SSTSH2_TSH2 3rd Sample and Hold Period Select [11:8] ADC_SSTSH2_TSH3 4th Sample and Hold Period Select [15:12] SSMUX3 ADC Sample Sequence Input Multiplexer Select 3 0x000000A0 ADC_SSMUX3_MUX0 1st Sample Input Select [3:0] SSCTL3 ADC Sample Sequence Control 3 0x000000A4 ADC_SSCTL3_D0 Sample Differential Input Select [0:0] ADC_SSCTL3_END0 End of Sequence [1:1] ADC_SSCTL3_IE0 Sample Interrupt Enable [2:2] ADC_SSCTL3_TS0 1st Sample Temp Sensor Select [3:3] SSFIFO3 ADC Sample Sequence Result FIFO 3 0x000000A8 ADC_SSFIFO3_DATA Conversion Result Data [11:0] SSFSTAT3 ADC Sample Sequence FIFO 3 Status 0x000000AC ADC_SSFSTAT3_TPTR FIFO Tail Pointer [3:0] ADC_SSFSTAT3_HPTR FIFO Head Pointer [7:4] ADC_SSFSTAT3_EMPTY FIFO Empty [8:8] ADC_SSFSTAT3_FULL FIFO Full [12:12] SSOP3 ADC Sample Sequence 3 Operation 0x000000B0 ADC_SSOP3_S0DCOP Sample 0 Digital Comparator Operation [0:0] SSDC3 ADC Sample Sequence 3 Digital Comparator Select 0x000000B4 ADC_SSDC3_S0DCSEL Sample 0 Digital Comparator Select [3:0] SSEMUX3 ADC Sample Sequence Extended Input Multiplexer Select 3 0x000000B8 ADC_SSEMUX3_EMUX0 1st Sample Input Select (Upper Bit) [0:0] SSTSH3 ADC Sample Sequence 3 Sample and Hold Time 0x000000BC ADC_SSTSH3_TSH0 1st Sample and Hold Period Select [3:0] DCRIC ADC Digital Comparator Reset Initial Conditions 0x00000D00 write-only ADC_DCRIC_DCINT0 Digital Comparator Interrupt 0 [0:0] write-only ADC_DCRIC_DCINT1 Digital Comparator Interrupt 1 [1:1] write-only ADC_DCRIC_DCINT2 Digital Comparator Interrupt 2 [2:2] write-only ADC_DCRIC_DCINT3 Digital Comparator Interrupt 3 [3:3] write-only ADC_DCRIC_DCINT4 Digital Comparator Interrupt 4 [4:4] write-only ADC_DCRIC_DCINT5 Digital Comparator Interrupt 5 [5:5] write-only ADC_DCRIC_DCINT6 Digital Comparator Interrupt 6 [6:6] write-only ADC_DCRIC_DCINT7 Digital Comparator Interrupt 7 [7:7] write-only ADC_DCRIC_DCTRIG0 Digital Comparator Trigger 0 [16:16] write-only ADC_DCRIC_DCTRIG1 Digital Comparator Trigger 1 [17:17] write-only ADC_DCRIC_DCTRIG2 Digital Comparator Trigger 2 [18:18] write-only ADC_DCRIC_DCTRIG3 Digital Comparator Trigger 3 [19:19] write-only ADC_DCRIC_DCTRIG4 Digital Comparator Trigger 4 [20:20] write-only ADC_DCRIC_DCTRIG5 Digital Comparator Trigger 5 [21:21] write-only ADC_DCRIC_DCTRIG6 Digital Comparator Trigger 6 [22:22] write-only ADC_DCRIC_DCTRIG7 Digital Comparator Trigger 7 [23:23] write-only DCCTL0 ADC Digital Comparator Control 0 0x00000E00 ADC_DCCTL0_CIM Comparison Interrupt Mode [1:0] ADC_DCCTL0_CIM_ALWAYS Always 0x0 ADC_DCCTL0_CIM_ONCE Once 0x1 ADC_DCCTL0_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL0_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL0_CIC Comparison Interrupt Condition [3:2] ADC_DCCTL0_CIC_LOW Low Band 0x0 ADC_DCCTL0_CIC_MID Mid Band 0x1 ADC_DCCTL0_CIC_HIGH High Band 0x3 ADC_DCCTL0_CIE Comparison Interrupt Enable [4:4] ADC_DCCTL0_CTM Comparison Trigger Mode [9:8] ADC_DCCTL0_CTM_ALWAYS Always 0x0 ADC_DCCTL0_CTM_ONCE Once 0x1 ADC_DCCTL0_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL0_CTM_HONCE Hysteresis Once 0x3 ADC_DCCTL0_CTC Comparison Trigger Condition [11:10] ADC_DCCTL0_CTC_LOW Low Band 0x0 ADC_DCCTL0_CTC_MID Mid Band 0x1 ADC_DCCTL0_CTC_HIGH High Band 0x3 ADC_DCCTL0_CTE Comparison Trigger Enable [12:12] DCCTL1 ADC Digital Comparator Control 1 0x00000E04 ADC_DCCTL1_CIM Comparison Interrupt Mode [1:0] ADC_DCCTL1_CIM_ALWAYS Always 0x0 ADC_DCCTL1_CIM_ONCE Once 0x1 ADC_DCCTL1_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL1_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL1_CIC Comparison Interrupt Condition [3:2] ADC_DCCTL1_CIC_LOW Low Band 0x0 ADC_DCCTL1_CIC_MID Mid Band 0x1 ADC_DCCTL1_CIC_HIGH High Band 0x3 ADC_DCCTL1_CIE Comparison Interrupt Enable [4:4] ADC_DCCTL1_CTM Comparison Trigger Mode [9:8] ADC_DCCTL1_CTM_ALWAYS Always 0x0 ADC_DCCTL1_CTM_ONCE Once 0x1 ADC_DCCTL1_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL1_CTM_HONCE Hysteresis Once 0x3 ADC_DCCTL1_CTC Comparison Trigger Condition [11:10] ADC_DCCTL1_CTC_LOW Low Band 0x0 ADC_DCCTL1_CTC_MID Mid Band 0x1 ADC_DCCTL1_CTC_HIGH High Band 0x3 ADC_DCCTL1_CTE Comparison Trigger Enable [12:12] DCCTL2 ADC Digital Comparator Control 2 0x00000E08 ADC_DCCTL2_CIM Comparison Interrupt Mode [1:0] ADC_DCCTL2_CIM_ALWAYS Always 0x0 ADC_DCCTL2_CIM_ONCE Once 0x1 ADC_DCCTL2_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL2_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL2_CIC Comparison Interrupt Condition [3:2] ADC_DCCTL2_CIC_LOW Low Band 0x0 ADC_DCCTL2_CIC_MID Mid Band 0x1 ADC_DCCTL2_CIC_HIGH High Band 0x3 ADC_DCCTL2_CIE Comparison Interrupt Enable [4:4] ADC_DCCTL2_CTM Comparison Trigger Mode [9:8] ADC_DCCTL2_CTM_ALWAYS Always 0x0 ADC_DCCTL2_CTM_ONCE Once 0x1 ADC_DCCTL2_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL2_CTM_HONCE Hysteresis Once 0x3 ADC_DCCTL2_CTC Comparison Trigger Condition [11:10] ADC_DCCTL2_CTC_LOW Low Band 0x0 ADC_DCCTL2_CTC_MID Mid Band 0x1 ADC_DCCTL2_CTC_HIGH High Band 0x3 ADC_DCCTL2_CTE Comparison Trigger Enable [12:12] DCCTL3 ADC Digital Comparator Control 3 0x00000E0C ADC_DCCTL3_CIM Comparison Interrupt Mode [1:0] ADC_DCCTL3_CIM_ALWAYS Always 0x0 ADC_DCCTL3_CIM_ONCE Once 0x1 ADC_DCCTL3_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL3_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL3_CIC Comparison Interrupt Condition [3:2] ADC_DCCTL3_CIC_LOW Low Band 0x0 ADC_DCCTL3_CIC_MID Mid Band 0x1 ADC_DCCTL3_CIC_HIGH High Band 0x3 ADC_DCCTL3_CIE Comparison Interrupt Enable [4:4] ADC_DCCTL3_CTM Comparison Trigger Mode [9:8] ADC_DCCTL3_CTM_ALWAYS Always 0x0 ADC_DCCTL3_CTM_ONCE Once 0x1 ADC_DCCTL3_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL3_CTM_HONCE Hysteresis Once 0x3 ADC_DCCTL3_CTC Comparison Trigger Condition [11:10] ADC_DCCTL3_CTC_LOW Low Band 0x0 ADC_DCCTL3_CTC_MID Mid Band 0x1 ADC_DCCTL3_CTC_HIGH High Band 0x3 ADC_DCCTL3_CTE Comparison Trigger Enable [12:12] DCCTL4 ADC Digital Comparator Control 4 0x00000E10 ADC_DCCTL4_CIM Comparison Interrupt Mode [1:0] ADC_DCCTL4_CIM_ALWAYS Always 0x0 ADC_DCCTL4_CIM_ONCE Once 0x1 ADC_DCCTL4_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL4_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL4_CIC Comparison Interrupt Condition [3:2] ADC_DCCTL4_CIC_LOW Low Band 0x0 ADC_DCCTL4_CIC_MID Mid Band 0x1 ADC_DCCTL4_CIC_HIGH High Band 0x3 ADC_DCCTL4_CIE Comparison Interrupt Enable [4:4] ADC_DCCTL4_CTM Comparison Trigger Mode [9:8] ADC_DCCTL4_CTM_ALWAYS Always 0x0 ADC_DCCTL4_CTM_ONCE Once 0x1 ADC_DCCTL4_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL4_CTM_HONCE Hysteresis Once 0x3 ADC_DCCTL4_CTC Comparison Trigger Condition [11:10] ADC_DCCTL4_CTC_LOW Low Band 0x0 ADC_DCCTL4_CTC_MID Mid Band 0x1 ADC_DCCTL4_CTC_HIGH High Band 0x3 ADC_DCCTL4_CTE Comparison Trigger Enable [12:12] DCCTL5 ADC Digital Comparator Control 5 0x00000E14 ADC_DCCTL5_CIM Comparison Interrupt Mode [1:0] ADC_DCCTL5_CIM_ALWAYS Always 0x0 ADC_DCCTL5_CIM_ONCE Once 0x1 ADC_DCCTL5_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL5_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL5_CIC Comparison Interrupt Condition [3:2] ADC_DCCTL5_CIC_LOW Low Band 0x0 ADC_DCCTL5_CIC_MID Mid Band 0x1 ADC_DCCTL5_CIC_HIGH High Band 0x3 ADC_DCCTL5_CIE Comparison Interrupt Enable [4:4] ADC_DCCTL5_CTM Comparison Trigger Mode [9:8] ADC_DCCTL5_CTM_ALWAYS Always 0x0 ADC_DCCTL5_CTM_ONCE Once 0x1 ADC_DCCTL5_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL5_CTM_HONCE Hysteresis Once 0x3 ADC_DCCTL5_CTC Comparison Trigger Condition [11:10] ADC_DCCTL5_CTC_LOW Low Band 0x0 ADC_DCCTL5_CTC_MID Mid Band 0x1 ADC_DCCTL5_CTC_HIGH High Band 0x3 ADC_DCCTL5_CTE Comparison Trigger Enable [12:12] DCCTL6 ADC Digital Comparator Control 6 0x00000E18 ADC_DCCTL6_CIM Comparison Interrupt Mode [1:0] ADC_DCCTL6_CIM_ALWAYS Always 0x0 ADC_DCCTL6_CIM_ONCE Once 0x1 ADC_DCCTL6_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL6_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL6_CIC Comparison Interrupt Condition [3:2] ADC_DCCTL6_CIC_LOW Low Band 0x0 ADC_DCCTL6_CIC_MID Mid Band 0x1 ADC_DCCTL6_CIC_HIGH High Band 0x3 ADC_DCCTL6_CIE Comparison Interrupt Enable [4:4] ADC_DCCTL6_CTM Comparison Trigger Mode [9:8] ADC_DCCTL6_CTM_ALWAYS Always 0x0 ADC_DCCTL6_CTM_ONCE Once 0x1 ADC_DCCTL6_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL6_CTM_HONCE Hysteresis Once 0x3 ADC_DCCTL6_CTC Comparison Trigger Condition [11:10] ADC_DCCTL6_CTC_LOW Low Band 0x0 ADC_DCCTL6_CTC_MID Mid Band 0x1 ADC_DCCTL6_CTC_HIGH High Band 0x3 ADC_DCCTL6_CTE Comparison Trigger Enable [12:12] DCCTL7 ADC Digital Comparator Control 7 0x00000E1C ADC_DCCTL7_CIM Comparison Interrupt Mode [1:0] ADC_DCCTL7_CIM_ALWAYS Always 0x0 ADC_DCCTL7_CIM_ONCE Once 0x1 ADC_DCCTL7_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL7_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL7_CIC Comparison Interrupt Condition [3:2] ADC_DCCTL7_CIC_LOW Low Band 0x0 ADC_DCCTL7_CIC_MID Mid Band 0x1 ADC_DCCTL7_CIC_HIGH High Band 0x3 ADC_DCCTL7_CIE Comparison Interrupt Enable [4:4] ADC_DCCTL7_CTM Comparison Trigger Mode [9:8] ADC_DCCTL7_CTM_ALWAYS Always 0x0 ADC_DCCTL7_CTM_ONCE Once 0x1 ADC_DCCTL7_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL7_CTM_HONCE Hysteresis Once 0x3 ADC_DCCTL7_CTC Comparison Trigger Condition [11:10] ADC_DCCTL7_CTC_LOW Low Band 0x0 ADC_DCCTL7_CTC_MID Mid Band 0x1 ADC_DCCTL7_CTC_HIGH High Band 0x3 ADC_DCCTL7_CTE Comparison Trigger Enable [12:12] DCCMP0 ADC Digital Comparator Range 0 0x00000E40 ADC_DCCMP0_COMP0 Compare 0 [11:0] ADC_DCCMP0_COMP1 Compare 1 [27:16] DCCMP1 ADC Digital Comparator Range 1 0x00000E44 ADC_DCCMP1_COMP0 Compare 0 [11:0] ADC_DCCMP1_COMP1 Compare 1 [27:16] DCCMP2 ADC Digital Comparator Range 2 0x00000E48 ADC_DCCMP2_COMP0 Compare 0 [11:0] ADC_DCCMP2_COMP1 Compare 1 [27:16] DCCMP3 ADC Digital Comparator Range 3 0x00000E4C ADC_DCCMP3_COMP0 Compare 0 [11:0] ADC_DCCMP3_COMP1 Compare 1 [27:16] DCCMP4 ADC Digital Comparator Range 4 0x00000E50 ADC_DCCMP4_COMP0 Compare 0 [11:0] ADC_DCCMP4_COMP1 Compare 1 [27:16] DCCMP5 ADC Digital Comparator Range 5 0x00000E54 ADC_DCCMP5_COMP0 Compare 0 [11:0] ADC_DCCMP5_COMP1 Compare 1 [27:16] DCCMP6 ADC Digital Comparator Range 6 0x00000E58 ADC_DCCMP6_COMP0 Compare 0 [11:0] ADC_DCCMP6_COMP1 Compare 1 [27:16] DCCMP7 ADC Digital Comparator Range 7 0x00000E5C ADC_DCCMP7_COMP0 Compare 0 [11:0] ADC_DCCMP7_COMP1 Compare 1 [27:16] PP ADC Peripheral Properties 0x00000FC0 ADC_PP_MCR Maximum Conversion Rate [3:0] ADC_PP_MCR_FULL Full conversion rate (FCONV) as defined by TADC and NSH 0x7 ADC_PP_CH ADC Channel Count [9:4] ADC_PP_DC Digital Comparator Count [15:10] ADC_PP_TYPE ADC Architecture [17:16] ADC_PP_TYPE_SAR SAR 0x0 ADC_PP_RSL Resolution [22:18] ADC_PP_TS Temperature Sensor [23:23] ADC_PP_APSHT Application-Programmable Sample-and-Hold Time [24:24] PC ADC Peripheral Configuration 0x00000FC4 ADC_PC_MCR Conversion Rate [3:0] ADC_PC_MCR_1_8 Eighth conversion rate. After a conversion completes, the logic pauses for 112 TADC periods before starting the next conversion 0x1 ADC_PC_MCR_1_4 Quarter conversion rate. After a conversion completes, the logic pauses for 48 TADC periods before starting the next conversion 0x3 ADC_PC_MCR_1_2 Half conversion rate. After a conversion completes, the logic pauses for 16 TADC periods before starting the next conversion 0x5 ADC_PC_MCR_FULL Full conversion rate (FCONV) as defined by TADC and NSH 0x7 CC ADC Clock Configuration 0x00000FC8 ADC_CC_CS ADC Clock Source [3:0] ADC_CC_CS_SYSPLL PLL VCO divided by CLKDIV 0x0 ADC_CC_CS_PIOSC PIOSC 0x1 ADC_CC_CS_MOSC MOSC 0x2 ADC_CC_CLKDIV PLL VCO Clock Divisor [9:4] ADC1 ADC1 0x40039000 ADC1SS046 ADC1SS147 ADC1SS248 ADC1SS349 COMP Register map for COMP peripheral COMP COMP 0x4003C000 0 0x00001000 registers COMP025 COMP126 COMP227 ACMIS Analog Comparator Masked Interrupt Status 0x00000000 COMP_ACMIS_IN0 Comparator 0 Masked Interrupt Status [0:0] COMP_ACMIS_IN1 Comparator 1 Masked Interrupt Status [1:1] COMP_ACMIS_IN2 Comparator 2 Masked Interrupt Status [2:2] ACRIS Analog Comparator Raw Interrupt Status 0x00000004 COMP_ACRIS_IN0 Comparator 0 Interrupt Status [0:0] COMP_ACRIS_IN1 Comparator 1 Interrupt Status [1:1] COMP_ACRIS_IN2 Comparator 2 Interrupt Status [2:2] ACINTEN Analog Comparator Interrupt Enable 0x00000008 COMP_ACINTEN_IN0 Comparator 0 Interrupt Enable [0:0] COMP_ACINTEN_IN1 Comparator 1 Interrupt Enable [1:1] COMP_ACINTEN_IN2 Comparator 2 Interrupt Enable [2:2] ACREFCTL Analog Comparator Reference Voltage Control 0x00000010 COMP_ACREFCTL_VREF Resistor Ladder Voltage Ref [3:0] COMP_ACREFCTL_RNG Resistor Ladder Range [8:8] COMP_ACREFCTL_EN Resistor Ladder Enable [9:9] ACSTAT0 Analog Comparator Status 0 0x00000020 COMP_ACSTAT0_OVAL Comparator Output Value [1:1] ACCTL0 Analog Comparator Control 0 0x00000024 COMP_ACCTL0_CINV Comparator Output Invert [1:1] COMP_ACCTL0_ISEN Interrupt Sense [3:2] COMP_ACCTL0_ISEN_LEVEL Level sense, see ISLVAL 0x0 COMP_ACCTL0_ISEN_FALL Falling edge 0x1 COMP_ACCTL0_ISEN_RISE Rising edge 0x2 COMP_ACCTL0_ISEN_BOTH Either edge 0x3 COMP_ACCTL0_ISLVAL Interrupt Sense Level Value [4:4] COMP_ACCTL0_TSEN Trigger Sense [6:5] COMP_ACCTL0_TSEN_LEVEL Level sense, see TSLVAL 0x0 COMP_ACCTL0_TSEN_FALL Falling edge 0x1 COMP_ACCTL0_TSEN_RISE Rising edge 0x2 COMP_ACCTL0_TSEN_BOTH Either edge 0x3 COMP_ACCTL0_TSLVAL Trigger Sense Level Value [7:7] COMP_ACCTL0_ASRCP Analog Source Positive [10:9] COMP_ACCTL0_ASRCP_PIN Pin value of Cn+ 0x0 COMP_ACCTL0_ASRCP_PIN0 Pin value of C0+ 0x1 COMP_ACCTL0_ASRCP_REF Internal voltage reference 0x2 COMP_ACCTL0_TOEN Trigger Output Enable [11:11] ACSTAT1 Analog Comparator Status 1 0x00000040 COMP_ACSTAT1_OVAL Comparator Output Value [1:1] ACCTL1 Analog Comparator Control 1 0x00000044 COMP_ACCTL1_CINV Comparator Output Invert [1:1] COMP_ACCTL1_ISEN Interrupt Sense [3:2] COMP_ACCTL1_ISEN_LEVEL Level sense, see ISLVAL 0x0 COMP_ACCTL1_ISEN_FALL Falling edge 0x1 COMP_ACCTL1_ISEN_RISE Rising edge 0x2 COMP_ACCTL1_ISEN_BOTH Either edge 0x3 COMP_ACCTL1_ISLVAL Interrupt Sense Level Value [4:4] COMP_ACCTL1_TSEN Trigger Sense [6:5] COMP_ACCTL1_TSEN_LEVEL Level sense, see TSLVAL 0x0 COMP_ACCTL1_TSEN_FALL Falling edge 0x1 COMP_ACCTL1_TSEN_RISE Rising edge 0x2 COMP_ACCTL1_TSEN_BOTH Either edge 0x3 COMP_ACCTL1_TSLVAL Trigger Sense Level Value [7:7] COMP_ACCTL1_ASRCP Analog Source Positive [10:9] COMP_ACCTL1_ASRCP_PIN Pin value of Cn+ 0x0 COMP_ACCTL1_ASRCP_PIN0 Pin value of C0+ 0x1 COMP_ACCTL1_ASRCP_REF Internal voltage reference 0x2 COMP_ACCTL1_TOEN Trigger Output Enable [11:11] ACSTAT2 Analog Comparator Status 2 0x00000060 COMP_ACSTAT2_OVAL Comparator Output Value [1:1] ACCTL2 Analog Comparator Control 2 0x00000064 COMP_ACCTL2_CINV Comparator Output Invert [1:1] COMP_ACCTL2_ISEN Interrupt Sense [3:2] COMP_ACCTL2_ISEN_LEVEL Level sense, see ISLVAL 0x0 COMP_ACCTL2_ISEN_FALL Falling edge 0x1 COMP_ACCTL2_ISEN_RISE Rising edge 0x2 COMP_ACCTL2_ISEN_BOTH Either edge 0x3 COMP_ACCTL2_ISLVAL Interrupt Sense Level Value [4:4] COMP_ACCTL2_TSEN Trigger Sense [6:5] COMP_ACCTL2_TSEN_LEVEL Level sense, see TSLVAL 0x0 COMP_ACCTL2_TSEN_FALL Falling edge 0x1 COMP_ACCTL2_TSEN_RISE Rising edge 0x2 COMP_ACCTL2_TSEN_BOTH Either edge 0x3 COMP_ACCTL2_TSLVAL Trigger Sense Level Value [7:7] COMP_ACCTL2_ASRCP Analog Source Positive [10:9] COMP_ACCTL2_ASRCP_PIN Pin value of Cn+ 0x0 COMP_ACCTL2_ASRCP_PIN0 Pin value of C0+ 0x1 COMP_ACCTL2_ASRCP_REF Internal voltage reference 0x2 COMP_ACCTL2_TOEN Trigger Output Enable [11:11] PP Analog Comparator Peripheral Properties 0x00000FC0 COMP_PP_CMP0 Comparator 0 Present [0:0] COMP_PP_CMP1 Comparator 1 Present [1:1] COMP_PP_CMP2 Comparator 2 Present [2:2] COMP_PP_C0O Comparator Output 0 Present [16:16] COMP_PP_C1O Comparator Output 1 Present [17:17] COMP_PP_C2O Comparator Output 2 Present [18:18] CAN0 Register map for CAN0 peripheral CAN CAN0 0x40040000 0 0x00001000 registers CAN038 CTL CAN Control 0x00000000 CAN_CTL_INIT Initialization [0:0] CAN_CTL_IE CAN Interrupt Enable [1:1] CAN_CTL_SIE Status Interrupt Enable [2:2] CAN_CTL_EIE Error Interrupt Enable [3:3] CAN_CTL_DAR Disable Automatic-Retransmission [5:5] CAN_CTL_CCE Configuration Change Enable [6:6] CAN_CTL_TEST Test Mode Enable [7:7] STS CAN Status 0x00000004 CAN_STS_LEC Last Error Code [2:0] CAN_STS_LEC_NONE No Error 0x0 CAN_STS_LEC_STUFF Stuff Error 0x1 CAN_STS_LEC_FORM Format Error 0x2 CAN_STS_LEC_ACK ACK Error 0x3 CAN_STS_LEC_BIT1 Bit 1 Error 0x4 CAN_STS_LEC_BIT0 Bit 0 Error 0x5 CAN_STS_LEC_CRC CRC Error 0x6 CAN_STS_LEC_NOEVENT No Event 0x7 CAN_STS_TXOK Transmitted a Message Successfully [3:3] CAN_STS_RXOK Received a Message Successfully [4:4] CAN_STS_EPASS Error Passive [5:5] CAN_STS_EWARN Warning Status [6:6] CAN_STS_BOFF Bus-Off Status [7:7] ERR CAN Error Counter 0x00000008 CAN_ERR_TEC Transmit Error Counter [7:0] CAN_ERR_REC Receive Error Counter [14:8] CAN_ERR_RP Received Error Passive [15:15] BIT CAN Bit Timing 0x0000000C CAN_BIT_BRP Baud Rate Prescaler [5:0] CAN_BIT_SJW (Re)Synchronization Jump Width [7:6] CAN_BIT_TSEG1 Time Segment Before Sample Point [11:8] CAN_BIT_TSEG2 Time Segment after Sample Point [14:12] INT CAN Interrupt 0x00000010 CAN_INT_INTID Interrupt Identifier [15:0] TST CAN Test 0x00000014 CAN_TST_BASIC Basic Mode [2:2] CAN_TST_SILENT Silent Mode [3:3] CAN_TST_LBACK Loopback Mode [4:4] CAN_TST_TX Transmit Control [6:5] CAN_TST_TX_CANCTL CAN Module Control 0x0 CAN_TST_TX_SAMPLE Sample Point 0x1 CAN_TST_TX_DOMINANT Driven Low 0x2 CAN_TST_TX_RECESSIVE Driven High 0x3 CAN_TST_RX Receive Observation [7:7] BRPE CAN Baud Rate Prescaler Extension 0x00000018 CAN_BRPE_BRPE Baud Rate Prescaler Extension [3:0] IF1CRQ CAN IF1 Command Request 0x00000020 CAN_IF1CRQ_MNUM Message Number [5:0] CAN_IF1CRQ_BUSY Busy Flag [15:15] IF1CMSK CAN IF1 Command Mask 0x00000024 CAN_IF1CMSK_DATAB Access Data Byte 4 to 7 [0:0] CAN_IF1CMSK_DATAA Access Data Byte 0 to 3 [1:1] CAN_IF1CMSK_NEWDAT Access New Data [2:2] CAN_IF1CMSK_CLRINTPND Clear Interrupt Pending Bit [3:3] CAN_IF1CMSK_CONTROL Access Control Bits [4:4] CAN_IF1CMSK_ARB Access Arbitration Bits [5:5] CAN_IF1CMSK_MASK Access Mask Bits [6:6] CAN_IF1CMSK_WRNRD Write, Not Read [7:7] IF1CMSK CAN IF1 Command Mask CAN0_ALT 0x00000024 CAN_IF1CMSK_TXRQST Access Transmission Request [2:2] IF1MSK1 CAN IF1 Mask 1 0x00000028 CAN_IF1MSK1_IDMSK Identifier Mask [15:0] IF1MSK2 CAN IF1 Mask 2 0x0000002C CAN_IF1MSK2_IDMSK Identifier Mask [12:0] CAN_IF1MSK2_MDIR Mask Message Direction [14:14] CAN_IF1MSK2_MXTD Mask Extended Identifier [15:15] IF1ARB1 CAN IF1 Arbitration 1 0x00000030 CAN_IF1ARB1_ID Message Identifier [15:0] IF1ARB2 CAN IF1 Arbitration 2 0x00000034 CAN_IF1ARB2_ID Message Identifier [12:0] CAN_IF1ARB2_DIR Message Direction [13:13] CAN_IF1ARB2_XTD Extended Identifier [14:14] CAN_IF1ARB2_MSGVAL Message Valid [15:15] IF1MCTL CAN IF1 Message Control 0x00000038 CAN_IF1MCTL_DLC Data Length Code [3:0] CAN_IF1MCTL_EOB End of Buffer [7:7] CAN_IF1MCTL_TXRQST Transmit Request [8:8] CAN_IF1MCTL_RMTEN Remote Enable [9:9] CAN_IF1MCTL_RXIE Receive Interrupt Enable [10:10] CAN_IF1MCTL_TXIE Transmit Interrupt Enable [11:11] CAN_IF1MCTL_UMASK Use Acceptance Mask [12:12] CAN_IF1MCTL_INTPND Interrupt Pending [13:13] CAN_IF1MCTL_MSGLST Message Lost [14:14] CAN_IF1MCTL_NEWDAT New Data [15:15] IF1DA1 CAN IF1 Data A1 0x0000003C CAN_IF1DA1_DATA Data [15:0] IF1DA2 CAN IF1 Data A2 0x00000040 CAN_IF1DA2_DATA Data [15:0] IF1DB1 CAN IF1 Data B1 0x00000044 CAN_IF1DB1_DATA Data [15:0] IF1DB2 CAN IF1 Data B2 0x00000048 CAN_IF1DB2_DATA Data [15:0] IF2CRQ CAN IF2 Command Request 0x00000080 CAN_IF2CRQ_MNUM Message Number [5:0] CAN_IF2CRQ_BUSY Busy Flag [15:15] IF2CMSK CAN IF2 Command Mask 0x00000084 CAN_IF2CMSK_DATAB Access Data Byte 4 to 7 [0:0] CAN_IF2CMSK_DATAA Access Data Byte 0 to 3 [1:1] CAN_IF2CMSK_NEWDAT Access New Data [2:2] CAN_IF2CMSK_CLRINTPND Clear Interrupt Pending Bit [3:3] CAN_IF2CMSK_CONTROL Access Control Bits [4:4] CAN_IF2CMSK_ARB Access Arbitration Bits [5:5] CAN_IF2CMSK_MASK Access Mask Bits [6:6] CAN_IF2CMSK_WRNRD Write, Not Read [7:7] IF2CMSK CAN IF2 Command Mask CAN0_ALT 0x00000084 CAN_IF2CMSK_TXRQST Access Transmission Request [2:2] IF2MSK1 CAN IF2 Mask 1 0x00000088 CAN_IF2MSK1_IDMSK Identifier Mask [15:0] IF2MSK2 CAN IF2 Mask 2 0x0000008C CAN_IF2MSK2_IDMSK Identifier Mask [12:0] CAN_IF2MSK2_MDIR Mask Message Direction [14:14] CAN_IF2MSK2_MXTD Mask Extended Identifier [15:15] IF2ARB1 CAN IF2 Arbitration 1 0x00000090 CAN_IF2ARB1_ID Message Identifier [15:0] IF2ARB2 CAN IF2 Arbitration 2 0x00000094 CAN_IF2ARB2_ID Message Identifier [12:0] CAN_IF2ARB2_DIR Message Direction [13:13] CAN_IF2ARB2_XTD Extended Identifier [14:14] CAN_IF2ARB2_MSGVAL Message Valid [15:15] IF2MCTL CAN IF2 Message Control 0x00000098 CAN_IF2MCTL_DLC Data Length Code [3:0] CAN_IF2MCTL_EOB End of Buffer [7:7] CAN_IF2MCTL_TXRQST Transmit Request [8:8] CAN_IF2MCTL_RMTEN Remote Enable [9:9] CAN_IF2MCTL_RXIE Receive Interrupt Enable [10:10] CAN_IF2MCTL_TXIE Transmit Interrupt Enable [11:11] CAN_IF2MCTL_UMASK Use Acceptance Mask [12:12] CAN_IF2MCTL_INTPND Interrupt Pending [13:13] CAN_IF2MCTL_MSGLST Message Lost [14:14] CAN_IF2MCTL_NEWDAT New Data [15:15] IF2DA1 CAN IF2 Data A1 0x0000009C CAN_IF2DA1_DATA Data [15:0] IF2DA2 CAN IF2 Data A2 0x000000A0 CAN_IF2DA2_DATA Data [15:0] IF2DB1 CAN IF2 Data B1 0x000000A4 CAN_IF2DB1_DATA Data [15:0] IF2DB2 CAN IF2 Data B2 0x000000A8 CAN_IF2DB2_DATA Data [15:0] TXRQ1 CAN Transmission Request 1 0x00000100 CAN_TXRQ1_TXRQST Transmission Request Bits [15:0] TXRQ2 CAN Transmission Request 2 0x00000104 CAN_TXRQ2_TXRQST Transmission Request Bits [15:0] NWDA1 CAN New Data 1 0x00000120 CAN_NWDA1_NEWDAT New Data Bits [15:0] NWDA2 CAN New Data 2 0x00000124 CAN_NWDA2_NEWDAT New Data Bits [15:0] MSG1INT CAN Message 1 Interrupt Pending 0x00000140 CAN_MSG1INT_INTPND Interrupt Pending Bits [15:0] MSG2INT CAN Message 2 Interrupt Pending 0x00000144 CAN_MSG2INT_INTPND Interrupt Pending Bits [15:0] MSG1VAL CAN Message 1 Valid 0x00000160 CAN_MSG1VAL_MSGVAL Message Valid Bits [15:0] MSG2VAL CAN Message 2 Valid 0x00000164 CAN_MSG2VAL_MSGVAL Message Valid Bits [15:0] CAN1 CAN1 0x40041000 CAN139 USB0 Register map for USB0 peripheral USB USB0 0x40050000 0 0x00001000 registers USB042 FADDR USB Device Functional Address 0x00000000 8 USB_FADDR Function Address [6:0] POWER USB Power 0x00000001 8 USB_POWER_PWRDNPHY Power Down PHY [0:0] USB_POWER_SUSPEND SUSPEND Mode [1:1] USB_POWER_RESUME RESUME Signaling [2:2] USB_POWER_RESET RESET Signaling [3:3] USB_POWER_HSMODE High Speed Enable [4:4] USB_POWER_HSENAB High Speed Enable [5:5] USB_POWER_SOFTCONN Soft Connect/Disconnect [6:6] USB_POWER_ISOUP Isochronous Update [7:7] TXIS USB Transmit Interrupt Status 0x00000002 16 USB_TXIS_EP0 TX and RX Endpoint 0 Interrupt [0:0] USB_TXIS_EP1 TX Endpoint 1 Interrupt [1:1] USB_TXIS_EP2 TX Endpoint 2 Interrupt [2:2] USB_TXIS_EP3 TX Endpoint 3 Interrupt [3:3] USB_TXIS_EP4 TX Endpoint 4 Interrupt [4:4] USB_TXIS_EP5 TX Endpoint 5 Interrupt [5:5] USB_TXIS_EP6 TX Endpoint 6 Interrupt [6:6] USB_TXIS_EP7 TX Endpoint 7 Interrupt [7:7] RXIS USB Receive Interrupt Status 0x00000004 16 USB_RXIS_EP1 RX Endpoint 1 Interrupt [1:1] USB_RXIS_EP2 RX Endpoint 2 Interrupt [2:2] USB_RXIS_EP3 RX Endpoint 3 Interrupt [3:3] USB_RXIS_EP4 RX Endpoint 4 Interrupt [4:4] USB_RXIS_EP5 RX Endpoint 5 Interrupt [5:5] USB_RXIS_EP6 RX Endpoint 6 Interrupt [6:6] USB_RXIS_EP7 RX Endpoint 7 Interrupt [7:7] TXIE USB Transmit Interrupt Enable 0x00000006 16 USB_TXIE_EP0 TX and RX Endpoint 0 Interrupt Enable [0:0] USB_TXIE_EP1 TX Endpoint 1 Interrupt Enable [1:1] USB_TXIE_EP2 TX Endpoint 2 Interrupt Enable [2:2] USB_TXIE_EP3 TX Endpoint 3 Interrupt Enable [3:3] USB_TXIE_EP4 TX Endpoint 4 Interrupt Enable [4:4] USB_TXIE_EP5 TX Endpoint 5 Interrupt Enable [5:5] USB_TXIE_EP6 TX Endpoint 6 Interrupt Enable [6:6] USB_TXIE_EP7 TX Endpoint 7 Interrupt Enable [7:7] RXIE USB Receive Interrupt Enable 0x00000008 16 USB_RXIE_EP1 RX Endpoint 1 Interrupt Enable [1:1] USB_RXIE_EP2 RX Endpoint 2 Interrupt Enable [2:2] USB_RXIE_EP3 RX Endpoint 3 Interrupt Enable [3:3] USB_RXIE_EP4 RX Endpoint 4 Interrupt Enable [4:4] USB_RXIE_EP5 RX Endpoint 5 Interrupt Enable [5:5] USB_RXIE_EP6 RX Endpoint 6 Interrupt Enable [6:6] USB_RXIE_EP7 RX Endpoint 7 Interrupt Enable [7:7] IS USB General Interrupt Status 0x0000000A 8 USB_IS_SUSPEND SUSPEND Signaling Detected [0:0] USB_IS_RESUME RESUME Signaling Detected [1:1] USB_IS_BABBLE Babble Detected [2:2] USB_IS_SOF Start of Frame [3:3] USB_IS_CONN Session Connect [4:4] USB_IS_DISCON Session Disconnect (OTG only) [5:5] USB_IS_SESREQ SESSION REQUEST (OTG only) [6:6] USB_IS_VBUSERR VBUS Error (OTG only) [7:7] IS USB General Interrupt Status USB0_ALT 0x0000000A 8 USB_IS_RESET RESET Signaling Detected [2:2] IE USB Interrupt Enable 0x0000000B 8 USB_IE_SUSPND Enable SUSPEND Interrupt [0:0] USB_IE_RESUME Enable RESUME Interrupt [1:1] USB_IE_BABBLE Enable Babble Interrupt [2:2] USB_IE_SOF Enable Start-of-Frame Interrupt [3:3] USB_IE_CONN Enable Connect Interrupt [4:4] USB_IE_DISCON Enable Disconnect Interrupt [5:5] USB_IE_SESREQ Enable Session Request (OTG only) [6:6] USB_IE_VBUSERR Enable VBUS Error Interrupt (OTG only) [7:7] IE USB Interrupt Enable USB0_ALT 0x0000000B 8 USB_IE_RESET Enable RESET Interrupt [2:2] FRAME USB Frame Value 0x0000000C 16 USB_FRAME Frame Number [10:0] EPIDX USB Endpoint Index 0x0000000E 8 USB_EPIDX_EPIDX Endpoint Index [3:0] TEST USB Test Mode 0x0000000F 8 USB_TEST_TESTSE0NAK Test_SE0_NAK Test Mode Enable [0:0] USB_TEST_TESTJ Test_J Mode Enable [1:1] USB_TEST_TESTK Test_K Mode Enable [2:2] USB_TEST_TESTPKT Test Packet Mode Enable [3:3] USB_TEST_FORCEHS Force High-Speed Mode [4:4] USB_TEST_FORCEFS Force Full-Speed Mode [5:5] USB_TEST_FIFOACC FIFO Access [6:6] USB_TEST_FORCEH Force Host Mode [7:7] FIFO0 USB FIFO Endpoint 0 0x00000020 USB_FIFO0_EPDATA Endpoint Data [31:0] FIFO1 USB FIFO Endpoint 1 0x00000024 USB_FIFO1_EPDATA Endpoint Data [31:0] FIFO2 USB FIFO Endpoint 2 0x00000028 USB_FIFO2_EPDATA Endpoint Data [31:0] FIFO3 USB FIFO Endpoint 3 0x0000002C USB_FIFO3_EPDATA Endpoint Data [31:0] FIFO4 USB FIFO Endpoint 4 0x00000030 USB_FIFO4_EPDATA Endpoint Data [31:0] FIFO5 USB FIFO Endpoint 5 0x00000034 USB_FIFO5_EPDATA Endpoint Data [31:0] FIFO6 USB FIFO Endpoint 6 0x00000038 USB_FIFO6_EPDATA Endpoint Data [31:0] FIFO7 USB FIFO Endpoint 7 0x0000003C USB_FIFO7_EPDATA Endpoint Data [31:0] DEVCTL USB Device Control 0x00000060 8 USB_DEVCTL_SESSION Session Start/End (OTG only) [0:0] USB_DEVCTL_HOSTREQ Host Request (OTG only) [1:1] USB_DEVCTL_HOST Host Mode [2:2] USB_DEVCTL_VBUS VBUS Level (OTG only) [4:3] USB_DEVCTL_VBUS_NONE Below SessionEnd 0x0 USB_DEVCTL_VBUS_SEND Above SessionEnd, below AValid 0x1 USB_DEVCTL_VBUS_AVALID Above AValid, below VBUSValid 0x2 USB_DEVCTL_VBUS_VALID Above VBUSValid 0x3 USB_DEVCTL_LSDEV Low-Speed Device Detected [5:5] USB_DEVCTL_FSDEV Full-Speed Device Detected [6:6] USB_DEVCTL_DEV Device Mode (OTG only) [7:7] CCONF USB Common Configuration 0x00000061 8 USB_CCONF_RXEDMA TX Early DMA Enable [0:0] USB_CCONF_TXEDMA TX Early DMA Enable [1:1] TXFIFOSZ USB Transmit Dynamic FIFO Sizing 0x00000062 8 USB_TXFIFOSZ_SIZE Max Packet Size [3:0] USB_TXFIFOSZ_SIZE_8 8 0x0 USB_TXFIFOSZ_SIZE_16 16 0x1 USB_TXFIFOSZ_SIZE_32 32 0x2 USB_TXFIFOSZ_SIZE_64 64 0x3 USB_TXFIFOSZ_SIZE_128 128 0x4 USB_TXFIFOSZ_SIZE_256 256 0x5 USB_TXFIFOSZ_SIZE_512 512 0x6 USB_TXFIFOSZ_SIZE_1024 1024 0x7 USB_TXFIFOSZ_SIZE_2048 2048 0x8 USB_TXFIFOSZ_DPB Double Packet Buffer Support [4:4] RXFIFOSZ USB Receive Dynamic FIFO Sizing 0x00000063 8 USB_RXFIFOSZ_SIZE Max Packet Size [3:0] USB_RXFIFOSZ_SIZE_8 8 0x0 USB_RXFIFOSZ_SIZE_16 16 0x1 USB_RXFIFOSZ_SIZE_32 32 0x2 USB_RXFIFOSZ_SIZE_64 64 0x3 USB_RXFIFOSZ_SIZE_128 128 0x4 USB_RXFIFOSZ_SIZE_256 256 0x5 USB_RXFIFOSZ_SIZE_512 512 0x6 USB_RXFIFOSZ_SIZE_1024 1024 0x7 USB_RXFIFOSZ_SIZE_2048 2048 0x8 USB_RXFIFOSZ_DPB Double Packet Buffer Support [4:4] TXFIFOADD USB Transmit FIFO Start Address 0x00000064 16 USB_TXFIFOADD_ADDR Transmit/Receive Start Address [8:0] RXFIFOADD USB Receive FIFO Start Address 0x00000066 16 USB_RXFIFOADD_ADDR Transmit/Receive Start Address [8:0] ULPIVBUSCTL USB ULPI VBUS Control 0x00000070 8 USB_ULPIVBUSCTL_USEEXTVBUS Use External VBUS [0:0] USB_ULPIVBUSCTL_USEEXTVBUSIND Use External VBUS Indicator [1:1] ULPIREGDATA USB ULPI Register Data 0x00000074 8 USB_ULPIREGDATA_REGDATA Register Data [7:0] ULPIREGADDR USB ULPI Register Address 0x00000075 8 USB_ULPIREGADDR_ADDR Register Address [7:0] ULPIREGCTL USB ULPI Register Control 0x00000076 8 USB_ULPIREGCTL_REGACC Initiate Register Access [0:0] USB_ULPIREGCTL_REGCMPLT Register Access Complete [1:1] USB_ULPIREGCTL_RDWR Read/Write Control [2:2] EPINFO USB Endpoint Information 0x00000078 8 USB_EPINFO_TXEP TX Endpoints [3:0] USB_EPINFO_RXEP RX Endpoints [7:4] RAMINFO USB RAM Information 0x00000079 8 USB_RAMINFO_RAMBITS RAM Address Bus Width [3:0] USB_RAMINFO_DMACHAN DMA Channels [7:4] CONTIM USB Connect Timing 0x0000007A 8 USB_CONTIM_WTID Wait ID [3:0] USB_CONTIM_WTCON Connect Wait [7:4] VPLEN USB OTG VBUS Pulse Timing 0x0000007B 8 USB_VPLEN_VPLEN VBUS Pulse Length [7:0] HSEOF USB High-Speed Last Transaction to End of Frame Timing 0x0000007C 8 USB_HSEOF_HSEOFG HIgh-Speed End-of-Frame Gap [7:0] FSEOF USB Full-Speed Last Transaction to End of Frame Timing 0x0000007D 8 USB_FSEOF_FSEOFG Full-Speed End-of-Frame Gap [7:0] LSEOF USB Low-Speed Last Transaction to End of Frame Timing 0x0000007E 8 USB_LSEOF_LSEOFG Low-Speed End-of-Frame Gap [7:0] TXFUNCADDR0 USB Transmit Functional Address Endpoint 0 0x00000080 8 USB_TXFUNCADDR0_ADDR Device Address [6:0] TXHUBADDR0 USB Transmit Hub Address Endpoint 0 0x00000082 8 USB_TXHUBADDR0_ADDR Hub Address [6:0] TXHUBPORT0 USB Transmit Hub Port Endpoint 0 0x00000083 8 USB_TXHUBPORT0_PORT Hub Port [6:0] TXFUNCADDR1 USB Transmit Functional Address Endpoint 1 0x00000088 8 USB_TXFUNCADDR1_ADDR Device Address [6:0] TXHUBADDR1 USB Transmit Hub Address Endpoint 1 0x0000008A 8 USB_TXHUBADDR1_ADDR Hub Address [6:0] TXHUBPORT1 USB Transmit Hub Port Endpoint 1 0x0000008B 8 USB_TXHUBPORT1_PORT Hub Port [6:0] RXFUNCADDR1 USB Receive Functional Address Endpoint 1 0x0000008C 8 USB_RXFUNCADDR1_ADDR Device Address [6:0] RXHUBADDR1 USB Receive Hub Address Endpoint 1 0x0000008E 8 USB_RXHUBADDR1_ADDR Hub Address [6:0] RXHUBPORT1 USB Receive Hub Port Endpoint 1 0x0000008F 8 USB_RXHUBPORT1_PORT Hub Port [6:0] TXFUNCADDR2 USB Transmit Functional Address Endpoint 2 0x00000090 8 USB_TXFUNCADDR2_ADDR Device Address [6:0] TXHUBADDR2 USB Transmit Hub Address Endpoint 2 0x00000092 8 USB_TXHUBADDR2_ADDR Hub Address [6:0] TXHUBPORT2 USB Transmit Hub Port Endpoint 2 0x00000093 8 USB_TXHUBPORT2_PORT Hub Port [6:0] RXFUNCADDR2 USB Receive Functional Address Endpoint 2 0x00000094 8 USB_RXFUNCADDR2_ADDR Device Address [6:0] RXHUBADDR2 USB Receive Hub Address Endpoint 2 0x00000096 8 USB_RXHUBADDR2_ADDR Hub Address [6:0] RXHUBPORT2 USB Receive Hub Port Endpoint 2 0x00000097 8 USB_RXHUBPORT2_PORT Hub Port [6:0] TXFUNCADDR3 USB Transmit Functional Address Endpoint 3 0x00000098 8 USB_TXFUNCADDR3_ADDR Device Address [6:0] TXHUBADDR3 USB Transmit Hub Address Endpoint 3 0x0000009A 8 USB_TXHUBADDR3_ADDR Hub Address [6:0] TXHUBPORT3 USB Transmit Hub Port Endpoint 3 0x0000009B 8 USB_TXHUBPORT3_PORT Hub Port [6:0] RXFUNCADDR3 USB Receive Functional Address Endpoint 3 0x0000009C 8 USB_RXFUNCADDR3_ADDR Device Address [6:0] RXHUBADDR3 USB Receive Hub Address Endpoint 3 0x0000009E 8 USB_RXHUBADDR3_ADDR Hub Address [6:0] RXHUBPORT3 USB Receive Hub Port Endpoint 3 0x0000009F 8 USB_RXHUBPORT3_PORT Hub Port [6:0] TXFUNCADDR4 USB Transmit Functional Address Endpoint 4 0x000000A0 8 USB_TXFUNCADDR4_ADDR Device Address [6:0] TXHUBADDR4 USB Transmit Hub Address Endpoint 4 0x000000A2 8 USB_TXHUBADDR4_ADDR Hub Address [6:0] TXHUBPORT4 USB Transmit Hub Port Endpoint 4 0x000000A3 8 USB_TXHUBPORT4_PORT Hub Port [6:0] RXFUNCADDR4 USB Receive Functional Address Endpoint 4 0x000000A4 8 USB_RXFUNCADDR4_ADDR Device Address [6:0] RXHUBADDR4 USB Receive Hub Address Endpoint 4 0x000000A6 8 USB_RXHUBADDR4_ADDR Hub Address [6:0] RXHUBPORT4 USB Receive Hub Port Endpoint 4 0x000000A7 8 USB_RXHUBPORT4_PORT Hub Port [6:0] TXFUNCADDR5 USB Transmit Functional Address Endpoint 5 0x000000A8 8 USB_TXFUNCADDR5_ADDR Device Address [6:0] TXHUBADDR5 USB Transmit Hub Address Endpoint 5 0x000000AA 8 USB_TXHUBADDR5_ADDR Hub Address [6:0] TXHUBPORT5 USB Transmit Hub Port Endpoint 5 0x000000AB 8 USB_TXHUBPORT5_PORT Hub Port [6:0] RXFUNCADDR5 USB Receive Functional Address Endpoint 5 0x000000AC 8 USB_RXFUNCADDR5_ADDR Device Address [6:0] RXHUBADDR5 USB Receive Hub Address Endpoint 5 0x000000AE 8 USB_RXHUBADDR5_ADDR Hub Address [6:0] RXHUBPORT5 USB Receive Hub Port Endpoint 5 0x000000AF 8 USB_RXHUBPORT5_PORT Hub Port [6:0] TXFUNCADDR6 USB Transmit Functional Address Endpoint 6 0x000000B0 8 USB_TXFUNCADDR6_ADDR Device Address [6:0] TXHUBADDR6 USB Transmit Hub Address Endpoint 6 0x000000B2 8 USB_TXHUBADDR6_ADDR Hub Address [6:0] TXHUBPORT6 USB Transmit Hub Port Endpoint 6 0x000000B3 8 USB_TXHUBPORT6_PORT Hub Port [6:0] RXFUNCADDR6 USB Receive Functional Address Endpoint 6 0x000000B4 8 USB_RXFUNCADDR6_ADDR Device Address [6:0] RXHUBADDR6 USB Receive Hub Address Endpoint 6 0x000000B6 8 USB_RXHUBADDR6_ADDR Hub Address [6:0] RXHUBPORT6 USB Receive Hub Port Endpoint 6 0x000000B7 8 USB_RXHUBPORT6_PORT Hub Port [6:0] TXFUNCADDR7 USB Transmit Functional Address Endpoint 7 0x000000B8 8 USB_TXFUNCADDR7_ADDR Device Address [6:0] TXHUBADDR7 USB Transmit Hub Address Endpoint 7 0x000000BA 8 USB_TXHUBADDR7_ADDR Hub Address [6:0] TXHUBPORT7 USB Transmit Hub Port Endpoint 7 0x000000BB 8 USB_TXHUBPORT7_PORT Hub Port [6:0] RXFUNCADDR7 USB Receive Functional Address Endpoint 7 0x000000BC 8 USB_RXFUNCADDR7_ADDR Device Address [6:0] RXHUBADDR7 USB Receive Hub Address Endpoint 7 0x000000BE 8 USB_RXHUBADDR7_ADDR Hub Address [6:0] RXHUBPORT7 USB Receive Hub Port Endpoint 7 0x000000BF 8 USB_RXHUBPORT7_PORT Hub Port [6:0] CSRL0 USB Control and Status Endpoint 0 Low 0x00000102 8 write-only USB_CSRL0_RXRDY Receive Packet Ready [0:0] write-only USB_CSRL0_TXRDY Transmit Packet Ready [1:1] write-only USB_CSRL0_STALLED Endpoint Stalled [2:2] write-only USB_CSRL0_DATAEND Data End [3:3] write-only USB_CSRL0_SETEND Setup End [4:4] write-only USB_CSRL0_STALL Send Stall [5:5] write-only USB_CSRL0_RXRDYC RXRDY Clear [6:6] write-only USB_CSRL0_SETENDC Setup End Clear [7:7] write-only CSRL0 USB Control and Status Endpoint 0 Low USB0_ALT 0x00000102 8 write-only USB_CSRL0_SETUP Setup Packet [3:3] write-only USB_CSRL0_ERROR Error [4:4] write-only USB_CSRL0_REQPKT Request Packet [5:5] write-only USB_CSRL0_STATUS STATUS Packet [6:6] write-only USB_CSRL0_NAKTO NAK Timeout [7:7] write-only CSRH0 USB Control and Status Endpoint 0 High 0x00000103 8 write-only USB_CSRH0_FLUSH Flush FIFO [0:0] write-only USB_CSRH0_DT Data Toggle [1:1] write-only USB_CSRH0_DTWE Data Toggle Write Enable [2:2] write-only USB_CSRH0_DISPING PING Disable [3:3] write-only COUNT0 USB Receive Byte Count Endpoint 0 0x00000108 8 USB_COUNT0_COUNT FIFO Count [6:0] TYPE0 USB Type Endpoint 0 0x0000010A 8 USB_TYPE0_SPEED Operating Speed [7:6] USB_TYPE0_SPEED_HIGH High 0x1 USB_TYPE0_SPEED_FULL Full 0x2 USB_TYPE0_SPEED_LOW Low 0x3 NAKLMT USB NAK Limit 0x0000010B 8 USB_NAKLMT_NAKLMT EP0 NAK Limit [4:0] TXMAXP1 USB Maximum Transmit Data Endpoint 1 0x00000110 16 USB_TXMAXP1_MAXLOAD Maximum Payload [10:0] TXCSRL1 USB Transmit Control and Status Endpoint 1 Low 0x00000112 8 USB_TXCSRL1_TXRDY Transmit Packet Ready [0:0] USB_TXCSRL1_FIFONE FIFO Not Empty [1:1] USB_TXCSRL1_ERROR Error [2:2] USB_TXCSRL1_FLUSH Flush FIFO [3:3] USB_TXCSRL1_SETUP Setup Packet [4:4] USB_TXCSRL1_STALLED Endpoint Stalled [5:5] USB_TXCSRL1_CLRDT Clear Data Toggle [6:6] USB_TXCSRL1_NAKTO NAK Timeout [7:7] TXCSRL1 USB Transmit Control and Status Endpoint 1 Low USB0_ALT 0x00000112 8 USB_TXCSRL1_UNDRN Underrun [2:2] USB_TXCSRL1_STALL Send STALL [4:4] TXCSRH1 USB Transmit Control and Status Endpoint 1 High 0x00000113 8 USB_TXCSRH1_DT Data Toggle [0:0] USB_TXCSRH1_DTWE Data Toggle Write Enable [1:1] USB_TXCSRH1_DMAMOD DMA Request Mode [2:2] USB_TXCSRH1_FDT Force Data Toggle [3:3] USB_TXCSRH1_DMAEN DMA Request Enable [4:4] USB_TXCSRH1_MODE Mode [5:5] USB_TXCSRH1_ISO Isochronous Transfers [6:6] USB_TXCSRH1_AUTOSET Auto Set [7:7] RXMAXP1 USB Maximum Receive Data Endpoint 1 0x00000114 16 USB_RXMAXP1_MAXLOAD Maximum Payload [10:0] RXCSRL1 USB Receive Control and Status Endpoint 1 Low 0x00000116 8 USB_RXCSRL1_RXRDY Receive Packet Ready [0:0] USB_RXCSRL1_FULL FIFO Full [1:1] USB_RXCSRL1_OVER Overrun [2:2] USB_RXCSRL1_DATAERR Data Error [3:3] USB_RXCSRL1_FLUSH Flush FIFO [4:4] USB_RXCSRL1_STALL Send STALL [5:5] USB_RXCSRL1_STALLED Endpoint Stalled [6:6] USB_RXCSRL1_CLRDT Clear Data Toggle [7:7] RXCSRL1 USB Receive Control and Status Endpoint 1 Low USB0_ALT 0x00000116 8 USB_RXCSRL1_ERROR Error [2:2] USB_RXCSRL1_NAKTO NAK Timeout [3:3] USB_RXCSRL1_REQPKT Request Packet [5:5] RXCSRH1 USB Receive Control and Status Endpoint 1 High 0x00000117 8 USB_RXCSRH1_INCOMPRX Incomplete RX Transmission Status [0:0] USB_RXCSRH1_DT Data Toggle [1:1] USB_RXCSRH1_DTWE Data Toggle Write Enable [2:2] USB_RXCSRH1_DMAMOD DMA Request Mode [3:3] USB_RXCSRH1_PIDERR PID Error [4:4] USB_RXCSRH1_DMAEN DMA Request Enable [5:5] USB_RXCSRH1_AUTORQ Auto Request [6:6] USB_RXCSRH1_AUTOCL Auto Clear [7:7] RXCSRH1 USB Receive Control and Status Endpoint 1 High USB0_ALT 0x00000117 8 USB_RXCSRH1_DISNYET Disable NYET [4:4] USB_RXCSRH1_ISO Isochronous Transfers [6:6] RXCOUNT1 USB Receive Byte Count Endpoint 1 0x00000118 16 USB_RXCOUNT1_COUNT Receive Packet Count [12:0] TXTYPE1 USB Host Transmit Configure Type Endpoint 1 0x0000011A 8 USB_TXTYPE1_TEP Target Endpoint Number [3:0] USB_TXTYPE1_PROTO Protocol [5:4] USB_TXTYPE1_PROTO_CTRL Control 0x0 USB_TXTYPE1_PROTO_ISOC Isochronous 0x1 USB_TXTYPE1_PROTO_BULK Bulk 0x2 USB_TXTYPE1_PROTO_INT Interrupt 0x3 USB_TXTYPE1_SPEED Operating Speed [7:6] USB_TXTYPE1_SPEED_DFLT Default 0x0 USB_TXTYPE1_SPEED_HIGH High 0x1 USB_TXTYPE1_SPEED_FULL Full 0x2 USB_TXTYPE1_SPEED_LOW Low 0x3 TXINTERVAL1 USB Host Transmit Interval Endpoint 1 0x0000011B 8 USB_TXINTERVAL1_TXPOLL TX Polling [7:0] TXINTERVAL1 USB Host Transmit Interval Endpoint 1 USB0_ALT 0x0000011B 8 USB_TXINTERVAL1_NAKLMT NAK Limit [7:0] RXTYPE1 USB Host Configure Receive Type Endpoint 1 0x0000011C 8 USB_RXTYPE1_TEP Target Endpoint Number [3:0] USB_RXTYPE1_PROTO Protocol [5:4] USB_RXTYPE1_PROTO_CTRL Control 0x0 USB_RXTYPE1_PROTO_ISOC Isochronous 0x1 USB_RXTYPE1_PROTO_BULK Bulk 0x2 USB_RXTYPE1_PROTO_INT Interrupt 0x3 USB_RXTYPE1_SPEED Operating Speed [7:6] USB_RXTYPE1_SPEED_DFLT Default 0x0 USB_RXTYPE1_SPEED_HIGH High 0x1 USB_RXTYPE1_SPEED_FULL Full 0x2 USB_RXTYPE1_SPEED_LOW Low 0x3 RXINTERVAL1 USB Host Receive Polling Interval Endpoint 1 0x0000011D 8 USB_RXINTERVAL1_TXPOLL RX Polling [7:0] RXINTERVAL1 USB Host Receive Polling Interval Endpoint 1 USB0_ALT 0x0000011D 8 USB_RXINTERVAL1_NAKLMT NAK Limit [7:0] TXMAXP2 USB Maximum Transmit Data Endpoint 2 0x00000120 16 USB_TXMAXP2_MAXLOAD Maximum Payload [10:0] TXCSRL2 USB Transmit Control and Status Endpoint 2 Low 0x00000122 8 USB_TXCSRL2_TXRDY Transmit Packet Ready [0:0] USB_TXCSRL2_FIFONE FIFO Not Empty [1:1] USB_TXCSRL2_ERROR Error [2:2] USB_TXCSRL2_FLUSH Flush FIFO [3:3] USB_TXCSRL2_SETUP Setup Packet [4:4] USB_TXCSRL2_STALLED Endpoint Stalled [5:5] USB_TXCSRL2_CLRDT Clear Data Toggle [6:6] USB_TXCSRL2_NAKTO NAK Timeout [7:7] TXCSRL2 USB Transmit Control and Status Endpoint 2 Low USB0_ALT 0x00000122 8 USB_TXCSRL2_UNDRN Underrun [2:2] USB_TXCSRL2_STALL Send STALL [4:4] TXCSRH2 USB Transmit Control and Status Endpoint 2 High 0x00000123 8 USB_TXCSRH2_DT Data Toggle [0:0] USB_TXCSRH2_DTWE Data Toggle Write Enable [1:1] USB_TXCSRH2_DMAMOD DMA Request Mode [2:2] USB_TXCSRH2_FDT Force Data Toggle [3:3] USB_TXCSRH2_DMAEN DMA Request Enable [4:4] USB_TXCSRH2_MODE Mode [5:5] USB_TXCSRH2_ISO Isochronous Transfers [6:6] USB_TXCSRH2_AUTOSET Auto Set [7:7] RXMAXP2 USB Maximum Receive Data Endpoint 2 0x00000124 16 USB_RXMAXP2_MAXLOAD Maximum Payload [10:0] RXCSRL2 USB Receive Control and Status Endpoint 2 Low 0x00000126 8 USB_RXCSRL2_RXRDY Receive Packet Ready [0:0] USB_RXCSRL2_FULL FIFO Full [1:1] USB_RXCSRL2_OVER Overrun [2:2] USB_RXCSRL2_DATAERR Data Error [3:3] USB_RXCSRL2_FLUSH Flush FIFO [4:4] USB_RXCSRL2_STALL Send STALL [5:5] USB_RXCSRL2_STALLED Endpoint Stalled [6:6] USB_RXCSRL2_CLRDT Clear Data Toggle [7:7] RXCSRL2 USB Receive Control and Status Endpoint 2 Low USB0_ALT 0x00000126 8 USB_RXCSRL2_ERROR Error [2:2] USB_RXCSRL2_NAKTO NAK Timeout [3:3] USB_RXCSRL2_REQPKT Request Packet [5:5] RXCSRH2 USB Receive Control and Status Endpoint 2 High 0x00000127 8 USB_RXCSRH2_INCOMPRX Incomplete RX Transmission Status [0:0] USB_RXCSRH2_DT Data Toggle [1:1] USB_RXCSRH2_DTWE Data Toggle Write Enable [2:2] USB_RXCSRH2_DMAMOD DMA Request Mode [3:3] USB_RXCSRH2_PIDERR PID Error [4:4] USB_RXCSRH2_DMAEN DMA Request Enable [5:5] USB_RXCSRH2_AUTORQ Auto Request [6:6] USB_RXCSRH2_AUTOCL Auto Clear [7:7] RXCSRH2 USB Receive Control and Status Endpoint 2 High USB0_ALT 0x00000127 8 USB_RXCSRH2_DISNYET Disable NYET [4:4] USB_RXCSRH2_ISO Isochronous Transfers [6:6] RXCOUNT2 USB Receive Byte Count Endpoint 2 0x00000128 16 USB_RXCOUNT2_COUNT Receive Packet Count [12:0] TXTYPE2 USB Host Transmit Configure Type Endpoint 2 0x0000012A 8 USB_TXTYPE2_TEP Target Endpoint Number [3:0] USB_TXTYPE2_PROTO Protocol [5:4] USB_TXTYPE2_PROTO_CTRL Control 0x0 USB_TXTYPE2_PROTO_ISOC Isochronous 0x1 USB_TXTYPE2_PROTO_BULK Bulk 0x2 USB_TXTYPE2_PROTO_INT Interrupt 0x3 USB_TXTYPE2_SPEED Operating Speed [7:6] USB_TXTYPE2_SPEED_DFLT Default 0x0 USB_TXTYPE2_SPEED_HIGH High 0x1 USB_TXTYPE2_SPEED_FULL Full 0x2 USB_TXTYPE2_SPEED_LOW Low 0x3 TXINTERVAL2 USB Host Transmit Interval Endpoint 2 0x0000012B 8 USB_TXINTERVAL2_TXPOLL TX Polling [7:0] TXINTERVAL2 USB Host Transmit Interval Endpoint 2 USB0_ALT 0x0000012B 8 USB_TXINTERVAL2_NAKLMT NAK Limit [7:0] RXTYPE2 USB Host Configure Receive Type Endpoint 2 0x0000012C 8 USB_RXTYPE2_TEP Target Endpoint Number [3:0] USB_RXTYPE2_PROTO Protocol [5:4] USB_RXTYPE2_PROTO_CTRL Control 0x0 USB_RXTYPE2_PROTO_ISOC Isochronous 0x1 USB_RXTYPE2_PROTO_BULK Bulk 0x2 USB_RXTYPE2_PROTO_INT Interrupt 0x3 USB_RXTYPE2_SPEED Operating Speed [7:6] USB_RXTYPE2_SPEED_DFLT Default 0x0 USB_RXTYPE2_SPEED_HIGH High 0x1 USB_RXTYPE2_SPEED_FULL Full 0x2 USB_RXTYPE2_SPEED_LOW Low 0x3 RXINTERVAL2 USB Host Receive Polling Interval Endpoint 2 0x0000012D 8 USB_RXINTERVAL2_TXPOLL RX Polling [7:0] RXINTERVAL2 USB Host Receive Polling Interval Endpoint 2 USB0_ALT 0x0000012D 8 USB_RXINTERVAL2_NAKLMT NAK Limit [7:0] TXMAXP3 USB Maximum Transmit Data Endpoint 3 0x00000130 16 USB_TXMAXP3_MAXLOAD Maximum Payload [10:0] TXCSRL3 USB Transmit Control and Status Endpoint 3 Low 0x00000132 8 USB_TXCSRL3_TXRDY Transmit Packet Ready [0:0] USB_TXCSRL3_FIFONE FIFO Not Empty [1:1] USB_TXCSRL3_ERROR Error [2:2] USB_TXCSRL3_FLUSH Flush FIFO [3:3] USB_TXCSRL3_SETUP Setup Packet [4:4] USB_TXCSRL3_STALLED Endpoint Stalled [5:5] USB_TXCSRL3_CLRDT Clear Data Toggle [6:6] USB_TXCSRL3_NAKTO NAK Timeout [7:7] TXCSRL3 USB Transmit Control and Status Endpoint 3 Low USB0_ALT 0x00000132 8 USB_TXCSRL3_UNDRN Underrun [2:2] USB_TXCSRL3_STALL Send STALL [4:4] TXCSRH3 USB Transmit Control and Status Endpoint 3 High 0x00000133 8 USB_TXCSRH3_DT Data Toggle [0:0] USB_TXCSRH3_DTWE Data Toggle Write Enable [1:1] USB_TXCSRH3_DMAMOD DMA Request Mode [2:2] USB_TXCSRH3_FDT Force Data Toggle [3:3] USB_TXCSRH3_DMAEN DMA Request Enable [4:4] USB_TXCSRH3_MODE Mode [5:5] USB_TXCSRH3_ISO Isochronous Transfers [6:6] USB_TXCSRH3_AUTOSET Auto Set [7:7] RXMAXP3 USB Maximum Receive Data Endpoint 3 0x00000134 16 USB_RXMAXP3_MAXLOAD Maximum Payload [10:0] RXCSRL3 USB Receive Control and Status Endpoint 3 Low 0x00000136 8 USB_RXCSRL3_RXRDY Receive Packet Ready [0:0] USB_RXCSRL3_FULL FIFO Full [1:1] USB_RXCSRL3_OVER Overrun [2:2] USB_RXCSRL3_DATAERR Data Error [3:3] USB_RXCSRL3_FLUSH Flush FIFO [4:4] USB_RXCSRL3_STALL Send STALL [5:5] USB_RXCSRL3_STALLED Endpoint Stalled [6:6] USB_RXCSRL3_CLRDT Clear Data Toggle [7:7] RXCSRL3 USB Receive Control and Status Endpoint 3 Low USB0_ALT 0x00000136 8 USB_RXCSRL3_ERROR Error [2:2] USB_RXCSRL3_NAKTO NAK Timeout [3:3] USB_RXCSRL3_REQPKT Request Packet [5:5] RXCSRH3 USB Receive Control and Status Endpoint 3 High 0x00000137 8 USB_RXCSRH3_INCOMPRX Incomplete RX Transmission Status [0:0] USB_RXCSRH3_DT Data Toggle [1:1] USB_RXCSRH3_DTWE Data Toggle Write Enable [2:2] USB_RXCSRH3_DMAMOD DMA Request Mode [3:3] USB_RXCSRH3_PIDERR PID Error [4:4] USB_RXCSRH3_DMAEN DMA Request Enable [5:5] USB_RXCSRH3_AUTORQ Auto Request [6:6] USB_RXCSRH3_AUTOCL Auto Clear [7:7] RXCSRH3 USB Receive Control and Status Endpoint 3 High USB0_ALT 0x00000137 8 USB_RXCSRH3_DISNYET Disable NYET [4:4] USB_RXCSRH3_ISO Isochronous Transfers [6:6] RXCOUNT3 USB Receive Byte Count Endpoint 3 0x00000138 16 USB_RXCOUNT3_COUNT Receive Packet Count [12:0] TXTYPE3 USB Host Transmit Configure Type Endpoint 3 0x0000013A 8 USB_TXTYPE3_TEP Target Endpoint Number [3:0] USB_TXTYPE3_PROTO Protocol [5:4] USB_TXTYPE3_PROTO_CTRL Control 0x0 USB_TXTYPE3_PROTO_ISOC Isochronous 0x1 USB_TXTYPE3_PROTO_BULK Bulk 0x2 USB_TXTYPE3_PROTO_INT Interrupt 0x3 USB_TXTYPE3_SPEED Operating Speed [7:6] USB_TXTYPE3_SPEED_DFLT Default 0x0 USB_TXTYPE3_SPEED_HIGH High 0x1 USB_TXTYPE3_SPEED_FULL Full 0x2 USB_TXTYPE3_SPEED_LOW Low 0x3 TXINTERVAL3 USB Host Transmit Interval Endpoint 3 0x0000013B 8 USB_TXINTERVAL3_TXPOLL TX Polling [7:0] TXINTERVAL3 USB Host Transmit Interval Endpoint 3 USB0_ALT 0x0000013B 8 USB_TXINTERVAL3_NAKLMT NAK Limit [7:0] RXTYPE3 USB Host Configure Receive Type Endpoint 3 0x0000013C 8 USB_RXTYPE3_TEP Target Endpoint Number [3:0] USB_RXTYPE3_PROTO Protocol [5:4] USB_RXTYPE3_PROTO_CTRL Control 0x0 USB_RXTYPE3_PROTO_ISOC Isochronous 0x1 USB_RXTYPE3_PROTO_BULK Bulk 0x2 USB_RXTYPE3_PROTO_INT Interrupt 0x3 USB_RXTYPE3_SPEED Operating Speed [7:6] USB_RXTYPE3_SPEED_DFLT Default 0x0 USB_RXTYPE3_SPEED_HIGH High 0x1 USB_RXTYPE3_SPEED_FULL Full 0x2 USB_RXTYPE3_SPEED_LOW Low 0x3 RXINTERVAL3 USB Host Receive Polling Interval Endpoint 3 0x0000013D 8 USB_RXINTERVAL3_TXPOLL RX Polling [7:0] RXINTERVAL3 USB Host Receive Polling Interval Endpoint 3 USB0_ALT 0x0000013D 8 USB_RXINTERVAL3_NAKLMT NAK Limit [7:0] TXMAXP4 USB Maximum Transmit Data Endpoint 4 0x00000140 16 USB_TXMAXP4_MAXLOAD Maximum Payload [10:0] TXCSRL4 USB Transmit Control and Status Endpoint 4 Low 0x00000142 8 USB_TXCSRL4_TXRDY Transmit Packet Ready [0:0] USB_TXCSRL4_FIFONE FIFO Not Empty [1:1] USB_TXCSRL4_ERROR Error [2:2] USB_TXCSRL4_FLUSH Flush FIFO [3:3] USB_TXCSRL4_SETUP Setup Packet [4:4] USB_TXCSRL4_STALLED Endpoint Stalled [5:5] USB_TXCSRL4_CLRDT Clear Data Toggle [6:6] USB_TXCSRL4_NAKTO NAK Timeout [7:7] TXCSRL4 USB Transmit Control and Status Endpoint 4 Low USB0_ALT 0x00000142 8 USB_TXCSRL4_UNDRN Underrun [2:2] USB_TXCSRL4_STALL Send STALL [4:4] TXCSRH4 USB Transmit Control and Status Endpoint 4 High 0x00000143 8 USB_TXCSRH4_DT Data Toggle [0:0] USB_TXCSRH4_DTWE Data Toggle Write Enable [1:1] USB_TXCSRH4_DMAMOD DMA Request Mode [2:2] USB_TXCSRH4_FDT Force Data Toggle [3:3] USB_TXCSRH4_DMAEN DMA Request Enable [4:4] USB_TXCSRH4_MODE Mode [5:5] USB_TXCSRH4_ISO Isochronous Transfers [6:6] USB_TXCSRH4_AUTOSET Auto Set [7:7] RXMAXP4 USB Maximum Receive Data Endpoint 4 0x00000144 16 USB_RXMAXP4_MAXLOAD Maximum Payload [10:0] RXCSRL4 USB Receive Control and Status Endpoint 4 Low 0x00000146 8 USB_RXCSRL4_RXRDY Receive Packet Ready [0:0] USB_RXCSRL4_FULL FIFO Full [1:1] USB_RXCSRL4_OVER Overrun [2:2] USB_RXCSRL4_DATAERR Data Error [3:3] USB_RXCSRL4_FLUSH Flush FIFO [4:4] USB_RXCSRL4_STALL Send STALL [5:5] USB_RXCSRL4_STALLED Endpoint Stalled [6:6] USB_RXCSRL4_CLRDT Clear Data Toggle [7:7] RXCSRL4 USB Receive Control and Status Endpoint 4 Low USB0_ALT 0x00000146 8 USB_RXCSRL4_ERROR Error [2:2] USB_RXCSRL4_NAKTO NAK Timeout [3:3] USB_RXCSRL4_REQPKT Request Packet [5:5] RXCSRH4 USB Receive Control and Status Endpoint 4 High 0x00000147 8 USB_RXCSRH4_INCOMPRX Incomplete RX Transmission Status [0:0] USB_RXCSRH4_DT Data Toggle [1:1] USB_RXCSRH4_DTWE Data Toggle Write Enable [2:2] USB_RXCSRH4_DMAMOD DMA Request Mode [3:3] USB_RXCSRH4_PIDERR PID Error [4:4] USB_RXCSRH4_DMAEN DMA Request Enable [5:5] USB_RXCSRH4_AUTORQ Auto Request [6:6] USB_RXCSRH4_AUTOCL Auto Clear [7:7] RXCSRH4 USB Receive Control and Status Endpoint 4 High USB0_ALT 0x00000147 8 USB_RXCSRH4_DISNYET Disable NYET [4:4] USB_RXCSRH4_ISO Isochronous Transfers [6:6] RXCOUNT4 USB Receive Byte Count Endpoint 4 0x00000148 16 USB_RXCOUNT4_COUNT Receive Packet Count [12:0] TXTYPE4 USB Host Transmit Configure Type Endpoint 4 0x0000014A 8 USB_TXTYPE4_TEP Target Endpoint Number [3:0] USB_TXTYPE4_PROTO Protocol [5:4] USB_TXTYPE4_PROTO_CTRL Control 0x0 USB_TXTYPE4_PROTO_ISOC Isochronous 0x1 USB_TXTYPE4_PROTO_BULK Bulk 0x2 USB_TXTYPE4_PROTO_INT Interrupt 0x3 USB_TXTYPE4_SPEED Operating Speed [7:6] USB_TXTYPE4_SPEED_DFLT Default 0x0 USB_TXTYPE4_SPEED_HIGH High 0x1 USB_TXTYPE4_SPEED_FULL Full 0x2 USB_TXTYPE4_SPEED_LOW Low 0x3 TXINTERVAL4 USB Host Transmit Interval Endpoint 4 0x0000014B 8 USB_TXINTERVAL4_TXPOLL TX Polling [7:0] TXINTERVAL4 USB Host Transmit Interval Endpoint 4 USB0_ALT 0x0000014B 8 USB_TXINTERVAL4_NAKLMT NAK Limit [7:0] RXTYPE4 USB Host Configure Receive Type Endpoint 4 0x0000014C 8 USB_RXTYPE4_TEP Target Endpoint Number [3:0] USB_RXTYPE4_PROTO Protocol [5:4] USB_RXTYPE4_PROTO_CTRL Control 0x0 USB_RXTYPE4_PROTO_ISOC Isochronous 0x1 USB_RXTYPE4_PROTO_BULK Bulk 0x2 USB_RXTYPE4_PROTO_INT Interrupt 0x3 USB_RXTYPE4_SPEED Operating Speed [7:6] USB_RXTYPE4_SPEED_DFLT Default 0x0 USB_RXTYPE4_SPEED_HIGH High 0x1 USB_RXTYPE4_SPEED_FULL Full 0x2 USB_RXTYPE4_SPEED_LOW Low 0x3 RXINTERVAL4 USB Host Receive Polling Interval Endpoint 4 0x0000014D 8 USB_RXINTERVAL4_TXPOLL RX Polling [7:0] RXINTERVAL4 USB Host Receive Polling Interval Endpoint 4 USB0_ALT 0x0000014D 8 USB_RXINTERVAL4_NAKLMT NAK Limit [7:0] TXMAXP5 USB Maximum Transmit Data Endpoint 5 0x00000150 16 USB_TXMAXP5_MAXLOAD Maximum Payload [10:0] TXCSRL5 USB Transmit Control and Status Endpoint 5 Low 0x00000152 8 USB_TXCSRL5_TXRDY Transmit Packet Ready [0:0] USB_TXCSRL5_FIFONE FIFO Not Empty [1:1] USB_TXCSRL5_ERROR Error [2:2] USB_TXCSRL5_FLUSH Flush FIFO [3:3] USB_TXCSRL5_SETUP Setup Packet [4:4] USB_TXCSRL5_STALLED Endpoint Stalled [5:5] USB_TXCSRL5_CLRDT Clear Data Toggle [6:6] USB_TXCSRL5_NAKTO NAK Timeout [7:7] TXCSRL5 USB Transmit Control and Status Endpoint 5 Low USB0_ALT 0x00000152 8 USB_TXCSRL5_UNDRN Underrun [2:2] USB_TXCSRL5_STALL Send STALL [4:4] TXCSRH5 USB Transmit Control and Status Endpoint 5 High 0x00000153 8 USB_TXCSRH5_DT Data Toggle [0:0] USB_TXCSRH5_DTWE Data Toggle Write Enable [1:1] USB_TXCSRH5_DMAMOD DMA Request Mode [2:2] USB_TXCSRH5_FDT Force Data Toggle [3:3] USB_TXCSRH5_DMAEN DMA Request Enable [4:4] USB_TXCSRH5_MODE Mode [5:5] USB_TXCSRH5_ISO Isochronous Transfers [6:6] USB_TXCSRH5_AUTOSET Auto Set [7:7] RXMAXP5 USB Maximum Receive Data Endpoint 5 0x00000154 16 USB_RXMAXP5_MAXLOAD Maximum Payload [10:0] RXCSRL5 USB Receive Control and Status Endpoint 5 Low 0x00000156 8 USB_RXCSRL5_RXRDY Receive Packet Ready [0:0] USB_RXCSRL5_FULL FIFO Full [1:1] USB_RXCSRL5_OVER Overrun [2:2] USB_RXCSRL5_DATAERR Data Error [3:3] USB_RXCSRL5_FLUSH Flush FIFO [4:4] USB_RXCSRL5_STALL Send STALL [5:5] USB_RXCSRL5_STALLED Endpoint Stalled [6:6] USB_RXCSRL5_CLRDT Clear Data Toggle [7:7] RXCSRL5 USB Receive Control and Status Endpoint 5 Low USB0_ALT 0x00000156 8 USB_RXCSRL5_ERROR Error [2:2] USB_RXCSRL5_NAKTO NAK Timeout [3:3] USB_RXCSRL5_REQPKT Request Packet [5:5] RXCSRH5 USB Receive Control and Status Endpoint 5 High 0x00000157 8 USB_RXCSRH5_INCOMPRX Incomplete RX Transmission Status [0:0] USB_RXCSRH5_DT Data Toggle [1:1] USB_RXCSRH5_DTWE Data Toggle Write Enable [2:2] USB_RXCSRH5_DMAMOD DMA Request Mode [3:3] USB_RXCSRH5_PIDERR PID Error [4:4] USB_RXCSRH5_DMAEN DMA Request Enable [5:5] USB_RXCSRH5_AUTORQ Auto Request [6:6] USB_RXCSRH5_AUTOCL Auto Clear [7:7] RXCSRH5 USB Receive Control and Status Endpoint 5 High USB0_ALT 0x00000157 8 USB_RXCSRH5_DISNYET Disable NYET [4:4] USB_RXCSRH5_ISO Isochronous Transfers [6:6] RXCOUNT5 USB Receive Byte Count Endpoint 5 0x00000158 16 USB_RXCOUNT5_COUNT Receive Packet Count [12:0] TXTYPE5 USB Host Transmit Configure Type Endpoint 5 0x0000015A 8 USB_TXTYPE5_TEP Target Endpoint Number [3:0] USB_TXTYPE5_PROTO Protocol [5:4] USB_TXTYPE5_PROTO_CTRL Control 0x0 USB_TXTYPE5_PROTO_ISOC Isochronous 0x1 USB_TXTYPE5_PROTO_BULK Bulk 0x2 USB_TXTYPE5_PROTO_INT Interrupt 0x3 USB_TXTYPE5_SPEED Operating Speed [7:6] USB_TXTYPE5_SPEED_DFLT Default 0x0 USB_TXTYPE5_SPEED_HIGH High 0x1 USB_TXTYPE5_SPEED_FULL Full 0x2 USB_TXTYPE5_SPEED_LOW Low 0x3 TXINTERVAL5 USB Host Transmit Interval Endpoint 5 0x0000015B 8 USB_TXINTERVAL5_TXPOLL TX Polling [7:0] TXINTERVAL5 USB Host Transmit Interval Endpoint 5 USB0_ALT 0x0000015B 8 USB_TXINTERVAL5_NAKLMT NAK Limit [7:0] RXTYPE5 USB Host Configure Receive Type Endpoint 5 0x0000015C 8 USB_RXTYPE5_TEP Target Endpoint Number [3:0] USB_RXTYPE5_PROTO Protocol [5:4] USB_RXTYPE5_PROTO_CTRL Control 0x0 USB_RXTYPE5_PROTO_ISOC Isochronous 0x1 USB_RXTYPE5_PROTO_BULK Bulk 0x2 USB_RXTYPE5_PROTO_INT Interrupt 0x3 USB_RXTYPE5_SPEED Operating Speed [7:6] USB_RXTYPE5_SPEED_DFLT Default 0x0 USB_RXTYPE5_SPEED_HIGH High 0x1 USB_RXTYPE5_SPEED_FULL Full 0x2 USB_RXTYPE5_SPEED_LOW Low 0x3 RXINTERVAL5 USB Host Receive Polling Interval Endpoint 5 0x0000015D 8 USB_RXINTERVAL5_TXPOLL RX Polling [7:0] RXINTERVAL5 USB Host Receive Polling Interval Endpoint 5 USB0_ALT 0x0000015D 8 USB_RXINTERVAL5_NAKLMT NAK Limit [7:0] TXMAXP6 USB Maximum Transmit Data Endpoint 6 0x00000160 16 USB_TXMAXP6_MAXLOAD Maximum Payload [10:0] TXCSRL6 USB Transmit Control and Status Endpoint 6 Low 0x00000162 8 USB_TXCSRL6_TXRDY Transmit Packet Ready [0:0] USB_TXCSRL6_FIFONE FIFO Not Empty [1:1] USB_TXCSRL6_ERROR Error [2:2] USB_TXCSRL6_FLUSH Flush FIFO [3:3] USB_TXCSRL6_SETUP Setup Packet [4:4] USB_TXCSRL6_STALLED Endpoint Stalled [5:5] USB_TXCSRL6_CLRDT Clear Data Toggle [6:6] USB_TXCSRL6_NAKTO NAK Timeout [7:7] TXCSRL6 USB Transmit Control and Status Endpoint 6 Low USB0_ALT 0x00000162 8 USB_TXCSRL6_UNDRN Underrun [2:2] USB_TXCSRL6_STALL Send STALL [4:4] TXCSRH6 USB Transmit Control and Status Endpoint 6 High 0x00000163 8 USB_TXCSRH6_DT Data Toggle [0:0] USB_TXCSRH6_DTWE Data Toggle Write Enable [1:1] USB_TXCSRH6_DMAMOD DMA Request Mode [2:2] USB_TXCSRH6_FDT Force Data Toggle [3:3] USB_TXCSRH6_DMAEN DMA Request Enable [4:4] USB_TXCSRH6_MODE Mode [5:5] USB_TXCSRH6_ISO Isochronous Transfers [6:6] USB_TXCSRH6_AUTOSET Auto Set [7:7] RXMAXP6 USB Maximum Receive Data Endpoint 6 0x00000164 16 USB_RXMAXP6_MAXLOAD Maximum Payload [10:0] RXCSRL6 USB Receive Control and Status Endpoint 6 Low 0x00000166 8 USB_RXCSRL6_RXRDY Receive Packet Ready [0:0] USB_RXCSRL6_FULL FIFO Full [1:1] USB_RXCSRL6_OVER Overrun [2:2] USB_RXCSRL6_DATAERR Data Error [3:3] USB_RXCSRL6_FLUSH Flush FIFO [4:4] USB_RXCSRL6_STALL Send STALL [5:5] USB_RXCSRL6_STALLED Endpoint Stalled [6:6] USB_RXCSRL6_CLRDT Clear Data Toggle [7:7] RXCSRL6 USB Receive Control and Status Endpoint 6 Low USB0_ALT 0x00000166 8 USB_RXCSRL6_ERROR Error [2:2] USB_RXCSRL6_NAKTO NAK Timeout [3:3] USB_RXCSRL6_REQPKT Request Packet [5:5] RXCSRH6 USB Receive Control and Status Endpoint 6 High 0x00000167 8 USB_RXCSRH6_INCOMPRX Incomplete RX Transmission Status [0:0] USB_RXCSRH6_DT Data Toggle [1:1] USB_RXCSRH6_DTWE Data Toggle Write Enable [2:2] USB_RXCSRH6_DMAMOD DMA Request Mode [3:3] USB_RXCSRH6_PIDERR PID Error [4:4] USB_RXCSRH6_DMAEN DMA Request Enable [5:5] USB_RXCSRH6_AUTORQ Auto Request [6:6] USB_RXCSRH6_AUTOCL Auto Clear [7:7] RXCSRH6 USB Receive Control and Status Endpoint 6 High USB0_ALT 0x00000167 8 USB_RXCSRH6_DISNYET Disable NYET [4:4] USB_RXCSRH6_ISO Isochronous Transfers [6:6] RXCOUNT6 USB Receive Byte Count Endpoint 6 0x00000168 16 USB_RXCOUNT6_COUNT Receive Packet Count [12:0] TXTYPE6 USB Host Transmit Configure Type Endpoint 6 0x0000016A 8 USB_TXTYPE6_TEP Target Endpoint Number [3:0] USB_TXTYPE6_PROTO Protocol [5:4] USB_TXTYPE6_PROTO_CTRL Control 0x0 USB_TXTYPE6_PROTO_ISOC Isochronous 0x1 USB_TXTYPE6_PROTO_BULK Bulk 0x2 USB_TXTYPE6_PROTO_INT Interrupt 0x3 USB_TXTYPE6_SPEED Operating Speed [7:6] USB_TXTYPE6_SPEED_DFLT Default 0x0 USB_TXTYPE6_SPEED_HIGH High 0x1 USB_TXTYPE6_SPEED_FULL Full 0x2 USB_TXTYPE6_SPEED_LOW Low 0x3 TXINTERVAL6 USB Host Transmit Interval Endpoint 6 0x0000016B 8 USB_TXINTERVAL6_TXPOLL TX Polling [7:0] TXINTERVAL6 USB Host Transmit Interval Endpoint 6 USB0_ALT 0x0000016B 8 USB_TXINTERVAL6_NAKLMT NAK Limit [7:0] RXTYPE6 USB Host Configure Receive Type Endpoint 6 0x0000016C 8 USB_RXTYPE6_TEP Target Endpoint Number [3:0] USB_RXTYPE6_PROTO Protocol [5:4] USB_RXTYPE6_PROTO_CTRL Control 0x0 USB_RXTYPE6_PROTO_ISOC Isochronous 0x1 USB_RXTYPE6_PROTO_BULK Bulk 0x2 USB_RXTYPE6_PROTO_INT Interrupt 0x3 USB_RXTYPE6_SPEED Operating Speed [7:6] USB_RXTYPE6_SPEED_DFLT Default 0x0 USB_RXTYPE6_SPEED_HIGH High 0x1 USB_RXTYPE6_SPEED_FULL Full 0x2 USB_RXTYPE6_SPEED_LOW Low 0x3 RXINTERVAL6 USB Host Receive Polling Interval Endpoint 6 0x0000016D 8 USB_RXINTERVAL6_TXPOLL RX Polling [7:0] RXINTERVAL6 USB Host Receive Polling Interval Endpoint 6 USB0_ALT 0x0000016D 8 USB_RXINTERVAL6_NAKLMT NAK Limit [7:0] TXMAXP7 USB Maximum Transmit Data Endpoint 7 0x00000170 16 USB_TXMAXP7_MAXLOAD Maximum Payload [10:0] TXCSRL7 USB Transmit Control and Status Endpoint 7 Low 0x00000172 8 USB_TXCSRL7_TXRDY Transmit Packet Ready [0:0] USB_TXCSRL7_FIFONE FIFO Not Empty [1:1] USB_TXCSRL7_ERROR Error [2:2] USB_TXCSRL7_FLUSH Flush FIFO [3:3] USB_TXCSRL7_SETUP Setup Packet [4:4] USB_TXCSRL7_STALLED Endpoint Stalled [5:5] USB_TXCSRL7_CLRDT Clear Data Toggle [6:6] USB_TXCSRL7_NAKTO NAK Timeout [7:7] TXCSRL7 USB Transmit Control and Status Endpoint 7 Low USB0_ALT 0x00000172 8 USB_TXCSRL7_UNDRN Underrun [2:2] USB_TXCSRL7_STALL Send STALL [4:4] TXCSRH7 USB Transmit Control and Status Endpoint 7 High 0x00000173 8 USB_TXCSRH7_DT Data Toggle [0:0] USB_TXCSRH7_DTWE Data Toggle Write Enable [1:1] USB_TXCSRH7_DMAMOD DMA Request Mode [2:2] USB_TXCSRH7_FDT Force Data Toggle [3:3] USB_TXCSRH7_DMAEN DMA Request Enable [4:4] USB_TXCSRH7_MODE Mode [5:5] USB_TXCSRH7_ISO Isochronous Transfers [6:6] USB_TXCSRH7_AUTOSET Auto Set [7:7] RXMAXP7 USB Maximum Receive Data Endpoint 7 0x00000174 16 USB_RXMAXP7_MAXLOAD Maximum Payload [10:0] RXCSRL7 USB Receive Control and Status Endpoint 7 Low 0x00000176 8 USB_RXCSRL7_RXRDY Receive Packet Ready [0:0] USB_RXCSRL7_FULL FIFO Full [1:1] USB_RXCSRL7_OVER Overrun [2:2] USB_RXCSRL7_DATAERR Data Error [3:3] USB_RXCSRL7_FLUSH Flush FIFO [4:4] USB_RXCSRL7_STALL Send STALL [5:5] USB_RXCSRL7_STALLED Endpoint Stalled [6:6] USB_RXCSRL7_CLRDT Clear Data Toggle [7:7] RXCSRL7 USB Receive Control and Status Endpoint 7 Low USB0_ALT 0x00000176 8 USB_RXCSRL7_ERROR Error [2:2] USB_RXCSRL7_NAKTO NAK Timeout [3:3] USB_RXCSRL7_REQPKT Request Packet [5:5] RXCSRH7 USB Receive Control and Status Endpoint 7 High 0x00000177 8 USB_RXCSRH7_INCOMPRX Incomplete RX Transmission Status [0:0] USB_RXCSRH7_DT Data Toggle [1:1] USB_RXCSRH7_DTWE Data Toggle Write Enable [2:2] USB_RXCSRH7_DMAMOD DMA Request Mode [3:3] USB_RXCSRH7_PIDERR PID Error [4:4] USB_RXCSRH7_DMAEN DMA Request Enable [5:5] USB_RXCSRH7_AUTORQ Auto Request [6:6] USB_RXCSRH7_AUTOCL Auto Clear [7:7] RXCSRH7 USB Receive Control and Status Endpoint 7 High USB0_ALT 0x00000177 8 USB_RXCSRH7_DISNYET Disable NYET [4:4] USB_RXCSRH7_ISO Isochronous Transfers [6:6] RXCOUNT7 USB Receive Byte Count Endpoint 7 0x00000178 16 USB_RXCOUNT7_COUNT Receive Packet Count [12:0] TXTYPE7 USB Host Transmit Configure Type Endpoint 7 0x0000017A 8 USB_TXTYPE7_TEP Target Endpoint Number [3:0] USB_TXTYPE7_PROTO Protocol [5:4] USB_TXTYPE7_PROTO_CTRL Control 0x0 USB_TXTYPE7_PROTO_ISOC Isochronous 0x1 USB_TXTYPE7_PROTO_BULK Bulk 0x2 USB_TXTYPE7_PROTO_INT Interrupt 0x3 USB_TXTYPE7_SPEED Operating Speed [7:6] USB_TXTYPE7_SPEED_DFLT Default 0x0 USB_TXTYPE7_SPEED_HIGH High 0x1 USB_TXTYPE7_SPEED_FULL Full 0x2 USB_TXTYPE7_SPEED_LOW Low 0x3 TXINTERVAL7 USB Host Transmit Interval Endpoint 7 0x0000017B 8 USB_TXINTERVAL7_TXPOLL TX Polling [7:0] TXINTERVAL7 USB Host Transmit Interval Endpoint 7 USB0_ALT 0x0000017B 8 USB_TXINTERVAL7_NAKLMT NAK Limit [7:0] RXTYPE7 USB Host Configure Receive Type Endpoint 7 0x0000017C 8 USB_RXTYPE7_TEP Target Endpoint Number [3:0] USB_RXTYPE7_PROTO Protocol [5:4] USB_RXTYPE7_PROTO_CTRL Control 0x0 USB_RXTYPE7_PROTO_ISOC Isochronous 0x1 USB_RXTYPE7_PROTO_BULK Bulk 0x2 USB_RXTYPE7_PROTO_INT Interrupt 0x3 USB_RXTYPE7_SPEED Operating Speed [7:6] USB_RXTYPE7_SPEED_DFLT Default 0x0 USB_RXTYPE7_SPEED_HIGH High 0x1 USB_RXTYPE7_SPEED_FULL Full 0x2 USB_RXTYPE7_SPEED_LOW Low 0x3 RXINTERVAL7 USB Host Receive Polling Interval Endpoint 7 0x0000017D 8 USB_RXINTERVAL7_TXPOLL RX Polling [7:0] RXINTERVAL7 USB Host Receive Polling Interval Endpoint 7 USB0_ALT 0x0000017D 8 USB_RXINTERVAL7_NAKLMT NAK Limit [7:0] DMAINTR USB DMA Interrupt 0x00000200 8 USB_DMAINTR_CH0 Channel 0 DMA Interrupt [0:0] USB_DMAINTR_CH1 Channel 1 DMA Interrupt [1:1] USB_DMAINTR_CH2 Channel 2 DMA Interrupt [2:2] USB_DMAINTR_CH3 Channel 3 DMA Interrupt [3:3] USB_DMAINTR_CH4 Channel 4 DMA Interrupt [4:4] USB_DMAINTR_CH5 Channel 5 DMA Interrupt [5:5] USB_DMAINTR_CH6 Channel 6 DMA Interrupt [6:6] USB_DMAINTR_CH7 Channel 7 DMA Interrupt [7:7] DMACTL0 USB DMA Control 0 0x00000204 16 USB_DMACTL0_ENABLE DMA Transfer Enable [0:0] USB_DMACTL0_DIR DMA Direction [1:1] USB_DMACTL0_MODE DMA Transfer Mode [2:2] USB_DMACTL0_IE DMA Interrupt Enable [3:3] USB_DMACTL0_EP Endpoint number [7:4] USB_DMACTL0_ERR Bus Error Bit [8:8] USB_DMACTL0_BRSTM Burst Mode [10:9] USB_DMACTL0_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL0_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL0_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL0_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 DMAADDR0 USB DMA Address 0 0x00000208 USB_DMAADDR0_ADDR DMA Address [31:2] DMACOUNT0 USB DMA Count 0 0x0000020C USB_DMACOUNT0_COUNT DMA Count [31:2] DMACTL1 USB DMA Control 1 0x00000214 16 USB_DMACTL1_ENABLE DMA Transfer Enable [0:0] USB_DMACTL1_DIR DMA Direction [1:1] USB_DMACTL1_MODE DMA Transfer Mode [2:2] USB_DMACTL1_IE DMA Interrupt Enable [3:3] USB_DMACTL1_EP Endpoint number [7:4] USB_DMACTL1_ERR Bus Error Bit [8:8] USB_DMACTL1_BRSTM Burst Mode [10:9] USB_DMACTL1_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL1_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL1_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL1_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 DMAADDR1 USB DMA Address 1 0x00000218 USB_DMAADDR1_ADDR DMA Address [31:2] DMACOUNT1 USB DMA Count 1 0x0000021C USB_DMACOUNT1_COUNT DMA Count [31:2] DMACTL2 USB DMA Control 2 0x00000224 16 USB_DMACTL2_ENABLE DMA Transfer Enable [0:0] USB_DMACTL2_DIR DMA Direction [1:1] USB_DMACTL2_MODE DMA Transfer Mode [2:2] USB_DMACTL2_IE DMA Interrupt Enable [3:3] USB_DMACTL2_EP Endpoint number [7:4] USB_DMACTL2_ERR Bus Error Bit [8:8] USB_DMACTL2_BRSTM Burst Mode [10:9] USB_DMACTL2_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL2_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL2_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL2_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 DMAADDR2 USB DMA Address 2 0x00000228 USB_DMAADDR2_ADDR DMA Address [31:2] DMACOUNT2 USB DMA Count 2 0x0000022C USB_DMACOUNT2_COUNT DMA Count [31:2] DMACTL3 USB DMA Control 3 0x00000234 16 USB_DMACTL3_ENABLE DMA Transfer Enable [0:0] USB_DMACTL3_DIR DMA Direction [1:1] USB_DMACTL3_MODE DMA Transfer Mode [2:2] USB_DMACTL3_IE DMA Interrupt Enable [3:3] USB_DMACTL3_EP Endpoint number [7:4] USB_DMACTL3_ERR Bus Error Bit [8:8] USB_DMACTL3_BRSTM Burst Mode [10:9] USB_DMACTL3_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL3_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL3_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL3_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 DMAADDR3 USB DMA Address 3 0x00000238 USB_DMAADDR3_ADDR DMA Address [31:2] DMACOUNT3 USB DMA Count 3 0x0000023C USB_DMACOUNT3_COUNT DMA Count [31:2] DMACTL4 USB DMA Control 4 0x00000244 16 USB_DMACTL4_ENABLE DMA Transfer Enable [0:0] USB_DMACTL4_DIR DMA Direction [1:1] USB_DMACTL4_MODE DMA Transfer Mode [2:2] USB_DMACTL4_IE DMA Interrupt Enable [3:3] USB_DMACTL4_EP Endpoint number [7:4] USB_DMACTL4_ERR Bus Error Bit [8:8] USB_DMACTL4_BRSTM Burst Mode [10:9] USB_DMACTL4_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL4_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL4_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL4_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 DMAADDR4 USB DMA Address 4 0x00000248 USB_DMAADDR4_ADDR DMA Address [31:2] DMACOUNT4 USB DMA Count 4 0x0000024C USB_DMACOUNT4_COUNT DMA Count [31:2] DMACTL5 USB DMA Control 5 0x00000254 16 USB_DMACTL5_ENABLE DMA Transfer Enable [0:0] USB_DMACTL5_DIR DMA Direction [1:1] USB_DMACTL5_MODE DMA Transfer Mode [2:2] USB_DMACTL5_IE DMA Interrupt Enable [3:3] USB_DMACTL5_EP Endpoint number [7:4] USB_DMACTL5_ERR Bus Error Bit [8:8] USB_DMACTL5_BRSTM Burst Mode [10:9] USB_DMACTL5_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL5_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL5_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL5_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 DMAADDR5 USB DMA Address 5 0x00000258 USB_DMAADDR5_ADDR DMA Address [31:2] DMACOUNT5 USB DMA Count 5 0x0000025C USB_DMACOUNT5_COUNT DMA Count [31:2] DMACTL6 USB DMA Control 6 0x00000264 16 USB_DMACTL6_ENABLE DMA Transfer Enable [0:0] USB_DMACTL6_DIR DMA Direction [1:1] USB_DMACTL6_MODE DMA Transfer Mode [2:2] USB_DMACTL6_IE DMA Interrupt Enable [3:3] USB_DMACTL6_EP Endpoint number [7:4] USB_DMACTL6_ERR Bus Error Bit [8:8] USB_DMACTL6_BRSTM Burst Mode [10:9] USB_DMACTL6_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL6_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL6_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL6_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 DMAADDR6 USB DMA Address 6 0x00000268 USB_DMAADDR6_ADDR DMA Address [31:2] DMACOUNT6 USB DMA Count 6 0x0000026C USB_DMACOUNT6_COUNT DMA Count [31:2] DMACTL7 USB DMA Control 7 0x00000274 16 USB_DMACTL7_ENABLE DMA Transfer Enable [0:0] USB_DMACTL7_DIR DMA Direction [1:1] USB_DMACTL7_MODE DMA Transfer Mode [2:2] USB_DMACTL7_IE DMA Interrupt Enable [3:3] USB_DMACTL7_EP Endpoint number [7:4] USB_DMACTL7_ERR Bus Error Bit [8:8] USB_DMACTL7_BRSTM Burst Mode [10:9] USB_DMACTL7_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL7_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL7_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL7_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 DMAADDR7 USB DMA Address 7 0x00000278 USB_DMAADDR7_ADDR DMA Address [31:2] DMACOUNT7 USB DMA Count 7 0x0000027C USB_DMACOUNT7_COUNT DMA Count [31:2] RQPKTCOUNT1 USB Request Packet Count in Block Transfer Endpoint 1 0x00000304 16 USB_RQPKTCOUNT1 Block Transfer Packet Count [15:0] RQPKTCOUNT2 USB Request Packet Count in Block Transfer Endpoint 2 0x00000308 16 USB_RQPKTCOUNT2 Block Transfer Packet Count [15:0] RQPKTCOUNT3 USB Request Packet Count in Block Transfer Endpoint 3 0x0000030C 16 USB_RQPKTCOUNT3 Block Transfer Packet Count [15:0] RQPKTCOUNT4 USB Request Packet Count in Block Transfer Endpoint 4 0x00000310 16 USB_RQPKTCOUNT4_COUNT Block Transfer Packet Count [15:0] RQPKTCOUNT5 USB Request Packet Count in Block Transfer Endpoint 5 0x00000314 16 USB_RQPKTCOUNT5_COUNT Block Transfer Packet Count [15:0] RQPKTCOUNT6 USB Request Packet Count in Block Transfer Endpoint 6 0x00000318 16 USB_RQPKTCOUNT6_COUNT Block Transfer Packet Count [15:0] RQPKTCOUNT7 USB Request Packet Count in Block Transfer Endpoint 7 0x0000031C 16 USB_RQPKTCOUNT7_COUNT Block Transfer Packet Count [15:0] RXDPKTBUFDIS USB Receive Double Packet Buffer Disable 0x00000340 16 USB_RXDPKTBUFDIS_EP1 EP1 RX Double-Packet Buffer Disable [1:1] USB_RXDPKTBUFDIS_EP2 EP2 RX Double-Packet Buffer Disable [2:2] USB_RXDPKTBUFDIS_EP3 EP3 RX Double-Packet Buffer Disable [3:3] USB_RXDPKTBUFDIS_EP4 EP4 RX Double-Packet Buffer Disable [4:4] USB_RXDPKTBUFDIS_EP5 EP5 RX Double-Packet Buffer Disable [5:5] USB_RXDPKTBUFDIS_EP6 EP6 RX Double-Packet Buffer Disable [6:6] USB_RXDPKTBUFDIS_EP7 EP7 RX Double-Packet Buffer Disable [7:7] TXDPKTBUFDIS USB Transmit Double Packet Buffer Disable 0x00000342 16 USB_TXDPKTBUFDIS_EP1 EP1 TX Double-Packet Buffer Disable [1:1] USB_TXDPKTBUFDIS_EP2 EP2 TX Double-Packet Buffer Disable [2:2] USB_TXDPKTBUFDIS_EP3 EP3 TX Double-Packet Buffer Disable [3:3] USB_TXDPKTBUFDIS_EP4 EP4 TX Double-Packet Buffer Disable [4:4] USB_TXDPKTBUFDIS_EP5 EP5 TX Double-Packet Buffer Disable [5:5] USB_TXDPKTBUFDIS_EP6 EP6 TX Double-Packet Buffer Disable [6:6] USB_TXDPKTBUFDIS_EP7 EP7 TX Double-Packet Buffer Disable [7:7] CTO USB Chirp Timeout 0x00000344 16 USB_CTO_CCTV Configurable Chirp Timeout Value [15:0] HHSRTN USB High Speed to UTM Operating Delay 0x00000346 16 USB_HHSRTN_HHSRTN HIgh Speed to UTM Operating Delay [15:0] HSBT USB High Speed Time-out Adder 0x00000348 16 USB_HSBT_HSBT High Speed Timeout Adder [3:0] LPMATTR USB LPM Attributes 0x00000360 16 USB_LPMATTR_LS Link State [3:0] USB_LPMATTR_LS_L1 Sleep State (L1) 0x1 USB_LPMATTR_HIRD Host Initiated Resume Duration [7:4] USB_LPMATTR_RMTWAK Remote Wake [8:8] USB_LPMATTR_ENDPT Endpoint [15:12] LPMCNTRL USB LPM Control 0x00000362 8 USB_LPMCNTRL_TXLPM Transmit LPM Transaction Enable [0:0] USB_LPMCNTRL_RES LPM Resume [1:1] USB_LPMCNTRL_EN LPM Enable [3:2] USB_LPMCNTRL_EN_NONE LPM and Extended transactions are not supported. In this case, the USB does not respond to LPM transactions and LPM transactions cause a timeout 0x0 USB_LPMCNTRL_EN_EXT LPM is not supported but extended transactions are supported. In this case, the USB does respond to an LPM transaction with a STALL 0x1 USB_LPMCNTRL_EN_LPMEXT The USB supports LPM extended transactions. In this case, the USB responds with a NYET or an ACK as determined by the value of TXLPM and other conditions 0x3 USB_LPMCNTRL_NAK LPM NAK [4:4] LPMIM USB LPM Interrupt Mask 0x00000363 8 USB_LPMIM_STALL LPM STALL Interrupt Mask [0:0] USB_LPMIM_NY LPM NY Interrupt Mask [1:1] USB_LPMIM_ACK LPM ACK Interrupt Mask [2:2] USB_LPMIM_NC LPM NC Interrupt Mask [3:3] USB_LPMIM_RES LPM Resume Interrupt Mask [4:4] USB_LPMIM_ERR LPM Error Interrupt Mask [5:5] LPMRIS USB LPM Raw Interrupt Status 0x00000364 8 USB_LPMRIS_LPMST LPM STALL Interrupt Status [0:0] USB_LPMRIS_NY LPM NY Interrupt Status [1:1] USB_LPMRIS_ACK LPM ACK Interrupt Status [2:2] USB_LPMRIS_NC LPM NC Interrupt Status [3:3] USB_LPMRIS_RES LPM Resume Interrupt Status [4:4] USB_LPMRIS_ERR LPM Interrupt Status [5:5] LPMFADDR USB LPM Function Address 0x00000365 8 USB_LPMFADDR_ADDR LPM Function Address [6:0] EPC USB External Power Control 0x00000400 USB_EPC_EPEN External Power Supply Enable Configuration [1:0] USB_EPC_EPEN_LOW Power Enable Active Low 0x0 USB_EPC_EPEN_HIGH Power Enable Active High 0x1 USB_EPC_EPEN_VBLOW Power Enable High if VBUS Low (OTG only) 0x2 USB_EPC_EPEN_VBHIGH Power Enable High if VBUS High (OTG only) 0x3 USB_EPC_EPENDE EPEN Drive Enable [2:2] USB_EPC_PFLTEN Power Fault Input Enable [4:4] USB_EPC_PFLTSEN_HIGH Power Fault Sense [5:5] USB_EPC_PFLTAEN Power Fault Action Enable [6:6] USB_EPC_PFLTACT Power Fault Action [9:8] USB_EPC_PFLTACT_UNCHG Unchanged 0x0 USB_EPC_PFLTACT_TRIS Tristate 0x1 USB_EPC_PFLTACT_LOW Low 0x2 USB_EPC_PFLTACT_HIGH High 0x3 EPCRIS USB External Power Control Raw Interrupt Status 0x00000404 USB_EPCRIS_PF USB Power Fault Interrupt Status [0:0] EPCIM USB External Power Control Interrupt Mask 0x00000408 USB_EPCIM_PF USB Power Fault Interrupt Mask [0:0] EPCISC USB External Power Control Interrupt Status and Clear 0x0000040C USB_EPCISC_PF USB Power Fault Interrupt Status and Clear [0:0] DRRIS USB Device RESUME Raw Interrupt Status 0x00000410 USB_DRRIS_RESUME RESUME Interrupt Status [0:0] DRIM USB Device RESUME Interrupt Mask 0x00000414 USB_DRIM_RESUME RESUME Interrupt Mask [0:0] DRISC USB Device RESUME Interrupt Status and Clear 0x00000418 write-only USB_DRISC_RESUME RESUME Interrupt Status and Clear [0:0] write-only GPCS USB General-Purpose Control and Status 0x0000041C USB_GPCS_DEVMOD Device Mode [2:0] USB_GPCS_DEVMOD_OTG Use USB0VBUS and USB0ID pin 0x0 USB_GPCS_DEVMOD_HOST Force USB0VBUS and USB0ID low 0x2 USB_GPCS_DEVMOD_DEV Force USB0VBUS and USB0ID high 0x3 USB_GPCS_DEVMOD_HOSTVBUS Use USB0VBUS and force USB0ID low 0x4 USB_GPCS_DEVMOD_DEVVBUS Use USB0VBUS and force USB0ID high 0x5 VDC USB VBUS Droop Control 0x00000430 USB_VDC_VBDEN VBUS Droop Enable [0:0] VDCRIS USB VBUS Droop Control Raw Interrupt Status 0x00000434 USB_VDCRIS_VD VBUS Droop Raw Interrupt Status [0:0] VDCIM USB VBUS Droop Control Interrupt Mask 0x00000438 USB_VDCIM_VD VBUS Droop Interrupt Mask [0:0] VDCISC USB VBUS Droop Control Interrupt Status and Clear 0x0000043C USB_VDCISC_VD VBUS Droop Interrupt Status and Clear [0:0] PP USB Peripheral Properties 0x00000FC0 USB_PP_TYPE Controller Type [3:0] USB_PP_TYPE_0 The first-generation USB controller revision 0x0 USB_PP_TYPE_1 The second-generation USB controller revision 0x1 USB_PP_PHY PHY Present [4:4] USB_PP_ULPI ULPI Present [5:5] USB_PP_USB USB Capability [7:6] USB_PP_USB_DEVICE DEVICE 0x1 USB_PP_USB_HOSTDEVICE HOST 0x2 USB_PP_USB_OTG OTG 0x3 USB_PP_ECNT Endpoint Count [15:8] PC USB Peripheral Configuration 0x00000FC4 USB_PC_ULPIEN ULPI Enable [16:16] CC USB Clock Configuration 0x00000FC8 USB_CC_CLKDIV PLL Clock Divisor [3:0] USB_CC_CSD Clock Source/Direction [8:8] USB_CC_CLKEN USB Clock Enable [9:9] GPIOA Register map for GPIOA peripheral GPIO GPIOA 0x40058000 0 0x00001000 registers GPIOA0 DATA GPIO Data 0x000003FC DIR GPIO Direction 0x00000400 IS GPIO Interrupt Sense 0x00000404 IBE GPIO Interrupt Both Edges 0x00000408 IEV GPIO Interrupt Event 0x0000040C IM GPIO Interrupt Mask 0x00000410 GPIO_IM_GPIO GPIO Interrupt Mask Enable [7:0] GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable [8:8] RIS GPIO Raw Interrupt Status 0x00000414 GPIO_RIS_GPIO GPIO Interrupt Raw Status [7:0] GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status [8:8] MIS GPIO Masked Interrupt Status 0x00000418 GPIO_MIS_GPIO GPIO Masked Interrupt Status [7:0] GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status [8:8] ICR GPIO Interrupt Clear 0x0000041C write-only GPIO_ICR_GPIO GPIO Interrupt Clear [7:0] write-only GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear [8:8] write-only AFSEL GPIO Alternate Function Select 0x00000420 DR2R GPIO 2-mA Drive Select 0x00000500 DR4R GPIO 4-mA Drive Select 0x00000504 DR8R GPIO 8-mA Drive Select 0x00000508 ODR GPIO Open Drain Select 0x0000050C PUR GPIO Pull-Up Select 0x00000510 PDR GPIO Pull-Down Select 0x00000514 SLR GPIO Slew Rate Control Select 0x00000518 DEN GPIO Digital Enable 0x0000051C LOCK GPIO Lock 0x00000520 GPIO_LOCK GPIO Lock [31:0] GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 CR GPIO Commit 0x00000524 AMSEL GPIO Analog Mode Select 0x00000528 PCTL GPIO Port Control 0x0000052C ADCCTL GPIO ADC Control 0x00000530 DMACTL GPIO DMA Control 0x00000534 SI GPIO Select Interrupt 0x00000538 GPIO_SI_SUM Summary Interrupt [0:0] DR12R GPIO 12-mA Drive Select 0x0000053C GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable [7:0] GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 WAKEPEN GPIO Wake Pin Enable 0x00000540 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable [4:4] WAKELVL GPIO Wake Level 0x00000544 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level [4:4] WAKESTAT GPIO Wake Status 0x00000548 GPIO_WAKESTAT_STAT4 P[4] Wake Status [4:4] PP GPIO Peripheral Property 0x00000FC0 GPIO_PP_EDE Extended Drive Enable [0:0] PC GPIO Peripheral Configuration 0x00000FC4 GPIO_PC_EDM0 Extended Drive Mode Bit 0 [1:0] GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 [3:2] GPIO_PC_EDM2 Extended Drive Mode Bit 2 [5:4] GPIO_PC_EDM3 Extended Drive Mode Bit 3 [7:6] GPIO_PC_EDM4 Extended Drive Mode Bit 4 [9:8] GPIO_PC_EDM5 Extended Drive Mode Bit 5 [11:10] GPIO_PC_EDM6 Extended Drive Mode Bit 6 [13:12] GPIO_PC_EDM7 Extended Drive Mode Bit 7 [15:14] GPIOB GPIOB 0x40059000 GPIOB1 GPIOC GPIOC 0x4005A000 GPIOC2 GPIOD GPIOD 0x4005B000 GPIOD3 GPIOE GPIOE 0x4005C000 GPIOE4 GPIOF GPIOF 0x4005D000 GPIOF30 GPIOG GPIOG 0x4005E000 GPIOG31 GPIOH GPIOH 0x4005F000 GPIOH32 GPIOJ GPIOJ 0x40060000 GPIOJ51 GPIOK GPIOK 0x40061000 GPIOK52 GPIOL GPIOL 0x40062000 GPIOL53 GPIOM GPIOM 0x40063000 GPIOM72 GPION GPION 0x40064000 GPION73 GPIOP GPIOP 0x40065000 GPIOP076 GPIOP177 GPIOP278 GPIOP379 GPIOP480 GPIOP581 GPIOP682 GPIOP783 GPIOQ GPIOQ 0x40066000 GPIOQ084 GPIOQ185 GPIOQ286 GPIOQ387 GPIOQ488 GPIOQ589 GPIOQ690 GPIOQ791 GPIOR GPIOR 0x40067000 GPIOR92 GPIOS GPIOS 0x40068000 GPIOS93 GPIOT GPIOT 0x40069000 GPIOT111 EEPROM Register map for EEPROM peripheral EEPROM EEPROM 0x400AF000 0 0x00001000 registers EESIZE EEPROM Size Information 0x00000000 EEPROM_EESIZE_WORDCNT Number of 32-Bit Words [15:0] EEPROM_EESIZE_BLKCNT Number of 16-Word Blocks [26:16] EEBLOCK EEPROM Current Block 0x00000004 EEPROM_EEBLOCK_BLOCK Current Block [15:0] EEOFFSET EEPROM Current Offset 0x00000008 EEPROM_EEOFFSET_OFFSET Current Address Offset [3:0] EERDWR EEPROM Read-Write 0x00000010 EEPROM_EERDWR_VALUE EEPROM Read or Write Data [31:0] EERDWRINC EEPROM Read-Write with Increment 0x00000014 EEPROM_EERDWRINC_VALUE EEPROM Read or Write Data with Increment [31:0] EEDONE EEPROM Done Status 0x00000018 EEPROM_EEDONE_WORKING EEPROM Working [0:0] EEPROM_EEDONE_WKERASE Working on an Erase [2:2] EEPROM_EEDONE_WKCOPY Working on a Copy [3:3] EEPROM_EEDONE_NOPERM Write Without Permission [4:4] EEPROM_EEDONE_WRBUSY Write Busy [5:5] EESUPP EEPROM Support Control and Status 0x0000001C EEPROM_EESUPP_ERETRY Erase Must Be Retried [2:2] EEPROM_EESUPP_PRETRY Programming Must Be Retried [3:3] EEUNLOCK EEPROM Unlock 0x00000020 EEPROM_EEUNLOCK_UNLOCK EEPROM Unlock [31:0] EEPROT EEPROM Protection 0x00000030 EEPROM_EEPROT_PROT Protection Control [2:0] EEPROM_EEPROT_PROT_RWNPW This setting is the default. If there is no password, the block is not protected and is readable and writable 0x0 EEPROM_EEPROT_PROT_RWPW If there is a password, the block is readable or writable only when unlocked 0x1 EEPROM_EEPROT_PROT_RONPW If there is no password, the block is readable, not writable 0x2 EEPROM_EEPROT_ACC Access Control [3:3] EEPASS0 EEPROM Password 0x00000034 EEPROM_EEPASS0_PASS Password [31:0] EEPASS1 EEPROM Password 0x00000038 EEPROM_EEPASS1_PASS Password [31:0] EEPASS2 EEPROM Password 0x0000003C EEPROM_EEPASS2_PASS Password [31:0] EEINT EEPROM Interrupt 0x00000040 EEPROM_EEINT_INT Interrupt Enable [0:0] EEHIDE0 EEPROM Block Hide 0 0x00000050 EEPROM_EEHIDE0_HN Hide Block [31:1] EEHIDE1 EEPROM Block Hide 1 0x00000054 EEPROM_EEHIDE1_HN Hide Block [31:0] EEHIDE2 EEPROM Block Hide 2 0x00000058 EEPROM_EEHIDE2_HN Hide Block [31:0] EEDBGME EEPROM Debug Mass Erase 0x00000080 EEPROM_EEDBGME_ME Mass Erase [0:0] EEPROM_EEDBGME_KEY Erase Key [31:16] PP EEPROM Peripheral Properties 0x00000FC0 EEPROM_PP_SIZE EEPROM Size [15:0] ONEWIRE0 Register map for ONEWIRE0 peripheral ONEWIRE ONEWIRE0 0x400B6000 0 0x00001000 registers ONEWIRE0105 CS 1-Wire Control and Status 0x00000000 ONEWIRE_CS_RST Reset Request [0:0] ONEWIRE_CS_OP Operation Request [2:1] ONEWIRE_CS_OP_NONE No operation 0x0 ONEWIRE_CS_OP_RD Read 0x1 ONEWIRE_CS_OP_WR Write 0x2 ONEWIRE_CS_OP_WRRD Write/Read 0x3 ONEWIRE_CS_SZ Data Operation Size [4:3] ONEWIRE_CS_ODRV Overdrive Enable [5:5] ONEWIRE_CS_LSAM Late Sample Enable [6:6] ONEWIRE_CS_SKATR Skip Answer-to-Reset Enable [7:7] ONEWIRE_CS_BUSY Busy Status [8:8] ONEWIRE_CS_NOATR Answer-to-Reset Status [9:9] ONEWIRE_CS_STUCK STUCK Status [10:10] ONEWIRE_CS_BSIZE Last Byte Size [18:16] ONEWIRE_CS_BSIZE_8 8 bits (1 byte) 0x0 ONEWIRE_CS_BSIZE_1 1 bit 0x1 ONEWIRE_CS_BSIZE_2 2 bits 0x2 ONEWIRE_CS_BSIZE_3 3 bits 0x3 ONEWIRE_CS_BSIZE_4 4 bits 0x4 ONEWIRE_CS_BSIZE_5 5 bits 0x5 ONEWIRE_CS_BSIZE_6 6 bits 0x6 ONEWIRE_CS_BSIZE_7 7 bits 0x7 ONEWIRE_CS_ALTP Alternate Polarity Enable [30:30] ONEWIRE_CS_USEALT Two Wire Enable [31:31] TIM 1-Wire Timing Override 0x00000004 ONEWIRE_TIM_RSTTIM Reset Low Time [5:0] ONEWIRE_TIM_ATRTIM Answer-to-Reset/Rest Period [10:6] ONEWIRE_TIM_ATRSAM Answer-to-Reset Sample [14:11] ONEWIRE_TIM_W1SAM Sample Time [18:15] ONEWIRE_TIM_W0REST Rest Time [22:19] ONEWIRE_TIM_W0TIM Value '0' Timing [27:23] ONEWIRE_TIM_W1TIM Value '1' Timing [31:28] DATW 1-Wire Data Write 0x00000008 ONEWIRE_DATW_B0 Lowest Data Byte [7:0] ONEWIRE_DATW_B1 Lower Middle Data Byte [15:8] ONEWIRE_DATW_B2 Upper Middle Data Byte [23:16] ONEWIRE_DATW_B3 Upper Data Byte [31:24] DATR 1-Wire Data Read 0x0000000C ONEWIRE_DATR_B0 Lowest Data Byte [7:0] ONEWIRE_DATR_B1 Lower Middle Data Byte [15:8] ONEWIRE_DATR_B2 Upper Middle Data Byte [23:16] ONEWIRE_DATR_B3 Upper Data Byte [31:24] IM 1-Wire Interrupt Mask 0x00000100 ONEWIRE_IM_RST Reset Interrupt Mask [0:0] ONEWIRE_IM_OPC Operation Complete Interrupt Mask [1:1] ONEWIRE_IM_NOATR No Answer-to-Reset Interrupt Mask [2:2] ONEWIRE_IM_STUCK Stuck Status Interrupt Mask [3:3] ONEWIRE_IM_DMA DMA Done Interrupt Mask [4:4] RIS 1-Wire Raw Interrupt Status 0x00000104 ONEWIRE_RIS_RST Reset Raw Interrupt Status [0:0] ONEWIRE_RIS_OPC Operation Complete Raw Interrupt Status [1:1] ONEWIRE_RIS_NOATR No Answer-to-Reset Raw Interrupt Status [2:2] ONEWIRE_RIS_STUCK Stuck Status Raw Interrupt Status [3:3] ONEWIRE_RIS_DMA DMA Done Raw Interrupt Status [4:4] MIS 1-Wire Masked Interrupt Status 0x00000108 ONEWIRE_MIS_RST Reset Interrupt Mask [0:0] ONEWIRE_MIS_OPC Operation Complete Masked Interrupt Status [1:1] ONEWIRE_MIS_NOATR No Answer-to-Reset Masked Interrupt Status [2:2] ONEWIRE_MIS_STUCK Stuck Status Masked Interrupt Status [3:3] ONEWIRE_MIS_DMA DMA Done Masked Interrupt Status [4:4] ICR 1-Wire Interrupt Clear 0x0000010C ONEWIRE_ICR_RST Reset Interrupt Clear [0:0] ONEWIRE_ICR_OPC Operation Complete Interrupt Clear [1:1] ONEWIRE_ICR_NOATR No Answer-to-Reset Interrupt Clear [2:2] ONEWIRE_ICR_STUCK Stuck Status Interrupt Clear [3:3] ONEWIRE_ICR_DMA DMA Done Interrupt Clear [4:4] DMA 1-Wire uDMA Control 0x00000120 ONEWIRE_DMA_RST uDMA Reset [0:0] ONEWIRE_DMA_DMAOP uDMA Operation [2:1] ONEWIRE_DMA_DMAOP_DIS uDMA disabled 0x0 ONEWIRE_DMA_DMAOP_RDSNG uDMA single read: 1-Wire requests uDMA to read ONEWIREDATR register after each read transaction 0x1 ONEWIRE_DMA_DMAOP_WRMUL uDMA multiple write: 1-Wire requests uDMA to load whenever the ONEWIREDATW register is empty 0x2 ONEWIRE_DMA_DMAOP_RDMUL uDMA multiple read: An initial read occurs and subsequent reads start after uDMA has read the ONEWIREDATR register 0x3 ONEWIRE_DMA_SG Scatter-Gather Enable [3:3] PP 1-Wire Peripheral Properties 0x00000FC0 ONEWIRE_PP_CNT 1-Wire Bus Count [1:0] ONEWIRE_PP_DMAP uDMA Present [4:4] I2C8 I2C8 0x400B8000 I2C8109 I2C9 I2C9 0x400B9000 I2C9110 I2C4 I2C4 0x400C0000 I2C470 I2C5 I2C5 0x400C1000 I2C571 I2C6 I2C6 0x400C2000 I2C6102 I2C7 I2C7 0x400C3000 I2C7103 EPI0 Register map for EPI0 peripheral EPI EPI0 0x400D0000 0 0x00001000 registers EPI050 CFG EPI Configuration 0x00000000 EPI_CFG_MODE Mode Select [3:0] EPI_CFG_MODE_NONE General Purpose 0x0 EPI_CFG_MODE_SDRAM SDRAM 0x1 EPI_CFG_MODE_HB8 8-Bit Host-Bus (HB8) 0x2 EPI_CFG_MODE_HB16 16-Bit Host-Bus (HB16) 0x3 EPI_CFG_BLKEN Block Enable [4:4] EPI_CFG_INTDIV Integer Clock Divider Enable [8:8] BAUD EPI Main Baud Rate 0x00000004 EPI_BAUD_COUNT0 Baud Rate Counter 0 [15:0] EPI_BAUD_COUNT1 Baud Rate Counter 1 [31:16] BAUD2 EPI Main Baud Rate 0x00000008 EPI_BAUD2_COUNT0 CS2n Baud Rate Counter 0 [15:0] EPI_BAUD2_COUNT1 CS3n Baud Rate Counter 1 [31:16] HB16CFG EPI Host-Bus 16 Configuration EPI_ALT16 0x00000010 EPI_HB16CFG_MODE Host Bus Sub-Mode [1:0] EPI_HB16CFG_MODE_ADMUX ADMUX - AD[15:0] 0x0 EPI_HB16CFG_MODE_ADNMUX ADNONMUX - D[15:0] 0x1 EPI_HB16CFG_MODE_SRAM Continuous Read - D[15:0] 0x2 EPI_HB16CFG_MODE_XFIFO XFIFO - D[15:0] 0x3 EPI_HB16CFG_BSEL Byte Select Configuration [2:2] EPI_HB16CFG_RDWS Read Wait States [5:4] EPI_HB16CFG_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB16CFG_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB16CFG_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB16CFG_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB16CFG_WRWS Write Wait States [7:6] EPI_HB16CFG_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB16CFG_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB16CFG_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB16CFG_WRWS_8 Active WRn is 8 EPI clocks 0x3 EPI_HB16CFG_MAXWAIT Maximum Wait [15:8] EPI_HB16CFG_BURST Burst Mode [16:16] EPI_HB16CFG_RDCRE PSRAM Configuration Register Read [17:17] EPI_HB16CFG_WRCRE PSRAM Configuration Register Write [18:18] EPI_HB16CFG_ALEHIGH ALE Strobe Polarity [19:19] EPI_HB16CFG_RDHIGH READ Strobe Polarity [20:20] EPI_HB16CFG_WRHIGH WRITE Strobe Polarity [21:21] EPI_HB16CFG_XFEEN External FIFO EMPTY Enable [22:22] EPI_HB16CFG_XFFEN External FIFO FULL Enable [23:23] EPI_HB16CFG_IRDYINV Input Ready Invert [27:27] EPI_HB16CFG_RDYEN Input Ready Enable [28:28] EPI_HB16CFG_CLKINV Invert Output Clock Enable [29:29] EPI_HB16CFG_CLKGATEI Clock Gated Idle [30:30] EPI_HB16CFG_CLKGATE Clock Gated [31:31] GPCFG EPI General-Purpose Configuration 0x00000010 EPI_GPCFG_DSIZE Size of Data Bus [1:0] EPI_GPCFG_DSIZE_4BIT 8 Bits Wide (EPI0S0 to EPI0S7) 0x0 EPI_GPCFG_DSIZE_16BIT 16 Bits Wide (EPI0S0 to EPI0S15) 0x1 EPI_GPCFG_DSIZE_24BIT 24 Bits Wide (EPI0S0 to EPI0S23) 0x2 EPI_GPCFG_DSIZE_32BIT 32 Bits Wide (EPI0S0 to EPI0S31) 0x3 EPI_GPCFG_ASIZE Address Bus Size [5:4] EPI_GPCFG_ASIZE_NONE No address 0x0 EPI_GPCFG_ASIZE_4BIT Up to 4 bits wide 0x1 EPI_GPCFG_ASIZE_12BIT Up to 12 bits wide. This size cannot be used with 24-bit data 0x2 EPI_GPCFG_ASIZE_20BIT Up to 20 bits wide. This size cannot be used with data sizes other than 8 0x3 EPI_GPCFG_WR2CYC 2-Cycle Writes [19:19] EPI_GPCFG_FRMCNT Frame Count [25:22] EPI_GPCFG_FRM50 50/50 Frame [26:26] EPI_GPCFG_CLKGATE Clock Gated [30:30] EPI_GPCFG_CLKPIN Clock Pin [31:31] SDRAMCFG EPI SDRAM Configuration EPI_ALTSD 0x00000010 EPI_SDRAMCFG_SIZE Size of SDRAM [1:0] EPI_SDRAMCFG_SIZE_8MB 64 megabits (8MB) 0x0 EPI_SDRAMCFG_SIZE_16MB 128 megabits (16MB) 0x1 EPI_SDRAMCFG_SIZE_32MB 256 megabits (32MB) 0x2 EPI_SDRAMCFG_SIZE_64MB 512 megabits (64MB) 0x3 EPI_SDRAMCFG_SLEEP Sleep Mode [9:9] EPI_SDRAMCFG_RFSH Refresh Counter [26:16] EPI_SDRAMCFG_FREQ EPI Frequency Range [31:30] EPI_SDRAMCFG_FREQ_NONE 0 - 15 MHz 0x0 EPI_SDRAMCFG_FREQ_15MHZ 15 - 30 MHz 0x1 EPI_SDRAMCFG_FREQ_30MHZ 30 - 50 MHz 0x2 HB8CFG EPI Host-Bus 8 Configuration EPI_ALT8 0x00000010 EPI_HB8CFG_MODE Host Bus Sub-Mode [1:0] EPI_HB8CFG_MODE_MUX ADMUX - AD[7:0] 0x0 EPI_HB8CFG_MODE_NMUX ADNONMUX - D[7:0] 0x1 EPI_HB8CFG_MODE_SRAM Continuous Read - D[7:0] 0x2 EPI_HB8CFG_MODE_FIFO XFIFO - D[7:0] 0x3 EPI_HB8CFG_RDWS Read Wait States [5:4] EPI_HB8CFG_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB8CFG_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB8CFG_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB8CFG_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB8CFG_WRWS Write Wait States [7:6] EPI_HB8CFG_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB8CFG_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB8CFG_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB8CFG_WRWS_8 Active WRn is 8 EPI clocks 0x3 EPI_HB8CFG_MAXWAIT Maximum Wait [15:8] EPI_HB8CFG_ALEHIGH ALE Strobe Polarity [19:19] EPI_HB8CFG_RDHIGH READ Strobe Polarity [20:20] EPI_HB8CFG_WRHIGH WRITE Strobe Polarity [21:21] EPI_HB8CFG_XFEEN External FIFO EMPTY Enable [22:22] EPI_HB8CFG_XFFEN External FIFO FULL Enable [23:23] EPI_HB8CFG_IRDYINV Input Ready Invert [27:27] EPI_HB8CFG_RDYEN Input Ready Enable [28:28] EPI_HB8CFG_CLKINV Invert Output Clock Enable [29:29] EPI_HB8CFG_CLKGATEI Clock Gated when Idle [30:30] EPI_HB8CFG_CLKGATE Clock Gated [31:31] HB8CFG2 EPI Host-Bus 8 Configuration 2 EPI_ALT8 0x00000014 EPI_HB8CFG2_MODE CS1n Host Bus Sub-Mode [1:0] EPI_HB8CFG2_MODE_ADMUX ADMUX - AD[7:0] 0x0 EPI_HB8CFG2_MODE_AD ADNONMUX - D[7:0] 0x1 EPI_HB8CFG2_RDWS CS1n Read Wait States [5:4] EPI_HB8CFG2_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB8CFG2_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB8CFG2_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB8CFG2_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB8CFG2_WRWS CS1n Write Wait States [7:6] EPI_HB8CFG2_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB8CFG2_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB8CFG2_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB8CFG2_WRWS_8 Active WRn is 8 EPI clocks 0x3 EPI_HB8CFG2_ALEHIGH CS1n ALE Strobe Polarity [19:19] EPI_HB8CFG2_RDHIGH CS1n READ Strobe Polarity [20:20] EPI_HB8CFG2_WRHIGH CS1n WRITE Strobe Polarity [21:21] EPI_HB8CFG2_CSCFG Chip Select Configuration [25:24] EPI_HB8CFG2_CSCFG_ALE ALE Configuration 0x0 EPI_HB8CFG2_CSCFG_CS CSn Configuration 0x1 EPI_HB8CFG2_CSCFG_DCS Dual CSn Configuration 0x2 EPI_HB8CFG2_CSCFG_ADCS ALE with Dual CSn Configuration 0x3 EPI_HB8CFG2_CSBAUD Chip Select Baud Rate and Multiple Sub-Mode Configuration enable [26:26] EPI_HB8CFG2_CSCFGEXT Chip Select Extended Configuration [27:27] HB16CFG2 EPI Host-Bus 16 Configuration 2 EPI_ALT16 0x00000014 EPI_HB16CFG2_MODE CS1n Host Bus Sub-Mode [1:0] EPI_HB16CFG2_MODE_ADMUX ADMUX - AD[15:0] 0x0 EPI_HB16CFG2_MODE_AD ADNONMUX - D[15:0] 0x1 EPI_HB16CFG2_RDWS CS1n Read Wait States [5:4] EPI_HB16CFG2_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB16CFG2_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB16CFG2_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB16CFG2_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB16CFG2_WRWS CS1n Write Wait States [7:6] EPI_HB16CFG2_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB16CFG2_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB16CFG2_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB16CFG2_WRWS_8 Active WRn is 8 EPI clocks 0x3 EPI_HB16CFG2_BURST CS1n Burst Mode [16:16] EPI_HB16CFG2_RDCRE CS1n PSRAM Configuration Register Read [17:17] EPI_HB16CFG2_WRCRE CS1n PSRAM Configuration Register Write [18:18] EPI_HB16CFG2_ALEHIGH CS1n ALE Strobe Polarity [19:19] EPI_HB16CFG2_RDHIGH CS1n READ Strobe Polarity [20:20] EPI_HB16CFG2_WRHIGH CS1n WRITE Strobe Polarity [21:21] EPI_HB16CFG2_CSCFG Chip Select Configuration [25:24] EPI_HB16CFG2_CSCFG_ALE ALE Configuration 0x0 EPI_HB16CFG2_CSCFG_CS CSn Configuration 0x1 EPI_HB16CFG2_CSCFG_DCS Dual CSn Configuration 0x2 EPI_HB16CFG2_CSCFG_ADCS ALE with Dual CSn Configuration 0x3 EPI_HB16CFG2_CSBAUD Chip Select Baud Rate and Multiple Sub-Mode Configuration enable [26:26] EPI_HB16CFG2_CSCFGEXT Chip Select Extended Configuration [27:27] ADDRMAP EPI Address Map 0x0000001C EPI_ADDRMAP_ERADR External RAM Address [1:0] EPI_ADDRMAP_ERADR_NONE Not mapped 0x0 EPI_ADDRMAP_ERADR_6000 At 0x6000.0000 0x1 EPI_ADDRMAP_ERADR_8000 At 0x8000.0000 0x2 EPI_ADDRMAP_ERADR_HBQS Only to be used with Host Bus quad chip select. In quad chip select mode, CS0n maps to 0x6000.0000 and CS1n maps to 0x8000.0000 0x3 EPI_ADDRMAP_ERSZ External RAM Size [3:2] EPI_ADDRMAP_ERSZ_256B 256 bytes; lower address range: 0x00 to 0xFF 0x0 EPI_ADDRMAP_ERSZ_64KB 64 KB; lower address range: 0x0000 to 0xFFFF 0x1 EPI_ADDRMAP_ERSZ_16MB 16 MB; lower address range: 0x00.0000 to 0xFF.FFFF 0x2 EPI_ADDRMAP_ERSZ_256MB 256 MB; lower address range: 0x000.0000 to 0xFFF.FFFF 0x3 EPI_ADDRMAP_EPADR External Peripheral Address [5:4] EPI_ADDRMAP_EPADR_NONE Not mapped 0x0 EPI_ADDRMAP_EPADR_A000 At 0xA000.0000 0x1 EPI_ADDRMAP_EPADR_C000 At 0xC000.0000 0x2 EPI_ADDRMAP_EPADR_HBQS Only to be used with Host Bus quad chip select. In quad chip select mode, CS2n maps to 0xA000.0000 and CS3n maps to 0xC000.0000 0x3 EPI_ADDRMAP_EPSZ External Peripheral Size [7:6] EPI_ADDRMAP_EPSZ_256B 256 bytes; lower address range: 0x00 to 0xFF 0x0 EPI_ADDRMAP_EPSZ_64KB 64 KB; lower address range: 0x0000 to 0xFFFF 0x1 EPI_ADDRMAP_EPSZ_16MB 16 MB; lower address range: 0x00.0000 to 0xFF.FFFF 0x2 EPI_ADDRMAP_EPSZ_256MB 256 MB; lower address range: 0x000.0000 to 0xFFF.FFFF 0x3 EPI_ADDRMAP_ECADR External Code Address [9:8] EPI_ADDRMAP_ECADR_NONE Not mapped 0x0 EPI_ADDRMAP_ECADR_1000 At 0x1000.0000 0x1 EPI_ADDRMAP_ECSZ External Code Size [11:10] EPI_ADDRMAP_ECSZ_256B 256 bytes; lower address range: 0x00 to 0xFF 0x0 EPI_ADDRMAP_ECSZ_64KB 64 KB; lower address range: 0x0000 to 0xFFFF 0x1 EPI_ADDRMAP_ECSZ_16MB 16 MB; lower address range: 0x00.0000 to 0xFF.FFFF 0x2 EPI_ADDRMAP_ECSZ_256MB 256MB; lower address range: 0x000.0000 to 0x0FFF.FFFF 0x3 RSIZE0 EPI Read Size 0 0x00000020 EPI_RSIZE0_SIZE Current Size [1:0] EPI_RSIZE0_SIZE_8BIT Byte (8 bits) 0x1 EPI_RSIZE0_SIZE_16BIT Half-word (16 bits) 0x2 EPI_RSIZE0_SIZE_32BIT Word (32 bits) 0x3 RADDR0 EPI Read Address 0 0x00000024 EPI_RADDR0_ADDR Current Address [31:0] RPSTD0 EPI Non-Blocking Read Data 0 0x00000028 EPI_RPSTD0_POSTCNT Post Count [12:0] RSIZE1 EPI Read Size 1 0x00000030 EPI_RSIZE1_SIZE Current Size [1:0] EPI_RSIZE1_SIZE_8BIT Byte (8 bits) 0x1 EPI_RSIZE1_SIZE_16BIT Half-word (16 bits) 0x2 EPI_RSIZE1_SIZE_32BIT Word (32 bits) 0x3 RADDR1 EPI Read Address 1 0x00000034 EPI_RADDR1_ADDR Current Address [31:0] RPSTD1 EPI Non-Blocking Read Data 1 0x00000038 EPI_RPSTD1_POSTCNT Post Count [12:0] STAT EPI Status 0x00000060 EPI_STAT_ACTIVE Register Active [0:0] EPI_STAT_NBRBUSY Non-Blocking Read Busy [4:4] EPI_STAT_WBUSY Write Busy [5:5] EPI_STAT_INITSEQ Initialization Sequence [6:6] EPI_STAT_XFEMPTY External FIFO Empty [7:7] EPI_STAT_XFFULL External FIFO Full [8:8] RFIFOCNT EPI Read FIFO Count 0x0000006C EPI_RFIFOCNT_COUNT FIFO Count [3:0] READFIFO0 EPI Read FIFO 0x00000070 EPI_READFIFO0_DATA Reads Data [31:0] READFIFO1 EPI Read FIFO Alias 1 0x00000074 EPI_READFIFO1_DATA Reads Data [31:0] READFIFO2 EPI Read FIFO Alias 2 0x00000078 EPI_READFIFO2_DATA Reads Data [31:0] READFIFO3 EPI Read FIFO Alias 3 0x0000007C EPI_READFIFO3_DATA Reads Data [31:0] READFIFO4 EPI Read FIFO Alias 4 0x00000080 EPI_READFIFO4_DATA Reads Data [31:0] READFIFO5 EPI Read FIFO Alias 5 0x00000084 EPI_READFIFO5_DATA Reads Data [31:0] READFIFO6 EPI Read FIFO Alias 6 0x00000088 EPI_READFIFO6_DATA Reads Data [31:0] READFIFO7 EPI Read FIFO Alias 7 0x0000008C EPI_READFIFO7_DATA Reads Data [31:0] FIFOLVL EPI FIFO Level Selects 0x00000200 EPI_FIFOLVL_RDFIFO Read FIFO [2:0] EPI_FIFOLVL_RDFIFO_1 Trigger when there are 1 or more entries in the NBRFIFO 0x1 EPI_FIFOLVL_RDFIFO_2 Trigger when there are 2 or more entries in the NBRFIFO 0x2 EPI_FIFOLVL_RDFIFO_4 Trigger when there are 4 or more entries in the NBRFIFO 0x3 EPI_FIFOLVL_RDFIFO_6 Trigger when there are 6 or more entries in the NBRFIFO 0x4 EPI_FIFOLVL_RDFIFO_7 Trigger when there are 7 or more entries in the NBRFIFO 0x5 EPI_FIFOLVL_RDFIFO_8 Trigger when there are 8 entries in the NBRFIFO 0x6 EPI_FIFOLVL_WRFIFO Write FIFO [6:4] EPI_FIFOLVL_WRFIFO_EMPT Interrupt is triggered while WRFIFO is empty. 0x0 EPI_FIFOLVL_WRFIFO_2 Interrupt is triggered until there are only two slots available. Thus, trigger is deasserted when there are two WRFIFO entries present. This configuration is optimized for bursts of 2 0x2 EPI_FIFOLVL_WRFIFO_1 Interrupt is triggered until there is one WRFIFO entry available. This configuration expects only single writes 0x3 EPI_FIFOLVL_WRFIFO_NFULL Trigger interrupt when WRFIFO is not full, meaning trigger will continue to assert until there are four entries in the WRFIFO 0x4 EPI_FIFOLVL_RSERR Read Stall Error [16:16] EPI_FIFOLVL_WFERR Write Full Error [17:17] WFIFOCNT EPI Write FIFO Count 0x00000204 EPI_WFIFOCNT_WTAV Available Write Transactions [2:0] DMATXCNT EPI DMA Transmit Count 0x00000208 EPI_DMATXCNT_TXCNT DMA Count [15:0] IM EPI Interrupt Mask 0x00000210 EPI_IM_ERRIM Error Interrupt Mask [0:0] EPI_IM_RDIM Read FIFO Full Interrupt Mask [1:1] EPI_IM_WRIM Write FIFO Empty Interrupt Mask [2:2] EPI_IM_DMARDIM Read uDMA Interrupt Mask [3:3] EPI_IM_DMAWRIM Write uDMA Interrupt Mask [4:4] RIS EPI Raw Interrupt Status 0x00000214 EPI_RIS_ERRRIS Error Raw Interrupt Status [0:0] EPI_RIS_RDRIS Read Raw Interrupt Status [1:1] EPI_RIS_WRRIS Write Raw Interrupt Status [2:2] EPI_RIS_DMARDRIS Read uDMA Raw Interrupt Status [3:3] EPI_RIS_DMAWRRIS Write uDMA Raw Interrupt Status [4:4] MIS EPI Masked Interrupt Status 0x00000218 EPI_MIS_ERRMIS Error Masked Interrupt Status [0:0] EPI_MIS_RDMIS Read Masked Interrupt Status [1:1] EPI_MIS_WRMIS Write Masked Interrupt Status [2:2] EPI_MIS_DMARDMIS Read uDMA Masked Interrupt Status [3:3] EPI_MIS_DMAWRMIS Write uDMA Masked Interrupt Status [4:4] EISC EPI Error and Interrupt Status and Clear 0x0000021C EPI_EISC_TOUT Timeout Error [0:0] EPI_EISC_RSTALL Read Stalled Error [1:1] EPI_EISC_WTFULL Write FIFO Full Error [2:2] EPI_EISC_DMARDIC Read uDMA Interrupt Clear [3:3] EPI_EISC_DMAWRIC Write uDMA Interrupt Clear [4:4] HB8CFG3 EPI Host-Bus 8 Configuration 3 0x00000308 EPI_HB8CFG3_MODE CS2n Host Bus Sub-Mode [1:0] EPI_HB8CFG3_MODE_ADMUX ADMUX - AD[7:0] 0x0 EPI_HB8CFG3_MODE_AD ADNONMUX - D[7:0] 0x1 EPI_HB8CFG3_RDWS CS2n Read Wait States [5:4] EPI_HB8CFG3_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB8CFG3_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB8CFG3_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB8CFG3_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB8CFG3_WRWS CS2n Write Wait States [7:6] EPI_HB8CFG3_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB8CFG3_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB8CFG3_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB8CFG3_WRWS_8 Active WRn is 8 EPI clocks 0x3 EPI_HB8CFG3_ALEHIGH CS2n ALE Strobe Polarity [19:19] EPI_HB8CFG3_RDHIGH CS2n READ Strobe Polarity [20:20] EPI_HB8CFG3_WRHIGH CS2n WRITE Strobe Polarity [21:21] HB16CFG3 EPI Host-Bus 16 Configuration 3 EPI_ALT16 0x00000308 EPI_HB16CFG3_MODE CS2n Host Bus Sub-Mode [1:0] EPI_HB16CFG3_MODE_ADMUX ADMUX - AD[15:0] 0x0 EPI_HB16CFG3_MODE_AD ADNONMUX - D[15:0] 0x1 EPI_HB16CFG3_RDWS CS2n Read Wait States [5:4] EPI_HB16CFG3_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB16CFG3_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB16CFG3_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB16CFG3_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB16CFG3_WRWS CS2n Write Wait States [7:6] EPI_HB16CFG3_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB16CFG3_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB16CFG3_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB16CFG3_WRWS_8 Active WRn is 8 EPI clocks 0x3 EPI_HB16CFG3_BURST CS2n Burst Mode [16:16] EPI_HB16CFG3_RDCRE CS2n PSRAM Configuration Register Read [17:17] EPI_HB16CFG3_WRCRE CS2n PSRAM Configuration Register Write [18:18] EPI_HB16CFG3_ALEHIGH CS2n ALE Strobe Polarity [19:19] EPI_HB16CFG3_RDHIGH CS2n READ Strobe Polarity [20:20] EPI_HB16CFG3_WRHIGH CS2n WRITE Strobe Polarity [21:21] HB16CFG4 EPI Host-Bus 16 Configuration 4 0x0000030C EPI_HB16CFG4_MODE CS3n Host Bus Sub-Mode [1:0] EPI_HB16CFG4_MODE_ADMUX ADMUX - AD[15:0] 0x0 EPI_HB16CFG4_MODE_AD ADNONMUX - D[15:0] 0x1 EPI_HB16CFG4_RDWS CS3n Read Wait States [5:4] EPI_HB16CFG4_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB16CFG4_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB16CFG4_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB16CFG4_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB16CFG4_WRWS CS3n Write Wait States [7:6] EPI_HB16CFG4_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB16CFG4_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB16CFG4_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB16CFG4_WRWS_8 Active WRn is 8 EPI clocks 0x3 EPI_HB16CFG4_BURST CS3n Burst Mode [16:16] EPI_HB16CFG4_RDCRE CS3n PSRAM Configuration Register Read [17:17] EPI_HB16CFG4_WRCRE CS3n PSRAM Configuration Register Write [18:18] EPI_HB16CFG4_ALEHIGH CS3n ALE Strobe Polarity [19:19] EPI_HB16CFG4_RDHIGH CS3n READ Strobe Polarity [20:20] EPI_HB16CFG4_WRHIGH CS3n WRITE Strobe Polarity [21:21] HB8CFG4 EPI Host-Bus 8 Configuration 4 EPI_ALT8 0x0000030C EPI_HB8CFG4_MODE CS3n Host Bus Sub-Mode [1:0] EPI_HB8CFG4_MODE_ADMUX ADMUX - AD[7:0] 0x0 EPI_HB8CFG4_MODE_AD ADNONMUX - D[7:0] 0x1 EPI_HB8CFG4_RDWS CS3n Read Wait States [5:4] EPI_HB8CFG4_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB8CFG4_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB8CFG4_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB8CFG4_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB8CFG4_WRWS CS3n Write Wait States [7:6] EPI_HB8CFG4_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB8CFG4_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB8CFG4_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB8CFG4_WRWS_8 Active WRn is 8 EPI clocks 0x3 EPI_HB8CFG4_ALEHIGH CS3n ALE Strobe Polarity [19:19] EPI_HB8CFG4_RDHIGH CS2n READ Strobe Polarity [20:20] EPI_HB8CFG4_WRHIGH CS3n WRITE Strobe Polarity [21:21] HB8TIME EPI Host-Bus 8 Timing Extension 0x00000310 EPI_HB8TIME_RDWSM Read Wait State Minus One [0:0] EPI_HB8TIME_WRWSM Write Wait State Minus One [4:4] EPI_HB8TIME_CAPWIDTH CS0n Inter-transfer Capture Width [13:12] EPI_HB8TIME_IRDYDLY CS0n Input Ready Delay [25:24] HB16TIME EPI Host-Bus 16 Timing Extension EPI_ALT16 0x00000310 EPI_HB16TIME_RDWSM Read Wait State Minus One [0:0] EPI_HB16TIME_WRWSM Write Wait State Minus One [4:4] EPI_HB16TIME_CAPWIDTH CS0n Inter-transfer Capture Width [13:12] EPI_HB16TIME_PSRAMSZ PSRAM Row Size [18:16] EPI_HB16TIME_PSRAMSZ_0 No row size limitation 0x0 EPI_HB16TIME_PSRAMSZ_128B 128 B 0x1 EPI_HB16TIME_PSRAMSZ_256B 256 B 0x2 EPI_HB16TIME_PSRAMSZ_512B 512 B 0x3 EPI_HB16TIME_PSRAMSZ_1KB 1024 B 0x4 EPI_HB16TIME_PSRAMSZ_2KB 2048 B 0x5 EPI_HB16TIME_PSRAMSZ_4KB 4096 B 0x6 EPI_HB16TIME_PSRAMSZ_8KB 8192 B 0x7 EPI_HB16TIME_IRDYDLY CS0n Input Ready Delay [25:24] HB8TIME2 EPI Host-Bus 8 Timing Extension 0x00000314 EPI_HB8TIME2_RDWSM CS1n Read Wait State Minus One [0:0] EPI_HB8TIME2_WRWSM CS1n Write Wait State Minus One [4:4] EPI_HB8TIME2_CAPWIDTH CS1n Inter-transfer Capture Width [13:12] EPI_HB8TIME2_IRDYDLY CS1n Input Ready Delay [25:24] HB16TIME2 EPI Host-Bus 16 Timing Extension EPI_ALT16 0x00000314 EPI_HB16TIME2_RDWSM CS1n Read Wait State Minus One [0:0] EPI_HB16TIME2_WRWSM CS1n Write Wait State Minus One [4:4] EPI_HB16TIME2_CAPWIDTH CS1n Inter-transfer Capture Width [13:12] EPI_HB16TIME2_PSRAMSZ PSRAM Row Size [18:16] EPI_HB16TIME2_PSRAMSZ_0 No row size limitation 0x0 EPI_HB16TIME2_PSRAMSZ_128B 128 B 0x1 EPI_HB16TIME2_PSRAMSZ_256B 256 B 0x2 EPI_HB16TIME2_PSRAMSZ_512B 512 B 0x3 EPI_HB16TIME2_PSRAMSZ_1KB 1024 B 0x4 EPI_HB16TIME2_PSRAMSZ_2KB 2048 B 0x5 EPI_HB16TIME2_PSRAMSZ_4KB 4096 B 0x6 EPI_HB16TIME2_PSRAMSZ_8KB 8192 B 0x7 EPI_HB16TIME2_IRDYDLY CS1n Input Ready Delay [25:24] HB16TIME3 EPI Host-Bus 16 Timing Extension 0x00000318 EPI_HB16TIME3_RDWSM CS2n Read Wait State Minus One [0:0] EPI_HB16TIME3_WRWSM CS2n Write Wait State Minus One [4:4] EPI_HB16TIME3_CAPWIDTH CS2n Inter-transfer Capture Width [13:12] EPI_HB16TIME3_PSRAMSZ PSRAM Row Size [18:16] EPI_HB16TIME3_PSRAMSZ_0 No row size limitation 0x0 EPI_HB16TIME3_PSRAMSZ_128B 128 B 0x1 EPI_HB16TIME3_PSRAMSZ_256B 256 B 0x2 EPI_HB16TIME3_PSRAMSZ_512B 512 B 0x3 EPI_HB16TIME3_PSRAMSZ_1KB 1024 B 0x4 EPI_HB16TIME3_PSRAMSZ_2KB 2048 B 0x5 EPI_HB16TIME3_PSRAMSZ_4KB 4096 B 0x6 EPI_HB16TIME3_PSRAMSZ_8KB 8192 B 0x7 EPI_HB16TIME3_IRDYDLY CS2n Input Ready Delay [25:24] HB8TIME3 EPI Host-Bus 8 Timing Extension EPI_ALT8 0x00000318 EPI_HB8TIME3_RDWSM CS2n Read Wait State Minus One [0:0] EPI_HB8TIME3_WRWSM CS2n Write Wait State Minus One [4:4] EPI_HB8TIME3_CAPWIDTH CS2n Inter-transfer Capture Width [13:12] EPI_HB8TIME3_IRDYDLY CS2n Input Ready Delay [25:24] HB8TIME4 EPI Host-Bus 8 Timing Extension EPI_ALT8 0x0000031C EPI_HB8TIME4_RDWSM CS3n Read Wait State Minus One [0:0] EPI_HB8TIME4_WRWSM CS3n Write Wait State Minus One [4:4] EPI_HB8TIME4_CAPWIDTH CS3n Inter-transfer Capture Width [13:12] EPI_HB8TIME4_IRDYDLY CS3n Input Ready Delay [25:24] HB16TIME4 EPI Host-Bus 16 Timing Extension 0x0000031C EPI_HB16TIME4_RDWSM CS3n Read Wait State Minus One [0:0] EPI_HB16TIME4_WRWSM CS3n Write Wait State Minus One [4:4] EPI_HB16TIME4_CAPWIDTH CS3n Inter-transfer Capture Width [13:12] EPI_HB16TIME4_PSRAMSZ PSRAM Row Size [18:16] EPI_HB16TIME4_PSRAMSZ_0 No row size limitation 0x0 EPI_HB16TIME4_PSRAMSZ_128B 128 B 0x1 EPI_HB16TIME4_PSRAMSZ_256B 256 B 0x2 EPI_HB16TIME4_PSRAMSZ_512B 512 B 0x3 EPI_HB16TIME4_PSRAMSZ_1KB 1024 B 0x4 EPI_HB16TIME4_PSRAMSZ_2KB 2048 B 0x5 EPI_HB16TIME4_PSRAMSZ_4KB 4096 B 0x6 EPI_HB16TIME4_PSRAMSZ_8KB 8192 B 0x7 EPI_HB16TIME4_IRDYDLY CS3n Input Ready Delay [25:24] HBPSRAM EPI Host-Bus PSRAM 0x00000360 EPI_HBPSRAM_CR PSRAM Config Register [20:0] TIMER6 TIMER6 0x400E0000 TIMER6A98 TIMER6B99 TIMER7 TIMER7 0x400E1000 TIMER7A100 TIMER7B101 EMAC0 Register map for EMAC0 peripheral MAC EMAC0 0x400EC000 0 0x00001000 registers EMAC040 CFG Ethernet MAC Configuration 0x00000000 EMAC_CFG_PRELEN Preamble Length for Transmit Frames [1:0] EMAC_CFG_PRELEN_7 7 bytes of preamble 0x0 EMAC_CFG_PRELEN_5 5 bytes of preamble 0x1 EMAC_CFG_PRELEN_3 3 bytes of preamble 0x2 EMAC_CFG_RE Receiver Enable [2:2] EMAC_CFG_TE Transmitter Enable [3:3] EMAC_CFG_DC Deferral Check [4:4] EMAC_CFG_BL Back-Off Limit [6:5] EMAC_CFG_BL_1024 k = min (n,10) 0x0 EMAC_CFG_BL_256 k = min (n,8) 0x1 EMAC_CFG_BL_8 k = min (n,4) 0x2 EMAC_CFG_BL_2 k = min (n,1) 0x3 EMAC_CFG_ACS Automatic Pad or CRC Stripping [7:7] EMAC_CFG_DR Disable Retry [9:9] EMAC_CFG_IPC Checksum Offload [10:10] EMAC_CFG_DUPM Duplex Mode [11:11] EMAC_CFG_LOOPBM Loopback Mode [12:12] EMAC_CFG_DRO Disable Receive Own [13:13] EMAC_CFG_FES Speed [14:14] EMAC_CFG_PS Port Select [15:15] EMAC_CFG_DISCRS Disable Carrier Sense During Transmission [16:16] EMAC_CFG_IFG Inter-Frame Gap (IFG) [19:17] EMAC_CFG_IFG_96 96 bit times 0x0 EMAC_CFG_IFG_88 88 bit times 0x1 EMAC_CFG_IFG_80 80 bit times 0x2 EMAC_CFG_IFG_72 72 bit times 0x3 EMAC_CFG_IFG_64 64 bit times 0x4 EMAC_CFG_IFG_56 56 bit times 0x5 EMAC_CFG_IFG_48 48 bit times 0x6 EMAC_CFG_IFG_40 40 bit times 0x7 EMAC_CFG_JFEN Jumbo Frame Enable [20:20] EMAC_CFG_JD Jabber Disable [22:22] EMAC_CFG_WDDIS Watchdog Disable [23:23] EMAC_CFG_CST CRC Stripping for Type Frames [25:25] EMAC_CFG_TWOKPEN IEEE 802 [27:27] FRAMEFLTR Ethernet MAC Frame Filter 0x00000004 EMAC_FRAMEFLTR_PR Promiscuous Mode [0:0] EMAC_FRAMEFLTR_HUC Hash Unicast [1:1] EMAC_FRAMEFLTR_HMC Hash Multicast [2:2] EMAC_FRAMEFLTR_DAIF Destination Address (DA) Inverse Filtering [3:3] EMAC_FRAMEFLTR_PM Pass All Multicast [4:4] EMAC_FRAMEFLTR_DBF Disable Broadcast Frames [5:5] EMAC_FRAMEFLTR_PCF Pass Control Frames [7:6] EMAC_FRAMEFLTR_PCF_ALL The MAC filters all control frames from reaching application 0x0 EMAC_FRAMEFLTR_PCF_PAUSE MAC forwards all control frames except PAUSE control frames to application even if they fail the address filter 0x1 EMAC_FRAMEFLTR_PCF_NONE MAC forwards all control frames to application even if they fail the address Filter 0x2 EMAC_FRAMEFLTR_PCF_ADDR MAC forwards control frames that pass the address Filter 0x3 EMAC_FRAMEFLTR_SAIF Source Address (SA) Inverse Filtering [8:8] EMAC_FRAMEFLTR_SAF Source Address Filter Enable [9:9] EMAC_FRAMEFLTR_HPF Hash or Perfect Filter [10:10] EMAC_FRAMEFLTR_VTFE VLAN Tag Filter Enable [16:16] EMAC_FRAMEFLTR_RA Receive All [31:31] HASHTBLH Ethernet MAC Hash Table High 0x00000008 EMAC_HASHTBLH_HTH Hash Table High [31:0] HASHTBLL Ethernet MAC Hash Table Low 0x0000000C EMAC_HASHTBLL_HTL Hash Table Low [31:0] MIIADDR Ethernet MAC MII Address 0x00000010 EMAC_MIIADDR_MIIB MII Busy [0:0] EMAC_MIIADDR_MIIW MII Write [1:1] EMAC_MIIADDR_CR Clock Reference Frequency Selection [5:2] EMAC_MIIADDR_CR_60_100 The frequency of the System Clock is 60 to 100 MHz providing a MDIO clock of SYSCLK/42 0x0 EMAC_MIIADDR_CR_100_150 The frequency of the System Clock is 100 to 150 MHz providing a MDIO clock of SYSCLK/62 0x1 EMAC_MIIADDR_CR_20_35 The frequency of the System Clock is 20-35 MHz providing a MDIO clock of System Clock/16 0x2 EMAC_MIIADDR_CR_35_60 The frequency of the System Clock is 35 to 60 MHz providing a MDIO clock of System Clock/26 0x3 EMAC_MIIADDR_MII MII Register [10:6] EMAC_MIIADDR_PLA Physical Layer Address [15:11] MIIDATA Ethernet MAC MII Data Register 0x00000014 EMAC_MIIDATA_DATA MII Data [15:0] FLOWCTL Ethernet MAC Flow Control 0x00000018 EMAC_FLOWCTL_FCBBPA Flow Control Busy or Back-pressure Activate [0:0] EMAC_FLOWCTL_TFE Transmit Flow Control Enable [1:1] EMAC_FLOWCTL_RFE Receive Flow Control Enable [2:2] EMAC_FLOWCTL_UP Unicast Pause Frame Detect [3:3] EMAC_FLOWCTL_PLT Pause Low Threshold [5:4] EMAC_FLOWCTL_PLT_4 The threshold is Pause time minus 4 slot times (PT - 4 slot times) 0x0 EMAC_FLOWCTL_PLT_28 The threshold is Pause time minus 28 slot times (PT - 28 slot times) 0x1 EMAC_FLOWCTL_PLT_144 The threshold is Pause time minus 144 slot times (PT - 144 slot times) 0x2 EMAC_FLOWCTL_PLT_156 The threshold is Pause time minus 256 slot times (PT - 256 slot times) 0x3 EMAC_FLOWCTL_DZQP Disable Zero-Quanta Pause [7:7] EMAC_FLOWCTL_PT Pause Time [31:16] VLANTG Ethernet MAC VLAN Tag 0x0000001C EMAC_VLANTG_VL VLAN Tag Identifier for Receive Frames [15:0] EMAC_VLANTG_ETV Enable 12-Bit VLAN Tag Comparison [16:16] EMAC_VLANTG_VTIM VLAN Tag Inverse Match Enable [17:17] EMAC_VLANTG_ESVL Enable S-VLAN [18:18] EMAC_VLANTG_VTHM VLAN Tag Hash Table Match Enable [19:19] STATUS Ethernet MAC Status 0x00000024 EMAC_STATUS_RPE MAC MII Receive Protocol Engine Status [0:0] EMAC_STATUS_RFCFC MAC Receive Frame Controller FIFO Status [2:1] EMAC_STATUS_RWC TX/RX Controller RX FIFO Write Controller Active Status [4:4] EMAC_STATUS_RRC TX/RX Controller Read Controller State [6:5] EMAC_STATUS_RRC_IDLE IDLE state 0x0 EMAC_STATUS_RRC_STATUS Reading frame data 0x1 EMAC_STATUS_RRC_DATA Reading frame status (or timestamp) 0x2 EMAC_STATUS_RRC_FLUSH Flushing the frame data and status 0x3 EMAC_STATUS_RXF TX/RX Controller RX FIFO Fill-level Status [9:8] EMAC_STATUS_RXF_EMPTY RX FIFO Empty 0x0 EMAC_STATUS_RXF_BELOW RX FIFO fill level is below the flow-control deactivate threshold 0x1 EMAC_STATUS_RXF_ABOVE RX FIFO fill level is above the flow-control activate threshold 0x2 EMAC_STATUS_RXF_FULL RX FIFO Full 0x3 EMAC_STATUS_TPE MAC MII Transmit Protocol Engine Status [16:16] EMAC_STATUS_TFC MAC Transmit Frame Controller Status [18:17] EMAC_STATUS_TFC_IDLE IDLE state 0x0 EMAC_STATUS_TFC_STATUS Waiting for status of previous frame or IFG or backoff period to be over 0x1 EMAC_STATUS_TFC_PAUSE Generating and transmitting a PAUSE control frame (in the full-duplex mode) 0x2 EMAC_STATUS_TFC_INPUT Transferring input frame for transmission 0x3 EMAC_STATUS_TXPAUSED MAC Transmitter PAUSE [19:19] EMAC_STATUS_TRC TX/RX Controller's TX FIFO Read Controller Status [21:20] EMAC_STATUS_TRC_IDLE IDLE state 0x0 EMAC_STATUS_TRC_READ READ state (transferring data to MAC transmitter) 0x1 EMAC_STATUS_TRC_WAIT Waiting for TX Status from MAC transmitter 0x2 EMAC_STATUS_TRC_WRFLUSH Writing the received TX Status or flushing the TX FIFO 0x3 EMAC_STATUS_TWC TX/RX Controller TX FIFO Write Controller Active Status [22:22] EMAC_STATUS_TXFE TX/RX Controller TX FIFO Not Empty Status [24:24] EMAC_STATUS_TXFF TX/RX Controller TX FIFO Full Status [25:25] RWUFF Ethernet MAC Remote Wake-Up Frame Filter 0x00000028 EMAC_RWUFF_WAKEUPFIL Remote Wake-Up Frame Filter [31:0] PMTCTLSTAT Ethernet MAC PMT Control and Status Register 0x0000002C EMAC_PMTCTLSTAT_PWRDWN Power Down [0:0] EMAC_PMTCTLSTAT_MGKPKTEN Magic Packet Enable [1:1] EMAC_PMTCTLSTAT_WUPFREN Wake-Up Frame Enable [2:2] EMAC_PMTCTLSTAT_MGKPRX Magic Packet Received [5:5] EMAC_PMTCTLSTAT_WUPRX Wake-Up Frame Received [6:6] EMAC_PMTCTLSTAT_GLBLUCAST Global Unicast [9:9] EMAC_PMTCTLSTAT_RWKPTR Remote Wake-Up FIFO Pointer [26:24] EMAC_PMTCTLSTAT_WUPFRRST Wake-Up Frame Filter Register Pointer Reset [31:31] LPICTLSTAT Ethernet MAC Low Power Idle Control and Status Register 0x00000030 EMAC_LPICTLSTAT_TLPIEN Transmit LPI Entry [0:0] EMAC_LPICTLSTAT_TLPIEX Transmit LPI Exit [1:1] EMAC_LPICTLSTAT_RLPIEN Receive LPI Entry [2:2] EMAC_LPICTLSTAT_RLPIEX Receive LPI Exit [3:3] EMAC_LPICTLSTAT_TLPIST Transmit LPI State [8:8] EMAC_LPICTLSTAT_RLPIST Receive LPI State [9:9] EMAC_LPICTLSTAT_LPIEN LPI Enable [16:16] EMAC_LPICTLSTAT_PLS PHY Link Status [17:17] EMAC_LPICTLSTAT_PLSEN PHY Link Status Enable [18:18] EMAC_LPICTLSTAT_LPITXA LPI TX Automate [19:19] LPITIMERCTL Ethernet MAC Low Power Idle Timer Control Register 0x00000034 EMAC_LPITIMERCTL_TWT LPI TW Timer [15:0] EMAC_LPITIMERCTL_LST LPI LS Timer [25:16] RIS Ethernet MAC Raw Interrupt Status 0x00000038 EMAC_RIS_PMT PMT Interrupt Status [3:3] EMAC_RIS_MMC MMC Interrupt Status [4:4] EMAC_RIS_MMCRX MMC Receive Interrupt Status [5:5] EMAC_RIS_MMCTX MMC Transmit Interrupt Status [6:6] EMAC_RIS_TS Timestamp Interrupt Status [9:9] EMAC_RIS_LPI LPI Interrupt Status [10:10] IM Ethernet MAC Interrupt Mask 0x0000003C EMAC_IM_PMT PMT Interrupt Mask [3:3] EMAC_IM_TSI Timestamp Interrupt Mask [9:9] EMAC_IM_LPII LPI Interrupt Mask [10:10] ADDR0H Ethernet MAC Address 0 High 0x00000040 EMAC_ADDR0H_ADDRHI MAC Address0 [47:32] [15:0] EMAC_ADDR0H_AE Address Enable [31:31] ADDR0L Ethernet MAC Address 0 Low Register 0x00000044 EMAC_ADDR0L_ADDRLO MAC Address0 [31:0] [31:0] ADDR1H Ethernet MAC Address 1 High 0x00000048 EMAC_ADDR1H_ADDRHI MAC Address1 [47:32] [15:0] EMAC_ADDR1H_MBC Mask Byte Control [29:24] EMAC_ADDR1H_SA Source Address [30:30] EMAC_ADDR1H_AE Address Enable [31:31] ADDR1L Ethernet MAC Address 1 Low 0x0000004C EMAC_ADDR1L_ADDRLO MAC Address1 [31:0] [31:0] ADDR2H Ethernet MAC Address 2 High 0x00000050 EMAC_ADDR2H_ADDRHI MAC Address2 [47:32] [15:0] EMAC_ADDR2H_MBC Mask Byte Control [29:24] EMAC_ADDR2H_SA Source Address [30:30] EMAC_ADDR2H_AE Address Enable [31:31] ADDR2L Ethernet MAC Address 2 Low 0x00000054 EMAC_ADDR2L_ADDRLO MAC Address2 [31:0] [31:0] ADDR3H Ethernet MAC Address 3 High 0x00000058 EMAC_ADDR3H_ADDRHI MAC Address3 [47:32] [15:0] EMAC_ADDR3H_MBC Mask Byte Control [29:24] EMAC_ADDR3H_SA Source Address [30:30] EMAC_ADDR3H_AE Address Enable [31:31] ADDR3L Ethernet MAC Address 3 Low 0x0000005C EMAC_ADDR3L_ADDRLO MAC Address3 [31:0] [31:0] WDOGTO Ethernet MAC Watchdog Timeout 0x000000DC EMAC_WDOGTO_WTO Watchdog Timeout [13:0] EMAC_WDOGTO_PWE Programmable Watchdog Enable [16:16] MMCCTRL Ethernet MAC MMC Control 0x00000100 EMAC_MMCCTRL_CNTRST Counters Reset [0:0] EMAC_MMCCTRL_CNTSTPRO Counters Stop Rollover [1:1] EMAC_MMCCTRL_RSTONRD Reset on Read [2:2] EMAC_MMCCTRL_CNTFREEZ MMC Counter Freeze [3:3] EMAC_MMCCTRL_CNTPRST Counters Preset [4:4] EMAC_MMCCTRL_CNTPRSTLVL Full/Half Preset Level Value [5:5] EMAC_MMCCTRL_UCDBC Update MMC Counters for Dropped Broadcast Frames [8:8] MMCRXRIS Ethernet MAC MMC Receive Raw Interrupt Status 0x00000104 EMAC_MMCRXRIS_GBF MMC Receive Good Bad Frame Counter Interrupt Status [0:0] EMAC_MMCRXRIS_CRCERR MMC Receive CRC Error Frame Counter Interrupt Status [5:5] EMAC_MMCRXRIS_ALGNERR MMC Receive Alignment Error Frame Counter Interrupt Status [6:6] EMAC_MMCRXRIS_UCGF MMC Receive Unicast Good Frame Counter Interrupt Status [17:17] MMCTXRIS Ethernet MAC MMC Transmit Raw Interrupt Status 0x00000108 EMAC_MMCTXRIS_GBF MMC Transmit Good Bad Frame Counter Interrupt Status [1:1] EMAC_MMCTXRIS_SCOLLGF MMC Transmit Single Collision Good Frame Counter Interrupt Status [14:14] EMAC_MMCTXRIS_MCOLLGF MMC Transmit Multiple Collision Good Frame Counter Interrupt Status [15:15] EMAC_MMCTXRIS_OCTCNT Octet Counter Interrupt Status [20:20] MMCRXIM Ethernet MAC MMC Receive Interrupt Mask 0x0000010C EMAC_MMCRXIM_GBF MMC Receive Good Bad Frame Counter Interrupt Mask [0:0] EMAC_MMCRXIM_CRCERR MMC Receive CRC Error Frame Counter Interrupt Mask [5:5] EMAC_MMCRXIM_ALGNERR MMC Receive Alignment Error Frame Counter Interrupt Mask [6:6] EMAC_MMCRXIM_UCGF MMC Receive Unicast Good Frame Counter Interrupt Mask [17:17] MMCTXIM Ethernet MAC MMC Transmit Interrupt Mask 0x00000110 EMAC_MMCTXIM_GBF MMC Transmit Good Bad Frame Counter Interrupt Mask [1:1] EMAC_MMCTXIM_SCOLLGF MMC Transmit Single Collision Good Frame Counter Interrupt Mask [14:14] EMAC_MMCTXIM_MCOLLGF MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask [15:15] EMAC_MMCTXIM_OCTCNT MMC Transmit Good Octet Counter Interrupt Mask [20:20] TXCNTGB Ethernet MAC Transmit Frame Count for Good and Bad Frames 0x00000118 EMAC_TXCNTGB_TXFRMGB This field indicates the number of good and bad frames transmitted, exclusive of retried frames [31:0] TXCNTSCOL Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision 0x0000014C EMAC_TXCNTSCOL_TXSNGLCOLG This field indicates the number of successfully transmitted frames after a single collision in the half-duplex mode [31:0] TXCNTMCOL Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions 0x00000150 EMAC_TXCNTMCOL_TXMULTCOLG This field indicates the number of successfully transmitted frames after multiple collisions in the half-duplex mode [31:0] TXOCTCNTG Ethernet MAC Transmit Octet Count Good 0x00000164 EMAC_TXOCTCNTG_TXOCTG This field indicates the number of bytes transmitted, exclusive of preamble, in good frames [31:0] RXCNTGB Ethernet MAC Receive Frame Count for Good and Bad Frames 0x00000180 EMAC_RXCNTGB_RXFRMGB This field indicates the number of received good and bad frames [31:0] RXCNTCRCERR Ethernet MAC Receive Frame Count for CRC Error Frames 0x00000194 EMAC_RXCNTCRCERR_RXCRCERR This field indicates the number of frames received with CRC error [31:0] RXCNTALGNERR Ethernet MAC Receive Frame Count for Alignment Error Frames 0x00000198 EMAC_RXCNTALGNERR_RXALGNERR This field indicates the number of frames received with alignment (dribble) error [31:0] RXCNTGUNI Ethernet MAC Receive Frame Count for Good Unicast Frames 0x000001C4 EMAC_RXCNTGUNI_RXUCASTG This field indicates the number of received good unicast frames [31:0] VLNINCREP Ethernet MAC VLAN Tag Inclusion or Replacement 0x00000584 EMAC_VLNINCREP_VLT VLAN Tag for Transmit Frames [15:0] EMAC_VLNINCREP_VLC VLAN Tag Control in Transmit Frames [17:16] EMAC_VLNINCREP_VLC_NONE No VLAN tag deletion, insertion, or replacement 0x0 EMAC_VLNINCREP_VLC_TAGDEL VLAN tag deletion 0x1 EMAC_VLNINCREP_VLC_TAGINS VLAN tag insertion 0x2 EMAC_VLNINCREP_VLC_TAGREP VLAN tag replacement 0x3 EMAC_VLNINCREP_VLP VLAN Priority Control [18:18] EMAC_VLNINCREP_CSVL C-VLAN or S-VLAN [19:19] VLANHASH Ethernet MAC VLAN Hash Table 0x00000588 EMAC_VLANHASH_VLHT VLAN Hash Table [15:0] TIMSTCTRL Ethernet MAC Timestamp Control 0x00000700 EMAC_TIMSTCTRL_TSEN Timestamp Enable [0:0] EMAC_TIMSTCTRL_TSFCUPDT Timestamp Fine or Coarse Update [1:1] EMAC_TIMSTCTRL_TSINIT Timestamp Initialize [2:2] EMAC_TIMSTCTRL_TSUPDT Timestamp Update [3:3] EMAC_TIMSTCTRL_INTTRIG Timestamp Interrupt Trigger Enable [4:4] EMAC_TIMSTCTRL_ADDREGUP Addend Register Update [5:5] EMAC_TIMSTCTRL_ALLF Enable Timestamp For All Frames [8:8] EMAC_TIMSTCTRL_DGTLBIN Timestamp Digital or Binary Rollover Control [9:9] EMAC_TIMSTCTRL_PTPVER2 Enable PTP Packet Processing For Version 2 Format [10:10] EMAC_TIMSTCTRL_PTPETH Enable Processing of PTP Over Ethernet Frames [11:11] EMAC_TIMSTCTRL_PTPIPV6 Enable Processing of PTP Frames Sent Over IPv6-UDP [12:12] EMAC_TIMSTCTRL_PTPIPV4 Enable Processing of PTP Frames Sent over IPv4-UDP [13:13] EMAC_TIMSTCTRL_TSEVNT Enable Timestamp Snapshot for Event Messages [14:14] EMAC_TIMSTCTRL_TSMAST Enable Snapshot for Messages Relevant to Master [15:15] EMAC_TIMSTCTRL_SELPTP Select PTP packets for Taking Snapshots [17:16] EMAC_TIMSTCTRL_PTPFLTR Enable MAC address for PTP Frame Filtering [18:18] SUBSECINC Ethernet MAC Sub-Second Increment 0x00000704 EMAC_SUBSECINC_SSINC Sub-second Increment Value [7:0] TIMSEC Ethernet MAC System Time - Seconds 0x00000708 EMAC_TIMSEC_TSS Timestamp Second [31:0] TIMNANO Ethernet MAC System Time - Nanoseconds 0x0000070C EMAC_TIMNANO_TSSS Timestamp Sub-Seconds [30:0] TIMSECU Ethernet MAC System Time - Seconds Update 0x00000710 EMAC_TIMSECU_TSS Timestamp Second [31:0] TIMNANOU Ethernet MAC System Time - Nanoseconds Update 0x00000714 EMAC_TIMNANOU_TSSS Timestamp Sub-Second [30:0] EMAC_TIMNANOU_ADDSUB Add or subtract time [31:31] TIMADD Ethernet MAC Timestamp Addend 0x00000718 EMAC_TIMADD_TSAR Timestamp Addend Register [31:0] TARGSEC Ethernet MAC Target Time Seconds 0x0000071C EMAC_TARGSEC_TSTR Target Time Seconds Register [31:0] TARGNANO Ethernet MAC Target Time Nanoseconds 0x00000720 EMAC_TARGNANO_TTSLO Target Timestamp Low Register [30:0] EMAC_TARGNANO_TRGTBUSY Target Time Register Busy [31:31] HWORDSEC Ethernet MAC System Time-Higher Word Seconds 0x00000724 EMAC_HWORDSEC_TSHWR Target Timestamp Higher Word Register [15:0] TIMSTAT Ethernet MAC Timestamp Status 0x00000728 EMAC_TIMSTAT_TSSOVF Timestamp Seconds Overflow [0:0] EMAC_TIMSTAT_TSTARGT Timestamp Target Time Reached [1:1] PPSCTRL Ethernet MAC PPS Control 0x0000072C EMAC_PPSCTRL_PPSCTRL EN0PPS Output Frequency Control (PPSCTRL) or Command Control (PPSCMD) [3:0] EMAC_PPSCTRL_PPSCTRL_1HZ When the PPSEN0 bit = 0x0, the EN0PPS signal is 1 pulse of the PTP reference clock.(of width clk_ptp_i) every second 0x0 EMAC_PPSCTRL_PPSCTRL_2HZ When the PPSEN0 bit = 0x0, the binary rollover is 2 Hz, and the digital rollover is 1 Hz 0x1 EMAC_PPSCTRL_PPSCTRL_4HZ When the PPSEN0 bit = 0x0, the binary rollover is 4 Hz, and the digital rollover is 2 Hz 0x2 EMAC_PPSCTRL_PPSCTRL_8HZ When thePPSEN0 bit = 0x0, the binary rollover is 8 Hz, and the digital rollover is 4 Hz, 0x3 EMAC_PPSCTRL_PPSCTRL_16HZ When thePPSEN0 bit = 0x0, the binary rollover is 16 Hz, and the digital rollover is 8 Hz 0x4 EMAC_PPSCTRL_PPSCTRL_32HZ When thePPSEN0 bit = 0x0, the binary rollover is 32 Hz, and the digital rollover is 16 Hz 0x5 EMAC_PPSCTRL_PPSCTRL_64HZ When thePPSEN0 bit = 0x0, the binary rollover is 64 Hz, and the digital rollover is 32 Hz 0x6 EMAC_PPSCTRL_PPSCTRL_128HZ When thePPSEN0 bit = 0x0, the binary rollover is 128 Hz, and the digital rollover is 64 Hz 0x7 EMAC_PPSCTRL_PPSCTRL_256HZ When thePPSEN0 bit = 0x0, the binary rollover is 256 Hz, and the digital rollover is 128 Hz 0x8 EMAC_PPSCTRL_PPSCTRL_512HZ When thePPSEN0 bit = 0x0, the binary rollover is 512 Hz, and the digital rollover is 256 Hz 0x9 EMAC_PPSCTRL_PPSCTRL_1024HZ When the PPSEN0 bit = 0x0, the binary rollover is 1.024 kHz, and the digital rollover is 512 Hz 0xa EMAC_PPSCTRL_PPSCTRL_2048HZ When thePPSEN0 bit = 0x0, the binary rollover is 2.048 kHz, and the digital rollover is 1.024 kHz 0xb EMAC_PPSCTRL_PPSCTRL_4096HZ When thePPSEN0 bit = 0x0, the binary rollover is 4.096 kHz, and the digital rollover is 2.048 kHz 0xc EMAC_PPSCTRL_PPSCTRL_8192HZ When thePPSEN0 bit = 0x0, the binary rollover is 8.192 kHz, and the digital rollover is 4.096 kHz 0xd EMAC_PPSCTRL_PPSCTRL_16384HZ When thePPSEN0 bit = 0x0, the binary rollover is 16.384 kHz, and the digital rollover is 8.092 kHz 0xe EMAC_PPSCTRL_PPSCTRL_32768HZ When thePPSEN0 bit = 0x0, the binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz 0xf EMAC_PPSCTRL_PPSEN0 Flexible PPS Output Mode Enable [4:4] EMAC_PPSCTRL_TRGMODS0 Target Time Register Mode for PPS0 Output [6:5] EMAC_PPSCTRL_TRGMODS0_INTONLY Indicates that the Target Time registers are programmed only for generating the interrupt event 0x0 EMAC_PPSCTRL_TRGMODS0_INTPPS0 Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the EN0PPS output signal 0x2 EMAC_PPSCTRL_TRGMODS0_PPS0ONLY Indicates that the Target Time registers are programmed only for starting or stopping the generation of the EN0PPS output signal. No interrupt is asserted 0x3 PPS0INTVL Ethernet MAC PPS0 Interval 0x00000760 EMAC_PPS0INTVL_PPS0INT PPS0 Output Signal Interval [31:0] PPS0WIDTH Ethernet MAC PPS0 Width 0x00000764 EMAC_PPS0WIDTH EN0PPS Output Signal Width [31:0] DMABUSMOD Ethernet MAC DMA Bus Mode 0x00000C00 EMAC_DMABUSMOD_SWR DMA Software Reset [0:0] EMAC_DMABUSMOD_DA DMA Arbitration Scheme [1:1] EMAC_DMABUSMOD_DSL Descriptor Skip Length [6:2] EMAC_DMABUSMOD_ATDS Alternate Descriptor Size [7:7] EMAC_DMABUSMOD_PBL Programmable Burst Length [13:8] EMAC_DMABUSMOD_PR Priority Ratio [15:14] EMAC_DMABUSMOD_FB Fixed Burst [16:16] EMAC_DMABUSMOD_RPBL RX DMA Programmable Burst Length (PBL) [22:17] EMAC_DMABUSMOD_USP Use Separate Programmable Burst Length (PBL) [23:23] EMAC_DMABUSMOD_8XPBL 8 x Programmable Burst Length (PBL) Mode [24:24] EMAC_DMABUSMOD_AAL Address Aligned Beats [25:25] EMAC_DMABUSMOD_MB Mixed Burst [26:26] EMAC_DMABUSMOD_TXPR Transmit Priority [27:27] EMAC_DMABUSMOD_RIB Rebuild Burst [31:31] TXPOLLD Ethernet MAC Transmit Poll Demand 0x00000C04 write-only EMAC_TXPOLLD_TPD Transmit Poll Demand [31:0] write-only RXPOLLD Ethernet MAC Receive Poll Demand 0x00000C08 write-only EMAC_RXPOLLD_RPD Receive Poll Demand [31:0] write-only RXDLADDR Ethernet MAC Receive Descriptor List Address 0x00000C0C EMAC_RXDLADDR_STRXLIST Start of Receive List [31:2] TXDLADDR Ethernet MAC Transmit Descriptor List Address 0x00000C10 EMAC_TXDLADDR_TXDLADDR Start of Transmit List Base Address [31:2] DMARIS Ethernet MAC DMA Interrupt Status 0x00000C14 EMAC_DMARIS_TI Transmit Interrupt [0:0] EMAC_DMARIS_TPS Transmit Process Stopped [1:1] EMAC_DMARIS_TU Transmit Buffer Unavailable [2:2] EMAC_DMARIS_TJT Transmit Jabber Timeout [3:3] EMAC_DMARIS_OVF Receive Overflow [4:4] EMAC_DMARIS_UNF Transmit Underflow [5:5] EMAC_DMARIS_RI Receive Interrupt [6:6] EMAC_DMARIS_RU Receive Buffer Unavailable [7:7] EMAC_DMARIS_RPS Receive Process Stopped [8:8] EMAC_DMARIS_RWT Receive Watchdog Timeout [9:9] EMAC_DMARIS_ETI Early Transmit Interrupt [10:10] EMAC_DMARIS_FBI Fatal Bus Error Interrupt [13:13] EMAC_DMARIS_ERI Early Receive Interrupt [14:14] EMAC_DMARIS_AIS Abnormal Interrupt Summary [15:15] EMAC_DMARIS_NIS Normal Interrupt Summary [16:16] EMAC_DMARIS_RS Received Process State [19:17] EMAC_DMARIS_RS_STOP Stopped: Reset or stop receive command issued 0x0 EMAC_DMARIS_RS_RUNRXTD Running: Fetching receive transfer descriptor 0x1 EMAC_DMARIS_RS_RUNRXD Running: Waiting for receive packet 0x3 EMAC_DMARIS_RS_SUSPEND Suspended: Receive descriptor unavailable 0x4 EMAC_DMARIS_RS_RUNCRD Running: Closing receive descriptor 0x5 EMAC_DMARIS_RS_TSWS Writing Timestamp 0x6 EMAC_DMARIS_RS_RUNTXD Running: Transferring the receive packet data from receive buffer to host memory 0x7 EMAC_DMARIS_TS Transmit Process State [22:20] EMAC_DMARIS_TS_STOP Stopped; Reset or Stop transmit command processed 0x0 EMAC_DMARIS_TS_RUNTXTD Running; Fetching transmit transfer descriptor 0x1 EMAC_DMARIS_TS_STATUS Running; Waiting for status 0x2 EMAC_DMARIS_TS_RUNTX Running; Reading data from host memory buffer and queuing it to transmit buffer (TX FIFO) 0x3 EMAC_DMARIS_TS_TSTAMP Writing Timestamp 0x4 EMAC_DMARIS_TS_SUSPEND Suspended; Transmit descriptor unavailable or transmit buffer underflow 0x6 EMAC_DMARIS_TS_RUNCTD Running; Closing transmit descriptor 0x7 EMAC_DMARIS_AE Access Error [25:23] EMAC_DMARIS_AE_RXDMAWD Error during RX DMA Write Data Transfer 0x0 EMAC_DMARIS_AE_TXDMARD Error during TX DMA Read Data Transfer 0x3 EMAC_DMARIS_AE_RXDMADW Error during RX DMA Descriptor Write Access 0x4 EMAC_DMARIS_AE_TXDMADW Error during TX DMA Descriptor Write Access 0x5 EMAC_DMARIS_AE_RXDMADR Error during RX DMA Descriptor Read Access 0x6 EMAC_DMARIS_AE_TXDMADR Error during TX DMA Descriptor Read Access 0x7 EMAC_DMARIS_MMC MAC MMC Interrupt [27:27] EMAC_DMARIS_PMT MAC PMT Interrupt Status [28:28] EMAC_DMARIS_TT Timestamp Trigger Interrupt Status [29:29] DMAOPMODE Ethernet MAC DMA Operation Mode 0x00000C18 EMAC_DMAOPMODE_SR Start or Stop Receive [1:1] EMAC_DMAOPMODE_OSF Operate on Second Frame [2:2] EMAC_DMAOPMODE_RTC Receive Threshold Control [4:3] EMAC_DMAOPMODE_RTC_64 64 bytes 0x0 EMAC_DMAOPMODE_RTC_32 32 bytes 0x1 EMAC_DMAOPMODE_RTC_96 96 bytes 0x2 EMAC_DMAOPMODE_RTC_128 128 bytes 0x3 EMAC_DMAOPMODE_DGF Drop Giant Frame Enable [5:5] EMAC_DMAOPMODE_FUF Forward Undersized Good Frames [6:6] EMAC_DMAOPMODE_FEF Forward Error Frames [7:7] EMAC_DMAOPMODE_ST Start or Stop Transmission Command [13:13] EMAC_DMAOPMODE_TTC Transmit Threshold Control [16:14] EMAC_DMAOPMODE_TTC_64 64 bytes 0x0 EMAC_DMAOPMODE_TTC_128 128 bytes 0x1 EMAC_DMAOPMODE_TTC_192 192 bytes 0x2 EMAC_DMAOPMODE_TTC_256 256 bytes 0x3 EMAC_DMAOPMODE_TTC_40 40 bytes 0x4 EMAC_DMAOPMODE_TTC_32 32 bytes 0x5 EMAC_DMAOPMODE_TTC_24 24 bytes 0x6 EMAC_DMAOPMODE_TTC_16 16 bytes 0x7 EMAC_DMAOPMODE_FTF Flush Transmit FIFO [20:20] EMAC_DMAOPMODE_TSF Transmit Store and Forward [21:21] EMAC_DMAOPMODE_DFF Disable Flushing of Received Frames [24:24] EMAC_DMAOPMODE_RSF Receive Store and Forward [25:25] EMAC_DMAOPMODE_DT Disable Dropping of TCP/IP Checksum Error Frames [26:26] DMAIM Ethernet MAC DMA Interrupt Mask Register 0x00000C1C EMAC_DMAIM_TIE Transmit Interrupt Enable [0:0] EMAC_DMAIM_TSE Transmit Stopped Enable [1:1] EMAC_DMAIM_TUE Transmit Buffer Unvailable Enable [2:2] EMAC_DMAIM_TJE Transmit Jabber Timeout Enable [3:3] EMAC_DMAIM_OVE Overflow Interrupt Enable [4:4] EMAC_DMAIM_UNE Underflow Interrupt Enable [5:5] EMAC_DMAIM_RIE Receive Interrupt Enable [6:6] EMAC_DMAIM_RUE Receive Buffer Unavailable Enable [7:7] EMAC_DMAIM_RSE Receive Stopped Enable [8:8] EMAC_DMAIM_RWE Receive Watchdog Timeout Enable [9:9] EMAC_DMAIM_ETE Early Transmit Interrupt Enable [10:10] EMAC_DMAIM_FBE Fatal Bus Error Enable [13:13] EMAC_DMAIM_ERE Early Receive Interrupt Enable [14:14] EMAC_DMAIM_AIE Abnormal Interrupt Summary Enable [15:15] EMAC_DMAIM_NIE Normal Interrupt Summary Enable [16:16] MFBOC Ethernet MAC Missed Frame and Buffer Overflow Counter 0x00000C20 EMAC_MFBOC_MISFRMCNT Missed Frame Counter [15:0] EMAC_MFBOC_MISCNTOVF Overflow bit for Missed Frame Counter [16:16] EMAC_MFBOC_OVFFRMCNT Overflow Frame Counter [27:17] EMAC_MFBOC_OVFCNTOVF Overflow Bit for FIFO Overflow Counter [28:28] RXINTWDT Ethernet MAC Receive Interrupt Watchdog Timer 0x00000C24 EMAC_RXINTWDT_RIWT Receive Interrupt Watchdog Timer Count [7:0] HOSTXDESC Ethernet MAC Current Host Transmit Descriptor 0x00000C48 EMAC_HOSTXDESC_CURTXDESC Host Transmit Descriptor Address Pointer [31:0] HOSRXDESC Ethernet MAC Current Host Receive Descriptor 0x00000C4C EMAC_HOSRXDESC_CURRXDESC Host Receive Descriptor Address Pointer [31:0] HOSTXBA Ethernet MAC Current Host Transmit Buffer Address 0x00000C50 EMAC_HOSTXBA_CURTXBUFA Host Transmit Buffer Address Pointer [31:0] HOSRXBA Ethernet MAC Current Host Receive Buffer Address 0x00000C54 EMAC_HOSRXBA_CURRXBUFA Host Receive Buffer Address Pointer [31:0] PP Ethernet MAC Peripheral Property Register 0x00000FC0 EMAC_PP_PHYTYPE Ethernet PHY Type [2:0] EMAC_PP_PHYTYPE_NONE No PHY 0x0 EMAC_PP_PHYTYPE_1 Snowflake class PHY 0x3 EMAC_PP_MACTYPE Ethernet MAC Type [10:8] PC Ethernet MAC Peripheral Configuration Register 0x00000FC4 EMAC_PC_PHYHOLD Ethernet PHY Hold [0:0] EMAC_PC_ANMODE Auto Negotiation Mode [2:1] EMAC_PC_ANMODE_10HD When ANEN = 0x0, the mode is 10Base-T, Half-Duplex 0x0 EMAC_PC_ANMODE_10FD When ANEN = 0x0, the mode is 10Base-T, Full-Duplex 0x1 EMAC_PC_ANMODE_100HD When ANEN = 0x0, the mode is 100Base-TX, Half-Duplex 0x2 EMAC_PC_ANMODE_100FD When ANEN = 0x0, the mode is 100Base-TX, Full-Duplex 0x3 EMAC_PC_ANEN Auto Negotiation Enable [3:3] EMAC_PC_FASTANSEL Fast Auto Negotiation Select [5:4] EMAC_PC_FASTANEN Fast Auto Negotiation Enable [6:6] EMAC_PC_EXTFD Extended Full Duplex Ability [7:7] EMAC_PC_FASTLUPD FAST Link-Up in Parallel Detect [8:8] EMAC_PC_FASTRXDV Fast RXDV Detection [9:9] EMAC_PC_MDIXEN MDIX Enable [10:10] EMAC_PC_FASTMDIX Fast Auto MDI-X [11:11] EMAC_PC_RBSTMDIX Robust Auto MDI-X [12:12] EMAC_PC_MDISWAP MDI Swap [13:13] EMAC_PC_POLSWAP Polarity Swap [14:14] EMAC_PC_FASTLDMODE Fast Link Down Mode [19:15] EMAC_PC_TDRRUN TDR Auto Run [20:20] EMAC_PC_LRR Link Loss Recovery [21:21] EMAC_PC_ISOMIILL Isolate MII in Link Loss [22:22] EMAC_PC_RXERIDLE RXER Detection During Idle [23:23] EMAC_PC_NIBDETDIS Odd Nibble TXER Detection Disable [24:24] EMAC_PC_DIGRESTART PHY Soft Restart [25:25] EMAC_PC_PINTFS Ethernet Interface Select [30:28] EMAC_PC_PINTFS_IMII MII (default) Used for internal PHY or external PHY connected via MII 0x0 EMAC_PC_PINTFS_RMII RMII: Used for external PHY connected via RMII 0x4 EMAC_PC_PHYEXT PHY Select [31:31] CC Ethernet MAC Clock Configuration Register 0x00000FC8 EMAC_CC_CLKEN EN0RREF_CLK Signal Enable [16:16] EMAC_CC_POL LED Polarity Control [17:17] EMAC_CC_PTPCEN PTP Clock Reference Enable [18:18] EPHYRIS Ethernet PHY Raw Interrupt Status 0x00000FCC EMAC_EPHYRIS_INT Ethernet PHY Raw Interrupt Status [0:0] EPHYIM Ethernet PHY Interrupt Mask 0x00000FD0 EMAC_EPHYIM_INT Ethernet PHY Interrupt Mask [0:0] EPHYMISC Ethernet PHY Masked Interrupt Status and Clear 0x00000FD4 EMAC_EPHYMISC_INT Ethernet PHY Status and Clear register [0:0] SYSEXC Register map for SYSEXC peripheral SYSEXC SYSEXC 0x400F9000 0 0x00001000 registers SYSEXC67 RIS System Exception Raw Interrupt Status 0x00000000 SYSEXC_RIS_FPIDCRIS Floating-Point Input Denormal Exception Raw Interrupt Status [0:0] SYSEXC_RIS_FPDZCRIS Floating-Point Divide By 0 Exception Raw Interrupt Status [1:1] SYSEXC_RIS_FPIOCRIS Floating-Point Invalid Operation Raw Interrupt Status [2:2] SYSEXC_RIS_FPUFCRIS Floating-Point Underflow Exception Raw Interrupt Status [3:3] SYSEXC_RIS_FPOFCRIS Floating-Point Overflow Exception Raw Interrupt Status [4:4] SYSEXC_RIS_FPIXCRIS Floating-Point Inexact Exception Raw Interrupt Status [5:5] IM System Exception Interrupt Mask 0x00000004 SYSEXC_IM_FPIDCIM Floating-Point Input Denormal Exception Interrupt Mask [0:0] SYSEXC_IM_FPDZCIM Floating-Point Divide By 0 Exception Interrupt Mask [1:1] SYSEXC_IM_FPIOCIM Floating-Point Invalid Operation Interrupt Mask [2:2] SYSEXC_IM_FPUFCIM Floating-Point Underflow Exception Interrupt Mask [3:3] SYSEXC_IM_FPOFCIM Floating-Point Overflow Exception Interrupt Mask [4:4] SYSEXC_IM_FPIXCIM Floating-Point Inexact Exception Interrupt Mask [5:5] MIS System Exception Masked Interrupt Status 0x00000008 SYSEXC_MIS_FPIDCMIS Floating-Point Input Denormal Exception Masked Interrupt Status [0:0] SYSEXC_MIS_FPDZCMIS Floating-Point Divide By 0 Exception Masked Interrupt Status [1:1] SYSEXC_MIS_FPIOCMIS Floating-Point Invalid Operation Masked Interrupt Status [2:2] SYSEXC_MIS_FPUFCMIS Floating-Point Underflow Exception Masked Interrupt Status [3:3] SYSEXC_MIS_FPOFCMIS Floating-Point Overflow Exception Masked Interrupt Status [4:4] SYSEXC_MIS_FPIXCMIS Floating-Point Inexact Exception Masked Interrupt Status [5:5] IC System Exception Interrupt Clear 0x0000000C write-only SYSEXC_IC_FPIDCIC Floating-Point Input Denormal Exception Interrupt Clear [0:0] write-only SYSEXC_IC_FPDZCIC Floating-Point Divide By 0 Exception Interrupt Clear [1:1] write-only SYSEXC_IC_FPIOCIC Floating-Point Invalid Operation Interrupt Clear [2:2] write-only SYSEXC_IC_FPUFCIC Floating-Point Underflow Exception Interrupt Clear [3:3] write-only SYSEXC_IC_FPOFCIC Floating-Point Overflow Exception Interrupt Clear [4:4] write-only SYSEXC_IC_FPIXCIC Floating-Point Inexact Exception Interrupt Clear [5:5] write-only HIB Register map for HIB peripheral HIB HIB 0x400FC000 0 0x00001000 registers HIB41 RTCC Hibernation RTC Counter 0x00000000 HIB_RTCC RTC Counter [31:0] RTCM0 Hibernation RTC Match 0 0x00000004 HIB_RTCM0 RTC Match 0 [31:0] RTCLD Hibernation RTC Load 0x0000000C HIB_RTCLD RTC Load [31:0] CTL Hibernation Control 0x00000010 HIB_CTL_RTCEN RTC Timer Enable [0:0] HIB_CTL_HIBREQ Hibernation Request [1:1] HIB_CTL_RTCWEN RTC Wake-up Enable [3:3] HIB_CTL_PINWEN External Wake Pin Enable [4:4] HIB_CTL_CLK32EN Clocking Enable [6:6] HIB_CTL_VABORT Power Cut Abort Enable [7:7] HIB_CTL_VDD3ON VDD Powered [8:8] HIB_CTL_BATWKEN Wake on Low Battery [9:9] HIB_CTL_BATCHK Check Battery Status [10:10] HIB_CTL_VBATSEL Select for Low-Battery Comparator [14:13] HIB_CTL_VBATSEL_1_9V 1.9 Volts 0x0 HIB_CTL_VBATSEL_2_1V 2.1 Volts (default) 0x1 HIB_CTL_VBATSEL_2_3V 2.3 Volts 0x2 HIB_CTL_VBATSEL_2_5V 2.5 Volts 0x3 HIB_CTL_OSCBYP Oscillator Bypass [16:16] HIB_CTL_OSCDRV Oscillator Drive Capability [17:17] HIB_CTL_OSCSEL Oscillator Select [19:19] HIB_CTL_RETCLR GPIO Retention/Clear [30:30] HIB_CTL_WRC Write Complete/Capable [31:31] IM Hibernation Interrupt Mask 0x00000014 HIB_IM_RTCALT0 RTC Alert 0 Interrupt Mask [0:0] HIB_IM_LOWBAT Low Battery Voltage Interrupt Mask [2:2] HIB_IM_EXTW External Wake-Up Interrupt Mask [3:3] HIB_IM_WC External Write Complete/Capable Interrupt Mask [4:4] HIB_IM_PADIOWK Pad I/O Wake-Up Interrupt Mask [5:5] HIB_IM_RSTWK Reset Pad I/O Wake-Up Interrupt Mask [6:6] HIB_IM_VDDFAIL VDD Fail Interrupt Mask [7:7] RIS Hibernation Raw Interrupt Status 0x00000018 HIB_RIS_RTCALT0 RTC Alert 0 Raw Interrupt Status [0:0] HIB_RIS_LOWBAT Low Battery Voltage Raw Interrupt Status [2:2] HIB_RIS_EXTW External Wake-Up Raw Interrupt Status [3:3] HIB_RIS_WC Write Complete/Capable Raw Interrupt Status [4:4] HIB_RIS_PADIOWK Pad I/O Wake-Up Raw Interrupt Status [5:5] HIB_RIS_RSTWK Reset Pad I/O Wake-Up Raw Interrupt Status [6:6] HIB_RIS_VDDFAIL VDD Fail Raw Interrupt Status [7:7] MIS Hibernation Masked Interrupt Status 0x0000001C HIB_MIS_RTCALT0 RTC Alert 0 Masked Interrupt Status [0:0] HIB_MIS_LOWBAT Low Battery Voltage Masked Interrupt Status [2:2] HIB_MIS_EXTW External Wake-Up Masked Interrupt Status [3:3] HIB_MIS_WC Write Complete/Capable Masked Interrupt Status [4:4] HIB_MIS_PADIOWK Pad I/O Wake-Up Interrupt Mask [5:5] HIB_MIS_RSTWK Reset Pad I/O Wake-Up Interrupt Mask [6:6] HIB_MIS_VDDFAIL VDD Fail Interrupt Mask [7:7] IC Hibernation Interrupt Clear 0x00000020 HIB_IC_RTCALT0 RTC Alert0 Masked Interrupt Clear [0:0] HIB_IC_LOWBAT Low Battery Voltage Interrupt Clear [2:2] HIB_IC_EXTW External Wake-Up Interrupt Clear [3:3] HIB_IC_WC Write Complete/Capable Interrupt Clear [4:4] HIB_IC_PADIOWK Pad I/O Wake-Up Interrupt Clear [5:5] HIB_IC_RSTWK Reset Pad I/O Wake-Up Interrupt Clear [6:6] HIB_IC_VDDFAIL VDD Fail Interrupt Clear [7:7] RTCT Hibernation RTC Trim 0x00000024 HIB_RTCT_TRIM RTC Trim Value [15:0] RTCSS Hibernation RTC Sub Seconds 0x00000028 HIB_RTCSS_RTCSSC RTC Sub Seconds Count [14:0] HIB_RTCSS_RTCSSM RTC Sub Seconds Match [30:16] IO Hibernation IO Configuration 0x0000002C HIB_IO_WUUNLK I/O Wake Pad Configuration Enable [0:0] HIB_IO_WURSTEN Reset Wake Source Enable [4:4] HIB_IO_IOWRC I/O Write Complete [31:31] DATA Hibernation Data 0x00000030 HIB_DATA_RTD Hibernation Module NV Data [31:0] CALCTL Hibernation Calendar Control 0x00000300 HIB_CALCTL_CALEN RTC Calendar/Counter Mode Select [0:0] HIB_CALCTL_CAL24 Calendar Mode [2:2] CAL0 Hibernation Calendar 0 0x00000310 HIB_CAL0_SEC Seconds [5:0] HIB_CAL0_MIN Minutes [13:8] HIB_CAL0_HR Hours [20:16] HIB_CAL0_AMPM AM/PM Designation [22:22] HIB_CAL0_VALID Valid Calendar Load [31:31] CAL1 Hibernation Calendar 1 0x00000314 HIB_CAL1_DOM Day of Month [4:0] HIB_CAL1_MON Month [11:8] HIB_CAL1_YEAR Year Value [22:16] HIB_CAL1_DOW Day of Week [26:24] HIB_CAL1_VALID Valid Calendar Load [31:31] CALLD0 Hibernation Calendar Load 0 0x00000320 write-only HIB_CALLD0_SEC Seconds [5:0] write-only HIB_CALLD0_MIN Minutes [13:8] write-only HIB_CALLD0_HR Hours [20:16] write-only HIB_CALLD0_AMPM AM/PM Designation [22:22] write-only CALLD1 Hibernation Calendar Load 0x00000324 write-only HIB_CALLD1_DOM Day of Month [4:0] write-only HIB_CALLD1_MON Month [11:8] write-only HIB_CALLD1_YEAR Year Value [22:16] write-only HIB_CALLD1_DOW Day of Week [26:24] write-only CALM0 Hibernation Calendar Match 0 0x00000330 HIB_CALM0_SEC Seconds [5:0] HIB_CALM0_MIN Minutes [13:8] HIB_CALM0_HR Hours [20:16] HIB_CALM0_AMPM AM/PM Designation [22:22] CALM1 Hibernation Calendar Match 1 0x00000334 HIB_CALM1_DOM Day of Month [4:0] LOCK Hibernation Lock 0x00000360 HIB_LOCK_HIBLOCK HIbernate Lock [31:0] TPCTL HIB Tamper Control 0x00000400 HIB_TPCTL_TPEN Tamper Module Enable [0:0] HIB_TPCTL_TPCLR Tamper Event Clear [4:4] HIB_TPCTL_MEMCLR HIB Memory Clear on Tamper Event [9:8] HIB_TPCTL_MEMCLR_NONE Do not Clear HIB memory on tamper event 0x0 HIB_TPCTL_MEMCLR_LOW32 Clear Lower 32 Bytes of HIB memory on tamper event 0x1 HIB_TPCTL_MEMCLR_HIGH32 Clear upper 32 Bytes of HIB memory on tamper event 0x2 HIB_TPCTL_MEMCLR_ALL Clear all HIB memory on tamper event 0x3 HIB_TPCTL_WAKE Wake from Hibernate on a Tamper Event [11:11] TPSTAT HIB Tamper Status 0x00000404 HIB_TPSTAT_XOSCFAIL External Oscillator Failure [0:0] HIB_TPSTAT_XOSCST External Oscillator Status [1:1] HIB_TPSTAT_STATE Tamper Module Status [3:2] HIB_TPSTAT_STATE_DISABLED Tamper disabled 0x0 HIB_TPSTAT_STATE_CONFIGED Tamper configured 0x1 HIB_TPSTAT_STATE_ERROR Tamper pin event occurred 0x2 TPIO HIB Tamper I/O Control 0x00000410 HIB_TPIO_EN0 TMPR0 Enable [0:0] HIB_TPIO_LEV0 TMPR0 Trigger Level [1:1] HIB_TPIO_PUEN0 TMPR0 Internal Weak Pull-up Enable [2:2] HIB_TPIO_GFLTR0 TMPR0 Glitch Filtering [3:3] HIB_TPIO_EN1 TMPR1Enable [8:8] HIB_TPIO_LEV1 TMPR1 Trigger Level [9:9] HIB_TPIO_PUEN1 TMPR1 Internal Weak Pull-up Enable [10:10] HIB_TPIO_GFLTR1 TMPR1 Glitch Filtering [11:11] HIB_TPIO_EN2 TMPR2 Enable [16:16] HIB_TPIO_LEV2 TMPR2 Trigger Level [17:17] HIB_TPIO_PUEN2 TMPR2 Internal Weak Pull-up Enable [18:18] HIB_TPIO_GFLTR2 TMPR2 Glitch Filtering [19:19] HIB_TPIO_EN3 TMPR3 Enable [24:24] HIB_TPIO_LEV3 TMPR3 Trigger Level [25:25] HIB_TPIO_PUEN3 TMPR3 Internal Weak Pull-up Enable [26:26] HIB_TPIO_GFLTR3 TMPR3 Glitch Filtering [27:27] TPLOG0 HIB Tamper Log 0 0x000004E0 HIB_TPLOG0_TIME Tamper Log Calendar Information [31:0] TPLOG1 HIB Tamper Log 1 0x000004E4 HIB_TPLOG1_TRIG0 Status of TMPR[0] Trigger [0:0] HIB_TPLOG1_TRIG1 Status of TMPR[1] Trigger [1:1] HIB_TPLOG1_TRIG2 Status of TMPR[2] Trigger [2:2] HIB_TPLOG1_TRIG3 Status of TMPR[3] Trigger [3:3] HIB_TPLOG1_XOSC Status of external 32 [16:16] TPLOG2 HIB Tamper Log 2 0x000004E8 HIB_TPLOG2_TIME Tamper Log Calendar Information [31:0] TPLOG3 HIB Tamper Log 3 0x000004EC HIB_TPLOG3_TRIG0 Status of TMPR[0] Trigger [0:0] HIB_TPLOG3_TRIG1 Status of TMPR[1] Trigger [1:1] HIB_TPLOG3_TRIG2 Status of TMPR[2] Trigger [2:2] HIB_TPLOG3_TRIG3 Status of TMPR[3] Trigger [3:3] HIB_TPLOG3_XOSC Status of external 32 [16:16] TPLOG4 HIB Tamper Log 4 0x000004F0 HIB_TPLOG4_TIME Tamper Log Calendar Information [31:0] TPLOG5 HIB Tamper Log 5 0x000004F4 HIB_TPLOG5_TRIG0 Status of TMPR[0] Trigger [0:0] HIB_TPLOG5_TRIG1 Status of TMPR[1] Trigger [1:1] HIB_TPLOG5_TRIG2 Status of TMPR[2] Trigger [2:2] HIB_TPLOG5_TRIG3 Status of TMPR[3] Trigger [3:3] HIB_TPLOG5_XOSC Status of external 32 [16:16] TPLOG6 HIB Tamper Log 6 0x000004F8 HIB_TPLOG6_TIME Tamper Log Calendar Information [31:0] TPLOG7 HIB Tamper Log 7 0x000004FC HIB_TPLOG7_TRIG0 Status of TMPR[0] Trigger [0:0] HIB_TPLOG7_TRIG1 Status of TMPR[1] Trigger [1:1] HIB_TPLOG7_TRIG2 Status of TMPR[2] Trigger [2:2] HIB_TPLOG7_TRIG3 Status of TMPR[3] Trigger [3:3] HIB_TPLOG7_XOSC Status of external 32 [16:16] PP Hibernation Peripheral Properties 0x00000FC0 HIB_PP_WAKENC Wake Pin Presence [0:0] HIB_PP_TAMPER Tamper Pin Presence [1:1] CC Hibernation Clock Control 0x00000FC8 HIB_CC_SYSCLKEN RTCOSC to System Clock Enable [0:0] FLASH_CTRL Register map for FLASH_CTRL peripheral FLASH_CTRL FLASH_CTRL 0x400FD000 0 0x00001000 registers 0x1000 0x00001000 registers FLASH_CTRL29 FMA Flash Memory Address 0x00000000 FLASH_FMA_OFFSET Address Offset [19:0] FMD Flash Memory Data 0x00000004 FLASH_FMD_DATA Data Value [31:0] FMC Flash Memory Control 0x00000008 FLASH_FMC_WRITE Write a Word into Flash Memory [0:0] FLASH_FMC_ERASE Erase a Page of Flash Memory [1:1] FLASH_FMC_MERASE Mass Erase Flash Memory [2:2] FLASH_FMC_COMT Commit Register Value [3:3] FLASH_FMC_WRKEY FLASH write key [31:17] FCRIS Flash Controller Raw Interrupt Status 0x0000000C FLASH_FCRIS_ARIS Access Raw Interrupt Status [0:0] FLASH_FCRIS_PRIS Programming Raw Interrupt Status [1:1] FLASH_FCRIS_ERIS EEPROM Raw Interrupt Status [2:2] FLASH_FCRIS_VOLTRIS Pump Voltage Raw Interrupt Status [9:9] FLASH_FCRIS_INVDRIS Invalid Data Raw Interrupt Status [10:10] FLASH_FCRIS_ERRIS Erase Verify Error Raw Interrupt Status [11:11] FLASH_FCRIS_PROGRIS Program Verify Error Raw Interrupt Status [13:13] FCIM Flash Controller Interrupt Mask 0x00000010 FLASH_FCIM_AMASK Access Interrupt Mask [0:0] FLASH_FCIM_PMASK Programming Interrupt Mask [1:1] FLASH_FCIM_EMASK EEPROM Interrupt Mask [2:2] FLASH_FCIM_VOLTMASK VOLT Interrupt Mask [9:9] FLASH_FCIM_INVDMASK Invalid Data Interrupt Mask [10:10] FLASH_FCIM_ERMASK ERVER Interrupt Mask [11:11] FLASH_FCIM_PROGMASK PROGVER Interrupt Mask [13:13] FCMISC Flash Controller Masked Interrupt Status and Clear 0x00000014 FLASH_FCMISC_AMISC Access Masked Interrupt Status and Clear [0:0] FLASH_FCMISC_PMISC Programming Masked Interrupt Status and Clear [1:1] FLASH_FCMISC_EMISC EEPROM Masked Interrupt Status and Clear [2:2] FLASH_FCMISC_VOLTMISC VOLT Masked Interrupt Status and Clear [9:9] FLASH_FCMISC_INVDMISC Invalid Data Masked Interrupt Status and Clear [10:10] FLASH_FCMISC_ERMISC ERVER Masked Interrupt Status and Clear [11:11] FLASH_FCMISC_PROGMISC PROGVER Masked Interrupt Status and Clear [13:13] FMC2 Flash Memory Control 2 0x00000020 FLASH_FMC2_WRBUF Buffered Flash Memory Write [0:0] FWBVAL Flash Write Buffer Valid 0x00000030 FLASH_FWBVAL_FWB Flash Memory Write Buffer [31:0] FLPEKEY Flash Program/Erase Key 0x0000003C FLASH_FLPEKEY_PEKEY Key Value [15:0] 32 4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 FWBN[%s] Flash Write Buffer n 0x00000100 FLASH_FWBN_DATA Data [31:0] PP Flash Peripheral Properties 0x00000FC0 FLASH_PP_SIZE Flash Size [15:0] FLASH_PP_MAINSS Flash Sector Size of the physical bank [18:16] FLASH_PP_MAINSS_1KB 1 KB 0x0 FLASH_PP_MAINSS_2KB 2 KB 0x1 FLASH_PP_MAINSS_4KB 4 KB 0x2 FLASH_PP_MAINSS_8KB 8 KB 0x3 FLASH_PP_MAINSS_16KB 16 KB 0x4 FLASH_PP_EESS EEPROM Sector Size of the physical bank [22:19] FLASH_PP_EESS_1KB 1 KB 0x0 FLASH_PP_EESS_2KB 2 KB 0x1 FLASH_PP_EESS_4KB 4 KB 0x2 FLASH_PP_EESS_8KB 8 KB 0x3 FLASH_PP_DFA DMA Flash Access [28:28] FLASH_PP_FMM Flash Mirror Mode [29:29] FLASH_PP_PFC Prefetch Buffer Mode [30:30] SSIZE SRAM Size 0x00000FC4 FLASH_SSIZE_SIZE SRAM Size [15:0] CONF Flash Configuration Register 0x00000FC8 FLASH_CONF_FPFOFF Force Prefetch Off [16:16] FLASH_CONF_FPFON Force Prefetch On [17:17] FLASH_CONF_CLRTV Clear Valid Tags [20:20] FLASH_CONF_SPFE Single Prefetch Mode Enable [29:29] FLASH_CONF_FMME Flash Mirror Mode Enable [30:30] ROMSWMAP ROM Software Map 0x00000FCC FLASH_ROMSWMAP_SW0EN ROM SW Region 0 Availability [1:0] FLASH_ROMSWMAP_SW0EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW0EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW1EN ROM SW Region 1 Availability [3:2] FLASH_ROMSWMAP_SW1EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW1EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW2EN ROM SW Region 2 Availability [5:4] FLASH_ROMSWMAP_SW2EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW2EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW3EN ROM SW Region 3 Availability [7:6] FLASH_ROMSWMAP_SW3EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW3EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW4EN ROM SW Region 4 Availability [9:8] FLASH_ROMSWMAP_SW4EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW4EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW5EN ROM SW Region 5 Availability [11:10] FLASH_ROMSWMAP_SW5EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW5EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW6EN ROM SW Region 6 Availability [13:12] FLASH_ROMSWMAP_SW6EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW6EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW7EN ROM SW Region 7 Availability [15:14] FLASH_ROMSWMAP_SW7EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW7EN_CORE Region available to core 0x1 DMASZ Flash DMA Address Size 0x00000FD0 FLASH_DMASZ_SIZE uDMA-accessible Memory Size [17:0] DMAST Flash DMA Starting Address 0x00000FD4 FLASH_DMAST_ADDR Contains the starting address of the flash region accessible by uDMA if the FLASHPP register DFA bit is set [28:11] RVP Reset Vector Pointer 0x000010D4 FLASH_RVP_RV Reset Vector Pointer Address [31:0] BOOTCFG Boot Configuration 0x000011D0 FLASH_BOOTCFG_DBG0 Debug Control 0 [0:0] FLASH_BOOTCFG_DBG1 Debug Control 1 [1:1] FLASH_BOOTCFG_KEY KEY Select [4:4] FLASH_BOOTCFG_EN Boot GPIO Enable [8:8] FLASH_BOOTCFG_POL Boot GPIO Polarity [9:9] FLASH_BOOTCFG_PIN Boot GPIO Pin [12:10] FLASH_BOOTCFG_PIN_0 Pin 0 0x0 FLASH_BOOTCFG_PIN_1 Pin 1 0x1 FLASH_BOOTCFG_PIN_2 Pin 2 0x2 FLASH_BOOTCFG_PIN_3 Pin 3 0x3 FLASH_BOOTCFG_PIN_4 Pin 4 0x4 FLASH_BOOTCFG_PIN_5 Pin 5 0x5 FLASH_BOOTCFG_PIN_6 Pin 6 0x6 FLASH_BOOTCFG_PIN_7 Pin 7 0x7 FLASH_BOOTCFG_PORT Boot GPIO Port [15:13] FLASH_BOOTCFG_PORT_A Port A 0x0 FLASH_BOOTCFG_PORT_B Port B 0x1 FLASH_BOOTCFG_PORT_C Port C 0x2 FLASH_BOOTCFG_PORT_D Port D 0x3 FLASH_BOOTCFG_PORT_E Port E 0x4 FLASH_BOOTCFG_PORT_F Port F 0x5 FLASH_BOOTCFG_PORT_G Port G 0x6 FLASH_BOOTCFG_PORT_H Port H 0x7 FLASH_BOOTCFG_NW Not Written [31:31] USERREG0 User Register 0 0x000011E0 FLASH_USERREG0_DATA User Data [31:0] USERREG1 User Register 1 0x000011E4 FLASH_USERREG1_DATA User Data [31:0] USERREG2 User Register 2 0x000011E8 FLASH_USERREG2_DATA User Data [31:0] USERREG3 User Register 3 0x000011EC FLASH_USERREG3_DATA User Data [31:0] FMPRE0 Flash Memory Protection Read Enable 0 0x00001200 FMPRE1 Flash Memory Protection Read Enable 1 0x00001204 FMPRE2 Flash Memory Protection Read Enable 2 0x00001208 FMPRE3 Flash Memory Protection Read Enable 3 0x0000120C FMPRE4 Flash Memory Protection Read Enable 4 0x00001210 FMPRE5 Flash Memory Protection Read Enable 5 0x00001214 FMPRE6 Flash Memory Protection Read Enable 6 0x00001218 FMPRE7 Flash Memory Protection Read Enable 7 0x0000121C FMPRE8 Flash Memory Protection Read Enable 8 0x00001220 FLASH_FMPRE8_READ_ENABLE Flash Read Enable [31:0] FMPRE9 Flash Memory Protection Read Enable 9 0x00001224 FLASH_FMPRE9_READ_ENABLE Flash Read Enable [31:0] FMPRE10 Flash Memory Protection Read Enable 10 0x00001228 FLASH_FMPRE10_READ_ENABLE Flash Read Enable [31:0] FMPRE11 Flash Memory Protection Read Enable 11 0x0000122C FLASH_FMPRE11_READ_ENABLE Flash Read Enable [31:0] FMPRE12 Flash Memory Protection Read Enable 12 0x00001230 FLASH_FMPRE12_READ_ENABLE Flash Read Enable [31:0] FMPRE13 Flash Memory Protection Read Enable 13 0x00001234 FLASH_FMPRE13_READ_ENABLE Flash Read Enable [31:0] FMPRE14 Flash Memory Protection Read Enable 14 0x00001238 FLASH_FMPRE14_READ_ENABLE Flash Read Enable [31:0] FMPRE15 Flash Memory Protection Read Enable 15 0x0000123C FLASH_FMPRE15_READ_ENABLE Flash Read Enable [31:0] FMPPE0 Flash Memory Protection Program Enable 0 0x00001400 FMPPE1 Flash Memory Protection Program Enable 1 0x00001404 FMPPE2 Flash Memory Protection Program Enable 2 0x00001408 FMPPE3 Flash Memory Protection Program Enable 3 0x0000140C FMPPE4 Flash Memory Protection Program Enable 4 0x00001410 FMPPE5 Flash Memory Protection Program Enable 5 0x00001414 FMPPE6 Flash Memory Protection Program Enable 6 0x00001418 FMPPE7 Flash Memory Protection Program Enable 7 0x0000141C FMPPE8 Flash Memory Protection Program Enable 8 0x00001420 FLASH_FMPPE8_PROG_ENABLE Flash Programming Enable [31:0] FMPPE9 Flash Memory Protection Program Enable 9 0x00001424 FLASH_FMPPE9_PROG_ENABLE Flash Programming Enable [31:0] FMPPE10 Flash Memory Protection Program Enable 10 0x00001428 FLASH_FMPPE10_PROG_ENABLE Flash Programming Enable [31:0] FMPPE11 Flash Memory Protection Program Enable 11 0x0000142C FLASH_FMPPE11_PROG_ENABLE Flash Programming Enable [31:0] FMPPE12 Flash Memory Protection Program Enable 12 0x00001430 FLASH_FMPPE12_PROG_ENABLE Flash Programming Enable [31:0] FMPPE13 Flash Memory Protection Program Enable 13 0x00001434 FLASH_FMPPE13_PROG_ENABLE Flash Programming Enable [31:0] FMPPE14 Flash Memory Protection Program Enable 14 0x00001438 FLASH_FMPPE14_PROG_ENABLE Flash Programming Enable [31:0] FMPPE15 Flash Memory Protection Program Enable 15 0x0000143C FLASH_FMPPE15_PROG_ENABLE Flash Programming Enable [31:0] SYSCTL Register map for SYSCTL peripheral SYSCTL SYSCTL 0x400FE000 0 0x00001000 registers SYSCTL28 DID0 Device Identification 0 0x00000000 SYSCTL_DID0_MIN Minor Revision [7:0] SYSCTL_DID0_MIN_0 Initial device, or a major revision update 0x0 SYSCTL_DID0_MIN_1 First metal layer change 0x1 SYSCTL_DID0_MIN_2 Second metal layer change 0x2 SYSCTL_DID0_MAJ Major Revision [15:8] SYSCTL_DID0_MAJ_REVA Revision A (initial device) 0x0 SYSCTL_DID0_MAJ_REVB Revision B (first base layer revision) 0x1 SYSCTL_DID0_MAJ_REVC Revision C (second base layer revision) 0x2 SYSCTL_DID0_CLASS Device Class [23:16] SYSCTL_DID0_CLASS_MSP432E4 MSP432E4 class microcontrollers 0xc SYSCTL_DID0_VER DID0 Version [30:28] SYSCTL_DID0_VER_1 Second version of the DID0 register format. 0x1 DID1 Device Identification 1 0x00000004 SYSCTL_DID1_QUAL Qualification Status [1:0] SYSCTL_DID1_QUAL_ES Engineering Sample (unqualified) 0x0 SYSCTL_DID1_QUAL_PP Pilot Production (unqualified) 0x1 SYSCTL_DID1_QUAL_FQ Fully Qualified 0x2 SYSCTL_DID1_ROHS RoHS-Compliance [2:2] SYSCTL_DID1_PKG Package Type [4:3] SYSCTL_DID1_PKG_QFP QFP package 0x1 SYSCTL_DID1_PKG_BGA BGA package 0x2 SYSCTL_DID1_TEMP Temperature Range [7:5] SYSCTL_DID1_TEMP_C Commercial temperature range 0x0 SYSCTL_DID1_TEMP_I Industrial temperature range 0x1 SYSCTL_DID1_TEMP_E Extended temperature range 0x2 SYSCTL_DID1_PINCNT Package Pin Count [15:13] SYSCTL_DID1_PINCNT_128 128-pin TQFP package 0x6 SYSCTL_DID1_PINCNT_212 212-pin BGA package 0x7 SYSCTL_DID1_PRTNO Part Number [23:16] SYSCTL_DID1_FAM Family [27:24] SYSCTL_DID1_VER DID1 Version [31:28] PTBOCTL Power-Temp Brown Out Control 0x00000038 SYSCTL_PTBOCTL_VDD_UBOR VDD (VDDS) under BOR Event Action [1:0] SYSCTL_PTBOCTL_VDD_UBOR_NONE No Action 0x0 SYSCTL_PTBOCTL_VDD_UBOR_SYSINT System control interrupt 0x1 SYSCTL_PTBOCTL_VDD_UBOR_NMI NMI 0x2 SYSCTL_PTBOCTL_VDD_UBOR_RST Reset 0x3 SYSCTL_PTBOCTL_VDDA_UBOR VDDA under BOR Event Action [9:8] SYSCTL_PTBOCTL_VDDA_UBOR_NONE No Action 0x0 SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT System control interrupt 0x1 SYSCTL_PTBOCTL_VDDA_UBOR_NMI NMI 0x2 SYSCTL_PTBOCTL_VDDA_UBOR_RST Reset 0x3 RIS Raw Interrupt Status 0x00000050 SYSCTL_RIS_BORRIS Brown-Out Reset Raw Interrupt Status [1:1] SYSCTL_RIS_MOFRIS Main Oscillator Failure Raw Interrupt Status [3:3] SYSCTL_RIS_PLLLRIS PLL Lock Raw Interrupt Status [6:6] SYSCTL_RIS_MOSCPUPRIS MOSC Power Up Raw Interrupt Status [8:8] IMC Interrupt Mask Control 0x00000054 SYSCTL_IMC_BORIM Brown-Out Reset Interrupt Mask [1:1] SYSCTL_IMC_MOFIM Main Oscillator Failure Interrupt Mask [3:3] SYSCTL_IMC_PLLLIM PLL Lock Interrupt Mask [6:6] SYSCTL_IMC_MOSCPUPIM MOSC Power Up Interrupt Mask [8:8] MISC Masked Interrupt Status and Clear 0x00000058 SYSCTL_MISC_BORMIS BOR Masked Interrupt Status [1:1] SYSCTL_MISC_MOFMIS Main Oscillator Failure Masked Interrupt Status [3:3] SYSCTL_MISC_PLLLMIS PLL Lock Masked Interrupt Status [6:6] SYSCTL_MISC_MOSCPUPMIS MOSC Power Up Masked Interrupt Status [8:8] RESC Reset Cause 0x0000005C SYSCTL_RESC_EXT External Reset [0:0] SYSCTL_RESC_POR Power-On Reset [1:1] SYSCTL_RESC_BOR Brown-Out Reset [2:2] SYSCTL_RESC_WDT0 Watchdog Timer 0 Reset [3:3] SYSCTL_RESC_SW Software Reset [4:4] SYSCTL_RESC_WDT1 Watchdog Timer 1 Reset [5:5] SYSCTL_RESC_HIB HIB Reset [6:6] SYSCTL_RESC_HSSR HSSR Reset [12:12] SYSCTL_RESC_MOSCFAIL MOSC Failure Reset [16:16] PWRTC Power-Temperature Cause 0x00000060 SYSCTL_PWRTC_VDD_UBOR VDD Under BOR Status [0:0] SYSCTL_PWRTC_VDDA_UBOR VDDA Under BOR Status [4:4] NMIC NMI Cause Register 0x00000064 SYSCTL_NMIC_EXTERNAL External Pin NMI [0:0] SYSCTL_NMIC_POWER Power/Brown Out Event NMI [2:2] SYSCTL_NMIC_WDT0 Watch Dog Timer (WDT) 0 NMI [3:3] SYSCTL_NMIC_WDT1 Watch Dog Timer (WDT) 1 NMI [5:5] SYSCTL_NMIC_TAMPER Tamper Event NMI [9:9] SYSCTL_NMIC_MOSCFAIL MOSC Failure NMI [16:16] MOSCCTL Main Oscillator Control 0x0000007C SYSCTL_MOSCCTL_CVAL Clock Validation for MOSC [0:0] SYSCTL_MOSCCTL_MOSCIM MOSC Failure Action [1:1] SYSCTL_MOSCCTL_NOXTAL No Crystal Connected [2:2] SYSCTL_MOSCCTL_PWRDN Power Down [3:3] SYSCTL_MOSCCTL_OSCRNG Oscillator Range [4:4] RSCLKCFG Run and Sleep Mode Configuration Register 0x000000B0 SYSCTL_RSCLKCFG_PSYSDIV PLL System Clock Divisor [9:0] SYSCTL_RSCLKCFG_OSYSDIV Oscillator System Clock Divisor [19:10] SYSCTL_RSCLKCFG_OSCSRC Oscillator Source [23:20] SYSCTL_RSCLKCFG_OSCSRC_PIOSC PIOSC is oscillator source 0x0 SYSCTL_RSCLKCFG_OSCSRC_LFIOSC LFIOSC is oscillator source 0x2 SYSCTL_RSCLKCFG_OSCSRC_MOSC MOSC is oscillator source 0x3 SYSCTL_RSCLKCFG_OSCSRC_RTC Hibernation Module RTC Oscillator (RTCOSC) 0x4 SYSCTL_RSCLKCFG_PLLSRC PLL Source [27:24] SYSCTL_RSCLKCFG_PLLSRC_PIOSC PIOSC is PLL input clock source 0x0 SYSCTL_RSCLKCFG_PLLSRC_MOSC MOSC is the PLL input clock source 0x3 SYSCTL_RSCLKCFG_USEPLL Use PLL [28:28] SYSCTL_RSCLKCFG_ACG Auto Clock Gating [29:29] SYSCTL_RSCLKCFG_NEWFREQ New PLLFREQ Accept [30:30] SYSCTL_RSCLKCFG_MEMTIMU Memory Timing Register Update [31:31] MEMTIM0 Memory Timing Parameter Register 0 for Main Flash and EEPROM 0x000000C0 SYSCTL_MEMTIM0_FWS Flash Wait State [3:0] RESERVED0 Value of this reserved bit must be read as 1 [4:4] SYSCTL_MEMTIM0_FBCE Flash Bank Clock Edge [5:5] SYSCTL_MEMTIM0_FBCHT Flash Bank Clock High Time [9:6] SYSCTL_MEMTIM0_FBCHT_0_5 1/2 system clock period 0x0 SYSCTL_MEMTIM0_FBCHT_1 1 system clock period 0x1 SYSCTL_MEMTIM0_FBCHT_1_5 1.5 system clock periods 0x2 SYSCTL_MEMTIM0_FBCHT_2 2 system clock periods 0x3 SYSCTL_MEMTIM0_FBCHT_2_5 2.5 system clock periods 0x4 SYSCTL_MEMTIM0_FBCHT_3 3 system clock periods 0x5 SYSCTL_MEMTIM0_FBCHT_3_5 3.5 system clock periods 0x6 SYSCTL_MEMTIM0_FBCHT_4 4 system clock periods 0x7 SYSCTL_MEMTIM0_FBCHT_4_5 4.5 system clock periods 0x8 SYSCTL_MEMTIM0_EWS EEPROM Wait States [19:16] RESERVED1 Value of this reserved bit must be read as 1 [20:20] SYSCTL_MEMTIM0_EBCE EEPROM Bank Clock Edge [21:21] SYSCTL_MEMTIM0_EBCHT EEPROM Clock High Time [25:22] SYSCTL_MEMTIM0_EBCHT_0_5 1/2 system clock period 0x0 SYSCTL_MEMTIM0_EBCHT_1 1 system clock period 0x1 SYSCTL_MEMTIM0_EBCHT_1_5 1.5 system clock periods 0x2 SYSCTL_MEMTIM0_EBCHT_2 2 system clock periods 0x3 SYSCTL_MEMTIM0_EBCHT_2_5 2.5 system clock periods 0x4 SYSCTL_MEMTIM0_EBCHT_3 3 system clock periods 0x5 SYSCTL_MEMTIM0_EBCHT_3_5 3.5 system clock periods 0x6 SYSCTL_MEMTIM0_EBCHT_4 4 system clock periods 0x7 SYSCTL_MEMTIM0_EBCHT_4_5 4.5 system clock periods 0x8 ALTCLKCFG Alternate Clock Configuration 0x00000138 SYSCTL_ALTCLKCFG_ALTCLK Alternate Clock Source [3:0] SYSCTL_ALTCLKCFG_ALTCLK_PIOSC PIOSC 0x0 SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC Hibernation Module Real-time clock output (RTCOSC) 0x3 SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC Low-frequency internal oscillator (LFIOSC) 0x4 DSCLKCFG Deep Sleep Clock Configuration Register 0x00000144 SYSCTL_DSCLKCFG_DSSYSDIV Deep Sleep Clock Divisor [9:0] SYSCTL_DSCLKCFG_DSOSCSRC Deep Sleep Oscillator Source [23:20] SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC PIOSC 0x0 SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC LFIOSC 0x2 SYSCTL_DSCLKCFG_DSOSCSRC_MOSC MOSC 0x3 SYSCTL_DSCLKCFG_DSOSCSRC_RTC Hibernation Module RTCOSC 0x4 SYSCTL_DSCLKCFG_MOSCDPD MOSC Disable Power Down [30:30] SYSCTL_DSCLKCFG_PIOSCPD PIOSC Power Down [31:31] DIVSCLK Divisor and Source Clock Configuration 0x00000148 SYSCTL_DIVSCLK_DIV Divisor Value [7:0] SYSCTL_DIVSCLK_SRC Clock Source [17:16] SYSCTL_DIVSCLK_SRC_SYSCLK System Clock 0x0 SYSCTL_DIVSCLK_SRC_PIOSC PIOSC 0x1 SYSCTL_DIVSCLK_SRC_MOSC MOSC 0x2 SYSCTL_DIVSCLK_EN DIVSCLK Enable [31:31] SYSPROP System Properties 0x0000014C SYSCTL_SYSPROP_FPU FPU Present [0:0] PIOSCCAL Precision Internal Oscillator Calibration 0x00000150 SYSCTL_PIOSCCAL_UT User Trim Value [6:0] SYSCTL_PIOSCCAL_UPDATE Update Trim [8:8] SYSCTL_PIOSCCAL_CAL Start Calibration [9:9] SYSCTL_PIOSCCAL_UTEN Use User Trim Value [31:31] PIOSCSTAT Precision Internal Oscillator Statistics 0x00000154 SYSCTL_PIOSCSTAT_CT Calibration Trim Value [6:0] SYSCTL_PIOSCSTAT_CR Calibration Result [9:8] SYSCTL_PIOSCSTAT_CRNONE Calibration has not been attempted 0x0 SYSCTL_PIOSCSTAT_CRPASS The last calibration operation completed to meet 1% accuracy 0x1 SYSCTL_PIOSCSTAT_CRFAIL The last calibration operation failed to meet 1% accuracy 0x2 SYSCTL_PIOSCSTAT_DT Default Trim Value [22:16] PLLFREQ0 PLL Frequency 0 0x00000160 SYSCTL_PLLFREQ0_MINT PLL M Integer Value [9:0] SYSCTL_PLLFREQ0_MFRAC PLL M Fractional Value [19:10] SYSCTL_PLLFREQ0_PLLPWR PLL Power [23:23] PLLFREQ1 PLL Frequency 1 0x00000164 SYSCTL_PLLFREQ1_N PLL N Value [4:0] SYSCTL_PLLFREQ1_Q PLL Q Value [12:8] PLLSTAT PLL Status 0x00000168 SYSCTL_PLLSTAT_LOCK PLL Lock [0:0] SLPPWRCFG Sleep Power Configuration 0x00000188 SYSCTL_SLPPWRCFG_SRAMPM SRAM Power Modes [1:0] SYSCTL_SLPPWRCFG_SRAMPM_NRM Active Mode 0x0 SYSCTL_SLPPWRCFG_SRAMPM_SBY Standby Mode 0x1 SYSCTL_SLPPWRCFG_SRAMPM_LP Low Power Mode 0x3 SYSCTL_SLPPWRCFG_FLASHPM Flash Power Modes [5:4] SYSCTL_SLPPWRCFG_FLASHPM_NRM Active Mode 0x0 SYSCTL_SLPPWRCFG_FLASHPM_SLP Low Power Mode 0x2 DSLPPWRCFG Deep-Sleep Power Configuration 0x0000018C SYSCTL_DSLPPWRCFG_SRAMPM SRAM Power Modes [1:0] SYSCTL_DSLPPWRCFG_SRAMPM_NRM Active Mode 0x0 SYSCTL_DSLPPWRCFG_SRAMPM_SBY Standby Mode 0x1 SYSCTL_DSLPPWRCFG_SRAMPM_LP Low Power Mode 0x3 SYSCTL_DSLPPWRCFG_FLASHPM Flash Power Modes [5:4] SYSCTL_DSLPPWRCFG_FLASHPM_NRM Active Mode 0x0 SYSCTL_DSLPPWRCFG_FLASHPM_SLP Low Power Mode 0x2 SYSCTL_DSLPPWRCFG_TSPD Temperature Sense Power Down [8:8] SYSCTL_DSLPPWRCFG_LDOSM LDO Sleep Mode [9:9] NVMSTAT Non-Volatile Memory Information 0x000001A0 SYSCTL_NVMSTAT_FWB 32 Word Flash Write Buffer Available [0:0] LDOSPCTL LDO Sleep Power Control 0x000001B4 SYSCTL_LDOSPCTL_VLDO LDO Output Voltage [7:0] SYSCTL_LDOSPCTL_VLDO_0_90V 0.90 V 0x12 SYSCTL_LDOSPCTL_VLDO_0_95V 0.95 V 0x13 SYSCTL_LDOSPCTL_VLDO_1_00V 1.00 V 0x14 SYSCTL_LDOSPCTL_VLDO_1_05V 1.05 V 0x15 SYSCTL_LDOSPCTL_VLDO_1_10V 1.10 V 0x16 SYSCTL_LDOSPCTL_VLDO_1_15V 1.15 V 0x17 SYSCTL_LDOSPCTL_VLDO_1_20V 1.20 V 0x18 SYSCTL_LDOSPCTL_VADJEN Voltage Adjust Enable [31:31] LDODPCTL LDO Deep-Sleep Power Control 0x000001BC SYSCTL_LDODPCTL_VLDO LDO Output Voltage [7:0] SYSCTL_LDODPCTL_VLDO_0_90V 0.90 V 0x12 SYSCTL_LDODPCTL_VLDO_0_95V 0.95 V 0x13 SYSCTL_LDODPCTL_VLDO_1_00V 1.00 V 0x14 SYSCTL_LDODPCTL_VLDO_1_05V 1.05 V 0x15 SYSCTL_LDODPCTL_VLDO_1_10V 1.10 V 0x16 SYSCTL_LDODPCTL_VLDO_1_15V 1.15 V 0x17 SYSCTL_LDODPCTL_VLDO_1_20V 1.20 V 0x18 SYSCTL_LDODPCTL_VLDO_1_25V 1.25 V 0x19 SYSCTL_LDODPCTL_VLDO_1_30V 1.30 V 0x1a SYSCTL_LDODPCTL_VLDO_1_35V 1.35 V 0x1b SYSCTL_LDODPCTL_VADJEN Voltage Adjust Enable [31:31] RESBEHAVCTL Reset Behavior Control Register 0x000001D8 SYSCTL_RESBEHAVCTL_EXTRES External RST Pin Operation [1:0] SYSCTL_RESBEHAVCTL_EXTRES_SYSRST External RST assertion issues a system reset. The application starts within 10 us 0x2 SYSCTL_RESBEHAVCTL_EXTRES_POR External RST assertion issues a simulated POR sequence. Application starts less than 500 us after deassertion (Default) 0x3 SYSCTL_RESBEHAVCTL_BOR BOR Reset operation [3:2] SYSCTL_RESBEHAVCTL_BOR_SYSRST Brown Out Reset issues system reset. The application starts within 10 us 0x2 SYSCTL_RESBEHAVCTL_BOR_POR Brown Out Reset issues a simulated POR sequence. The application starts less than 500 us after deassertion (Default) 0x3 SYSCTL_RESBEHAVCTL_WDOG0 Watchdog 0 Reset Operation [5:4] SYSCTL_RESBEHAVCTL_WDOG0_SYSRST Watchdog 0 issues a system reset. The application starts within 10 us 0x2 SYSCTL_RESBEHAVCTL_WDOG0_POR Watchdog 0 issues a simulated POR sequence. Application starts less than 500 us after deassertion (Default) 0x3 SYSCTL_RESBEHAVCTL_WDOG1 Watchdog 1 Reset Operation [7:6] SYSCTL_RESBEHAVCTL_WDOG1_SYSRST Watchdog 1 issues a system reset. The application starts within 10 us 0x2 SYSCTL_RESBEHAVCTL_WDOG1_POR Watchdog 1 issues a simulated POR sequence. Application starts less than 500 us after deassertion (Default) 0x3 HSSR Hardware System Service Request 0x000001F4 SYSCTL_HSSR_CDOFF Command Descriptor Pointer [23:0] SYSCTL_HSSR_KEY Write Key [31:24] USBPDS USB Power Domain Status 0x00000280 SYSCTL_USBPDS_PWRSTAT Power Domain Status [1:0] SYSCTL_USBPDS_PWRSTAT_OFF OFF 0x0 SYSCTL_USBPDS_PWRSTAT_ON ON 0x3 SYSCTL_USBPDS_MEMSTAT Memory Array Power Status [3:2] SYSCTL_USBPDS_MEMSTAT_OFF Array OFF 0x0 SYSCTL_USBPDS_MEMSTAT_RETAIN SRAM Retention 0x1 SYSCTL_USBPDS_MEMSTAT_ON Array On 0x3 USBMPC USB Memory Power Control 0x00000284 SYSCTL_USBMPC_PWRCTL Memory Array Power Control [1:0] SYSCTL_USBMPC_PWRCTL_OFF Array OFF 0x0 SYSCTL_USBMPC_PWRCTL_RETAIN SRAM Retention 0x1 SYSCTL_USBMPC_PWRCTL_ON Array On 0x3 EMACPDS Ethernet MAC Power Domain Status 0x00000288 SYSCTL_EMACPDS_PWRSTAT Power Domain Status [1:0] SYSCTL_EMACPDS_PWRSTAT_OFF OFF 0x0 SYSCTL_EMACPDS_PWRSTAT_ON ON 0x3 SYSCTL_EMACPDS_MEMSTAT Memory Array Power Status [3:2] SYSCTL_EMACPDS_MEMSTAT_OFF Array OFF 0x0 SYSCTL_EMACPDS_MEMSTAT_ON Array On 0x3 EMACMPC Ethernet MAC Memory Power Control 0x0000028C SYSCTL_EMACMPC_PWRCTL Memory Array Power Control [1:0] SYSCTL_EMACMPC_PWRCTL_OFF Array OFF 0x0 SYSCTL_EMACMPC_PWRCTL_ON Array On 0x3 LCDMPC LCD Memory Power Control 0x00000294 SYSCTL_LCDMPC_PWRCTL Memory Array Power Control [1:0] SYSCTL_LCDMPC_PWRCTL_OFF Array OFF 0x0 SYSCTL_LCDMPC_PWRCTL_ON Array On 0x3 PPWD Watchdog Timer Peripheral Present 0x00000300 SYSCTL_PPWD_P0 Watchdog Timer 0 Present [0:0] SYSCTL_PPWD_P1 Watchdog Timer 1 Present [1:1] PPTIMER 16/32-Bit General-Purpose Timer Peripheral Present 0x00000304 SYSCTL_PPTIMER_P0 16/32-Bit General-Purpose Timer 0 Present [0:0] SYSCTL_PPTIMER_P1 16/32-Bit General-Purpose Timer 1 Present [1:1] SYSCTL_PPTIMER_P2 16/32-Bit General-Purpose Timer 2 Present [2:2] SYSCTL_PPTIMER_P3 16/32-Bit General-Purpose Timer 3 Present [3:3] SYSCTL_PPTIMER_P4 16/32-Bit General-Purpose Timer 4 Present [4:4] SYSCTL_PPTIMER_P5 16/32-Bit General-Purpose Timer 5 Present [5:5] SYSCTL_PPTIMER_P6 16/32-Bit General-Purpose Timer 6 Present [6:6] SYSCTL_PPTIMER_P7 16/32-Bit General-Purpose Timer 7 Present [7:7] PPGPIO General-Purpose Input/Output Peripheral Present 0x00000308 SYSCTL_PPGPIO_P0 GPIO Port A Present [0:0] SYSCTL_PPGPIO_P1 GPIO Port B Present [1:1] SYSCTL_PPGPIO_P2 GPIO Port C Present [2:2] SYSCTL_PPGPIO_P3 GPIO Port D Present [3:3] SYSCTL_PPGPIO_P4 GPIO Port E Present [4:4] SYSCTL_PPGPIO_P5 GPIO Port F Present [5:5] SYSCTL_PPGPIO_P6 GPIO Port G Present [6:6] SYSCTL_PPGPIO_P7 GPIO Port H Present [7:7] SYSCTL_PPGPIO_P8 GPIO Port J Present [8:8] SYSCTL_PPGPIO_P9 GPIO Port K Present [9:9] SYSCTL_PPGPIO_P10 GPIO Port L Present [10:10] SYSCTL_PPGPIO_P11 GPIO Port M Present [11:11] SYSCTL_PPGPIO_P12 GPIO Port N Present [12:12] SYSCTL_PPGPIO_P13 GPIO Port P Present [13:13] SYSCTL_PPGPIO_P14 GPIO Port Q Present [14:14] SYSCTL_PPGPIO_P15 GPIO Port R Present [15:15] SYSCTL_PPGPIO_P16 GPIO Port S Present [16:16] SYSCTL_PPGPIO_P17 GPIO Port T Present [17:17] PPDMA Micro Direct Memory Access Peripheral Present 0x0000030C SYSCTL_PPDMA_P0 uDMA Module Present [0:0] PPEPI EPI Peripheral Present 0x00000310 SYSCTL_PPEPI_P0 EPI Module Present [0:0] PPHIB Hibernation Peripheral Present 0x00000314 SYSCTL_PPHIB_P0 Hibernation Module Present [0:0] PPUART Universal Asynchronous Receiver/Transmitter Peripheral Present 0x00000318 SYSCTL_PPUART_P0 UART Module 0 Present [0:0] SYSCTL_PPUART_P1 UART Module 1 Present [1:1] SYSCTL_PPUART_P2 UART Module 2 Present [2:2] SYSCTL_PPUART_P3 UART Module 3 Present [3:3] SYSCTL_PPUART_P4 UART Module 4 Present [4:4] SYSCTL_PPUART_P5 UART Module 5 Present [5:5] SYSCTL_PPUART_P6 UART Module 6 Present [6:6] SYSCTL_PPUART_P7 UART Module 7 Present [7:7] PPSSI Synchronous Serial Interface Peripheral Present 0x0000031C SYSCTL_PPSSI_P0 SSI Module 0 Present [0:0] SYSCTL_PPSSI_P1 SSI Module 1 Present [1:1] SYSCTL_PPSSI_P2 SSI Module 2 Present [2:2] SYSCTL_PPSSI_P3 SSI Module 3 Present [3:3] PPI2C Inter-Integrated Circuit Peripheral Present 0x00000320 SYSCTL_PPI2C_P0 I2C Module 0 Present [0:0] SYSCTL_PPI2C_P1 I2C Module 1 Present [1:1] SYSCTL_PPI2C_P2 I2C Module 2 Present [2:2] SYSCTL_PPI2C_P3 I2C Module 3 Present [3:3] SYSCTL_PPI2C_P4 I2C Module 4 Present [4:4] SYSCTL_PPI2C_P5 I2C Module 5 Present [5:5] SYSCTL_PPI2C_P6 I2C Module 6 Present [6:6] SYSCTL_PPI2C_P7 I2C Module 7 Present [7:7] SYSCTL_PPI2C_P8 I2C Module 8 Present [8:8] SYSCTL_PPI2C_P9 I2C Module 9 Present [9:9] PPUSB Universal Serial Bus Peripheral Present 0x00000328 SYSCTL_PPUSB_P0 USB Module Present [0:0] PPEPHY Ethernet PHY Peripheral Present 0x00000330 SYSCTL_PPEPHY_P0 Ethernet PHY Module Present [0:0] PPCAN Controller Area Network Peripheral Present 0x00000334 SYSCTL_PPCAN_P0 CAN Module 0 Present [0:0] SYSCTL_PPCAN_P1 CAN Module 1 Present [1:1] PPADC Analog-to-Digital Converter Peripheral Present 0x00000338 SYSCTL_PPADC_P0 ADC Module 0 Present [0:0] SYSCTL_PPADC_P1 ADC Module 1 Present [1:1] PPACMP Analog Comparator Peripheral Present 0x0000033C SYSCTL_PPACMP_P0 Analog Comparator Module Present [0:0] PPPWM Pulse Width Modulator Peripheral Present 0x00000340 SYSCTL_PPPWM_P0 PWM Module 0 Present [0:0] PPQEI Quadrature Encoder Interface Peripheral Present 0x00000344 SYSCTL_PPQEI_P0 QEI Module 0 Present [0:0] PPEEPROM EEPROM Peripheral Present 0x00000358 SYSCTL_PPEEPROM_P0 EEPROM Module Present [0:0] PPCCM CRC and Cryptographic Modules Peripheral Present 0x00000374 SYSCTL_PPCCM_P0 CRC and Cryptographic Modules Present [0:0] PPLCD LCD Peripheral Present 0x00000390 SYSCTL_PPLCD_P0 LCD Module Present [0:0] PPOWIRE 1-Wire Peripheral Present 0x00000398 SYSCTL_PPOWIRE_P0 1-Wire Module Present [0:0] PPEMAC Ethernet MAC Peripheral Present 0x0000039C SYSCTL_PPEMAC_P0 Ethernet Controller Module Present [0:0] SRWD Watchdog Timer Software Reset 0x00000500 SYSCTL_SRWD_R0 Watchdog Timer 0 Software Reset [0:0] SYSCTL_SRWD_R1 Watchdog Timer 1 Software Reset [1:1] SRTIMER 16/32-Bit General-Purpose Timer Software Reset 0x00000504 SYSCTL_SRTIMER_R0 16/32-Bit General-Purpose Timer 0 Software Reset [0:0] SYSCTL_SRTIMER_R1 16/32-Bit General-Purpose Timer 1 Software Reset [1:1] SYSCTL_SRTIMER_R2 16/32-Bit General-Purpose Timer 2 Software Reset [2:2] SYSCTL_SRTIMER_R3 16/32-Bit General-Purpose Timer 3 Software Reset [3:3] SYSCTL_SRTIMER_R4 16/32-Bit General-Purpose Timer 4 Software Reset [4:4] SYSCTL_SRTIMER_R5 16/32-Bit General-Purpose Timer 5 Software Reset [5:5] SYSCTL_SRTIMER_R6 16/32-Bit General-Purpose Timer 6 Software Reset [6:6] SYSCTL_SRTIMER_R7 16/32-Bit General-Purpose Timer 7 Software Reset [7:7] SRGPIO General-Purpose Input/Output Software Reset 0x00000508 SYSCTL_SRGPIO_R0 GPIO Port A Software Reset [0:0] SYSCTL_SRGPIO_R1 GPIO Port B Software Reset [1:1] SYSCTL_SRGPIO_R2 GPIO Port C Software Reset [2:2] SYSCTL_SRGPIO_R3 GPIO Port D Software Reset [3:3] SYSCTL_SRGPIO_R4 GPIO Port E Software Reset [4:4] SYSCTL_SRGPIO_R5 GPIO Port F Software Reset [5:5] SYSCTL_SRGPIO_R6 GPIO Port G Software Reset [6:6] SYSCTL_SRGPIO_R7 GPIO Port H Software Reset [7:7] SYSCTL_SRGPIO_R8 GPIO Port J Software Reset [8:8] SYSCTL_SRGPIO_R9 GPIO Port K Software Reset [9:9] SYSCTL_SRGPIO_R10 GPIO Port L Software Reset [10:10] SYSCTL_SRGPIO_R11 GPIO Port M Software Reset [11:11] SYSCTL_SRGPIO_R12 GPIO Port N Software Reset [12:12] SYSCTL_SRGPIO_R13 GPIO Port P Software Reset [13:13] SYSCTL_SRGPIO_R14 GPIO Port Q Software Reset [14:14] SYSCTL_SRGPIO_R15 GPIO Port R Software Reset [15:15] SYSCTL_SRGPIO_R16 GPIO Port S Software Reset [16:16] SYSCTL_SRGPIO_R17 GPIO Port T Software Reset [17:17] SRDMA Micro Direct Memory Access Software Reset 0x0000050C SYSCTL_SRDMA_R0 uDMA Module Software Reset [0:0] SREPI EPI Software Reset 0x00000510 SYSCTL_SREPI_R0 EPI Module Software Reset [0:0] SRHIB Hibernation Software Reset 0x00000514 SYSCTL_SRHIB_R0 Hibernation Module Software Reset [0:0] SRUART Universal Asynchronous Receiver/Transmitter Software Reset 0x00000518 SYSCTL_SRUART_R0 UART Module 0 Software Reset [0:0] SYSCTL_SRUART_R1 UART Module 1 Software Reset [1:1] SYSCTL_SRUART_R2 UART Module 2 Software Reset [2:2] SYSCTL_SRUART_R3 UART Module 3 Software Reset [3:3] SYSCTL_SRUART_R4 UART Module 4 Software Reset [4:4] SYSCTL_SRUART_R5 UART Module 5 Software Reset [5:5] SYSCTL_SRUART_R6 UART Module 6 Software Reset [6:6] SYSCTL_SRUART_R7 UART Module 7 Software Reset [7:7] SRSSI Synchronous Serial Interface Software Reset 0x0000051C SYSCTL_SRSSI_R0 SSI Module 0 Software Reset [0:0] SYSCTL_SRSSI_R1 SSI Module 1 Software Reset [1:1] SYSCTL_SRSSI_R2 SSI Module 2 Software Reset [2:2] SYSCTL_SRSSI_R3 SSI Module 3 Software Reset [3:3] SRI2C Inter-Integrated Circuit Software Reset 0x00000520 SYSCTL_SRI2C_R0 I2C Module 0 Software Reset [0:0] SYSCTL_SRI2C_R1 I2C Module 1 Software Reset [1:1] SYSCTL_SRI2C_R2 I2C Module 2 Software Reset [2:2] SYSCTL_SRI2C_R3 I2C Module 3 Software Reset [3:3] SYSCTL_SRI2C_R4 I2C Module 4 Software Reset [4:4] SYSCTL_SRI2C_R5 I2C Module 5 Software Reset [5:5] SYSCTL_SRI2C_R6 I2C Module 6 Software Reset [6:6] SYSCTL_SRI2C_R7 I2C Module 7 Software Reset [7:7] SYSCTL_SRI2C_R8 I2C Module 8 Software Reset [8:8] SYSCTL_SRI2C_R9 I2C Module 9 Software Reset [9:9] SRUSB Universal Serial Bus Software Reset 0x00000528 SYSCTL_SRUSB_R0 USB Module Software Reset [0:0] SREPHY Ethernet PHY Software Reset 0x00000530 SYSCTL_SREPHY_R0 Ethernet PHY Module Software Reset [0:0] SRCAN Controller Area Network Software Reset 0x00000534 SYSCTL_SRCAN_R0 CAN Module 0 Software Reset [0:0] SYSCTL_SRCAN_R1 CAN Module 1 Software Reset [1:1] SRADC Analog-to-Digital Converter Software Reset 0x00000538 SYSCTL_SRADC_R0 ADC Module 0 Software Reset [0:0] SYSCTL_SRADC_R1 ADC Module 1 Software Reset [1:1] SRACMP Analog Comparator Software Reset 0x0000053C SYSCTL_SRACMP_R0 Analog Comparator Module 0 Software Reset [0:0] SRPWM Pulse Width Modulator Software Reset 0x00000540 SYSCTL_SRPWM_R0 PWM Module 0 Software Reset [0:0] SRQEI Quadrature Encoder Interface Software Reset 0x00000544 SYSCTL_SRQEI_R0 QEI Module 0 Software Reset [0:0] SREEPROM EEPROM Software Reset 0x00000558 SYSCTL_SREEPROM_R0 EEPROM Module Software Reset [0:0] SRCCM CRC and Cryptographic Modules Software Reset 0x00000574 SYSCTL_SRCCM_R0 CRC and Cryptographic Modules Software Reset [0:0] SRLCD LCD Controller Software Reset 0x00000590 SYSCTL_SRLCD_R0 LCD Module 0 Software Reset [0:0] SROWIRE 1-Wire Software Reset 0x00000598 SYSCTL_SROWIRE_R0 1-Wire Module Software Reset [0:0] SREMAC Ethernet MAC Software Reset 0x0000059C SYSCTL_SREMAC_R0 Ethernet Controller MAC Module 0 Software Reset [0:0] RCGCWD Watchdog Timer Run Mode Clock Gating Control 0x00000600 SYSCTL_RCGCWD_R0 Watchdog Timer 0 Run Mode Clock Gating Control [0:0] SYSCTL_RCGCWD_R1 Watchdog Timer 1 Run Mode Clock Gating Control [1:1] RCGCTIMER 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control 0x00000604 SYSCTL_RCGCTIMER_R0 16/32-Bit General-Purpose Timer 0 Run Mode Clock Gating Control [0:0] SYSCTL_RCGCTIMER_R1 16/32-Bit General-Purpose Timer 1 Run Mode Clock Gating Control [1:1] SYSCTL_RCGCTIMER_R2 16/32-Bit General-Purpose Timer 2 Run Mode Clock Gating Control [2:2] SYSCTL_RCGCTIMER_R3 16/32-Bit General-Purpose Timer 3 Run Mode Clock Gating Control [3:3] SYSCTL_RCGCTIMER_R4 16/32-Bit General-Purpose Timer 4 Run Mode Clock Gating Control [4:4] SYSCTL_RCGCTIMER_R5 16/32-Bit General-Purpose Timer 5 Run Mode Clock Gating Control [5:5] SYSCTL_RCGCTIMER_R6 16/32-Bit General-Purpose Timer 6 Run Mode Clock Gating Control [6:6] SYSCTL_RCGCTIMER_R7 16/32-Bit General-Purpose Timer 7 Run Mode Clock Gating Control [7:7] RCGCGPIO General-Purpose Input/Output Run Mode Clock Gating Control 0x00000608 SYSCTL_RCGCGPIO_R0 GPIO Port A Run Mode Clock Gating Control [0:0] SYSCTL_RCGCGPIO_R1 GPIO Port B Run Mode Clock Gating Control [1:1] SYSCTL_RCGCGPIO_R2 GPIO Port C Run Mode Clock Gating Control [2:2] SYSCTL_RCGCGPIO_R3 GPIO Port D Run Mode Clock Gating Control [3:3] SYSCTL_RCGCGPIO_R4 GPIO Port E Run Mode Clock Gating Control [4:4] SYSCTL_RCGCGPIO_R5 GPIO Port F Run Mode Clock Gating Control [5:5] SYSCTL_RCGCGPIO_R6 GPIO Port G Run Mode Clock Gating Control [6:6] SYSCTL_RCGCGPIO_R7 GPIO Port H Run Mode Clock Gating Control [7:7] SYSCTL_RCGCGPIO_R8 GPIO Port J Run Mode Clock Gating Control [8:8] SYSCTL_RCGCGPIO_R9 GPIO Port K Run Mode Clock Gating Control [9:9] SYSCTL_RCGCGPIO_R10 GPIO Port L Run Mode Clock Gating Control [10:10] SYSCTL_RCGCGPIO_R11 GPIO Port M Run Mode Clock Gating Control [11:11] SYSCTL_RCGCGPIO_R12 GPIO Port N Run Mode Clock Gating Control [12:12] SYSCTL_RCGCGPIO_R13 GPIO Port P Run Mode Clock Gating Control [13:13] SYSCTL_RCGCGPIO_R14 GPIO Port Q Run Mode Clock Gating Control [14:14] SYSCTL_RCGCGPIO_R15 GPIO Port R Run Mode Clock Gating Control [15:15] SYSCTL_RCGCGPIO_R16 GPIO Port S Run Mode Clock Gating Control [16:16] SYSCTL_RCGCGPIO_R17 GPIO Port T Run Mode Clock Gating Control [17:17] RCGCDMA Micro Direct Memory Access Run Mode Clock Gating Control 0x0000060C SYSCTL_RCGCDMA_R0 uDMA Module Run Mode Clock Gating Control [0:0] RCGCEPI EPI Run Mode Clock Gating Control 0x00000610 SYSCTL_RCGCEPI_R0 EPI Module Run Mode Clock Gating Control [0:0] RCGCHIB Hibernation Run Mode Clock Gating Control 0x00000614 SYSCTL_RCGCHIB_R0 Hibernation Module Run Mode Clock Gating Control [0:0] RCGCUART Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control 0x00000618 SYSCTL_RCGCUART_R0 UART Module 0 Run Mode Clock Gating Control [0:0] SYSCTL_RCGCUART_R1 UART Module 1 Run Mode Clock Gating Control [1:1] SYSCTL_RCGCUART_R2 UART Module 2 Run Mode Clock Gating Control [2:2] SYSCTL_RCGCUART_R3 UART Module 3 Run Mode Clock Gating Control [3:3] SYSCTL_RCGCUART_R4 UART Module 4 Run Mode Clock Gating Control [4:4] SYSCTL_RCGCUART_R5 UART Module 5 Run Mode Clock Gating Control [5:5] SYSCTL_RCGCUART_R6 UART Module 6 Run Mode Clock Gating Control [6:6] SYSCTL_RCGCUART_R7 UART Module 7 Run Mode Clock Gating Control [7:7] RCGCSSI Synchronous Serial Interface Run Mode Clock Gating Control 0x0000061C SYSCTL_RCGCSSI_R0 SSI Module 0 Run Mode Clock Gating Control [0:0] SYSCTL_RCGCSSI_R1 SSI Module 1 Run Mode Clock Gating Control [1:1] SYSCTL_RCGCSSI_R2 SSI Module 2 Run Mode Clock Gating Control [2:2] SYSCTL_RCGCSSI_R3 SSI Module 3 Run Mode Clock Gating Control [3:3] RCGCI2C Inter-Integrated Circuit Run Mode Clock Gating Control 0x00000620 SYSCTL_RCGCI2C_R0 I2C Module 0 Run Mode Clock Gating Control [0:0] SYSCTL_RCGCI2C_R1 I2C Module 1 Run Mode Clock Gating Control [1:1] SYSCTL_RCGCI2C_R2 I2C Module 2 Run Mode Clock Gating Control [2:2] SYSCTL_RCGCI2C_R3 I2C Module 3 Run Mode Clock Gating Control [3:3] SYSCTL_RCGCI2C_R4 I2C Module 4 Run Mode Clock Gating Control [4:4] SYSCTL_RCGCI2C_R5 I2C Module 5 Run Mode Clock Gating Control [5:5] SYSCTL_RCGCI2C_R6 I2C Module 6 Run Mode Clock Gating Control [6:6] SYSCTL_RCGCI2C_R7 I2C Module 7 Run Mode Clock Gating Control [7:7] SYSCTL_RCGCI2C_R8 I2C Module 8 Run Mode Clock Gating Control [8:8] SYSCTL_RCGCI2C_R9 I2C Module 9 Run Mode Clock Gating Control [9:9] RCGCUSB Universal Serial Bus Run Mode Clock Gating Control 0x00000628 SYSCTL_RCGCUSB_R0 USB Module Run Mode Clock Gating Control [0:0] RCGCEPHY Ethernet PHY Run Mode Clock Gating Control 0x00000630 SYSCTL_RCGCEPHY_R0 Ethernet PHY Module Run Mode Clock Gating Control [0:0] RCGCCAN Controller Area Network Run Mode Clock Gating Control 0x00000634 SYSCTL_RCGCCAN_R0 CAN Module 0 Run Mode Clock Gating Control [0:0] SYSCTL_RCGCCAN_R1 CAN Module 1 Run Mode Clock Gating Control [1:1] RCGCADC Analog-to-Digital Converter Run Mode Clock Gating Control 0x00000638 SYSCTL_RCGCADC_R0 ADC Module 0 Run Mode Clock Gating Control [0:0] SYSCTL_RCGCADC_R1 ADC Module 1 Run Mode Clock Gating Control [1:1] RCGCACMP Analog Comparator Run Mode Clock Gating Control 0x0000063C SYSCTL_RCGCACMP_R0 Analog Comparator Module 0 Run Mode Clock Gating Control [0:0] RCGCPWM Pulse Width Modulator Run Mode Clock Gating Control 0x00000640 SYSCTL_RCGCPWM_R0 PWM Module 0 Run Mode Clock Gating Control [0:0] RCGCQEI Quadrature Encoder Interface Run Mode Clock Gating Control 0x00000644 SYSCTL_RCGCQEI_R0 QEI Module 0 Run Mode Clock Gating Control [0:0] RCGCEEPROM EEPROM Run Mode Clock Gating Control 0x00000658 SYSCTL_RCGCEEPROM_R0 EEPROM Module Run Mode Clock Gating Control [0:0] RCGCCCM CRC and Cryptographic Modules Run Mode Clock Gating Control 0x00000674 SYSCTL_RCGCCCM_R0 CRC and Cryptographic Modules Run Mode Clock Gating Control [0:0] RCGCLCD LCD Controller Run Mode Clock Gating Control 0x00000690 SYSCTL_RCGCLCD_R0 LCD Controller Module 0 Run Mode Clock Gating Control [0:0] RCGCOWIRE 1-Wire Run Mode Clock Gating Control 0x00000698 SYSCTL_RCGCOWIRE_R0 1-Wire Module 0 Run Mode Clock Gating Control [0:0] RCGCEMAC Ethernet MAC Run Mode Clock Gating Control 0x0000069C SYSCTL_RCGCEMAC_R0 Ethernet MAC Module 0 Run Mode Clock Gating Control [0:0] SCGCWD Watchdog Timer Sleep Mode Clock Gating Control 0x00000700 SYSCTL_SCGCWD_S0 Watchdog Timer 0 Sleep Mode Clock Gating Control [0:0] SYSCTL_SCGCWD_S1 Watchdog Timer 1 Sleep Mode Clock Gating Control [1:1] SCGCTIMER 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control 0x00000704 SYSCTL_SCGCTIMER_S0 16/32-Bit General-Purpose Timer 0 Sleep Mode Clock Gating Control [0:0] SYSCTL_SCGCTIMER_S1 16/32-Bit General-Purpose Timer 1 Sleep Mode Clock Gating Control [1:1] SYSCTL_SCGCTIMER_S2 16/32-Bit General-Purpose Timer 2 Sleep Mode Clock Gating Control [2:2] SYSCTL_SCGCTIMER_S3 16/32-Bit General-Purpose Timer 3 Sleep Mode Clock Gating Control [3:3] SYSCTL_SCGCTIMER_S4 16/32-Bit General-Purpose Timer 4 Sleep Mode Clock Gating Control [4:4] SYSCTL_SCGCTIMER_S5 16/32-Bit General-Purpose Timer 5 Sleep Mode Clock Gating Control [5:5] SYSCTL_SCGCTIMER_S6 16/32-Bit General-Purpose Timer 6 Sleep Mode Clock Gating Control [6:6] SYSCTL_SCGCTIMER_S7 16/32-Bit General-Purpose Timer 7 Sleep Mode Clock Gating Control [7:7] SCGCGPIO General-Purpose Input/Output Sleep Mode Clock Gating Control 0x00000708 SYSCTL_SCGCGPIO_S0 GPIO Port A Sleep Mode Clock Gating Control [0:0] SYSCTL_SCGCGPIO_S1 GPIO Port B Sleep Mode Clock Gating Control [1:1] SYSCTL_SCGCGPIO_S2 GPIO Port C Sleep Mode Clock Gating Control [2:2] SYSCTL_SCGCGPIO_S3 GPIO Port D Sleep Mode Clock Gating Control [3:3] SYSCTL_SCGCGPIO_S4 GPIO Port E Sleep Mode Clock Gating Control [4:4] SYSCTL_SCGCGPIO_S5 GPIO Port F Sleep Mode Clock Gating Control [5:5] SYSCTL_SCGCGPIO_S6 GPIO Port G Sleep Mode Clock Gating Control [6:6] SYSCTL_SCGCGPIO_S7 GPIO Port H Sleep Mode Clock Gating Control [7:7] SYSCTL_SCGCGPIO_S8 GPIO Port J Sleep Mode Clock Gating Control [8:8] SYSCTL_SCGCGPIO_S9 GPIO Port K Sleep Mode Clock Gating Control [9:9] SYSCTL_SCGCGPIO_S10 GPIO Port L Sleep Mode Clock Gating Control [10:10] SYSCTL_SCGCGPIO_S11 GPIO Port M Sleep Mode Clock Gating Control [11:11] SYSCTL_SCGCGPIO_S12 GPIO Port N Sleep Mode Clock Gating Control [12:12] SYSCTL_SCGCGPIO_S13 GPIO Port P Sleep Mode Clock Gating Control [13:13] SYSCTL_SCGCGPIO_S14 GPIO Port Q Sleep Mode Clock Gating Control [14:14] SYSCTL_SCGCGPIO_S15 GPIO Port R Sleep Mode Clock Gating Control [15:15] SYSCTL_SCGCGPIO_S16 GPIO Port S Sleep Mode Clock Gating Control [16:16] SYSCTL_SCGCGPIO_S17 GPIO Port T Sleep Mode Clock Gating Control [17:17] SCGCDMA Micro Direct Memory Access Sleep Mode Clock Gating Control 0x0000070C SYSCTL_SCGCDMA_S0 uDMA Module Sleep Mode Clock Gating Control [0:0] SCGCEPI EPI Sleep Mode Clock Gating Control 0x00000710 SYSCTL_SCGCEPI_S0 EPI Module Sleep Mode Clock Gating Control [0:0] SCGCHIB Hibernation Sleep Mode Clock Gating Control 0x00000714 SYSCTL_SCGCHIB_S0 Hibernation Module Sleep Mode Clock Gating Control [0:0] SCGCUART Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control 0x00000718 SYSCTL_SCGCUART_S0 UART Module 0 Sleep Mode Clock Gating Control [0:0] SYSCTL_SCGCUART_S1 UART Module 1 Sleep Mode Clock Gating Control [1:1] SYSCTL_SCGCUART_S2 UART Module 2 Sleep Mode Clock Gating Control [2:2] SYSCTL_SCGCUART_S3 UART Module 3 Sleep Mode Clock Gating Control [3:3] SYSCTL_SCGCUART_S4 UART Module 4 Sleep Mode Clock Gating Control [4:4] SYSCTL_SCGCUART_S5 UART Module 5 Sleep Mode Clock Gating Control [5:5] SYSCTL_SCGCUART_S6 UART Module 6 Sleep Mode Clock Gating Control [6:6] SYSCTL_SCGCUART_S7 UART Module 7 Sleep Mode Clock Gating Control [7:7] SCGCSSI Synchronous Serial Interface Sleep Mode Clock Gating Control 0x0000071C SYSCTL_SCGCSSI_S0 SSI Module 0 Sleep Mode Clock Gating Control [0:0] SYSCTL_SCGCSSI_S1 SSI Module 1 Sleep Mode Clock Gating Control [1:1] SYSCTL_SCGCSSI_S2 SSI Module 2 Sleep Mode Clock Gating Control [2:2] SYSCTL_SCGCSSI_S3 SSI Module 3 Sleep Mode Clock Gating Control [3:3] SCGCI2C Inter-Integrated Circuit Sleep Mode Clock Gating Control 0x00000720 SYSCTL_SCGCI2C_S0 I2C Module 0 Sleep Mode Clock Gating Control [0:0] SYSCTL_SCGCI2C_S1 I2C Module 1 Sleep Mode Clock Gating Control [1:1] SYSCTL_SCGCI2C_S2 I2C Module 2 Sleep Mode Clock Gating Control [2:2] SYSCTL_SCGCI2C_S3 I2C Module 3 Sleep Mode Clock Gating Control [3:3] SYSCTL_SCGCI2C_S4 I2C Module 4 Sleep Mode Clock Gating Control [4:4] SYSCTL_SCGCI2C_S5 I2C Module 5 Sleep Mode Clock Gating Control [5:5] SYSCTL_SCGCI2C_S6 I2C Module 6 Sleep Mode Clock Gating Control [6:6] SYSCTL_SCGCI2C_S7 I2C Module 7 Sleep Mode Clock Gating Control [7:7] SYSCTL_SCGCI2C_S8 I2C Module 8 Sleep Mode Clock Gating Control [8:8] SYSCTL_SCGCI2C_S9 I2C Module 9 Sleep Mode Clock Gating Control [9:9] SCGCUSB Universal Serial Bus Sleep Mode Clock Gating Control 0x00000728 SYSCTL_SCGCUSB_S0 USB Module Sleep Mode Clock Gating Control [0:0] SCGCEPHY Ethernet PHY Sleep Mode Clock Gating Control 0x00000730 SYSCTL_SCGCEPHY_S0 PHY Module Sleep Mode Clock Gating Control [0:0] SCGCCAN Controller Area Network Sleep Mode Clock Gating Control 0x00000734 SYSCTL_SCGCCAN_S0 CAN Module 0 Sleep Mode Clock Gating Control [0:0] SYSCTL_SCGCCAN_S1 CAN Module 1 Sleep Mode Clock Gating Control [1:1] SCGCADC Analog-to-Digital Converter Sleep Mode Clock Gating Control 0x00000738 SYSCTL_SCGCADC_S0 ADC Module 0 Sleep Mode Clock Gating Control [0:0] SYSCTL_SCGCADC_S1 ADC Module 1 Sleep Mode Clock Gating Control [1:1] SCGCACMP Analog Comparator Sleep Mode Clock Gating Control 0x0000073C SYSCTL_SCGCACMP_S0 Analog Comparator Module 0 Sleep Mode Clock Gating Control [0:0] SCGCPWM Pulse Width Modulator Sleep Mode Clock Gating Control 0x00000740 SYSCTL_SCGCPWM_S0 PWM Module 0 Sleep Mode Clock Gating Control [0:0] SCGCQEI Quadrature Encoder Interface Sleep Mode Clock Gating Control 0x00000744 SYSCTL_SCGCQEI_S0 QEI Module 0 Sleep Mode Clock Gating Control [0:0] SCGCEEPROM EEPROM Sleep Mode Clock Gating Control 0x00000758 SYSCTL_SCGCEEPROM_S0 EEPROM Module Sleep Mode Clock Gating Control [0:0] SCGCCCM CRC and Cryptographic Modules Sleep Mode Clock Gating Control 0x00000774 SYSCTL_SCGCCCM_S0 CRC and Cryptographic Modules Sleep Mode Clock Gating Control [0:0] SCGCLCD LCD Controller Sleep Mode Clock Gating Control 0x00000790 SYSCTL_SCGCLCD_S0 LCD Controller Module 0 Sleep Mode Clock Gating Control [0:0] SCGCOWIRE 1-Wire Sleep Mode Clock Gating Control 0x00000798 SYSCTL_SCGCOWIRE_S0 1-Wire Module 0 Sleep Mode Clock Gating Control [0:0] SCGCEMAC Ethernet MAC Sleep Mode Clock Gating Control 0x0000079C SYSCTL_SCGCEMAC_S0 Ethernet MAC Module 0 Sleep Mode Clock Gating Control [0:0] DCGCWD Watchdog Timer Deep-Sleep Mode Clock Gating Control 0x00000800 SYSCTL_DCGCWD_D0 Watchdog Timer 0 Deep-Sleep Mode Clock Gating Control [0:0] SYSCTL_DCGCWD_D1 Watchdog Timer 1 Deep-Sleep Mode Clock Gating Control [1:1] DCGCTIMER 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control 0x00000804 SYSCTL_DCGCTIMER_D0 16/32-Bit General-Purpose Timer 0 Deep-Sleep Mode Clock Gating Control [0:0] SYSCTL_DCGCTIMER_D1 16/32-Bit General-Purpose Timer 1 Deep-Sleep Mode Clock Gating Control [1:1] SYSCTL_DCGCTIMER_D2 16/32-Bit General-Purpose Timer 2 Deep-Sleep Mode Clock Gating Control [2:2] SYSCTL_DCGCTIMER_D3 16/32-Bit General-Purpose Timer 3 Deep-Sleep Mode Clock Gating Control [3:3] SYSCTL_DCGCTIMER_D4 16/32-Bit General-Purpose Timer 4 Deep-Sleep Mode Clock Gating Control [4:4] SYSCTL_DCGCTIMER_D5 16/32-Bit General-Purpose Timer 5 Deep-Sleep Mode Clock Gating Control [5:5] SYSCTL_DCGCTIMER_D6 16/32-Bit General-Purpose Timer 6 Deep-Sleep Mode Clock Gating Control [6:6] SYSCTL_DCGCTIMER_D7 16/32-Bit General-Purpose Timer 7 Deep-Sleep Mode Clock Gating Control [7:7] DCGCGPIO General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control 0x00000808 SYSCTL_DCGCGPIO_D0 GPIO Port A Deep-Sleep Mode Clock Gating Control [0:0] SYSCTL_DCGCGPIO_D1 GPIO Port B Deep-Sleep Mode Clock Gating Control [1:1] SYSCTL_DCGCGPIO_D2 GPIO Port C Deep-Sleep Mode Clock Gating Control [2:2] SYSCTL_DCGCGPIO_D3 GPIO Port D Deep-Sleep Mode Clock Gating Control [3:3] SYSCTL_DCGCGPIO_D4 GPIO Port E Deep-Sleep Mode Clock Gating Control [4:4] SYSCTL_DCGCGPIO_D5 GPIO Port F Deep-Sleep Mode Clock Gating Control [5:5] SYSCTL_DCGCGPIO_D6 GPIO Port G Deep-Sleep Mode Clock Gating Control [6:6] SYSCTL_DCGCGPIO_D7 GPIO Port H Deep-Sleep Mode Clock Gating Control [7:7] SYSCTL_DCGCGPIO_D8 GPIO Port J Deep-Sleep Mode Clock Gating Control [8:8] SYSCTL_DCGCGPIO_D9 GPIO Port K Deep-Sleep Mode Clock Gating Control [9:9] SYSCTL_DCGCGPIO_D10 GPIO Port L Deep-Sleep Mode Clock Gating Control [10:10] SYSCTL_DCGCGPIO_D11 GPIO Port M Deep-Sleep Mode Clock Gating Control [11:11] SYSCTL_DCGCGPIO_D12 GPIO Port N Deep-Sleep Mode Clock Gating Control [12:12] SYSCTL_DCGCGPIO_D13 GPIO Port P Deep-Sleep Mode Clock Gating Control [13:13] SYSCTL_DCGCGPIO_D14 GPIO Port Q Deep-Sleep Mode Clock Gating Control [14:14] SYSCTL_DCGCGPIO_D15 GPIO Port R Deep-Sleep Mode Clock Gating Control [15:15] SYSCTL_DCGCGPIO_D16 GPIO Port S Deep-Sleep Mode Clock Gating Control [16:16] SYSCTL_DCGCGPIO_D17 GPIO Port T Deep-Sleep Mode Clock Gating Control [17:17] DCGCDMA Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control 0x0000080C SYSCTL_DCGCDMA_D0 uDMA Module Deep-Sleep Mode Clock Gating Control [0:0] DCGCEPI EPI Deep-Sleep Mode Clock Gating Control 0x00000810 SYSCTL_DCGCEPI_D0 EPI Module Deep-Sleep Mode Clock Gating Control [0:0] DCGCHIB Hibernation Deep-Sleep Mode Clock Gating Control 0x00000814 SYSCTL_DCGCHIB_D0 Hibernation Module Deep-Sleep Mode Clock Gating Control [0:0] DCGCUART Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control 0x00000818 SYSCTL_DCGCUART_D0 UART Module 0 Deep-Sleep Mode Clock Gating Control [0:0] SYSCTL_DCGCUART_D1 UART Module 1 Deep-Sleep Mode Clock Gating Control [1:1] SYSCTL_DCGCUART_D2 UART Module 2 Deep-Sleep Mode Clock Gating Control [2:2] SYSCTL_DCGCUART_D3 UART Module 3 Deep-Sleep Mode Clock Gating Control [3:3] SYSCTL_DCGCUART_D4 UART Module 4 Deep-Sleep Mode Clock Gating Control [4:4] SYSCTL_DCGCUART_D5 UART Module 5 Deep-Sleep Mode Clock Gating Control [5:5] SYSCTL_DCGCUART_D6 UART Module 6 Deep-Sleep Mode Clock Gating Control [6:6] SYSCTL_DCGCUART_D7 UART Module 7 Deep-Sleep Mode Clock Gating Control [7:7] DCGCSSI Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control 0x0000081C SYSCTL_DCGCSSI_D0 SSI Module 0 Deep-Sleep Mode Clock Gating Control [0:0] SYSCTL_DCGCSSI_D1 SSI Module 1 Deep-Sleep Mode Clock Gating Control [1:1] SYSCTL_DCGCSSI_D2 SSI Module 2 Deep-Sleep Mode Clock Gating Control [2:2] SYSCTL_DCGCSSI_D3 SSI Module 3 Deep-Sleep Mode Clock Gating Control [3:3] DCGCI2C Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control 0x00000820 SYSCTL_DCGCI2C_D0 I2C Module 0 Deep-Sleep Mode Clock Gating Control [0:0] SYSCTL_DCGCI2C_D1 I2C Module 1 Deep-Sleep Mode Clock Gating Control [1:1] SYSCTL_DCGCI2C_D2 I2C Module 2 Deep-Sleep Mode Clock Gating Control [2:2] SYSCTL_DCGCI2C_D3 I2C Module 3 Deep-Sleep Mode Clock Gating Control [3:3] SYSCTL_DCGCI2C_D4 I2C Module 4 Deep-Sleep Mode Clock Gating Control [4:4] SYSCTL_DCGCI2C_D5 I2C Module 5 Deep-Sleep Mode Clock Gating Control [5:5] SYSCTL_DCGCI2C_D6 I2C Module 6 Deep-Sleep Mode Clock Gating Control [6:6] SYSCTL_DCGCI2C_D7 I2C Module 7 Deep-Sleep Mode Clock Gating Control [7:7] SYSCTL_DCGCI2C_D8 I2C Module 8 Deep-Sleep Mode Clock Gating Control [8:8] SYSCTL_DCGCI2C_D9 I2C Module 9 Deep-Sleep Mode Clock Gating Control [9:9] DCGCUSB Universal Serial Bus Deep-Sleep Mode Clock Gating Control 0x00000828 SYSCTL_DCGCUSB_D0 USB Module Deep-Sleep Mode Clock Gating Control [0:0] DCGCEPHY Ethernet PHY Deep-Sleep Mode Clock Gating Control 0x00000830 SYSCTL_DCGCEPHY_D0 PHY Module Deep-Sleep Mode Clock Gating Control [0:0] DCGCCAN Controller Area Network Deep-Sleep Mode Clock Gating Control 0x00000834 SYSCTL_DCGCCAN_D0 CAN Module 0 Deep-Sleep Mode Clock Gating Control [0:0] SYSCTL_DCGCCAN_D1 CAN Module 1 Deep-Sleep Mode Clock Gating Control [1:1] DCGCADC Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control 0x00000838 SYSCTL_DCGCADC_D0 ADC Module 0 Deep-Sleep Mode Clock Gating Control [0:0] SYSCTL_DCGCADC_D1 ADC Module 1 Deep-Sleep Mode Clock Gating Control [1:1] DCGCACMP Analog Comparator Deep-Sleep Mode Clock Gating Control 0x0000083C SYSCTL_DCGCACMP_D0 Analog Comparator Module 0 Deep-Sleep Mode Clock Gating Control [0:0] DCGCPWM Pulse Width Modulator Deep-Sleep Mode Clock Gating Control 0x00000840 SYSCTL_DCGCPWM_D0 PWM Module 0 Deep-Sleep Mode Clock Gating Control [0:0] DCGCQEI Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control 0x00000844 SYSCTL_DCGCQEI_D0 QEI Module 0 Deep-Sleep Mode Clock Gating Control [0:0] DCGCEEPROM EEPROM Deep-Sleep Mode Clock Gating Control 0x00000858 SYSCTL_DCGCEEPROM_D0 EEPROM Module Deep-Sleep Mode Clock Gating Control [0:0] DCGCCCM CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control 0x00000874 SYSCTL_DCGCCCM_D0 CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control [0:0] DCGCLCD LCD Controller Deep-Sleep Mode Clock Gating Control 0x00000890 SYSCTL_DCGCLCD_D0 LCD Controller Module 0 Deep-Sleep Mode Clock Gating Control [0:0] DCGCOWIRE 1-Wire Deep-Sleep Mode Clock Gating Control 0x00000898 SYSCTL_DCGCOWIRE_D0 1-Wire Module 0 Deep-Sleep Mode Clock Gating Control [0:0] DCGCEMAC Ethernet MAC Deep-Sleep Mode Clock Gating Control 0x0000089C SYSCTL_DCGCEMAC_D0 Ethernet MAC Module 0 Deep-Sleep Mode Clock Gating Control [0:0] PCWD Watchdog Timer Power Control 0x00000900 SYSCTL_PCWD_P0 Watchdog Timer 0 Power Control [0:0] SYSCTL_PCWD_P1 Watchdog Timer 1 Power Control [1:1] PCTIMER 16/32-Bit General-Purpose Timer Power Control 0x00000904 SYSCTL_PCTIMER_P0 General-Purpose Timer 0 Power Control [0:0] SYSCTL_PCTIMER_P1 General-Purpose Timer 1 Power Control [1:1] SYSCTL_PCTIMER_P2 General-Purpose Timer 2 Power Control [2:2] SYSCTL_PCTIMER_P3 General-Purpose Timer 3 Power Control [3:3] SYSCTL_PCTIMER_P4 General-Purpose Timer 4 Power Control [4:4] SYSCTL_PCTIMER_P5 General-Purpose Timer 5 Power Control [5:5] SYSCTL_PCTIMER_P6 General-Purpose Timer 6 Power Control [6:6] SYSCTL_PCTIMER_P7 General-Purpose Timer 7 Power Control [7:7] PCGPIO General-Purpose Input/Output Power Control 0x00000908 SYSCTL_PCGPIO_P0 GPIO Port A Power Control [0:0] SYSCTL_PCGPIO_P1 GPIO Port B Power Control [1:1] SYSCTL_PCGPIO_P2 GPIO Port C Power Control [2:2] SYSCTL_PCGPIO_P3 GPIO Port D Power Control [3:3] SYSCTL_PCGPIO_P4 GPIO Port E Power Control [4:4] SYSCTL_PCGPIO_P5 GPIO Port F Power Control [5:5] SYSCTL_PCGPIO_P6 GPIO Port G Power Control [6:6] SYSCTL_PCGPIO_P7 GPIO Port H Power Control [7:7] SYSCTL_PCGPIO_P8 GPIO Port J Power Control [8:8] SYSCTL_PCGPIO_P9 GPIO Port K Power Control [9:9] SYSCTL_PCGPIO_P10 GPIO Port L Power Control [10:10] SYSCTL_PCGPIO_P11 GPIO Port M Power Control [11:11] SYSCTL_PCGPIO_P12 GPIO Port N Power Control [12:12] SYSCTL_PCGPIO_P13 GPIO Port P Power Control [13:13] SYSCTL_PCGPIO_P14 GPIO Port Q Power Control [14:14] SYSCTL_PCGPIO_P15 GPIO Port R Power Control [15:15] SYSCTL_PCGPIO_P16 GPIO Port S Power Control [16:16] SYSCTL_PCGPIO_P17 GPIO Port T Power Control [17:17] PCDMA Micro Direct Memory Access Power Control 0x0000090C SYSCTL_PCDMA_P0 uDMA Module Power Control [0:0] PCEPI External Peripheral Interface Power Control 0x00000910 SYSCTL_PCEPI_P0 EPI Module Power Control [0:0] PCHIB Hibernation Power Control 0x00000914 SYSCTL_PCHIB_P0 Hibernation Module Power Control [0:0] PCUART Universal Asynchronous Receiver/Transmitter Power Control 0x00000918 SYSCTL_PCUART_P0 UART Module 0 Power Control [0:0] SYSCTL_PCUART_P1 UART Module 1 Power Control [1:1] SYSCTL_PCUART_P2 UART Module 2 Power Control [2:2] SYSCTL_PCUART_P3 UART Module 3 Power Control [3:3] SYSCTL_PCUART_P4 UART Module 4 Power Control [4:4] SYSCTL_PCUART_P5 UART Module 5 Power Control [5:5] SYSCTL_PCUART_P6 UART Module 6 Power Control [6:6] SYSCTL_PCUART_P7 UART Module 7 Power Control [7:7] PCSSI Synchronous Serial Interface Power Control 0x0000091C SYSCTL_PCSSI_P0 SSI Module 0 Power Control [0:0] SYSCTL_PCSSI_P1 SSI Module 1 Power Control [1:1] SYSCTL_PCSSI_P2 SSI Module 2 Power Control [2:2] SYSCTL_PCSSI_P3 SSI Module 3 Power Control [3:3] PCI2C Inter-Integrated Circuit Power Control 0x00000920 SYSCTL_PCI2C_P0 I2C Module 0 Power Control [0:0] SYSCTL_PCI2C_P1 I2C Module 1 Power Control [1:1] SYSCTL_PCI2C_P2 I2C Module 2 Power Control [2:2] SYSCTL_PCI2C_P3 I2C Module 3 Power Control [3:3] SYSCTL_PCI2C_P4 I2C Module 4 Power Control [4:4] SYSCTL_PCI2C_P5 I2C Module 5 Power Control [5:5] SYSCTL_PCI2C_P6 I2C Module 6 Power Control [6:6] SYSCTL_PCI2C_P7 I2C Module 7 Power Control [7:7] SYSCTL_PCI2C_P8 I2C Module 8 Power Control [8:8] SYSCTL_PCI2C_P9 I2C Module 9 Power Control [9:9] PCUSB Universal Serial Bus Power Control 0x00000928 SYSCTL_PCUSB_P0 USB Module Power Control [0:0] PCEPHY Ethernet PHY Power Control 0x00000930 SYSCTL_PCEPHY_P0 Ethernet PHY Module Power Control [0:0] PCCAN Controller Area Network Power Control 0x00000934 SYSCTL_PCCAN_P0 CAN Module 0 Power Control [0:0] SYSCTL_PCCAN_P1 CAN Module 1 Power Control [1:1] PCADC Analog-to-Digital Converter Power Control 0x00000938 SYSCTL_PCADC_P0 ADC Module 0 Power Control [0:0] SYSCTL_PCADC_P1 ADC Module 1 Power Control [1:1] PCACMP Analog Comparator Power Control 0x0000093C SYSCTL_PCACMP_P0 Analog Comparator Module 0 Power Control [0:0] PCPWM Pulse Width Modulator Power Control 0x00000940 SYSCTL_PCPWM_P0 PWM Module 0 Power Control [0:0] PCQEI Quadrature Encoder Interface Power Control 0x00000944 SYSCTL_PCQEI_P0 QEI Module 0 Power Control [0:0] PCEEPROM EEPROM Power Control 0x00000958 SYSCTL_PCEEPROM_P0 EEPROM Module 0 Power Control [0:0] PCCCM CRC and Cryptographic Modules Power Control 0x00000974 SYSCTL_PCCCM_P0 CRC and Cryptographic Modules Power Control [0:0] PCLCD LCD Controller Power Control 0x00000990 SYSCTL_PCLCD_P0 LCD Controller Module 0 Power Control [0:0] PCOWIRE 1-Wire Power Control 0x00000998 SYSCTL_PCOWIRE_P0 1-Wire Module 0 Power Control [0:0] PCEMAC Ethernet MAC Power Control 0x0000099C SYSCTL_PCEMAC_P0 Ethernet MAC Module 0 Power Control [0:0] PRWD Watchdog Timer Peripheral Ready 0x00000A00 SYSCTL_PRWD_R0 Watchdog Timer 0 Peripheral Ready [0:0] SYSCTL_PRWD_R1 Watchdog Timer 1 Peripheral Ready [1:1] PRTIMER 16/32-Bit General-Purpose Timer Peripheral Ready 0x00000A04 SYSCTL_PRTIMER_R0 16/32-Bit General-Purpose Timer 0 Peripheral Ready [0:0] SYSCTL_PRTIMER_R1 16/32-Bit General-Purpose Timer 1 Peripheral Ready [1:1] SYSCTL_PRTIMER_R2 16/32-Bit General-Purpose Timer 2 Peripheral Ready [2:2] SYSCTL_PRTIMER_R3 16/32-Bit General-Purpose Timer 3 Peripheral Ready [3:3] SYSCTL_PRTIMER_R4 16/32-Bit General-Purpose Timer 4 Peripheral Ready [4:4] SYSCTL_PRTIMER_R5 16/32-Bit General-Purpose Timer 5 Peripheral Ready [5:5] SYSCTL_PRTIMER_R6 16/32-Bit General-Purpose Timer 6 Peripheral Ready [6:6] SYSCTL_PRTIMER_R7 16/32-Bit General-Purpose Timer 7 Peripheral Ready [7:7] PRGPIO General-Purpose Input/Output Peripheral Ready 0x00000A08 SYSCTL_PRGPIO_R0 GPIO Port A Peripheral Ready [0:0] SYSCTL_PRGPIO_R1 GPIO Port B Peripheral Ready [1:1] SYSCTL_PRGPIO_R2 GPIO Port C Peripheral Ready [2:2] SYSCTL_PRGPIO_R3 GPIO Port D Peripheral Ready [3:3] SYSCTL_PRGPIO_R4 GPIO Port E Peripheral Ready [4:4] SYSCTL_PRGPIO_R5 GPIO Port F Peripheral Ready [5:5] SYSCTL_PRGPIO_R6 GPIO Port G Peripheral Ready [6:6] SYSCTL_PRGPIO_R7 GPIO Port H Peripheral Ready [7:7] SYSCTL_PRGPIO_R8 GPIO Port J Peripheral Ready [8:8] SYSCTL_PRGPIO_R9 GPIO Port K Peripheral Ready [9:9] SYSCTL_PRGPIO_R10 GPIO Port L Peripheral Ready [10:10] SYSCTL_PRGPIO_R11 GPIO Port M Peripheral Ready [11:11] SYSCTL_PRGPIO_R12 GPIO Port N Peripheral Ready [12:12] SYSCTL_PRGPIO_R13 GPIO Port P Peripheral Ready [13:13] SYSCTL_PRGPIO_R14 GPIO Port Q Peripheral Ready [14:14] SYSCTL_PRGPIO_R15 GPIO Port R Peripheral Ready [15:15] SYSCTL_PRGPIO_R16 GPIO Port S Peripheral Ready [16:16] SYSCTL_PRGPIO_R17 GPIO Port T Peripheral Ready [17:17] PRDMA Micro Direct Memory Access Peripheral Ready 0x00000A0C SYSCTL_PRDMA_R0 uDMA Module Peripheral Ready [0:0] PREPI EPI Peripheral Ready 0x00000A10 SYSCTL_PREPI_R0 EPI Module Peripheral Ready [0:0] PRHIB Hibernation Peripheral Ready 0x00000A14 SYSCTL_PRHIB_R0 Hibernation Module Peripheral Ready [0:0] PRUART Universal Asynchronous Receiver/Transmitter Peripheral Ready 0x00000A18 SYSCTL_PRUART_R0 UART Module 0 Peripheral Ready [0:0] SYSCTL_PRUART_R1 UART Module 1 Peripheral Ready [1:1] SYSCTL_PRUART_R2 UART Module 2 Peripheral Ready [2:2] SYSCTL_PRUART_R3 UART Module 3 Peripheral Ready [3:3] SYSCTL_PRUART_R4 UART Module 4 Peripheral Ready [4:4] SYSCTL_PRUART_R5 UART Module 5 Peripheral Ready [5:5] SYSCTL_PRUART_R6 UART Module 6 Peripheral Ready [6:6] SYSCTL_PRUART_R7 UART Module 7 Peripheral Ready [7:7] PRSSI Synchronous Serial Interface Peripheral Ready 0x00000A1C SYSCTL_PRSSI_R0 SSI Module 0 Peripheral Ready [0:0] SYSCTL_PRSSI_R1 SSI Module 1 Peripheral Ready [1:1] SYSCTL_PRSSI_R2 SSI Module 2 Peripheral Ready [2:2] SYSCTL_PRSSI_R3 SSI Module 3 Peripheral Ready [3:3] PRI2C Inter-Integrated Circuit Peripheral Ready 0x00000A20 SYSCTL_PRI2C_R0 I2C Module 0 Peripheral Ready [0:0] SYSCTL_PRI2C_R1 I2C Module 1 Peripheral Ready [1:1] SYSCTL_PRI2C_R2 I2C Module 2 Peripheral Ready [2:2] SYSCTL_PRI2C_R3 I2C Module 3 Peripheral Ready [3:3] SYSCTL_PRI2C_R4 I2C Module 4 Peripheral Ready [4:4] SYSCTL_PRI2C_R5 I2C Module 5 Peripheral Ready [5:5] SYSCTL_PRI2C_R6 I2C Module 6 Peripheral Ready [6:6] SYSCTL_PRI2C_R7 I2C Module 7 Peripheral Ready [7:7] SYSCTL_PRI2C_R8 I2C Module 8 Peripheral Ready [8:8] SYSCTL_PRI2C_R9 I2C Module 9 Peripheral Ready [9:9] PRUSB Universal Serial Bus Peripheral Ready 0x00000A28 SYSCTL_PRUSB_R0 USB Module Peripheral Ready [0:0] PREPHY Ethernet PHY Peripheral Ready 0x00000A30 SYSCTL_PREPHY_R0 Ethernet PHY Module Peripheral Ready [0:0] PRCAN Controller Area Network Peripheral Ready 0x00000A34 SYSCTL_PRCAN_R0 CAN Module 0 Peripheral Ready [0:0] SYSCTL_PRCAN_R1 CAN Module 1 Peripheral Ready [1:1] PRADC Analog-to-Digital Converter Peripheral Ready 0x00000A38 SYSCTL_PRADC_R0 ADC Module 0 Peripheral Ready [0:0] SYSCTL_PRADC_R1 ADC Module 1 Peripheral Ready [1:1] PRACMP Analog Comparator Peripheral Ready 0x00000A3C SYSCTL_PRACMP_R0 Analog Comparator Module 0 Peripheral Ready [0:0] PRPWM Pulse Width Modulator Peripheral Ready 0x00000A40 SYSCTL_PRPWM_R0 PWM Module 0 Peripheral Ready [0:0] PRQEI Quadrature Encoder Interface Peripheral Ready 0x00000A44 SYSCTL_PRQEI_R0 QEI Module 0 Peripheral Ready [0:0] PREEPROM EEPROM Peripheral Ready 0x00000A58 SYSCTL_PREEPROM_R0 EEPROM Module Peripheral Ready [0:0] PRCCM CRC and Cryptographic Modules Peripheral Ready 0x00000A74 SYSCTL_PRCCM_R0 CRC and Cryptographic Modules Peripheral Ready [0:0] PRLCD LCD Controller Peripheral Ready 0x00000A90 SYSCTL_PRLCD_R0 LCD Controller Module 0 Peripheral Ready [0:0] PROWIRE 1-Wire Peripheral Ready 0x00000A98 SYSCTL_PROWIRE_R0 1-Wire Module 0 Peripheral Ready [0:0] PREMAC Ethernet MAC Peripheral Ready 0x00000A9C SYSCTL_PREMAC_R0 Ethernet MAC Module 0 Peripheral Ready [0:0] UNIQUEID0 Unique ID 0 0x00000F20 UNIQUEID1 Unique ID 1 0x00000F24 UNIQUEID2 Unique ID 2 0x00000F28 UNIQUEID3 Unique ID 3 0x00000F2C UDMA Register map for UDMA peripheral UDM UDMA 0x400FF000 0 0x00001000 registers UDMA44 UDMAERR45 STAT DMA Status 0x00000000 UDMA_STAT_MASTEN Master Enable Status [0:0] UDMA_STAT_STATE Control State Machine Status [7:4] UDMA_STAT_STATE_IDLE Idle 0x0 UDMA_STAT_STATE_RD_CTRL Reading channel controller data 0x1 UDMA_STAT_STATE_RD_SRCENDP Reading source end pointer 0x2 UDMA_STAT_STATE_RD_DSTENDP Reading destination end pointer 0x3 UDMA_STAT_STATE_RD_SRCDAT Reading source data 0x4 UDMA_STAT_STATE_WR_DSTDAT Writing destination data 0x5 UDMA_STAT_STATE_WAIT Waiting for uDMA request to clear 0x6 UDMA_STAT_STATE_WR_CTRL Writing channel controller data 0x7 UDMA_STAT_STATE_STALL Stalled 0x8 UDMA_STAT_STATE_DONE Done 0x9 UDMA_STAT_STATE_UNDEF Undefined 0xa UDMA_STAT_DMACHANS Available uDMA Channels Minus 1 [20:16] CFG DMA Configuration 0x00000004 write-only UDMA_CFG_MASTEN Controller Master Enable [0:0] write-only CTLBASE DMA Channel Control Base Pointer 0x00000008 UDMA_CTLBASE_ADDR Channel Control Base Address [31:10] ALTBASE DMA Alternate Channel Control Base Pointer 0x0000000C UDMA_ALTBASE_ADDR Alternate Channel Address Pointer [31:0] WAITSTAT DMA Channel Wait-on-Request Status 0x00000010 UDMA_WAITSTAT_WAITREQ Channel [n] Wait Status [31:0] SWREQ DMA Channel Software Request 0x00000014 write-only UDMA_SWREQ Channel [n] Software Request [31:0] write-only USEBURSTSET DMA Channel Useburst Set 0x00000018 UDMA_USEBURSTSET_SET Channel [n] Useburst Set [31:0] USEBURSTCLR DMA Channel Useburst Clear 0x0000001C write-only UDMA_USEBURSTCLR_CLR Channel [n] Useburst Clear [31:0] write-only REQMASKSET DMA Channel Request Mask Set 0x00000020 UDMA_REQMASKSET_SET Channel [n] Request Mask Set [31:0] REQMASKCLR DMA Channel Request Mask Clear 0x00000024 write-only UDMA_REQMASKCLR_CLR Channel [n] Request Mask Clear [31:0] write-only ENASET DMA Channel Enable Set 0x00000028 UDMA_ENASET_SET Channel [n] Enable Set [31:0] ENACLR DMA Channel Enable Clear 0x0000002C write-only UDMA_ENACLR_CLR Clear Channel [n] Enable Clear [31:0] write-only ALTSET DMA Channel Primary Alternate Set 0x00000030 UDMA_ALTSET_SET Channel [n] Alternate Set [31:0] ALTCLR DMA Channel Primary Alternate Clear 0x00000034 write-only UDMA_ALTCLR_CLR Channel [n] Alternate Clear [31:0] write-only PRIOSET DMA Channel Priority Set 0x00000038 UDMA_PRIOSET_SET Channel [n] Priority Set [31:0] PRIOCLR DMA Channel Priority Clear 0x0000003C write-only UDMA_PRIOCLR_CLR Channel [n] Priority Clear [31:0] write-only ERRCLR DMA Bus Error Clear 0x0000004C UDMA_ERRCLR_ERRCLR uDMA Bus Error Status [0:0] CHMAP0 DMA Channel Map Select 0 0x00000510 UDMA_CHMAP0_CH0SEL uDMA Channel 0 Source Select [3:0] UDMA_CHMAP0_CH1SEL uDMA Channel 1 Source Select [7:4] UDMA_CHMAP0_CH2SEL uDMA Channel 2 Source Select [11:8] UDMA_CHMAP0_CH3SEL uDMA Channel 3 Source Select [15:12] UDMA_CHMAP0_CH4SEL uDMA Channel 4 Source Select [19:16] UDMA_CHMAP0_CH5SEL uDMA Channel 5 Source Select [23:20] UDMA_CHMAP0_CH6SEL uDMA Channel 6 Source Select [27:24] UDMA_CHMAP0_CH7SEL uDMA Channel 7 Source Select [31:28] CHMAP1 DMA Channel Map Select 1 0x00000514 UDMA_CHMAP1_CH8SEL uDMA Channel 8 Source Select [3:0] UDMA_CHMAP1_CH9SEL uDMA Channel 9 Source Select [7:4] UDMA_CHMAP1_CH10SEL uDMA Channel 10 Source Select [11:8] UDMA_CHMAP1_CH11SEL uDMA Channel 11 Source Select [15:12] UDMA_CHMAP1_CH12SEL uDMA Channel 12 Source Select [19:16] UDMA_CHMAP1_CH13SEL uDMA Channel 13 Source Select [23:20] UDMA_CHMAP1_CH14SEL uDMA Channel 14 Source Select [27:24] UDMA_CHMAP1_CH15SEL uDMA Channel 15 Source Select [31:28] CHMAP2 DMA Channel Map Select 2 0x00000518 UDMA_CHMAP2_CH16SEL uDMA Channel 16 Source Select [3:0] UDMA_CHMAP2_CH17SEL uDMA Channel 17 Source Select [7:4] UDMA_CHMAP2_CH18SEL uDMA Channel 18 Source Select [11:8] UDMA_CHMAP2_CH19SEL uDMA Channel 19 Source Select [15:12] UDMA_CHMAP2_CH20SEL uDMA Channel 20 Source Select [19:16] UDMA_CHMAP2_CH21SEL uDMA Channel 21 Source Select [23:20] UDMA_CHMAP2_CH22SEL uDMA Channel 22 Source Select [27:24] UDMA_CHMAP2_CH23SEL uDMA Channel 23 Source Select [31:28] CHMAP3 DMA Channel Map Select 3 0x0000051C UDMA_CHMAP3_CH24SEL uDMA Channel 24 Source Select [3:0] UDMA_CHMAP3_CH25SEL uDMA Channel 25 Source Select [7:4] UDMA_CHMAP3_CH26SEL uDMA Channel 26 Source Select [11:8] UDMA_CHMAP3_CH27SEL uDMA Channel 27 Source Select [15:12] UDMA_CHMAP3_CH28SEL uDMA Channel 28 Source Select [19:16] UDMA_CHMAP3_CH29SEL uDMA Channel 29 Source Select [23:20] UDMA_CHMAP3_CH30SEL uDMA Channel 30 Source Select [27:24] UDMA_CHMAP3_CH31SEL uDMA Channel 31 Source Select [31:28] CCM0 Register map for CCM0 peripheral CCM CCM0 0x44030204 0 0x00000004 registers CCMCGREQ Cryptographic Modules Clock Gating Request 0x00000000 CRC Register map for CRC peripheral CRC 0x44030400 0 0x0000001C registers CTRL CRC Control 0x00000000 CRC_CTRL_TYPE Operation Type [3:0] CRC_CTRL_TYPE_P8055 Polynomial 0x8005 0x0 CRC_CTRL_TYPE_P1021 Polynomial 0x1021 0x1 CRC_CTRL_TYPE_P4C11DB7 Polynomial 0x4C11DB7 0x2 CRC_CTRL_TYPE_P1EDC6F41 Polynomial 0x1EDC6F41 0x3 CRC_CTRL_TYPE_TCPCHKSUM TCP checksum 0x8 CRC_CTRL_ENDIAN Endian Control [5:4] CRC_CTRL_ENDIAN_SBHW Configuration unchanged. (B3, B2, B1, B0) 0x0 CRC_CTRL_ENDIAN_SHW Bytes are swapped in half-words but half-words are not swapped (B2, B3, B0, B1) 0x1 CRC_CTRL_ENDIAN_SHWNB Half-words are swapped but bytes are not swapped in half-word. (B1, B0, B3, B2) 0x2 CRC_CTRL_ENDIAN_SBSW Bytes are swapped in half-words and half-words are swapped. (B0, B1, B2, B3) 0x3 CRC_CTRL_BR Bit reverse enable [7:7] CRC_CTRL_OBR Output Reverse Enable [8:8] CRC_CTRL_RESINV Result Inverse Enable [9:9] CRC_CTRL_SIZE Input Data Size [12:12] CRC_CTRL_INIT CRC Initialization [14:13] CRC_CTRL_INIT_SEED Use the CRCSEED register context as the starting value 0x0 CRC_CTRL_INIT_0 Initialize to all '0s' 0x2 CRC_CTRL_INIT_1 Initialize to all '1s' 0x3 CRCSEED CRC SEED/Context 0x00000010 CRC_SEED_SEED SEED/Context Value [31:0] CRCDIN CRC Data Input 0x00000014 CRC_DIN_DATAIN Data Input [31:0] CRCRSLTPP CRC Post Processing Result 0x00000018 CRC_RSLTPP_RSLTPP Post Processing Result [31:0] SHAMD5 Register map for SHAMD5 peripheral SHAMD5 SHAMD5 0x44034000 0 0x00002000 registers ODIGEST_A SHA Outer Digest A 0x00000000 SHAMD5_ODIGEST_A_DATA Digest/Key Data [31:0] ODIGEST_B SHA Outer Digest B 0x00000004 SHAMD5_ODIGEST_B_DATA Digest/Key Data [31:0] ODIGEST_C SHA Outer Digest C 0x00000008 SHAMD5_ODIGEST_C_DATA Digest/Key Data [31:0] ODIGEST_D SHA Outer Digest D 0x0000000C SHAMD5_ODIGEST_D_DATA Digest/Key Data [31:0] ODIGEST_E SHA Outer Digest E 0x00000010 SHAMD5_ODIGEST_E_DATA Digest/Key Data [31:0] ODIGEST_F SHA Outer Digest F 0x00000014 SHAMD5_ODIGEST_F_DATA Digest/Key Data [31:0] ODIGEST_G SHA Outer Digest G 0x00000018 SHAMD5_ODIGEST_G_DATA Digest/Key Data [31:0] ODIGEST_H SHA Outer Digest H 0x0000001C SHAMD5_ODIGEST_H_DATA Digest/Key Data [31:0] IDIGEST_A SHA Inner Digest A 0x00000020 SHAMD5_IDIGEST_A_DATA Digest/Key Data [31:0] IDIGEST_B SHA Inner Digest B 0x00000024 SHAMD5_IDIGEST_B_DATA Digest/Key Data [31:0] IDIGEST_C SHA Inner Digest C 0x00000028 SHAMD5_IDIGEST_C_DATA Digest/Key Data [31:0] IDIGEST_D SHA Inner Digest D 0x0000002C SHAMD5_IDIGEST_D_DATA Digest/Key Data [31:0] IDIGEST_E SHA Inner Digest E 0x00000030 SHAMD5_IDIGEST_E_DATA Digest/Key Data [31:0] IDIGEST_F SHA Inner Digest F 0x00000034 SHAMD5_IDIGEST_F_DATA Digest/Key Data [31:0] IDIGEST_G SHA Inner Digest G 0x00000038 SHAMD5_IDIGEST_G_DATA Digest/Key Data [31:0] IDIGEST_H SHA Inner Digest H 0x0000003C SHAMD5_IDIGEST_H_DATA Digest/Key Data [31:0] DIGEST_COUNT SHA Digest Count 0x00000040 SHAMD5_DIGEST_COUNT Digest Count [31:0] MODE SHA Mode 0x00000044 SHAMD5_MODE_ALGO Hash Algorithm [2:0] SHAMD5_MODE_ALGO_MD5 MD5 0x0 SHAMD5_MODE_ALGO_SHA1 SHA-1 0x2 SHAMD5_MODE_ALGO_SHA224 SHA-224 0x4 SHAMD5_MODE_ALGO_SHA256 SHA-256 0x6 SHAMD5_MODE_ALGO_CONSTANT The initial digest register will be overwritten with the algorithm constants for the selected algorithm when hashing and the initial digest count register will be reset to 0 [3:3] SHAMD5_MODE_CLOSE_HASH Performs the padding, the Hash/HMAC will be 'closed' at the end of the block, as per MD5/SHA-1/SHA-2 specification [4:4] SHAMD5_MODE_HMAC_KEY_PROC HMAC Key Processing Enable [5:5] SHAMD5_MODE_HMAC_OUTER_HASH HMAC Outer Hash Processing Enable [7:7] LENGTH SHA Length 0x00000048 SHAMD5_LENGTH Block Length/Remaining Byte Count [31:0] DATA_0_IN SHA Data 0 Input 0x00000080 SHAMD5_DATA_0_IN_DATA Digest/Key Data [31:0] DATA_1_IN SHA Data 1 Input 0x00000084 SHAMD5_DATA_1_IN_DATA Digest/Key Data [31:0] DATA_2_IN SHA Data 2 Input 0x00000088 SHAMD5_DATA_2_IN_DATA Digest/Key Data [31:0] DATA_3_IN SHA Data 3 Input 0x0000008C SHAMD5_DATA_3_IN_DATA Digest/Key Data [31:0] DATA_4_IN SHA Data 4 Input 0x00000090 SHAMD5_DATA_4_IN_DATA Digest/Key Data [31:0] DATA_5_IN SHA Data 5 Input 0x00000094 SHAMD5_DATA_5_IN_DATA Digest/Key Data [31:0] DATA_6_IN SHA Data 6 Input 0x00000098 SHAMD5_DATA_6_IN_DATA Digest/Key Data [31:0] DATA_7_IN SHA Data 7 Input 0x0000009C SHAMD5_DATA_7_IN_DATA Digest/Key Data [31:0] DATA_8_IN SHA Data 8 Input 0x000000A0 SHAMD5_DATA_8_IN_DATA Digest/Key Data [31:0] DATA_9_IN SHA Data 9 Input 0x000000A4 SHAMD5_DATA_9_IN_DATA Digest/Key Data [31:0] DATA_10_IN SHA Data 10 Input 0x000000A8 SHAMD5_DATA_10_IN_DATA Digest/Key Data [31:0] DATA_11_IN SHA Data 11 Input 0x000000AC SHAMD5_DATA_11_IN_DATA Digest/Key Data [31:0] DATA_12_IN SHA Data 12 Input 0x000000B0 SHAMD5_DATA_12_IN_DATA Digest/Key Data [31:0] DATA_13_IN SHA Data 13 Input 0x000000B4 SHAMD5_DATA_13_IN_DATA Digest/Key Data [31:0] DATA_14_IN SHA Data 14 Input 0x000000B8 SHAMD5_DATA_14_IN_DATA Digest/Key Data [31:0] DATA_15_IN SHA Data 15 Input 0x000000BC SHAMD5_DATA_15_IN_DATA Digest/Key Data [31:0] REVISION SHA Revision 0x00000100 SHAMD5_REVISION Revision Number [31:0] SYSCONFIG SHA System Configuration 0x00000110 SHAMD5_SYSCONFIG_SOFTRESET Soft reset [1:1] SHAMD5_SYSCONFIG_IT_EN Interrupt Enable [2:2] SHAMD5_SYSCONFIG_DMA_EN uDMA Request Enable [3:3] SHAMD5_SYSCONFIG_SIDLE Sidle mode [5:4] SHAMD5_SYSCONFIG_SIDLE_FORCE Force-idle mode 0x0 SHAMD5_SYSCONFIG_SADVANCED Advanced Mode Enable [7:7] SYSSTATUS SHA System Status 0x00000114 SHAMD5_SYSSTATUS_RESETDONE Reset done status [0:0] IRQSTATUS SHA Interrupt Status 0x00000118 SHAMD5_IRQSTATUS_OUTPUT_READY Output Ready Status [0:0] SHAMD5_IRQSTATUS_INPUT_READY Input Ready Status [1:1] SHAMD5_IRQSTATUS_CONTEXT_READY Context Ready Status [3:3] IRQENABLE SHA Interrupt Enable 0x0000011C SHAMD5_IRQENABLE_OUTPUT_READY Mask for output ready interrupt [0:0] SHAMD5_IRQENABLE_INPUT_READY Mask for input ready interrupt [1:1] SHAMD5_IRQENABLE_CONTEXT_READY Mask for context ready interrupt [3:3] SHAMD5_DMA Register map for SHAMD5 DMA peripheral SHAMD5_DMA SHAMD5_DMA 0x44030010 0 0x00000010 registers SHAMD5_DMAIM SHAMD5 DMA Interrupt Mask 0x00000000 SHAMD5_DMAIM_CIN Context In DMA Done Interrupt Mask [0:0] SHAMD5_DMAIM_COUT Context Out DMA Done Interrupt Mask [1:1] SHAMD5_DMAIM_DIN Data In DMA Done Interrupt Mask [2:2] SHAMD5_DMAIM_DOUT Data Out DMA Done Interrupt Mask [3:3] SHAMD5_DMARIS SHAMD5 DMA Raw Interrupt Status 0x00000004 SHAMD5_DMARIS_CIN Context In DMA Done Raw Interrupt Status [0:0] SHAMD5_DMARIS_COUT Context Out DMA Done Raw Interrupt Status [1:1] SHAMD5_DMARIS_DIN Data In DMA Done Raw Interrupt Status [2:2] SHAMD5_DMARIS_DOUT Data Out DMA Done Raw Interrupt Status [3:3] SHAMD5_DMAMIS SHAMD5 DMA Masked Interrupt Status 0x00000008 SHAMD5_DMAMIS_CIN Context In DMA Done Masked Interrupt Status [0:0] SHAMD5_DMAMIS_COUT Context Out DMA Done Masked Interrupt Status [1:1] SHAMD5_DMAMIS_DIN Data In DMA Done Masked Interrupt Status [2:2] SHAMD5_DMAMIS_DOUT Data Out DMA Done Masked Interrupt Status [3:3] SHAMD5_DMAIC SHAMD5 DMA Interrupt Clear 0x0000000C SHAMD5_DMAIC_CIN Context In DMA Done Interrupt Clear [0:0] SHAMD5_DMAIC_COUT Context Out DMA Done Interrupt Clear [1:1] SHAMD5_DMAIC_DIN Data In DMA Done Interrupt Clear [2:2] SHAMD5_DMAIC_DOUT Data Out DMA Done Interrupt Clear [3:3] AES Register map for AES peripheral AES AES 0x44036000 0 0x00002000 registers KEY2_6 AES Key 2_6 0x00000000 AES_KEY2_6_KEY Key Data [31:0] KEY2_7 AES Key 2_7 0x00000004 AES_KEY2_7_KEY Key Data [31:0] KEY2_4 AES Key 2_4 0x00000008 AES_KEY2_4_KEY Key Data [31:0] KEY2_5 AES Key 2_5 0x0000000C AES_KEY2_5_KEY Key Data [31:0] KEY2_2 AES Key 2_2 0x00000010 AES_KEY2_2_KEY Key Data [31:0] KEY2_3 AES Key 2_3 0x00000014 AES_KEY2_3_KEY Key Data [31:0] KEY2_0 AES Key 2_0 0x00000018 AES_KEY2_0_KEY Key Data [31:0] KEY2_1 AES Key 2_1 0x0000001C AES_KEY2_1_KEY Key Data [31:0] KEY1_6 AES Key 1_6 0x00000020 AES_KEY1_6_KEY Key Data [31:0] KEY1_7 AES Key 1_7 0x00000024 AES_KEY1_7_KEY Key Data [31:0] KEY1_4 AES Key 1_4 0x00000028 AES_KEY1_4_KEY Key Data [31:0] KEY1_5 AES Key 1_5 0x0000002C AES_KEY1_5_KEY Key Data [31:0] KEY1_2 AES Key 1_2 0x00000030 AES_KEY1_2_KEY Key Data [31:0] KEY1_3 AES Key 1_3 0x00000034 AES_KEY1_3_KEY Key Data [31:0] KEY1_0 AES Key 1_0 0x00000038 AES_KEY1_0_KEY Key Data [31:0] KEY1_1 AES Key 1_1 0x0000003C AES_KEY1_1_KEY Key Data [31:0] IV_IN_0 AES Initialization Vector Input 0 0x00000040 AES_IV_IN_0_DATA Initialization Vector Input [31:0] IV_IN_1 AES Initialization Vector Input 1 0x00000044 AES_IV_IN_1_DATA Initialization Vector Input [31:0] IV_IN_2 AES Initialization Vector Input 2 0x00000048 AES_IV_IN_2_DATA Initialization Vector Input [31:0] IV_IN_3 AES Initialization Vector Input 3 0x0000004C AES_IV_IN_3_DATA Initialization Vector Input [31:0] CTRL AES Control 0x00000050 AES_CTRL_OUTPUT_READY Output Ready Status [0:0] AES_CTRL_INPUT_READY Input Ready Status [1:1] AES_CTRL_DIRECTION Encryption/Decryption Selection [2:2] AES_CTRL_KEY_SIZE Key Size [4:3] AES_CTRL_KEY_SIZE_128 Key is 128 bits 0x1 AES_CTRL_KEY_SIZE_192 Key is 192 bits 0x2 AES_CTRL_KEY_SIZE_256 Key is 256 bits 0x3 AES_CTRL_MODE ECB/CBC Mode [5:5] AES_CTRL_CTR Counter Mode [6:6] AES_CTRL_CTR_WIDTH AES-CTR Mode Counter Width [8:7] AES_CTRL_CTR_WIDTH_32 Counter is 32 bits 0x0 AES_CTRL_CTR_WIDTH_64 Counter is 64 bits 0x1 AES_CTRL_CTR_WIDTH_96 Counter is 96 bits 0x2 AES_CTRL_CTR_WIDTH_128 Counter is 128 bits 0x3 AES_CTRL_ICM AES Integer Counter Mode (ICM) Enable [9:9] AES_CTRL_CFB Full block AES cipher feedback mode (CFB128) Enable [10:10] AES_CTRL_XTS AES-XTS Operation Enabled [12:11] AES_CTRL_XTS_NOP No operation 0x0 AES_CTRL_XTS_TWEAKJL Previous/intermediate tweak value and j loaded (value is loaded via IV, j is loaded via the AAD length register) 0x1 AES_CTRL_XTS_K2IJL Key2, n and j are loaded (n is loaded via IV, j is loaded via the AAD length register) 0x2 AES_CTRL_XTS_K2ILJ0 Key2 and n are loaded; j=0 (n is loaded via IV) 0x3 AES_CTRL_F8 AES f8 Mode Enable [13:13] AES_CTRL_F9 AES f9 Mode Enable [14:14] AES_CTRL_CBCMAC AES-CBC MAC Enable [15:15] AES_CTRL_GCM AES-GCM Mode Enable [17:16] AES_CTRL_GCM_NOP No operation 0x0 AES_CTRL_GCM_HLY0ZERO GHASH with H loaded and Y0-encrypted forced to zero 0x1 AES_CTRL_GCM_HLY0CALC GHASH with H loaded and Y0-encrypted calculated internally 0x2 AES_CTRL_GCM_HY0CALC Autonomous GHASH (both H and Y0-encrypted calculated internally) 0x3 AES_CTRL_CCM AES-CCM Mode Enable [18:18] AES_CTRL_CCM_L L Value [21:19] AES_CTRL_CCM_L_2 width = 2 0x1 AES_CTRL_CCM_L_4 width = 4 0x3 AES_CTRL_CCM_L_8 width = 8 0x7 AES_CTRL_CCM_M Counter with CBC-MAC (CCM) [24:22] AES_CTRL_SAVE_CONTEXT TAG or Result IV Save [29:29] AES_CTRL_SVCTXTRDY AES TAG/IV Block(s) Ready [30:30] AES_CTRL_CTXTRDY Context Data Registers Ready [31:31] C_LENGTH_0 AES Crypto Data Length 0 0x00000054 AES_C_LENGTH_0_LENGTH Data Length [31:0] C_LENGTH_1 AES Crypto Data Length 1 0x00000058 AES_C_LENGTH_1_LENGTH Data Length [31:0] AUTH_LENGTH AES Authentication Data Length 0x0000005C AES_AUTH_LENGTH_AUTH Authentication Data Length [31:0] DATA_IN_0 AES Data RW Plaintext/Ciphertext 0 0x00000060 AES_DATA_IN_0_DATA Secure Data RW Plaintext/Ciphertext [31:0] DATA_IN_1 AES Data RW Plaintext/Ciphertext 1 0x00000064 AES_DATA_IN_1_DATA Secure Data RW Plaintext/Ciphertext [31:0] DATA_IN_2 AES Data RW Plaintext/Ciphertext 2 0x00000068 AES_DATA_IN_2_DATA Secure Data RW Plaintext/Ciphertext [31:0] DATA_IN_3 AES Data RW Plaintext/Ciphertext 3 0x0000006C AES_DATA_IN_3_DATA Secure Data RW Plaintext/Ciphertext [31:0] TAG_OUT_0 AES Hash Tag Out 0 0x00000070 AES_TAG_OUT_0_HASH Hash Result [31:0] TAG_OUT_1 AES Hash Tag Out 1 0x00000074 AES_TAG_OUT_1_HASH Hash Result [31:0] TAG_OUT_2 AES Hash Tag Out 2 0x00000078 AES_TAG_OUT_2_HASH Hash Result [31:0] TAG_OUT_3 AES Hash Tag Out 3 0x0000007C AES_TAG_OUT_3_HASH Hash Result [31:0] REVISION AES IP Revision Identifier 0x00000080 AES_REVISION Revision number [31:0] SYSCONFIG AES System Configuration 0x00000084 AES_SYSCONFIG_SOFTRESET Soft reset [1:1] AES_SYSCONFIG_DMA_REQ_DATA_IN_EN DMA Request Data In Enable [5:5] AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN DMA Request Data Out Enable [6:6] AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN DMA Request Context In Enable [7:7] AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN DMA Request Context Out Enable [8:8] AES_SYSCONFIG_MAP_CONTEXT_OUT_ON_DATA_OUT Map Context Out on Data Out Enable [9:9] AES_SYSCONFIG_KEYENC Key Encoding [11:11] AES_SYSCONFIG_K3 K3 Select [12:12] SYSSTATUS AES System Status 0x00000088 AES_SYSSTATUS_RESETDONE Reset Done [0:0] IRQSTATUS AES Interrupt Status 0x0000008C AES_IRQSTATUS_CONTEXT_IN Context In Interrupt Status [0:0] AES_IRQSTATUS_DATA_IN Data In Interrupt Status [1:1] AES_IRQSTATUS_DATA_OUT Data Out Interrupt Status [2:2] AES_IRQSTATUS_CONTEXT_OUT Context Output Interrupt Status [3:3] IRQENABLE AES Interrupt Enable 0x00000090 AES_IRQENABLE_CONTEXT_IN Context In Interrupt Enable [0:0] AES_IRQENABLE_DATA_IN Data In Interrupt Enable [1:1] AES_IRQENABLE_DATA_OUT Data Out Interrupt Enable [2:2] AES_IRQENABLE_CONTEXT_OUT Context Out Interrupt Enable [3:3] DIRTYBITS AES Dirty Bits 0x00000094 AES_DIRTYBITS_S_ACCESS AES Access Bit [0:0] AES_DIRTYBITS_S_DIRTY AES Dirty Bit [1:1] AES_DMA Register map for AES DMA peripheral AES_DMA AES_DMA 0x44030020 0 0x00000010 registers AES_DMAIM AES DMA Interrupt Mask 0x00000000 AES_DMAIM_CIN Context In DMA Done Interrupt Mask [0:0] AES_DMAIM_COUT Context Out DMA Done Interrupt Mask [1:1] AES_DMAIM_DIN Data In DMA Done Interrupt Mask [2:2] AES_DMAIM_DOUT Data Out DMA Done Interrupt Mask [3:3] AES_DMARIS AES DMA Raw Interrupt Status 0x00000004 AES_DMARIS_CIN Context In DMA Done Raw Interrupt Status [0:0] AES_DMARIS_COUT Context Out DMA Done Raw Interrupt Status [1:1] AES_DMARIS_DIN Data In DMA Done Raw Interrupt Status [2:2] AES_DMARIS_DOUT Data Out DMA Done Raw Interrupt Status [3:3] AES_DMAMIS AES DMA Masked Interrupt Status 0x00000008 AES_DMAMIS_CIN Context In DMA Done Masked Interrupt Status [0:0] AES_DMAMIS_COUT Context Out DMA Done Masked Interrupt Status [1:1] AES_DMAMIS_DIN Data In DMA Done Masked Interrupt Status [2:2] AES_DMAMIS_DOUT Data Out DMA Done Masked Interrupt Status [3:3] AES_DMAIC AES DMA Interrupt Clear 0x0000000C AES_DMAIC_CIN Context In DMA Done Interrupt Clear [0:0] AES_DMAIC_COUT Context Out DMA Done Interrupt Clear [1:1] AES_DMAIC_DIN Data In DMA Done Interrupt Clear [2:2] AES_DMAIC_DOUT Data Out DMA Done Interrupt Clear [3:3] DES Register map for DES peripheral DES DES 0x44038000 0 0x00002000 registers KEY3_L DES Key 3 LSW for 192-Bit Key 0x00000000 DES_KEY3_L_KEY Key Data [31:0] KEY3_H DES Key 3 MSW for 192-Bit Key 0x00000004 DES_KEY3_H_KEY Key Data [31:0] KEY2_L DES Key 2 LSW for 128-Bit Key 0x00000008 DES_KEY2_L_KEY Key Data [31:0] KEY2_H DES Key 2 MSW for 128-Bit Key 0x0000000C DES_KEY2_H_KEY Key Data [31:0] KEY1_L DES Key 1 LSW for 64-Bit Key 0x00000010 DES_KEY1_L_KEY Key Data [31:0] KEY1_H DES Key 1 MSW for 64-Bit Key 0x00000014 DES_KEY1_H_KEY Key Data [31:0] IV_L DES Initialization Vector 0x00000018 DES_IV_L Initialization vector for CBC, CFB modes (LSW) [31:0] IV_H DES Initialization Vector 0x0000001C DES_IV_H Initialization vector for CBC, CFB modes (MSW) [31:0] CTRL DES Control 0x00000020 DES_CTRL_OUTPUT_READY When 1, Data decrypted/encrypted ready [0:0] DES_CTRL_INPUT_READY When 1, ready to encrypt/decrypt data [1:1] DES_CTRL_DIRECTION Select encryption/decryption 0x0: decryption is selected0x1: Encryption is selected [2:2] DES_CTRL_TDES Select DES or triple DES encryption/decryption [3:3] DES_CTRL_MODE Select CBC, ECB or CFB mode0x0: ECB mode0x1: CBC mode0x2: CFB mode0x3: reserved [5:4] DES_CTRL_CONTEXT If 1, this read-only status bit indicates that the context data registers can be overwritten and the host is permitted to write the next context [31:31] LENGTH DES Cryptographic Data Length 0x00000024 DES_LENGTH Cryptographic data length in bytes for all modes [31:0] DATA_L DES LSW Data RW 0x00000028 DES_DATA_L Data for encryption/decryption, LSW [31:0] DATA_H DES MSW Data RW 0x0000002C DES_DATA_H Data for encryption/decryption, MSW [31:0] REVISION DES Revision Number 0x00000030 DES_REVISION Revision number [31:0] SYSCONFIG DES System Configuration 0x00000034 DES_SYSCONFIG_SOFTRESET Soft reset [1:1] DES_SYSCONFIG_SIDLE Sidle mode [3:2] DES_SYSCONFIG_SIDLE_FORCE Force-idle mode 0x0 DES_SYSCONFIG_DMA_REQ_DATA_IN_EN DMA Request Data In Enable [5:5] DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN DMA Request Data Out Enable [6:6] DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN DMA Request Context In Enable [7:7] SYSSTATUS DES System Status 0x00000038 DES_SYSSTATUS_RESETDONE Reset Done [0:0] IRQSTATUS DES Interrupt Status 0x0000003C DES_IRQSTATUS_CONTEX_IN This bit indicates context interrupt is active and triggers the interrupt output [0:0] DES_IRQSTATUS_DATA_IN This bit indicates data input interrupt is active and triggers the interrupt output [1:1] DES_IRQSTATUS_DATA_OUT This bit indicates data output interrupt is active and triggers the interrupt output [2:2] IRQENABLE DES Interrupt Enable 0x00000040 DES_IRQENABLE_M_CONTEX_IN If this bit is set to 1 the context interrupt is enabled [0:0] DES_IRQENABLE_M_DATA_IN If this bit is set to 1 the data input interrupt is enabled [1:1] DES_IRQENABLE_M_DATA_OUT If this bit is set to 1 the data output interrupt is enabled [2:2] DIRTYBITS DES Dirty Bits 0x00000044 DES_DIRTYBITS_S_ACCESS This bit is set to 1 by the module if any of the DES_* registers is read [0:0] DES_DIRTYBITS_S_DIRTY This bit is set to 1 by the module if any of the DES_* registers is written [1:1] DES_DMA Register map for DES DMA peripheral DES_DMA DES_DMA 0x44030030 0 0x00000010 registers DES_DMAIM DES DMA Interrupt Mask 0x00000000 DES_DMAIM_CIN Context In DMA Done Interrupt Mask [0:0] DES_DMAIM_COUT Context Out DMA Done Interrupt Mask [1:1] DES_DMAIM_DIN Data In DMA Done Interrupt Mask [2:2] DES_DMAIM_DOUT Data Out DMA Done Interrupt Mask [3:3] DES_DMARIS DES DMA Raw Interrupt Status 0x00000004 DES_DMARIS_CIN Context In DMA Done Raw Interrupt Status [0:0] DES_DMARIS_COUT Context Out DMA Done Raw Interrupt Status [1:1] DES_DMARIS_DIN Data In DMA Done Raw Interrupt Status [2:2] DES_DMARIS_DOUT Data Out DMA Done Raw Interrupt Status [3:3] DES_DMAMIS DES DMA Masked Interrupt Status 0x00000008 DES_DMAMIS_CIN Context In DMA Done Masked Interrupt Status [0:0] DES_DMAMIS_COUT Context Out DMA Done Masked Interrupt Status [1:1] DES_DMAMIS_DIN Data In DMA Done Masked Interrupt Status [2:2] DES_DMAMIS_DOUT Data Out DMA Done Masked Interrupt Status [3:3] DES_DMAIC DES DMA Interrupt Clear 0x0000000C DES_DMAIC_CIN Context In DMA Done Interrupt Clear [0:0] DES_DMAIC_COUT Context Out DMA Done Interrupt Clear [1:1] DES_DMAIC_DIN Data In DMA Done Interrupt Clear [2:2] DES_DMAIC_DOUT Data Out DMA Done Interrupt Clear [3:3] LCD0 Register map for LCD0 peripheral LCD LCD0 0x44050000 0 0x00001000 registers LCD097 PID LCD PID Register Format 0x00000000 LCD_PID_MINOR Minor Release Number [5:0] LCD_PID_MAJOR Major Release Number [10:8] CTL LCD Control 0x00000004 LCD_CTL_LCDMODE LCD Mode Select [0:0] LCD_CTL_UFLOWRST Underflow Restart [1:1] LCD_CTL_CLKDIV Clock Divisor [15:8] LIDDCTL LCD LIDD Control 0x0000000C LCD_LIDDCTL_MODE LIDD Mode Select [2:0] LCD_LIDDCTL_MODE_SYNCM68 Synchronous Motorola 6800 Mode 0x0 LCD_LIDDCTL_MODE_ASYNCM68 Asynchronous Motorola 6800 Mode 0x1 LCD_LIDDCTL_MODE_SYNCM80 Synchronous Intel 8080 mode 0x2 LCD_LIDDCTL_MODE_ASYNCM80 Asynchronous Intel 8080 mode 0x3 LCD_LIDDCTL_MODE_ASYNCHIT Asynchronous Hitachi mode 0x4 LCD_LIDDCTL_ALE Address Latch Enable (ALE) Polarity Control [3:3] LCD_LIDDCTL_RDEN Read Strobe (RD) /Direct Enable (EN) Polarity Control [4:4] LCD_LIDDCTL_WRDIRINV Write Strobe (WR) /Direction (DIR) Polarity Control [5:5] LCD_LIDDCTL_CS0E0 Chip Select 0 (CS0)/Enable 0 (E0) Polarity Control [6:6] LCD_LIDDCTL_CS1E1 Chip Select 1 (CS1)/Enable 1(E1) Polarity Control [7:7] LCD_LIDDCTL_DMAEN LIDD DMA Enable [8:8] LCD_LIDDCTL_DMACS CS0/CS1 Select for LIDD DMA Writes [9:9] LIDDCS0CFG LCD LIDD CS0 Configuration 0x00000010 LCD_LIDDCS0CFG_GAP Field value defines the number of LCDMCLK cycles (GAP +1) between the end of one CS0 (LCDAC) device access and the start of another CS0 (LCDAC) device access unless the two accesses are both reads [1:0] LCD_LIDDCS0CFG_RDHOLD Read Strobe (RD) Hold cycles [5:2] LCD_LIDDCS0CFG_RDDUR Read Strobe (RD) Duration cycles [11:6] LCD_LIDDCS0CFG_RDSU Read Strobe (RD) Set-Up cycles [16:12] LCD_LIDDCS0CFG_WRHOLD Write Strobe (WR) Hold cycles [20:17] LCD_LIDDCS0CFG_WRDUR Write Strobe (WR) Duration Cycles [26:21] LCD_LIDDCS0CFG_WRSU Write Strobe (WR) Set-Up Cycles [31:27] LIDDCS0ADDR LIDD CS0 Read/Write Address 0x00000014 LCD_LIDDCS0ADDR_CS0ADDR LCD Address [15:0] LIDDCS0DATA LIDD CS0 Data Read/Write Initiation 0x00000018 LCD_LIDDCS0DATA_CS0DATA LCD Data Read/Write [15:0] LIDDCS1CFG LIDD CS1 Configuration 0x0000001C LCD_LIDDCS1CFG_GAP Field value defines the number of LCDMCLK cycles (GAP + 1) between the end of one CS1 (LCDAC) device access and the start of another CS0 (LCDAC) device access unless the two accesses are both reads [1:0] LCD_LIDDCS1CFG_RDHOLD Read Strobe (RD) Hold cycles [5:2] LCD_LIDDCS1CFG_RDDUR Read Strobe (RD) Duration cycles [11:6] LCD_LIDDCS1CFG_RDSU Read Strobe (RD) Set-Up cycles [16:12] LCD_LIDDCS1CFG_WRHOLD Write Strobe (WR) Hold cycles [20:17] LCD_LIDDCS1CFG_WRDUR Write Strobe (WR) Duration Cycles [26:21] LCD_LIDDCS1CFG_WRSU Write Strobe (WR) Set-Up Cycles [31:27] LIDDCS1ADDR LIDD CS1 Address Read/Write Initiation 0x00000020 LCD_LIDDCS1ADDR_CS1ADDR LCD Address Bus [15:0] LIDDCS1DATA LIDD CS1 Data Read/Write Initiation 0x00000024 LCD_LIDDCS1DATA_CS0DATA LCD Data Read/Write Initiation [15:0] RASTRCTL LCD Raster Control 0x00000028 LCD_RASTRCTL_LCDEN LCD Controller Enable for Raster Operations [0:0] LCD_RASTRCTL_LCDBW LCD Monochrome [1:1] LCD_RASTRCTL_LCDTFT LCD TFT [7:7] LCD_RASTRCTL_RDORDER Raster Data Order Select [8:8] LCD_RASTRCTL_MONO8B Mono 8-Bit [9:9] LCD_RASTRCTL_REQDLY Palette Loading Delay [19:12] LCD_RASTRCTL_PALMODE Pallette Loading Mode [21:20] LCD_RASTRCTL_PALMODE_PALDAT Palette and data loading, reset value 0x0 LCD_RASTRCTL_PALMODE_PAL Palette loading only 0x1 LCD_RASTRCTL_PALMODE_DAT Data loading only 0x2 LCD_RASTRCTL_NIBMODE Nibble Mode [22:22] LCD_RASTRCTL_TFTMAP TFT Mode Alternate Signal Mapping for Palettized Framebuffer [23:23] LCD_RASTRCTL_FRMBUFSZ Frame Buffer Select [24:24] LCD_RASTRCTL_TFT24 24-Bit TFT Mode [25:25] LCD_RASTRCTL_TFT24UPCK 24-bit TFT Mode Packing [26:26] RASTRTIM0 LCD Raster Timing 0 0x0000002C LCD_RASTRTIM0_MSBPPL Pixels-per-line MSB[10] [3:3] LCD_RASTRTIM0_PPL Pixels-per-line LSB[9:4] [9:4] LCD_RASTRTIM0_HSW Horizontal Sync Pulse Width Lowbits [15:10] LCD_RASTRTIM0_HFP Horizontal Front Porch Lowbits [23:16] LCD_RASTRTIM0_HBP Horizontal Back Porch Lowbits [31:24] RASTRTIM1 LCD Raster Timing 1 0x00000030 LCD_RASTRTIM1_LPP Lines Per Panel [9:0] LCD_RASTRTIM1_VSW Vertical Sync Width Pulse [15:10] LCD_RASTRTIM1_VFP Vertical Front Porch [23:16] LCD_RASTRTIM1_VBP Vertical Back Porch [31:24] RASTRTIM2 LCD Raster Timing 2 0x00000034 LCD_RASTRTIM2_MSBHFP Bits 9:8 of the horizontal front porch field [1:0] LCD_RASTRTIM2_MSBHBP Bits 9:8 of the horizontal back porch field [5:4] LCD_RASTRTIM2_ACBF AC Bias Pin Frequency [15:8] LCD_RASTRTIM2_ACBI AC Bias Pins Transitions per Interrupt [19:16] LCD_RASTRTIM2_IVS Invert Vsync [20:20] LCD_RASTRTIM2_IHS Invert Hysync [21:21] LCD_RASTRTIM2_INVPXLCLK Invert Pixel Clock [22:22] LCD_RASTRTIM2_INVOE Invert Output Enable [23:23] LCD_RASTRTIM2_PSYNCRF Program HSYNC/VSYNC Rise or Fall [24:24] LCD_RASTRTIM2_PXLCLKCTL Hsync/Vsync Pixel Clock Control On/Off [25:25] LCD_RASTRTIM2_MSBLPP MSB of Lines Per Panel [26:26] LCD_RASTRTIM2_HSW Bits 9:6 of the horizontal sync width field [30:27] RASTRSUBP1 LCD Raster Subpanel Display 1 0x00000038 LCD_RASTRSUBP1_DPDLSB Default Pixel Data LSB[15:0] [15:0] LCD_RASTRSUBP1_LPPT Line Per Panel Threshold [25:16] LCD_RASTRSUBP1_HOLS High or Low Signal [29:29] LCD_RASTRSUBP1_SPEN Sub Panel Enable [31:31] RASTRSUBP2 LCD Raster Subpanel Display 2 0x0000003C LCD_RASTRSUBP2_DPDMSB Default Pixel Data MSB [23:16] [7:0] LCD_RASTRSUBP2_LPPTMSB Lines Per Panel Threshold Bit 10 [8:8] DMACTL LCD DMA Control 0x00000040 LCD_DMACTL_FMODE Frame Mode [0:0] LCD_DMACTL_BIGDEND Big Endian Enable [1:1] LCD_DMACTL_BYTESWAP This bit controls the bytelane ordering of the data on the output of the DMA module [3:3] LCD_DMACTL_BURSTSZ Burst Size setting for DMA transfers (all DMA transfers are 32 bits wide): [6:4] LCD_DMACTL_BURSTSZ_4 burst size of 4 0x2 LCD_DMACTL_BURSTSZ_8 burst size of 8 0x3 LCD_DMACTL_BURSTSZ_16 burst size of 16 0x4 LCD_DMACTL_FIFORDY DMA FIFO threshold [10:8] LCD_DMACTL_FIFORDY_8 8 words 0x0 LCD_DMACTL_FIFORDY_16 16 words 0x1 LCD_DMACTL_FIFORDY_32 32 words 0x2 LCD_DMACTL_FIFORDY_64 64 words 0x3 LCD_DMACTL_FIFORDY_128 128 words 0x4 LCD_DMACTL_FIFORDY_256 256 words 0x5 LCD_DMACTL_FIFORDY_512 512 words 0x6 DMABAFB0 LCD DMA Frame Buffer 0 Base Address 0x00000044 LCD_DMABAFB0_FB0BA Frame Buffer 0 Base Address pointer [31:2] DMACAFB0 LCD DMA Frame Buffer 0 Ceiling Address 0x00000048 LCD_DMACAFB0_FB0CA Frame Buffer 0 Ceiling Address pointer [31:2] DMABAFB1 LCD DMA Frame Buffer 1 Base Address 0x0000004C LCD_DMABAFB1_FB1BA Frame Buffer 1 Base Address pointer [31:2] DMACAFB1 LCD DMA Frame Buffer 1 Ceiling Address 0x00000050 LCD_DMACAFB1_FB1CA Frame Buffer 1 Ceiling Address pointer [31:2] SYSCFG LCD System Configuration Register 0x00000054 LCD_SYSCFG_IDLEMODE Idle Mode [3:2] LCD_SYSCFG_IDLEMODE_FORCE Force-idle mode: local target's idle state follows (acknowledges) the system's idle requests unconditionally, that is, regardless of the IP module's internal requirements. Backup mode, for debug only 0x0 LCD_SYSCFG_IDLEMODE_NONE No-idle mode: local target never enters idle state. Backup mode, for debug only 0x1 LCD_SYSCFG_IDLEMODE_SMART Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-requestrelated) wakeup events 0x2 LCD_SYSCFG_STDBY Standby Mode [5:4] LCD_SYSCFG_STDBY_FORCE Force-standby mode: local initiator is unconditionally placed in standby state. Backup mode, for debug only 0x0 LCD_SYSCFG_STDBY_NONE No-standby mode: local initiator is unconditionally placed out of standby state. Backup mode, for debug only 0x1 LCD_SYSCFG_STDBY_SMART Smart-standby mode: local initiator standby status depends on local conditions, that is, the module's functional requirement from the initiator. IP module shall not generate (initiator-related) wakeup events 0x2 RISSET LCD Interrupt Raw Status and Set Register 0x00000058 LCD_RISSET_DONE Raster or LIDD Frame Done (shared, depends on whether Raster or LIDD mode enabled) Raw Interrupt Status and Set [0:0] LCD_RISSET_RRASTRDONE Raster Mode Frame Done interrupt [1:1] LCD_RISSET_SYNCS Frame Synchronization Lost Raw Interrupt Status and Set [2:2] LCD_RISSET_ACBS AC Bias Count Raw Interrupt Status and Set [3:3] LCD_RISSET_FIFOU DMA FIFO Underflow Raw Interrupt Status and Set [5:5] LCD_RISSET_PALLOAD DMA Palette Loaded Raw Interrupt Status and Set [6:6] LCD_RISSET_EOF0 DMA End-of-Frame 0 Raw Interrupt Status and Set [8:8] LCD_RISSET_EOF1 DMA End-of-Frame 1 Raw Interrupt Status and Set [9:9] MISCLR LCD Interrupt Status and Clear 0x0000005C LCD_MISCLR_DONE Raster or LIDD Frame Done (shared, depends on whether Raster or LIDD mode enabled) Enabled Interrupt and Clear [0:0] LCD_MISCLR_RRASTRDONE Raster Mode Frame Done interrupt [1:1] LCD_MISCLR_SYNCS Frame Synchronization Lost Enabled Interrupt and Clear [2:2] LCD_MISCLR_ACBS AC Bias Count Enabled Interrupt and Clear [3:3] LCD_MISCLR_FIFOU DMA FIFO Underflow Enabled Interrupt and Clear [5:5] LCD_MISCLR_PALLOAD DMA Palette Loaded Enabled Interrupt and Clear [6:6] LCD_MISCLR_EOF0 DMA End-of-Frame 0 Raw Interrupt and Clear [8:8] LCD_MISCLR_EOF1 DMA End-of-Frame 1 Enabled Interrupt and Clear [9:9] IM LCD Interrupt Mask 0x00000060 LCD_IM_DONE Raster or LIDD Frame Done (shared, depends on whether Raster or LIDD mode enabled) Interrupt Enable Set [0:0] LCD_IM_RRASTRDONE Raster Mode Frame Done Interrupt Enable Set [1:1] LCD_IM_SYNCS Frame Synchronization Lost Interrupt Enable Set [2:2] LCD_IM_ACBS AC Bias Count Interrupt Enable Set [3:3] LCD_IM_FIFOU DMA FIFO Underflow Interrupt Enable Set [5:5] LCD_IM_PALLOAD DMA Palette Loaded Interrupt Enable Set [6:6] LCD_IM_EOF0 DMA End-of-Frame 0 Interrupt Enable Set [8:8] LCD_IM_EOF1 DMA End-of-Frame 1 Interrupt Enable Set [9:9] IENC LCD Interrupt Enable Clear 0x00000064 LCD_IENC_DONE Raster or LIDD Frame Done (shared, depends on whether Raster or LIDD mode enabled) Interrupt Enable Clear [0:0] LCD_IENC_RRASTRDONE Raster Mode Frame Done Interrupt Enable Clear [1:1] LCD_IENC_SYNCS Frame Synchronization Lost Interrupt Enable Clear [2:2] LCD_IENC_ACBS AC Bias Count Interrupt Enable Clear [3:3] LCD_IENC_FIFOU DMA FIFO Underflow Interrupt Enable Clear [5:5] LCD_IENC_PALLOAD DMA Palette Loaded Interrupt Enable Clear [6:6] LCD_IENC_EOF0 DMA End-of-Frame 0 Interrupt Enable Clear [8:8] LCD_IENC_EOF1 DMA End-of-Frame 1 Interrupt Enable Clear [9:9] CLKEN LCD Clock Enable 0x0000006C LCD_CLKEN_CORE LCD Core Clock Enable [0:0] LCD_CLKEN_LIDD LIDD Submodule Clock Enable [1:1] LCD_CLKEN_DMA DMA Clock Enable [2:2] CLKRESET LCD Clock Resets 0x00000070 LCD_CLKRESET_CORE Software Reset for the Core, which encompasses the Raster Active Matrix and Passive Matrix logic [0:0] LCD_CLKRESET_LIDD Software Reset for the LIDD submodule (character displays) [1:1] LCD_CLKRESET_DMA Software Reset for the DMA submodule [2:2] LCD_CLKRESET_MAIN Software Reset for the entire LCD module [3:3] FLASH FLASH Memory Map for MSP432E411Y 0x00000000 0 0x00100000 FLASH Memory ROM ROM Memory Map for MSP432E411Y 0x01000000 0 0x00008c00 ROM Boot Loader SRAM SRAM Memory Map for MSP432E411Y 0x20000000 0 0x00040000 SRAM