CC26x0 2.3 SimpleLink CC26xx Ultra-low power wireless MCU CM3 r2p1 little false false 3 false 8 32 32 read-write 0xFFFFFFFF AON_BATMON Always On (AON) Battery And Temperature MONitor (BATMON) residing in the AON domain Note: This module only supports 32 bit Read/Write access from MCU. 0x40095000 0 0x400 registers CTL Internal. Only to be used through TI provided API. 0 read-write 0x00000000 CALC_EN CALC_EN [1:1] MEAS_EN MEAS_EN [0:0] MEASCFG Internal. Only to be used through TI provided API. 4 read-write 0x00000000 PER PER [1:0] TEMPP0 Internal. Only to be used through TI provided API. 12 read-write 0x00000000 CFG CFG [7:0] TEMPP1 Internal. Only to be used through TI provided API. 16 read-write 0x00000000 CFG CFG [5:0] TEMPP2 Internal. Only to be used through TI provided API. 20 read-write 0x00000000 CFG CFG [4:0] BATMONP0 Internal. Only to be used through TI provided API. 24 read-write 0x00000000 CFG CFG [5:0] BATMONP1 Internal. Only to be used through TI provided API. 28 read-write 0x00000000 CFG CFG [5:0] IOSTRP0 Internal. Only to be used through TI provided API. 32 read-write 0x00000028 CFG2 CFG2 [5:4] CFG1 CFG1 [3:0] FLASHPUMPP0 Internal. Only to be used through TI provided API. 36 read-write 0x00000000 FALLB FALLB [8:8] HIGHLIM HIGHLIM [7:6] LOWLIM LOWLIM [5:5] OVR OVR [4:4] CFG CFG [3:0] BAT Last Measured Battery Voltage This register may be read while BATUPD.STAT = 1 40 read-only 0x00000000 INT INT [10:8] FRAC FRAC [7:0] BATUPD Battery Update Indicates BAT Updates 44 read-write 0x00000000 STAT STAT [0:0] oneToClear TEMP Temperature Last Measured Temperature in Degrees Celsius This register may be read while TEMPUPD.STAT = 1. 48 read-only 0x00000000 INT INT [16:8] TEMPUPD Temperature Update Indicates TEMP Updates 52 read-write 0x00000000 STAT STAT [0:0] oneToClear AON_EVENT This module configures the event fabric located in the AON domain. Note: This module is only supporting 32 bit ReadWrite access from MCU 0x40093000 0 0x400 registers MCUWUSEL Wake-up Selector For MCU This register contains pointers to 4 events which are routed to AON_WUC as wakeup sources for MCU. AON_WUC will start a wakeup sequence for the MCU domain when either of the 4 selected events are asserted. A wakeup sequence will guarantee that the MCU power switches are turned on, LDO resources are available and SCLK_HF is available and selected as clock source for MCU. Note: It is recommended ( or required when AON_WUC:MCUCLK.PWR_DWN_SRC=NONE) to also setup a wakeup event here before MCU is requesting powerdown. ( PRCM requests uLDO, see conditions in PRCM:VDCTL.ULDO ) as it will speed up the wakeup procedure. 0 read-write 0x3f3f3f3f WU3_EV WU3_EV [29:24] WU2_EV WU2_EV [21:16] WU1_EV WU1_EV [13:8] WU0_EV WU0_EV [5:0] AUXWUSEL Wake-up Selector For AUX This register contains pointers to 3 events which are routed to AON_WUC as wakeup sources for AUX. AON_WUC will start a wakeup sequence for the AUX domain when either of the 3 selected events are asserted. A wakeup sequence will guarantee that the AUX power switches are turned on, LDO resources are available and SCLK_HF is available and selected as clock source for AUX. Note: It is recommended ( or required when AON_WUC:AUXCLK.PWR_DWN_SRC=NONE) to also setup a wakeup event here before AUX is requesting powerdown. ( AUX_WUC:PWRDWNREQ.REQ is asserted] ) as it will speed up the wakeup procedure. 4 read-write 0x003f3f3f WU2_EV WU2_EV [21:16] WU1_EV WU1_EV [13:8] WU0_EV WU0_EV [5:0] EVTOMCUSEL Event Selector For MCU Event Fabric This register contains pointers for 3 AON events that are routed to the MCU Event Fabric EVENT 8 read-write 0x002b2b2b AON_PROG2_EV AON_PROG2_EV [21:16] AON_PROG1_EV AON_PROG1_EV [13:8] AON_PROG0_EV AON_PROG0_EV [5:0] RTCSEL RTC Capture Event Selector For AON_RTC This register contains a pointer to select an AON event for RTC capture. Please refer to AON_RTC:CH1CAPT 12 read-write 0x0000003f RTC_CH1_CAPT_EV RTC_CH1_CAPT_EV [5:0] AON_IOC Always On (AON) IO Controller - controls IO operation when the MCU IO Controller (IOC) is powered off and resides in the AON domain. Note: This module only supports 32 bit Read/Write access from MCU. 0x40094000 0 0x400 registers IOSTRMIN Internal. Only to be used through TI provided API. 0 read-write 0x00000003 GRAY_CODE GRAY_CODE [2:0] IOSTRMED Internal. Only to be used through TI provided API. 4 read-write 0x00000006 GRAY_CODE GRAY_CODE [2:0] IOSTRMAX Internal. Only to be used through TI provided API. 8 read-write 0x00000005 GRAY_CODE GRAY_CODE [2:0] IOCLATCH IO Latch Control Controls transparency of all latches holding I/O or configuration state from the MCU IOC 12 read-write 0x00000001 EN EN [0:0] CLK32KCTL SCLK_LF External Output Control 16 read-write 0x00000001 OE_N OE_N [0:0] AON_RTC This component control the Real Time Clock residing in AON Note: This module is only supporting 32 bit ReadWrite access. 0x40092000 0 0x400 registers CTL Control This register contains various bitfields for configuration of RTC 0 read-write 0x00000000 COMB_EV_MASK COMB_EV_MASK [18:16] EV_DELAY EV_DELAY [11:8] RESET RESET [7:7] oneToClear RTC_4KHZ_EN RTC_4KHZ_EN [2:2] RTC_UPD_EN RTC_UPD_EN [1:1] EN EN [0:0] EVFLAGS Event Flags, RTC Status This register contains event flags from the 3 RTC channels. Each flag will be cleared when writing a '1' to the corresponding bitfield. 4 read-write 0x00000000 CH2 CH2 [16:16] oneToClear CH1 CH1 [8:8] oneToClear CH0 CH0 [0:0] oneToClear SEC Second Counter Value, Integer Part 8 read-write 0x00000000 VALUE VALUE [31:0] SUBSEC Second Counter Value, Fractional Part 12 read-write 0x00000000 VALUE VALUE [31:0] SUBSECINC Subseconds Increment Value added to SUBSEC.VALUE on every SCLK_LFclock cycle. 16 read-only 0x00800000 VALUEINC VALUEINC [23:0] CHCTL Channel Configuration 20 read-write 0x00000000 CH2_CONT_EN CH2_CONT_EN [18:18] CH2_EN CH2_EN [16:16] CH1_CAPT_EN CH1_CAPT_EN [9:9] CH1_EN CH1_EN [8:8] CH0_EN CH0_EN [0:0] CH0CMP Channel 0 Compare Value 24 read-write 0x00000000 VALUE VALUE [31:0] CH1CMP Channel 1 Compare Value 28 read-write 0x00000000 VALUE VALUE [31:0] CH2CMP Channel 2 Compare Value 32 read-write 0x00000000 VALUE VALUE [31:0] CH2CMPINC Channel 2 Compare Value Auto-increment This register is primarily used to generate periodical wake-up for the AUX_SCE module, through the [AUX_EVCTL.EVSTAT0.AON_RTC] event. 36 read-write 0x00000000 VALUE VALUE [31:0] CH1CAPT Channel 1 Capture Value If CHCTL.CH1_EN = 1and CHCTL.CH1_CAPT_EN = 1, capture occurs on each rising edge of the event selected in AON_EVENT:RTCSEL. 40 read-only 0x00000000 SEC SEC [31:16] SUBSEC SUBSEC [15:0] SYNC AON Synchronization This register is used for synchronizing between MCU and entire AON domain. 44 read-write 0x00000000 WBUSY WBUSY [0:0] AON_SYSCTL This component controls AON_SYSCTL, which is the device's system controller. Note: This module is only supporting 32 bit ReadWrite access from MCU 0x40090000 0 0x400 registers PWRCTL Power Management This register controls bitfields for setting low level power management features such as selection of regulator for VDDR supply and control of IO ring where certain segments can be enabled / disabled. 0 read-write 0x00000000 DCDC_ACTIVE DCDC_ACTIVE [2:2] EXT_REG_MODE EXT_REG_MODE [1:1] DCDC_EN DCDC_EN [0:0] RESETCTL Reset Management This register contains bitfields releated to system reset such as reset source and reset request and control of brown out resets. 4 read-write 0x000000e0 SYSRESET SYSRESET [31:31] BOOT_DET_1_CLR BOOT_DET_1_CLR [25:25] BOOT_DET_0_CLR BOOT_DET_0_CLR [24:24] BOOT_DET_1_SET BOOT_DET_1_SET [17:17] BOOT_DET_0_SET BOOT_DET_0_SET [16:16] WU_FROM_SD WU_FROM_SD [15:15] GPIO_WU_FROM_SD GPIO_WU_FROM_SD [14:14] BOOT_DET_1 BOOT_DET_1 [13:13] BOOT_DET_0 BOOT_DET_0 [12:12] VDDS_LOSS_EN_OVR VDDS_LOSS_EN_OVR [11:11] VDDR_LOSS_EN_OVR VDDR_LOSS_EN_OVR [10:10] VDD_LOSS_EN_OVR VDD_LOSS_EN_OVR [9:9] VDDS_LOSS_EN VDDS_LOSS_EN [7:7] VDDR_LOSS_EN VDDR_LOSS_EN [6:6] VDD_LOSS_EN VDD_LOSS_EN [5:5] CLK_LOSS_EN CLK_LOSS_EN [4:4] RESET_SRC RESET_SRC [3:1] SLEEPCTL Sleep Mode This register is used to unfreeze the IO pad ring after waking up from SHUTDOWN 8 read-write 0x00000000 IO_PAD_SLEEP_DIS IO_PAD_SLEEP_DIS [0:0] AON_WUC This component control the Wakeup controller residing in the AON domain. Note: This module is only supporting 32 bit ReadWrite access from MCU 0x40091000 0 0x1000 registers MCUCLK MCU Clock Management This register contains bitfields related to the MCU clock. 0 read-write 0x00000000 RCOSC_HF_CAL_DONE RCOSC_HF_CAL_DONE [2:2] PWR_DWN_SRC PWR_DWN_SRC [1:0] AUXCLK AUX Clock Management This register contains bitfields that are relevant for setting up the clock to the AUX domain. 4 read-write 0x00000001 PWR_DWN_SRC PWR_DWN_SRC [12:11] SCLK_HF_DIV SCLK_HF_DIV [10:8] SRC SRC [2:0] MCUCFG MCU Configuration This register contains power management related bitfields for the MCU domain. 8 read-write 0x0000000f VIRT_OFF VIRT_OFF [17:17] FIXED_WU_EN FIXED_WU_EN [16:16] SRAM_RET_EN SRAM_RET_EN [3:0] AUXCFG AUX Configuration This register contains power management related signals for the AUX domain. 12 read-write 0x00000001 RAM_RET_EN RAM_RET_EN [0:0] AUXCTL AUX Control This register contains events and control signals for the AUX domain. 16 read-write 0x00000000 RESET_REQ RESET_REQ [31:31] SCE_RUN_EN SCE_RUN_EN [2:2] SWEV SWEV [1:1] AUX_FORCE_ON AUX_FORCE_ON [0:0] PWRSTAT Power Status This register is used to monitor various power management related signals in AON. Most signals are for test, calibration and debug purpose only, and others can be used to detect that AUX or JTAG domains are powered up. 20 read-write 0xe00000000 AUX_PWR_DWN AUX_PWR_DWN [9:9] JTAG_PD_ON JTAG_PD_ON [6:6] AUX_PD_ON AUX_PD_ON [5:5] MCU_PD_ON MCU_PD_ON [4:4] AUX_BUS_CONNECTED AUX_BUS_CONNECTED [2:2] AUX_RESET_DONE AUX_RESET_DONE [1:1] SHUTDOWN Shutdown Control This register contains bitfields required for entering shutdown mode 24 read-write 0x00000000 EN EN [0:0] CTL0 Control 0 This register contains various chip level control and debug bitfields. 32 read-write 0x00000000 PWR_DWN_DIS PWR_DWN_DIS [8:8] AUX_SRAM_ERASE AUX_SRAM_ERASE [3:3] MCU_SRAM_ERASE MCU_SRAM_ERASE [2:2] CTL1 Control 1 This register contains various chip level control and debug bitfields. 36 read-write 0x00000000 MCU_RESET_SRC MCU_RESET_SRC [1:1] oneToClear MCU_WARM_RESET MCU_WARM_RESET [0:0] oneToClear RECHARGECFG Recharge Controller Configuration This register sets all relevant patameters for controlling the recharge algorithm. 48 read-write 0x00000000 ADAPTIVE_EN ADAPTIVE_EN [31:31] C2 C2 [23:20] C1 C1 [19:16] MAX_PER_M MAX_PER_M [15:11] MAX_PER_E MAX_PER_E [10:8] PER_M PER_M [7:3] PER_E PER_E [2:0] RECHARGESTAT Recharge Controller Status This register controls various status registers which are updated during recharge. The register is mostly intended for test and debug. 52 read-write 0x00000000 VDDR_SMPLS VDDR_SMPLS [19:16] MAX_USED_PER MAX_USED_PER [15:0] OSCCFG Oscillator Configuration This register sets the period for Amplitude compensation requests sent to the oscillator control system. The amplitude compensations is only applicable when XOSC_HF is running in low power mode. 56 read-write 0x00000000 PER_M PER_M [7:3] PER_E PER_E [2:0] JTAGCFG JTAG Configuration This register contains control for configuration of the JTAG domain,- hereunder access permissions for each TAP. 64 read-write 0x00000100 JTAG_PD_FORCE_ON JTAG_PD_FORCE_ON [8:8] JTAGUSERCODE JTAG USERCODE Boot code copies the JTAG USERCODE to this register from where it is forwarded to the debug subsystem. 68 read-write 0x0b99a02f USER_CODE USER_CODE [31:0] AUX_ADI4 Configuration registers controlling analog peripherals of AUX. Registers Fields should be considered static unless otherwise noted (as dynamic) 0x400cb000 8 0 0x10 registers MUX0 Internal. Only to be used through TI provided API. 0 read-write 0x00000000 COMPA_IN COMPA_IN [7:4] COMPA_REF COMPA_REF [3:0] MUX1 Internal. Only to be used through TI provided API. 1 read-write 0x00000000 COMPA_IN COMPA_IN [7:0] MUX2 Internal. Only to be used through TI provided API. 2 read-write 0x00000000 ADCCOMPB_IN ADCCOMPB_IN [7:3] COMPB_REF COMPB_REF [2:0] MUX3 Internal. Only to be used through TI provided API. 3 read-write 0x00000000 ADCCOMPB_IN ADCCOMPB_IN [7:0] ISRC Current Source Strength and trim control for current source 4 read-write 0x00000000 TRIM TRIM [7:2] EN EN [0:0] COMP Comparator Control COMPA and COMPB comparators 5 read-write 0x00000000 COMPA_REF_RES_EN COMPA_REF_RES_EN [7:7] COMPA_REF_CURR_EN COMPA_REF_CURR_EN [6:6] COMPB_TRIM COMPB_TRIM [5:3] COMPB_EN COMPB_EN [2:2] COMPA_EN COMPA_EN [0:0] MUX4 Internal. Only to be used through TI provided API. 7 read-write 0x00000000 COMPA_REF COMPA_REF [7:0] ADC0 ADC Control 0 8 read-write 0x00000000 SMPL_MODE SMPL_MODE [7:7] SMPL_CYCLE_EXP SMPL_CYCLE_EXP [6:3] RESET_N RESET_N [1:1] EN EN [0:0] ADC1 ADC Control 1 9 read-write 0x00000000 SCALE_DIS SCALE_DIS [0:0] ADCREF0 ADC Reference 0 Control reference used by the ADC 10 read-write 0x00000000 REF_ON_IDLE REF_ON_IDLE [6:6] IOMUX IOMUX [5:5] EXT EXT [4:4] SRC SRC [3:3] EN EN [0:0] ADCREF1 ADC Reference 1 Control reference used by the ADC 11 read-write 0x00000000 VTRIM VTRIM [5:0] AUX_AIODIO0 AUX Analog/Digital Input Output Controller 0x400c1000 0 4096 registers GPIODOUT General Purpose Input/Output Data Out This register is used to set data on the pads assigned to AUX 0 read-write 0x00000000 IO7_0 IO7_0 [7:0] IOMODE Input Output Mode Controls pull-up pull-down and output mode for the IO pins assigned to AUX 4 read-write 0x00000000 IO7 IO7 [15:14] IO6 IO6 [13:12] IO5 IO5 [11:10] IO4 IO4 [9:8] IO3 IO3 [7:6] IO2 IO2 [5:4] IO1 IO1 [3:2] IO0 IO0 [1:0] GPIODIN General Purpose Input Output Data In 8 read-only 0x00000000 IO7_0 IO7_0 [7:0] GPIODOUTSET General Purpose Input Output Data Out Set Strobes for setting output data register bits 12 read-write 0x00000000 IO7_0 IO7_0 [7:0] GPIODOUTCLR General Purpose Input Output Data Out Clear Strobes for clearing output data register bits 16 read-write 0x00000000 IO7_0 IO7_0 [7:0] GPIODOUTTGL General Purpose Input Output Data Out Toggle Strobes for toggling output data register bits 20 read-write 0x00000000 IO7_0 IO7_0 [7:0] GPIODIE General Purpose Input Output Input Enable 24 read-write 0x00000000 IO7_0 IO7_0 [7:0] AUX_AIODIO1 AUX Analog/Digital Input Output Controller 0x400c2000 0 4096 registers GPIODOUT General Purpose Input/Output Data Out This register is used to set data on the pads assigned to AUX 0 read-write 0x00000000 IO7_0 IO7_0 [7:0] IOMODE Input Output Mode Controls pull-up pull-down and output mode for the IO pins assigned to AUX 4 read-write 0x00000000 IO7 IO7 [15:14] IO6 IO6 [13:12] IO5 IO5 [11:10] IO4 IO4 [9:8] IO3 IO3 [7:6] IO2 IO2 [5:4] IO1 IO1 [3:2] IO0 IO0 [1:0] GPIODIN General Purpose Input Output Data In 8 read-only 0x00000000 IO7_0 IO7_0 [7:0] GPIODOUTSET General Purpose Input Output Data Out Set Strobes for setting output data register bits 12 read-write 0x00000000 IO7_0 IO7_0 [7:0] GPIODOUTCLR General Purpose Input Output Data Out Clear Strobes for clearing output data register bits 16 read-write 0x00000000 IO7_0 IO7_0 [7:0] GPIODOUTTGL General Purpose Input Output Data Out Toggle Strobes for toggling output data register bits 20 read-write 0x00000000 IO7_0 IO7_0 [7:0] GPIODIE General Purpose Input Output Input Enable 24 read-write 0x00000000 IO7_0 IO7_0 [7:0] AUX_ANAIF AUX Analog Peripheral Control Module 0x400c9000 0 4096 registers ADCCTL ADC Control 16 read-write 0x00000000 START_POL START_POL [13:13] START_SRC START_SRC [12:8] CMD CMD [1:0] ADCFIFOSTAT ADC FIFO Status FIFO can hold up to four ADC samples 20 read-only 0x00000001 OVERFLOW OVERFLOW [4:4] UNDERFLOW UNDERFLOW [3:3] FULL FULL [2:2] ALMOST_FULL ALMOST_FULL [1:1] EMPTY EMPTY [0:0] ADCFIFO ADC FIFO 24 read-write 0x00000000 DATA DATA [11:0] ADCTRIG ADC Trigger 28 read-write 0x00000000 START START [0:0] ISRCCTL Current Source Control 32 read-write 0x00000001 RESET_N RESET_N [0:0] AUX_DDI0_OSC This is the DDI for the digital block that controls all the analog clock oscillators (OSC_DIG) and performs qualification of the clocks generated. 0x400ca000 0 0x40 registers CTL0 Control 0 Controls various clock source selects 0 read-write 0x00000000 XTAL_IS_24M XTAL_IS_24M [31:31] BYPASS_XOSC_LF_CLK_QUAL BYPASS_XOSC_LF_CLK_QUAL [29:29] BYPASS_RCOSC_LF_CLK_QUAL BYPASS_RCOSC_LF_CLK_QUAL [28:28] DOUBLER_START_DURATION DOUBLER_START_DURATION [27:26] DOUBLER_RESET_DURATION DOUBLER_RESET_DURATION [25:25] FORCE_KICKSTART_EN FORCE_KICKSTART_EN [22:22] ALLOW_SCLK_HF_SWITCHING ALLOW_SCLK_HF_SWITCHING [16:16] RCOSC_LF_TRIMMED RCOSC_LF_TRIMMED [12:12] XOSC_HF_POWER_MODE XOSC_HF_POWER_MODE [11:11] XOSC_LF_DIG_BYPASS XOSC_LF_DIG_BYPASS [10:10] CLK_LOSS_EN CLK_LOSS_EN [9:9] ACLK_TDC_SRC_SEL ACLK_TDC_SRC_SEL [8:7] ACLK_REF_SRC_SEL ACLK_REF_SRC_SEL [6:5] SCLK_LF_SRC_SEL SCLK_LF_SRC_SEL [3:2] SCLK_MF_SRC_SEL SCLK_MF_SRC_SEL [1:1] SCLK_HF_SRC_SEL SCLK_HF_SRC_SEL [0:0] CTL1 Control 1 This register contains various OSC_DIG configuration 4 read-write 0x00000000 RCOSCHFCTRIMFRACT RCOSCHFCTRIMFRACT [22:18] RCOSCHFCTRIMFRACT_EN RCOSCHFCTRIMFRACT_EN [17:17] XOSC_HF_FAST_START XOSC_HF_FAST_START [1:0] RADCEXTCFG RADC External Configuration 8 read-write 0x00000000 HPM_IBIAS_WAIT_CNT HPM_IBIAS_WAIT_CNT [31:22] LPM_IBIAS_WAIT_CNT LPM_IBIAS_WAIT_CNT [21:16] IDAC_STEP IDAC_STEP [15:12] RADC_DAC_TH RADC_DAC_TH [11:6] RADC_MODE_IS_SAR RADC_MODE_IS_SAR [5:5] AMPCOMPCTL Amplitude Compensation Control 12 read-write 0x00000000 AMPCOMP_REQ_MODE AMPCOMP_REQ_MODE [30:30] AMPCOMP_FSM_UPDATE_RATE AMPCOMP_FSM_UPDATE_RATE [29:28] AMPCOMP_SW_CTRL AMPCOMP_SW_CTRL [27:27] AMPCOMP_SW_EN AMPCOMP_SW_EN [26:26] IBIAS_OFFSET IBIAS_OFFSET [23:20] IBIAS_INIT IBIAS_INIT [19:16] LPM_IBIAS_WAIT_CNT_FINAL LPM_IBIAS_WAIT_CNT_FINAL [15:8] CAP_STEP CAP_STEP [7:4] IBIASCAP_HPTOLP_OL_CNT IBIASCAP_HPTOLP_OL_CNT [3:0] AMPCOMPTH1 Amplitude Compensation Threashold 1 This register contains various threshhold values for amplitude compensation algorithm 16 read-write 0x00000000 HPMRAMP3_LTH HPMRAMP3_LTH [23:18] HPMRAMP3_HTH HPMRAMP3_HTH [15:10] IBIASCAP_LPTOHP_OL_CNT IBIASCAP_LPTOHP_OL_CNT [9:6] HPMRAMP1_TH HPMRAMP1_TH [5:0] AMPCOMPTH2 Amplitude Compensation Threashold 2 This register contains various threshhold values for amplitude compensation algorithm. 20 read-write 0x00000000 LPMUPDATE_LTH LPMUPDATE_LTH [31:26] LPMUPDATE_HTH LPMUPDATE_HTH [23:18] ADC_COMP_AMPTH_LPM ADC_COMP_AMPTH_LPM [15:10] ADC_COMP_AMPTH_HPM ADC_COMP_AMPTH_HPM [7:2] ANABYPASSVAL1 Analog Bypass Values 1 24 read-write 0x00000000 XOSC_HF_ROW_Q12 XOSC_HF_ROW_Q12 [19:16] XOSC_HF_COLUMN_Q12 XOSC_HF_COLUMN_Q12 [15:0] ANABYPASSVAL2 Internal. Only to be used through TI provided API. 28 read-write 0x00000000 XOSC_HF_IBIASTHERM XOSC_HF_IBIASTHERM [13:0] ATESTCTL Analog Test Control 32 read-write 0x00000000 SCLK_LF_AUX_EN SCLK_LF_AUX_EN [29:29] ADCDOUBLERNANOAMPCTL ADC Doubler Nanoamp Control 36 read-write 0x00000000 NANOAMP_BIAS_ENABLE NANOAMP_BIAS_ENABLE [24:24] SPARE23 SPARE23 [23:23] ADC_SH_MODE_EN ADC_SH_MODE_EN [5:5] ADC_SH_VBUF_EN ADC_SH_VBUF_EN [4:4] ADC_IREF_CTRL ADC_IREF_CTRL [1:0] XOSCHFCTL XOSCHF Control 40 read-write 0x00000000 PEAK_DET_ITRIM PEAK_DET_ITRIM [9:8] BYPASS BYPASS [6:6] HP_BUF_ITRIM HP_BUF_ITRIM [4:2] LP_BUF_ITRIM LP_BUF_ITRIM [1:0] LFOSCCTL Low Frequency Oscillator Control 44 read-write 0x00000000 XOSCLF_REGULATOR_TRIM XOSCLF_REGULATOR_TRIM [23:22] XOSCLF_CMIRRWR_RATIO XOSCLF_CMIRRWR_RATIO [21:18] RCOSCLF_RTUNE_TRIM RCOSCLF_RTUNE_TRIM [9:8] RCOSCLF_CTUNE_TRIM RCOSCLF_CTUNE_TRIM [7:0] RCOSCHFCTL RCOSCHF Control 48 read-write 0x00000000 RCOSCHF_CTRIM RCOSCHF_CTRIM [15:8] STAT0 Status 0 This register contains status signals from OSC_DIG 52 read-only 0x00000000 SCLK_LF_SRC SCLK_LF_SRC [30:29] SCLK_HF_SRC SCLK_HF_SRC [28:28] RCOSC_HF_EN RCOSC_HF_EN [22:22] RCOSC_LF_EN RCOSC_LF_EN [21:21] XOSC_LF_EN XOSC_LF_EN [20:20] CLK_DCDC_RDY CLK_DCDC_RDY [19:19] CLK_DCDC_RDY_ACK CLK_DCDC_RDY_ACK [18:18] SCLK_HF_LOSS SCLK_HF_LOSS [17:17] SCLK_LF_LOSS SCLK_LF_LOSS [16:16] XOSC_HF_EN XOSC_HF_EN [15:15] XB_48M_CLK_EN XB_48M_CLK_EN [13:13] XOSC_HF_LP_BUF_EN XOSC_HF_LP_BUF_EN [11:11] XOSC_HF_HP_BUF_EN XOSC_HF_HP_BUF_EN [10:10] ADC_THMET ADC_THMET [8:8] ADC_DATA_READY ADC_DATA_READY [7:7] ADC_DATA ADC_DATA [6:1] PENDINGSCLKHFSWITCHING PENDINGSCLKHFSWITCHING [0:0] STAT1 Status 1 This register contains status signals from OSC_DIG 56 read-only 0x00000000 RAMPSTATE RAMPSTATE [31:28] HMP_UPDATE_AMP HMP_UPDATE_AMP [27:22] LPM_UPDATE_AMP LPM_UPDATE_AMP [21:16] FORCE_RCOSC_HF FORCE_RCOSC_HF [15:15] SCLK_HF_EN SCLK_HF_EN [14:14] SCLK_MF_EN SCLK_MF_EN [13:13] ACLK_ADC_EN ACLK_ADC_EN [12:12] ACLK_TDC_EN ACLK_TDC_EN [11:11] ACLK_REF_EN ACLK_REF_EN [10:10] CLK_CHP_EN CLK_CHP_EN [9:9] CLK_DCDC_EN CLK_DCDC_EN [8:8] SCLK_HF_GOOD SCLK_HF_GOOD [7:7] SCLK_MF_GOOD SCLK_MF_GOOD [6:6] SCLK_LF_GOOD SCLK_LF_GOOD [5:5] ACLK_ADC_GOOD ACLK_ADC_GOOD [4:4] ACLK_TDC_GOOD ACLK_TDC_GOOD [3:3] ACLK_REF_GOOD ACLK_REF_GOOD [2:2] CLK_CHP_GOOD CLK_CHP_GOOD [1:1] CLK_DCDC_GOOD CLK_DCDC_GOOD [0:0] STAT2 Status 2 This register contains status signals from AMPCOMP FSM 60 read-only 0x00000000 ADC_DCBIAS ADC_DCBIAS [31:26] HPM_RAMP1_THMET HPM_RAMP1_THMET [25:25] HPM_RAMP2_THMET HPM_RAMP2_THMET [24:24] HPM_RAMP3_THMET HPM_RAMP3_THMET [23:23] RAMPSTATE RAMPSTATE [15:12] AMPCOMP_REQ AMPCOMP_REQ [3:3] XOSC_HF_AMPGOOD XOSC_HF_AMPGOOD [2:2] XOSC_HF_FREQGOOD XOSC_HF_FREQGOOD [1:1] XOSC_HF_RF_FREQGOOD XOSC_HF_RF_FREQGOOD [0:0] AUX_EVCTL AUX Event Controller 0x400c5000 0 4096 registers VECCFG0 Vector Configuration 0 AUX_SCE event vectors 0 and 1 configuration 0 read-write 0x00000000 VEC1_POL VEC1_POL [14:14] VEC1_EN VEC1_EN [13:13] VEC1_EV VEC1_EV [12:8] VEC0_POL VEC0_POL [6:6] VEC0_EN VEC0_EN [5:5] VEC0_EV VEC0_EV [4:0] VECCFG1 Vector Configuration 1 AUX_SCE event vectors 2 and 3 configuration 4 read-write 0x00000000 VEC3_POL VEC3_POL [14:14] VEC3_EN VEC3_EN [13:13] VEC3_EV VEC3_EV [12:8] VEC2_POL VEC2_POL [6:6] VEC2_EN VEC2_EN [5:5] VEC2_EV VEC2_EV [4:0] SCEWEVSEL Sensor Controller Engine Wait Event Selection Event selection for the AUX_SCE WEV0, WEV1, BEV0 and BEV1 instructions 8 read-write 0x00000000 WEV7_EV WEV7_EV [4:0] EVTOAONFLAGS Events To AON Domain Flags AUX event flags going to/through the AON domain These events may be used to wake up the MCU domain. The flags may be cleared by writing 0 to these bits or writing 1 to the corresponding bits in EVTOAONFLAGSCLR. 12 read-write 0x00000000 TIMER1_EV TIMER1_EV [8:8] zeroToClear TIMER0_EV TIMER0_EV [7:7] zeroToClear TDC_DONE TDC_DONE [6:6] zeroToClear ADC_DONE ADC_DONE [5:5] zeroToClear AUX_COMPB AUX_COMPB [4:4] zeroToClear AUX_COMPA AUX_COMPA [3:3] zeroToClear SWEV2 SWEV2 [2:2] zeroToClear SWEV1 SWEV1 [1:1] zeroToClear SWEV0 SWEV0 [0:0] zeroToClear EVTOAONPOL Events To AON Domain Polarity AUX event source polarity for the event flags going to/through the AON domain Note the inverse polarity (0 = high, 1 = low). 16 read-write 0x00000000 TIMER1_EV TIMER1_EV [8:8] TIMER0_EV TIMER0_EV [7:7] TDC_DONE TDC_DONE [6:6] ADC_DONE ADC_DONE [5:5] AUX_COMPB AUX_COMPB [4:4] AUX_COMPA AUX_COMPA [3:3] DMACTL Direct Memory Access Control 20 read-write 0x00000000 REQ_MODE REQ_MODE [2:2] EN EN [1:1] SEL SEL [0:0] SWEVSET Software Event Set Strobes for setting software events from the AUX domain to the AON/MCU Domains The use of these events is software-defined. 24 read-write 0x00000000 SWEV2 SWEV2 [2:2] SWEV1 SWEV1 [1:1] SWEV0 SWEV0 [0:0] EVSTAT0 Event Status 0 Current event source levels, 15:0 28 read-only 0x00000000 AUXIO2 AUXIO2 [15:15] AUXIO1 AUXIO1 [14:14] AUXIO0 AUXIO0 [13:13] AON_PROG_WU AON_PROG_WU [12:12] AON_SW AON_SW [11:11] OBSMUX1 OBSMUX1 [10:10] OBSMUX0 OBSMUX0 [9:9] ADC_FIFO_ALMOST_FULL ADC_FIFO_ALMOST_FULL [8:8] ADC_DONE ADC_DONE [7:7] SMPH_AUTOTAKE_DONE SMPH_AUTOTAKE_DONE [6:6] TIMER1_EV TIMER1_EV [5:5] TIMER0_EV TIMER0_EV [4:4] TDC_DONE TDC_DONE [3:3] AUX_COMPB AUX_COMPB [2:2] AUX_COMPA AUX_COMPA [1:1] AON_RTC_CH2 AON_RTC_CH2 [0:0] EVSTAT1 Event Status 1 Current event source levels, 31:16 32 read-only 0x00000000 ADC_IRQ ADC_IRQ [15:15] MCU_EV MCU_EV [14:14] ACLK_REF ACLK_REF [13:13] AUXIO15 AUXIO15 [12:12] AUXIO14 AUXIO14 [11:11] AUXIO13 AUXIO13 [10:10] AUXIO12 AUXIO12 [9:9] AUXIO11 AUXIO11 [8:8] AUXIO10 AUXIO10 [7:7] AUXIO9 AUXIO9 [6:6] AUXIO8 AUXIO8 [5:5] AUXIO7 AUXIO7 [4:4] AUXIO6 AUXIO6 [3:3] AUXIO5 AUXIO5 [2:2] AUXIO4 AUXIO4 [1:1] AUXIO3 AUXIO3 [0:0] EVTOMCUPOL Event To MCU Domain Polarity AUX event source polarity for the event flags to the MCU domain Note the inverse polarity (0 = high, 1 = low). 36 read-write 0x00000000 ADC_IRQ ADC_IRQ [10:10] OBSMUX0 OBSMUX0 [9:9] ADC_FIFO_ALMOST_FULL ADC_FIFO_ALMOST_FULL [8:8] ADC_DONE ADC_DONE [7:7] SMPH_AUTOTAKE_DONE SMPH_AUTOTAKE_DONE [6:6] TIMER1_EV TIMER1_EV [5:5] TIMER0_EV TIMER0_EV [4:4] TDC_DONE TDC_DONE [3:3] AUX_COMPB AUX_COMPB [2:2] AUX_COMPA AUX_COMPA [1:1] AON_WU_EV AON_WU_EV [0:0] EVTOMCUFLAGS Events to MCU Domain Flags AUX event flags going to the MCU domain The flags may be cleared by writing 0 to these bits or writing 1 to the corresponding bits in EVTOMCUFLAGSCLR. 40 read-write 0x00000000 ADC_IRQ ADC_IRQ [10:10] zeroToClear OBSMUX0 OBSMUX0 [9:9] zeroToClear ADC_FIFO_ALMOST_FULL ADC_FIFO_ALMOST_FULL [8:8] zeroToClear ADC_DONE ADC_DONE [7:7] zeroToClear SMPH_AUTOTAKE_DONE SMPH_AUTOTAKE_DONE [6:6] zeroToClear TIMER1_EV TIMER1_EV [5:5] zeroToClear TIMER0_EV TIMER0_EV [4:4] zeroToClear TDC_DONE TDC_DONE [3:3] zeroToClear AUX_COMPB AUX_COMPB [2:2] zeroToClear AUX_COMPA AUX_COMPA [1:1] zeroToClear AON_WU_EV AON_WU_EV [0:0] zeroToClear COMBEVTOMCUMASK Combined Event To MCU Domain Mask Selects which of the flags In EVTOMCUFLAGS that contribute to the AUX_COMB event to the MCU domain The AUX_COMB event is asserted as long as one or more of the included event flags are set. 44 read-write 0x00000000 ADC_IRQ ADC_IRQ [10:10] OBSMUX0 OBSMUX0 [9:9] ADC_FIFO_ALMOST_FULL ADC_FIFO_ALMOST_FULL [8:8] ADC_DONE ADC_DONE [7:7] SMPH_AUTOTAKE_DONE SMPH_AUTOTAKE_DONE [6:6] TIMER1_EV TIMER1_EV [5:5] TIMER0_EV TIMER0_EV [4:4] TDC_DONE TDC_DONE [3:3] AUX_COMPB AUX_COMPB [2:2] AUX_COMPA AUX_COMPA [1:1] AON_WU_EV AON_WU_EV [0:0] VECFLAGS Vector Flags If a vector flag has been set and AUX_SCE is sleeping, it will wake up and execute the vector. If multiple vectors have been set, the one with the lowest index will execute first, and the next after returning to sleep. During execution of a vector, the flag must be cleared, by writing a 1 to the corresponding bit in VECFLAGSCLR. 52 read-write 0x00000000 VEC3 VEC3 [3:3] zeroToClear VEC2 VEC2 [2:2] zeroToClear VEC1 VEC1 [1:1] zeroToClear VEC0 VEC0 [0:0] zeroToClear EVTOMCUFLAGSCLR Events To MCU Domain Flags Clear Strobes for clearing flags in EVTOMCUFLAGS. 56 read-write 0x00000000 ADC_IRQ ADC_IRQ [10:10] OBSMUX0 OBSMUX0 [9:9] ADC_FIFO_ALMOST_FULL ADC_FIFO_ALMOST_FULL [8:8] ADC_DONE ADC_DONE [7:7] SMPH_AUTOTAKE_DONE SMPH_AUTOTAKE_DONE [6:6] TIMER1_EV TIMER1_EV [5:5] TIMER0_EV TIMER0_EV [4:4] TDC_DONE TDC_DONE [3:3] AUX_COMPB AUX_COMPB [2:2] AUX_COMPA AUX_COMPA [1:1] AON_WU_EV AON_WU_EV [0:0] EVTOAONFLAGSCLR Events To AON Domain Clear Strobes for clearing flags in EVTOAONFLAGS. 60 read-write 0x00000000 TIMER1_EV TIMER1_EV [8:8] TIMER0_EV TIMER0_EV [7:7] TDC_DONE TDC_DONE [6:6] ADC_DONE ADC_DONE [5:5] AUX_COMPB AUX_COMPB [4:4] AUX_COMPA AUX_COMPA [3:3] SWEV2 SWEV2 [2:2] SWEV1 SWEV1 [1:1] SWEV0 SWEV0 [0:0] VECFLAGSCLR Vector Flags Clear Strobes for clearing flags in VECFLAGS. 64 read-write 0x00000000 VEC3 VEC3 [3:3] VEC2 VEC2 [2:2] VEC1 VEC1 [1:1] VEC0 VEC0 [0:0] AUX_SCE AUX Sensor Control Engine Control Module 0x400e1000 0 4096 registers CTL Internal. Only to be used through TI provided API. 0 read-write 0x00000000 FORCE_EV_LOW FORCE_EV_LOW [31:24] FORCE_EV_HIGH FORCE_EV_HIGH [23:16] RESET_VECTOR RESET_VECTOR [11:8] DBG_FREEZE_EN DBG_FREEZE_EN [6:6] FORCE_WU_LOW FORCE_WU_LOW [5:5] FORCE_WU_HIGH FORCE_WU_HIGH [4:4] RESTART RESTART [3:3] SINGLE_STEP SINGLE_STEP [2:2] SUSPEND SUSPEND [1:1] CLK_EN CLK_EN [0:0] FETCHSTAT Internal. Only to be used through TI provided API. 4 read-only 0x00000000 OPCODE OPCODE [31:16] PC PC [15:0] CPUSTAT Internal. Only to be used through TI provided API. 8 read-only 0x00000000 BUS_ERROR BUS_ERROR [11:11] SLEEP SLEEP [10:10] WEV WEV [9:9] SELF_STOP SELF_STOP [8:8] V_FLAG V_FLAG [3:3] C_FLAG C_FLAG [2:2] N_FLAG N_FLAG [1:1] Z_FLAG Z_FLAG [0:0] WUSTAT Internal. Only to be used through TI provided API. 12 read-only 0x00000000 EXC_VECTOR EXC_VECTOR [17:16] WU_SIGNAL WU_SIGNAL [8:8] EV_SIGNALS EV_SIGNALS [7:0] REG1_0 Internal. Only to be used through TI provided API. 16 read-only 0x00000000 REG1 REG1 [31:16] REG0 REG0 [15:0] REG3_2 Internal. Only to be used through TI provided API. 20 read-only 0x00000000 REG3 REG3 [31:16] REG2 REG2 [15:0] REG5_4 Internal. Only to be used through TI provided API. 24 read-only 0x00000000 REG5 REG5 [31:16] REG4 REG4 [15:0] REG7_6 Internal. Only to be used through TI provided API. 28 read-only 0x00000000 REG7 REG7 [31:16] REG6 REG6 [15:0] LOOPADDR Internal. Only to be used through TI provided API. 32 read-only 0x00000000 STOP STOP [31:16] START START [15:0] LOOPCNT Internal. Only to be used through TI provided API. 36 read-only 0x00000000 ITER_LEFT ITER_LEFT [7:0] AUX_SMPH AUX Semaphore Controller 0x400c8000 0 4096 registers SMPH0 Semaphore 0 0 read-write 0x00000001 STAT STAT [0:0] SMPH1 Semaphore 1 4 read-write 0x00000001 STAT STAT [0:0] SMPH2 Semaphore 2 8 read-write 0x00000001 STAT STAT [0:0] SMPH3 Semaphore 3 12 read-write 0x00000001 STAT STAT [0:0] SMPH4 Semaphore 4 16 read-write 0x00000001 STAT STAT [0:0] SMPH5 Semaphore 5 20 read-write 0x00000001 STAT STAT [0:0] SMPH6 Semaphore 6 24 read-write 0x00000001 STAT STAT [0:0] SMPH7 Semaphore 7 28 read-write 0x00000001 STAT STAT [0:0] AUTOTAKE Sticky Request For Single Semaphore 32 read-write 0x00000000 SMPH_ID SMPH_ID [2:0] AUX_TDCIF AUX Time To Digital Converter 0x400c4000 0 4096 registers CTL Control 0 read-write 0x00000000 CMD CMD [1:0] STAT Status 4 read-only 0x00000006 SAT SAT [7:7] DONE DONE [6:6] STATE STATE [5:0] RESULT Result Result of last TDC conversion 8 read-only 0x00000002 VALUE VALUE [24:0] SATCFG Saturation Configuration 12 read-write 0x0000000f LIMIT LIMIT [3:0] TRIGSRC Trigger Source TDC start/stop trigger source selection 16 read-write 0x00000000 STOP_POL STOP_POL [13:13] STOP_SRC STOP_SRC [12:8] START_POL START_POL [5:5] START_SRC START_SRC [4:0] TRIGCNT Trigger Counter Stop counter status/control of TDC 20 read-write 0x00000000 CNT CNT [15:0] TRIGCNTLOAD Trigger Counter Load Stop counter control of TDC 24 read-write 0x00000000 CNT CNT [15:0] TRIGCNTCFG Trigger Counter Configuration 28 read-write 0x00000000 EN EN [0:0] PRECTL Prescaler Control The prescaler can be used to count events that are faster than the AUX clock speed. It can be used standalone or as a start/stop source for the TDC by configuring TRIGSRC.START_SRC and TRIGSRC.STOP_SRC to TDC_PRE. When counting fast signals with the TDC that are faster than 1/10th of the clock frequency of AUX it is recommended to use the prescaler. 32 read-write 0x0000001f RESET_N RESET_N [7:7] RATIO RATIO [6:6] SRC SRC [4:0] PRECNT Prescaler Counter Value of prescaler counter 36 read-write 0x00000000 CNT CNT [15:0] AUX_TIMER AUX Timer 0x400c7000 0 4096 registers T0CFG Timer 0 Configuration 0 read-write 0x00000000 TICK_SRC_POL TICK_SRC_POL [13:13] TICK_SRC TICK_SRC [12:8] PRE PRE [7:4] MODE MODE [1:1] RELOAD RELOAD [0:0] T1CFG Timer 1 Configuration 4 read-write 0x00000000 TICK_SRC_POL TICK_SRC_POL [13:13] TICK_SRC TICK_SRC [12:8] PRE PRE [7:4] MODE MODE [1:1] RELOAD RELOAD [0:0] T0CTL Timer 0 Control Run control/status for timer 0 8 read-write 0x00000000 EN EN [0:0] T0TARGET Timer 0 Target Target counter value for timer 0 12 read-write 0x00000000 VALUE VALUE [15:0] T1TARGET Timer 1 Target Target Counter Value Timer 1 16 read-write 0x00000000 VALUE VALUE [7:0] T1CTL Timer 1 Control Run Control/Status For Timer 1 20 read-write 0x00000000 EN EN [0:0] AUX_WUC AUX Wake-up controller 0x400c6000 0 4096 registers MODCLKEN0 Module Clock Enable Clock enable for each module in the AUX domain For use by the system CPU The settings in this register are OR'ed with the corresponding settings in MODCLKEN1. This allows the system CPU and AUX_SCE to request clocks independently. Settings take effect immediately. 0 read-write 0x00000000 AUX_ADI4 AUX_ADI4 [7:7] AUX_DDI0_OSC AUX_DDI0_OSC [6:6] TDC TDC [5:5] ANAIF ANAIF [4:4] TIMER TIMER [3:3] AIODIO1 AIODIO1 [2:2] AIODIO0 AIODIO0 [1:1] SMPH SMPH [0:0] PWROFFREQ Power Off Request Requests power off request for the AUX domain. When powered of the power supply and clock is disabled. This may only be used when taking the entire device into shutdown mode (i.e. with full device reset when resuming operation). Power off is prevented if AON_WUC:AUXCTL.AUX_FORCE_ON has been set, or if MCUBUSCTL.DISCONNECT_REQ has been cleared. 4 read-write 0x00000000 REQ REQ [0:0] PWRDWNREQ Power Down Request Request from AUX for system to enter power down. When system is in power down there is limited current supply available and the clock source is set by AON_WUC:AUXCLK.PWR_DWN_SRC 8 read-write 0x00000000 REQ REQ [0:0] PWRDWNACK Power Down Acknowledgment 12 read-only 0x00000000 ACK ACK [0:0] CLKLFREQ Low Frequency Clock Request 16 read-write 0x00000000 REQ REQ [0:0] CLKLFACK Low Frequency Clock Acknowledgment 20 read-only 0x00000000 ACK ACK [0:0] WUEVFLAGS Wake-up Event Flags Status of wake-up events from the AON domain The event flags are cleared by setting the corresponding bits in WUEVCLR 40 read-only 0x00000000 AON_RTC_CH2 AON_RTC_CH2 [2:2] AON_SW AON_SW [1:1] AON_PROG_WU AON_PROG_WU [0:0] WUEVCLR Wake-up Event Clear Clears wake-up events from the AON domain 44 read-write 0x00000000 AON_RTC_CH2 AON_RTC_CH2 [2:2] AON_SW AON_SW [1:1] AON_PROG_WU AON_PROG_WU [0:0] ADCCLKCTL ADC Clock Control Controls the ADC internal clock Note that the ADC command and data interface requires MODCLKEN0.ANAIF or MODCLKEN1.ANAIF also to be set 48 read-write 0x00000000 ACK ACK [1:1] REQ REQ [0:0] TDCCLKCTL TDC Clock Control Controls the TDC counter clock source, which steps the TDC counter value The source of this clock is controlled by OSC_DIG:CTL0.ACLK_TDC_SRC_SEL. 52 read-write 0x00000000 ACK ACK [1:1] REQ REQ [0:0] REFCLKCTL Reference Clock Control Controls the TDC reference clock source, which is to be compared against the TDC counter clock. The source of this clock is controlled by OSC_DIG:CTL0.ACLK_REF_SRC_SEL. 56 read-write 0x00000000 ACK ACK [1:1] REQ REQ [0:0] RTCSUBSECINC0 Real Time Counter Sub Second Increment 0 New value for the real-time counter (AON_RTC) sub-second increment value, part corresponding to AON_RTC:SUBSECINC bits 15:0. After setting INC15_0 and RTCSUBSECINC1.INC23_16, the value is loaded into AON_RTC:SUBSECINC.VALUEINC by setting RTCSUBSECINCCTL.UPD_REQ. 60 read-write 0x00000000 INC15_0 INC15_0 [15:0] RTCSUBSECINC1 Real Time Counter Sub Second Increment 1 New value for the real-time counter (AON_RTC) sub-second increment value, part corresponding to AON_RTC:SUBSECINC bits 23:16. After setting RTCSUBSECINC0.INC15_0 and INC23_16, the value is loaded into AON_RTC:SUBSECINC.VALUEINC by setting RTCSUBSECINCCTL.UPD_REQ. 64 read-write 0x00000000 INC23_16 INC23_16 [7:0] RTCSUBSECINCCTL Real Time Counter Sub Second Increment Control 68 read-write 0x00000000 UPD_ACK UPD_ACK [1:1] UPD_REQ UPD_REQ [0:0] MCUBUSCTL MCU Bus Control Controls the connection between the AUX domain bus and the MCU domain bus. The buses must be disconnected to allow power-down or power-off of the AUX domain. 72 read-write 0x00000000 DISCONNECT_REQ DISCONNECT_REQ [0:0] MCUBUSSTAT MCU Bus Status Indicates the connection state of the AUX domain and MCU domain buses. Note that this register cannot be read from the MCU domain while disconnected, and is therefore only useful for the AUX_SCE. 76 read-only 0x00000000 DISCONNECTED DISCONNECTED [1:1] DISCONNECT_ACK DISCONNECT_ACK [0:0] AONCTLSTAT AON Domain Control Status Status of AUX domain control from AON_WUC. 80 read-only 0x00000000 AUX_FORCE_ON AUX_FORCE_ON [1:1] SCE_RUN_EN SCE_RUN_EN [0:0] AUXIOLATCH AUX Input Output Latch Controls latching of signals between AUX_AIODIO0/AUX_AIODIO1 and AON_IOC. 84 read-write 0x00000000 EN EN [0:0] MODCLKEN1 Module Clock Enable 1 Clock enable for each module in the AUX domain, for use by the AUX_SCE. Settings take effect immediately. The settings in this register are OR'ed with the corresponding settings in MODCLKEN0. This allows system CPU and AUX_SCE to request clocks independently. 92 read-write 0x00000000 AUX_ADI4 AUX_ADI4 [7:7] AUX_DDI0_OSC AUX_DDI0_OSC [6:6] ANAIF ANAIF [4:4] TIMER TIMER [3:3] AIODIO1 AIODIO1 [2:2] AIODIO0 AIODIO0 [1:1] SMPH SMPH [0:0] CCFG Customer configuration area (CCFG) 0x50003000 0 0x1000 registers EXT_LF_CLK Extern LF clock configuration 4008 read-only 0xffffffff DIO DIO [31:24] RTC_INCREMENT RTC_INCREMENT [23:0] MODE_CONF_1 Mode Configuration 1 4012 read-only 0xfffbffff ALT_DCDC_VMIN ALT_DCDC_VMIN [23:20] ALT_DCDC_DITHER_EN ALT_DCDC_DITHER_EN [19:19] ALT_DCDC_IPEAK ALT_DCDC_IPEAK [18:16] DELTA_IBIAS_INIT DELTA_IBIAS_INIT [15:12] DELTA_IBIAS_OFFSET DELTA_IBIAS_OFFSET [11:8] XOSC_MAX_START XOSC_MAX_START [7:0] SIZE_AND_DIS_FLAGS CCFG Size and Disable Flags 4016 read-only 0x10000ffff SIZE_OF_CCFG SIZE_OF_CCFG [31:16] DISABLE_FLAGS DISABLE_FLAGS [15:3] DIS_GPRAM DIS_GPRAM [2:2] DIS_ALT_DCDC_SETTING DIS_ALT_DCDC_SETTING [1:1] DIS_XOSC_OVR DIS_XOSC_OVR [0:0] MODE_CONF Mode Configuration 0 4020 read-only 0xffffffff VDDR_TRIM_SLEEP_DELTA VDDR_TRIM_SLEEP_DELTA [31:28] DCDC_RECHARGE DCDC_RECHARGE [27:27] DCDC_ACTIVE DCDC_ACTIVE [26:26] VDDR_EXT_LOAD VDDR_EXT_LOAD [25:25] VDDS_BOD_LEVEL VDDS_BOD_LEVEL [24:24] SCLK_LF_OPTION SCLK_LF_OPTION [23:22] VDDR_TRIM_SLEEP_TC VDDR_TRIM_SLEEP_TC [21:21] RTC_COMP RTC_COMP [20:20] XOSC_FREQ XOSC_FREQ [19:18] XOSC_CAP_MOD XOSC_CAP_MOD [17:17] HF_COMP HF_COMP [16:16] XOSC_CAPARRAY_DELTA XOSC_CAPARRAY_DELTA [15:8] VDDR_CAP VDDR_CAP [7:0] VOLT_LOAD_0 Voltage Load 0 Enabled by MODE_CONF.VDDR_EXT_LOAD. 4024 read-only 0xffffffff VDDR_EXT_TP45 VDDR_EXT_TP45 [31:24] VDDR_EXT_TP25 VDDR_EXT_TP25 [23:16] VDDR_EXT_TP5 VDDR_EXT_TP5 [15:8] VDDR_EXT_TM15 VDDR_EXT_TM15 [7:0] VOLT_LOAD_1 Voltage Load 1 Enabled by MODE_CONF.VDDR_EXT_LOAD. 4028 read-only 0xffffffff VDDR_EXT_TP125 VDDR_EXT_TP125 [31:24] VDDR_EXT_TP105 VDDR_EXT_TP105 [23:16] VDDR_EXT_TP85 VDDR_EXT_TP85 [15:8] VDDR_EXT_TP65 VDDR_EXT_TP65 [7:0] RTC_OFFSET Real Time Clock Offset Enabled by MODE_CONF.RTC_COMP. 4032 read-only 0xffffffff RTC_COMP_P0 RTC_COMP_P0 [31:16] RTC_COMP_P1 RTC_COMP_P1 [15:8] RTC_COMP_P2 RTC_COMP_P2 [7:0] FREQ_OFFSET Frequency Offset 4036 read-only 0xffffffff HF_COMP_P0 HF_COMP_P0 [31:16] HF_COMP_P1 HF_COMP_P1 [15:8] HF_COMP_P2 HF_COMP_P2 [7:0] IEEE_MAC_0 IEEE MAC Address 0 4040 read-only 0xffffffff ADDR ADDR [31:0] IEEE_MAC_1 IEEE MAC Address 1 4044 read-only 0xffffffff ADDR ADDR [31:0] IEEE_BLE_0 IEEE BLE Address 0 4048 read-only 0xffffffff ADDR ADDR [31:0] IEEE_BLE_1 IEEE BLE Address 1 4052 read-only 0xffffffff ADDR ADDR [31:0] BL_CONFIG Bootloader Configuration Configures the functionality of the ROM boot loader. If both the boot loader is enabled by the BOOTLOADER_ENABLE field and the boot loader backdoor is enabled by the BL_ENABLE field it is possible to force entry of the ROM boot loader even if a valid image is present in flash. 4056 read-only 0xc5ffffff BOOTLOADER_ENABLE BOOTLOADER_ENABLE [31:24] BL_LEVEL BL_LEVEL [16:16] BL_PIN_NUMBER BL_PIN_NUMBER [15:8] BL_ENABLE BL_ENABLE [7:0] ERASE_CONF Erase Configuration 4060 read-only 0xffffffff CHIP_ERASE_DIS_N CHIP_ERASE_DIS_N [8:8] BANK_ERASE_DIS_N BANK_ERASE_DIS_N [0:0] CCFG_TI_OPTIONS TI Options 4064 read-only 0xffffffc5 TI_FA_ENABLE TI_FA_ENABLE [7:0] CCFG_TAP_DAP_0 Test Access Points Enable 0 4068 read-only 0xffc5c5c5 CPU_DAP_ENABLE CPU_DAP_ENABLE [23:16] PRCM_TAP_ENABLE PRCM_TAP_ENABLE [15:8] TEST_TAP_ENABLE TEST_TAP_ENABLE [7:0] CCFG_TAP_DAP_1 Test Access Points Enable 1 4072 read-only 0xffc5c5c5 PBIST2_TAP_ENABLE PBIST2_TAP_ENABLE [23:16] PBIST1_TAP_ENABLE PBIST1_TAP_ENABLE [15:8] WUC_TAP_ENABLE WUC_TAP_ENABLE [7:0] IMAGE_VALID_CONF Image Valid 4076 read-only 0xffffffff IMAGE_VALID IMAGE_VALID [31:0] CCFG_PROT_31_0 Protect Sectors 0-31 Each bit write protects one 4KB flash sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. 4080 read-only 0xffffffff WRT_PROT_SEC_31 WRT_PROT_SEC_31 [31:31] WRT_PROT_SEC_30 WRT_PROT_SEC_30 [30:30] WRT_PROT_SEC_29 WRT_PROT_SEC_29 [29:29] WRT_PROT_SEC_28 WRT_PROT_SEC_28 [28:28] WRT_PROT_SEC_27 WRT_PROT_SEC_27 [27:27] WRT_PROT_SEC_26 WRT_PROT_SEC_26 [26:26] WRT_PROT_SEC_25 WRT_PROT_SEC_25 [25:25] WRT_PROT_SEC_24 WRT_PROT_SEC_24 [24:24] WRT_PROT_SEC_23 WRT_PROT_SEC_23 [23:23] WRT_PROT_SEC_22 WRT_PROT_SEC_22 [22:22] WRT_PROT_SEC_21 WRT_PROT_SEC_21 [21:21] WRT_PROT_SEC_20 WRT_PROT_SEC_20 [20:20] WRT_PROT_SEC_19 WRT_PROT_SEC_19 [19:19] WRT_PROT_SEC_18 WRT_PROT_SEC_18 [18:18] WRT_PROT_SEC_17 WRT_PROT_SEC_17 [17:17] WRT_PROT_SEC_16 WRT_PROT_SEC_16 [16:16] WRT_PROT_SEC_15 WRT_PROT_SEC_15 [15:15] WRT_PROT_SEC_14 WRT_PROT_SEC_14 [14:14] WRT_PROT_SEC_13 WRT_PROT_SEC_13 [13:13] WRT_PROT_SEC_12 WRT_PROT_SEC_12 [12:12] WRT_PROT_SEC_11 WRT_PROT_SEC_11 [11:11] WRT_PROT_SEC_10 WRT_PROT_SEC_10 [10:10] WRT_PROT_SEC_9 WRT_PROT_SEC_9 [9:9] WRT_PROT_SEC_8 WRT_PROT_SEC_8 [8:8] WRT_PROT_SEC_7 WRT_PROT_SEC_7 [7:7] WRT_PROT_SEC_6 WRT_PROT_SEC_6 [6:6] WRT_PROT_SEC_5 WRT_PROT_SEC_5 [5:5] WRT_PROT_SEC_4 WRT_PROT_SEC_4 [4:4] WRT_PROT_SEC_3 WRT_PROT_SEC_3 [3:3] WRT_PROT_SEC_2 WRT_PROT_SEC_2 [2:2] WRT_PROT_SEC_1 WRT_PROT_SEC_1 [1:1] WRT_PROT_SEC_0 WRT_PROT_SEC_0 [0:0] CCFG_PROT_63_32 Protect Sectors 32-63 Each bit write protects one 4KB flash sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. Not in use by CC26xx and CC13xx. 4084 read-only 0xffffffff WRT_PROT_SEC_63 WRT_PROT_SEC_63 [31:31] WRT_PROT_SEC_62 WRT_PROT_SEC_62 [30:30] WRT_PROT_SEC_61 WRT_PROT_SEC_61 [29:29] WRT_PROT_SEC_60 WRT_PROT_SEC_60 [28:28] WRT_PROT_SEC_59 WRT_PROT_SEC_59 [27:27] WRT_PROT_SEC_58 WRT_PROT_SEC_58 [26:26] WRT_PROT_SEC_57 WRT_PROT_SEC_57 [25:25] WRT_PROT_SEC_56 WRT_PROT_SEC_56 [24:24] WRT_PROT_SEC_55 WRT_PROT_SEC_55 [23:23] WRT_PROT_SEC_54 WRT_PROT_SEC_54 [22:22] WRT_PROT_SEC_53 WRT_PROT_SEC_53 [21:21] WRT_PROT_SEC_52 WRT_PROT_SEC_52 [20:20] WRT_PROT_SEC_51 WRT_PROT_SEC_51 [19:19] WRT_PROT_SEC_50 WRT_PROT_SEC_50 [18:18] WRT_PROT_SEC_49 WRT_PROT_SEC_49 [17:17] WRT_PROT_SEC_48 WRT_PROT_SEC_48 [16:16] WRT_PROT_SEC_47 WRT_PROT_SEC_47 [15:15] WRT_PROT_SEC_46 WRT_PROT_SEC_46 [14:14] WRT_PROT_SEC_45 WRT_PROT_SEC_45 [13:13] WRT_PROT_SEC_44 WRT_PROT_SEC_44 [12:12] WRT_PROT_SEC_43 WRT_PROT_SEC_43 [11:11] WRT_PROT_SEC_42 WRT_PROT_SEC_42 [10:10] WRT_PROT_SEC_41 WRT_PROT_SEC_41 [9:9] WRT_PROT_SEC_40 WRT_PROT_SEC_40 [8:8] WRT_PROT_SEC_39 WRT_PROT_SEC_39 [7:7] WRT_PROT_SEC_38 WRT_PROT_SEC_38 [6:6] WRT_PROT_SEC_37 WRT_PROT_SEC_37 [5:5] WRT_PROT_SEC_36 WRT_PROT_SEC_36 [4:4] WRT_PROT_SEC_35 WRT_PROT_SEC_35 [3:3] WRT_PROT_SEC_34 WRT_PROT_SEC_34 [2:2] WRT_PROT_SEC_33 WRT_PROT_SEC_33 [1:1] WRT_PROT_SEC_32 WRT_PROT_SEC_32 [0:0] CCFG_PROT_95_64 Protect Sectors 64-95 Each bit write protects one flash sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. Not in use by CC26xx and CC13xx. 4088 read-only 0xffffffff WRT_PROT_SEC_95 WRT_PROT_SEC_95 [31:31] WRT_PROT_SEC_94 WRT_PROT_SEC_94 [30:30] WRT_PROT_SEC_93 WRT_PROT_SEC_93 [29:29] WRT_PROT_SEC_92 WRT_PROT_SEC_92 [28:28] WRT_PROT_SEC_91 WRT_PROT_SEC_91 [27:27] WRT_PROT_SEC_90 WRT_PROT_SEC_90 [26:26] WRT_PROT_SEC_89 WRT_PROT_SEC_89 [25:25] WRT_PROT_SEC_88 WRT_PROT_SEC_88 [24:24] WRT_PROT_SEC_87 WRT_PROT_SEC_87 [23:23] WRT_PROT_SEC_86 WRT_PROT_SEC_86 [22:22] WRT_PROT_SEC_85 WRT_PROT_SEC_85 [21:21] WRT_PROT_SEC_84 WRT_PROT_SEC_84 [20:20] WRT_PROT_SEC_83 WRT_PROT_SEC_83 [19:19] WRT_PROT_SEC_82 WRT_PROT_SEC_82 [18:18] WRT_PROT_SEC_81 WRT_PROT_SEC_81 [17:17] WRT_PROT_SEC_80 WRT_PROT_SEC_80 [16:16] WRT_PROT_SEC_79 WRT_PROT_SEC_79 [15:15] WRT_PROT_SEC_78 WRT_PROT_SEC_78 [14:14] WRT_PROT_SEC_77 WRT_PROT_SEC_77 [13:13] WRT_PROT_SEC_76 WRT_PROT_SEC_76 [12:12] WRT_PROT_SEC_75 WRT_PROT_SEC_75 [11:11] WRT_PROT_SEC_74 WRT_PROT_SEC_74 [10:10] WRT_PROT_SEC_73 WRT_PROT_SEC_73 [9:9] WRT_PROT_SEC_72 WRT_PROT_SEC_72 [8:8] WRT_PROT_SEC_71 WRT_PROT_SEC_71 [7:7] WRT_PROT_SEC_70 WRT_PROT_SEC_70 [6:6] WRT_PROT_SEC_69 WRT_PROT_SEC_69 [5:5] WRT_PROT_SEC_68 WRT_PROT_SEC_68 [4:4] WRT_PROT_SEC_67 WRT_PROT_SEC_67 [3:3] WRT_PROT_SEC_66 WRT_PROT_SEC_66 [2:2] WRT_PROT_SEC_65 WRT_PROT_SEC_65 [1:1] WRT_PROT_SEC_64 WRT_PROT_SEC_64 [0:0] CCFG_PROT_127_96 Protect Sectors 96-127 Each bit write protects one flash sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. Not in use by CC26xx and CC13xx. 4092 read-only 0xffffffff WRT_PROT_SEC_127 WRT_PROT_SEC_127 [31:31] WRT_PROT_SEC_126 WRT_PROT_SEC_126 [30:30] WRT_PROT_SEC_125 WRT_PROT_SEC_125 [29:29] WRT_PROT_SEC_124 WRT_PROT_SEC_124 [28:28] WRT_PROT_SEC_123 WRT_PROT_SEC_123 [27:27] WRT_PROT_SEC_122 WRT_PROT_SEC_122 [26:26] WRT_PROT_SEC_121 WRT_PROT_SEC_121 [25:25] WRT_PROT_SEC_120 WRT_PROT_SEC_120 [24:24] WRT_PROT_SEC_119 WRT_PROT_SEC_119 [23:23] WRT_PROT_SEC_118 WRT_PROT_SEC_118 [22:22] WRT_PROT_SEC_117 WRT_PROT_SEC_117 [21:21] WRT_PROT_SEC_116 WRT_PROT_SEC_116 [20:20] WRT_PROT_SEC_115 WRT_PROT_SEC_115 [19:19] WRT_PROT_SEC_114 WRT_PROT_SEC_114 [18:18] WRT_PROT_SEC_113 WRT_PROT_SEC_113 [17:17] WRT_PROT_SEC_112 WRT_PROT_SEC_112 [16:16] WRT_PROT_SEC_111 WRT_PROT_SEC_111 [15:15] WRT_PROT_SEC_110 WRT_PROT_SEC_110 [14:14] WRT_PROT_SEC_109 WRT_PROT_SEC_109 [13:13] WRT_PROT_SEC_108 WRT_PROT_SEC_108 [12:12] WRT_PROT_SEC_107 WRT_PROT_SEC_107 [11:11] WRT_PROT_SEC_106 WRT_PROT_SEC_106 [10:10] WRT_PROT_SEC_105 WRT_PROT_SEC_105 [9:9] WRT_PROT_SEC_104 WRT_PROT_SEC_104 [8:8] WRT_PROT_SEC_103 WRT_PROT_SEC_103 [7:7] WRT_PROT_SEC_102 WRT_PROT_SEC_102 [6:6] WRT_PROT_SEC_101 WRT_PROT_SEC_101 [5:5] WRT_PROT_SEC_100 WRT_PROT_SEC_100 [4:4] WRT_PROT_SEC_99 WRT_PROT_SEC_99 [3:3] WRT_PROT_SEC_98 WRT_PROT_SEC_98 [2:2] WRT_PROT_SEC_97 WRT_PROT_SEC_97 [1:1] WRT_PROT_SEC_96 WRT_PROT_SEC_96 [0:0] CPU_TIPROP Cortex-M's TI proprietary registers 0xe00fe000 0 0x1000 registers TRACECLKMUX Internal. Only to be used through TI provided API. 4088 read-write 0x00000000 TRACECLK_N_SWV TRACECLK_N_SWV [0:0] DYN_CG Internal. Only to be used through TI provided API. 4092 read-write 0x00000000 DYN_CG DYN_CG [1:0] CRYPTO Crypto core with DMA capability and local key storage 0x40024000 0 0x800 registers DMACH0CTL DMA Channel 0 Control 0 read-write 0x00000000 PRIO PRIO [1:1] EN EN [0:0] DMACH0EXTADDR DMA Channel 0 External Address 4 read-write 0x00000000 ADDR ADDR [31:0] DMACH0LEN DMA Channel 0 Length 12 read-write 0x00000000 LEN LEN [15:0] DMASTAT DMA Controller Status 24 read-only 0x00000000 PORT_ERR PORT_ERR [17:17] CH1_ACTIVE CH1_ACTIVE [1:1] CH0_ACTIVE CH0_ACTIVE [0:0] DMASWRESET DMA Controller Software Reset 28 write-only 0x00000000 RESET RESET [0:0] zeroToClear DMACH1CTL DMA Channel 1 Control 32 read-write 0x00000000 PRIO PRIO [1:1] EN EN [0:0] DMACH1EXTADDR DMA Channel 1 External Address 36 read-write 0x00000000 ADDR ADDR [31:0] DMACH1LEN DMA Channel 1 Length 44 read-write 0x00000000 LEN LEN [15:0] DMABUSCFG DMA Controller Master Configuration 120 read-write 0x00002400 AHB_MST1_BURST_SIZE AHB_MST1_BURST_SIZE [15:12] AHB_MST1_IDLE_EN AHB_MST1_IDLE_EN [11:11] AHB_MST1_INCR_EN AHB_MST1_INCR_EN [10:10] AHB_MST1_LOCK_EN AHB_MST1_LOCK_EN [9:9] AHB_MST1_BIGEND AHB_MST1_BIGEND [8:8] DMAPORTERR DMA Controller Port Error 124 read-only 0x00000000 AHB_ERR AHB_ERR [12:12] LAST_CH LAST_CH [9:9] DMAHWVER DMA Controller Version 252 read-only 0x01012ed1 HW_MAJOR_VER HW_MAJOR_VER [27:24] HW_MINOR_VER HW_MINOR_VER [23:20] HW_PATCH_LVL HW_PATCH_LVL [19:16] VER_NUM_COMPL VER_NUM_COMPL [15:8] VER_NUM VER_NUM [7:0] KEYWRITEAREA Key Write Area 1024 read-write 0x00000000 RAM_AREA7 RAM_AREA7 [7:7] RAM_AREA6 RAM_AREA6 [6:6] RAM_AREA5 RAM_AREA5 [5:5] RAM_AREA4 RAM_AREA4 [4:4] RAM_AREA3 RAM_AREA3 [3:3] RAM_AREA2 RAM_AREA2 [2:2] RAM_AREA1 RAM_AREA1 [1:1] RAM_AREA0 RAM_AREA0 [0:0] KEYWRITTENAREA Key Written Area Status This register shows which areas of the key store RAM contain valid written keys. When a new key needs to be written to the key store, on a location that is already occupied by a valid key, this key area must be cleared first. This can be done by writing this register before the new key is written to the key store memory. Attempting to write to a key area that already contains a valid key is not allowed and will result in an error. 1028 read-write 0x00000000 RAM_AREA_WRITTEN7 RAM_AREA_WRITTEN7 [7:7] oneToClear RAM_AREA_WRITTEN6 RAM_AREA_WRITTEN6 [6:6] oneToClear RAM_AREA_WRITTEN5 RAM_AREA_WRITTEN5 [5:5] oneToClear RAM_AREA_WRITTEN4 RAM_AREA_WRITTEN4 [4:4] oneToClear RAM_AREA_WRITTEN3 RAM_AREA_WRITTEN3 [3:3] oneToClear RAM_AREA_WRITTEN2 RAM_AREA_WRITTEN2 [2:2] oneToClear RAM_AREA_WRITTEN1 RAM_AREA_WRITTEN1 [1:1] oneToClear RAM_AREA_WRITTEN0 RAM_AREA_WRITTEN0 [0:0] oneToClear KEYSIZE Key Size This register defines the size of the keys that are written with DMA. 1032 read-write 0x00000001 SIZE SIZE [1:0] KEYREADAREA Key Read Area 1036 read-write 0x00000008 BUSY BUSY [31:31] RAM_AREA RAM_AREA [3:0] 4 4 0-3 AESKEY2%s Clear AES_KEY2/GHASH Key 1280 write-only 0x00000000 KEY2 KEY2 [31:0] 4 4 0-3 AESKEY3%s Clear AES_KEY3 1296 write-only 0x00000000 KEY3 KEY3 [31:0] 4 4 0-3 AESIV%s AES Initialization Vector 1344 read-write 0x00000000 IV IV [31:0] AESCTL AES Input/Output Buffer Control 1360 read-write 0x80000000 CONTEXT_RDY CONTEXT_RDY [31:31] SAVED_CONTEXT_RDY SAVED_CONTEXT_RDY [30:30] SAVE_CONTEXT SAVE_CONTEXT [29:29] CCM_M CCM_M [24:22] CCM_L CCM_L [21:19] CCM CCM [18:18] CBC_MAC CBC_MAC [15:15] CTR_WIDTH CTR_WIDTH [8:7] CTR CTR [6:6] CBC CBC [5:5] KEY_SIZE KEY_SIZE [4:3] DIR DIR [2:2] INPUT_RDY INPUT_RDY [1:1] OUTPUT_RDY OUTPUT_RDY [0:0] AESDATALEN0 Crypto Data Length LSW 1364 write-only 0x00000000 LEN_LSW LEN_LSW [31:0] AESDATALEN1 Crypto Data Length MSW 1368 write-only 0x00000000 LEN_MSW LEN_MSW [28:0] AESAUTHLEN AES Authentication Length 1372 write-only 0x00000000 LEN LEN [31:0] AESDATAOUT0 Data Input/Output 1376 read-only 0x00000000 DATA DATA [31:0] AESDATAIN0 AESDATAIN0 AES Data Input/Output 0 1376 write-only 0x00000000 DATA DATA [31:0] AESDATAOUT1 AES Data Input/Output 3 1380 read-only 0x00000000 DATA DATA [31:0] AESDATAIN1 AESDATAIN1 AES Data Input/Output 1 1380 write-only 0x00000000 DATA DATA [31:0] AESDATAOUT2 AES Data Input/Output 2 1384 read-only 0x00000000 DATA DATA [31:0] AESDATAIN2 AESDATAIN2 AES Data Input/Output 2 1384 write-only 0x00000000 DATA DATA [31:0] AESDATAOUT3 AES Data Input/Output 3 1388 read-only 0x00000000 DATA DATA [31:0] AESDATAIN3 AESDATAIN3 Data Input/Output 1388 write-only 0x00000000 DATA DATA [31:0] 4 4 0-3 AESTAGOUT%s AES Tag Output 1392 read-only 0x00000000 TAG TAG [31:0] ALGSEL Master Algorithm Select This register configures the internal destination of the DMA controller. 1792 read-write 0x00000000 TAG TAG [31:31] AES AES [1:1] KEY_STORE KEY_STORE [0:0] DMAPROTCTL Master Protection Control 1796 read-write 0x00000000 EN EN [0:0] SWRESET Software Reset 1856 read-write 0x00000000 RESET RESET [0:0] oneToClear IRQTYPE Interrupt Configuration 1920 read-write 0x00000000 IEN IEN [0:0] IRQEN Interrupt Enable 1924 read-write 0x00000000 DMA_IN_DONE DMA_IN_DONE [1:1] RESULT_AVAIL RESULT_AVAIL [0:0] IRQCLR Interrupt Clear 1928 write-only 0x00000000 DMA_BUS_ERR DMA_BUS_ERR [31:31] KEY_ST_WR_ERR KEY_ST_WR_ERR [30:30] KEY_ST_RD_ERR KEY_ST_RD_ERR [29:29] DMA_IN_DONE DMA_IN_DONE [1:1] RESULT_AVAIL RESULT_AVAIL [0:0] IRQSET Interrupt Set 1932 write-only 0x00000000 DMA_IN_DONE DMA_IN_DONE [1:1] RESULT_AVAIL RESULT_AVAIL [0:0] IRQSTAT Interrupt Status 1936 read-only 0x00000000 DMA_BUS_ERR DMA_BUS_ERR [31:31] KEY_ST_WR_ERR KEY_ST_WR_ERR [30:30] KEY_ST_RD_ERR KEY_ST_RD_ERR [29:29] DMA_IN_DONE DMA_IN_DONE [1:1] RESULT_AVAIL RESULT_AVAIL [0:0] HWVER CTRL Module Version 2044 read-only 0x91118778 HW_MAJOR_VER HW_MAJOR_VER [27:24] HW_MINOR_VER HW_MINOR_VER [23:20] HW_PATCH_LVL HW_PATCH_LVL [19:16] VER_NUM_COMPL VER_NUM_COMPL [15:8] VER_NUM VER_NUM [7:0] EVENT Event Fabric Component Definition 0x40083000 0 0x1000 registers AON_GPIO_EDGE 0x0 I2C_IRQ 0x4 RFC_CPE_1 0x8 AON_RTC_COMB 0x10 UART0_COMB 0x14 AUX_SWEV0 0x18 SSI0_COMB 0x1C SSI1_COMB 0x20 RFC_CPE_0 0x24 RFC_HW_COMB 0x28 RFC_CMD_ACK 0x2C I2S_IRQ 0x30 AUX_SWEV1 0x34 WDT_IRQ 0x38 GPT0A 0x3C GPT0B 0x40 GPT1A 0x44 GPT1B 0x48 GPT2A 0x4C GPT2B 0x50 GPT3A 0x54 GPT3B 0x58 CRYPTO_RESULT_AVAIL_IRQ 0x5C DMA_DONE_COMB 0x60 DMA_ERR 0x64 FLASH 0x68 SWEV0 0x6C AUX_COMB 0x70 AON_PROG0 0x74 PROG0 0x78 AUX_COMPA 0x7C AUX_ADC_IRQ 0x80 TRNG_IRQ 0x84 CPUIRQSEL0 Output Selection for CPU Interrupt 0 0 read-only 0x00000004 EV EV [6:0] CPUIRQSEL1 Output Selection for CPU Interrupt 1 4 read-only 0x00000009 EV EV [6:0] CPUIRQSEL2 Output Selection for CPU Interrupt 2 8 read-only 0x0000001e EV EV [6:0] CPUIRQSEL3 Output Selection for CPU Interrupt 3 12 read-only 0x00000038 CPUIRQSEL4 Output Selection for CPU Interrupt 4 16 read-only 0x00000007 EV EV [6:0] CPUIRQSEL5 Output Selection for CPU Interrupt 5 20 read-only 0x00000024 EV EV [6:0] CPUIRQSEL6 Output Selection for CPU Interrupt 6 24 read-only 0x0000001c EV EV [6:0] CPUIRQSEL7 Output Selection for CPU Interrupt 7 28 read-only 0x00000022 EV EV [6:0] CPUIRQSEL8 Output Selection for CPU Interrupt 8 32 read-only 0x00000023 EV EV [6:0] CPUIRQSEL9 Output Selection for CPU Interrupt 9 36 read-only 0x0000001b EV EV [6:0] CPUIRQSEL10 Output Selection for CPU Interrupt 10 40 read-only 0x0000001a EV EV [6:0] CPUIRQSEL11 Output Selection for CPU Interrupt 11 44 read-only 0x00000019 EV EV [6:0] CPUIRQSEL12 Output Selection for CPU Interrupt 12 48 read-only 0x00000008 EV EV [6:0] CPUIRQSEL13 Output Selection for CPU Interrupt 13 52 read-only 0x0000001d EV EV [6:0] CPUIRQSEL14 Output Selection for CPU Interrupt 14 56 read-only 0x00000018 EV EV [6:0] CPUIRQSEL15 Output Selection for CPU Interrupt 15 60 read-only 0x00000010 EV EV [6:0] CPUIRQSEL16 Output Selection for CPU Interrupt 16 64 read-only 0x00000011 EV EV [6:0] CPUIRQSEL17 Output Selection for CPU Interrupt 17 68 read-only 0x00000012 EV EV [6:0] CPUIRQSEL18 Output Selection for CPU Interrupt 18 72 read-only 0x00000013 EV EV [6:0] CPUIRQSEL19 Output Selection for CPU Interrupt 19 76 read-only 0x0000000c EV EV [6:0] CPUIRQSEL20 Output Selection for CPU Interrupt 20 80 read-only 0x0000000d EV EV [6:0] CPUIRQSEL21 Output Selection for CPU Interrupt 21 84 read-only 0x0000000e EV EV [6:0] CPUIRQSEL22 Output Selection for CPU Interrupt 22 88 read-only 0x0000000f EV EV [6:0] CPUIRQSEL23 Output Selection for CPU Interrupt 23 92 read-only 0x0000005d EV EV [6:0] CPUIRQSEL24 Output Selection for CPU Interrupt 24 96 read-only 0x00000027 EV EV [6:0] CPUIRQSEL25 Output Selection for CPU Interrupt 25 100 read-only 0x00000026 EV EV [6:0] CPUIRQSEL26 Output Selection for CPU Interrupt 26 104 read-only 0x00000015 EV EV [6:0] CPUIRQSEL27 Output Selection for CPU Interrupt 27 108 read-only 0x00000064 EV EV [6:0] CPUIRQSEL28 Output Selection for CPU Interrupt 28 112 read-only 0x0000000b EV EV [6:0] CPUIRQSEL29 Output Selection for CPU Interrupt 29 116 read-only 0x00000001 EV EV [6:0] CPUIRQSEL30 Output Selection for CPU Interrupt 30 120 read-write 0x00000000 EV EV [6:0] CPUIRQSEL31 Output Selection for CPU Interrupt 31 124 read-only 0x0000006a EV EV [6:0] CPUIRQSEL32 Output Selection for CPU Interrupt 32 128 read-only 0x00000073 EV EV [6:0] CPUIRQSEL33 Output Selection for CPU Interrupt 33 132 read-only 0x00000068 EV EV [6:0] RFCSEL0 Output Selection for RFC Event 0 256 read-only 0x0000003d EV EV [6:0] RFCSEL1 Output Selection for RFC Event 1 260 read-only 0x0000003e EV EV [6:0] RFCSEL2 Output Selection for RFC Event 2 264 read-only 0x0000003f EV EV [6:0] RFCSEL3 Output Selection for RFC Event 3 268 read-only 0x00000040 EV EV [6:0] RFCSEL4 Output Selection for RFC Event 4 272 read-only 0x00000041 EV EV [6:0] RFCSEL5 Output Selection for RFC Event 5 276 read-only 0x00000042 EV EV [6:0] RFCSEL6 Output Selection for RFC Event 6 280 read-only 0x00000043 EV EV [6:0] RFCSEL7 Output Selection for RFC Event 7 284 read-only 0x00000044 EV EV [6:0] RFCSEL8 Output Selection for RFC Event 8 288 read-only 0x00000077 EV EV [6:0] RFCSEL9 Output Selection for RFC Event 9 292 read-write 0x00000002 EV EV [6:0] GPT0ACAPTSEL Output Selection for GPT0 0 512 read-write 0x00000055 EV EV [6:0] GPT0BCAPTSEL Output Selection for GPT0 1 516 read-write 0x00000056 EV EV [6:0] GPT1ACAPTSEL Output Selection for GPT1 0 768 read-write 0x00000057 EV EV [6:0] GPT1BCAPTSEL Output Selection for GPT1 1 772 read-write 0x00000058 EV EV [6:0] GPT2ACAPTSEL Output Selection for GPT2 0 1024 read-write 0x00000059 EV EV [6:0] GPT2BCAPTSEL Output Selection for GPT2 1 1028 read-write 0x0000005a EV EV [6:0] UDMACH1SSEL Output Selection for DMA Channel 1 SREQ 1288 read-only 0x00000031 EV EV [6:0] UDMACH1BSEL Output Selection for DMA Channel 1 REQ 1292 read-only 0x00000030 EV EV [6:0] UDMACH2SSEL Output Selection for DMA Channel 2 SREQ 1296 read-only 0x00000033 EV EV [6:0] UDMACH2BSEL Output Selection for DMA Channel 2 REQ 1300 read-only 0x00000032 EV EV [6:0] UDMACH3SSEL Output Selection for DMA Channel 3 SREQ 1304 read-only 0x00000029 EV EV [6:0] UDMACH3BSEL Output Selection for DMA Channel 3 REQ 1308 read-only 0x00000028 EV EV [6:0] UDMACH4SSEL Output Selection for DMA Channel 4 SREQ 1312 read-only 0x0000002b EV EV [6:0] UDMACH4BSEL Output Selection for DMA Channel 4 REQ 1316 read-only 0x0000002a EV EV [6:0] UDMACH5SSEL Output Selection for DMA Channel 5 SREQ 1320 read-only 0x0000003a UDMACH5BSEL Output Selection for DMA Channel 5 REQ 1324 read-only 0x00000039 UDMACH6SSEL Output Selection for DMA Channel 6 SREQ 1328 read-only 0x0000003c UDMACH6BSEL Output Selection for DMA Channel 6 REQ 1332 read-only 0x0000003b UDMACH7SSEL Output Selection for DMA Channel 7 SREQ 1336 read-only 0x00000075 EV EV [6:0] UDMACH7BSEL Output Selection for DMA Channel 7 REQ 1340 read-only 0x00000076 EV EV [6:0] UDMACH8SSEL Output Selection for DMA Channel 8 SREQ Single request is ignored for this channel 1344 read-only 0x00000074 EV EV [6:0] UDMACH8BSEL Output Selection for DMA Channel 8 REQ 1348 read-only 0x00000074 EV EV [6:0] UDMACH9SSEL Output Selection for DMA Channel 9 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS 1352 read-write 0x00000045 EV EV [6:0] UDMACH9BSEL Output Selection for DMA Channel 9 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS 1356 read-write 0x0000004d EV EV [6:0] UDMACH10SSEL Output Selection for DMA Channel 10 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS 1360 read-write 0x00000046 EV EV [6:0] UDMACH10BSEL Output Selection for DMA Channel 10 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS 1364 read-write 0x0000004e EV EV [6:0] UDMACH11SSEL Output Selection for DMA Channel 11 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS 1368 read-write 0x00000047 EV EV [6:0] UDMACH11BSEL Output Selection for DMA Channel 11 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS 1372 read-write 0x0000004f EV EV [6:0] UDMACH12SSEL Output Selection for DMA Channel 12 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS 1376 read-write 0x00000048 EV EV [6:0] UDMACH12BSEL Output Selection for DMA Channel 12 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS 1380 read-write 0x00000050 EV EV [6:0] UDMACH13BSEL Output Selection for DMA Channel 13 REQ 1388 read-only 0x00000003 EV EV [6:0] UDMACH14BSEL Output Selection for DMA Channel 14 REQ 1396 read-write 0x00000001 EV EV [6:0] UDMACH15BSEL Output Selection for DMA Channel 15 REQ 1404 read-only 0x00000007 EV EV [6:0] UDMACH16SSEL Output Selection for DMA Channel 16 SREQ 1408 read-only 0x0000002d EV EV [6:0] UDMACH16BSEL Output Selection for DMA Channel 16 REQ 1412 read-only 0x0000002c EV EV [6:0] UDMACH17SSEL Output Selection for DMA Channel 17 SREQ 1416 read-only 0x0000002f EV EV [6:0] UDMACH17BSEL Output Selection for DMA Channel 17 REQ 1420 read-only 0x0000002e EV EV [6:0] UDMACH21SSEL Output Selection for DMA Channel 21 SREQ 1448 read-only 0x00000064 EV EV [6:0] UDMACH21BSEL Output Selection for DMA Channel 21 REQ 1452 read-only 0x00000064 EV EV [6:0] UDMACH22SSEL Output Selection for DMA Channel 22 SREQ 1456 read-only 0x00000065 EV EV [6:0] UDMACH22BSEL Output Selection for DMA Channel 22 REQ 1460 read-only 0x00000065 EV EV [6:0] UDMACH23SSEL Output Selection for DMA Channel 23 SREQ 1464 read-only 0x00000066 EV EV [6:0] UDMACH23BSEL Output Selection for DMA Channel 23 REQ 1468 read-only 0x00000066 EV EV [6:0] UDMACH24SSEL Output Selection for DMA Channel 24 SREQ 1472 read-only 0x00000067 EV EV [6:0] UDMACH24BSEL Output Selection for DMA Channel 24 REQ 1476 read-only 0x00000067 EV EV [6:0] GPT3ACAPTSEL Output Selection for GPT3 0 1536 read-write 0x0000005b EV EV [6:0] GPT3BCAPTSEL Output Selection for GPT3 1 1540 read-write 0x0000005c EV EV [6:0] AUXSEL0 Output Selection for AUX Subscriber 0 1792 read-write 0x00000010 EV EV [6:0] CM3NMISEL0 Output Selection for NMI Subscriber 0 2048 read-only 0x00000063 EV EV [6:0] I2SSTMPSEL0 Output Selection for I2S Subscriber 0 2304 read-write 0x0000005f EV EV [6:0] FRZSEL0 Output Selection for FRZ Subscriber 0 2560 read-write 0x00000078 EV EV [6:0] SWEV Set or Clear Software Events 3840 read-write 0x00000000 SWEV3 SWEV3 [24:24] SWEV2 SWEV2 [16:16] SWEV1 SWEV1 [8:8] SWEV0 SWEV0 [0:0] FCFG1 Factory configuration area (FCFG1) 0x50001000 0 0x400 registers MISC_CONF_1 Misc configurations 160 read-only 0xffffff00 DEVICE_MINOR_REV DEVICE_MINOR_REV [7:0] BAW_MEAS_5 Internal. Only to be used through TI provided API. 176 read-only 0x00000000 BAW_D5 BAW_D5 [31:16] BAW_T5 BAW_T5 [15:8] BAW_DT5 BAW_DT5 [7:0] BAW_MEAS_4 Internal. Only to be used through TI provided API. 180 read-only 0x00000000 BAW_D4 BAW_D4 [31:16] BAW_T4 BAW_T4 [15:8] BAW_DT4 BAW_DT4 [7:0] BAW_MEAS_3 Internal. Only to be used through TI provided API. 184 read-only 0x00000000 BAW_D3 BAW_D3 [31:16] BAW_T3 BAW_T3 [15:8] BAW_DT3 BAW_DT3 [7:0] BAW_MEAS_2 Internal. Only to be used through TI provided API. 188 read-only 0x00000000 BAW_D2 BAW_D2 [31:16] BAW_T2 BAW_T2 [15:8] BAW_DT2 BAW_DT2 [7:0] BAW_MEAS_1 Internal. Only to be used through TI provided API. 192 read-only 0x00000000 BAW_D1 BAW_D1 [31:16] BAW_T1 BAW_T1 [15:8] BAW_DT1 BAW_DT1 [7:0] CONFIG_RF_FRONTEND_DIV5 Internal. Only to be used through TI provided API. 196 read-only 0xffffffff IFAMP_IB IFAMP_IB [31:28] LNA_IB LNA_IB [27:24] IFAMP_TRIM IFAMP_TRIM [23:19] CTL_PA0_TRIM CTL_PA0_TRIM [18:14] RFLDO_TRIM_OUTPUT RFLDO_TRIM_OUTPUT [6:0] CONFIG_RF_FRONTEND_DIV6 Internal. Only to be used through TI provided API. 200 read-only 0xffffffff IFAMP_IB IFAMP_IB [31:28] LNA_IB LNA_IB [27:24] IFAMP_TRIM IFAMP_TRIM [23:19] CTL_PA0_TRIM CTL_PA0_TRIM [18:14] RFLDO_TRIM_OUTPUT RFLDO_TRIM_OUTPUT [6:0] CONFIG_RF_FRONTEND_DIV10 Internal. Only to be used through TI provided API. 204 read-only 0xffffffff IFAMP_IB IFAMP_IB [31:28] LNA_IB LNA_IB [27:24] IFAMP_TRIM IFAMP_TRIM [23:19] CTL_PA0_TRIM CTL_PA0_TRIM [18:14] RFLDO_TRIM_OUTPUT RFLDO_TRIM_OUTPUT [6:0] CONFIG_RF_FRONTEND_DIV12 Internal. Only to be used through TI provided API. 208 read-only 0xffffffff IFAMP_IB IFAMP_IB [31:28] LNA_IB LNA_IB [27:24] IFAMP_TRIM IFAMP_TRIM [23:19] CTL_PA0_TRIM CTL_PA0_TRIM [18:14] RFLDO_TRIM_OUTPUT RFLDO_TRIM_OUTPUT [6:0] CONFIG_RF_FRONTEND_DIV15 Internal. Only to be used through TI provided API. 212 read-only 0xffffffff IFAMP_IB IFAMP_IB [31:28] LNA_IB LNA_IB [27:24] IFAMP_TRIM IFAMP_TRIM [23:19] CTL_PA0_TRIM CTL_PA0_TRIM [18:14] RFLDO_TRIM_OUTPUT RFLDO_TRIM_OUTPUT [6:0] CONFIG_RF_FRONTEND_DIV30 Internal. Only to be used through TI provided API. 216 read-only 0xffffffff IFAMP_IB IFAMP_IB [31:28] LNA_IB LNA_IB [27:24] IFAMP_TRIM IFAMP_TRIM [23:19] CTL_PA0_TRIM CTL_PA0_TRIM [18:14] RFLDO_TRIM_OUTPUT RFLDO_TRIM_OUTPUT [6:0] CONFIG_SYNTH_DIV5 Internal. Only to be used through TI provided API. 220 read-only 0xffffffff RFC_MDM_DEMIQMC0 RFC_MDM_DEMIQMC0 [27:12] LDOVCO_TRIM_OUTPUT LDOVCO_TRIM_OUTPUT [11:6] SLDO_TRIM_OUTPUT SLDO_TRIM_OUTPUT [5:0] CONFIG_SYNTH_DIV6 Internal. Only to be used through TI provided API. 224 read-only 0xffffffff RFC_MDM_DEMIQMC0 RFC_MDM_DEMIQMC0 [27:12] LDOVCO_TRIM_OUTPUT LDOVCO_TRIM_OUTPUT [11:6] SLDO_TRIM_OUTPUT SLDO_TRIM_OUTPUT [5:0] CONFIG_SYNTH_DIV10 Internal. Only to be used through TI provided API. 228 read-only 0xffffffff RFC_MDM_DEMIQMC0 RFC_MDM_DEMIQMC0 [27:12] LDOVCO_TRIM_OUTPUT LDOVCO_TRIM_OUTPUT [11:6] SLDO_TRIM_OUTPUT SLDO_TRIM_OUTPUT [5:0] CONFIG_SYNTH_DIV12 Internal. Only to be used through TI provided API. 232 read-only 0xffffffff RFC_MDM_DEMIQMC0 RFC_MDM_DEMIQMC0 [27:12] LDOVCO_TRIM_OUTPUT LDOVCO_TRIM_OUTPUT [11:6] SLDO_TRIM_OUTPUT SLDO_TRIM_OUTPUT [5:0] CONFIG_SYNTH_DIV15 Internal. Only to be used through TI provided API. 236 read-only 0xffffffff RFC_MDM_DEMIQMC0 RFC_MDM_DEMIQMC0 [27:12] LDOVCO_TRIM_OUTPUT LDOVCO_TRIM_OUTPUT [11:6] SLDO_TRIM_OUTPUT SLDO_TRIM_OUTPUT [5:0] CONFIG_SYNTH_DIV30 Internal. Only to be used through TI provided API. 240 read-only 0xffffffff RFC_MDM_DEMIQMC0 RFC_MDM_DEMIQMC0 [27:12] LDOVCO_TRIM_OUTPUT LDOVCO_TRIM_OUTPUT [11:6] SLDO_TRIM_OUTPUT SLDO_TRIM_OUTPUT [5:0] CONFIG_MISC_ADC_DIV5 Internal. Only to be used through TI provided API. 244 read-only 0xffffffff RSSI_OFFSET RSSI_OFFSET [16:9] QUANTCTLTHRES QUANTCTLTHRES [8:6] DACTRIM DACTRIM [5:0] CONFIG_MISC_ADC_DIV6 Internal. Only to be used through TI provided API. 248 read-only 0xffffffff RSSI_OFFSET RSSI_OFFSET [16:9] QUANTCTLTHRES QUANTCTLTHRES [8:6] DACTRIM DACTRIM [5:0] CONFIG_MISC_ADC_DIV10 Internal. Only to be used through TI provided API. 252 read-only 0xffffffff RSSI_OFFSET RSSI_OFFSET [16:9] QUANTCTLTHRES QUANTCTLTHRES [8:6] DACTRIM DACTRIM [5:0] CONFIG_MISC_ADC_DIV12 Internal. Only to be used through TI provided API. 256 read-only 0xffffffff RSSI_OFFSET RSSI_OFFSET [16:9] QUANTCTLTHRES QUANTCTLTHRES [8:6] DACTRIM DACTRIM [5:0] CONFIG_MISC_ADC_DIV15 Internal. Only to be used through TI provided API. 260 read-only 0xffffffff RSSI_OFFSET RSSI_OFFSET [16:9] QUANTCTLTHRES QUANTCTLTHRES [8:6] DACTRIM DACTRIM [5:0] CONFIG_MISC_ADC_DIV30 Internal. Only to be used through TI provided API. 264 read-only 0xffffffff RSSI_OFFSET RSSI_OFFSET [16:9] QUANTCTLTHRES QUANTCTLTHRES [8:6] DACTRIM DACTRIM [5:0] SHDW_DIE_ID_0 Shadow of DIE_ID_0 register in eFuse 280 read-only 0x00000000 ID_31_0 ID_31_0 [31:0] SHDW_DIE_ID_1 Shadow of DIE_ID_1 register in eFuse 284 read-only 0x00000000 ID_63_32 ID_63_32 [31:0] SHDW_DIE_ID_2 Shadow of DIE_ID_2 register in eFuse 288 read-only 0x00000000 ID_95_64 ID_95_64 [31:0] SHDW_DIE_ID_3 Shadow of DIE_ID_3 register in eFuse 292 read-only 0x00000000 ID_127_96 ID_127_96 [31:0] SHDW_OSC_BIAS_LDO_TRIM Internal. Only to be used through TI provided API. 312 read-only 0x00000000 SET_RCOSC_HF_COARSE_RESISTOR SET_RCOSC_HF_COARSE_RESISTOR [28:27] TRIMMAG TRIMMAG [26:23] TRIMIREF TRIMIREF [22:18] ITRIM_DIG_LDO ITRIM_DIG_LDO [17:16] VTRIM_DIG VTRIM_DIG [15:12] VTRIM_COARSE VTRIM_COARSE [11:8] RCOSCHF_CTRIM RCOSCHF_CTRIM [7:0] SHDW_ANA_TRIM Internal. Only to be used through TI provided API. 316 read-only 0x00000000 BOD_BANDGAP_TRIM_CNF BOD_BANDGAP_TRIM_CNF [26:25] VDDR_ENABLE_PG1 VDDR_ENABLE_PG1 [24:24] VDDR_OK_HYS VDDR_OK_HYS [23:23] IPTAT_TRIM IPTAT_TRIM [22:21] VDDR_TRIM VDDR_TRIM [20:16] TRIMBOD_INTMODE TRIMBOD_INTMODE [15:11] TRIMBOD_EXTMODE TRIMBOD_EXTMODE [10:6] TRIMTEMP TRIMTEMP [5:0] FLASH_NUMBER 356 read-only 0x00000000 LOT_NUMBER LOT_NUMBER [31:0] FLASH_COORDINATE 364 read-only 0x00000000 XCOORDINATE XCOORDINATE [31:16] YCOORDINATE YCOORDINATE [15:0] FLASH_E_P Internal. Only to be used through TI provided API. 368 read-only 0x17331a33 PSU PSU [31:24] ESU ESU [23:16] PVSU PVSU [15:8] EVSU EVSU [7:0] FLASH_C_E_P_R Internal. Only to be used through TI provided API. 372 read-only 0x0a0a2000 RVSU RVSU [31:24] PV_ACCESS PV_ACCESS [23:16] A_EXEZ_SETUP A_EXEZ_SETUP [15:12] CVSU CVSU [11:0] FLASH_P_R_PV Internal. Only to be used through TI provided API. 376 read-only 0x026e0200 PH PH [31:24] RH RH [23:16] PVH PVH [15:8] PVH2 PVH2 [7:0] FLASH_EH_SEQ Internal. Only to be used through TI provided API. 380 read-only 0x0200f000 EH EH [31:24] SEQ SEQ [23:16] VSTAT VSTAT [15:12] SM_FREQUENCY SM_FREQUENCY [11:0] FLASH_VHV_E Internal. Only to be used through TI provided API. 384 read-only 0x00000001 VHV_E_START VHV_E_START [31:16] VHV_E_STEP_HIGHT VHV_E_STEP_HIGHT [15:0] FLASH_PP Internal. Only to be used through TI provided API. 388 read-only 0x00000014 PUMP_SU PUMP_SU [31:24] MAX_PP MAX_PP [15:0] FLASH_PROG_EP Internal. Only to be used through TI provided API. 392 read-only 0x0fa00010 MAX_EP MAX_EP [31:16] PROGRAM_PW PROGRAM_PW [15:0] FLASH_ERA_PW Internal. Only to be used through TI provided API. 396 read-only 0x00000fa0 ERASE_PW ERASE_PW [31:0] FLASH_VHV Internal. Only to be used through TI provided API. 400 read-only 0x00000004 TRIM13_P TRIM13_P [27:24] VHV_P VHV_P [19:16] TRIM13_E TRIM13_E [11:8] VHV_E VHV_E [3:0] FLASH_VHV_PV Internal. Only to be used through TI provided API. 404 read-only 0x00080001 TRIM13_PV TRIM13_PV [27:24] VHV_PV VHV_PV [19:16] VCG2P5 VCG2P5 [15:8] VINH VINH [7:0] FLASH_V Internal. Only to be used through TI provided API. 408 read-only 0x00000000 VSL_P VSL_P [31:24] VWL_P VWL_P [23:16] V_READ V_READ [15:8] USER_ID User Identification. Reading this register or the ICEPICK_DEVICE_ID register is the only support way of identifying a device. The value of this register will be written to AON_WUC:JTAGUSERCODE by boot FW while in safezone. 660 read-only 0x00000000 PG_REV PG_REV [31:28] VER VER [27:26] SEQUENCE SEQUENCE [22:19] PKG PKG [18:16] PROTOCOL PROTOCOL [15:12] FLASH_OTP_DATA3 Internal. Only to be used through TI provided API. 688 read-only 0x00110003 EC_STEP_SIZE EC_STEP_SIZE [31:23] DO_PRECOND DO_PRECOND [22:22] MAX_EC_LEVEL MAX_EC_LEVEL [21:18] TRIM_1P7 TRIM_1P7 [17:16] FLASH_SIZE FLASH_SIZE [15:8] WAIT_SYSCODE WAIT_SYSCODE [7:0] ANA2_TRIM Internal. Only to be used through TI provided API. 692 read-only 0x8240f47f RCOSCHFCTRIMFRACT_EN RCOSCHFCTRIMFRACT_EN [31:31] RCOSCHFCTRIMFRACT RCOSCHFCTRIMFRACT [30:26] SET_RCOSC_HF_FINE_RESISTOR SET_RCOSC_HF_FINE_RESISTOR [24:23] ATESTLF_UDIGLDO_IBIAS_TRIM ATESTLF_UDIGLDO_IBIAS_TRIM [22:22] NANOAMP_RES_TRIM NANOAMP_RES_TRIM [21:16] DITHER_EN DITHER_EN [11:11] DCDC_IPEAK DCDC_IPEAK [10:8] DEAD_TIME_TRIM DEAD_TIME_TRIM [7:6] DCDC_LOW_EN_SEL DCDC_LOW_EN_SEL [5:3] DCDC_HIGH_EN_SEL DCDC_HIGH_EN_SEL [2:0] LDO_TRIM Internal. Only to be used through TI provided API. 696 read-only 0xe0f8e0fb VDDR_TRIM_SLEEP VDDR_TRIM_SLEEP [28:24] GLDO_CURSRC GLDO_CURSRC [18:16] ITRIM_DIGLDO_LOAD ITRIM_DIGLDO_LOAD [12:11] ITRIM_UDIGLDO ITRIM_UDIGLDO [10:8] VTRIM_DELTA VTRIM_DELTA [2:0] MAC_BLE_0 MAC BLE Address 0 744 read-only 0x00000000 ADDR_0_31 ADDR_0_31 [31:0] MAC_BLE_1 MAC BLE Address 1 748 read-only 0x00000000 ADDR_32_63 ADDR_32_63 [31:0] MAC_15_4_0 MAC IEEE 802.15.4 Address 0 752 read-only 0x00000000 ADDR_0_31 ADDR_0_31 [31:0] MAC_15_4_1 MAC IEEE 802.15.4 Address 1 756 read-only 0x00000000 ADDR_32_63 ADDR_32_63 [31:0] FLASH_OTP_DATA4 Internal. Only to be used through TI provided API. 776 read-only 0x98989f9f STANDBY_MODE_SEL_INT_WRT STANDBY_MODE_SEL_INT_WRT [31:31] STANDBY_PW_SEL_INT_WRT STANDBY_PW_SEL_INT_WRT [30:29] DIS_STANDBY_INT_WRT DIS_STANDBY_INT_WRT [28:28] DIS_IDLE_INT_WRT DIS_IDLE_INT_WRT [27:27] VIN_AT_X_INT_WRT VIN_AT_X_INT_WRT [26:24] STANDBY_MODE_SEL_EXT_WRT STANDBY_MODE_SEL_EXT_WRT [23:23] STANDBY_PW_SEL_EXT_WRT STANDBY_PW_SEL_EXT_WRT [22:21] DIS_STANDBY_EXT_WRT DIS_STANDBY_EXT_WRT [20:20] DIS_IDLE_EXT_WRT DIS_IDLE_EXT_WRT [19:19] VIN_AT_X_EXT_WRT VIN_AT_X_EXT_WRT [18:16] STANDBY_MODE_SEL_INT_RD STANDBY_MODE_SEL_INT_RD [15:15] STANDBY_PW_SEL_INT_RD STANDBY_PW_SEL_INT_RD [14:13] DIS_STANDBY_INT_RD DIS_STANDBY_INT_RD [12:12] DIS_IDLE_INT_RD DIS_IDLE_INT_RD [11:11] VIN_AT_X_INT_RD VIN_AT_X_INT_RD [10:8] STANDBY_MODE_SEL_EXT_RD STANDBY_MODE_SEL_EXT_RD [7:7] STANDBY_PW_SEL_EXT_RD STANDBY_PW_SEL_EXT_RD [6:5] DIS_STANDBY_EXT_RD DIS_STANDBY_EXT_RD [4:4] DIS_IDLE_EXT_RD DIS_IDLE_EXT_RD [3:3] VIN_AT_X_EXT_RD VIN_AT_X_EXT_RD [2:0] MISC_TRIM Miscellaneous Trim Parameters 780 read-only 0xffffff33 TEMPVSLOPE TEMPVSLOPE [7:0] RCOSC_HF_TEMPCOMP Internal. Only to be used through TI provided API. 784 read-only 0x00000003 FINE_RESISTOR FINE_RESISTOR [31:24] CTRIM CTRIM [23:16] CTRIMFRACT_QUAD CTRIMFRACT_QUAD [15:8] CTRIMFRACT_SLOPE CTRIMFRACT_SLOPE [7:0] ICEPICK_DEVICE_ID IcePick Device Identification Reading this register or the USER_ID register is the only support way of identifying a device. 792 read-only 0x8b99a02f PG_REV PG_REV [31:28] WAFER_ID WAFER_ID [27:12] MANUFACTURER_ID MANUFACTURER_ID [11:0] FCFG1_REVISION Factory Configuration (FCFG1) Revision 796 read-only 0x00000023 REV REV [31:0] MISC_OTP_DATA Misc OTP Data 800 read-only 0x0000c600 RCOSC_HF_ITUNE RCOSC_HF_ITUNE [31:28] RCOSC_HF_CRIM RCOSC_HF_CRIM [27:20] PER_M PER_M [19:15] PER_E PER_E [14:12] PO_TAIL_RES_TRIM PO_TAIL_RES_TRIM [11:8] TEST_PROGRAM_REV TEST_PROGRAM_REV [7:0] IOCONF IO Configuration 836 read-only 0x7fffff8000 GPIO_CNT GPIO_CNT [6:0] CONFIG_IF_ADC Internal. Only to be used through TI provided API. 844 read-only 0x3460f400 FF2ADJ FF2ADJ [31:28] FF3ADJ FF3ADJ [27:24] INT3ADJ INT3ADJ [23:20] FF1ADJ FF1ADJ [19:16] AAFCAP AAFCAP [15:14] INT2ADJ INT2ADJ [13:10] IFDIGLDO_TRIM_OUTPUT IFDIGLDO_TRIM_OUTPUT [9:5] IFANALDO_TRIM_OUTPUT IFANALDO_TRIM_OUTPUT [4:0] CONFIG_OSC_TOP Internal. Only to be used through TI provided API. 848 read-only 0xfc00fc00 XOSC_HF_ROW_Q12 XOSC_HF_ROW_Q12 [29:26] XOSC_HF_COLUMN_Q12 XOSC_HF_COLUMN_Q12 [25:10] RCOSCLF_CTUNE_TRIM RCOSCLF_CTUNE_TRIM [9:2] RCOSCLF_RTUNE_TRIM RCOSCLF_RTUNE_TRIM [1:0] CONFIG_RF_FRONTEND Internal. Only to be used through TI provided API. 852 read-only 0x70001f80 IFAMP_IB IFAMP_IB [31:28] LNA_IB LNA_IB [27:24] IFAMP_TRIM IFAMP_TRIM [23:19] CTL_PA0_TRIM CTL_PA0_TRIM [18:14] PATRIMCOMPLETE_N PATRIMCOMPLETE_N [13:13] RFLDO_TRIM_OUTPUT RFLDO_TRIM_OUTPUT [6:0] CONFIG_SYNTH Internal. Only to be used through TI provided API. 856 read-only 0xfffff000 RFC_MDM_DEMIQMC0 RFC_MDM_DEMIQMC0 [27:12] LDOVCO_TRIM_OUTPUT LDOVCO_TRIM_OUTPUT [11:6] SLDO_TRIM_OUTPUT SLDO_TRIM_OUTPUT [5:0] SOC_ADC_ABS_GAIN AUX_ADC Gain in Absolute Reference Mode 860 read-only 0x00000000 SOC_ADC_ABS_GAIN_TEMP1 SOC_ADC_ABS_GAIN_TEMP1 [15:0] SOC_ADC_REL_GAIN AUX_ADC Gain in Relative Reference Mode 864 read-only 0x00000000 SOC_ADC_REL_GAIN_TEMP1 SOC_ADC_REL_GAIN_TEMP1 [15:0] SOC_ADC_OFFSET_INT AUX_ADC Temperature Offsets in Absolute Reference Mode 872 read-only 0x00000000 SOC_ADC_REL_OFFSET_TEMP1 SOC_ADC_REL_OFFSET_TEMP1 [23:16] SOC_ADC_ABS_OFFSET_TEMP1 SOC_ADC_ABS_OFFSET_TEMP1 [7:0] SOC_ADC_REF_TRIM_AND_OFFSET_EXT Internal. Only to be used through TI provided API. 876 read-only 0x00300080 SOC_ADC_REF_VOLTAGE_TRIM_TEMP1 SOC_ADC_REF_VOLTAGE_TRIM_TEMP1 [5:0] AMPCOMP_TH1 Internal. Only to be used through TI provided API. 880 read-only 0xff7b828e HPMRAMP3_LTH HPMRAMP3_LTH [23:18] HPMRAMP3_HTH HPMRAMP3_HTH [15:10] IBIASCAP_LPTOHP_OL_CNT IBIASCAP_LPTOHP_OL_CNT [9:6] HPMRAMP1_TH HPMRAMP1_TH [5:0] AMPCOMP_TH2 Internal. Only to be used through TI provided API. 884 read-only 0x6b8b0303 LPMUPDATE_LTH LPMUPDATE_LTH [31:26] LPMUPDATE_HTM LPMUPDATE_HTM [23:18] ADC_COMP_AMPTH_LPM ADC_COMP_AMPTH_LPM [15:10] ADC_COMP_AMPTH_HPM ADC_COMP_AMPTH_HPM [7:2] AMPCOMP_CTRL1 Internal. Only to be used through TI provided API. 888 read-only 0xff183f47 AMPCOMP_REQ_MODE AMPCOMP_REQ_MODE [30:30] IBIAS_OFFSET IBIAS_OFFSET [23:20] IBIAS_INIT IBIAS_INIT [19:16] LPM_IBIAS_WAIT_CNT_FINAL LPM_IBIAS_WAIT_CNT_FINAL [15:8] CAP_STEP CAP_STEP [7:4] IBIASCAP_HPTOLP_OL_CNT IBIASCAP_HPTOLP_OL_CNT [3:0] ANABYPASS_VALUE2 Internal. Only to be used through TI provided API. 892 read-only 0xffffc3ff XOSC_HF_IBIASTHERM XOSC_HF_IBIASTHERM [13:0] CONFIG_MISC_ADC Internal. Only to be used through TI provided API. 896 read-only 0xfffc014d RSSITRIMCOMPLETE_N RSSITRIMCOMPLETE_N [17:17] RSSI_OFFSET RSSI_OFFSET [16:9] QUANTCTLTHRES QUANTCTLTHRES [8:6] DACTRIM DACTRIM [5:0] VOLT_TRIM Internal. Only to be used through TI provided API. 904 read-only 0xffffffe0 VDDR_TRIM_HH VDDR_TRIM_HH [28:24] VDDR_TRIM_H VDDR_TRIM_H [20:16] VDDR_TRIM_SLEEP_H VDDR_TRIM_SLEEP_H [12:8] TRIMBOD_H TRIMBOD_H [4:0] OSC_CONF OSC Configuration 908 read-only 0xf0080000 ADC_SH_VBUF_EN ADC_SH_VBUF_EN [29:29] ADC_SH_MODE_EN ADC_SH_MODE_EN [28:28] ATESTLF_RCOSCLF_IBIAS_TRIM ATESTLF_RCOSCLF_IBIAS_TRIM [27:27] XOSCLF_REGULATOR_TRIM XOSCLF_REGULATOR_TRIM [26:25] XOSCLF_CMIRRWR_RATIO XOSCLF_CMIRRWR_RATIO [24:21] XOSC_HF_FAST_START XOSC_HF_FAST_START [20:19] XOSC_OPTION XOSC_OPTION [18:18] BAW_OPTION BAW_OPTION [17:17] BAW_BIAS_HOLD_MODE_EN BAW_BIAS_HOLD_MODE_EN [16:16] BAW_CURRMIRR_RATIO BAW_CURRMIRR_RATIO [15:12] BAW_BIAS_RES_SET BAW_BIAS_RES_SET [11:8] BAW_FILTER_EN BAW_FILTER_EN [7:7] BAW_BIAS_RECHARGE_DELAY BAW_BIAS_RECHARGE_DELAY [6:5] BAW_SERIES_CAP BAW_SERIES_CAP [2:1] BAW_DIV3_BYPASS BAW_DIV3_BYPASS [0:0] CAP_TRIM Internal. Only to be used through TI provided API. 916 read-only 0xffffffff FLUX_CAP_0P28_TRIM FLUX_CAP_0P28_TRIM [31:16] FLUX_CAP_0P4_TRIM FLUX_CAP_0P4_TRIM [15:0] MISC_OTP_DATA_1 Internal. Only to be used through TI provided API. 920 read-only 0xe00403f8 PEAK_DET_ITRIM PEAK_DET_ITRIM [28:27] HP_BUF_ITRIM HP_BUF_ITRIM [26:24] LP_BUF_ITRIM LP_BUF_ITRIM [23:22] DBLR_LOOP_FILTER_RESET_VOLTAGE DBLR_LOOP_FILTER_RESET_VOLTAGE [21:20] HPM_IBIAS_WAIT_CNT HPM_IBIAS_WAIT_CNT [19:10] LPM_IBIAS_WAIT_CNT LPM_IBIAS_WAIT_CNT [9:4] IDAC_STEP IDAC_STEP [3:0] PWD_CURR_20C Power Down Current Control 20C 924 read-only 0x080ba608 DELTA_CACHE_REF DELTA_CACHE_REF [31:24] DELTA_RFMEM_RET DELTA_RFMEM_RET [23:16] DELTA_XOSC_LPM DELTA_XOSC_LPM [15:8] BASELINE BASELINE [7:0] PWD_CURR_35C Power Down Current Control 35C 928 read-only 0x0c10a50a DELTA_CACHE_REF DELTA_CACHE_REF [31:24] DELTA_RFMEM_RET DELTA_RFMEM_RET [23:16] DELTA_XOSC_LPM DELTA_XOSC_LPM [15:8] BASELINE BASELINE [7:0] PWD_CURR_50C Power Down Current Control 50C 932 read-only 0x1218a20d DELTA_CACHE_REF DELTA_CACHE_REF [31:24] DELTA_RFMEM_RET DELTA_RFMEM_RET [23:16] DELTA_XOSC_LPM DELTA_XOSC_LPM [15:8] BASELINE BASELINE [7:0] PWD_CURR_65C Power Down Current Control 65C 936 read-only 0x1c259c14 DELTA_CACHE_REF DELTA_CACHE_REF [31:24] DELTA_RFMEM_RET DELTA_RFMEM_RET [23:16] DELTA_XOSC_LPM DELTA_XOSC_LPM [15:8] BASELINE BASELINE [7:0] PWD_CURR_80C Power Down Current Control 80C 940 read-only 0x2e3b9021 DELTA_CACHE_REF DELTA_CACHE_REF [31:24] DELTA_RFMEM_RET DELTA_RFMEM_RET [23:16] DELTA_XOSC_LPM DELTA_XOSC_LPM [15:8] BASELINE BASELINE [7:0] PWD_CURR_95C Power Down Current Control 95C 944 read-only 0x4c627a3b DELTA_CACHE_REF DELTA_CACHE_REF [31:24] DELTA_RFMEM_RET DELTA_RFMEM_RET [23:16] DELTA_XOSC_LPM DELTA_XOSC_LPM [15:8] BASELINE BASELINE [7:0] PWD_CURR_110C Power Down Current Control 110C 948 read-only 0x789e706b DELTA_CACHE_REF DELTA_CACHE_REF [31:24] DELTA_RFMEM_RET DELTA_RFMEM_RET [23:16] DELTA_XOSC_LPM DELTA_XOSC_LPM [15:8] BASELINE BASELINE [7:0] PWD_CURR_125C Power Down Current Control 125C 952 read-only 0xade1809a DELTA_CACHE_REF DELTA_CACHE_REF [31:24] DELTA_RFMEM_RET DELTA_RFMEM_RET [23:16] DELTA_XOSC_LPM DELTA_XOSC_LPM [15:8] BASELINE BASELINE [7:0] FLASH Flash sub-system registers, includes the Flash Memory Controller (FMC), flash read path, and an integrated Efuse controller and EFUSEROM. 0x40030000 0 0x00004000 registers STAT FMC and Efuse Status 28 read-only 0x00000000 EFUSE_BLANK EFUSE_BLANK [15:15] EFUSE_TIMEOUT EFUSE_TIMEOUT [14:14] EFUSE_CRC_ERROR EFUSE_CRC_ERROR [13:13] EFUSE_ERRCODE EFUSE_ERRCODE [12:8] SAMHOLD_DIS SAMHOLD_DIS [2:2] BUSY BUSY [1:1] POWER_MODE POWER_MODE [0:0] CFG Internal. Only to be used through TI provided API. 36 read-write 0x00000000 STANDBY_MODE_SEL STANDBY_MODE_SEL [8:8] STANDBY_PW_SEL STANDBY_PW_SEL [7:6] DIS_EFUSECLK DIS_EFUSECLK [5:5] DIS_READACCESS DIS_READACCESS [4:4] ENABLE_SWINTF ENABLE_SWINTF [3:3] DIS_STANDBY DIS_STANDBY [1:1] DIS_IDLE DIS_IDLE [0:0] SYSCODE_START Internal. Only to be used through TI provided API. 40 read-write 0x00000000 SYSCODE_START SYSCODE_START [4:0] FLASH_SIZE Internal. Only to be used through TI provided API. 44 read-write 0x00000000 SECTORS SECTORS [7:0] FWLOCK Internal. Only to be used through TI provided API. 60 read-write 0x00000000 FWLOCK FWLOCK [2:0] FWFLAG Internal. Only to be used through TI provided API. 64 read-write 0x00000000 FWFLAG FWFLAG [2:0] EFUSE Internal. Only to be used through TI provided API. 4096 write-only 0x00000000 INSTRUCTION INSTRUCTION [28:24] DUMPWORD DUMPWORD [15:0] EFUSEADDR Internal. Only to be used through TI provided API. 4100 write-only 0x00000000 BLOCK BLOCK [15:11] ROW ROW [10:0] DATAUPPER Internal. Only to be used through TI provided API. 4104 write-only 0x00000000 SPARE SPARE [7:3] P P [2:2] R R [1:1] EEN EEN [0:0] DATALOWER Internal. Only to be used through TI provided API. 4108 write-only 0x00000000 DATA DATA [31:0] EFUSECFG Internal. Only to be used through TI provided API. 4112 write-only 0x00000001 IDLEGATING IDLEGATING [8:8] SLAVEPOWER SLAVEPOWER [4:3] GATING GATING [0:0] EFUSESTAT Internal. Only to be used through TI provided API. 4116 write-only 0x00000001 RESETDONE RESETDONE [0:0] ACC Internal. Only to be used through TI provided API. 4120 write-only 0x00000000 ACCUMULATOR ACCUMULATOR [23:0] BOUNDARY Internal. Only to be used through TI provided API. 4124 write-only 0x00000000 DISROW0 DISROW0 [23:23] SPARE SPARE [22:22] EFC_SELF_TEST_ERROR EFC_SELF_TEST_ERROR [21:21] EFC_INSTRUCTION_INFO EFC_INSTRUCTION_INFO [20:20] EFC_INSTRUCTION_ERROR EFC_INSTRUCTION_ERROR [19:19] EFC_AUTOLOAD_ERROR EFC_AUTOLOAD_ERROR [18:18] OUTPUTENABLE OUTPUTENABLE [17:14] SYS_ECC_SELF_TEST_EN SYS_ECC_SELF_TEST_EN [13:13] SYS_ECC_OVERRIDE_EN SYS_ECC_OVERRIDE_EN [12:12] EFC_FDI EFC_FDI [11:11] SYS_DIEID_AUTOLOAD_EN SYS_DIEID_AUTOLOAD_EN [10:10] SYS_REPAIR_EN SYS_REPAIR_EN [9:8] SYS_WS_READ_STATES SYS_WS_READ_STATES [7:4] INPUTENABLE INPUTENABLE [3:0] EFUSEFLAG Internal. Only to be used through TI provided API. 4128 write-only 0x00000000 KEY KEY [0:0] EFUSEKEY Internal. Only to be used through TI provided API. 4132 write-only 0x00000000 CODE CODE [31:0] EFUSERELEASE Internal. Only to be used through TI provided API. 4136 write-only 0x00000000 ODPYEAR ODPYEAR [31:25] ODPMONTH ODPMONTH [24:21] ODPDAY ODPDAY [20:16] EFUSEYEAR EFUSEYEAR [15:9] EFUSEMONTH EFUSEMONTH [8:5] EFUSEDAY EFUSEDAY [4:0] EFUSEPINS Internal. Only to be used through TI provided API. 4140 write-only 0x00000000 EFC_SELF_TEST_DONE EFC_SELF_TEST_DONE [15:15] EFC_SELF_TEST_ERROR EFC_SELF_TEST_ERROR [14:14] SYS_ECC_SELF_TEST_EN SYS_ECC_SELF_TEST_EN [13:13] EFC_INSTRUCTION_INFO EFC_INSTRUCTION_INFO [12:12] EFC_INSTRUCTION_ERROR EFC_INSTRUCTION_ERROR [11:11] EFC_AUTOLOAD_ERROR EFC_AUTOLOAD_ERROR [10:10] SYS_ECC_OVERRIDE_EN SYS_ECC_OVERRIDE_EN [9:9] EFC_READY EFC_READY [8:8] EFC_FCLRZ EFC_FCLRZ [7:7] SYS_DIEID_AUTOLOAD_EN SYS_DIEID_AUTOLOAD_EN [6:6] SYS_REPAIR_EN SYS_REPAIR_EN [5:4] SYS_WS_READ_STATES SYS_WS_READ_STATES [3:0] EFUSECRA Internal. Only to be used through TI provided API. 4144 write-only 0x00000000 DATA DATA [5:0] EFUSEREAD Internal. Only to be used through TI provided API. 4148 write-only 0x00000000 DATABIT DATABIT [9:8] READCLOCK READCLOCK [7:4] DEBUG DEBUG [3:3] SPARE SPARE [2:2] MARGIN MARGIN [1:0] EFUSEPROGRAM Internal. Only to be used through TI provided API. 4152 write-only 0x00000000 COMPAREDISABLE COMPAREDISABLE [30:30] CLOCKSTALL CLOCKSTALL [29:14] VPPTOVDD VPPTOVDD [13:13] ITERATIONS ITERATIONS [12:9] WRITECLOCK WRITECLOCK [8:0] EFUSEERROR Internal. Only to be used through TI provided API. 4156 write-only 0x00000000 DONE DONE [5:5] CODE CODE [4:0] SINGLEBIT Internal. Only to be used through TI provided API. 4160 write-only 0x00000000 FROMN FROMN [31:1] FROM0 FROM0 [0:0] TWOBIT Internal. Only to be used through TI provided API. 4164 write-only 0x00000000 FROMN FROMN [31:1] FROM0 FROM0 [0:0] SELFTESTCYC Internal. Only to be used through TI provided API. 4168 write-only 0x00000000 CYCLES CYCLES [31:0] SELFTESTSIGN Internal. Only to be used through TI provided API. 4172 write-only 0x00000000 SIGNATURE SIGNATURE [31:0] FRDCTL Internal. Only to be used through TI provided API. 8192 read-write 0x00000200 RWAIT RWAIT [11:8] FSPRD Internal. Only to be used through TI provided API. 8196 read-write 0x00000000 RMBSEM RMBSEM [15:8] RM1 RM1 [1:1] RM0 RM0 [0:0] FEDACCTL1 Internal. Only to be used through TI provided API. 8200 read-write 0x00000000 SUSP_IGNR SUSP_IGNR [24:24] FEDACSTAT Internal. Only to be used through TI provided API. 8220 read-write 0x00000000 RVF_INT RVF_INT [25:25] oneToClear FSM_DONE FSM_DONE [24:24] oneToClear FBPROT Internal. Only to be used through TI provided API. 8240 read-write 0x00000000 PROTL1DIS PROTL1DIS [0:0] FBSE Internal. Only to be used through TI provided API. 8244 read-write 0x00000000 BSE BSE [15:0] FBBUSY Internal. Only to be used through TI provided API. 8248 read-only 0x000000fe BUSY BUSY [7:0] FBAC Internal. Only to be used through TI provided API. 8252 read-write 0x0000000f OTPPROTDIS OTPPROTDIS [16:16] BAGP BAGP [15:8] VREADS VREADS [7:0] FBFALLBACK Internal. Only to be used through TI provided API. 8256 read-write 0x0505ffff FSM_PWRSAV FSM_PWRSAV [27:24] REG_PWRSAV REG_PWRSAV [19:16] BANKPWR7 BANKPWR7 [15:14] BANKPWR6 BANKPWR6 [13:12] BANKPWR5 BANKPWR5 [11:10] BANKPWR4 BANKPWR4 [9:8] BANKPWR3 BANKPWR3 [7:6] BANKPWR2 BANKPWR2 [5:4] BANKPWR1 BANKPWR1 [3:2] BANKPWR0 BANKPWR0 [1:0] FBPRDY Internal. Only to be used through TI provided API. 8260 read-only 0x00ff00fe BANKBUSY BANKBUSY [16:16] PUMPRDY PUMPRDY [15:15] BANKRDY BANKRDY [0:0] FPAC1 Internal. Only to be used through TI provided API. 8264 read-write 0x02082081 PSLEEPTDIS PSLEEPTDIS [27:16] PUMPRESET_PW PUMPRESET_PW [15:4] PUMPPWR PUMPPWR [1:0] FPAC2 Internal. Only to be used through TI provided API. 8268 read-write 0x00000000 PAGP PAGP [15:0] FMAC Internal. Only to be used through TI provided API. 8272 read-write 0x00000000 BANK BANK [2:0] FMSTAT Internal. Only to be used through TI provided API. 8276 read-only 0x00000000 RVSUSP RVSUSP [17:17] RDVER RDVER [16:16] RVF RVF [15:15] ILA ILA [14:14] DBF DBF [13:13] PGV PGV [12:12] PCV PCV [11:11] EV EV [10:10] CV CV [9:9] BUSY BUSY [8:8] ERS ERS [7:7] PGM PGM [6:6] INVDAT INVDAT [5:5] CSTAT CSTAT [4:4] VOLSTAT VOLSTAT [3:3] ESUSP ESUSP [2:2] PSUSP PSUSP [1:1] SLOCK SLOCK [0:0] FLOCK Internal. Only to be used through TI provided API. 8292 read-write 0x000055aa ENCOM ENCOM [15:0] FVREADCT Internal. Only to be used through TI provided API. 8320 read-write 0x00000008 VREADCT VREADCT [3:0] FVHVCT1 Internal. Only to be used through TI provided API. 8324 read-write 0x00840088 TRIM13_E TRIM13_E [23:20] VHVCT_E VHVCT_E [19:16] TRIM13_PV TRIM13_PV [7:4] VHVCT_PV VHVCT_PV [3:0] FVHVCT2 Internal. Only to be used through TI provided API. 8328 read-write 0x00a20000 TRIM13_P TRIM13_P [23:20] VHVCT_P VHVCT_P [19:16] FVHVCT3 Internal. Only to be used through TI provided API. 8332 read-write 0x000f0000 WCT WCT [19:16] VHVCT_READ VHVCT_READ [3:0] FVNVCT Internal. Only to be used through TI provided API. 8336 read-write 0x00000800 VCG2P5CT VCG2P5CT [12:8] VIN_CT VIN_CT [4:0] FVSLP Internal. Only to be used through TI provided API. 8340 read-write 0x00008000 VSL_P VSL_P [15:12] FVWLCT Internal. Only to be used through TI provided API. 8344 read-write 0x00000008 VWLCT_P VWLCT_P [4:0] FEFUSECTL Internal. Only to be used through TI provided API. 8348 read-write 0x0701010a CHAIN_SEL CHAIN_SEL [26:24] WRITE_EN WRITE_EN [17:17] BP_SEL BP_SEL [16:16] EF_CLRZ EF_CLRZ [8:8] EF_TEST EF_TEST [4:4] EFUSE_EN EFUSE_EN [3:0] FEFUSESTAT Internal. Only to be used through TI provided API. 8352 read-write 0x00000000 SHIFT_DONE SHIFT_DONE [0:0] oneToClear FEFUSEDATA Internal. Only to be used through TI provided API. 8356 read-write 0x00000000 FEFUSEDATA FEFUSEDATA [31:0] FSEQPMP Internal. Only to be used through TI provided API. 8360 read-write 0x85080000 TRIM_3P4 TRIM_3P4 [27:24] TRIM_1P7 TRIM_1P7 [21:20] TRIM_0P8 TRIM_0P8 [19:16] VIN_AT_X VIN_AT_X [14:12] VIN_BY_PASS VIN_BY_PASS [8:8] FBSTROBES Internal. Only to be used through TI provided API. 8448 read-write 0x00000104 ECBIT ECBIT [24:24] RWAIT2_FLCLK RWAIT2_FLCLK [18:18] RWAIT_FLCLK RWAIT_FLCLK [17:17] FLCLKEN FLCLKEN [16:16] CTRLENZ CTRLENZ [8:8] NOCOLRED NOCOLRED [6:6] PRECOL PRECOL [5:5] TI_OTP TI_OTP [4:4] OTP OTP [3:3] TEZ TEZ [2:2] FPSTROBES Internal. Only to be used through TI provided API. 8452 read-write 0x00000103 EXECUTEZ EXECUTEZ [8:8] V3PWRDNZ V3PWRDNZ [1:1] V5PWRDNZ V5PWRDNZ [0:0] FBMODE Internal. Only to be used through TI provided API. 8456 read-write 0x00000000 MODE MODE [2:0] FTCR Internal. Only to be used through TI provided API. 8460 read-write 0x00000000 TCR TCR [6:0] FADDR Internal. Only to be used through TI provided API. 8464 read-write 0x00000000 FADDR FADDR [31:0] FTCTL Internal. Only to be used through TI provided API. 8476 read-write 0x00000000 WDATA_BLK_CLR WDATA_BLK_CLR [16:16] TEST_EN TEST_EN [1:1] FWPWRITE0 Internal. Only to be used through TI provided API. 8480 read-write 0xffffffff FWPWRITE0 FWPWRITE0 [31:0] FWPWRITE1 Internal. Only to be used through TI provided API. 8484 read-write 0xffffffff FWPWRITE1 FWPWRITE1 [31:0] FWPWRITE2 Internal. Only to be used through TI provided API. 8488 read-write 0xffffffff FWPWRITE2 FWPWRITE2 [31:0] FWPWRITE3 Internal. Only to be used through TI provided API. 8492 read-write 0xffffffff FWPWRITE3 FWPWRITE3 [31:0] FWPWRITE4 Internal. Only to be used through TI provided API. 8496 read-write 0xffffffff FWPWRITE4 FWPWRITE4 [31:0] FWPWRITE5 Internal. Only to be used through TI provided API. 8500 read-write 0xffffffff FWPWRITE5 FWPWRITE5 [31:0] FWPWRITE6 Internal. Only to be used through TI provided API. 8504 read-write 0xffffffff FWPWRITE6 FWPWRITE6 [31:0] FWPWRITE7 Internal. Only to be used through TI provided API. 8508 read-write 0xffffffff FWPWRITE7 FWPWRITE7 [31:0] FWPWRITE_ECC Internal. Only to be used through TI provided API. 8512 read-write 0xffffffff ECCBYTES07_00 ECCBYTES07_00 [31:24] ECCBYTES15_08 ECCBYTES15_08 [23:16] ECCBYTES23_16 ECCBYTES23_16 [15:8] ECCBYTES31_24 ECCBYTES31_24 [7:0] FSWSTAT Internal. Only to be used through TI provided API. 8516 read-only 0x00000001 SAFELV SAFELV [0:0] FSM_GLBCTL Internal. Only to be used through TI provided API. 8704 read-only 0x00000001 CLKSEL CLKSEL [0:0] FSM_STATE Internal. Only to be used through TI provided API. 8708 read-only 0x00000c00 CTRLENZ CTRLENZ [11:11] EXECUTEZ EXECUTEZ [10:10] FSM_ACT FSM_ACT [8:8] TIOTP_ACT TIOTP_ACT [7:7] OTP_ACT OTP_ACT [6:6] FSM_STAT Internal. Only to be used through TI provided API. 8712 read-only 0x00000004 NON_OP NON_OP [2:2] OVR_PUL_CNT OVR_PUL_CNT [1:1] INV_DAT INV_DAT [0:0] FSM_CMD Internal. Only to be used through TI provided API. 8716 read-write 0x00000000 FSMCMD FSMCMD [5:0] FSM_PE_OSU Internal. Only to be used through TI provided API. 8720 read-write 0x00000000 PGM_OSU PGM_OSU [15:8] ERA_OSU ERA_OSU [7:0] FSM_VSTAT Internal. Only to be used through TI provided API. 8724 read-write 0x00003000 VSTAT_CNT VSTAT_CNT [15:12] FSM_PE_VSU Internal. Only to be used through TI provided API. 8728 read-write 0x00000000 PGM_VSU PGM_VSU [15:8] ERA_VSU ERA_VSU [7:0] FSM_CMP_VSU Internal. Only to be used through TI provided API. 8732 read-write 0x00000000 ADD_EXZ ADD_EXZ [15:12] FSM_EX_VAL Internal. Only to be used through TI provided API. 8736 read-write 0x00000301 REP_VSU REP_VSU [15:8] EXE_VALD EXE_VALD [7:0] FSM_RD_H Internal. Only to be used through TI provided API. 8740 read-write 0x0000005a RD_H RD_H [7:0] FSM_P_OH Internal. Only to be used through TI provided API. 8744 read-write 0x00000100 PGM_OH PGM_OH [15:8] FSM_ERA_OH Internal. Only to be used through TI provided API. 8748 read-write 0x00000001 ERA_OH ERA_OH [15:0] FSM_SAV_PPUL Internal. Only to be used through TI provided API. 8752 read-only 0x00000000 SAV_P_PUL SAV_P_PUL [11:0] FSM_PE_VH Internal. Only to be used through TI provided API. 8756 read-write 0x00000100 PGM_VH PGM_VH [15:8] FSM_PRG_PW Internal. Only to be used through TI provided API. 8768 read-write 0x00000000 PROG_PUL_WIDTH PROG_PUL_WIDTH [15:0] FSM_ERA_PW Internal. Only to be used through TI provided API. 8772 read-write 0x00000000 FSM_ERA_PW FSM_ERA_PW [31:0] FSM_SAV_ERA_PUL Internal. Only to be used through TI provided API. 8788 read-only 0x00000000 SAV_ERA_PUL SAV_ERA_PUL [11:0] FSM_TIMER Internal. Only to be used through TI provided API. 8792 read-only 0x00000000 FSM_TIMER FSM_TIMER [31:0] FSM_MODE Internal. Only to be used through TI provided API. 8796 read-only 0x00000000 RDV_SUBMODE RDV_SUBMODE [19:18] PGM_SUBMODE PGM_SUBMODE [17:16] ERA_SUBMODE ERA_SUBMODE [15:14] SUBMODE SUBMODE [13:12] SAV_PGM_CMD SAV_PGM_CMD [11:9] SAV_ERA_MODE SAV_ERA_MODE [8:6] MODE MODE [5:3] CMD CMD [2:0] FSM_PGM Internal. Only to be used through TI provided API. 8800 read-only 0x00000000 PGM_BANK PGM_BANK [25:23] PGM_ADDR PGM_ADDR [22:0] FSM_ERA Internal. Only to be used through TI provided API. 8804 read-only 0x00000000 ERA_BANK ERA_BANK [25:23] ERA_ADDR ERA_ADDR [22:0] FSM_PRG_PUL Internal. Only to be used through TI provided API. 8808 read-write 0x00040032 BEG_EC_LEVEL BEG_EC_LEVEL [19:16] MAX_PRG_PUL MAX_PRG_PUL [11:0] FSM_ERA_PUL Internal. Only to be used through TI provided API. 8812 read-write 0x00040bb8 MAX_EC_LEVEL MAX_EC_LEVEL [19:16] MAX_ERA_PUL MAX_ERA_PUL [11:0] FSM_STEP_SIZE Internal. Only to be used through TI provided API. 8816 read-write 0x00000000 EC_STEP_SIZE EC_STEP_SIZE [24:16] FSM_PUL_CNTR Internal. Only to be used through TI provided API. 8820 read-only 0x00000000 CUR_EC_LEVEL CUR_EC_LEVEL [24:16] PUL_CNTR PUL_CNTR [11:0] FSM_EC_STEP_HEIGHT Internal. Only to be used through TI provided API. 8824 read-write 0x00000000 EC_STEP_HEIGHT EC_STEP_HEIGHT [3:0] FSM_ST_MACHINE Internal. Only to be used through TI provided API. 8828 read-write 0x00800500 DO_PRECOND DO_PRECOND [23:23] FSM_INT_EN FSM_INT_EN [22:22] ALL_BANKS ALL_BANKS [21:21] CMPV_ALLOWED CMPV_ALLOWED [20:20] RANDOM RANDOM [19:19] RV_SEC_EN RV_SEC_EN [18:18] RV_RES RV_RES [17:17] RV_INT_EN RV_INT_EN [16:16] ONE_TIME_GOOD ONE_TIME_GOOD [14:14] DO_REDU_COL DO_REDU_COL [11:11] DBG_SHORT_ROW DBG_SHORT_ROW [10:7] PGM_SEC_COF_EN PGM_SEC_COF_EN [5:5] PREC_STOP_EN PREC_STOP_EN [4:4] DIS_TST_EN DIS_TST_EN [3:3] CMD_EN CMD_EN [2:2] INV_DATA INV_DATA [1:1] OVERRIDE OVERRIDE [0:0] FSM_FLES Internal. Only to be used through TI provided API. 8832 read-write 0x00000000 BLK_TIOTP BLK_TIOTP [11:8] BLK_OTP BLK_OTP [7:0] FSM_WR_ENA Internal. Only to be used through TI provided API. 8840 read-write 0x00000002 WR_ENA WR_ENA [2:0] FSM_ACC_PP Internal. Only to be used through TI provided API. 8844 read-only 0x00000000 FSM_ACC_PP FSM_ACC_PP [31:0] FSM_ACC_EP Internal. Only to be used through TI provided API. 8848 read-only 0x00000000 ACC_EP ACC_EP [15:0] FSM_ADDR Internal. Only to be used through TI provided API. 8864 read-only 0x00000000 BANK BANK [30:28] CUR_ADDR CUR_ADDR [27:0] FSM_SECTOR Internal. Only to be used through TI provided API. 8868 read-write 0xffff0000 SECT_ERASED SECT_ERASED [31:16] FSM_SECTOR_EXTENSION FSM_SECTOR_EXTENSION [15:8] SECTOR SECTOR [7:4] SEC_OUT SEC_OUT [3:0] FMC_REV_ID Internal. Only to be used through TI provided API. 8872 read-only 0x00000000 MOD_VERSION MOD_VERSION [31:12] CONFIG_CRC CONFIG_CRC [11:0] FSM_ERR_ADDR Internal. Only to be used through TI provided API. 8876 read-only 0x00000000 FSM_ERR_ADDR FSM_ERR_ADDR [31:8] FSM_ERR_BANK FSM_ERR_BANK [3:0] FSM_PGM_MAXPUL Internal. Only to be used through TI provided API. 8880 read-only 0x00000000 FSM_PGM_MAXPUL FSM_PGM_MAXPUL [11:0] FSM_EXECUTE Internal. Only to be used through TI provided API. 8884 read-write 0x000a000a SUSPEND_NOW SUSPEND_NOW [19:16] FSMEXECUTE FSMEXECUTE [4:0] FSM_SECTOR1 Internal. Only to be used through TI provided API. 8896 read-write 0xffffffff FSM_SECTOR1 FSM_SECTOR1 [31:0] FSM_SECTOR2 Internal. Only to be used through TI provided API. 8900 read-write 0x00000000 FSM_SECTOR2 FSM_SECTOR2 [31:0] FSM_BSLE0 Internal. Only to be used through TI provided API. 8928 read-write 0x00000000 FSM_BSLE0 FSM_BSLE0 [31:0] FSM_BSLE1 Internal. Only to be used through TI provided API. 8932 read-write 0x00000000 FSM_BSL1 FSM_BSL1 [31:0] FSM_BSLP0 Internal. Only to be used through TI provided API. 8944 read-write 0x00000000 FSM_BSLP0 FSM_BSLP0 [31:0] FSM_BSLP1 Internal. Only to be used through TI provided API. 8948 read-write 0x00000000 FSM_BSL1 FSM_BSL1 [31:0] FCFG_BANK Internal. Only to be used through TI provided API. 9216 read-only 0x00000401 EE_BANK_WIDTH EE_BANK_WIDTH [31:20] EE_NUM_BANK EE_NUM_BANK [19:16] MAIN_BANK_WIDTH MAIN_BANK_WIDTH [15:4] MAIN_NUM_BANK MAIN_NUM_BANK [3:0] FCFG_WRAPPER Internal. Only to be used through TI provided API. 9220 read-only 0x50009007 FAMILY_TYPE FAMILY_TYPE [31:24] MEM_MAP MEM_MAP [20:20] CPU2 CPU2 [19:16] EE_IN_MAIN EE_IN_MAIN [15:12] ROM ROM [11:11] IFLUSH IFLUSH [10:10] SIL3 SIL3 [9:9] ECCA ECCA [8:8] AUTO_SUSP AUTO_SUSP [7:6] UERR UERR [5:4] CPU_TYPE1 CPU_TYPE1 [3:0] FCFG_BNK_TYPE Internal. Only to be used through TI provided API. 9224 read-only 0x00000003 B7_TYPE B7_TYPE [31:28] B6_TYPE B6_TYPE [27:24] B5_TYPE B5_TYPE [23:20] B4_TYPE B4_TYPE [19:16] B3_TYPE B3_TYPE [15:12] B2_TYPE B2_TYPE [11:8] B1_TYPE B1_TYPE [7:4] B0_TYPE B0_TYPE [3:0] FCFG_B0_START Internal. Only to be used through TI provided API. 9232 read-only 0x02000000 B0_MAX_SECTOR B0_MAX_SECTOR [31:28] B0_MUX_FACTOR B0_MUX_FACTOR [27:24] B0_START_ADDR B0_START_ADDR [23:0] FCFG_B1_START Internal. Only to be used through TI provided API. 9236 read-only 0x00000000 B1_MAX_SECTOR B1_MAX_SECTOR [31:28] B1_MUX_FACTOR B1_MUX_FACTOR [27:24] B1_START_ADDR B1_START_ADDR [23:0] FCFG_B2_START Internal. Only to be used through TI provided API. 9240 read-only 0x00000000 B2_MAX_SECTOR B2_MAX_SECTOR [31:28] B2_MUX_FACTOR B2_MUX_FACTOR [27:24] B2_START_ADDR B2_START_ADDR [23:0] FCFG_B3_START Internal. Only to be used through TI provided API. 9244 read-only 0x00000000 B3_MAX_SECTOR B3_MAX_SECTOR [31:28] B3_MUX_FACTOR B3_MUX_FACTOR [27:24] B3_START_ADDR B3_START_ADDR [23:0] FCFG_B4_START Internal. Only to be used through TI provided API. 9248 read-only 0x00000000 B4_MAX_SECTOR B4_MAX_SECTOR [31:28] B4_MUX_FACTOR B4_MUX_FACTOR [27:24] B4_START_ADDR B4_START_ADDR [23:0] FCFG_B5_START Internal. Only to be used through TI provided API. 9252 read-only 0x00000000 B5_MAX_SECTOR B5_MAX_SECTOR [31:28] B5_MUX_FACTOR B5_MUX_FACTOR [27:24] B5_START_ADDR B5_START_ADDR [23:0] FCFG_B6_START Internal. Only to be used through TI provided API. 9256 read-only 0x00000000 B6_MAX_SECTOR B6_MAX_SECTOR [31:28] B6_MUX_FACTOR B6_MUX_FACTOR [27:24] B6_START_ADDR B6_START_ADDR [23:0] FCFG_B7_START Internal. Only to be used through TI provided API. 9260 read-only 0x00000000 B7_MAX_SECTOR B7_MAX_SECTOR [31:28] B7_MUX_FACTOR B7_MUX_FACTOR [27:24] B7_START_ADDR B7_START_ADDR [23:0] FCFG_B0_SSIZE0 Internal. Only to be used through TI provided API. 9264 read-only 0x00200004 B0_NUM_SECTORS B0_NUM_SECTORS [27:16] B0_SECT_SIZE B0_SECT_SIZE [3:0] GPIO MCU GPIO - I/F for controlling and reading IO status and IO event status 0x40022000 0 0x400 registers DOUT3_0 Data Out 0 to 3 Alias register for byte access to each bit in DOUT31_0 0 read-write 0x00000000 DIO3 DIO3 [24:24] DIO2 DIO2 [16:16] DIO1 DIO1 [8:8] DIO0 DIO0 [0:0] DOUT7_4 Data Out 4 to 7 Alias register for byte access to each bit in DOUT31_0 4 read-write 0x00000000 DIO7 DIO7 [24:24] DIO6 DIO6 [16:16] DIO5 DIO5 [8:8] DIO4 DIO4 [0:0] DOUT11_8 Data Out 8 to 11 Alias register for byte access to each bit in DOUT31_0 8 read-write 0x00000000 DIO11 DIO11 [24:24] DIO10 DIO10 [16:16] DIO9 DIO9 [8:8] DIO8 DIO8 [0:0] DOUT15_12 Data Out 12 to 15 Alias register for byte access to each bit in DOUT31_0 12 read-write 0x00000000 DIO15 DIO15 [24:24] DIO14 DIO14 [16:16] DIO13 DIO13 [8:8] DIO12 DIO12 [0:0] DOUT19_16 Data Out 16 to 19 Alias register for byte access to each bit in DOUT31_0 16 read-write 0x00000000 DIO19 DIO19 [24:24] DIO18 DIO18 [16:16] DIO17 DIO17 [8:8] DIO16 DIO16 [0:0] DOUT23_20 Data Out 20 to 23 Alias register for byte access to each bit in DOUT31_0 20 read-write 0x00000000 DIO23 DIO23 [24:24] DIO22 DIO22 [16:16] DIO21 DIO21 [8:8] DIO20 DIO20 [0:0] DOUT27_24 Data Out 24 to 27 Alias register for byte access to each bit in DOUT31_0 24 read-write 0x00000000 DIO27 DIO27 [24:24] DIO26 DIO26 [16:16] DIO25 DIO25 [8:8] DIO24 DIO24 [0:0] DOUT31_28 Data Out 28 to 31 Alias register for byte access to each bit in DOUT31_0 28 read-write 0x00000000 DIO31 DIO31 [24:24] DIO30 DIO30 [16:16] DIO29 DIO29 [8:8] DIO28 DIO28 [0:0] DOUT31_0 Data Output for DIO 0 to 31 128 read-write 0x00000000 DIO31 DIO31 [31:31] DIO30 DIO30 [30:30] DIO29 DIO29 [29:29] DIO28 DIO28 [28:28] DIO27 DIO27 [27:27] DIO26 DIO26 [26:26] DIO25 DIO25 [25:25] DIO24 DIO24 [24:24] DIO23 DIO23 [23:23] DIO22 DIO22 [22:22] DIO21 DIO21 [21:21] DIO20 DIO20 [20:20] DIO19 DIO19 [19:19] DIO18 DIO18 [18:18] DIO17 DIO17 [17:17] DIO16 DIO16 [16:16] DIO15 DIO15 [15:15] DIO14 DIO14 [14:14] DIO13 DIO13 [13:13] DIO12 DIO12 [12:12] DIO11 DIO11 [11:11] DIO10 DIO10 [10:10] DIO9 DIO9 [9:9] DIO8 DIO8 [8:8] DIO7 DIO7 [7:7] DIO6 DIO6 [6:6] DIO5 DIO5 [5:5] DIO4 DIO4 [4:4] DIO3 DIO3 [3:3] DIO2 DIO2 [2:2] DIO1 DIO1 [1:1] DIO0 DIO0 [0:0] DOUTSET31_0 Data Out Set Writing 1 to a bit position sets the corresponding bit in the DOUT31_0 register 144 write-only 0x00000000 DIO31 DIO31 [31:31] oneToSet DIO30 DIO30 [30:30] oneToSet DIO29 DIO29 [29:29] oneToSet DIO28 DIO28 [28:28] oneToSet DIO27 DIO27 [27:27] oneToSet DIO26 DIO26 [26:26] oneToSet DIO25 DIO25 [25:25] oneToSet DIO24 DIO24 [24:24] oneToSet DIO23 DIO23 [23:23] oneToSet DIO22 DIO22 [22:22] oneToSet DIO21 DIO21 [21:21] oneToSet DIO20 DIO20 [20:20] oneToSet DIO19 DIO19 [19:19] oneToSet DIO18 DIO18 [18:18] oneToSet DIO17 DIO17 [17:17] oneToSet DIO16 DIO16 [16:16] oneToSet DIO15 DIO15 [15:15] oneToSet DIO14 DIO14 [14:14] oneToSet DIO13 DIO13 [13:13] oneToSet DIO12 DIO12 [12:12] oneToSet DIO11 DIO11 [11:11] oneToSet DIO10 DIO10 [10:10] oneToSet DIO9 DIO9 [9:9] oneToSet DIO8 DIO8 [8:8] oneToSet DIO7 DIO7 [7:7] oneToSet DIO6 DIO6 [6:6] oneToSet DIO5 DIO5 [5:5] oneToSet DIO4 DIO4 [4:4] oneToSet DIO3 DIO3 [3:3] oneToSet DIO2 DIO2 [2:2] oneToSet DIO1 DIO1 [1:1] oneToSet DIO0 DIO0 [0:0] oneToSet DOUTCLR31_0 Data Out Clear Writing 1 to a bit position clears the corresponding bit in the DOUT31_0 register 160 write-only 0x00000000 DIO31 DIO31 [31:31] oneToClear DIO30 DIO30 [30:30] oneToClear DIO29 DIO29 [29:29] oneToClear DIO28 DIO28 [28:28] oneToClear DIO27 DIO27 [27:27] oneToClear DIO26 DIO26 [26:26] oneToClear DIO25 DIO25 [25:25] oneToClear DIO24 DIO24 [24:24] oneToClear DIO23 DIO23 [23:23] oneToClear DIO22 DIO22 [22:22] oneToClear DIO21 DIO21 [21:21] oneToClear DIO20 DIO20 [20:20] oneToClear DIO19 DIO19 [19:19] oneToClear DIO18 DIO18 [18:18] oneToClear DIO17 DIO17 [17:17] oneToClear DIO16 DIO16 [16:16] oneToClear DIO15 DIO15 [15:15] oneToClear DIO14 DIO14 [14:14] oneToClear DIO13 DIO13 [13:13] oneToClear DIO12 DIO12 [12:12] oneToClear DIO11 DIO11 [11:11] oneToClear DIO10 DIO10 [10:10] oneToClear DIO9 DIO9 [9:9] oneToClear DIO8 DIO8 [8:8] oneToClear DIO7 DIO7 [7:7] oneToClear DIO6 DIO6 [6:6] oneToClear DIO5 DIO5 [5:5] oneToClear DIO4 DIO4 [4:4] oneToClear DIO3 DIO3 [3:3] oneToClear DIO2 DIO2 [2:2] oneToClear DIO1 DIO1 [1:1] oneToClear DIO0 DIO0 [0:0] oneToClear DOUTTGL31_0 Data Out Toggle Writing 1 to a bit position will invert the corresponding DIO output. 176 read-write 0x00000000 DIO31 DIO31 [31:31] DIO30 DIO30 [30:30] DIO29 DIO29 [29:29] DIO28 DIO28 [28:28] DIO27 DIO27 [27:27] DIO26 DIO26 [26:26] DIO25 DIO25 [25:25] DIO24 DIO24 [24:24] DIO23 DIO23 [23:23] DIO22 DIO22 [22:22] DIO21 DIO21 [21:21] DIO20 DIO20 [20:20] DIO19 DIO19 [19:19] DIO18 DIO18 [18:18] DIO17 DIO17 [17:17] DIO16 DIO16 [16:16] DIO15 DIO15 [15:15] DIO14 DIO14 [14:14] DIO13 DIO13 [13:13] DIO12 DIO12 [12:12] DIO11 DIO11 [11:11] DIO10 DIO10 [10:10] DIO9 DIO9 [9:9] DIO8 DIO8 [8:8] DIO7 DIO7 [7:7] DIO6 DIO6 [6:6] DIO5 DIO5 [5:5] DIO4 DIO4 [4:4] DIO3 DIO3 [3:3] DIO2 DIO2 [2:2] DIO1 DIO1 [1:1] DIO0 DIO0 [0:0] DIN31_0 Data Input from DIO 0 to 31 192 read-only 0x00000000 DIO31 DIO31 [31:31] DIO30 DIO30 [30:30] DIO29 DIO29 [29:29] DIO28 DIO28 [28:28] DIO27 DIO27 [27:27] DIO26 DIO26 [26:26] DIO25 DIO25 [25:25] DIO24 DIO24 [24:24] DIO23 DIO23 [23:23] DIO22 DIO22 [22:22] DIO21 DIO21 [21:21] DIO20 DIO20 [20:20] DIO19 DIO19 [19:19] DIO18 DIO18 [18:18] DIO17 DIO17 [17:17] DIO16 DIO16 [16:16] DIO15 DIO15 [15:15] DIO14 DIO14 [14:14] DIO13 DIO13 [13:13] DIO12 DIO12 [12:12] DIO11 DIO11 [11:11] DIO10 DIO10 [10:10] DIO9 DIO9 [9:9] DIO8 DIO8 [8:8] DIO7 DIO7 [7:7] DIO6 DIO6 [6:6] DIO5 DIO5 [5:5] DIO4 DIO4 [4:4] DIO3 DIO3 [3:3] DIO2 DIO2 [2:2] DIO1 DIO1 [1:1] DIO0 DIO0 [0:0] DOE31_0 Data Output Enable for DIO 0 to 31 208 read-write 0x00000000 DIO31 DIO31 [31:31] DIO30 DIO30 [30:30] DIO29 DIO29 [29:29] DIO28 DIO28 [28:28] DIO27 DIO27 [27:27] DIO26 DIO26 [26:26] DIO25 DIO25 [25:25] DIO24 DIO24 [24:24] DIO23 DIO23 [23:23] DIO22 DIO22 [22:22] DIO21 DIO21 [21:21] DIO20 DIO20 [20:20] DIO19 DIO19 [19:19] DIO18 DIO18 [18:18] DIO17 DIO17 [17:17] DIO16 DIO16 [16:16] DIO15 DIO15 [15:15] DIO14 DIO14 [14:14] DIO13 DIO13 [13:13] DIO12 DIO12 [12:12] DIO11 DIO11 [11:11] DIO10 DIO10 [10:10] DIO9 DIO9 [9:9] DIO8 DIO8 [8:8] DIO7 DIO7 [7:7] DIO6 DIO6 [6:6] DIO5 DIO5 [5:5] DIO4 DIO4 [4:4] DIO3 DIO3 [3:3] DIO2 DIO2 [2:2] DIO1 DIO1 [1:1] DIO0 DIO0 [0:0] EVFLAGS31_0 Event Register for DIO 0 to 31 Reading this registers will return 1 for triggered event and 0 for non-triggered events. Writing a 1 to a bit field will clear the event. The configuration of events is done inside MCU IOC, e.g. events for DIO #0 is configured in IOC:IOCFG0.EDGE_DET and IOC:IOCFG0.EDGE_IRQ_EN. 224 read-write 0x00000000 DIO31 DIO31 [31:31] oneToClear DIO30 DIO30 [30:30] oneToClear DIO29 DIO29 [29:29] oneToClear DIO28 DIO28 [28:28] oneToClear DIO27 DIO27 [27:27] oneToClear DIO26 DIO26 [26:26] oneToClear DIO25 DIO25 [25:25] oneToClear DIO24 DIO24 [24:24] oneToClear DIO23 DIO23 [23:23] oneToClear DIO22 DIO22 [22:22] oneToClear DIO21 DIO21 [21:21] oneToClear DIO20 DIO20 [20:20] oneToClear DIO19 DIO19 [19:19] oneToClear DIO18 DIO18 [18:18] oneToClear DIO17 DIO17 [17:17] oneToClear DIO16 DIO16 [16:16] oneToClear DIO15 DIO15 [15:15] oneToClear DIO14 DIO14 [14:14] oneToClear DIO13 DIO13 [13:13] oneToClear DIO12 DIO12 [12:12] oneToClear DIO11 DIO11 [11:11] oneToClear DIO10 DIO10 [10:10] oneToClear DIO9 DIO9 [9:9] oneToClear DIO8 DIO8 [8:8] oneToClear DIO7 DIO7 [7:7] oneToClear DIO6 DIO6 [6:6] oneToClear DIO5 DIO5 [5:5] oneToClear DIO4 DIO4 [4:4] oneToClear DIO3 DIO3 [3:3] oneToClear DIO2 DIO2 [2:2] oneToClear DIO1 DIO1 [1:1] oneToClear DIO0 DIO0 [0:0] oneToClear GPT0 General Purpose Timer. 0x40010000 0 0x1000 registers CFG Configuration 0 read-write 0x00000000 CFG CFG [2:0] TAMR Timer A Mode 4 read-write 0x00000000 TCACT TCACT [15:13] TACINTD TACINTD [12:12] TAPLO TAPLO [11:11] TAMRSU TAMRSU [10:10] TAPWMIE TAPWMIE [9:9] TAILD TAILD [8:8] TASNAPS TASNAPS [7:7] TAWOT TAWOT [6:6] TAMIE TAMIE [5:5] TACDIR TACDIR [4:4] TAAMS TAAMS [3:3] TACM TACM [2:2] TAMR TAMR [1:0] TBMR Timer B Mode 8 read-write 0x00000000 TCACT TCACT [15:13] TBCINTD TBCINTD [12:12] TBPLO TBPLO [11:11] TBMRSU TBMRSU [10:10] TBPWMIE TBPWMIE [9:9] TBILD TBILD [8:8] TBSNAPS TBSNAPS [7:7] TBWOT TBWOT [6:6] TBMIE TBMIE [5:5] TBCDIR TBCDIR [4:4] TBAMS TBAMS [3:3] TBCM TBCM [2:2] TBMR TBMR [1:0] CTL Control 12 read-write 0x00000000 TBPWML TBPWML [14:14] TBEVENT TBEVENT [11:10] TBSTALL TBSTALL [9:9] TBEN TBEN [8:8] TAPWML TAPWML [6:6] RTCEN RTCEN [4:4] TAEVENT TAEVENT [3:2] TASTALL TASTALL [1:1] TAEN TAEN [0:0] SYNC Synch Register 16 read-write 0x00000000 SYNC3 SYNC3 [7:6] SYNC2 SYNC2 [5:4] SYNC1 SYNC1 [3:2] SYNC0 SYNC0 [1:0] IMR Interrupt Mask This register is used to enable the interrupts. Associated registers: RIS, MIS, ICLR 24 read-write 0x00000000 WUMIS WUMIS [16:16] DMABIM DMABIM [13:13] TBMIM TBMIM [11:11] CBEIM CBEIM [10:10] CBMIM CBMIM [9:9] TBTOIM TBTOIM [8:8] DMAAIM DMAAIM [5:5] TAMIM TAMIM [4:4] RTCIM RTCIM [3:3] CAEIM CAEIM [2:2] CAMIM CAMIM [1:1] TATOIM TATOIM [0:0] RIS Raw Interrupt Status Associated registers: IMR, MIS, ICLR 28 read-only 0x00000000 WURIS WURIS [16:16] DMABRIS DMABRIS [13:13] TBMRIS TBMRIS [11:11] CBERIS CBERIS [10:10] CBMRIS CBMRIS [9:9] TBTORIS TBTORIS [8:8] DMAARIS DMAARIS [5:5] TAMRIS TAMRIS [4:4] RTCRIS RTCRIS [3:3] CAERIS CAERIS [2:2] CAMRIS CAMRIS [1:1] TATORIS TATORIS [0:0] MIS Masked Interrupt Status Values are result of bitwise AND operation between RIS and IMR Assosciated clear register: ICLR 32 read-only 0x00000000 WUMIS WUMIS [16:16] DMABMIS DMABMIS [13:13] TBMMIS TBMMIS [11:11] CBEMIS CBEMIS [10:10] CBMMIS CBMMIS [9:9] TBTOMIS TBTOMIS [8:8] DMAAMIS DMAAMIS [5:5] TAMMIS TAMMIS [4:4] RTCMIS RTCMIS [3:3] CAEMIS CAEMIS [2:2] CAMMIS CAMMIS [1:1] TATOMIS TATOMIS [0:0] ICLR Interrupt Clear This register is used to clear status bits in the RIS and MIS registers 36 read-write 0x00000000 WUECINT WUECINT [16:16] oneToClear DMABINT DMABINT [13:13] oneToClear TBMCINT TBMCINT [11:11] oneToClear CBECINT CBECINT [10:10] oneToClear CBMCINT CBMCINT [9:9] oneToClear TBTOCINT TBTOCINT [8:8] oneToClear DMAAINT DMAAINT [5:5] oneToClear TAMCINT TAMCINT [4:4] oneToClear RTCCINT RTCCINT [3:3] oneToClear CAECINT CAECINT [2:2] oneToClear CAMCINT CAMCINT [1:1] oneToClear TATOCINT TATOCINT [0:0] oneToClear TAILR Timer A Interval Load Register 40 read-write 0xffffffff TAILR TAILR [31:0] TBILR Timer B Interval Load Register 44 read-write 0x0000ffff TBILR TBILR [31:0] TAMATCHR Timer A Match Register Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along with TAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in TAILR minus this value. Note that in edge-count mode, when executing an up-count, the value of TAPR and TAILR must be greater than the value of TAPMR and TAMATCHR. In PWM mode, this value along with TAILR, determines the duty cycle of the output PWM signal. When a 16/32-bit GPT is configured to one of the 32-bit modes, TAMATCHR appears as a 32-bit register. (The upper 16-bits correspond to the contents TBMATCHR). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of TBMATCHR. Note : This register is updated internally (takes effect) based on TAMR.TAMRSU 48 read-write 0xffffffff TAMATCHR TAMATCHR [31:0] TBMATCHR Timer B Match Register When a GPT is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of TAMATCHR. Reads from this register return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases. Note : This register is updated internally (takes effect) based on TBMR.TBMRSU 52 read-write 0x0000ffff TBMATCHR TBMATCHR [15:0] TAPR Timer A Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TAR and TAV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. 56 read-write 0x00000000 TAPSR TAPSR [7:0] TBPR Timer B Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TBR and TBV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. 60 read-write 0x00000000 TBPSR TBPSR [7:0] TAPMR Timer A Pre-scale Match This register allows software to extend the range of the TAMATCHR when used individually. 64 read-write 0x00000000 TAPSMR TAPSMR [7:0] TBPMR Timer B Pre-scale Match This register allows software to extend the range of the TBMATCHR when used individually. 68 read-write 0x00000000 TBPSMR TBPSMR [7:0] TAR Timer A Register 72 read-only 0xffffffff TAR TAR [31:0] TBR Timer B Register 76 read-only 0x0000ffff TBR TBR [31:0] TAV Timer A Value This register shows the current value of the free running 16-bit Timer A. In the 32-bit mode 80 read-write 0xffffffff TAV TAV [31:0] TBV Timer B Value This register shows the current value of the free running 16-bit Timer B. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count 1. 84 read-write 0x0000ffff TBV TBV [31:0] RTCPD RTC Pre-divide Value This register shows the current value of the RTC pre-divider in RTC mode. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count -1. 88 read-only 0x00007fff RTCPD RTCPD [15:0] TAPS Timer A Pre-scale Snap-shot Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer A pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled a read of a timer value will return the current count -1. 92 read-only 0x00000000 PSS PSS [7:0] TBPS Timer B Pre-scale Snap-shot Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer B pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled a read of a timer value will return the current count -1. 96 read-only 0x00000000 PSS PSS [7:0] TAPV Timer A Pre-scale Value This register shows the current value of the Timer A free running pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count 1. 100 read-only 0x00000000 PSV PSV [7:0] TBPV Timer B Pre-scale Value This register shows the current value of the Timer B free running pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count-1. 104 read-only 0x00000000 PSV PSV [7:0] DMAEV DMA Event This register allows software to enable/disable GPT DMA trigger events. 108 read-write 0x00000000 TBMDMAEN TBMDMAEN [11:11] CBEDMAEN CBEDMAEN [10:10] CBMDMAEN CBMDMAEN [9:9] TBTODMAEN TBTODMAEN [8:8] TAMDMAEN TAMDMAEN [4:4] RTCDMAEN RTCDMAEN [3:3] CAEDMAEN CAEDMAEN [2:2] CAMDMAEN CAMDMAEN [1:1] TATODMAEN TATODMAEN [0:0] VERSION Peripheral Version This register provides information regarding the GPT version 4016 read-only 0x00000400 VERSION VERSION [31:0] ANDCCP Combined CCP Output This register is used to logically AND CCP output pairs for each timer 4020 read-write 0x00000000 CCP_AND_EN CCP_AND_EN [0:0] GPT1 General Purpose Timer. 0x40011000 0 0x1000 registers CFG Configuration 0 read-write 0x00000000 CFG CFG [2:0] TAMR Timer A Mode 4 read-write 0x00000000 TCACT TCACT [15:13] TACINTD TACINTD [12:12] TAPLO TAPLO [11:11] TAMRSU TAMRSU [10:10] TAPWMIE TAPWMIE [9:9] TAILD TAILD [8:8] TASNAPS TASNAPS [7:7] TAWOT TAWOT [6:6] TAMIE TAMIE [5:5] TACDIR TACDIR [4:4] TAAMS TAAMS [3:3] TACM TACM [2:2] TAMR TAMR [1:0] TBMR Timer B Mode 8 read-write 0x00000000 TCACT TCACT [15:13] TBCINTD TBCINTD [12:12] TBPLO TBPLO [11:11] TBMRSU TBMRSU [10:10] TBPWMIE TBPWMIE [9:9] TBILD TBILD [8:8] TBSNAPS TBSNAPS [7:7] TBWOT TBWOT [6:6] TBMIE TBMIE [5:5] TBCDIR TBCDIR [4:4] TBAMS TBAMS [3:3] TBCM TBCM [2:2] TBMR TBMR [1:0] CTL Control 12 read-write 0x00000000 TBPWML TBPWML [14:14] TBEVENT TBEVENT [11:10] TBSTALL TBSTALL [9:9] TBEN TBEN [8:8] TAPWML TAPWML [6:6] RTCEN RTCEN [4:4] TAEVENT TAEVENT [3:2] TASTALL TASTALL [1:1] TAEN TAEN [0:0] SYNC Synch Register 16 read-write 0x00000000 SYNC3 SYNC3 [7:6] SYNC2 SYNC2 [5:4] SYNC1 SYNC1 [3:2] SYNC0 SYNC0 [1:0] IMR Interrupt Mask This register is used to enable the interrupts. Associated registers: RIS, MIS, ICLR 24 read-write 0x00000000 WUMIS WUMIS [16:16] DMABIM DMABIM [13:13] TBMIM TBMIM [11:11] CBEIM CBEIM [10:10] CBMIM CBMIM [9:9] TBTOIM TBTOIM [8:8] DMAAIM DMAAIM [5:5] TAMIM TAMIM [4:4] RTCIM RTCIM [3:3] CAEIM CAEIM [2:2] CAMIM CAMIM [1:1] TATOIM TATOIM [0:0] RIS Raw Interrupt Status Associated registers: IMR, MIS, ICLR 28 read-only 0x00000000 WURIS WURIS [16:16] DMABRIS DMABRIS [13:13] TBMRIS TBMRIS [11:11] CBERIS CBERIS [10:10] CBMRIS CBMRIS [9:9] TBTORIS TBTORIS [8:8] DMAARIS DMAARIS [5:5] TAMRIS TAMRIS [4:4] RTCRIS RTCRIS [3:3] CAERIS CAERIS [2:2] CAMRIS CAMRIS [1:1] TATORIS TATORIS [0:0] MIS Masked Interrupt Status Values are result of bitwise AND operation between RIS and IMR Assosciated clear register: ICLR 32 read-only 0x00000000 WUMIS WUMIS [16:16] DMABMIS DMABMIS [13:13] TBMMIS TBMMIS [11:11] CBEMIS CBEMIS [10:10] CBMMIS CBMMIS [9:9] TBTOMIS TBTOMIS [8:8] DMAAMIS DMAAMIS [5:5] TAMMIS TAMMIS [4:4] RTCMIS RTCMIS [3:3] CAEMIS CAEMIS [2:2] CAMMIS CAMMIS [1:1] TATOMIS TATOMIS [0:0] ICLR Interrupt Clear This register is used to clear status bits in the RIS and MIS registers 36 read-write 0x00000000 WUECINT WUECINT [16:16] oneToClear DMABINT DMABINT [13:13] oneToClear TBMCINT TBMCINT [11:11] oneToClear CBECINT CBECINT [10:10] oneToClear CBMCINT CBMCINT [9:9] oneToClear TBTOCINT TBTOCINT [8:8] oneToClear DMAAINT DMAAINT [5:5] oneToClear TAMCINT TAMCINT [4:4] oneToClear RTCCINT RTCCINT [3:3] oneToClear CAECINT CAECINT [2:2] oneToClear CAMCINT CAMCINT [1:1] oneToClear TATOCINT TATOCINT [0:0] oneToClear TAILR Timer A Interval Load Register 40 read-write 0xffffffff TAILR TAILR [31:0] TBILR Timer B Interval Load Register 44 read-write 0x0000ffff TBILR TBILR [31:0] TAMATCHR Timer A Match Register Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along with TAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in TAILR minus this value. Note that in edge-count mode, when executing an up-count, the value of TAPR and TAILR must be greater than the value of TAPMR and TAMATCHR. In PWM mode, this value along with TAILR, determines the duty cycle of the output PWM signal. When a 16/32-bit GPT is configured to one of the 32-bit modes, TAMATCHR appears as a 32-bit register. (The upper 16-bits correspond to the contents TBMATCHR). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of TBMATCHR. Note : This register is updated internally (takes effect) based on TAMR.TAMRSU 48 read-write 0xffffffff TAMATCHR TAMATCHR [31:0] TBMATCHR Timer B Match Register When a GPT is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of TAMATCHR. Reads from this register return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases. Note : This register is updated internally (takes effect) based on TBMR.TBMRSU 52 read-write 0x0000ffff TBMATCHR TBMATCHR [15:0] TAPR Timer A Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TAR and TAV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. 56 read-write 0x00000000 TAPSR TAPSR [7:0] TBPR Timer B Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TBR and TBV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. 60 read-write 0x00000000 TBPSR TBPSR [7:0] TAPMR Timer A Pre-scale Match This register allows software to extend the range of the TAMATCHR when used individually. 64 read-write 0x00000000 TAPSMR TAPSMR [7:0] TBPMR Timer B Pre-scale Match This register allows software to extend the range of the TBMATCHR when used individually. 68 read-write 0x00000000 TBPSMR TBPSMR [7:0] TAR Timer A Register 72 read-only 0xffffffff TAR TAR [31:0] TBR Timer B Register 76 read-only 0x0000ffff TBR TBR [31:0] TAV Timer A Value This register shows the current value of the free running 16-bit Timer A. In the 32-bit mode 80 read-write 0xffffffff TAV TAV [31:0] TBV Timer B Value This register shows the current value of the free running 16-bit Timer B. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count 1. 84 read-write 0x0000ffff TBV TBV [31:0] RTCPD RTC Pre-divide Value This register shows the current value of the RTC pre-divider in RTC mode. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count -1. 88 read-only 0x00007fff RTCPD RTCPD [15:0] TAPS Timer A Pre-scale Snap-shot Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer A pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled a read of a timer value will return the current count -1. 92 read-only 0x00000000 PSS PSS [7:0] TBPS Timer B Pre-scale Snap-shot Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer B pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled a read of a timer value will return the current count -1. 96 read-only 0x00000000 PSS PSS [7:0] TAPV Timer A Pre-scale Value This register shows the current value of the Timer A free running pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count 1. 100 read-only 0x00000000 PSV PSV [7:0] TBPV Timer B Pre-scale Value This register shows the current value of the Timer B free running pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count-1. 104 read-only 0x00000000 PSV PSV [7:0] DMAEV DMA Event This register allows software to enable/disable GPT DMA trigger events. 108 read-write 0x00000000 TBMDMAEN TBMDMAEN [11:11] CBEDMAEN CBEDMAEN [10:10] CBMDMAEN CBMDMAEN [9:9] TBTODMAEN TBTODMAEN [8:8] TAMDMAEN TAMDMAEN [4:4] RTCDMAEN RTCDMAEN [3:3] CAEDMAEN CAEDMAEN [2:2] CAMDMAEN CAMDMAEN [1:1] TATODMAEN TATODMAEN [0:0] VERSION Peripheral Version This register provides information regarding the GPT version 4016 read-only 0x00000400 VERSION VERSION [31:0] ANDCCP Combined CCP Output This register is used to logically AND CCP output pairs for each timer 4020 read-write 0x00000000 CCP_AND_EN CCP_AND_EN [0:0] GPT2 General Purpose Timer. 0x40012000 0 0x1000 registers CFG Configuration 0 read-write 0x00000000 CFG CFG [2:0] TAMR Timer A Mode 4 read-write 0x00000000 TCACT TCACT [15:13] TACINTD TACINTD [12:12] TAPLO TAPLO [11:11] TAMRSU TAMRSU [10:10] TAPWMIE TAPWMIE [9:9] TAILD TAILD [8:8] TASNAPS TASNAPS [7:7] TAWOT TAWOT [6:6] TAMIE TAMIE [5:5] TACDIR TACDIR [4:4] TAAMS TAAMS [3:3] TACM TACM [2:2] TAMR TAMR [1:0] TBMR Timer B Mode 8 read-write 0x00000000 TCACT TCACT [15:13] TBCINTD TBCINTD [12:12] TBPLO TBPLO [11:11] TBMRSU TBMRSU [10:10] TBPWMIE TBPWMIE [9:9] TBILD TBILD [8:8] TBSNAPS TBSNAPS [7:7] TBWOT TBWOT [6:6] TBMIE TBMIE [5:5] TBCDIR TBCDIR [4:4] TBAMS TBAMS [3:3] TBCM TBCM [2:2] TBMR TBMR [1:0] CTL Control 12 read-write 0x00000000 TBPWML TBPWML [14:14] TBEVENT TBEVENT [11:10] TBSTALL TBSTALL [9:9] TBEN TBEN [8:8] TAPWML TAPWML [6:6] RTCEN RTCEN [4:4] TAEVENT TAEVENT [3:2] TASTALL TASTALL [1:1] TAEN TAEN [0:0] SYNC Synch Register 16 read-write 0x00000000 SYNC3 SYNC3 [7:6] SYNC2 SYNC2 [5:4] SYNC1 SYNC1 [3:2] SYNC0 SYNC0 [1:0] IMR Interrupt Mask This register is used to enable the interrupts. Associated registers: RIS, MIS, ICLR 24 read-write 0x00000000 WUMIS WUMIS [16:16] DMABIM DMABIM [13:13] TBMIM TBMIM [11:11] CBEIM CBEIM [10:10] CBMIM CBMIM [9:9] TBTOIM TBTOIM [8:8] DMAAIM DMAAIM [5:5] TAMIM TAMIM [4:4] RTCIM RTCIM [3:3] CAEIM CAEIM [2:2] CAMIM CAMIM [1:1] TATOIM TATOIM [0:0] RIS Raw Interrupt Status Associated registers: IMR, MIS, ICLR 28 read-only 0x00000000 WURIS WURIS [16:16] DMABRIS DMABRIS [13:13] TBMRIS TBMRIS [11:11] CBERIS CBERIS [10:10] CBMRIS CBMRIS [9:9] TBTORIS TBTORIS [8:8] DMAARIS DMAARIS [5:5] TAMRIS TAMRIS [4:4] RTCRIS RTCRIS [3:3] CAERIS CAERIS [2:2] CAMRIS CAMRIS [1:1] TATORIS TATORIS [0:0] MIS Masked Interrupt Status Values are result of bitwise AND operation between RIS and IMR Assosciated clear register: ICLR 32 read-only 0x00000000 WUMIS WUMIS [16:16] DMABMIS DMABMIS [13:13] TBMMIS TBMMIS [11:11] CBEMIS CBEMIS [10:10] CBMMIS CBMMIS [9:9] TBTOMIS TBTOMIS [8:8] DMAAMIS DMAAMIS [5:5] TAMMIS TAMMIS [4:4] RTCMIS RTCMIS [3:3] CAEMIS CAEMIS [2:2] CAMMIS CAMMIS [1:1] TATOMIS TATOMIS [0:0] ICLR Interrupt Clear This register is used to clear status bits in the RIS and MIS registers 36 read-write 0x00000000 WUECINT WUECINT [16:16] oneToClear DMABINT DMABINT [13:13] oneToClear TBMCINT TBMCINT [11:11] oneToClear CBECINT CBECINT [10:10] oneToClear CBMCINT CBMCINT [9:9] oneToClear TBTOCINT TBTOCINT [8:8] oneToClear DMAAINT DMAAINT [5:5] oneToClear TAMCINT TAMCINT [4:4] oneToClear RTCCINT RTCCINT [3:3] oneToClear CAECINT CAECINT [2:2] oneToClear CAMCINT CAMCINT [1:1] oneToClear TATOCINT TATOCINT [0:0] oneToClear TAILR Timer A Interval Load Register 40 read-write 0xffffffff TAILR TAILR [31:0] TBILR Timer B Interval Load Register 44 read-write 0x0000ffff TBILR TBILR [31:0] TAMATCHR Timer A Match Register Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along with TAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in TAILR minus this value. Note that in edge-count mode, when executing an up-count, the value of TAPR and TAILR must be greater than the value of TAPMR and TAMATCHR. In PWM mode, this value along with TAILR, determines the duty cycle of the output PWM signal. When a 16/32-bit GPT is configured to one of the 32-bit modes, TAMATCHR appears as a 32-bit register. (The upper 16-bits correspond to the contents TBMATCHR). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of TBMATCHR. Note : This register is updated internally (takes effect) based on TAMR.TAMRSU 48 read-write 0xffffffff TAMATCHR TAMATCHR [31:0] TBMATCHR Timer B Match Register When a GPT is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of TAMATCHR. Reads from this register return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases. Note : This register is updated internally (takes effect) based on TBMR.TBMRSU 52 read-write 0x0000ffff TBMATCHR TBMATCHR [15:0] TAPR Timer A Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TAR and TAV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. 56 read-write 0x00000000 TAPSR TAPSR [7:0] TBPR Timer B Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TBR and TBV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. 60 read-write 0x00000000 TBPSR TBPSR [7:0] TAPMR Timer A Pre-scale Match This register allows software to extend the range of the TAMATCHR when used individually. 64 read-write 0x00000000 TAPSMR TAPSMR [7:0] TBPMR Timer B Pre-scale Match This register allows software to extend the range of the TBMATCHR when used individually. 68 read-write 0x00000000 TBPSMR TBPSMR [7:0] TAR Timer A Register 72 read-only 0xffffffff TAR TAR [31:0] TBR Timer B Register 76 read-only 0x0000ffff TBR TBR [31:0] TAV Timer A Value This register shows the current value of the free running 16-bit Timer A. In the 32-bit mode 80 read-write 0xffffffff TAV TAV [31:0] TBV Timer B Value This register shows the current value of the free running 16-bit Timer B. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count 1. 84 read-write 0x0000ffff TBV TBV [31:0] RTCPD RTC Pre-divide Value This register shows the current value of the RTC pre-divider in RTC mode. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count -1. 88 read-only 0x00007fff RTCPD RTCPD [15:0] TAPS Timer A Pre-scale Snap-shot Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer A pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled a read of a timer value will return the current count -1. 92 read-only 0x00000000 PSS PSS [7:0] TBPS Timer B Pre-scale Snap-shot Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer B pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled a read of a timer value will return the current count -1. 96 read-only 0x00000000 PSS PSS [7:0] TAPV Timer A Pre-scale Value This register shows the current value of the Timer A free running pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count 1. 100 read-only 0x00000000 PSV PSV [7:0] TBPV Timer B Pre-scale Value This register shows the current value of the Timer B free running pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count-1. 104 read-only 0x00000000 PSV PSV [7:0] DMAEV DMA Event This register allows software to enable/disable GPT DMA trigger events. 108 read-write 0x00000000 TBMDMAEN TBMDMAEN [11:11] CBEDMAEN CBEDMAEN [10:10] CBMDMAEN CBMDMAEN [9:9] TBTODMAEN TBTODMAEN [8:8] TAMDMAEN TAMDMAEN [4:4] RTCDMAEN RTCDMAEN [3:3] CAEDMAEN CAEDMAEN [2:2] CAMDMAEN CAMDMAEN [1:1] TATODMAEN TATODMAEN [0:0] VERSION Peripheral Version This register provides information regarding the GPT version 4016 read-only 0x00000400 VERSION VERSION [31:0] ANDCCP Combined CCP Output This register is used to logically AND CCP output pairs for each timer 4020 read-write 0x00000000 CCP_AND_EN CCP_AND_EN [0:0] GPT3 General Purpose Timer. 0x40013000 0 0x1000 registers CFG Configuration 0 read-write 0x00000000 CFG CFG [2:0] TAMR Timer A Mode 4 read-write 0x00000000 TCACT TCACT [15:13] TACINTD TACINTD [12:12] TAPLO TAPLO [11:11] TAMRSU TAMRSU [10:10] TAPWMIE TAPWMIE [9:9] TAILD TAILD [8:8] TASNAPS TASNAPS [7:7] TAWOT TAWOT [6:6] TAMIE TAMIE [5:5] TACDIR TACDIR [4:4] TAAMS TAAMS [3:3] TACM TACM [2:2] TAMR TAMR [1:0] TBMR Timer B Mode 8 read-write 0x00000000 TCACT TCACT [15:13] TBCINTD TBCINTD [12:12] TBPLO TBPLO [11:11] TBMRSU TBMRSU [10:10] TBPWMIE TBPWMIE [9:9] TBILD TBILD [8:8] TBSNAPS TBSNAPS [7:7] TBWOT TBWOT [6:6] TBMIE TBMIE [5:5] TBCDIR TBCDIR [4:4] TBAMS TBAMS [3:3] TBCM TBCM [2:2] TBMR TBMR [1:0] CTL Control 12 read-write 0x00000000 TBPWML TBPWML [14:14] TBEVENT TBEVENT [11:10] TBSTALL TBSTALL [9:9] TBEN TBEN [8:8] TAPWML TAPWML [6:6] RTCEN RTCEN [4:4] TAEVENT TAEVENT [3:2] TASTALL TASTALL [1:1] TAEN TAEN [0:0] SYNC Synch Register 16 read-write 0x00000000 SYNC3 SYNC3 [7:6] SYNC2 SYNC2 [5:4] SYNC1 SYNC1 [3:2] SYNC0 SYNC0 [1:0] IMR Interrupt Mask This register is used to enable the interrupts. Associated registers: RIS, MIS, ICLR 24 read-write 0x00000000 WUMIS WUMIS [16:16] DMABIM DMABIM [13:13] TBMIM TBMIM [11:11] CBEIM CBEIM [10:10] CBMIM CBMIM [9:9] TBTOIM TBTOIM [8:8] DMAAIM DMAAIM [5:5] TAMIM TAMIM [4:4] RTCIM RTCIM [3:3] CAEIM CAEIM [2:2] CAMIM CAMIM [1:1] TATOIM TATOIM [0:0] RIS Raw Interrupt Status Associated registers: IMR, MIS, ICLR 28 read-only 0x00000000 WURIS WURIS [16:16] DMABRIS DMABRIS [13:13] TBMRIS TBMRIS [11:11] CBERIS CBERIS [10:10] CBMRIS CBMRIS [9:9] TBTORIS TBTORIS [8:8] DMAARIS DMAARIS [5:5] TAMRIS TAMRIS [4:4] RTCRIS RTCRIS [3:3] CAERIS CAERIS [2:2] CAMRIS CAMRIS [1:1] TATORIS TATORIS [0:0] MIS Masked Interrupt Status Values are result of bitwise AND operation between RIS and IMR Assosciated clear register: ICLR 32 read-only 0x00000000 WUMIS WUMIS [16:16] DMABMIS DMABMIS [13:13] TBMMIS TBMMIS [11:11] CBEMIS CBEMIS [10:10] CBMMIS CBMMIS [9:9] TBTOMIS TBTOMIS [8:8] DMAAMIS DMAAMIS [5:5] TAMMIS TAMMIS [4:4] RTCMIS RTCMIS [3:3] CAEMIS CAEMIS [2:2] CAMMIS CAMMIS [1:1] TATOMIS TATOMIS [0:0] ICLR Interrupt Clear This register is used to clear status bits in the RIS and MIS registers 36 read-write 0x00000000 WUECINT WUECINT [16:16] oneToClear DMABINT DMABINT [13:13] oneToClear TBMCINT TBMCINT [11:11] oneToClear CBECINT CBECINT [10:10] oneToClear CBMCINT CBMCINT [9:9] oneToClear TBTOCINT TBTOCINT [8:8] oneToClear DMAAINT DMAAINT [5:5] oneToClear TAMCINT TAMCINT [4:4] oneToClear RTCCINT RTCCINT [3:3] oneToClear CAECINT CAECINT [2:2] oneToClear CAMCINT CAMCINT [1:1] oneToClear TATOCINT TATOCINT [0:0] oneToClear TAILR Timer A Interval Load Register 40 read-write 0xffffffff TAILR TAILR [31:0] TBILR Timer B Interval Load Register 44 read-write 0x0000ffff TBILR TBILR [31:0] TAMATCHR Timer A Match Register Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along with TAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in TAILR minus this value. Note that in edge-count mode, when executing an up-count, the value of TAPR and TAILR must be greater than the value of TAPMR and TAMATCHR. In PWM mode, this value along with TAILR, determines the duty cycle of the output PWM signal. When a 16/32-bit GPT is configured to one of the 32-bit modes, TAMATCHR appears as a 32-bit register. (The upper 16-bits correspond to the contents TBMATCHR). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of TBMATCHR. Note : This register is updated internally (takes effect) based on TAMR.TAMRSU 48 read-write 0xffffffff TAMATCHR TAMATCHR [31:0] TBMATCHR Timer B Match Register When a GPT is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of TAMATCHR. Reads from this register return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases. Note : This register is updated internally (takes effect) based on TBMR.TBMRSU 52 read-write 0x0000ffff TBMATCHR TBMATCHR [15:0] TAPR Timer A Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TAR and TAV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. 56 read-write 0x00000000 TAPSR TAPSR [7:0] TBPR Timer B Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TBR and TBV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. 60 read-write 0x00000000 TBPSR TBPSR [7:0] TAPMR Timer A Pre-scale Match This register allows software to extend the range of the TAMATCHR when used individually. 64 read-write 0x00000000 TAPSMR TAPSMR [7:0] TBPMR Timer B Pre-scale Match This register allows software to extend the range of the TBMATCHR when used individually. 68 read-write 0x00000000 TBPSMR TBPSMR [7:0] TAR Timer A Register 72 read-only 0xffffffff TAR TAR [31:0] TBR Timer B Register 76 read-only 0x0000ffff TBR TBR [31:0] TAV Timer A Value This register shows the current value of the free running 16-bit Timer A. In the 32-bit mode 80 read-write 0xffffffff TAV TAV [31:0] TBV Timer B Value This register shows the current value of the free running 16-bit Timer B. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count 1. 84 read-write 0x0000ffff TBV TBV [31:0] RTCPD RTC Pre-divide Value This register shows the current value of the RTC pre-divider in RTC mode. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count -1. 88 read-only 0x00007fff RTCPD RTCPD [15:0] TAPS Timer A Pre-scale Snap-shot Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer A pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled a read of a timer value will return the current count -1. 92 read-only 0x00000000 PSS PSS [7:0] TBPS Timer B Pre-scale Snap-shot Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer B pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled a read of a timer value will return the current count -1. 96 read-only 0x00000000 PSS PSS [7:0] TAPV Timer A Pre-scale Value This register shows the current value of the Timer A free running pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count 1. 100 read-only 0x00000000 PSV PSV [7:0] TBPV Timer B Pre-scale Value This register shows the current value of the Timer B free running pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count-1. 104 read-only 0x00000000 PSV PSV [7:0] DMAEV DMA Event This register allows software to enable/disable GPT DMA trigger events. 108 read-write 0x00000000 TBMDMAEN TBMDMAEN [11:11] CBEDMAEN CBEDMAEN [10:10] CBMDMAEN CBMDMAEN [9:9] TBTODMAEN TBTODMAEN [8:8] TAMDMAEN TAMDMAEN [4:4] RTCDMAEN RTCDMAEN [3:3] CAEDMAEN CAEDMAEN [2:2] CAMDMAEN CAMDMAEN [1:1] TATODMAEN TATODMAEN [0:0] VERSION Peripheral Version This register provides information regarding the GPT version 4016 read-only 0x00000400 VERSION VERSION [31:0] ANDCCP Combined CCP Output This register is used to logically AND CCP output pairs for each timer 4020 read-write 0x00000000 CCP_AND_EN CCP_AND_EN [0:0] I2C0 I2CMaster/Slave Serial Controler 0x40002000 0 0x1000 registers SOAR Slave Own Address This register consists of seven address bits that identify this I2C device on the I2C bus. 0 read-write 0x00000000 OAR OAR [6:0] SSTAT Slave Status Note: This register shares address with SCTL, meaning that this register functions as a control register when written, and a status register when read. 4 read-only 0x00000000 FBR FBR [2:2] TREQ TREQ [1:1] RREQ RREQ [0:0] SCTL Slave Control Note: This register shares address with SSTAT, meaning that this register functions as a control register when written, and a status register when read. 4 write-only 0x00000000 DA DA [0:0] SSTAT SDR Slave Data This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state. 8 read-write 0x00000000 DATA DATA [7:0] SIMR Slave Interrupt Mask This register controls whether a raw interrupt is promoted to a controller interrupt. 12 read-write 0x00000000 STOPIM STOPIM [2:2] STARTIM STARTIM [1:1] DATAIM DATAIM [0:0] SRIS Slave Raw Interrupt Status This register shows the unmasked interrupt status. 16 read-only 0x00000000 STOPRIS STOPRIS [2:2] STARTRIS STARTRIS [1:1] DATARIS DATARIS [0:0] SMIS Slave Masked Interrupt Status This register show which interrupt is active (based on result from SRIS and SIMR). 20 read-only 0x00000000 STOPMIS STOPMIS [2:2] STARTMIS STARTMIS [1:1] DATAMIS DATAMIS [0:0] SICR Slave Interrupt Clear This register clears the raw interrupt SRIS. 24 write-only 0x00000000 STOPIC STOPIC [2:2] STARTIC STARTIC [1:1] DATAIC DATAIC [0:0] MSA Master Salve Address This register contains seven address bits of the slave to be accessed by the master (a6-a0), and an RS bit determining if the next operation is a receive or transmit. 2048 read-write 0x00000000 SA SA [7:1] RS RS [0:0] MSTAT Master Status 2052 read-only 0x00000020 BUSBSY BUSBSY [6:6] IDLE IDLE [5:5] ARBLST ARBLST [4:4] DATACK_N DATACK_N [3:3] ADRACK_N ADRACK_N [2:2] ERR ERR [1:1] BUSY BUSY [0:0] MCTRL Master Control This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller as stated in MSTAT. When written, the control register configures the I2C controller operation. To generate a single transmit cycle, the I2C Master Slave Address (MSA) register is written with the desired address, the MSA.RS bit is cleared, and this register is written with * ACK=X (0 or 1), * STOP=1, * START=1, * RUN=1 to perform the operation and stop. When the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the MDR register. 2052 write-only 0x00000000 ACK ACK [3:3] STOP STOP [2:2] START START [1:1] RUN RUN [0:0] MSTAT MDR Master Data This register contains the data to be transmitted when in the Master Transmit state and the data received when in the Master Receive state. 2056 read-write 0x00000000 DATA DATA [7:0] MTPR I2C Master Timer Period This register specifies the period of the SCL clock. 2060 read-write 0x00000001 TPR_7 TPR_7 [7:7] TPR TPR [6:0] MIMR Master Interrupt Mask This register controls whether a raw interrupt is promoted to a controller interrupt. 2064 read-write 0x00000000 IM IM [0:0] MRIS Master Raw Interrupt Status This register show the unmasked interrupt status. 2068 read-only 0x00000000 RIS RIS [0:0] MMIS Master Masked Interrupt Status This register show which interrupt is active (based on result from MRIS and MIMR). 2072 read-only 0x00000000 MIS MIS [0:0] MICR Master Interrupt Clear This register clears the raw and masked interrupt. 2076 write-only 0x00000000 IC IC [0:0] MCR Master Configuration This register configures the mode (Master or Slave) and sets the interface for test mode loopback. 2080 read-write 0x00000000 SFE SFE [5:5] MFE MFE [4:4] LPBK LPBK [0:0] I2S0 I2S Audio DMA module supporting formats I2S, LJF, RJF and DSP 0x40021000 0 0x1000 registers AIFWCLKSRC WCLK Source Selection 0 read-write 0x00000000 WCLK_INV WCLK_INV [2:2] WCLK_SRC WCLK_SRC [1:0] AIFDMACFG DMA Buffer Size Configuration 4 read-write 0x00000000 END_FRAME_IDX END_FRAME_IDX [7:0] AIFDIRCFG Pin Direction 8 read-write 0x00000000 AD2 AD2 [9:8] AD1 AD1 [5:4] AD0 AD0 [1:0] AIFFMTCFG Serial Interface Format Configuration 12 read-write 0x00000170 DATA_DELAY DATA_DELAY [15:8] MEM_LEN_24 MEM_LEN_24 [7:7] SMPL_EDGE SMPL_EDGE [6:6] DUAL_PHASE DUAL_PHASE [5:5] WORD_LEN WORD_LEN [4:0] AIFWMASK0 Word Selection Bit Mask for Pin 0 16 read-write 0x00000003 MASK MASK [7:0] AIFWMASK1 Word Selection Bit Mask for Pin 1 20 read-write 0x00000003 MASK MASK [7:0] AIFWMASK2 Word Selection Bit Mask for Pin 2 24 read-write 0x00000003 MASK MASK [7:0] AIFPWMVALUE Audio Interface PWM Debug Value 28 read-write 0x00000000 PULSE_WIDTH PULSE_WIDTH [15:0] AIFINPTRNEXT DMA Input Buffer Next Pointer 32 read-write 0x00000000 PTR PTR [31:0] AIFINPTR DMA Input Buffer Current Pointer 36 read-write 0x00000000 PTR PTR [31:0] AIFOUTPTRNEXT DMA Output Buffer Next Pointer 40 read-write 0x00000000 PTR PTR [31:0] AIFOUTPTR DMA Output Buffer Current Pointer 44 read-write 0x00000000 PTR PTR [31:0] STMPCTL SampleStaMP Generator Control Register 52 read-write 0x00000000 OUT_RDY OUT_RDY [2:2] IN_RDY IN_RDY [1:1] STMP_EN STMP_EN [0:0] STMPXCNTCAPT0 Captured XOSC Counter Value, Capture Channel 0 56 read-only 0x00000000 CAPT_VALUE CAPT_VALUE [15:0] STMPXPER XOSC Period Value 60 read-only 0x00000000 VALUE VALUE [15:0] STMPWCNTCAPT0 Captured WCLK Counter Value, Capture Channel 0 64 read-only 0x00000000 CAPT_VALUE CAPT_VALUE [15:0] STMPWPER WCLK Counter Period Value 68 read-write 0x00000000 VALUE VALUE [15:0] STMPINTRIG WCLK Counter Trigger Value for Input Pins 72 read-write 0x00000000 IN_START_WCNT IN_START_WCNT [15:0] STMPOUTTRIG WCLK Counter Trigger Value for Output Pins 76 read-write 0x00000000 OUT_START_WCNT OUT_START_WCNT [15:0] STMPWSET WCLK Counter Set Operation 80 read-write 0x00000000 VALUE VALUE [15:0] STMPWADD WCLK Counter Add Operation 84 read-write 0x00000000 VALUE_INC VALUE_INC [15:0] STMPXPERMIN XOSC Minimum Period Value Minimum Value of STMPXPER 88 read-write 0x0000ffff VALUE VALUE [15:0] STMPWCNT Current Value of WCNT 92 read-only 0x00000000 CURR_VALUE CURR_VALUE [15:0] STMPXCNT Current Value of XCNT 96 read-only 0x00000000 CURR_VALUE CURR_VALUE [15:0] STMPXCNTCAPT1 Captured XOSC Counter Value, Capture Channel 1 100 read-only 0x00000000 CAPT_VALUE CAPT_VALUE [15:0] STMPWCNTCAPT1 Captured WCLK Counter Value, Capture Channel 1 104 read-only 0x00000000 CAPT_VALUE CAPT_VALUE [15:0] IRQMASK Masked Interrupt Status Register 112 read-write 0x00000000 AIF_DMA_IN AIF_DMA_IN [5:5] AIF_DMA_OUT AIF_DMA_OUT [4:4] WCLK_TIMEOUT WCLK_TIMEOUT [3:3] BUS_ERR BUS_ERR [2:2] WCLK_ERR WCLK_ERR [1:1] PTR_ERR PTR_ERR [0:0] IRQFLAGS Raw Interrupt Status Register 116 read-only 0x00000000 AIF_DMA_IN AIF_DMA_IN [5:5] AIF_DMA_OUT AIF_DMA_OUT [4:4] WCLK_TIMEOUT WCLK_TIMEOUT [3:3] BUS_ERR BUS_ERR [2:2] WCLK_ERR WCLK_ERR [1:1] PTR_ERR PTR_ERR [0:0] IRQSET Interrupt Set Register 120 write-only 0x00000000 AIF_DMA_IN AIF_DMA_IN [5:5] AIF_DMA_OUT AIF_DMA_OUT [4:4] WCLK_TIMEOUT WCLK_TIMEOUT [3:3] BUS_ERR BUS_ERR [2:2] WCLK_ERR WCLK_ERR [1:1] PTR_ERR PTR_ERR [0:0] IRQCLR Interrupt Clear Register 124 write-only 0x00000000 AIF_DMA_IN AIF_DMA_IN [5:5] AIF_DMA_OUT AIF_DMA_OUT [4:4] WCLK_TIMEOUT WCLK_TIMEOUT [3:3] BUS_ERR BUS_ERR [2:2] WCLK_ERR WCLK_ERR [1:1] PTR_ERR PTR_ERR [0:0] IOC IO Controller (IOC) - configures all the DIOs and resides in the MCU domain. 0x40081000 0 0x1000 registers IOCFG0 Configuration of DIO0 0 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG1 Configuration of DIO1 4 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG2 Configuration of DIO2 8 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG3 Configuration of DIO3 12 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG4 Configuration of DIO4 16 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG5 Configuration of DIO5 20 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG6 Configuration of DIO6 24 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG7 Configuration of DIO7 28 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG8 Configuration of DIO8 32 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG9 Configuration of DIO9 36 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG10 Configuration of DIO10 40 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG11 Configuration of DIO11 44 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG12 Configuration of DIO12 48 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG13 Configuration of DIO13 52 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG14 Configuration of DIO14 56 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG15 Configuration of DIO15 60 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG16 Configuration of DIO16 64 read-write 0x00086000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG17 Configuration of DIO17 68 read-write 0x8000006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG18 Configuration of DIO18 72 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG19 Configuration of DIO19 76 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG20 Configuration of DIO20 80 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG21 Configuration of DIO21 84 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG22 Configuration of DIO22 88 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG23 Configuration of DIO23 92 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG24 Configuration of DIO24 96 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG25 Configuration of DIO25 100 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG26 Configuration of DIO26 104 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG27 Configuration of DIO27 108 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG28 Configuration of DIO28 112 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG29 Configuration of DIO29 116 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG30 Configuration of DIO30 120 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] IOCFG31 Configuration of DIO31 124 read-write 0x00006000 HYST_EN HYST_EN [30:30] IE IE [29:29] WU_CFG WU_CFG [28:27] IOMODE IOMODE [26:24] EDGE_IRQ_EN EDGE_IRQ_EN [18:18] EDGE_DET EDGE_DET [17:16] PULL_CTL PULL_CTL [14:13] SLEW_RED SLEW_RED [12:12] IOCURR IOCURR [11:10] IOSTR IOSTR [9:8] PORT_ID PORT_ID [5:0] PRCM Power, Reset and Clock Management 0x40082000 0 0x00001000 registers INFRCLKDIVR Infrastructure Clock Division Factor For Run Mode 0 read-write 0x00000000 RATIO RATIO [1:0] INFRCLKDIVS Infrastructure Clock Division Factor For Sleep Mode 4 read-write 0x00000000 RATIO RATIO [1:0] INFRCLKDIVDS Infrastructure Clock Division Factor For DeepSleep Mode 8 read-write 0x00000000 RATIO RATIO [1:0] VDCTL MCU Voltage Domain Control 12 read-write 0x00000000 MCU_VD MCU_VD [2:2] ULDO ULDO [0:0] CLKLOADCTL Clock Load Control 40 read-write 0x00000002 LOAD_DONE LOAD_DONE [1:1] LOAD LOAD [0:0] RFCCLKG RFC Clock Gate 44 read-write 0x00000001 CLK_EN CLK_EN [0:0] VIMSCLKG VIMS Clock Gate 48 read-write 0x00000003 CLK_EN CLK_EN [1:0] SECDMACLKGR TRNG, CRYPTO And UDMA Clock Gate For Run Mode 60 read-write 0x00000000 DMA_CLK_EN DMA_CLK_EN [8:8] TRNG_CLK_EN TRNG_CLK_EN [1:1] CRYPTO_CLK_EN CRYPTO_CLK_EN [0:0] SECDMACLKGS TRNG, CRYPTO And UDMA Clock Gate For Sleep Mode 64 read-write 0x00000000 DMA_CLK_EN DMA_CLK_EN [8:8] TRNG_CLK_EN TRNG_CLK_EN [1:1] CRYPTO_CLK_EN CRYPTO_CLK_EN [0:0] SECDMACLKGDS TRNG, CRYPTO And UDMA Clock Gate For Deep Sleep Mode 68 read-write 0x00000000 DMA_CLK_EN DMA_CLK_EN [8:8] TRNG_CLK_EN TRNG_CLK_EN [1:1] CRYPTO_CLK_EN CRYPTO_CLK_EN [0:0] GPIOCLKGR GPIO Clock Gate For Run Mode 72 read-write 0x00000000 CLK_EN CLK_EN [0:0] GPIOCLKGS GPIO Clock Gate For Sleep Mode 76 read-write 0x00000000 CLK_EN CLK_EN [0:0] GPIOCLKGDS GPIO Clock Gate For Deep Sleep Mode 80 read-write 0x00000000 CLK_EN CLK_EN [0:0] GPTCLKGR GPT Clock Gate For Run Mode 84 read-write 0x00000000 CLK_EN CLK_EN [3:0] GPTCLKGS GPT Clock Gate For Sleep Mode 88 read-write 0x00000000 CLK_EN CLK_EN [3:0] GPTCLKGDS GPT Clock Gate For Deep Sleep Mode 92 read-write 0x00000000 CLK_EN CLK_EN [3:0] I2CCLKGR I2C Clock Gate For Run Mode 96 read-write 0x00000000 CLK_EN CLK_EN [0:0] I2CCLKGS I2C Clock Gate For Sleep Mode 100 read-write 0x00000000 CLK_EN CLK_EN [0:0] I2CCLKGDS I2C Clock Gate For Deep Sleep Mode 104 read-write 0x00000000 CLK_EN CLK_EN [0:0] UARTCLKGR UART Clock Gate For Run Mode 108 read-write 0x00000000 CLK_EN CLK_EN [0:0] UARTCLKGS UART Clock Gate For Sleep Mode 112 read-write 0x00000000 CLK_EN CLK_EN [0:0] UARTCLKGDS UART Clock Gate For Deep Sleep Mode 116 read-write 0x00000000 CLK_EN CLK_EN [0:0] SSICLKGR SSI Clock Gate For Run Mode 120 read-write 0x00000000 CLK_EN CLK_EN [1:0] SSICLKGS SSI Clock Gate For Sleep Mode 124 read-write 0x00000000 CLK_EN CLK_EN [1:0] SSICLKGDS SSI Clock Gate For Deep Sleep Mode 128 read-write 0x00000000 CLK_EN CLK_EN [1:0] I2SCLKGR I2S Clock Gate For Run Mode 132 read-write 0x00000000 CLK_EN CLK_EN [0:0] I2SCLKGS I2S Clock Gate For Sleep Mode 136 read-write 0x00000000 CLK_EN CLK_EN [0:0] I2SCLKGDS I2S Clock Gate For Deep Sleep Mode 140 read-write 0x00000000 CLK_EN CLK_EN [0:0] CPUCLKDIV Internal. Only to be used through TI provided API. 184 read-write 0x00000000 RATIO RATIO [0:0] I2SBCLKSEL I2S Clock Control 200 read-write 0x00000000 SRC SRC [0:0] GPTCLKDIV GPT Scalar 204 read-write 0x00000000 RATIO RATIO [3:0] I2SCLKCTL I2S Clock Control 208 read-write 0x00000000 SMPL_ON_POSEDGE SMPL_ON_POSEDGE [3:3] WCLK_PHASE WCLK_PHASE [2:1] EN EN [0:0] I2SMCLKDIV MCLK Division Ratio 212 read-write 0x00000000 MDIV MDIV [9:0] I2SBCLKDIV BCLK Division Ratio 216 read-write 0x00000000 BDIV BDIV [9:0] I2SWCLKDIV WCLK Division Ratio 220 read-write 0x00000000 WDIV WDIV [15:0] SWRESET SW Initiated Resets 268 read-write 0x00000000 MCU MCU [2:2] WARMRESET WARM Reset Control And Status 272 read-write 0x00000000 WR_TO_PINRESET WR_TO_PINRESET [2:2] LOCKUP_STAT LOCKUP_STAT [1:1] WDT_STAT WDT_STAT [0:0] PDCTL0 Power Domain Control 300 read-write 0x00000000 PERIPH_ON PERIPH_ON [2:2] SERIAL_ON SERIAL_ON [1:1] RFC_ON RFC_ON [0:0] PDCTL0RFC RFC Power Domain Control 304 read-write 0x00000000 ON ON [0:0] PDCTL0SERIAL SERIAL Power Domain Control 308 read-write 0x00000000 ON ON [0:0] PDCTL0PERIPH PERIPH Power Domain Control 312 read-write 0x00000000 ON ON [0:0] PDSTAT0 Power Domain Status 320 read-only 0x00000000 PERIPH_ON PERIPH_ON [2:2] SERIAL_ON SERIAL_ON [1:1] RFC_ON RFC_ON [0:0] PDSTAT0RFC RFC Power Domain Status 324 read-only 0x00000000 ON ON [0:0] PDSTAT0SERIAL SERIAL Power Domain Status 328 read-only 0x00000000 ON ON [0:0] PDSTAT0PERIPH PERIPH Power Domain Status 332 read-only 0x00000000 ON ON [0:0] PDCTL1 Power Domain Control 380 read-write 0x0000000a VIMS_MODE VIMS_MODE [3:3] RFC_ON RFC_ON [2:2] CPU_ON CPU_ON [1:1] PDCTL1CPU CPU Power Domain Control 388 read-write 0x00000001 ON ON [0:0] PDCTL1RFC RFC Power Domain Control 392 read-write 0x00000000 ON ON [0:0] PDCTL1VIMS VIMS Power Domain Control 396 read-write 0x00000001 ON ON [0:0] PDSTAT1 Power Domain Status 404 read-only 0x0000001a BUS_ON BUS_ON [4:4] VIMS_MODE VIMS_MODE [3:3] RFC_ON RFC_ON [2:2] CPU_ON CPU_ON [1:1] PDSTAT1BUS BUS Power Domain Status 408 read-only 0x00000001 ON ON [0:0] PDSTAT1RFC RFC Power Domain Status 412 read-only 0x00000000 ON ON [0:0] PDSTAT1CPU CPU Power Domain Status 416 read-only 0x00000001 ON ON [0:0] PDSTAT1VIMS VIMS Power Domain Status 420 read-only 0x00000001 ON ON [0:0] RFCMODESEL Selected RFC Mode 464 read-write 0x00000000 CURR CURR [2:0] RAMRETEN Memory Retention Control 548 read-write 0x00000003 RFC RFC [2:2] VIMS VIMS [1:0] RFC_DBELL RF Core Doorbell 0x40041000 0 0x40 registers CMDR Doorbell Command Register 0 read-write 0x00000000 CMD CMD [31:0] CMDSTA Doorbell Command Status Register 4 read-only 0x00000000 STAT STAT [31:0] RFHWIFG Interrupt Flags From RF Hardware Modules 8 read-write 0x00000000 RATCH7 RATCH7 [19:19] RATCH6 RATCH6 [18:18] RATCH5 RATCH5 [17:17] RATCH4 RATCH4 [16:16] RATCH3 RATCH3 [15:15] RATCH2 RATCH2 [14:14] RATCH1 RATCH1 [13:13] RATCH0 RATCH0 [12:12] RFESOFT2 RFESOFT2 [11:11] RFESOFT1 RFESOFT1 [10:10] RFESOFT0 RFESOFT0 [9:9] RFEDONE RFEDONE [8:8] TRCTK TRCTK [6:6] MDMSOFT MDMSOFT [5:5] MDMOUT MDMOUT [4:4] MDMIN MDMIN [3:3] MDMDONE MDMDONE [2:2] FSCA FSCA [1:1] RFHWIEN Interrupt Enable For RF Hardware Modules 12 read-write 0x00000000 RATCH7 RATCH7 [19:19] RATCH6 RATCH6 [18:18] RATCH5 RATCH5 [17:17] RATCH4 RATCH4 [16:16] RATCH3 RATCH3 [15:15] RATCH2 RATCH2 [14:14] RATCH1 RATCH1 [13:13] RATCH0 RATCH0 [12:12] RFESOFT2 RFESOFT2 [11:11] RFESOFT1 RFESOFT1 [10:10] RFESOFT0 RFESOFT0 [9:9] RFEDONE RFEDONE [8:8] TRCTK TRCTK [6:6] MDMSOFT MDMSOFT [5:5] MDMOUT MDMOUT [4:4] MDMIN MDMIN [3:3] MDMDONE MDMDONE [2:2] FSCA FSCA [1:1] RFCPEIFG Interrupt Flags For Command and Packet Engine Generated Interrupts 16 read-write 0x00000000 INTERNAL_ERROR INTERNAL_ERROR [31:31] BOOT_DONE BOOT_DONE [30:30] MODULES_UNLOCKED MODULES_UNLOCKED [29:29] SYNTH_NO_LOCK SYNTH_NO_LOCK [28:28] IRQ27 IRQ27 [27:27] RX_ABORTED RX_ABORTED [26:26] RX_N_DATA_WRITTEN RX_N_DATA_WRITTEN [25:25] RX_DATA_WRITTEN RX_DATA_WRITTEN [24:24] RX_ENTRY_DONE RX_ENTRY_DONE [23:23] RX_BUF_FULL RX_BUF_FULL [22:22] RX_CTRL_ACK RX_CTRL_ACK [21:21] RX_CTRL RX_CTRL [20:20] RX_EMPTY RX_EMPTY [19:19] RX_IGNORED RX_IGNORED [18:18] RX_NOK RX_NOK [17:17] RX_OK RX_OK [16:16] IRQ15 IRQ15 [15:15] IRQ14 IRQ14 [14:14] IRQ13 IRQ13 [13:13] IRQ12 IRQ12 [12:12] TX_BUFFER_CHANGED TX_BUFFER_CHANGED [11:11] TX_ENTRY_DONE TX_ENTRY_DONE [10:10] TX_RETRANS TX_RETRANS [9:9] TX_CTRL_ACK_ACK TX_CTRL_ACK_ACK [8:8] TX_CTRL_ACK TX_CTRL_ACK [7:7] TX_CTRL TX_CTRL [6:6] TX_ACK TX_ACK [5:5] TX_DONE TX_DONE [4:4] LAST_FG_COMMAND_DONE LAST_FG_COMMAND_DONE [3:3] FG_COMMAND_DONE FG_COMMAND_DONE [2:2] LAST_COMMAND_DONE LAST_COMMAND_DONE [1:1] COMMAND_DONE COMMAND_DONE [0:0] RFCPEIEN Interrupt Enable For Command and Packet Engine Generated Interrupts 20 read-write 0xffffffff INTERNAL_ERROR INTERNAL_ERROR [31:31] BOOT_DONE BOOT_DONE [30:30] MODULES_UNLOCKED MODULES_UNLOCKED [29:29] SYNTH_NO_LOCK SYNTH_NO_LOCK [28:28] IRQ27 IRQ27 [27:27] RX_ABORTED RX_ABORTED [26:26] RX_N_DATA_WRITTEN RX_N_DATA_WRITTEN [25:25] RX_DATA_WRITTEN RX_DATA_WRITTEN [24:24] RX_ENTRY_DONE RX_ENTRY_DONE [23:23] RX_BUF_FULL RX_BUF_FULL [22:22] RX_CTRL_ACK RX_CTRL_ACK [21:21] RX_CTRL RX_CTRL [20:20] RX_EMPTY RX_EMPTY [19:19] RX_IGNORED RX_IGNORED [18:18] RX_NOK RX_NOK [17:17] RX_OK RX_OK [16:16] IRQ15 IRQ15 [15:15] IRQ14 IRQ14 [14:14] IRQ13 IRQ13 [13:13] IRQ12 IRQ12 [12:12] TX_BUFFER_CHANGED TX_BUFFER_CHANGED [11:11] TX_ENTRY_DONE TX_ENTRY_DONE [10:10] TX_RETRANS TX_RETRANS [9:9] TX_CTRL_ACK_ACK TX_CTRL_ACK_ACK [8:8] TX_CTRL_ACK TX_CTRL_ACK [7:7] TX_CTRL TX_CTRL [6:6] TX_ACK TX_ACK [5:5] TX_DONE TX_DONE [4:4] LAST_FG_COMMAND_DONE LAST_FG_COMMAND_DONE [3:3] FG_COMMAND_DONE FG_COMMAND_DONE [2:2] LAST_COMMAND_DONE LAST_COMMAND_DONE [1:1] COMMAND_DONE COMMAND_DONE [0:0] RFCPEISL Interrupt Vector Selection For Command and Packet Engine Generated Interrupts 24 read-write 0xffff0000 INTERNAL_ERROR INTERNAL_ERROR [31:31] BOOT_DONE BOOT_DONE [30:30] MODULES_UNLOCKED MODULES_UNLOCKED [29:29] SYNTH_NO_LOCK SYNTH_NO_LOCK [28:28] IRQ27 IRQ27 [27:27] RX_ABORTED RX_ABORTED [26:26] RX_N_DATA_WRITTEN RX_N_DATA_WRITTEN [25:25] RX_DATA_WRITTEN RX_DATA_WRITTEN [24:24] RX_ENTRY_DONE RX_ENTRY_DONE [23:23] RX_BUF_FULL RX_BUF_FULL [22:22] RX_CTRL_ACK RX_CTRL_ACK [21:21] RX_CTRL RX_CTRL [20:20] RX_EMPTY RX_EMPTY [19:19] RX_IGNORED RX_IGNORED [18:18] RX_NOK RX_NOK [17:17] RX_OK RX_OK [16:16] IRQ15 IRQ15 [15:15] IRQ14 IRQ14 [14:14] IRQ13 IRQ13 [13:13] IRQ12 IRQ12 [12:12] TX_BUFFER_CHANGED TX_BUFFER_CHANGED [11:11] TX_ENTRY_DONE TX_ENTRY_DONE [10:10] TX_RETRANS TX_RETRANS [9:9] TX_CTRL_ACK_ACK TX_CTRL_ACK_ACK [8:8] TX_CTRL_ACK TX_CTRL_ACK [7:7] TX_CTRL TX_CTRL [6:6] TX_ACK TX_ACK [5:5] TX_DONE TX_DONE [4:4] LAST_FG_COMMAND_DONE LAST_FG_COMMAND_DONE [3:3] FG_COMMAND_DONE FG_COMMAND_DONE [2:2] LAST_COMMAND_DONE LAST_COMMAND_DONE [1:1] COMMAND_DONE COMMAND_DONE [0:0] RFACKIFG Doorbell Command Acknowledgement Interrupt Flag 28 read-write 0x00000000 ACKFLAG ACKFLAG [0:0] SYSGPOCTL RF Core General Purpose Output Control 32 read-write 0x00000000 GPOCTL3 GPOCTL3 [15:12] GPOCTL2 GPOCTL2 [11:8] GPOCTL1 GPOCTL1 [7:4] GPOCTL0 GPOCTL0 [3:0] RFC_PWR RF Core Power Management 0x40040000 0 0x4 registers PWMCLKEN RF Core Power Management and Clock Enable 0 read-write 0x00000001 RFCTRC RFCTRC [10:10] FSCA FSCA [9:9] PHA PHA [8:8] RAT RAT [7:7] RFERAM RFERAM [6:6] RFE RFE [5:5] MDMRAM MDMRAM [4:4] MDM MDM [3:3] CPERAM CPERAM [2:2] CPE CPE [1:1] RFC RFC [0:0] RFC_RAT RF Core Radio Timer 0x40043000 0 0x100 registers RATCNT Radio Timer Counter Value 4 read-write 0x00000000 CNT CNT [31:0] RATCH0VAL Timer Channel 0 Capture/Compare Register 128 read-write 0x00000000 VAL VAL [31:0] RATCH1VAL Timer Channel 1 Capture/Compare Register 132 read-write 0x00000000 VAL VAL [31:0] RATCH2VAL Timer Channel 2 Capture/Compare Register 136 read-write 0x00000000 VAL VAL [31:0] RATCH3VAL Timer Channel 3 Capture/Compare Register 140 read-write 0x00000000 VAL VAL [31:0] RATCH4VAL Timer Channel 4 Capture/Compare Register 144 read-write 0x00000000 VAL VAL [31:0] RATCH5VAL Timer Channel 5 Capture/Compare Register 148 read-write 0x00000000 VAL VAL [31:0] RATCH6VAL Timer Channel 6 Capture/Compare Register 152 read-write 0x00000000 VAL VAL [31:0] RATCH7VAL Timer Channel 7 Capture/Compare Register 156 read-write 0x00000000 VAL VAL [31:0] SMPH MCU Semaphore Module This module provides 32 binary semaphores. The state of a binary semaphore is either taken or available. A semaphore does not implement any ownership attribute. Still, a semaphore can be used to handle mutual exclusion scenarios. 0x40084000 0 0x1000 registers SMPH0 MCU SEMAPHORE 0 0 read-write 0x00000001 STAT STAT [0:0] clear SMPH1 MCU SEMAPHORE 1 4 read-write 0x00000001 STAT STAT [0:0] clear SMPH2 MCU SEMAPHORE 2 8 read-write 0x00000001 STAT STAT [0:0] clear SMPH3 MCU SEMAPHORE 3 12 read-write 0x00000001 STAT STAT [0:0] clear SMPH4 MCU SEMAPHORE 4 16 read-write 0x00000001 STAT STAT [0:0] clear SMPH5 MCU SEMAPHORE 5 20 read-write 0x00000001 STAT STAT [0:0] clear SMPH6 MCU SEMAPHORE 6 24 read-write 0x00000001 STAT STAT [0:0] clear SMPH7 MCU SEMAPHORE 7 28 read-write 0x00000001 STAT STAT [0:0] clear SMPH8 MCU SEMAPHORE 8 32 read-write 0x00000001 STAT STAT [0:0] clear SMPH9 MCU SEMAPHORE 9 36 read-write 0x00000001 STAT STAT [0:0] clear SMPH10 MCU SEMAPHORE 10 40 read-write 0x00000001 STAT STAT [0:0] clear SMPH11 MCU SEMAPHORE 11 44 read-write 0x00000001 STAT STAT [0:0] clear SMPH12 MCU SEMAPHORE 12 48 read-write 0x00000001 STAT STAT [0:0] clear SMPH13 MCU SEMAPHORE 13 52 read-write 0x00000001 STAT STAT [0:0] clear SMPH14 MCU SEMAPHORE 14 56 read-write 0x00000001 STAT STAT [0:0] clear SMPH15 MCU SEMAPHORE 15 60 read-write 0x00000001 STAT STAT [0:0] clear SMPH16 MCU SEMAPHORE 16 64 read-write 0x00000001 STAT STAT [0:0] clear SMPH17 MCU SEMAPHORE 17 68 read-write 0x00000001 STAT STAT [0:0] clear SMPH18 MCU SEMAPHORE 18 72 read-write 0x00000001 STAT STAT [0:0] clear SMPH19 MCU SEMAPHORE 19 76 read-write 0x00000001 STAT STAT [0:0] clear SMPH20 MCU SEMAPHORE 20 80 read-write 0x00000001 STAT STAT [0:0] clear SMPH21 MCU SEMAPHORE 21 84 read-write 0x00000001 STAT STAT [0:0] clear SMPH22 MCU SEMAPHORE 22 88 read-write 0x00000001 STAT STAT [0:0] clear SMPH23 MCU SEMAPHORE 23 92 read-write 0x00000001 STAT STAT [0:0] clear SMPH24 MCU SEMAPHORE 24 96 read-write 0x00000001 STAT STAT [0:0] clear SMPH25 MCU SEMAPHORE 25 100 read-write 0x00000001 STAT STAT [0:0] clear SMPH26 MCU SEMAPHORE 26 104 read-write 0x00000001 STAT STAT [0:0] clear SMPH27 MCU SEMAPHORE 27 108 read-write 0x00000001 STAT STAT [0:0] clear SMPH28 MCU SEMAPHORE 28 112 read-write 0x00000001 STAT STAT [0:0] clear SMPH29 MCU SEMAPHORE 29 116 read-write 0x00000001 STAT STAT [0:0] clear SMPH30 MCU SEMAPHORE 30 120 read-write 0x00000001 STAT STAT [0:0] clear SMPH31 MCU SEMAPHORE 31 124 read-write 0x00000001 STAT STAT [0:0] clear PEEK0 MCU SEMAPHORE 0 ALIAS 2048 read-only 0x00000001 STAT STAT [0:0] PEEK1 MCU SEMAPHORE 1 ALIAS 2052 read-only 0x00000001 STAT STAT [0:0] PEEK2 MCU SEMAPHORE 2 ALIAS 2056 read-only 0x00000001 STAT STAT [0:0] PEEK3 MCU SEMAPHORE 3 ALIAS 2060 read-only 0x00000001 STAT STAT [0:0] PEEK4 MCU SEMAPHORE 4 ALIAS 2064 read-only 0x00000001 STAT STAT [0:0] PEEK5 MCU SEMAPHORE 5 ALIAS 2068 read-only 0x00000001 STAT STAT [0:0] PEEK6 MCU SEMAPHORE 6 ALIAS 2072 read-only 0x00000001 STAT STAT [0:0] PEEK7 MCU SEMAPHORE 7 ALIAS 2076 read-only 0x00000001 STAT STAT [0:0] PEEK8 MCU SEMAPHORE 8 ALIAS 2080 read-only 0x00000001 STAT STAT [0:0] PEEK9 MCU SEMAPHORE 9 ALIAS 2084 read-only 0x00000001 STAT STAT [0:0] PEEK10 MCU SEMAPHORE 10 ALIAS 2088 read-only 0x00000001 STAT STAT [0:0] PEEK11 MCU SEMAPHORE 11 ALIAS 2092 read-only 0x00000001 STAT STAT [0:0] PEEK12 MCU SEMAPHORE 12 ALIAS 2096 read-only 0x00000001 STAT STAT [0:0] PEEK13 MCU SEMAPHORE 13 ALIAS 2100 read-only 0x00000001 STAT STAT [0:0] PEEK14 MCU SEMAPHORE 14 ALIAS 2104 read-only 0x00000001 STAT STAT [0:0] PEEK15 MCU SEMAPHORE 15 ALIAS 2108 read-only 0x00000001 STAT STAT [0:0] PEEK16 MCU SEMAPHORE 16 ALIAS 2112 read-only 0x00000001 STAT STAT [0:0] PEEK17 MCU SEMAPHORE 17 ALIAS 2116 read-only 0x00000001 STAT STAT [0:0] PEEK18 MCU SEMAPHORE 18 ALIAS 2120 read-only 0x00000001 STAT STAT [0:0] PEEK19 MCU SEMAPHORE 19 ALIAS 2124 read-only 0x00000001 STAT STAT [0:0] PEEK20 MCU SEMAPHORE 20 ALIAS 2128 read-only 0x00000001 STAT STAT [0:0] PEEK21 MCU SEMAPHORE 21 ALIAS 2132 read-only 0x00000001 STAT STAT [0:0] PEEK22 MCU SEMAPHORE 22 ALIAS 2136 read-only 0x00000001 STAT STAT [0:0] PEEK23 MCU SEMAPHORE 23 ALIAS 2140 read-only 0x00000001 STAT STAT [0:0] PEEK24 MCU SEMAPHORE 24 ALIAS 2144 read-only 0x00000001 STAT STAT [0:0] PEEK25 MCU SEMAPHORE 25 ALIAS 2148 read-only 0x00000001 STAT STAT [0:0] PEEK26 MCU SEMAPHORE 26 ALIAS 2152 read-only 0x00000001 STAT STAT [0:0] PEEK27 MCU SEMAPHORE 27 ALIAS 2156 read-only 0x00000001 STAT STAT [0:0] PEEK28 MCU SEMAPHORE 28 ALIAS 2160 read-only 0x00000001 STAT STAT [0:0] PEEK29 MCU SEMAPHORE 29 ALIAS 2164 read-only 0x00000001 STAT STAT [0:0] PEEK30 MCU SEMAPHORE 30 ALIAS 2168 read-only 0x00000001 STAT STAT [0:0] PEEK31 MCU SEMAPHORE 31 ALIAS 2172 read-only 0x00000001 STAT STAT [0:0] SSI0 Synchronous Serial Interface with master and slave capabilities 0x40000000 0 0x1000 registers CR0 Control 0 0 read-write 0x00000000 SCR SCR [15:8] SPH SPH [7:7] SPO SPO [6:6] FRF FRF [5:4] DSS DSS [3:0] CR1 Control 1 4 read-write 0x00000000 SOD SOD [3:3] MS MS [2:2] SSE SSE [1:1] LBM LBM [0:0] DR Data 16-bits wide data register: When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When written, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. 8 read-write 0x00000000 DATA DATA [15:0] SR Status 12 read-only 0x00000003 BSY BSY [4:4] RFF RFF [3:3] RNE RNE [2:2] TNF TNF [1:1] TFE TFE [0:0] CPSR Clock Prescale 16 read-write 0x00000000 CPSDVSR CPSDVSR [7:0] IMSC Interrupt Mask Set and Clear 20 read-write 0x00000000 TXIM TXIM [3:3] RXIM RXIM [2:2] RTIM RTIM [1:1] RORIM RORIM [0:0] RIS Raw Interrupt Status 24 read-only 0x00000008 TXRIS TXRIS [3:3] RXRIS RXRIS [2:2] RTRIS RTRIS [1:1] RORRIS RORRIS [0:0] MIS Masked Interrupt Status 28 read-only 0x00000000 TXMIS TXMIS [3:3] RXMIS RXMIS [2:2] RTMIS RTMIS [1:1] RORMIS RORMIS [0:0] ICR Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. 32 write-only 0x00000000 RTIC RTIC [1:1] RORIC RORIC [0:0] DMACR DMA Control 36 read-write 0x00000000 TXDMAE TXDMAE [1:1] RXDMAE RXDMAE [0:0] SSI1 Synchronous Serial Interface with master and slave capabilities 0x40008000 0 0x1000 registers CR0 Control 0 0 read-write 0x00000000 SCR SCR [15:8] SPH SPH [7:7] SPO SPO [6:6] FRF FRF [5:4] DSS DSS [3:0] CR1 Control 1 4 read-write 0x00000000 SOD SOD [3:3] MS MS [2:2] SSE SSE [1:1] LBM LBM [0:0] DR Data 16-bits wide data register: When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When written, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. 8 read-write 0x00000000 DATA DATA [15:0] SR Status 12 read-only 0x00000003 BSY BSY [4:4] RFF RFF [3:3] RNE RNE [2:2] TNF TNF [1:1] TFE TFE [0:0] CPSR Clock Prescale 16 read-write 0x00000000 CPSDVSR CPSDVSR [7:0] IMSC Interrupt Mask Set and Clear 20 read-write 0x00000000 TXIM TXIM [3:3] RXIM RXIM [2:2] RTIM RTIM [1:1] RORIM RORIM [0:0] RIS Raw Interrupt Status 24 read-only 0x00000008 TXRIS TXRIS [3:3] RXRIS RXRIS [2:2] RTRIS RTRIS [1:1] RORRIS RORRIS [0:0] MIS Masked Interrupt Status 28 read-only 0x00000000 TXMIS TXMIS [3:3] RXMIS RXMIS [2:2] RTMIS RTMIS [1:1] RORMIS RORMIS [0:0] ICR Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. 32 write-only 0x00000000 RTIC RTIC [1:1] RORIC RORIC [0:0] DMACR DMA Control 36 read-write 0x00000000 TXDMAE TXDMAE [1:1] RXDMAE RXDMAE [0:0] TRNG True Random Number Generator 0x40028000 0 0x2000 registers OUT0 Random Number Lower Word Readout Value 0 read-only 0x00000000 VALUE_31_0 VALUE_31_0 [31:0] OUT1 Random Number Upper Word Readout Value 4 read-only 0x00000000 VALUE_63_32 VALUE_63_32 [31:0] IRQFLAGSTAT Interrupt Status 8 read-only 0x00000000 NEED_CLOCK NEED_CLOCK [31:31] SHUTDOWN_OVF SHUTDOWN_OVF [1:1] RDY RDY [0:0] IRQFLAGMASK Interrupt Mask 12 read-write 0x00000000 SHUTDOWN_OVF SHUTDOWN_OVF [1:1] RDY RDY [0:0] IRQFLAGCLR Interrupt Flag Clear 16 write-only 0x00000000 SHUTDOWN_OVF SHUTDOWN_OVF [1:1] RDY RDY [0:0] CTL Control 20 read-write 0x00000000 STARTUP_CYCLES STARTUP_CYCLES [31:16] TRNG_EN TRNG_EN [10:10] NO_LFSR_FB NO_LFSR_FB [2:2] TEST_MODE TEST_MODE [1:1] CFG0 Configuration 0 24 read-write 0x00000000 MAX_REFILL_CYCLES MAX_REFILL_CYCLES [31:16] SMPL_DIV SMPL_DIV [11:8] MIN_REFILL_CYCLES MIN_REFILL_CYCLES [7:0] ALARMCNT Alarm Control 28 read-write 0x000000ff SHUTDOWN_CNT SHUTDOWN_CNT [29:24] SHUTDOWN_THR SHUTDOWN_THR [20:16] ALARM_THR ALARM_THR [7:0] FROEN FRO Enable 32 read-write 0x00ffffff FRO_MASK FRO_MASK [23:0] FRODETUNE FRO De-tune Bit 36 read-write 0x00000000 FRO_MASK FRO_MASK [23:0] ALARMMASK Alarm Event 40 read-write 0x00000000 FRO_MASK FRO_MASK [23:0] ALARMSTOP Alarm Shutdown 44 read-write 0x00000000 FRO_FLAGS FRO_FLAGS [23:0] LFSR0 LFSR Readout Value 48 read-write 0x00000000 LFSR_31_0 LFSR_31_0 [31:0] LFSR1 LFSR Readout Value 52 read-write 0x00000000 LFSR_63_32 LFSR_63_32 [31:0] LFSR2 LFSR Readout Value 56 read-write 0x00000000 LFSR_80_64 LFSR_80_64 [16:0] HWOPT TRNG Engine Options Information 120 read-only 0x00000600 NR_OF_FROS NR_OF_FROS [11:6] HWVER0 HW Version 0 EIP Number And Core Revision 124 read-only 0x0200b44b HW_MAJOR_VER HW_MAJOR_VER [27:24] HW_MINOR_VER HW_MINOR_VER [23:20] HW_PATCH_LVL HW_PATCH_LVL [19:16] EIP_NUM_COMPL EIP_NUM_COMPL [15:8] EIP_NUM EIP_NUM [7:0] IRQSTATMASK Interrupt Status After Masking 8152 read-only 0x00000000 SHUTDOWN_OVF SHUTDOWN_OVF [1:1] RDY RDY [0:0] HWVER1 HW Version 1 TRNG Revision Number 8160 read-only 0x00000020 REV REV [7:0] IRQSET Interrupt Set 8172 read-write 0x00000000 SWRESET SW Reset Control 8176 read-write 0x00000000 RESET RESET [0:0] IRQSTAT Interrupt Status 8184 read-only 0x00000000 STAT STAT [0:0] UART0 Universal Asynchronous Receiver/Transmitter (UART) interface 0x40001000 0 0x1000 registers DR Data For words to be transmitted: - if the FIFOs are enabled (LCRH.FEN = 1), data written to this location is pushed onto the transmit FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), data is stored in the transmitter holding register (the bottom word of the transmit FIFO). The write operation initiates transmission from the UART. The data is prefixed with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop bit. The resultant word is then transmitted. For received words: - if the FIFOs are enabled (LCRH.FEN = 1), the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data byte is read by performing reads from this register along with the corresponding status information. The status information can also be read by a read of the RSR register. 0 write-only 0x00000000 OE OE [11:11] BE BE [10:10] PE PE [9:9] FE FE [8:8] DATA DATA [7:0] RSR Status This register is mapped to the same address as ECR register. Reads from this address are associated with RSR register and return the receive status. Writes to this address are associated with ECR register and clear the receive status flags (framing, parity, break, and overrun errors). If the status is read from this register, then the status information for break, framing and parity corresponds to the data character read from the Data Register, DR prior to reading the RSR. The status information for overrun is set immediately when an overrun condition occurs. 4 read-only 0x00000000 OE OE [3:3] BE BE [2:2] PE PE [1:1] FE FE [0:0] ECR Error Clear This register is mapped to the same address as RSR register. Reads from this address are associated with RSR register and return the receive status. Writes to this address are associated with ECR register and clear the receive status flags (framing, parity, break, and overrun errors). 4 write-only 0x00000000 OE OE [3:3] BE BE [2:2] PE PE [1:1] FE FE [0:0] RSR FR Flag Reads from this register return the UART flags. 24 read-only 0x00000090 TXFE TXFE [7:7] RXFF RXFF [6:6] TXFF TXFF [5:5] RXFE RXFE [4:4] BUSY BUSY [3:3] CTS CTS [0:0] IBRD Integer Baud-Rate Divisor If this register is modified while trasmission or reception is on-going, the baudrate will not be updated until transmission or reception of the current character is complete. 36 read-write 0x00000000 DIVINT DIVINT [15:0] FBRD Fractional Baud-Rate Divisor If this register is modified while trasmission or reception is on-going, the baudrate will not be updated until transmission or reception of the current character is complete. 40 read-write 0x00000000 DIVFRAC DIVFRAC [5:0] LCRH Line Control 44 read-write 0x00000000 SPS SPS [7:7] WLEN WLEN [6:5] FEN FEN [4:4] STP2 STP2 [3:3] EPS EPS [2:2] PEN PEN [1:1] BRK BRK [0:0] CTL Control 48 read-write 0x00000300 CTSEN CTSEN [15:15] RTSEN RTSEN [14:14] RTS RTS [11:11] RXE RXE [9:9] TXE TXE [8:8] LBE LBE [7:7] UARTEN UARTEN [0:0] IFLS Interrupt FIFO Level Select 52 read-write 0x00000012 RXSEL RXSEL [5:3] TXSEL TXSEL [2:0] IMSC Interrupt Mask Set/Clear 56 read-write 0x00000000 OEIM OEIM [10:10] BEIM BEIM [9:9] PEIM PEIM [8:8] FEIM FEIM [7:7] RTIM RTIM [6:6] TXIM TXIM [5:5] RXIM RXIM [4:4] CTSMIM CTSMIM [1:1] RIS Raw Interrupt Status 60 read-only 0x0000000d OERIS OERIS [10:10] BERIS BERIS [9:9] PERIS PERIS [8:8] FERIS FERIS [7:7] RTRIS RTRIS [6:6] TXRIS TXRIS [5:5] RXRIS RXRIS [4:4] CTSRMIS CTSRMIS [1:1] MIS Masked Interrupt Status 64 read-only 0x00000000 OEMIS OEMIS [10:10] BEMIS BEMIS [9:9] PEMIS PEMIS [8:8] FEMIS FEMIS [7:7] RTMIS RTMIS [6:6] TXMIS TXMIS [5:5] RXMIS RXMIS [4:4] CTSMMIS CTSMMIS [1:1] ICR Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. 68 write-only 0x00000000 OEIC OEIC [10:10] BEIC BEIC [9:9] PEIC PEIC [8:8] FEIC FEIC [7:7] RTIC RTIC [6:6] TXIC TXIC [5:5] RXIC RXIC [4:4] CTSMIC CTSMIC [1:1] DMACTL DMA Control 72 read-write 0x00000000 DMAONERR DMAONERR [2:2] TXDMAE TXDMAE [1:1] RXDMAE RXDMAE [0:0] UDMA0 ARM Micro Direct Memory Access Controller 0x40020000 0 0x1000 registers STATUS Status 0 read-only 0x001f0000 TEST TEST [31:28] TOTALCHANNELS TOTALCHANNELS [20:16] STATE STATE [7:4] MASTERENABLE MASTERENABLE [0:0] CFG Configuration 4 write-only 0x00000000 PRTOCTRL PRTOCTRL [7:5] MASTERENABLE MASTERENABLE [0:0] CTRL Channel Control Data Base Pointer 8 read-write 0x00000000 BASEPTR BASEPTR [31:10] ALTCTRL Channel Alternate Control Data Base Pointer 12 read-only 0x00000200 BASEPTR BASEPTR [31:0] WAITONREQ Channel Wait On Request Status 16 read-only 0xffff1eff CHNLSTATUS CHNLSTATUS [31:0] SOFTREQ Channel Software Request 20 write-only 0x00000000 CHNLS CHNLS [31:0] SETBURST Channel Set UseBurst 24 read-write 0x00000000 CHNLS CHNLS [31:0] CLEARBURST Channel Clear UseBurst 28 write-only 0x00000000 CHNLS CHNLS [31:0] SETREQMASK Channel Set Request Mask 32 read-write 0x00000000 CHNLS CHNLS [31:0] CLEARREQMASK Clear Channel Request Mask 36 write-only 0x00000000 CHNLS CHNLS [31:0] SETCHANNELEN Set Channel Enable 40 read-write 0x00000000 CHNLS CHNLS [31:0] CLEARCHANNELEN Clear Channel Enable 44 write-only 0x00000000 CHNLS CHNLS [31:0] SETCHNLPRIALT Channel Set Primary-Alternate 48 read-write 0x00000000 CHNLS CHNLS [31:0] CLEARCHNLPRIALT Channel Clear Primary-Alternate 52 write-only 0x00000000 CHNLS CHNLS [31:0] SETCHNLPRIORITY Set Channel Priority 56 read-write 0x00000000 CHNLS CHNLS [31:0] CLEARCHNLPRIORITY Clear Channel Priority 60 write-only 0x00000000 CHNLS CHNLS [31:0] ERROR Error Status and Clear 76 read-write 0x00000000 STATUS STATUS [0:0] REQDONE Channel Request Done 1284 read-write 0x00000000 CHNLS CHNLS [31:0] DONEMASK Channel Request Done Mask 1312 read-write 0x00000000 CHNLS CHNLS [31:0] VIMS Versatile Instruction Memory System Controls memory access to the Flash and encapsulates the following instruction memories: - Boot ROM - Cache / GPRAM 0x40034000 0 0x400 registers STAT Status Displays current VIMS mode and line buffer status 0 read-only 0x00000000 IDCODE_LB_DIS IDCODE_LB_DIS [5:5] SYSBUS_LB_DIS SYSBUS_LB_DIS [4:4] MODE_CHANGING MODE_CHANGING [3:3] INV INV [2:2] MODE MODE [1:0] CTL Control Configure VIMS mode and line buffer settings 4 read-write 0x00000000 STATS_CLR STATS_CLR [31:31] STATS_EN STATS_EN [30:30] DYN_CG_EN DYN_CG_EN [29:29] IDCODE_LB_DIS IDCODE_LB_DIS [5:5] SYSBUS_LB_DIS SYSBUS_LB_DIS [4:4] ARB_CFG ARB_CFG [3:3] PREF_EN PREF_EN [2:2] MODE MODE [1:0] WDT Watchdog Timer 0x40080000 0 0x1000 registers LOAD Configuration 0 read-write 0xffffffff WDTLOAD WDTLOAD [31:0] VALUE Current Count Value 4 read-only 0xffffffff WDTVALUE WDTVALUE [31:0] CTL Control 8 read-write 0x00000000 INTTYPE INTTYPE [2:2] RESEN RESEN [1:1] INTEN INTEN [0:0] ICR Interrupt Clear 12 write-only 0x00000000 WDTICR WDTICR [31:0] RIS Raw Interrupt Status 16 read-only 0x00000000 WDTRIS WDTRIS [0:0] MIS Masked Interrupt Status 20 read-only 0x00000000 WDTMIS WDTMIS [0:0] TEST Test Mode 1048 read-write 0x00000000 STALL STALL [8:8] TEST_EN TEST_EN [0:0] INT_CAUS Interrupt Cause Test Mode 1052 read-only 0x00000000 CAUSE_RESET CAUSE_RESET [1:1] CAUSE_INTR CAUSE_INTR [0:0] LOCK Lock 3072 read-write 0x00000000 WDTLOCK WDTLOCK [31:0]