SIM3L166_C 1 256K Flash, 32K RAM, LCD, 64 PIN 8 32 32 read-write ACCTR_0 A None ACCTR_0 0x40042000 0x0 0xffc registers ACCTR0_IRQn 22 CONFIG Configuration 0x0 0x02000000 0xFFFFFFFF UPDSTSF Write Update Status Flag. 0 1 read-only NOT_SET An internal pulse counter register update is not in progress. 0 SET An internal pulse counter register update is in progress. 1 DBGSEL Debug Signal Select. 5 3 NONE No debug signals output. 0 LCC0_LCC1 (LC Mode) DBG0 = CMP0OUT, DBG1 = CMP1OUT. 1 LCC0_INT0 (LC Mode) DBG0 = CMP0OUT, DBG1 = INTEG0. 2 LCC1_INT1 (LC Mode) DBG0 = CMP1OUT, DBG1 = INTEG1. 3 INT0_INT1 (Any Mode) DBG0 = INTEG0 DBG1 = INTEG1. 4 CMP0_CMP1 (Switch Mode) DBG0 = CMP0OUT, DBG1 = CMP1OUT. 5 CMP0_INT0 (Switch Mode) DBG0 = CMP0OUT, DBG1 = INTEG0. 6 CMP1_INT1 (Switch Mode) DBG0= CMP1OUT, DBG1 = INTEG1. 7 FLQDEN Flutter Quadrature-to-Dual Switch Enable. 24 1 DISABLED The pulse counter remains in quadrature mode during a flutter event. 0 ENABLED The pulse counter switches from quadrature mode to dual mode during a flutter event. 1 FLSTPEN Flutter Stop Enable. 25 1 DISABLED The pulse counter continues operating during a flutter event. 0 ENABLED The 24-bit counters stop counting during a flutter event. 1 TOPMD Topology Mode. 29 1 SWITCH Select the switch closure topology. 0 LC Select the LC resonant topology. 1 PCMD Pulse Counter Mode. 30 2 DISABLED Disable the pulse counter. 0 SINGLE Select single channel mode. 1 DUAL Select dual channel mode. 2 QUADRATURE Select quadrature mode. 3 CONTROL Control Register 0x10 0x44000000 0xFFFFFFFF CMPLTH Comparator Low Threshold. 15 2 32_PERCENT Set the digital comparator low threshold to 32% of VIO. 0 36_PERCENT Set the digital comparator low threshold to 36% of VIO. 1 40_PERCENT Set the digital comparator low threshold to 40% of VIO. 2 44_PERCENT Set the digital comparator low threshold to 44% of VIO. 3 CMPHTH Comparator High Threshold. 17 2 48_PERCENT Set the digital comparator high threshold to 48% of VIO. 0 52_PERCENT Set the digital comparator high threshold to 52% of VIO. 1 56_PERCENT Set the digital comparator high threshold to 56% of VIO. 2 60_PERCENT Set the digital comparator high threshold to 60% of VIO. 3 CALMD Automatic Calibration Mode. 19 1 UNTIL_PASS Continue to calibrate until a passing condition occurs. 0 UNTIL_FAIL Continue to calibrate until a failing condition occurs. 1 CALPUMD Automatic Calibration Pull-up Mode. 20 2 FULL Use full pull-up mode. 0 SMALL Use small pull-up mode. 1 MEDIUM Use medium pull-up mode. 2 LARGE Use large pull-up mode. 3 FPUPEN Force Continuous Pull-up Enable. 22 1 DISABLED Pull-ups are enabled automatically by hardware. 0 ENABLED Always enable the pull-ups. 1 FPDNEN Force Ground Input Enable. 23 1 DISABLED Disable input grounding. 0 ENABLED Enable input grounding. The IN0 and IN1 inputs are grounded. 1 PUVAL Pull-up Value. 24 5 CALSEL Automatic Calibration Input Select. 29 1 IN0 Calibrate the IN0 input. 0 IN1 Calibrate the IN1 input. 1 CALRF Calibration Result Flag. 30 1 read-only NOT_SET The automatic calibration operation did not succeed. 0 SET The automatic calibration operation succeeded. 1 CALBUSYF Calibration Busy Flag. 31 1 NOT_SET A calibration operation is not in progress. 0 SET A calibration operation is in progress. Hardware will clear this flag when the operation completes. 1 LCCONFIG LC Configuration 0x20 0x01718C61 0xFFFFFFFF PEMD LC Pulse Extension Mode. 0 2 LOW Stretch the LC comparator output low pulses by approximately 20 ns. 0 HIGH Stretch the LC comparator output high pulses by approximately 20 ns. 1 NONE No pulse extension. 2 CMP0FTH LC Comparator 0 Fine Threshold. 2 3 CMP0CTH LC Comparator 0 Coarse Threshold. 5 6 CMP0THR LC Comparator 0 Threshold Range. 11 1 LOW Set the comparator 0 threshold to the low range (0 V to VIO/8 in 48 steps). 0 FULL Set the comparator 0 threshold to a full range (0 V to VIO in 64 steps). 1 CMP1FTH LC Comparator 1 Fine Threshold. 12 3 CMP1CTH LC Comparator 1 Coarse Threshold. 15 6 CMP1THR LC Comparator 1 Threshold Range. 21 1 LOW Set the comparator 1 threshold to the low range (0 V to VIO/8 in 48 steps). 0 FULL Set the comparator 1 threshold to a full range (0 V to VIO in 64 steps). 1 CMPLHYS LC Comparator Low-side Hysteresis. 22 2 0_MV Set both LC comparators to use 0 mV low-side hysteresis. 0 5_MV Set both LC comparators to use 5 mV low-side hysteresis. 1 10_MV Set both LC comparators to use 10 mV low-side hysteresis. 2 20_MV Set both LC comparators to use 20 mV low-side hysteresis. 3 CMPHHYS LC Comparator High-side Hysteresis. 24 2 0_MV Set both LC comparators to use 0 mV high-side hysteresis. 0 5_MV Set both LC comparators to use 5 mV high-side hysteresis. 1 10_MV Set both LC comparators to use 10 mV high-side hysteresis. 2 20_MV Set both LC comparators to use 20 mV high-side hysteresis. 3 CMPMD LC Comparator Mode. 26 2 5_US Mode 0 (slowest response time, lowest power consumption). 0 1_US Mode 1. 1 400_NS Mode 2. 2 200_NS Mode 3 (fastest response time, highest power consumption). 3 CMP0CNT1EN LC Comparator 0 to Count 1 Enable. 28 1 DISABLED Use LC comparator 0 as an input to counter 0 and LC comparator 1 as an input to counter 1. 0 ENABLED Use LC comparator 0 as an input to both counter 0 and counter 1. 1 FCMP0EN Force LC Comparator 0 On Enable. 29 1 DISABLED Hardware automatically turns LC comparator 0 on and off. 0 ENABLED Force LC comparator 0 always on. 1 FCMP1EN Force LC Comparator 1 On Enable. 30 1 DISABLED Hardware automatically turns LC comparator 1 on and off. 0 ENABLED Force LC comparator 1 always on. 1 TIMING Timing 0x30 0x40000018 0xFFFFFFFF STATE Timing State. 0 3 read-only B0OEN Bias 0 Offset Enable. 3 1 DISABLED The bias 0 pulse is a full width (minimum 2 RTC cycles). 0 ENABLED The bias 0 pulse is delayed 1/2 an RTC cycle and de-asserts 1/2 an RTC cycle early (minimum 3 RTC cycles). 1 B1OEN Bias 1 Offset Enable. 4 1 DISABLED The bias 1 pulse is a full width (minimum 2 RTC cycles). 0 ENABLED The bias 1 pulse is delayed 1/2 an RTC cycle and de-asserts 1/2 an RTC cycle early (minimum 3 RTC cycles). 1 ZONED Zone D Count. 9 3 ZONEC Zone C Count. 12 3 ZONEB Zone B Count. 15 3 ZONEA Zone A Count. 18 3 ZONEP Zone P Count. 21 3 WAKEMD LC Wake Mode. 24 3 DISABLED Disable wake up events. 0 WZONEP Wake or interrupt at the start of zone P. 1 WZONEA Wake or interrupt at the start of zone A. 2 WZONEB Wake or interrupt at the start of zone B. 3 WZONEC Wake or interrupt at the start of zone C. 4 WZONED Wake or interrupt at the start of zone D. 5 WEND Wake or interrupt at the end of the LC sequence. 6 WKSTOP Wake or interrupt at the end of the LC sequence and stop the sequencer when this event occurs. 7 START Sequencer Start. 27 1 DISABLED Do not start the sequencer. 0 ENABLED Start the sequencer. 1 PERIOD Pulse Counter Period. 28 4 4_CYCLES Set the period to 4 RTC cycles. 0 8_CYCLES Set the period to 8 RTC cycles. 1 16_CYCLES Set the period to 16 RTC cycles. 2 32_CYCLES Set the period to 32 RTC cycles. 3 64_CYCLES Set the period to 64 RTC cycles. 4 128_CYCLES Set the period to 128 RTC cycles. 5 256_CYCLES Set the period to 256 RTC cycles. 6 512_CYCLES Set the period to 512 RTC cycles. 7 1024_CYCLES Set the period to 1024 RTC cycles. 8 2048_CYCLES Set the period to 2048 RTC cycles. 9 4096_CYCLES Set the period to 4096 RTC cycles. 10 SINGLE_SAMPLE Set the module to single sample mode and disable the period counter after the next completion of the sequencer. In this mode, firmware must start each sample by setting FLCSEN to 1. 14 CONSECUTIVE_SAMPLE Set the module to consecutive sample mode and disable the period counter. After completing zone D, the timing engine will jump directly to zone A, skipping both the W and P zones. 15 LCMODE LC Mode 0x40 0x0258A742 0xFFFFFFFF ATRKEN Automatic Tracking Enable. 0 1 DISABLED Disable automatic tracking. 0 ENABLED Enable automatic tracking. A new MAX value of any size will increase both the MAX and MIN by 1, and a new MIN value of any size will decrease both the MAX and MIN by 1. 1 ACDEN Automatic Center Discriminator Enable. 1 1 DISABLED Disable automatic center discriminator mode. Firmware must set the CD0 and CD1 fields. 0 ENABLED Enable automatic center discriminator mode. Hardware will keep the CD0 and CD1 fields centered between MAX and MIN. 1 LCD0HYS LC Discriminator 0 Digital Hysterisis. 2 2 ZERO A high-to-low transition occurs if LCCOUNT0 is less than CD0. 0 MINUS1 A high-to-low transition occurs if LCCOUNT0 is less than CD0 - 1. 1 MINUS2 A high-to-low transition occurs if LCCOUNT0 is less than CD0 - 2. 2 MINUS3 A high-to-low transition occurs if LCCOUNT0 is less than CD0 - 3. 3 LCD1HYS LC Discriminator 1 Digital Hysterisis. 4 2 ZERO A high-to-low transition occurs if LCCOUNT1 is less than CD1. 0 MINUS1 A high-to-low transition occurs if LCCOUNT1 is less than CD1 - 1. 1 MINUS2 A high-to-low transition occurs if LCCOUNT1 is less than CD1 - 2. 2 MINUS3 A high-to-low transition occurs if LCCOUNT1 is less than CD1 - 3. 3 C0ZONE Counter 0 Active Zone Select. 6 2 ZONEA Select zone A as the active zone for counter 0 (LCIN0 input). 0 ZONEB Select zone B as the active zone for counter 0 (LCIN0 input). 1 ZONEC Select zone C as the active zone for counter 0 (LCIN0 input). 2 ZONED Select zone D as the active zone for counter 0 (LCIN0 input). 3 C1ZONE Counter 1 Active Zone Select. 8 2 ZONEA Select zone A as the active zone for counter 1 (LCIN1 input). 0 ZONEB Select zone B as the active zone for counter 1 (LCIN1 input). 1 ZONEC Select zone C as the active zone for counter 1 (LCIN1 input). 2 ZONED Select zone D as the active zone for counter 1 (LCIN1 input). 3 P0ZONE Pulse 0 Active Zone Select. 10 2 DISABLED Disable the pulse 0 output (LCPUL0). 0 C_ONLY Select zone C only as the active zone for the pulse 0 output (LCPUL0). 1 A_ONLY Select zone A only as the active zone for the pulse 0 output (LCPUL0). 2 A_AND_C Select zones A and C as the active zones for the pulse 0 output (LCPUL0). 3 P1ZONE Pulse 1 Active Zone Select. 12 2 DISABLED Disable the pulse 1 output (LCPUL1). 0 C_ONLY Select zone C only as the active zone for the pulse 1 output (LCPUL1). 1 A_ONLY Select zone A only as the active zone for the pulse 1 output (LCPUL1). 2 A_AND_C Select zones A and C as the active zones for the pulse 1 output (LCPUL1). 3 PMD LC Pulse Mode. 14 2 DISABLED Disable pulse mode. 0 TOGGLE Toggle at the start of zone A or zone C. 1 PULSE_LOW Set the pulse mode to idle high, pulse low. 2 PULSE_HIGH Set the pulse mode to idle low, pulse high. 3 B0ZONECEN Bias 0 Zone C Enable. 16 1 DISABLED Disable bias 0 during zone C. 0 ENABLED Enable bias 0 during zone C. 1 B0ZONEBEN Bias 0 Zone B Enable. 17 1 DISABLED Disable bias 0 during zone B. 0 ENABLED Enable bias 0 during zone B. 1 B0ZONEAEN Bias 0 Zone A Enable. 18 1 DISABLED Disable bias 0 during zone A. 0 ENABLED Enable bias 0 during zone A. 1 B0ZONEPEN Bias 0 Zone P Enable. 19 1 DISABLED Disable bias 0 during zone P. 0 ENABLED Enable bias 0 during zone P. 1 B0POL Bias 0 Polarity. 20 1 PULSE_LOW Set bias 0 to idle high, pulse low. 0 PULSE_HIGH Set bias 0 to idle low, pulse high. 1 B1ZONECEN Bias 1 Zone C Enable. 21 1 DISABLED Disable bias 1 during zone C. 0 ENABLED Enable bias 1 during zone C. 1 B1ZONEBEN Bias 1 Zone B Enable. 22 1 DISABLED Disable bias 1 during zone B. 0 ENABLED Enable bias 1 during zone B. 1 B1ZONEAEN Bias 1 Zone A Enable. 23 1 DISABLED Disable bias 1 during zone A. 0 ENABLED Enable bias 1 during zone A. 1 B1ZONEPEN Bias 1 Zone P Enable. 24 1 DISABLED Disable bias 1 during zone P. 0 ENABLED Enable bias 1 during zone P. 1 B1POL Bias 1 Polarity. 25 1 PULSE_LOW Set bias 1 to idle high, pulse low. 0 PULSE_HIGH Set bias 1 to idle low, pulse high. 1 BMD Bias Mode. 26 2 MODE0 Disable the bias signals. 0 MODE1 Use the bias signals externally only (LCBIAS0 and LCBIAS1 outputs). 1 MODE2 Use the bias signals internally only. 2 MODE3 Use the bias signals externally (LCBIAS0 and LCBIAS1 outputs) and internally. 3 LCMD LC Mode. 28 4 MODE0 The LC pulse asserts throughout zone A or zone C with a single-ended comparator using the counter and discriminator. 0 MODE1 The LC pulse asserts throughout zone A or zone C with differential comparators using the counter and discriminator. 1 MODE2 The LC pulse asserts throughout zone A or zone C with a single-ended comparator sampling and holding at the end of the LC pulse. 2 MODE3 The LC pulse asserts throughout zone A or zone C with differential comparators sampling and holding at the end of the LC pulse. 3 MODE4 The LC pulse starts at the beginning of zone A or C and stops with the timer with a single-ended comparator using the counter and discriminator. 4 MODE5 The LC pulse starts at the beginning of zone A or C and stops with the timer with differential comparators using the counter and discriminator. 5 MODE6 The LC pulse starts at the beginning of zone A or C and stops with the timer with a single-ended comparator sampling and holding at the end of the LC pulse. 6 MODE7 The LC pulse starts at the beginning of zone A or C and stops with the timer with differential comparators sampling and holding at the end of the LC pulse. 7 MODE8 The LC pulse starts at beginning of zone A or C and stops with the rising edge of the external stop input (STOPx) with a single-ended comparator using the counter and discriminator. 8 MODE9 The LC pulse starts at beginning of zone A or C and stops with the falling edge of the external stop input (STOPx) with single-ended comparators using the counter and discriminator. 9 MODE10 The LC pulse starts at beginning of zone A or C and stops with the rising edge of the external stop input (STOPx) with a single-ended comparator sampling and holding at the end of the LC pulse. 10 MODE11 The LC pulse starts at beginning of zone A or C and stops with the falling edge of the external stop input (STOPx) with single-ended comparators sampling and holding at the end of the LC pulse. 11 MODE12 Do not generate a pulse with a single-ended comparator using the timer and discrimintor. 12 MODE13 Do not generate a pulse with differential comparators using the timer and discrimintor. 13 MODE14 Do not generate a pulse with a single-ended comparator sampling and holding at the end of the zone. 14 MODE15 Do not genreate a pulse with differential comparators sampling and holding at the end of the zone. 15 LCCLKCONTROL LC Clock Control 0x50 0x00000000 0xFFFFFFFF CLKCYCLES LC Oscillator Clock Cycles. 0 12 read-only CLKCAL LC Oscillator Calibration Start. 12 1 NOT_IN_PROGRESS A calibration operation is not in progress. 0 START Start an oscillator calibration or a calibration operation is in progress. 1 RELOAD LC Oscillator Reload Value. 16 12 LCLIMITS LC Counter Limits 0x60 0x00FF00FF 0xFFFFFFFF MIN0 LC Counter 0 Minimum Value. 0 8 read-only MAX0 LC Counter 0 Maximum Value. 8 8 read-only MIN1 LC Counter 1 Minimum Value. 16 8 read-only MAX1 LC Counter 1 Maximum Value. 24 8 read-only LCCOUNT LC Counters 0x70 0x0F000F00 0xFFFFFFFF LCCOUNT0 LC Counter 0. 0 8 read-only CD0 LC Counter 0 Discriminator. 8 8 LCCOUNT1 LC Counter 1. 16 8 read-only CD1 LC Counter 1 Discriminator. 24 8 DBCONFIG Pulse Counter Debounce Configuration 0x80 0x00000000 0xFFFFFFFF LDBTH Integrator Low Debounce. 0 8 HDBTH Integrator High Debounce. 8 8 INTEGDCEN PC Integrator Disconnect Enable. 16 1 DISABLED Connect integrator to 24 bit counter state machine logic. 0 ENABLED Disconnect the integrators from the IN0 and IN1 inputs. 1 INTEG0 PC Integrator 0 Output. 17 1 read-only LOW The integrator 0 output is low. 0 HIGH The integrator 0 output is high. 1 INTEG1 PC Integrator 1 Output. 18 1 read-only LOW The integrator 1 output is low. 0 HIGH The integrator 1 output is high. 1 COUNT0 Pulse Counter 0 0x90 0x00000000 0xFFFFFFFF COUNT0 Pulse Counter 0. 0 24 read-only COUNT1 Pulse Counter 1 0xa0 0x00000000 0xFFFFFFFF COUNT1 Pulse Counter 1. 0 24 read-only COMP0 Comparator 0 0xb0 0x00FFFFFF 0xFFFFFFFF COMP0 Pulse Counter Comparator 0 Threshold. 0 24 COMP1 Pulse Counter Comparator 1 Threshold 0xc0 0x00FFFFFF 0xFFFFFFFF COMP1 Pulse Counter Comparator 1 Threshold. 0 24 STATUS Pulse Counter Status 0xd0 0x3F400000 0xFFFFFFFF DIRCHGI Direction Change Interrupt Flag. 0 1 NOT_SET A direction change did not occur. 0 SET A direction change occurred. 1 OVFI Counter Overflow Interrupt Flag. 1 1 NOT_SET Neither of the counters overflowed. 0 SET One of the counters overflowed. 1 CMP0I Digital Comparator 0 Interrupt Flag. 2 1 NOT_SET A digital comparator 0 and counter 0 match did not occur. 0 SET A digital comparator 0 and counter 0 match occurred. 1 CMP1I Digital Comparator 1 Interrupt Flag. 3 1 NOT_SET A digital comparator 1 and counter 1 match did not occur. 0 SET A digital comparator 1 and counter 1 match occurred. 1 TRANSI Integrator Transition Interrupt Flag. 4 1 NOT_SET An integrator output transition did not occur. 0 SET An integrator output transition occurred. 1 QERRI Quadrature Error Interrupt Flag. 5 1 NOT_SET A quadrature error did not occur. 0 SET A quadrature error occurred. 1 FLSTOPI Flutter Stop Interrupt Flag. 6 1 NOT_SET A flutter detection end event did not occur. 0 SET A flutter detection end event occurred. 1 FLSTARTI Flutter Start Interrupt Flag. 7 1 NOT_SET A flutter detection start event did not occur. 0 SET A flutter detection start event occurred. 1 DIRCHGIEN Direction Change Interrupt Enable. 8 1 DISABLED Disable direction change as an interrupt or wake up source. 0 ENABLED Enable direction change as an interrupt or wake up source. 1 OVFIEN Counter Overflow Interrupt Enable. 9 1 DISABLED Disable counter overflows as an interrupt or wake up source. 0 ENABLED Enable counter overflows as an interrupt or wake up source. 1 CMP0IEN Digital Comparator 0 Interrupt Enable. 10 1 DISABLED Disable comparator 0 as an interrupt or wake up source. 0 ENABLED Enable comparator 0 as an interrupt or wake up source. 1 CMP1IEN Digital Comparator 1 Interrupt Enable. 11 1 DISABLED Disable comparator 1 as an interrupt or wake up source. 0 ENABLED Enable comparator 1 as an interrupt or wake up source. 1 TRANSIEN Integrator Transition Interrupt Enable. 12 1 DISABLED Disable integrator transitions as an interrupt or wake up source. 0 ENABLED Enable integrator transitions as an interrupt or wake up source. 1 QERRIEN Quadrature Error Interrupt Enable. 13 1 DISABLED Disable quadrature error as an interrupt or wake up source. 0 ENABLED Enable quadrature error as an interrupt or wake up source. 1 FLSTOPIEN Flutter Stop Interrupt Enable. 14 1 DISABLED Disable flutter detection end events as an interrupt or wake up source. 0 ENABLED Enable flutter detection end events as an interrupt or wake up source. 1 FLSTARTIEN Flutter Start Interrupt Enable. 15 1 DISABLED Disable flutter detection start events as an interrupt or wake up source. 0 ENABLED Enable flutter detection start events as an interrupt or wake up source. 1 IN0 Integrator 0 Output. 16 1 read-only LOW The integrator 0 output is low. 0 HIGH The integrator 0 output is high. 1 IN1 Integrator 1 Output. 17 1 read-only LOW The integrator 1 output is low. 0 HIGH The integrator 1 output is high. 1 IN0PREV Previous Integrator 0 Output. 18 1 read-only LOW The previous integrator 0 output was low. 0 HIGH The previous integrator 0 output was high. 1 IN1PREV Previous Integrator 1 Output. 19 1 read-only LOW The previous integrator 1 output was low. 0 HIGH The previous integrator 1 output was high. 1 STATE Pulse Counter State. 20 2 read-only ST0 The pulse counter is in state 0. 0 ST1 The pulse counter is in state 1. 1 ST2 The pulse counter is in state 2. 2 ST3 The pulse counter is in state 3. 3 DIRF Direction Flag. 22 1 read-only COUNTER_CLOCKWISE The current direction is counter-clockwise. 0 CLOCKWISE The current direction is clockwise. 1 FLF Flutter Detected Flag. 23 1 read-only NOT_SET The switch operates normally. 0 SET A flutter event was detected. 1 DIRHIST Direction History . 24 4 read-only CMP0OUT Comparator 0 Output. 28 1 read-only LOW The output of comparator 0 is low. 0 HIGH The output of comparator 0 is high. 1 CMP1OUT Comparator 1 Output. 29 1 read-only LOW The output of comparator 1 is low. 0 HIGH The output of comparator1 is high. 1 DEBUGEN Calibration 0xe0 0x00000624 0xFFFFFFFF DBGOEN Debug Output Enable. 14 1 DISABLED 0 ENABLED 1 AES_0 B None AES_0 0x40027000 0x0 0xffc registers AES0_IRQn 35 CONTROL Module Control 0x0 0x80000000 0xFFFFFFFF XFRSTA AES Transfer Start. 0 1 START Start the AES operation. 1 KEYCPEN Key Capture Enable. 1 1 DISABLED Disable key capture. 0 ENABLED Enable key capture. 1 EDMD Encryption/Decryption Mode. 2 1 DECRYPT AES module performs a decryption operation 0 ENCRYPT AES module performs an encryption operation. 1 SWMDEN Software Mode Enable. 8 1 DISABLED Disable software mode. 0 ENABLED Enable software mode. 1 BEN Bypass AES Operation Enable. 9 1 DISABLED Do not bypass AES operations. 0 ENABLED Bypass AES operations. 1 XOREN XOR Enable. 10 2 XOR_DISABLED Disable the XOR paths. 0 XOR_INPUT Enable the XOR input path, disable the XOR output path. 1 XOR_OUTPUT Disable the XOR input path, enable the XOR output path. 2 HCTREN Hardware Counter Mode Enable. 12 1 DISABLED Disable hardware counter mode. 0 ENABLED Enable hardware counter mode. 1 HCBCEN Hardware Cipher-Block Chaining Mode Enable. 13 1 DISABLED Disable hardware cipher-block chaining (CBC) mode. 0 ENABLED Enable hardware cipher-block chaining (CBC) mode. 1 KEYSIZE Keystore Size Select. 16 2 KEY128 Key is composed of 128 bits. 0 KEY192 Key is composed of 192 bits. 1 KEY256 Key is composed of 256 bits. 2 ERRIEN Error Interrupt Enable. 24 1 DISABLED Disable the error interrupt. 0 ENABLED Enable the error interrupt. An interrupt is generated when the Input/Output Data FIFO Overun (DORI), Input/Output Data FIFO Underun (DURI), or XOR Data FIFO Overrun (XORI) flags are set. 1 OCIEN Operation Complete Interrupt Enable. 25 1 DISABLED Disable the operation complete interrupt. 0 ENABLED Enable the operation complete interrupt. An interrupt is generated when the Operation Complete Interrupt (OCI) flag is set. 1 DBGMD AES Debug Mode. 30 1 HALT A debug breakpoint will cause the AES module to halt. 0 RUN The AES module will continue to operate while the core is halted in debug mode. 1 RESET Module Soft Reset. 31 1 INACTIVE AES module is not in soft reset. 0 ACTIVE AES module is in soft reset and none of the module bits can be accessed. 1 XFRSIZE Number of Blocks 0x10 0x00000000 0xFFFFFFFF XFRSIZE Transfer Size. 0 11 DATAFIFO Input/Output Data FIFO Access 0x20 0x00000000 0xFFFFFFFF modifyExternal DATAFIFO Input/Output Data FIFO Access. 0 32 XORFIFO XOR Data FIFO Access 0x30 0x00000000 0xFFFFFFFF XORFIFO XOR Data FIFO Access. 0 32 HWKEY0 Hardware Key Word 0 0x40 0x00000000 0xFFFFFFFF HWKEY0 Hardware Key Word 0. 0 32 HWKEY1 Hardware Key Word 1 0x50 0x00000000 0xFFFFFFFF HWKEY1 Hardware Key Word 1. 0 32 HWKEY2 Hardware Key Word 2 0x60 0x00000000 0xFFFFFFFF HWKEY2 Hardware Key Word 2. 0 32 HWKEY3 Hardware Key Word 3 0x70 0x00000000 0xFFFFFFFF HWKEY3 Hardware Key Word 3. 0 32 HWKEY4 Hardware Key Word 4 0x80 0x00000000 0xFFFFFFFF HWKEY4 Hardware Key Word 4. 0 32 HWKEY5 Hardware Key Word 5 0x90 0x00000000 0xFFFFFFFF HWKEY5 Hardware Key Word 5. 0 32 HWKEY6 Hardware Key Word 6 0xa0 0x00000000 0xFFFFFFFF HWKEY6 Hardware Key Word 6. 0 32 HWKEY7 Hardware Key Word 7 0xb0 0x00000000 0xFFFFFFFF HWKEY7 Hardware Key Word 7. 0 32 HWCTR0 Hardware Counter Word 0 0xc0 0x00000000 0xFFFFFFFF HWCTR0 Hardware Counter Word 0. 0 32 HWCTR1 Hardware Counter Word 1 0xd0 0x00000000 0xFFFFFFFF HWCTR1 Hardware Counter Word 1. 0 32 HWCTR2 Hardware Counter Word 2 0xe0 0x00000000 0xFFFFFFFF HWCTR2 Hardware Counter Word 2. 0 32 HWCTR3 Hardware Counter Word 3 0xf0 0x00000000 0xFFFFFFFF HWCTR3 Hardware Counter Word 3. 0 32 STATUS Module Status 0x100 0x00000000 0xFFFFFFFF DFIFOLVL Input/Output Data FIFO Level. 0 5 read-only EMPTY Input/Output data FIFO is empty. 0 1_BYTE Input/Output data FIFO contains 1 byte. 1 2_BYTES Input/Output data FIFO contains 2 bytes. 2 3_BYTES Input/Output data FIFO contains 3 bytes. 3 4_BYTES Input/Output data FIFO contains 4 bytes. 4 5_BYTES Input/Output data FIFO contains 5 bytes. 5 6_BYTES Input/Output data FIFO contains 6 bytes. 6 7_BYTES Input/Output data FIFO contains 7 bytes. 7 8_BYTES Input/Output data FIFO contains 8 bytes. 8 9_BYTES Input/Output data FIFO contains 9 bytes. 9 10_BYTES Input/Output data FIFO contains 10 bytes. 10 11_BYTES Input/Output data FIFO contains 11 bytes. 11 12_BYTES Input/Output data FIFO contains 12 bytes. 12 13_BYTES Input/Output data FIFO contains 13 bytes. 13 14_BYTES Input/Output data FIFO contains 14 bytes. 14 15_BYTES Input/Output data FIFO contains 15 bytes. 15 FULL Input/Output data FIFO contains 16 bytes (full). 16 XFIFOLVL XOR Data FIFO Level. 8 5 read-only EMPTY XOR data FIFO is empty. 0 1_BYTE XOR data FIFO contains 1 byte. 1 2_BYTES XOR data FIFO contains 2 bytes. 2 3_BYTES XOR data FIFO contains 3 bytes. 3 4_BYTES XOR data FIFO contains 4 bytes. 4 5_BYTES XOR data FIFO contains 5 bytes. 5 6_BYTES XOR data FIFO contains 6 bytes. 6 7_BYTES XOR data FIFO contains 7 bytes. 7 8_BYTES XOR data FIFO contains 8 bytes. 8 9_BYTES XOR data FIFO contains 9 bytes. 9 10_BYTES XOR data FIFO contains 10 bytes. 10 11_BYTES XOR data FIFO contains 11 bytes. 11 12_BYTES XOR data FIFO contains 12 bytes. 12 13_BYTES XOR data FIFO contains 13 bytes. 13 14_BYTES XOR data FIFO contains 14 bytes. 14 15_BYTES XOR data FIFO contains 15 bytes. 15 FULL XOR data FIFO contains 16 bytes (full). 16 BUSYF Module Busy Flag. 24 1 read-only NOT_SET AES module is not busy. 0 SET AES module is completing an operation. 1 DURI Input/Output Data FIFO Underrun Interrupt Flag. 28 1 NOT_SET No input/output data FIFO underrun. 0 SET An input/output data FIFO underrun has occurred. 1 DORI Input/Output Data FIFO Overrun Interrupt Flag. 29 1 NOT_SET No input/output data FIFO overrun. 0 SET An input/output data FIFO overrun has occurred. 1 XORI XOR Data FIFO Overrun Interrupt Flag. 30 1 NOT_SET No XOR data FIFO overrun. 0 SET An XOR data FIFO overrun has occurred. 1 OCI Operation Complete Interrupt Flag. 31 1 NOT_SET AES operation complete interrupt has not occurred. 0 SET AES operation complete interrupt occurred. 1 CLKCTRL_0 A None CLKCTRL_0 0x4002d000 0x0 0xffc registers CONTROL Module Control 0x0 0x10000000 0xFFFFFFFF AHBSEL AHB Clock Source Select. 0 3 LPOSC0 AHB clock source is the Low-Power Oscillator. 0 LFOSC0 AHB clock source is the Low-Frequency Oscillator. 1 RTC0TCLK AHB clock source is the RTC0TCLK signal. 2 EXTOSC0 AHB clock source is the External Oscillator. 3 VIORFCLK AHB clock source is the VIORFCLK input pin. 4 PLL0OSC AHB clock source is the PLL. 5 LPOSC0_DIV AHB clock source is a divided version of the Low-Power Oscillator. 6 AHBDIV AHB Clock Divider. 8 3 DIV1 AHB clock divided by 1. 0 DIV2 AHB clock divided by 2. 1 DIV4 AHB clock divided by 4. 2 DIV8 AHB clock divided by 8. 3 DIV16 AHB clock divided by 16. 4 DIV32 AHB clock divided by 32. 5 DIV64 AHB clock divided by 64. 6 DIV128 AHB clock divided by 128. 7 APBDIV APB Clock Divider. 16 1 DIV1 APB clock is the same as the AHB clock (divided by 1). 0 DIV2 APB clock is the AHB clock divided by 2. 1 EXTESEL External Clock Edge Select. 28 1 BOTH_EDGES External clock generated by both rising and falling edges of the external oscillator. 0 RISING_ONLY External clock generated by only rising edges of the external oscillator. 1 OBUSYF Oscillators Busy Flag. 29 1 read-only NOT_SET AHB and APB oscillators are not busy. 0 SET AHB and APB oscillators are busy and the AHBSEL, AHBDIV, and APBDIV fields should not be modified. 1 VIORFCLKEN VIORF Clock Enable. 30 1 DISABLED Disable the VIORFCLK input. 0 ENABLED Enable the VIORFCLK input. 1 EXTOSCEN External Clock Input Enable. 31 1 DISABLED Disable the EXTOSC input. 0 ENABLED Enable the EXTOSC input. 1 AHBCLKG AHB Clock Gate 0x10 0x00000005 0xFFFFFFFF RAMCEN RAM Clock Enable. 0 1 DISABLED Disable the AHB clock to the RAM. 0 ENABLED Enable the AHB clock to the RAM. 1 DMACEN DMA Clock Enable. 1 1 DISABLED Disable the AHB clock to the DMA Controller. 0 ENABLED Enable the AHB clock to the DMA Controller. 1 FLASHCEN Flash Clock Enable. 2 1 DISABLED Disable the AHB clock to the Flash. 0 ENABLED Enable the AHB clock to the Flash. 1 DTM0EN DTM0 Clock Enable. 3 1 DISABLED Disable the AHB clock to Data Transfer Manager 0 (DTM0). 0 ENABLED Enable the AHB clock to Data Transfer Manager 0 (DTM0). 1 DTM1EN DTM1 Clock Enable. 4 1 DISABLED Disable the AHB clock to Data Transfer Manager 1 (DTM1). 0 ENABLED Enable the AHB clock to Data Transfer Manager 1 (DTM1). 1 DTM2EN DTM2 Clock Enable. 5 1 DISABLED Disable the AHB clock to Data Transfer Manager 2 (DTM2). 0 ENABLED Enable the AHB clock to Data Transfer Manager 2 (DTM2). 1 APBCLKG0 APB Clock Gate 0 0x20 0x00000000 0xFFFFFFFF FLCTRLCEN Flash Controller Clock Enable. 0 1 DISABLED Disable the APB clock to the Flash Controller Module (FLASHCTRL0). 0 ENABLED Enable the APB clock to the Flash Controller Module (FLASHCTRL0). 1 PB0CEN Port Bank Clock Enable. 1 1 DISABLED Disable the APB clock to the Port Bank Modules. 0 ENABLED Enable the APB clock to the Port Bank Modules. 1 USART0CEN USART0 Clock Enable. 2 1 DISABLED Disable the APB clock to the USART0 Module. 0 ENABLED Enable the APB clock to the USART0 Module. 1 UART0CEN UART0 Clock Enable. 3 1 DISABLED Disable the APB clock to the UART0 Module. 0 ENABLED Enable the APB clock to the UART0 Module. 1 SPI0CEN SPI0 Clock Enable. 4 1 DISABLED Disable the APB clock to the SPI0 Module. 0 ENABLED Enable the APB clock to the SPI0 Module. 1 SPI1CEN SPI1 Clock Enable. 5 1 DISABLED Disable the APB clock to the SPI1 Module. 0 ENABLED Enable the APB clock to the SPI1 Module. 1 I2C0CEN I2C0 Clock Enable. 6 1 DISABLED Disable the APB clock to the I2C0 Module. 0 ENABLED Enable the APB clock to the I2C0 Module. 1 EPCA0CEN EPCA0 Clock Enable. 7 1 DISABLED Disable the APB clock to the EPCA0 Module. 0 ENABLED Enable the APB clock to the EPCA0 Module. 1 TIMER0CEN TIMER0 Clock Enable. 8 1 DISABLED Disable the APB clock to the TIMER0 Module. 0 ENABLED Enable the APB clock to the TIMER0 Module. 1 TIMER1CEN TIMER1 Clock Enable. 9 1 DISABLED Disable the APB clock to the TIMER1 Module. 0 ENABLED Enable the APB clock to the TIMER1 Module. 1 TIMER2CEN TIMER2 Clock Enable. 10 1 DISABLED Disable the APB clock to the TIMER2 Module. 0 ENABLED Enable the APB clock to the TIMER2 Module. 1 ADC0CEN SARADC0 Clock Enable. 11 1 DISABLED Disable the APB clock to the SARADC0 Module. 0 ENABLED Enable the APB clock to the SARADC0 Module. 1 CMP0CEN CMP0 Clock Enable. 12 1 DISABLED Disable the APB clock to the Comparator 0 Module. 0 ENABLED Enable the APB clock to the Comparator 0 Module. 1 CMP1CEN CMP1 Clock Enable. 13 1 DISABLED Disable the APB clock to the Comparator 1 Module. 0 ENABLED Enable the APB clock to the Comparator 1 Module. 1 AES0CEN AES0 Clock Enable. 14 1 DISABLED Disable the APB clock to the AES0 Module. 0 ENABLED Enable the APB clock to the AES0 Module. 1 CRC0CEN CRC0 Clock Enable. 15 1 DISABLED Disable the APB clock to the CRC0 Module. 0 ENABLED Enable the APB clock to the CRC0 Module. 1 IDAC0CEN IDAC0 Clock Enable. 16 1 DISABLED Disable the APB clock to the IDAC0 Module. 0 ENABLED Enable the APB clock to the IDAC0 Module. 1 LPT0CEN LPT0 Clock Enable. 17 1 DISABLED Disable the APB clock to the LPTIMER0 Module. 0 ENABLED Enable the APB clock to the LPTIMER0 Module. 1 ACCTR0CEN ACCTR0 Enable. 18 1 DISABLED Disable the APB clock to the ACCTR0 Module. 0 ENABLED Enable the APB clock to the ACCTR0 Module. 1 DTM0CEN DTM0 Clock Enable. 19 1 DISABLED Disable the APB clock to the DTM0 Register interface. 0 ENABLED Enable the APB clock to the DTM0 Register interface. 1 DTM1CEN DTM1 Clock Enable. 20 1 DISABLED Disable the APB clock to the DTM1 Register interface. 0 ENABLED Enable the APB clock to the DTM1 Register interface. 1 DTM2CEN DTM2 Clock Enable. 21 1 DISABLED Disable the APB clock to the DTM2 Register interface. 0 ENABLED Enable the APB clock to the DTM2 Register interface. 1 LCD0CEN LCD0 Clock Enable. 22 1 DISABLED Disable the APB clock to the LCD0 Module. 0 ENABLED Enable the APB clock to the LCD0 Module. 1 DCDC0CEN DCDC0 Clock Enable. 23 1 DISABLED Disable the APB clock to the DCDC0 Module. 0 ENABLED Enable the APB clock to the DCDC0 Module. 1 ENCDEC0CEN ENCDEC0 Clock Enable. 24 1 DISABLED Disable the APB clock to the ENCDEC0 Module. 0 ENABLED Enable the APB clock to the ENCDEC0 Module. 1 PLL0CEN PLL0 Clock Enable. 25 1 DISABLED Disable the APB clock to the PLL0 registers. 0 ENABLED Enable the APB clock to the PLL0 registers. 1 APBCLKG1 APB Clock Gate 1 0x30 0x00000002 0xFFFFFFFF MISC0CEN Miscellaneous 0 Clock Enable. 0 1 DISABLED Disable the APB clock to the VMON0, LDO0, EXTOSC0, LPOSC0, RTC0 and RSTSRC modules. 0 ENABLED Enable the APB clock to the VMON0, LDO0, EXTOSC0, LPOSC0, RTC0 and RSTSRC modules. 1 MISC1CEN Miscellaneous 1 Clock Enable. 1 1 DISABLED Disable the APB clock to the Watchdog Timer (WDTIMER0) and DMA Crossbar (DMAXBAR0) modules. 0 ENABLED Enable the APB clock to the Watchdog Timer (WDTIMER0) and DMA Crossbar (DMAXBAR0) modules. 1 PM3CN Power Mode 3 Clock Control 0x40 0x00000000 0xFFFFFFFF PM3CSEL Power Mode 3 Fast-Wake Clock Source. 0 3 LPOSC0_DIV Power Mode 3 clock source is the Low-Power Oscillator. 0 LFOSC0 Power Mode 3 clock source is the Low-Frequency Oscillator. 1 RTC0TCLK Power Mode 3 clock source is the RTC0TCLK signal. 2 EXTOSC0 Power Mode 3 clock source is the External Oscillator. 3 VIORFCLK Power Mode 3 clock source is the VIORFCLK input pin. 4 PLL0OSC Power Mode 3 clock source is the PLL. 5 LPOSC0 Power Mode 3 clock source is a divided version of the Low-Power Oscillator. 6 PM3CEN Power Mode 3 Fast-Wake Clock Enable. 16 1 DISABLED Disable the core clock when in Power Mode 3. 0 ENABLED The core clock is enabled and runs off the clock selected by PM3CSEL in Power Mode 3. 1 CONFIG Configuration Options 0x60 0x00000000 0xFFFFFFFF PMSEL Power Mode Select. 0 1 PM8_DIS Power Mode < PM8. 0 PM8_EN Power Mode = PM8. 1 CMP_0 A None Comparator 0x4001f000 0x0 0xffc registers CMP0_IRQn 30 CONTROL Module Control 0x0 0x00000000 0xFFFFFFFF CMPFI Falling Edge Interrupt Flag. 13 1 NOT_SET No comparator falling edge has occurred since this flag was last cleared. 0 SET A comparator falling edge occurred since last flag was cleared. 1 CMPRI Rising Edge Interrupt Flag. 14 1 NOT_SET No comparator rising edge has occurred since this flag was last cleared. 0 SET A comparator rising edge occurred since last flag was cleared. 1 CMPOUT Output State. 30 1 read-only POS_LT_NEG Voltage on CMP+ < CMP- (INVEN = 0). 0 POS_GT_NEG Voltage on CMP+ > CMP- (INVEN = 0). 1 CMPEN Comparator Enable. 31 1 DISABLED Disable the comparator. 0 ENABLED Enable the comparator. 1 MODE Input and Module Mode 0x10 0x00000800 0xFFFFFFFF NMUX Negative Input Select. 0 4 CMPNN0 Select CMPnN.0 (PB0.1). 0 CMPNN1 Select CMPnN.1 (PB0.8). 1 CMPNN2 Select CMPnN.2 (PB1.1). 2 CMPNN3 Select CMPnN.3 (PB1.8). 3 CMPNN4 Select CMPnN.4 (RESERVED). 4 CMPNN5 Select CMPnN.5 (PB2.5). 5 CMPNN6 Select CMPnN.6 (PB3.3). 6 CMPNN7 Select CMPnN.7 (PB3.5). 7 CMPNN8 Select CMPnN.8 (VREF Pin). 8 CMPNN9 Select CMPnN.9 (VBAT). 9 CMPNN10 Select CMPnN.10 (VDC). 10 CMPNN11 Select CMPnN.11 (Digital LDO Output). 11 CMPNN12 Select CMPnN.12 (Memory LDO Output). 12 CMPNN13 Select CMPnN.13 (Analog LDO Output). 13 CMPNN14 Select CMPnN.14 (VIO). 14 CMPNN15 Select CMPnN.15 (RESERVED). 15 PMUX Positive Input Select. 4 4 CMPNP0 Select CMPnP.0 (PB0.0). 0 CMPNP1 Select CMPnP.1 (PB0.3). 1 CMPNP2 Select CMPnP.2 (PB1.0). 2 CMPNP3 Select CMPnP.3 (PB1.7). 3 CMPNP4 Select CMPnP.4 (PB2.0). 4 CMPNP5 Select CMPnP.5 (PB2.4). 5 CMPNP6 Select CMPnP.6 (PB3.2). 6 CMPNP7 Select CMPnP.7 (PB3.4). 7 CMPNP8 Select CMPnP.8 (VREF Pin). 8 CMPNP9 Select CMPnP.9 (RESERVED). 9 CMPNP10 Select CMPnP.10 (Temperature Sensor Output). 10 CMPNP11 Select CMPnP.11 (Charge Pump / 2). 11 CMPNP12 Select CMPnP.12 (Digital LDO Output). 12 CMPNP13 Select CMPnP.13 (Memory LDO Output). 13 CMPNP14 Select CMPnP.14 (Analog LDO Output). 14 CMPNP15 Select CMPnP.15 (RESERVED). 15 INMUX Input MUX Select. 8 2 DIRECT Connects the NMUX signal to CMP- and the PMUX signal to CMP+. 0 CMPP_VSS Connects VSS to CMP- and the PMUX signal to CMP+. 1 CMPP_DAC Connects the NMUX signal to CMP-, the PMUX signal to the Comparator DAC voltage reference, and the DAC output to CMP+. 2 CMPN_DAC Connects the PMUX signal to CMP+, the NMUX signal to the Comparator DAC voltage reference, and the DAC output to CMP-. 3 CMPMD Comparator Mode. 10 2 MODE0 Mode 0 (fastest response time, highest power consumption). 0 MODE1 Mode 1. 1 MODE2 Mode 2. 2 MODE3 Mode 3 (slowest response time, lowest power consumption). 3 FIEN Falling Edge Interrupt Enable. 13 1 DISABLED Disable the comparator falling edge interrupt. 0 ENABLED Enable the comparator falling edge interrupt. 1 RIEN Rising Edge Interrupt Enable. 14 1 DISABLED Disable the comparator rising edge interrupt. 0 ENABLED Enable the comparator rising edge interrupt. 1 DACLVL Comparator DAC Output Level. 16 6 NWPUEN Negative Input Weak Pullup Enable. 22 1 DISABLED Disable the negative input weak pull up. 0 ENABLED Enable the negative input weak pull up. 1 PWPUEN Positive Input Weak Pullup Enable. 23 1 DISABLED Disable the positive input weak pull up. 0 ENABLED Enable the positive input weak pull up. 1 CMPHYN Negative Hysteresis Control. 24 2 DISABLED Disable negative hysteresis. 0 NEG_5_MV Set negative hysteresis to 5 mV. 1 NEG_10_MV Set negative hysteresis to 10 mV. 2 NEG_20_MV Set negative hysteresis to 20 mV. 3 CMPHYP Positive Hysteresis Control. 26 2 DISABLED Disable positive hysteresis. 0 POS_5_MV Set positive hysteresis to 5 mV. 1 POS_10_MV Set positive hysteresis to 10 mV. 2 POS_20_MV Set positive hysteresis to 20 mV. 3 INVEN Invert Comparator Output Enable. 30 1 DISABLED Do not invert the comparator output. 0 ENABLED Invert the comparator output. 1 CMP_1 A None Comparator 0x40020000 0x0 0xffc registers CMP1_IRQn 31 CONTROL Module Control 0x0 0x00000000 0xFFFFFFFF CMPFI Falling Edge Interrupt Flag. 13 1 NOT_SET No comparator falling edge has occurred since this flag was last cleared. 0 SET A comparator falling edge occurred since last flag was cleared. 1 CMPRI Rising Edge Interrupt Flag. 14 1 NOT_SET No comparator rising edge has occurred since this flag was last cleared. 0 SET A comparator rising edge occurred since last flag was cleared. 1 CMPOUT Output State. 30 1 read-only POS_LT_NEG Voltage on CMP+ < CMP- (INVEN = 0). 0 POS_GT_NEG Voltage on CMP+ > CMP- (INVEN = 0). 1 CMPEN Comparator Enable. 31 1 DISABLED Disable the comparator. 0 ENABLED Enable the comparator. 1 MODE Input and Module Mode 0x10 0x00000800 0xFFFFFFFF NMUX Negative Input Select. 0 4 CMPNN0 Select CMPnN.0 (PB0.2). 0 CMPNN1 Select CMPnN.1 (RESERVED). 1 CMPNN2 Select CMPnN.2 (PB1.3). 2 CMPNN3 Select CMPnN.3 (PB1.10). 3 CMPNN4 Select CMPnN.4 (RESERVED). 4 CMPNN5 Select CMPnN.5 (PB2.7). 5 CMPNN6 Select CMPnN.6 (RESERVED). 6 CMPNN7 Select CMPnN.7 (PB3.7). 7 CMPNN8 Select CMPnN.8 (VREF Pin). 8 CMPNN9 Select CMPnN.9 (VBAT). 9 CMPNN10 Select CMPnN.10 (VDC). 10 CMPNN11 Select CMPnN.11 (Digital LDO Output). 11 CMPNN12 Select CMPnN.12 (Memory LDO Output). 12 CMPNN13 Select CMPnN.13 (Analog LDO Output). 13 CMPNN14 Select CMPnN.14 (VIO). 14 CMPNN15 Select CMPnN.15 (RESERVED). 15 PMUX Positive Input Select. 4 4 CMPNP0 Select CMPnP.0 (PB0.1). 0 CMPNP1 Select CMPnP.1 (PB0.9). 1 CMPNP2 Select CMPnP.2 (PB1.2). 2 CMPNP3 Select CMPnP.3 (PB1.9). 3 CMPNP4 Select CMPnP.4 (RESERVED). 4 CMPNP5 Select CMPnP.5 (PB2.6). 5 CMPNP6 Select CMPnP.6 (RESERVED). 6 CMPNP7 Select CMPnP.7 (PB3.6). 7 CMPNP8 Select CMPnP.8 (VREF Pin). 8 CMPNP9 Select CMPnP.9 (RESERVED). 9 CMPNP10 Select CMPnP.10 (Temperature Sensor Output). 10 CMPNP11 Select CMPnP.11 (Charge Pump / 2). 11 CMPNP12 Select CMPnP.12 (Digital LDO Output). 12 CMPNP13 Select CMPnP.13 (Memory LDO Output). 13 CMPNP14 Select CMPnP.14 (Analog LDO Output). 14 CMPNP15 Select CMPnP.15 (RESERVED). 15 INMUX Input MUX Select. 8 2 DIRECT Connects the NMUX signal to CMP- and the PMUX signal to CMP+. 0 CMPP_VSS Connects VSS to CMP- and the PMUX signal to CMP+. 1 CMPP_DAC Connects the NMUX signal to CMP-, the PMUX signal to the Comparator DAC voltage reference, and the DAC output to CMP+. 2 CMPN_DAC Connects the PMUX signal to CMP+, the NMUX signal to the Comparator DAC voltage reference, and the DAC output to CMP-. 3 CMPMD Comparator Mode. 10 2 MODE0 Mode 0 (fastest response time, highest power consumption). 0 MODE1 Mode 1. 1 MODE2 Mode 2. 2 MODE3 Mode 3 (slowest response time, lowest power consumption). 3 FIEN Falling Edge Interrupt Enable. 13 1 DISABLED Disable the comparator falling edge interrupt. 0 ENABLED Enable the comparator falling edge interrupt. 1 RIEN Rising Edge Interrupt Enable. 14 1 DISABLED Disable the comparator rising edge interrupt. 0 ENABLED Enable the comparator rising edge interrupt. 1 DACLVL Comparator DAC Output Level. 16 6 NWPUEN Negative Input Weak Pullup Enable. 22 1 DISABLED Disable the negative input weak pull up. 0 ENABLED Enable the negative input weak pull up. 1 PWPUEN Positive Input Weak Pullup Enable. 23 1 DISABLED Disable the positive input weak pull up. 0 ENABLED Enable the positive input weak pull up. 1 CMPHYN Negative Hysteresis Control. 24 2 DISABLED Disable negative hysteresis. 0 NEG_5_MV Set negative hysteresis to 5 mV. 1 NEG_10_MV Set negative hysteresis to 10 mV. 2 NEG_20_MV Set negative hysteresis to 20 mV. 3 CMPHYP Positive Hysteresis Control. 26 2 DISABLED Disable positive hysteresis. 0 POS_5_MV Set positive hysteresis to 5 mV. 1 POS_10_MV Set positive hysteresis to 10 mV. 2 POS_20_MV Set positive hysteresis to 20 mV. 3 INVEN Invert Comparator Output Enable. 30 1 DISABLED Do not invert the comparator output. 0 ENABLED Invert the comparator output. 1 DCDC_0 A None DCDC_0 0x4004e000 0x0 0xffc registers DCDC_IRQn 40 CONTROL Module Control 0x0 0x0C0C0000 0xFFFFFFFF RDYLOWF DC-DC Converter Ready Low Flag. 0 1 read-only NOT_SET The output voltage (VDC) is below the threshold set in the RDYLOWTH threshold field (RDYLOWTH). 0 SET The output voltage (VDC) is above the threshold set in the RDYLOWTH threshold field (RDYLOWTH). 1 RDYHIGHF DC-DC Converter Ready High Flag. 1 1 read-only NOT_SET The output voltage (VDC) has not exceeded 105% of the programmed output value. 0 SET The output voltage (VDC) has exceeded 105% of the programmed output value. 1 DROPOUTF DC-DC Converter Dropout Flag. 2 1 read-only NOT_SET The input voltage (VBATDC) is more than 0.4 V above the output voltage (VDC). The DC-DC converter is not in dropout. 0 SET The input voltage (VBATDC) is less than 0.4 V above the output voltage (VDC). The DC-DC converter is in dropout, and firmware should enable the bypass switch (BEN=1). 1 BGRDYF Bandgap Ready Flag. 3 1 read-only NOT_SET The bandgap voltage is not above the threshold. 0 SET The bandgap voltage is above the threshold. 1 OSCDIS Oscillator Disable. 8 1 INACTIVE Enable the DC-DC local oscillator. 0 ACTIVE Disable the DC-DC local oscillator. 1 CLKSEL Clock Source Select. 9 1 DCDCOSC Select the local DC-DC oscillator as the clock source. 0 APB Select the APB clock as the clock source. 1 CLKDIV Clock Divider. 10 3 DIV1 Use the APB clock divided by 1 as the converter switching frequency. 0 DIV2 Use the APB clock divided by 2 as the converter switching frequency. 1 DIV4 Use the APB clock divided by 4 as the converter switching frequency. 2 DIV8 Use the APB clock divided by 8 as the converter switching frequency. 3 DIV16 Use the APB clock divided by 16 as the converter switching frequency. 4 ADCSYNCEN ADC Synchronization Enable. 13 1 DISABLED Do not synchronize the ADC to the DC-DC converter. 0 ENABLED Synchronize the ADC to the DC-DC converter. 1 CLKINVEN Clock Inversion Enable. 14 1 DISABLED Do not invert the APB clock input. 0 ENABLED Invert the APB clock input. 1 ADCCLKINVEN ADC Clock Inversion Enable. 15 1 DISABLED Do not invert the ADC clock derived from the DC-DC switching frequency. 0 ENABLED Invert the ADC clock derived from the DC-DC switching frequency. 1 OUTVSEL Output Voltage Select. 16 5 MIEN Module Interrupt Enable. 22 1 DISABLED Disable DC-DC module interrupts. 0 ENABLED Enable DC-DC module interrupts. 1 MINPWSEL Minimum Pulse Width Select. 24 2 DISABLED Disable pulse skipping. 0 10_NS Set the minimum pulse width to 10 ns. 1 20_NS Set the minimum pulse width to 20 ns. 2 40_NS Set the minimum pulse width to 40 ns. 3 PSMD Power Switch Mode. 26 2 SWSEL0 Mode 0. Set the M1 and M2 power switches to each use one MOSFET only. 0 SWSEL1 Mode 1. Set the M1 and M2 power switches to each use 2 MOSFETS in parallel. 1 SWSEL2 Mode 2. Set the M1 and M2 power switches to each use 3 MOSFETS in parallel. 2 SWSEL3 Mode 3. Set the M1 and M2 power switches to each use 4 MOSFETS in parallel. 3 ASYNCEN Asynchronous Mode Enable. 28 1 DISABLED Enable DC-DC synchronous mode. 0 ENABLED Enable DC-DC asynchronous mode. This mode is more efficient for very light output loads. 1 ABEN Automatic Bypass Enable. 29 1 DISABLED Disable automatic bypass. 0 ENABLED Enable automatic bypass. 1 BEN Bypass Enable. 30 1 DISABLED Disable the MBYP bypass switch. 0 ENABLED Enable the MBYP bypass switch. 1 DCDCEN DC-DC Converter Enable. 31 1 DISABLED Disable the DC-DC converter. 0 ENABLED Enable the DC-DC converter. 1 CONFIG Module Configuration 0x10 0x00001F40 0xFFFFFFFF ILIMIT Inductor Peak Current Limit. 4 3 LIMIT1 Limit the peak inductor current to 200 mA. 1 LIMIT2 Limit the peak inductor current to 300 mA. 2 LIMIT3 Limit the peak inductor current to 400 mA. 3 LIMIT4 Limit the peak inductor current to 500 mA. 4 LIMIT5 Limit the peak inductor current to 600 mA. 5 LIMIT6 Limit the peak inductor current to 700 mA. 6 LIMIT7 Limit the peak inductor current to 800 mA. 7 INTMD Interrupt Mode. 16 2 OUTPUT_TOO_LOW Generate an interrupt when the regulated converter output voltage is too low, according to the RDYLOWF flag. 0 OUTPUT_NOT_TOO_LOW Generate an interrupt when the regulated converter output voltage is not too low according to the RDYLOWF flag. 1 OUT_OF_REG Generate an interrupt when the output voltage is out of regulation. The converter output can be either too high or too low, according to the RDYLOWF and RDYHIGHF flags. 2 IN_REG Generate an interrupt when the output voltage is in regulation. 3 RDYLOWTH Converter Ready Low Threshold. 20 2 95_PERCENT Hardware sets the RDYLOWF flag if the regulated output voltage is greater than 95% of the programmed output voltage. 0 90_PERCENT Hardware sets the RDYLOWF flag if the regulated output voltage is greater than 90% of the programmed output voltage. 1 85_PERCENT Hardware sets the RDYLOWF flag if the regulated output voltage is greater than 85% of the programmed output voltage. 2 80_PERCENT Hardware sets the RDYLOWF flag if the regulated output voltage is greater than 80% of the programmed output voltage. 3 DMACTRL_0 A None DMA 0x40036000 0x0 0xffc registers STATUS Controller Status 0x0 0x00090000 0xFFFFFFFF DMAENSTS DMA Enable Status. 0 1 read-only NOT_SET DMA controller is disabled 0 SET DMA controller is enabled. 1 STATE State Machine State. 4 4 read-only IDLE Idle. 0 READING_CHANNEL_CONFIG Reading channel controller data. 1 READING_SOURCE_POINTER Reading source data end pointer. 2 READING_DEST_POINTER Reading destination data end pointer. 3 READING_SOURCE_DATA Reading source data. 4 WRITING_DEST_DATA Writing destination data. 5 WAITING_DMA_REQ_CLEAR Waiting for a DMA request to clear. 6 WRITING_CHANNEL_CONFIG Writing channel controller data. 7 STALLED Stalled. 8 DONE Done. 9 SCATTER_GATHER_TRANSITION Peripheral scatter-gather transition. 10 NUMCHAN Number of Supported DMA Channels. 16 5 read-only CONFIG Controller Configuration 0x4 0x00000000 0xFFFFFFFF DMAEN DMA Enable. 0 1 write-only DISABLED Disable the DMA controller. 0 ENABLED Enable the DMA controller. 1 BASEPTR Base Pointer 0x8 0x00000000 0xFFFFFFFF BASEPTR Control Base Pointer. 9 23 ABASEPTR Alternate Base Pointer 0xc 0x00000100 0xFFFFFFFF ABASEPTR Alternate Control Base Pointer. 0 32 read-only CHSTATUS Channel Status 0x10 0x000003FF 0xFFFFFFFF CH0 Channel 0 Status. 0 1 read-only NOT_WAITING DMA Channel 0 is not waiting for a data request. 0 WAITING DMA Channel 0 is waiting for a data request. 1 CH1 Channel 1 Status. 1 1 read-only NOT_WAITING DMA Channel 1 is not waiting for a data request. 0 WAITING DMA Channel 1 is waiting for a data request. 1 CH2 Channel 2 Status. 2 1 read-only NOT_WAITING DMA Channel 2 is not waiting for a data request. 0 WAITING DMA Channel 2 is waiting for a data request. 1 CH3 Channel 3 Status. 3 1 read-only NOT_WAITING DMA Channel 3 is not waiting for a data request. 0 WAITING DMA Channel 3 is waiting for a data request. 1 CH4 Channel 4 Status. 4 1 read-only NOT_WAITING DMA Channel 4 is not waiting for a data request. 0 WAITING DMA Channel 4 is waiting for a data request. 1 CH5 Channel 5 Status. 5 1 read-only NOT_WAITING DMA Channel 5 is not waiting for a data request. 0 WAITING DMA Channel 5 is waiting for a data request. 1 CH6 Channel 6 Status. 6 1 read-only NOT_WAITING DMA Channel 6 is not waiting for a data request. 0 WAITING DMA Channel 6 is waiting for a data request. 1 CH7 Channel 7 Status. 7 1 read-only NOT_WAITING DMA Channel 7 is not waiting for a data request. 0 WAITING DMA Channel 7 is waiting for a data request. 1 CH8 Channel 8 Status. 8 1 read-only NOT_WAITING DMA Channel 8 is not waiting for a data request. 0 WAITING DMA Channel 8 is waiting for a data request. 1 CH9 Channel 9 Status. 9 1 read-only NOT_WAITING DMA Channel 9 is not waiting for a data request. 0 WAITING DMA Channel 9 is waiting for a data request. 1 CHSWRCN Channel Software Request Control 0x14 0x00000000 0xFFFFFFFF CH0 Channel 0 Software Request. 0 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 0 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 0 generates a software data request. 1 CH1 Channel 1 Software Request. 1 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 1 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 1 generates a software data request. 1 CH2 Channel 2 Software Request. 2 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 2 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 2 generates a software data request. 1 CH3 Channel 3 Software Request. 3 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 3 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 3 generates a software data request. 1 CH4 Channel 4 Software Request. 4 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 4 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 4 generates a software data request. 1 CH5 Channel 5 Software Request. 5 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 5 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 5 generates a software data request. 1 CH6 Channel 6 Software Request. 6 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 6 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 6 generates a software data request. 1 CH7 Channel 7 Software Request. 7 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 7 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 7 generates a software data request. 1 CH8 Channel 8 Software Request. 8 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 8 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 8 generates a software data request. 1 CH9 Channel 9 Software Request. 9 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 9 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 9 generates a software data request. 1 CHREQMSET Channel Request Mask Set 0x20 0x00000000 0xFFFFFFFF CH0 Channel 0 Request Mask Enable. 0 1 ENABLED Read: 0: DMA Channel 0 peripheral data requests enabled. 1: DMA Channel 0 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 0 peripheral data requests. 1 CH1 Channel 1 Request Mask Enable. 1 1 ENABLED Read: 0: DMA Channel 1 peripheral data requests enabled. 1: DMA Channel 1 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 1 peripheral data requests. 1 CH2 Channel 2 Request Mask Enable. 2 1 ENABLED Read: 0: DMA Channel 2 peripheral data requests enabled. 1: DMA Channel 2 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 2 peripheral data requests. 1 CH3 Channel 3 Request Mask Enable. 3 1 ENABLED Read: 0: DMA Channel 3 peripheral data requests enabled. 1: DMA Channel 3 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 3 peripheral data requests. 1 CH4 Channel 4 Request Mask Enable. 4 1 ENABLED Read: 0: DMA Channel 4 peripheral data requests enabled. 1: DMA Channel 4 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 4 peripheral data requests. 1 CH5 Channel 5 Request Mask Enable. 5 1 ENABLED Read: 0: DMA Channel 5 peripheral data requests enabled. 1: DMA Channel 5 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 5 peripheral data requests. 1 CH6 Channel 6 Request Mask Enable. 6 1 ENABLED Read: 0: DMA Channel 6 peripheral data requests enabled. 1: DMA Channel 6 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 6 peripheral data requests. 1 CH7 Channel 7 Request Mask Enable. 7 1 ENABLED Read: 0: DMA Channel 7 peripheral data requests enabled. 1: DMA Channel 7 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 7 peripheral data requests. 1 CH8 Channel 8 Request Mask Enable. 8 1 ENABLED Read: 0: DMA Channel 8 peripheral data requests enabled. 1: DMA Channel 8 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 8 peripheral data requests. 1 CH9 Channel 9 Request Mask Enable. 9 1 ENABLED Read: 0: DMA Channel 9 peripheral data requests enabled. 1: DMA Channel 9 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 9 peripheral data requests. 1 CHREQMCLR Channel Request Mask Clear 0x24 0x00000000 0xFFFFFFFF CH0 Channel 0 Request Mask Disable. 0 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 0 peripheral data requests. 1 CH1 Channel 1 Request Mask Disable. 1 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 1 peripheral data requests. 1 CH2 Channel 2 Request Mask Disable. 2 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 2 peripheral data requests. 1 CH3 Channel 3 Request Mask Disable. 3 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 3 peripheral data requests. 1 CH4 Channel 4 Request Mask Disable. 4 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 4 peripheral data requests. 1 CH5 Channel 5 Request Mask Disable. 5 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 5 peripheral data requests. 1 CH6 Channel 6 Request Mask Disable. 6 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 6 peripheral data requests. 1 CH7 Channel 7 Request Mask Disable. 7 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 7 peripheral data requests. 1 CH8 Channel 8 Request Mask Disable. 8 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 8 peripheral data requests. 1 CH9 Channel 9 Request Mask Disable. 9 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 9 peripheral data requests. 1 CHENSET Channel Enable Set 0x28 0x00000000 0xFFFFFFFF CH0 Channel 0 Enable. 0 1 ENABLED Read: 0: DMA Channel 0 disabled. 1: DMA Channel 0 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 0. 1 CH1 Channel 1 Enable. 1 1 ENABLED Read: 0: DMA Channel 1 disabled. 1: DMA Channel 1 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 1. 1 CH2 Channel 2 Enable. 2 1 ENABLED Read: 0: DMA Channel 2 disabled. 1: DMA Channel 2 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 2. 1 CH3 Channel 3 Enable. 3 1 ENABLED Read: 0: DMA Channel 3 disabled. 1: DMA Channel 3 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 3. 1 CH4 Channel 4 Enable. 4 1 ENABLED Read: 0: DMA Channel 4 disabled. 1: DMA Channel 4 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 4. 1 CH5 Channel 5 Enable. 5 1 ENABLED Read: 0: DMA Channel 5 disabled. 1: DMA Channel 5 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 5. 1 CH6 Channel 6 Enable. 6 1 ENABLED Read: 0: DMA Channel 6 disabled. 1: DMA Channel 6 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 6. 1 CH7 Channel 7 Enable. 7 1 ENABLED Read: 0: DMA Channel 7 disabled. 1: DMA Channel 7 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 7. 1 CH8 Channel 8 Enable. 8 1 ENABLED Read: 0: DMA Channel 8 disabled. 1: DMA Channel 8 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 8. 1 CH9 Channel 9 Enable. 9 1 ENABLED Read: 0: DMA Channel 9 disabled. 1: DMA Channel 9 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 9. 1 CHENCLR Channel Enable Clear 0x2c 0x00000000 0xFFFFFFFF CH0 Channel 0 Disable. 0 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 0. 1 CH1 Channel 1 Disable. 1 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 1. 1 CH2 Channel 2 Disable. 2 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 2. 1 CH3 Channel 3 Disable. 3 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 3. 1 CH4 Channel 4 Disable. 4 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 4. 1 CH5 Channel 5 Disable. 5 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 5. 1 CH6 Channel 6 Disable. 6 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 6. 1 CH7 Channel 7 Disable. 7 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 7. 1 CH8 Channel 8 Disable. 8 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 8. 1 CH9 Channel 9 Disable. 9 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 9. 1 CHALTSET Channel Alternate Select Set 0x30 0x00000000 0xFFFFFFFF CH0 Channel 0 Alternate Enable. 0 1 ENABLED Read: 0: DMA Channel 0 is using primary data structure. 1: DMA Channel 0 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 0. 1 CH1 Channel 1 Alternate Enable. 1 1 ENABLED Read: 0: DMA Channel 1 is using primary data structure. 1: DMA Channel 1 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 1. 1 CH2 Channel 2 Alternate Enable. 2 1 ENABLED Read: 0: DMA Channel 2 is using primary data structure. 1: DMA Channel 2 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 2. 1 CH3 Channel 3 Alternate Enable. 3 1 ENABLED Read: 0: DMA Channel 3 is using primary data structure. 1: DMA Channel 3 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 3. 1 CH4 Channel 4 Alternate Enable. 4 1 ENABLED Read: 0: DMA Channel 4 is using primary data structure. 1: DMA Channel 4 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 4. 1 CH5 Channel 5 Alternate Enable. 5 1 ENABLED Read: 0: DMA Channel 5 is using primary data structure. 1: DMA Channel 5 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 5. 1 CH6 Channel 6 Alternate Enable. 6 1 ENABLED Read: 0: DMA Channel 6 is using primary data structure. 1: DMA Channel 6 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 6. 1 CH7 Channel 7 Alternate Enable. 7 1 ENABLED Read: 0: DMA Channel 7 is using primary data structure. 1: DMA Channel 7 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 7. 1 CH8 Channel 8 Alternate Enable. 8 1 ENABLED Read: 0: DMA Channel 8 is using primary data structure. 1: DMA Channel 8 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 8. 1 CH9 Channel 9 Alternate Enable. 9 1 ENABLED Read: 0: DMA Channel 9 is using primary data structure. 1: DMA Channel 9 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 9. 1 CHALTCLR Channel Alternate Select Clear 0x34 0x00000000 0xFFFFFFFF CH0 Channel 0 Alternate Disable. 0 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 0. 1 CH1 Channel 1 Alternate Disable. 1 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 1. 1 CH2 Channel 2 Alternate Disable. 2 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 2. 1 CH3 Channel 3 Alternate Disable. 3 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 3. 1 CH4 Channel 4 Alternate Disable. 4 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 4. 1 CH5 Channel 5 Alternate Disable. 5 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 5. 1 CH6 Channel 6 Alternate Disable. 6 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 6. 1 CH7 Channel 7 Alternate Disable. 7 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 7. 1 CH8 Channel 8 Alternate Disable. 8 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 8. 1 CH9 Channel 9 Alternate Disable. 9 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 9. 1 CHHPSET Channel High Priority Set 0x38 0x00000000 0xFFFFFFFF CH0 Channel 0 High Priority Enable. 0 1 ENABLED Read: 0: DMA Channel 0 is using the default priority level. 1: DMA Channel 0 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 0. 1 CH1 Channel 1 High Priority Enable. 1 1 ENABLED Read: 0: DMA Channel 1 is using the default priority level. 1: DMA Channel 1 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 1. 1 CH2 Channel 2 High Priority Enable. 2 1 ENABLED Read: 0: DMA Channel 2 is using the default priority level. 1: DMA Channel 2 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 2. 1 CH3 Channel 3 High Priority Enable. 3 1 ENABLED Read: 0: DMA Channel 3 is using the default priority level. 1: DMA Channel 3 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 3. 1 CH4 Channel 4 High Priority Enable. 4 1 ENABLED Read: 0: DMA Channel 4 is using the default priority level. 1: DMA Channel 4 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 4. 1 CH5 Channel 5 High Priority Enable. 5 1 ENABLED Read: 0: DMA Channel 5 is using the default priority level. 1: DMA Channel 5 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 5. 1 CH6 Channel 6 High Priority Enable. 6 1 ENABLED Read: 0: DMA Channel 6 is using the default priority level. 1: DMA Channel 6 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 6. 1 CH7 Channel 7 High Priority Enable. 7 1 ENABLED Read: 0: DMA Channel 7 is using the default priority level. 1: DMA Channel 7 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 7. 1 CH8 Channel 8 High Priority Enable. 8 1 ENABLED Read: 0: DMA Channel 8 is using the default priority level. 1: DMA Channel 8 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 8. 1 CH9 Channel 9 High Priority Enable. 9 1 ENABLED Read: 0: DMA Channel 9 is using the default priority level. 1: DMA Channel 9 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 9. 1 CHHPCLR Channel High Priority Clear 0x3c 0x00000000 0xFFFFFFFF CH0 Channel 0 High Priority Disable. 0 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 0. 1 CH1 Channel 1 High Priority Disable. 1 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 1. 1 CH2 Channel 2 High Priority Disable. 2 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 2. 1 CH3 Channel 3 High Priority Disable. 3 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 3. 1 CH4 Channel 4 High Priority Disable. 4 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 4. 1 CH5 Channel 5 High Priority Disable. 5 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 5. 1 CH6 Channel 6 High Priority Disable. 6 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 6. 1 CH7 Channel 7 High Priority Disable. 7 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 7. 1 CH8 Channel 8 High Priority Disable. 8 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 8. 1 CH9 Channel 9 High Priority Disable. 9 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 9. 1 BERRCLR Bus Error Clear 0x4c 0x00000000 0xFFFFFFFF ERROR DMA Bus Error Clear. 0 1 CLEAR Read: 0: DMA error did not occur. 1: DMA error occurred since the last time ERROR was cleared. Write: 0: No effect. 1: Clear the DMA error flag. 1 DMAXBAR_0 A None DMA 0x40037000 0x0 0xffc registers DMAERR_IRQn 5 DMACH0_IRQn 6 DMACH1_IRQn 7 DMACH2_IRQn 8 DMACH3_IRQn 9 DMACH4_IRQn 10 DMACH5_IRQn 11 DMACH6_IRQn 12 DMACH7_IRQn 13 DMACH8_IRQn 14 DMACH9_IRQn 15 DMAXBAR0 Channel 0-7 Trigger Select 0x0 0x00000000 0xFFFFFFFF CH0SEL DMA Channel 0 Peripheral Select. 0 4 DTM0_A Service DTM0 A data requests. 0 SPI0_TX Service SPI0 TX data requests. 1 AES0_TX Service AES0 TX data requests. 2 USART0_RX Service USART0 RX data requests. 3 I2C0_RX Service I2C0 RX data requests. 4 I2C0_TX Service I2C0 TX data requests. 5 EPCA0_CAPTURE Service EPCA0 capture data requests. 6 TIMER0L Service TIMER0L overflow data requests. 7 TIMER0H Service TIMER0H overflow data requests. 8 DMA0T0_RISE Service DMA0T0 rising edge data requests. 9 DMA0T0_FALL Service DMA0T0 falling edge data requests. 10 UNASSIGNED Unassigned. 15 CH1SEL DMA Channel 1 Peripheral Select. 4 4 DTM0_B Service DTM0 B data requests. 0 SPI0_RX Service SPI0 RX data requests. 1 AES0_RX Service AES0 RX data requests. 2 USART0_TX Service USART0 TX data requests. 3 SARADC0 Service SARADC0 data requests. 4 EPCA0_CAPTURE Service EPCA0 capture data requests. 5 EPCA0_CONTROL Service EPCA0 control data requests. 6 TIMER1L Service TIMER1L overflow data requests. 7 TIMER1H Service TIMER1H overflow data requests. 8 DMA0T1_RISE Service DMA0T1 rising edge data requests. 9 DMA0T1_FALL Service DMA0T1 falling edge data requests. 10 UNASSIGNED Unassigned. 15 CH2SEL DMA Channel 2 Peripheral Select. 8 4 DTM0_C Service DTM0 C data requests. 0 DTM2_A Service DTM2 A data requests. 1 ENCDEC0_TX Service ENCDEC0 TX data requests. 2 AES0_XOR Service AES0 XOR data requests. 3 SPI1_TX Service SPI1 TX data requests. 4 USART0_RX Service USART0 RX data requests. 5 I2C0_RX Service I2C0 RX data requests. 6 IDAC0 Service IDAC0 data requests. 7 TIMER0L Service TIMER0L overflow data requests. 8 TIMER0H Service TIMER0H overflow data requests. 9 DMA0T0_RISE Service DMA0T0 rising edge data requests. 10 DMA0T0_FALL Service DMA0T0 falling edge data requests. 11 UNASSIGNED Unassigned. 15 CH3SEL DMA Channel 3 Peripheral Select. 12 4 DTM0_D Service DTM0 D data requests. 0 DTM2_B Service DTM2 B data requests. 1 ENCDEC0_RX Service ENCDEC0 RX data requests. 2 SPI1_RX Service SPI1 RX data requests. 3 USART0_TX Service USART0 TX data requests. 4 I2C0_RX Service I2C0 RX data requests. 5 I2C0_TX Service I2C0 TX data requests. 6 TIMER1L Service TIMER1L overflow data requests. 7 TIMER1H Service TIMER1H overflow data requests. 8 DMA0T1_RISE Service DMA0T1 rising edge data requests. 9 DMA0T1_FALL Service DMA0T1 falling edge data requests. 10 UNASSIGNED Unassigned. 15 CH4SEL DMA Channel 4 Peripheral Select. 16 4 DTM1_A Service DTM1 A data requests. 0 DTM2_C Service DTM2 C data requests. 1 SPI0_TX Service SPI1 TX data requests. 2 AES0_TX Service AES0 TX data requests. 3 SARADC0 Service SARADC0 data requests. 4 EPCA0_CAPTURE Service EPCA0 capture data requests. 5 EPCA0_CONTROL Service EPCA0 control data requests. 6 TIMER0L Service TIMER0L overflow data requests. 7 TIMER0H Service TIMER0H overflow data requests. 8 DMA0T0_RISE Service DMA0T0 rising edge data requests. 9 DMA0T0_FALL Service DMA0T0 falling edge data requests. 10 UNASSIGNED Unassigned. 15 CH5SEL DMA Channel 5 Peripheral Select. 20 4 DTM1_B Service DTM1 B data requests. 0 DTM2_D Service DTM2 D data requests. 1 SPI0_RX Service SPI0 RX data requests. 2 AES0_RX Service AES0 RX data requests. 3 USART0_RX Service USART0 RX data requests. 4 I2C0_RX Service I2C0 RX data requests. 5 IDAC0 Service IDAC0 data requests. 6 EPCA0_CONTROL Service EPCA0 control data requests. 7 TIMER1L Service TIMER1L overflow data requests. 8 TIMER1H Service TIMER1H overflow data requests. 9 DMA0T1_RISE Service DMA0T1 rising edge data requests. 10 DMA0T1_FALL Service DMA0T1 falling edge data requests. 11 UNASSIGNED Unassigned. 15 CH6SEL DMA Channel 6 Peripheral Select. 24 4 DTM1_C Service DTM1 C data requests. 0 DTM2_A Service DTM2 A data requests. 1 ENCDEC0_TX Service ENCDEC0 TX data requests. 2 AES0_XOR Service AES0 XOR data requests. 3 USART0_TX Service USART0 TX data requests. 4 I2C0_RX Service I2C0 RX data requests. 5 I2C0_TX Service I2C0 TX data requests. 6 SARADC0 Service SARADC0 data requests. 7 TIMER0L Service TIMER0L overflow data requests. 8 TIMER0H Service TIMER0H overflow data requests. 9 DMA0T0_RISE Service DMA0T0 rising edge data requests. 10 DMA0T0_FALL Service DMA0T0 falling edge data requests. 11 UNASSIGNED Unassigned. 15 CH7SEL DMA Channel 7 Peripheral Select. 28 4 DTM1_D Service DTM1 D data requests. 0 DTM2_B Service DTM2 B data requests. 1 ENCDEC0_RX Service ENCDEC0 RX data requests. 2 SPI1_TX Service SPI1 TX data requests. 3 USART0_RX Service USART0 RX data requests. 4 IDAC0 Service IDAC0 data requests. 5 TIMER1L Service TIMER1L overflow data requests. 6 TIMER1H Service TIMER1H overflow data requests. 7 DMA0T1_RISE Service DMA0T1 rising edge data requests. 8 DMA0T1_FALL Service DMA0T1 falling edge data requests. 9 UNASSIGNED Unassigned. 15 DMAXBAR1 Channel 8-15 Trigger Select 0x10 0x00000000 0xFFFFFFFF CH8SEL DMA Channel 8 Peripheral Select. 0 4 DTM2_C Service DTM2 C data requests. 0 SPI0_TX Service SPI0 TX data requests. 1 SPI1_RX Service SPI1 RX data requests. 2 USART0_TX Service USART0 TX data requests. 3 I2C0_RX Service I2C0 RX data requests. 4 SARADC0 Service SARADC0 data requests. 5 EPCA0_CAPTURE Service EPCA0 capture data requests. 6 TIMER0L Service TIMER0L overflow data requests. 7 TIMER0H Service TIMER0H overflow data requests. 8 DMA0T0_RISE Service DMA0T0 rising edge data requests. 9 DMA0T0_FALL Service DMA0T0 falling edge data requests. 10 UNASSIGNED Unassigned. 15 CH9SEL DMA Channel 9 Peripheral Select. 4 4 DTM2_D Service DTM2 D data requests. 0 SPI0_RX Service SPI0 TX data requests. 1 I2C0_RX Service I2C0 RX data requests. 2 I2C0_TX Service I2C0 TX data requests. 3 IDAC0 Service IDAC0 data requests. 4 EPCA0_CAPTURE Service EPCA0 capture data requests. 5 EPCA0_CONTROL Service EPCA0 control data requests. 6 TIMER1L Service TIMER1L overflow data requests. 7 TIMER1H Service TIMER1H overflow data requests. 8 DMA0T1_RISE Service DMA0T1 rising edge data requests. 9 DMA0T1_FALL Service DMA0T1 falling edge data requests. 10 UNASSIGNED Unassigned. 15 DTM_0 A None DTM 0x4004a000 0x0 0xffc registers DTM0_IRQn 32 CONTROL Module Control 0x0 0x0600FF00 0xFFFFFFFF STCOUNT Active State Counter. 0 8 ST Active State. 8 4 LASTST Last State. 12 4 read-only INHSSEL Inhibit Signal Select. 16 4 DTMNINH0 Select inhibit signal source DTMnINH.0. 0 DTMNINH1 Select inhibit signal source DTMnINH.1. 1 DTMNINH2 Select inhibit signal source DTMnINH.2. 2 DTMNINH3 Select inhibit signal source DTMnINH.3. 3 DTMNINH4 Select inhibit signal source DTMnINH.4. 4 DTMNINH5 Select inhibit signal source DTMnINH.5. 5 DTMNINH6 Select inhibit signal source DTMnINH.6. 6 DTMNINH7 Select inhibit signal source DTMnINH.7. 7 DTMNINH8 Select inhibit signal source DTMnINH.8. 8 DTMNINH9 Select inhibit signal source DTMnINH.9. 9 DTMNINH10 Select inhibit signal source DTMnINH.10. 10 DTMNINH11 Select inhibit signal source DTMnINH.11. 11 DTMNINH12 Select inhibit signal source DTMnINH.12. 12 DTMNINH13 Select inhibit signal source DTMnINH.13. 13 DTMNINH14 Select inhibit signal source DTMnINH.14. 14 DTMNINH15 Select inhibit signal source DTMnINH.15. 15 DBGMD Debug Mode. 23 1 RUN The DTM module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the DTM module to halt. 1 INHF Inhibit Status Flag. 24 1 read-only NOT_SET The inhibit signal is inactive. 0 SET The inhibit signal is active. 1 DSTREQF Destination Peripheral DMA Request Status Flag. 25 1 read-only NOT_SET The destination peripheral did not request a DMA transfer. 0 SET The destination peripheral requested a DMA transfer. 1 SRCREQF Source Peripheral DMA Request Status Flag. 26 1 read-only NOT_SET The source peripheral did not request a DMA transfer. 0 SET The source peripheral requested a DMA transfer. 1 DTMINH DTM Module Inhibit. 27 1 INACTIVE The DTM module does not ignore DMA requests. 0 ACTIVE The DTM module ignores DMA requests until this bit is cleared. 1 TOERRI Timeout Error Interrupt Flag. 28 1 NOT_SET A timeout error has not occurred. 0 SET A timeout error occurred. 1 DMAERRI DMA Error Interrupt Flag. 29 1 NOT_SET A DMA error has not occurred. 0 SET A DMA error occurred. 1 DTMI Module Interrupt Flag. 30 1 NOT_SET A state transition or timeout has not occurred. 0 SET A state transition (SECSTIEN or PRISTIEN set to 1) or timeout (TOERRIEN = 1) occurred. 1 DTMEN Module Enable. 31 1 DISABLED Disable the DTM module. 0 ENABLED Enable the DTM module. 1 TIMEOUT Module Timeout 0x10 0x00000000 0xFFFFFFFF TORELOAD Timeout Counter Reload. 0 16 TOCOUNT Timeout Counter. 16 16 MSTCOUNT Master Counter 0x20 0x00000000 0xFFFFFFFF MSTCOUNT Master Counter. 0 16 STATEADDR State Address 0x30 0x00000000 0xFFFFFFFF STATEADDR State Address. 2 30 STATE Active DTM State 0x40 0x00FFFF00 0xFFFFFFFF STRELOAD Active State Counter Reload. 0 8 read-only SECST Secondary State. 8 4 read-only PRIST Primary State. 12 4 read-only DSTMOD Destination Module. 16 4 read-only DTMNDST0 Select destination module DTMnDST.0. 0 DTMNDST1 Select destination module DTMnDST.1. 1 DTMNDST2 Select destination module DTMnDST.2. 2 DTMNDST3 Select destination module DTMnDST.3. 3 DTMNDST4 Select destination module DTMnDST.4. 4 DTMNDST5 Select destination module DTMnDST.5. 5 DTMNDST6 Select destination module DTMnDST.6. 6 DTMNDST7 Select destination module DTMnDST.7. 7 DTMNDST8 Select destination module DTMnDST.8. 8 DTMNDST9 Select destination module DTMnDST.9. 9 DTMNDST10 Select destination module DTMnDST.10. 10 DTMNDST11 Select destination module DTMnDST.11. 11 DTMNDST12 Select destination module DTMnDST.12. 12 DTMNDST13 Select destination module DTMnDST.13. 13 DTMNDST14 Select destination module DTMnDST.14. 14 DTMNDST15 Select no destination module (DTMnDST.15). 15 SRCMOD Source Module. 20 4 read-only DTMNSRC0 Select source module DTMnSRC.0. 0 DTMNSRC1 Select source module DTMnSRC.1. 1 DTMNSRC2 Select source module DTMnSRC.2. 2 DTMNSRC3 Select source module DTMnSRC.3. 3 DTMNSRC4 Select source module DTMnSRC.4. 4 DTMNSRC5 Select source module DTMnSRC.5. 5 DTMNSRC6 Select source module DTMnSRC.6. 6 DTMNSRC7 Select source module DTMnSRC.7. 7 DTMNSRC8 Select source module DTMnSRC.8. 8 DTMNSRC9 Select source module DTMnSRC.9. 9 DTMNSRC10 Select source module DTMnSRC.10. 10 DTMNSRC11 Select source module DTMnSRC.11. 11 DTMNSRC12 Select source module DTMnSRC.12. 12 DTMNSRC13 Select source module DTMnSRC.13. 13 DTMNSRC14 Select source module DTMnSRC.14. 14 DTMNSRC15 Select no source module (DTMnSRC.15). 15 DTMCHSEL DTM Channel Select. 24 2 read-only CH_A Select DTMn channel A for this state. 0 CH_B Select DTMn channel B for this state. 1 CH_C Select DTMn channel C for this state. 2 CH_D Select DTMn channel D for this state. 3 INHSPOL Inhibit Signal Polarity. 26 1 read-only ACTIVE_LOW A logic low on the pin selected by INHSEL will allow the DTM to proceed. 0 ACTIVE_HIGH A logic high on the pin selected by INHSEL will allow the DTM to proceed. 1 DTMINH Module Inhibit Enable. 27 1 read-only INACTIVE The DTM module does not ignore any DMA requests. 0 ACTIVE The DTM module ignores all DMA requests until the inhibit signal selected by INHSSEL matches the polarity polarity set by INHSPOL. 1 MSTDECEN Master Decrement Enable. 28 1 read-only DISABLED Disable master counter decrements. 0 ENABLED Enable master counter decrements. 1 TOERRIEN Timeout Enable. 29 1 read-only DISABLED Disable timeouts and timeout interrupts. 0 ENABLED Enable timeouts and timeout interrupts. 1 SECSTIEN Secondary State Transition Interrupt Enable. 30 1 read-only DISABLED Disable secondary state transition interrupts. 0 ENABLED Enable secondary state transition interrupts. 1 PRISTIEN Primary State Transition Interrupt Enable. 31 1 read-only DISABLED Disable primary state transition interrupts. 0 ENABLED Enable primary state transition interrupts. 1 DTM_1 A None DTM 0x4004b000 0x0 0xffc registers DTM1_IRQn 33 CONTROL Module Control 0x0 0x0600FF00 0xFFFFFFFF STCOUNT Active State Counter. 0 8 ST Active State. 8 4 LASTST Last State. 12 4 read-only INHSSEL Inhibit Signal Select. 16 4 DTMNINH0 Select inhibit signal source DTMnINH.0. 0 DTMNINH1 Select inhibit signal source DTMnINH.1. 1 DTMNINH2 Select inhibit signal source DTMnINH.2. 2 DTMNINH3 Select inhibit signal source DTMnINH.3. 3 DTMNINH4 Select inhibit signal source DTMnINH.4. 4 DTMNINH5 Select inhibit signal source DTMnINH.5. 5 DTMNINH6 Select inhibit signal source DTMnINH.6. 6 DTMNINH7 Select inhibit signal source DTMnINH.7. 7 DTMNINH8 Select inhibit signal source DTMnINH.8. 8 DTMNINH9 Select inhibit signal source DTMnINH.9. 9 DTMNINH10 Select inhibit signal source DTMnINH.10. 10 DTMNINH11 Select inhibit signal source DTMnINH.11. 11 DTMNINH12 Select inhibit signal source DTMnINH.12. 12 DTMNINH13 Select inhibit signal source DTMnINH.13. 13 DTMNINH14 Select inhibit signal source DTMnINH.14. 14 DTMNINH15 Select inhibit signal source DTMnINH.15. 15 DBGMD Debug Mode. 23 1 RUN The DTM module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the DTM module to halt. 1 INHF Inhibit Status Flag. 24 1 read-only NOT_SET The inhibit signal is inactive. 0 SET The inhibit signal is active. 1 DSTREQF Destination Peripheral DMA Request Status Flag. 25 1 read-only NOT_SET The destination peripheral did not request a DMA transfer. 0 SET The destination peripheral requested a DMA transfer. 1 SRCREQF Source Peripheral DMA Request Status Flag. 26 1 read-only NOT_SET The source peripheral did not request a DMA transfer. 0 SET The source peripheral requested a DMA transfer. 1 DTMINH DTM Module Inhibit. 27 1 INACTIVE The DTM module does not ignore DMA requests. 0 ACTIVE The DTM module ignores DMA requests until this bit is cleared. 1 TOERRI Timeout Error Interrupt Flag. 28 1 NOT_SET A timeout error has not occurred. 0 SET A timeout error occurred. 1 DMAERRI DMA Error Interrupt Flag. 29 1 NOT_SET A DMA error has not occurred. 0 SET A DMA error occurred. 1 DTMI Module Interrupt Flag. 30 1 NOT_SET A state transition or timeout has not occurred. 0 SET A state transition (SECSTIEN or PRISTIEN set to 1) or timeout (TOERRIEN = 1) occurred. 1 DTMEN Module Enable. 31 1 DISABLED Disable the DTM module. 0 ENABLED Enable the DTM module. 1 TIMEOUT Module Timeout 0x10 0x00000000 0xFFFFFFFF TORELOAD Timeout Counter Reload. 0 16 TOCOUNT Timeout Counter. 16 16 MSTCOUNT Master Counter 0x20 0x00000000 0xFFFFFFFF MSTCOUNT Master Counter. 0 16 STATEADDR State Address 0x30 0x00000000 0xFFFFFFFF STATEADDR State Address. 2 30 STATE Active DTM State 0x40 0x00FFFF00 0xFFFFFFFF STRELOAD Active State Counter Reload. 0 8 read-only SECST Secondary State. 8 4 read-only PRIST Primary State. 12 4 read-only DSTMOD Destination Module. 16 4 read-only DTMNDST0 Select destination module DTMnDST.0. 0 DTMNDST1 Select destination module DTMnDST.1. 1 DTMNDST2 Select destination module DTMnDST.2. 2 DTMNDST3 Select destination module DTMnDST.3. 3 DTMNDST4 Select destination module DTMnDST.4. 4 DTMNDST5 Select destination module DTMnDST.5. 5 DTMNDST6 Select destination module DTMnDST.6. 6 DTMNDST7 Select destination module DTMnDST.7. 7 DTMNDST8 Select destination module DTMnDST.8. 8 DTMNDST9 Select destination module DTMnDST.9. 9 DTMNDST10 Select destination module DTMnDST.10. 10 DTMNDST11 Select destination module DTMnDST.11. 11 DTMNDST12 Select destination module DTMnDST.12. 12 DTMNDST13 Select destination module DTMnDST.13. 13 DTMNDST14 Select destination module DTMnDST.14. 14 DTMNDST15 Select no destination module (DTMnDST.15). 15 SRCMOD Source Module. 20 4 read-only DTMNSRC0 Select source module DTMnSRC.0. 0 DTMNSRC1 Select source module DTMnSRC.1. 1 DTMNSRC2 Select source module DTMnSRC.2. 2 DTMNSRC3 Select source module DTMnSRC.3. 3 DTMNSRC4 Select source module DTMnSRC.4. 4 DTMNSRC5 Select source module DTMnSRC.5. 5 DTMNSRC6 Select source module DTMnSRC.6. 6 DTMNSRC7 Select source module DTMnSRC.7. 7 DTMNSRC8 Select source module DTMnSRC.8. 8 DTMNSRC9 Select source module DTMnSRC.9. 9 DTMNSRC10 Select source module DTMnSRC.10. 10 DTMNSRC11 Select source module DTMnSRC.11. 11 DTMNSRC12 Select source module DTMnSRC.12. 12 DTMNSRC13 Select source module DTMnSRC.13. 13 DTMNSRC14 Select source module DTMnSRC.14. 14 DTMNSRC15 Select no source module (DTMnSRC.15). 15 DTMCHSEL DTM Channel Select. 24 2 read-only CH_A Select DTMn channel A for this state. 0 CH_B Select DTMn channel B for this state. 1 CH_C Select DTMn channel C for this state. 2 CH_D Select DTMn channel D for this state. 3 INHSPOL Inhibit Signal Polarity. 26 1 read-only ACTIVE_LOW A logic low on the pin selected by INHSEL will allow the DTM to proceed. 0 ACTIVE_HIGH A logic high on the pin selected by INHSEL will allow the DTM to proceed. 1 DTMINH Module Inhibit Enable. 27 1 read-only INACTIVE The DTM module does not ignore any DMA requests. 0 ACTIVE The DTM module ignores all DMA requests until the inhibit signal selected by INHSSEL matches the polarity polarity set by INHSPOL. 1 MSTDECEN Master Decrement Enable. 28 1 read-only DISABLED Disable master counter decrements. 0 ENABLED Enable master counter decrements. 1 TOERRIEN Timeout Enable. 29 1 read-only DISABLED Disable timeouts and timeout interrupts. 0 ENABLED Enable timeouts and timeout interrupts. 1 SECSTIEN Secondary State Transition Interrupt Enable. 30 1 read-only DISABLED Disable secondary state transition interrupts. 0 ENABLED Enable secondary state transition interrupts. 1 PRISTIEN Primary State Transition Interrupt Enable. 31 1 read-only DISABLED Disable primary state transition interrupts. 0 ENABLED Enable primary state transition interrupts. 1 DTM_2 A None DTM 0x4004c000 0x0 0xffc registers DTM2_IRQn 34 CONTROL Module Control 0x0 0x0600FF00 0xFFFFFFFF STCOUNT Active State Counter. 0 8 ST Active State. 8 4 LASTST Last State. 12 4 read-only INHSSEL Inhibit Signal Select. 16 4 DTMNINH0 Select inhibit signal source DTMnINH.0. 0 DTMNINH1 Select inhibit signal source DTMnINH.1. 1 DTMNINH2 Select inhibit signal source DTMnINH.2. 2 DTMNINH3 Select inhibit signal source DTMnINH.3. 3 DTMNINH4 Select inhibit signal source DTMnINH.4. 4 DTMNINH5 Select inhibit signal source DTMnINH.5. 5 DTMNINH6 Select inhibit signal source DTMnINH.6. 6 DTMNINH7 Select inhibit signal source DTMnINH.7. 7 DTMNINH8 Select inhibit signal source DTMnINH.8. 8 DTMNINH9 Select inhibit signal source DTMnINH.9. 9 DTMNINH10 Select inhibit signal source DTMnINH.10. 10 DTMNINH11 Select inhibit signal source DTMnINH.11. 11 DTMNINH12 Select inhibit signal source DTMnINH.12. 12 DTMNINH13 Select inhibit signal source DTMnINH.13. 13 DTMNINH14 Select inhibit signal source DTMnINH.14. 14 DTMNINH15 Select inhibit signal source DTMnINH.15. 15 DBGMD Debug Mode. 23 1 RUN The DTM module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the DTM module to halt. 1 INHF Inhibit Status Flag. 24 1 read-only NOT_SET The inhibit signal is inactive. 0 SET The inhibit signal is active. 1 DSTREQF Destination Peripheral DMA Request Status Flag. 25 1 read-only NOT_SET The destination peripheral did not request a DMA transfer. 0 SET The destination peripheral requested a DMA transfer. 1 SRCREQF Source Peripheral DMA Request Status Flag. 26 1 read-only NOT_SET The source peripheral did not request a DMA transfer. 0 SET The source peripheral requested a DMA transfer. 1 DTMINH DTM Module Inhibit. 27 1 INACTIVE The DTM module does not ignore DMA requests. 0 ACTIVE The DTM module ignores DMA requests until this bit is cleared. 1 TOERRI Timeout Error Interrupt Flag. 28 1 NOT_SET A timeout error has not occurred. 0 SET A timeout error occurred. 1 DMAERRI DMA Error Interrupt Flag. 29 1 NOT_SET A DMA error has not occurred. 0 SET A DMA error occurred. 1 DTMI Module Interrupt Flag. 30 1 NOT_SET A state transition or timeout has not occurred. 0 SET A state transition (SECSTIEN or PRISTIEN set to 1) or timeout (TOERRIEN = 1) occurred. 1 DTMEN Module Enable. 31 1 DISABLED Disable the DTM module. 0 ENABLED Enable the DTM module. 1 TIMEOUT Module Timeout 0x10 0x00000000 0xFFFFFFFF TORELOAD Timeout Counter Reload. 0 16 TOCOUNT Timeout Counter. 16 16 MSTCOUNT Master Counter 0x20 0x00000000 0xFFFFFFFF MSTCOUNT Master Counter. 0 16 STATEADDR State Address 0x30 0x00000000 0xFFFFFFFF STATEADDR State Address. 2 30 STATE Active DTM State 0x40 0x00FFFF00 0xFFFFFFFF STRELOAD Active State Counter Reload. 0 8 read-only SECST Secondary State. 8 4 read-only PRIST Primary State. 12 4 read-only DSTMOD Destination Module. 16 4 read-only DTMNDST0 Select destination module DTMnDST.0. 0 DTMNDST1 Select destination module DTMnDST.1. 1 DTMNDST2 Select destination module DTMnDST.2. 2 DTMNDST3 Select destination module DTMnDST.3. 3 DTMNDST4 Select destination module DTMnDST.4. 4 DTMNDST5 Select destination module DTMnDST.5. 5 DTMNDST6 Select destination module DTMnDST.6. 6 DTMNDST7 Select destination module DTMnDST.7. 7 DTMNDST8 Select destination module DTMnDST.8. 8 DTMNDST9 Select destination module DTMnDST.9. 9 DTMNDST10 Select destination module DTMnDST.10. 10 DTMNDST11 Select destination module DTMnDST.11. 11 DTMNDST12 Select destination module DTMnDST.12. 12 DTMNDST13 Select destination module DTMnDST.13. 13 DTMNDST14 Select destination module DTMnDST.14. 14 DTMNDST15 Select no destination module (DTMnDST.15). 15 SRCMOD Source Module. 20 4 read-only DTMNSRC0 Select source module DTMnSRC.0. 0 DTMNSRC1 Select source module DTMnSRC.1. 1 DTMNSRC2 Select source module DTMnSRC.2. 2 DTMNSRC3 Select source module DTMnSRC.3. 3 DTMNSRC4 Select source module DTMnSRC.4. 4 DTMNSRC5 Select source module DTMnSRC.5. 5 DTMNSRC6 Select source module DTMnSRC.6. 6 DTMNSRC7 Select source module DTMnSRC.7. 7 DTMNSRC8 Select source module DTMnSRC.8. 8 DTMNSRC9 Select source module DTMnSRC.9. 9 DTMNSRC10 Select source module DTMnSRC.10. 10 DTMNSRC11 Select source module DTMnSRC.11. 11 DTMNSRC12 Select source module DTMnSRC.12. 12 DTMNSRC13 Select source module DTMnSRC.13. 13 DTMNSRC14 Select source module DTMnSRC.14. 14 DTMNSRC15 Select no source module (DTMnSRC.15). 15 DTMCHSEL DTM Channel Select. 24 2 read-only CH_A Select DTMn channel A for this state. 0 CH_B Select DTMn channel B for this state. 1 CH_C Select DTMn channel C for this state. 2 CH_D Select DTMn channel D for this state. 3 INHSPOL Inhibit Signal Polarity. 26 1 read-only ACTIVE_LOW A logic low on the pin selected by INHSEL will allow the DTM to proceed. 0 ACTIVE_HIGH A logic high on the pin selected by INHSEL will allow the DTM to proceed. 1 DTMINH Module Inhibit Enable. 27 1 read-only INACTIVE The DTM module does not ignore any DMA requests. 0 ACTIVE The DTM module ignores all DMA requests until the inhibit signal selected by INHSSEL matches the polarity polarity set by INHSPOL. 1 MSTDECEN Master Decrement Enable. 28 1 read-only DISABLED Disable master counter decrements. 0 ENABLED Enable master counter decrements. 1 TOERRIEN Timeout Enable. 29 1 read-only DISABLED Disable timeouts and timeout interrupts. 0 ENABLED Enable timeouts and timeout interrupts. 1 SECSTIEN Secondary State Transition Interrupt Enable. 30 1 read-only DISABLED Disable secondary state transition interrupts. 0 ENABLED Enable secondary state transition interrupts. 1 PRISTIEN Primary State Transition Interrupt Enable. 31 1 read-only DISABLED Disable primary state transition interrupts. 0 ENABLED Enable primary state transition interrupts. 1 DEVICEID_0 A None DEVICEID_0 0x400490c0 0x0 0xffc registers DEVICEID0 Device ID Word 0 0x0 0x00000001 0xFFFFFFFF REVID Revision ID. 0 4 REVA Revision A. 0 REVB Revision B. 1 REVC Revision C. 2 DEVICEID0 Device ID 0. 4 28 DEVICEID1 Device ID Word 1 0x10 0x00000000 0xFFFFFFFF DEVICEID1 Device ID 1. 0 32 DEVICEID2 Device ID Word 2 0x20 0x00000000 0xFFFFFFFF DEVICEID2 Device ID 2. 0 32 DEVICEID3 Device ID Word 3 0x30 0x00000000 0xFFFFFFFF DEVICEID3 Device ID 3. 0 32 ECRC_0 A None ECRC_0 0x40028000 0x0 0xffc registers CONTROL Module Control 0x0 0x00000002 0xFFFFFFFF SINITEN Seed Initialization Enable. 0 1 write-only DISABLED Do not initialize the CRC module to the value set by the SEED bit. 0 ENABLED Initialize the CRC module to the value set by the SEED bit. 1 SEED Seed Setting. 1 1 ALL_ZEROES CRC seed value is all 0's (0x00000000) 0 ALL_ONES CRC seed value is all 1's (0xFFFFFFFF). 1 CRCEN CRC Enable. 2 1 DISABLED Disable CRC operations. 0 ENABLED Enable CRC operations. 1 POLYSEL Polynomial Selection. 4 1 CRC32_FIXED Select the fixed 32-bit polynomial: 0x04C11DB7. 0 CRC16_PROG Select the programmable 16-bit polynomial. The POLY register sets the polynomial coefficients. 1 BMDEN Byte Mode Enable. 8 1 DISABLED Disable byte mode (word/byte width is determined automatically by the hardware). 0 ENABLED Enable byte mode (all writes are considered as bytes). 1 BBREN Byte-Level Bit Reversal Enable. 9 1 DISABLED No byte-level bit reversal (input is same order as written). 0 ENABLED Byte-level bit reversal enabled (the bits in each byte are reversed). 1 ORDER Input Processing Order. 10 2 NO_REORDER No byte reorientation (output is same order as input). 0 BIG_ENDIAN_16 Swap for 16-bit big endian order (input: B3 B2 B1 B0, output: B2 B3 B0 B1). 1 BIG_ENDIAN_32 Swap for 32-bit big endian order (input: B3 B2 B1 B0, output: B0 B1 B2 B3). 2 ASEEDEN Automatic Seed Enable. 13 1 DISABLED Disable automatic seeding. 0 ENABLED Enable automatic seeding. Reading the byte of the DATA register selected by ASEEDSEL re-seeds the CRC result with the setting selected by SEED. 1 ASEEDSEL Automatic Seed Byte Select. 14 1 LSB_READ Select a read of the least-significant byte ([7:0]) of DATA, RDATA or BRDATA for automatic re-seeding. 0 MSB_READ Select a read of the most-significant byte [31:24] for 32-bit operations, and [15:8] for 16-bit operations) of DATA, RDATA or BRDATA for automatic re-seeding. 1 POLY 16-bit Programmable Polynomial 0x10 0x00001021 0xFFFFFFFF POLY 16-bit Programmable Polynomial. 0 16 DATA Input/Result Data 0x20 0xFFFFFFFF 0xFFFFFFFF DATA Input/Result Data. 0 32 RDATA Bit-Reversed Output Data 0x30 0xFFFFFFFF 0xFFFFFFFF RDATA Bit-Reversed Output Data. 0 32 read-only BRDATA Byte-Reversed Output Data 0x40 0xFFFFFFFF 0xFFFFFFFF BRDATA Byte-Reversed Output Data. 0 32 read-only SCONTROL Bus Snooping Control 0x50 0x00000000 0xFFFFFFFF SEN Snooping Enable. 0 1 DISABLED Disable automatic bus snooping. 0 ENABLED Enable automatic bus snooping. 1 SDIRSEL Snooping Direction Select. 1 1 WRITES ECRC will snoop writes to the selected peripheral. 0 READS ECRC will snoop reads from the selected peripheral. 1 SPERISEL Snooping Peripheral Select. 4 4 SADDR Snooping Address. 18 10 ENCDEC_0 A None ENCDEC_0 0x4004f000 0x0 0xffc registers ENDEC0_IRQn 36 CONTROL Module Control 0x0 0x00000000 0xFFFFFFFF INRDYIEN Input Ready Interrupt Enable. 0 1 DISABLED Disable the input ready interrupt. 0 ENABLED Enable the input ready interrupt. 1 ORDYIEN Output Ready Interrupt Enable. 1 1 DISABLED Disable the output ready interrupt. 0 ENABLED Enable the output ready interrupt. 1 ERRIEN Error Interrupt Enable. 2 1 DISABLED Disable the error interrupt. 0 ENABLED Enable the error interrupt. 1 RESET Module Reset. 3 1 write-only ACTIVE Reset the module. 1 MOSIZE Manchester Output Size. 4 1 SMALL Manchester encode operations generate a half-word output, and decode operations generate a byte output. 0 LARGE Manchester encode operations generate a word output, and decode operations generate a half-word output. 1 EDMD Encode Decode Mode. 5 1 DECODE Decode data written to DATAIN. 0 ENCODE Encode data written to DATAIN. 1 OPMD Operation Mode. 6 1 MANCHESTER The operation selected by EDMD uses Manchester mode. 0 3OUTOF6 The operation selected by EDMD uses Three-out-of-Six mode. 1 BEN Bypass Encoder/Decoder Operation Enable. 8 1 DISABLED Do not bypass ENCDEC operations. 0 ENABLED Bypass ENCDEC operations. 1 DMAEN DMA Mode Enable. 9 1 DISABLED Disable DMA mode. 0 ENABLED Enable DMA mode. 1 DBGMD Debug Mode. 10 1 RUN The ENCDEC module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the ENCDEC module to halt. 1 OORDER Output Order Mode. 12 2 NO_CHANGE The module outputs data to DATAOUT in the same order as it was processed (input: B3 B2 B1 B0, output: B3 B2 B1 B0). 0 HALF_WORD The module flips the data in half-words before outputting to DATAOUT (input: B3 B2 B1 B0, output: B2 B3 B0 B1). 1 WORD The module flips the data in words before outputting to DATAOUT (input: B3 B2 B1 B0, output: B0 B1 B2 B3). 2 LOWER_THREE_BYTES The module flips the lower three bytes before outputting to DATAOUT (input: B3 B2 B1 B0, output: B3 B0 B1 B2). 3 IORDER Input Order Mode. 14 2 NO_CHANGE Data written to DATAIN is processed in the order written (input: B3 B2 B1 B0, output: B3 B2 B1 B0). 0 HALF_WORD The module flips the DATAIN input data in half-words (input: B2 B3 B0 B1, output: B3 B2 B1 B0). 1 WORD The module flips the DATAIN input data in words (input: B0 B1 B2 B3, output: B3 B2 B1 B0). 2 LOWER_THREE_BYTES The module flips the lower three bytes of the DATAIN input data (input: B3 B0 B1 B2, output: B3 B2 B1 B0). 3 STATUS Module Status 0x10 0x00000001 0xFFFFFFFF INRDYI Input Ready Interrupt Flag. 0 1 read-only NOT_SET The input FIFO is not ready for new data. 0 SET Firmware can write new input data to DATAIN. 1 ORDYI Output Ready Interrupt Flag. 1 1 read-only NOT_SET The output data is not ready. 0 SET The output data is ready to be read by firmware. 1 DERRI Data Error Interrupt Flag. 2 1 NOT_SET 0 SET 1 DURI Data Underrun Interrupt Flag. 3 1 NOT_SET No output data FIFO underrun. 0 SET An output data FIFO underrun has occurred. 1 DORI Data Overrun Interrupt Flag. 4 1 NOT_SET No input data FIFO overrun. 0 SET An input data FIFO overrun has occurred. 1 DATAIN Data Input 0x20 0x00000000 0xFFFFFFFF modifyExternal DATAIN Data Input. 0 32 DATAOUT Data Output 0x30 0x00000000 0xFFFFFFFF modifyExternal DATAOUT Data Output. 0 32 DATAOUTC Data Output Complement 0x40 0xFFFFFFFF 0xFFFFFFFF modifyExternal DATAOUTC Data Output Complement. 0 32 read-only EPCA_0 A None EPCA_0 0x4000e000 0x0 0xffc registers EPCA0_IRQn 23 MODE Module Operating Mode 0x180 0x01FF0000 0xFFFFFFFF CLKDIV Input Clock Divider. 0 10 CLKSEL Input Clock (F<subscript>CLKIN</subscript>) Select. 10 3 APB Set the APB as the input clock (FCLKIN). 0 TIMER0 Set Timer 0 low overflows divided by 2 as the input clock (FCLKIN). 1 HL_ECI Set high-to-low transitions on ECI divided by 2 as the input clock (FCLKIN). 2 EXTOSCN Set the external oscillator module output (EXTOSCn) divided by 2 as the input clock (FCLKIN). 3 ECI Set ECI transitions divided by 2 as the input clock (FCLKIN). 4 DEND DMA Write End Index. 16 3 LIMIT Set the last register in a DMA write transfer to LIMITUPD. 0 CH0 Set the last register in a DMA write transfer to Channel 0 CCAPVUPD. 1 CH1 Set the last register in a DMA write transfer to Channel 1 CCAPVUPD. 2 CH2 Set the last register in a DMA write transfer to Channel 2 CCAPVUPD. 3 CH3 Set the last register in a DMA write transfer to Channel 3 CCAPVUPD. 4 CH4 Set the last register in a DMA write transfer to Channel 4 CCAPVUPD. 5 CH5 Set the last register in a DMA write transfer to Channel 5 CCAPVUPD. 6 EMPTY Empty slot. 7 DPTR DMA Write Transfer Pointer. 19 3 LIMIT The DMA channel will write to LIMITUPD next. 0 CH0 The DMA channel will write to Channel 0 CCAPVUPD next. 1 CH1 The DMA channel will write to Channel 1 CCAPVUPD next. 2 CH2 The DMA channel will write to Channel 2 CCAPVUPD next. 3 CH3 The DMA channel will write to Channel 3 CCAPVUPD next. 4 CH4 The DMA channel will write to Channel 4 CCAPVUPD next. 5 CH5 The DMA channel will write to Channel 5 CCAPVUPD next. 6 EMPTY Empty slot. 7 DSTART DMA Target Start Index. 22 3 LIMIT Set the first register in a DMA write transfer to LIMITUPD. 0 CH0 Set the first register in a DMA write transfer to Channel 0 CCAPVUPD. 1 CH1 Set the first register in a DMA write transfer to Channel 1 CCAPVUPD. 2 CH2 Set the first register in a DMA write transfer to Channel 2 CCAPVUPD. 3 CH3 Set the first register in a DMA write transfer to Channel 3 CCAPVUPD. 4 CH4 Set the first register in a DMA write transfer to Channel 4 CCAPVUPD. 5 CH5 Set the first register in a DMA write transfer to Channel 5 CCAPVUPD. 6 EMPTY Empty slot. 7 DBUSYF DMA Busy Flag. 25 1 IDLE The DMA channel is not servicing an EPCA control transfer. 0 BUSY The DMA channel is busy servicing an EPCA control transfer. 1 STDOSEL Standard Port Bank Output Select. 27 2 NO_DIFF Select the non-differential channel outputs (Channels 0-5) for the standard PB pins. 0 ONE_DIFF Select the differential output from Channel 2 and non-differential outputs from Channels 0, 1, 2, and 3 for the standard PB pins. 1 TWO_DIFF Select the differential outputs from Channels 1 and 2 and non-differential outputs from Channels 0 and 1 for the standard PB pins. 2 THREE_DIFF Select three differential outputs from Channels 0, 1, and 2 for the standard PB pins. 3 CONTROL Module Control 0x190 0x00000000 0xFFFFFFFF OVFIEN EPCA Counter Overflow/Limit Interrupt Enable. 0 1 DISABLED Disable the EPCA counter overflow/limit event interrupt. 0 ENABLED Enable the EPCA counter overflow/limit event interrupt. 1 OVFDEN EPCA Counter Overflow/Limit DMA Request Enable. 1 1 DISABLED Do not request DMA data when a EPCA counter overflow/limit event occurs. 0 ENABLED Request DMA data when a EPCA counter overflow/limit event occurs. 1 OVFSEN EPCA Counter Overflow/Limit Synchronization Signal Enable. 2 1 DISABLED Do not send a synchronization signal when a EPCA counter overflow/limit event occurs. 0 ENABLED Send a synchronization signal when a EPCA counter overflow/limit event occurs. 1 NOUPD Internal Register Update Inhibit. 4 1 INACTIVE The EPCA registers will automatically load any new update values after an overflow/limit event occurs. 0 ACTIVE The EPCA registers will not load any new update values after an overflow/limit event occurs. 1 DBGMD EPCA Debug Mode. 6 1 HALT A debug breakpoint will stop the EPCA counter/timer. 0 RUN The EPCA will continue to operate while the core is halted in debug mode. 1 STSEL Synchronous Input Trigger Select. 11 2 EPCANT0 Select input trigger 0, Comparator0 output. 0 EPCANT1 Select input trigger 1, Comparator1 output. 1 EPCANT2 Select input trigger 2, Timer 0 high overflow. 2 EPCANT3 Select input trigger 3, Timer 1 high overflow. 3 STESEL Synchronous Input Trigger Edge Select. 13 1 FALLING A high-to-low transition (falling edge) on EPCAnTx will start the counter/timer. 0 RISING A low-to-high transition (rising edge) on EPCAnTx will start the counter/timer. 1 STEN Synchronous Input Trigger Enable. 14 1 DISABLED Disable the input trigger (EPCAnTx). The EPCA counter/timer will continue to run if the RUN bit is set regardless of the value on the input trigger. 0 ENABLED Enable the input trigger (EPCAnTx). If RUN is set to 1, the EPCA counter/timer will start running when the selected input trigger (STSEL) meets the criteria set by STESEL. It will not stop running if the criteria is no longer met. 1 DIVST Clock Divider Output State. 21 1 OUTPUT_HIGH The clock divider is currently in the first half-cycle. 0 OUTPUT_LOW The clock divider is currently in the second half-cycle. 1 DIV Current Clock Divider Count. 22 10 STATUS Module Status 0x1a0 0x00000000 0xFFFFFFFF C0CCI Channel 0 Capture/Compare Interrupt Flag. 0 1 NOT_SET A Channel 0 match or capture event did not occur. 0 SET A Channel 0 match or capture event occurred. 1 C1CCI Channel 1 Capture/Compare Interrupt Flag. 1 1 NOT_SET A Channel 1 match or capture event did not occur. 0 SET A Channel 1 match or capture event occurred. 1 C2CCI Channel 2 Capture/Compare Interrupt Flag. 2 1 NOT_SET A Channel 2 match or capture event did not occur. 0 SET A Channel 2 match or capture event occurred. 1 C3CCI Channel 3 Capture/Compare Interrupt Flag. 3 1 NOT_SET A Channel 3 match or capture event did not occur. 0 SET A Channel 3 match or capture event occurred. 1 C4CCI Channel 4 Capture/Compare Interrupt Flag. 4 1 NOT_SET A Channel 4 match or capture event did not occur. 0 SET A Channel 4 match or capture event occurred. 1 C5CCI Channel 5 Capture/Compare Interrupt Flag. 5 1 NOT_SET A Channel 5 match or capture event did not occur. 0 SET A Channel 5 match or capture event occurred. 1 RUN Counter/Timer Run. 6 1 STOP Stop the EPCA Counter/Timer. 0 START Start the EPCA Counter/Timer. 1 OVFI Counter/Timer Overflow/Limit Interrupt Flag. 7 1 NOT_SET An EPCA Counter/Timer overflow/limit event did not occur. 0 SET An EPCA Counter/Timer overflow/limit event occurred. 1 UPDCF Register Update Complete Flag. 8 1 EMPTY An EPCA register update completed or is not pending. 0 FULL An EPCA register update has not completed and is still pending. 1 C0IOVFI Channel 0 Intermediate Overflow Interrupt Flag. 10 1 NOT_SET Channel 0 did not count past the channel n-bit mode limit. 0 SET Channel 0 counted past the channel n-bit mode limit. 1 C1IOVFI Channel 1 Intermediate Overflow Interrupt Flag. 11 1 NOT_SET Channel 1 did not count past the channel n-bit mode limit. 0 SET Channel 1 counted past the channel n-bit mode limit. 1 C2IOVFI Channel 2 Intermediate Overflow Interrupt Flag. 12 1 NOT_SET Channel 2 did not count past the channel n-bit mode limit. 0 SET Channel 2 counted past the channel n-bit mode limit. 1 C3IOVFI Channel 3 Intermediate Overflow Interrupt Flag. 13 1 NOT_SET Channel 3 did not count past the channel n-bit mode limit. 0 SET Channel 3 counted past the channel n-bit mode limit. 1 C4IOVFI Channel 4 Intermediate Overflow Interrupt Flag. 14 1 NOT_SET Channel 4 did not count past the channel n-bit mode limit. 0 SET Channel 4 counted past the channel n-bit mode limit. 1 C5IOVFI Channel 5 Intermediate Overflow Interrupt Flag. 15 1 NOT_SET Channel 5 did not count past the channel n-bit mode limit. 0 SET Channel 5 counted past the channel n-bit mode limit. 1 COUNTER Module Counter/Timer 0x1b0 0x00000000 0xFFFFFFFF COUNTER Counter/Timer. 0 16 LIMIT Module Upper Limit 0x1c0 0x0000FFFF 0xFFFFFFFF LIMIT Upper Limit. 0 16 LIMITUPD Module Upper Limit Update Value 0x1d0 0x00000000 0xFFFFFFFF LIMITUPD Module Upper Limit Update Value. 0 16 DTIME Phase Delay Time 0x1e0 0x00000000 0xFFFFFFFF DTIMEX X Phase Delay Time. 0 8 DTIMEY Y Phase Delay Time. 8 8 DTARGET DMA Transfer Target 0x200 0x00000000 0xFFFFFFFF DTARGET DMA Transfer Target. 0 32 write-only MODE_0 Channel Capture/Compare Mode 0x0 0x00000000 0xFFFFFFFF COSEL Channel Output Function Select. 0 2 TOGGLE_OUTPUT Toggle the channel output at the next capture/compare, overflow, or intermediate event. 0 SET_OUTPUT Set the channel output at the next capture/compare, overflow, or intermediate event. 1 CLEAR_OUTPUT Clear the output at the next capture/compare, overflow, or intermediate event. 2 NO_CHANGE Capture/Compare, overflow, or intermediate events do not control the output state. 3 PWMMD PWM N-Bit Mode. 2 4 DIFGEN Differential Signal Generator Enable. 6 1 DISABLED Disable the differential signal generator. The channel will output a single non-differential output. 0 ENABLED Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH). 1 CMD Channel Operating Mode. 8 3 EDGE_PWM Configure the channel for edge-aligned PWM mode. 0 CENTER_ALIGNED_PWM Configure the channel for center-aligned PWM mode. 1 HF_SQUARE_WAVE Configure the channel for high-frequency/square-wave mode. 2 TIMER_CAPTURE Configure the channel for timer/capture mode. 3 N_BIT_PWM Configure the channel for n-bit edge-aligned PWM mode. 4 CONTROL_0 Channel Capture/Compare Control 0x10 0x00000000 0xFFFFFFFF COUTST Channel Output State. 0 1 LOW The channel output state is low. 0 HIGH The channel output state is high. 1 CPCAPEN Positive Edge Input Capture Enable. 1 1 DISABLED Disable positive-edge input capture. 0 ENABLED Enable positive-edge input capture. 1 CNCAPEN Negative Edge Input Capture Enable. 2 1 DISABLED Disable negative-edge input capture. 0 ENABLED Enable negative-edge input capture. 1 CUPDCF Channel Register Update Complete Flag. 3 1 NOT_SET A EPCA channel register update completed or is not pending. 0 SET A EPCA channel register update has not completed and is still pending. 1 YPHST Differential Y Phase State. 5 1 LOW Set the Y Phase output state to low. 0 HIGH Set the Y Phase output state to high. 1 ACTIVEPH Active Channel Select. 6 1 YACTIVE The Y Phase is active and X Phase is inactive. 0 XACTIVE The X Phase is active and Y Phase is inactive. 1 XPHST Differential X Phase State. 7 1 LOW Set the X Phase output state to low. 0 HIGH Set the X Phase output state to high. 1 CCIEN Capture/Compare Interrupt Enable. 8 1 DISABLED Disable the channel capture/compare interrupt. 0 ENABLED Enable the channel capture/compare interrupt. 1 CCDEN Capture/Compare DMA Request Enable. 9 1 DISABLED Do not request DMA data when a channel capture/compare event occurs. 0 ENABLED Request DMA data when a channel capture/compare event occurs. 1 CCSEN Capture/Compare Synchronization Signal Enable. 10 1 DISABLED Do not send a synchronization signal when a channel capture/compare event occurs. 0 ENABLED Send a synchronization signal when a channel capture/compare event occurs. 1 CIOVFIEN Intermediate Overflow Interrupt Enable. 11 1 DISABLED Disable the channel intermediate overflow interrupt. 0 ENABLED Enable the channel intermediate overflow interrupt. 1 CIOVFDEN Intermediate Overflow DMA Request Enable. 12 1 DISABLED Do not request DMA data when a channel intermediate overflow event occurs. 0 ENABLED Request DMA data when a channel intermediate overflow event occurs. 1 CIOVFSEN Intermediate Overflow Synchronization Signal Enable. 13 1 DISABLED Do not send a synchronization signal when a channel intermediate overflow event occurs. 0 ENABLED Send a synchronization signal when a channel intermediate overflow occurs. 1 CCAPV_0 Channel Compare Value 0x20 0x00000000 0xFFFFFFFF CCAPV Channel Compare Value. 0 18 CCAPVUPD_0 Channel Compare Update Value 0x30 0x00000000 0xFFFFFFFF CCAPVUPD Channel Compare Update Value. 0 18 MODE_1 Channel Capture/Compare Mode 0x40 0x00000000 0xFFFFFFFF COSEL Channel Output Function Select. 0 2 TOGGLE_OUTPUT Toggle the channel output at the next capture/compare, overflow, or intermediate event. 0 SET_OUTPUT Set the channel output at the next capture/compare, overflow, or intermediate event. 1 CLEAR_OUTPUT Clear the output at the next capture/compare, overflow, or intermediate event. 2 NO_CHANGE Capture/Compare, overflow, or intermediate events do not control the output state. 3 PWMMD PWM N-Bit Mode. 2 4 DIFGEN Differential Signal Generator Enable. 6 1 DISABLED Disable the differential signal generator. The channel will output a single non-differential output. 0 ENABLED Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH). 1 CMD Channel Operating Mode. 8 3 EDGE_PWM Configure the channel for edge-aligned PWM mode. 0 CENTER_ALIGNED_PWM Configure the channel for center-aligned PWM mode. 1 HF_SQUARE_WAVE Configure the channel for high-frequency/square-wave mode. 2 TIMER_CAPTURE Configure the channel for timer/capture mode. 3 N_BIT_PWM Configure the channel for n-bit edge-aligned PWM mode. 4 CONTROL_1 Channel Capture/Compare Control 0x50 0x00000000 0xFFFFFFFF COUTST Channel Output State. 0 1 LOW The channel output state is low. 0 HIGH The channel output state is high. 1 CPCAPEN Positive Edge Input Capture Enable. 1 1 DISABLED Disable positive-edge input capture. 0 ENABLED Enable positive-edge input capture. 1 CNCAPEN Negative Edge Input Capture Enable. 2 1 DISABLED Disable negative-edge input capture. 0 ENABLED Enable negative-edge input capture. 1 CUPDCF Channel Register Update Complete Flag. 3 1 NOT_SET A EPCA channel register update completed or is not pending. 0 SET A EPCA channel register update has not completed and is still pending. 1 YPHST Differential Y Phase State. 5 1 LOW Set the Y Phase output state to low. 0 HIGH Set the Y Phase output state to high. 1 ACTIVEPH Active Channel Select. 6 1 YACTIVE The Y Phase is active and X Phase is inactive. 0 XACTIVE The X Phase is active and Y Phase is inactive. 1 XPHST Differential X Phase State. 7 1 LOW Set the X Phase output state to low. 0 HIGH Set the X Phase output state to high. 1 CCIEN Capture/Compare Interrupt Enable. 8 1 DISABLED Disable the channel capture/compare interrupt. 0 ENABLED Enable the channel capture/compare interrupt. 1 CCDEN Capture/Compare DMA Request Enable. 9 1 DISABLED Do not request DMA data when a channel capture/compare event occurs. 0 ENABLED Request DMA data when a channel capture/compare event occurs. 1 CCSEN Capture/Compare Synchronization Signal Enable. 10 1 DISABLED Do not send a synchronization signal when a channel capture/compare event occurs. 0 ENABLED Send a synchronization signal when a channel capture/compare event occurs. 1 CIOVFIEN Intermediate Overflow Interrupt Enable. 11 1 DISABLED Disable the channel intermediate overflow interrupt. 0 ENABLED Enable the channel intermediate overflow interrupt. 1 CIOVFDEN Intermediate Overflow DMA Request Enable. 12 1 DISABLED Do not request DMA data when a channel intermediate overflow event occurs. 0 ENABLED Request DMA data when a channel intermediate overflow event occurs. 1 CIOVFSEN Intermediate Overflow Synchronization Signal Enable. 13 1 DISABLED Do not send a synchronization signal when a channel intermediate overflow event occurs. 0 ENABLED Send a synchronization signal when a channel intermediate overflow occurs. 1 CCAPV_1 Channel Compare Value 0x60 0x00000000 0xFFFFFFFF CCAPV Channel Compare Value. 0 18 CCAPVUPD_1 Channel Compare Update Value 0x70 0x00000000 0xFFFFFFFF CCAPVUPD Channel Compare Update Value. 0 18 MODE_2 Channel Capture/Compare Mode 0x80 0x00000000 0xFFFFFFFF COSEL Channel Output Function Select. 0 2 TOGGLE_OUTPUT Toggle the channel output at the next capture/compare, overflow, or intermediate event. 0 SET_OUTPUT Set the channel output at the next capture/compare, overflow, or intermediate event. 1 CLEAR_OUTPUT Clear the output at the next capture/compare, overflow, or intermediate event. 2 NO_CHANGE Capture/Compare, overflow, or intermediate events do not control the output state. 3 PWMMD PWM N-Bit Mode. 2 4 DIFGEN Differential Signal Generator Enable. 6 1 DISABLED Disable the differential signal generator. The channel will output a single non-differential output. 0 ENABLED Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH). 1 CMD Channel Operating Mode. 8 3 EDGE_PWM Configure the channel for edge-aligned PWM mode. 0 CENTER_ALIGNED_PWM Configure the channel for center-aligned PWM mode. 1 HF_SQUARE_WAVE Configure the channel for high-frequency/square-wave mode. 2 TIMER_CAPTURE Configure the channel for timer/capture mode. 3 N_BIT_PWM Configure the channel for n-bit edge-aligned PWM mode. 4 CONTROL_2 Channel Capture/Compare Control 0x90 0x00000000 0xFFFFFFFF COUTST Channel Output State. 0 1 LOW The channel output state is low. 0 HIGH The channel output state is high. 1 CPCAPEN Positive Edge Input Capture Enable. 1 1 DISABLED Disable positive-edge input capture. 0 ENABLED Enable positive-edge input capture. 1 CNCAPEN Negative Edge Input Capture Enable. 2 1 DISABLED Disable negative-edge input capture. 0 ENABLED Enable negative-edge input capture. 1 CUPDCF Channel Register Update Complete Flag. 3 1 NOT_SET A EPCA channel register update completed or is not pending. 0 SET A EPCA channel register update has not completed and is still pending. 1 YPHST Differential Y Phase State. 5 1 LOW Set the Y Phase output state to low. 0 HIGH Set the Y Phase output state to high. 1 ACTIVEPH Active Channel Select. 6 1 YACTIVE The Y Phase is active and X Phase is inactive. 0 XACTIVE The X Phase is active and Y Phase is inactive. 1 XPHST Differential X Phase State. 7 1 LOW Set the X Phase output state to low. 0 HIGH Set the X Phase output state to high. 1 CCIEN Capture/Compare Interrupt Enable. 8 1 DISABLED Disable the channel capture/compare interrupt. 0 ENABLED Enable the channel capture/compare interrupt. 1 CCDEN Capture/Compare DMA Request Enable. 9 1 DISABLED Do not request DMA data when a channel capture/compare event occurs. 0 ENABLED Request DMA data when a channel capture/compare event occurs. 1 CCSEN Capture/Compare Synchronization Signal Enable. 10 1 DISABLED Do not send a synchronization signal when a channel capture/compare event occurs. 0 ENABLED Send a synchronization signal when a channel capture/compare event occurs. 1 CIOVFIEN Intermediate Overflow Interrupt Enable. 11 1 DISABLED Disable the channel intermediate overflow interrupt. 0 ENABLED Enable the channel intermediate overflow interrupt. 1 CIOVFDEN Intermediate Overflow DMA Request Enable. 12 1 DISABLED Do not request DMA data when a channel intermediate overflow event occurs. 0 ENABLED Request DMA data when a channel intermediate overflow event occurs. 1 CIOVFSEN Intermediate Overflow Synchronization Signal Enable. 13 1 DISABLED Do not send a synchronization signal when a channel intermediate overflow event occurs. 0 ENABLED Send a synchronization signal when a channel intermediate overflow occurs. 1 CCAPV_2 Channel Compare Value 0xa0 0x00000000 0xFFFFFFFF CCAPV Channel Compare Value. 0 18 CCAPVUPD_2 Channel Compare Update Value 0xb0 0x00000000 0xFFFFFFFF CCAPVUPD Channel Compare Update Value. 0 18 MODE_3 Channel Capture/Compare Mode 0xc0 0x00000000 0xFFFFFFFF COSEL Channel Output Function Select. 0 2 TOGGLE_OUTPUT Toggle the channel output at the next capture/compare, overflow, or intermediate event. 0 SET_OUTPUT Set the channel output at the next capture/compare, overflow, or intermediate event. 1 CLEAR_OUTPUT Clear the output at the next capture/compare, overflow, or intermediate event. 2 NO_CHANGE Capture/Compare, overflow, or intermediate events do not control the output state. 3 PWMMD PWM N-Bit Mode. 2 4 DIFGEN Differential Signal Generator Enable. 6 1 DISABLED Disable the differential signal generator. The channel will output a single non-differential output. 0 ENABLED Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH). 1 CMD Channel Operating Mode. 8 3 EDGE_PWM Configure the channel for edge-aligned PWM mode. 0 CENTER_ALIGNED_PWM Configure the channel for center-aligned PWM mode. 1 HF_SQUARE_WAVE Configure the channel for high-frequency/square-wave mode. 2 TIMER_CAPTURE Configure the channel for timer/capture mode. 3 N_BIT_PWM Configure the channel for n-bit edge-aligned PWM mode. 4 CONTROL_3 Channel Capture/Compare Control 0xd0 0x00000000 0xFFFFFFFF COUTST Channel Output State. 0 1 LOW The channel output state is low. 0 HIGH The channel output state is high. 1 CPCAPEN Positive Edge Input Capture Enable. 1 1 DISABLED Disable positive-edge input capture. 0 ENABLED Enable positive-edge input capture. 1 CNCAPEN Negative Edge Input Capture Enable. 2 1 DISABLED Disable negative-edge input capture. 0 ENABLED Enable negative-edge input capture. 1 CUPDCF Channel Register Update Complete Flag. 3 1 NOT_SET A EPCA channel register update completed or is not pending. 0 SET A EPCA channel register update has not completed and is still pending. 1 YPHST Differential Y Phase State. 5 1 LOW Set the Y Phase output state to low. 0 HIGH Set the Y Phase output state to high. 1 ACTIVEPH Active Channel Select. 6 1 YACTIVE The Y Phase is active and X Phase is inactive. 0 XACTIVE The X Phase is active and Y Phase is inactive. 1 XPHST Differential X Phase State. 7 1 LOW Set the X Phase output state to low. 0 HIGH Set the X Phase output state to high. 1 CCIEN Capture/Compare Interrupt Enable. 8 1 DISABLED Disable the channel capture/compare interrupt. 0 ENABLED Enable the channel capture/compare interrupt. 1 CCDEN Capture/Compare DMA Request Enable. 9 1 DISABLED Do not request DMA data when a channel capture/compare event occurs. 0 ENABLED Request DMA data when a channel capture/compare event occurs. 1 CCSEN Capture/Compare Synchronization Signal Enable. 10 1 DISABLED Do not send a synchronization signal when a channel capture/compare event occurs. 0 ENABLED Send a synchronization signal when a channel capture/compare event occurs. 1 CIOVFIEN Intermediate Overflow Interrupt Enable. 11 1 DISABLED Disable the channel intermediate overflow interrupt. 0 ENABLED Enable the channel intermediate overflow interrupt. 1 CIOVFDEN Intermediate Overflow DMA Request Enable. 12 1 DISABLED Do not request DMA data when a channel intermediate overflow event occurs. 0 ENABLED Request DMA data when a channel intermediate overflow event occurs. 1 CIOVFSEN Intermediate Overflow Synchronization Signal Enable. 13 1 DISABLED Do not send a synchronization signal when a channel intermediate overflow event occurs. 0 ENABLED Send a synchronization signal when a channel intermediate overflow occurs. 1 CCAPV_3 Channel Compare Value 0xe0 0x00000000 0xFFFFFFFF CCAPV Channel Compare Value. 0 18 CCAPVUPD_3 Channel Compare Update Value 0xf0 0x00000000 0xFFFFFFFF CCAPVUPD Channel Compare Update Value. 0 18 MODE_4 Channel Capture/Compare Mode 0x100 0x00000000 0xFFFFFFFF COSEL Channel Output Function Select. 0 2 TOGGLE_OUTPUT Toggle the channel output at the next capture/compare, overflow, or intermediate event. 0 SET_OUTPUT Set the channel output at the next capture/compare, overflow, or intermediate event. 1 CLEAR_OUTPUT Clear the output at the next capture/compare, overflow, or intermediate event. 2 NO_CHANGE Capture/Compare, overflow, or intermediate events do not control the output state. 3 PWMMD PWM N-Bit Mode. 2 4 DIFGEN Differential Signal Generator Enable. 6 1 DISABLED Disable the differential signal generator. The channel will output a single non-differential output. 0 ENABLED Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH). 1 CMD Channel Operating Mode. 8 3 EDGE_PWM Configure the channel for edge-aligned PWM mode. 0 CENTER_ALIGNED_PWM Configure the channel for center-aligned PWM mode. 1 HF_SQUARE_WAVE Configure the channel for high-frequency/square-wave mode. 2 TIMER_CAPTURE Configure the channel for timer/capture mode. 3 N_BIT_PWM Configure the channel for n-bit edge-aligned PWM mode. 4 CONTROL_4 Channel Capture/Compare Control 0x110 0x00000000 0xFFFFFFFF COUTST Channel Output State. 0 1 LOW The channel output state is low. 0 HIGH The channel output state is high. 1 CPCAPEN Positive Edge Input Capture Enable. 1 1 DISABLED Disable positive-edge input capture. 0 ENABLED Enable positive-edge input capture. 1 CNCAPEN Negative Edge Input Capture Enable. 2 1 DISABLED Disable negative-edge input capture. 0 ENABLED Enable negative-edge input capture. 1 CUPDCF Channel Register Update Complete Flag. 3 1 NOT_SET A EPCA channel register update completed or is not pending. 0 SET A EPCA channel register update has not completed and is still pending. 1 YPHST Differential Y Phase State. 5 1 LOW Set the Y Phase output state to low. 0 HIGH Set the Y Phase output state to high. 1 ACTIVEPH Active Channel Select. 6 1 YACTIVE The Y Phase is active and X Phase is inactive. 0 XACTIVE The X Phase is active and Y Phase is inactive. 1 XPHST Differential X Phase State. 7 1 LOW Set the X Phase output state to low. 0 HIGH Set the X Phase output state to high. 1 CCIEN Capture/Compare Interrupt Enable. 8 1 DISABLED Disable the channel capture/compare interrupt. 0 ENABLED Enable the channel capture/compare interrupt. 1 CCDEN Capture/Compare DMA Request Enable. 9 1 DISABLED Do not request DMA data when a channel capture/compare event occurs. 0 ENABLED Request DMA data when a channel capture/compare event occurs. 1 CCSEN Capture/Compare Synchronization Signal Enable. 10 1 DISABLED Do not send a synchronization signal when a channel capture/compare event occurs. 0 ENABLED Send a synchronization signal when a channel capture/compare event occurs. 1 CIOVFIEN Intermediate Overflow Interrupt Enable. 11 1 DISABLED Disable the channel intermediate overflow interrupt. 0 ENABLED Enable the channel intermediate overflow interrupt. 1 CIOVFDEN Intermediate Overflow DMA Request Enable. 12 1 DISABLED Do not request DMA data when a channel intermediate overflow event occurs. 0 ENABLED Request DMA data when a channel intermediate overflow event occurs. 1 CIOVFSEN Intermediate Overflow Synchronization Signal Enable. 13 1 DISABLED Do not send a synchronization signal when a channel intermediate overflow event occurs. 0 ENABLED Send a synchronization signal when a channel intermediate overflow occurs. 1 CCAPV_4 Channel Compare Value 0x120 0x00000000 0xFFFFFFFF CCAPV Channel Compare Value. 0 18 CCAPVUPD_4 Channel Compare Update Value 0x130 0x00000000 0xFFFFFFFF CCAPVUPD Channel Compare Update Value. 0 18 MODE_5 Channel Capture/Compare Mode 0x140 0x00000000 0xFFFFFFFF COSEL Channel Output Function Select. 0 2 TOGGLE_OUTPUT Toggle the channel output at the next capture/compare, overflow, or intermediate event. 0 SET_OUTPUT Set the channel output at the next capture/compare, overflow, or intermediate event. 1 CLEAR_OUTPUT Clear the output at the next capture/compare, overflow, or intermediate event. 2 NO_CHANGE Capture/Compare, overflow, or intermediate events do not control the output state. 3 PWMMD PWM N-Bit Mode. 2 4 DIFGEN Differential Signal Generator Enable. 6 1 DISABLED Disable the differential signal generator. The channel will output a single non-differential output. 0 ENABLED Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH). 1 CMD Channel Operating Mode. 8 3 EDGE_PWM Configure the channel for edge-aligned PWM mode. 0 CENTER_ALIGNED_PWM Configure the channel for center-aligned PWM mode. 1 HF_SQUARE_WAVE Configure the channel for high-frequency/square-wave mode. 2 TIMER_CAPTURE Configure the channel for timer/capture mode. 3 N_BIT_PWM Configure the channel for n-bit edge-aligned PWM mode. 4 CONTROL_5 Channel Capture/Compare Control 0x150 0x00000000 0xFFFFFFFF COUTST Channel Output State. 0 1 LOW The channel output state is low. 0 HIGH The channel output state is high. 1 CPCAPEN Positive Edge Input Capture Enable. 1 1 DISABLED Disable positive-edge input capture. 0 ENABLED Enable positive-edge input capture. 1 CNCAPEN Negative Edge Input Capture Enable. 2 1 DISABLED Disable negative-edge input capture. 0 ENABLED Enable negative-edge input capture. 1 CUPDCF Channel Register Update Complete Flag. 3 1 NOT_SET A EPCA channel register update completed or is not pending. 0 SET A EPCA channel register update has not completed and is still pending. 1 YPHST Differential Y Phase State. 5 1 LOW Set the Y Phase output state to low. 0 HIGH Set the Y Phase output state to high. 1 ACTIVEPH Active Channel Select. 6 1 YACTIVE The Y Phase is active and X Phase is inactive. 0 XACTIVE The X Phase is active and Y Phase is inactive. 1 XPHST Differential X Phase State. 7 1 LOW Set the X Phase output state to low. 0 HIGH Set the X Phase output state to high. 1 CCIEN Capture/Compare Interrupt Enable. 8 1 DISABLED Disable the channel capture/compare interrupt. 0 ENABLED Enable the channel capture/compare interrupt. 1 CCDEN Capture/Compare DMA Request Enable. 9 1 DISABLED Do not request DMA data when a channel capture/compare event occurs. 0 ENABLED Request DMA data when a channel capture/compare event occurs. 1 CCSEN Capture/Compare Synchronization Signal Enable. 10 1 DISABLED Do not send a synchronization signal when a channel capture/compare event occurs. 0 ENABLED Send a synchronization signal when a channel capture/compare event occurs. 1 CIOVFIEN Intermediate Overflow Interrupt Enable. 11 1 DISABLED Disable the channel intermediate overflow interrupt. 0 ENABLED Enable the channel intermediate overflow interrupt. 1 CIOVFDEN Intermediate Overflow DMA Request Enable. 12 1 DISABLED Do not request DMA data when a channel intermediate overflow event occurs. 0 ENABLED Request DMA data when a channel intermediate overflow event occurs. 1 CIOVFSEN Intermediate Overflow Synchronization Signal Enable. 13 1 DISABLED Do not send a synchronization signal when a channel intermediate overflow event occurs. 0 ENABLED Send a synchronization signal when a channel intermediate overflow occurs. 1 CCAPV_5 Channel Compare Value 0x160 0x00000000 0xFFFFFFFF CCAPV Channel Compare Value. 0 18 CCAPVUPD_5 Channel Compare Update Value 0x170 0x00000000 0xFFFFFFFF CCAPVUPD Channel Compare Update Value. 0 18 LPOSC_0 A None Factory 0x40041000 0x0 0xffc registers OSCVAL Low Power Oscillator Output Value 0x0 0x00000008 0xFFFFFFFF OSCVAL Low Power Oscillator Output Value. 0 4 read-only FLASHCTRL_0 A None FLASHCTRL_0 0x4002e000 0x0 0xffc registers CONFIG Controller Configuration 0x0 0x00000720 0xFFFFFFFF SPMD Flash Speed Mode. 0 2 MODE0 Read and write the flash at speed mode 0. 0 MODE1 Read and write the flash at speed mode 1. 1 MODE2 Read and write the flash at speed mode 2. 2 MODE3 Read and write the flash at speed mode 3. 3 RDSEN Read Store Mode Enable. 4 1 DISABLED Disable read store mode. 0 ENABLED Enable read store mode. 1 DPFEN Data Prefetch Enable. 6 1 DISABLED Data accesses are excluded from the prefetch buffer. 0 ENABLED Data accesses are included in the prefetch buffer. 1 PFINH Prefetch Inhibit. 7 1 INACTIVE Any reads from flash are prefetched until the prefetch buffer is full. 0 ACTIVE Inhibit the prefetch engine. 1 SQWEN Flash Write Sequence Enable. 16 1 DISABLED Disable sequential write mode. 0 ENABLED Enable sequential write mode. 1 ERASEEN Flash Page Erase Enable. 18 1 DISABLED Writes to the WRDATA field will initiate a write to flash at the address in the WRADDR field. 0 ENABLED Writes to the WRDATA field will initiate an erase of the flash page containing the address in the WRADDR field. 1 BUFSTS Flash Buffer Status. 19 1 read-only EMPTY The flash controller write data buffer is empty. 0 FULL The flash controller write data buffer is full. 1 BUSYF Flash Operation Busy Flag. 20 1 read-only NOT_SET The flash interface is not busy. 0 SET The flash interface is busy with an operation. 1 WRADDR Flash Write Address 0xa0 0x00000000 0xFFFFFFFF WRADDR Flash Write Address. 0 32 WRDATA Flash Write Data 0xb0 0x00000000 0xFFFFFFFF WRDATA Flash Write Data. 0 32 write-only KEY Flash Modification Key 0xc0 0x00000000 0xFFFFFFFF KEY Flash Key. 0 8 MULTI_LOCK 90 INITIAL_UNLOCK 165 SINGLE_UNLOCK 241 MULTI_UNLOCK 242 TCONTROL Flash Timing Control 0xd0 0x0003005C 0xFFFFFFFF FLRTMD Flash Read Timing Mode. 6 1 SLOW Configure the flash read controller for AHB clocks below 12 MHz. 0 FAST Configure the flash read controller for AHB clocks above 12 MHz. 1 I2C_0 A None I2C_0 0x40009000 0x0 0xffc registers I2C0_IRQn 28 CONTROL Module Control 0x0 0x10000000 0xFFFFFFFF BUSYF Busy Flag. 0 1 read-only NOT_SET A transaction is not currently taking place. 0 SET A transaction is currently taking place. 1 ACK Acknowledge. 1 1 NOT_SET Read: ACK has not been received. Write: Do not send an ACK. 0 SET Read: ACK received. Write: Send an ACK. 1 ARBLF Arbitration Lost Flag. 2 1 read-only NOT_SET Arbitration lost error has not occurred. 0 SET Arbitration lost error occurred. 1 ACKRQF Acknowledge Request Flag. 3 1 read-only NOT_SET ACK has not been requested. 0 SET ACK requested. 1 STO Stop. 4 1 NOT_SET Read: A stop is not pending and a stop / repeat start has not been detected. Write: Clear the STO bit. 0 SET Read: Stop or stop / repeat start detected. This bit must be cleared by firmware. Write: Generate a stop. 1 STA Start. 5 1 NOT_SET Read: A start is not pending and a repeat start has not been detected. Write: Clear the STA bit. 0 SET Read: Start or repeat start detected. This bit must be cleared by firmware. Write: Generate a start or repeat start. 1 TXMDF Transmit Mode Flag. 6 1 read-only RECEIVE Module is in receiver mode. 0 TRANSMIT Module is in transmitter mode. 1 MSMDF Master/Slave Mode Flag. 7 1 read-only SLAVE Module is operating in Slave mode. 0 MASTER Module is operating in Master mode. 1 STOI Stop Interrupt Flag. 8 1 NOT_SET Read: A stop interrupt has not occurred. Write: Clear the stop interrupt flag (STOI). 0 SET Read: Stop interrupt detected. In Slave mode, a stop has been detected on the bus. In Master mode, a stop has been generated. Write: Force a stop interrupt. 1 ACKI Acknowledge Interrupt Flag. 9 1 NOT_SET Read: An acknowledge interrupt has not occurred. Write: Clear the acknowledge interrupt (ACKI). 0 SET Read: An acknowledge interrupt occurred. Write: Force an acknowledge interrupt. 1 RXI Receive Done Interrupt Flag. 10 1 NOT_SET Read: A receive done interrupt has not occurred. Write: Clear the receive done interrupt (RXI). 0 SET Read: Receive done interrupt occurred. Write: Force a receive done interrupt. 1 TXI Transmit Done Interrupt Flag. 11 1 NOT_SET Read: A transmit done interrupt has not occurred. Write: Clear the transmit done interrupt (TXI). 0 SET Read: Transmit done interrupt detected. If the transmit is forced to abort by a NACK response, the acknowledge interrupt (ACKI) will also be set. Write: Force a transmit done interrupt. 1 STAI Start Interrupt Flag. 12 1 NOT_SET Read: Start interrupt has not occurred. Write: Clear the start interrupt (STAI). 0 SET Read: Start or repeat start interrupt occurred. In Slave mode, a start or repeat start is detected. In Master mode, a start or repeat start has been generated. 1 ARBLI Arbitration Lost Interrupt Flag. 13 1 NOT_SET Read: An arbitration lost interrupt has not occurred. Write: Clear the arbitration lost interrupt (ARBLI). 0 SET Read: Arbitration lost interrupt detected. Write: Force an arbitration lost interrupt. 1 T0I I2C Timer Byte 0 Interrupt Flag. 14 1 NOT_SET Read: A I2C Timer Byte 0 interrupt has not occurred. Write: Clear the I2C Timer Byte 0 interrupt (T0I). 0 SET Read: I2C Timer Byte 0 overflow interrupt detected. Write: Force a I2C Timer Byte 0 interrupt. 1 T1I I2C Timer Byte 1 Interrupt Flag. 15 1 NOT_SET Read: No interrupt occurred. Write: Clear the I2C Timer Byte 1 interrupt (T1I). 0 SET Read: I2C Timer Byte 1 overflow interrupt is detected. Write: Force a I2C Timer Byte 1 interrupt. 1 T2I I2C Timer Byte 2 Interrupt Flag. 16 1 NOT_SET Read: A I2C Timer Byte 2 interrupt has not occurred. Write: Clear the I2C Timer Byte 2 interrupt (T2I). 0 SET Read: I2C Timer Byte 2 overflow interrupt detected. Write: Force a I2C Timer Byte 2 interrupt. 1 T3I I2C Timer Byte 3 Interrupt Flag. 17 1 NOT_SET Read: A I2C Timer Byte 3 interrupt or SCL low timeout has not occurred. Write: Clear the I2C Timer Byte 3 interrupt (T3I). 0 SET Read: I2C Timer Byte 3 overflow or SCL low timeout interrupt detected. Write: Force a I2C Timer Byte 3 interrupt. 1 RXARM Receive Arm. 18 1 DISABLED Disable data and address reception. 0 ENABLED Enable the module to perform a receive operation. 1 TXARM Transmit Arm. 19 1 DISABLED Disable data and address transmission. 0 ENABLED Enable the module to perform a transmit operation. 1 SLVAF Slave Address Type Flag. 20 1 read-only SLAVE_ADDRESS Slave address detected. 0 GENERAL_CALL General Call address detected. 1 ATXRXEN Auto Transmit or Receive Enable. 21 1 DISABLED Do not automatically switch to transmit or receive mode after a Start. 0 ENABLED If automatic hardware acknowledge mode is enabled (HACKEN = 1), automatically switch to transmit or receive mode after a Start. 1 FMD Filter Mode. 22 1 DISABLED Disable the input filter. 0 ENABLED Enable the input filter. 1 DBGMD I2C Debug Mode. 23 1 RUN The I2C module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the I2C module to halt. 1 SMINH Slave Mode Inhibit. 24 1 INACTIVE Enable Slave modes. 0 ACTIVE Inhibit Slave modes. The module will not respond to a Master on the bus. 1 HACKEN Auto Acknowledge Enable . 25 1 DISABLED Disable automatic hardware acknowledge. 0 ENABLED Enable automatic hardware acknowledge. 1 LBACKEN Last Byte Acknowledge Enable. 27 1 DISABLED NACK after the last byte is received. 0 ENABLED ACK after the last byte is received. 1 GCEN General Call Address Enable. 29 1 DISABLED Disable General Call address decoding. 0 ENABLED Enable General Call address decoding. 1 RESET Module Soft Reset. 30 1 INACTIVE I2C module is not in soft reset. 0 ACTIVE I2C module is in soft reset and firmware cannot access all bits in the module. 1 I2CEN I2C Enable. 31 1 DISABLED Disable the I2C module. 0 ENABLED Enable the I2C module. 1 CONFIG Module Configuration 0x10 0x00000000 0xFFFFFFFF SCALER I2C Clock Scaler. 0 6 STOIEN Stop Interrupt Enable. 8 1 DISABLED Disable the stop interrupt. 0 ENABLED Enable the stop interrupt (STOI). 1 ACKIEN Acknowledge Interrupt Enable. 9 1 DISABLED Disable the acknowledge interrupt. 0 ENABLED Enable the acknowledge interrupt (ACKI). 1 RXIEN Receive Done Interrupt Enable. 10 1 DISABLED Disable the receive done interrupt. 0 ENABLED Enable the receive done interrupt (RXI). 1 TXIEN Transmit Done Interrupt Enable. 11 1 DISABLED Disable the transmit done interrupt. 0 ENABLED Enable the transmit done interrupt (TXI). 1 STAIEN Start Interrupt Enable. 12 1 DISABLED Disable the start interrupt. 0 ENABLED Enable the start interrupt (STAI). 1 ARBLIEN Arbitration Lost Interrupt Enable. 13 1 DISABLED Disable the arbitration lost interrupt. 0 ENABLED Enable the arbitration lost interrupt (ARBLI). 1 T0IEN I2C Timer Byte 0 Interrupt Enable. 14 1 DISABLED Disable the I2C Timer Byte 0 interrupt. 0 ENABLED Enable the I2C Timer Byte 0 interrupt (T0I). 1 T1IEN I2C Timer Byte 1 Interrupt Enable. 15 1 DISABLED Disable the I2C Timer Byte 1 interrupt. 0 ENABLED Enable the I2C Timer Byte 1 interrupt (T1I). 1 T2IEN I2C Timer Byte 2 Interrupt Enable. 16 1 DISABLED Disable the I2C Timer Byte 2 interrupt. 0 ENABLED Enable the I2C Timer Byte 2 interrupt (T2I). 1 T3IEN I2C Timer Byte 3 Interrupt Enable. 17 1 DISABLED Disable the I2C Timer Byte 3 and SCL low timeout interrupt. 0 ENABLED Enable the I2C Timer Byte 3 and SCL low timeout interrupt (T3I). 1 BC Transfer Byte Count. 20 2 BP Transfer Byte Pointer. 22 2 read-only T0RUN I2C Timer Byte 0 Run. 24 1 STOP Stop Timer Byte 0. 0 START Start Timer Byte 0 running. 1 T1RUN I2C Timer Byte 1 Run. 25 1 STOP Stop Timer Byte 1. 0 START Start Timer Byte 1 running. 1 T2RUN I2C Timer Byte 2 Run. 26 1 STOP Stop Timer Byte 2. 0 START Start Timer Byte 2 running. 1 T3RUN I2C Timer Byte 3 Run. 27 1 STOP Stop Timer Byte 3. 0 START Start Timer Byte 3 running. 1 TMD I2C Timer Mode. 28 2 MODE0 I2C Timer Mode 0: Operate the I2C timer as a single 32-bit timer : Timer Bytes [3 : 2 : 1 : 0]. 0 MODE1 I2C Timer Mode 1: Operate the I2C timer as two 16-bit timers : Timer Bytes [3 : 2] and Timer Bytes [1 : 0]. 1 MODE2 I2C Timer Mode 2: Operate the I2C timer as four independent 8-bit timers : Timer Byte 3, Timer Byte 2, Timer Byte 1, and Timer Byte 0. 2 MODE3 I2C Timer Mode 3: Operate the I2C timer as one 16-bit and two 8-bit timers : Timer Bytes [3 : 2], Timer Byte 1, and Timer Byte 0. 3 TIMEREN I2C Timer Enable. 31 1 DISABLED Disable I2C Timer. 0 ENABLED Enable I2C Timer for general purpose use. This setting should not be used when the I2C module is enabled (I2CEN = 1). 1 SADDRESS Slave Address 0x20 0x00000000 0xFFFFFFFF ADDRESS Slave Address. 1 7 SMASK Slave Address Mask 0x30 0x00000000 0xFFFFFFFF MASK Slave Address Mask. 1 7 DATA Data Buffer Access 0x40 0x00000000 0xFFFFFFFF DATA Data. 0 32 TIMER Timer Data 0x50 0x00000000 0xFFFFFFFF T0 Timer Byte 0. 0 8 T1 Timer Byte 1. 8 8 T2 Timer Byte 2. 16 8 T3 Timer Byte 3. 24 8 TIMERRL Timer Reload Values 0x60 0x00000000 0xFFFFFFFF T0RL Timer Byte 0 Reload / Bus Free Timeout. 0 8 T1RL Timer Byte 1 Reload / SCL High Time. 8 8 T2RL Timer Byte 2 Reload / SCL Low Timeout Bits [11:4]. 16 8 T3RL Timer Byte 3 Reload / SCL Low Timeout Bits [19:12]. 24 8 SCONFIG SCL Signal Configuration 0x70 0x00000000 0xFFFFFFFF SETUP Data Setup Time Extension. 0 4 HOLD Data Hold Time Extension. 4 4 SCLL SCL Low Time. 8 8 SCLLTIMER SCL Low Timeout Bits [3:0]. 16 4 read-only I2CDMA DMA Configuration 0x80 0x00000000 0xFFFFFFFF DMALEN DMA Transfer Length. 0 8 DMAEN DMA Mode Enable. 31 1 DISABLED Disable I2C DMA data requests. 0 ENABLED Enable I2C DMA data requests. 1 IDAC_0 A None IDAC_0 0x40031000 0x0 0xffc registers IDAC0_IRQn 42 CONTROL Module Control 0x0 0x00000007 0xFFFFFFFF OUPDT Output Update Trigger. 0 3 DACNT8 The IDAC output updates using the DACnT8 (Timer 0 Low Overflow) trigger source. 0 DACNT9 The IDAC output updates using the DACnT9 (Timer 0 High Overflow) trigger source. 1 DACNT10 The IDAC output updates using the DACnT10 (Timer 1 Low Overflow) trigger source. 2 DACNT11 The IDAC output updates using the DACnT11 (Timer 1 High Overflow) trigger source. 3 DACNT12 The IDAC output updates on the rising edge of the trigger source selected by ETRIG. 4 DACNT13 The IDAC output updates on the falling edge of the trigger source selected by ETRIG. 5 DACNT14 The IDAC output updates on any edge of the trigger source selected by ETRIG. 6 DACNT15 The IDAC output updates on write to DATA register (On Demand). 7 ETRIG Edge Trigger Source Select. 3 3 DACNT0 Select DACnT0 (DAC0T0 routed through crossbar) as the IDAC external trigger source. 0 DACNT1 Select DACnT1 (RESERVED) as the IDAC external trigger source. 1 DACNT2 Select DACnT2 (RESERVED) as the IDAC external trigger source. 2 DACNT3 Select DACnT3 (RESERVED) as the IDAC external trigger source. 3 DACNT4 Select DACnT4 (RESERVED) as the IDAC external trigger source. 4 DACNT5 Select DACnT5 (RESERVED) as the IDAC external trigger source. 5 DACNT6 Select DACnT6 (RESERVED) as the IDAC external trigger source. 6 DACNT7 Select DACnT7 (RESERVED) as the IDAC external trigger source. 7 OUTMD Output Mode. 6 2 0P5_MA The full-scale output current is 0.5 mA. 0 1_MA The full-scale output current is 1 mA. 1 2_MA The full-scale output current is 2 mA. 2 INFMT Data Input Format. 8 2 1_10_BIT Writes are interpreted as one 10-bit sample. 0 2_10_BIT Writes are interpreted as two 10-bit samples. 1 4_8_BIT Writes are interpreted as four 8-bit samples. 2 DMARUN DMA Run. 10 1 DISABLED Read: No DMA operations are occurring or the DMA is done. Write: No effect. 0 ENABLED Read: A DMA operation is currently in progress. Write: Start a DMA operation. 1 JSEL Data Justification Select. 11 1 RIGHT Data is right-justified. 0 LEFT Data is left-justified. 1 BUFRESET Data Buffer Reset. 12 1 write-only RESET Initiate a data buffer reset. 1 TRIGINH Trigger Source Inhibit. 13 1 INACTIVE The selected trigger source will cause the IDAC output to update. 0 ACTIVE The selected trigger source will not update the IDAC output, except for On-Demand DATA writes. 1 WRAPEN Wrap Mode Enable. 16 1 DISABLED The IDAC will not wrap when it reaches the end of the data buffer. 0 ENABLED The IDAC will cycle through the data buffer contents. 1 ORIEN FIFO Overrun Interrupt Enable. 20 1 DISABLED Disable the FIFO overrun interrupt (ORI). 0 ENABLED Enable the FIFO overrun interrupt (ORI). 1 URIEN FIFO Underrun Interrupt Enable. 21 1 DISABLED Disable the FIFO underrun interrupt (URI). 0 ENABLED Enable the FIFO underrun interrupt (URI). 1 WEIEN FIFO Went Empty Interrupt Enable. 22 1 DISABLED Disable the FIFO went empty interrupt (WEI). 0 ENABLED Enable the FIFO went empty interrupt (WEI). 1 DBGMD IDAC Debug Mode. 29 1 RUN The IDAC module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the IDAC module to halt (ignore update triggers). 1 LOADEN Load Resistor Enable. 30 1 DISABLED Disable the internal load resistor. 0 ENABLED Enable the internal load resistor. 1 IDACEN IDAC Enable. 31 1 DISABLED Disable the IDAC. 0 ENABLED Enable the IDAC. 1 DATA Output Data 0x10 0x00000000 0xFFFFFFFF DATA Output Data. 0 32 BUFSTATUS FIFO Buffer Status 0x20 0x00000000 0xFFFFFFFF LEVEL FIFO Level. 0 3 read-only EMPTY The data FIFO is empty. 0 1WORD The data FIFO contains one word. 1 2WORDS The data FIFO contains two words. 2 3WORDS The data FIFO contains three words. 3 4WORDS The data FIFO is full and contains four words. 4 ORI FIFO Overrun Interrupt Flag. 4 1 NOT_SET Read: A FIFO overrun has not occurred. Write: Clear the interrupt. 0 SET Read: A FIFO overrun occurred. Write: Force a FIFO overrun interrupt. 1 URI FIFO Underrun Interrupt Flag. 5 1 NOT_SET Read: A FIFO underrun has not occurred. Write: Clear the interrupt. 0 SET Read: A FIFO underrun occurred. Write: Force a FIFO underrun interrupt. 1 WEI FIFO Went Empty Interrupt Flag. 6 1 NOT_SET Read: A FIFO went empty condition has not occurred. Write: Clear the interrupt. 0 SET Read: The FIFO is empty. Write: Force a FIFO went empty interrupt. 1 BUFFER10 FIFO Buffer Entries 0 and 1 0x30 0x00000000 0xFFFFFFFF BUFFER0 FIFO Buffer Entry 0. 0 16 read-only BUFFER1 FIFO Buffer Entry 1. 16 16 read-only BUFFER32 FIFO Buffer Entries 2 and 3 0x40 0x00000000 0xFFFFFFFF BUFFER2 FIFO Buffer Entry 2. 0 16 read-only BUFFER3 FIFO Buffer Entry 3. 16 16 read-only GAINADJ Output Current Gain Adjust 0x50 0x0000000D 0xFFFFFFFF GAINADJ Output Current Gain Adjust. 0 5 LCD_0 A None LCD_0 0x4004d000 0x0 0xffc registers CONFIG Configuration 0x0 0x00180000 0xFFFFFFFF LCDEN Module Enable. 0 1 DISABLED Disable the LCD module. 0 ENABLED Enable the LCD module. 1 CPFPDEN Charge Pump Full Power Drive Mode Enable. 2 1 DISABLED Disable the LCD charge pump's full power drive mode. The charge pump draws less power but operates with reduced output current capabilities. 0 ENABLED Enable the LCD charge pump's full output drive mode. The charge pump operates at full power. 1 MCDEN LCD Missing Clock Detector Enable. 3 1 DISABLED Disable the dedicated LCD missing clock detector. 0 ENABLED Enable the dedicated LCD missing clock detector. 1 RTCCEN RTC Clock Request Enable. 4 1 DISABLED The LCD module does not require the RTC clock. 0 ENABLED The LCD module requires an active and valid RTC clock (RTC0TCLK). 1 BIASEN Bias Enable. 5 1 DISABLED Disable the LCD bias current. 0 ENABLED Enable the LCD bias current. 1 DCDCBIASEN DCDC Bias Output Enable. 6 1 DISABLED Disable the secondary bias current output. 0 ENABLED Enable the secondary bias current output. 1 DCDCSTDBYEN DCDC Bias Standby Enable. 7 1 DISABLED The DCDC bias is enabled in Power Mode 8. 0 ENABLED The DCDC bias is disabled in Power Mode 8. 1 CPBEN Charge Pump Bypass Enable. 8 1 DISABLED The LCD charge pump generates the VLCD voltage. 0 ENABLED Bypass the LCD charge pump and connect VLCD directly to VBAT. 1 HCVLPMEN High-Contrast-Voltage Low-Power Mode Enable. 9 1 DISABLED Disable the high-contrast-voltage low-power mode. 0 ENABLED Enable the high-contrast-voltage low-power mode. This mode reduces power consumption when VLCD is higher than VBAT. 1 VBMLPEN VBAT Monitor Low Power Enable. 10 1 DISABLED Disable the LCD VBAT Monitor low power mode. 0 ENABLED Enable the LCD VBAT Monitor low power mode. 1 CPOLPEN Charge-Pump Oscillator Low-Power Enable. 11 1 DISABLED Disable the charge-pump oscillator low-power mode. 0 ENABLED Enable the charge-pump oscillator low-power mode. 1 CMPBLPEN Comparator Buffer Low-Power Enable. 12 1 DISABLED Disable the comparator buffer low-power mode. 0 ENABLED Enable the comparator buffer low-power mode. 1 BIASSEN Bias Switching Enable. 13 1 DISABLED Disable bias switching. 0 ENABLED Enable bias switching. 1 RBGSEN Reference Band Gap Switching Enable. 14 1 DISABLED Disable reference band gap switching mode. 0 ENABLED Enable reference band gap switching mode. 1 CPACEN Charge-Pump Auto-Contrast Enable. 16 1 DISABLED VLCD continues to track VBAT when VBAT drops below the programmed VLCD value. 0 ENABLED The module automatically enables the charge pump and maintains the VLCD voltage when VBAT drops below the programmed VBAT monitor level. 1 FBIASCEN Force Bias Continuous Mode Enable. 17 1 DISABLED The bias operates as configured. 0 ENABLED Force the bias to operate in continuous mode. The bias will cleanly transition from its configuration settings to continuous mode. 1 HCVCBYPEN High-Contrast-Voltage Comparator Bypass Enable. 24 1 DISABLED Hardware enables the high-contrast-voltage comparator as needed. 0 ENABLED High-contrast-voltage comparator in bypass mode. 1 HCVCFOEN High-Contrast-Voltage Comparator Force On Enable. 25 1 DISABLED Hardware enables the high-contrast-voltage comparator as needed. 0 ENABLED High-contrast-voltage comparator force on enabled. 1 HCVCHMD High-Contrast-Voltage Comparator Hysteresis. 26 1 HIGH Set the high-contrast-voltage comparator to high-hysteresis mode. This is the recommended setting. 0 LOW Set the high-contrast-voltage comparator to low-hysteresis mode. 1 HCVCBMD High-Contrast-Voltage Comparator Bias. 27 1 HIGH Set the high-contrast-voltage comparator to high bias mode. 0 LOW Set the high-contrast-voltage comparator to low-bias mode. This is the recommended setting. 1 CPCS High-Contrast-Voltage Comparator Status. 30 1 read-only VBAT VBAT is greater than VLCD. 0 VLCD VLCD is greater than VBAT. 1 CLKCONTROL Clock Control 0x20 0x04A8FC00 0xFFFFFFFF CLKDIV Clock Divider. 0 10 RTCCLKDIV RTC Input Clock Divider. 28 2 DIVIDE_BY_1 0 DIVIDE_BY_2 1 DIVIDE_BY_4 2 DIVIDE_BY_8 3 BLKCONTROL Blinking Control 0x30 0x00000000 0xFFFFFFFF BLKMASK Hardware Blinking Enable. 0 8 BLKREXP Hardware Blinking Rate Divider Exponent. 8 4 DIVIDE_BY_2 Set blink rate divider to divide by 2. 2 DIVIDE_BY_4 Set blink rate divider to divide by 4. 3 DIVIDE_BY_8 Set blink rate divider to divide by 8. 4 DIVIDE_BY_16 Set blink rate divider to divide by 16. 5 DIVIDE_BY_32 Set blink rate divider to divide by 32. 6 DIVIDE_BY_64 Set blink rate divider to divide by 64. 7 DIVIDE_BY_128 Set blink rate divider to divide by 128. 8 DIVIDE_BY_256 Set blink rate divider to divide by 256. 9 DIVIDE_BY_512 Set blink rate divider to divide by 512. 10 DIVIDE_BY_1024 Set blink rate divider to divide by 1024. 11 DIVIDE_BY_2048 Set blink rate divider to divide by 2048. 12 DIVIDE_BY_4096 Set blink rate divider to divide by 4096. 13 SEGCONTROL Segment Control 0x40 0x00000080 0xFFFFFFFF BIASMD Hardware Bias Mode. 0 1 ONE_THIRD Select 1/3 bias. Use for three-mux segment mode and four-mux segment mode. 0 ONE_HALF Select 1/2 bias. Use for two-mux segment mode. 1 SEGMD Segment Mode. 1 2 STATIC Select static segment mode with one common COMn.0 used. 0 2_MUX Select two-mux segment mode with two commons (COMn.0 and COMn.1) used. 1 3_MUX Select three-mux segment mode with three commons (COMn.0, COMn.1, COMn.2) used. 2 4_MUX Select four-mux segment mode with four commons (COMn.0, COMn.1, COMn.2 and COMn.3) used. 3 BLANKEN Segment Blank Enable. 4 1 DISABLED Operate segments normally. 0 ENABLED Blank the LCD by disabling all LCD segment and common pins. 1 RPHEN Reset Phase Enable. 5 1 DISABLED Hardware switches the LCD segment and common pin controls directly from one state to another. 0 ENABLED Hardware switches the LCD segment and common pin controls to intermediate states for several RTC clock cycles before switching to the next state. 1 RPHMD Reset Phase Mode. 6 3 CTRSTCONTROL Contrast Control 0x60 0x32800000 0xFFFFFFFF CTRST Contrast Voltage. 0 5 CTRSTBF Contrast Busy Flag. 16 1 read-only NOT_SET An update of the internal contrast registers is not in progress. 0 SET The internal contrast registers are busy updating. 1 CPCDEN Charge Pump Capacitor Divider Enable. 29 1 DISABLED Disable the charge pump capacitor divider. 0 ENABLED Enable the charge pump capacitor divider. 1 VBMCONTROL VBAT Monitor Control 0x70 0x22C00000 0xFFFFFFFF VBMTH VBAT Monitor Threshold. 0 5 VBMBF VBAT Monitor Busy Flag. 16 1 read-only NOT_SET An update of the internal VBAT monitor registers is not in progress. 0 SET The internal VBAT monitor registers are busy updating. 1 VBMCLKDIV VBAT Monitor Clock Divider. 22 3 VBMCDEN VBAT Monitor Capacitor Divider Enable. 29 1 DISABLED Disable the VBAT monitor capacitor divider. 0 ENABLED Enable the VBAT monitor capacitor divider. 1 VBMOEN VBAT Monitor Offset Enable. 30 1 DISABLED The VBAT monitor threshold set by the VBMTH field functions as an absolute threshold value for the VBAT monitor. 0 ENABLED The VBAT monitor threshold set by the VBMTH field functions as an offset to the LCD contrast value set by CTRSTMD. 1 VBMEN VBAT Monitor Enable. 31 1 DISABLED Disable the VBAT monitor. 0 ENABLED Enable the VBAT monitor. 1 SEGMASK0 Segment Mask 0 0x80 0x00000000 0xFFFFFFFF SEGEN Segment Enable. 0 32 SEGMASK1 Segment Mask 1 0x90 0x00000000 0xFFFFFFFF SEGEN Segment Enable. 0 8 SEGDATA0 Segment Data 0 0xa0 0x00000000 0xFFFFFFFF SEGPIN0 Segment LCDn.0 Control. 0 4 SEGPIN1 Segment LCDn.1 Control. 4 4 SEGPIN2 Segment LCDn.2 Control. 8 4 SEGPIN3 Segment LCDn.3 Control. 12 4 SEGPIN4 Segment LCDn.4 Control. 16 4 SEGPIN5 Segment LCDn.5 Control. 20 4 SEGPIN6 Segment LCDn.6 Control. 24 4 SEGPIN7 Segment LCDn.7 Control. 28 4 SEGDATA1 Segment Data 1 0xb0 0x00000000 0xFFFFFFFF SEGPIN8 Segment LCDn.8 Control. 0 4 SEGPIN9 Segment LCDn.9 Control. 4 4 SEGPIN10 Segment LCDn.10 Control. 8 4 SEGPIN11 Segment LCDn.11 Control. 12 4 SEGPIN12 Segment LCDn.12 Control. 16 4 SEGPIN13 Segment LCDn.13 Control. 20 4 SEGPIN14 Segment LCDn.14 Control. 24 4 SEGPIN15 Segment LCDn.15 Control. 28 4 SEGDATA2 Segment Data 2 0xc0 0x00000000 0xFFFFFFFF SEGPIN16 Segment LCDn.16 Control. 0 4 SEGPIN17 Segment LCDn.17 Control. 4 4 SEGPIN18 Segment LCDn.18 Control. 8 4 SEGPIN19 Segment LCDn.19 Control. 12 4 SEGPIN20 Segment LCDn.20 Control. 16 4 SEGPIN21 Segment LCDn.21 Control. 20 4 SEGPIN22 Segment LCDn.22 Control. 24 4 SEGPIN23 Segment LCDn.23 Control. 28 4 SEGDATA3 Segment Data 3 0xd0 0x00000000 0xFFFFFFFF SEGPIN24 Segment LCDn.24 Control. 0 4 SEGPIN25 Segment LCDn.25 Control. 4 4 SEGPIN26 Segment LCDn.26 Control. 8 4 SEGPIN27 Segment LCDn.27 Control. 12 4 SEGPIN28 Segment LCDn.28 Control. 16 4 SEGPIN29 Segment LCDn.29 Control. 20 4 SEGPIN30 Segment LCDn.30 Control. 24 4 SEGPIN31 Segment LCDn.31 Control. 28 4 SEGDATA4 Segment Data 4 0xe0 0x00000000 0xFFFFFFFF SEGPIN32 Segment LCDn.32 Control. 0 4 SEGPIN33 Segment LCDn.33 Control. 4 4 SEGPIN34 Segment LCDn.34 Control. 8 4 SEGPIN35 Segment LCDn.35 Control. 12 4 SEGPIN36 Segment LCDn.36 Control. 16 4 SEGPIN37 Segment LCDn.37 Control. 20 4 SEGPIN38 Segment LCDn.38 Control. 24 4 SEGPIN39 Segment LCDn.39 Control. 28 4 LDO_0 A None LDO_0 0x40039000 0x0 0xffc registers CONTROL Control 0x0 0x00343434 0xFFFFFFFF ALDOOVAL Analog LDO Output Value Select. 0 5 ALDOBSEL Analog LDO Bias Select. 5 1 LOW Select a low bias for the analog LDO. 0 HIGH Select a high bias for the analog LDO. 1 ALDOSSEL Analog LDO Source Select. 6 1 VBAT Select the VBAT pin as the input voltage to the analog LDO. 0 DCDC Select the output of the DC-DC converter as the input voltage to the analog LDO. 1 MLDOOVAL Memory LDO Output Value Select. 8 5 MLDOBSEL Memory LDO Bias Select. 13 1 LOW Select a low bias for the memory LDO. 0 HIGH Select a high bias for the memory LDO. 1 MLDOSSEL Memory LDO Source Select. 14 1 VBAT Select the VBAT pin as the input voltage to the memory LDO. 0 DCDC Select the output of the DC-DC converter as the input voltage to the memory LDO. 1 DLDOOVAL Digital LDO Output Value Select. 16 5 DLDOBSEL Digital LDO Bias Select. 21 1 LOW Select a low bias for the digital LDO. 0 HIGH Select a high bias for the digital LDO. 1 DLDOSSEL Digital LDO Source Select. 22 1 VBAT Select the VBAT pin as the input voltage to the digital LDO. 0 DCDC Select the output of the DC-DC converter as the input voltage to the digital LDO. 1 LOCK_0 A None LOCK_0 0x40049000 0x0 0xffc registers KEY Security Key 0x0 0x00000000 0xFFFFFFFF KEY Peripheral Lock Mask Key. 0 8 LOCKED PERIPHLOCK registers are locked and no valid values have been written to KEY. 0 INTERMEDIATE PERIPHLOCK registers are locked and the first valid value (0xA5) has been written to KEY. 1 UNLOCKED PERIPHLOCK registers are unlocked. Any subsequent writes to KEY will lock the interface. 2 PERIPHLOCK0 Peripheral Lock Control 0 0x20 0x00000000 0xFFFFFFFF USARTL USART/UART Module Lock Enable. 0 1 UNLOCKED Unlock the USART0 and UART0 Module registers. 0 LOCKED Lock the USART0 and UART0 Module registers (bits can still be read). 1 SPIL SPI Module Lock Enable. 1 1 UNLOCKED Unlock the SPI0 and SPI1 Module registers. 0 LOCKED Lock the SPI0 and SPI1 Module registers (bits can still be read). 1 I2CL I2C Module Lock Enable. 2 1 UNLOCKED Unlock the I2C0 Module registers. 0 LOCKED Lock the I2C0 Module registers (bits can still be read). 1 PCAL PCA Module Lock Enable. 3 1 UNLOCKED Unlock the EPCA0 Module registers. 0 LOCKED Lock the EPCA0 Module registers (bits can still be read). 1 TIMERL Timer Module Lock Enable. 4 1 UNLOCKED Unlock the TIMER0, TIMER1, and TIMER2 Module registers. 0 LOCKED Lock the TIMER0, TIMER1, and TIMER2 Module registers (bits can still be read). 1 SARADCL SARADC Module Lock Enable. 5 1 UNLOCKED Unlock the SARADC0 Module registers. 0 LOCKED Lock the SARADC0 Module registers (bits can still be read). 1 CMPL Comparator Module Lock Enable. 6 1 UNLOCKED Unlock the Comparator 0 and Comparator 1 Module registers. 0 LOCKED Lock the Comparator 0 and Comparator 1 Module registers (bits can still be read). 1 AESL AES Module Lock Enable. 7 1 UNLOCKED Unlock the AES0 Module registers. 0 LOCKED Lock the AES0 Module registers (bits can still be read). 1 CRCL CRC Module Lock Enable. 8 1 UNLOCKED Unlock the CRC0 Module registers. 0 LOCKED Lock the CRC0 Module registers (bits can still be read). 1 RTCL RTC Module Lock Enable. 9 1 UNLOCKED Unlock the RTC0 Module registers. 0 LOCKED Lock the RTC0 Module registers (bits can still be read). 1 RSTSRCL Reset Sources Module Lock Enable. 10 1 UNLOCKED Unlock the Reset Sources (RSTSRC) Module registers. 0 LOCKED Lock the Reset Sources (RSTSRC) Module registers (bits can still be read). 1 CLKCTRL Clock Control Lock Enable. 11 1 UNLOCKED Unlock the Clock Control (CLKCTRL)Module registers. 0 LOCKED Lock the Clock Control (CLKCTRL) Module registers (bits can still be read). 1 VMONL Voltage Supply Monitor Module Lock Enable. 12 1 UNLOCKED Unlock the Voltage Supply Monitor (VMON0) Module registers. 0 LOCKED Lock the Voltage Supply Monitor (VMON0) Module registers (bits can still be read). 1 IDACL IDAC Module Lock Enable. 13 1 UNLOCKED Unlock the IDAC0 Module registers. 0 LOCKED Lock the IDAC0 Module registers (bits can still be read). 1 DMACTRLL DMA Controller Module Lock Enable. 14 1 UNLOCKED Unlock the DMA Controller (DMACTRL0) Module registers. 0 LOCKED Lock the DMA Controller (DMACTRL0) Module registers (bits can still be read). 1 DMAXBARL DMA Crossbar Module Lock Enable. 15 1 UNLOCKED Unlock the DMA Crossbar (DMAXBAR0) Module registers. 0 LOCKED Lock the DMA Crossbar (DMAXBAR0) Module registers (bits can still be read). 1 LPTL Low Power Timer Module Lock Enable. 16 1 UNLOCKED Unlock the Low Power Timer (LPTIMER0) Module registers. 0 LOCKED Lock the Low Power Timer (LPTIMER0) Module registers (bits can still be read). 1 LDOL Voltage Reference Module Lock Enable. 17 1 UNLOCKED Unlock the LDO0 Module registers. 0 LOCKED Lock the LDO0 Module registers (bits can still be read). 1 PLLL PLL Module Lock Enable. 18 1 UNLOCKED Unlock the PLL0 Module registers. 0 LOCKED Lock the PLL0 Module registers (bits can still be read). 1 EXTOSCL External Oscillator Module Lock Enable. 19 1 UNLOCKED Unlock the External Oscillator (EXTOSC0) Module registers. 0 LOCKED Lock the External Oscillator (EXTOSC0) Module registers (bits can still be read). 1 PVTL PVT Oscillator Module Lock Enable. 20 1 UNLOCKED Unlock the PVTOSC0 Module registers. 0 LOCKED Lock the PVTOSC0 Module registers (bits can still be read). 1 LPOSCL Low Power Oscillator Lock Enable. 21 1 UNLOCKED Unlock the Low Power Oscillator (LPOSC0) Module registers. 0 LOCKED Lock the Low Power Oscillator (LPOSC0) Module registers (bits can still be read). 1 ACCTRL Advanced Capture Counter Module Lock. 22 1 UNLOCKED Unlock the Advanced Capture Counter (ACCTR0) Module registers. 0 LOCKED Lock the Advanced Capture Counter (ACCTR0) Module registers (bits can still be read). 1 PMUL PMU Module Lock Enable. 27 1 UNLOCKED Unlock the PMU Module registers. 0 LOCKED Lock the PMU Module registers (bits can still be read). 1 DTML DTM Module Lock. 28 1 UNLOCKED Unlock the DTM0, DTM1, and DTM2 Module registers. 0 LOCKED Lock the DTM0, DTM1, and DTM2 Module registers (bits can still be read). 1 LCDL LCD Module Lock. 29 1 UNLOCKED Unlock the LCD0 Module registers. 0 LOCKED Lock the LCD0 Module registers (bits can still be read). 1 DCDCL DC-DC Converter Module Lock. 30 1 UNLOCKED Unlock the DCDC0 Module registers. 0 LOCKED Lock the DCDC0 Module registers (bits can still be read). 1 PERIPHLOCK1 Peripheral Lock Control 1 0x40 0x00000000 0xFFFFFFFF ENCDECL Encoder Decoder Module Lock. 0 1 UNLOCKED Unlock the ENCDEC0 Module registers. 0 LOCKED Lock the ENCDEC0 Module registers (bits can still be read). 1 LPTIMER_0 B None LPTIMER_0 0x40038000 0x0 0xffc registers LPTIMER0_IRQn 4 CONTROL Module Control 0x0 0x20000400 0xFFFFFFFF CMD Count Mode. 0 2 FREE The timer is free running mode on the RTC timer clock (RTC0TCLK). 0 RISING_EDGE The timer is incremented on the rising edges of the selected external trigger (LPTnTx). 1 FALLING_EDGE The timer is incremented on the falling edges of the selected external trigger (LPTnTx). 2 ANY_EDGE The timer is incremented on both edges of the selected external trigger (LPTnTx). 3 EXTSEL External Trigger Source Select. 4 4 LPTNT0 Select external trigger LPTnT0. 0 LPTNT1 Select external trigger LPTnT1. 1 LPTNT2 Select external trigger LPTnT2. 2 LPTNT3 Select external trigger LPTnT3. 3 LPTNT4 Select external trigger LPTnT4. 4 LPTNT5 Select external trigger LPTnT5. 5 LPTNT6 Select external trigger LPTnT6. 6 LPTNT7 Select external trigger LPTnT7. 7 LPTNT8 Select external trigger LPTnT8. 8 LPTNT9 Select external trigger LPTnT9. 9 LPTNT10 Select external trigger LPTnT10. 10 LPTNT11 Select external trigger LPTnT11. 11 LPTNT12 Select external trigger LPTnT12. 12 LPTNT13 Select external trigger LPTnT13. 13 LPTNT14 Select external trigger LPTnT14. 14 LPTNT15 Select external trigger LPTnT15. 15 TMRSET Timer Set. 8 1 SET Writing a 1 to TMRSET initiates a copy of the value from the COUNT register into the internal timer register. This field is automatically cleared by hardware when the copy is complete and does not need to be cleared by software. 1 TMRCAP Timer Capture. 9 1 SET Writing a 1 to TMRCAP initiates a read of internal timer register into the COUNT register. This field is automatically cleared by hardware when the operation completes and does not need to be cleared by software. 1 HSMDEN High Speed Timer Access Mode Enable. 10 1 DISABLED Disable high speed timer access mode. 0 ENABLED Enable high speed timer access mode. 1 CMP0EN Timer Compare 0 Threshold Enable. 11 1 DISABLED 0 ENABLED 1 CMP1EN Timer Compare 1 Threshold Enable. 12 1 DISABLED 0 ENABLED 1 OUTEN Output Enable. 13 1 DISABLED Disable the LPTIMER0 output. 0 ENABLED Enable the LPTIMER0 output. 1 OVFIEN Timer Overflow Interrupt Enable. 16 1 DISABLED Disable the timer overflow interrupt. 0 ENABLED Enable the timer overflow interrupt. 1 CMP0IEN Timer Compare 0 Event Interrupt Enable. 17 1 DISABLED Disable the timer compare 0 event interrupt. 0 ENABLED Enable the timer compare 0 event interrupt. 1 OVFOEN Timer Overflow Output Enable. 18 1 DISABLED Timer overflows do not modify the Low Power Timer output. 0 ENABLED Timer overflows set the Low Power Timer output to 1. 1 CMP0OEN Timer Compare 0 Event Output Enable. 19 1 DISABLED Timer compare 0 events do not modify the Low Power Timer output. 0 ENABLED Timer compare 0 events clear the Low Power Timer output to 0. 1 CMP1IEN Timer Compare 1 Event Interrupt Enable. 20 1 DISABLED Disable the timer compare 1 event interrupt. 0 ENABLED Enable the timer compare 1 event interrupt. 1 CMP1OEN Timer Compare 1 Event Output Enable. 21 1 DISABLED Timer compare 1 events do not modify the Low Power Timer output. 0 ENABLED Timer compare 1 events set the Low Power Timer output to 1. 1 OUTINVEN Output Inversion Enable. 22 1 DISABLED Do not invert the LPTIMER0 output. 0 ENABLED Invert the LPTIMER0 output. 1 CMP0RSTEN Timer Compare 0 Event Reset Enable. 24 1 DISABLED Timer compare 0 events do not reset the timer. 0 ENABLED Timer compare 0 events reset the timer. 1 CMP1RSTEN Timer Compare 1 Event Reset Enable. 25 1 DISABLED Timer compare 1 events do not reset the timer. 0 ENABLED Timer compare 1 events reset the timer. 1 MCLKEN Low Power Timer Module Clock Enable. 29 1 DISABLED Disable the clock to the Low Power Timer module. 0 ENABLED Enable the clock to the Low Power Timer module. 1 DBGMD Low Power Timer Debug Mode. 30 1 RUN The Low Power Timer module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the Low Power Timer module to halt. 1 RUN Timer Run Control and Compare Threshold Enable. 31 1 STOP Stop the timer and disable the compare threshold. 0 START Start the timer running and enable the compare threshold. 1 COUNT Timer Value 0x10 0x00000000 0xFFFFFFFF TIMER Timer Value. 0 16 THRESHOLD Threshold Values 0x20 0x00000000 0xFFFFFFFF COMPARE0 Timer Compare 0 Threshold Value. 0 16 COMPARE1 Timer Compare 1 Threshold Value. 16 16 STATUS Module Status 0x30 0x00000000 0xFFFFFFFF OVFI Timer Overflow Interrupt Flag. 0 1 NOT_SET A timer overflow has not occurred. 0 SET A timer overflow occurred. 1 CMP0I Timer Compare 0 Event Interrupt Flag. 1 1 NOT_SET A timer compare 0 event has not occurred. 0 SET A timer compare 0 event occurred. 1 CMP1I Timer Compare 1 Event Interrupt Flag. 2 1 NOT_SET A timer compare 1 event has not occurred. 0 SET A timer compare 1 event occurred. 1 PLL_0 A None Oscillators 0x4003b000 0x0 0xffc registers PLL0_IRQn 43 DIVIDER Reference Divider Setting 0x0 0x00000000 0xFFFFFFFF M M Divider Value. 0 12 N N Divider Value. 16 12 CONTROL Module Control 0x10 0x00010800 0xFFFFFFFF LLMTF CAL Saturation (Low) Flag. 0 1 read-only NOT_SET DCO period is not saturated low. 0 SET DCO period is saturated low. 1 HLMTF CAL Saturation (High) Flag. 1 1 read-only NOT_SET DCO period is not saturated high. 0 SET DCO period is saturated high. 1 LCKI Phase-Lock and Frequency-Lock Locked Interrupt Flag. 2 1 read-only NOT_SET DCO is disabled or not locked. 0 SET DCO is enabled and locked. 1 LMTIEN Limit Interrupt Enable. 9 1 DISABLED Saturation (high and low) interrupt disabled. 0 ENABLED Saturation (high and low) interrupt enabled. 1 LCKIEN Locked Interrupt Enable. 10 1 DISABLED The PLL locking does not cause an interrupt 0 ENABLED An interrupt is generated if LCKI matches the state selected by LCKPOL. 1 LCKPOL Lock Interrupt Polarity. 11 1 ACTIVE_LOW The lock state PLL interrupt will occur when LCKI is 0. 0 ACTIVE_HIGH The lock state PLL interrupt will occur when LCKI is 1. 1 REFSEL Reference Clock Selection Control. 16 2 RTC0TCLK PLL reference clock (FREF) is the RTC0 oscillator (RTC0TCLK). 0 LPOSC0DIV PLL reference clock (FREF) is the divided Low Power Oscillator (LPOSC0). 1 EXTOSC0 PLL reference clock (FREF) is the external oscillator output (EXTOSC0). 2 LOCKTH Lock Threshold Control. 20 2 STALL DCO Output Updates Stall. 26 1 DISABLED In phase-lock and frequency-lock modes, spectrum spreading, and dithering operate normally, if enabled. 0 ENABLED In phase-lock and frequency-lock modes, spectrum spreading, and dithering are prevented from updating the output of the DCO. 1 DITHEN Dithering Enable. 28 1 DISABLED Automatic DCO output dithering disabled. 0 ENABLED Automatic DCO output dithering enabled. 1 EDGSEL Edge Lock Select. 29 1 FALLING_EDGE Lock DCO output frequency to the falling edge of the reference frequency. 0 RISING_EDGE Lock DCO output frequency to the rising edge of the reference frequency. 1 OUTMD PLL Output Mode. 30 2 OFF DCO output is off. 0 DCO DCO output is in Free-Running DCO mode. 1 FLL DCO output is in frequency-lock mode (reference source required). 2 PLL DCO output is in phase-lock mode (reference source required). 3 SSPR Spectrum Spreading Control 0x20 0x00000000 0xFFFFFFFF SSAMP Spectrum Spreading Amplitude. 0 3 DISABLED Disable Spectrum Spreading. 0 SETTING1 Spectrum Spreading set to approximately +/- 0.1% of TDCO. 1 SETTING2 Spectrum Spreading set to approximately +/- 0.2% of TDCO. 2 SETTING3 Spectrum Spreading set to approximately +/- 0.4% of TDCO. 3 SETTING4 Spectrum Spreading set to approximately +/- 0.8% of TDCO. 4 SETTING5 Spectrum Spreading set to approximately +/- 1.6% of TDCO. 5 SSUINV Spectrum Spreading Update Interval. 8 5 CALCONFIG Calibration Configuration 0x30 0x00000000 0xFFFFFFFF DITHER DCO Dither Setting. 0 4 CAL DCO Calibration Value. 4 12 RANGE DCO Range. 16 3 RANGE0 DCO operates from 23 to 37 MHz. 0 RANGE1 DCO operates from 33 to 50 MHz. 1 RANGE2 DCO operates from 45 to 50 MHz. 2 EXTOSC_0 A None Oscillators 0x4003c000 0x0 0xffc registers CONTROL Oscillator Control 0x0 0x00000000 0xFFFFFFFF FREQCN Frequency Control. 0 3 RANGE0 Set the external oscillator to range 0. 0 RANGE1 Set the external oscillator to range 1. 1 RANGE2 Set the external oscillator to range 2. 2 RANGE3 Set the external oscillator to range 3. 3 RANGE4 Set the external oscillator to range 4. 4 RANGE5 Set the external oscillator to range 5. 5 RANGE6 Set the external oscillator to range 6. 6 RANGE7 Set the external oscillator to range 7. 7 OSCVLDF Oscillator Valid Flag. 3 1 read-only NOT_SET The external oscillator is unused or not yet stable. 0 SET The external oscillator is running and stable. 1 OSCMD Oscillator Mode. 4 3 OFF External oscillator off. 0 CMOS External CMOS clock mode. 2 CMOSDIV2 External CMOS with divide by 2 stage. 3 RC RC oscillator mode with divide by 2 stage. 4 C C oscillator mode with divide by 2 stage. 5 XTAL Crystal oscillator mode. 6 XTALDIV2 Crystal oscillator mode with divide by 2 stage. 7 PVTOSC_0 A None Oscillators 0x4003d000 0x0 0xffc registers CONTROL Module Control 0x0 0x00000000 0xFFFFFFFF DIGOSCEN Digital LDO Oscillator Enable. 0 1 DISABLED Disable the digital LDO PVT oscillator. 0 ENABLED Enable the digital LDO PVT oscillator. 1 MEMOSCEN Memory LDO Oscillator Enable. 1 1 DISABLED Disable the memory LDO PVT oscillator. 0 ENABLED Enable the memory LDO PVT oscillator. 1 DIGOSCMD Digital LDO Oscillator Mode. 4 1 FAST Select fast mode for the digital LDO PVT oscillator. 0 SLOW Select slow mode for the digital LDO PVT oscillator. 1 MEMOSCMD High Voltage Oscillator Mode. 5 1 FAST Select fast mode for the memory LDO PVT oscillator. 0 SLOW Select slow mode for the memory LDO PVT oscillator. 1 CLKSEL Clock Select. 6 1 OSCILLATORS Select the digital and memory oscillators as the inputs to the clock dividers. 0 AHB Select the APB clock as the input to the clock dividers. 1 PMU_0 A None PMU_0 0x40048000 0x0 0xffc registers CPFAIL_IRQn 39 CONTROL Module Control 0x0 0x00FF0060 0xFFFFFFFF WAKECLR Wakeup Source Clear. 0 1 write-only CLEAR Clear all wakeup sources. 0 PWAKEEN Pin Wake Match Enable. 3 1 DISABLED Disable Pin Wake. 0 ENABLED Enable Pin Wake. 1 PMUASLPEN PMU Asleep Pin Enable. 4 1 DISABLED Disable the PMU Asleep pin. 0 ENABLED Enable the PMU Asleep pin. 1 CPMONEN Low Power Charge Pump Voltage Monitor Enable. 5 1 DISABLED Disable the low power charge pump voltage monitor. 0 ENABLED Enable the low power charge pump voltage monitor. 1 CPMONIEN Low Power Charge Pump Voltage Monitor Interrupt Enable. 6 1 DISABLED Disable the low power charge pump voltage monitor interrupt. 0 ENABLED Enable the low power charge pump voltage monitor interrupt. 1 RAM0REN RAM 0 Retention Enable. 16 1 DISABLED Disable power to RAM 0 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF). 0 ENABLED Enable power to RAM 0 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF). 1 RAM1REN RAM 1 Retention Enable. 17 1 DISABLED Disable power to RAM 1 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF). 0 ENABLED Enable power to RAM 1 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF). 1 RAM2REN RAM 2 Retention Enable. 18 1 DISABLED Disable power to RAM 2 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF). 0 ENABLED Enable power to RAM 2 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF). 1 RAM3REN RAM 3 Retention Enable. 19 1 DISABLED Disable power to RAM 3 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF). 0 ENABLED Enable power to RAM 3 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF). 1 RAM4REN RAM 4 Retention Enable. 20 1 DISABLED Disable power to RAM 4 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF). 0 ENABLED Enable power to RAM 4 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF). 1 RAM5REN RAM 5 Retention Enable. 21 1 DISABLED Disable power to RAM 5 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF). 0 ENABLED Enable power to RAM 5 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF). 1 RAM6REN RAM 6 Retention Enable. 22 1 DISABLED Disable power to RAM 6 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF). 0 ENABLED Enable power to RAM 6 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF). 1 RAM7REN RAM 7 Retention Enable. 23 1 DISABLED Disable power to RAM 7 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF). 0 ENABLED Enable power to RAM 7 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF). 1 CONFIG Module Configuration 0x10 0x00000000 0xFFFFFFFF VBATMONEN VBAT Monitor Disable. 4 1 ENABLED Enable the 0.8 V VBAT monitor. 0 DISABLED Disable the 0.8V VBAT monitor. 1 VDRVSMD VDRV Switch Mode. 5 2 HIGHZ High-Z. 0 VBAT VBAT connected to VDRV. 2 VDC DC-DC output connected to VDRV. 3 CPEN Low Power Charge Pump Enable. 8 1 DISABLED 0 ENABLED 1 CPLOAD Charge Pump Load Setting. 10 2 STATUS Module Status 0x20 0x0000000C 0xFFFFFFFF PM8EF Power Mode 8 Exited Flag. 0 1 NOT_SET The device has not exited Power Mode 8. 0 SET The device has exited Power Mode 8. This bit must be cleared by firmware. 1 PWAKEF Pin Wake Status Flag. 1 1 read-only NOT_SET A Pin Wake event has not occurred. 0 SET A Pin Wake event has occurred. 1 PORF Power-On Reset Flag. 2 1 NOT_SET A power-on reset did not occur since the last time PORF was cleared. 0 SET A power-on reset occurred. 1 CPSTS Low Power Charge Pump Voltage Monitor Status. 3 1 read-only NOT_SET The low power charge pump supply voltage is below the threshold. 0 SET The low power charge pump supply voltage is greater than the threshold. 1 WAKEEN Wakeup Enable 0x30 0x00000000 0xFFFFFFFF RTC0FWEN RTC0 Fail Wake Enable. 0 1 DISABLED An RTC0 Fail event does not wake the device. 0 ENABLED An RTC0 Fail event awakens the device. 1 RTC0A0WEN RTC0 Alarm Wake Enable. 1 1 DISABLED An RTC0 Alarm event does not wake the device. 0 ENABLED An RTC0 Alarm event awakens the device. 1 CMP0WEN Comparator 0 Wake Enable. 2 1 DISABLED A Comparator 0 event does not wake the device. 0 ENABLED A Comparator 0 event awakens the device. 1 ACC0WEN Advanced Capture Counter 0 Wake Enable. 3 1 DISABLED An Advanced Capture Counter (ACCTR0) event does not wake the device. 0 ENABLED An Advanced Capture Counter (ACCTR0) event awakens the device. 1 LCDMONWEN LCD VBAT Voltage Monitor Wake Enable. 4 1 DISABLED An LCD VBAT voltage monitor event does not wake the device. 0 ENABLED An LCD VBAT voltage monitor event awakens the device. 1 PWAKEWEN Pin Wake Wake Enable. 5 1 DISABLED A Pin Wake event does not wake the device. 0 ENABLED A Pin Wake event awakens the device. 1 LPT0WEN Low Power Timer Wake Enable. 6 1 DISABLED An LPTIMER0 event does not wake the device. 0 ENABLED An LPTIMER0 event awakens the device. 1 UART0WEN UART0 Wake Enable. 7 1 DISABLED A UART0 event does not wake the device. 0 ENABLED A UART0 event awakens the device. 1 CPFWEN Low Power Charge Pump Supply Fail Wake Enable. 8 1 DISABLED A low power charge pump supply fail event does not wake the device. 0 ENABLED A low power charge pump supply fail event awakens the device. 1 WAKESTATUS Wakeup Status 0x40 0x00000000 0xFFFFFFFF RTC0FWF RTC0 Fail Wake Flag. 0 1 read-only NOT_SET An RTC0 Fail event did not wake the device. 0 SET An RTC0 Fail event woke the device. 1 RTC0A0WF RTC0 Alarm Wake Flag. 1 1 read-only NOT_SET An RTC0 Alarm event did not wake the device. 0 SET An RTC0 Alarm event woke the device. 1 CMP0WF Comparator 0 Wake Flag. 2 1 read-only NOT_SET A Comparator 0 event did not wake the device. 0 SET A Comparator 0 event woke the device. 1 ACC0WF Advanced Capture Counter 0 Wake Flag. 3 1 read-only NOT_SET An Advanced Capture Counter (ACCTR0) event did not wake the device. 0 SET An Advanced Capture Counter (ACCTR0) event woke the device. 1 LCDMONWF LCD VBAT Voltage Monitor Wake Flag. 4 1 read-only NOT_SET A LCD VBAT voltage monitor event did not wake the device. 0 SET A LCD VBAT voltage monitor event woke the device. 1 PWAKEWF Pin Wake Wake Flag. 5 1 read-only NOT_SET A Pin Wake event did not wake the device. 0 SET A Pin Wake event woke the device. 1 LPT0WF Low Power Timer Wake Flag. 6 1 read-only NOT_SET An LPTIMER0 event did not wake the device. 0 SET An LPTIMER0 event woke the device. 1 UART0WF UART0 Wake Flag. 7 1 read-only NOT_SET A UART0 event did not wake the device. 0 SET A UART0 event woke the device. 1 CPFWF Low Power Charge Pump Supply Fail Wake Flag. 8 1 read-only NOT_SET A low power charge pump supply fail event did not wake the device. 0 SET A low power charge pump supply fail event woke the device. 1 RSTWF Reset Pin Wake Flag. 9 1 read-only NOT_SET A /RESET Pin event did not wake the device. 0 SET A /RESET Pin event woke the device. 1 PWEN Pin Wake Pin Enable 0x50 0x00000000 0xFFFFFFFF PW0EN WAKE.0 Enable. 0 1 DISABLED WAKE.0 does not cause a Pin Wake event. 0 ENABLED Enable WAKE.0 as a Pin Wake source. 1 PW1EN WAKE.1 Enable. 1 1 DISABLED WAKE.1 does not cause a Pin Wake event. 0 ENABLED Enable WAKE.1 as a Pin Wake source. 1 PW2EN WAKE.2 Enable. 2 1 DISABLED WAKE.2 does not cause a Pin Wake event. 0 ENABLED Enable WAKE.2 as a Pin Wake source. 1 PW3EN WAKE.3 Enable. 3 1 DISABLED WAKE.3 does not cause a Pin Wake event. 0 ENABLED Enable WAKE.3 as a Pin Wake source. 1 PW4EN WAKE.4 Enable. 4 1 DISABLED WAKE.4 does not cause a Pin Wake event. 0 ENABLED Enable WAKE.4 as a Pin Wake source. 1 PW5EN WAKE.5 Enable. 5 1 DISABLED WAKE.5 does not cause a Pin Wake event. 0 ENABLED Enable WAKE.5 as a Pin Wake source. 1 PW6EN WAKE.6 Enable. 6 1 DISABLED WAKE.6 does not cause a Pin Wake event. 0 ENABLED Enable WAKE.6 as a Pin Wake source. 1 PW7EN WAKE.7 Enable. 7 1 DISABLED WAKE.7 does not cause a Pin Wake event. 0 ENABLED Enable WAKE.7 as a Pin Wake source. 1 PW8EN WAKE.8 Enable. 8 1 DISABLED WAKE.8 does not cause a Pin Wake event. 0 ENABLED Enable WAKE.8 as a Pin Wake source. 1 PW9EN WAKE.9 Enable. 9 1 DISABLED WAKE.9 does not cause a Pin Wake event. 0 ENABLED Enable WAKE.9 as a Pin Wake source. 1 PW10EN WAKE.10 Enable. 10 1 DISABLED WAKE.10 does not cause a Pin Wake event. 0 ENABLED Enable WAKE.10 as a Pin Wake source. 1 PW11EN WAKE.11 Enable. 11 1 DISABLED WAKE.11 does not cause a Pin Wake event. 0 ENABLED Enable WAKE.11 as a Pin Wake source. 1 PW12EN WAKE.12 Enable. 12 1 DISABLED WAKE.12 does not cause a Pin Wake event. 0 ENABLED Enable WAKE.12 as a Pin Wake source. 1 PW13EN WAKE.13 Enable. 13 1 DISABLED WAKE.13 does not cause a Pin Wake event. 0 ENABLED Enable WAKE.13 as a Pin Wake source. 1 PW14EN WAKE.14 Enable. 14 1 DISABLED WAKE.14 does not cause a Pin Wake event. 0 ENABLED Enable WAKE.14 as a Pin Wake source. 1 PW15EN WAKE.15 Enable. 15 1 DISABLED WAKE.15 does not cause a Pin Wake event. 0 ENABLED Enable WAKE.15 as a Pin Wake source. 1 PWPOL Pin Wake Pin Polarity Select 0x60 0x00000000 0xFFFFFFFF PW0POL WAKE.0 Polarity Select. 0 1 LOW A logic low on WAKE.0 causes a Pin Wake event if PW0EN is set to 1. 0 HIGH A logic high on WAKE.0 causes a Pin Wake event if PW0EN is set to 1. 1 PW1POL WAKE.1 Polarity Select. 1 1 LOW A logic low on WAKE.1 causes a Pin Wake event if PW1EN is set to 1. 0 HIGH A logic high on WAKE.1 causes a Pin Wake event if PW1EN is set to 1. 1 PW2POL WAKE.2 Polarity Select. 2 1 LOW A logic low on WAKE.2 causes a Pin Wake event if PW2EN is set to 1. 0 HIGH A logic high on WAKE.2 causes a Pin Wake event if PW2EN is set to 1. 1 PW3POL WAKE.3 Polarity Select. 3 1 LOW A logic low on WAKE.3 causes a Pin Wake event if PW3EN is set to 1. 0 HIGH A logic high on WAKE.3 causes a Pin Wake event if PW3EN is set to 1. 1 PW4POL WAKE.4 Polarity Select. 4 1 LOW A logic low on WAKE.4 causes a Pin Wake event if PW4EN is set to 1. 0 HIGH A logic high on WAKE.4 causes a Pin Wake event if PW4EN is set to 1. 1 PW5POL WAKE.5 Polarity Select. 5 1 LOW A logic low on WAKE.5 causes a Pin Wake event if PW5EN is set to 1. 0 HIGH A logic high on WAKE.5 causes a Pin Wake event if PW5EN is set to 1. 1 PW6POL WAKE.6 Polarity Select. 6 1 LOW A logic low on WAKE.6 causes a Pin Wake event if PW6EN is set to 1. 0 HIGH A logic high on WAKE.6 causes a Pin Wake event if PW6EN is set to 1. 1 PW7POL WAKE.7 Polarity Select. 7 1 LOW A logic low on WAKE.7 causes a Pin Wake event if PW7EN is set to 1. 0 HIGH A logic high on WAKE.7 causes a Pin Wake event if PW7EN is set to 1. 1 PW8POL WAKE.8 Polarity Select. 8 1 LOW A logic low on WAKE.8 causes a Pin Wake event if PW8EN is set to 1. 0 HIGH A logic high on WAKE.8 causes a Pin Wake event if PW8EN is set to 1. 1 PW9POL WAKE.9 Polarity Select. 9 1 LOW A logic low on WAKE.9 causes a Pin Wake event if PW9EN is set to 1. 0 HIGH A logic high on WAKE.9 causes a Pin Wake event if PW9EN is set to 1. 1 PW10POL WAKE.10 Polarity Select. 10 1 LOW A logic low on WAKE.10 causes a Pin Wake event if PW10EN is set to 1. 0 HIGH A logic high on WAKE.10 causes a Pin Wake event if PW10EN is set to 1. 1 PW11POL WAKE.11 Polarity Select. 11 1 LOW A logic low on WAKE.11 causes a Pin Wake event if PW11EN is set to 1. 0 HIGH A logic high on WAKE.11 causes a Pin Wake event if PW11EN is set to 1. 1 PW12POL WAKE.12 Polarity Select. 12 1 LOW A logic low on WAKE.12 causes a Pin Wake event if PW12EN is set to 1. 0 HIGH A logic high on WAKE.12 causes a Pin Wake event if PW12EN is set to 1. 1 PW13POL WAKE.13 Polarity Select. 13 1 LOW A logic low on WAKE.13 causes a Pin Wake event if PW13EN is set to 1. 0 HIGH A logic high on WAKE.13 causes a Pin Wake event if PW13EN is set to 1. 1 PW14POL WAKE.14 Polarity Select. 14 1 LOW A logic low on WAKE.14 causes a Pin Wake event if PW14EN is set to 1. 0 HIGH A logic high on WAKE.14 causes a Pin Wake event if PW14EN is set to 1. 1 PW15POL WAKE.15 Polarity Select. 15 1 LOW A logic low on WAKE.15 causes a Pin Wake event if PW15EN is set to 1. 0 HIGH A logic high on WAKE.15 causes a Pin Wake event if PW15EN is set to 1. 1 PBCFG_0 A None PBCFG_0 0x4002a000 0x0 0xffc registers PBEXT0_IRQn 1 PBEXT1_IRQn 2 PMATCH_IRQn 41 CONTROL0 Global Port Control 0 0x0 0x80000000 0xFFFFFFFF INT0SEL External Interrupt 0 Pin Selection. 0 4 INT0_0 Select INT0.0 0 INT0_1 Select INT0.1 1 INT0_2 Select INT0.2 2 INT0_3 Select INT0.3 3 INT0_4 Select INT0.4 4 INT0_5 Select INT0.5 5 INT0_6 Select INT0.6 6 INT0_7 Select INT0.7 7 INT0_8 Select INT0.8 8 INT0_9 Select INT0.9 9 INT0_10 Select INT0.10 10 INT0_11 Select INT0.11 11 INT0_12 Select INT0.12 12 INT0_13 Select INT0.13 13 INT0_14 Select INT0.14 14 INT0_15 Select INT0.15 15 INT0POL External Interrupt 0 Polarity. 4 1 LOW A low value or falling edge on the selected pin will cause interrupt. 0 HIGH A high value or rising edge on the selected pin will cause interrupt. 1 INT0MD External Interrupt 0 Mode. 5 2 LEVEL Interrupt on logic level at pin, as selected by the INT0POL field. 0 EDGE Interrupt on either rising or falling edge, as selected by the INT0POL field. 1 DUAL_EDGE Interrupt on both rising and falling edges (ignores INT0POL). 2 INT0EN External Interrupt 0 Enable. 7 1 DISABLED Disable external interrupt 0. 0 ENABLED Enable external interrupt 0. 1 INT1SEL External Interrupt 1 Pin Selection. 8 4 INT1_0 Select INT1.0 0 INT1_1 Select INT1.1 1 INT1_2 Select INT1.2 2 INT1_3 Select INT1.3 3 INT1_4 Select INT1.4 4 INT1_5 Select INT1.5 5 INT1_6 Select INT1.6 6 INT1_7 Select INT1.7 7 INT1_8 Select INT1.8 8 INT1_9 Select INT1.9 9 INT1_10 Select INT1.10 10 INT1_11 Select INT1.11 11 INT1_12 Select INT1.12 12 INT1_13 Select INT1.13 13 INT1_14 Select INT1.14 14 INT1_15 Select INT1.15 15 INT1POL External Interrupt 1 Polarity. 12 1 LOW A low value or falling edge on the selected pin will cause interrupt. 0 HIGH A high value or rising edge on the selected pin will cause interrupt. 1 INT1MD External Interrupt 1 Mode. 13 2 LEVEL Interrupt on logic level at pin, as selected by the INT1POL field. 0 EDGE Interrupt on either rising or falling edge, as selected by the INT1POL field. 1 DUAL_EDGE Interrupt on both rising and falling edges (ignores INT1POL). 2 INT1EN External Interrupt 1 Enable. 15 1 DISABLED Disable external interrupt 1. 0 ENABLED Enable external interrupt 1. 1 PGTIMER Pulse Generator Timer. 24 5 PGDONEF Pulse Generator Timer Done Flag. 31 1 read-only NOT_SET Firmware has written to the PBPGPHASE register, but the Pulse Generator timer has not expired. 0 SET The Pulse Generator cycle finished since the last time PBPGPHASE was written. 1 CONTROL1 Global Port Control 1 0x10 0x00000001 0xFFFFFFFF JTAGEN JTAG Enable. 0 1 DISABLED JTAG functionality is not pinned out. 0 ENABLED JTAG functionality is pinned out. 1 ETMEN ETM Enable. 1 1 DISABLED ETM not pinned out. 0 ENABLED ETM is enabled and pinned out. 1 SWVEN SWV Enable. 2 1 DISABLED SWV is not pinned out. 0 ENABLED SWV is enabled and pinned out. 1 SPI1SEL SPI1 Fixed Port Selection. 8 1 DISABLED Disconnect SPI1 from the dedicated pins. 0 ENABLED Connect SPI1 to the dedicated pins. 1 PMATCHEN Port Match Interrupt Enable. 9 1 DISABLED Disable the port match logic. The PBnMAT registers are not read/write accessible on the APB bus. 0 ENABLED Enable the port match logic to generate a port match interrupt. The PBnMAT registers are read/write accessible on the APB bus. 1 LPTOSEL Low Power Timer Output Pin Select. 12 1 LPT0OUT0 Route the Low Power Timer output to LPT0OUT0. 0 LPT0OUT1 Route the Low Power Timer output to LPT0OUT1. 1 LOCK Port Bank Configuration Lock. 31 1 UNLOCKED Port Bank Configuration and Control registers are unlocked. 0 LOCKED The following registers are locked from write access: CONTROL1, XBAR0, and all PBSKIP registers. 1 XBAR0 Crossbar 0 Control 0x20 0x00000000 0xFFFFFFFF USART0EN USART0 Enable. 0 1 DISABLED Disable USART0 RX and TX on Crossbar 0. 0 ENABLED Enable USART0 RX and TX on Crossbar 0. 1 USART0FCEN USART0 Flow Control Enable. 1 1 DISABLED Disable USART0 flow control on Crossbar 0. 0 ENABLED Enable USART0 flow control on Crossbar 0. 1 USART0CEN USART0 Clock Signal Enable. 2 1 DISABLED Disable USART0 clock on Crossbar 0. 0 ENABLED Enable USART0 clock on Crossbar 0. 1 DMA0T0EN DMA Trigger 0 Enable. 3 1 DISABLED Disable the DMA trigger 0 on Crossbar 0. 0 ENABLED Enable the DMA trigger 0 on Crossbar 0. 1 DMA0T1EN DMA Trigger 1 Enabled. 4 1 DISABLED Disable the DMA trigger 1 on Crossbar 0. 0 ENABLED Enable the DMA trigger 1 on Crossbar 0. 1 IDAC0TEN IDAC0 Trigger Enable. 5 1 DISABLED Disable the IDAC0 trigger on Crossbar 0. 0 ENABLED Enable the IDAC0 trigger on Crossbar 0. 1 SPI0EN SPI0 Enable. 6 1 DISABLED Disable SPI0 SCK, MISO, and MOSI on Crossbar 0. 0 ENABLED Enable SPI0 SCK, MISO, and MOSI on Crossbar 0. 1 SPI0NSSEN SPI0 NSS Pin Enable. 7 1 DISABLED Disable SPI0 NSS on Crossbar 0. 0 ENABLED Enable SPI0 NSS on Crossbar 0. 1 EPCA0EN EPCA0 Channel Enable. 8 3 NONE Disable all EPCA0 channels on Crossbar 0. 0 CEX0_0 Enable EPCA0 CEX0 on Crossbar 0. 1 CEX0_1 Enable EPCA0 CEX0 and CEX1 on Crossbar 0. 2 CEX0_2 Enable EPCA0 CEX0, CEX1, and CEX2 on Crossbar 0. 3 CEX0_3 Enable EPCA0 CEX0, CEX1, CEX2, and CEX3 on Crossbar 0. 4 CEX0_4 Enable EPCA0 CEX0, CEX1, CEX2, CEX3, and CEX4 on Crossbar 0. 5 CEX0_5 Enable EPCA0 CEX0, CEX1, CEX2, CEX3, CEX4, and CEX5 on Crossbar 0. 6 EECI0EN EPCA0 ECI Enable. 11 1 DISABLED Disable EPCA0 ECI on Crossbar 0. 0 ENABLED Enable EPCA0 ECI on Crossbar 0. 1 I2C0EN I2C0 Enable. 12 1 DISABLED Disable I2C0 SDA and SCL on Crossbar 0. 0 ENABLED Enable I2C0 SDA and SCL on Crossbar 0. 1 CMP0SEN Comparator 0 Synchronous Output (CMP0S) Enable. 13 1 DISABLED Disable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0. 0 ENABLED Enable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0. 1 CMP0AEN Comparator 0 Asynchronous Output (CMP0A) Enable. 14 1 DISABLED Disable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0. 0 ENABLED Enable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0. 1 CMP1SEN Comparator 1 Synchronous Output (CMP1S) Enable. 15 1 DISABLED Disable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0. 0 ENABLED Enable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0. 1 CMP1AEN Comparator 1 Asynchronous Output (CMP1A) Enable. 16 1 DISABLED Disable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0. 0 ENABLED Enable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0. 1 TMR0CTEN TIMER0 T0CT Enable. 17 1 DISABLED Disable TIMER0 CT on Crossbar 0. 0 ENABLED Enable TIMER0 CT on Crossbar 0. 1 TMR0EXEN TIMER0 T0EX Enable. 18 1 DISABLED Disable TIMER0 EX on Crossbar 0. 0 ENABLED Enable TIMER0 EX on Crossbar 0. 1 TMR1CTEN TIMER1 T1CT Enable. 19 1 DISABLED Disable TIMER1 CT on Crossbar 0. 0 ENABLED Enable TIMER1 CT on Crossbar 0. 1 TMR1EXEN TIMER1 T1EX Enable. 20 1 DISABLED Disable TIMER1 EX on Crossbar 0. 0 ENABLED Enable TIMER1 EX on Crossbar 0. 1 SARADC0TEN SARADC0 Trigger Enable. 21 1 DISABLED Disable SARADC0 conversion start trigger on Crossbar 0. 0 ENABLED Enable SARADC0 conversion start trigger on Crossbar 0. 1 AHBEN AHB Clock Output Enable. 22 1 DISABLED Disable the AHB Clock / 16 output on Crossbar 0. 0 ENABLED Enable the AHB Clock / 16 output on Crossbar 0. 1 XBAR0EN Crossbar 0 Enable. 31 1 DISABLED Disable Crossbar 0. 0 ENABLED Enable Crossbar 0. 1 PBKEY Global Port Key 0x30 0x00000000 0xFFFFFFFF KEY Port Bank Key. 0 8 LOCKED Port Bank registers are locked and no valid values have been written to PBKEY. 0 INTERMEDIATE Port Bank registers are locked and the first valid value (0xA5) has been written to PBKEY. 1 UNLOCKED Port Bank registers are unlocked. Any subsequent writes to the Port Bank registers or PBKEY will lock the interface. 2 PBGP_4 A None PBGP_4 0x4002a320 0x0 0xffc registers PB Output Latch 0x0 0x0000FFFF 0xFFFFFFFF PB Output Latch. 0 16 PBPIN Pin Value 0x10 0x00000000 0xFFFFFFFF PBPIN Pin Value. 0 16 read-only PBMDSEL Mode Select 0x20 0x0000FFFF 0xFFFFFFFF PBMDSEL Mode Select. 0 16 PBOUTMD Output Mode 0x30 0x00000000 0xFFFFFFFF PBOUTMD Output Mode. 0 16 PBDRV Drive Strength 0x40 0x00010000 0xFFFFFFFF PBDRV Drive Strength. 0 16 PBPUEN Port Bank Weak Pull-up Enable. 16 1 DISABLED Disable weak pull-ups for this port. 0 ENABLED Enable weak pull-ups for this port. 1 PM Port Match Value 0x50 0x00000000 0xFFFFFFFF PM Port Match Value. 0 16 PMEN Port Match Enable 0x60 0x00000000 0xFFFFFFFF PMEN Port Match Enable. 0 16 PBSTD_0 A None Port_Standard 0x4002a0a0 0x0 0xffc registers PB Output Latch 0x0 0x0000FFFF 0xFFFFFFFF PB Output Latch. 0 16 PBPIN Pin Value 0x10 0x00000000 0xFFFFFFFF PBPIN Pin Value. 0 16 read-only PBMDSEL Mode Select 0x20 0x0000FFFF 0xFFFFFFFF PBMDSEL Mode Select. 0 16 PBSKIPEN Crossbar Pin Skip Enable 0x30 0x00000000 0xFFFFFFFF PBSKIPEN Crossbar Pin Skip Enable. 0 16 PBOUTMD Output Mode 0x40 0x00000000 0xFFFFFFFF PBOUTMD Output Mode. 0 16 PBDRV Drive Strength 0x50 0x00010000 0xFFFFFFFF PBDRV Drive Strength. 0 16 PBPUEN Port Bank Weak Pull-up Enable. 16 1 DISABLED Disable weak pull-ups for this port. 0 ENABLED Enable weak pull-ups for this port. 1 PM Port Match Value 0x60 0x00000000 0xFFFFFFFF PM Port Match Value. 0 16 PMEN Port Match Enable 0x70 0x00000000 0xFFFFFFFF PMEN Port Match Enable. 0 16 PBPGEN Pulse Generator Pin Enable 0x80 0x00000000 0xFFFFFFFF PBPGEN Pulse Generator Pin Enable. 0 12 PBPGPHASE Pulse Generator Phase 0x90 0x00000FFF 0xFFFFFFFF PBPGPH0 Pulse Generator Phase 0. 0 12 PBPGPH1 Pulse Generator Phase 1. 16 12 PBSTD_1 A None Port_Standard 0x4002a140 0x0 0xffc registers PB Output Latch 0x0 0x0000FFFF 0xFFFFFFFF PB Output Latch. 0 16 PBPIN Pin Value 0x10 0x00000000 0xFFFFFFFF PBPIN Pin Value. 0 16 read-only PBMDSEL Mode Select 0x20 0x0000FFFF 0xFFFFFFFF PBMDSEL Mode Select. 0 16 PBSKIPEN Crossbar Pin Skip Enable 0x30 0x00000000 0xFFFFFFFF PBSKIPEN Crossbar Pin Skip Enable. 0 16 PBOUTMD Output Mode 0x40 0x00000000 0xFFFFFFFF PBOUTMD Output Mode. 0 16 PBDRV Drive Strength 0x50 0x00010000 0xFFFFFFFF PBDRV Drive Strength. 0 16 PBPUEN Port Bank Weak Pull-up Enable. 16 1 DISABLED Disable weak pull-ups for this port. 0 ENABLED Enable weak pull-ups for this port. 1 PM Port Match Value 0x60 0x00000000 0xFFFFFFFF PM Port Match Value. 0 16 PMEN Port Match Enable 0x70 0x00000000 0xFFFFFFFF PMEN Port Match Enable. 0 16 PBSTD_2 A None Port_Standard 0x4002a1e0 0x0 0xffc registers PB Output Latch 0x0 0x0000FFFF 0xFFFFFFFF PB Output Latch. 0 16 PBPIN Pin Value 0x10 0x00000000 0xFFFFFFFF PBPIN Pin Value. 0 16 read-only PBMDSEL Mode Select 0x20 0x0000FFFF 0xFFFFFFFF PBMDSEL Mode Select. 0 16 PBSKIPEN Crossbar Pin Skip Enable 0x30 0x00000000 0xFFFFFFFF PBSKIPEN Crossbar Pin Skip Enable. 0 16 PBOUTMD Output Mode 0x40 0x00000000 0xFFFFFFFF PBOUTMD Output Mode. 0 16 PBDRV Drive Strength 0x50 0x00010000 0xFFFFFFFF PBDRV Drive Strength. 0 16 PBPUEN Port Bank Weak Pull-up Enable. 16 1 DISABLED Disable weak pull-ups for this port. 0 ENABLED Enable weak pull-ups for this port. 1 PM Port Match Value 0x60 0x00000000 0xFFFFFFFF PM Port Match Value. 0 16 PMEN Port Match Enable 0x70 0x00000000 0xFFFFFFFF PMEN Port Match Enable. 0 16 PBSTD_3 A None Port_Standard 0x4002a280 0x0 0xffc registers PB Output Latch 0x0 0x0000FFFF 0xFFFFFFFF PB Output Latch. 0 16 PBPIN Pin Value 0x10 0x00000000 0xFFFFFFFF PBPIN Pin Value. 0 16 read-only PBMDSEL Mode Select 0x20 0x0000FFFF 0xFFFFFFFF PBMDSEL Mode Select. 0 16 PBSKIPEN Crossbar Pin Skip Enable 0x30 0x00000000 0xFFFFFFFF PBSKIPEN Crossbar Pin Skip Enable. 0 16 PBOUTMD Output Mode 0x40 0x00000000 0xFFFFFFFF PBOUTMD Output Mode. 0 16 PBDRV Drive Strength 0x50 0x00010000 0xFFFFFFFF PBDRV Drive Strength. 0 16 PBPUEN Port Bank Weak Pull-up Enable. 16 1 DISABLED Disable weak pull-ups for this port. 0 ENABLED Enable weak pull-ups for this port. 1 PM Port Match Value 0x60 0x00000000 0xFFFFFFFF PM Port Match Value. 0 16 PMEN Port Match Enable 0x70 0x00000000 0xFFFFFFFF PMEN Port Match Enable. 0 16 RTC_0 B None RTC_0 0x40029000 0x0 0xffc registers RTC0ALRM_IRQn 3 RTC0FAIL_IRQn 37 CONFIG RTC Configuration 0x0 0x00000000 0xFFFFFFFF ALM0AREN Alarm 0 Automatic Reset Enable. 0 1 DISABLED Disable the Alarm 0 automatic reset. 0 ENABLED Enable the Alarm 0 automatic reset. 1 RUN RTC Timer Run Control. 1 1 STOP Stop the RTC timer. 0 START Run the RTC timer. 1 MCLKEN Missing Clock Detector Enable. 2 1 DISABLED Disable the missing clock detector. 0 ENABLED Enable the missing clock detector. If the missing clock detector triggers, it will generate an RTC Fail event. 1 ASEN Automatic Crystal Load Capacitance Stepping Enable. 3 1 DISABLED Disable automatic load capacitance stepping. 0 ENABLED Enable automatic load capacitance stepping. 1 RTCLC Load Capacitance Value. 4 4 BDEN Bias Doubler Enable. 16 1 DISABLED Disable the bias doubler, saving power. 0 ENABLED Enable the bias doubler. 1 CRYSEN Crystal Oscillator Enable. 17 1 DISABLED Disable the crystal oscillator circuitry. 0 ENABLED Enable the crystal oscillator circuitry. 1 AGCEN Automatic Gain Control Enable. 18 1 DISABLED Disable automatic gain control. 0 ENABLED Enable automatic gain control, saving power. 1 ALM0EN Alarm 0 Enable. 24 1 DISABLED Disable RTC Alarm 0. 0 ENABLED Enable RTC Alarm 0. 1 ALM1EN Alarm 1 Enable. 25 1 DISABLED Disable RTC Alarm 1. 0 ENABLED Enable RTC Alarm 1. 1 ALM2EN Alarm 2 Enable. 26 1 DISABLED Disable RTC Alarm 2. 0 ENABLED Enable RTC Alarm 2. 1 CLKOEN RTC Clock Output Enable. 28 1 DISABLED Disable the RTCnTCLK output to the timer and other internal modules. 0 ENABLED Enable the RTCnTCLK output to the timer and other internal modules. 1 RTCOEN RTC External Output Enable. 29 1 DISABLED Disable the external RTCnTCLK_OUT output. 0 ENABLED Enable the external RTCnTCLK_OUT output. 1 CLKSEL RTC Timer Clock Select. 30 1 RTCNOSC Select the External Crystal or External CMOS Clock as the RTC Timer clock (RTCnTCLK) source. 0 LFOSCN Select the Low Frequency Oscillator as the RTC Timer clock (RTCnTCLK) source. 1 RTCEN RTC Timer Enable. 31 1 DISABLED Disable the RTC timer. 0 ENABLED Enable the RTC timer. 1 CONTROL RTC Control 0x10 0x00000000 0xFFFFFFFF ALM0I Alarm 0 Interrupt Flag. 0 1 NOT_SET Alarm 0 event has not occurred. 0 SET Alarm 0 event occurred. 1 ALM1I Alarm 1 Interrupt Flag. 1 1 NOT_SET Alarm 1 event has not occurred. 0 SET Alarm 1 event occurred. 1 ALM2I Alarm 2 Interrupt Flag. 2 1 NOT_SET Alarm 2 event has not occurred. 0 SET Alarm 2 event occurred. 1 TMRCAP RTC Timer Capture. 3 1 NOT_SET RTC timer capture operation is complete. 0 SET Start the RTC timer capture. 1 TMRSET RTC Timer Set. 4 1 NOT_SET RTC timer set operation is complete. 0 SET Start the RTC timer set. 1 CLKVF RTC External Oscillator Valid Flag. 5 1 read-only NOT_SET External oscillator is not valid. 0 SET External oscillator is valid. 1 OSCFI RTC Oscillator Fail Interrupt Flag. 6 1 NOT_SET Oscillator is running. 0 SET Oscillator has failed. 1 HSMDEN RTC High Speed Mode Enable. 7 1 DISABLED Disable high speed mode. (AHBCLK < 4x RTCnTCLK) 0 ENABLED Enable high speed mode. (AHBCLK >= 4x RTCnTCLK) 1 LRDYF RTC Load Capacitance Ready Flag. 8 1 read-only NOT_SET The load capacitance is currently stepping. 0 SET The load capacitance has reached its programmed value. 1 ALARM0 RTC Alarm 0 0x20 0x00000000 0xFFFFFFFF ALARM0 RTC Alarm 0. 0 32 ALARM1 RTC Alarm 1 0x30 0x00000000 0xFFFFFFFF ALARM1 RTC Alarm 1. 0 32 ALARM2 RTC Alarm 2 0x40 0x00000000 0xFFFFFFFF ALARM2 RTC Alarm 2. 0 32 SETCAP RTC Timer Set/Capture Value 0x50 0x00000000 0xFFFFFFFF SETCAP RTC Timer Set/Capture Value. 0 32 LFOCONTROL LFOSC Control 0x60 0xC0000000 0xFFFFFFFF LFOOEN Low Frequency Oscillator Output Enable. 30 1 DISABLED Disable the Low Frequency Oscillator output to internal modules. 0 ENABLED Enable the Low Frequency Oscillator output to internal module. 1 LFOSCEN Low Frequency Oscillator Enable. 31 1 DISABLED Disable the Low Frequency Oscillator (LFOSCn). 0 ENABLED Enable the Low Frequency Oscillator (LFOSCn). 1 RSTSRC_0 A None RSTSRC_0 0x4002c000 0x0 0xffc registers RESETEN System Reset Source Enable 0x0 0x0000082F 0xFFFFFFFF VMONREN Voltage Supply Monitor VBAT Reset Enable. 2 1 DISABLED Disable the Voltage Supply Monitor VBAT event as a reset source. 0 ENABLED Enable the Voltage Supply Monitor VBAT event as a reset source. 1 MCDREN Missing Clock Detector Reset Enable. 4 1 DISABLED Disable the Missing Clock Detector event as a reset source. 0 ENABLED Enable the Missing Clock Detector event as a reset source. 1 WDTREN Watchdog Timer Reset Enable. 5 1 DISABLED Disable the Watchdog Timer event as a reset source. 0 ENABLED Enable the Watchdog Timer event as a reset source. 1 SWREN Software Reset. 6 1 DISABLED Do not generate a Software Reset. 0 ENABLED Generate a Software Reset. 1 CMP0REN Comparator 0 Reset Enable. 7 1 DISABLED Disable the Comparator 0 event as a reset source. 0 ENABLED Enable the Comparator 0 event as a reset source. 1 CMP1REN Comparator 1 Reset Enable. 8 1 DISABLED Disable the Comparator 1 event as a reset source. 0 ENABLED Enable the Comparator 1 event as a reset source. 1 CPFREN Low Power Mode Charge Pump Supply Fail Reset Enable. 9 1 DISABLED Disable the low power mode charge pump supply fail event as a reset source. 0 ENABLED Enable the low power mode charge pump supply fail event as a reset source. 1 RTC0REN RTC0 Reset Enable. 10 1 DISABLED Disable the RTC0 event as a reset source. 0 ENABLED Enable the RTC0 event as a reset source. 1 CPMREN Low Power Mode Charge Pump Module Reset Enable. 27 1 DISABLED Disable low power mode charge pump module resets. 0 ENABLED Enable low power mode charge pump module resets. 1 UART0MREN UART0 Module Reset Enable. 28 1 DISABLED Disable UART0 module resets. 0 ENABLED Enable UART0 module resets. 1 LCD0MREN LCD0 Module Reset Enable. 29 1 DISABLED Disable LCD0 module resets. 0 ENABLED Enable LCD0 module resets. 1 ACC0MREN ACCTR0 Module Reset Enable. 30 1 DISABLED Disable ACCTR0 module resets. 0 ENABLED Enable ACCTR0 module resets. 1 RTC0MREN RTC0 Module Reset Enable. 31 1 DISABLED Disable RTC0 module resets. 0 ENABLED Enable RTC0 module resets. 1 RESETFLAG System Reset Flags 0x10 0x00000002 0xFFFFFFFF PINRF Pin Reset Flag. 0 1 read-only NOT_SET A /RESET pin event did not cause the last system reset. 0 SET A /RESET pin event caused the last system reset. 1 PORRF Power-On Reset Flag. 1 1 read-only NOT_SET A Power-On Reset event did not cause the last system reset. 0 SET A Power-On Reset event caused the last system reset. 1 VMONRF Voltage Supply Monitor VBAT Reset Flag. 2 1 read-only NOT_SET A Voltage Supply Monitor VBAT Reset event did not cause the last system reset. 0 SET A Voltage Supply Monitor VBAT Reset event caused the last system reset. 1 CORERF Core Reset Flag. 3 1 read-only NOT_SET A Core Reset event did not cause the last system reset. 0 SET A Core Reset event caused the last system reset. 1 MCDRF Missing Clock Detector Reset Flag. 4 1 read-only NOT_SET A Missing Clock Detector event did not cause the last system reset. 0 SET A Missing Clock Detector event caused the last system reset. 1 WDTRF Watchdog Timer Reset Flag. 5 1 read-only NOT_SET A Watchdog Timer event did not cause the last system reset. 0 SET A Watchdog Timer event caused the last system reset. 1 SWRF Software Reset Flag. 6 1 read-only NOT_SET A Software Reset event did not cause the last system reset. 0 SET A Software Reset event caused the last system reset. 1 CMP0RF Comparator 0 Reset Flag. 7 1 read-only NOT_SET A Comparator 0 event did not cause the last system reset. 0 SET A Comparator 0 event caused the last system reset. 1 CMP1RF Comparator 1 Reset Flag. 8 1 read-only NOT_SET A Comparator 1 event did not cause the last system reset. 0 SET A Comparator 1 event caused the last system reset. 1 CPFRF Low Power Mode Charge Pump Supply Fail Reset Flag. 9 1 read-only NOT_SET A low power mode charge pump supply fail event did not cause the last system reset. 0 SET A low power mode charge pump supply fail event caused the last system reset. 1 RTC0RF RTC0 Reset Flag. 10 1 read-only NOT_SET An RTC0 event did not cause the last system reset. 0 SET An RTC0 event caused the last system reset. 1 WAKERF PMU Wakeup Reset Flag. 11 1 read-only NOT_SET A PMU Wakeup event did not cause the last system reset. 0 SET A PMU Wakeup event caused the last system reset. 1 SARADC_0 A None SARADC_0 0x4001a000 0x0 0xffc registers SARADC0_IRQn 29 CONFIG Module Configuration 0x0 0x00000000 0xFFFFFFFF PACKMD Output Packing Mode. 6 2 UPPER_ONLY Data is written to the upper half-word and the lower half-word is filled with 0's. An SCI interrupt is triggered when data is written, if enabled. 0 LOWER_ONLY Data is written to the lower half-word, and the upper half-word is filled with 0's. An SCI interrupt is triggered when data is written, if enabled. 1 UPPER_FIRST Two data words are packed into the register with the upper half-word representing the earlier data, and the lower half-word representing the later data. The ADC write to the lower half-word will trigger the SCI interrupt, if enabled. 2 LOWER_FIRST Two data words are packed into the register with the lower half-word representing the earlier data, and the upper half-word representing the later data. The ADC write to the upper half-word will trigger the SCI interrupt, if enabled. 3 SCANEN Scan Mode Enable. 10 1 DISABLED Disable ADC scan mode. 0 ENABLED Enable ADC scan mode. The ADC will scan through the defined time slots in sequence on every start of conversion. 1 SCANMD Scan Mode Select. 12 1 ONCE The channel sequencer will cycle through all of the specified time slots once. 0 LOOP The channel sequencer will cycle through all of the specified time slots in a loop until SCANEN is cleared to 0. 1 DMAEN DMA Interface Enable . 14 1 DISABLED Disable the ADC module DMA interface. 0 ENABLED Enable the ADC module DMA interface. 1 BCLKSEL Burst Mode Clock Select. 15 1 LPOSC0 Burst mode uses the Low Power Oscillator. 0 APB Burst mode uses the APB clock. 1 CLKDIV SAR Clock Divider. 16 11 SCCIEN Single Conversion Complete Interrupt Enable. 27 1 DISABLED Disable the ADC single data conversion complete interrupt. 0 ENABLED Enable the ADC single data conversion complete interrupt. 1 SDIEN Scan Done Interrupt Enable. 28 1 DISABLED Disable the ADC scan complete interrupt. 0 ENABLED Enable the ADC scan complete interrupt. 1 FORIEN FIFO Overrun Interrupt Enable. 29 1 DISABLED Disable the data FIFO overrun interrupt. 0 ENABLED Enable the data FIFO overrun interrupt. 1 FURIEN FIFO Underrun Interrupt Enable. 30 1 DISABLED Disable the data FIFO underrun interrupt. 0 ENABLED Enable the data FIFO underrun interrupt. 1 CONTROL Measurement Control 0x10 0x1008F078 0xFFFFFFFF REFGNDSEL Reference Ground Select. 0 1 INTERNAL The internal device ground is used as the ground reference for ADC conversions. 0 EXTERNAL The VREFGND pin is used as the ground reference for ADC conversions. 1 CLKESEL Sampling Clock Edge Select. 1 1 RISING Select the rising edge of the APB clock. 0 FALLING Select the falling edge of the APB clock. 1 BMTK Burst Mode Tracking Time. 2 6 SCSEL Start-Of-Conversion Source Select. 8 4 ADCNT0 An ADC conversion triggers from the ADCnT0 ("On Demand" by writing 1 to ADBUSY) trigger source. 0 ADCNT1 An ADC conversion triggers from the ADCnT1 (Timer 0 Low Overflow) trigger source. 1 ADCNT2 An ADC conversion triggers from the ADCnT2 (Timer 0 High Overflow) trigger source. 2 ADCNT3 An ADC conversion triggers from the ADCnT3 (Timer 1 Low Overflow) trigger source. 3 ADCNT4 An ADC conversion triggers from the ADCnT4 (Timer 1 High Overflow) trigger source. 4 ADCNT5 An ADC conversion triggers from the ADCnT5 (EPCA0 synchronization pulse) trigger source. 5 ADCNT6 An ADC conversion triggers from the ADCnT6 (I2C0 Timer overflow) trigger source. 6 ADCNT7 An ADC conversion triggers from the ADCnT7 (RESERVED) trigger source. 7 ADCNT8 An ADC conversion triggers from the ADCnT8 (RESERVED) trigger source. 8 ADCNT9 An ADC conversion triggers from the ADCnT9 (RESERVED) trigger source. 9 ADCNT10 An ADC conversion triggers from the ADCnT10 (RESERVED) trigger source. 10 ADCNT11 An ADC conversion triggers from the ADCnT11 (RESERVED) trigger source. 11 ADCNT12 An ADC conversion triggers from the ADCnT12 (RESERVED) trigger source. 12 ADCNT13 An ADC conversion triggers from the ADCnT13 (RESERVED) trigger source. 13 ADCNT14 An ADC conversion triggers from the ADCnT14 (RESERVED) trigger source. 14 ADCNT15 An ADC conversion triggers from the ADCnT15 (ADCnT15 routed through crossbar) trigger source. 15 PWRTIME Burst Mode Power Up Time. 12 4 BURSTEN Burst Mode Enable. 16 1 DISABLED Disable burst mode. 0 ENABLED Enable burst mode. 1 ADCEN ADC Enable. 17 1 DISABLED Disable the ADC (low-power shutdown). 0 ENABLED Enable the ADC (active and ready for data conversions). 1 AD12BSSEL 12-Bit Mode Sample Select. 18 1 FOUR The ADC re-samples the input before each of the four conversions. 0 ONE The ADC samples once before the first conversion and converts four times. 1 VCMEN Common Mode Buffer Enable. 19 1 DISABLED Disable the common mode buffer. 0 ENABLED Enable the common mode buffer. 1 ACCMD Accumulation Mode. 21 1 ACCUMULATE Conversions will be accumulated for the specified number of cycles in burst mode according to the channel configuration. 0 REPEAT Conversions will not be accumulated in burst mode. 1 TRKMD ADC Tracking Mode. 22 1 NORMAL Normal Tracking Mode: When the ADC is enabled, a conversion begins immediately following the start-of-conversion signal. 0 DELAYED Delayed Tracking Mode: When the ADC is enabled, a conversion begins 3 SAR clock cycles following the start-of-conversion signal. The ADC is allowed to track during this time. 1 ADBUSY ADC Busy. 23 1 BIASSEL Bias Power Select. 24 2 MODE0 Select bias current mode 0. Recommended to use modes 1, 2, or 3. 0 MODE1 Select bias current mode 1 (SARCLK = 16 MHz). 1 MODE2 Select bias current mode 2. 2 MODE3 Select bias current mode 3 (SARCLK = 4 MHz). 3 LPMDEN Low Power Mode Enable. 26 1 DISABLED Disable low power mode. 0 ENABLED Enable low power mode (requires extended tracking time). 1 MREFLPEN MUX and VREF Low Power Enable. 27 1 DISABLED Disable low power mode. 0 ENABLED Enable low power mode (SAR clock <= 4 MHz). 1 VREFSEL Voltage Reference Select. 30 2 INTERNAL_VREF Select the internal, dedicated SARADC voltage reference as the ADC reference. 0 VDD Select the VBAT pin as the ADC reference. 1 LDO_OUT Select the output of the internal LDO regulator (~1.8 V) as the ADC reference. 2 EXTERNAL_VREF Select the VREF pin as the ADC reference. This option is used for either an external VREF or the on-chip VREF driving out to the VREF pin. 3 SQ7654 Channel Sequencer Time Slots 4-7 Setup 0x20 0x00000000 0xFFFFFFFF TS4CHR Time Slot 4 Conversion Characteristic. 0 2 CC0 Select conversion characteristic 0 for time slot 4. 0 CC1 Select conversion characteristic 1 for time slot 4. 1 CC2 Select conversion characteristic 2 for time slot 4. 2 CC3 Select conversion characteristic 3 for time slot 4. 3 TS4MUX Time Slot 4 Input Channel. 2 5 ADCN0 Select channel ADCn.0 (PB0.3). 0 ADCN1 Select channel ADCn.1 (PB0.8). 1 ADCN2 Select channel ADCn.2 (PB0.9). 2 ADCN3 Select channel ADCn.3 (PB1.4). 3 ADCN4 Select channel ADCn.4 (PB1.5). 4 ADCN5 Select channel ADCn.5 (PB1.6). 5 ADCN6 Select channel ADCn.6 (PB2.0). 6 ADCN7 Select channel ADCn.7 (PB2.4). 7 ADCN8 Select channel ADCn.8 (PB2.5). 8 ADCN9 Select channel ADCn.9 (PB2.6). 9 ADCN10 Select channel ADCn.10 (PB2.7). 10 ADCN11 Select channel ADCn.11 (PB3.0). 11 ADCN12 Select channel ADCn.12 (PB3.1). 12 ADCN13 Select channel ADCn.13 (PB3.8). 13 ADCN14 Select channel ADCn.14 (PB3.9). 14 ADCN15 Select channel ADCn.15 (PB3.10). 15 ADCN16 Select channel ADCn.16 (PB3.11). 16 ADCN17 Select channel ADCn.17 (PB4.0). 17 ADCN18 Select channel ADCn.18 (PB4.1). 18 ADCN19 Select channel ADCn.19 (PB4.2). 19 ADCN20 Select channel ADCn.20 (PB0.0). 20 ADCN21 Select channel ADCn.21 (RESERVED). 21 ADCN22 Select channel ADCn.22 (PB0.2). 22 ADCN23 Select channel ADCn.23 (PB0.3). 23 ADCN24 Select channel ADCn.24 (VSS). 24 ADCN25 Select channel ADCn.25 (Digital LDO Output). 25 ADCN26 Select channel ADCn.26 (Memory LDO Output). 26 ADCN27 Select channel ADCn.27 (VDC). 27 ADCN28 Select channel ADCn.28 (VBAT). 28 ADCN29 Select channel ADCn.29 (1/2 Charge Pump Output). 29 ADCN30 Select channel ADCn.30 (Temperature Sensor Output). 30 END None - End the sequence. 31 TS5CHR Time Slot 5 Conversion Characteristic. 8 2 CC0 Select conversion characteristic 0 for time slot 5. 0 CC1 Select conversion characteristic 1 for time slot 5. 1 CC2 Select conversion characteristic 2 for time slot 5. 2 CC3 Select conversion characteristic 3 for time slot 5. 3 TS5MUX Time Slot 5 Input Channel. 10 5 ADCN0 Select channel ADCn.0 (PB0.3). 0 ADCN1 Select channel ADCn.1 (PB0.8). 1 ADCN2 Select channel ADCn.2 (PB0.9). 2 ADCN3 Select channel ADCn.3 (PB1.4). 3 ADCN4 Select channel ADCn.4 (PB1.5). 4 ADCN5 Select channel ADCn.5 (PB1.6). 5 ADCN6 Select channel ADCn.6 (PB2.0). 6 ADCN7 Select channel ADCn.7 (PB2.4). 7 ADCN8 Select channel ADCn.8 (PB2.5). 8 ADCN9 Select channel ADCn.9 (PB2.6). 9 ADCN10 Select channel ADCn.10 (PB2.7). 10 ADCN11 Select channel ADCn.11 (PB3.0). 11 ADCN12 Select channel ADCn.12 (PB3.1). 12 ADCN13 Select channel ADCn.13 (PB3.8). 13 ADCN14 Select channel ADCn.14 (PB3.9). 14 ADCN15 Select channel ADCn.15 (PB3.10). 15 ADCN16 Select channel ADCn.16 (PB3.11). 16 ADCN17 Select channel ADCn.17 (PB4.0). 17 ADCN18 Select channel ADCn.18 (PB4.1). 18 ADCN19 Select channel ADCn.19 (PB4.2). 19 ADCN20 Select channel ADCn.20 (PB0.0). 20 ADCN21 Select channel ADCn.21 (RESERVED). 21 ADCN22 Select channel ADCn.22 (PB0.2). 22 ADCN23 Select channel ADCn.23 (PB0.3). 23 ADCN24 Select channel ADCn.24 (VSS). 24 ADCN25 Select channel ADCn.25 (Digital LDO Output). 25 ADCN26 Select channel ADCn.26 (Memory LDO Output). 26 ADCN27 Select channel ADCn.27 (VDC). 27 ADCN28 Select channel ADCn.28 (VBAT). 28 ADCN29 Select channel ADCn.29 (1/2 Charge Pump Output). 29 ADCN30 Select channel ADCn.30 (Temperature Sensor Output). 30 END None - End the sequence. 31 TS6CHR Time Slot 6 Conversion Characteristic. 16 2 CC0 Select conversion characteristic 0 for time slot 6. 0 CC1 Select conversion characteristic 1 for time slot 6. 1 CC2 Select conversion characteristic 2 for time slot 6. 2 CC3 Select conversion characteristic 3 for time slot 6. 3 TS6MUX Time Slot 6 Input Channel. 18 5 ADCN0 Select channel ADCn.0 (PB0.3). 0 ADCN1 Select channel ADCn.1 (PB0.8). 1 ADCN2 Select channel ADCn.2 (PB0.9). 2 ADCN3 Select channel ADCn.3 (PB1.4). 3 ADCN4 Select channel ADCn.4 (PB1.5). 4 ADCN5 Select channel ADCn.5 (PB1.6). 5 ADCN6 Select channel ADCn.6 (PB2.0). 6 ADCN7 Select channel ADCn.7 (PB2.4). 7 ADCN8 Select channel ADCn.8 (PB2.5). 8 ADCN9 Select channel ADCn.9 (PB2.6). 9 ADCN10 Select channel ADCn.10 (PB2.7). 10 ADCN11 Select channel ADCn.11 (PB3.0). 11 ADCN12 Select channel ADCn.12 (PB3.1). 12 ADCN13 Select channel ADCn.13 (PB3.8). 13 ADCN14 Select channel ADCn.14 (PB3.9). 14 ADCN15 Select channel ADCn.15 (PB3.10). 15 ADCN16 Select channel ADCn.16 (PB3.11). 16 ADCN17 Select channel ADCn.17 (PB4.0). 17 ADCN18 Select channel ADCn.18 (PB4.1). 18 ADCN19 Select channel ADCn.19 (PB4.2). 19 ADCN20 Select channel ADCn.20 (PB0.0). 20 ADCN21 Select channel ADCn.21 (RESERVED). 21 ADCN22 Select channel ADCn.22 (PB0.2). 22 ADCN23 Select channel ADCn.23 (PB0.3). 23 ADCN24 Select channel ADCn.24 (VSS). 24 ADCN25 Select channel ADCn.25 (Digital LDO Output). 25 ADCN26 Select channel ADCn.26 (Memory LDO Output). 26 ADCN27 Select channel ADCn.27 (VDC). 27 ADCN28 Select channel ADCn.28 (VBAT). 28 ADCN29 Select channel ADCn.29 (1/2 Charge Pump Output). 29 ADCN30 Select channel ADCn.30 (Temperature Sensor Output). 30 END None - End the sequence. 31 TS7CHR Time Slot 7 Conversion Characteristic. 24 2 CC0 Select conversion characteristic 0 for time slot 7. 0 CC1 Select conversion characteristic 1 for time slot 7. 1 CC2 Select conversion characteristic 2 for time slot 7. 2 CC3 Select conversion characteristic 3 for time slot 7. 3 TS7MUX Time Slot 7 Input Channel. 26 5 ADCN0 Select channel ADCn.0 (PB0.3). 0 ADCN1 Select channel ADCn.1 (PB0.8). 1 ADCN2 Select channel ADCn.2 (PB0.9). 2 ADCN3 Select channel ADCn.3 (PB1.4). 3 ADCN4 Select channel ADCn.4 (PB1.5). 4 ADCN5 Select channel ADCn.5 (PB1.6). 5 ADCN6 Select channel ADCn.6 (PB2.0). 6 ADCN7 Select channel ADCn.7 (PB2.4). 7 ADCN8 Select channel ADCn.8 (PB2.5). 8 ADCN9 Select channel ADCn.9 (PB2.6). 9 ADCN10 Select channel ADCn.10 (PB2.7). 10 ADCN11 Select channel ADCn.11 (PB3.0). 11 ADCN12 Select channel ADCn.12 (PB3.1). 12 ADCN13 Select channel ADCn.13 (PB3.8). 13 ADCN14 Select channel ADCn.14 (PB3.9). 14 ADCN15 Select channel ADCn.15 (PB3.10). 15 ADCN16 Select channel ADCn.16 (PB3.11). 16 ADCN17 Select channel ADCn.17 (PB4.0). 17 ADCN18 Select channel ADCn.18 (PB4.1). 18 ADCN19 Select channel ADCn.19 (PB4.2). 19 ADCN20 Select channel ADCn.20 (PB0.0). 20 ADCN21 Select channel ADCn.21 (RESERVED). 21 ADCN22 Select channel ADCn.22 (PB0.2). 22 ADCN23 Select channel ADCn.23 (PB0.3). 23 ADCN24 Select channel ADCn.24 (VSS). 24 ADCN25 Select channel ADCn.25 (Digital LDO Output). 25 ADCN26 Select channel ADCn.26 (Memory LDO Output). 26 ADCN27 Select channel ADCn.27 (VDC). 27 ADCN28 Select channel ADCn.28 (VBAT). 28 ADCN29 Select channel ADCn.29 (1/2 Charge Pump Output). 29 ADCN30 Select channel ADCn.30 (Temperature Sensor Output). 30 END None - End the sequence. 31 SQ3210 Channel Sequencer Time Slots 0-3 Setup 0x30 0x00000000 0xFFFFFFFF TS0CHR Time Slot 0 Conversion Characteristic. 0 2 CC0 Select conversion characteristic 0 for time slot 0. 0 CC1 Select conversion characteristic 1 for time slot 0. 1 CC2 Select conversion characteristic 2 for time slot 0. 2 CC3 Select conversion characteristic 3 for time slot 0. 3 TS0MUX Time Slot 0 Input Channel. 2 5 ADCN0 Select channel ADCn.0 (PB0.3). 0 ADCN1 Select channel ADCn.1 (PB0.8). 1 ADCN2 Select channel ADCn.2 (PB0.9). 2 ADCN3 Select channel ADCn.3 (PB1.4). 3 ADCN4 Select channel ADCn.4 (PB1.5). 4 ADCN5 Select channel ADCn.5 (PB1.6). 5 ADCN6 Select channel ADCn.6 (PB2.0). 6 ADCN7 Select channel ADCn.7 (PB2.4). 7 ADCN8 Select channel ADCn.8 (PB2.5). 8 ADCN9 Select channel ADCn.9 (PB2.6). 9 ADCN10 Select channel ADCn.10 (PB2.7). 10 ADCN11 Select channel ADCn.11 (PB3.0). 11 ADCN12 Select channel ADCn.12 (PB3.1). 12 ADCN13 Select channel ADCn.13 (PB3.8). 13 ADCN14 Select channel ADCn.14 (PB3.9). 14 ADCN15 Select channel ADCn.15 (PB3.10). 15 ADCN16 Select channel ADCn.16 (PB3.11). 16 ADCN17 Select channel ADCn.17 (PB4.0). 17 ADCN18 Select channel ADCn.18 (PB4.1). 18 ADCN19 Select channel ADCn.19 (PB4.2). 19 ADCN20 Select channel ADCn.20 (PB0.0). 20 ADCN21 Select channel ADCn.21 (RESERVED). 21 ADCN22 Select channel ADCn.22 (PB0.2). 22 ADCN23 Select channel ADCn.23 (PB0.3). 23 ADCN24 Select channel ADCn.24 (VSS). 24 ADCN25 Select channel ADCn.25 (Digital LDO Output). 25 ADCN26 Select channel ADCn.26 (Memory LDO Output). 26 ADCN27 Select channel ADCn.27 (VDC). 27 ADCN28 Select channel ADCn.28 (VBAT). 28 ADCN29 Select channel ADCn.29 (1/2 Charge Pump Output). 29 ADCN30 Select channel ADCn.30 (Temperature Sensor Output). 30 END None - End the sequence. 31 TS1CHR Time Slot 1 Conversion Characteristic. 8 2 CC0 Select conversion characteristic 0 for time slot 1. 0 CC1 Select conversion characteristic 1 for time slot 1. 1 CC2 Select conversion characteristic 2 for time slot 1. 2 CC3 Select conversion characteristic 3 for time slot 1. 3 TS1MUX Time Slot 1 Input Channel. 10 5 ADCN0 Select channel ADCn.0 (PB0.3). 0 ADCN1 Select channel ADCn.1 (PB0.8). 1 ADCN2 Select channel ADCn.2 (PB0.9). 2 ADCN3 Select channel ADCn.3 (PB1.4). 3 ADCN4 Select channel ADCn.4 (PB1.5). 4 ADCN5 Select channel ADCn.5 (PB1.6). 5 ADCN6 Select channel ADCn.6 (PB2.0). 6 ADCN7 Select channel ADCn.7 (PB2.4). 7 ADCN8 Select channel ADCn.8 (PB2.5). 8 ADCN9 Select channel ADCn.9 (PB2.6). 9 ADCN10 Select channel ADCn.10 (PB2.7). 10 ADCN11 Select channel ADCn.11 (PB3.0). 11 ADCN12 Select channel ADCn.12 (PB3.1). 12 ADCN13 Select channel ADCn.13 (PB3.8). 13 ADCN14 Select channel ADCn.14 (PB3.9). 14 ADCN15 Select channel ADCn.15 (PB3.10). 15 ADCN16 Select channel ADCn.16 (PB3.11). 16 ADCN17 Select channel ADCn.17 (PB4.0). 17 ADCN18 Select channel ADCn.18 (PB4.1). 18 ADCN19 Select channel ADCn.19 (PB4.2). 19 ADCN20 Select channel ADCn.20 (PB0.0). 20 ADCN21 Select channel ADCn.21 (RESERVED). 21 ADCN22 Select channel ADCn.22 (PB0.2). 22 ADCN23 Select channel ADCn.23 (PB0.3). 23 ADCN24 Select channel ADCn.24 (VSS). 24 ADCN25 Select channel ADCn.25 (Digital LDO Output). 25 ADCN26 Select channel ADCn.26 (Memory LDO Output). 26 ADCN27 Select channel ADCn.27 (VDC). 27 ADCN28 Select channel ADCn.28 (VBAT). 28 ADCN29 Select channel ADCn.29 (1/2 Charge Pump Output). 29 ADCN30 Select channel ADCn.30 (Temperature Sensor Output). 30 END None - End the sequence. 31 TS2CHR Time Slot 2 Conversion Characteristic. 16 2 CC0 Select conversion characteristic 0 for time slot 2. 0 CC1 Select conversion characteristic 1 for time slot 2. 1 CC2 Select conversion characteristic 2 for time slot 2. 2 CC3 Select conversion characteristic 3 for time slot 2. 3 TS2MUX Time Slot 2 Input Channel. 18 5 ADCN0 Select channel ADCn.0 (PB0.3). 0 ADCN1 Select channel ADCn.1 (PB0.8). 1 ADCN2 Select channel ADCn.2 (PB0.9). 2 ADCN3 Select channel ADCn.3 (PB1.4). 3 ADCN4 Select channel ADCn.4 (PB1.5). 4 ADCN5 Select channel ADCn.5 (PB1.6). 5 ADCN6 Select channel ADCn.6 (PB2.0). 6 ADCN7 Select channel ADCn.7 (PB2.4). 7 ADCN8 Select channel ADCn.8 (PB2.5). 8 ADCN9 Select channel ADCn.9 (PB2.6). 9 ADCN10 Select channel ADCn.10 (PB2.7). 10 ADCN11 Select channel ADCn.11 (PB3.0). 11 ADCN12 Select channel ADCn.12 (PB3.1). 12 ADCN13 Select channel ADCn.13 (PB3.8). 13 ADCN14 Select channel ADCn.14 (PB3.9). 14 ADCN15 Select channel ADCn.15 (PB3.10). 15 ADCN16 Select channel ADCn.16 (PB3.11). 16 ADCN17 Select channel ADCn.17 (PB4.0). 17 ADCN18 Select channel ADCn.18 (PB4.1). 18 ADCN19 Select channel ADCn.19 (PB4.2). 19 ADCN20 Select channel ADCn.20 (PB0.0). 20 ADCN21 Select channel ADCn.21 (RESERVED). 21 ADCN22 Select channel ADCn.22 (PB0.2). 22 ADCN23 Select channel ADCn.23 (PB0.3). 23 ADCN24 Select channel ADCn.24 (VSS). 24 ADCN25 Select channel ADCn.25 (Digital LDO Output). 25 ADCN26 Select channel ADCn.26 (Memory LDO Output). 26 ADCN27 Select channel ADCn.27 (VDC). 27 ADCN28 Select channel ADCn.28 (VBAT). 28 ADCN29 Select channel ADCn.29 (1/2 Charge Pump Output). 29 ADCN30 Select channel ADCn.30 (Temperature Sensor Output). 30 END None - End the sequence. 31 TS3CHR Time Slot 3 Conversion Characteristic. 24 2 CC0 Select conversion characteristic 0 for time slot 3. 0 CC1 Select conversion characteristic 1 for time slot 3. 1 CC2 Select conversion characteristic 2 for time slot 3. 2 CC3 Select conversion characteristic 3 for time slot 3. 3 TS3MUX Time Slot 3 Input Channel. 26 5 ADCN0 Select channel ADCn.0 (PB0.3). 0 ADCN1 Select channel ADCn.1 (PB0.8). 1 ADCN2 Select channel ADCn.2 (PB0.9). 2 ADCN3 Select channel ADCn.3 (PB1.4). 3 ADCN4 Select channel ADCn.4 (PB1.5). 4 ADCN5 Select channel ADCn.5 (PB1.6). 5 ADCN6 Select channel ADCn.6 (PB2.0). 6 ADCN7 Select channel ADCn.7 (PB2.4). 7 ADCN8 Select channel ADCn.8 (PB2.5). 8 ADCN9 Select channel ADCn.9 (PB2.6). 9 ADCN10 Select channel ADCn.10 (PB2.7). 10 ADCN11 Select channel ADCn.11 (PB3.0). 11 ADCN12 Select channel ADCn.12 (PB3.1). 12 ADCN13 Select channel ADCn.13 (PB3.8). 13 ADCN14 Select channel ADCn.14 (PB3.9). 14 ADCN15 Select channel ADCn.15 (PB3.10). 15 ADCN16 Select channel ADCn.16 (PB3.11). 16 ADCN17 Select channel ADCn.17 (PB4.0). 17 ADCN18 Select channel ADCn.18 (PB4.1). 18 ADCN19 Select channel ADCn.19 (PB4.2). 19 ADCN20 Select channel ADCn.20 (PB0.0). 20 ADCN21 Select channel ADCn.21 (RESERVED). 21 ADCN22 Select channel ADCn.22 (PB0.2). 22 ADCN23 Select channel ADCn.23 (PB0.3). 23 ADCN24 Select channel ADCn.24 (VSS). 24 ADCN25 Select channel ADCn.25 (Digital LDO Output). 25 ADCN26 Select channel ADCn.26 (Memory LDO Output). 26 ADCN27 Select channel ADCn.27 (VDC). 27 ADCN28 Select channel ADCn.28 (VBAT). 28 ADCN29 Select channel ADCn.29 (1/2 Charge Pump Output). 29 ADCN30 Select channel ADCn.30 (Temperature Sensor Output). 30 END None - End the sequence. 31 CHAR32 Conversion Characteristic 2 and 3 Setup 0x40 0x00000000 0xFFFFFFFF CHR2GN Conversion Characteristic 2 Gain. 0 1 UNITY The on-chip PGA gain is 1. 0 HALF The on-chip PGA gain is 0.5. 1 CHR2RPT Conversion Characteristic 2 Repeat Counter. 1 3 ACC1 Accumulate one sample. 0 ACC4 Accumulate four samples. 1 ACC8 Accumulate eight samples. 2 ACC16 Accumulate sixteen samples. 3 ACC32 Accumulate thirty-two samples (10-bit mode only). 4 ACC64 Accumulate sixty-four samples (10-bit mode only). 5 CHR2LS Conversion Characteristic 2 Left-Shift Bits. 4 3 CHR2RSEL Conversion Characteristic 2 Resolution Selection. 7 1 B10 Select 10-bit Mode. 0 B12 Select 12-bit Mode (burst mode must be enabled). 1 CHR2WCIEN Conversion Characteristic 2 Window Comparator Interrupt Enable. 8 1 DISABLED Disable window comparison interrupts. 0 ENABLED Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic. 1 CHR3GN Conversion Characteristic 3 Gain. 16 1 UNITY The on-chip PGA gain is 1. 0 HALF The on-chip PGA gain is 0.5. 1 CHR3RPT Conversion Characteristic 3 Repeat Counter. 17 3 ACC1 Accumulate one sample. 0 ACC4 Accumulate four samples. 1 ACC8 Accumulate eight samples. 2 ACC16 Accumulate sixteen samples. 3 ACC32 Accumulate thirty-two samples (10-bit mode only). 4 ACC64 Accumulate sixty-four samples (10-bit mode only). 5 CHR3LS Conversion Characteristic 3 Left-Shift Bits. 20 3 CHR3RSEL Conversion Characteristic 3 Resolution Selection. 23 1 B10 Select 10-bit Mode. 0 B12 Select 12-bit Mode (burst mode must be enabled). 1 CHR3WCIEN Conversion Characteristic 3 Window Comparator Interrupt Enable. 24 1 DISABLED Disable window comparison interrupts. 0 ENABLED Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic. 1 CHAR10 Conversion Characteristic 0 and 1 Setup 0x50 0x00000000 0xFFFFFFFF CHR0GN Conversion Characteristic 0 Gain. 0 1 UNITY The on-chip PGA gain is 1. 0 HALF The on-chip PGA gain is 0.5. 1 CHR0RPT Conversion Characteristic 0 Repeat Counter. 1 3 ACC1 Accumulate one sample. 0 ACC4 Accumulate four samples. 1 ACC8 Accumulate eight samples. 2 ACC16 Accumulate sixteen samples. 3 ACC32 Accumulate thirty-two samples (10-bit mode only). 4 ACC64 Accumulate sixty-four samples (10-bit mode only). 5 CHR0LS Conversion Characteristic 0 Left-Shift Bits. 4 3 CHR0RSEL Conversion Characteristic 0 Resolution Selection. 7 1 B10 Select 10-bit Mode. 0 B12 Select 12-bit Mode (burst mode must be enabled). 1 CHR0WCIEN Conversion Characteristic 0 Window Comparator Interrupt Enable. 8 1 DISABLED Disable window comparison interrupts. 0 ENABLED Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic. 1 CHR1GN Conversion Characteristic 1 Gain. 16 1 UNITY The on-chip PGA gain is 1. 0 HALF The on-chip PGA gain is 0.5. 1 CHR1RPT Conversion Characteristic 1 Repeat Counter. 17 3 ACC1 Accumulate one sample. 0 ACC4 Accumulate four samples. 1 ACC8 Accumulate eight samples. 2 ACC16 Accumulate sixteen samples. 3 ACC32 Accumulate thirty-two samples (10-bit mode only). 4 ACC64 Accumulate sixty-four samples (10-bit mode only). 5 CHR1LS Conversion Characteristic 1 Left-Shift Bits. 20 3 CHR1RSEL Conversion Characteristic 1 Resolution Selection. 23 1 B10 Select 10-bit Mode. 0 B12 Select 12-bit Mode (burst mode must be enabled). 1 CHR1WCIEN Conversion Characteristic 1 Window Comparator Interrupt Enable. 24 1 DISABLED Disable window comparison interrupts. 0 ENABLED Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic. 1 DATA Output Data Word 0x60 0x00000000 0xFFFFFFFF DATA Output Data Word. 0 32 read-only WCLIMITS Window Comparator Limits 0x70 0x00000000 0xFFFFFFFF WCLT Less-Than Window Comparator Limit. 0 16 WCGT Greater-Than Window Comparator Limit. 16 16 ACC Accumulator Initial Value 0x80 0x00000000 0xFFFFFFFF ACC Accumulator Initial Value. 0 16 write-only STATUS Module Status 0x90 0x00000000 0xFFFFFFFF WCI Window Compare Interrupt. 0 1 NOT_SET Read: A window compare interrupt has not occurred. Write: Clear the interrupt. 0 SET Read: A window compare interrupt occurred. Write: Force a window compare interrupt. 1 SCCI Single Conversion Complete Interrupt. 1 1 NOT_SET Read: A single data conversion interrupt has not occurred. Write: Clear the interrupt. 0 SET Read: A single data conversion interrupt occurred. Write: Force a single data conversion interrupt. 1 SDI Scan Done Interrupt. 2 1 NOT_SET Read: A scan done interrupt has not occurred. Write: Clear the interrupt. 0 SET Read: A scan done interrupt occurred. Write: Force a scan done interrupt. 1 FORI FIFO Overrun Interrupt. 3 1 NOT_SET Read: A data FIFO overrun interrupt has not occurred. Write: Clear the interrupt. 0 SET Read: A data FIFO overrun interrupt occurred. Write: Force a data FIFO overrun interrupt. 1 FURI FIFO Underrun Interrupt. 4 1 NOT_SET Read: A data FIFO underrun interrupt has not occurred. Write: Clear the interrupt. 0 SET Read: A data FIFO underrun interrupt occurred. Write: Force a data FIFO underrun interrupt. 1 FIFOSTATUS FIFO Status 0xa0 0x00000010 0xFFFFFFFF FIFOLVL FIFO Level. 0 4 read-only DPSTS Data Packing Status. 4 1 read-only LOWER The next ADC conversion will be written to the lower half-word. 0 UPPER The next ADC conversion will be written to the upper half-word. 1 DRDYF Data Ready Flag. 5 1 read-only NOT_SET New data is not produced yet. 0 SET New data is ready. 1 SPI_0 B None SPI 0x40004000 0x0 0xffc registers SPI0_IRQn 26 DATA Input/Output Data 0x0 0x00000000 0xFFFFFFFF modifyExternal DATA Input/Output Data. 0 32 CONTROL Module Control 0x10 0x00004084 0xFFFFFFFF RFRQI Receive FIFO Read Request Interrupt Flag. 0 1 read-only NOT_SET The RX FIFO has fewer bytes than the level defined by RFTH. 0 SET The RX FIFO has equal or more bytes than the level defined by RFTH. 1 RFORI Receive FIFO Overrun Interrupt Flag. 1 1 NOT_SET Read: A receive FIFO overrun has not occurred. Write: Clear the flag. 0 SET Read: A receive FIFO overrun occurred. Write: Force a receive overrun interrupt. 1 TFRQI Transmit FIFO Write Request Interrupt Flag. 2 1 read-only NOT_SET The TX FIFO has fewer empty slots than the level defined by TFTH. 0 SET The TX FIFO has at least as many empty slots as the level defined by TFTH. 1 TFORI Transmit FIFO Overrun Interrupt Flag. 3 1 NOT_SET Read: A transmit FIFO overrun has not occurred. Write: Clear the flag. 0 SET Read: A transmit FIFO overrun occurred. Write: Force a transmit overrun interrupt. 1 SLVSELI Slave Selected Interrupt Flag. 4 1 read-only NOT_SET The slave select signal (NSS) is not active. 0 SET The slave select signal (NSS) is active. 1 MDFI Mode Fault Interrupt Flag. 5 1 NOT_SET Read: A master mode collision is not detected. Write: Clear the flag. 0 SET Read: A master mode collision occurred. Write: Force a mode fault interrupt. 1 URI Underrun Interrupt Flag. 6 1 NOT_SET Read: A data transfer is still in progress. Write: Clear the flag. 0 SET Read: The transmit FIFO and shift register are empty and the data transfer has ended. Write: Force an underrun interrupt. 1 SREI Shift Register Empty Interrupt Flag. 7 1 read-only NOT_SET There is data still present in the transmit FIFO or shift register. 0 SET All data has been transferred out of the shift register and there is no data waiting in the transmit FIFO. 1 RFILI Illegal Receive FIFO Access Interrupt Flag. 8 1 NOT_SET Read: An illegal write or read of the receive FIFO has not occurred. Write: Clear the flag. 0 SET Read: An illegal write or read of the receive FIFO occurred. Write: Force an illegal receive access interrupt. 1 TFILI Illegal Transmit FIFO Access Interrupt Flag. 9 1 NOT_SET Read: An illegal write or read of the transmit FIFO has not occurred. Write: Clear the flag. 0 SET Read: An illegal write or read of the transmit FIFO occurred. Write: Force an illegal transmit access interrupt. 1 NSSSTS NSS Instantaneous Pin Status. 14 1 read-only LOW NSS is currently a logic low. 0 HIGH NSS is currently a logic high. 1 BUSYF SPI Busy. 15 1 read-only NOT_SET The SPI is not busy and a transfer is not in progress. 0 SET The SPI is currently busy and a transfer is in progress. 1 RFCNT Receive FIFO Counter. 16 4 read-only TFCNT Transmit FIFO Counter. 20 4 read-only DBGMD SPI Debug Mode. 24 1 RUN The SPI module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the SPI module to halt. 1 CONFIG Module Configuration 0x20 0x00000000 0xFFFFFFFF RFRQIEN Receive FIFO Read Request Interrupt Enable. 0 1 DISABLED Disable the receive FIFO request interrupt. 0 ENABLED Enable the receive FIFO request interrupt. 1 RFORIEN Receive FIFO Overrun Interrupt Enable. 1 1 DISABLED Disable the receive FIFO overrun interrupt. 0 ENABLED Enable the receive FIFO overrun interrupt. 1 TFRQIEN Transmit FIFO Write Request Interrupt Enable. 2 1 DISABLED Disable the transmit FIFO data request interrupt. 0 ENABLED Enable the transmit FIFO data request interrupt. 1 TFORIEN Transmit FIFO Overrun Interrupt Enable. 3 1 DISABLED Disable the transmit FIFO overrun interrupt. 0 ENABLED Enable the transmit FIFO overrun interrupt. 1 SLVSELIEN Slave Selected Interrupt Enable. 4 1 DISABLED Disable the slave select interrupt. 0 ENABLED Enable the slave select interrupt. 1 MDFIEN Mode Fault Interrupt Enable. 5 1 DISABLED Disable the mode fault interrupt. 0 ENABLED Enable the mode fault interrupt. 1 URIEN Underrun Interrupt Enable. 6 1 DISABLED Disable the underrun interrupt. 0 ENABLED Enable the underrun interrupt. 1 SREIEN Shift Register Empty Interrupt Enable. 7 1 DISABLED Disable the shift register empty interrupt. 0 ENABLED Enable the shift register empty interrupt. 1 SPIEN SPI Enable. 8 1 DISABLED Disable the SPI. 0 ENABLED Enable the SPI. 1 MSTEN Master Mode Enable. 9 1 DISABLED Operate in slave mode. 0 ENABLED Operate in master mode. 1 CLKPOL SPI Clock Polarity. 10 1 LOW The SCK line is low in the idle state. 0 HIGH The SCK line is high in the idle state. 1 CLKPHA SPI Clock Phase. 11 1 CENTER The first edge of SCK is the sample edge (center of data bit). 0 EDGE The first edge of SCK is the shift edge (edge of data bit). 1 NSSPOL Slave Select Polarity Select. 12 1 LOW NSS is active low. 0 HIGH NSS is active high. 1 DDIRSEL Data Direction Select. 13 1 MSB_FIRST Data will be shifted MSB first. 0 LSB_FIRST Data will be shifted LSB first. 1 NSSMD Slave Select Mode. 14 2 3_WIRE_MASTER_SLAVE 3-wire Slave or 3-wire Master. 0 4_WIRE_SLAVE 4-wire slave (NSS input). This setting can also be used for multi-master configurations. 1 4_WIRE_MASTER_NSS_LOW 4-wire master with NSS low (NSS output). 2 4_WIRE_MASTER_NSS_HIGH 4-wire master with NSS high (NSS output). 3 RFTH Receive FIFO Threshold. 16 2 ONE A DMA / RFRQ request asserts when >= 1 FIFO slot is filled. 0 TWO A DMA / RFRQ request asserts when >= 2 FIFO slots are filled. 1 FOUR A DMA / RFRQ request asserts when >= 4 FIFO slots are filled. 2 FULL A DMA / RFRQ request asserts when all FIFO slots are filled. 3 TFTH Transmit FIFO Threshold. 18 2 ONE A DMA / TFRQ request asserts when >= 1 FIFO slot is empty. 0 TWO A DMA / TFRQ request asserts when >= 2 FIFO slots are empty. 1 FOUR A DMA / TFRQ request asserts when >= 4 FIFO slots are empty. 2 EMPTY A DMA / TFRQ request asserts when all FIFO slots are empty. 3 DSIZE Data Size. 20 4 DMAEN DMA Enable. 24 1 DISABLED Disable DMA requests. 0 ENABLED Enable DMA requests according to the TFRQI and RFRQI flags. 1 RFIFOFL Receive FIFO Flush. 29 1 SET Flush the receive FIFO. 1 TFIFOFL Transmit FIFO Flush. 30 1 SET Flush the transmit FIFO. 1 RESET Module Soft Reset. 31 1 INACTIVE SPI module is not in soft reset. 0 ACTIVE SPI module is in soft reset and some of the module bits cannot be accessed until this bit is cleared to 0 by hardware. 1 CLKRATE Module Clock Rate Control 0x30 0x00000000 0xFFFFFFFF CLKDIV Clock Divider. 0 16 FSTATUS FIFO Status 0x40 0x00000000 0xFFFFFFFF RFRPTR Receive FIFO Read Pointer. 0 4 read-only RFWPTR Receive FIFO Write Pointer. 4 4 read-only TFRPTR Transmit FIFO Read Pointer. 8 4 read-only TFWPTR Transmit FIFO Write Pointer. 12 4 read-only CONFIGMD Mode Configuration 0x50 0x00000000 0xFFFFFFFF OPMD Operation Mode. 0 2 NORMAL Full-duplex (normal) mode. 0 RECEIVE Receive-only mode. 1 TRANSMIT Transmit only mode. 2 FLOWCONTROL Flow control mode. 3 AUTONSS Auto NSS Mode. 2 1 DISABLED 0 ENABLED 1 CTSEN CTS Flow Control Enable. 3 1 DISABLED 0 ENABLED 1 FLOWMD Flow Control Mode. 4 1 DISABLED Store CTS byte (see chapter text for details). 0 ENABLED Disregard CTS byte. 1 ABORT Software Abort. 5 1 DISABLED 0 ENABLED 1 TXONREQ Transmit On Request. 6 1 DISABLED 0 ENABLED 1 NSSCNT NSS Data Count. 8 8 NSSDELAY NSS Delay. 16 8 TFRCNT Transfer Count. 24 3 AUTO Automatic. The request type determines the number of bytes to write/read. 0 TRANSFER1 A single byte is written/read per request. 1 TRANSFER2 Up to two bytes can be written/read per request. 2 TRANSFER3 Up to three bytes can be written/read per request. 3 TRANSFER4 Up to four bytes can be written/read per request. 4 SPI_1 B None SPI 0x40005000 0x0 0xffc registers SPI1_IRQn 27 DATA Input/Output Data 0x0 0x00000000 0xFFFFFFFF modifyExternal DATA Input/Output Data. 0 32 CONTROL Module Control 0x10 0x00004084 0xFFFFFFFF RFRQI Receive FIFO Read Request Interrupt Flag. 0 1 read-only NOT_SET The RX FIFO has fewer bytes than the level defined by RFTH. 0 SET The RX FIFO has equal or more bytes than the level defined by RFTH. 1 RFORI Receive FIFO Overrun Interrupt Flag. 1 1 NOT_SET Read: A receive FIFO overrun has not occurred. Write: Clear the flag. 0 SET Read: A receive FIFO overrun occurred. Write: Force a receive overrun interrupt. 1 TFRQI Transmit FIFO Write Request Interrupt Flag. 2 1 read-only NOT_SET The TX FIFO has fewer empty slots than the level defined by TFTH. 0 SET The TX FIFO has at least as many empty slots as the level defined by TFTH. 1 TFORI Transmit FIFO Overrun Interrupt Flag. 3 1 NOT_SET Read: A transmit FIFO overrun has not occurred. Write: Clear the flag. 0 SET Read: A transmit FIFO overrun occurred. Write: Force a transmit overrun interrupt. 1 SLVSELI Slave Selected Interrupt Flag. 4 1 read-only NOT_SET The slave select signal (NSS) is not active. 0 SET The slave select signal (NSS) is active. 1 MDFI Mode Fault Interrupt Flag. 5 1 NOT_SET Read: A master mode collision is not detected. Write: Clear the flag. 0 SET Read: A master mode collision occurred. Write: Force a mode fault interrupt. 1 URI Underrun Interrupt Flag. 6 1 NOT_SET Read: A data transfer is still in progress. Write: Clear the flag. 0 SET Read: The transmit FIFO and shift register are empty and the data transfer has ended. Write: Force an underrun interrupt. 1 SREI Shift Register Empty Interrupt Flag. 7 1 read-only NOT_SET There is data still present in the transmit FIFO or shift register. 0 SET All data has been transferred out of the shift register and there is no data waiting in the transmit FIFO. 1 RFILI Illegal Receive FIFO Access Interrupt Flag. 8 1 NOT_SET Read: An illegal write or read of the receive FIFO has not occurred. Write: Clear the flag. 0 SET Read: An illegal write or read of the receive FIFO occurred. Write: Force an illegal receive access interrupt. 1 TFILI Illegal Transmit FIFO Access Interrupt Flag. 9 1 NOT_SET Read: An illegal write or read of the transmit FIFO has not occurred. Write: Clear the flag. 0 SET Read: An illegal write or read of the transmit FIFO occurred. Write: Force an illegal transmit access interrupt. 1 NSSSTS NSS Instantaneous Pin Status. 14 1 read-only LOW NSS is currently a logic low. 0 HIGH NSS is currently a logic high. 1 BUSYF SPI Busy. 15 1 read-only NOT_SET The SPI is not busy and a transfer is not in progress. 0 SET The SPI is currently busy and a transfer is in progress. 1 RFCNT Receive FIFO Counter. 16 4 read-only TFCNT Transmit FIFO Counter. 20 4 read-only DBGMD SPI Debug Mode. 24 1 RUN The SPI module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the SPI module to halt. 1 CONFIG Module Configuration 0x20 0x00000000 0xFFFFFFFF RFRQIEN Receive FIFO Read Request Interrupt Enable. 0 1 DISABLED Disable the receive FIFO request interrupt. 0 ENABLED Enable the receive FIFO request interrupt. 1 RFORIEN Receive FIFO Overrun Interrupt Enable. 1 1 DISABLED Disable the receive FIFO overrun interrupt. 0 ENABLED Enable the receive FIFO overrun interrupt. 1 TFRQIEN Transmit FIFO Write Request Interrupt Enable. 2 1 DISABLED Disable the transmit FIFO data request interrupt. 0 ENABLED Enable the transmit FIFO data request interrupt. 1 TFORIEN Transmit FIFO Overrun Interrupt Enable. 3 1 DISABLED Disable the transmit FIFO overrun interrupt. 0 ENABLED Enable the transmit FIFO overrun interrupt. 1 SLVSELIEN Slave Selected Interrupt Enable. 4 1 DISABLED Disable the slave select interrupt. 0 ENABLED Enable the slave select interrupt. 1 MDFIEN Mode Fault Interrupt Enable. 5 1 DISABLED Disable the mode fault interrupt. 0 ENABLED Enable the mode fault interrupt. 1 URIEN Underrun Interrupt Enable. 6 1 DISABLED Disable the underrun interrupt. 0 ENABLED Enable the underrun interrupt. 1 SREIEN Shift Register Empty Interrupt Enable. 7 1 DISABLED Disable the shift register empty interrupt. 0 ENABLED Enable the shift register empty interrupt. 1 SPIEN SPI Enable. 8 1 DISABLED Disable the SPI. 0 ENABLED Enable the SPI. 1 MSTEN Master Mode Enable. 9 1 DISABLED Operate in slave mode. 0 ENABLED Operate in master mode. 1 CLKPOL SPI Clock Polarity. 10 1 LOW The SCK line is low in the idle state. 0 HIGH The SCK line is high in the idle state. 1 CLKPHA SPI Clock Phase. 11 1 CENTER The first edge of SCK is the sample edge (center of data bit). 0 EDGE The first edge of SCK is the shift edge (edge of data bit). 1 NSSPOL Slave Select Polarity Select. 12 1 LOW NSS is active low. 0 HIGH NSS is active high. 1 DDIRSEL Data Direction Select. 13 1 MSB_FIRST Data will be shifted MSB first. 0 LSB_FIRST Data will be shifted LSB first. 1 NSSMD Slave Select Mode. 14 2 3_WIRE_MASTER_SLAVE 3-wire Slave or 3-wire Master. 0 4_WIRE_SLAVE 4-wire slave (NSS input). This setting can also be used for multi-master configurations. 1 4_WIRE_MASTER_NSS_LOW 4-wire master with NSS low (NSS output). 2 4_WIRE_MASTER_NSS_HIGH 4-wire master with NSS high (NSS output). 3 RFTH Receive FIFO Threshold. 16 2 ONE A DMA / RFRQ request asserts when >= 1 FIFO slot is filled. 0 TWO A DMA / RFRQ request asserts when >= 2 FIFO slots are filled. 1 FOUR A DMA / RFRQ request asserts when >= 4 FIFO slots are filled. 2 FULL A DMA / RFRQ request asserts when all FIFO slots are filled. 3 TFTH Transmit FIFO Threshold. 18 2 ONE A DMA / TFRQ request asserts when >= 1 FIFO slot is empty. 0 TWO A DMA / TFRQ request asserts when >= 2 FIFO slots are empty. 1 FOUR A DMA / TFRQ request asserts when >= 4 FIFO slots are empty. 2 EMPTY A DMA / TFRQ request asserts when all FIFO slots are empty. 3 DSIZE Data Size. 20 4 DMAEN DMA Enable. 24 1 DISABLED Disable DMA requests. 0 ENABLED Enable DMA requests according to the TFRQI and RFRQI flags. 1 RFIFOFL Receive FIFO Flush. 29 1 SET Flush the receive FIFO. 1 TFIFOFL Transmit FIFO Flush. 30 1 SET Flush the transmit FIFO. 1 RESET Module Soft Reset. 31 1 INACTIVE SPI module is not in soft reset. 0 ACTIVE SPI module is in soft reset and some of the module bits cannot be accessed until this bit is cleared to 0 by hardware. 1 CLKRATE Module Clock Rate Control 0x30 0x00000000 0xFFFFFFFF CLKDIV Clock Divider. 0 16 FSTATUS FIFO Status 0x40 0x00000000 0xFFFFFFFF RFRPTR Receive FIFO Read Pointer. 0 4 read-only RFWPTR Receive FIFO Write Pointer. 4 4 read-only TFRPTR Transmit FIFO Read Pointer. 8 4 read-only TFWPTR Transmit FIFO Write Pointer. 12 4 read-only CONFIGMD Mode Configuration 0x50 0x00000000 0xFFFFFFFF OPMD Operation Mode. 0 2 NORMAL Full-duplex (normal) mode. 0 RECEIVE Receive-only mode. 1 TRANSMIT Transmit only mode. 2 FLOWCONTROL Flow control mode. 3 AUTONSS Auto NSS Mode. 2 1 DISABLED 0 ENABLED 1 CTSEN CTS Flow Control Enable. 3 1 DISABLED 0 ENABLED 1 FLOWMD Flow Control Mode. 4 1 DISABLED Store CTS byte (see chapter text for details). 0 ENABLED Disregard CTS byte. 1 ABORT Software Abort. 5 1 DISABLED 0 ENABLED 1 TXONREQ Transmit On Request. 6 1 DISABLED 0 ENABLED 1 NSSCNT NSS Data Count. 8 8 NSSDELAY NSS Delay. 16 8 TFRCNT Transfer Count. 24 3 AUTO Automatic. The request type determines the number of bytes to write/read. 0 TRANSFER1 A single byte is written/read per request. 1 TRANSFER2 Up to two bytes can be written/read per request. 2 TRANSFER3 Up to three bytes can be written/read per request. 3 TRANSFER4 Up to four bytes can be written/read per request. 4 SCONFIG_0 A None SCONFIG_0 0x400490b0 0x0 0xffc registers CONFIG System Configuration 0x0 0x00000000 0xFFFFFFFF FDMAEN Faster DMA Mode Enable. 0 1 DISABLED Disable the faster DMA mode. The DMA module and channels will behave like a standard uDMA. 0 ENABLED Enable the faster DMA mode. 1 PM8DBGEN Power Mode 8 Debug Enable. 1 1 DISABLED Disable debugging through Power Mode 8. 0 ENABLED Enable debugging through Power Mode 8. Power measurements cannot be made with debugging enabled. 1 TIMER_0 A None Timer 0x40014000 0x0 0xffc registers TIMER0L_IRQn 16 TIMER0H_IRQn 17 CONFIG High and Low Timer Configuration 0x0 0x00000000 0xFFFFFFFF LCLK Low Clock Source. 0 2 APB Select the APB clock as the timer source. 0 EXTOSCN Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock. 1 TIMER_CLKDIV Select the dedicated 8-bit prescaler as the timer source. 2 CT_FALLING_EDGE Select falling edges of the CT signal as the timer clock source. 3 LMSTREN Low Run Master Enable. 4 1 DISABLED MSTRUN does not need to be set for the low timer to run. 0 ENABLED MSTRUN must be set for the low timer to run. 1 SPLITEN Split Mode Enable. 5 1 DISABLED The timer operates as a single 32-bit timer controlled by the high timer fields. 0 ENABLED The timer operates as two independent 16-bit timers. 1 LEXIEN Low Timer Extra Interrupt Enable. 6 1 DISABLED The state of the LEXI flag does not affect the low timer interrupt. 0 ENABLED A low timer interrupt request is generated if LEXI is set to 1. 1 LOVFIEN Low Timer Overflow Interrupt Enable. 7 1 DISABLED The state of LOVFI does not affect the low timer interrupt. 0 ENABLED A low timer interrupt request is generated if LOVFI = 1. 1 LMD Low Timer Mode. 8 3 AUTO_RELOAD The low timer is in Auto-Reload Mode. 0 UP_DOWN The low timer is in Up/Down Count Mode. 1 FALL_CAPTURE The low timer is in Falling Edge Capture Mode. 2 RISE_CAPTURE The low timer is in Rising Edge Capture Mode. 3 LOW_CAPTURE The low timer is in Low Time Capture Mode. 4 HIGH_CAPTURE The low timer is in High Time Capture Mode. 5 DC_CAPTURE The low timer is in Duty Cycle Capture Mode. 6 ONESHOT The low timer is in Oneshot Mode. 7 LSTATE Low Multi Purpose State Indicator. 12 1 NOT_SET 0 SET 1 LRUN Run Control Low. 13 1 STOP Stop the low timer if split mode is enabled (SPLITEN = 1). 0 START The low timer runs if split mode is enabled (SPLITEN = 1) and (LMSTREN = 0 or MSTRUN = 1 in Timer 0). 1 LEXI Low Timer Extra Interrupt Flag. 14 1 NOT_SET Read: A low timer extra interrupt is not pending. Write: Clear the interrupt. 0 SET Read: Indicates the low 16-bit timer has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by hardware in all modes except Auto-Reload and Toggle. This flag is not set by hardware when split mode is disabled (SPLITEN = 0). Write: Force a low timer extra interrupt. 1 LOVFI Low Timer Overflow Interrupt. 15 1 NOT_SET Read: A low timer overflow interrupt is not pending. Write: Clear the interrupt. 0 SET Read: The low 16-bit timer has wrapped or reloaded after reaching all 1's. This bit is set by the module regardless of the state of SPLITEN and can be set in all modes. Write: Force a low timer overflow interrupt. 1 HCLK High Clock Source. 16 2 APB Select the APB clock as the timer source. 0 EXTOSCN Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock. 1 TIMER_CLKDIV Select the dedicated 8-bit prescaler as the timer source. 2 CT_FALLING_EDGE Select falling edges of the CT signal as the timer clock source. 3 MSTRUN Master Run Control. 19 1 STOP Disable the master run control for all timers. 0 START Enable the master run control for all timers. 1 HMSTREN High Master Enable. 20 1 DISABLED MSTRUN does not need to be set for the timer to run. 0 ENABLED MSTRUN must be set for the timer to run. 1 DBGMD Timer Debug Mode. 21 1 RUN The timer will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the Timer to halt. 1 HEXIEN High Timer Extra Interrupt Enable. 22 1 DISABLED The state of the HEXI flag does not affect the high timer interrupt. 0 ENABLED A high timer interrupt request is generated if HEXI is set to 1. 1 HOVFIEN High Timer Overflow Interrupt Enable. 23 1 DISABLED The state of HOVFI does not affect the high timer interrupt. 0 ENABLED A high timer interrupt request is generated if HOVFI is set to 1. 1 HMD High Timer Mode. 24 4 AUTO_RELOAD The high 16-bit timer or entire 32-bit timer is in Auto-Reload Mode. 0 UP_DOWN The high 16-bit timer or entire 32-bit timer is in Up/Down Count Mode. 1 FALL_CAPTURE The high 16-bit timer or entire 32-bit timer is in Falling Edge Capture Mode. 2 RISE_CAPTURE The high 16-bit timer or entire 32-bit timer is in Rising Edge Capture Mode. 3 LOW_CAPTURE The high 16-bit timer or entire 32-bit timer is in Low Time Capture Mode. 4 HIGH_CAPTURE The high 16-bit timer or entire 32-bit timer is in High Time Capture Mode. 5 DC_CAPTURE The high 16-bit timer or entire 32-bit timer is in Duty Cycle Capture Mode. 6 ONESHOT The high 16-bit timer or entire 32-bit timer is in Oneshot Mode. 7 TOGGLE The high 16-bit timer or entire 32-bit timer is in Square Wave Output Mode. 8 PWM The high 16-bit timer or entire 32-bit timer is in PWM Mode. 9 HSTATE High Multi Purpose State Indicator. 28 1 NOT_SET 0 SET 1 HRUN High Run Control. 29 1 STOP Stop the high timer or entire 32-bit timer. 0 START The high timer runs if HMSTREN = 0 or MSTRUN (in Timer 0) = 1. The full 32-bit timer runs if split mode is disabled and (HMSTREN = 0 or MSTRUN = 1). 1 HEXI High Timer Extra Interrupt Flag. 30 1 NOT_SET Read: A high timer extra interrupt is not pending. Write: Clear the interrupt. 0 SET Read: Indicates the high 16-bit timer (or 32-bit timer if SPLITEN = 0) has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by the timer module in all modes except Auto-Reload and Toggle. Write: Force a high timer extra interrupt. 1 HOVFI High Timer Overflow Interrupt Flag. 31 1 NOT_SET Read: A high timer overflow interrupt is not pending. Write: Clear the interrupt. 0 SET Read: If split mode is enabled (SPLITEN = 1), this value indicates the high 16-bit timer has wrapped or reloaded after reaching all 1's. If split mode is disabled (SPLITEN = 0), this value indicates the 32-bit timer has wrapped or reloaded after reaching all 1's. The timer module can set this bit in all modes. Write: Force a high timer overflow interrupt. 1 CLKDIV Module Clock Divider Control 0x10 0x00000000 0xFFFFFFFF CLKDIVRL Clock Divider Reload Value. 0 8 CLKDIVCT Clock Divider Counter. 16 8 COUNT Timer Value 0x20 0x00000000 0xFFFFFFFF LCOUNT Low Timer Count. 0 16 HCOUNT High Timer Count. 16 16 CAPTURE Timer Capture/Reload Value 0x30 0x00000000 0xFFFFFFFF LCCR Low Timer Capture/Reload. 0 16 HCCR High Timer Capture/Reload. 16 16 TIMER_1 A None Timer 0x40015000 0x0 0xffc registers TIMER1L_IRQn 18 TIMER1H_IRQn 19 CONFIG High and Low Timer Configuration 0x0 0x00000000 0xFFFFFFFF LCLK Low Clock Source. 0 2 APB Select the APB clock as the timer source. 0 EXTOSCN Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock. 1 TIMER_CLKDIV Select the dedicated 8-bit prescaler as the timer source. 2 CT_FALLING_EDGE Select falling edges of the CT signal as the timer clock source. 3 LMSTREN Low Run Master Enable. 4 1 DISABLED MSTRUN does not need to be set for the low timer to run. 0 ENABLED MSTRUN must be set for the low timer to run. 1 SPLITEN Split Mode Enable. 5 1 DISABLED The timer operates as a single 32-bit timer controlled by the high timer fields. 0 ENABLED The timer operates as two independent 16-bit timers. 1 LEXIEN Low Timer Extra Interrupt Enable. 6 1 DISABLED The state of the LEXI flag does not affect the low timer interrupt. 0 ENABLED A low timer interrupt request is generated if LEXI is set to 1. 1 LOVFIEN Low Timer Overflow Interrupt Enable. 7 1 DISABLED The state of LOVFI does not affect the low timer interrupt. 0 ENABLED A low timer interrupt request is generated if LOVFI = 1. 1 LMD Low Timer Mode. 8 3 AUTO_RELOAD The low timer is in Auto-Reload Mode. 0 UP_DOWN The low timer is in Up/Down Count Mode. 1 FALL_CAPTURE The low timer is in Falling Edge Capture Mode. 2 RISE_CAPTURE The low timer is in Rising Edge Capture Mode. 3 LOW_CAPTURE The low timer is in Low Time Capture Mode. 4 HIGH_CAPTURE The low timer is in High Time Capture Mode. 5 DC_CAPTURE The low timer is in Duty Cycle Capture Mode. 6 ONESHOT The low timer is in Oneshot Mode. 7 LSTATE Low Multi Purpose State Indicator. 12 1 NOT_SET 0 SET 1 LRUN Run Control Low. 13 1 STOP Stop the low timer if split mode is enabled (SPLITEN = 1). 0 START The low timer runs if split mode is enabled (SPLITEN = 1) and (LMSTREN = 0 or MSTRUN = 1 in Timer 0). 1 LEXI Low Timer Extra Interrupt Flag. 14 1 NOT_SET Read: A low timer extra interrupt is not pending. Write: Clear the interrupt. 0 SET Read: Indicates the low 16-bit timer has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by hardware in all modes except Auto-Reload and Toggle. This flag is not set by hardware when split mode is disabled (SPLITEN = 0). Write: Force a low timer extra interrupt. 1 LOVFI Low Timer Overflow Interrupt. 15 1 NOT_SET Read: A low timer overflow interrupt is not pending. Write: Clear the interrupt. 0 SET Read: The low 16-bit timer has wrapped or reloaded after reaching all 1's. This bit is set by the module regardless of the state of SPLITEN and can be set in all modes. Write: Force a low timer overflow interrupt. 1 HCLK High Clock Source. 16 2 APB Select the APB clock as the timer source. 0 EXTOSCN Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock. 1 TIMER_CLKDIV Select the dedicated 8-bit prescaler as the timer source. 2 CT_FALLING_EDGE Select falling edges of the CT signal as the timer clock source. 3 MSTRUN Master Run Control. 19 1 STOP Disable the master run control for all timers. 0 START Enable the master run control for all timers. 1 HMSTREN High Master Enable. 20 1 DISABLED MSTRUN does not need to be set for the timer to run. 0 ENABLED MSTRUN must be set for the timer to run. 1 DBGMD Timer Debug Mode. 21 1 RUN The timer will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the Timer to halt. 1 HEXIEN High Timer Extra Interrupt Enable. 22 1 DISABLED The state of the HEXI flag does not affect the high timer interrupt. 0 ENABLED A high timer interrupt request is generated if HEXI is set to 1. 1 HOVFIEN High Timer Overflow Interrupt Enable. 23 1 DISABLED The state of HOVFI does not affect the high timer interrupt. 0 ENABLED A high timer interrupt request is generated if HOVFI is set to 1. 1 HMD High Timer Mode. 24 4 AUTO_RELOAD The high 16-bit timer or entire 32-bit timer is in Auto-Reload Mode. 0 UP_DOWN The high 16-bit timer or entire 32-bit timer is in Up/Down Count Mode. 1 FALL_CAPTURE The high 16-bit timer or entire 32-bit timer is in Falling Edge Capture Mode. 2 RISE_CAPTURE The high 16-bit timer or entire 32-bit timer is in Rising Edge Capture Mode. 3 LOW_CAPTURE The high 16-bit timer or entire 32-bit timer is in Low Time Capture Mode. 4 HIGH_CAPTURE The high 16-bit timer or entire 32-bit timer is in High Time Capture Mode. 5 DC_CAPTURE The high 16-bit timer or entire 32-bit timer is in Duty Cycle Capture Mode. 6 ONESHOT The high 16-bit timer or entire 32-bit timer is in Oneshot Mode. 7 TOGGLE The high 16-bit timer or entire 32-bit timer is in Square Wave Output Mode. 8 PWM The high 16-bit timer or entire 32-bit timer is in PWM Mode. 9 HSTATE High Multi Purpose State Indicator. 28 1 NOT_SET 0 SET 1 HRUN High Run Control. 29 1 STOP Stop the high timer or entire 32-bit timer. 0 START The high timer runs if HMSTREN = 0 or MSTRUN (in Timer 0) = 1. The full 32-bit timer runs if split mode is disabled and (HMSTREN = 0 or MSTRUN = 1). 1 HEXI High Timer Extra Interrupt Flag. 30 1 NOT_SET Read: A high timer extra interrupt is not pending. Write: Clear the interrupt. 0 SET Read: Indicates the high 16-bit timer (or 32-bit timer if SPLITEN = 0) has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by the timer module in all modes except Auto-Reload and Toggle. Write: Force a high timer extra interrupt. 1 HOVFI High Timer Overflow Interrupt Flag. 31 1 NOT_SET Read: A high timer overflow interrupt is not pending. Write: Clear the interrupt. 0 SET Read: If split mode is enabled (SPLITEN = 1), this value indicates the high 16-bit timer has wrapped or reloaded after reaching all 1's. If split mode is disabled (SPLITEN = 0), this value indicates the 32-bit timer has wrapped or reloaded after reaching all 1's. The timer module can set this bit in all modes. Write: Force a high timer overflow interrupt. 1 CLKDIV Module Clock Divider Control 0x10 0x00000000 0xFFFFFFFF CLKDIVRL Clock Divider Reload Value. 0 8 CLKDIVCT Clock Divider Counter. 16 8 COUNT Timer Value 0x20 0x00000000 0xFFFFFFFF LCOUNT Low Timer Count. 0 16 HCOUNT High Timer Count. 16 16 CAPTURE Timer Capture/Reload Value 0x30 0x00000000 0xFFFFFFFF LCCR Low Timer Capture/Reload. 0 16 HCCR High Timer Capture/Reload. 16 16 TIMER_2 A None Timer 0x40016000 0x0 0xffc registers TIMER2L_IRQn 20 TIMER2H_IRQn 21 CONFIG High and Low Timer Configuration 0x0 0x00000000 0xFFFFFFFF LCLK Low Clock Source. 0 2 APB Select the APB clock as the timer source. 0 EXTOSCN Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock. 1 TIMER_CLKDIV Select the dedicated 8-bit prescaler as the timer source. 2 CT_FALLING_EDGE Select falling edges of the CT signal as the timer clock source. 3 LMSTREN Low Run Master Enable. 4 1 DISABLED MSTRUN does not need to be set for the low timer to run. 0 ENABLED MSTRUN must be set for the low timer to run. 1 SPLITEN Split Mode Enable. 5 1 DISABLED The timer operates as a single 32-bit timer controlled by the high timer fields. 0 ENABLED The timer operates as two independent 16-bit timers. 1 LEXIEN Low Timer Extra Interrupt Enable. 6 1 DISABLED The state of the LEXI flag does not affect the low timer interrupt. 0 ENABLED A low timer interrupt request is generated if LEXI is set to 1. 1 LOVFIEN Low Timer Overflow Interrupt Enable. 7 1 DISABLED The state of LOVFI does not affect the low timer interrupt. 0 ENABLED A low timer interrupt request is generated if LOVFI = 1. 1 LMD Low Timer Mode. 8 3 AUTO_RELOAD The low timer is in Auto-Reload Mode. 0 UP_DOWN The low timer is in Up/Down Count Mode. 1 FALL_CAPTURE The low timer is in Falling Edge Capture Mode. 2 RISE_CAPTURE The low timer is in Rising Edge Capture Mode. 3 LOW_CAPTURE The low timer is in Low Time Capture Mode. 4 HIGH_CAPTURE The low timer is in High Time Capture Mode. 5 DC_CAPTURE The low timer is in Duty Cycle Capture Mode. 6 ONESHOT The low timer is in Oneshot Mode. 7 LSTATE Low Multi Purpose State Indicator. 12 1 NOT_SET 0 SET 1 LRUN Run Control Low. 13 1 STOP Stop the low timer if split mode is enabled (SPLITEN = 1). 0 START The low timer runs if split mode is enabled (SPLITEN = 1) and (LMSTREN = 0 or MSTRUN = 1 in Timer 0). 1 LEXI Low Timer Extra Interrupt Flag. 14 1 NOT_SET Read: A low timer extra interrupt is not pending. Write: Clear the interrupt. 0 SET Read: Indicates the low 16-bit timer has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by hardware in all modes except Auto-Reload and Toggle. This flag is not set by hardware when split mode is disabled (SPLITEN = 0). Write: Force a low timer extra interrupt. 1 LOVFI Low Timer Overflow Interrupt. 15 1 NOT_SET Read: A low timer overflow interrupt is not pending. Write: Clear the interrupt. 0 SET Read: The low 16-bit timer has wrapped or reloaded after reaching all 1's. This bit is set by the module regardless of the state of SPLITEN and can be set in all modes. Write: Force a low timer overflow interrupt. 1 HCLK High Clock Source. 16 2 APB Select the APB clock as the timer source. 0 EXTOSCN Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock. 1 TIMER_CLKDIV Select the dedicated 8-bit prescaler as the timer source. 2 CT_FALLING_EDGE Select falling edges of the CT signal as the timer clock source. 3 MSTRUN Master Run Control. 19 1 STOP Disable the master run control for all timers. 0 START Enable the master run control for all timers. 1 HMSTREN High Master Enable. 20 1 DISABLED MSTRUN does not need to be set for the timer to run. 0 ENABLED MSTRUN must be set for the timer to run. 1 DBGMD Timer Debug Mode. 21 1 RUN The timer will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the Timer to halt. 1 HEXIEN High Timer Extra Interrupt Enable. 22 1 DISABLED The state of the HEXI flag does not affect the high timer interrupt. 0 ENABLED A high timer interrupt request is generated if HEXI is set to 1. 1 HOVFIEN High Timer Overflow Interrupt Enable. 23 1 DISABLED The state of HOVFI does not affect the high timer interrupt. 0 ENABLED A high timer interrupt request is generated if HOVFI is set to 1. 1 HMD High Timer Mode. 24 4 AUTO_RELOAD The high 16-bit timer or entire 32-bit timer is in Auto-Reload Mode. 0 UP_DOWN The high 16-bit timer or entire 32-bit timer is in Up/Down Count Mode. 1 FALL_CAPTURE The high 16-bit timer or entire 32-bit timer is in Falling Edge Capture Mode. 2 RISE_CAPTURE The high 16-bit timer or entire 32-bit timer is in Rising Edge Capture Mode. 3 LOW_CAPTURE The high 16-bit timer or entire 32-bit timer is in Low Time Capture Mode. 4 HIGH_CAPTURE The high 16-bit timer or entire 32-bit timer is in High Time Capture Mode. 5 DC_CAPTURE The high 16-bit timer or entire 32-bit timer is in Duty Cycle Capture Mode. 6 ONESHOT The high 16-bit timer or entire 32-bit timer is in Oneshot Mode. 7 TOGGLE The high 16-bit timer or entire 32-bit timer is in Square Wave Output Mode. 8 PWM The high 16-bit timer or entire 32-bit timer is in PWM Mode. 9 HSTATE High Multi Purpose State Indicator. 28 1 NOT_SET 0 SET 1 HRUN High Run Control. 29 1 STOP Stop the high timer or entire 32-bit timer. 0 START The high timer runs if HMSTREN = 0 or MSTRUN (in Timer 0) = 1. The full 32-bit timer runs if split mode is disabled and (HMSTREN = 0 or MSTRUN = 1). 1 HEXI High Timer Extra Interrupt Flag. 30 1 NOT_SET Read: A high timer extra interrupt is not pending. Write: Clear the interrupt. 0 SET Read: Indicates the high 16-bit timer (or 32-bit timer if SPLITEN = 0) has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by the timer module in all modes except Auto-Reload and Toggle. Write: Force a high timer extra interrupt. 1 HOVFI High Timer Overflow Interrupt Flag. 31 1 NOT_SET Read: A high timer overflow interrupt is not pending. Write: Clear the interrupt. 0 SET Read: If split mode is enabled (SPLITEN = 1), this value indicates the high 16-bit timer has wrapped or reloaded after reaching all 1's. If split mode is disabled (SPLITEN = 0), this value indicates the 32-bit timer has wrapped or reloaded after reaching all 1's. The timer module can set this bit in all modes. Write: Force a high timer overflow interrupt. 1 CLKDIV Module Clock Divider Control 0x10 0x00000000 0xFFFFFFFF CLKDIVRL Clock Divider Reload Value. 0 8 CLKDIVCT Clock Divider Counter. 16 8 COUNT Timer Value 0x20 0x00000000 0xFFFFFFFF LCOUNT Low Timer Count. 0 16 HCOUNT High Timer Count. 16 16 CAPTURE Timer Capture/Reload Value 0x30 0x00000000 0xFFFFFFFF LCCR Low Timer Capture/Reload. 0 16 HCCR High Timer Capture/Reload. 16 16 UART_0 B None UART_0 0x40001000 0x0 0xffc registers UART0_IRQn 25 CONFIG Module Configuration 0x0 0x030D030D 0xFFFFFFFF RSTRTEN Receiver Start Enable. 0 1 DISABLED Do not expect a start bit during receptions. 0 ENABLED Expect a start bit during receptions. 1 RPAREN Receiver Parity Enable. 1 1 DISABLED Do not expect a parity bit during receptions. 0 ENABLED Expect a parity bit during receptions. 1 RSTPEN Receiver Stop Enable. 2 1 DISABLED Do not expect stop bits during receptions. 0 ENABLED Expect stop bits during receptions. 1 RSTPMD Receiver Stop Mode. 3 2 0P5_STOP 0.5 stop bit. 0 1_STOP 1 stop bit. 1 1P5_STOP 1.5 stop bits. 2 2_STOP 2 stop bits. 3 RPARMD Receiver Parity Mode. 5 2 ODD Odd Parity. 0 EVEN Even Parity. 1 MARK Set (Parity = 1). 2 SPACE Clear (Parity = 0). 3 RDATLN Receiver Data Length. 8 3 5_BITS 5 bits. 0 6_BITS 6 bits. 1 7_BITS 7 bits. 2 8_BITS 8 bits. 3 9_BITS_STORED 9 bits. The 9th bit is stored in the FIFO (normal mode). 4 9_BITS_MATCH 9 bits. The 9th bit is not stored in the FIFO (fixed mode). This mode is used when the 9th bit is only used for match operations (see MATMD). 5 RSCEN Receiver Smartcard Parity Response Enable. 12 1 DISABLED The receiver does not send a Smartcard parity error response. 0 ENABLED The receiver sends a Smartcard parity response. 1 RIRDAEN Receiver IrDA Enable. 13 1 DISABLED The receiver does not operate in IrDA mode. 0 ENABLED The receiver operates in IrDA mode. 1 RINVEN Receiver Invert Enable. 14 1 DISABLED Do not invert the RX pin signals (the RX idle state is high). 0 ENABLED Invert the RX pin signals (the RX idle state is low). 1 TSTRTEN Transmitter Start Enable. 16 1 DISABLED Do not generate a start bit during transmissions. 0 ENABLED Generate a start bit during transmissions. 1 TPAREN Transmitter Parity Enable. 17 1 DISABLED Do not send a parity bit during transmissions. 0 ENABLED Send a parity bit during transmissions. 1 TSTPEN Transmitter Stop Enable. 18 1 DISABLED Do not send stop bits during transmissions. 0 ENABLED Send stop bits during transmissions. 1 TSTPMD Transmitter Stop Mode. 19 2 0P5_STOP 0.5 stop bit. 0 1_STOP 1 stop bit. 1 1P5_STOP 1.5 stop bits. 2 2_STOP 2 stop bits. 3 TPARMD Transmitter Parity Mode. 21 2 ODD Odd Parity. 0 EVEN Even Parity. 1 MARK Set (Parity = 1). 2 SPACE Clear (Parity = 0). 3 TDATLN Transmitter Data Length. 24 3 5_BITS 5 bits. 0 6_BITS 6 bits. 1 7_BITS 7 bits. 2 8_BITS 8 bits. 3 9_BITS_FIFO 9 bits. The 9th bit is taken from the FIFO data (normal mode). 4 9_BITS_TBIT 9 bits. The 9th bit is set by the value of TBIT (fixed mode). 5 TSCEN Transmitter Smartcard Parity Response Enable. 28 1 DISABLED The transmitter does not check for a Smartcard parity error response. 0 ENABLED The transmitter checks for a Smartcard parity error response. 1 TIRDAEN Transmitter IrDA Enable. 29 1 DISABLED Disable IrDA transmit mode. 0 ENABLED Enable IrDA transmit mode. 1 TINVEN Transmitter Invert Enable. 30 1 DISABLED Do not invert the TX pin signals (the TX idle state is high). 0 ENABLED Invert the TX pin signals (the TX idle state is low). 1 MODE Module Mode Select 0x10 0x00600000 0xFFFFFFFF RTCCKMD RTC Clock Mode. 8 1 APBCLK UART clocked from the APB clock. The RBAUD and TBAUD controls will use the APB clock mode to determine the baudrate unless RTCBDMD = 1. 0 RTC0TCLK UART clocked from RTC0TCLK. The RBAUD and TBAUD controls will use the RTC0TCLK mode to determine the baudrate. Software should only set this bit to one when the UART is idle. 1 RTCBDMD RTC Baud Rate Mode. 9 1 DISABLED The RBAUD and TBAUD controls use the RTCCKMD setting to determine whether to use APB clock mode (RTCCKMD = 0) or the RTC0TCLK mode (RTCCKMD = 1). Use this setting when APB clock != RTC0TCLK. 0 ENABLED The RBAUD and TBAUD controls use RTC0TCLK mode. Use this setting when APB clock = RTC0TCLK and RTCCKMD = 0 to force the RBAUD and TBAUD controls into RTC0TCLK mode. 1 FORCECLK Force Clock On. 10 1 DISABLED UART clock is only on when necessary. 0 ENABLED Force the UART clock to always be on. 1 CLKBUSY Clock Switch Busy Status. 11 1 read-only IDLE Clock switch completed. 0 BUSY Clock switch in progress. 1 RXCLKSW Receive Automatic Clock Switch. 12 1 DISABLED UART will always use the selected clock for receive operations. 0 ENABLED UART will automatically switch from RTC0TCLK to the APB clock when a receive interrupt is pending. 1 TXCLKSW Transmit Automatic Clock Switch. 13 1 DISABLED UART will always use the selected clock for transmit operations. 0 ENABLED UART will automatically switch from RTC0TCLK to the APB clock when a transmit interrupt is pending. 1 DBGMD UART Debug Mode. 16 1 RUN The UART module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the UART module to halt. Any active transmissions and receptions will complete first. 1 LBMD Loop Back Mode. 18 2 DISABLED Loop back is disabled and the TX and RX signals are connected to the corresponding external pins. 0 RXONLY Receive loop back. The receiver input path is disconnected from the RX pin and internally connected to the transmitter. Data transmitted will be sent out on TX and also received by the device. 1 TXONLY Transmit loop back. The transmitter output path is disconnected from the TX pin and the RX input pin is internally looped back out to the TX pin. Data received at RX will be received by the device and also sent directly back out on TX. 2 BOTH Full loop back. Internally, the transmitter output is routed back to the receiver input. Neither the transmitter nor receiver are connected to external device pins. The device pin RX is looped back to TX in a similar fashion. Data transmitted on TX will be sent directly back in on RX. 3 DUPLEXMD Duplex Mode. 27 1 FULL_DUPLEX Full-duplex mode. The transmitter and receiver can operate simultaneously. 0 HALF_DUPLEX Half-duplex mode. The transmitter automatically inhibits when the receiver is active and the receiver automatically inhibits when the transmitter is active. 1 ITSEN Idle TX Tristate Enable. 30 1 DISABLED The TX pin is always an output in this mode, even when idle. 0 ENABLED The TX pin is tristated when idle. 1 FLOWCN Flow Control 0x20 0x00000001 0xFFFFFFFF RX RX Pin Status. 1 1 read-only LOW RX pin (after optional inversion) is low. 0 HIGH RX pin (after optional inversion) is high. 1 TXOEN TX Output Enable. 12 1 DISABLED The pin assigned to TX is controlled by the direct port output value. 0 ENABLED The pin assigned to TX is controlled by the UART. 1 TX TX State. 17 1 LOW The TX pin (before optional inversion) is low. 0 HIGH The TX pin (before optional inversion) is high. 1 TIRDAPW Transmit IrDA Pulse Width. 28 2 1_16TH The IrDA pulse width is 1/16th of a bit period. 0 1_8TH The IrDA pulse width is 1/8th of a bit period. 1 3_16TH The IrDA pulse width is 3/16th of a bit period. 2 1_4TH The IrDA pulse width is 1/4th of a bit period. 3 CONTROL Module Control 0x30 0x00000000 0xFFFFFFFF RFRMERI Receive Frame Error Interrupt Flag. 0 1 NOT_SET Read: A frame error has not occurred since RFRMERI was last cleared. Write: Clear the interrupt. 0 SET Read: A frame error occurred. Write: Force a frame error interrupt. 1 RPARERI Receive Parity Error Interrupt Flag. 1 1 NOT_SET Read: An invalid parity bit has not been received since RPARERI was last cleared. Write: Clear the interrupt. 0 SET Read: An invalid parity bit has been received since RPARERI was last cleared. Write: Force a parity error interrupt. 1 ROREI Receive Overrun Error Interrupt Flag. 2 1 NOT_SET Read: A receiver overrun has not occurred since ROREI was last cleared. Write: Clear the interrupt. 0 SET Read: A receiver overrun occurred. Write: Force a receiver overrun interrupt. 1 RDREQI Receive Data Request Interrupt Flag. 3 1 read-only NOT_SET Fewer than RFTH FIFO entries are filled with data. 0 SET At least RFTH FIFO entries are filled with data. 1 RERIEN Receive Error Interrupt Enable. 5 1 DISABLED Disable the receive error interrupt. 0 ENABLED Enable the receive error interrupt. A receive interrupt is asserted when ROREI, RFRMERI, or RPARERI is set to 1. 1 RDREQIEN Receive Data Request Interrupt Enable. 6 1 DISABLED Disable the read data request interrupt. 0 ENABLED Enable the read data request interrupt. A receive interrupt is generated when RDREQI is set to 1. 1 MATMD Match Mode. 8 2 OFF Disable the match function. 0 MCE (MCE) Data whose last data bit equals RBIT is accepted and stored. 1 FRAME (Frame) A framing error is asserted if the last received data bit matches RBIT. 2 STORE (Store) Store the last incoming data bit in RBIT. This mode can be used inconjunction with the RDATLN setting. 3 RABDEN Receiver Auto-Baud Enable. 10 1 DISABLED Disable receiver auto-baud. 0 ENABLED Enable receiver auto-baud. 1 RBUSYF Receiver Busy Flag. 11 1 read-only NOT_SET The UART receiver is idle. 0 SET The UART receiver is receiving data. 1 RBIT Last Receive Bit. 12 1 NOT_SET 0 SET 1 ROSEN Receiver One-Shot Enable. 13 1 DISABLED Disable one-shot receive mode. 0 ENABLED Enable one-shot receive mode. 1 RINH Receiver Inhibit. 14 1 INACTIVE The receiver operates normally. 0 ACTIVE The receiver will complete any ongoing reception, but ignore all traffic after that. 1 REN Receiver Enable. 15 1 DISABLED Disable the receiver. The receiver can receive one data transaction only if ROSEN is set. 0 ENABLED Enable the receiver. 1 TSCERI Smartcard Parity Error Interrupt Flag. 16 1 NOT_SET Read: A Smartcard parity error has not occurred since TSCERI was last cleared. Write: Clear the interrupt. 0 SET Read: A Smartcard parity error occurred. Write: Force a Smartcard parity error interrupt. 1 TDREQI Transmit Data Request Interrupt Flag. 18 1 read-only NOT_SET The transmitter is not requesting more FIFO data. 0 SET The transmitter is requesting more FIFO data. 1 TCPTI Transmit Complete Interrupt Flag. 19 1 NOT_SET Read: A transmit has not completed since TCPTI was last cleared. Write: Clear the interrupt. 0 SET Read: A byte was transmitted (TCCPTH = 0) or the last available byte was transmitted (TCPTTH = 1). Write: Force a transmit complete interrupt. 1 TCPTTH Transmit Complete Threshold. 20 1 SET_ON_TX The TCPTI flag is set after each data transmission. 0 SET_ON_EMPTY The TCPTI flag is set after transmission of the last available data. 1 TERIEN Transmit Error Interrupt Enable. 21 1 DISABLED Disable the transmit error interrupt. 0 ENABLED Enable the transmit error interrupt. A transmit interrupt is generated when TUREI or TSCERI is set to 1. 1 TDREQIEN Transmit Data Request Interrupt Enable. 22 1 DISABLED Disable the transmit data request interrupt. 0 ENABLED Enable the transmit data request interrupt. A transmit interrupt is asserted when TDREQI is set to 1. 1 TCPTIEN Transmit Complete Interrupt Enable. 23 1 DISABLED Disable the transmit complete interrupt. 0 ENABLED Enable the transmit complete interrupt. A transmit interrupt is generated when TCPTI is set to 1. 1 TBUSYF Transmitter Busy Flag. 27 1 read-only NOT_SET The UART transmitter is idle. 0 SET The UART transmitter is active and transmitting. 1 TBIT Last Transmit Bit. 28 1 NOT_SET 0 SET 1 TINH Transmit Inhibit. 30 1 INACTIVE The transmitter operates normally. 0 ACTIVE Transmissions are inhibited. The transmitter will stall after any current transmission is complete. 1 TEN Transmitter Enable. 31 1 DISABLED Disable the transmitter. When cleared, the transmitter immediately aborts any active transmission. Clearing this bit does not automatically flush the transmit FIFO. 0 ENABLED Enable the transmitter. The transmitter will initiate a transmission when data becomes available in the transmit FIFO. 1 IPDELAY Inter-Packet Delay 0x40 0x00000000 0xFFFFFFFF IPDELAY Inter-Packet Delay. 16 8 BAUDRATE Transmit and Receive Baud Rate 0x50 0x00000000 0xFFFFFFFF RBAUD Receiver Baud Rate Control. 0 16 TBAUD Transmitter Baud Rate Control. 16 16 FIFOCN FIFO Control 0x60 0x00000000 0xFFFFFFFF RCNT Receive FIFO Count. 0 3 read-only RFTH Receive FIFO Threshold. 4 2 ONE A read data request interrupt (RDREQI) is asserted when >= 1 FIFO entry is full. 0 TWO A read data request interrupt (RDREQI) is asserted when >= 2 FIFO entries are full. 1 THREE A read data request interrupt (RDREQI) is asserted when >= 3 FIFO entries are full. 2 FOUR A read data request interrupt (RDREQI) is asserted when >= 4 FIFO entries are full. 3 RFIFOFL Receive FIFO Flush. 8 1 SET Flush the contents of the receive FIFO and any data in the receive shift register. 1 RFERI Receive FIFO Error Interrupt Flag. 9 1 NOT_SET A receive FIFO error has not occurred since RFERI was last cleared. 0 SET A receive FIFO error occurred. 1 RSRFULLF Receive Shift Register Full Flag. 10 1 read-only NOT_SET The receive data shift register is not full. 0 SET The receive data shift register is full. 1 TCNT Transmit FIFO Count. 16 3 read-only TFTH Transmit FIFO Threshold. 20 2 ONE A transmit data request interrupt (TDREQI) is asserted when >= 1 FIFO entry is empty. 0 TWO A transmit data request interrupt (TDREQI) is asserted when >= 2 FIFO entries are empty. 1 THREE A transmit data request interrupt (TDREQI) is asserted when >= 3 FIFO entries are empty. 2 FOUR A transmit data request interrupt (TDREQI) is asserted when >= 4 FIFO entries are empty. 3 TFIFOFL Transmit FIFO Flush. 24 1 SET Flush the contents of the transmit FIFO. If data is pending in the transmit shift register but a transmit has not begun, the shift register is also flushed. 1 TFERI Transmit FIFO Error Interrupt Flag. 25 1 NOT_SET A transmit FIFO error has not occurred since TFERI was last cleared. 0 SET A transmit FIFO error occurred. 1 TSRFULLF Transmit Shift Register Full Flag. 26 1 read-only NOT_SET The transmit shift register is not full. 0 SET The transmit shift register is full. 1 DATA FIFO Input/Output Data 0x70 0x00000000 0xFFFFFFFF modifyExternal DATA FIFO Data. 0 32 CLKDIV Clock Divider 0x80 0x00000001 0xFFFFFFFF CLKDIV Clock Divider. 0 2 DIV1 Divide by 1. 0 DIV2 Divide by 2. 1 DIV4 Divide by 4. 2 USART_0 B None USART_0 0x40000000 0x0 0xffc registers USART0_IRQn 24 CONFIG Module Configuration 0x0 0x030D030D 0xFFFFFFFF RSTRTEN Receiver Start Enable. 0 1 DISABLED Do not expect a start bit during receptions. 0 ENABLED Expect a start bit during receptions. 1 RPAREN Receiver Parity Enable. 1 1 DISABLED Do not expect a parity bit during receptions. 0 ENABLED Expect a parity bit during receptions. 1 RSTPEN Receiver Stop Enable. 2 1 DISABLED Do not expect stop bits during receptions. 0 ENABLED Expect stop bits during receptions. 1 RSTPMD Receiver Stop Mode. 3 2 0P5_STOP 0.5 stop bit. 0 1_STOP 1 stop bit. 1 1P5_STOP 1.5 stop bits. 2 2_STOP 2 stop bits. 3 RPARMD Receiver Parity Mode. 5 2 ODD Odd Parity. 0 EVEN Even Parity. 1 MARK Set (Parity = 1). 2 SPACE Clear (Parity = 0). 3 RDATLN Receiver Data Length. 8 3 5_BITS 5 bits. 0 6_BITS 6 bits. 1 7_BITS 7 bits. 2 8_BITS 8 bits. 3 9_BITS_STORED 9 bits. The 9th bit is stored in the FIFO (normal mode). 4 9_BITS_MATCH 9 bits. The 9th bit is not stored in the FIFO (fixed mode). This mode is used when the 9th bit is only used for match operations (see MATMD). 5 RSCEN Receiver Smartcard Parity Response Enable. 12 1 DISABLED The receiver does not send a Smartcard parity error response. 0 ENABLED The receiver sends a Smartcard parity response. 1 RIRDAEN Receiver IrDA Enable. 13 1 DISABLED The receiver does not operate in IrDA mode. 0 ENABLED The receiver operates in IrDA mode. 1 RINVEN Receiver Invert Enable. 14 1 DISABLED Do not invert the RX pin signals (the RX idle state is high). 0 ENABLED Invert the RX pin signals (the RX idle state is low). 1 RSYNCEN Receiver Synchronous Mode Enable. 15 1 DISABLED The receiver operates in asynchronous mode. 0 ENABLED The receiver operates in synchronous mode. 1 TSTRTEN Transmitter Start Enable. 16 1 DISABLED Do not generate a start bit during transmissions. 0 ENABLED Generate a start bit during transmissions. 1 TPAREN Transmitter Parity Enable. 17 1 DISABLED Do not send a parity bit during transmissions. 0 ENABLED Send a parity bit during transmissions. 1 TSTPEN Transmitter Stop Enable. 18 1 DISABLED Do not send stop bits during transmissions. 0 ENABLED Send stop bits during transmissions. 1 TSTPMD Transmitter Stop Mode. 19 2 0P5_STOP 0.5 stop bit. 0 1_STOP 1 stop bit. 1 1P5_STOP 1.5 stop bits. 2 2_STOP 2 stop bits. 3 TPARMD Transmitter Parity Mode. 21 2 ODD Odd Parity. 0 EVEN Even Parity. 1 MARK Set (Parity = 1). 2 SPACE Clear (Parity = 0). 3 TDATLN Transmitter Data Length. 24 3 5_BITS 5 bits. 0 6_BITS 6 bits. 1 7_BITS 7 bits. 2 8_BITS 8 bits. 3 9_BITS_FIFO 9 bits. The 9th bit is taken from the FIFO data (normal mode). 4 9_BITS_TBIT 9 bits. The 9th bit is set by the value of TBIT (fixed mode). 5 TSCEN Transmitter Smartcard Parity Response Enable. 28 1 DISABLED The transmitter does not check for a Smartcard parity error response. 0 ENABLED The transmitter checks for a Smartcard parity error response. 1 TIRDAEN Transmitter IrDA Enable. 29 1 DISABLED Disable IrDA transmit mode. 0 ENABLED Enable IrDA transmit mode. 1 TINVEN Transmitter Invert Enable. 30 1 DISABLED Do not invert the TX pin signals (the TX idle state is high). 0 ENABLED Invert the TX pin signals (the TX idle state is low). 1 TSYNCEN Transmitter Synchronous Mode Enable. 31 1 DISABLED The transmitter operates in asynchronous mode. 0 ENABLED The transmitter operates in synchronous mode. 1 MODE Module Mode Select 0x10 0x00600000 0xFFFFFFFF DBGMD USART Debug Mode. 16 1 RUN The USART module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the USART module to halt. Any active transmissions and receptions will complete first. 1 LBMD Loop Back Mode. 18 2 DISABLED Loop back is disabled and the TX and RX signals are connected to the corresponding external pins. 0 RXONLY Receive loop back. The receiver input path is disconnected from the RX pin and internally connected to the transmitter. Data transmitted will be sent out on TX and also received by the device. 1 TXONLY Transmit loop back. The transmitter output path is disconnected from the TX pin and the RX input pin is internally looped back out to the TX pin. Data received at RX will be received by the device and also sent directly back out on TX. 2 BOTH Full loop back. Internally, the transmitter output is routed back to the receiver input. Neither the transmitter nor receiver are connected to external device pins. The device pin RX is looped back to TX in a similar fashion. Data transmitted on TX will be sent directly back in on RX. 3 STPSTCLK Stop State Clock Control. 21 1 DISABLED When the USART is a clock master, the clock is not generated during stop bits. 0 ENABLED When the USART is a clock master, the clock is generated during stop bits. 1 STRTSTCLK Start State Clock Control. 22 1 DISABLED When the USART is a clock master, the clock is held idle during a start bit. 0 ENABLED When the USART is a clock master, the clock is generated during a start bit. 1 ISTCLK Idle Clock Control. 23 1 DISABLED When the USART is a clock master, the clock is held idle between transmissions. 0 ENABLED When the USART is a clock master, the clock is generated between transmissions or receptions. 1 DUPLEXMD Duplex Mode. 27 1 FULL_DUPLEX Full-duplex mode. The transmitter and receiver can operate simultaneously. 0 HALF_DUPLEX Half-duplex mode. The transmitter automatically inhibits when the receiver is active and the receiver automatically inhibits when the transmitter is active. 1 CLKIDLE Clock Idle State. 28 1 IDLE_LOW The synchronous clock is low when idle. 0 IDLE_HIGH The synchronous clock is high when idle. 1 CLKESEL Clock Edge Select. 29 1 FALLING The clock falls in the middle of each bit. 0 RISING The clock rises in the middle of each bit. 1 ITSEN Idle TX/UCLK Tristate Enable. 30 1 DISABLED The TX and UCLK (if in synchronous master mode) pins are always an output in this mode, even when idle. 0 ENABLED If ISTCLK is cleared to 0, the TX pin is tristated when idle. The UCLK pin will also be tristated when idle if in synchronous master mode. 1 OPMD Operational Mode. 31 1 SLAVE The USART operates as a slave. 0 MASTER The USART operates as a master. 1 FLOWCN Flow Control 0x20 0x00000001 0xFFFFFFFF RTS RTS State. 0 1 LOW RTS pin (before optional inversion) is driven low. 0 HIGH RTS pin (before optional inversion) is driven high. 1 RX RX Pin Status. 1 1 read-only LOW RX pin (after optional inversion) is low. 0 HIGH RX pin (after optional inversion) is high. 1 RTSINVEN RTS Invert Enable. 5 1 DISABLED The USART does not invert the RTS signal before driving the pin. 0 ENABLED The USART inverts the RTS signal driving the pin. 1 RTSTH RTS Threshold Control. 6 1 FULL RTS is de-asserted when the receive FIFO and shift register are full and no more incoming data can be stored. 0 ONE_BYTE_FREE RTS is de-asserted when the receive FIFO and shift register are nearly full and only one more data can be received. 1 RTSEN RTS Enable. 7 1 DISABLED The RTS state is not changed by hardware. The RTS bit can be written only when hardware RTS is disabled (RTSEN = 0). 0 ENABLED Hardware sets RTS when the receive FIFO is at or above the threshold set by RTSTH and clears RTS otherwise. 1 TXOEN TX Output Enable. 12 1 DISABLED The pin assigned to TX is tri-stated, regardless of other settings. 0 ENABLED The pin assigned to TX is controlled by the USART. 1 CTS CTS State. 16 1 read-only LOW Indicates the CTS pin state (after optional inversion) is low. 0 HIGH Indicates the CTS pin state (after optional inversion) is high. 1 TX TX State. 17 1 LOW The TX pin (before optional inversion) is low. 0 HIGH The TX pin (before optional inversion) is high. 1 UCLK UCLK State. 18 1 LOW The UCLK pin is low. 0 HIGH The UCLK pin is high. 1 CTSINVEN CTS Invert Enable. 21 1 DISABLED The USART does not invert CTS. 0 ENABLED The USART inverts CTS. 1 CTSEN CTS Enable. 23 1 DISABLED The CTS pin state does not affect transmissions. 0 ENABLED Transmissions will begin only if the CTS pin (after optional inversion) is low. 1 TIRDAPW Transmit IrDA Pulse Width. 28 2 1_16TH The IrDA pulse width is 1/16th of a bit period. 0 1_8TH The IrDA pulse width is 1/8th of a bit period. 1 3_16TH The IrDA pulse width is 3/16th of a bit period. 2 1_4TH The IrDA pulse width is 1/4th of a bit period. 3 CONTROL Module Control 0x30 0x00000000 0xFFFFFFFF RFRMERI Receive Frame Error Interrupt Flag. 0 1 NOT_SET Read: A frame error has not occurred since RFRMERI was last cleared. Write: Clear the interrupt. 0 SET Read: A frame error occurred. Write: Force a frame error interrupt. 1 RPARERI Receive Parity Error Interrupt Flag. 1 1 NOT_SET Read: An invalid parity bit has not been received since RPARERI was last cleared. Write: Clear the interrupt. 0 SET Read: An invalid parity bit has been received since RPARERI was last cleared. Write: Force a parity error interrupt. 1 ROREI Receive Overrun Error Interrupt Flag. 2 1 NOT_SET Read: A receiver overrun has not occurred since ROREI was last cleared. Write: Clear the interrupt. 0 SET Read: A receiver overrun occurred. Write: Force a receiver overrun interrupt. 1 RDREQI Receive Data Request Interrupt Flag. 3 1 read-only NOT_SET Fewer than RFTH FIFO entries are filled with data. 0 SET At least RFTH FIFO entries are filled with data. 1 RERIEN Receive Error Interrupt Enable. 5 1 DISABLED Disable the receive error interrupt. 0 ENABLED Enable the receive error interrupt. A receive interrupt is asserted when ROREI, RFRMERI, or RPARERI is set to 1. 1 RDREQIEN Receive Data Request Interrupt Enable. 6 1 DISABLED Disable the read data request interrupt. 0 ENABLED Enable the read data request interrupt. A receive interrupt is generated when RDREQI is set to 1. 1 MATMD Match Mode. 8 2 OFF Disable the match function. 0 MCE (MCE) Data whose last data bit equals RBIT is accepted and stored. 1 FRAME (Frame) A framing error is asserted if the last received data bit matches RBIT. 2 STORE (Store) Store the last incoming data bit in RBIT. This mode can be used inconjunction with the RDATLN setting. 3 RABDEN Receiver Auto-Baud Enable. 10 1 DISABLED Disable receiver auto-baud. 0 ENABLED Enable receiver auto-baud. 1 RBUSYF Receiver Busy Flag. 11 1 read-only NOT_SET The USART receiver is idle. 0 SET The USART receiver is receiving data. 1 RBIT Last Receive Bit. 12 1 NOT_SET 0 SET 1 ROSEN Receiver One-Shot Enable. 13 1 DISABLED Disable one-shot receive mode. 0 ENABLED Enable one-shot receive mode. 1 RINH Receiver Inhibit. 14 1 INACTIVE The receiver operates normally. 0 ACTIVE RTS is immediately asserted when RINH is set. The receiver will complete any ongoing reception, but ignore all traffic after that. 1 REN Receiver Enable. 15 1 DISABLED Disable the receiver. The receiver can receive one data transaction only if ROSEN is set. 0 ENABLED Enable the receiver. 1 TSCERI Smartcard Parity Error Interrupt Flag. 16 1 NOT_SET Read: A Smartcard parity error has not occurred since TSCERI was last cleared. Write: Clear the interrupt. 0 SET Read: A Smartcard parity error occurred. Write: Force a Smartcard parity error interrupt. 1 TUREI Transmit Underrun Error Interrupt Flag. 17 1 NOT_SET Read: A transmitter underrun has not occurred since TUREI was last cleared. Write: Clear the interrupt. 0 SET Read: A transmitter underrun occurred. Write: Force a transmitter underrun interrupt. 1 TDREQI Transmit Data Request Interrupt Flag. 18 1 read-only NOT_SET The transmitter is not requesting more FIFO data. 0 SET The transmitter is requesting more FIFO data. 1 TCPTI Transmit Complete Interrupt Flag. 19 1 NOT_SET Read: A transmit has not completed since TCPTI was last cleared. Write: Clear the interrupt. 0 SET Read: A byte was transmitted (TCCPTH = 0) or the last available byte was transmitted (TCPTTH = 1). Write: Force a transmit complete interrupt. 1 TCPTTH Transmit Complete Threshold. 20 1 SET_ON_TX The TCPTI flag is set after each data transmission. 0 SET_ON_EMPTY The TCPTI flag is set after transmission of the last available data. 1 TERIEN Transmit Error Interrupt Enable. 21 1 DISABLED Disable the transmit error interrupt. 0 ENABLED Enable the transmit error interrupt. A transmit interrupt is generated when TUREI or TSCERI is set to 1. 1 TDREQIEN Transmit Data Request Interrupt Enable. 22 1 DISABLED Disable the transmit data request interrupt. 0 ENABLED Enable the transmit data request interrupt. A transmit interrupt is asserted when TDREQI is set to 1. 1 TCPTIEN Transmit Complete Interrupt Enable. 23 1 DISABLED Disable the transmit complete interrupt. 0 ENABLED Enable the transmit complete interrupt. A transmit interrupt is generated when TCPTI is set to 1. 1 TBUSYF Transmitter Busy Flag. 27 1 read-only NOT_SET The USART transmitter is idle. 0 SET The USART transmitter is active and transmitting. 1 TBIT Last Transmit Bit. 28 1 NOT_SET 0 SET 1 TINH Transmit Inhibit. 30 1 INACTIVE The transmitter operates normally. 0 ACTIVE Transmissions are inhibited. The transmitter will stall after any current transmission is complete. 1 TEN Transmitter Enable. 31 1 DISABLED Disable the transmitter. When cleared, the transmitter immediately aborts any active transmission. Clearing this bit does not automatically flush the transmit FIFO. 0 ENABLED Enable the transmitter. The transmitter will initiate a transmission when data becomes available in the transmit FIFO. 1 IPDELAY Inter-Packet Delay 0x40 0x00000000 0xFFFFFFFF IPDELAY Inter-Packet Delay. 16 8 BAUDRATE Transmit and Receive Baud Rate 0x50 0x00000000 0xFFFFFFFF RBAUD Receiver Baud Rate Control. 0 16 TBAUD Transmitter Baud Rate Control. 16 16 FIFOCN FIFO Control 0x60 0x00000000 0xFFFFFFFF RCNT Receive FIFO Count. 0 3 read-only RFTH Receive FIFO Threshold. 4 2 ONE A DMA request or read data request interrupt (RDREQI) is asserted when >= 1 FIFO entry is full. 0 TWO A DMA request or read data request interrupt (RDREQI) is asserted when >= 2 FIFO entries are full. 1 THREE A DMA request or read data request interrupt (RDREQI) is asserted when >= 3 FIFO entries are full. 2 FOUR A DMA request or read data request interrupt (RDREQI) is asserted when >= 4 FIFO entries are full. 3 RDMAEN Receiver DMA Enable. 7 1 DISABLED Disable receive FIFO DMA requests. 0 ENABLED Enable receive FIFO DMA requests. 1 RFIFOFL Receive FIFO Flush. 8 1 SET Flush the contents of the receive FIFO and any data in the receive shift register. 1 RFERI Receive FIFO Error Interrupt Flag. 9 1 NOT_SET A receive FIFO error has not occurred since RFERI was last cleared. 0 SET A receive FIFO error occurred. 1 RSRFULLF Receive Shift Register Full Flag. 10 1 read-only NOT_SET The receive data shift register is not full. 0 SET The receive data shift register is full. 1 TCNT Transmit FIFO Count. 16 3 read-only TFTH Transmit FIFO Threshold. 20 2 ONE A DMA request or transmit data request interrupt (TDREQI) is asserted when >= 1 FIFO entry is empty. 0 TWO A DMA request or transmit data request interrupt (TDREQI) is asserted when >= 2 FIFO entries are empty. 1 THREE A DMA request or transmit data request interrupt (TDREQI) is asserted when >= 3 FIFO entries are empty. 2 FOUR A DMA request or transmit data request interrupt (TDREQI) is asserted when >= 4 FIFO entries are empty. 3 TDMAEN Transmitter DMA Enable. 23 1 DISABLED Disable transmit FIFO DMA requests. 0 ENABLED Enable transmit FIFO DMA requests. 1 TFIFOFL Transmit FIFO Flush. 24 1 SET Flush the contents of the transmit FIFO. If data is pending in the transmit shift register but a transmit has not begun, the shift register is also flushed. 1 TFERI Transmit FIFO Error Interrupt Flag. 25 1 NOT_SET A transmit FIFO error has not occurred since TFERI was last cleared. 0 SET A transmit FIFO error occurred. 1 TSRFULLF Transmit Shift Register Full Flag. 26 1 read-only NOT_SET The transmit shift register is not full. 0 SET The transmit shift register is full. 1 DATA FIFO Input/Output Data 0x70 0x00000000 0xFFFFFFFF modifyExternal DATA FIFO Data. 0 32 VMON_0 B None VMON_0 0x4002f000 0x0 0xffc registers VDDLOW_IRQn 38 CONTROL Module Control 0x0 0x80000000 0xFFFFFFFF VBATRSTF VBAT Reset Threshold Status Flag. 2 1 read-only VBAT_IS_BELOW_RESET The VBAT voltage is below the VBAT reset threshold. 0 VBAT_IS_ABOVE_RESET The VBAT voltage is above the VBAT reset threshold. 1 VBATLI VBAT Low Interrupt Flag. 3 1 read-only VBAT_IS_LOW The VBAT voltage is below the early warning threshold. 0 VBAT_IS_OK The VBAT voltage is above the early warning threshold. 1 VBATHITHEN VBAT High Threshold Enable. 4 1 DISABLED Use the standard VBAT thresholds. 0 ENABLED Use the high VBAT thresholds. 1 VBATLIEN VBAT Low Interrupt Enable. 6 1 DISABLED Disable the VBAT low interrupt. 0 ENABLED Enable the VBAT low interrupt. 1 VMONEN VBAT Supply Monitor Enable. 31 1 DISABLED Disable the VBAT supply monitor. 0 ENABLED Enable the VBAT supply monitor. 1 VREF_0 B None VREF_0 0x40039010 0x0 0xffc registers CONTROL Module Control 0x0 0x00000000 0xFFFFFFFF VREF2X Voltage Reference Doubler. 0 1 DISABLED VREF output is nominally 1.2 V 0 ENABLED VREF output is nominally 2.4 V 1 TEMPEN Temperature Sensor Enable. 1 1 DISABLED Disable the temperature sensor. 0 ENABLED Enable the temperature sensor. 1 VREFOUTEN VREF Output Enable. 2 1 DISABLED Internal VREF is not driven on the VREF pin. 0 ENABLED Internal VREF is driven out to the VREF pin. 1 WDTIMER_0 A None WDTIMER_0 0x40030000 0x0 0xffc registers WDTIMER0_IRQn 0 CONTROL Module Control 0x0 0x00000002 0xFFFFFFFF EWIEN Early Warning Interrupt Enable. 0 1 DISABLED Disable the early warning interrupt (EWI). 0 ENABLED Enable the early warning interrupt (EWI). 1 DBGMD Watchdog Timer Debug Mode. 1 1 RUN The WDTIMER module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the WDTIMER module to halt. 1 STATUS Module Status 0x10 0x00000000 0xFFFFFFFF KEYSTS Key Status. 0 1 read-only IDLE No keys have been processed by the interface. 0 READY The attention key has been received and the module is awaiting a command. 1 PRIVSTS Register Access Status. 1 1 read-only READ_ONLY The watchdog timer registers are currently read-only. 0 READ_WRITE A write transaction can be performed on the module registers. 1 EWI Early Warning Interrupt Flag. 2 1 NOT_SET Read: An early warning match did not occur. Write: Clear the early warning interrupt. 0 SET Read: An early warning match occurred and the interrupt is pending. Write: Force a watchdog timer early warning interrupt to occur. 1 RTHF Reset Threshold Flag. 3 1 read-only LT The counter is currently less than the reset threshold (RTH) value. 0 GTE The counter is currently greater than or equal to the reset threshold (RTH) value. 1 UPDSTS Watchdog Timer Threshold Update Status. 4 1 read-only IDLE An update completed or is not pending. The EWTH and RTH fields can be written. 0 UPDATING An update of the threshold register is occurring. The EWTH and RTH fields should not be modified until hardware clears UPDSTS to 0. 1 THRESHOLD Threshold Values 0x20 0xFFFF7FFF 0xFFFFFFFF EWTH Early Warning Threshold. 0 16 RTH Reset Threshold. 16 16 WDTKEY Module Key 0x30 0x00000000 0xFFFFFFFF KEY Watchdog Timer Key. 0 8 write-only ATTN Attention key to start the command sequence. 165 RESET Reset the watchdog timer. 204 DISABLE Disable the watchdog timer. 221 START Start the watchdog timer. 238 WRITE Allow one write access to the module registers. 241 LOCK Lock the module from any other writes until the next system reset. 255