SIM3C164_B 1 256K Flash, 32K RAM 8 32 32 read-write SARADC_0 A None ADC 0x4001a000 0x0 0xffc registers SARADC0_IRQn 35 CONFIG Module Configuration 0x0 0x00000000 0xFFFFFFFF SPSEL Sampling Phase Select. 0 4 PHASE0 The ADC samples at SSG phase 0. 0 PHASE1 The ADC samples at SSG phase 1. 1 PHASE2 The ADC samples at SSG phase 2. 2 PHASE3 The ADC samples at SSG phase 3. 3 PHASE4 The ADC samples at SSG phase 4. 4 PHASE5 The ADC samples at SSG phase 5. 5 PHASE6 The ADC samples at SSG phase 6. 6 PHASE7 The ADC samples at SSG phase 7. 7 PHASE8 The ADC samples at SSG phase 8. 8 PHASE9 The ADC samples at SSG phase 9. 9 PHASE10 The ADC samples at SSG phase 10. 10 PHASE11 The ADC samples at SSG phase 11. 11 PHASE12 The ADC samples at SSG phase 12. 12 PHASE13 The ADC samples at SSG phase 13. 13 PHASE14 The ADC samples at SSG phase 14. 14 PHASE15 The ADC samples at SSG phase 15. 15 SPEN Sampling Phase Enable. 4 1 DISABLED Disable Phase Select. The ADC will always sample on the start-of-conversion trigger selected by the SCSEL field. 0 ENABLED Enable Phase Select. The ADC will sample according to the phase selected by the SPSEL field. 1 SSGEN Synchronous Sample Generator Enable. 5 1 DISABLED Disable the SAR clock output to SSG. 0 ENABLED The ADC is the SSG master, and the SAR clock will be output to the SSG block. 1 PACKMD Output Packing Mode. 6 2 UPPER_ONLY Data is written to the upper half-word and the lower half-word is filled with 0's. An SCI interrupt is triggered when data is written, if enabled. 0 LOWER_ONLY Data is written to the lower half-word, and the upper half-word is filled with 0's. An SCI interrupt is triggered when data is written, if enabled. 1 UPPER_FIRST Two data words are packed into the register with the upper half-word representing the earlier data, and the lower half-word representing the later data. If SIMCEN is set to 1, the upper half-word represents data from the master ADC (selected by SSGEN) and the lower half-word represents data from the slave ADC. The ADC write to the lower half-word will trigger the SCI interrupt, if enabled. 2 LOWER_FIRST Two data words are packed into the register with the lower half-word representing the earlier data, and the upper half-word representing the later data. If SIMCEN is set to 1, the lower half-word represents data from the master ADC (selected by SSGEN) and the upper half-word represents data from the slave ADC. The ADC write to the upper half-word will trigger the SCI interrupt, if enabled. 3 SIMCEN Simultaneous Conversion Packing Enable. 8 1 DISABLED Disable simultaneous mode conversion packing. 0 ENABLED Enable simultaneous mode conversion packing. 1 INTLVEN Interleaved Conversion Packing Enable. 9 1 DISABLED Disable interleaved mode conversion packing. 0 ENABLED Enable interleaved mode conversion packing. 1 SCANEN Scan Mode Enable. 10 1 DISABLED Disable ADC scan mode. 0 ENABLED Enable ADC scan mode. The ADC will scan through the defined time slots in sequence on every start of conversion. 1 SCANMD Scan Mode Select. 12 1 ONCE The channel sequencer will cycle through all of the specified time slots once. 0 LOOP The channel sequencer will cycle through all of the specified time slots in a loop until SCANEN is cleared to 0. 1 DMAEN DMA Interface Enable . 14 1 DISABLED Disable the ADC module DMA interface. 0 ENABLED Enable the ADC module DMA interface. 1 BCLKSEL Burst Mode Clock Select. 15 1 LPOSC0 Burst mode uses the Low Power Oscillator. 0 APB Burst mode uses the APB clock. 1 CLKDIV SAR Clock Divider. 16 11 SCCIEN Single Conversion Complete Interrupt Enable. 27 1 DISABLED Disable the ADC single data conversion complete interrupt. 0 ENABLED Enable the ADC single data conversion complete interrupt. 1 SDIEN Scan Done Interrupt Enable. 28 1 DISABLED Disable the ADC scan complete interrupt. 0 ENABLED Enable the ADC scan complete interrupt. 1 FORIEN FIFO Overrun Interrupt Enable. 29 1 DISABLED Disable the data FIFO overrun interrupt. 0 ENABLED Enable the data FIFO overrun interrupt. 1 FURIEN FIFO Underrun Interrupt Enable. 30 1 DISABLED Disable the data FIFO underrun interrupt. 0 ENABLED Enable the data FIFO underrun interrupt. 1 CONTROL Measurement Control 0x10 0x1008F078 0xFFFFFFFF REFGNDSEL Reference Ground Select. 0 1 INTERNAL The internal device ground is used as the ground reference for ADC conversions. 0 EXTERNAL The VREFGND pin is used as the ground reference for ADC conversions. 1 CLKESEL Sampling Clock Edge Select. 1 1 RISING Select the rising edge of the APB clock. 0 FALLING Select the falling edge of the APB clock. 1 BMTK Burst Mode Tracking Time. 2 6 SCSEL Start-Of-Conversion Source Select. 8 4 ADCNT0 An ADC conversion triggers from the ADCnT0 ("On Demand" by writing 1 to ADBUSY) trigger source. 0 ADCNT1 An ADC conversion triggers from the ADCnT1 (Timer 0 Low Overflow) trigger source. 1 ADCNT2 An ADC conversion triggers from the ADCnT2 (Timer 0 High Overflow) trigger source. 2 ADCNT3 An ADC conversion triggers from the ADCnT3 (Timer 1 Low Overflow) trigger source. 3 ADCNT4 An ADC conversion triggers from the ADCnT4 (Timer 1 High Overflow) trigger source. 4 ADCNT5 An ADC conversion triggers from the ADCnT5 (EPCA0 synchronization pulse) trigger source. 5 ADCNT6 An ADC conversion triggers from the ADCnT6 (I2C0 Timer overflow) trigger source. 6 ADCNT7 An ADC conversion triggers from the ADCnT7 (I2C1 Timer overflow) trigger source. 7 ADCNT8 An ADC conversion triggers from the ADCnT8 (SSG phase defined by ADSP bits) trigger source. 8 ADCNT9 An ADC conversion triggers from the ADCnT9 (RESERVED) trigger source. 9 ADCNT10 An ADC conversion triggers from the ADCnT10 (RESERVED) trigger source. 10 ADCNT11 An ADC conversion triggers from the ADCnT11 (RESERVED) trigger source. 11 ADCNT12 An ADC conversion triggers from the ADCnT12 (RESERVED) trigger source. 12 ADCNT13 An ADC conversion triggers from the ADCnT13 (RESERVED) trigger source. 13 ADCNT14 An ADC conversion triggers from the ADCnT14 (RESERVED) trigger source. 14 ADCNT15 An ADC conversion triggers from the ADCnT15 (PB0.12) trigger source. 15 PWRTIME Burst Mode Power Up Time. 12 4 BURSTEN Burst Mode Enable. 16 1 DISABLED Disable burst mode. 0 ENABLED Enable burst mode. 1 ADCEN ADC Enable. 17 1 DISABLED Disable the ADC (low-power shutdown). 0 ENABLED Enable the ADC (active and ready for data conversions). 1 AD12BSSEL 12-Bit Mode Sample Select. 18 1 FOUR The ADC re-samples the input before each of the four conversions. 0 ONE The ADC samples once before the first conversion and converts four times. 1 VCMEN Common Mode Buffer Enable. 19 1 DISABLED Disable the common mode buffer. 0 ENABLED Enable the common mode buffer. 1 ACCMD Accumulation Mode. 21 1 ACCUMULATE Conversions will be accumulated for the specified number of cycles in burst mode according to the channel configuration. 0 REPEAT Conversions will not be accumulated in burst mode. 1 TRKMD ADC Tracking Mode. 22 1 NORMAL Normal Tracking Mode: When the ADC is enabled, a conversion begins immediately following the start-of-conversion signal. 0 DELAYED Delayed Tracking Mode: When the ADC is enabled, a conversion begins 3 SAR clock cycles following the start-of-conversion signal. The ADC is allowed to track during this time. 1 ADBUSY ADC Busy. 23 1 BIASSEL Bias Power Select. 24 2 MODE0 Select bias current mode 0. Recommended to use modes 1, 2, or 3. 0 MODE1 Select bias current mode 1 (SARCLK = 16 MHz). 1 MODE2 Select bias current mode 2. 2 MODE3 Select bias current mode 3 (SARCLK = 4 MHz). 3 LPMDEN Low Power Mode Enable. 26 1 DISABLED Disable low power mode. 0 ENABLED Enable low power mode (requires extended tracking time). 1 MREFLPEN MUX and VREF Low Power Enable. 27 1 DISABLED Disable low power mode. 0 ENABLED Enable low power mode (SAR clock <= 4 MHz). 1 VREFSEL Voltage Reference Select. 30 2 INTERNAL_VREF Select the internal, dedicated SARADC voltage reference as the ADC reference. 0 VDD Select the VDD pin as the ADC reference. 1 LDO_OUT Select the output of the internal LDO regulator (~1.8 V) as the ADC reference. 2 EXTERNAL_VREF Select the VREF pin as the ADC reference. This option is used for either an external VREF or the on-chip VREF driving out to the VREF pin. 3 SQ7654 Channel Sequencer Time Slots 4-7 Setup 0x20 0x00000000 0xFFFFFFFF TS4CHR Time Slot 4 Conversion Characteristic. 0 2 CC0 Select conversion characteristic 0 for time slot 4. 0 CC1 Select conversion characteristic 1 for time slot 4. 1 CC2 Select conversion characteristic 2 for time slot 4. 2 CC3 Select conversion characteristic 3 for time slot 4. 3 TS4MUX Time Slot 4 Input Channel. 2 5 ADCN0 Select channel ADCn.0 (PB0.6). 0 ADCN1 Select channel ADCn.1 (PB0.7). 1 ADCN2 Select channel ADCn.2 (RESERVED). 2 ADCN3 Select channel ADCn.3 (RESERVED). 3 ADCN4 Select channel ADCn.4 (RESERVED). 4 ADCN5 Select channel ADCn.5 (RESERVED). 5 ADCN6 Select channel ADCn.6 (RESERVED). 6 ADCN7 Select channel ADCn.7 (RESERVED). 7 ADCN8 Select channel ADCn.8 (PB0.0). 8 ADCN9 Select channel ADCn.9 (PB0.2). 9 ADCN10 Select channel ADCn.10 (PB0.3). 10 ADCN11 Select channel ADCn.11 (RESERVED). 11 ADCN12 Select channel ADCn.12 (RESERVED). 12 ADCN13 Select channel ADCn.13 (RESERVED). 13 ADCN14 Select channel ADCn.14 (PB0.8). 14 ADCN15 Select channel ADCn.15 (PB0.9). 15 ADCN16 Select channel ADCn.16 (IVC0.0 Output (IVC0C0)). 16 ADCN17 Select channel ADCn.17 (VSS). 17 ADCN18 Select channel ADCn.18 (1.8V Output of LDO). 18 ADCN19 Select channel ADCn.19 (VDD). 19 ADCN20 Select channel ADCn.20 (Temperature Sensor Output). 20 ADCN21 Select channel ADCn.21 (VIOHD / 4). 21 ADCN22 Select channel ADCn.22 (RESERVED). 22 ADCN23 Select channel ADCn.23 (RESERVED). 23 ADCN24 Select channel ADCn.24 (RESERVED). 24 ADCN25 Select channel ADCn.25 (RESERVED). 25 ADCN26 Select channel ADCn.26 (RESERVED). 26 ADCN27 Select channel ADCn.27 (RESERVED). 27 ADCN28 Select channel ADCn.28 (RESERVED). 28 ADCN29 Select channel ADCn.29 (RESERVED). 29 ADCN30 Select channel ADCn.30 (RESERVED). 30 END None - End the sequence. 31 TS5CHR Time Slot 5 Conversion Characteristic. 8 2 CC0 Select conversion characteristic 0 for time slot 5. 0 CC1 Select conversion characteristic 1 for time slot 5. 1 CC2 Select conversion characteristic 2 for time slot 5. 2 CC3 Select conversion characteristic 3 for time slot 5. 3 TS5MUX Time Slot 5 Input Channel. 10 5 ADCN0 Select channel ADCn.0 (PB0.6). 0 ADCN1 Select channel ADCn.1 (PB0.7). 1 ADCN2 Select channel ADCn.2 (RESERVED). 2 ADCN3 Select channel ADCn.3 (RESERVED). 3 ADCN4 Select channel ADCn.4 (RESERVED). 4 ADCN5 Select channel ADCn.5 (RESERVED). 5 ADCN6 Select channel ADCn.6 (RESERVED). 6 ADCN7 Select channel ADCn.7 (RESERVED). 7 ADCN8 Select channel ADCn.8 (PB0.0). 8 ADCN9 Select channel ADCn.9 (PB0.2). 9 ADCN10 Select channel ADCn.10 (PB0.3). 10 ADCN11 Select channel ADCn.11 (RESERVED). 11 ADCN12 Select channel ADCn.12 (RESERVED). 12 ADCN13 Select channel ADCn.13 (RESERVED). 13 ADCN14 Select channel ADCn.14 (PB0.8). 14 ADCN15 Select channel ADCn.15 (PB0.9). 15 ADCN16 Select channel ADCn.16 (IVC0.0 Output (IVC0C0)). 16 ADCN17 Select channel ADCn.17 (VSS). 17 ADCN18 Select channel ADCn.18 (1.8V Output of LDO). 18 ADCN19 Select channel ADCn.19 (VDD). 19 ADCN20 Select channel ADCn.20 (Temperature Sensor Output). 20 ADCN21 Select channel ADCn.21 (VIOHD / 4). 21 ADCN22 Select channel ADCn.22 (RESERVED). 22 ADCN23 Select channel ADCn.23 (RESERVED). 23 ADCN24 Select channel ADCn.24 (RESERVED). 24 ADCN25 Select channel ADCn.25 (RESERVED). 25 ADCN26 Select channel ADCn.26 (RESERVED). 26 ADCN27 Select channel ADCn.27 (RESERVED). 27 ADCN28 Select channel ADCn.28 (RESERVED). 28 ADCN29 Select channel ADCn.29 (RESERVED). 29 ADCN30 Select channel ADCn.30 (RESERVED). 30 END None - End the sequence. 31 TS6CHR Time Slot 6 Conversion Characteristic. 16 2 CC0 Select conversion characteristic 0 for time slot 6. 0 CC1 Select conversion characteristic 1 for time slot 6. 1 CC2 Select conversion characteristic 2 for time slot 6. 2 CC3 Select conversion characteristic 3 for time slot 6. 3 TS6MUX Time Slot 6 Input Channel. 18 5 ADCN0 Select channel ADCn.0 (PB0.6). 0 ADCN1 Select channel ADCn.1 (PB0.7). 1 ADCN2 Select channel ADCn.2 (RESERVED). 2 ADCN3 Select channel ADCn.3 (RESERVED). 3 ADCN4 Select channel ADCn.4 (RESERVED). 4 ADCN5 Select channel ADCn.5 (RESERVED). 5 ADCN6 Select channel ADCn.6 (RESERVED). 6 ADCN7 Select channel ADCn.7 (RESERVED). 7 ADCN8 Select channel ADCn.8 (PB0.0). 8 ADCN9 Select channel ADCn.9 (PB0.2). 9 ADCN10 Select channel ADCn.10 (PB0.3). 10 ADCN11 Select channel ADCn.11 (RESERVED). 11 ADCN12 Select channel ADCn.12 (RESERVED). 12 ADCN13 Select channel ADCn.13 (RESERVED). 13 ADCN14 Select channel ADCn.14 (PB0.8). 14 ADCN15 Select channel ADCn.15 (PB0.9). 15 ADCN16 Select channel ADCn.16 (IVC0.0 Output (IVC0C0)). 16 ADCN17 Select channel ADCn.17 (VSS). 17 ADCN18 Select channel ADCn.18 (1.8V Output of LDO). 18 ADCN19 Select channel ADCn.19 (VDD). 19 ADCN20 Select channel ADCn.20 (Temperature Sensor Output). 20 ADCN21 Select channel ADCn.21 (VIOHD / 4). 21 ADCN22 Select channel ADCn.22 (RESERVED). 22 ADCN23 Select channel ADCn.23 (RESERVED). 23 ADCN24 Select channel ADCn.24 (RESERVED). 24 ADCN25 Select channel ADCn.25 (RESERVED). 25 ADCN26 Select channel ADCn.26 (RESERVED). 26 ADCN27 Select channel ADCn.27 (RESERVED). 27 ADCN28 Select channel ADCn.28 (RESERVED). 28 ADCN29 Select channel ADCn.29 (RESERVED). 29 ADCN30 Select channel ADCn.30 (RESERVED). 30 END None - End the sequence. 31 TS7CHR Time Slot 7 Conversion Characteristic. 24 2 CC0 Select conversion characteristic 0 for time slot 7. 0 CC1 Select conversion characteristic 1 for time slot 7. 1 CC2 Select conversion characteristic 2 for time slot 7. 2 CC3 Select conversion characteristic 3 for time slot 7. 3 TS7MUX Time Slot 7 Input Channel. 26 5 ADCN0 Select channel ADCn.0 (PB0.6). 0 ADCN1 Select channel ADCn.1 (PB0.7). 1 ADCN2 Select channel ADCn.2 (RESERVED). 2 ADCN3 Select channel ADCn.3 (RESERVED). 3 ADCN4 Select channel ADCn.4 (RESERVED). 4 ADCN5 Select channel ADCn.5 (RESERVED). 5 ADCN6 Select channel ADCn.6 (RESERVED). 6 ADCN7 Select channel ADCn.7 (RESERVED). 7 ADCN8 Select channel ADCn.8 (PB0.0). 8 ADCN9 Select channel ADCn.9 (PB0.2). 9 ADCN10 Select channel ADCn.10 (PB0.3). 10 ADCN11 Select channel ADCn.11 (RESERVED). 11 ADCN12 Select channel ADCn.12 (RESERVED). 12 ADCN13 Select channel ADCn.13 (RESERVED). 13 ADCN14 Select channel ADCn.14 (PB0.8). 14 ADCN15 Select channel ADCn.15 (PB0.9). 15 ADCN16 Select channel ADCn.16 (IVC0.0 Output (IVC0C0)). 16 ADCN17 Select channel ADCn.17 (VSS). 17 ADCN18 Select channel ADCn.18 (1.8V Output of LDO). 18 ADCN19 Select channel ADCn.19 (VDD). 19 ADCN20 Select channel ADCn.20 (Temperature Sensor Output). 20 ADCN21 Select channel ADCn.21 (VIOHD / 4). 21 ADCN22 Select channel ADCn.22 (RESERVED). 22 ADCN23 Select channel ADCn.23 (RESERVED). 23 ADCN24 Select channel ADCn.24 (RESERVED). 24 ADCN25 Select channel ADCn.25 (RESERVED). 25 ADCN26 Select channel ADCn.26 (RESERVED). 26 ADCN27 Select channel ADCn.27 (RESERVED). 27 ADCN28 Select channel ADCn.28 (RESERVED). 28 ADCN29 Select channel ADCn.29 (RESERVED). 29 ADCN30 Select channel ADCn.30 (RESERVED). 30 END None - End the sequence. 31 SQ3210 Channel Sequencer Time Slots 0-3 Setup 0x30 0x00000000 0xFFFFFFFF TS0CHR Time Slot 0 Conversion Characteristic. 0 2 CC0 Select conversion characteristic 0 for time slot 0. 0 CC1 Select conversion characteristic 1 for time slot 0. 1 CC2 Select conversion characteristic 2 for time slot 0. 2 CC3 Select conversion characteristic 3 for time slot 0. 3 TS0MUX Time Slot 0 Input Channel. 2 5 ADCN0 Select channel ADCn.0 (PB0.6). 0 ADCN1 Select channel ADCn.1 (PB0.7). 1 ADCN2 Select channel ADCn.2 (RESERVED). 2 ADCN3 Select channel ADCn.3 (RESERVED). 3 ADCN4 Select channel ADCn.4 (RESERVED). 4 ADCN5 Select channel ADCn.5 (RESERVED). 5 ADCN6 Select channel ADCn.6 (RESERVED). 6 ADCN7 Select channel ADCn.7 (RESERVED). 7 ADCN8 Select channel ADCn.8 (PB0.0). 8 ADCN9 Select channel ADCn.9 (PB0.2). 9 ADCN10 Select channel ADCn.10 (PB0.3). 10 ADCN11 Select channel ADCn.11 (RESERVED). 11 ADCN12 Select channel ADCn.12 (RESERVED). 12 ADCN13 Select channel ADCn.13 (RESERVED). 13 ADCN14 Select channel ADCn.14 (PB0.8). 14 ADCN15 Select channel ADCn.15 (PB0.9). 15 ADCN16 Select channel ADCn.16 (IVC0.0 Output (IVC0C0)). 16 ADCN17 Select channel ADCn.17 (VSS). 17 ADCN18 Select channel ADCn.18 (1.8V Output of LDO). 18 ADCN19 Select channel ADCn.19 (VDD). 19 ADCN20 Select channel ADCn.20 (Temperature Sensor Output). 20 ADCN21 Select channel ADCn.21 (VIOHD / 4). 21 ADCN22 Select channel ADCn.22 (RESERVED). 22 ADCN23 Select channel ADCn.23 (RESERVED). 23 ADCN24 Select channel ADCn.24 (RESERVED). 24 ADCN25 Select channel ADCn.25 (RESERVED). 25 ADCN26 Select channel ADCn.26 (RESERVED). 26 ADCN27 Select channel ADCn.27 (RESERVED). 27 ADCN28 Select channel ADCn.28 (RESERVED). 28 ADCN29 Select channel ADCn.29 (RESERVED). 29 ADCN30 Select channel ADCn.30 (RESERVED). 30 END None - End the sequence. 31 TS1CHR Time Slot 1 Conversion Characteristic. 8 2 CC0 Select conversion characteristic 0 for time slot 1. 0 CC1 Select conversion characteristic 1 for time slot 1. 1 CC2 Select conversion characteristic 2 for time slot 1. 2 CC3 Select conversion characteristic 3 for time slot 1. 3 TS1MUX Time Slot 1 Input Channel. 10 5 ADCN0 Select channel ADCn.0 (PB0.6). 0 ADCN1 Select channel ADCn.1 (PB0.7). 1 ADCN2 Select channel ADCn.2 (RESERVED). 2 ADCN3 Select channel ADCn.3 (RESERVED). 3 ADCN4 Select channel ADCn.4 (RESERVED). 4 ADCN5 Select channel ADCn.5 (RESERVED). 5 ADCN6 Select channel ADCn.6 (RESERVED). 6 ADCN7 Select channel ADCn.7 (RESERVED). 7 ADCN8 Select channel ADCn.8 (PB0.0). 8 ADCN9 Select channel ADCn.9 (PB0.2). 9 ADCN10 Select channel ADCn.10 (PB0.3). 10 ADCN11 Select channel ADCn.11 (RESERVED). 11 ADCN12 Select channel ADCn.12 (RESERVED). 12 ADCN13 Select channel ADCn.13 (RESERVED). 13 ADCN14 Select channel ADCn.14 (PB0.8). 14 ADCN15 Select channel ADCn.15 (PB0.9). 15 ADCN16 Select channel ADCn.16 (IVC0.0 Output (IVC0C0)). 16 ADCN17 Select channel ADCn.17 (VSS). 17 ADCN18 Select channel ADCn.18 (1.8V Output of LDO). 18 ADCN19 Select channel ADCn.19 (VDD). 19 ADCN20 Select channel ADCn.20 (Temperature Sensor Output). 20 ADCN21 Select channel ADCn.21 (VIOHD / 4). 21 ADCN22 Select channel ADCn.22 (RESERVED). 22 ADCN23 Select channel ADCn.23 (RESERVED). 23 ADCN24 Select channel ADCn.24 (RESERVED). 24 ADCN25 Select channel ADCn.25 (RESERVED). 25 ADCN26 Select channel ADCn.26 (RESERVED). 26 ADCN27 Select channel ADCn.27 (RESERVED). 27 ADCN28 Select channel ADCn.28 (RESERVED). 28 ADCN29 Select channel ADCn.29 (RESERVED). 29 ADCN30 Select channel ADCn.30 (RESERVED). 30 END None - End the sequence. 31 TS2CHR Time Slot 2 Conversion Characteristic. 16 2 CC0 Select conversion characteristic 0 for time slot 2. 0 CC1 Select conversion characteristic 1 for time slot 2. 1 CC2 Select conversion characteristic 2 for time slot 2. 2 CC3 Select conversion characteristic 3 for time slot 2. 3 TS2MUX Time Slot 2 Input Channel. 18 5 ADCN0 Select channel ADCn.0 (PB0.6). 0 ADCN1 Select channel ADCn.1 (PB0.7). 1 ADCN2 Select channel ADCn.2 (RESERVED). 2 ADCN3 Select channel ADCn.3 (RESERVED). 3 ADCN4 Select channel ADCn.4 (RESERVED). 4 ADCN5 Select channel ADCn.5 (RESERVED). 5 ADCN6 Select channel ADCn.6 (RESERVED). 6 ADCN7 Select channel ADCn.7 (RESERVED). 7 ADCN8 Select channel ADCn.8 (PB0.0). 8 ADCN9 Select channel ADCn.9 (PB0.2). 9 ADCN10 Select channel ADCn.10 (PB0.3). 10 ADCN11 Select channel ADCn.11 (RESERVED). 11 ADCN12 Select channel ADCn.12 (RESERVED). 12 ADCN13 Select channel ADCn.13 (RESERVED). 13 ADCN14 Select channel ADCn.14 (PB0.8). 14 ADCN15 Select channel ADCn.15 (PB0.9). 15 ADCN16 Select channel ADCn.16 (IVC0.0 Output (IVC0C0)). 16 ADCN17 Select channel ADCn.17 (VSS). 17 ADCN18 Select channel ADCn.18 (1.8V Output of LDO). 18 ADCN19 Select channel ADCn.19 (VDD). 19 ADCN20 Select channel ADCn.20 (Temperature Sensor Output). 20 ADCN21 Select channel ADCn.21 (VIOHD / 4). 21 ADCN22 Select channel ADCn.22 (RESERVED). 22 ADCN23 Select channel ADCn.23 (RESERVED). 23 ADCN24 Select channel ADCn.24 (RESERVED). 24 ADCN25 Select channel ADCn.25 (RESERVED). 25 ADCN26 Select channel ADCn.26 (RESERVED). 26 ADCN27 Select channel ADCn.27 (RESERVED). 27 ADCN28 Select channel ADCn.28 (RESERVED). 28 ADCN29 Select channel ADCn.29 (RESERVED). 29 ADCN30 Select channel ADCn.30 (RESERVED). 30 END None - End the sequence. 31 TS3CHR Time Slot 3 Conversion Characteristic. 24 2 CC0 Select conversion characteristic 0 for time slot 3. 0 CC1 Select conversion characteristic 1 for time slot 3. 1 CC2 Select conversion characteristic 2 for time slot 3. 2 CC3 Select conversion characteristic 3 for time slot 3. 3 TS3MUX Time Slot 3 Input Channel. 26 5 ADCN0 Select channel ADCn.0 (PB0.6). 0 ADCN1 Select channel ADCn.1 (PB0.7). 1 ADCN2 Select channel ADCn.2 (RESERVED). 2 ADCN3 Select channel ADCn.3 (RESERVED). 3 ADCN4 Select channel ADCn.4 (RESERVED). 4 ADCN5 Select channel ADCn.5 (RESERVED). 5 ADCN6 Select channel ADCn.6 (RESERVED). 6 ADCN7 Select channel ADCn.7 (RESERVED). 7 ADCN8 Select channel ADCn.8 (PB0.0). 8 ADCN9 Select channel ADCn.9 (PB0.2). 9 ADCN10 Select channel ADCn.10 (PB0.3). 10 ADCN11 Select channel ADCn.11 (RESERVED). 11 ADCN12 Select channel ADCn.12 (RESERVED). 12 ADCN13 Select channel ADCn.13 (RESERVED). 13 ADCN14 Select channel ADCn.14 (PB0.8). 14 ADCN15 Select channel ADCn.15 (PB0.9). 15 ADCN16 Select channel ADCn.16 (IVC0.0 Output (IVC0C0)). 16 ADCN17 Select channel ADCn.17 (VSS). 17 ADCN18 Select channel ADCn.18 (1.8V Output of LDO). 18 ADCN19 Select channel ADCn.19 (VDD). 19 ADCN20 Select channel ADCn.20 (Temperature Sensor Output). 20 ADCN21 Select channel ADCn.21 (VIOHD / 4). 21 ADCN22 Select channel ADCn.22 (RESERVED). 22 ADCN23 Select channel ADCn.23 (RESERVED). 23 ADCN24 Select channel ADCn.24 (RESERVED). 24 ADCN25 Select channel ADCn.25 (RESERVED). 25 ADCN26 Select channel ADCn.26 (RESERVED). 26 ADCN27 Select channel ADCn.27 (RESERVED). 27 ADCN28 Select channel ADCn.28 (RESERVED). 28 ADCN29 Select channel ADCn.29 (RESERVED). 29 ADCN30 Select channel ADCn.30 (RESERVED). 30 END None - End the sequence. 31 CHAR32 Conversion Characteristic 2 and 3 Setup 0x40 0x00000000 0xFFFFFFFF CHR2GN Conversion Characteristic 2 Gain. 0 1 UNITY The on-chip PGA gain is 1. 0 HALF The on-chip PGA gain is 0.5. 1 CHR2RPT Conversion Characteristic 2 Repeat Counter. 1 3 ACC1 Accumulate one sample. 0 ACC4 Accumulate four samples. 1 ACC8 Accumulate eight samples. 2 ACC16 Accumulate sixteen samples. 3 ACC32 Accumulate thirty-two samples (10-bit mode only). 4 ACC64 Accumulate sixty-four samples (10-bit mode only). 5 CHR2LS Conversion Characteristic 2 Left-Shift Bits. 4 3 CHR2RSEL Conversion Characteristic 2 Resolution Selection. 7 1 B10 Select 10-bit Mode. 0 B12 Select 12-bit Mode (burst mode must be enabled). 1 CHR2WCIEN Conversion Characteristic 2 Window Comparator Interrupt Enable. 8 1 DISABLED Disable window comparison interrupts. 0 ENABLED Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic. 1 CHR3GN Conversion Characteristic 3 Gain. 16 1 UNITY The on-chip PGA gain is 1. 0 HALF The on-chip PGA gain is 0.5. 1 CHR3RPT Conversion Characteristic 3 Repeat Counter. 17 3 ACC1 Accumulate one sample. 0 ACC4 Accumulate four samples. 1 ACC8 Accumulate eight samples. 2 ACC16 Accumulate sixteen samples. 3 ACC32 Accumulate thirty-two samples (10-bit mode only). 4 ACC64 Accumulate sixty-four samples (10-bit mode only). 5 CHR3LS Conversion Characteristic 3 Left-Shift Bits. 20 3 CHR3RSEL Conversion Characteristic 3 Resolution Selection. 23 1 B10 Select 10-bit Mode. 0 B12 Select 12-bit Mode (burst mode must be enabled). 1 CHR3WCIEN Conversion Characteristic 3 Window Comparator Interrupt Enable. 24 1 DISABLED Disable window comparison interrupts. 0 ENABLED Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic. 1 CHAR10 Conversion Characteristic 0 and 1 Setup 0x50 0x00000000 0xFFFFFFFF CHR0GN Conversion Characteristic 0 Gain. 0 1 UNITY The on-chip PGA gain is 1. 0 HALF The on-chip PGA gain is 0.5. 1 CHR0RPT Conversion Characteristic 0 Repeat Counter. 1 3 ACC1 Accumulate one sample. 0 ACC4 Accumulate four samples. 1 ACC8 Accumulate eight samples. 2 ACC16 Accumulate sixteen samples. 3 ACC32 Accumulate thirty-two samples (10-bit mode only). 4 ACC64 Accumulate sixty-four samples (10-bit mode only). 5 CHR0LS Conversion Characteristic 0 Left-Shift Bits. 4 3 CHR0RSEL Conversion Characteristic 0 Resolution Selection. 7 1 B10 Select 10-bit Mode. 0 B12 Select 12-bit Mode (burst mode must be enabled). 1 CHR0WCIEN Conversion Characteristic 0 Window Comparator Interrupt Enable. 8 1 DISABLED Disable window comparison interrupts. 0 ENABLED Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic. 1 CHR1GN Conversion Characteristic 1 Gain. 16 1 UNITY The on-chip PGA gain is 1. 0 HALF The on-chip PGA gain is 0.5. 1 CHR1RPT Conversion Characteristic 1 Repeat Counter. 17 3 ACC1 Accumulate one sample. 0 ACC4 Accumulate four samples. 1 ACC8 Accumulate eight samples. 2 ACC16 Accumulate sixteen samples. 3 ACC32 Accumulate thirty-two samples (10-bit mode only). 4 ACC64 Accumulate sixty-four samples (10-bit mode only). 5 CHR1LS Conversion Characteristic 1 Left-Shift Bits. 20 3 CHR1RSEL Conversion Characteristic 1 Resolution Selection. 23 1 B10 Select 10-bit Mode. 0 B12 Select 12-bit Mode (burst mode must be enabled). 1 CHR1WCIEN Conversion Characteristic 1 Window Comparator Interrupt Enable. 24 1 DISABLED Disable window comparison interrupts. 0 ENABLED Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic. 1 DATA Output Data Word 0x60 0x00000000 0xFFFFFFFF DATA Output Data Word. 0 32 read-only WCLIMITS Window Comparator Limits 0x70 0x00000000 0xFFFFFFFF WCLT Less-Than Window Comparator Limit. 0 16 WCGT Greater-Than Window Comparator Limit. 16 16 ACC Accumulator Initial Value 0x80 0x00000000 0xFFFFFFFF ACC Accumulator Initial Value. 0 16 write-only STATUS Module Status 0x90 0x00000000 0xFFFFFFFF WCI Window Compare Interrupt. 0 1 NOT_SET Read: A window compare interrupt has not occurred. Write: Clear the interrupt. 0 SET Read: A window compare interrupt occurred. Write: Force a window compare interrupt. 1 SCCI Single Conversion Complete Interrupt. 1 1 NOT_SET Read: A single data conversion interrupt has not occurred. Write: Clear the interrupt. 0 SET Read: A single data conversion interrupt occurred. Write: Force a single data conversion interrupt. 1 SDI Scan Done Interrupt. 2 1 NOT_SET Read: A scan done interrupt has not occurred. Write: Clear the interrupt. 0 SET Read: A scan done interrupt occurred. Write: Force a scan done interrupt. 1 FORI FIFO Overrun Interrupt. 3 1 NOT_SET Read: A data FIFO overrun interrupt has not occurred. Write: Clear the interrupt. 0 SET Read: A data FIFO overrun interrupt occurred. Write: Force a data FIFO overrun interrupt. 1 FURI FIFO Underrun Interrupt. 4 1 NOT_SET Read: A data FIFO underrun interrupt has not occurred. Write: Clear the interrupt. 0 SET Read: A data FIFO underrun interrupt occurred. Write: Force a data FIFO underrun interrupt. 1 FIFOSTATUS FIFO Status 0xa0 0x00000010 0xFFFFFFFF FIFOLVL FIFO Level. 0 4 read-only DPSTS Data Packing Status. 4 1 read-only LOWER The next ADC conversion will be written to the lower half-word. 0 UPPER The next ADC conversion will be written to the upper half-word. 1 DRDYF Data Ready Flag. 5 1 read-only NOT_SET New data is not produced yet. 0 SET New data is ready. 1 SARADC_1 A None ADC 0x4001b000 0x0 0xffc registers SARADC1_IRQn 36 CONFIG Module Configuration 0x0 0x00000000 0xFFFFFFFF SPSEL Sampling Phase Select. 0 4 PHASE0 The ADC samples at SSG phase 0. 0 PHASE1 The ADC samples at SSG phase 1. 1 PHASE2 The ADC samples at SSG phase 2. 2 PHASE3 The ADC samples at SSG phase 3. 3 PHASE4 The ADC samples at SSG phase 4. 4 PHASE5 The ADC samples at SSG phase 5. 5 PHASE6 The ADC samples at SSG phase 6. 6 PHASE7 The ADC samples at SSG phase 7. 7 PHASE8 The ADC samples at SSG phase 8. 8 PHASE9 The ADC samples at SSG phase 9. 9 PHASE10 The ADC samples at SSG phase 10. 10 PHASE11 The ADC samples at SSG phase 11. 11 PHASE12 The ADC samples at SSG phase 12. 12 PHASE13 The ADC samples at SSG phase 13. 13 PHASE14 The ADC samples at SSG phase 14. 14 PHASE15 The ADC samples at SSG phase 15. 15 SPEN Sampling Phase Enable. 4 1 DISABLED Disable Phase Select. The ADC will always sample on the start-of-conversion trigger selected by the SCSEL field. 0 ENABLED Enable Phase Select. The ADC will sample according to the phase selected by the SPSEL field. 1 SSGEN Synchronous Sample Generator Enable. 5 1 DISABLED Disable the SAR clock output to SSG. 0 ENABLED The ADC is the SSG master, and the SAR clock will be output to the SSG block. 1 PACKMD Output Packing Mode. 6 2 UPPER_ONLY Data is written to the upper half-word and the lower half-word is filled with 0's. An SCI interrupt is triggered when data is written, if enabled. 0 LOWER_ONLY Data is written to the lower half-word, and the upper half-word is filled with 0's. An SCI interrupt is triggered when data is written, if enabled. 1 UPPER_FIRST Two data words are packed into the register with the upper half-word representing the earlier data, and the lower half-word representing the later data. If SIMCEN is set to 1, the upper half-word represents data from the master ADC (selected by SSGEN) and the lower half-word represents data from the slave ADC. The ADC write to the lower half-word will trigger the SCI interrupt, if enabled. 2 LOWER_FIRST Two data words are packed into the register with the lower half-word representing the earlier data, and the upper half-word representing the later data. If SIMCEN is set to 1, the lower half-word represents data from the master ADC (selected by SSGEN) and the upper half-word represents data from the slave ADC. The ADC write to the upper half-word will trigger the SCI interrupt, if enabled. 3 SIMCEN Simultaneous Conversion Packing Enable. 8 1 DISABLED Disable simultaneous mode conversion packing. 0 ENABLED Enable simultaneous mode conversion packing. 1 INTLVEN Interleaved Conversion Packing Enable. 9 1 DISABLED Disable interleaved mode conversion packing. 0 ENABLED Enable interleaved mode conversion packing. 1 SCANEN Scan Mode Enable. 10 1 DISABLED Disable ADC scan mode. 0 ENABLED Enable ADC scan mode. The ADC will scan through the defined time slots in sequence on every start of conversion. 1 SCANMD Scan Mode Select. 12 1 ONCE The channel sequencer will cycle through all of the specified time slots once. 0 LOOP The channel sequencer will cycle through all of the specified time slots in a loop until SCANEN is cleared to 0. 1 DMAEN DMA Interface Enable . 14 1 DISABLED Disable the ADC module DMA interface. 0 ENABLED Enable the ADC module DMA interface. 1 BCLKSEL Burst Mode Clock Select. 15 1 LPOSC0 Burst mode uses the Low Power Oscillator. 0 APB Burst mode uses the APB clock. 1 CLKDIV SAR Clock Divider. 16 11 SCCIEN Single Conversion Complete Interrupt Enable. 27 1 DISABLED Disable the ADC single data conversion complete interrupt. 0 ENABLED Enable the ADC single data conversion complete interrupt. 1 SDIEN Scan Done Interrupt Enable. 28 1 DISABLED Disable the ADC scan complete interrupt. 0 ENABLED Enable the ADC scan complete interrupt. 1 FORIEN FIFO Overrun Interrupt Enable. 29 1 DISABLED Disable the data FIFO overrun interrupt. 0 ENABLED Enable the data FIFO overrun interrupt. 1 FURIEN FIFO Underrun Interrupt Enable. 30 1 DISABLED Disable the data FIFO underrun interrupt. 0 ENABLED Enable the data FIFO underrun interrupt. 1 CONTROL Measurement Control 0x10 0x1008F078 0xFFFFFFFF REFGNDSEL Reference Ground Select. 0 1 INTERNAL The internal device ground is used as the ground reference for ADC conversions. 0 EXTERNAL The VREFGND pin is used as the ground reference for ADC conversions. 1 CLKESEL Sampling Clock Edge Select. 1 1 RISING Select the rising edge of the APB clock. 0 FALLING Select the falling edge of the APB clock. 1 BMTK Burst Mode Tracking Time. 2 6 SCSEL Start-Of-Conversion Source Select. 8 4 ADCNT0 An ADC conversion triggers from the ADCnT0 ("On Demand" by writing 1 to ADBUSY) trigger source. 0 ADCNT1 An ADC conversion triggers from the ADCnT1 (Timer 0 Low Overflow) trigger source. 1 ADCNT2 An ADC conversion triggers from the ADCnT2 (Timer 0 High Overflow) trigger source. 2 ADCNT3 An ADC conversion triggers from the ADCnT3 (Timer 1 Low Overflow) trigger source. 3 ADCNT4 An ADC conversion triggers from the ADCnT4 (Timer 1 High Overflow) trigger source. 4 ADCNT5 An ADC conversion triggers from the ADCnT5 (EPCA0 synchronization pulse) trigger source. 5 ADCNT6 An ADC conversion triggers from the ADCnT6 (I2C0 Timer overflow) trigger source. 6 ADCNT7 An ADC conversion triggers from the ADCnT7 (I2C1 Timer overflow) trigger source. 7 ADCNT8 An ADC conversion triggers from the ADCnT8 (SSG phase defined by ADSP bits) trigger source. 8 ADCNT9 An ADC conversion triggers from the ADCnT9 (RESERVED) trigger source. 9 ADCNT10 An ADC conversion triggers from the ADCnT10 (RESERVED) trigger source. 10 ADCNT11 An ADC conversion triggers from the ADCnT11 (RESERVED) trigger source. 11 ADCNT12 An ADC conversion triggers from the ADCnT12 (RESERVED) trigger source. 12 ADCNT13 An ADC conversion triggers from the ADCnT13 (RESERVED) trigger source. 13 ADCNT14 An ADC conversion triggers from the ADCnT14 (RESERVED) trigger source. 14 ADCNT15 An ADC conversion triggers from the ADCnT15 (PB0.13) trigger source. 15 PWRTIME Burst Mode Power Up Time. 12 4 BURSTEN Burst Mode Enable. 16 1 DISABLED Disable burst mode. 0 ENABLED Enable burst mode. 1 ADCEN ADC Enable. 17 1 DISABLED Disable the ADC (low-power shutdown). 0 ENABLED Enable the ADC (active and ready for data conversions). 1 AD12BSSEL 12-Bit Mode Sample Select. 18 1 FOUR The ADC re-samples the input before each of the four conversions. 0 ONE The ADC samples once before the first conversion and converts four times. 1 VCMEN Common Mode Buffer Enable. 19 1 DISABLED Disable the common mode buffer. 0 ENABLED Enable the common mode buffer. 1 ACCMD Accumulation Mode. 21 1 ACCUMULATE Conversions will be accumulated for the specified number of cycles in burst mode according to the channel configuration. 0 REPEAT Conversions will not be accumulated in burst mode. 1 TRKMD ADC Tracking Mode. 22 1 NORMAL Normal Tracking Mode: When the ADC is enabled, a conversion begins immediately following the start-of-conversion signal. 0 DELAYED Delayed Tracking Mode: When the ADC is enabled, a conversion begins 3 SAR clock cycles following the start-of-conversion signal. The ADC is allowed to track during this time. 1 ADBUSY ADC Busy. 23 1 BIASSEL Bias Power Select. 24 2 MODE0 Select bias current mode 0. Recommended to use modes 1, 2, or 3. 0 MODE1 Select bias current mode 1 (SARCLK = 16 MHz). 1 MODE2 Select bias current mode 2. 2 MODE3 Select bias current mode 3 (SARCLK = 4 MHz). 3 LPMDEN Low Power Mode Enable. 26 1 DISABLED Disable low power mode. 0 ENABLED Enable low power mode (requires extended tracking time). 1 MREFLPEN MUX and VREF Low Power Enable. 27 1 DISABLED Disable low power mode. 0 ENABLED Enable low power mode (SAR clock <= 4 MHz). 1 VREFSEL Voltage Reference Select. 30 2 INTERNAL_VREF Select the internal, dedicated SARADC voltage reference as the ADC reference. 0 VDD Select the VDD pin as the ADC reference. 1 LDO_OUT Select the output of the internal LDO regulator (~1.8 V) as the ADC reference. 2 EXTERNAL_VREF Select the VREF pin as the ADC reference. This option is used for either an external VREF or the on-chip VREF driving out to the VREF pin. 3 SQ7654 Channel Sequencer Time Slots 4-7 Setup 0x20 0x00000000 0xFFFFFFFF TS4CHR Time Slot 4 Conversion Characteristic. 0 2 CC0 Select conversion characteristic 0 for time slot 4. 0 CC1 Select conversion characteristic 1 for time slot 4. 1 CC2 Select conversion characteristic 2 for time slot 4. 2 CC3 Select conversion characteristic 3 for time slot 4. 3 TS4MUX Time Slot 4 Input Channel. 2 5 ADCN0 Select channel ADCn.0 (PB1.1). 0 ADCN1 Select channel ADCn.1 (PB1.0). 1 ADCN2 Select channel ADCn.2 (PB0.15). 2 ADCN3 Select channel ADCn.3 (PB0.14). 3 ADCN4 Select channel ADCn.4 (PB0.13). 4 ADCN5 Select channel ADCn.5 (PB0.12). 5 ADCN6 Select channel ADCn.6 (PB0.4). 6 ADCN7 Select channel ADCn.7 (PB0.11). 7 ADCN8 Select channel ADCn.8 (PB0.10). 8 ADCN9 Select channel ADCn.9 (RESERVED). 9 ADCN10 Select channel ADCn.10 (RESERVED). 10 ADCN11 Select channel ADCn.11 (RESERVED). 11 ADCN12 Select channel ADCn.12 (RESERVED). 12 ADCN13 Select channel ADCn.13 (RESERVED). 13 ADCN14 Select channel ADCn.14 (PB0.8). 14 ADCN15 Select channel ADCn.15 (PB0.9). 15 ADCN16 Select channel ADCn.16 (IVC0.1 Output (IVC0C1)). 16 ADCN17 Select channel ADCn.17 (Voltage at VREGIN / 4). 17 ADCN18 Select channel ADCn.18 (EXTVREG0 Current Sense). 18 ADCN19 Select channel ADCn.19 (VIO). 19 ADCN20 Select channel ADCn.20 (Temperature Sensor Output). 20 ADCN21 Select channel ADCn.21 (VIOHD / 4). 21 ADCN22 Select channel ADCn.22 (RESERVED). 22 ADCN23 Select channel ADCn.23 (RESERVED). 23 ADCN24 Select channel ADCn.24 (RESERVED). 24 ADCN25 Select channel ADCn.25 (RESERVED). 25 ADCN26 Select channel ADCn.26 (RESERVED). 26 ADCN27 Select channel ADCn.27 (RESERVED). 27 ADCN28 Select channel ADCn.28 (RESERVED). 28 ADCN29 Select channel ADCn.29 (RESERVED). 29 ADCN30 Select channel ADCn.30 (RESERVED). 30 END None - End the sequence. 31 TS5CHR Time Slot 5 Conversion Characteristic. 8 2 CC0 Select conversion characteristic 0 for time slot 5. 0 CC1 Select conversion characteristic 1 for time slot 5. 1 CC2 Select conversion characteristic 2 for time slot 5. 2 CC3 Select conversion characteristic 3 for time slot 5. 3 TS5MUX Time Slot 5 Input Channel. 10 5 ADCN0 Select channel ADCn.0 (PB1.1). 0 ADCN1 Select channel ADCn.1 (PB1.0). 1 ADCN2 Select channel ADCn.2 (PB0.15). 2 ADCN3 Select channel ADCn.3 (PB0.14). 3 ADCN4 Select channel ADCn.4 (PB0.13). 4 ADCN5 Select channel ADCn.5 (PB0.12). 5 ADCN6 Select channel ADCn.6 (PB0.4). 6 ADCN7 Select channel ADCn.7 (PB0.11). 7 ADCN8 Select channel ADCn.8 (PB0.10). 8 ADCN9 Select channel ADCn.9 (RESERVED). 9 ADCN10 Select channel ADCn.10 (RESERVED). 10 ADCN11 Select channel ADCn.11 (RESERVED). 11 ADCN12 Select channel ADCn.12 (RESERVED). 12 ADCN13 Select channel ADCn.13 (RESERVED). 13 ADCN14 Select channel ADCn.14 (PB0.8). 14 ADCN15 Select channel ADCn.15 (PB0.9). 15 ADCN16 Select channel ADCn.16 (IVC0.1 Output (IVC0C1)). 16 ADCN17 Select channel ADCn.17 (Voltage at VREGIN / 4). 17 ADCN18 Select channel ADCn.18 (EXTVREG0 Current Sense). 18 ADCN19 Select channel ADCn.19 (VIO). 19 ADCN20 Select channel ADCn.20 (Temperature Sensor Output). 20 ADCN21 Select channel ADCn.21 (VIOHD / 4). 21 ADCN22 Select channel ADCn.22 (RESERVED). 22 ADCN23 Select channel ADCn.23 (RESERVED). 23 ADCN24 Select channel ADCn.24 (RESERVED). 24 ADCN25 Select channel ADCn.25 (RESERVED). 25 ADCN26 Select channel ADCn.26 (RESERVED). 26 ADCN27 Select channel ADCn.27 (RESERVED). 27 ADCN28 Select channel ADCn.28 (RESERVED). 28 ADCN29 Select channel ADCn.29 (RESERVED). 29 ADCN30 Select channel ADCn.30 (RESERVED). 30 END None - End the sequence. 31 TS6CHR Time Slot 6 Conversion Characteristic. 16 2 CC0 Select conversion characteristic 0 for time slot 6. 0 CC1 Select conversion characteristic 1 for time slot 6. 1 CC2 Select conversion characteristic 2 for time slot 6. 2 CC3 Select conversion characteristic 3 for time slot 6. 3 TS6MUX Time Slot 6 Input Channel. 18 5 ADCN0 Select channel ADCn.0 (PB1.1). 0 ADCN1 Select channel ADCn.1 (PB1.0). 1 ADCN2 Select channel ADCn.2 (PB0.15). 2 ADCN3 Select channel ADCn.3 (PB0.14). 3 ADCN4 Select channel ADCn.4 (PB0.13). 4 ADCN5 Select channel ADCn.5 (PB0.12). 5 ADCN6 Select channel ADCn.6 (PB0.4). 6 ADCN7 Select channel ADCn.7 (PB0.11). 7 ADCN8 Select channel ADCn.8 (PB0.10). 8 ADCN9 Select channel ADCn.9 (RESERVED). 9 ADCN10 Select channel ADCn.10 (RESERVED). 10 ADCN11 Select channel ADCn.11 (RESERVED). 11 ADCN12 Select channel ADCn.12 (RESERVED). 12 ADCN13 Select channel ADCn.13 (RESERVED). 13 ADCN14 Select channel ADCn.14 (PB0.8). 14 ADCN15 Select channel ADCn.15 (PB0.9). 15 ADCN16 Select channel ADCn.16 (IVC0.1 Output (IVC0C1)). 16 ADCN17 Select channel ADCn.17 (Voltage at VREGIN / 4). 17 ADCN18 Select channel ADCn.18 (EXTVREG0 Current Sense). 18 ADCN19 Select channel ADCn.19 (VIO). 19 ADCN20 Select channel ADCn.20 (Temperature Sensor Output). 20 ADCN21 Select channel ADCn.21 (VIOHD / 4). 21 ADCN22 Select channel ADCn.22 (RESERVED). 22 ADCN23 Select channel ADCn.23 (RESERVED). 23 ADCN24 Select channel ADCn.24 (RESERVED). 24 ADCN25 Select channel ADCn.25 (RESERVED). 25 ADCN26 Select channel ADCn.26 (RESERVED). 26 ADCN27 Select channel ADCn.27 (RESERVED). 27 ADCN28 Select channel ADCn.28 (RESERVED). 28 ADCN29 Select channel ADCn.29 (RESERVED). 29 ADCN30 Select channel ADCn.30 (RESERVED). 30 END None - End the sequence. 31 TS7CHR Time Slot 7 Conversion Characteristic. 24 2 CC0 Select conversion characteristic 0 for time slot 7. 0 CC1 Select conversion characteristic 1 for time slot 7. 1 CC2 Select conversion characteristic 2 for time slot 7. 2 CC3 Select conversion characteristic 3 for time slot 7. 3 TS7MUX Time Slot 7 Input Channel. 26 5 ADCN0 Select channel ADCn.0 (PB1.1). 0 ADCN1 Select channel ADCn.1 (PB1.0). 1 ADCN2 Select channel ADCn.2 (PB0.15). 2 ADCN3 Select channel ADCn.3 (PB0.14). 3 ADCN4 Select channel ADCn.4 (PB0.13). 4 ADCN5 Select channel ADCn.5 (PB0.12). 5 ADCN6 Select channel ADCn.6 (PB0.4). 6 ADCN7 Select channel ADCn.7 (PB0.11). 7 ADCN8 Select channel ADCn.8 (PB0.10). 8 ADCN9 Select channel ADCn.9 (RESERVED). 9 ADCN10 Select channel ADCn.10 (RESERVED). 10 ADCN11 Select channel ADCn.11 (RESERVED). 11 ADCN12 Select channel ADCn.12 (RESERVED). 12 ADCN13 Select channel ADCn.13 (RESERVED). 13 ADCN14 Select channel ADCn.14 (PB0.8). 14 ADCN15 Select channel ADCn.15 (PB0.9). 15 ADCN16 Select channel ADCn.16 (IVC0.1 Output (IVC0C1)). 16 ADCN17 Select channel ADCn.17 (Voltage at VREGIN / 4). 17 ADCN18 Select channel ADCn.18 (EXTVREG0 Current Sense). 18 ADCN19 Select channel ADCn.19 (VIO). 19 ADCN20 Select channel ADCn.20 (Temperature Sensor Output). 20 ADCN21 Select channel ADCn.21 (VIOHD / 4). 21 ADCN22 Select channel ADCn.22 (RESERVED). 22 ADCN23 Select channel ADCn.23 (RESERVED). 23 ADCN24 Select channel ADCn.24 (RESERVED). 24 ADCN25 Select channel ADCn.25 (RESERVED). 25 ADCN26 Select channel ADCn.26 (RESERVED). 26 ADCN27 Select channel ADCn.27 (RESERVED). 27 ADCN28 Select channel ADCn.28 (RESERVED). 28 ADCN29 Select channel ADCn.29 (RESERVED). 29 ADCN30 Select channel ADCn.30 (RESERVED). 30 END None - End the sequence. 31 SQ3210 Channel Sequencer Time Slots 0-3 Setup 0x30 0x00000000 0xFFFFFFFF TS0CHR Time Slot 0 Conversion Characteristic. 0 2 CC0 Select conversion characteristic 0 for time slot 0. 0 CC1 Select conversion characteristic 1 for time slot 0. 1 CC2 Select conversion characteristic 2 for time slot 0. 2 CC3 Select conversion characteristic 3 for time slot 0. 3 TS0MUX Time Slot 0 Input Channel. 2 5 ADCN0 Select channel ADCn.0 (PB1.1). 0 ADCN1 Select channel ADCn.1 (PB1.0). 1 ADCN2 Select channel ADCn.2 (PB0.15). 2 ADCN3 Select channel ADCn.3 (PB0.14). 3 ADCN4 Select channel ADCn.4 (PB0.13). 4 ADCN5 Select channel ADCn.5 (PB0.12). 5 ADCN6 Select channel ADCn.6 (PB0.4). 6 ADCN7 Select channel ADCn.7 (PB0.11). 7 ADCN8 Select channel ADCn.8 (PB0.10). 8 ADCN9 Select channel ADCn.9 (RESERVED). 9 ADCN10 Select channel ADCn.10 (RESERVED). 10 ADCN11 Select channel ADCn.11 (RESERVED). 11 ADCN12 Select channel ADCn.12 (RESERVED). 12 ADCN13 Select channel ADCn.13 (RESERVED). 13 ADCN14 Select channel ADCn.14 (PB0.8). 14 ADCN15 Select channel ADCn.15 (PB0.9). 15 ADCN16 Select channel ADCn.16 (IVC0.1 Output (IVC0C1)). 16 ADCN17 Select channel ADCn.17 (Voltage at VREGIN / 4). 17 ADCN18 Select channel ADCn.18 (EXTVREG0 Current Sense). 18 ADCN19 Select channel ADCn.19 (VIO). 19 ADCN20 Select channel ADCn.20 (Temperature Sensor Output). 20 ADCN21 Select channel ADCn.21 (VIOHD / 4). 21 ADCN22 Select channel ADCn.22 (RESERVED). 22 ADCN23 Select channel ADCn.23 (RESERVED). 23 ADCN24 Select channel ADCn.24 (RESERVED). 24 ADCN25 Select channel ADCn.25 (RESERVED). 25 ADCN26 Select channel ADCn.26 (RESERVED). 26 ADCN27 Select channel ADCn.27 (RESERVED). 27 ADCN28 Select channel ADCn.28 (RESERVED). 28 ADCN29 Select channel ADCn.29 (RESERVED). 29 ADCN30 Select channel ADCn.30 (RESERVED). 30 END None - End the sequence. 31 TS1CHR Time Slot 1 Conversion Characteristic. 8 2 CC0 Select conversion characteristic 0 for time slot 1. 0 CC1 Select conversion characteristic 1 for time slot 1. 1 CC2 Select conversion characteristic 2 for time slot 1. 2 CC3 Select conversion characteristic 3 for time slot 1. 3 TS1MUX Time Slot 1 Input Channel. 10 5 ADCN0 Select channel ADCn.0 (PB1.1). 0 ADCN1 Select channel ADCn.1 (PB1.0). 1 ADCN2 Select channel ADCn.2 (PB0.15). 2 ADCN3 Select channel ADCn.3 (PB0.14). 3 ADCN4 Select channel ADCn.4 (PB0.13). 4 ADCN5 Select channel ADCn.5 (PB0.12). 5 ADCN6 Select channel ADCn.6 (PB0.4). 6 ADCN7 Select channel ADCn.7 (PB0.11). 7 ADCN8 Select channel ADCn.8 (PB0.10). 8 ADCN9 Select channel ADCn.9 (RESERVED). 9 ADCN10 Select channel ADCn.10 (RESERVED). 10 ADCN11 Select channel ADCn.11 (RESERVED). 11 ADCN12 Select channel ADCn.12 (RESERVED). 12 ADCN13 Select channel ADCn.13 (RESERVED). 13 ADCN14 Select channel ADCn.14 (PB0.8). 14 ADCN15 Select channel ADCn.15 (PB0.9). 15 ADCN16 Select channel ADCn.16 (IVC0.1 Output (IVC0C1)). 16 ADCN17 Select channel ADCn.17 (Voltage at VREGIN / 4). 17 ADCN18 Select channel ADCn.18 (EXTVREG0 Current Sense). 18 ADCN19 Select channel ADCn.19 (VIO). 19 ADCN20 Select channel ADCn.20 (Temperature Sensor Output). 20 ADCN21 Select channel ADCn.21 (VIOHD / 4). 21 ADCN22 Select channel ADCn.22 (RESERVED). 22 ADCN23 Select channel ADCn.23 (RESERVED). 23 ADCN24 Select channel ADCn.24 (RESERVED). 24 ADCN25 Select channel ADCn.25 (RESERVED). 25 ADCN26 Select channel ADCn.26 (RESERVED). 26 ADCN27 Select channel ADCn.27 (RESERVED). 27 ADCN28 Select channel ADCn.28 (RESERVED). 28 ADCN29 Select channel ADCn.29 (RESERVED). 29 ADCN30 Select channel ADCn.30 (RESERVED). 30 END None - End the sequence. 31 TS2CHR Time Slot 2 Conversion Characteristic. 16 2 CC0 Select conversion characteristic 0 for time slot 2. 0 CC1 Select conversion characteristic 1 for time slot 2. 1 CC2 Select conversion characteristic 2 for time slot 2. 2 CC3 Select conversion characteristic 3 for time slot 2. 3 TS2MUX Time Slot 2 Input Channel. 18 5 ADCN0 Select channel ADCn.0 (PB1.1). 0 ADCN1 Select channel ADCn.1 (PB1.0). 1 ADCN2 Select channel ADCn.2 (PB0.15). 2 ADCN3 Select channel ADCn.3 (PB0.14). 3 ADCN4 Select channel ADCn.4 (PB0.13). 4 ADCN5 Select channel ADCn.5 (PB0.12). 5 ADCN6 Select channel ADCn.6 (PB0.4). 6 ADCN7 Select channel ADCn.7 (PB0.11). 7 ADCN8 Select channel ADCn.8 (PB0.10). 8 ADCN9 Select channel ADCn.9 (RESERVED). 9 ADCN10 Select channel ADCn.10 (RESERVED). 10 ADCN11 Select channel ADCn.11 (RESERVED). 11 ADCN12 Select channel ADCn.12 (RESERVED). 12 ADCN13 Select channel ADCn.13 (RESERVED). 13 ADCN14 Select channel ADCn.14 (PB0.8). 14 ADCN15 Select channel ADCn.15 (PB0.9). 15 ADCN16 Select channel ADCn.16 (IVC0.1 Output (IVC0C1)). 16 ADCN17 Select channel ADCn.17 (Voltage at VREGIN / 4). 17 ADCN18 Select channel ADCn.18 (EXTVREG0 Current Sense). 18 ADCN19 Select channel ADCn.19 (VIO). 19 ADCN20 Select channel ADCn.20 (Temperature Sensor Output). 20 ADCN21 Select channel ADCn.21 (VIOHD / 4). 21 ADCN22 Select channel ADCn.22 (RESERVED). 22 ADCN23 Select channel ADCn.23 (RESERVED). 23 ADCN24 Select channel ADCn.24 (RESERVED). 24 ADCN25 Select channel ADCn.25 (RESERVED). 25 ADCN26 Select channel ADCn.26 (RESERVED). 26 ADCN27 Select channel ADCn.27 (RESERVED). 27 ADCN28 Select channel ADCn.28 (RESERVED). 28 ADCN29 Select channel ADCn.29 (RESERVED). 29 ADCN30 Select channel ADCn.30 (RESERVED). 30 END None - End the sequence. 31 TS3CHR Time Slot 3 Conversion Characteristic. 24 2 CC0 Select conversion characteristic 0 for time slot 3. 0 CC1 Select conversion characteristic 1 for time slot 3. 1 CC2 Select conversion characteristic 2 for time slot 3. 2 CC3 Select conversion characteristic 3 for time slot 3. 3 TS3MUX Time Slot 3 Input Channel. 26 5 ADCN0 Select channel ADCn.0 (PB1.1). 0 ADCN1 Select channel ADCn.1 (PB1.0). 1 ADCN2 Select channel ADCn.2 (PB0.15). 2 ADCN3 Select channel ADCn.3 (PB0.14). 3 ADCN4 Select channel ADCn.4 (PB0.13). 4 ADCN5 Select channel ADCn.5 (PB0.12). 5 ADCN6 Select channel ADCn.6 (PB0.4). 6 ADCN7 Select channel ADCn.7 (PB0.11). 7 ADCN8 Select channel ADCn.8 (PB0.10). 8 ADCN9 Select channel ADCn.9 (RESERVED). 9 ADCN10 Select channel ADCn.10 (RESERVED). 10 ADCN11 Select channel ADCn.11 (RESERVED). 11 ADCN12 Select channel ADCn.12 (RESERVED). 12 ADCN13 Select channel ADCn.13 (RESERVED). 13 ADCN14 Select channel ADCn.14 (PB0.8). 14 ADCN15 Select channel ADCn.15 (PB0.9). 15 ADCN16 Select channel ADCn.16 (IVC0.1 Output (IVC0C1)). 16 ADCN17 Select channel ADCn.17 (Voltage at VREGIN / 4). 17 ADCN18 Select channel ADCn.18 (EXTVREG0 Current Sense). 18 ADCN19 Select channel ADCn.19 (VIO). 19 ADCN20 Select channel ADCn.20 (Temperature Sensor Output). 20 ADCN21 Select channel ADCn.21 (VIOHD / 4). 21 ADCN22 Select channel ADCn.22 (RESERVED). 22 ADCN23 Select channel ADCn.23 (RESERVED). 23 ADCN24 Select channel ADCn.24 (RESERVED). 24 ADCN25 Select channel ADCn.25 (RESERVED). 25 ADCN26 Select channel ADCn.26 (RESERVED). 26 ADCN27 Select channel ADCn.27 (RESERVED). 27 ADCN28 Select channel ADCn.28 (RESERVED). 28 ADCN29 Select channel ADCn.29 (RESERVED). 29 ADCN30 Select channel ADCn.30 (RESERVED). 30 END None - End the sequence. 31 CHAR32 Conversion Characteristic 2 and 3 Setup 0x40 0x00000000 0xFFFFFFFF CHR2GN Conversion Characteristic 2 Gain. 0 1 UNITY The on-chip PGA gain is 1. 0 HALF The on-chip PGA gain is 0.5. 1 CHR2RPT Conversion Characteristic 2 Repeat Counter. 1 3 ACC1 Accumulate one sample. 0 ACC4 Accumulate four samples. 1 ACC8 Accumulate eight samples. 2 ACC16 Accumulate sixteen samples. 3 ACC32 Accumulate thirty-two samples (10-bit mode only). 4 ACC64 Accumulate sixty-four samples (10-bit mode only). 5 CHR2LS Conversion Characteristic 2 Left-Shift Bits. 4 3 CHR2RSEL Conversion Characteristic 2 Resolution Selection. 7 1 B10 Select 10-bit Mode. 0 B12 Select 12-bit Mode (burst mode must be enabled). 1 CHR2WCIEN Conversion Characteristic 2 Window Comparator Interrupt Enable. 8 1 DISABLED Disable window comparison interrupts. 0 ENABLED Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic. 1 CHR3GN Conversion Characteristic 3 Gain. 16 1 UNITY The on-chip PGA gain is 1. 0 HALF The on-chip PGA gain is 0.5. 1 CHR3RPT Conversion Characteristic 3 Repeat Counter. 17 3 ACC1 Accumulate one sample. 0 ACC4 Accumulate four samples. 1 ACC8 Accumulate eight samples. 2 ACC16 Accumulate sixteen samples. 3 ACC32 Accumulate thirty-two samples (10-bit mode only). 4 ACC64 Accumulate sixty-four samples (10-bit mode only). 5 CHR3LS Conversion Characteristic 3 Left-Shift Bits. 20 3 CHR3RSEL Conversion Characteristic 3 Resolution Selection. 23 1 B10 Select 10-bit Mode. 0 B12 Select 12-bit Mode (burst mode must be enabled). 1 CHR3WCIEN Conversion Characteristic 3 Window Comparator Interrupt Enable. 24 1 DISABLED Disable window comparison interrupts. 0 ENABLED Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic. 1 CHAR10 Conversion Characteristic 0 and 1 Setup 0x50 0x00000000 0xFFFFFFFF CHR0GN Conversion Characteristic 0 Gain. 0 1 UNITY The on-chip PGA gain is 1. 0 HALF The on-chip PGA gain is 0.5. 1 CHR0RPT Conversion Characteristic 0 Repeat Counter. 1 3 ACC1 Accumulate one sample. 0 ACC4 Accumulate four samples. 1 ACC8 Accumulate eight samples. 2 ACC16 Accumulate sixteen samples. 3 ACC32 Accumulate thirty-two samples (10-bit mode only). 4 ACC64 Accumulate sixty-four samples (10-bit mode only). 5 CHR0LS Conversion Characteristic 0 Left-Shift Bits. 4 3 CHR0RSEL Conversion Characteristic 0 Resolution Selection. 7 1 B10 Select 10-bit Mode. 0 B12 Select 12-bit Mode (burst mode must be enabled). 1 CHR0WCIEN Conversion Characteristic 0 Window Comparator Interrupt Enable. 8 1 DISABLED Disable window comparison interrupts. 0 ENABLED Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic. 1 CHR1GN Conversion Characteristic 1 Gain. 16 1 UNITY The on-chip PGA gain is 1. 0 HALF The on-chip PGA gain is 0.5. 1 CHR1RPT Conversion Characteristic 1 Repeat Counter. 17 3 ACC1 Accumulate one sample. 0 ACC4 Accumulate four samples. 1 ACC8 Accumulate eight samples. 2 ACC16 Accumulate sixteen samples. 3 ACC32 Accumulate thirty-two samples (10-bit mode only). 4 ACC64 Accumulate sixty-four samples (10-bit mode only). 5 CHR1LS Conversion Characteristic 1 Left-Shift Bits. 20 3 CHR1RSEL Conversion Characteristic 1 Resolution Selection. 23 1 B10 Select 10-bit Mode. 0 B12 Select 12-bit Mode (burst mode must be enabled). 1 CHR1WCIEN Conversion Characteristic 1 Window Comparator Interrupt Enable. 24 1 DISABLED Disable window comparison interrupts. 0 ENABLED Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic. 1 DATA Output Data Word 0x60 0x00000000 0xFFFFFFFF DATA Output Data Word. 0 32 read-only WCLIMITS Window Comparator Limits 0x70 0x00000000 0xFFFFFFFF WCLT Less-Than Window Comparator Limit. 0 16 WCGT Greater-Than Window Comparator Limit. 16 16 ACC Accumulator Initial Value 0x80 0x00000000 0xFFFFFFFF ACC Accumulator Initial Value. 0 16 write-only STATUS Module Status 0x90 0x00000000 0xFFFFFFFF WCI Window Compare Interrupt. 0 1 NOT_SET Read: A window compare interrupt has not occurred. Write: Clear the interrupt. 0 SET Read: A window compare interrupt occurred. Write: Force a window compare interrupt. 1 SCCI Single Conversion Complete Interrupt. 1 1 NOT_SET Read: A single data conversion interrupt has not occurred. Write: Clear the interrupt. 0 SET Read: A single data conversion interrupt occurred. Write: Force a single data conversion interrupt. 1 SDI Scan Done Interrupt. 2 1 NOT_SET Read: A scan done interrupt has not occurred. Write: Clear the interrupt. 0 SET Read: A scan done interrupt occurred. Write: Force a scan done interrupt. 1 FORI FIFO Overrun Interrupt. 3 1 NOT_SET Read: A data FIFO overrun interrupt has not occurred. Write: Clear the interrupt. 0 SET Read: A data FIFO overrun interrupt occurred. Write: Force a data FIFO overrun interrupt. 1 FURI FIFO Underrun Interrupt. 4 1 NOT_SET Read: A data FIFO underrun interrupt has not occurred. Write: Clear the interrupt. 0 SET Read: A data FIFO underrun interrupt occurred. Write: Force a data FIFO underrun interrupt. 1 FIFOSTATUS FIFO Status 0xa0 0x00000010 0xFFFFFFFF FIFOLVL FIFO Level. 0 4 read-only DPSTS Data Packing Status. 4 1 read-only LOWER The next ADC conversion will be written to the lower half-word. 0 UPPER The next ADC conversion will be written to the upper half-word. 1 DRDYF Data Ready Flag. 5 1 read-only NOT_SET New data is not produced yet. 0 SET New data is ready. 1 AES_0 A None AES_0 0x40027000 0x0 0xffc registers AES0_IRQn 42 CONTROL Module Control 0x0 0x80000000 0xFFFFFFFF XFRSTA AES Transfer Start. 0 1 START Start the AES operation. 1 KEYCPEN Key Capture Enable. 1 1 DISABLED Disable key capture. 0 ENABLED Enable key capture. 1 EDMD Encryption/Decryption Mode. 2 1 DECRYPT AES module performs a decryption operation 0 ENCRYPT AES module performs an encryption operation. 1 SWMDEN Software Mode Enable. 8 1 DISABLED Disable software mode. 0 ENABLED Enable software mode. 1 BEN Bypass AES Operation Enable. 9 1 DISABLED Do not bypass AES operations. 0 ENABLED Bypass AES operations. 1 XOREN XOR Enable. 10 2 XOR_DISABLED Disable the XOR paths. 0 XOR_INPUT Enable the XOR input path, disable the XOR output path. 1 XOR_OUTPUT Disable the XOR input path, enable the XOR output path. 2 HCTREN Hardware Counter Mode Enable. 12 1 DISABLED Disable hardware counter mode. 0 ENABLED Enable hardware counter mode. 1 HCBCEN Hardware Cipher-Block Chaining Mode Enable. 13 1 DISABLED Disable hardware cipher-block chaining (CBC) mode. 0 ENABLED Enable hardware cipher-block chaining (CBC) mode. 1 KEYSIZE Keystore Size Select. 16 2 KEY128 Key is composed of 128 bits. 0 KEY192 Key is composed of 192 bits. 1 KEY256 Key is composed of 256 bits. 2 ERRIEN Error Interrupt Enable. 24 1 DISABLED Disable the error interrupt. 0 ENABLED Enable the error interrupt. 1 OCIEN Operation Complete Interrupt Enable. 25 1 DISABLED Disable the operation complete interrupt. 0 ENABLED Enable the operation complete interrupt. 1 DBGMD AES Debug Mode. 30 1 HALT A debug breakpoint will cause the AES module to halt. 0 RUN The AES module will continue to operate while the core is halted in debug mode. 1 RESET Module Soft Reset. 31 1 INACTIVE AES module is not in soft reset. 0 ACTIVE AES module is in soft reset and none of the module bits can be accessed. 1 XFRSIZE Number of Blocks 0x10 0x00000000 0xFFFFFFFF XFRSIZE Transfer Size. 0 11 DATAFIFO Input/Output Data FIFO Access 0x20 0x00000000 0xFFFFFFFF modifyExternal DATAFIFO Input/Output Data FIFO Access. 0 32 XORFIFO XOR Data FIFO Access 0x30 0x00000000 0xFFFFFFFF modifyExternal XORFIFO XOR Data FIFO Access. 0 32 HWKEY0 Hardware Key Word 0 0x40 0x00000000 0xFFFFFFFF HWKEY0 Hardware Key Word 0. 0 32 HWKEY1 Hardware Key Word 1 0x50 0x00000000 0xFFFFFFFF HWKEY1 Hardware Key Word 1. 0 32 HWKEY2 Hardware Key Word 2 0x60 0x00000000 0xFFFFFFFF HWKEY2 Hardware Key Word 2. 0 32 HWKEY3 Hardware Key Word 3 0x70 0x00000000 0xFFFFFFFF HWKEY3 Hardware Key Word 3. 0 32 HWKEY4 Hardware Key Word 4 0x80 0x00000000 0xFFFFFFFF HWKEY4 Hardware Key Word 4. 0 32 HWKEY5 Hardware Key Word 5 0x90 0x00000000 0xFFFFFFFF HWKEY5 Hardware Key Word 5. 0 32 HWKEY6 Hardware Key Word 6 0xa0 0x00000000 0xFFFFFFFF HWKEY6 Hardware Key Word 6. 0 32 HWKEY7 Hardware Key Word 7 0xb0 0x00000000 0xFFFFFFFF HWKEY7 Hardware Key Word 7. 0 32 HWCTR0 Hardware Counter Word 0 0xc0 0x00000000 0xFFFFFFFF HWCTR0 Hardware Counter Word 0. 0 32 HWCTR1 Hardware Counter Word 1 0xd0 0x00000000 0xFFFFFFFF HWCTR1 Hardware Counter Word 1. 0 32 HWCTR2 Hardware Counter Word 2 0xe0 0x00000000 0xFFFFFFFF HWCTR2 Hardware Counter Word 2. 0 32 HWCTR3 Hardware Counter Word 3 0xf0 0x00000000 0xFFFFFFFF HWCTR3 Hardware Counter Word 3. 0 32 STATUS Module Status 0x100 0x00000000 0xFFFFFFFF DURF Input/Output Data FIFO Underrun Flag. 0 1 read-only NOT_SET No input/output data FIFO underrun. 0 SET An input/output data FIFO underrun has occurred. 1 DORF Input/Output Data FIFO Overrun Flag. 1 1 read-only NOT_SET No input/output data FIFO overrun. 0 SET An input/output data FIFO overrun has occurred. 1 XORF XOR Data FIFO Overrun Flag. 2 1 read-only NOT_SET No XOR data FIFO overrun. 0 SET An XOR data FIFO overrun has occurred. 1 DFIFOLVL Input/Output Data FIFO Level. 4 3 read-only EMPTY Input/Output data FIFO is empty. 0 1WORD Input/Output data FIFO contains 1 word. 1 2WORDS Input/Output data FIFO contains 2 words. 2 3WORDS Input/Output data FIFO contains 3 words. 3 FULL Input/Output data FIFO contains 4 words (full). 4 XFIFOLVL XOR Data FIFO Level. 8 3 read-only EMPTY XOR data FIFO is empty. 0 1WORD XOR data FIFO contains 1 word. 1 2WORDS XOR data FIFO contains 2 words. 2 3WORDS XOR data FIFO contains 3 words. 3 FULL XOR data FIFO contains 4 words (full). 4 BUSYF Module Busy Flag. 16 1 read-only NOT_SET AES module is not busy. 0 SET AES module is completing an operation. 1 ERRI Error Interrupt Flag. 30 1 NOT_SET AES error interrupt has not occurred. 0 SET AES error interrupt has occurred. 1 OCI Operation Complete Interrupt Flag. 31 1 NOT_SET AES operation complete interrupt has not occurred. 0 SET AES operation complete interrupt occurred. 1 CRC_0 A None CRC_0 0x40028000 0x0 0xffc registers CONTROL Module Control 0x0 0x00000000 0xFFFFFFFF SINITEN Seed Initialization Enable. 0 1 write-only DISABLED Do not initialize the CRC module to the value set by the SEED bit. 0 ENABLED Initialize the CRC module to the value set by the SEED bit. 1 SEED Seed Setting. 1 1 write-only ALL_ZEROES CRC seed value is all 0's (0x00000000) 0 ALL_ONES CRC seed value is all 1's (0xFFFFFFFF). 1 CRCEN CRC Enable. 2 1 DISABLED Disable CRC operations. 0 ENABLED Enable CRC operations. 1 POLYSEL Polynomial Selection. 4 2 CRC_32_04C11DB7 Select 32-bit polynomial: 0x04C11DB7. 0 CRC_16_1021 Select 16-bit polynomial: 0x1021. 1 CRC_16_3D65 Select 16-bit polynomial: 0x3D65. 2 CRC_16_8005 Select 16-bit polynomial: 0x8005. 3 BMDEN Byte Mode Enable. 8 1 DISABLED Disable byte mode (word/byte width is determined automatically by the hardware). 0 ENABLED Enable byte mode (all writes are considered as bytes). 1 BBREN Byte-Level Bit Reversal Enable. 9 1 DISABLED No byte-level bit reversal (input is same order as written). 0 ENABLED Byte-level bit reversal enabled (the bits in each byte are reversed). 1 ORDER Input Processing Order. 10 2 NO_REORDER No byte reorientation (output is same order as input). 0 BIG_ENDIAN_16 Swap for 16-bit big endian order (input: B3 B2 B1 B0, output: B2 B3 B0 B1). 1 BIG_ENDIAN_32 Swap for 32-bit big endian order (input: B3 B2 B1 B0, output: B0 B1 B2 B3). 2 DATA Input/Result Data 0x10 0xFFFFFFFF 0xFFFFFFFF modifyExternal DATA Input/Result Data. 0 32 RDATA Bit-Reversed Output Data 0x20 0xFFFFFFFF 0xFFFFFFFF RDATA Bit-Reversed Output Data. 0 32 read-only CAPSENSE_0 A None CAPSENSE_0 0x40023000 0x0 0xffc registers CAPSENSE0_IRQn 39 CONTROL Module Control 0x0 0x00000040 0xFFFFFFFF BUSYF Start and Busy Flag. 0 1 IDLE Read: A capacitive sensing conversion is complete or a conversion is not currently in progress. Write: No effect. 0 BUSY Read: A capacitive sensing conversion is in progress. Write: Initiate a capacitive sensing conversion if BUSYF is selected as the start of conversion source. 1 CSEN Module Enable. 1 1 DISABLED Disable the capacitive sensing module. 0 ENABLED Enable the capacitive sensing module. 1 BIASEN Bias Enable. 2 1 DISABLED Disable the bias. 0 ENABLED Enable the bias. 1 CMPPOL Digital Comparator Polarity Select. 3 1 GT The digital comparator generates an interrupt if the conversion is greater than the CSTH threshold. 0 LTE The digital comparator generates an interrupt if the conversion is less than or equal to the CSTH threshold. 1 CMD Conversion Mode Select. 4 2 SINGLE Single Conversion Mode: One conversion occurs on a single channel. 0 SCAN Single Scan Mode: One conversion on each channel selected by SCANEN occurs. An end-of-scan interrupt indicates all channels have been measured. 1 CONT_SINGLE Continuous Single Conversion Mode: Continuously converts on a single channel. This operation ends only if the module is disabled (CSEN = 0) or if a compare threshold event occurs (CMPI = 1). 2 CONT_SCAN Continuous Scan Mode: Continuously loops through and converts on all the channels selected by SCANEN. This operation ends only if the module is disabled (CSEN = 0) or if a compare threshold event occurs (CMPI = 1). 3 CNVR Conversion Rate. 6 2 12BIT Conversions last 12 internal CAPSENSE clocks and results are 12 bits in length. 0 13BIT Conversions last 13 internal CAPSENSE clocks and results are 13 bits in length. 1 14BIT Conversions last 14 internal CAPSENSE clocks and results are 14 bits in length. 2 16BIT Conversions last 16 internal CAPSENSE clocks and results are 16 bits in length. 3 ACCMD Accumulator Mode Select. 8 3 ACC_1 Accumulate 1 sample. 0 ACC_4 Accumulate 4 samples. 1 ACC_8 Accumulate 8 samples. 2 ACC_16 Accumulate 16 samples. 3 ACC_32 Accumulate 32 samples. 4 ACC_64 Accumulate 64 samples. 5 MCEN Multiple Channel Enable. 11 1 DISABLED Disable the multiple channel measurement feature. 0 ENABLED Enable the multiple channel measurement feature. 1 CSCM Start of Conversion Mode Select. 12 4 CSNT0 The CSnT0 ("On Demand" by writing 1 to CSBUSY) trigger source starts conversions. 0 CSNT1 The CSnT1 (Timer 0 Low Overflow) trigger source starts conversions. 1 CSNT2 The CSnT2 (Timer 0 High Overflow) trigger source starts conversions. 2 CSNT3 The CSnT3 (Timer 1 Low Overflow) trigger source starts conversions. 3 CSNT4 The CSnT4 (Timer 1 High Overflow) trigger source starts conversions. 4 CSNT5 The CSnT5 (I2C0 Timer Byte 1 Overflow) trigger source starts conversions. 5 CSNT6 The CSnT6 (I2C0 Timer Byte 3 Overflow) trigger source starts conversions. 6 CSNT7 The CSnT7 (I2C1 Timer Byte 1 Overflow) trigger source starts conversions. 7 CSNT8 The CSnT8 (I2C1 Timer Byte 3 Overflow) trigger source starts conversions. 8 CSNT9 The CSnT9 (RESERVED) trigger source starts conversions. 9 CSNT10 The CSnT10 (RESERVED) trigger source starts conversions. 10 CSNT11 The CSnT11 (RESERVED) trigger source starts conversions. 11 CSNT12 The CSnT12 (RESERVED) trigger source starts conversions. 12 CSNT13 The CSnT13 (RESERVED) trigger source starts conversions. 13 CSNT14 The CSnT14 (RESERVED) trigger source starts conversions. 14 CSNT15 The CSnT15 (RESERVED) trigger source starts conversions. 15 PMMD Pin Monitor Mode. 16 2 ALWAYS_RETRY Always retry on a pin state change. 0 RETRY_TWICE Retry up to twice on consecutive bit cycles. 1 RETRY_FOUR_TIMES Retry up to four times on consecutive bit cycles. 2 DO_NOT_RETRY Ignore monitored signal state change. 3 PMEF Pin Monitor Event Flag. 18 1 NOT_SET A retry did not occur due to a pin monitor event during the last conversion. 0 SET A retry occurred due to a pin monitor event during the last conversion. 1 CMPEN Threshold Comparator Enable. 20 1 DISABLED Disable the threshold comparator. 0 ENABLED Enable the threshold comparator. 1 CDIEN Conversion Done Interrupt Enable. 21 1 DISABLED Disable the single conversion done interrupt. 0 ENABLED Enable the single conversion done interrupt. 1 EOSIEN End-of-Scan Interrupt Enable. 22 1 DISABLED Disable the single scan end-of-scan interrupt. 0 ENABLED Enable the single scan end-of-scan interrupt. 1 CMPI Threshold Comparator Interrupt Flag. 24 1 read-only NOT_SET The capacitive sensing result did not cause a compare threshold interrupt. 0 SET The capacitive sensing result caused a compare threshold interrupt. 1 CDI Conversion Done Interrupt Flag. 25 1 NOT_SET Read: The CAPSENSEn module has not completed a data conversion since the last time CDI was cleared. Write: Clear the interrupt. 0 SET Read: The CAPSENSEn module completed a data conversion. Write: Force a conversion complete interrupt. 1 EOSI End-of-Scan Interrupt Flag. 26 1 read-only NOT_SET The CAPSENSEn module has not completed a scan since the last time EOSI was cleared. 0 SET The CAPSENSEn module completed a scan. 1 MODE Measurement Mode 0x10 0x00000007 0xFFFFFFFF CGSEL Capacitance Gain Select. 0 3 DRSEL Double Reset Select. 4 2 RAMPSEL Ramp Selection. 6 2 IASEL Output Current Select. 8 3 DTSEL Discharge Time Select. 12 3 LPFSEL Low Pass Filter Select. 16 3 DATA Measurement Data 0x20 0x00000000 0xFFFFFFFF DATA Capacitive Sensing Data. 0 16 SCAN Channel Scan Enable 0x30 0x00000000 0xFFFFFFFF SCANEN Channel Scan Enable. 0 16 CSTH Compare Threshold 0x40 0x00000000 0xFFFFFFFF CSTH Compare Threshold. 0 16 MUX Mux Channel Select 0x50 0x00000080 0xFFFFFFFF CSMX Mux Channel Select. 0 4 CSN0 Select CSn.0 (PB0.2). 0 CSN1 Select CSn.1 (PB0.3). 1 CSN2 Select CSn.2 (PB0.4). 2 CSN3 Select CSn.3 (PB0.6). 3 CSN4 Select CSn.4 (PB0.7). 4 CSN5 Select CSn.5 (RESERVED). 5 CSN6 Select CSn.6 (RESERVED). 6 CSN7 Select CSn.7 (PB0.0). 7 CSN8 Select CSn.8 (RESERVED). 8 CSN9 Select CSn.9 (RESERVED). 9 CSN10 Select CSn.10 (PB0.12). 10 CSN11 Select CSn.11 (PB0.13). 11 CSN12 Select CSn.12 (PB0.14). 12 CSN13 Select CSn.13 (PB0.15). 13 CSN14 Select CSn.14 (PB1.0). 14 CSN15 Select CSn.15 (PB1.1). 15 CSDISC Channel Disconnect. 7 1 CONNECT Connect the capacitive sensing circuit to the selected channel. 0 DISCONNECT Disconnect the capacitive sensing input channel. 1 CLKCTRL_0 A None CLKCTRL_0 0x4002d000 0x0 0xffc registers CONTROL Module Control 0x0 0x10000000 0xFFFFFFFF AHBSEL AHB Clock Source Select. 0 3 LPOSC0 AHB clock source is the Low-Power Oscillator. 0 LFOSC0 AHB clock source is the Low-Frequency Oscillator. 1 RTC0OSC AHB clock source is the RTC Oscillator. 2 EXTOSC0 AHB clock source is the External Oscillator. 3 PLL0OSC AHB clock source is the PLL. 5 LPOSC0_DIV AHB clock source is a divided version of the Low-Power Oscillator. 6 AHBDIV AHB Clock Divider. 8 3 DIV1 AHB clock divided by 1. 0 DIV2 AHB clock divided by 2. 1 DIV4 AHB clock divided by 4. 2 DIV8 AHB clock divided by 8. 3 DIV16 AHB clock divided by 16. 4 DIV32 AHB clock divided by 32. 5 DIV64 AHB clock divided by 64. 6 DIV128 AHB clock divided by 128. 7 APBDIV APB Clock Divider. 16 1 DIV1 APB clock is the same as the AHB clock (divided by 1). 0 DIV2 APB clock is the AHB clock divided by 2. 1 EXTESEL External Clock Edge Select. 28 1 BOTH_EDGES External clock generated by both rising and falling edges of the external oscillator. 0 RISING_ONLY External clock generated by only rising edges of the external oscillator. 1 OBUSYF Oscillators Busy Flag. 29 1 read-only NOT_SET AHB and APB oscillators are not busy. 0 SET AHB and APB oscillators are busy and the AHBSEL, AHBDIV, and APBDIV fields should not be modified. 1 AHBCLKG AHB Clock Gate 0x10 0x00000005 0xFFFFFFFF RAMCEN RAM Clock Enable. 0 1 DISABLED Disable the AHB clock to the RAM. 0 ENABLED Enable the AHB clock to the RAM (default). 1 DMACEN DMA Controller Clock Enable. 1 1 DISABLED Disable the AHB clock to the DMA Controller (default). 0 ENABLED Enable the AHB clock to the DMA Controller. 1 FLASHCEN Flash Clock Enable. 2 1 DISABLED Disable the AHB clock to the Flash. 0 ENABLED Enable the AHB clock to the Flash (default). 1 EMIF0CEN EMIF Clock Enable. 3 1 DISABLED Disable the AHB clock to the External Memory Interface (EMIF) (default). 0 ENABLED Enable the AHB clock to the External Memory Interface (EMIF). 1 APBCLKG0 APB Clock Gate 0 0x20 0x00000000 0xFFFFFFFF PLL0CEN PLL Module Clock Enable. 0 1 DISABLED Disable the APB clock to the PLL0 registers (default). 0 ENABLED Enable the APB clock to the PLL0 registers. 1 PB0CEN Port Bank Module Clock Enable. 1 1 DISABLED Disable the APB clock to the Port Bank Modules (default). 0 ENABLED Enable the APB clock to the Port Bank Modules. 1 USART0CEN USART0 Module Clock Enable. 2 1 DISABLED Disable the APB clock to the USART0 Module (default). 0 ENABLED Enable the APB clock to the USART0 Module. 1 USART1CEN USART1 Module Clock Enable. 3 1 DISABLED Disable the APB clock to the USART1 Module (default). 0 ENABLED Enable the APB clock to the USART1 Module. 1 UART0CEN UART0 Module Clock Enable. 4 1 DISABLED Disable the APB clock to the UART0 Module (default). 0 ENABLED Enable the APB clock to the UART0 Module. 1 UART1CEN UART1 Module Clock Enable. 5 1 DISABLED Disable the APB clock to the UART1 Module (default). 0 ENABLED Enable the APB clock to the UART1 Module. 1 SPI0CEN SPI0 Module Clock Enable. 6 1 DISABLED Disable the APB clock to the SPI0 Module (default). 0 ENABLED Enable the APB clock to the SPI0 Module. 1 SPI1CEN SPI1 Module Clock Enable. 7 1 DISABLED Disable the APB clock to the SPI1 Module (default). 0 ENABLED Enable the APB clock to the SPI1 Module. 1 SPI2CEN SPI2 Module Clock Enable. 8 1 DISABLED Disable the APB clock to the SPI2 Module (default). 0 ENABLED Enable the APB clock to the SPI2 Module. 1 I2C0CEN I2C0 Module Clock Enable. 9 1 DISABLED Disable the APB clock to the I2C0 Module (default). 0 ENABLED Enable the APB clock to the I2C0 Module. 1 I2C1CEN I2C1 Module Clock Enable. 10 1 DISABLED Disable the APB clock to the I2C1 Module (default). 0 ENABLED Enable the APB clock to the I2C1 Module. 1 EPCA0CEN EPCA0 Module Clock Enable. 11 1 DISABLED Disable the APB clock to the EPCA0 Module (default). 0 ENABLED Enable the APB clock to the EPCA0 Module. 1 PCA0CEN PCA0 Module Clock Enable. 12 1 DISABLED Disable the APB clock to the PCA0 Module (default). 0 ENABLED Enable the APB clock to the PCA0 Module. 1 PCA1CEN PCA1 Module Clock Enable. 13 1 DISABLED Disable the APB clock to the PCA1 Module (default). 0 ENABLED Enable the APB clock to the PCA1 Module. 1 SSG0CEN SSG0 Module Clock Enable. 14 1 DISABLED Disable the APB clock to the SSG0 Module (default). 0 ENABLED Enable the APB clock to the SSG0 Module. 1 TIMER0CEN TIMER0 Module Clock Enable. 15 1 DISABLED Disable the APB clock to the TIMER0 Module (default). 0 ENABLED Enable the APB clock to the TIMER0 Module. 1 TIMER1CEN TIMER1 Module Clock Enable. 16 1 DISABLED Disable the APB clock to the TIMER1 Module (default). 0 ENABLED Enable the APB clock to the TIMER1 Module. 1 ADC0CEN SARADC0 Module Clock Enable. 17 1 DISABLED Disable the APB clock to the SARADC0 Module (default). 0 ENABLED Enable the APB clock to the SARADC0 Module. 1 ADC1CEN SARADC1 Module Clock Enable. 18 1 DISABLED Disable the APB clock to the SARADC1 Module (default). 0 ENABLED Enable the APB clock to the SARADC1 Module. 1 CMP0CEN Comparator 0 Module Clock Enable. 19 1 DISABLED Disable the APB clock to the Comparator 0 Module (default). 0 ENABLED Enable the APB clock to the Comparator 0 Module. 1 CMP1CEN Comparator 1 Module Clock Enable. 20 1 DISABLED Disable the APB clock to the Comparator 1 Module (default). 0 ENABLED Enable the APB clock to the Comparator 1 Module. 1 CS0CEN Capacitive Sensing (CAPSENSE0) Module Clock Enable. 21 1 DISABLED Disable the APB clock to the CAPSENSE0 Module (default). 0 ENABLED Enable the APB clock to the CAPSENSE0 Module. 1 AES0CEN AES0 Module Clock Enable. 22 1 DISABLED Disable the APB clock to the AES0 Module (default). 0 ENABLED Enable the APB clock to the AES0 Module. 1 CRC0CEN CRC0 Module Clock Enable. 23 1 DISABLED Disable the APB clock to the CRC0 Module (default). 0 ENABLED Enable the APB clock to the CRC0 Module. 1 IDAC0CEN IDAC0 Module Clock Enable. 24 1 DISABLED Disable the APB clock to the IDAC0 Module (default). 0 ENABLED Enable the APB clock to the IDAC0 Module. 1 IDAC1CEN IDAC1 Module Clock Enable. 25 1 DISABLED Disable the APB clock to the IDAC1 Module (default). 0 ENABLED Enable the APB clock to the IDAC1 Module. 1 LPT0CEN Low Power Timer (LPTIMER0) Module Clock Enable. 26 1 DISABLED Disable the APB clock to the LPTIMER0 Module (default). 0 ENABLED Enable the APB clock to the LPTIMER0 Module. 1 I2S0CEN I2S0 Module Clock Enable. 27 1 DISABLED Disable the APB clock to the I2S0 Module (default). 0 ENABLED Enable the APB clock to the I2S0 Module. 1 EVREGCEN External Regulator Clock Enable. 29 1 DISABLED Disable the APB clock to the External Regulator Module (EXTVREG0) (default). 0 ENABLED Enable the APB clock to the External Regulator Module (EXTVREG0). 1 FLCTRLCEN Flash Controller Clock Enable. 30 1 DISABLED Disable the APB clock to the Flash Controller Module (FLASHCTRL0) (default). 0 ENABLED Enable the APB clock to the Flash Controller Module (FLASHCTRL0). 1 APBCLKG1 APB Clock Gate 1 0x30 0x00000002 0xFFFFFFFF MISC0CEN Miscellaneous 0 Clock Enable. 0 1 DISABLED Disable the APB clock to the RSTSRC0, LOCK0, VMON0, VREG0, LDO0, VREF0, EXTOSC0, LPOSC0, EXTVREG0, IVC0 and RTC0 modules (default). 0 ENABLED Enable the APB clock to the RSTSRC0, LOCK0, VMON0, VREG0, LDO0, VREF0, EXTOSC0, LPOSC0, EXTVREG0, IVC0 and RTC0 modules. 1 MISC1CEN Miscellaneous 1 Clock Enable. 1 1 DISABLED Disable the APB clock to the Watchdog Timer (WDTIMER0), EMIF0, and DMA Crossbar (DMAXBAR0) modules. 0 ENABLED Enable the APB clock to the Watchdog Timer (WDTIMER0), EMIF0, and DMA Crossbar (DMAXBAR0) modules (default). 1 MISC2CEN Miscellaneous 2 Clock Enable. 2 1 DISABLED Disable the APB clock to the OSCVLDF flag in the EXTOSC module (default). 0 ENABLED Enable the APB clock to the OSCVLDF flag in the EXTOSC module. 1 PM3CN Power Mode 3 Clock Control 0x40 0x00000000 0xFFFFFFFF PM3CSEL Power Mode 3 Fast-Wake Clock Source. 0 3 LPOSC0 Power Mode 3 clock source is the Low-Power Oscillator. 0 LFOSC0 Power Mode 3 clock source is the Low-Frequency Oscillator. 1 RTC0OSC Power Mode 3 clock source is the RTC Oscillator. 2 EXTOSC0 Power Mode 3 clock source is the External Oscillator. 3 PLL0OSC Power Mode 3 clock source is the PLL. 5 LPOSC0_DIV Power Mode 3 clock source is a divided version of the Low-Power Oscillator. 6 PM3CEN Power Mode 3 Fast-Wake Clock Enable. 16 1 DISABLED Disable the core clock when in Power Mode 3. 0 ENABLED The core clock is enabled and runs off the clock selected by PM3CSEL in Power Mode 3. 1 CMP_0 A None Comparator 0x4001f000 0x0 0xffc registers CMP0_IRQn 37 CONTROL Module Control 0x0 0x00000000 0xFFFFFFFF CMPFI Falling Edge Interrupt Flag. 13 1 NOT_SET No comparator falling edge has occurred since this flag was last cleared. 0 SET A comparator falling edge occurred since last flag was cleared. 1 CMPRI Rising Edge Interrupt Flag. 14 1 NOT_SET No comparator rising edge has occurred since this flag was last cleared. 0 SET A comparator rising edge occurred since last flag was cleared. 1 CMPOUT Output State. 30 1 read-only POS_LT_NEG Voltage on CP+ < CP-. 0 POS_GT_NEG Voltage on CP+ > CP-. 1 CMPEN Comparator Enable. 31 1 DISABLED Disable the comparator. 0 ENABLED Enable the comparator. 1 MODE Input and Module Mode 0x10 0x00000800 0xFFFFFFFF NMUX Negative Input Select. 0 4 CMPNN0 Select CMPnN.0 (PB1.3). 0 CMPNN1 Select CMPnN.1 (PB3.1). 1 CMPNN2 Select CMPnN.2 (PB3.3). 2 CMPNN3 Select CMPnN.3 (RESERVED). 3 CMPNN4 Select CMPnN.4 (RESERVED). 4 CMPNN5 Select CMPnN.5 (RESERVED). 5 CMPNN6 Select CMPnN.6 (RESERVED). 6 CMPNN7 Select CMPnN.7 (RESERVED). 7 CMPNN8 Select CMPnN.8 (VDD). 8 CMPNN9 Select CMPnN.9 (VREF). 9 CMPNN10 Select CMPnN.10 (RESERVED). 10 CMPNN11 Select CMPnN.11 (RESERVED). 11 CMPNN12 Select CMPnN.12 (RESERVED). 12 CMPNN13 Select CMPnN.13 (RESERVED). 13 CMPNN14 Select CMPnN.14 (RESERVED). 14 CMPNN15 Select CMPnN.15 (RESERVED). 15 PMUX Positive Input Select. 4 4 CMPNP0 Select CMPnP.0 (PB1.2). 0 CMPNP1 Select CMPnP.1 (PB3.0). 1 CMPNP2 Select CMPnP.2 (PB3.2). 2 CMPNP3 Select CMPnP.3 (RESERVED). 3 CMPNP4 Select CMPnP.4 (RESERVED). 4 CMPNP5 Select CMPnP.5 (RESERVED). 5 CMPNP6 Select CMPnP.6 (RESERVED). 6 CMPNP7 Select CMPnP.7 (RESERVED). 7 CMPNP8 Select CMPnP.8 (Voltage at VREGIN / 4). 8 CMPNP9 Select CMPnP.9 (EXTVREG0 Current Sense). 9 CMPNP10 Select CMPnP.10 (1.8V Output of LDO). 10 CMPNP11 Select CMPnP.11 (VDDOSC Supply). 11 CMPNP12 Select CMPnP.12 (VREF). 12 CMPNP13 Select CMPnP.13 (VIO). 13 CMPNP14 Select CMPnP.14 (Voltage at VIOHD / 4). 14 CMPNP15 Select CMPnP.15 (RESERVED). 15 INMUX Input MUX Select. 8 2 DIRECT Connects the NMUX signal to CP- and the PMUX signal to CP+. 0 CMPP_VSS Connects VSS to CP- and the PMUX signal to CP+. 1 CMPP_DAC Connects the NMUX signal to CP-, the PMUX signal to the Comparator DAC voltage reference, and the DAC output to CP+. 2 CMPN_DAC Connects the PMUX signal to CP+, the NMUX signal to the Comparator DAC voltage reference, and the DAC output to CP-. 3 CMPMD Comparator Mode. 10 2 MODE0 Mode 0 (fastest response time, highest power consumption). 0 MODE1 Mode 1. 1 MODE2 Mode 2. 2 MODE3 Mode 3 (slowest response time, lowest power consumption). 3 FIEN Falling Edge Interrupt Enable. 13 1 DISABLED Disable the comparator falling edge interrupt. 0 ENABLED Enable the comparator falling edge interrupt. 1 RIEN Rising Edge Interrupt Enable. 14 1 DISABLED Disable the comparator rising edge interrupt. 0 ENABLED Enable the comparator rising edge interrupt. 1 DACLVL Comparator DAC Output Level. 16 6 NWPUEN Negative Input Weak Pullup Enable. 22 1 DISABLED Disable the negative input weak pull up. 0 ENABLED Enable the negative input weak pull up. 1 PWPUEN Positive Input Weak Pullup Enable. 23 1 DISABLED Disable the positive input weak pull up. 0 ENABLED Enable the positive input weak pull up. 1 CMPHYN Negative Hysteresis Control. 24 2 DISABLED Disable negative hysteresis. 0 NEG_5_MV Set negative hysteresis to 5 mV. 1 NEG_10_MV Set negative hysteresis to 10 mV. 2 NEG_20_MV Set negative hysteresis to 20 mV. 3 CMPHYP Positive Hysteresis Control. 26 2 DISABLED Disable positive hysteresis. 0 POS_5_MV Set positive hysteresis to 5 mV. 1 POS_10_MV Set positive hysteresis to 10 mV. 2 POS_20_MV Set positive hysteresis to 20 mV. 3 INVEN Invert Comparator Output Enable. 30 1 DISABLED Do not invert the comparator output. 0 ENABLED Invert the comparator output. 1 CMP_1 A None Comparator 0x40020000 0x0 0xffc registers CMP1_IRQn 38 CONTROL Module Control 0x0 0x00000000 0xFFFFFFFF CMPFI Falling Edge Interrupt Flag. 13 1 NOT_SET No comparator falling edge has occurred since this flag was last cleared. 0 SET A comparator falling edge occurred since last flag was cleared. 1 CMPRI Rising Edge Interrupt Flag. 14 1 NOT_SET No comparator rising edge has occurred since this flag was last cleared. 0 SET A comparator rising edge occurred since last flag was cleared. 1 CMPOUT Output State. 30 1 read-only POS_LT_NEG Voltage on CP+ < CP-. 0 POS_GT_NEG Voltage on CP+ > CP-. 1 CMPEN Comparator Enable. 31 1 DISABLED Disable the comparator. 0 ENABLED Enable the comparator. 1 MODE Input and Module Mode 0x10 0x00000800 0xFFFFFFFF NMUX Negative Input Select. 0 4 CMPNN0 Select CMPnN.0 (PB1.3). 0 CMPNN1 Select CMPnN.1 (PB3.1). 1 CMPNN2 Select CMPnN.2 (PB3.3). 2 CMPNN3 Select CMPnN.3 (RESERVED). 3 CMPNN4 Select CMPnN.4 (RESERVED). 4 CMPNN5 Select CMPnN.5 (RESERVED). 5 CMPNN6 Select CMPnN.6 (RESERVED). 6 CMPNN7 Select CMPnN.7 (RESERVED). 7 CMPNN8 Select CMPnN.8 (VDD). 8 CMPNN9 Select CMPnN.9 (VREF). 9 CMPNN10 Select CMPnN.10 (RESERVED). 10 CMPNN11 Select CMPnN.11 (RESERVED). 11 CMPNN12 Select CMPnN.12 (RESERVED). 12 CMPNN13 Select CMPnN.13 (RESERVED). 13 CMPNN14 Select CMPnN.14 (RESERVED). 14 CMPNN15 Select CMPnN.15 (RESERVED). 15 PMUX Positive Input Select. 4 4 CMPNP0 Select CMPnP.0 (PB1.2). 0 CMPNP1 Select CMPnP.1 (PB3.0). 1 CMPNP2 Select CMPnP.2 (PB3.2). 2 CMPNP3 Select CMPnP.3 (RESERVED). 3 CMPNP4 Select CMPnP.4 (RESERVED). 4 CMPNP5 Select CMPnP.5 (RESERVED). 5 CMPNP6 Select CMPnP.6 (RESERVED). 6 CMPNP7 Select CMPnP.7 (RESERVED). 7 CMPNP8 Select CMPnP.8 (Voltage at VREGIN / 4). 8 CMPNP9 Select CMPnP.9 (EXTVREG0 Current Sense). 9 CMPNP10 Select CMPnP.10 (1.8V Output of LDO). 10 CMPNP11 Select CMPnP.11 (VDDOSC Supply). 11 CMPNP12 Select CMPnP.12 (VREF). 12 CMPNP13 Select CMPnP.13 (VIO). 13 CMPNP14 Select CMPnP.14 (Voltage at VIOHD / 4). 14 CMPNP15 Select CMPnP.15 (RESERVED). 15 INMUX Input MUX Select. 8 2 DIRECT Connects the NMUX signal to CP- and the PMUX signal to CP+. 0 CMPP_VSS Connects VSS to CP- and the PMUX signal to CP+. 1 CMPP_DAC Connects the NMUX signal to CP-, the PMUX signal to the Comparator DAC voltage reference, and the DAC output to CP+. 2 CMPN_DAC Connects the PMUX signal to CP+, the NMUX signal to the Comparator DAC voltage reference, and the DAC output to CP-. 3 CMPMD Comparator Mode. 10 2 MODE0 Mode 0 (fastest response time, highest power consumption). 0 MODE1 Mode 1. 1 MODE2 Mode 2. 2 MODE3 Mode 3 (slowest response time, lowest power consumption). 3 FIEN Falling Edge Interrupt Enable. 13 1 DISABLED Disable the comparator falling edge interrupt. 0 ENABLED Enable the comparator falling edge interrupt. 1 RIEN Rising Edge Interrupt Enable. 14 1 DISABLED Disable the comparator rising edge interrupt. 0 ENABLED Enable the comparator rising edge interrupt. 1 DACLVL Comparator DAC Output Level. 16 6 NWPUEN Negative Input Weak Pullup Enable. 22 1 DISABLED Disable the negative input weak pull up. 0 ENABLED Enable the negative input weak pull up. 1 PWPUEN Positive Input Weak Pullup Enable. 23 1 DISABLED Disable the positive input weak pull up. 0 ENABLED Enable the positive input weak pull up. 1 CMPHYN Negative Hysteresis Control. 24 2 DISABLED Disable negative hysteresis. 0 NEG_5_MV Set negative hysteresis to 5 mV. 1 NEG_10_MV Set negative hysteresis to 10 mV. 2 NEG_20_MV Set negative hysteresis to 20 mV. 3 CMPHYP Positive Hysteresis Control. 26 2 DISABLED Disable positive hysteresis. 0 POS_5_MV Set positive hysteresis to 5 mV. 1 POS_10_MV Set positive hysteresis to 10 mV. 2 POS_20_MV Set positive hysteresis to 20 mV. 3 INVEN Invert Comparator Output Enable. 30 1 DISABLED Do not invert the comparator output. 0 ENABLED Invert the comparator output. 1 DMACTRL_0 A None DMA 0x40036000 0x0 0xffc registers STATUS Controller Status 0x0 0x000F0000 0xFFFFFFFF DMAENSTS DMA Enable Status. 0 1 read-only NOT_SET DMA controller is disabled 0 SET DMA controller is enabled. 1 STATE State Machine State. 4 4 read-only IDLE Idle. 0 READING_CHANNEL_CONFIG Reading channel controller data. 1 READING_SOURCE_POINTER Reading source data end pointer. 2 READING_DEST_POINTER Reading destination data end pointer. 3 READING_SOURCE_DATA Reading source data. 4 WRITING_DEST_DATA Writing destination data. 5 WAITING_DMA_REQ_CLEAR Waiting for a DMA request to clear. 6 WRITING_CHANNEL_CONFIG Writing channel controller data. 7 STALLED Stalled. 8 DONE Done. 9 SCATTER_GATHER_TRANSITION Peripheral scatter-gather transition. 10 NUMCHAN Number of Supported DMA Channels. 16 5 read-only CONFIG Controller Configuration 0x4 0x00000000 0xFFFFFFFF DMAEN DMA Enable. 0 1 write-only DISABLED Disable the DMA controller. 0 ENABLED Enable the DMA controller. 1 BASEPTR Base Pointer 0x8 0x00000000 0xFFFFFFFF BASEPTR Control Base Pointer. 5 27 ABASEPTR Alternate Base Pointer 0xc 0x00000100 0xFFFFFFFF ABASEPTR Alternate Control Base Pointer. 0 32 read-only CHSTATUS Channel Status 0x10 0x0000FFFF 0xFFFFFFFF CH0 Channel 0 Status. 0 1 read-only NOT_WAITING DMA Channel 0 is not waiting for a data request. 0 WAITING DMA Channel 0 is waiting for a data request. 1 CH1 Channel 1 Status. 1 1 read-only NOT_WAITING DMA Channel 1 is not waiting for a data request. 0 WAITING DMA Channel 1 is waiting for a data request. 1 CH2 Channel 2 Status. 2 1 read-only NOT_WAITING DMA Channel 2 is not waiting for a data request. 0 WAITING DMA Channel 2 is waiting for a data request. 1 CH3 Channel 3 Status. 3 1 read-only NOT_WAITING DMA Channel 3 is not waiting for a data request. 0 WAITING DMA Channel 3 is waiting for a data request. 1 CH4 Channel 4 Status. 4 1 read-only NOT_WAITING DMA Channel 4 is not waiting for a data request. 0 WAITING DMA Channel 4 is waiting for a data request. 1 CH5 Channel 5 Status. 5 1 read-only NOT_WAITING DMA Channel 5 is not waiting for a data request. 0 WAITING DMA Channel 5 is waiting for a data request. 1 CH6 Channel 6 Status. 6 1 read-only NOT_WAITING DMA Channel 6 is not waiting for a data request. 0 WAITING DMA Channel 6 is waiting for a data request. 1 CH7 Channel 7 Status. 7 1 read-only NOT_WAITING DMA Channel 7 is not waiting for a data request. 0 WAITING DMA Channel 7 is waiting for a data request. 1 CH8 Channel 8 Status. 8 1 read-only NOT_WAITING DMA Channel 8 is not waiting for a data request. 0 WAITING DMA Channel 8 is waiting for a data request. 1 CH9 Channel 9 Status. 9 1 read-only NOT_WAITING DMA Channel 9 is not waiting for a data request. 0 WAITING DMA Channel 9 is waiting for a data request. 1 CH10 Channel 10 Status. 10 1 read-only NOT_WAITING DMA Channel 10 is not waiting for a data request. 0 WAITING DMA Channel 10 is waiting for a data request. 1 CH11 Channel 11 Status. 11 1 read-only NOT_WAITING DMA Channel 11 is not waiting for a data request. 0 WAITING DMA Channel 11 is waiting for a data request. 1 CH12 Channel 12 Status. 12 1 read-only NOT_WAITING DMA Channel 12 is not waiting for a data request. 0 WAITING DMA Channel 12 is waiting for a data request. 1 CH13 Channel 13 Status. 13 1 read-only NOT_WAITING DMA Channel 13 is not waiting for a data request. 0 WAITING DMA Channel 13 is waiting for a data request. 1 CH14 Channel 14 Status. 14 1 read-only NOT_WAITING DMA Channel 14 is not waiting for a data request. 0 WAITING DMA Channel 14 is waiting for a data request. 1 CH15 Channel 15 Status. 15 1 read-only NOT_WAITING DMA Channel 15 is not waiting for a data request. 0 WAITING DMA Channel 15 is waiting for a data request. 1 CHSWRCN Channel Software Request Control 0x14 0x00000000 0xFFFFFFFF CH0 Channel 0 Software Request. 0 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 0 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 0 generates a software data request. 1 CH1 Channel 1 Software Request. 1 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 1 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 1 generates a software data request. 1 CH2 Channel 2 Software Request. 2 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 2 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 2 generates a software data request. 1 CH3 Channel 3 Software Request. 3 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 3 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 3 generates a software data request. 1 CH4 Channel 4 Software Request. 4 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 4 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 4 generates a software data request. 1 CH5 Channel 5 Software Request. 5 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 5 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 5 generates a software data request. 1 CH6 Channel 6 Software Request. 6 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 6 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 6 generates a software data request. 1 CH7 Channel 7 Software Request. 7 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 7 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 7 generates a software data request. 1 CH8 Channel 8 Software Request. 8 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 8 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 8 generates a software data request. 1 CH9 Channel 9 Software Request. 9 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 9 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 9 generates a software data request. 1 CH10 Channel 10 Software Request. 10 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 10 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 10 generates a software data request. 1 CH11 Channel 11 Software Request. 11 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 11 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 11 generates a software data request. 1 CH12 Channel 12 Software Request. 12 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 12 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 12 generates a software data request. 1 CH13 Channel 13 Software Request. 13 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 13 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 13 generates a software data request. 1 CH14 Channel 14 Software Request. 14 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 14 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 14 generates a software data request. 1 CH15 Channel 15 Software Request. 15 1 write-only DO_NOT_GENERATE_SW_REQ DMA Channel 15 does not generate a software data request. 0 GENERATE_SW_REQ DMA Channel 15 generates a software data request. 1 CHREQMSET Channel Request Mask Set 0x20 0x00000000 0xFFFFFFFF CH0 Channel 0 Request Mask Enable. 0 1 ENABLED Read: 0: DMA Channel 0 peripheral data requests enabled. 1: DMA Channel 0 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 0 peripheral data requests. 1 CH1 Channel 1 Request Mask Enable. 1 1 ENABLED Read: 0: DMA Channel 1 peripheral data requests enabled. 1: DMA Channel 1 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 1 peripheral data requests. 1 CH2 Channel 2 Request Mask Enable. 2 1 ENABLED Read: 0: DMA Channel 2 peripheral data requests enabled. 1: DMA Channel 2 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 2 peripheral data requests. 1 CH3 Channel 3 Request Mask Enable. 3 1 ENABLED Read: 0: DMA Channel 3 peripheral data requests enabled. 1: DMA Channel 3 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 3 peripheral data requests. 1 CH4 Channel 4 Request Mask Enable. 4 1 ENABLED Read: 0: DMA Channel 4 peripheral data requests enabled. 1: DMA Channel 4 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 4 peripheral data requests. 1 CH5 Channel 5 Request Mask Enable. 5 1 ENABLED Read: 0: DMA Channel 5 peripheral data requests enabled. 1: DMA Channel 5 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 5 peripheral data requests. 1 CH6 Channel 6 Request Mask Enable. 6 1 ENABLED Read: 0: DMA Channel 6 peripheral data requests enabled. 1: DMA Channel 6 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 6 peripheral data requests. 1 CH7 Channel 7 Request Mask Enable. 7 1 ENABLED Read: 0: DMA Channel 7 peripheral data requests enabled. 1: DMA Channel 7 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 7 peripheral data requests. 1 CH8 Channel 8 Request Mask Enable. 8 1 ENABLED Read: 0: DMA Channel 8 peripheral data requests enabled. 1: DMA Channel 8 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 8 peripheral data requests. 1 CH9 Channel 9 Request Mask Enable. 9 1 ENABLED Read: 0: DMA Channel 9 peripheral data requests enabled. 1: DMA Channel 9 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 9 peripheral data requests. 1 CH10 Channel 10 Request Mask Enable. 10 1 ENABLED Read: 0: DMA Channel 10 peripheral data requests enabled. 1: DMA Channel 10 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 10 peripheral data requests. 1 CH11 Channel 11 Request Mask Enable. 11 1 ENABLED Read: 0: DMA Channel 11 peripheral data requests enabled. 1: DMA Channel 11 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 11 peripheral data requests. 1 CH12 Channel 12 Request Mask Enable. 12 1 ENABLED Read: 0: DMA Channel 12 peripheral data requests enabled. 1: DMA Channel 12 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 12 peripheral data requests. 1 CH13 Channel 13 Request Mask Enable. 13 1 ENABLED Read: 0: DMA Channel 13 peripheral data requests enabled. 1: DMA Channel 13 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 13 peripheral data requests. 1 CH14 Channel 14 Request Mask Enable. 14 1 ENABLED Read: 0: DMA Channel 14 peripheral data requests enabled. 1: DMA Channel 14 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 14 peripheral data requests. 1 CH15 Channel 15 Request Mask Enable. 15 1 ENABLED Read: 0: DMA Channel 15 peripheral data requests enabled. 1: DMA Channel 15 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 15 peripheral data requests. 1 CHREQMCLR Channel Request Mask Clear 0x24 0x00000000 0xFFFFFFFF CH0 Channel 0 Request Mask Disable. 0 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 0 peripheral data requests. 1 CH1 Channel 1 Request Mask Disable. 1 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 1 peripheral data requests. 1 CH2 Channel 2 Request Mask Disable. 2 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 2 peripheral data requests. 1 CH3 Channel 3 Request Mask Disable. 3 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 3 peripheral data requests. 1 CH4 Channel 4 Request Mask Disable. 4 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 4 peripheral data requests. 1 CH5 Channel 5 Request Mask Disable. 5 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 5 peripheral data requests. 1 CH6 Channel 6 Request Mask Disable. 6 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 6 peripheral data requests. 1 CH7 Channel 7 Request Mask Disable. 7 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 7 peripheral data requests. 1 CH8 Channel 8 Request Mask Disable. 8 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 8 peripheral data requests. 1 CH9 Channel 9 Request Mask Disable. 9 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 9 peripheral data requests. 1 CH10 Channel 10 Request Mask Disable. 10 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 10 peripheral data requests. 1 CH11 Channel 11 Request Mask Disable. 11 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 11 peripheral data requests. 1 CH12 Channel 12 Request Mask Disable. 12 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 12 peripheral data requests. 1 CH13 Channel 13 Request Mask Disable. 13 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 13 peripheral data requests. 1 CH14 Channel 14 Request Mask Disable. 14 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 14 peripheral data requests. 1 CH15 Channel 15 Request Mask Disable. 15 1 write-only RESERVED No effect. 0 DISABLED Enable DMA Channel 15 peripheral data requests. 1 CHENSET Channel Enable Set 0x28 0x00000000 0xFFFFFFFF CH0 Channel 0 Enable. 0 1 ENABLED Read: 0: DMA Channel 0 disabled. 1: DMA Channel 0 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 0. 1 CH1 Channel 1 Enable. 1 1 ENABLED Read: 0: DMA Channel 1 disabled. 1: DMA Channel 1 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 1. 1 CH2 Channel 2 Enable. 2 1 ENABLED Read: 0: DMA Channel 2 disabled. 1: DMA Channel 2 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 2. 1 CH3 Channel 3 Enable. 3 1 ENABLED Read: 0: DMA Channel 3 disabled. 1: DMA Channel 3 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 3. 1 CH4 Channel 4 Enable. 4 1 ENABLED Read: 0: DMA Channel 4 disabled. 1: DMA Channel 4 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 4. 1 CH5 Channel 5 Enable. 5 1 ENABLED Read: 0: DMA Channel 5 disabled. 1: DMA Channel 5 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 5. 1 CH6 Channel 6 Enable. 6 1 ENABLED Read: 0: DMA Channel 6 disabled. 1: DMA Channel 6 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 6. 1 CH7 Channel 7 Enable. 7 1 ENABLED Read: 0: DMA Channel 7 disabled. 1: DMA Channel 7 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 7. 1 CH8 Channel 8 Enable. 8 1 ENABLED Read: 0: DMA Channel 8 disabled. 1: DMA Channel 8 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 8. 1 CH9 Channel 9 Enable. 9 1 ENABLED Read: 0: DMA Channel 9 disabled. 1: DMA Channel 9 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 9. 1 CH10 Channel 10 Enable. 10 1 ENABLED Read: 0: DMA Channel 10 disabled. 1: DMA Channel 10 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 10. 1 CH11 Channel 11 Enable. 11 1 ENABLED Read: 0: DMA Channel 11 disabled. 1: DMA Channel 11 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 11. 1 CH12 Channel 12 Enable. 12 1 ENABLED Read: 0: DMA Channel 12 disabled. 1: DMA Channel 12 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 12. 1 CH13 Channel 13 Enable. 13 1 ENABLED Read: 0: DMA Channel 13 disabled. 1: DMA Channel 13 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 13. 1 CH14 Channel 14 Enable. 14 1 ENABLED Read: 0: DMA Channel 14 disabled. 1: DMA Channel 14 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 14. 1 CH15 Channel 15 Enable. 15 1 ENABLED Read: 0: DMA Channel 15 disabled. 1: DMA Channel 15 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 15. 1 CHENCLR Channel Enable Clear 0x2c 0x00000000 0xFFFFFFFF CH0 Channel 0 Disable. 0 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 0. 1 CH1 Channel 1 Disable. 1 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 1. 1 CH2 Channel 2 Disable. 2 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 2. 1 CH3 Channel 3 Disable. 3 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 3. 1 CH4 Channel 4 Disable. 4 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 4. 1 CH5 Channel 5 Disable. 5 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 5. 1 CH6 Channel 6 Disable. 6 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 6. 1 CH7 Channel 7 Disable. 7 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 7. 1 CH8 Channel 8 Disable. 8 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 8. 1 CH9 Channel 9 Disable. 9 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 9. 1 CH10 Channel 10 Disable. 10 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 10. 1 CH11 Channel 11 Disable. 11 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 11. 1 CH12 Channel 12 Disable. 12 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 12. 1 CH13 Channel 13 Disable. 13 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 13. 1 CH14 Channel 14 Disable. 14 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 14. 1 CH15 Channel 15 Disable. 15 1 write-only RESERVED No effect. 0 DISABLED Disable DMA Channel 15. 1 CHALTSET Channel Alternate Select Set 0x30 0x00000000 0xFFFFFFFF CH0 Channel 0 Alternate Enable. 0 1 ENABLED Read: 0: DMA Channel 0 is using primary data structure. 1: DMA Channel 0 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 0. 1 CH1 Channel 1 Alternate Enable. 1 1 ENABLED Read: 0: DMA Channel 1 is using primary data structure. 1: DMA Channel 1 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 1. 1 CH2 Channel 2 Alternate Enable. 2 1 ENABLED Read: 0: DMA Channel 2 is using primary data structure. 1: DMA Channel 2 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 2. 1 CH3 Channel 3 Alternate Enable. 3 1 ENABLED Read: 0: DMA Channel 3 is using primary data structure. 1: DMA Channel 3 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 3. 1 CH4 Channel 4 Alternate Enable. 4 1 ENABLED Read: 0: DMA Channel 4 is using primary data structure. 1: DMA Channel 4 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 4. 1 CH5 Channel 5 Alternate Enable. 5 1 ENABLED Read: 0: DMA Channel 5 is using primary data structure. 1: DMA Channel 5 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 5. 1 CH6 Channel 6 Alternate Enable. 6 1 ENABLED Read: 0: DMA Channel 6 is using primary data structure. 1: DMA Channel 6 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 6. 1 CH7 Channel 7 Alternate Enable. 7 1 ENABLED Read: 0: DMA Channel 7 is using primary data structure. 1: DMA Channel 7 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 7. 1 CH8 Channel 8 Alternate Enable. 8 1 ENABLED Read: 0: DMA Channel 8 is using primary data structure. 1: DMA Channel 8 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 8. 1 CH9 Channel 9 Alternate Enable. 9 1 ENABLED Read: 0: DMA Channel 9 is using primary data structure. 1: DMA Channel 9 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 9. 1 CH10 Channel 10 Alternate Enable. 10 1 ENABLED Read: 0: DMA Channel 10 is using primary data structure. 1: DMA Channel 10 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 10. 1 CH11 Channel 11 Alternate Enable. 11 1 ENABLED Read: 0: DMA Channel 11 is using primary data structure. 1: DMA Channel 11 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 11. 1 CH12 Channel 12 Alternate Enable. 12 1 ENABLED Read: 0: DMA Channel 12 is using primary data structure. 1: DMA Channel 12 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 12. 1 CH13 Channel 13 Alternate Enable. 13 1 ENABLED Read: 0: DMA Channel 13 is using primary data structure. 1: DMA Channel 13 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 13. 1 CH14 Channel 14 Alternate Enable. 14 1 ENABLED Read: 0: DMA Channel 14 is using primary data structure. 1: DMA Channel 14 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 14. 1 CH15 Channel 15 Alternate Enable. 15 1 ENABLED Read: 0: DMA Channel 15 is using primary data structure. 1: DMA Channel 15 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 15. 1 CHALTCLR Channel Alternate Select Clear 0x34 0x00000000 0xFFFFFFFF CH0 Channel 0 Alternate Disable. 0 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 0. 1 CH1 Channel 1 Alternate Disable. 1 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 1. 1 CH2 Channel 2 Alternate Disable. 2 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 2. 1 CH3 Channel 3 Alternate Disable. 3 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 3. 1 CH4 Channel 4 Alternate Disable. 4 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 4. 1 CH5 Channel 5 Alternate Disable. 5 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 5. 1 CH6 Channel 6 Alternate Disable. 6 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 6. 1 CH7 Channel 7 Alternate Disable. 7 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 7. 1 CH8 Channel 8 Alternate Disable. 8 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 8. 1 CH9 Channel 9 Alternate Disable. 9 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 9. 1 CH10 Channel 10 Alternate Disable. 10 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 10. 1 CH11 Channel 11 Alternate Disable. 11 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 11. 1 CH12 Channel 12 Alternate Disable. 12 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 12. 1 CH13 Channel 13 Alternate Disable. 13 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 13. 1 CH14 Channel 14 Alternate Disable. 14 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 14. 1 CH15 Channel 15 Alternate Disable. 15 1 write-only RESERVED No effect. 0 DISABLED Use the primary data structure for DMA Channel 15. 1 CHHPSET Channel High Priority Set 0x38 0x00000000 0xFFFFFFFF CH0 Channel 0 High Priority Enable. 0 1 ENABLED Read: 0: DMA Channel 0 is using the default priority level. 1: DMA Channel 0 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 0. 1 CH1 Channel 1 High Priority Enable. 1 1 ENABLED Read: 0: DMA Channel 1 is using the default priority level. 1: DMA Channel 1 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 1. 1 CH2 Channel 2 High Priority Enable. 2 1 ENABLED Read: 0: DMA Channel 2 is using the default priority level. 1: DMA Channel 2 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 2. 1 CH3 Channel 3 High Priority Enable. 3 1 ENABLED Read: 0: DMA Channel 3 is using the default priority level. 1: DMA Channel 3 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 3. 1 CH4 Channel 4 High Priority Enable. 4 1 ENABLED Read: 0: DMA Channel 4 is using the default priority level. 1: DMA Channel 4 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 4. 1 CH5 Channel 5 High Priority Enable. 5 1 ENABLED Read: 0: DMA Channel 5 is using the default priority level. 1: DMA Channel 5 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 5. 1 CH6 Channel 6 High Priority Enable. 6 1 ENABLED Read: 0: DMA Channel 6 is using the default priority level. 1: DMA Channel 6 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 6. 1 CH7 Channel 7 High Priority Enable. 7 1 ENABLED Read: 0: DMA Channel 7 is using the default priority level. 1: DMA Channel 7 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 7. 1 CH8 Channel 8 High Priority Enable. 8 1 ENABLED Read: 0: DMA Channel 8 is using the default priority level. 1: DMA Channel 8 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 8. 1 CH9 Channel 9 High Priority Enable. 9 1 ENABLED Read: 0: DMA Channel 9 is using the default priority level. 1: DMA Channel 9 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 9. 1 CH10 Channel 10 High Priority Enable. 10 1 ENABLED Read: 0: DMA Channel 10 is using the default priority level. 1: DMA Channel 10 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 10. 1 CH11 Channel 11 High Priority Enable. 11 1 ENABLED Read: 0: DMA Channel 11 is using the default priority level. 1: DMA Channel 11 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 11. 1 CH12 Channel 12 High Priority Enable. 12 1 ENABLED Read: 0: DMA Channel 12 is using the default priority level. 1: DMA Channel 12 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 12. 1 CH13 Channel 13 High Priority Enable. 13 1 ENABLED Read: 0: DMA Channel 13 is using the default priority level. 1: DMA Channel 13 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 13. 1 CH14 Channel 14 High Priority Enable. 14 1 ENABLED Read: 0: DMA Channel 14 is using the default priority level. 1: DMA Channel 14 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 14. 1 CH15 Channel 15 High Priority Enable. 15 1 ENABLED Read: 0: DMA Channel 15 is using the default priority level. 1: DMA Channel 15 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 15. 1 CHHPCLR Channel High Priority Clear 0x3c 0x00000000 0xFFFFFFFF CH0 Channel 0 High Priority Disable. 0 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 0. 1 CH1 Channel 1 High Priority Disable. 1 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 1. 1 CH2 Channel 2 High Priority Disable. 2 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 2. 1 CH3 Channel 3 High Priority Disable. 3 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 3. 1 CH4 Channel 4 High Priority Disable. 4 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 4. 1 CH5 Channel 5 High Priority Disable. 5 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 5. 1 CH6 Channel 6 High Priority Disable. 6 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 6. 1 CH7 Channel 7 High Priority Disable. 7 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 7. 1 CH8 Channel 8 High Priority Disable. 8 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 8. 1 CH9 Channel 9 High Priority Disable. 9 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 9. 1 CH10 Channel 10 High Priority Disable. 10 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 10. 1 CH11 Channel 11 High Priority Disable. 11 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 11. 1 CH12 Channel 12 High Priority Disable. 12 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 12. 1 CH13 Channel 13 High Priority Disable. 13 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 13. 1 CH14 Channel 14 High Priority Disable. 14 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 14. 1 CH15 Channel 15 High Priority Disable. 15 1 write-only RESERVED No effect. 0 DISABLED Use the high default level for DMA Channel 15. 1 BERRCLR Bus Error Clear 0x4c 0x00000000 0xFFFFFFFF ERROR DMA Bus Error Clear. 0 1 CLEAR Read: 0: DMA error did not occur. 1: DMA error occurred since the last time ERROR was cleared. Write: 0: No effect. 1: Clear the DMA error flag. 1 DMAXBAR_0 A None DMA 0x40037000 0x0 0xffc registers DMACH0_IRQn 4 DMACH1_IRQn 5 DMACH2_IRQn 6 DMACH3_IRQn 7 DMACH4_IRQn 8 DMACH5_IRQn 9 DMACH6_IRQn 10 DMACH7_IRQn 11 DMACH8_IRQn 12 DMACH9_IRQn 13 DMACH10_IRQn 14 DMACH11_IRQn 15 DMACH12_IRQn 16 DMACH13_IRQn 17 DMACH14_IRQn 18 DMACH15_IRQn 19 DMAXBAR0 Channel 0-7 Trigger Select 0x0 0x00000000 0xFFFFFFFF CH0SEL DMA Channel 0 Peripheral Select. 0 4 SPI1_RX Service SPI1 RX data requests. 1 USART0_RX Service USART0 RX data requests. 2 I2C0_TX Service I2C0 TX data requests. 3 DMA0T0_RISE Service DMAXT0 (PB0.10) rising edge data requests. 4 DMA0T0_FALL Service DMAXT0 (PB0.10) falling edge data requests. 5 DMA0T1_RISE Service DMAXT1 (PB0.11) rising edge data requests. 6 DMA0T1_FALL Service DMAXT1 (PB0.11) falling edge data requests. 7 TIMER0L Service TIMER0L overflow data requests. 8 TIMER0H Service TIMER0H overflow data requests. 9 TIMER1L Service TIMER1L overflow data requests. 10 TIMER1H Service TIMER1H overflow data requests. 11 CH1SEL DMA Channel 1 Peripheral Select. 4 4 SPI0_RX Service SPI0 RX data requests. 1 USART1_RX Service USART1 RX data requests. 2 I2C0_RX Service I2C0 RX data requests. 3 IDAC1 Service IDAC1 data requests. 4 EPCA0_CONTROL Service EPCA0 control data requests. 5 DMA0T0_RISE Service DMAXT0 (PB0.10) rising edge data requests. 6 DMA0T0_FALL Service DMAXT0 (PB0.10) falling edge data requests. 7 DMA0T1_RISE Service DMAXT1 (PB0.11) rising edge data requests. 8 DMA0T1_FALL Service DMAXT1 (PB0.11) falling edge data requests. 9 TIMER0L Service TIMER0L overflow data requests. 10 TIMER1L Service TIMER1L overflow data requests. 11 TIMER1H Service TIMER1H overflow data requests. 12 CH2SEL DMA Channel 2 Peripheral Select. 8 4 SPI0_TX Service SPI0 TX data requests. 1 USART0_TX Service USART0 TX data requests. 2 SARADC0 Service SARADC0 data requests. 3 IDAC1 Service IDAC1 data requests. 4 I2S0_TX Service I2S0 TX data requests. 5 EPCA0_CONTROL Service EPCA0 control data requests. 6 DMA0T0_RISE Service DMAXT0 (PB0.10) rising edge data requests. 7 DMA0T0_FALL Service DMAXT0 (PB0.10) falling edge data requests. 8 DMA0T1_RISE Service DMAXT1 (PB0.11) rising edge data requests. 9 DMA0T1_FALL Service DMAXT1 (PB0.11) falling edge data requests. 10 CH3SEL DMA Channel 3 Peripheral Select. 12 4 SARADC1 Service SARADC1 data requests. 1 IDAC0 Service IDAC0 data requests. 2 I2S0_TX Service I2S0 TX data requests. 3 EPCA0_CAPTURE Service EPCA0 capture data requests. 4 DMA0T0_RISE Service DMAXT0 (PB0.10) rising edge data requests. 5 DMA0T0_FALL Service DMAXT0 (PB0.10) falling edge data requests. 6 DMA0T1_RISE Service DMAXT1 (PB0.11) rising edge data requests. 7 DMA0T1_FALL Service DMAXT1 (PB0.11) falling edge data requests. 8 TIMER1H Service TIMER1H overflow data requests. 9 CH4SEL DMA Channel 4 Peripheral Select. 16 4 SPI1_TX Service SPI1 TX data requests. 1 USART0_TX Service USART0 TX data requests. 2 SARADC0 Service SARADC0 data requests. 3 I2S0_RX Service I2S0 RX data requests. 4 EPCA0_CAPTURE Service EPCA0 capture data requests. 5 DMA0T0_RISE Service DMAXT0 (PB0.10) rising edge data requests. 6 DMA0T0_FALL Service DMAXT0 (PB0.10) falling edge data requests. 7 DMA0T1_RISE Service DMAXT1 (PB0.11) rising edge data requests. 8 DMA0T1_FALL Service DMAXT1 (PB0.11) falling edge data requests. 9 TIMER0H Service TIMER0H overflow data requests. 10 CH5SEL DMA Channel 5 Peripheral Select. 20 4 AES0_TX Service AES0 TX data requests. 1 USART1_TX Service USART1 TX data requests. 2 SARADC0 Service SARADC0 data requests. 3 I2S0_RX Service I2S0 RX data requests. 4 DMA0T0_RISE Service DMAXT0 (PB0.10) rising edge data requests. 5 DMA0T0_FALL Service DMAXT0 (PB0.10) falling edge data requests. 6 DMA0T1_RISE Service DMAXT1 (PB0.11) rising edge data requests. 7 DMA0T1_FALL Service DMAXT1 (PB0.11) falling edge data requests. 8 CH6SEL DMA Channel 6 Peripheral Select. 24 4 AES0_RX Service AES0 RX data requests. 1 USART0_RX Service USART0 RX data requests. 2 I2C0_RX Service I2C0 RX data requests. 3 IDAC0 Service IDAC0 data requests. 4 DMA0T0_RISE Service DMAXT0 (PB0.10) rising edge data requests. 5 DMA0T0_FALL Service DMAXT0 (PB0.10) falling edge data requests. 6 DMA0T1_RISE Service DMAXT1 (PB0.11) rising edge data requests. 7 DMA0T1_FALL Service DMAXT1 (PB0.11) falling edge data requests. 8 TIMER0H Service TIMER0H overflow data requests. 9 CH7SEL DMA Channel 7 Peripheral Select. 28 4 AES0_XOR Service AES0 XOR data requests. 1 SPI1_TX Service SPI1 TX data requests. 2 USART0_TX Service USART0 TX data requests. 3 DMA0T0_RISE Service DMAXT0 (PB0.10) rising edge data requests. 4 DMA0T0_FALL Service DMAXT0 (PB0.10) falling edge data requests. 5 DMA0T1_RISE Service DMAXT1 (PB0.11) rising edge data requests. 6 DMA0T1_FALL Service DMAXT1 (PB0.11) falling edge data requests. 7 TIMER0L Service TIMER0L overflow data requests. 8 TIMER1L Service TIMER1L overflow data requests. 9 TIMER1H Service TIMER1H overflow data requests. 10 DMAXBAR1 Channel 8-15 Trigger Select 0x10 0x00000000 0xFFFFFFFF CH8SEL DMA Channel 8 Peripheral Select. 0 4 USART1_RX Service USART1 RX data requests. 1 SPI1_RX Service SPI1 RX data requests. 2 USART0_RX Service USART0 RX data requests. 3 EPCA0_CAPTURE Service EPCA0 capture data requests. 4 DMA0T0_RISE Service DMAXT0 (PB0.10) rising edge data requests. 5 DMA0T0_FALL Service DMAXT0 (PB0.10) falling edge data requests. 6 DMA0T1_RISE Service DMAXT1 (PB0.11) rising edge data requests. 7 DMA0T1_FALL Service DMAXT1 (PB0.11) falling edge data requests. 8 CH9SEL DMA Channel 9 Peripheral Select. 4 4 USART1_TX Service USART1 TX data requests. 1 I2C0_TX Service I2C0 TX data requests. 2 EPCA0_CAPTURE Service EPCA0 capture data requests. 3 DMA0T0_RISE Service DMAXT0 (PB0.10) rising edge data requests. 4 DMA0T0_FALL Service DMAXT0 (PB0.10) falling edge data requests. 5 DMA0T1_RISE Service DMAXT1 (PB0.11) rising edge data requests. 6 DMA0T1_FALL Service DMAXT1 (PB0.11) falling edge data requests. 7 TIMER0H Service TIMER0H overflow data requests. 8 CH10SEL DMA Channel 10 Peripheral Select. 8 4 AES0_TX Service AES0 TX data requests. 1 SARADC1 Service SARADC1 data requests. 2 I2S0_RX Service I2S0 RX data requests. 3 DMA0T0_RISE Service DMAXT0 (PB0.10) rising edge data requests. 4 DMA0T0_FALL Service DMAXT0 (PB0.10) falling edge data requests. 5 DMA0T1_RISE Service DMAXT1 (PB0.11) rising edge data requests. 6 DMA0T1_FALL Service DMAXT1 (PB0.11) falling edge data requests. 7 TIMER1H Service TIMER1H overflow data requests. 8 CH11SEL DMA Channel 11 Peripheral Select. 12 4 AES0_RX Service AES0 RX data requests. 1 USART1_RX Service USART1 RX data requests. 2 USART0_RX Service USART0 RX data requests. 3 I2C0_RX Service I2C0 RX data requests. 4 I2S0_RX Service I2S0 RX data requests. 5 DMA0T0_RISE Service DMAXT0 (PB0.10) rising edge data requests. 6 DMA0T0_FALL Service DMAXT0 (PB0.10) falling edge data requests. 7 DMA0T1_RISE Service DMAXT1 (PB0.11) rising edge data requests. 8 DMA0T1_FALL Service DMAXT1 (PB0.11) falling edge data requests. 9 TIMER0H Service TIMER0H overflow data requests. 10 CH12SEL DMA Channel 12 Peripheral Select. 16 4 AES0_XOR Service AES0 XOR data requests. 1 USART1_TX Service USART1 TX data requests. 2 SPI1_TX Service SPI1 TX data requests. 3 IDAC1 Service IDAC1 data requests. 4 I2S0_TX Service I2S0 TX data requests. 5 DMA0T0_RISE Service DMAXT0 (PB0.10) rising edge data requests. 6 DMA0T0_FALL Service DMAXT0 (PB0.10) falling edge data requests. 7 DMA0T1_RISE Service DMAXT1 (PB0.11) rising edge data requests. 8 DMA0T1_FALL Service DMAXT1 (PB0.11) falling edge data requests. 9 TIMER0L Service TIMER0L overflow data requests. 10 TIMER1L Service TIMER1L overflow data requests. 11 TIMER1H Service TIMER1H overflow data requests. 12 CH13SEL DMA Channel 13 Peripheral Select. 20 4 SPI0_RX Service SPI0 RX data requests. 1 USART0_RX Service USART0 RX data requests. 2 IDAC1 Service IDAC1 data requests. 3 I2S0_TX Service I2S0 TX data requests. 4 DMA0T0_RISE Service DMAXT0 (PB0.10) rising edge data requests. 5 DMA0T0_FALL Service DMAXT0 (PB0.10) falling edge data requests. 6 DMA0T1_RISE Service DMAXT1 (PB0.11) rising edge data requests. 7 DMA0T1_FALL Service DMAXT1 (PB0.11) falling edge data requests. 8 TIMER0H Service TIMER0H overflow data requests. 9 CH14SEL DMA Channel 14 Peripheral Select. 24 4 SPI0_TX Service SPI0 TX data requests. 1 USART0_TX Service USART0 TX data requests. 2 IDAC0 Service IDAC0 data requests. 3 EPCA0_CONTROL Service EPCA0 control data requests. 4 DMA0T0_RISE Service DMAXT0 (PB0.10) rising edge data requests. 5 DMA0T0_FALL Service DMAXT0 (PB0.10) falling edge data requests. 6 DMA0T1_RISE Service DMAXT1 (PB0.11) rising edge data requests. 7 DMA0T1_FALL Service DMAXT1 (PB0.11) falling edge data requests. 8 TIMER0L Service TIMER0L overflow data requests. 9 TIMER1L Service TIMER1L overflow data requests. 10 CH15SEL DMA Channel 15 Peripheral Select. 28 4 SARADC1 Service SARADC1 data requests. 1 IDAC0 Service IDAC0 data requests. 2 EPCA0_CONTROL Service EPCA0 control data requests. 3 DMA0T0_RISE Service DMAXT0 (PB0.10) rising edge data requests. 4 DMA0T0_FALL Service DMAXT0 (PB0.10) falling edge data requests. 5 DMA0T1_RISE Service DMAXT1 (PB0.11) rising edge data requests. 6 DMA0T1_FALL Service DMAXT1 (PB0.11) falling edge data requests. 7 TIMER0H Service TIMER0H overflow data requests. 8 TIMER1H Service TIMER1H overflow data requests. 9 DEVICEID_0 A None DEVICEID_0 0x400490c0 0x0 0xffc registers DEVICEID0 Device ID Word 0 0x0 0x00000000 0xFFFFFFFF REVID Revision ID. 0 4 REVA Revision A. 0 DEVICEID0 Device ID 0. 4 28 DEVICEID1 Device ID Word 1 0x10 0x00000000 0xFFFFFFFF DEVICEID1 Device ID 1. 0 32 DEVICEID2 Device ID Word 2 0x20 0x00000000 0xFFFFFFFF DEVICEID2 Device ID 2. 0 32 DEVICEID3 Device ID Word 3 0x30 0x00000000 0xFFFFFFFF DEVICEID3 Device ID 3. 0 32 EPCA_0 A None EPCA_0 0x4000e000 0x0 0xffc registers EPCA0_IRQn 24 MODE Module Operating Mode 0x180 0x01FF0000 0xFFFFFFFF CLKDIV Input Clock Divider. 0 10 CLKSEL Input Clock (F<subscript>CLKIN</subscript>) Select. 10 3 APB Set the APB as the input clock (FCLKIN). 0 TIMER0 Set Timer 0 low overflows divided by 2 as the input clock (FCLKIN). 1 HL_ECI Set high-to-low transitions on ECI divided by 2 as the input clock (FCLKIN). 2 EXTOSCN Set the external oscillator module output (EXTOSCn) divided by 2 as the input clock (FCLKIN). 3 ECI Set ECI transitions divided by 2 as the input clock (FCLKIN). 4 HDOSEL High Drive Port Bank Output Select. 14 2 THREE_DIFF Select three differential outputs from Channels 3, 4, and 5 for the High Drive pins. 0 TWO_DIFF Select the differential outputs from Channels 4 and 5 and non-differential outputs from Channels 2 and 3 for the High Drive pins. 1 ONE_DIFF Select the differential output from Channel 5 and non-differential outputs from Channels 1-4 for the High Drive pins. 2 NO_DIFF Select the non-differential channel outputs (Channels 0-5) for the High Drive pins. 3 DEND DMA Write End Index. 16 3 LIMIT Set the last register in a DMA write transfer to LIMITUPD. 0 CH0 Set the last register in a DMA write transfer to Channel 0 CCAPVUPD. 1 CH1 Set the last register in a DMA write transfer to Channel 1 CCAPVUPD. 2 CH2 Set the last register in a DMA write transfer to Channel 2 CCAPVUPD. 3 CH3 Set the last register in a DMA write transfer to Channel 3 CCAPVUPD. 4 CH4 Set the last register in a DMA write transfer to Channel 4 CCAPVUPD. 5 CH5 Set the last register in a DMA write transfer to Channel 5 CCAPVUPD. 6 EMPTY Empty slot. 7 DPTR DMA Write Transfer Pointer. 19 3 LIMIT The DMA channel will write to LIMITUPD next. 0 CH0 The DMA channel will write to Channel 0 CCAPVUPD next. 1 CH1 The DMA channel will write to Channel 1 CCAPVUPD next. 2 CH2 The DMA channel will write to Channel 2 CCAPVUPD next. 3 CH3 The DMA channel will write to Channel 3 CCAPVUPD next. 4 CH4 The DMA channel will write to Channel 4 CCAPVUPD next. 5 CH5 The DMA channel will write to Channel 5 CCAPVUPD next. 6 EMPTY Empty slot. 7 DSTART DMA Target Start Index. 22 3 LIMIT Set the first register in a DMA write transfer to LIMITUPD. 0 CH0 Set the first register in a DMA write transfer to Channel 0 CCAPVUPD. 1 CH1 Set the first register in a DMA write transfer to Channel 1 CCAPVUPD. 2 CH2 Set the first register in a DMA write transfer to Channel 2 CCAPVUPD. 3 CH3 Set the first register in a DMA write transfer to Channel 3 CCAPVUPD. 4 CH4 Set the first register in a DMA write transfer to Channel 4 CCAPVUPD. 5 CH5 Set the first register in a DMA write transfer to Channel 5 CCAPVUPD. 6 EMPTY Empty slot. 7 DBUSYF DMA Busy Flag. 25 1 IDLE The DMA channel is not servicing an EPCA control transfer. 0 BUSY The DMA channel is busy servicing an EPCA control transfer. 1 STDOSEL Standard Port Bank Output Select. 27 2 NO_DIFF Select the non-differential channel outputs (Channels 0-5) for the standard PB pins. 0 ONE_DIFF Select the differential output from Channel 2 and non-differential outputs from Channels 0, 1, 3, and 4 for the standard PB pins. 1 TWO_DIFF Select the differential outputs from Channels 1 and 2 and non-differential outputs from Channels 0 and 3 for the standard PB pins. 2 THREE_DIFF Select three differential outputs from Channels 0, 1, and 2 for the standard PB pins. 3 CONTROL Module Control 0x190 0x00000000 0xFFFFFFFF OVFIEN EPCA Counter Overflow/Limit Interrupt Enable. 0 1 DISABLED Disable the EPCA counter overflow/limit event interrupt. 0 ENABLED Enable the EPCA counter overflow/limit event interrupt. 1 OVFDEN EPCA Counter Overflow/Limit DMA Request Enable. 1 1 DISABLED Do not request DMA data when a EPCA counter overflow/limit event occurs. 0 ENABLED Request DMA data when a EPCA counter overflow/limit event occurs. 1 OVFSEN EPCA Counter Overflow/Limit Synchronization Signal Enable. 2 1 DISABLED Do not send a synchronization signal when a EPCA counter overflow/limit event occurs. 0 ENABLED Send a synchronization signal when a EPCA counter overflow/limit event occurs. 1 HALTIEN EPCA Halt Input Interrupt Enable. 3 1 DISABLED Do not generate an interrupt if the EPCA halt input is high. 0 ENABLED Generate an interrupt if the EPCA halt input is high. 1 NOUPD Internal Register Update Inhibit. 4 1 INACTIVE The EPCA registers will automatically load any new update values after an overflow/limit event occurs. 0 ACTIVE The EPCA registers will not load any new update values after an overflow/limit event occurs. 1 IDLEBEN Idle Bypass Enable. 5 1 DISABLED The EPCA module will stop running when the core halts (idle). 0 ENABLED The EPCA module will continue normal operation when the core halts (idle). 1 DBGMD EPCA Debug Mode. 6 1 HALT A debug breakpoint will stop the EPCA counter/timer. 0 RUN The EPCA will continue to operate while the core is halted in debug mode. 1 HALTEN Halt Input Enable. 9 1 DISABLED The Halt input (PB_HDKill) does not affect the EPCA counter/timer. 0 ENABLED An assertion of the Halt input (PB_HDKill) will stop the EPCA counter/timer. 1 STSEL Synchronous Input Trigger Select. 11 2 EPCANT0 Select input trigger 0, EPCAnT0 (Comparator 0 Output). 0 EPCANT1 Select input trigger 1, EPCAnT1 (Comparator 1 Output). 1 EPCANT2 Select input trigger 2, EPCAnT2 (Timer 0 High Overflow ). 2 EPCANT3 Select input trigger 3, EPCAnT3 (Timer 1 High Overflow). 3 STESEL Synchronous Input Trigger Edge Select. 13 1 FALLING A high-to-low transition (falling edge) on EPCAnTx will start the counter/timer. 0 RISING A low-to-high transition (rising edge) on EPCAnTx will start the counter/timer. 1 STEN Synchronous Input Trigger Enable. 14 1 DISABLED Disable the input trigger (EPCAnTx). The EPCA counter/timer will continue to run if the RUN bit is set regardless of the value on the input trigger. 0 ENABLED Enable the input trigger (EPCAnTx). If RUN is set to 1, the EPCA counter/timer will start running when the selected input trigger (STSEL) meets the criteria set by STESEL. It will not stop running if the criteria is no longer met. 1 DIVST Clock Divider Output State. 21 1 OUTPUT_HIGH The clock divider is currently in the first half-cycle. 0 OUTPUT_LOW The clock divider is currently in the second half-cycle. 1 DIV Current Clock Divider Count. 22 10 STATUS Module Status 0x1a0 0x00000000 0xFFFFFFFF C0CCI Channel 0 Capture/Compare Interrupt Flag. 0 1 NOT_SET A Channel 0 match or capture event did not occur. 0 SET A Channel 0 match or capture event occurred. 1 C1CCI Channel 1 Capture/Compare Interrupt Flag. 1 1 NOT_SET A Channel 1 match or capture event did not occur. 0 SET A Channel 1 match or capture event occurred. 1 C2CCI Channel 2 Capture/Compare Interrupt Flag. 2 1 NOT_SET A Channel 2 match or capture event did not occur. 0 SET A Channel 2 match or capture event occurred. 1 C3CCI Channel 3 Capture/Compare Interrupt Flag. 3 1 NOT_SET A Channel 3 match or capture event did not occur. 0 SET A Channel 3 match or capture event occurred. 1 C4CCI Channel 4 Capture/Compare Interrupt Flag. 4 1 NOT_SET A Channel 4 match or capture event did not occur. 0 SET A Channel 4 match or capture event occurred. 1 C5CCI Channel 5 Capture/Compare Interrupt Flag. 5 1 NOT_SET A Channel 5 match or capture event did not occur. 0 SET A Channel 5 match or capture event occurred. 1 RUN Counter/Timer Run. 6 1 STOP Stop the EPCA Counter/Timer. 0 START Start the EPCA Counter/Timer. 1 OVFI Counter/Timer Overflow/Limit Interrupt Flag. 7 1 NOT_SET An EPCA Counter/Timer overflow/limit event did not occur. 0 SET An EPCA Counter/Timer overflow/limit event occurred. 1 UPDCF Register Update Complete Flag. 8 1 EMPTY An EPCA register update completed or is not pending. 0 FULL An EPCA register update has not completed and is still pending. 1 HALTI Halt Input Interrupt Flag. 9 1 NOT_SET The Halt input (PB_HDKill) was not asserted. 0 SET The Halt input (PB_HDKill) was asserted. 1 C0IOVFI Channel 0 Intermediate Overflow Interrupt Flag. 10 1 NOT_SET Channel 0 did not count past the channel n-bit mode limit. 0 SET Channel 0 counted past the channel n-bit mode limit. 1 C1IOVFI Channel 1 Intermediate Overflow Interrupt Flag. 11 1 NOT_SET Channel 1 did not count past the channel n-bit mode limit. 0 SET Channel 1 counted past the channel n-bit mode limit. 1 C2IOVFI Channel 2 Intermediate Overflow Interrupt Flag. 12 1 NOT_SET Channel 2 did not count past the channel n-bit mode limit. 0 SET Channel 2 counted past the channel n-bit mode limit. 1 C3IOVFI Channel 3 Intermediate Overflow Interrupt Flag. 13 1 NOT_SET Channel 3 did not count past the channel n-bit mode limit. 0 SET Channel 3 counted past the channel n-bit mode limit. 1 C4IOVFI Channel 4 Intermediate Overflow Interrupt Flag. 14 1 NOT_SET Channel 4 did not count past the channel n-bit mode limit. 0 SET Channel 4 counted past the channel n-bit mode limit. 1 C5IOVFI Channel 5 Intermediate Overflow Interrupt Flag. 15 1 NOT_SET Channel 5 did not count past the channel n-bit mode limit. 0 SET Channel 5 counted past the channel n-bit mode limit. 1 COUNTER Module Counter/Timer 0x1b0 0x00000000 0xFFFFFFFF COUNTER Counter/Timer. 0 16 LIMIT Module Upper Limit 0x1c0 0x0000FFFF 0xFFFFFFFF LIMIT Upper Limit. 0 16 LIMITUPD Module Upper Limit Update Value 0x1d0 0x00000000 0xFFFFFFFF LIMITUPD Module Upper Limit Update Value. 0 16 DTIME Phase Delay Time 0x1e0 0x00000000 0xFFFFFFFF DTIMEX X Phase Delay Time. 0 8 DTIMEY Y Phase Delay Time. 8 8 DTARGET DMA Transfer Target 0x200 0x00000000 0xFFFFFFFF DTARGET DMA Transfer Target. 0 32 write-only MODE_0 Channel Capture/Compare Mode 0x0 0x00000000 0xFFFFFFFF COSEL Channel Output Function Select. 0 2 TOGGLE_OUTPUT Toggle the channel output at the next capture/compare, overflow, or intermediate event. 0 SET_OUTPUT Set the channel output at the next capture/compare, overflow, or intermediate event. 1 CLEAR_OUTPUT Clear the output at the next capture/compare, overflow, or intermediate event. 2 NO_CHANGE Capture/Compare, overflow, or intermediate events do not control the output state. 3 PWMMD PWM N-Bit Mode. 2 4 DIFGEN Differential Signal Generator Enable. 6 1 DISABLED Disable the differential signal generator. The channel will output a single non-differential output. 0 ENABLED Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH). 1 CMD Channel Operating Mode. 8 3 EDGE_PWM Configure the channel for edge-aligned PWM mode. 0 CENTER_ALIGNED_PWM Configure the channel for center-aligned PWM mode. 1 HF_SQUARE_WAVE Configure the channel for high-frequency/square-wave mode. 2 TIMER_CAPTURE Configure the channel for timer/capture mode. 3 N_BIT_PWM Configure the channel for n-bit edge-aligned PWM mode. 4 CONTROL_0 Channel Capture/Compare Control 0x10 0x00000000 0xFFFFFFFF COUTST Channel Output State. 0 1 LOW The channel output state is low. 0 HIGH The channel output state is high. 1 CPCAPEN Positive Edge Input Capture Enable. 1 1 DISABLED Disable positive-edge input capture. 0 ENABLED Enable positive-edge input capture. 1 CNCAPEN Negative Edge Input Capture Enable. 2 1 DISABLED Disable negative-edge input capture. 0 ENABLED Enable negative-edge input capture. 1 CUPDCF Channel Register Update Complete Flag. 3 1 NOT_SET A EPCA channel register update completed or is not pending. 0 SET A EPCA channel register update has not completed and is still pending. 1 YPHST Differential Y Phase State. 5 1 LOW Set the Y Phase output state to low. 0 HIGH Set the Y Phase output state to high. 1 ACTIVEPH Active Channel Select. 6 1 YACTIVE The Y Phase is active and X Phase is inactive. 0 XACTIVE The X Phase is active and Y Phase is inactive. 1 XPHST Differential X Phase State. 7 1 LOW Set the X Phase output state to low. 0 HIGH Set the X Phase output state to high. 1 CCIEN Capture/Compare Interrupt Enable. 8 1 DISABLED Disable the channel capture/compare interrupt. 0 ENABLED Enable the channel capture/compare interrupt. 1 CCDEN Capture/Compare DMA Request Enable. 9 1 DISABLED Do not request DMA data when a channel capture/compare event occurs. 0 ENABLED Request DMA data when a channel capture/compare event occurs. 1 CCSEN Capture/Compare Synchronization Signal Enable. 10 1 DISABLED Do not send a synchronization signal when a channel capture/compare event occurs. 0 ENABLED Send a synchronization signal when a channel capture/compare event occurs. 1 CIOVFIEN Intermediate Overflow Interrupt Enable. 11 1 DISABLED Disable the channel intermediate overflow interrupt. 0 ENABLED Enable the channel intermediate overflow interrupt. 1 CIOVFDEN Intermediate Overflow DMA Request Enable. 12 1 DISABLED Do not request DMA data when a channel intermediate overflow event occurs. 0 ENABLED Request DMA data when a channel intermediate overflow event occurs. 1 CIOVFSEN Intermediate Overflow Synchronization Signal Enable. 13 1 DISABLED Do not send a synchronization signal when a channel intermediate overflow event occurs. 0 ENABLED Send a synchronization signal when a channel intermediate overflow occurs. 1 CCAPV_0 Channel Compare Value 0x20 0x00000000 0xFFFFFFFF CCAPV Channel Compare Value. 0 18 CCAPVUPD_0 Channel Compare Update Value 0x30 0x00000000 0xFFFFFFFF CCAPVUPD Channel Compare Update Value. 0 18 MODE_1 Channel Capture/Compare Mode 0x40 0x00000000 0xFFFFFFFF COSEL Channel Output Function Select. 0 2 TOGGLE_OUTPUT Toggle the channel output at the next capture/compare, overflow, or intermediate event. 0 SET_OUTPUT Set the channel output at the next capture/compare, overflow, or intermediate event. 1 CLEAR_OUTPUT Clear the output at the next capture/compare, overflow, or intermediate event. 2 NO_CHANGE Capture/Compare, overflow, or intermediate events do not control the output state. 3 PWMMD PWM N-Bit Mode. 2 4 DIFGEN Differential Signal Generator Enable. 6 1 DISABLED Disable the differential signal generator. The channel will output a single non-differential output. 0 ENABLED Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH). 1 CMD Channel Operating Mode. 8 3 EDGE_PWM Configure the channel for edge-aligned PWM mode. 0 CENTER_ALIGNED_PWM Configure the channel for center-aligned PWM mode. 1 HF_SQUARE_WAVE Configure the channel for high-frequency/square-wave mode. 2 TIMER_CAPTURE Configure the channel for timer/capture mode. 3 N_BIT_PWM Configure the channel for n-bit edge-aligned PWM mode. 4 CONTROL_1 Channel Capture/Compare Control 0x50 0x00000000 0xFFFFFFFF COUTST Channel Output State. 0 1 LOW The channel output state is low. 0 HIGH The channel output state is high. 1 CPCAPEN Positive Edge Input Capture Enable. 1 1 DISABLED Disable positive-edge input capture. 0 ENABLED Enable positive-edge input capture. 1 CNCAPEN Negative Edge Input Capture Enable. 2 1 DISABLED Disable negative-edge input capture. 0 ENABLED Enable negative-edge input capture. 1 CUPDCF Channel Register Update Complete Flag. 3 1 NOT_SET A EPCA channel register update completed or is not pending. 0 SET A EPCA channel register update has not completed and is still pending. 1 YPHST Differential Y Phase State. 5 1 LOW Set the Y Phase output state to low. 0 HIGH Set the Y Phase output state to high. 1 ACTIVEPH Active Channel Select. 6 1 YACTIVE The Y Phase is active and X Phase is inactive. 0 XACTIVE The X Phase is active and Y Phase is inactive. 1 XPHST Differential X Phase State. 7 1 LOW Set the X Phase output state to low. 0 HIGH Set the X Phase output state to high. 1 CCIEN Capture/Compare Interrupt Enable. 8 1 DISABLED Disable the channel capture/compare interrupt. 0 ENABLED Enable the channel capture/compare interrupt. 1 CCDEN Capture/Compare DMA Request Enable. 9 1 DISABLED Do not request DMA data when a channel capture/compare event occurs. 0 ENABLED Request DMA data when a channel capture/compare event occurs. 1 CCSEN Capture/Compare Synchronization Signal Enable. 10 1 DISABLED Do not send a synchronization signal when a channel capture/compare event occurs. 0 ENABLED Send a synchronization signal when a channel capture/compare event occurs. 1 CIOVFIEN Intermediate Overflow Interrupt Enable. 11 1 DISABLED Disable the channel intermediate overflow interrupt. 0 ENABLED Enable the channel intermediate overflow interrupt. 1 CIOVFDEN Intermediate Overflow DMA Request Enable. 12 1 DISABLED Do not request DMA data when a channel intermediate overflow event occurs. 0 ENABLED Request DMA data when a channel intermediate overflow event occurs. 1 CIOVFSEN Intermediate Overflow Synchronization Signal Enable. 13 1 DISABLED Do not send a synchronization signal when a channel intermediate overflow event occurs. 0 ENABLED Send a synchronization signal when a channel intermediate overflow occurs. 1 CCAPV_1 Channel Compare Value 0x60 0x00000000 0xFFFFFFFF CCAPV Channel Compare Value. 0 18 CCAPVUPD_1 Channel Compare Update Value 0x70 0x00000000 0xFFFFFFFF CCAPVUPD Channel Compare Update Value. 0 18 MODE_2 Channel Capture/Compare Mode 0x80 0x00000000 0xFFFFFFFF COSEL Channel Output Function Select. 0 2 TOGGLE_OUTPUT Toggle the channel output at the next capture/compare, overflow, or intermediate event. 0 SET_OUTPUT Set the channel output at the next capture/compare, overflow, or intermediate event. 1 CLEAR_OUTPUT Clear the output at the next capture/compare, overflow, or intermediate event. 2 NO_CHANGE Capture/Compare, overflow, or intermediate events do not control the output state. 3 PWMMD PWM N-Bit Mode. 2 4 DIFGEN Differential Signal Generator Enable. 6 1 DISABLED Disable the differential signal generator. The channel will output a single non-differential output. 0 ENABLED Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH). 1 CMD Channel Operating Mode. 8 3 EDGE_PWM Configure the channel for edge-aligned PWM mode. 0 CENTER_ALIGNED_PWM Configure the channel for center-aligned PWM mode. 1 HF_SQUARE_WAVE Configure the channel for high-frequency/square-wave mode. 2 TIMER_CAPTURE Configure the channel for timer/capture mode. 3 N_BIT_PWM Configure the channel for n-bit edge-aligned PWM mode. 4 CONTROL_2 Channel Capture/Compare Control 0x90 0x00000000 0xFFFFFFFF COUTST Channel Output State. 0 1 LOW The channel output state is low. 0 HIGH The channel output state is high. 1 CPCAPEN Positive Edge Input Capture Enable. 1 1 DISABLED Disable positive-edge input capture. 0 ENABLED Enable positive-edge input capture. 1 CNCAPEN Negative Edge Input Capture Enable. 2 1 DISABLED Disable negative-edge input capture. 0 ENABLED Enable negative-edge input capture. 1 CUPDCF Channel Register Update Complete Flag. 3 1 NOT_SET A EPCA channel register update completed or is not pending. 0 SET A EPCA channel register update has not completed and is still pending. 1 YPHST Differential Y Phase State. 5 1 LOW Set the Y Phase output state to low. 0 HIGH Set the Y Phase output state to high. 1 ACTIVEPH Active Channel Select. 6 1 YACTIVE The Y Phase is active and X Phase is inactive. 0 XACTIVE The X Phase is active and Y Phase is inactive. 1 XPHST Differential X Phase State. 7 1 LOW Set the X Phase output state to low. 0 HIGH Set the X Phase output state to high. 1 CCIEN Capture/Compare Interrupt Enable. 8 1 DISABLED Disable the channel capture/compare interrupt. 0 ENABLED Enable the channel capture/compare interrupt. 1 CCDEN Capture/Compare DMA Request Enable. 9 1 DISABLED Do not request DMA data when a channel capture/compare event occurs. 0 ENABLED Request DMA data when a channel capture/compare event occurs. 1 CCSEN Capture/Compare Synchronization Signal Enable. 10 1 DISABLED Do not send a synchronization signal when a channel capture/compare event occurs. 0 ENABLED Send a synchronization signal when a channel capture/compare event occurs. 1 CIOVFIEN Intermediate Overflow Interrupt Enable. 11 1 DISABLED Disable the channel intermediate overflow interrupt. 0 ENABLED Enable the channel intermediate overflow interrupt. 1 CIOVFDEN Intermediate Overflow DMA Request Enable. 12 1 DISABLED Do not request DMA data when a channel intermediate overflow event occurs. 0 ENABLED Request DMA data when a channel intermediate overflow event occurs. 1 CIOVFSEN Intermediate Overflow Synchronization Signal Enable. 13 1 DISABLED Do not send a synchronization signal when a channel intermediate overflow event occurs. 0 ENABLED Send a synchronization signal when a channel intermediate overflow occurs. 1 CCAPV_2 Channel Compare Value 0xa0 0x00000000 0xFFFFFFFF CCAPV Channel Compare Value. 0 18 CCAPVUPD_2 Channel Compare Update Value 0xb0 0x00000000 0xFFFFFFFF CCAPVUPD Channel Compare Update Value. 0 18 MODE_3 Channel Capture/Compare Mode 0xc0 0x00000000 0xFFFFFFFF COSEL Channel Output Function Select. 0 2 TOGGLE_OUTPUT Toggle the channel output at the next capture/compare, overflow, or intermediate event. 0 SET_OUTPUT Set the channel output at the next capture/compare, overflow, or intermediate event. 1 CLEAR_OUTPUT Clear the output at the next capture/compare, overflow, or intermediate event. 2 NO_CHANGE Capture/Compare, overflow, or intermediate events do not control the output state. 3 PWMMD PWM N-Bit Mode. 2 4 DIFGEN Differential Signal Generator Enable. 6 1 DISABLED Disable the differential signal generator. The channel will output a single non-differential output. 0 ENABLED Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH). 1 CMD Channel Operating Mode. 8 3 EDGE_PWM Configure the channel for edge-aligned PWM mode. 0 CENTER_ALIGNED_PWM Configure the channel for center-aligned PWM mode. 1 HF_SQUARE_WAVE Configure the channel for high-frequency/square-wave mode. 2 TIMER_CAPTURE Configure the channel for timer/capture mode. 3 N_BIT_PWM Configure the channel for n-bit edge-aligned PWM mode. 4 CONTROL_3 Channel Capture/Compare Control 0xd0 0x00000000 0xFFFFFFFF COUTST Channel Output State. 0 1 LOW The channel output state is low. 0 HIGH The channel output state is high. 1 CPCAPEN Positive Edge Input Capture Enable. 1 1 DISABLED Disable positive-edge input capture. 0 ENABLED Enable positive-edge input capture. 1 CNCAPEN Negative Edge Input Capture Enable. 2 1 DISABLED Disable negative-edge input capture. 0 ENABLED Enable negative-edge input capture. 1 CUPDCF Channel Register Update Complete Flag. 3 1 NOT_SET A EPCA channel register update completed or is not pending. 0 SET A EPCA channel register update has not completed and is still pending. 1 YPHST Differential Y Phase State. 5 1 LOW Set the Y Phase output state to low. 0 HIGH Set the Y Phase output state to high. 1 ACTIVEPH Active Channel Select. 6 1 YACTIVE The Y Phase is active and X Phase is inactive. 0 XACTIVE The X Phase is active and Y Phase is inactive. 1 XPHST Differential X Phase State. 7 1 LOW Set the X Phase output state to low. 0 HIGH Set the X Phase output state to high. 1 CCIEN Capture/Compare Interrupt Enable. 8 1 DISABLED Disable the channel capture/compare interrupt. 0 ENABLED Enable the channel capture/compare interrupt. 1 CCDEN Capture/Compare DMA Request Enable. 9 1 DISABLED Do not request DMA data when a channel capture/compare event occurs. 0 ENABLED Request DMA data when a channel capture/compare event occurs. 1 CCSEN Capture/Compare Synchronization Signal Enable. 10 1 DISABLED Do not send a synchronization signal when a channel capture/compare event occurs. 0 ENABLED Send a synchronization signal when a channel capture/compare event occurs. 1 CIOVFIEN Intermediate Overflow Interrupt Enable. 11 1 DISABLED Disable the channel intermediate overflow interrupt. 0 ENABLED Enable the channel intermediate overflow interrupt. 1 CIOVFDEN Intermediate Overflow DMA Request Enable. 12 1 DISABLED Do not request DMA data when a channel intermediate overflow event occurs. 0 ENABLED Request DMA data when a channel intermediate overflow event occurs. 1 CIOVFSEN Intermediate Overflow Synchronization Signal Enable. 13 1 DISABLED Do not send a synchronization signal when a channel intermediate overflow event occurs. 0 ENABLED Send a synchronization signal when a channel intermediate overflow occurs. 1 CCAPV_3 Channel Compare Value 0xe0 0x00000000 0xFFFFFFFF CCAPV Channel Compare Value. 0 18 CCAPVUPD_3 Channel Compare Update Value 0xf0 0x00000000 0xFFFFFFFF CCAPVUPD Channel Compare Update Value. 0 18 MODE_4 Channel Capture/Compare Mode 0x100 0x00000000 0xFFFFFFFF COSEL Channel Output Function Select. 0 2 TOGGLE_OUTPUT Toggle the channel output at the next capture/compare, overflow, or intermediate event. 0 SET_OUTPUT Set the channel output at the next capture/compare, overflow, or intermediate event. 1 CLEAR_OUTPUT Clear the output at the next capture/compare, overflow, or intermediate event. 2 NO_CHANGE Capture/Compare, overflow, or intermediate events do not control the output state. 3 PWMMD PWM N-Bit Mode. 2 4 DIFGEN Differential Signal Generator Enable. 6 1 DISABLED Disable the differential signal generator. The channel will output a single non-differential output. 0 ENABLED Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH). 1 CMD Channel Operating Mode. 8 3 EDGE_PWM Configure the channel for edge-aligned PWM mode. 0 CENTER_ALIGNED_PWM Configure the channel for center-aligned PWM mode. 1 HF_SQUARE_WAVE Configure the channel for high-frequency/square-wave mode. 2 TIMER_CAPTURE Configure the channel for timer/capture mode. 3 N_BIT_PWM Configure the channel for n-bit edge-aligned PWM mode. 4 CONTROL_4 Channel Capture/Compare Control 0x110 0x00000000 0xFFFFFFFF COUTST Channel Output State. 0 1 LOW The channel output state is low. 0 HIGH The channel output state is high. 1 CPCAPEN Positive Edge Input Capture Enable. 1 1 DISABLED Disable positive-edge input capture. 0 ENABLED Enable positive-edge input capture. 1 CNCAPEN Negative Edge Input Capture Enable. 2 1 DISABLED Disable negative-edge input capture. 0 ENABLED Enable negative-edge input capture. 1 CUPDCF Channel Register Update Complete Flag. 3 1 NOT_SET A EPCA channel register update completed or is not pending. 0 SET A EPCA channel register update has not completed and is still pending. 1 YPHST Differential Y Phase State. 5 1 LOW Set the Y Phase output state to low. 0 HIGH Set the Y Phase output state to high. 1 ACTIVEPH Active Channel Select. 6 1 YACTIVE The Y Phase is active and X Phase is inactive. 0 XACTIVE The X Phase is active and Y Phase is inactive. 1 XPHST Differential X Phase State. 7 1 LOW Set the X Phase output state to low. 0 HIGH Set the X Phase output state to high. 1 CCIEN Capture/Compare Interrupt Enable. 8 1 DISABLED Disable the channel capture/compare interrupt. 0 ENABLED Enable the channel capture/compare interrupt. 1 CCDEN Capture/Compare DMA Request Enable. 9 1 DISABLED Do not request DMA data when a channel capture/compare event occurs. 0 ENABLED Request DMA data when a channel capture/compare event occurs. 1 CCSEN Capture/Compare Synchronization Signal Enable. 10 1 DISABLED Do not send a synchronization signal when a channel capture/compare event occurs. 0 ENABLED Send a synchronization signal when a channel capture/compare event occurs. 1 CIOVFIEN Intermediate Overflow Interrupt Enable. 11 1 DISABLED Disable the channel intermediate overflow interrupt. 0 ENABLED Enable the channel intermediate overflow interrupt. 1 CIOVFDEN Intermediate Overflow DMA Request Enable. 12 1 DISABLED Do not request DMA data when a channel intermediate overflow event occurs. 0 ENABLED Request DMA data when a channel intermediate overflow event occurs. 1 CIOVFSEN Intermediate Overflow Synchronization Signal Enable. 13 1 DISABLED Do not send a synchronization signal when a channel intermediate overflow event occurs. 0 ENABLED Send a synchronization signal when a channel intermediate overflow occurs. 1 CCAPV_4 Channel Compare Value 0x120 0x00000000 0xFFFFFFFF CCAPV Channel Compare Value. 0 18 CCAPVUPD_4 Channel Compare Update Value 0x130 0x00000000 0xFFFFFFFF CCAPVUPD Channel Compare Update Value. 0 18 MODE_5 Channel Capture/Compare Mode 0x140 0x00000000 0xFFFFFFFF COSEL Channel Output Function Select. 0 2 TOGGLE_OUTPUT Toggle the channel output at the next capture/compare, overflow, or intermediate event. 0 SET_OUTPUT Set the channel output at the next capture/compare, overflow, or intermediate event. 1 CLEAR_OUTPUT Clear the output at the next capture/compare, overflow, or intermediate event. 2 NO_CHANGE Capture/Compare, overflow, or intermediate events do not control the output state. 3 PWMMD PWM N-Bit Mode. 2 4 DIFGEN Differential Signal Generator Enable. 6 1 DISABLED Disable the differential signal generator. The channel will output a single non-differential output. 0 ENABLED Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH). 1 CMD Channel Operating Mode. 8 3 EDGE_PWM Configure the channel for edge-aligned PWM mode. 0 CENTER_ALIGNED_PWM Configure the channel for center-aligned PWM mode. 1 HF_SQUARE_WAVE Configure the channel for high-frequency/square-wave mode. 2 TIMER_CAPTURE Configure the channel for timer/capture mode. 3 N_BIT_PWM Configure the channel for n-bit edge-aligned PWM mode. 4 CONTROL_5 Channel Capture/Compare Control 0x150 0x00000000 0xFFFFFFFF COUTST Channel Output State. 0 1 LOW The channel output state is low. 0 HIGH The channel output state is high. 1 CPCAPEN Positive Edge Input Capture Enable. 1 1 DISABLED Disable positive-edge input capture. 0 ENABLED Enable positive-edge input capture. 1 CNCAPEN Negative Edge Input Capture Enable. 2 1 DISABLED Disable negative-edge input capture. 0 ENABLED Enable negative-edge input capture. 1 CUPDCF Channel Register Update Complete Flag. 3 1 NOT_SET A EPCA channel register update completed or is not pending. 0 SET A EPCA channel register update has not completed and is still pending. 1 YPHST Differential Y Phase State. 5 1 LOW Set the Y Phase output state to low. 0 HIGH Set the Y Phase output state to high. 1 ACTIVEPH Active Channel Select. 6 1 YACTIVE The Y Phase is active and X Phase is inactive. 0 XACTIVE The X Phase is active and Y Phase is inactive. 1 XPHST Differential X Phase State. 7 1 LOW Set the X Phase output state to low. 0 HIGH Set the X Phase output state to high. 1 CCIEN Capture/Compare Interrupt Enable. 8 1 DISABLED Disable the channel capture/compare interrupt. 0 ENABLED Enable the channel capture/compare interrupt. 1 CCDEN Capture/Compare DMA Request Enable. 9 1 DISABLED Do not request DMA data when a channel capture/compare event occurs. 0 ENABLED Request DMA data when a channel capture/compare event occurs. 1 CCSEN Capture/Compare Synchronization Signal Enable. 10 1 DISABLED Do not send a synchronization signal when a channel capture/compare event occurs. 0 ENABLED Send a synchronization signal when a channel capture/compare event occurs. 1 CIOVFIEN Intermediate Overflow Interrupt Enable. 11 1 DISABLED Disable the channel intermediate overflow interrupt. 0 ENABLED Enable the channel intermediate overflow interrupt. 1 CIOVFDEN Intermediate Overflow DMA Request Enable. 12 1 DISABLED Do not request DMA data when a channel intermediate overflow event occurs. 0 ENABLED Request DMA data when a channel intermediate overflow event occurs. 1 CIOVFSEN Intermediate Overflow Synchronization Signal Enable. 13 1 DISABLED Do not send a synchronization signal when a channel intermediate overflow event occurs. 0 ENABLED Send a synchronization signal when a channel intermediate overflow occurs. 1 CCAPV_5 Channel Compare Value 0x160 0x00000000 0xFFFFFFFF CCAPV Channel Compare Value. 0 18 CCAPVUPD_5 Channel Compare Update Value 0x170 0x00000000 0xFFFFFFFF CCAPVUPD Channel Compare Update Value. 0 18 FLASHCTRL_0 A None FLASHCTRL_0 0x4002e000 0x0 0xffc registers CONFIG Controller Configuration 0x0 0x00000720 0xFFFFFFFF SPMD Flash Speed Mode. 0 2 MODE0 Read and write the Flash at speed mode 0. 0 MODE1 Read and write the Flash at speed mode 1. 1 MODE2 Read and write the Flash at speed mode 2. 2 MODE3 Read and write the Flash at speed mode 3. 3 RDSEN Read Store Mode Enable. 4 1 DISABLED Disable read store mode. 0 ENABLED Enable read store mode. 1 DPFEN Data Prefetch Enable. 6 1 DISABLED Data accesses are excluded from the prefetch buffer. 0 ENABLED Data accesses are included in the prefetch buffer. 1 PFINH Prefetch Inhibit. 7 1 INACTIVE Any reads from Flash are prefetched until the prefetch buffer is full. 0 ACTIVE Inhibit the prefetch engine. 1 SQWEN Flash Write Sequence Enable. 16 1 DISABLED Disable sequential write mode. 0 ENABLED Enable sequential write mode. 1 ERASEEN Flash Page Erase Enable. 18 1 DISABLED Writes to the WRDATA field will initiate a write to Flash at the address in the WRADDR field. 0 ENABLED Writes to the WRDATA field will initiate an erase of the Flash page containing the address in the WRADDR field. 1 BUFSTS Flash Buffer Status. 19 1 read-only EMPTY The Flash controller write data buffer is empty. 0 FULL The Flash controller write data buffer is full. 1 BUSYF Flash Operation Busy Flag. 20 1 read-only NOT_SET The Flash interface is not busy. 0 SET The Flash interface is busy with an operation. 1 WRADDR Flash Write Address 0xa0 0x00000000 0xFFFFFFFF WRADDR Flash Write Address. 0 32 WRDATA Flash Write Data 0xb0 0x00000000 0xFFFFFFFF WRDATA Flash Write Data. 0 32 write-only KEY Flash Modification Key 0xc0 0x00000000 0xFFFFFFFF KEY Flash Key. 0 8 MULTI_LOCK 90 INITIAL_UNLOCK 165 SINGLE_UNLOCK 241 MULTI_UNLOCK 242 TCONTROL Flash Timing Control 0xd0 0x0003005C 0xFFFFFFFF FLRTMD Flash Read Timing Mode. 6 1 SLOW Configure the Flash read controller for AHB clocks below 20 MHz. 0 FAST Configure the Flash read controller for AHB clocks above 20 MHz. 1 I2C_0 A None I2C 0x40009000 0x0 0xffc registers I2C0_IRQn 32 CONTROL Module Control 0x0 0x10000000 0xFFFFFFFF BUSYF Busy Flag. 0 1 read-only NOT_SET A transaction is not currently taking place. 0 SET A transaction is currently taking place. 1 ACK Acknowledge. 1 1 NOT_SET Read: ACK has not been received. Write: Do not send an ACK. 0 SET Read: ACK received. Write: Send an ACK. 1 ARBLF Arbitration Lost Flag. 2 1 read-only NOT_SET Arbitration lost error has not occurred. 0 SET Arbitration lost error occurred. 1 ACKRQF Acknowledge Request Flag. 3 1 read-only NOT_SET ACK has not been requested. 0 SET ACK requested. 1 STO Stop. 4 1 NOT_SET Read: A stop is not pending and a stop / repeat start has not been detected. Write: Clear the STO bit. 0 SET Read: Stop or stop / repeat start detected. This bit must be cleared by firmware. Write: Generate a stop. 1 STA Start. 5 1 NOT_SET Read: A start is not pending and a repeat start has not been detected. Write: Clear the STA bit. 0 SET Read: Start or repeat start detected. This bit must be cleared by firmware. Write: Generate a start or repeat start. 1 TXMDF Transmit Mode Flag. 6 1 read-only RECEIVE Module is in receiver mode. 0 TRANSMIT Module is in transmitter mode. 1 MSMDF Master/Slave Mode Flag. 7 1 read-only SLAVE Module is operating in Slave mode. 0 MASTER Module is operating in Master mode. 1 STOI Stop Interrupt Flag. 8 1 NOT_SET Read: A stop interrupt has not occurred. Write: Clear the stop interrupt flag (STOI). 0 SET Read: Stop interrupt detected. In Slave mode, a stop has been detected on the bus. In Master mode, a stop has been generated. Write: Force a stop interrupt. 1 ACKI Acknowledge Interrupt Flag. 9 1 NOT_SET Read: An acknowledge interrupt has not occurred. Write: Clear the acknowledge interrupt (ACKI). 0 SET Read: An acknowledge interrupt occurred. Write: Force an acknowledge interrupt. 1 RXI Receive Done Interrupt Flag. 10 1 NOT_SET Read: A receive done interrupt has not occurred. Write: Clear the receive done interrupt (RXI). 0 SET Read: Receive done interrupt occurred. Write: Force a receive done interrupt. 1 TXI Transmit Done Interrupt Flag. 11 1 NOT_SET Read: A transmit done interrupt has not occurred. Write: Clear the transmit done interrupt (TXI). 0 SET Read: Transmit done interrupt detected. If the transmit is forced to abort by a NACK response, the acknowledge interrupt (ACKI) will also be set. Write: Force a transmit done interrupt. 1 STAI Start Interrupt Flag. 12 1 NOT_SET Read: Start interrupt has not occurred. Write: Clear the start interrupt (STAI). 0 SET Read: Start or repeat start interrupt occurred. In Slave mode, a start or repeat start is detected. In Master mode, a start or repeat start has been generated. 1 ARBLI Arbitration Lost Interrupt Flag. 13 1 NOT_SET Read: An arbitration lost interrupt has not occurred. Write: Clear the arbitration lost interrupt (ARBLI). 0 SET Read: Arbitration lost interrupt detected. Write: Force an arbitration lost interrupt. 1 T0I I2C Timer Byte 0 Interrupt Flag. 14 1 NOT_SET Read: A I2C Timer Byte 0 interrupt has not occurred. Write: Clear the I2C Timer Byte 0 interrupt (T0I). 0 SET Read: I2C Timer Byte 0 overflow interrupt detected. Write: Force a I2C Timer Byte 0 interrupt. 1 T1I I2C Timer Byte 1 Interrupt Flag. 15 1 NOT_SET Read: No interrupt occurred. Write: Clear the I2C Timer Byte 1 interrupt (T1I). 0 SET Read: I2C Timer Byte 1 overflow interrupt is detected. Write: Force a I2C Timer Byte 1 interrupt. 1 T2I I2C Timer Byte 2 Interrupt Flag. 16 1 NOT_SET Read: A I2C Timer Byte 2 interrupt has not occurred. Write: Clear the I2C Timer Byte 2 interrupt (T2I). 0 SET Read: I2C Timer Byte 2 overflow interrupt detected. Write: Force a I2C Timer Byte 2 interrupt. 1 T3I I2C Timer Byte 3 Interrupt Flag. 17 1 NOT_SET Read: A I2C Timer Byte 3 interrupt or SCL low timeout has not occurred. Write: Clear the I2C Timer Byte 3 interrupt (T3I). 0 SET Read: I2C Timer Byte 3 overflow or SCL low timeout interrupt detected. Write: Force a I2C Timer Byte 3 interrupt. 1 RXARM Receive Arm. 18 1 DISABLED Disable data and address reception. 0 ENABLED Enable the module to perform a receive operation. 1 TXARM Transmit Arm. 19 1 DISABLED Disable data and address transmission. 0 ENABLED Enable the module to perform a transmit operation. 1 SLVAF Slave Address Type Flag. 20 1 read-only SLAVE_ADDRESS Slave address detected. 0 GENERAL_CALL General Call address detected. 1 ATXRXEN Auto Transmit or Receive Enable. 21 1 DISABLED Do not automatically switch to transmit or receive mode after a Start. 0 ENABLED If automatic hardware acknowledge mode is enabled (HACKEN = 1), automatically switch to transmit or receive mode after a Start. 1 FMD Filter Mode. 22 1 DISABLED Disable the input filter. 0 ENABLED Enable the input filter. 1 DBGMD I2C Debug Mode. 23 1 RUN The I2C module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the I2C module to halt. 1 SMINH Slave Mode Inhibit. 24 1 INACTIVE Enable Slave modes. 0 ACTIVE Inhibit Slave modes. The module will not respond to a Master on the bus. 1 HACKEN Auto Acknowledge Enable . 25 1 DISABLED Disable automatic hardware acknowledge. 0 ENABLED Enable automatic hardware acknowledge. 1 SLVAMD Slave Address Mode. 26 1 7BIT Slave addresses are 7 bits. 0 10BIT Slave addresses are 10 bits. 1 LBACKEN Last Byte Acknowledge Enable. 27 1 DISABLED NACK after the last byte is received. 0 ENABLED ACK after the last byte is received. 1 GCEN General Call Address Enable. 29 1 DISABLED Disable General Call address decoding. 0 ENABLED Enable General Call address decoding. 1 RESET Module Soft Reset. 30 1 INACTIVE I2C module is not in soft reset. 0 ACTIVE I2C module is in soft reset and firmware cannot access all bits in the module. 1 I2CEN I2C Enable. 31 1 DISABLED Disable the I2C module. 0 ENABLED Enable the I2C module. 1 CONFIG Module Configuration 0x10 0x00000000 0xFFFFFFFF SCALER I2C Clock Scaler. 0 6 STOIEN Stop Interrupt Enable. 8 1 DISABLED Disable the stop interrupt. 0 ENABLED Enable the stop interrupt (STOI). 1 ACKIEN Acknowledge Interrupt Enable. 9 1 DISABLED Disable the acknowledge interrupt. 0 ENABLED Enable the acknowledge interrupt (ACKI). 1 RXIEN Receive Done Interrupt Enable. 10 1 DISABLED Disable the receive done interrupt. 0 ENABLED Enable the receive done interrupt (RXI). 1 TXIEN Transmit Done Interrupt Enable. 11 1 DISABLED Disable the transmit done interrupt. 0 ENABLED Enable the transmit done interrupt (TXI). 1 STAIEN Start Interrupt Enable. 12 1 DISABLED Disable the start interrupt. 0 ENABLED Enable the start interrupt (STAI). 1 ARBLIEN Arbitration Lost Interrupt Enable. 13 1 DISABLED Disable the arbitration lost interrupt. 0 ENABLED Enable the arbitration lost interrupt (ARBLI). 1 T0IEN I2C Timer Byte 0 Interrupt Enable. 14 1 DISABLED Disable the I2C Timer Byte 0 interrupt. 0 ENABLED Enable the I2C Timer Byte 0 interrupt (T0I). 1 T1IEN I2C Timer Byte 1 Interrupt Enable. 15 1 DISABLED Disable the I2C Timer Byte 1 interrupt. 0 ENABLED Enable the I2C Timer Byte 1 interrupt (T1I). 1 T2IEN I2C Timer Byte 2 Interrupt Enable. 16 1 DISABLED Disable the I2C Timer Byte 2 interrupt. 0 ENABLED Enable the I2C Timer Byte 2 interrupt (T2I). 1 T3IEN I2C Timer Byte 3 Interrupt Enable. 17 1 DISABLED Disable the I2C Timer Byte 3 and SCL low timeout interrupt. 0 ENABLED Enable the I2C Timer Byte 3 and SCL low timeout interrupt (T3I). 1 BC Transfer Byte Count. 20 2 BP Transfer Byte Pointer. 22 2 read-only T0RUN I2C Timer Byte 0 Run. 24 1 STOP Stop Timer Byte 0. 0 START Start Timer Byte 0 running. 1 T1RUN I2C Timer Byte 1 Run. 25 1 STOP Stop Timer Byte 1. 0 START Start Timer Byte 1 running. 1 T2RUN I2C Timer Byte 2 Run. 26 1 STOP Stop Timer Byte 2. 0 START Start Timer Byte 2 running. 1 T3RUN I2C Timer Byte 3 Run. 27 1 STOP Stop Timer Byte 3. 0 START Start Timer Byte 3 running. 1 TMD I2C Timer Mode. 28 2 MODE0 I2C Timer Mode 0: Operate the I2C timer as a single 32-bit timer : Timer Bytes [3 : 2 : 1 : 0]. 0 MODE1 I2C Timer Mode 1: Operate the I2C timer as two 16-bit timers : Timer Bytes [3 : 2] and Timer Bytes [1 : 0]. 1 MODE2 I2C Timer Mode 2: Operate the I2C timer as four independent 8-bit timers : Timer Byte 3, Timer Byte 2, Timer Byte 1, and Timer Byte 0. 2 MODE3 I2C Timer Mode 3: Operate the I2C timer as one 16-bit and two 8-bit timers : Timer Bytes [3 : 2], Timer Byte 1, and Timer Byte 0. 3 TIMEREN I2C Timer Enable. 31 1 DISABLED Disable I2C Timer. 0 ENABLED Enable I2C Timer for general purpose use. This setting should not be used when the I2C module is enabled (I2CEN = 1). 1 SADDRESS Slave Address 0x20 0x00000000 0xFFFFFFFF ADDRESS Slave Address. 1 10 SMASK Slave Address Mask 0x30 0x00000000 0xFFFFFFFF MASK Slave Address Mask. 1 10 DATA Data Buffer Access 0x40 0x00000000 0xFFFFFFFF DATA Data. 0 32 TIMER Timer Data 0x50 0x00000000 0xFFFFFFFF T0 Timer Byte 0. 0 8 T1 Timer Byte 1. 8 8 T2 Timer Byte 2. 16 8 T3 Timer Byte 3. 24 8 TIMERRL Timer Reload Values 0x60 0x00000000 0xFFFFFFFF T0RL Timer Byte 0 Reload Value. 0 8 T1RL Timer Byte 1 Reload Value. 8 8 T2RL Timer Byte 2 Reload Value. 16 8 T3RL Timer Byte 3 Reload Value. 24 8 SCONFIG SCL Signal Configuration 0x70 0x00000000 0xFFFFFFFF SETUP Data Setup Time Extension. 0 4 HOLD Data Hold Time Extension. 4 4 SCLL SCL Low Time Extension. 8 8 SCLLTIMER SCL Low Timer Bits [3:0]. 16 4 read-only I2CDMA DMA Configuration 0x80 0x00000000 0xFFFFFFFF DMALEN DMA Transfer Length. 0 8 DMAEN DMA Mode Enable. 31 1 DISABLED Disable I2C DMA data requests. 0 ENABLED Enable I2C DMA data requests. 1 I2C_1 A None I2C 0x4000a000 0x0 0xffc registers I2C1_IRQn 33 CONTROL Module Control 0x0 0x10000000 0xFFFFFFFF BUSYF Busy Flag. 0 1 read-only NOT_SET A transaction is not currently taking place. 0 SET A transaction is currently taking place. 1 ACK Acknowledge. 1 1 NOT_SET Read: ACK has not been received. Write: Do not send an ACK. 0 SET Read: ACK received. Write: Send an ACK. 1 ARBLF Arbitration Lost Flag. 2 1 read-only NOT_SET Arbitration lost error has not occurred. 0 SET Arbitration lost error occurred. 1 ACKRQF Acknowledge Request Flag. 3 1 read-only NOT_SET ACK has not been requested. 0 SET ACK requested. 1 STO Stop. 4 1 NOT_SET Read: A stop is not pending and a stop / repeat start has not been detected. Write: Clear the STO bit. 0 SET Read: Stop or stop / repeat start detected. This bit must be cleared by firmware. Write: Generate a stop. 1 STA Start. 5 1 NOT_SET Read: A start is not pending and a repeat start has not been detected. Write: Clear the STA bit. 0 SET Read: Start or repeat start detected. This bit must be cleared by firmware. Write: Generate a start or repeat start. 1 TXMDF Transmit Mode Flag. 6 1 read-only RECEIVE Module is in receiver mode. 0 TRANSMIT Module is in transmitter mode. 1 MSMDF Master/Slave Mode Flag. 7 1 read-only SLAVE Module is operating in Slave mode. 0 MASTER Module is operating in Master mode. 1 STOI Stop Interrupt Flag. 8 1 NOT_SET Read: A stop interrupt has not occurred. Write: Clear the stop interrupt flag (STOI). 0 SET Read: Stop interrupt detected. In Slave mode, a stop has been detected on the bus. In Master mode, a stop has been generated. Write: Force a stop interrupt. 1 ACKI Acknowledge Interrupt Flag. 9 1 NOT_SET Read: An acknowledge interrupt has not occurred. Write: Clear the acknowledge interrupt (ACKI). 0 SET Read: An acknowledge interrupt occurred. Write: Force an acknowledge interrupt. 1 RXI Receive Done Interrupt Flag. 10 1 NOT_SET Read: A receive done interrupt has not occurred. Write: Clear the receive done interrupt (RXI). 0 SET Read: Receive done interrupt occurred. Write: Force a receive done interrupt. 1 TXI Transmit Done Interrupt Flag. 11 1 NOT_SET Read: A transmit done interrupt has not occurred. Write: Clear the transmit done interrupt (TXI). 0 SET Read: Transmit done interrupt detected. If the transmit is forced to abort by a NACK response, the acknowledge interrupt (ACKI) will also be set. Write: Force a transmit done interrupt. 1 STAI Start Interrupt Flag. 12 1 NOT_SET Read: Start interrupt has not occurred. Write: Clear the start interrupt (STAI). 0 SET Read: Start or repeat start interrupt occurred. In Slave mode, a start or repeat start is detected. In Master mode, a start or repeat start has been generated. 1 ARBLI Arbitration Lost Interrupt Flag. 13 1 NOT_SET Read: An arbitration lost interrupt has not occurred. Write: Clear the arbitration lost interrupt (ARBLI). 0 SET Read: Arbitration lost interrupt detected. Write: Force an arbitration lost interrupt. 1 T0I I2C Timer Byte 0 Interrupt Flag. 14 1 NOT_SET Read: A I2C Timer Byte 0 interrupt has not occurred. Write: Clear the I2C Timer Byte 0 interrupt (T0I). 0 SET Read: I2C Timer Byte 0 overflow interrupt detected. Write: Force a I2C Timer Byte 0 interrupt. 1 T1I I2C Timer Byte 1 Interrupt Flag. 15 1 NOT_SET Read: No interrupt occurred. Write: Clear the I2C Timer Byte 1 interrupt (T1I). 0 SET Read: I2C Timer Byte 1 overflow interrupt is detected. Write: Force a I2C Timer Byte 1 interrupt. 1 T2I I2C Timer Byte 2 Interrupt Flag. 16 1 NOT_SET Read: A I2C Timer Byte 2 interrupt has not occurred. Write: Clear the I2C Timer Byte 2 interrupt (T2I). 0 SET Read: I2C Timer Byte 2 overflow interrupt detected. Write: Force a I2C Timer Byte 2 interrupt. 1 T3I I2C Timer Byte 3 Interrupt Flag. 17 1 NOT_SET Read: A I2C Timer Byte 3 interrupt or SCL low timeout has not occurred. Write: Clear the I2C Timer Byte 3 interrupt (T3I). 0 SET Read: I2C Timer Byte 3 overflow or SCL low timeout interrupt detected. Write: Force a I2C Timer Byte 3 interrupt. 1 RXARM Receive Arm. 18 1 DISABLED Disable data and address reception. 0 ENABLED Enable the module to perform a receive operation. 1 TXARM Transmit Arm. 19 1 DISABLED Disable data and address transmission. 0 ENABLED Enable the module to perform a transmit operation. 1 SLVAF Slave Address Type Flag. 20 1 read-only SLAVE_ADDRESS Slave address detected. 0 GENERAL_CALL General Call address detected. 1 ATXRXEN Auto Transmit or Receive Enable. 21 1 DISABLED Do not automatically switch to transmit or receive mode after a Start. 0 ENABLED If automatic hardware acknowledge mode is enabled (HACKEN = 1), automatically switch to transmit or receive mode after a Start. 1 FMD Filter Mode. 22 1 DISABLED Disable the input filter. 0 ENABLED Enable the input filter. 1 DBGMD I2C Debug Mode. 23 1 RUN The I2C module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the I2C module to halt. 1 SMINH Slave Mode Inhibit. 24 1 INACTIVE Enable Slave modes. 0 ACTIVE Inhibit Slave modes. The module will not respond to a Master on the bus. 1 HACKEN Auto Acknowledge Enable . 25 1 DISABLED Disable automatic hardware acknowledge. 0 ENABLED Enable automatic hardware acknowledge. 1 SLVAMD Slave Address Mode. 26 1 7BIT Slave addresses are 7 bits. 0 10BIT Slave addresses are 10 bits. 1 LBACKEN Last Byte Acknowledge Enable. 27 1 DISABLED NACK after the last byte is received. 0 ENABLED ACK after the last byte is received. 1 GCEN General Call Address Enable. 29 1 DISABLED Disable General Call address decoding. 0 ENABLED Enable General Call address decoding. 1 RESET Module Soft Reset. 30 1 INACTIVE I2C module is not in soft reset. 0 ACTIVE I2C module is in soft reset and firmware cannot access all bits in the module. 1 I2CEN I2C Enable. 31 1 DISABLED Disable the I2C module. 0 ENABLED Enable the I2C module. 1 CONFIG Module Configuration 0x10 0x00000000 0xFFFFFFFF SCALER I2C Clock Scaler. 0 6 STOIEN Stop Interrupt Enable. 8 1 DISABLED Disable the stop interrupt. 0 ENABLED Enable the stop interrupt (STOI). 1 ACKIEN Acknowledge Interrupt Enable. 9 1 DISABLED Disable the acknowledge interrupt. 0 ENABLED Enable the acknowledge interrupt (ACKI). 1 RXIEN Receive Done Interrupt Enable. 10 1 DISABLED Disable the receive done interrupt. 0 ENABLED Enable the receive done interrupt (RXI). 1 TXIEN Transmit Done Interrupt Enable. 11 1 DISABLED Disable the transmit done interrupt. 0 ENABLED Enable the transmit done interrupt (TXI). 1 STAIEN Start Interrupt Enable. 12 1 DISABLED Disable the start interrupt. 0 ENABLED Enable the start interrupt (STAI). 1 ARBLIEN Arbitration Lost Interrupt Enable. 13 1 DISABLED Disable the arbitration lost interrupt. 0 ENABLED Enable the arbitration lost interrupt (ARBLI). 1 T0IEN I2C Timer Byte 0 Interrupt Enable. 14 1 DISABLED Disable the I2C Timer Byte 0 interrupt. 0 ENABLED Enable the I2C Timer Byte 0 interrupt (T0I). 1 T1IEN I2C Timer Byte 1 Interrupt Enable. 15 1 DISABLED Disable the I2C Timer Byte 1 interrupt. 0 ENABLED Enable the I2C Timer Byte 1 interrupt (T1I). 1 T2IEN I2C Timer Byte 2 Interrupt Enable. 16 1 DISABLED Disable the I2C Timer Byte 2 interrupt. 0 ENABLED Enable the I2C Timer Byte 2 interrupt (T2I). 1 T3IEN I2C Timer Byte 3 Interrupt Enable. 17 1 DISABLED Disable the I2C Timer Byte 3 and SCL low timeout interrupt. 0 ENABLED Enable the I2C Timer Byte 3 and SCL low timeout interrupt (T3I). 1 BC Transfer Byte Count. 20 2 BP Transfer Byte Pointer. 22 2 read-only T0RUN I2C Timer Byte 0 Run. 24 1 STOP Stop Timer Byte 0. 0 START Start Timer Byte 0 running. 1 T1RUN I2C Timer Byte 1 Run. 25 1 STOP Stop Timer Byte 1. 0 START Start Timer Byte 1 running. 1 T2RUN I2C Timer Byte 2 Run. 26 1 STOP Stop Timer Byte 2. 0 START Start Timer Byte 2 running. 1 T3RUN I2C Timer Byte 3 Run. 27 1 STOP Stop Timer Byte 3. 0 START Start Timer Byte 3 running. 1 TMD I2C Timer Mode. 28 2 MODE0 I2C Timer Mode 0: Operate the I2C timer as a single 32-bit timer : Timer Bytes [3 : 2 : 1 : 0]. 0 MODE1 I2C Timer Mode 1: Operate the I2C timer as two 16-bit timers : Timer Bytes [3 : 2] and Timer Bytes [1 : 0]. 1 MODE2 I2C Timer Mode 2: Operate the I2C timer as four independent 8-bit timers : Timer Byte 3, Timer Byte 2, Timer Byte 1, and Timer Byte 0. 2 MODE3 I2C Timer Mode 3: Operate the I2C timer as one 16-bit and two 8-bit timers : Timer Bytes [3 : 2], Timer Byte 1, and Timer Byte 0. 3 TIMEREN I2C Timer Enable. 31 1 DISABLED Disable I2C Timer. 0 ENABLED Enable I2C Timer for general purpose use. This setting should not be used when the I2C module is enabled (I2CEN = 1). 1 SADDRESS Slave Address 0x20 0x00000000 0xFFFFFFFF ADDRESS Slave Address. 1 10 SMASK Slave Address Mask 0x30 0x00000000 0xFFFFFFFF MASK Slave Address Mask. 1 10 DATA Data Buffer Access 0x40 0x00000000 0xFFFFFFFF DATA Data. 0 32 TIMER Timer Data 0x50 0x00000000 0xFFFFFFFF T0 Timer Byte 0. 0 8 T1 Timer Byte 1. 8 8 T2 Timer Byte 2. 16 8 T3 Timer Byte 3. 24 8 TIMERRL Timer Reload Values 0x60 0x00000000 0xFFFFFFFF T0RL Timer Byte 0 Reload Value. 0 8 T1RL Timer Byte 1 Reload Value. 8 8 T2RL Timer Byte 2 Reload Value. 16 8 T3RL Timer Byte 3 Reload Value. 24 8 SCONFIG SCL Signal Configuration 0x70 0x00000000 0xFFFFFFFF SETUP Data Setup Time Extension. 0 4 HOLD Data Hold Time Extension. 4 4 SCLL SCL Low Time Extension. 8 8 SCLLTIMER SCL Low Timer Bits [3:0]. 16 4 read-only I2S_0 A None I2S_0 0x4003a000 0x0 0xffc registers I2S0RX_IRQn 40 I2S0TX_IRQn 41 TXCONTROL Transmit Control 0x0 0x02000000 0xFFFFFFFF FSGEN DFS Generator Enable. 0 1 DISABLED Disable the internal DFS generator. 0 ENABLED Enable the internal DFS generator. 1 FSSEN DFS Synchronize Enable. 1 1 DISABLED The internal DFS generator starts immediately when FSGEN is set to 1. 0 ENABLED Synchronize the rising edge of the internally generated WS signal from the DFS generator to the rising edge of the external WS input signal. 1 DDIS Transmit Delay Disable. 5 1 INACTIVE The first data bit is sent on the second or later rising edge of SCK after WS changes. 0 ACTIVE The first data bit is sent on the first rising edge of SCK after WS changes. 1 FSDEL Transmit Initial Phase Delay. 6 8 FSSRCSEL Transmit Frame Sync Source Select. 14 1 FSIN_EXT The word select or frame sync is input from the WS pin. 0 FSIN_INT The word select or frame sync is input from the internal DFS generator. 1 FILLSEL Transmit Data Fill Select. 15 2 ZEROS Send zeros during unused bit cycles. 0 ONES Send ones during unused bit cycles. 1 SIGN Send the sign bit of the current sample (MSB-first format) or last sample (LSB-first format) during unused bit cycles. 2 RANDOM Send pseudo-random data generated by an 8-bit LFSR during unused bit cycles. 3 JSEL Transmit Data Justification Select. 17 1 LEFT Use left-justified or I2S-style formats. 0 RIGHT Use right-justified format. 1 FSINVEN Transmit WS Inversion Enable. 20 1 DISABLED Don't invert the WS signal. Use this setting for I2S format. 0 ENABLED Invert the WS signal. 1 SCLKINVEN Transmit SCK Inversion Enable. 21 1 DISABLED Do not invert the transmitter bit clock. 0 ENABLED Invert the transmitter bit clock. 1 ORDER Transmit Order. 22 1 LEFT_RIGHT Left sample transmitted first, right sample transmitted second. Use this setting for I2S format. 0 RIGHT_LEFT Right sample transmitted first, left sample transmitted second. 1 MBSEL Transmit Mono Bit-Width Select. 24 3 8BITS 8 bits are sent per mono sample. 0 9BITS 9 bits are sent per mono sample. 1 16BITS 16 bits are sent per mono sample. 2 24BITS 24 bits are sent per mono sample. 3 32BITS 32 bits are sent per mono sample. 4 TXEN Transmitter Enable. 29 1 DISABLED Disable the I2S transmitter. 0 ENABLED Enable the I2S transmitter. 1 TXMODE Transmit Mode 0x10 0x00000000 0xFFFFFFFF CYCLE Transmit Clock Cycle Select. 0 12 START Transmit Start Control. 12 8 SLOTS Transmit Drive Select. 20 5 DEDIS Transmit Drive Early Disable. 25 1 INACTIVE Drive the output during every cycle of the transmitter's assigned slot(s), including the last clock cycle. 0 ACTIVE Drive the output for every cycle of the transmitter's assigned slot(s), except for the last clock cycle of the last slot. 1 DIMD Transmit Drive Inactive Mode. 26 1 ZERO Drive zero on the data output pin during non-active slots. 0 HIGH_Z Don't drive the data output pin. The data output pin is tristated. 1 TDMEN Transmit Time Division Multiplexing Enable. 27 1 DISABLED Disable the time division multiplexing (TDM) feature. 0 ENABLED Enable the time division multiplexing (TDM) feature. 1 FSDUTY Frame Sync Duty Cycle 0x20 0x00000000 0xFFFFFFFF FSLOW Frame Sync Low Time. 0 16 FSHIGH Frame Sync High Time. 16 16 RXCONTROL Receive Control 0x30 0x00010000 0xFFFFFFFF FSDEL Receive Initial Phase Delay. 0 8 JSEL Receive Data Justification. 8 1 LEFT Use left-justified or I2S-style formats. 0 RIGHT Use right-justified format. 1 DDIS Receive Delay Disable. 9 1 INACTIVE The first data bit is captured on the second or later rising edge of SCK after WS changes. 0 ACTIVE The first data bit is captured by the receiver on the first rising edge of SCK after WS changes. 1 FSINVEN Receive WS Inversion Enable. 11 1 DISABLED Don't invert the WS signal. Use this setting for I2S format. 0 ENABLED Invert the WS signal. 1 SCLKINVEN Receive SCK Inversion Enable. 12 1 DISABLED Do not invert the receiver bit clock. 0 ENABLED Invert the receiver bit clock. 1 ORDER Receive Order. 13 1 LEFT_RIGHT Left sample received first, right sample received second. Use this setting for I2S format. 0 RIGHT_LEFT Right sample received first, left sample received second. 1 MBSEL Receive Mono Bit-Width Select. 15 3 8BITS 8 bits are received per mono sample. 0 9BITS 9 bits are received per mono sample. 1 16BITS 16 bits are received per mono sample. 2 24BITS 24 bits are received per mono sample. 3 32BITS 32 bits are received per mono sample. 4 FSSRCSEL Receive Frame Sync Source Select. 20 1 FSIN_EXT The word select or frame sync is input from the WS pin. 0 FSIN_INT The word select or frame sync is input from the internal DFS generator. 1 RXEN Receive Enable. 21 1 DISABLED Disable the I2S receiver. 0 ENABLED Enable the I2S receiver. 1 RXMODE Receive Mode 0x40 0x00000000 0xFFFFFFFF CYCLE Receive Clock Cycle Select. 0 12 START Receive Start Control. 12 8 SLOTS Receive Drive Select. 20 6 TDMEN Receive Time Division Multiplexing Enable. 27 1 DISABLED Disable the time division multiplexing (TDM) feature. 0 ENABLED Enable the time division multiplexing (TDM) feature. 1 CLKCONTROL Clock Control 0x50 0x00000000 0xFFFFFFFF INTDIV Clock Divider Integer Value. 0 10 FRACDIV Clock Divider Fractional Value. 10 8 DUTYMD Duty Cycle Adjustment Mode. 18 1 MORE When the division is fractional, the clock high time will be greater than 50% (by half of the source clock period). 0 LESS When the division is fractional, the clock low time will be greater than 50% (by half of the source clock period). 1 CLKUPD Clock Divider Update. 19 1 write-only UPDATE Update the clock divider with new values of INTDIV, FRACDIV, and DIVEN. 1 DIVEN Clock Divider Enable. 20 1 DISABLED Disable the clock divider. 0 ENABLED Enable the clock divider. 1 TXCLKSEL Transmit Clock Select. 21 1 INTERNAL The I2S transmitter is clocked from the internal clock divider. 0 EXTERNAL The I2S transmitter is clocked from the SCK pin. 1 RXCLKSEL Receive Clock Select. 22 1 INTERNAL The I2S receiver is clocked from the internal clock divider. 0 EXTERNAL The I2S receiver is clocked from the SCK pin. 1 RESET I2S Module Reset. 23 1 write-only ACTIVE Reset the I2S module. 1 RXCLKEN Receive Clock Enable. 24 1 DISABLED Disable the I2S receiver clock. 0 ENABLED Enable the I2S receiver clock. 1 TXCLKEN Transmit Clock Enable. 25 1 DISABLED Disable the I2S transmitter clock. 0 ENABLED Enable the I2S transmitter clock. 1 RXSCLKMD Receive SCK Mode. 26 1 SCK_OUTPUT The I2S receiver SCK signal is an output. 0 SCK_INPUT The I2S receiver SCK signal is an input. 1 TXSCLKMD Transmit SCK Mode. 27 1 SCK_OUTPUT The I2S transmitter SCK signal is an output. 0 SCK_INPUT The I2S transmitter SCK signal is an input. 1 TXFIFO Transmit Data FIFO 0x60 0x00000000 0xFFFFFFFF modifyExternal TXFIFO Transmit Data FIFO. 0 32 write-only RXFIFO Receive Data FIFO 0x70 0x00000000 0xFFFFFFFF modifyExternal RXFIFO Receive Data FIFO. 0 32 read-only FIFOSTATUS FIFO Status 0x80 0x00000000 0xFFFFFFFF TXFIFONUM Transmit FIFO Status. 0 4 read-only RXFIFONUM Receive FIFO Status. 16 4 read-only FIFOCONTROL FIFO Control 0x90 0x00000000 0xFFFFFFFF TXFIFOWM Transmit FIFO Low Watermark. 0 4 RXFIFOWM Receive FIFO High Watermark. 16 4 TXFIFOFL Transmit FIFO Flush. 21 1 write-only SET Flush the I2S transmitter FIFO. 1 RXFIFOFL Receive FIFO Flush. 22 1 write-only SET Flush the I2S receiver FIFO. 1 INTCONTROL Interrupt Control 0xa0 0x00000000 0xFFFFFFFF TXUFIEN Transmit Underflow Interrupt Enable. 0 1 DISABLED Disable the transmit underflow interrupt. 0 ENABLED Enable the transmit underflow interrupt. 1 RXOFIEN Receive Overflow Interrupt Enable. 1 1 DISABLED Disable the receive overflow interrupt. 0 ENABLED Enable the receive overflow interrupt. 1 TXLWMIEN Transmit FIFO Low Watermark Interrupt Enable. 2 1 DISABLED Disable the transmit FIFO low watermark interrupt. 0 ENABLED Enable the transmit FIFO low watermark interrupt. 1 RXHWMIEN Receive FIFO High Watermark Interrupt Enable. 3 1 DISABLED Disable the receive FIFO high watermark interrupt. 0 ENABLED Enable the receive FIFO high watermark interrupt. 1 STATUS Module Status 0xb0 0x0000002C 0xFFFFFFFF TXUFI Transmit Underflow Interrupt Flag. 0 1 NOT_SET A transmit underflow has not occurred. 0 SET A transmit underflow occurred. 1 RXOFI Receive Overflow Interrupt Flag. 1 1 NOT_SET A receive overflow has not occurred. 0 SET A receive overflow occurred. 1 TXLWMI Transmit FIFO Low Watermark Interrupt Flag. 2 1 read-only NOT_SET Transmit FIFO level is above the low watermark. 0 SET Transmit FIFO level is at or below the low watermark. 1 RXHWMI Receive FIFO High Watermark Interrupt Flag. 3 1 read-only NOT_SET Receive FIFO level is below the high watermark. 0 SET Receive FIFO level is at or above the high watermark. 1 CDBUSYF Clock Divider Busy Flag. 4 1 read-only NOT_BUSY The divider is not busy and an update is not pending. 0 BUSY The divider is busy and an update is pending. 1 CDSTS Clock Divider Counter Status. 5 1 read-only RUNNING Divided clock output is running. 0 HALTED Divided clock output is halted. 1 TXCLKSELRF Transmit Clock Select Ready Flag. 6 1 read-only NOT_SET The transmit clock is not synchronized. 0 SET The transmit clock is synchronized and the transmitter is ready to send data. 1 RXCLKSELRF Receive Clock Select Ready Flag. 7 1 read-only NOT_SET The receive clock is not synchronized. 0 SET The receive clock is synchronized and the receiver is ready to accept data. 1 TXCLKENRF Transmit Clock Enable Ready Flag. 8 1 read-only NOT_SET The transmit clock is not synchronized. 0 SET The transmit clock is synchronized and the transmitter is ready to send data. 1 RXCLKENRF Receive Clock Enable Ready Flag. 9 1 read-only NOT_SET The receive clock is not synchronized. 0 SET The receive clock is synchronized and the receiver is ready to accept data. 1 DMACONTROL DMA Control 0xc0 0x00000000 0xFFFFFFFF TXDMAEN Transmit DMA Enable. 0 1 DISABLED Disable transmitter DMA data requests. 0 ENABLED Enable transmitter DMA data requests. 1 RXDMAEN Receive DMA Enable. 1 1 DISABLED Disable receiver DMA data transfer requests. 0 ENABLED Enable receiver DMA data transfer requests. 1 TXDMABMD Transmit DMA Burst Mode. 2 1 ONE_WORD The transmitter transmits one word at a time. Whenever there is any room in the transmit FIFO, a single word burst DMA data request is generated. 0 FOUR_WORDS The transmitter transmits four words at a time. Whenever the FIFO depth drops below five, a DMA burst request is generated for four words. 1 RXDMABMD Receive DMA Burst Mode. 3 1 ONE_WORD The receiver receives one word at a time. Whenever there is at least one word in the receive FIFO, a single word burst DMA request is generated. 0 FOUR_WORDS The receiver receives four words at a time. Whenever the FIFO depth rises above three, a DMA burst request is generated for four words. 1 DBGCONTROL Debug Control 0xd0 0x00000000 0xFFFFFFFF TXDBGHEN I2S Transmit DMA Debug Halt Enable. 0 1 DISABLED Transmit DMA requests continue while the core is debug mode. 0 ENABLED Transmit DMA requests stop while the core is debug mode. 1 RXDBGHEN I2S Receive DMA Debug Halt Enable. 1 1 DISABLED Receive DMA requests continue while the core is debug mode. 0 ENABLED Receive DMA requests stop while the core is debug mode. 1 TXDBGMD I2S Transmit Debug Mode. 2 1 RUN The clock to the I2S transmitter is active in debug mode. 0 HALT The clock to the I2S transmitter is not active in debug mode. The clock divider keeps running and the clock will be disabled when two samples are ready to be sent by the transmitter. 1 RXDBGMD I2S Receive Debug Mode. 3 1 RUN The clock to the I2S receiver is active in debug mode. 0 HALT The clock to the I2S receiver is not active in debug mode. The clock divider keeps running and the clock will be disabled when two samples are captured in the receiver. 1 IDAC_0 A None IDAC 0x40031000 0x0 0xffc registers IDAC0_IRQn 48 CONTROL Module Control 0x0 0x00000007 0xFFFFFFFF OUPDT Output Update Trigger. 0 3 DACNT8 The IDAC output updates using the DACnT8 (Timer 0 Low Overflow) trigger source. 0 DACNT9 The IDAC output updates using the DACnT9 (Timer 1 High Overflow) trigger source. 1 DACNT10 The IDAC output updates using the DACnT10 (Timer 1 Low Overflow) trigger source. 2 DACNT11 The IDAC output updates using the DACnT11 (Timer 1 High Overflow) trigger source. 3 DACNT12 The IDAC output updates on the rising edge of the trigger source selected by ETRIG. 4 DACNT13 The IDAC output updates on the falling edge of the trigger source selected by ETRIG. 5 DACNT14 The IDAC output updates on any edge of the trigger source selected by ETRIG. 6 DACNT15 The IDAC output updates on write to DATA register (On Demand). 7 ETRIG Edge Trigger Source Select. 3 3 DACNT0 Select DACnT0 (PB3.0) as the IDAC external trigger source. 0 DACNT1 Select DACnT1 (PB3.1) as the IDAC external trigger source. 1 DACNT2 Select DACnT2 (PB3.2) as the IDAC external trigger source. 2 DACNT3 Select DACnT3 (PB3.3) as the IDAC external trigger source. 3 DACNT4 Select DACnT4 (RESERVED) as the IDAC external trigger source. 4 DACNT5 Select DACnT5 (RESERVED) as the IDAC external trigger source. 5 DACNT6 Select DACnT6 (RESERVED) as the IDAC external trigger source. 6 DACNT7 Select DACnT7 (SSG0 EX2) as the IDAC external trigger source. 7 OUTMD Output Mode. 6 2 0P5_MA The full-scale output current is 0.5 mA. 0 1_MA The full-scale output current is 1 mA. 1 2_MA The full-scale output current is 2 mA. 2 INFMT Data Input Format. 8 2 1_10_BIT Writes are interpreted as one 10-bit sample. 0 2_10_BIT Writes are interpreted as two 10-bit samples. 1 4_8_BIT Writes are interpreted as four 8-bit samples. 2 DMARUN DMA Run. 10 1 DISABLED Read: No DMA operations are occurring or the DMA is done. Write: No effect. 0 ENABLED Read: A DMA operation is currently in progress. Write: Start a DMA operation. 1 JSEL Data Justification Select. 11 1 RIGHT Data is right-justified. 0 LEFT Data is left-justified. 1 BUFRESET Data Buffer Reset. 12 1 write-only RESET Initiate a data buffer reset. 1 TRIGINH Trigger Source Inhibit. 13 1 INACTIVE The selected trigger source will cause the IDAC output to update. 0 ACTIVE The selected trigger source will not update the IDAC output, except for On-Demand DATA writes. 1 WRAPEN Wrap Mode Enable. 16 1 DISABLED The IDAC will not wrap when it reaches the end of the data buffer. 0 ENABLED The IDAC will cycle through the data buffer contents. 1 ORIEN FIFO Overrun Interrupt Enable. 20 1 DISABLED Disable the FIFO overrun interrupt (ORI). 0 ENABLED Enable the FIFO overrun interrupt (ORI). 1 URIEN FIFO Underrun Interrupt Enable. 21 1 DISABLED Disable the FIFO underrun interrupt (URI). 0 ENABLED Enable the FIFO underrun interrupt (URI). 1 WEIEN FIFO Went Empty Interrupt Enable. 22 1 DISABLED Disable the FIFO went empty interrupt (WEI). 0 ENABLED Enable the FIFO went empty interrupt (WEI). 1 DBGMD IDAC Debug Mode. 29 1 RUN The IDAC module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the IDAC module to halt. 1 LOADEN Load Resistor Enable. 30 1 DISABLED Disable the internal load resistor. 0 ENABLED Enable the internal load resistor. 1 IDACEN IDAC Enable. 31 1 DISABLED Disable the IDAC. 0 ENABLED Enable the IDAC. 1 DATA Output Data 0x10 0x00000000 0xFFFFFFFF DATA Output Data. 0 32 BUFSTATUS FIFO Buffer Status 0x20 0x00000000 0xFFFFFFFF LEVEL FIFO Level. 0 3 read-only EMPTY The data FIFO is empty. 0 1WORD The data FIFO contains one word. 1 2WORDS The data FIFO contains two words. 2 3WORDS The data FIFO contains three words. 3 4WORDS The data FIFO is full and contains four words. 4 ORI FIFO Overrun Interrupt Flag. 4 1 NOT_SET Read: A FIFO overrun has not occurred. Write: Clear the interrupt. 0 SET Read: A FIFO overrun occurred. Write: Force a FIFO overrun interrupt. 1 URI FIFO Underrun Interrupt Flag. 5 1 NOT_SET Read: A FIFO underrun has not occurred. Write: Clear the interrupt. 0 SET Read: A FIFO underrun occurred. Write: Force a FIFO underrun interrupt. 1 WEI FIFO Went Empty Interrupt Flag. 6 1 NOT_SET Read: A FIFO went empty condition has not occurred. Write: Clear the interrupt. 0 SET Read: The FIFO is empty. Write: Force a FIFO went empty interrupt. 1 BUFFER10 FIFO Buffer Entries 0 and 1 0x30 0x00000000 0xFFFFFFFF BUFFER0 FIFO Buffer Entry 0. 0 16 read-only BUFFER1 FIFO Buffer Entry 1. 16 16 read-only BUFFER32 FIFO Buffer Entries 2 and 3 0x40 0x00000000 0xFFFFFFFF BUFFER2 FIFO Buffer Entry 2. 0 16 read-only BUFFER3 FIFO Buffer Entry 3. 16 16 read-only GAINADJ Output Current Gain Adjust 0x50 0x0000000D 0xFFFFFFFF GAINADJ Output Current Gain Adjust. 0 5 IDAC_1 A None IDAC 0x40032000 0x0 0xffc registers IDAC1_IRQn 49 CONTROL Module Control 0x0 0x00000007 0xFFFFFFFF OUPDT Output Update Trigger. 0 3 DACNT8 The IDAC output updates using the DACnT8 (Timer 0 Low Overflow) trigger source. 0 DACNT9 The IDAC output updates using the DACnT9 (Timer 1 High Overflow) trigger source. 1 DACNT10 The IDAC output updates using the DACnT10 (Timer 1 Low Overflow) trigger source. 2 DACNT11 The IDAC output updates using the DACnT11 (Timer 1 High Overflow) trigger source. 3 DACNT12 The IDAC output updates on the rising edge of the trigger source selected by ETRIG. 4 DACNT13 The IDAC output updates on the falling edge of the trigger source selected by ETRIG. 5 DACNT14 The IDAC output updates on any edge of the trigger source selected by ETRIG. 6 DACNT15 The IDAC output updates on write to DATA register (On Demand). 7 ETRIG Edge Trigger Source Select. 3 3 DACNT0 Select DACnT0 (PB3.0) as the IDAC external trigger source. 0 DACNT1 Select DACnT1 (PB3.1) as the IDAC external trigger source. 1 DACNT2 Select DACnT2 (PB3.2) as the IDAC external trigger source. 2 DACNT3 Select DACnT3 (PB3.3) as the IDAC external trigger source. 3 DACNT4 Select DACnT4 (RESERVED) as the IDAC external trigger source. 4 DACNT5 Select DACnT5 (RESERVED) as the IDAC external trigger source. 5 DACNT6 Select DACnT6 (RESERVED) as the IDAC external trigger source. 6 DACNT7 Select DACnT7 (SSG0 EX3) as the IDAC external trigger source. 7 OUTMD Output Mode. 6 2 0P5_MA The full-scale output current is 0.5 mA. 0 1_MA The full-scale output current is 1 mA. 1 2_MA The full-scale output current is 2 mA. 2 INFMT Data Input Format. 8 2 1_10_BIT Writes are interpreted as one 10-bit sample. 0 2_10_BIT Writes are interpreted as two 10-bit samples. 1 4_8_BIT Writes are interpreted as four 8-bit samples. 2 DMARUN DMA Run. 10 1 DISABLED Read: No DMA operations are occurring or the DMA is done. Write: No effect. 0 ENABLED Read: A DMA operation is currently in progress. Write: Start a DMA operation. 1 JSEL Data Justification Select. 11 1 RIGHT Data is right-justified. 0 LEFT Data is left-justified. 1 BUFRESET Data Buffer Reset. 12 1 write-only RESET Initiate a data buffer reset. 1 TRIGINH Trigger Source Inhibit. 13 1 INACTIVE The selected trigger source will cause the IDAC output to update. 0 ACTIVE The selected trigger source will not update the IDAC output, except for On-Demand DATA writes. 1 WRAPEN Wrap Mode Enable. 16 1 DISABLED The IDAC will not wrap when it reaches the end of the data buffer. 0 ENABLED The IDAC will cycle through the data buffer contents. 1 ORIEN FIFO Overrun Interrupt Enable. 20 1 DISABLED Disable the FIFO overrun interrupt (ORI). 0 ENABLED Enable the FIFO overrun interrupt (ORI). 1 URIEN FIFO Underrun Interrupt Enable. 21 1 DISABLED Disable the FIFO underrun interrupt (URI). 0 ENABLED Enable the FIFO underrun interrupt (URI). 1 WEIEN FIFO Went Empty Interrupt Enable. 22 1 DISABLED Disable the FIFO went empty interrupt (WEI). 0 ENABLED Enable the FIFO went empty interrupt (WEI). 1 DBGMD IDAC Debug Mode. 29 1 RUN The IDAC module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the IDAC module to halt. 1 LOADEN Load Resistor Enable. 30 1 DISABLED Disable the internal load resistor. 0 ENABLED Enable the internal load resistor. 1 IDACEN IDAC Enable. 31 1 DISABLED Disable the IDAC. 0 ENABLED Enable the IDAC. 1 DATA Output Data 0x10 0x00000000 0xFFFFFFFF DATA Output Data. 0 32 BUFSTATUS FIFO Buffer Status 0x20 0x00000000 0xFFFFFFFF LEVEL FIFO Level. 0 3 read-only EMPTY The data FIFO is empty. 0 1WORD The data FIFO contains one word. 1 2WORDS The data FIFO contains two words. 2 3WORDS The data FIFO contains three words. 3 4WORDS The data FIFO is full and contains four words. 4 ORI FIFO Overrun Interrupt Flag. 4 1 NOT_SET Read: A FIFO overrun has not occurred. Write: Clear the interrupt. 0 SET Read: A FIFO overrun occurred. Write: Force a FIFO overrun interrupt. 1 URI FIFO Underrun Interrupt Flag. 5 1 NOT_SET Read: A FIFO underrun has not occurred. Write: Clear the interrupt. 0 SET Read: A FIFO underrun occurred. Write: Force a FIFO underrun interrupt. 1 WEI FIFO Went Empty Interrupt Flag. 6 1 NOT_SET Read: A FIFO went empty condition has not occurred. Write: Clear the interrupt. 0 SET Read: The FIFO is empty. Write: Force a FIFO went empty interrupt. 1 BUFFER10 FIFO Buffer Entries 0 and 1 0x30 0x00000000 0xFFFFFFFF BUFFER0 FIFO Buffer Entry 0. 0 16 read-only BUFFER1 FIFO Buffer Entry 1. 16 16 read-only BUFFER32 FIFO Buffer Entries 2 and 3 0x40 0x00000000 0xFFFFFFFF BUFFER2 FIFO Buffer Entry 2. 0 16 read-only BUFFER3 FIFO Buffer Entry 3. 16 16 read-only GAINADJ Output Current Gain Adjust 0x50 0x0000000D 0xFFFFFFFF GAINADJ Output Current Gain Adjust. 0 5 IVC_0 A None IVC_0 0x40044000 0x0 0xffc registers CONTROL Module Control 0x0 0x00000000 0xFFFFFFFF IN0RANGE Input 0 Range. 0 3 6_MA Input range is 0-6 mA. 0 5_MA Input range is 0-5 mA. 1 4_MA Input range is 0-4 mA. 2 3_MA Input range is 0-3 mA. 3 2_MA Input range is 0-2 mA. 4 1_MA Input range is 0-1 mA. 5 IN1RANGE Input 1 Range. 4 3 6_MA Input range is 0-6 mA. 0 5_MA Input range is 0-5 mA. 1 4_MA Input range is 0-4 mA. 2 3_MA Input range is 0-3 mA. 3 2_MA Input range is 0-2 mA. 4 1_MA Input range is 0-1 mA. 5 C0EN Converter 0 Enable. 30 1 DISABLED Disable IVC channel 0. 0 ENABLED Enable IVC channel 0. 1 C1EN Converter 1 Enable. 31 1 DISABLED Disable IVC channel 1. 0 ENABLED Enable IVC channel 1. 1 LOCK_0 A None LOCK_0 0x40049000 0x0 0xffc registers KEY Security Key 0x0 0x00000000 0xFFFFFFFF KEY Peripheral Lock Mask Key. 0 8 LOCKED PERIPHLOCK registers are locked and no valid values have been written to KEY. 0 INTERMEDIATE PERIPHLOCK registers are locked and the first valid value (0xA5) has been written to KEY. 1 UNLOCKED PERIPHLOCK registers are unlocked. Any subsequent writes to KEY will lock the interface. 2 PERIPHLOCK0 Peripheral Lock Control 0 0x20 0x00000000 0xFFFFFFFF USARTL USART/UART Module Lock Enable. 0 1 UNLOCKED Unlock the USART0, USART1, UART0, and UART1 Module registers. 0 LOCKED Lock the USART0, USART1, UART0, and UART1 Module registers (bits can still be read). 1 SPIL SPI Module Lock Enable. 1 1 UNLOCKED Unlock the SPI0, SPI1, and SPI2 Module registers. 0 LOCKED Lock the SPI0, SPI1, and SPI2 Module registers (bits can still be read). 1 I2CL I2C Module Lock Enable. 2 1 UNLOCKED Unlock the I2C0 and I2C1 Module registers. 0 LOCKED Lock the I2C0 and I2C1 Module registers (bits can still be read). 1 PCAL PCA Module Lock Enable. 3 1 UNLOCKED Unlock the EPCA0, PCA0, and PCA1 Module registers. 0 LOCKED Lock the EPCA0, PCA0, and PCA1 Module registers (bits can still be read). 1 TIMERL Timer Module Lock Enable. 4 1 UNLOCKED Unlock the TIMER0 and TIMER1 Module registers. 0 LOCKED Lock the TIMER0 and TIMER1 Module registers (bits can still be read). 1 SARADCL SARADC Module Lock Enable. 6 1 UNLOCKED Unlock the SARADC0 and SARADC1 Module registers. 0 LOCKED Lock the SARADC0 and SARADC1 Module registers (bits can still be read). 1 SSGL SSG Module Lock Enable. 7 1 UNLOCKED Unlock the SSG0 Module registers. 0 LOCKED Lock the SSG0 Module registers (bits can still be read). 1 CMPL Comparator Module Lock Enable. 8 1 UNLOCKED Unlock the Comparator 0 and Comparator 1 Module registers. 0 LOCKED Lock the Comparator 0 and Comparator 1 Module registers (bits can still be read). 1 CSL Capacitive Sensing Module Lock Enable. 9 1 UNLOCKED Unlock the Capacitive Sensing (CAPSENSE0) Module registers. 0 LOCKED Lock the Capacitive Sensing (CAPSENSE0) Module registers (bits can still be read). 1 EMIFL EMIF Module Lock Enable. 10 1 UNLOCKED Unlock the External Memory Interface (EMIF0) Module registers. 0 LOCKED Lock the External Memory Interface (EMIF0) Module registers (bits can still be read). 1 AESL AES Module Lock Enable. 11 1 UNLOCKED Unlock the AES0 Module registers. 0 LOCKED Lock the AES0 Module registers (bits can still be read). 1 CRCL CRC Module Lock Enable. 12 1 UNLOCKED Unlock the CRC0 Module registers. 0 LOCKED Lock the CRC0 Module registers (bits can still be read). 1 RTCL RTC Module Lock Enable. 13 1 UNLOCKED Unlock the RTC0 Module registers. 0 LOCKED Lock the RTC0 Module registers (bits can still be read). 1 CLKRSTL Clock Control and Reset Sources Lock Enable. 14 1 UNLOCKED Unlock the Clock Control (CLKCTRL) and Reset Sources (RSTSRC) Module registers. 0 LOCKED Lock the Clock Control (CLKCTRL) and Reset Sources (RSTSRC) Module registers (bits can still be read). 1 VMONL Voltage Supply Monitor Module Lock Enable. 15 1 UNLOCKED Unlock the Voltage Supply Monitor (VMON0) Module registers. 0 LOCKED Lock the Voltage Supply Monitor (VMON0) Module registers (bits can still be read). 1 IDACL IDAC Module Lock Enable. 16 1 UNLOCKED Unlock the IDAC0 and IDAC1 Module registers. 0 LOCKED Lock the IDAC0 and IDAC1 Module registers (bits can still be read). 1 DMACTRLL DMA Controller Module Lock Enable. 17 1 UNLOCKED Unlock the DMA Controller (DMACTRL0) Module registers. 0 LOCKED Lock the DMA Controller (DMACTRL0) Module registers (bits can still be read). 1 DMAXBARL DMA Crossbar Module Lock Enable. 18 1 UNLOCKED Unlock the DMA Crossbar (DMAXBAR0) Module registers. 0 LOCKED Lock the DMA Crossbar (DMAXBAR0) Module registers (bits can still be read). 1 LPTL Low Power Timer Module Lock Enable. 19 1 UNLOCKED Unlock the Low Power Timer (LPTIMER0) Module registers. 0 LOCKED Lock the Low Power Timer (LPTIMER0) Module registers (bits can still be read). 1 VREFL Voltage Reference Module Lock Enable. 20 1 UNLOCKED Unlock the Voltage Reference (VREF0) Module registers. 0 LOCKED Lock the Voltage Reference (VREF0) Module registers (bits can still be read). 1 I2SL I2S Module Lock Enable. 21 1 UNLOCKED Unlock the I2S0 Module registers. 0 LOCKED Lock the I2S0 Module registers (bits can still be read). 1 PLLL PLL Module Lock Enable. 22 1 UNLOCKED Unlock the PLL0 Module registers. 0 LOCKED Lock the PLL0 Module registers (bits can still be read). 1 EXTOSCL External Oscillator Module Lock Enable. 23 1 UNLOCKED Unlock the External Oscillator (EXTOSC0) Module registers. 0 LOCKED Lock the External Oscillator (EXTOSC0) Module registers (bits can still be read). 1 VREGL Voltage Regulator Module Lock Enable. 24 1 UNLOCKED Unlock the Voltage Regulator (VREG0) Module registers. 0 LOCKED Lock the Voltage Regulator (VREG0) Module registers (bits can still be read). 1 LPOSCL Low Power Oscillator Lock Enable. 25 1 UNLOCKED Unlock the Low Power Oscillator (LPOSC0) Module registers. 0 LOCKED Lock the Low Power Oscillator (LPOSC0) Module registers (bits can still be read). 1 EVREGL External Regulator Module Lock Enable. 26 1 UNLOCKED Unlock the External Regulator (EXTVREG0) Module registers. 0 LOCKED Lock the External Regulator (EXTVREG0) Module registers (bits can still be read). 1 IVCL IVC Module Lock Enable. 28 1 UNLOCKED Unlock the IVC0 Module registers. 0 LOCKED Lock the IVC0 Module registers (bits can still be read). 1 PERIPHLOCK1 Peripheral Lock Control 1 0x40 0x00000000 0xFFFFFFFF PMUL PMU Module Lock Enable. 0 1 UNLOCKED Unlock the PMU Module registers. 0 LOCKED Lock the PMU Module registers (bits can still be read). 1 LPTIMER_0 A None LPTIMER_0 0x40038000 0x0 0xffc registers LPTIMER0_IRQn 50 CONTROL Module Control 0x0 0x00000000 0xFFFFFFFF CMD Count Mode. 0 2 FREE The timer is free running mode on the RTCn module clock (RTCnOSC or LFOSCn). 0 RISING_EDGE The timer is incremented on the rising edges of the selected external trigger (LPTnTx). 1 FALLING_EDGE The timer is incremented on the falling edges of the selected external trigger (LPTnTx). 2 ANY_EDGE The timer is incremented on both edges of the selected external trigger (LPTnTx). 3 EXTSEL External Trigger Source Select. 4 4 LPTNT0 Select external trigger LPTnT0 (PB3.0). 0 LPTNT1 Select external trigger LPTnT1 (PB3.1). 1 LPTNT2 Select external trigger LPTnT2 (PB3.2). 2 LPTNT3 Select external trigger LPTnT3 (Comparator 0 Output). 3 LPTNT4 Select external trigger LPTnT4 (RESERVED). 4 LPTNT5 Select external trigger LPTnT5 (RESERVED). 5 LPTNT6 Select external trigger LPTnT6 (RESERVED). 6 LPTNT7 Select external trigger LPTnT7 (RESERVED). 7 LPTNT8 Select external trigger LPTnT8 (RESERVED). 8 LPTNT9 Select external trigger LPTnT9 (RESERVED). 9 LPTNT10 Select external trigger LPTnT10 (RESERVED). 10 LPTNT11 Select external trigger LPTnT11 (RESERVED). 11 LPTNT12 Select external trigger LPTnT12 (RESERVED). 12 LPTNT13 Select external trigger LPTnT13 (RESERVED). 13 LPTNT14 Select external trigger LPTnT14 (RESERVED). 14 LPTNT15 Select external trigger LPTnT15 (RESERVED). 15 TMRSET Timer Set. 8 1 SET Writing a 1 to TMRSET initiates a copy of the value from the DATA register into the internal timer register. This field is automatically cleared by hardware when the copy is complete and does not need to be cleared by software. 1 TMRCAP Timer Capture. 9 1 SET Writing a 1 to TMRCAP initiates a read of internal timer register into the DATA register. This field is automatically cleared by hardware when the operation completes and does not need to be cleared by software. 1 CMPSET Timer Comparator Set. 10 1 SET Writing a 1 to CMPSET initiates a copy of the value in DATA into the internal timer comparator register. This field is automatically cleared by hardware when the copy is complete and does not need to be cleared by software. 1 CMPCAP Timer Comparator Capture. 11 1 SET Writing a 1 to CMPCAP initiates a read of the internal comparator register into the DATA register. This field is automatically cleared by hardware when the operation completes and does not need to be cleared by software. 1 OVFIEN Timer Overflow Interrupt Enable. 16 1 DISABLED Disable the timer overflow interrupt. 0 ENABLED Enable the timer overflow interrupt. 1 CMPIEN Timer Compare Event Interrupt Enable. 17 1 DISABLED Disable the timer compare event interrupt. 0 ENABLED Enable the timer compare event interrupt. 1 OVFTMD Timer Overflow Toggle Mode. 18 1 DISABLED Timer overflows do not toggle the Low Power Timer output. 0 ENABLED Timer overflows toggle the Low Power Timer output. 1 CMPTMD Timer Compare Event Toggle Mode . 19 1 DISABLED Timer compare events do not toggle the Low Power Timer output. 0 ENABLED Timer compare events toggle the Low Power Timer output. 1 CMPRSTEN Timer Compare Event Reset Enable. 24 1 DISABLED Timer compare events do not reset the timer. 0 ENABLED Timer compare events reset the timer. 1 DBGMD Low Power Timer Debug Mode. 30 1 RUN The Low Power Timer module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the Low Power Timer module to halt. 1 RUN Timer Run Control and Compare Threshold Enable. 31 1 STOP Stop the timer and disable the compare threshold. 0 START Start the timer running and enable the compare threshold. 1 DATA Timer and Comparator Data 0x10 0x00000000 0xFFFFFFFF DATA Timer and Comparator Data. 0 16 STATUS Module Status 0x20 0x00000000 0xFFFFFFFF OVFI Timer Overflow Interrupt Flag. 0 1 NOT_SET A timer overflow has not occurred. 0 SET A timer overflow occurred. 1 CMPI Timer Compare Event Interrupt Flag. 1 1 NOT_SET A timer compare event has not occurred. 0 SET A timer compare event occurred. 1 PLL_0 A None Oscillators 0x4003b000 0x0 0xffc registers PLL_IRQn 51 DIVIDER Reference Divider Setting 0x0 0x00000000 0xFFFFFFFF M M Divider Value. 0 12 N N Divider Value. 16 12 CONTROL Module Control 0x10 0x00000800 0xFFFFFFFF LLMTF CAL Saturation (Low) Flag. 0 1 read-only NOT_SET DCO period is not saturated low. 0 SET DCO period is saturated low. 1 HLMTF CAL Saturation (High) Flag. 1 1 read-only NOT_SET DCO period is not saturated high. 0 SET DCO period is saturated high. 1 LCKI Phase-Lock and Frequency-Lock Locked Interrupt Flag. 2 1 read-only NOT_SET DCO is disabled or not locked. 0 SET DCO is enabled and locked. 1 LMTIEN Limit Interrupt Enable. 9 1 DISABLED Saturation (high and low) interrupt disabled. 0 ENABLED Saturation (high and low) interrupt enabled. 1 LCKIEN Locked Interrupt Enable. 10 1 DISABLED The PLL locking does not cause an interrupt 0 ENABLED An interrupt is generated if LCKI matches the state selected by LCKPOL. 1 LCKPOL Lock Interrupt Polarity. 11 1 ACTIVE_LOW The lock state PLL interrupt will occur when LCKI is 0. 0 ACTIVE_HIGH The lock state PLL interrupt will occur when LCKI is 1. 1 REFSEL Reference Clock Selection Control. 16 2 RTC0OSC PLL reference clock (FREF) is the RTC0 oscillator (RTC0OSC). 0 LPOSC0DIV PLL reference clock (FREF) is the divided Low Power Oscillator (LPOSC0). 1 EXTOSC0 PLL reference clock (FREF) is the external oscillator output (EXTOSC0). 2 USBOSC0 PLL reference clock (FREF) is the USB0 oscillator (USB0OSC). 3 LOCKTH Lock Threshold Control. 20 2 STALL DCO Output Updates Stall. 26 1 DISABLED In phase-lock and frequency-lock modes, spectrum spreading, and dithering operate normally, if enabled. 0 ENABLED In phase-lock and frequency-lock modes, spectrum spreading, and dithering are prevented from updating the output of the DCO. 1 DITHEN Dithering Enable. 28 1 DISABLED Automatic DCO output dithering disabled. 0 ENABLED Automatic DCO output dithering enabled. 1 EDGSEL Edge Lock Select. 29 1 FALLING_EDGE Lock DCO output frequency to the falling edge of the reference frequency. 0 RISING_EDGE Lock DCO output frequency to the rising edge of the reference frequency. 1 OUTMD PLL Output Mode. 30 2 OFF DCO output is off. 0 DCO DCO output is in Free-Running DCO mode. 1 FLL DCO output is in frequency-lock mode (reference source required). 2 PLL DCO output is in phase-lock mode (reference source required). 3 SSPR Spectrum Spreading Control 0x20 0x00000000 0xFFFFFFFF SSAMP Spectrum Spreading Amplitude. 0 3 DISABLED Disable Spectrum Spreading. 0 SETTING1 Spectrum Spreading set to approximately +/- 0.1% of TDCO. 1 SETTING2 Spectrum Spreading set to approximately +/- 0.2% of TDCO. 2 SETTING3 Spectrum Spreading set to approximately +/- 0.4% of TDCO. 3 SETTING4 Spectrum Spreading set to approximately +/- 0.8% of TDCO. 4 SETTING5 Spectrum Spreading set to approximately +/- 1.6% of TDCO. 5 SSUINV Spectrum Spreading Update Interval. 8 5 CALCONFIG Calibration Configuration 0x30 0x00000000 0xFFFFFFFF DITHER DCO Dither Setting. 0 4 CAL DCO Calibration Value. 4 12 RANGE DCO Range. 16 3 RANGE0 DCO operates from 23 to 37 MHz. 0 RANGE1 DCO operates from 33 to 54 MHz. 1 RANGE2 DCO operates from 45 to 71 MHz. 2 RANGE3 DCO operates from 53 to 80 MHz. 3 RANGE4 DCO operates from 73 to 80 MHz. 4 EXTOSC_0 A None Oscillators 0x4003c000 0x0 0xffc registers CONTROL Oscillator Control 0x0 0x00000000 0xFFFFFFFF FREQCN Frequency Control. 0 3 RANGE0 Set the external oscillator to range 0. 0 RANGE1 Set the external oscillator to range 1. 1 RANGE2 Set the external oscillator to range 2. 2 RANGE3 Set the external oscillator to range 3. 3 RANGE4 Set the external oscillator to range 4. 4 RANGE5 Set the external oscillator to range 5. 5 RANGE6 Set the external oscillator to range 6. 6 RANGE7 Set the external oscillator to range 7. 7 OSCVLDF Oscillator Valid Flag. 3 1 read-only NOT_SET The external oscillator is unused or not yet stable. 0 SET The external oscillator is running and stable. 1 OSCMD Oscillator Mode. 4 3 OFF External oscillator off. 0 CMOS External CMOS clock mode. 2 CMOSDIV2 External CMOS with divide by 2 stage. 3 RC RC oscillator mode with divide by 2 stage. 4 C C oscillator mode with divide by 2 stage. 5 XTAL Crystal oscillator mode. 6 XTALDIV2 Crystal oscillator mode with divide by 2 stage. 7 LPOSC_0 A None Oscillators 0x40041000 0x0 0xffc registers OSCVAL Low Power Oscillator Output Value 0x0 0x00000008 0xFFFFFFFF OSCVAL Low Power Oscillator Output Value. 0 4 read-only PCA_0 A None PCA 0x4000f000 0x0 0xffc registers PCA0_IRQn 25 MODE Module Operating Mode 0x180 0x00000000 0xFFFFFFFF CLKDIV Input Clock Divisor. 0 10 CLKSEL Input Clock (F<subscript>CLKIN</subscript>) Select. 10 3 APB Set the APB as the input clock (FCLKIN). 0 TIMER0 Set Timer 0 low overflows divided by 2 as the input clock (FCLKIN). 1 HL_ECI Set high-to-low transitions on ECI divided by 2 as the input clock (FCLKIN). 2 EXTOSCN Set the external oscillator module output (EXTOSCn) divided by 2 as the input clock (FCLKIN). 3 ECI Set ECI transitions divided by 2 as the input clock (FCLKIN). 4 CONTROL Module Control 0x190 0x00000000 0xFFFFFFFF OVFIEN PCA Counter Overflow/Limit Interrupt Enable. 0 1 DISABLED Disable the PCA counter overflow/limit event interrupt. 0 ENABLED Enable the PCA counter overflow/limit event interrupt. 1 DBGMD PCA Debug Mode. 6 1 HALT A debug breakpoint will cause the PCA to halt. 0 RUN The PCA will continue to operate while the core is halted in debug mode. 1 DIVST Clock Divider Output State. 21 1 OUTPUT_HIGH The clock divider is currently in the first half-cycle. 0 OUTPUT_LOW The clock divider is currently in the second half-cycle. 1 DIV Current Clock Divider Count. 22 10 STATUS Module Status 0x1a0 0x00000000 0xFFFFFFFF C0CCI Channel 0 Capture/Compare Interrupt Flag. 0 1 NOT_SET A Channel 0 match or capture event did not occur. 0 SET A Channel 0 match or capture event occurred. 1 C1CCI Channel 1 Capture/Compare Interrupt Flag. 1 1 NOT_SET A Channel 1 match or capture event did not occur. 0 SET A Channel 1 match or capture event occurred. 1 RUN Counter/Timer Run. 6 1 STOP Stop the PCA Counter/Timer. 0 START Start the PCA Counter/Timer. 1 OVFI Counter/Timer Overflow/Limit Interrupt Flag. 7 1 NOT_SET A PCA Counter/Timer overflow/limit event did not occur. 0 SET A PCA Counter/Timer overflow/limit event occurred. 1 C0IOVFI Channel 0 Intermediate Overflow Interrupt Flag. 10 1 NOT_SET Channel 0 did not count past the channel n-bit mode limit. 0 SET Channel 0 counted past the channel n-bit mode limit. 1 C1IOVFI Channel 1 Intermediate Overflow Interrupt Flag. 11 1 NOT_SET Channel 1 did not count past the channel n-bit mode limit. 0 SET Channel 1 counted past the channel n-bit mode limit. 1 COUNTER Module Counter/Timer 0x1b0 0x00000000 0xFFFFFFFF COUNTER Counter/Timer. 0 16 LIMIT Module Counter/Timer Upper Limit 0x1c0 0x0000FFFF 0xFFFFFFFF LIMIT Upper Limit. 0 16 MODE_0 Channel Capture/Compare Mode 0x0 0x00000000 0xFFFFFFFF COSEL Channel Output Function Select. 0 2 TOGGLE_OUTPUT Toggle the channel output at the next capture/compare, overflow, or intermediate event. 0 SET_OUTPUT Set the channel output at the next capture/compare, overflow, or intermediate event. 1 CLEAR_OUTPUT Clear the output at the next capture/compare, overflow, or intermediate event. 2 NO_CHANGE Capture/Compare, overflow, or intermediate events do not control the output state. 3 PWMMD PWM N-Bit Mode. 2 4 CMD Channel Operating Mode. 8 3 EDGE_PWM Configure the channel for edge-aligned PWM mode. 0 CENTER_ALIGNED_PWM Configure the channel for center-aligned PWM mode. 1 HF_SQUARE_WAVE Configure the channel for high-frequency/square-wave mode. 2 TIMER_CAPTURE Configure the channel for timer/capture mode. 3 N_BIT_PWM Configure the channel for n-bit edge-aligned PWM mode. 4 CONTROL_0 Channel Capture/Compare Control 0x10 0x00000000 0xFFFFFFFF COUTST Channel Output State. 0 1 LOW The channel output state is low. 0 HIGH The channel output state is high. 1 CPCAPEN Positive Edge Input Capture Enable. 1 1 DISABLED Disable positive-edge input capture. 0 ENABLED Enable positive-edge input capture. 1 CNCAPEN Negative Edge Input Capture Enable. 2 1 DISABLED Disable negative-edge input capture. 0 ENABLED Enable negative-edge input capture. 1 CUPDCF Channel Register Update Complete Flag. 3 1 NOT_SET A PCA channel register update completed or is not pending. 0 SET A PCA channel register update has not completed and is still pending. 1 CCIEN Capture/Compare Interrupt Enable. 8 1 DISABLED Disable the channel capture/compare interrupt. 0 ENABLED Enable the channel capture/compare interrupt. 1 CIOVFIEN Intermediate Overflow Interrupt Enable. 11 1 DISABLED Disable the channel intermediate overflow interrupt. 0 ENABLED Enable the channel intermediate overflow interrupt. 1 CCAPV_0 Channel Compare Value 0x20 0x00000000 0xFFFFFFFF CCAPV Channel Compare Value. 0 18 CCAPVUPD_0 Channel Compare Update Value 0x30 0x00000000 0xFFFFFFFF CCAPVUPD Channel Compare Update Value. 0 18 MODE_1 Channel Capture/Compare Mode 0x40 0x00000000 0xFFFFFFFF COSEL Channel Output Function Select. 0 2 TOGGLE_OUTPUT Toggle the channel output at the next capture/compare, overflow, or intermediate event. 0 SET_OUTPUT Set the channel output at the next capture/compare, overflow, or intermediate event. 1 CLEAR_OUTPUT Clear the output at the next capture/compare, overflow, or intermediate event. 2 NO_CHANGE Capture/Compare, overflow, or intermediate events do not control the output state. 3 PWMMD PWM N-Bit Mode. 2 4 CMD Channel Operating Mode. 8 3 EDGE_PWM Configure the channel for edge-aligned PWM mode. 0 CENTER_ALIGNED_PWM Configure the channel for center-aligned PWM mode. 1 HF_SQUARE_WAVE Configure the channel for high-frequency/square-wave mode. 2 TIMER_CAPTURE Configure the channel for timer/capture mode. 3 N_BIT_PWM Configure the channel for n-bit edge-aligned PWM mode. 4 CONTROL_1 Channel Capture/Compare Control 0x50 0x00000000 0xFFFFFFFF COUTST Channel Output State. 0 1 LOW The channel output state is low. 0 HIGH The channel output state is high. 1 CPCAPEN Positive Edge Input Capture Enable. 1 1 DISABLED Disable positive-edge input capture. 0 ENABLED Enable positive-edge input capture. 1 CNCAPEN Negative Edge Input Capture Enable. 2 1 DISABLED Disable negative-edge input capture. 0 ENABLED Enable negative-edge input capture. 1 CUPDCF Channel Register Update Complete Flag. 3 1 NOT_SET A PCA channel register update completed or is not pending. 0 SET A PCA channel register update has not completed and is still pending. 1 CCIEN Capture/Compare Interrupt Enable. 8 1 DISABLED Disable the channel capture/compare interrupt. 0 ENABLED Enable the channel capture/compare interrupt. 1 CIOVFIEN Intermediate Overflow Interrupt Enable. 11 1 DISABLED Disable the channel intermediate overflow interrupt. 0 ENABLED Enable the channel intermediate overflow interrupt. 1 CCAPV_1 Channel Compare Value 0x60 0x00000000 0xFFFFFFFF CCAPV Channel Compare Value. 0 18 CCAPVUPD_1 Channel Compare Update Value 0x70 0x00000000 0xFFFFFFFF CCAPVUPD Channel Compare Update Value. 0 18 PCA_1 A None PCA 0x40010000 0x0 0xffc registers PCA1_IRQn 26 MODE Module Operating Mode 0x180 0x00000000 0xFFFFFFFF CLKDIV Input Clock Divisor. 0 10 CLKSEL Input Clock (F<subscript>CLKIN</subscript>) Select. 10 3 APB Set the APB as the input clock (FCLKIN). 0 TIMER0 Set Timer 0 low overflows divided by 2 as the input clock (FCLKIN). 1 HL_ECI Set high-to-low transitions on ECI divided by 2 as the input clock (FCLKIN). 2 EXTOSCN Set the external oscillator module output (EXTOSCn) divided by 2 as the input clock (FCLKIN). 3 ECI Set ECI transitions divided by 2 as the input clock (FCLKIN). 4 CONTROL Module Control 0x190 0x00000000 0xFFFFFFFF OVFIEN PCA Counter Overflow/Limit Interrupt Enable. 0 1 DISABLED Disable the PCA counter overflow/limit event interrupt. 0 ENABLED Enable the PCA counter overflow/limit event interrupt. 1 DBGMD PCA Debug Mode. 6 1 HALT A debug breakpoint will cause the PCA to halt. 0 RUN The PCA will continue to operate while the core is halted in debug mode. 1 DIVST Clock Divider Output State. 21 1 OUTPUT_HIGH The clock divider is currently in the first half-cycle. 0 OUTPUT_LOW The clock divider is currently in the second half-cycle. 1 DIV Current Clock Divider Count. 22 10 STATUS Module Status 0x1a0 0x00000000 0xFFFFFFFF C0CCI Channel 0 Capture/Compare Interrupt Flag. 0 1 NOT_SET A Channel 0 match or capture event did not occur. 0 SET A Channel 0 match or capture event occurred. 1 C1CCI Channel 1 Capture/Compare Interrupt Flag. 1 1 NOT_SET A Channel 1 match or capture event did not occur. 0 SET A Channel 1 match or capture event occurred. 1 RUN Counter/Timer Run. 6 1 STOP Stop the PCA Counter/Timer. 0 START Start the PCA Counter/Timer. 1 OVFI Counter/Timer Overflow/Limit Interrupt Flag. 7 1 NOT_SET A PCA Counter/Timer overflow/limit event did not occur. 0 SET A PCA Counter/Timer overflow/limit event occurred. 1 C0IOVFI Channel 0 Intermediate Overflow Interrupt Flag. 10 1 NOT_SET Channel 0 did not count past the channel n-bit mode limit. 0 SET Channel 0 counted past the channel n-bit mode limit. 1 C1IOVFI Channel 1 Intermediate Overflow Interrupt Flag. 11 1 NOT_SET Channel 1 did not count past the channel n-bit mode limit. 0 SET Channel 1 counted past the channel n-bit mode limit. 1 COUNTER Module Counter/Timer 0x1b0 0x00000000 0xFFFFFFFF COUNTER Counter/Timer. 0 16 LIMIT Module Counter/Timer Upper Limit 0x1c0 0x0000FFFF 0xFFFFFFFF LIMIT Upper Limit. 0 16 MODE_0 Channel Capture/Compare Mode 0x0 0x00000000 0xFFFFFFFF COSEL Channel Output Function Select. 0 2 TOGGLE_OUTPUT Toggle the channel output at the next capture/compare, overflow, or intermediate event. 0 SET_OUTPUT Set the channel output at the next capture/compare, overflow, or intermediate event. 1 CLEAR_OUTPUT Clear the output at the next capture/compare, overflow, or intermediate event. 2 NO_CHANGE Capture/Compare, overflow, or intermediate events do not control the output state. 3 PWMMD PWM N-Bit Mode. 2 4 CMD Channel Operating Mode. 8 3 EDGE_PWM Configure the channel for edge-aligned PWM mode. 0 CENTER_ALIGNED_PWM Configure the channel for center-aligned PWM mode. 1 HF_SQUARE_WAVE Configure the channel for high-frequency/square-wave mode. 2 TIMER_CAPTURE Configure the channel for timer/capture mode. 3 N_BIT_PWM Configure the channel for n-bit edge-aligned PWM mode. 4 CONTROL_0 Channel Capture/Compare Control 0x10 0x00000000 0xFFFFFFFF COUTST Channel Output State. 0 1 LOW The channel output state is low. 0 HIGH The channel output state is high. 1 CPCAPEN Positive Edge Input Capture Enable. 1 1 DISABLED Disable positive-edge input capture. 0 ENABLED Enable positive-edge input capture. 1 CNCAPEN Negative Edge Input Capture Enable. 2 1 DISABLED Disable negative-edge input capture. 0 ENABLED Enable negative-edge input capture. 1 CUPDCF Channel Register Update Complete Flag. 3 1 NOT_SET A PCA channel register update completed or is not pending. 0 SET A PCA channel register update has not completed and is still pending. 1 CCIEN Capture/Compare Interrupt Enable. 8 1 DISABLED Disable the channel capture/compare interrupt. 0 ENABLED Enable the channel capture/compare interrupt. 1 CIOVFIEN Intermediate Overflow Interrupt Enable. 11 1 DISABLED Disable the channel intermediate overflow interrupt. 0 ENABLED Enable the channel intermediate overflow interrupt. 1 CCAPV_0 Channel Compare Value 0x20 0x00000000 0xFFFFFFFF CCAPV Channel Compare Value. 0 18 CCAPVUPD_0 Channel Compare Update Value 0x30 0x00000000 0xFFFFFFFF CCAPVUPD Channel Compare Update Value. 0 18 MODE_1 Channel Capture/Compare Mode 0x40 0x00000000 0xFFFFFFFF COSEL Channel Output Function Select. 0 2 TOGGLE_OUTPUT Toggle the channel output at the next capture/compare, overflow, or intermediate event. 0 SET_OUTPUT Set the channel output at the next capture/compare, overflow, or intermediate event. 1 CLEAR_OUTPUT Clear the output at the next capture/compare, overflow, or intermediate event. 2 NO_CHANGE Capture/Compare, overflow, or intermediate events do not control the output state. 3 PWMMD PWM N-Bit Mode. 2 4 CMD Channel Operating Mode. 8 3 EDGE_PWM Configure the channel for edge-aligned PWM mode. 0 CENTER_ALIGNED_PWM Configure the channel for center-aligned PWM mode. 1 HF_SQUARE_WAVE Configure the channel for high-frequency/square-wave mode. 2 TIMER_CAPTURE Configure the channel for timer/capture mode. 3 N_BIT_PWM Configure the channel for n-bit edge-aligned PWM mode. 4 CONTROL_1 Channel Capture/Compare Control 0x50 0x00000000 0xFFFFFFFF COUTST Channel Output State. 0 1 LOW The channel output state is low. 0 HIGH The channel output state is high. 1 CPCAPEN Positive Edge Input Capture Enable. 1 1 DISABLED Disable positive-edge input capture. 0 ENABLED Enable positive-edge input capture. 1 CNCAPEN Negative Edge Input Capture Enable. 2 1 DISABLED Disable negative-edge input capture. 0 ENABLED Enable negative-edge input capture. 1 CUPDCF Channel Register Update Complete Flag. 3 1 NOT_SET A PCA channel register update completed or is not pending. 0 SET A PCA channel register update has not completed and is still pending. 1 CCIEN Capture/Compare Interrupt Enable. 8 1 DISABLED Disable the channel capture/compare interrupt. 0 ENABLED Enable the channel capture/compare interrupt. 1 CIOVFIEN Intermediate Overflow Interrupt Enable. 11 1 DISABLED Disable the channel intermediate overflow interrupt. 0 ENABLED Enable the channel intermediate overflow interrupt. 1 CCAPV_1 Channel Compare Value 0x60 0x00000000 0xFFFFFFFF CCAPV Channel Compare Value. 0 18 CCAPVUPD_1 Channel Compare Update Value 0x70 0x00000000 0xFFFFFFFF CCAPVUPD Channel Compare Update Value. 0 18 PMU_0 A None PMU_0 0x40048000 0x0 0xffc registers CONTROL Module Control 0x0 0x00000000 0xFFFFFFFF WAKECLR Wakeup Source Clear. 0 1 write-only CLEAR Clear all wakeup sources. 0 PERILPEN Peripheral Low Power Enable. 1 1 DISABLED Disable the peripheral low power state. 0 ENABLED Enable the peripheral low power state. The peripherals will not be accessible in this state. 1 PINLPEN Pin Low Power Enable. 2 1 DISABLED Disable the pin low power state. 0 ENABLED Enable the pin low power state. The pins will not be accessible in this state. 1 PWAKEEN Pin Wake Match Enable. 3 1 DISABLED Disable Pin Wake. 0 ENABLED Enable Pin Wake. 1 PMUASLPEN PMU Asleep Pin Enable. 4 1 DISABLED Disable the PMU Asleep pin. 0 ENABLED Enable the PMU Asleep pin. 1 CONFIG Module Configuration 0x10 0x00000100 0xFFFFFFFF RTC0FREN RTC0 Fail RTC0/LPTIMER0 Reset Enable. 8 1 DISABLED An RTC0 fail event does not cause the RTC0 and LPTIMER0 modules to reset. 0 ENABLED An RTC0 fail event causes the RTC0 and LPTIMER0 modules to reset. 1 RTC0AREN RTC0 Alarm RTC0/LPTIMER0 Reset Enable. 9 1 DISABLED An RTC0 alarm event does not cause the RTC0 and LPTIMER0 modules to reset. 0 ENABLED An RTC0 alarm event causes the RTC0 and LPTIMER0 modules to reset. 1 CMP0REN Comparator 0 RTC0/LPTIMER0 Reset Enable. 13 1 DISABLED A Comparator 0 event does not cause the RTC0 and LPTIMER0 modules to reset. 0 ENABLED A Comparator 0 event causes the RTC0 and LPTIMER0 modules to reset. 1 PWAKEREN Pin Wake RTC0/LPTIMER0 Reset Enable. 14 1 DISABLED A Pin Wake event does not cause the RTC0 and LPTIMER0 modules to reset. 0 ENABLED A Pin Wake event causes the RTC0 and LPTIMER0 modules to reset. 1 LPT0REN Low Power Timer RTC0/LPTIMER0 Reset Enable. 15 1 DISABLED An LPTIMER0 event does not cause the RTC0 and LPTIMER0 modules to reset. 0 ENABLED An LPTIMER0 event causes the RTC0 and LPTIMER0 modules to reset. 1 STATUS Module Status 0x20 0x00000006 0xFFFFFFFF PM9EF Power Mode 9 Exited Flag. 0 1 NOT_SET The device has not exited Power Mode 9. 0 SET The device has exited Power Mode 9. This bit must be cleared by firmware. 1 PWAKEF Pin Wake Status Flag. 1 1 read-only SET A Pin Wake event has occurred. 0 NOT_SET A Pin Wake event has not occurred. 1 PORF Power-On Reset Flag. 2 1 NOT_SET A power-on reset did not occur since the last time PORF was cleared. 0 SET A power-on reset occurred. 1 WAKEEN Wake Source Enable 0x30 0x00000100 0xFFFFFFFF RTC0FWEN RTC0 Fail Wake Enable. 0 1 DISABLED An RTC0 fail event does not wake the device. 0 ENABLED An RTC0 fail event awakens the device. 1 RTC0AWEN RTC0 Alarm Wake Enable. 1 1 DISABLED An RTC0 alarm event does not wake the device. 0 ENABLED An RTC0 alarm event awakens the device. 1 CMP0WEN Comparator 0 Wake Enable. 5 1 DISABLED A Comparator 0 event does not wake the device. 0 ENABLED A Comparator 0 event awakens the device. 1 PWAKEWEN Pin Wake Wake Enable. 6 1 DISABLED A Pin Wake event does not wake the device. 0 ENABLED A Pin Wake event awakens the device. 1 LPT0WEN Low Power Timer Wake Enable. 7 1 DISABLED An LPTIMER0 event does not wake the device. 0 ENABLED An LPTIMER0 event awakens the device. 1 RSTWEN Reset Pin Wake Enable. 8 1 DISABLED A /RESET Pin event does not wake the device. 0 ENABLED A /RESET Pin event awakens the device. 1 WAKESTATUS Wake Source Status 0x40 0x00000000 0xFFFFFFFF RTC0FWF RTC0 Fail Wake Flag. 0 1 read-only NOT_SET An RTC0 fail event did not wake the device. 0 SET An RTC0 fail event woke the device. 1 RTC0AWF RTC0 Alarm Wake Flag. 1 1 read-only NOT_SET An RTC0 alarm event did not wake the device. 0 SET An RTC0 alarm event woke the device. 1 CMP0WF Comparator 0 Wake Flag. 5 1 read-only NOT_SET A Comparator 0 event did not wake the device. 0 SET A Comparator 0 event woke the device. 1 PWAKEWF Pin Wake Wake Flag. 6 1 read-only NOT_SET A Pin Wake event did not wake the device. 0 SET A Pin Wake event woke the device. 1 LPT0WF Low Power Timer Wake Flag. 7 1 read-only NOT_SET An LPTIMER0 event did not wake the device. 0 SET An LPTIMER0 event woke the device. 1 RSTWF Reset Pin Wake Flag. 8 1 read-only NOT_SET A /RESET Pin event did not wake the device. 0 SET A /RESET Pin event woke the device. 1 PWEN Pin Wake Pin Enable 0x50 0x00000000 0xFFFFFFFF PW0EN WAKE.0 Enable. 0 1 DISABLED WAKE.0 (PB0.12) is not used in the Pin Wake comparison. 0 ENABLED WAKE.0 (PB0.12) is used in the Pin Wake comparison. 1 PW1EN WAKE.1 Enable. 1 1 DISABLED WAKE.1 (PB0.13) is not used in the Pin Wake comparison. 0 ENABLED WAKE.1 (PB0.13) is used in the Pin Wake comparison. 1 PW2EN WAKE.2 Enable. 2 1 DISABLED WAKE.2 (PB0.14) is not used in the Pin Wake comparison. 0 ENABLED WAKE.2 (PB0.14) is used in the Pin Wake comparison. 1 PW3EN WAKE.3 Enable. 3 1 DISABLED WAKE.3 (PB0.15) is not used in the Pin Wake comparison. 0 ENABLED WAKE.3 (PB0.15) is used in the Pin Wake comparison. 1 PW4EN WAKE.4 Enable. 4 1 DISABLED WAKE.4 (PB1.0) is not used in the Pin Wake comparison. 0 ENABLED WAKE.4 (PB1.0) is used in the Pin Wake comparison. 1 PW5EN WAKE.5 Enable. 5 1 DISABLED WAKE.5 (PB1.1) is not used in the Pin Wake comparison. 0 ENABLED WAKE.5 (PB1.1) is used in the Pin Wake comparison. 1 PW6EN WAKE.6 Enable. 6 1 DISABLED WAKE.6 (RESERVED) is not used in the Pin Wake comparison. 0 ENABLED WAKE.6 (RESERVED) is used in the Pin Wake comparison. 1 PW7EN WAKE.7 Enable. 7 1 DISABLED WAKE.7 (RESERVED) is not used in the Pin Wake comparison. 0 ENABLED WAKE.7 (RESERVED) is used in the Pin Wake comparison. 1 PW8EN WAKE.8 Enable. 8 1 DISABLED WAKE.8 (RESERVED) is not used in the Pin Wake comparison. 0 ENABLED WAKE.8 (RESERVED) is used in the Pin Wake comparison. 1 PW9EN WAKE.9 Enable. 9 1 DISABLED WAKE.9 (RESERVED) is not used in the Pin Wake comparison. 0 ENABLED WAKE.9 (RESERVED) is used in the Pin Wake comparison. 1 PW10EN WAKE.10 Enable. 10 1 DISABLED WAKE.10 (RESERVED) is not used in the Pin Wake comparison. 0 ENABLED WAKE.10 (RESERVED) is used in the Pin Wake comparison. 1 PW11EN WAKE.11 Enable. 11 1 DISABLED WAKE.11 (RESERVED) is not used in the Pin Wake comparison. 0 ENABLED WAKE.11 (RESERVED) is used in the Pin Wake comparison. 1 PW12EN WAKE.12 Enable. 12 1 DISABLED WAKE.12 (PB3.0) is not used in the Pin Wake comparison. 0 ENABLED WAKE.12 (PB3.0) is used in the Pin Wake comparison. 1 PW13EN WAKE.13 Enable. 13 1 DISABLED WAKE.13 (PB3.1) is not used in the Pin Wake comparison. 0 ENABLED WAKE.13 (PB3.1) is used in the Pin Wake comparison. 1 PW14EN WAKE.14 Enable. 14 1 DISABLED WAKE.14 (PB3.2) is not used in the Pin Wake comparison. 0 ENABLED WAKE.14 (PB3.2) is used in the Pin Wake comparison. 1 PW15EN WAKE.15 Enable. 15 1 DISABLED WAKE.15 (PB3.3) is not used in the Pin Wake comparison. 0 ENABLED WAKE.15 (PB3.3) is used in the Pin Wake comparison. 1 PWPOL Pin Wake Pin Polarity Select 0x60 0x00000000 0xFFFFFFFF PW0POL WAKE.0 Polarity Select. 0 1 LOW The WAKE.0 (PB0.12) comparison value is logic low. 0 HIGH The WAKE.0 (PB0.12) comparison value is logic high. 1 PW1POL WAKE.1 Polarity Select. 1 1 LOW The WAKE.1 (PB0.13) comparison value is logic low. 0 HIGH The WAKE.1 (PB0.13) comparison value is logic high. 1 PW2POL WAKE.2 Polarity Select. 2 1 LOW The WAKE.2 (PB0.14) comparison value is logic low. 0 HIGH The WAKE.2 (PB0.14) comparison value is logic high. 1 PW3POL WAKE.3 Polarity Select. 3 1 LOW The WAKE.3 (PB0.15) comparison value is logic low. 0 HIGH The WAKE.3 (PB0.15) comparison value is logic high. 1 PW4POL WAKE.4 Polarity Select. 4 1 LOW The WAKE.4 (PB1.0) comparison value is logic low. 0 HIGH The WAKE.4 (PB1.0) comparison value is logic high. 1 PW5POL WAKE.5 Polarity Select. 5 1 LOW The WAKE.5 (PB1.1) comparison value is logic low. 0 HIGH The WAKE.5 (PB1.1) comparison value is logic high. 1 PW6POL WAKE.6 Polarity Select. 6 1 LOW The WAKE.6 (RESERVED) comparison value is logic low. 0 HIGH The WAKE.6 (RESERVED) comparison value is logic high. 1 PW7POL WAKE.7 Polarity Select. 7 1 LOW The WAKE.7 (RESERVED) comparison value is logic low. 0 HIGH The WAKE.7 (RESERVED) comparison value is logic high. 1 PW8POL WAKE.8 Polarity Select. 8 1 LOW The WAKE.8 (RESERVED) comparison value is logic low. 0 HIGH The WAKE.8 (RESERVED) comparison value is logic high. 1 PW9POL WAKE.9 Polarity Select. 9 1 LOW The WAKE.9 (RESERVED) comparison value is logic low. 0 HIGH The WAKE.9 (RESERVED) comparison value is logic high. 1 PW10POL WAKE.10 Polarity Select. 10 1 LOW The WAKE.10 (RESERVED) comparison value is logic low. 0 HIGH The WAKE.10 (RESERVED) comparison value is logic high. 1 PW11POL WAKE.11 Polarity Select. 11 1 LOW The WAKE.11 (RESERVED) comparison value is logic low. 0 HIGH The WAKE.11 (RESERVED) comparison value is logic high. 1 PW12POL WAKE.12 Polarity Select. 12 1 LOW The WAKE.12 (PB3.0) comparison value is logic low. 0 HIGH The WAKE.12 (PB3.0) comparison value is logic high. 1 PW13POL WAKE.13 Polarity Select. 13 1 LOW The WAKE.13 (PB3.1) comparison value is logic low. 0 HIGH The WAKE.13 (PB3.1) comparison value is logic high. 1 PW14POL WAKE.14 Polarity Select. 14 1 LOW The WAKE.14 (PB3.2) comparison value is logic low. 0 HIGH The WAKE.14 (PB3.2) comparison value is logic high. 1 PW15POL WAKE.15 Polarity Select. 15 1 LOW The WAKE.15 (PB3.3) comparison value is logic low. 0 HIGH The WAKE.15 (PB3.3) comparison value is logic high. 1 PBCFG_0 A None PBCFG_0 0x4002a000 0x0 0xffc registers PBEXT0_IRQn 1 PBEXT1_IRQn 2 PMATCH_IRQn 45 CONTROL0 Global Port Control 0 0x0 0x80000000 0xFFFFFFFF INT0SEL External Interrupt 0 Pin Selection. 0 4 INT0_0 Select INT0.0 (PB3.0) 0 INT0_1 Select INT0.1 (PB3.1) 1 INT0_2 Select INT0.2 (PB3.2) 2 INT0_3 Select INT0.3 (PB3.3) 3 INT0_4 Select INT0.4 (RESERVED) 4 INT0_5 Select INT0.5 (RESERVED) 5 INT0_6 Select INT0.6 (RESERVED) 6 INT0_7 Select INT0.7 (RESERVED) 7 INT0_8 Select INT0.8 (RESERVED) 8 INT0_9 Select INT0.9 (RESERVED) 9 INT0_10 Select INT0.10 (RESERVED) 10 INT0_11 Select INT0.11 (RESERVED) 11 INT0_12 Select INT0.12 (RESERVED) 12 INT0_13 Select INT0.13 (RESERVED) 13 INT0_14 Select INT0.14 (RESERVED) 14 INT0_15 Select INT0.15 (RESERVED) 15 INT0POL External Interrupt 0 Polarity. 4 1 LOW A low value or falling edge on the selected pin will cause interrupt. 0 HIGH A high value or rising edge on the selected pin will cause interrupt. 1 INT0MD External Interrupt 0 Mode. 5 1 LEVEL Interrupt based on level sensitivity. 0 EDGE Interrupt based on edge sensitivity. 1 INT0EN External Interrupt 0 Enable. 7 1 DISABLED Disable external interrupt 0. 0 ENABLED Enable external interrupt 0. 1 INT1SEL External Interrupt 1 Pin Selection. 8 4 INT1_0 Select INT1.0 (PB3.0) 0 INT1_1 Select INT1.1 (PB3.1) 1 INT1_2 Select INT1.2 (PB3.2) 2 INT1_3 Select INT1.3 (PB3.3) 3 INT1_4 Select INT1.4 (RESERVED) 4 INT1_5 Select INT1.5 (RESERVED) 5 INT1_6 Select INT1.6 (RESERVED) 6 INT1_7 Select INT1.7 (RESERVED) 7 INT1_8 Select INT1.8 (RESERVED) 8 INT1_9 Select INT1.9 (RESERVED) 9 INT1_10 Select INT1.10 (RESERVED) 10 INT1_11 Select INT1.11 (RESERVED) 11 INT1_12 Select INT1.12 (RESERVED) 12 INT1_13 Select INT1.13 (RESERVED) 13 INT1_14 Select INT1.14 (RESERVED) 14 INT1_15 Select INT1.15 (RESERVED) 15 INT1POL External Interrupt 1 Polarity. 12 1 LOW A low value or falling edge on the selected pin will cause interrupt. 0 HIGH A high value or rising edge on the selected pin will cause interrupt. 1 INT1MD External Interrupt 1 Mode. 13 1 LEVEL Interrupt based on level sensitivity. 0 EDGE Interrupt based on edge sensitivity. 1 INT1EN External Interrupt 1 Enable. 15 1 DISABLED Disable external interrupt 1. 0 ENABLED Enable external interrupt 1. 1 PGTIMER Pulse Generator Timer. 24 5 PGDONEF Pulse Generator Timer Done Flag. 31 1 read-only NOT_SET Firmware has written to the PBPGPHASE register, but the Pulse Generator timer has not expired. 0 SET The Pulse Generator cycle finished since the last time PBPGPHASE was written. 1 CONTROL1 Global Port Control 1 0x10 0x00000001 0xFFFFFFFF JTAGEN JTAG Enable. 0 1 DISABLED JTAG functionality is not pinned out. 0 ENABLED JTAG functionality is pinned out. 1 ETMEN ETM Enable. 1 1 DISABLED ETM not pinned out. 0 ENABLED ETM is enabled and pinned out. 1 EMIFBE0BEN EMIF <overline>BE0</overline> Pin Enable. 7 1 DISABLED Disable the EMIF /BE0 pin. 0 ENABLED Enable the /BE0 pin if EMIFEN is also set to 1. 1 EMIFCS1EN EMIF CS1 Pin Enable. 8 1 DISABLED Disable the EMIF CS1 pin. 0 ENABLED Enable the CS1 pin if EMIFEN is also set to 1. 1 EMIFEN EMIF Enable. 9 1 DISABLED Disable the EMIF pins. 0 ENABLED EMIF is enabled and pinned out. 1 EMIFWIDTH EMIF Width. 10 6 AWIDTH_8 EMIF Address[7:0] 0 AWIDTH_9 EMIF Address[8:0], PB2.8 = A[8] 1 AWIDTH_10 EMIF Address[9:0], PB2.7 = A[9] 2 AWIDTH_11 EMIF Address[10:0], PB2.6 = A[10] 3 AWIDTH_12 EMIF Address[11:0], PB2.5 = A[11] 4 AWIDTH_13 EMIF Address[12:0], PB2.4 = A[12] 5 AWIDTH_14 EMIF Address[13:0], PB2.3 = A[13] 6 AWIDTH_15 EMIF Address[14:0], PB2.2 = A[14] 7 AWIDTH_16 EMIF Address[15:0], PB2.1 = A[15] 8 AWIDTH_17 EMIF Address[16:0], PB2.0 = A[16] 9 AWIDTH_18 EMIF Address[17:0], PB1.15 = A[17] 10 AWIDTH_19 EMIF Address[18:0], PB1.14 = A[18] 11 AWIDTH_20 EMIF Address[19:0], PB1.13 = A[19] 12 AWIDTH_21 EMIF Address[20:0], PB1.12 = A[20] 13 AWIDTH_22 EMIF Address[21:0], PB1.11 = A[21] 14 AWIDTH_23 EMIF Address[22:0], PB1.10 = A[22] 15 AWIDTH_24 EMIF Address[23:0], PB1.10 = A[23] 16 MATMD Match Mode. 16 2 PINMATCH Port Match registers used to provide interrupt / wake sources. 0 CAPSENSE_TX Port Match registers used to monitor output pin activity for Capacitive Sensing measurements. 1 CAPSENSE_RX Port Match registers used to monitor input pin activity for Capacitive Sensing measurements. 2 RESERVED Reserved. 3 EVREGRMD External Regulator Reset Mode. 23 1 RESET_ON_ANY The pins used by the external regulator will default to digital inputs with weak pull-up enabled on any reset. 0 RESET_ON_POR The pins used by the external regulator will default to digital inputs with weak pull-up enabled only on Power-On Reset. Their configured mode will be preserved through all other resets. 1 LOCK Port Bank Configuration Lock. 31 1 UNLOCKED Port Bank Configuration and Control registers are unlocked. 0 LOCKED The following registers are locked from write access: CONTROL1, XBAR0L, XBAR0H, XBAR1, and all PBSKIP registers. 1 XBAR0L Crossbar 0 Control (Low) 0x20 0x00000000 0xFFFFFFFF USART0EN USART0 Enable. 0 1 DISABLED Disable USART0 RX and TX on Crossbar 0. 0 ENABLED Enable USART0 RX and TX on Crossbar 0. 1 USART0FCEN USART0 Flow Control Enable. 1 1 DISABLED Disable USART0 flow control on Crossbar 0. 0 ENABLED Enable USART0 flow control on Crossbar 0. 1 USART0CEN USART0 Clock Signal Enable. 2 1 DISABLED Disable USART0 clock on Crossbar 0. 0 ENABLED Enable USART0 clock on Crossbar 0. 1 SPI0EN SPI0 Enable. 3 1 DISABLED Disable SPI0 SCK, MISO, and MOSI on Crossbar 0. 0 ENABLED Enable SPI0 SCK, MISO, and MOSI on Crossbar 0. 1 SPI0NSSEN SPI0 NSS Pin Enable. 4 1 DISABLED Disable SPI0 NSS on Crossbar 0. 0 ENABLED Enable SPI0 NSS on Crossbar 0. 1 USART1EN USART1 Enable. 5 1 DISABLED Disable USART1 RX and TX on Crossbar 0. 0 ENABLED Enable USART1 RX and TX on Crossbar 0. 1 USART1FCEN USART1 Flow Control Enable. 6 1 DISABLED Disable USART1 flow control on Crossbar 0. 0 ENABLED Enable USART1 flow control on Crossbar 0. 1 USART1CEN USART1 Clock Signal Enable. 7 1 DISABLED Disable USART1 clock on Crossbar 0. 0 ENABLED Enable USART1 clock on Crossbar 0. 1 EPCA0EN EPCA0 Channel Enable. 8 3 NONE Disable all EPCA0 channels on Crossbar 0. 0 STD_CEX0 Enable EPCA0 STD_CEX0 on Crossbar 0. 1 STD_CEX0_1 Enable EPCA0 STD_CEX0 and STD_CEX1 on Crossbar 0. 2 STD_CEX0_2 Enable EPCA0 STD_CEX0, STD_CEX1, and STD_CEX2 on Crossbar 0. 3 STD_CEX0_3 Enable EPCA0 STD_CEX0, STD_CEX1, STD_CEX2, and STD_CEX3 on Crossbar 0. 4 STD_CEX0_4 Enable EPCA0 STD_CEX0, STD_CEX1, STD_CEX2, STD_CEX3, and STD_CEX4 on Crossbar 0. 5 STD_CEX0_5 Enable EPCA0 STD_CEX0, STD_CEX1, STD_CEX2, STD_CEX3, STD_CEX4, and STD_CEX5 on Crossbar 0. 6 PCA0EN PCA0 Channel Enable. 14 2 NONE Disable all PCA0 channels on Crossbar 0. 0 CEX0 Enable PCA0 CEX0 on Crossbar 0. 1 CEX0_1 Enable PCA0 CEX0 and CEX1 on Crossbar 0. 3 PCA1EN PCA1 Channel Enable. 16 2 NONE Disable all PCA1 channels on Crossbar 0. 0 CEX0 Enable PCA1 CEX0 on Crossbar 0. 1 CEX0_1 Enable PCA1 CEX0 and CEX1 on Crossbar 0. 3 EECI0EN EPCA0 ECI Enable. 18 1 DISABLED Disable EPCA0 ECI on Crossbar 0. 0 ENABLED Enable EPCA0 ECI on Crossbar 0. 1 ECI0EN PCA0 ECI Enable. 19 1 DISABLED Disable PCA0 ECI on Crossbar 0. 0 ENABLED Enable PCA0 ECI on Crossbar 0. 1 ECI1EN PCA1 ECI Enable. 20 1 DISABLED Disable PCA1 ECI on Crossbar 0. 0 ENABLED Enable PCA1 ECI on Crossbar 0. 1 I2S0TXEN I2S0 TX Enable. 21 1 DISABLED Disable I2S0 TX on Crossbar 0. 0 ENABLED Enable I2S0 TX on Crossbar 0. 1 I2C0EN I2C0 Enable. 22 1 DISABLED Disable I2C0 SDA and SCL on Crossbar 0. 0 ENABLED Enable I2C0 SDA and SCL on Crossbar 0. 1 CMP0SEN Comparator 0 Synchronous Output (CMP0S) Enable. 23 1 DISABLED Disable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0. 0 ENABLED Enable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0. 1 CMP0AEN Comparator 0 Asynchronous Output (CMP0A) Enable. 24 1 DISABLED Disable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0. 0 ENABLED Enable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0. 1 CMP1SEN Comparator 1 Synchronous Output (CMP1S) Enable. 25 1 DISABLED Disable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0. 0 ENABLED Enable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0. 1 CMP1AEN Comparator 1 Asynchronous Output (CMP1A) Enable. 26 1 DISABLED Disable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0. 0 ENABLED Enable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0. 1 TMR0CTEN TIMER0 T0CT Enable. 27 1 DISABLED Disable TIMER0 CT on Crossbar 0. 0 ENABLED Enable TIMER0 CT on Crossbar 0. 1 TMR0EXEN TIMER0 T0EX Enable. 28 1 DISABLED Disable TIMER0 EX on Crossbar 0. 0 ENABLED Enable TIMER0 EX on Crossbar 0. 1 TMR1CTEN TIMER1 T1CT Enable. 29 1 DISABLED Disable TIMER1 CT on Crossbar 0. 0 ENABLED Enable TIMER1 CT on Crossbar 0. 1 TMR1EXEN TIMER1 T1EX Enable. 30 1 DISABLED Disable TIMER1 EX on Crossbar 0. 0 ENABLED Enable TIMER1 EX on Crossbar 0. 1 XBAR0H Crossbar 0 Control (High) 0x30 0x00000000 0xFFFFFFFF UART0EN UART0 Enable. 0 1 DISABLED Disable UART0 RX and TX on Crossbar 0. 0 ENABLED Enable UART0 RX and TX on Crossbar 0. 1 UART0FCEN UART0 Flow Control Enable. 1 1 DISABLED Disable UART0 flow control on Crossbar 0. 0 ENABLED Enable UART0 flow control on Crossbar 0. 1 UART1EN UART1 Enable. 2 1 DISABLED Disable UART1 RX and TX on Crossbar 0. 0 ENABLED Enable UART1 RX and TX on Crossbar 0. 1 SPI1EN SPI1 Enable. 3 1 DISABLED Disable SPI1 SCK, MISO, and MOSI on Crossbar 0. 0 ENABLED Enable SPI1 SCK, MISO, and MOSI on Crossbar 0. 1 SPI1NSSEN SPI1 NSS Pin Enable. 4 1 DISABLED Disable SPI1 NSS on Crossbar 0. 0 ENABLED Enable SPI1 NSS on Crossbar 0. 1 SPI2EN SPI2 Enable. 5 1 DISABLED Disable SPI2 SCK, MISO, and MOSI on Crossbar 0. 0 ENABLED Enable SPI2 SCK, MISO, and MOSI on Crossbar 0. 1 SPI2NSSEN SPI2 NSS Pin Enable. 6 1 DISABLED Disable SPI2 NSS on Crossbar 0. 0 ENABLED Enable SPI2 NSS on Crossbar 0. 1 AHBEN AHB Clock Output Enable. 7 1 DISABLED Disable the AHB Clock / 16 output on Crossbar 0. 0 ENABLED Enable the AHB Clock / 16 output on Crossbar 0. 1 XBAR0EN Crossbar 0 Enable. 31 1 DISABLED Disable Crossbar 0. 0 ENABLED Enable Crossbar 0. 1 XBAR1 Crossbar 1 Control 0x40 0x00000000 0xFFFFFFFF SSG0EN SSG0 Enable. 0 2 NONE Disable all SSG0 channels on Crossbar 1. 0 EX0 Enable SSG0 EX0 on Crossbar 1. 1 EX0_1 Enable SSG0 EX0 and EX1 on Crossbar 1. 2 EX0_3 Enable SSG0 EX0, EX1, EX2, and EX3 on Crossbar 1. 3 CMP0SEN Comparator 0 Synchronous Output (CMP0S) Enable. 2 1 DISABLED Disable Comparator 0 Synchronous Output (CMP0S) on Crossbar 1. 0 ENABLED Enable Comparator 0 Synchronous Output (CMP0S) on Crossbar 1. 1 CMP1SEN Comparator 1 Synchronous Output (CMP1S) Enable. 3 1 DISABLED Disable Comparator 1 Synchronous Output (CMP1S) on Crossbar 1. 0 ENABLED Enable Comparator 1 Synchronous Output (CMP1S) on Crossbar 1. 1 SPI1EN SPI1 Enable. 4 1 DISABLED Disable SPI1 SCK, MISO, and MOSI on Crossbar 1. 0 ENABLED Enable SPI1 SCK, MISO, and MOSI on Crossbar 1. 1 SPI1NSSEN SPI1 NSS Pin Enable. 5 1 DISABLED Disable SPI1 NSS on Crossbar 1. 0 ENABLED Enable SPI1 NSS on Crossbar 1. 1 RTC0EN RTC0 Output Enable. 6 1 DISABLED Disable RTC0 Output on Crossbar 1. 0 ENABLED Enable RTC0 Output on Crossbar 1. 1 SPI2EN SPI2 Enable. 7 1 DISABLED Disable SPI2 SCK, MISO, and MOSI on Crossbar 1. 0 ENABLED Enable SPI2 SCK, MISO, and MOSI on Crossbar 1. 1 SPI2NSSEN SPI2 NSS Pin Enable. 8 1 DISABLED Disable SPI2 NSS on Crossbar 1. 0 ENABLED Enable SPI2 NSS on Crossbar 1. 1 USART1EN USART1 Enable. 9 1 DISABLED Disable USART1 RX and TX on Crossbar 1. 0 ENABLED Enable USART1 RX and TX on Crossbar 1. 1 USART1FCEN USART1 Flow Control Enable. 10 1 DISABLED Disable USART1 flow control on Crossbar 1. 0 ENABLED Enable USART1 flow control on Crossbar 1. 1 USART1CEN USART1 Clock Signal Enable. 11 1 DISABLED Disable USART1 clock on Crossbar 1. 0 ENABLED Enable USART1 clock on Crossbar 1. 1 UART0EN UART0 Enable. 12 1 DISABLED Disable UART0 RX and TX on Crossbar 1. 0 ENABLED Enable UART0 RX and TX on Crossbar 1. 1 UART0FCEN UART0 Flow Control Enable. 13 1 DISABLED Disable UART0 flow control on Crossbar 1. 0 ENABLED Enable UART0 flow control on Crossbar1. 1 I2S0TXEN I2S0 TX Enable. 14 1 DISABLED Disable I2S0 TX on Crossbar 1. 0 ENABLED Enable I2S0 TX on Crossbar 1. 1 I2C0EN I2C0 Enable. 15 1 DISABLED Disable I2C0 SDA and SCL on Crossbar 1. 0 ENABLED Enable I2C0 SDA and SCL on Crossbar 1. 1 UART1EN UART1 Enable. 16 1 DISABLED Disable UART1 RX and TX on Crossbar 1. 0 ENABLED Enable UART1 RX and TX on Crossbar 1. 1 I2S0RXEN I2S0 RX Enable. 17 1 DISABLED Disable I2S0 RX on Crossbar 1. 0 ENABLED Enable I2S0 RX on Crossbar 1. 1 LPT0OEN LPTIMER0 Output Enable. 19 1 DISABLED Disable LPTIMER0 Output on Crossbar 1. 0 ENABLED Enable LPTIMER0 Output on Crossbar 1. 1 I2C1EN I2C1 Enable. 20 1 DISABLED Disable I2C1 SDA and SCL on Crossbar 1. 0 ENABLED Enable I2C1 SDA and SCL on Crossbar 1. 1 KILLHDEN High Drive Kill Pin Enable. 21 1 DISABLED Disable the PB High Drive Kill Pin on Crossbar 1. 0 ENABLED Enable the PB High Drive Kill Pin on Crossbar 1. 1 XBAR1EN Crossbar 1 Enable. 31 1 DISABLED Disable Crossbar 1. 0 ENABLED Enable Crossbar 1. 1 PBKEY Global Port Key 0x50 0x00000000 0xFFFFFFFF KEY Port Bank 2, 3, and 4 Key. 0 8 LOCKED Port Bank 2, 3, and 4 registers are locked and no valid values have been written to PBKEY. 0 INTERMEDIATE Port Bank 2, 3, and 4 registers are locked and the first valid value (0xA5) has been written to PBKEY. 1 UNLOCKED Port Bank 2, 3, and 4 registers are unlocked. Any subsequent writes to the Port Bank 2, 3, or 4 registers or PBKEY will lock the interface. 2 PBHD_4 A None PBHD_4 0x4002a3c0 0x0 0xffc registers PB Output Latch 0x0 0x0000003F 0xFFFFFFFF PB Output Latch. 0 6 PBPIN Pin Value 0x10 0x00000000 0xFFFFFFFF PBPIN Pin Value. 0 6 read-only PBMDSEL Mode Select 0x20 0x0000003F 0xFFFFFFFF PBMDSEL Mode Select. 0 6 PBDEN Driver Enable 0x30 0x00000000 0xFFFFFFFF PBNDEN Port Bank N-Channel Driver Enable. 0 6 PBPDEN Port Bank P-Channel Driver Enable. 16 6 PBDRV Drive Strength 0x40 0x00000000 0xFFFFFFFF PBDRV Drive Strength. 0 6 PBPUEN Port Bank Weak Pull-up Enable. 16 1 DISABLED Disable weak pull-ups for this port. 0 ENABLED Enable weak pull-ups for this port. 1 PBLVMD Port Low Voltage Mode. 17 1 NORMAL Port configured for normal mode. 0 LOW Port configured for low power mode. 1 PBSLEW Port Slew Control. 18 2 FASTEST Select the fastest transition speed for this port bank. 0 FASTER Select the faster transition speed for this port bank. 1 SLOWER Select the slower transition speed for this port bank. 2 SLOWEST Select the slowest transition speed for this port bank. 3 PBBIASEN Port Bias Enable. 21 1 DISABLED Disable the biasing to the port pins. 0 ENABLED Enable the biasing to the port pins. 1 PBDRVEN Port Drive Enable. 22 1 DISABLED Disable the port drivers. 0 ENABLED Enable the port drivers. 1 PBVTRKEN Port Voltage Supply Tracking Enable. 23 1 DISABLED Disable VIOHD tracking. 0 ENABLED Enable VIOHD tracking. 1 PBILIMIT Current Limit 0x50 0x00000000 0xFFFFFFFF PBILEN Current Limit Enable. 0 6 NILIMIT N-Channel Current Limit. 16 4 MODE0 Set sink limit to mode 0. 0 MODE1 Set sink limit to mode 1. 1 MODE2 Set sink limit to mode 2. 2 MODE3 Set sink limit to mode 3. 3 MODE4 Set sink limit to mode 4. 4 MODE5 Set sink limit to mode 5. 5 MODE6 Set sink limit to mode 6. 6 MODE7 Set sink limit to mode 7. 7 MODE8 Set sink limit to mode 8. 8 MODE9 Set sink limit to mode 9. 9 MODE10 Set sink limit to mode 10. 10 MODE11 Set sink limit to mode 11. 11 MODE12 Set sink limit to mode 12. 12 MODE13 Set sink limit to mode 13. 13 MODE14 Set sink limit to mode 14. 14 MODE15 Set sink limit to mode 15. 15 PILIMIT P-Channel Current Limit. 20 4 MODE0 Set source limit to mode 0. 0 MODE1 Set source limit to mode 1. 1 MODE2 Set source limit to mode 2. 2 MODE3 Set source limit to mode 3. 3 MODE4 Set source limit to mode 4. 4 MODE5 Set source limit to mode 5. 5 MODE6 Set source limit to mode 6. 6 MODE7 Set source limit to mode 7. 7 MODE8 Set source limit to mode 8. 8 MODE9 Set source limit to mode 9. 9 MODE10 Set source limit to mode 10. 10 MODE11 Set source limit to mode 11. 11 MODE12 Set source limit to mode 12. 12 MODE13 Set source limit to mode 13. 13 MODE14 Set source limit to mode 14. 14 MODE15 Set source limit to mode 15. 15 PBFSEL Function Select 0x70 0x00000000 0xFFFFFFFF PB0SEL Port Bank n.0 Function Select. 0 2 GPIO Pin configured for GPIO. 0 PMLS Pin configured for Port Mapped Level Shift. 1 EPCA0 Pin configured for EPCA0 output. 2 RESERVED Reserved. 3 PB1SEL Port Bank n.1 Function Select. 2 2 GPIO Pin configured for GPIO. 0 PMLS Pin configured for Port Mapped Level Shift. 1 EPCA0 Pin configured for EPCA0 output. 2 RESERVED Reserved. 3 PB2SEL Port Bank n.2 Function Select. 4 2 GPIO Pin configured for GPIO. 0 PMLS Pin configured for Port Mapped Level Shift. 1 EPCA0 Pin configured for EPCA0 output. 2 UART1 Pin configured for UART1 TX. 3 PB3SEL Port Bank n.3 Function Select. 6 2 GPIO Pin configured for GPIO. 0 PMLS Pin configured for Port Mapped Level Shift. 1 EPCA0 Pin configured for EPCA0 output. 2 UART1 Pin configured for UART1 RX. 3 PB4SEL Port Bank n.4 Function Select. 8 2 GPIO Pin configured for GPIO. 0 PMLS Pin configured for Port Mapped Level Shift. 1 EPCA0 Pin configured for EPCA0 output. 2 UART1 Pin configured for UART1 RTS. 3 PB5SEL Port Bank n.5 Function Select. 10 3 GPIO Pin configured for GPIO. 0 PMLS Pin configured for Port Mapped Level Shift. 1 EPCA0 Pin configured for EPCA0 output. 2 UART1 Pin configured for UART1 CTS. 3 LPTIMER0 Pin configured for LPTIMER0 toggle output. 4 PBSS Safe State Control 0x80 0x00000000 0xFFFFFFFF PB0SSSEL Port Bank n.0 Safe State Select. 0 2 HIZ Place PBn.0 in a High Impedance state. 0 HIGH Drive PBn.0 High. 1 LOW Drive PBn.0 Low. 2 DISABLED Ignore the safe state signal (weak pull-ups disabled). 3 PB1SSSEL Port Bank n.1 Safe State Select. 2 2 HIZ Place PBn.1 in a High Impedance state. 0 HIGH Drive PBn.1 High. 1 LOW Drive PBn.1 Low. 2 DISABLED Ignore the safe state signal (weak pull-ups disabled). 3 PB2SSSEL Port Bank n.2 Safe State Select. 4 2 HIZ Place PBn.2 in a High Impedance state. 0 HIGH Drive PBn.2 High. 1 LOW Drive PBn.2 Low. 2 DISABLED Ignore the safe state signal (weak pull-ups disabled). 3 PB3SSSEL Port Bank n.3 Safe State Select. 6 2 HIZ Place PBn.3 in a High Impedance state. 0 HIGH Drive PBn.3 High. 1 LOW Drive PBn.3 Low. 2 DISABLED Ignore the safe state signal (weak pull-ups disabled). 3 PB4SSSEL Port Bank n.4 Safe State Select. 8 2 HIZ Place PBn.4 in a High Impedance state. 0 HIGH Drive PBn.4 High. 1 LOW Drive PBn.4 Low. 2 DISABLED Ignore the safe state signal (weak pull-ups disabled). 3 PB5SSSEL Port Bank n.5 Safe State Select. 10 2 HIZ Place PBn.5 in a High Impedance state. 0 HIGH Drive PBn.5 High. 1 LOW Drive PBn.5 Low. 2 DISABLED Ignore the safe state signal (weak pull-ups disabled). 3 SSMDEN Enter Safe State Mode. 16 1 DISABLED Disable Safe State. 0 ENABLED Enter Safe State. Each PBn.x pin will enter the states defined by PBxSSSEL. 1 PBSSSMD Safe State Signal Mode. 17 1 DEGLITCH Enable deglitching on the kill signal input. The kill signal must be asserted for two APB clocks to be recognized. 0 IMMEDIATE Disable deglitching on the kill signal input. The kill signal will take immediate effect. 1 PBLOCK Lock Control 0x90 0x0000003F 0xFFFFFFFF PBLOCK Port Bank Lock. 0 6 PBSTD_0 A None Port_Standard 0x4002a0a0 0x0 0xffc registers PB Output Latch 0x0 0x0000FFFF 0xFFFFFFFF PB Output Latch. 0 16 PBPIN Pin Value 0x10 0x00000000 0xFFFFFFFF PBPIN Pin Value. 0 16 read-only PBMDSEL Mode Select 0x20 0x0000FFFF 0xFFFFFFFF PBMDSEL Mode Select. 0 16 PBSKIPEN Crossbar Pin Skip Enable 0x30 0x00000000 0xFFFFFFFF PBSKIPEN Crossbar Pin Skip Enable. 0 16 PBOUTMD Output Mode 0x40 0x00000000 0xFFFFFFFF PBOUTMD Output Mode. 0 16 PBDRV Drive Strength 0x50 0x00010000 0xFFFFFFFF PBDRV Drive Strength. 0 16 PBPUEN Port Bank Weak Pull-up Enable. 16 1 DISABLED Disable weak pull-ups for this port. 0 ENABLED Enable weak pull-ups for this port. 1 PM Port Match Value 0x60 0x00000000 0xFFFFFFFF PM Port Match Value. 0 16 PMEN Port Match Enable 0x70 0x00000000 0xFFFFFFFF PMEN Port Match Enable. 0 16 PBSTD_1 A None Port_Standard 0x4002a140 0x0 0xffc registers PB Output Latch 0x0 0x0000FFFF 0xFFFFFFFF PB Output Latch. 0 16 PBPIN Pin Value 0x10 0x00000000 0xFFFFFFFF PBPIN Pin Value. 0 16 read-only PBMDSEL Mode Select 0x20 0x0000FFFF 0xFFFFFFFF PBMDSEL Mode Select. 0 16 PBSKIPEN Crossbar Pin Skip Enable 0x30 0x00000000 0xFFFFFFFF PBSKIPEN Crossbar Pin Skip Enable. 0 16 PBOUTMD Output Mode 0x40 0x00000000 0xFFFFFFFF PBOUTMD Output Mode. 0 16 PBDRV Drive Strength 0x50 0x00010000 0xFFFFFFFF PBDRV Drive Strength. 0 16 PBPUEN Port Bank Weak Pull-up Enable. 16 1 DISABLED Disable weak pull-ups for this port. 0 ENABLED Enable weak pull-ups for this port. 1 PM Port Match Value 0x60 0x00000000 0xFFFFFFFF PM Port Match Value. 0 16 PMEN Port Match Enable 0x70 0x00000000 0xFFFFFFFF PMEN Port Match Enable. 0 16 PBSTD_2 A None Port_Standard 0x4002a1e0 0x0 0xffc registers PB Output Latch 0x0 0x0000FFFF 0xFFFFFFFF PB Output Latch. 0 16 PBPIN Pin Value 0x10 0x00000000 0xFFFFFFFF PBPIN Pin Value. 0 16 read-only PBMDSEL Mode Select 0x20 0x0000FFFF 0xFFFFFFFF PBMDSEL Mode Select. 0 16 PBSKIPEN Crossbar Pin Skip Enable 0x30 0x00000000 0xFFFFFFFF PBSKIPEN Crossbar Pin Skip Enable. 0 16 PBOUTMD Output Mode 0x40 0x00000000 0xFFFFFFFF PBOUTMD Output Mode. 0 16 PBDRV Drive Strength 0x50 0x00010000 0xFFFFFFFF PBDRV Drive Strength. 0 16 PBPUEN Port Bank Weak Pull-up Enable. 16 1 DISABLED Disable weak pull-ups for this port. 0 ENABLED Enable weak pull-ups for this port. 1 PM Port Match Value 0x60 0x00000000 0xFFFFFFFF PM Port Match Value. 0 16 PMEN Port Match Enable 0x70 0x00000000 0xFFFFFFFF PMEN Port Match Enable. 0 16 PBLOCK Lock Control 0x80 0x00000000 0xFFFFFFFF PBLOCK Port Bank Lock. 0 16 PBPGEN Pulse Generator Pin Enable 0x90 0x00000000 0xFFFFFFFF PBPGEN Pulse Generator Pin Enable. 0 16 PBPGPHASE Pulse Generator Phase 0xa0 0x0000FFFF 0xFFFFFFFF PBPGPH0 Pulse Generator Phase 0. 0 16 PBPGPH1 Pulse Generator Phase 1. 16 16 PBSTD_3 A None Port_Standard 0x4002a320 0x0 0xffc registers PB Output Latch 0x0 0x0000FFFF 0xFFFFFFFF PB Output Latch. 0 16 PBPIN Pin Value 0x10 0x00000000 0xFFFFFFFF PBPIN Pin Value. 0 16 read-only PBMDSEL Mode Select 0x20 0x0000FFFF 0xFFFFFFFF PBMDSEL Mode Select. 0 16 PBSKIPEN Crossbar Pin Skip Enable 0x30 0x00000000 0xFFFFFFFF PBSKIPEN Crossbar Pin Skip Enable. 0 16 PBOUTMD Output Mode 0x40 0x00000000 0xFFFFFFFF PBOUTMD Output Mode. 0 16 PBDRV Drive Strength 0x50 0x00010000 0xFFFFFFFF PBDRV Drive Strength. 0 16 PBPUEN Port Bank Weak Pull-up Enable. 16 1 DISABLED Disable weak pull-ups for this port. 0 ENABLED Enable weak pull-ups for this port. 1 PM Port Match Value 0x60 0x00000000 0xFFFFFFFF PM Port Match Value. 0 16 PMEN Port Match Enable 0x70 0x00000000 0xFFFFFFFF PMEN Port Match Enable. 0 16 PBLOCK Lock Control 0x80 0x00000000 0xFFFFFFFF PBLOCK Port Bank Lock. 0 16 RTC_0 A None RTC_0 0x40029000 0x0 0xffc registers RTCALRM_IRQn 3 RTCFAIL_IRQn 44 CONFIG RTC Configuration 0x0 0x00000000 0xFFFFFFFF ALM0AREN Alarm 0 Automatic Reset Enable. 0 1 DISABLED Disable the Alarm 0 automatic reset. 0 ENABLED Enable the Alarm 0 automatic reset. 1 RUN RTC Timer Enable. 1 1 STOP Stop the RTC timer. 0 START Start the RTC timer running. 1 MCLKEN Missing Clock Detector Enable. 2 1 DISABLED Disable the missing clock detector. 0 ENABLED Enable the missing clock detector. If the missing clock detector triggers, it will generate an RTC Fail event. 1 ASEN Automatic Crystal Load Capacitance Stepping Enable. 3 1 DISABLED Disable automatic load capacitance stepping. 0 ENABLED Enable automatic load capacitance stepping. 1 RTCLC Load Capacitance Value. 4 4 BDEN Bias Doubler Enable. 16 1 DISABLED Disable the bias doubler, saving power. 0 ENABLED Enable the bias doubler, allowing for faster oscillator start up time. 1 CRYSEN Crystal Oscillator Enable. 17 1 DISABLED Disable the crystal oscillator circuitry. 0 ENABLED Enable the crystal oscillator circuitry. 1 AGCEN Automatic Gain Control Enable. 18 1 DISABLED Disable automatic gain control. 0 ENABLED Enable automatic gain control, saving power. 1 ALM0EN Alarm 0 Enable. 24 1 DISABLED Disable RTC Alarm 0. 0 ENABLED Enable RTC Alarm 0. 1 ALM1EN Alarm 1 Enable. 25 1 DISABLED Disable RTC Alarm 1. 0 ENABLED Enable RTC Alarm 1. 1 ALM2EN Alarm 2 Enable. 26 1 DISABLED Disable RTC Alarm 2. 0 ENABLED Enable RTC Alarm 2. 1 RTCOEN RTC0 External Output Enable. 29 1 DISABLED Disable the external RTCnOSC output. 0 ENABLED Enable the external RTCnOSC output. 1 CLKSEL RTC Timer Clock Select. 30 1 RTCNOSC Select the RTC clock (RTCnOSC) as the RTC Timer clock. 0 LFOSCN Select the Low Frequency Oscillator (LFOSCn) clock as the RTC Timer clock. 1 RTCEN RTC Oscillator and Timer Enable. 31 1 DISABLED Disable the RTC Oscillator and Timer. 0 ENABLED Enable the RTC Oscillator and Timer. 1 CONTROL RTC Control 0x10 0x00000000 0xFFFFFFFF ALM0I Alarm 0 Interrupt Flag. 0 1 NOT_SET Alarm 0 event has not occurred. 0 SET Alarm 0 event occurred. 1 ALM1I Alarm 1 Interrupt Flag. 1 1 NOT_SET Alarm 1 event has not occurred. 0 SET Alarm 1 event occurred. 1 ALM2I Alarm 2 Interrupt Flag. 2 1 NOT_SET Alarm 2 event has not occurred. 0 SET Alarm 2 event occurred. 1 TMRCAP RTC Timer Capture. 3 1 NOT_SET RTC timer capture operation is complete. 0 SET Start the RTC timer capture. 1 TMRSET RTC Timer Set. 4 1 NOT_SET RTC timer set operation is complete. 0 SET Start the RTC timer set. 1 CLKVF RTC External Oscillator Valid Flag. 5 1 read-only NOT_SET External oscillator is not valid. 0 SET External oscillator is valid. 1 OSCFI RTC Oscillator Fail Interrupt Flag. 6 1 NOT_SET Oscillator is running. 0 SET Oscillator has failed. 1 HSMDEN RTC High Speed Mode Enable. 7 1 DISABLED Disable high speed mode. 0 ENABLED Enable high speed mode. 1 LRDYF RTC Load Capacitance Ready Flag. 8 1 read-only NOT_SET The load capacitance is currently stepping. 0 SET The load capacitance has reached its programmed value. 1 ALARM0 RTC Alarm 0 0x20 0x00000000 0xFFFFFFFF ALARM0 RTC Alarm 0. 0 32 ALARM1 RTC Alarm 1 0x30 0x00000000 0xFFFFFFFF ALARM1 RTC Alarm 1. 0 32 ALARM2 RTC Alarm 2 0x40 0x00000000 0xFFFFFFFF ALARM2 RTC Alarm 2. 0 32 SETCAP RTC Timer Set/Capture Value 0x50 0x00000000 0xFFFFFFFF SETCAP RTC Timer Set/Capture Value. 0 32 LFOCONTROL LFOSC Control 0x60 0x80000000 0xFFFFFFFF LFOSCEN Low Frequency Oscillator Enable. 31 1 DISABLED Disable the Low Frequency Oscillator (LFOSCn). 0 ENABLED Enable the Low Frequency Oscillator (LFOSCn). 1 LFOSCADJ LFOSC Output Frequency Adjust 0x80 0x00000000 0xFFFFFFFF LFOSCADJ LFOSC Output Frequency Adjust. 0 4 RSTSRC_0 A None RSTSRC_0 0x4002d060 0x0 0xffc registers RESETEN System Reset Source Enable 0x0 0x0000082F 0xFFFFFFFF VMONREN Voltage Supply Monitor VDD Reset Enable. 2 1 DISABLED Disable the Voltage Supply Monitor VDD event as a reset source. 0 ENABLED Enable the Voltage Supply Monitor VDD event as a reset source. 1 MCDREN Missing Clock Detector Reset Enable. 4 1 DISABLED Disable the Missing Clock Detector event as a reset source. 0 ENABLED Enable the Missing Clock Detector event as a reset source. 1 WDTREN Watchdog Timer Reset Enable. 5 1 DISABLED Disable the Watchdog Timer event as a reset source. 0 ENABLED Enable the Watchdog Timer event as a reset source. 1 SWREN Software Reset. 6 1 DISABLED Do not generate a Software Reset. 0 ENABLED Generate a Software Reset. 1 CMP0REN Comparator 0 Reset Enable. 7 1 DISABLED Disable the Comparator 0 event as a reset source. 0 ENABLED Enable the Comparator 0 event as a reset source. 1 CMP1REN Comparator 1 Reset Enable. 8 1 DISABLED Disable the Comparator 1 event as a reset source. 0 ENABLED Enable the Comparator 1 event as a reset source. 1 RTC0REN RTC0 Reset Enable. 10 1 DISABLED Disable the RTC0 event as a reset source. 0 ENABLED Enable the RTC0 event as a reset source. 1 WAKEREN PMU Wakeup Reset Enable. 11 1 ENABLED Enable the PMU Wakeup event as a reset source. 1 RESETFLAG System Reset Flags 0x10 0x00000002 0xFFFFFFFF PINRF Pin Reset Flag. 0 1 read-only NOT_SET A /RESET pin event did not cause the last system reset. 0 SET A /RESET pin event caused the last system reset. 1 PORRF Power-On Reset Flag. 1 1 read-only NOT_SET A Power-On Reset event did not cause the last system reset. 0 SET A Power-On Reset event caused the last system reset. 1 VMONRF Voltage Supply Monitor VDD Reset Flag. 2 1 read-only NOT_SET A Voltage Supply Monitor VDD Reset event did not cause the last system reset. 0 SET A Voltage Supply Monitor VDD Reset event caused the last system reset. 1 CORERF Core Reset Flag. 3 1 read-only NOT_SET A Core Reset event did not cause the last system reset. 0 SET A Core Reset event caused the last system reset. 1 MCDRF Missing Clock Detector Reset Flag. 4 1 read-only NOT_SET A Missing Clock Detector event did not cause the last system reset. 0 SET A Missing Clock Detector event caused the last system reset. 1 WDTRF Watchdog Timer Reset Flag. 5 1 read-only NOT_SET A Watchdog Timer event did not cause the last system reset. 0 SET A Watchdog Timer event caused the last system reset. 1 SWRF Software Reset Flag. 6 1 read-only NOT_SET A Software Reset event did not cause the last system reset. 0 SET A Software Reset event caused the last system reset. 1 CMP0RF Comparator 0 Reset Flag. 7 1 read-only NOT_SET A Comparator 0 event did not cause the last system reset. 0 SET A Comparator 0 event caused the last system reset. 1 CMP1RF Comparator 1 Reset Flag. 8 1 read-only NOT_SET A Comparator 1 event did not cause the last system reset. 0 SET A Comparator 1 event caused the last system reset. 1 RTC0RF RTC0 Reset Flag. 10 1 read-only NOT_SET An RTC0 event did not cause the last system reset. 0 SET An RTC0 event caused the last system reset. 1 WAKERF PMU Wakeup Reset Flag. 11 1 read-only NOT_SET A PMU Wakeup event did not cause the last system reset. 0 SET A PMU Wakeup event caused the last system reset. 1 CONFIG Configuration Options 0x20 0x00000000 0xFFFFFFFF PMSEL Power Mode Select. 0 1 PM9_DIS Power Mode < PM9. 0 PM9_EN Power Mode = PM9. 1 SPI_0 A None SPI 0x40004000 0x0 0xffc registers SPI0_IRQn 29 DATA Input/Output Data 0x0 0x00000000 0xFFFFFFFF modifyExternal DATA Input/Output Data. 0 32 CONTROL Module Control 0x10 0x00004084 0xFFFFFFFF RFRQI Receive FIFO Read Request Interrupt Flag. 0 1 read-only NOT_SET The RX FIFO has fewer bytes than the level defined by RFTH. 0 SET The RX FIFO has equal or more bytes than the level defined by RFTH. 1 RFORI Receive FIFO Overrun Interrupt Flag. 1 1 NOT_SET Read: A receive FIFO overrun has not occurred. Write: Clear the flag. 0 SET Read: A receive FIFO overrun occurred. Write: Force a receive overrun interrupt. 1 TFRQI Transmit FIFO Write Request Interrupt Flag. 2 1 read-only NOT_SET The TX FIFO has fewer bytes than the level defined by TFTH. 0 SET The TX FIFO has equal or more bytes than the level defined by TFTH. 1 TFORI Transmit FIFO Overrun Interrupt Flag. 3 1 NOT_SET Read: A transmit FIFO overrun has not occurred. Write: Clear the flag. 0 SET Read: A transmit FIFO overrun occurred. Write: Force a transmit overrun interrupt. 1 SLVSELI Slave Selected Interrupt Flag. 4 1 read-only NOT_SET The slave select signal (NSS) is not active. 0 SET The slave select signal (NSS) is active. 1 MDFI Mode Fault Interrupt Flag. 5 1 NOT_SET Read: A master mode collision is not detected. Write: Clear the flag. 0 SET Read: A master mode collision occurred. Write: Force a mode fault interrupt. 1 URI Underrun Interrupt Flag. 6 1 NOT_SET Read: A data transfer is still in progress. Write: Clear the flag. 0 SET Read: The transmit FIFO and shift register are empty and the data transfer has ended. Write: Force an underrun interrupt. 1 SREI Shift Register Empty Interrupt Flag. 7 1 read-only NOT_SET There is data still present in the transmit FIFO. 0 SET All data has been transferred out of the shift register and there is no data waiting in the transmit FIFO. 1 RFILI Illegal Receive FIFO Access Interrupt Flag. 8 1 NOT_SET Read: An illegal write or read of the receive FIFO has not occurred. Write: Clear the flag. 0 SET Read: An illegal write or read of the receive FIFO occurred. Write: Force an illegal receive access interrupt. 1 TFILI Illegal Transmit FIFO Access Interrupt Flag. 9 1 NOT_SET Read: An illegal write or read of the transmit FIFO has not occurred. Write: Clear the flag. 0 SET Read: An illegal write or read of the transmit FIFO occurred. Write: Force an illegal transmit access interrupt. 1 NSSSTS NSS Instantaneous Pin Status. 14 1 read-only LOW NSS is currently a logic low. 0 HIGH NSS is currently a logic high. 1 BUSYF SPI Busy. 15 1 read-only NOT_SET The SPI is not busy and a transfer is not in progress. 0 SET The SPI is currently busy and a transfer is in progress. 1 RFCNT Receive FIFO Counter. 16 4 read-only TFCNT Transmit FIFO Counter. 20 4 read-only DBGMD SPI Debug Mode. 24 1 RUN The SPI module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the SPI module to halt. 1 CONFIG Module Configuration 0x20 0x00000000 0xFFFFFFFF RFRQIEN Receive FIFO Read Request Interrupt Enable. 0 1 DISABLED Disable the receive FIFO request interrupt. 0 ENABLED Enable the receive FIFO request interrupt. 1 RFORIEN Receive FIFO Overrun Interrupt Enable. 1 1 DISABLED Disable the receive FIFO overrun interrupt. 0 ENABLED Enable the receive FIFO overrun interrupt. 1 TFRQIEN Transmit FIFO Write Request Interrupt Enable. 2 1 DISABLED Disable the transmit FIFO data request interrupt. 0 ENABLED Enable the transmit FIFO data request interrupt. 1 TFORIEN Transmit FIFO Overrun Interrupt Enable. 3 1 DISABLED Disable the transmit FIFO overrun interrupt. 0 ENABLED Enable the transmit FIFO overrun interrupt. 1 SLVSELIEN Slave Selected Interrupt Enable. 4 1 DISABLED Disable the slave select interrupt. 0 ENABLED Enable the slave select interrupt. 1 MDFIEN Mode Fault Interrupt Enable. 5 1 DISABLED Disable the mode fault interrupt. 0 ENABLED Enable the mode fault interrupt. 1 URIEN Underrun Interrupt Enable. 6 1 DISABLED Disable the underrun interrupt. 0 ENABLED Enable the underrun interrupt. 1 SREIEN Shift Register Empty Interrupt Enable. 7 1 DISABLED Disable the shift register empty interrupt. 0 ENABLED Enable the shift register empty interrupt. 1 SPIEN SPI Enable. 8 1 DISABLED Disable the SPI. 0 ENABLED Enable the SPI. 1 MSTEN Master Mode Enable. 9 1 DISABLED Operate in slave mode. 0 ENABLED Operate in master mode. 1 CLKPOL SPI Clock Polarity. 10 1 LOW The SCK line is low in the idle state. 0 HIGH The SCK line is high in the idle state. 1 CLKPHA SPI Clock Phase. 11 1 CENTER The first edge of SCK is the sample edge (center of data bit). 0 EDGE The first edge of SCK is the shift edge (edge of data bit). 1 NSSPOL Slave Select Polarity Select. 12 1 LOW NSS is active low. 0 HIGH NSS is active high. 1 DDIRSEL Data Direction Select. 13 1 MSB_FIRST Data will be shifted MSB first. 0 LSB_FIRST Data will be shifted LSB first. 1 NSSMD Slave Select Mode. 14 2 3_WIRE_MASTER_SLAVE 3-wire Slave or 3-wire Master. 0 4_WIRE_SLAVE 4-wire slave (NSS input). This setting can also be used for multi-master configurations. 1 4_WIRE_MASTER_NSS_LOW 4-wire master with NSS low (NSS output). 2 4_WIRE_MASTER_NSS_HIGH 4-wire master with NSS high (NSS output). 3 RFTH Receive FIFO Threshold. 16 2 ONE A DMA / RFRQ request asserts when >= 1 FIFO slot is filled. 0 TWO A DMA / RFRQ request asserts when >= 2 FIFO slots are filled. 1 FOUR A DMA / RFRQ request asserts when >= 4 FIFO slots are filled. 2 FULL A DMA / RFRQ request asserts when all FIFO slots are filled. 3 TFTH Transmit FIFO Threshold. 18 2 ONE A DMA / TFRQ request asserts when >= 1 FIFO slot is empty. 0 TWO A DMA / TFRQ request asserts when >= 2 FIFO slots are empty. 1 FOUR A DMA / TFRQ request asserts when >= 4 FIFO slots are empty. 2 EMPTY A DMA / TFRQ request asserts when all FIFO slots are empty. 3 DSIZE Data Size. 20 4 DMAEN DMA Enable. 24 1 DISABLED Disable DMA requests. 0 ENABLED Enable DMA requests when the transmit buffer is empty or the receive buffer is full. 1 RFIFOFL Receive FIFO Flush. 29 1 SET Flush the receive FIFO. 1 TFIFOFL Transmit FIFO Flush. 30 1 SET Flush the transmit FIFO. 1 RESET Module Soft Reset. 31 1 INACTIVE SPI module is not in soft reset. 0 ACTIVE SPI module is in soft reset and some of the module bits cannot be accessed until this bit is cleared to 0 by hardware. 1 CLKRATE Module Clock Rate Control 0x30 0x00000000 0xFFFFFFFF CLKDIV Clock Divider. 0 16 FSTATUS FIFO Status 0x40 0x00000000 0xFFFFFFFF RFRPTR Receive FIFO Read Pointer. 0 4 read-only RFWPTR Receive FIFO Write Pointer. 4 4 read-only TFRPTR Transmit FIFO Read Pointer. 8 4 read-only TFWPTR Transmit FIFO Write Pointer. 12 4 read-only SPI_1 A None SPI 0x40005000 0x0 0xffc registers SPI1_IRQn 30 DATA Input/Output Data 0x0 0x00000000 0xFFFFFFFF modifyExternal DATA Input/Output Data. 0 32 CONTROL Module Control 0x10 0x00004084 0xFFFFFFFF RFRQI Receive FIFO Read Request Interrupt Flag. 0 1 read-only NOT_SET The RX FIFO has fewer bytes than the level defined by RFTH. 0 SET The RX FIFO has equal or more bytes than the level defined by RFTH. 1 RFORI Receive FIFO Overrun Interrupt Flag. 1 1 NOT_SET Read: A receive FIFO overrun has not occurred. Write: Clear the flag. 0 SET Read: A receive FIFO overrun occurred. Write: Force a receive overrun interrupt. 1 TFRQI Transmit FIFO Write Request Interrupt Flag. 2 1 read-only NOT_SET The TX FIFO has fewer bytes than the level defined by TFTH. 0 SET The TX FIFO has equal or more bytes than the level defined by TFTH. 1 TFORI Transmit FIFO Overrun Interrupt Flag. 3 1 NOT_SET Read: A transmit FIFO overrun has not occurred. Write: Clear the flag. 0 SET Read: A transmit FIFO overrun occurred. Write: Force a transmit overrun interrupt. 1 SLVSELI Slave Selected Interrupt Flag. 4 1 read-only NOT_SET The slave select signal (NSS) is not active. 0 SET The slave select signal (NSS) is active. 1 MDFI Mode Fault Interrupt Flag. 5 1 NOT_SET Read: A master mode collision is not detected. Write: Clear the flag. 0 SET Read: A master mode collision occurred. Write: Force a mode fault interrupt. 1 URI Underrun Interrupt Flag. 6 1 NOT_SET Read: A data transfer is still in progress. Write: Clear the flag. 0 SET Read: The transmit FIFO and shift register are empty and the data transfer has ended. Write: Force an underrun interrupt. 1 SREI Shift Register Empty Interrupt Flag. 7 1 read-only NOT_SET There is data still present in the transmit FIFO. 0 SET All data has been transferred out of the shift register and there is no data waiting in the transmit FIFO. 1 RFILI Illegal Receive FIFO Access Interrupt Flag. 8 1 NOT_SET Read: An illegal write or read of the receive FIFO has not occurred. Write: Clear the flag. 0 SET Read: An illegal write or read of the receive FIFO occurred. Write: Force an illegal receive access interrupt. 1 TFILI Illegal Transmit FIFO Access Interrupt Flag. 9 1 NOT_SET Read: An illegal write or read of the transmit FIFO has not occurred. Write: Clear the flag. 0 SET Read: An illegal write or read of the transmit FIFO occurred. Write: Force an illegal transmit access interrupt. 1 NSSSTS NSS Instantaneous Pin Status. 14 1 read-only LOW NSS is currently a logic low. 0 HIGH NSS is currently a logic high. 1 BUSYF SPI Busy. 15 1 read-only NOT_SET The SPI is not busy and a transfer is not in progress. 0 SET The SPI is currently busy and a transfer is in progress. 1 RFCNT Receive FIFO Counter. 16 4 read-only TFCNT Transmit FIFO Counter. 20 4 read-only DBGMD SPI Debug Mode. 24 1 RUN The SPI module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the SPI module to halt. 1 CONFIG Module Configuration 0x20 0x00000000 0xFFFFFFFF RFRQIEN Receive FIFO Read Request Interrupt Enable. 0 1 DISABLED Disable the receive FIFO request interrupt. 0 ENABLED Enable the receive FIFO request interrupt. 1 RFORIEN Receive FIFO Overrun Interrupt Enable. 1 1 DISABLED Disable the receive FIFO overrun interrupt. 0 ENABLED Enable the receive FIFO overrun interrupt. 1 TFRQIEN Transmit FIFO Write Request Interrupt Enable. 2 1 DISABLED Disable the transmit FIFO data request interrupt. 0 ENABLED Enable the transmit FIFO data request interrupt. 1 TFORIEN Transmit FIFO Overrun Interrupt Enable. 3 1 DISABLED Disable the transmit FIFO overrun interrupt. 0 ENABLED Enable the transmit FIFO overrun interrupt. 1 SLVSELIEN Slave Selected Interrupt Enable. 4 1 DISABLED Disable the slave select interrupt. 0 ENABLED Enable the slave select interrupt. 1 MDFIEN Mode Fault Interrupt Enable. 5 1 DISABLED Disable the mode fault interrupt. 0 ENABLED Enable the mode fault interrupt. 1 URIEN Underrun Interrupt Enable. 6 1 DISABLED Disable the underrun interrupt. 0 ENABLED Enable the underrun interrupt. 1 SREIEN Shift Register Empty Interrupt Enable. 7 1 DISABLED Disable the shift register empty interrupt. 0 ENABLED Enable the shift register empty interrupt. 1 SPIEN SPI Enable. 8 1 DISABLED Disable the SPI. 0 ENABLED Enable the SPI. 1 MSTEN Master Mode Enable. 9 1 DISABLED Operate in slave mode. 0 ENABLED Operate in master mode. 1 CLKPOL SPI Clock Polarity. 10 1 LOW The SCK line is low in the idle state. 0 HIGH The SCK line is high in the idle state. 1 CLKPHA SPI Clock Phase. 11 1 CENTER The first edge of SCK is the sample edge (center of data bit). 0 EDGE The first edge of SCK is the shift edge (edge of data bit). 1 NSSPOL Slave Select Polarity Select. 12 1 LOW NSS is active low. 0 HIGH NSS is active high. 1 DDIRSEL Data Direction Select. 13 1 MSB_FIRST Data will be shifted MSB first. 0 LSB_FIRST Data will be shifted LSB first. 1 NSSMD Slave Select Mode. 14 2 3_WIRE_MASTER_SLAVE 3-wire Slave or 3-wire Master. 0 4_WIRE_SLAVE 4-wire slave (NSS input). This setting can also be used for multi-master configurations. 1 4_WIRE_MASTER_NSS_LOW 4-wire master with NSS low (NSS output). 2 4_WIRE_MASTER_NSS_HIGH 4-wire master with NSS high (NSS output). 3 RFTH Receive FIFO Threshold. 16 2 ONE A DMA / RFRQ request asserts when >= 1 FIFO slot is filled. 0 TWO A DMA / RFRQ request asserts when >= 2 FIFO slots are filled. 1 FOUR A DMA / RFRQ request asserts when >= 4 FIFO slots are filled. 2 FULL A DMA / RFRQ request asserts when all FIFO slots are filled. 3 TFTH Transmit FIFO Threshold. 18 2 ONE A DMA / TFRQ request asserts when >= 1 FIFO slot is empty. 0 TWO A DMA / TFRQ request asserts when >= 2 FIFO slots are empty. 1 FOUR A DMA / TFRQ request asserts when >= 4 FIFO slots are empty. 2 EMPTY A DMA / TFRQ request asserts when all FIFO slots are empty. 3 DSIZE Data Size. 20 4 DMAEN DMA Enable. 24 1 DISABLED Disable DMA requests. 0 ENABLED Enable DMA requests when the transmit buffer is empty or the receive buffer is full. 1 RFIFOFL Receive FIFO Flush. 29 1 SET Flush the receive FIFO. 1 TFIFOFL Transmit FIFO Flush. 30 1 SET Flush the transmit FIFO. 1 RESET Module Soft Reset. 31 1 INACTIVE SPI module is not in soft reset. 0 ACTIVE SPI module is in soft reset and some of the module bits cannot be accessed until this bit is cleared to 0 by hardware. 1 CLKRATE Module Clock Rate Control 0x30 0x00000000 0xFFFFFFFF CLKDIV Clock Divider. 0 16 FSTATUS FIFO Status 0x40 0x00000000 0xFFFFFFFF RFRPTR Receive FIFO Read Pointer. 0 4 read-only RFWPTR Receive FIFO Write Pointer. 4 4 read-only TFRPTR Transmit FIFO Read Pointer. 8 4 read-only TFWPTR Transmit FIFO Write Pointer. 12 4 read-only SPI_2 A None SPI 0x40006000 0x0 0xffc registers SPI2_IRQn 31 DATA Input/Output Data 0x0 0x00000000 0xFFFFFFFF modifyExternal DATA Input/Output Data. 0 32 CONTROL Module Control 0x10 0x00004084 0xFFFFFFFF RFRQI Receive FIFO Read Request Interrupt Flag. 0 1 read-only NOT_SET The RX FIFO has fewer bytes than the level defined by RFTH. 0 SET The RX FIFO has equal or more bytes than the level defined by RFTH. 1 RFORI Receive FIFO Overrun Interrupt Flag. 1 1 NOT_SET Read: A receive FIFO overrun has not occurred. Write: Clear the flag. 0 SET Read: A receive FIFO overrun occurred. Write: Force a receive overrun interrupt. 1 TFRQI Transmit FIFO Write Request Interrupt Flag. 2 1 read-only NOT_SET The TX FIFO has fewer bytes than the level defined by TFTH. 0 SET The TX FIFO has equal or more bytes than the level defined by TFTH. 1 TFORI Transmit FIFO Overrun Interrupt Flag. 3 1 NOT_SET Read: A transmit FIFO overrun has not occurred. Write: Clear the flag. 0 SET Read: A transmit FIFO overrun occurred. Write: Force a transmit overrun interrupt. 1 SLVSELI Slave Selected Interrupt Flag. 4 1 read-only NOT_SET The slave select signal (NSS) is not active. 0 SET The slave select signal (NSS) is active. 1 MDFI Mode Fault Interrupt Flag. 5 1 NOT_SET Read: A master mode collision is not detected. Write: Clear the flag. 0 SET Read: A master mode collision occurred. Write: Force a mode fault interrupt. 1 URI Underrun Interrupt Flag. 6 1 NOT_SET Read: A data transfer is still in progress. Write: Clear the flag. 0 SET Read: The transmit FIFO and shift register are empty and the data transfer has ended. Write: Force an underrun interrupt. 1 SREI Shift Register Empty Interrupt Flag. 7 1 read-only NOT_SET There is data still present in the transmit FIFO. 0 SET All data has been transferred out of the shift register and there is no data waiting in the transmit FIFO. 1 RFILI Illegal Receive FIFO Access Interrupt Flag. 8 1 NOT_SET Read: An illegal write or read of the receive FIFO has not occurred. Write: Clear the flag. 0 SET Read: An illegal write or read of the receive FIFO occurred. Write: Force an illegal receive access interrupt. 1 TFILI Illegal Transmit FIFO Access Interrupt Flag. 9 1 NOT_SET Read: An illegal write or read of the transmit FIFO has not occurred. Write: Clear the flag. 0 SET Read: An illegal write or read of the transmit FIFO occurred. Write: Force an illegal transmit access interrupt. 1 NSSSTS NSS Instantaneous Pin Status. 14 1 read-only LOW NSS is currently a logic low. 0 HIGH NSS is currently a logic high. 1 BUSYF SPI Busy. 15 1 read-only NOT_SET The SPI is not busy and a transfer is not in progress. 0 SET The SPI is currently busy and a transfer is in progress. 1 RFCNT Receive FIFO Counter. 16 4 read-only TFCNT Transmit FIFO Counter. 20 4 read-only DBGMD SPI Debug Mode. 24 1 RUN The SPI module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the SPI module to halt. 1 CONFIG Module Configuration 0x20 0x00000000 0xFFFFFFFF RFRQIEN Receive FIFO Read Request Interrupt Enable. 0 1 DISABLED Disable the receive FIFO request interrupt. 0 ENABLED Enable the receive FIFO request interrupt. 1 RFORIEN Receive FIFO Overrun Interrupt Enable. 1 1 DISABLED Disable the receive FIFO overrun interrupt. 0 ENABLED Enable the receive FIFO overrun interrupt. 1 TFRQIEN Transmit FIFO Write Request Interrupt Enable. 2 1 DISABLED Disable the transmit FIFO data request interrupt. 0 ENABLED Enable the transmit FIFO data request interrupt. 1 TFORIEN Transmit FIFO Overrun Interrupt Enable. 3 1 DISABLED Disable the transmit FIFO overrun interrupt. 0 ENABLED Enable the transmit FIFO overrun interrupt. 1 SLVSELIEN Slave Selected Interrupt Enable. 4 1 DISABLED Disable the slave select interrupt. 0 ENABLED Enable the slave select interrupt. 1 MDFIEN Mode Fault Interrupt Enable. 5 1 DISABLED Disable the mode fault interrupt. 0 ENABLED Enable the mode fault interrupt. 1 URIEN Underrun Interrupt Enable. 6 1 DISABLED Disable the underrun interrupt. 0 ENABLED Enable the underrun interrupt. 1 SREIEN Shift Register Empty Interrupt Enable. 7 1 DISABLED Disable the shift register empty interrupt. 0 ENABLED Enable the shift register empty interrupt. 1 SPIEN SPI Enable. 8 1 DISABLED Disable the SPI. 0 ENABLED Enable the SPI. 1 MSTEN Master Mode Enable. 9 1 DISABLED Operate in slave mode. 0 ENABLED Operate in master mode. 1 CLKPOL SPI Clock Polarity. 10 1 LOW The SCK line is low in the idle state. 0 HIGH The SCK line is high in the idle state. 1 CLKPHA SPI Clock Phase. 11 1 CENTER The first edge of SCK is the sample edge (center of data bit). 0 EDGE The first edge of SCK is the shift edge (edge of data bit). 1 NSSPOL Slave Select Polarity Select. 12 1 LOW NSS is active low. 0 HIGH NSS is active high. 1 DDIRSEL Data Direction Select. 13 1 MSB_FIRST Data will be shifted MSB first. 0 LSB_FIRST Data will be shifted LSB first. 1 NSSMD Slave Select Mode. 14 2 3_WIRE_MASTER_SLAVE 3-wire Slave or 3-wire Master. 0 4_WIRE_SLAVE 4-wire slave (NSS input). This setting can also be used for multi-master configurations. 1 4_WIRE_MASTER_NSS_LOW 4-wire master with NSS low (NSS output). 2 4_WIRE_MASTER_NSS_HIGH 4-wire master with NSS high (NSS output). 3 RFTH Receive FIFO Threshold. 16 2 ONE A DMA / RFRQ request asserts when >= 1 FIFO slot is filled. 0 TWO A DMA / RFRQ request asserts when >= 2 FIFO slots are filled. 1 FOUR A DMA / RFRQ request asserts when >= 4 FIFO slots are filled. 2 FULL A DMA / RFRQ request asserts when all FIFO slots are filled. 3 TFTH Transmit FIFO Threshold. 18 2 ONE A DMA / TFRQ request asserts when >= 1 FIFO slot is empty. 0 TWO A DMA / TFRQ request asserts when >= 2 FIFO slots are empty. 1 FOUR A DMA / TFRQ request asserts when >= 4 FIFO slots are empty. 2 EMPTY A DMA / TFRQ request asserts when all FIFO slots are empty. 3 DSIZE Data Size. 20 4 DMAEN DMA Enable. 24 1 DISABLED Disable DMA requests. 0 ENABLED Enable DMA requests when the transmit buffer is empty or the receive buffer is full. 1 RFIFOFL Receive FIFO Flush. 29 1 SET Flush the receive FIFO. 1 TFIFOFL Transmit FIFO Flush. 30 1 SET Flush the transmit FIFO. 1 RESET Module Soft Reset. 31 1 INACTIVE SPI module is not in soft reset. 0 ACTIVE SPI module is in soft reset and some of the module bits cannot be accessed until this bit is cleared to 0 by hardware. 1 CLKRATE Module Clock Rate Control 0x30 0x00000000 0xFFFFFFFF CLKDIV Clock Divider. 0 16 FSTATUS FIFO Status 0x40 0x00000000 0xFFFFFFFF RFRPTR Receive FIFO Read Pointer. 0 4 read-only RFWPTR Receive FIFO Write Pointer. 4 4 read-only TFRPTR Transmit FIFO Read Pointer. 8 4 read-only TFWPTR Transmit FIFO Write Pointer. 12 4 read-only SSG_0 A None SSG_0 0x4001e000 0x0 0xffc registers CONFIG Module Configuration 0x0 0x00000000 0xFFFFFFFF COUNT Pulse Generator Counter. 0 12 SSEL Speed Select. 12 1 NORMAL The SSG module runs at normal speed, where each pulse and phase cycle consists of 16 ADC clocks. 0 DOUBLE The SSG module runs at double speed, where each pulse and phase cycle consists of 8 ADC clocks. 1 PHGFREN Phase Generator Free-Run Enable. 13 1 DISABLED The Phase Generator runs only when pulse generation occurs. 0 ENABLED The Phase Generator runs when an ADC is enabled, regardless of the Pulse Generator settings. 1 PUGFREN Pulse Generator Free-Run Enable. 14 1 DISABLED The COUNT field determines the number of pulses generated by the Pulse Generator. 0 ENABLED The Pulse Generator always generates pulses regardless of COUNT unless all outputs are disabled (EX0EN, EX1EN, EX2EN, and EX3EN are all 0). 1 CONTROL Module Control 0x10 0x00000000 0xFFFFFFFF EX0INVEN Output 0 Invert Enable. 0 1 NORMAL Do not invert the Pulse Generator output on EX0. 0 INVERT Invert the Pulse Generator output on EX0. 1 EX1INVEN Output 1 Invert Enable. 1 1 NORMAL Do not invert the Pulse Generator output on EX1. 0 INVERT Invert the Pulse Generator output on EX1. 1 EX2INVEN Output 2 Invert Enable. 2 1 NORMAL Do not invert the Pulse Generator output on EX2. 0 INVERT Invert the Pulse Generator output on EX2. 1 EX3INVEN Output 3 Invert Enable. 3 1 NORMAL Do not invert the Pulse Generator output on EX3. 0 INVERT Invert the Pulse Generator output on EX3. 1 EX0EN Output 0 Enable. 4 1 DISABLED Disable the EX0 Pulse Generator output. 0 ENABLED Enable the EX0 Pulse Generator output. 1 EX1EN Output 1 Enable. 5 1 DISABLED Disable the EX1 Pulse Generator output. 0 ENABLED Enable the EX1 Pulse Generator output. 1 EX2EN Output 2 Enable. 6 1 DISABLED Disable the EX2 Pulse Generator output. 0 ENABLED Enable the EX2 Pulse Generator output. 1 EX3EN Output 3 Enable. 7 1 DISABLED Disable the EX3 Pulse Generator output. 0 ENABLED Enable the EX3 Pulse Generator output. 1 STATUS SSG Module Status. 8 1 read-only IDLE The SSG module is idle and the Pulse Generator is not operating. 0 ACTIVE The SSG module is active and the Pulse Generator is counting. 1 TIMER_0 A None Timer 0x40014000 0x0 0xffc registers TIMER0L_IRQn 20 TIMER0H_IRQn 21 CONFIG High and Low Timer Configuration 0x0 0x00000000 0xFFFFFFFF LCLK Low Clock Source. 0 2 APB Select the APB clock as the timer source. 0 EXTOSCN Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock. 1 TIMER_CLKDIV Select the dedicated 8-bit prescaler as the timer source. 2 CT_FALLING_EDGE Select falling edges of the CT signal as the timer clock source. 3 LMSTREN Low Run Master Enable. 4 1 DISABLED MSTRUN does not need to be set for the low timer to run. 0 ENABLED MSTRUN must be set for the low timer to run. 1 SPLITEN Split Mode Enable. 5 1 DISABLED The timer operates as a single 32-bit timer controlled by the high timer fields. 0 ENABLED The timer operates as two independent 16-bit timers. 1 LEXIEN Low Timer Extra Interrupt Enable. 6 1 DISABLED The state of the LEXI flag does not affect the low timer interrupt. 0 ENABLED A low timer interrupt request is generated if LEXI is set to 1. 1 LOVFIEN Low Timer Overflow Interrupt Enable. 7 1 DISABLED The state of LOVFI does not affect the low timer interrupt. 0 ENABLED A low timer interrupt request is generated if LOVFI = 1. 1 LMD Low Timer Mode. 8 3 AUTO_RELOAD The low timer is in Auto-Reload Mode. 0 UP_DOWN The low timer is in Up/Down Count Mode. 1 FALL_CAPTURE The low timer is in Falling Edge Capture Mode. 2 RISE_CAPTURE The low timer is in Rising Edge Capture Mode. 3 LOW_CAPTURE The low timer is in Low Time Capture Mode. 4 HIGH_CAPTURE The low timer is in High Time Capture Mode. 5 DC_CAPTURE The low timer is in Duty Cycle Capture Mode. 6 ONESHOT The low timer is in Oneshot Mode. 7 LSTATE Low Multi Purpose State Indicator. 12 1 NOT_SET 0 SET 1 LRUN Run Control Low. 13 1 STOP Stop the low timer if split mode is enabled (SPLITEN = 1). 0 START The low timer runs if split mode is enabled (SPLITEN = 1) and (LMSTREN = 0 or MSTRUN = 1). 1 LEXI Low Timer Extra Interrupt Flag. 14 1 NOT_SET Read: A low timer extra interrupt is not pending. Write: Clear the interrupt. 0 SET Read: Indicates the low 16-bit timer has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by hardware in all modes except Auto-Reload and Toggle. This flag is not set by hardware when split mode is disabled (SPLITEN = 0). Write: Force a low timer extra interrupt. 1 LOVFI Low Timer Overflow Interrupt. 15 1 NOT_SET Read: A low timer overflow interrupt is not pending. Write: Clear the interrupt. 0 SET Read: The low 16-bit timer has wrapped or reloaded after reaching all 1's. This bit is set by the module regardless of the state of SPLITEN and can be set in all modes. Write: Force a low timer overflow interrupt. 1 HCLK High Clock Source. 16 2 APB Select the APB clock as the timer source. 0 EXTOSCN Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock. 1 TIMER_CLKDIV Select the dedicated 8-bit prescaler as the timer source. 2 CT_FALLING_EDGE Select falling edges of the CT signal as the timer clock source. 3 MSTRUN Master Run Control. 19 1 STOP Disable the master run control for all timers. 0 START Enable the master run control for all timers. 1 HMSTREN High Master Enable. 20 1 DISABLED MSTRUN does not need to be set for the high timer to run. 0 ENABLED MSTRUN must be set for the high timer to run. 1 DBGMD Timer Debug Mode. 21 1 RUN The Timer will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the Timer to halt. 1 HEXIEN High Timer Extra Interrupt Enable. 22 1 DISABLED The state of the HEXI flag does not affect the high timer interrupt. 0 ENABLED A high timer interrupt request is generated if HEXI is set to 1. 1 HOVFIEN High Timer Overflow Interrupt Enable. 23 1 DISABLED The state of HOVFI does not affect the high timer interrupt. 0 ENABLED A high timer interrupt request is generated if HOVFI is set to 1. 1 HMD High Timer Mode. 24 4 AUTO_RELOAD The high 16-bit timer or entire 32-bit timer is in Auto-Reload Mode. 0 UP_DOWN The high 16-bit timer or entire 32-bit timer is in Up/Down Count Mode. 1 FALL_CAPTURE The high 16-bit timer or entire 32-bit timer is in Falling Edge Capture Mode. 2 RISE_CAPTURE The high 16-bit timer or entire 32-bit timer is in Rising Edge Capture Mode. 3 LOW_CAPTURE The high 16-bit timer or entire 32-bit timer is in Low Time Capture Mode. 4 HIGH_CAPTURE The high 16-bit timer or entire 32-bit timer is in High Time Capture Mode. 5 DC_CAPTURE The high 16-bit timer or entire 32-bit timer is in Duty Cycle Capture Mode. 6 ONESHOT The high 16-bit timer or entire 32-bit timer is in Oneshot Mode. 7 TOGGLE The high 16-bit timer or entire 32-bit timer is in Toggle Output Mode. 8 PWM The high 16-bit timer or entire 32-bit timer is in PWM Mode. 9 HSTATE High Multi Purpose State Indicator. 28 1 NOT_SET 0 SET 1 HRUN High Run Control. 29 1 STOP Stop the high timer or entire 32-bit timer. 0 START The high timer runs if HMSTREN = 0 or MSTRUN = 1. The full 32-bit timer runs if split mode is disabled and (HMSTREN = 0 or MSTRUN = 1). 1 HEXI High Timer Extra Interrupt Flag. 30 1 NOT_SET Read: A high timer extra interrupt is not pending. Write: Clear the interrupt. 0 SET Read: Indicates the high 16-bit timer (or 32-bit timer if SPLITEN = 0) has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by the timer module in all modes except Auto-Reload and Toggle. Write: Force a high timer extra interrupt. 1 HOVFI High Timer Overflow Interrupt Flag. 31 1 NOT_SET Read: A high timer overflow interrupt is not pending. Write: Clear the interrupt. 0 SET Read: If split mode is enabled (SPLITEN = 1), this value indicates the high 16-bit timer has wrapped or reloaded after reaching all 1's. If split mode is disabled (SPLITEN = 0), this value indicates the 32-bit timer has wrapped or reloaded after reaching all 1's. The timer module can set this bit in all modes. Write: Force a high timer overflow interrupt. 1 CLKDIV Module Clock Divider Control 0x10 0x00000000 0xFFFFFFFF CLKDIVRL Clock Divider Reload Value. 0 8 CLKDIVCT Clock Divider Counter. 16 8 COUNT Timer Value 0x20 0x00000000 0xFFFFFFFF LCOUNT Low Timer Count. 0 16 HCOUNT High Timer Count. 16 16 CAPTURE Timer Capture/Reload Value 0x30 0x00000000 0xFFFFFFFF LCCR Low Timer Capture/Reload. 0 16 HCCR High Timer Capture/Reload. 16 16 TIMER_1 A None Timer 0x40015000 0x0 0xffc registers TIMER1L_IRQn 22 TIMER1H_IRQn 23 CONFIG High and Low Timer Configuration 0x0 0x00000000 0xFFFFFFFF LCLK Low Clock Source. 0 2 APB Select the APB clock as the timer source. 0 EXTOSCN Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock. 1 TIMER_CLKDIV Select the dedicated 8-bit prescaler as the timer source. 2 CT_FALLING_EDGE Select falling edges of the CT signal as the timer clock source. 3 LMSTREN Low Run Master Enable. 4 1 DISABLED MSTRUN does not need to be set for the low timer to run. 0 ENABLED MSTRUN must be set for the low timer to run. 1 SPLITEN Split Mode Enable. 5 1 DISABLED The timer operates as a single 32-bit timer controlled by the high timer fields. 0 ENABLED The timer operates as two independent 16-bit timers. 1 LEXIEN Low Timer Extra Interrupt Enable. 6 1 DISABLED The state of the LEXI flag does not affect the low timer interrupt. 0 ENABLED A low timer interrupt request is generated if LEXI is set to 1. 1 LOVFIEN Low Timer Overflow Interrupt Enable. 7 1 DISABLED The state of LOVFI does not affect the low timer interrupt. 0 ENABLED A low timer interrupt request is generated if LOVFI = 1. 1 LMD Low Timer Mode. 8 3 AUTO_RELOAD The low timer is in Auto-Reload Mode. 0 UP_DOWN The low timer is in Up/Down Count Mode. 1 FALL_CAPTURE The low timer is in Falling Edge Capture Mode. 2 RISE_CAPTURE The low timer is in Rising Edge Capture Mode. 3 LOW_CAPTURE The low timer is in Low Time Capture Mode. 4 HIGH_CAPTURE The low timer is in High Time Capture Mode. 5 DC_CAPTURE The low timer is in Duty Cycle Capture Mode. 6 ONESHOT The low timer is in Oneshot Mode. 7 LSTATE Low Multi Purpose State Indicator. 12 1 NOT_SET 0 SET 1 LRUN Run Control Low. 13 1 STOP Stop the low timer if split mode is enabled (SPLITEN = 1). 0 START The low timer runs if split mode is enabled (SPLITEN = 1) and (LMSTREN = 0 or MSTRUN = 1). 1 LEXI Low Timer Extra Interrupt Flag. 14 1 NOT_SET Read: A low timer extra interrupt is not pending. Write: Clear the interrupt. 0 SET Read: Indicates the low 16-bit timer has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by hardware in all modes except Auto-Reload and Toggle. This flag is not set by hardware when split mode is disabled (SPLITEN = 0). Write: Force a low timer extra interrupt. 1 LOVFI Low Timer Overflow Interrupt. 15 1 NOT_SET Read: A low timer overflow interrupt is not pending. Write: Clear the interrupt. 0 SET Read: The low 16-bit timer has wrapped or reloaded after reaching all 1's. This bit is set by the module regardless of the state of SPLITEN and can be set in all modes. Write: Force a low timer overflow interrupt. 1 HCLK High Clock Source. 16 2 APB Select the APB clock as the timer source. 0 EXTOSCN Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock. 1 TIMER_CLKDIV Select the dedicated 8-bit prescaler as the timer source. 2 CT_FALLING_EDGE Select falling edges of the CT signal as the timer clock source. 3 MSTRUN Master Run Control. 19 1 STOP Disable the master run control for all timers. 0 START Enable the master run control for all timers. 1 HMSTREN High Master Enable. 20 1 DISABLED MSTRUN does not need to be set for the high timer to run. 0 ENABLED MSTRUN must be set for the high timer to run. 1 DBGMD Timer Debug Mode. 21 1 RUN The Timer will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the Timer to halt. 1 HEXIEN High Timer Extra Interrupt Enable. 22 1 DISABLED The state of the HEXI flag does not affect the high timer interrupt. 0 ENABLED A high timer interrupt request is generated if HEXI is set to 1. 1 HOVFIEN High Timer Overflow Interrupt Enable. 23 1 DISABLED The state of HOVFI does not affect the high timer interrupt. 0 ENABLED A high timer interrupt request is generated if HOVFI is set to 1. 1 HMD High Timer Mode. 24 4 AUTO_RELOAD The high 16-bit timer or entire 32-bit timer is in Auto-Reload Mode. 0 UP_DOWN The high 16-bit timer or entire 32-bit timer is in Up/Down Count Mode. 1 FALL_CAPTURE The high 16-bit timer or entire 32-bit timer is in Falling Edge Capture Mode. 2 RISE_CAPTURE The high 16-bit timer or entire 32-bit timer is in Rising Edge Capture Mode. 3 LOW_CAPTURE The high 16-bit timer or entire 32-bit timer is in Low Time Capture Mode. 4 HIGH_CAPTURE The high 16-bit timer or entire 32-bit timer is in High Time Capture Mode. 5 DC_CAPTURE The high 16-bit timer or entire 32-bit timer is in Duty Cycle Capture Mode. 6 ONESHOT The high 16-bit timer or entire 32-bit timer is in Oneshot Mode. 7 TOGGLE The high 16-bit timer or entire 32-bit timer is in Toggle Output Mode. 8 PWM The high 16-bit timer or entire 32-bit timer is in PWM Mode. 9 HSTATE High Multi Purpose State Indicator. 28 1 NOT_SET 0 SET 1 HRUN High Run Control. 29 1 STOP Stop the high timer or entire 32-bit timer. 0 START The high timer runs if HMSTREN = 0 or MSTRUN = 1. The full 32-bit timer runs if split mode is disabled and (HMSTREN = 0 or MSTRUN = 1). 1 HEXI High Timer Extra Interrupt Flag. 30 1 NOT_SET Read: A high timer extra interrupt is not pending. Write: Clear the interrupt. 0 SET Read: Indicates the high 16-bit timer (or 32-bit timer if SPLITEN = 0) has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by the timer module in all modes except Auto-Reload and Toggle. Write: Force a high timer extra interrupt. 1 HOVFI High Timer Overflow Interrupt Flag. 31 1 NOT_SET Read: A high timer overflow interrupt is not pending. Write: Clear the interrupt. 0 SET Read: If split mode is enabled (SPLITEN = 1), this value indicates the high 16-bit timer has wrapped or reloaded after reaching all 1's. If split mode is disabled (SPLITEN = 0), this value indicates the 32-bit timer has wrapped or reloaded after reaching all 1's. The timer module can set this bit in all modes. Write: Force a high timer overflow interrupt. 1 CLKDIV Module Clock Divider Control 0x10 0x00000000 0xFFFFFFFF CLKDIVRL Clock Divider Reload Value. 0 8 CLKDIVCT Clock Divider Counter. 16 8 COUNT Timer Value 0x20 0x00000000 0xFFFFFFFF LCOUNT Low Timer Count. 0 16 HCOUNT High Timer Count. 16 16 CAPTURE Timer Capture/Reload Value 0x30 0x00000000 0xFFFFFFFF LCCR Low Timer Capture/Reload. 0 16 HCCR High Timer Capture/Reload. 16 16 UART_0 A None UART 0x40002000 0x0 0xffc registers UART0_IRQn 46 CONFIG Module Configuration 0x0 0x030D030D 0xFFFFFFFF RSTRTEN Receiver Start Enable. 0 1 DISABLED Do not expect a start bit during receptions. 0 ENABLED Expect a start bit during receptions. 1 RPAREN Receiver Parity Enable. 1 1 DISABLED Do not expect a parity bit during receptions. 0 ENABLED Expect a parity bit during receptions. 1 RSTPEN Receiver Stop Enable. 2 1 DISABLED Do not expect stop bits during receptions. 0 ENABLED Expect stop bits during receptions. 1 RSTPMD Receiver Stop Mode. 3 2 0P5_STOP 0.5 stop bit. 0 1_STOP 1 stop bit. 1 1P5_STOP 1.5 stop bits. 2 2_STOP 2 stop bits. 3 RPARMD Receiver Parity Mode. 5 2 ODD Odd Parity. 0 EVEN Even Parity. 1 MARK Set (Parity = 1). 2 SPACE Clear (Parity = 0). 3 RDATLN Receiver Data Length. 8 3 5_BITS 5 bits. 0 6_BITS 6 bits. 1 7_BITS 7 bits. 2 8_BITS 8 bits. 3 9_BITS_STORED 9 bits. The 9th bit is stored in the FIFO (normal mode). 4 9_BITS_MATCH 9 bits. The 9th bit is not stored in the FIFO (fixed mode). This mode is used when the 9th bit is only used for match operations (see MATMD). 5 RSCEN Receiver Smartcard Parity Response Enable. 12 1 DISABLED The receiver does not send a Smartcard parity error response. 0 ENABLED The receiver sends a Smartcard Parity response. 1 RIRDAEN Receiver IrDA Enable. 13 1 DISABLED The receiver does not operate in IrDA mode. 0 ENABLED The receiver operates in IrDA mode. 1 RINVEN Receiver Invert Enable. 14 1 DISABLED Do not invert the RX pin signals (the RX idle state is high). 0 ENABLED Invert the RX pin signals (the RX idle state is low). 1 TSTRTEN Transmitter Start Enable. 16 1 DISABLED Do not generate a start bit during transmissions. 0 ENABLED Generate a start bit during transmissions. 1 TPAREN Transmitter Parity Enable. 17 1 DISABLED Do not send a parity bit during transmissions. 0 ENABLED Send a parity bit during transmissions. 1 TSTPEN Transmitter Stop Enable. 18 1 DISABLED Do not send stop bits during transmissions. 0 ENABLED Send stop bits during transmissions. 1 TSTPMD Transmitter Stop Mode. 19 2 0P5_STOP 0.5 stop bit. 0 1_STOP 1 stop bit. 1 1P5_STOP 1.5 stop bits. 2 2_STOP 2 stop bits. 3 TPARMD Transmitter Parity Mode. 21 2 ODD Odd Parity. 0 EVEN Even Parity. 1 MARK Set (Parity = 1). 2 SPACE Clear (Parity = 0). 3 TDATLN Transmitter Data Length. 24 3 5_BITS 5 bits. 0 6_BITS 6 bits. 1 7_BITS 7 bits. 2 8_BITS 8 bits. 3 9_BITS_FIFO 9 bits. The 9th bit is taken from the FIFO data (normal mode). 4 9_BITS_TBIT 9 bits. The 9th bit is set by the value of TBIT (fixed mode). 5 TSCEN Transmitter Smartcard Parity Response Enable. 28 1 DISABLED The transmitter does not check for a Smartcard parity error response. 0 ENABLED The transmitter checks for a Smartcard parity error response. 1 TIRDAEN Transmitter IrDA Enable. 29 1 DISABLED Disable IrDA transmit mode. 0 ENABLED Enable IrDA transmit mode. 1 TINVEN Transmitter Invert Enable. 30 1 DISABLED Do not invert the TX pin signals (the TX idle state is high). 0 ENABLED Invert the TX pin signals (the TX idle state is low). 1 MODE Module Mode Select 0x10 0x00600000 0xFFFFFFFF DBGMD UART Debug Mode. 16 1 RUN The UART module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the UART module to halt. Any active transmissions and receptions will complete first. 1 LBMD Loop Back Mode. 18 2 DISABLED Loop back is disabled and the TX and RX signals are connected to the corresponding external pins. 0 RX_ONLY Receive loop back. The receiver input path is disconnected from the RX pin and internally connected to the transmitter. Data transmitted will be sent out on TX and also received by the device. 1 TX_ONLY Transmit loop back. The transmitter output path is disconnected from the TX pin and the RX input pin is internally looped back out to the TX pin. Data received at RX will be received by the device and also sent directly back out on TX. 2 BOTH Full loop back. Internally, the transmitter output is routed back to the receiver input. Neither the transmitter nor receiver are connected to external device pins. The device pin RX is looped back to TX in a similar fashion. Data transmitted on TX will be sent directly back in on RX. 3 DUPLEXMD Duplex Mode. 27 1 FULL_DUPLEX Full-duplex mode. The transmitter and receiver can operate simultaneously. 0 HALF_DUPLEX Half-duplex mode. The transmitter automatically inhibits when the receiver is active and the receiver automatically inhibits when the transmitter is active. 1 ITSEN Idle TX Tristate Enable. 30 1 DISABLED The TX and UCLK (if in synchronous master mode) pins are always an output in this mode, even when idle. 0 ENABLED The TX pin is tristated when idle. If ISTCLK is cleared to 0 and the transmitter is configured in synchronous master mode, the UCLK pin will also be tristated when idle. 1 FLOWCN Flow Control 0x20 0x00020001 0xFFFFFFFF RTS RTS State. 0 1 LOW RTS pin (before optional inversion) is driven low. 0 HIGH RTS pin (before optional inversion) is driven high. 1 RX RX Pin Status. 1 1 read-only LOW RX pin (after optional inversion) is low. 0 HIGH RX pin (after optional inversion) is high. 1 RTSINVEN RTS Invert Enable. 5 1 DISABLED The UART does not invert the RTS signal before driving the pin. 0 ENABLED The UART inverts the RTS signal driving the pin. 1 RTSTH RTS Threshold Control. 6 1 FULL RTS is de-asserted when the receive FIFO and shift register are full and no more incoming data can be stored. 0 ONE_BYTE_FREE RTS is de-asserted when the receive FIFO and shift register are nearly full and only one more data can be received. 1 RTSEN RTS Enable. 7 1 DISABLED The RTS state is not changed by hardware. The RTS bit can be written only when hardware RTS is disabled (RTSEN = 0). 0 ENABLED Hardware sets RTS when the receive FIFO is at or above the threshold set by RTSTH and clears RTS otherwise. 1 CTS CTS State. 16 1 read-only LOW Indicates the CTS pin state (after optional inversion) is low. 0 HIGH Indicates the CTS pin state (after optional inversion) is high. 1 TX TX State. 17 1 LOW The TX pin (before optional inversion) is low. 0 HIGH The TX pin (before optional inversion) is high. 1 CTSINVEN CTS Invert Enable. 21 1 DISABLED The UART does not invert CTS. 0 ENABLED The UART inverts CTS. 1 CTSEN CTS Enable. 23 1 DISABLED The CTS pin state does not affect transmissions. 0 ENABLED Transmissions will begin only if the CTS pin (after optional inversion) is low. 1 TIRDAPW Transmit IrDA Pulse Width. 28 2 1_16TH The IrDA pulse width is 1/16th of a bit period. 0 1_8TH The IrDA pulse width is 1/8th of a bit period. 1 3_16TH The IrDA pulse width is 3/16th of a bit period. 2 1_4TH The IrDA pulse width is 1/4th of a bit period. 3 CONTROL Module Control 0x30 0x00000000 0xFFFFFFFF RFRMERI Receive Frame Error Interrupt Flag. 0 1 NOT_SET Read: A frame error has not occurred since RFRMERI was last cleared. Write: Clear the interrupt. 0 SET Read: A frame error occurred. Write: Force a frame error interrupt. 1 RPARERI Receive Parity Error Interrupt Flag. 1 1 NOT_SET Read: An invalid parity bit has not been received since RPARERI was last cleared. Write: Clear the interrupt. 0 SET Read: An invalid parity bit has been received since RPARERI was last cleared. Write: Force a parity error interrupt. 1 ROREI Receive Overrun Error Interrupt Flag. 2 1 NOT_SET Read: A receiver overrun has not occurred since ROREI was last cleared. Write: Clear the interrupt. 0 SET Read: A receiver overrun occurred. Write: Force a receiver overrun interrupt. 1 RDREQI Receive Data Request Interrupt Flag. 3 1 read-only NOT_SET Fewer than RFTH FIFO slots are filled with data. 0 SET At least RFTH FIFO slots are filled with data. 1 RERIEN Receive Error Interrupt Enable. 5 1 DISABLED Disable the receive error interrupt. 0 ENABLED Enable the receive error interrupt. A receive error interrupt is asserted when ROREI, RFRMERI, or RPARERI is set to 1. 1 RDREQIEN Receive Data Request Interrupt Enable. 6 1 DISABLED Disable the read data request interrupt. 0 ENABLED Enable the read data request interrupt. A receive interrupt is generated when RDREQI is set to 1. 1 MATMD Match Mode. 8 2 OFF Disable the match function. 0 MCE (MCE) Data whose last data bit equals RBIT is accepted and stored. 1 FRAME (Frame) A framing error is asserted if the last received bit matches RBIT. 2 STORE (Store) Store the last incoming data bit in RBIT. This mode can be used inconjunction with the RDATLN setting. 3 RABDEN Receiver Auto-Baud Enable. 10 1 DISABLED Disable receiver auto-baud. 0 ENABLED Enable receiver auto-baud. 1 RBUSYF Receiver Busy Flag. 11 1 read-only NOT_SET The UART receiver is idle. 0 SET The UART receiver is receiving data. 1 RBIT Last Receive Bit. 12 1 NOT_SET 0 SET 1 ROSEN Receiver One-Shot Enable. 13 1 DISABLED Disable one-shot receive mode. 0 ENABLED Enable one-shot receive mode. 1 RINH Receiver Inhibit. 14 1 INACTIVE The receiver operates normally. 0 ACTIVE RTS is immediately asserted when RINH is set. The receiver will complete any ongoing reception, but ignore all traffic after that. 1 REN Receiver Enable. 15 1 DISABLED Disable the receiver. The receiver can receive one data transaction only if ROSEN is set. 0 ENABLED Enable the receiver. 1 TSCERI Smartcard Parity Error Interrupt Flag. 16 1 NOT_SET Read: A Smartcard parity error has not occurred since TSCERI was last cleared. Write: Clear the interrupt. 0 SET Read: A Smartcard parity error occurred. Write: Force a Smartcard parity error interrupt. 1 TDREQI Transmit Data Request Interrupt Flag. 18 1 read-only NOT_SET The transmitter is not requesting more FIFO data. 0 SET The transmitter is requesting more FIFO data. 1 TCPTI Transmit Complete Interrupt Flag. 19 1 NOT_SET Read: A transmit has not completed since TCPTI was last cleared. Write: Clear the interrupt. 0 SET Read: A byte was transmitted (TCCPTH = 0) or the last available byte was transmitted (TCPTTH = 1). Write: Force a transmit complete interrupt. 1 TCPTTH Transmit Complete Threshold. 20 1 SET_ON_TX A transmit is completed (TCPTI = 1) at the end of each transmission. 0 SET_ON_EMPTY A transmit is completed (TCPTI = 1) only at the end of a transmission when no more data is available to transmit. 1 TERIEN Transmit Error Interrupt Enable. 21 1 DISABLED Disable the transmit error interrupt. 0 ENABLED Enable the transmit error interrupt. A transmit interrupt is generated when TUREI or TSCERI is set to 1. 1 TDREQIEN Transmit Data Request Interrupt Enable. 22 1 DISABLED Disable the transmit data request interrupt. 0 ENABLED Enable the transmit data request interrupt. A transmit interrupt is asserted when TDREQI is set to 1. 1 TCPTIEN Transmit Complete Interrupt Enable. 23 1 DISABLED Disable the transmit complete interrupt. 0 ENABLED Enable the transmit complete interrupt. A transmit interrupt is generated when TCPTI is set to 1. 1 TBUSYF Transmitter Busy Flag. 27 1 read-only NOT_SET The UART transmitter is idle. 0 SET The UART transmitter is active and transmitting. 1 TBIT Last Transmit Bit. 28 1 NOT_SET 0 SET 1 TINH Transmit Inhibit. 30 1 INACTIVE The transmitter operates normally. 0 ACTIVE Transmissions are inhibited. The transmitter will stall after any current transmission is complete. 1 TEN Transmitter Enable. 31 1 DISABLED Disable the transmitter. When cleared, the transmitter immediately aborts any active transmission. Clearing this bit does not automatically flush the transmit FIFO. 0 ENABLED Enable the transmitter. The transmitter will initiate a transmission when data becomes available in the transmit FIFO. 1 IPDELAY Inter-Packet Delay 0x40 0x00000000 0xFFFFFFFF IPDELAY Inter-Packet Delay. 16 8 BAUDRATE Transmit and Receive Baud Rate 0x50 0x00000000 0xFFFFFFFF RBAUD Receiver Baud Rate Control. 0 16 TBAUD Transmitter Baud Rate Control. 16 16 FIFOCN FIFO Control 0x60 0x00000000 0xFFFFFFFF RCNT Receive FIFO Count. 0 3 read-only RFTH Receive FIFO Threshold. 4 2 ONE A read data request interrupt (RDREQI) is asserted when >= 1 FIFO slot is full. 0 TWO A read data request interrupt (RDREQI) is asserted when >= 2 FIFO slots are full. 1 FOUR A read data request interrupt (RDREQI) is asserted when >= 4 FIFO slots are full. 2 RFIFOFL Receive FIFO Flush. 8 1 SET Flush the contents of the receive FIFO and any data in the receive shift register. 1 RFERI Receive FIFO Error Interrupt Flag. 9 1 NOT_SET A receive FIFO error has not occurred since RFERI was last cleared. 0 SET A receive FIFO error occurred. 1 RSRFULLF Receive Shift Register Full . 10 1 read-only NOT_SET The receive data shift register is not full. 0 SET The receive data shift register is full. 1 TCNT Transmit FIFO Count. 16 3 read-only TFTH Transmit FIFO Threshold. 20 2 ONE A transmit data request interrupt (TDREQI) is asserted when >= 1 FIFO slot is empty. 0 TWO A transmit data request interrupt (TDREQI) is asserted when >= 2 FIFO slots are empty. 1 FOUR A transmit data request interrupt (TDREQI) is asserted when >= 4 FIFO slots are empty. 2 TFIFOFL Transmit FIFO Flush. 24 1 SET Flush the contents of the transmit FIFO. If data is pending in the transmit shift register but a transmit has not begun, the shift register is also flushed. 1 TFERI Transmit FIFO Error Interrupt Flag. 25 1 NOT_SET A transmit FIFO error has not occurred since TFERI was last cleared. 0 SET A transmit FIFO error occurred. 1 TSRFULLF Transmit Shift Register Full Flag. 26 1 read-only NOT_SET The transmit shift register is not full. 0 SET The transmit shift register is full. 1 DATA FIFO Input/Output Data 0x70 0x00000000 0xFFFFFFFF modifyExternal DATA FIFO Data. 0 32 UART_1 A None UART 0x40003000 0x0 0xffc registers UART1_IRQn 47 CONFIG Module Configuration 0x0 0x030D030D 0xFFFFFFFF RSTRTEN Receiver Start Enable. 0 1 DISABLED Do not expect a start bit during receptions. 0 ENABLED Expect a start bit during receptions. 1 RPAREN Receiver Parity Enable. 1 1 DISABLED Do not expect a parity bit during receptions. 0 ENABLED Expect a parity bit during receptions. 1 RSTPEN Receiver Stop Enable. 2 1 DISABLED Do not expect stop bits during receptions. 0 ENABLED Expect stop bits during receptions. 1 RSTPMD Receiver Stop Mode. 3 2 0P5_STOP 0.5 stop bit. 0 1_STOP 1 stop bit. 1 1P5_STOP 1.5 stop bits. 2 2_STOP 2 stop bits. 3 RPARMD Receiver Parity Mode. 5 2 ODD Odd Parity. 0 EVEN Even Parity. 1 MARK Set (Parity = 1). 2 SPACE Clear (Parity = 0). 3 RDATLN Receiver Data Length. 8 3 5_BITS 5 bits. 0 6_BITS 6 bits. 1 7_BITS 7 bits. 2 8_BITS 8 bits. 3 9_BITS_STORED 9 bits. The 9th bit is stored in the FIFO (normal mode). 4 9_BITS_MATCH 9 bits. The 9th bit is not stored in the FIFO (fixed mode). This mode is used when the 9th bit is only used for match operations (see MATMD). 5 RSCEN Receiver Smartcard Parity Response Enable. 12 1 DISABLED The receiver does not send a Smartcard parity error response. 0 ENABLED The receiver sends a Smartcard Parity response. 1 RIRDAEN Receiver IrDA Enable. 13 1 DISABLED The receiver does not operate in IrDA mode. 0 ENABLED The receiver operates in IrDA mode. 1 RINVEN Receiver Invert Enable. 14 1 DISABLED Do not invert the RX pin signals (the RX idle state is high). 0 ENABLED Invert the RX pin signals (the RX idle state is low). 1 TSTRTEN Transmitter Start Enable. 16 1 DISABLED Do not generate a start bit during transmissions. 0 ENABLED Generate a start bit during transmissions. 1 TPAREN Transmitter Parity Enable. 17 1 DISABLED Do not send a parity bit during transmissions. 0 ENABLED Send a parity bit during transmissions. 1 TSTPEN Transmitter Stop Enable. 18 1 DISABLED Do not send stop bits during transmissions. 0 ENABLED Send stop bits during transmissions. 1 TSTPMD Transmitter Stop Mode. 19 2 0P5_STOP 0.5 stop bit. 0 1_STOP 1 stop bit. 1 1P5_STOP 1.5 stop bits. 2 2_STOP 2 stop bits. 3 TPARMD Transmitter Parity Mode. 21 2 ODD Odd Parity. 0 EVEN Even Parity. 1 MARK Set (Parity = 1). 2 SPACE Clear (Parity = 0). 3 TDATLN Transmitter Data Length. 24 3 5_BITS 5 bits. 0 6_BITS 6 bits. 1 7_BITS 7 bits. 2 8_BITS 8 bits. 3 9_BITS_FIFO 9 bits. The 9th bit is taken from the FIFO data (normal mode). 4 9_BITS_TBIT 9 bits. The 9th bit is set by the value of TBIT (fixed mode). 5 TSCEN Transmitter Smartcard Parity Response Enable. 28 1 DISABLED The transmitter does not check for a Smartcard parity error response. 0 ENABLED The transmitter checks for a Smartcard parity error response. 1 TIRDAEN Transmitter IrDA Enable. 29 1 DISABLED Disable IrDA transmit mode. 0 ENABLED Enable IrDA transmit mode. 1 TINVEN Transmitter Invert Enable. 30 1 DISABLED Do not invert the TX pin signals (the TX idle state is high). 0 ENABLED Invert the TX pin signals (the TX idle state is low). 1 MODE Module Mode Select 0x10 0x00600000 0xFFFFFFFF DBGMD UART Debug Mode. 16 1 RUN The UART module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the UART module to halt. Any active transmissions and receptions will complete first. 1 LBMD Loop Back Mode. 18 2 DISABLED Loop back is disabled and the TX and RX signals are connected to the corresponding external pins. 0 RX_ONLY Receive loop back. The receiver input path is disconnected from the RX pin and internally connected to the transmitter. Data transmitted will be sent out on TX and also received by the device. 1 TX_ONLY Transmit loop back. The transmitter output path is disconnected from the TX pin and the RX input pin is internally looped back out to the TX pin. Data received at RX will be received by the device and also sent directly back out on TX. 2 BOTH Full loop back. Internally, the transmitter output is routed back to the receiver input. Neither the transmitter nor receiver are connected to external device pins. The device pin RX is looped back to TX in a similar fashion. Data transmitted on TX will be sent directly back in on RX. 3 DUPLEXMD Duplex Mode. 27 1 FULL_DUPLEX Full-duplex mode. The transmitter and receiver can operate simultaneously. 0 HALF_DUPLEX Half-duplex mode. The transmitter automatically inhibits when the receiver is active and the receiver automatically inhibits when the transmitter is active. 1 ITSEN Idle TX Tristate Enable. 30 1 DISABLED The TX and UCLK (if in synchronous master mode) pins are always an output in this mode, even when idle. 0 ENABLED The TX pin is tristated when idle. If ISTCLK is cleared to 0 and the transmitter is configured in synchronous master mode, the UCLK pin will also be tristated when idle. 1 FLOWCN Flow Control 0x20 0x00020001 0xFFFFFFFF RTS RTS State. 0 1 LOW RTS pin (before optional inversion) is driven low. 0 HIGH RTS pin (before optional inversion) is driven high. 1 RX RX Pin Status. 1 1 read-only LOW RX pin (after optional inversion) is low. 0 HIGH RX pin (after optional inversion) is high. 1 RTSINVEN RTS Invert Enable. 5 1 DISABLED The UART does not invert the RTS signal before driving the pin. 0 ENABLED The UART inverts the RTS signal driving the pin. 1 RTSTH RTS Threshold Control. 6 1 FULL RTS is de-asserted when the receive FIFO and shift register are full and no more incoming data can be stored. 0 ONE_BYTE_FREE RTS is de-asserted when the receive FIFO and shift register are nearly full and only one more data can be received. 1 RTSEN RTS Enable. 7 1 DISABLED The RTS state is not changed by hardware. The RTS bit can be written only when hardware RTS is disabled (RTSEN = 0). 0 ENABLED Hardware sets RTS when the receive FIFO is at or above the threshold set by RTSTH and clears RTS otherwise. 1 CTS CTS State. 16 1 read-only LOW Indicates the CTS pin state (after optional inversion) is low. 0 HIGH Indicates the CTS pin state (after optional inversion) is high. 1 TX TX State. 17 1 LOW The TX pin (before optional inversion) is low. 0 HIGH The TX pin (before optional inversion) is high. 1 CTSINVEN CTS Invert Enable. 21 1 DISABLED The UART does not invert CTS. 0 ENABLED The UART inverts CTS. 1 CTSEN CTS Enable. 23 1 DISABLED The CTS pin state does not affect transmissions. 0 ENABLED Transmissions will begin only if the CTS pin (after optional inversion) is low. 1 TIRDAPW Transmit IrDA Pulse Width. 28 2 1_16TH The IrDA pulse width is 1/16th of a bit period. 0 1_8TH The IrDA pulse width is 1/8th of a bit period. 1 3_16TH The IrDA pulse width is 3/16th of a bit period. 2 1_4TH The IrDA pulse width is 1/4th of a bit period. 3 CONTROL Module Control 0x30 0x00000000 0xFFFFFFFF RFRMERI Receive Frame Error Interrupt Flag. 0 1 NOT_SET Read: A frame error has not occurred since RFRMERI was last cleared. Write: Clear the interrupt. 0 SET Read: A frame error occurred. Write: Force a frame error interrupt. 1 RPARERI Receive Parity Error Interrupt Flag. 1 1 NOT_SET Read: An invalid parity bit has not been received since RPARERI was last cleared. Write: Clear the interrupt. 0 SET Read: An invalid parity bit has been received since RPARERI was last cleared. Write: Force a parity error interrupt. 1 ROREI Receive Overrun Error Interrupt Flag. 2 1 NOT_SET Read: A receiver overrun has not occurred since ROREI was last cleared. Write: Clear the interrupt. 0 SET Read: A receiver overrun occurred. Write: Force a receiver overrun interrupt. 1 RDREQI Receive Data Request Interrupt Flag. 3 1 read-only NOT_SET Fewer than RFTH FIFO slots are filled with data. 0 SET At least RFTH FIFO slots are filled with data. 1 RERIEN Receive Error Interrupt Enable. 5 1 DISABLED Disable the receive error interrupt. 0 ENABLED Enable the receive error interrupt. A receive error interrupt is asserted when ROREI, RFRMERI, or RPARERI is set to 1. 1 RDREQIEN Receive Data Request Interrupt Enable. 6 1 DISABLED Disable the read data request interrupt. 0 ENABLED Enable the read data request interrupt. A receive interrupt is generated when RDREQI is set to 1. 1 MATMD Match Mode. 8 2 OFF Disable the match function. 0 MCE (MCE) Data whose last data bit equals RBIT is accepted and stored. 1 FRAME (Frame) A framing error is asserted if the last received bit matches RBIT. 2 STORE (Store) Store the last incoming data bit in RBIT. This mode can be used inconjunction with the RDATLN setting. 3 RABDEN Receiver Auto-Baud Enable. 10 1 DISABLED Disable receiver auto-baud. 0 ENABLED Enable receiver auto-baud. 1 RBUSYF Receiver Busy Flag. 11 1 read-only NOT_SET The UART receiver is idle. 0 SET The UART receiver is receiving data. 1 RBIT Last Receive Bit. 12 1 NOT_SET 0 SET 1 ROSEN Receiver One-Shot Enable. 13 1 DISABLED Disable one-shot receive mode. 0 ENABLED Enable one-shot receive mode. 1 RINH Receiver Inhibit. 14 1 INACTIVE The receiver operates normally. 0 ACTIVE RTS is immediately asserted when RINH is set. The receiver will complete any ongoing reception, but ignore all traffic after that. 1 REN Receiver Enable. 15 1 DISABLED Disable the receiver. The receiver can receive one data transaction only if ROSEN is set. 0 ENABLED Enable the receiver. 1 TSCERI Smartcard Parity Error Interrupt Flag. 16 1 NOT_SET Read: A Smartcard parity error has not occurred since TSCERI was last cleared. Write: Clear the interrupt. 0 SET Read: A Smartcard parity error occurred. Write: Force a Smartcard parity error interrupt. 1 TDREQI Transmit Data Request Interrupt Flag. 18 1 read-only NOT_SET The transmitter is not requesting more FIFO data. 0 SET The transmitter is requesting more FIFO data. 1 TCPTI Transmit Complete Interrupt Flag. 19 1 NOT_SET Read: A transmit has not completed since TCPTI was last cleared. Write: Clear the interrupt. 0 SET Read: A byte was transmitted (TCCPTH = 0) or the last available byte was transmitted (TCPTTH = 1). Write: Force a transmit complete interrupt. 1 TCPTTH Transmit Complete Threshold. 20 1 SET_ON_TX A transmit is completed (TCPTI = 1) at the end of each transmission. 0 SET_ON_EMPTY A transmit is completed (TCPTI = 1) only at the end of a transmission when no more data is available to transmit. 1 TERIEN Transmit Error Interrupt Enable. 21 1 DISABLED Disable the transmit error interrupt. 0 ENABLED Enable the transmit error interrupt. A transmit interrupt is generated when TUREI or TSCERI is set to 1. 1 TDREQIEN Transmit Data Request Interrupt Enable. 22 1 DISABLED Disable the transmit data request interrupt. 0 ENABLED Enable the transmit data request interrupt. A transmit interrupt is asserted when TDREQI is set to 1. 1 TCPTIEN Transmit Complete Interrupt Enable. 23 1 DISABLED Disable the transmit complete interrupt. 0 ENABLED Enable the transmit complete interrupt. A transmit interrupt is generated when TCPTI is set to 1. 1 TBUSYF Transmitter Busy Flag. 27 1 read-only NOT_SET The UART transmitter is idle. 0 SET The UART transmitter is active and transmitting. 1 TBIT Last Transmit Bit. 28 1 NOT_SET 0 SET 1 TINH Transmit Inhibit. 30 1 INACTIVE The transmitter operates normally. 0 ACTIVE Transmissions are inhibited. The transmitter will stall after any current transmission is complete. 1 TEN Transmitter Enable. 31 1 DISABLED Disable the transmitter. When cleared, the transmitter immediately aborts any active transmission. Clearing this bit does not automatically flush the transmit FIFO. 0 ENABLED Enable the transmitter. The transmitter will initiate a transmission when data becomes available in the transmit FIFO. 1 IPDELAY Inter-Packet Delay 0x40 0x00000000 0xFFFFFFFF IPDELAY Inter-Packet Delay. 16 8 BAUDRATE Transmit and Receive Baud Rate 0x50 0x00000000 0xFFFFFFFF RBAUD Receiver Baud Rate Control. 0 16 TBAUD Transmitter Baud Rate Control. 16 16 FIFOCN FIFO Control 0x60 0x00000000 0xFFFFFFFF RCNT Receive FIFO Count. 0 3 read-only RFTH Receive FIFO Threshold. 4 2 ONE A read data request interrupt (RDREQI) is asserted when >= 1 FIFO slot is full. 0 TWO A read data request interrupt (RDREQI) is asserted when >= 2 FIFO slots are full. 1 FOUR A read data request interrupt (RDREQI) is asserted when >= 4 FIFO slots are full. 2 RFIFOFL Receive FIFO Flush. 8 1 SET Flush the contents of the receive FIFO and any data in the receive shift register. 1 RFERI Receive FIFO Error Interrupt Flag. 9 1 NOT_SET A receive FIFO error has not occurred since RFERI was last cleared. 0 SET A receive FIFO error occurred. 1 RSRFULLF Receive Shift Register Full . 10 1 read-only NOT_SET The receive data shift register is not full. 0 SET The receive data shift register is full. 1 TCNT Transmit FIFO Count. 16 3 read-only TFTH Transmit FIFO Threshold. 20 2 ONE A transmit data request interrupt (TDREQI) is asserted when >= 1 FIFO slot is empty. 0 TWO A transmit data request interrupt (TDREQI) is asserted when >= 2 FIFO slots are empty. 1 FOUR A transmit data request interrupt (TDREQI) is asserted when >= 4 FIFO slots are empty. 2 TFIFOFL Transmit FIFO Flush. 24 1 SET Flush the contents of the transmit FIFO. If data is pending in the transmit shift register but a transmit has not begun, the shift register is also flushed. 1 TFERI Transmit FIFO Error Interrupt Flag. 25 1 NOT_SET A transmit FIFO error has not occurred since TFERI was last cleared. 0 SET A transmit FIFO error occurred. 1 TSRFULLF Transmit Shift Register Full Flag. 26 1 read-only NOT_SET The transmit shift register is not full. 0 SET The transmit shift register is full. 1 DATA FIFO Input/Output Data 0x70 0x00000000 0xFFFFFFFF modifyExternal DATA FIFO Data. 0 32 USART_0 A None USART 0x40000000 0x0 0xffc registers USART0_IRQn 27 CONFIG Module Configuration 0x0 0x030D030D 0xFFFFFFFF RSTRTEN Receiver Start Enable. 0 1 DISABLED Do not expect a start bit during receptions. 0 ENABLED Expect a start bit during receptions. 1 RPAREN Receiver Parity Enable. 1 1 DISABLED Do not expect a parity bit during receptions. 0 ENABLED Expect a parity bit during receptions. 1 RSTPEN Receiver Stop Enable. 2 1 DISABLED Do not expect stop bits during receptions. 0 ENABLED Expect stop bits during receptions. 1 RSTPMD Receiver Stop Mode. 3 2 0P5_STOP 0.5 stop bit. 0 1_STOP 1 stop bit. 1 1P5_STOP 1.5 stop bits. 2 2_STOP 2 stop bits. 3 RPARMD Receiver Parity Mode. 5 2 ODD Odd Parity. 0 EVEN Even Parity. 1 MARK Set (Parity = 1). 2 SPACE Clear (Parity = 0). 3 RDATLN Receiver Data Length. 8 3 5_BITS 5 bits. 0 6_BITS 6 bits. 1 7_BITS 7 bits. 2 8_BITS 8 bits. 3 9_BITS_STORED 9 bits. The 9th bit is stored in the FIFO (normal mode). 4 9_BITS_MATCH 9 bits. The 9th bit is not stored in the FIFO (fixed mode). This mode is used when the 9th bit is only used for match operations (see MATMD). 5 RSCEN Receiver Smartcard Parity Response Enable. 12 1 DISABLED The receiver does not send a Smartcard parity error response. 0 ENABLED The receiver sends a Smartcard parity response. 1 RIRDAEN Receiver IrDA Enable. 13 1 DISABLED The receiver does not operate in IrDA mode. 0 ENABLED The receiver operates in IrDA mode. 1 RINVEN Receiver Invert Enable. 14 1 DISABLED Do not invert the RX pin signals (the RX idle state is high). 0 ENABLED Invert the RX pin signals (the RX idle state is low). 1 RSYNCEN Receiver Synchronous Mode Enable. 15 1 DISABLED The receiver operates in asynchronous mode. 0 ENABLED The receiver operates in synchronous mode. 1 TSTRTEN Transmitter Start Enable. 16 1 DISABLED Do not generate a start bit during transmissions. 0 ENABLED Generate a start bit during transmissions. 1 TPAREN Transmitter Parity Enable. 17 1 DISABLED Do not send a parity bit during transmissions. 0 ENABLED Send a parity bit during transmissions. 1 TSTPEN Transmitter Stop Enable. 18 1 DISABLED Do not send stop bits during transmissions. 0 ENABLED Send stop bits during transmissions. 1 TSTPMD Transmitter Stop Mode. 19 2 0P5_STOP 0.5 stop bit. 0 1_STOP 1 stop bit. 1 1P5_STOP 1.5 stop bits. 2 2_STOP 2 stop bits. 3 TPARMD Transmitter Parity Mode. 21 2 ODD Odd Parity. 0 EVEN Even Parity. 1 MARK Set (Parity = 1). 2 SPACE Clear (Parity = 0). 3 TDATLN Transmitter Data Length. 24 3 5_BITS 5 bits. 0 6_BITS 6 bits. 1 7_BITS 7 bits. 2 8_BITS 8 bits. 3 9_BITS_FIFO 9 bits. The 9th bit is taken from the FIFO data (normal mode). 4 9_BITS_TBIT 9 bits. The 9th bit is set by the value of TBIT (fixed mode). 5 TSCEN Transmitter Smartcard Parity Response Enable. 28 1 DISABLED The transmitter does not check for a Smartcard parity error response. 0 ENABLED The transmitter checks for a Smartcard parity error response. 1 TIRDAEN Transmitter IrDA Enable. 29 1 DISABLED Disable IrDA transmit mode. 0 ENABLED Enable IrDA transmit mode. 1 TINVEN Transmitter Invert Enable. 30 1 DISABLED Do not invert the TX pin signals (the TX idle state is high). 0 ENABLED Invert the TX pin signals (the TX idle state is low). 1 TSYNCEN Transmitter Synchronous Mode Enable. 31 1 DISABLED The transmitter operates in asynchronous mode. 0 ENABLED The transmitter operates in synchronous mode. 1 MODE Module Mode Select 0x10 0x00600000 0xFFFFFFFF DBGMD USART Debug Mode. 16 1 RUN The USART module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the USART module to halt. Any active transmissions and receptions will complete first. 1 LBMD Loop Back Mode. 18 2 DISABLED Loop back is disabled and the TX and RX signals are connected to the corresponding external pins. 0 RXONLY Receive loop back. The receiver input path is disconnected from the RX pin and internally connected to the transmitter. Data transmitted will be sent out on TX and also received by the device. 1 TXONLY Transmit loop back. The transmitter output path is disconnected from the TX pin and the RX input pin is internally looped back out to the TX pin. Data received at RX will be received by the device and also sent directly back out on TX. 2 BOTH Full loop back. Internally, the transmitter output is routed back to the receiver input. Neither the transmitter nor receiver are connected to external device pins. The device pin RX is looped back to TX in a similar fashion. Data transmitted on TX will be sent directly back in on RX. 3 STPSTCLK Stop State Clock Control. 21 1 DISABLED When the USART is a clock master, the clock is not generated during stop bits. 0 ENABLED When the USART is a clock master, the clock is generated during stop bits. 1 STRTSTCLK Start State Clock Control. 22 1 DISABLED When the USART is a clock master, the clock is held idle during a start bit. 0 ENABLED When the USART is a clock master, the clock is generated during a start bit. 1 ISTCLK Idle Clock Control. 23 1 DISABLED When the USART is a clock master and CLKESEL is not equal to CLKIDLE, the clock is held idle between transmissions. When the USART is a clock master and CLKESEL equals CLKIDEL, the clock will still be generated between transmissions. When the USART is a clock slave, the USART will begin transmissions without waiting for the next clock edge. 0 ENABLED When the USART is a clock master, the clock is generated between transmissions or receptions. When the USART is a clock slave, the USART will wait until the next clock edge before transmitting. 1 DUPLEXMD Duplex Mode. 27 1 FULL_DUPLEX Full-duplex mode. The transmitter and receiver can operate simultaneously. 0 HALF_DUPLEX Half-duplex mode. The transmitter automatically inhibits when the receiver is active and the receiver automatically inhibits when the transmitter is active. 1 CLKIDLE Clock Idle State. 28 1 IDLE_LOW The synchronous clock is low when idle. 0 IDLE_HIGH The synchronous clock is high when idle. 1 CLKESEL Clock Edge Select. 29 1 FALLING The clock falls in the middle of each bit. 0 RISING The clock rises in the middle of each bit. 1 ITSEN Idle TX/UCLK Tristate Enable. 30 1 DISABLED The TX and UCLK (if in synchronous master mode) pins are always an output in this mode, even when idle. 0 ENABLED The TX pin is tristated when idle. If ISTCLK is cleared to 0 and the transmitter is configured in synchronous master mode, the UCLK pin will also be tristated when idle. 1 OPMD Operational Mode. 31 1 SLAVE The USART operates as a slave. 0 MASTER The USART operates as a master. 1 FLOWCN Flow Control 0x20 0x00020001 0xFFFFFFFF RTS RTS State. 0 1 LOW RTS pin (before optional inversion) is driven low. 0 HIGH RTS pin (before optional inversion) is driven high. 1 RX RX Pin Status. 1 1 read-only LOW RX pin (after optional inversion) is low. 0 HIGH RX pin (after optional inversion) is high. 1 RTSINVEN RTS Invert Enable. 5 1 DISABLED The USART does not invert the RTS signal before driving the pin. 0 ENABLED The USART inverts the RTS signal driving the pin. 1 RTSTH RTS Threshold Control. 6 1 FULL RTS is de-asserted when the receive FIFO and shift register are full and no more incoming data can be stored. 0 ONE_BYTE_FREE RTS is de-asserted when the receive FIFO and shift register are nearly full and only one more data can be received. 1 RTSEN RTS Enable. 7 1 DISABLED The RTS state is not changed by hardware. The RTS bit can be written only when hardware RTS is disabled (RTSEN = 0). 0 ENABLED Hardware sets RTS when the receive FIFO is at or above the threshold set by RTSTH and clears RTS otherwise. 1 CTS CTS State. 16 1 read-only LOW Indicates the CTS pin state (after optional inversion) is low. 0 HIGH Indicates the CTS pin state (after optional inversion) is high. 1 TX TX State. 17 1 LOW The TX pin (before optional inversion) is low. 0 HIGH The TX pin (before optional inversion) is high. 1 UCLK UCLK State. 18 1 LOW The UCLK pin is low. 0 HIGH The UCLK pin is high. 1 CTSINVEN CTS Invert Enable. 21 1 DISABLED The USART does not invert CTS. 0 ENABLED The USART inverts CTS. 1 CTSEN CTS Enable. 23 1 DISABLED The CTS pin state does not affect transmissions. 0 ENABLED Transmissions will begin only if the CTS pin (after optional inversion) is low. 1 TIRDAPW Transmit IrDA Pulse Width. 28 2 1_16TH The IrDA pulse width is 1/16th of a bit period. 0 1_8TH The IrDA pulse width is 1/8th of a bit period. 1 3_16TH The IrDA pulse width is 3/16th of a bit period. 2 1_4TH The IrDA pulse width is 1/4th of a bit period. 3 CONTROL Module Control 0x30 0x00000000 0xFFFFFFFF RFRMERI Receive Frame Error Interrupt Flag. 0 1 NOT_SET Read: A frame error has not occurred since RFRMERI was last cleared. Write: Clear the interrupt. 0 SET Read: A frame error occurred. Write: Force a frame error interrupt. 1 RPARERI Receive Parity Error Interrupt Flag. 1 1 NOT_SET Read: An invalid parity bit has not been received since RPARERI was last cleared. Write: Clear the interrupt. 0 SET Read: An invalid parity bit has been received since RPARERI was last cleared. Write: Force a parity error interrupt. 1 ROREI Receive Overrun Error Interrupt Flag. 2 1 NOT_SET Read: A receiver overrun has not occurred since ROREI was last cleared. Write: Clear the interrupt. 0 SET Read: A receiver overrun occurred. Write: Force a receiver overrun interrupt. 1 RDREQI Receive Data Request Interrupt Flag. 3 1 read-only NOT_SET Fewer than RFTH FIFO slots are filled with data. 0 SET At least RFTH FIFO slots are filled with data. 1 RERIEN Receive Error Interrupt Enable. 5 1 DISABLED Disable the receive error interrupt. 0 ENABLED Enable the receive error interrupt. A receive error interrupt is asserted when ROREI, RFRMERI, or RPARERI is set to 1. 1 RDREQIEN Receive Data Request Interrupt Enable. 6 1 DISABLED Disable the read data request interrupt. 0 ENABLED Enable the read data request interrupt. A receive interrupt is generated when RDREQI is set to 1. 1 MATMD Match Mode. 8 2 OFF Disable the match function. 0 MCE (MCE) Data whose last data bit equals RBIT is accepted and stored. 1 FRAME (Frame) A framing error is asserted if the last received bit matches RBIT. 2 STORE (Store) Store the last incoming data bit in RBIT. This mode can be used inconjunction with the RDATLN setting. 3 RABDEN Receiver Auto-Baud Enable. 10 1 DISABLED Disable receiver auto-baud. 0 ENABLED Enable receiver auto-baud. 1 RBUSYF Receiver Busy Flag. 11 1 read-only NOT_SET The USART receiver is idle. 0 SET The USART receiver is receiving data. 1 RBIT Last Receive Bit. 12 1 NOT_SET 0 SET 1 ROSEN Receiver One-Shot Enable. 13 1 DISABLED Disable one-shot receive mode. 0 ENABLED Enable one-shot receive mode. 1 RINH Receiver Inhibit. 14 1 INACTIVE The receiver operates normally. 0 ACTIVE RTS is immediately asserted when RINH is set. The receiver will complete any ongoing reception, but ignore all traffic after that. 1 REN Receiver Enable. 15 1 DISABLED Disable the receiver. The receiver can receive one data transaction only if ROSEN is set. 0 ENABLED Enable the receiver. 1 TSCERI Smartcard Parity Error Interrupt Flag. 16 1 NOT_SET Read: A Smartcard parity error has not occurred since TSCERI was last cleared. Write: Clear the interrupt. 0 SET Read: A Smartcard parity error occurred. Write: Force a Smartcard parity error interrupt. 1 TUREI Transmit Underrun Error Interrupt Flag. 17 1 NOT_SET Read: A transmitter underrun has not occurred since TUREI was last cleared. Write: Clear the interrupt. 0 SET Read: A transmitter underrun occurred. Write: Force a transmitter underrun interrupt. 1 TDREQI Transmit Data Request Interrupt Flag. 18 1 read-only NOT_SET The transmitter is not requesting more FIFO data. 0 SET The transmitter is requesting more FIFO data. 1 TCPTI Transmit Complete Interrupt Flag. 19 1 NOT_SET Read: A transmit has not completed since TCPTI was last cleared. Write: Clear the interrupt. 0 SET Read: A byte was transmitted (TCCPTH = 0) or the last available byte was transmitted (TCPTTH = 1). Write: Force a transmit complete interrupt. 1 TCPTTH Transmit Complete Threshold. 20 1 SET_ON_TX A transmit is completed (TCPTI = 1) at the end of each transmission. 0 SET_ON_EMPTY A transmit is completed (TCPTI = 1) only at the end of a transmission when no more data is available to transmit. 1 TERIEN Transmit Error Interrupt Enable. 21 1 DISABLED Disable the transmit error interrupt. 0 ENABLED Enable the transmit error interrupt. A transmit interrupt is generated when TUREI or TSCERI is set to 1. 1 TDREQIEN Transmit Data Request Interrupt Enable. 22 1 DISABLED Disable the transmit data request interrupt. 0 ENABLED Enable the transmit data request interrupt. A transmit interrupt is asserted when TDREQI is set to 1. 1 TCPTIEN Transmit Complete Interrupt Enable. 23 1 DISABLED Disable the transmit complete interrupt. 0 ENABLED Enable the transmit complete interrupt. A transmit interrupt is generated when TCPTI is set to 1. 1 TBUSYF Transmitter Busy Flag. 27 1 read-only NOT_SET The USART transmitter is idle. 0 SET The USART transmitter is active and transmitting. 1 TBIT Last Transmit Bit. 28 1 NOT_SET 0 SET 1 TINH Transmit Inhibit. 30 1 INACTIVE The transmitter operates normally. 0 ACTIVE Transmissions are inhibited. The transmitter will stall after any current transmission is complete. 1 TEN Transmitter Enable. 31 1 DISABLED Disable the transmitter. When cleared, the transmitter immediately aborts any active transmission. Clearing this bit does not automatically flush the transmit FIFO. 0 ENABLED Enable the transmitter. The transmitter will initiate a transmission when data becomes available in the transmit FIFO. 1 IPDELAY Inter-Packet Delay 0x40 0x00000000 0xFFFFFFFF IPDELAY Inter-Packet Delay. 16 8 BAUDRATE Transmit and Receive Baud Rate 0x50 0x00000000 0xFFFFFFFF RBAUD Receiver Baud Rate Control. 0 16 TBAUD Transmitter Baud Rate Control. 16 16 FIFOCN FIFO Control 0x60 0x00000000 0xFFFFFFFF RCNT Receive FIFO Count. 0 3 read-only RFTH Receive FIFO Threshold. 4 2 ONE A DMA request or read data request interrupt (RDREQI) is asserted when >= 1 FIFO slot is full. 0 TWO A DMA request or read data request interrupt (RDREQI) is asserted when >= 2 FIFO slots are full. 1 FOUR A DMA request or read data request interrupt (RDREQ) is asserted when >= 4 FIFO slots are full. 2 RDMAEN Receiver DMA Enable. 7 1 DISABLED Disable receive FIFO DMA requests. 0 ENABLED Enable receive FIFO DMA requests. 1 RFIFOFL Receive FIFO Flush. 8 1 SET Flush the contents of the receive FIFO and any data in the receive shift register. 1 RFERI Receive FIFO Error Interrupt Flag. 9 1 NOT_SET A receive FIFO error has not occurred since RFERI was last cleared. 0 SET A receive FIFO error occurred. 1 RSRFULLF Receive Shift Register Full Flag. 10 1 read-only NOT_SET The receive data shift register is not full. 0 SET The receive data shift register is full. 1 TCNT Transmit FIFO Count. 16 3 read-only TFTH Transmit FIFO Threshold. 20 2 ONE A DMA request or transmit data request interrupt (TDREQI) is asserted when >= 1 FIFO slot is empty. 0 TWO A DMA request or transmit data request interrupt (TDREQI) is asserted when >= 2 FIFO slots are empty. 1 FOUR A DMA request or transmit data request interrupt (TDREQ) is asserted when >= 4 FIFO slots are empty. 2 TDMAEN Transmitter DMA Enable. 23 1 DISABLED Disable transmit FIFO DMA requests. 0 ENABLED Enable transmit FIFO DMA requests. 1 TFIFOFL Transmit FIFO Flush. 24 1 SET Flush the contents of the transmit FIFO. If data is pending in the transmit shift register but a transmit has not begun, the shift register is also flushed. 1 TFERI Transmit FIFO Error Interrupt Flag. 25 1 NOT_SET A transmit FIFO error has not occurred since TFERI was last cleared. 0 SET A transmit FIFO error occurred. 1 TSRFULLF Transmit Shift Register Full Flag. 26 1 read-only NOT_SET The transmit shift register is not full. 0 SET The transmit shift register is full. 1 DATA FIFO Input/Output Data 0x70 0x00000000 0xFFFFFFFF modifyExternal DATA FIFO Data. 0 32 USART_1 A None USART 0x40001000 0x0 0xffc registers USART1_IRQn 28 CONFIG Module Configuration 0x0 0x030D030D 0xFFFFFFFF RSTRTEN Receiver Start Enable. 0 1 DISABLED Do not expect a start bit during receptions. 0 ENABLED Expect a start bit during receptions. 1 RPAREN Receiver Parity Enable. 1 1 DISABLED Do not expect a parity bit during receptions. 0 ENABLED Expect a parity bit during receptions. 1 RSTPEN Receiver Stop Enable. 2 1 DISABLED Do not expect stop bits during receptions. 0 ENABLED Expect stop bits during receptions. 1 RSTPMD Receiver Stop Mode. 3 2 0P5_STOP 0.5 stop bit. 0 1_STOP 1 stop bit. 1 1P5_STOP 1.5 stop bits. 2 2_STOP 2 stop bits. 3 RPARMD Receiver Parity Mode. 5 2 ODD Odd Parity. 0 EVEN Even Parity. 1 MARK Set (Parity = 1). 2 SPACE Clear (Parity = 0). 3 RDATLN Receiver Data Length. 8 3 5_BITS 5 bits. 0 6_BITS 6 bits. 1 7_BITS 7 bits. 2 8_BITS 8 bits. 3 9_BITS_STORED 9 bits. The 9th bit is stored in the FIFO (normal mode). 4 9_BITS_MATCH 9 bits. The 9th bit is not stored in the FIFO (fixed mode). This mode is used when the 9th bit is only used for match operations (see MATMD). 5 RSCEN Receiver Smartcard Parity Response Enable. 12 1 DISABLED The receiver does not send a Smartcard parity error response. 0 ENABLED The receiver sends a Smartcard parity response. 1 RIRDAEN Receiver IrDA Enable. 13 1 DISABLED The receiver does not operate in IrDA mode. 0 ENABLED The receiver operates in IrDA mode. 1 RINVEN Receiver Invert Enable. 14 1 DISABLED Do not invert the RX pin signals (the RX idle state is high). 0 ENABLED Invert the RX pin signals (the RX idle state is low). 1 RSYNCEN Receiver Synchronous Mode Enable. 15 1 DISABLED The receiver operates in asynchronous mode. 0 ENABLED The receiver operates in synchronous mode. 1 TSTRTEN Transmitter Start Enable. 16 1 DISABLED Do not generate a start bit during transmissions. 0 ENABLED Generate a start bit during transmissions. 1 TPAREN Transmitter Parity Enable. 17 1 DISABLED Do not send a parity bit during transmissions. 0 ENABLED Send a parity bit during transmissions. 1 TSTPEN Transmitter Stop Enable. 18 1 DISABLED Do not send stop bits during transmissions. 0 ENABLED Send stop bits during transmissions. 1 TSTPMD Transmitter Stop Mode. 19 2 0P5_STOP 0.5 stop bit. 0 1_STOP 1 stop bit. 1 1P5_STOP 1.5 stop bits. 2 2_STOP 2 stop bits. 3 TPARMD Transmitter Parity Mode. 21 2 ODD Odd Parity. 0 EVEN Even Parity. 1 MARK Set (Parity = 1). 2 SPACE Clear (Parity = 0). 3 TDATLN Transmitter Data Length. 24 3 5_BITS 5 bits. 0 6_BITS 6 bits. 1 7_BITS 7 bits. 2 8_BITS 8 bits. 3 9_BITS_FIFO 9 bits. The 9th bit is taken from the FIFO data (normal mode). 4 9_BITS_TBIT 9 bits. The 9th bit is set by the value of TBIT (fixed mode). 5 TSCEN Transmitter Smartcard Parity Response Enable. 28 1 DISABLED The transmitter does not check for a Smartcard parity error response. 0 ENABLED The transmitter checks for a Smartcard parity error response. 1 TIRDAEN Transmitter IrDA Enable. 29 1 DISABLED Disable IrDA transmit mode. 0 ENABLED Enable IrDA transmit mode. 1 TINVEN Transmitter Invert Enable. 30 1 DISABLED Do not invert the TX pin signals (the TX idle state is high). 0 ENABLED Invert the TX pin signals (the TX idle state is low). 1 TSYNCEN Transmitter Synchronous Mode Enable. 31 1 DISABLED The transmitter operates in asynchronous mode. 0 ENABLED The transmitter operates in synchronous mode. 1 MODE Module Mode Select 0x10 0x00600000 0xFFFFFFFF DBGMD USART Debug Mode. 16 1 RUN The USART module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the USART module to halt. Any active transmissions and receptions will complete first. 1 LBMD Loop Back Mode. 18 2 DISABLED Loop back is disabled and the TX and RX signals are connected to the corresponding external pins. 0 RXONLY Receive loop back. The receiver input path is disconnected from the RX pin and internally connected to the transmitter. Data transmitted will be sent out on TX and also received by the device. 1 TXONLY Transmit loop back. The transmitter output path is disconnected from the TX pin and the RX input pin is internally looped back out to the TX pin. Data received at RX will be received by the device and also sent directly back out on TX. 2 BOTH Full loop back. Internally, the transmitter output is routed back to the receiver input. Neither the transmitter nor receiver are connected to external device pins. The device pin RX is looped back to TX in a similar fashion. Data transmitted on TX will be sent directly back in on RX. 3 STPSTCLK Stop State Clock Control. 21 1 DISABLED When the USART is a clock master, the clock is not generated during stop bits. 0 ENABLED When the USART is a clock master, the clock is generated during stop bits. 1 STRTSTCLK Start State Clock Control. 22 1 DISABLED When the USART is a clock master, the clock is held idle during a start bit. 0 ENABLED When the USART is a clock master, the clock is generated during a start bit. 1 ISTCLK Idle Clock Control. 23 1 DISABLED When the USART is a clock master and CLKESEL is not equal to CLKIDLE, the clock is held idle between transmissions. When the USART is a clock master and CLKESEL equals CLKIDEL, the clock will still be generated between transmissions. When the USART is a clock slave, the USART will begin transmissions without waiting for the next clock edge. 0 ENABLED When the USART is a clock master, the clock is generated between transmissions or receptions. When the USART is a clock slave, the USART will wait until the next clock edge before transmitting. 1 DUPLEXMD Duplex Mode. 27 1 FULL_DUPLEX Full-duplex mode. The transmitter and receiver can operate simultaneously. 0 HALF_DUPLEX Half-duplex mode. The transmitter automatically inhibits when the receiver is active and the receiver automatically inhibits when the transmitter is active. 1 CLKIDLE Clock Idle State. 28 1 IDLE_LOW The synchronous clock is low when idle. 0 IDLE_HIGH The synchronous clock is high when idle. 1 CLKESEL Clock Edge Select. 29 1 FALLING The clock falls in the middle of each bit. 0 RISING The clock rises in the middle of each bit. 1 ITSEN Idle TX/UCLK Tristate Enable. 30 1 DISABLED The TX and UCLK (if in synchronous master mode) pins are always an output in this mode, even when idle. 0 ENABLED The TX pin is tristated when idle. If ISTCLK is cleared to 0 and the transmitter is configured in synchronous master mode, the UCLK pin will also be tristated when idle. 1 OPMD Operational Mode. 31 1 SLAVE The USART operates as a slave. 0 MASTER The USART operates as a master. 1 FLOWCN Flow Control 0x20 0x00020001 0xFFFFFFFF RTS RTS State. 0 1 LOW RTS pin (before optional inversion) is driven low. 0 HIGH RTS pin (before optional inversion) is driven high. 1 RX RX Pin Status. 1 1 read-only LOW RX pin (after optional inversion) is low. 0 HIGH RX pin (after optional inversion) is high. 1 RTSINVEN RTS Invert Enable. 5 1 DISABLED The USART does not invert the RTS signal before driving the pin. 0 ENABLED The USART inverts the RTS signal driving the pin. 1 RTSTH RTS Threshold Control. 6 1 FULL RTS is de-asserted when the receive FIFO and shift register are full and no more incoming data can be stored. 0 ONE_BYTE_FREE RTS is de-asserted when the receive FIFO and shift register are nearly full and only one more data can be received. 1 RTSEN RTS Enable. 7 1 DISABLED The RTS state is not changed by hardware. The RTS bit can be written only when hardware RTS is disabled (RTSEN = 0). 0 ENABLED Hardware sets RTS when the receive FIFO is at or above the threshold set by RTSTH and clears RTS otherwise. 1 CTS CTS State. 16 1 read-only LOW Indicates the CTS pin state (after optional inversion) is low. 0 HIGH Indicates the CTS pin state (after optional inversion) is high. 1 TX TX State. 17 1 LOW The TX pin (before optional inversion) is low. 0 HIGH The TX pin (before optional inversion) is high. 1 UCLK UCLK State. 18 1 LOW The UCLK pin is low. 0 HIGH The UCLK pin is high. 1 CTSINVEN CTS Invert Enable. 21 1 DISABLED The USART does not invert CTS. 0 ENABLED The USART inverts CTS. 1 CTSEN CTS Enable. 23 1 DISABLED The CTS pin state does not affect transmissions. 0 ENABLED Transmissions will begin only if the CTS pin (after optional inversion) is low. 1 TIRDAPW Transmit IrDA Pulse Width. 28 2 1_16TH The IrDA pulse width is 1/16th of a bit period. 0 1_8TH The IrDA pulse width is 1/8th of a bit period. 1 3_16TH The IrDA pulse width is 3/16th of a bit period. 2 1_4TH The IrDA pulse width is 1/4th of a bit period. 3 CONTROL Module Control 0x30 0x00000000 0xFFFFFFFF RFRMERI Receive Frame Error Interrupt Flag. 0 1 NOT_SET Read: A frame error has not occurred since RFRMERI was last cleared. Write: Clear the interrupt. 0 SET Read: A frame error occurred. Write: Force a frame error interrupt. 1 RPARERI Receive Parity Error Interrupt Flag. 1 1 NOT_SET Read: An invalid parity bit has not been received since RPARERI was last cleared. Write: Clear the interrupt. 0 SET Read: An invalid parity bit has been received since RPARERI was last cleared. Write: Force a parity error interrupt. 1 ROREI Receive Overrun Error Interrupt Flag. 2 1 NOT_SET Read: A receiver overrun has not occurred since ROREI was last cleared. Write: Clear the interrupt. 0 SET Read: A receiver overrun occurred. Write: Force a receiver overrun interrupt. 1 RDREQI Receive Data Request Interrupt Flag. 3 1 read-only NOT_SET Fewer than RFTH FIFO slots are filled with data. 0 SET At least RFTH FIFO slots are filled with data. 1 RERIEN Receive Error Interrupt Enable. 5 1 DISABLED Disable the receive error interrupt. 0 ENABLED Enable the receive error interrupt. A receive error interrupt is asserted when ROREI, RFRMERI, or RPARERI is set to 1. 1 RDREQIEN Receive Data Request Interrupt Enable. 6 1 DISABLED Disable the read data request interrupt. 0 ENABLED Enable the read data request interrupt. A receive interrupt is generated when RDREQI is set to 1. 1 MATMD Match Mode. 8 2 OFF Disable the match function. 0 MCE (MCE) Data whose last data bit equals RBIT is accepted and stored. 1 FRAME (Frame) A framing error is asserted if the last received bit matches RBIT. 2 STORE (Store) Store the last incoming data bit in RBIT. This mode can be used inconjunction with the RDATLN setting. 3 RABDEN Receiver Auto-Baud Enable. 10 1 DISABLED Disable receiver auto-baud. 0 ENABLED Enable receiver auto-baud. 1 RBUSYF Receiver Busy Flag. 11 1 read-only NOT_SET The USART receiver is idle. 0 SET The USART receiver is receiving data. 1 RBIT Last Receive Bit. 12 1 NOT_SET 0 SET 1 ROSEN Receiver One-Shot Enable. 13 1 DISABLED Disable one-shot receive mode. 0 ENABLED Enable one-shot receive mode. 1 RINH Receiver Inhibit. 14 1 INACTIVE The receiver operates normally. 0 ACTIVE RTS is immediately asserted when RINH is set. The receiver will complete any ongoing reception, but ignore all traffic after that. 1 REN Receiver Enable. 15 1 DISABLED Disable the receiver. The receiver can receive one data transaction only if ROSEN is set. 0 ENABLED Enable the receiver. 1 TSCERI Smartcard Parity Error Interrupt Flag. 16 1 NOT_SET Read: A Smartcard parity error has not occurred since TSCERI was last cleared. Write: Clear the interrupt. 0 SET Read: A Smartcard parity error occurred. Write: Force a Smartcard parity error interrupt. 1 TUREI Transmit Underrun Error Interrupt Flag. 17 1 NOT_SET Read: A transmitter underrun has not occurred since TUREI was last cleared. Write: Clear the interrupt. 0 SET Read: A transmitter underrun occurred. Write: Force a transmitter underrun interrupt. 1 TDREQI Transmit Data Request Interrupt Flag. 18 1 read-only NOT_SET The transmitter is not requesting more FIFO data. 0 SET The transmitter is requesting more FIFO data. 1 TCPTI Transmit Complete Interrupt Flag. 19 1 NOT_SET Read: A transmit has not completed since TCPTI was last cleared. Write: Clear the interrupt. 0 SET Read: A byte was transmitted (TCCPTH = 0) or the last available byte was transmitted (TCPTTH = 1). Write: Force a transmit complete interrupt. 1 TCPTTH Transmit Complete Threshold. 20 1 SET_ON_TX A transmit is completed (TCPTI = 1) at the end of each transmission. 0 SET_ON_EMPTY A transmit is completed (TCPTI = 1) only at the end of a transmission when no more data is available to transmit. 1 TERIEN Transmit Error Interrupt Enable. 21 1 DISABLED Disable the transmit error interrupt. 0 ENABLED Enable the transmit error interrupt. A transmit interrupt is generated when TUREI or TSCERI is set to 1. 1 TDREQIEN Transmit Data Request Interrupt Enable. 22 1 DISABLED Disable the transmit data request interrupt. 0 ENABLED Enable the transmit data request interrupt. A transmit interrupt is asserted when TDREQI is set to 1. 1 TCPTIEN Transmit Complete Interrupt Enable. 23 1 DISABLED Disable the transmit complete interrupt. 0 ENABLED Enable the transmit complete interrupt. A transmit interrupt is generated when TCPTI is set to 1. 1 TBUSYF Transmitter Busy Flag. 27 1 read-only NOT_SET The USART transmitter is idle. 0 SET The USART transmitter is active and transmitting. 1 TBIT Last Transmit Bit. 28 1 NOT_SET 0 SET 1 TINH Transmit Inhibit. 30 1 INACTIVE The transmitter operates normally. 0 ACTIVE Transmissions are inhibited. The transmitter will stall after any current transmission is complete. 1 TEN Transmitter Enable. 31 1 DISABLED Disable the transmitter. When cleared, the transmitter immediately aborts any active transmission. Clearing this bit does not automatically flush the transmit FIFO. 0 ENABLED Enable the transmitter. The transmitter will initiate a transmission when data becomes available in the transmit FIFO. 1 IPDELAY Inter-Packet Delay 0x40 0x00000000 0xFFFFFFFF IPDELAY Inter-Packet Delay. 16 8 BAUDRATE Transmit and Receive Baud Rate 0x50 0x00000000 0xFFFFFFFF RBAUD Receiver Baud Rate Control. 0 16 TBAUD Transmitter Baud Rate Control. 16 16 FIFOCN FIFO Control 0x60 0x00000000 0xFFFFFFFF RCNT Receive FIFO Count. 0 3 read-only RFTH Receive FIFO Threshold. 4 2 ONE A DMA request or read data request interrupt (RDREQI) is asserted when >= 1 FIFO slot is full. 0 TWO A DMA request or read data request interrupt (RDREQI) is asserted when >= 2 FIFO slots are full. 1 FOUR A DMA request or read data request interrupt (RDREQ) is asserted when >= 4 FIFO slots are full. 2 RDMAEN Receiver DMA Enable. 7 1 DISABLED Disable receive FIFO DMA requests. 0 ENABLED Enable receive FIFO DMA requests. 1 RFIFOFL Receive FIFO Flush. 8 1 SET Flush the contents of the receive FIFO and any data in the receive shift register. 1 RFERI Receive FIFO Error Interrupt Flag. 9 1 NOT_SET A receive FIFO error has not occurred since RFERI was last cleared. 0 SET A receive FIFO error occurred. 1 RSRFULLF Receive Shift Register Full Flag. 10 1 read-only NOT_SET The receive data shift register is not full. 0 SET The receive data shift register is full. 1 TCNT Transmit FIFO Count. 16 3 read-only TFTH Transmit FIFO Threshold. 20 2 ONE A DMA request or transmit data request interrupt (TDREQI) is asserted when >= 1 FIFO slot is empty. 0 TWO A DMA request or transmit data request interrupt (TDREQI) is asserted when >= 2 FIFO slots are empty. 1 FOUR A DMA request or transmit data request interrupt (TDREQ) is asserted when >= 4 FIFO slots are empty. 2 TDMAEN Transmitter DMA Enable. 23 1 DISABLED Disable transmit FIFO DMA requests. 0 ENABLED Enable transmit FIFO DMA requests. 1 TFIFOFL Transmit FIFO Flush. 24 1 SET Flush the contents of the transmit FIFO. If data is pending in the transmit shift register but a transmit has not begun, the shift register is also flushed. 1 TFERI Transmit FIFO Error Interrupt Flag. 25 1 NOT_SET A transmit FIFO error has not occurred since TFERI was last cleared. 0 SET A transmit FIFO error occurred. 1 TSRFULLF Transmit Shift Register Full Flag. 26 1 read-only NOT_SET The transmit shift register is not full. 0 SET The transmit shift register is full. 1 DATA FIFO Input/Output Data 0x70 0x00000000 0xFFFFFFFF modifyExternal DATA FIFO Data. 0 32 VMON_0 A None VMON_0 0x4002f000 0x0 0xffc registers VDDLOW_IRQn 43 VREGLOW_IRQn 53 CONTROL Module Control 0x0 0x80000000 0xFFFFFFFF VREGINSEN VREGIN Supply Monitor Enable. 0 1 DISABLED Disable the VREGIN supply monitor. 0 ENABLED Enable the VREGIN supply monitor. 1 VREGINLI VREGIN Low Interrupt Flag. 1 1 read-only VREGIN_IS_LOW VREGIN is not above the interrupt threshold. 0 VREGIN_IS_OK VREGIN is above the interrupt threshold. 1 VDDRSTF VDD Reset Threshold Status Flag. 2 1 read-only VDD_IS_BELOW_RESET The VDD voltage is below the VDD reset threshold. 0 VDD_IS_ABOVE_RESET The VDD voltage is above the VDD reset threshold. 1 VDDLI VDD Low Interrupt Flag. 3 1 read-only VDD_IS_LOW The VDD voltage is below the early warning threshold. 0 VDD_IS_OK The VDD voltage is above the early warning threshold. 1 VDDHITHEN VDD High Threshold Enable. 4 1 DISABLED Use the standard VDD thresholds. 0 ENABLED Use the high VDD thresholds. 1 VDDLIEN VDD Low Interrupt Enable. 6 1 DISABLED Disable the VDD low interrupt. 0 ENABLED Enable the VDD low interrupt. 1 VREGINLIEN VREGIN Low Interrupt Enable. 7 1 DISABLED Disable the VREGIN low interrupt. 0 ENABLED Enable the VREGIN low interrupt. 1 VMONEN VDD Supply Monitor Enable. 31 1 DISABLED Disable the VDD supply monitor. 0 ENABLED Enable the VDD supply monitor. 1 VREF_0 A None VREF_0 0x40039010 0x0 0xffc registers CONTROL Voltage Reference Control 0x0 0x00000000 0xFFFFFFFF VREF2X Voltage Reference Doubler. 0 1 DISABLED VREF output is nominally 1.2 V 0 ENABLED VREF output is nominally 2.4 V 1 TEMPEN Temperature Sensor Enable. 1 1 DISABLED Disable the temperature sensor. 0 ENABLED Enable the temperature sensor. 1 VREFEN Voltage Reference Enable. 31 1 DISABLED Disable the Voltage Reference. 0 ENABLED Enable the Voltage Reference. 1 EXTVREG_0 A None Voltage_Regulators 0x40042000 0x0 0xffc registers CONTROL Module Control 0x0 0x00000000 0xFFFFFFFF SAEN Stand-Alone Mode Enable. 0 1 DISABLED Use the external regulator in normal mode. 0 ENABLED Use the external regulator in stand-alone mode. 1 WPULLEN Weak Pull Up/Down Enable. 24 1 DISABLED Disable the external regulator weak pull-up/down resistor on the EXREGBD pin and weak pull-down resistor on the EXREGOUT pin. 0 ENABLED Enable the external regulator weak pull-up/down resistor on the EXREGBD pin and weak pull-down resistor on the EXREGOUT pin. 1 FBLEN Foldback Limiting Enable. 25 1 DISABLED Disable foldback limiting. 0 ENABLED Enable foldback limiting. 1 PNSEL NPN/PNP Type Select. 26 1 NPN Select NPN Mode. 0 PNP Select PNP Mode. 1 FBPINSEL Foldback Sensing Pin Select. 27 1 EXREGSN Use the input to the EXREGSN pin for foldback limiting. 0 VREGIN Use the input to the VREGIN pin for foldback limiting. 1 EVREGEN External Regulator Enable. 31 1 DISABLED Disable the external regulator. 0 ENABLED Enable the external regulator. 1 CONFIG Module Configuration 0x10 0x00000000 0xFFFFFFFF IMINFINE Minimum Current Fine Select. 0 2 0_UA Minimum current limit is IMIN current + 0 uA. 0 0P25_UA Minimum current limit is IMIN current + 0.25 uA. 1 0P5_UA Minimum current limit is IMIN current + 0.50 uA. 2 0P75_UA Minimum current limit is IMIN current + 0.75 uA. 3 IMIN Minimum Current Select. 2 3 1_UA Minimum current limit is 1 uA + IMINFINE current. 0 2_UA Minimum current limit is 2 uA + IMINFINE current. 1 3_UA Minimum current limit is 3 uA + IMINFINE current. 2 4_UA Minimum current limit is 4 uA + IMINFINE current. 3 5_UA Minimum current limit is 5 uA + IMINFINE current. 4 6_UA Minimum current limit is 6 uA + IMINFINE current. 5 7_UA Minimum current limit is 7 uA + IMINFINE current. 6 8_UA Minimum current limit is 8 uA + IMINFINE current. 7 FBVOSEL Foldback Voltage Offset Select. 8 3 0_V Foldback voltage offset is 0 V. 0 0P5_V Foldback voltage offset is 0.5 V. 1 1_V Foldback voltage offset is 1 V. 2 1P5_V Foldback voltage offset is 1.5 V. 3 2_V Foldback voltage offset is 2 V. 4 2P5_V Foldback voltage offset is 2.5 V. 5 3_V Foldback voltage offset is 3 V. 6 3P5_V Foldback voltage offset is 3.5 V. 7 FBRATE Voltage Sense Gain Multiplier. 12 3 4_UA_PER_V Set the foldback rate to 4 uA/V. 0 2_UA_PER_V Set the foldback rate to 2 uA/V. 1 1_UA_PER_V Set the foldback rate to 1 uA/V. 2 0P5_UA_PER_V Set the foldback rate to 0.5 uA/V. 3 8_UA_PER_V Set the foldback rate to 8 uA/V. 5 16_UA_PER_V Set the foldback rate to 16 uA/V. 6 32_UA_PER_V Set the foldback rate to 32 uA/V. 7 IMAX Maximum Current Select. 16 3 2_UA Maximum current limit is 2 uA. 0 3_UA Maximum current limit is 3 uA. 1 4_UA Maximum current limit is 4 uA. 2 5_UA Maximum current limit is 5 uA. 3 6_UA Maximum current limit is 6 uA. 4 7_UA Maximum current limit is 7 uA. 5 8_UA Maximum current limit is 8 uA. 6 9_UA Maximum current limit is 9 uA. 7 VOUTSEL Regulator Output Voltage Select. 24 6 STATUS Module Status 0x20 0x00000000 0xFFFFFFFF FBMAXF Maximum Foldback Flag. 0 1 read-only NOT_SET Maximum foldback has not been reached. 0 SET Maximum foldback has been reached. 1 CSCONTROL Current Sense Control 0x40 0x00000000 0xFFFFFFFF ISNSEN External Regulator Current Sense Enable. 30 1 DISABLED Disable external regulator current sensing. 0 ENABLED Enable external regulator current sensing. 1 ADCISNSEN ADC Current Sense Enable. 31 1 DISABLED Disable ADC current sensing. 0 ENABLED Enable ADC current sensing. 1 CSCONFIG Current Sense Configuration 0x50 0x00000000 0xFFFFFFFF ISADCGAIN ADC Current Sense Gain. 0 3 16X ADC current sensing input gain is 16. 0 8X ADC current sensing input gain is 8. 1 4X ADC current sensing input gain is 4. 2 2X ADC current sensing input gain is 2. 3 1X ADC current sensing input gain is 1. 4 ISOGAIN External Regulator Current Sense Gain. 3 3 16X External regulator current sensing gain is 16. 0 8X External regulator current sensing gain is 8. 1 4X External regulator current sensing gain is 4. 2 2X External regulator current sensing gain is 2. 3 1X External regulator current sensing gain is 1. 4 ISINSEL External Regulator Current Sense Input Select. 6 2 MODE0 Select external regulator current sensing mode 0. 0 MODE1 Select external regulator current sensing mode 1. 1 MODE2 Select external regulator current sensing mode 2. 2 VREG_0 A None Voltage_Regulators 0x40040000 0x0 0xffc registers VREGDROPOUT_IRQn 52 CONTROL Module Control 0x0 0x40000100 0xFFFFFFFF VBUSVLDF VBUS Valid Flag. 0 1 read-only NOT_SET The current voltage on the VBUS pin is below the valid threshold. 0 SET The current voltage on the VBUS pin is above the valid threshold. 1 SUSEN Voltage Regulator Suspend Enable. 1 1 DISABLED Disable regulator suspend mode. 0 ENABLED Enable regulator suspend mode. 1 BGDIS Band Gap Disable. 5 1 INACTIVE Enable the voltage regulator band gap. 0 ACTIVE Disable the voltage regulator band gap. 1 SENSEEN VREGIN Sense Enable. 6 1 DISABLED Disable VREGIN voltage sensing. 0 ENABLED Enable VREGIN voltage sensing. 1 VBUSIVLDI VBUS Invalid Interrupt Flag. 7 1 NOT_SET The voltage on the VBUS pin has not dropped below the valid threshold. 0 SET The voltage on the VBUS pin dropped below the valid threshold since the last time this bit was cleared. 1 VBUSIVLDIEN VBUS Invalid Interrupt Enable. 8 1 DISABLED Disable the VBUS invalid interrupt. 0 ENABLED Enable the VBUS invalid interrupt. 1 VREGDIS Voltage Regulator Disable. 31 1 INACTIVE Enable the voltage regulator. 0 ACTIVE Disable the voltage regulator. 1 LDO_0 A None Voltage_Regulators 0x40039000 0x0 0xffc registers CONTROL Control 0x0 0x80000000 0xFFFFFFFF LDOIBIAS LDO Bias Current Selection. 1 1 HIGHBIAS Select high bias. 0 LOWBIAS Select low bias (AHB frequency <= 2.5 MHz). 1 LDOAEN LDO Analog Enable. 31 1 DISABLE LDO0 analog output disabled. 0 ENABLE LDO0 analog output enabled. 1 WDTIMER_0 A None WDTIMER_0 0x40030000 0x0 0xffc registers WDTIMER_IRQn 0 CONTROL Module Control 0x0 0x00000002 0xFFFFFFFF EWIEN Early Warning Interrupt Enable. 0 1 DISABLED Disable the early warning interrupt (EWI). 0 ENABLED Enable the early warning interrupt (EWI). 1 DBGMD Watchdog Timer Debug Mode. 1 1 RUN The WDTIMER module will continue to operate while the core is halted in debug mode. 0 HALT A debug breakpoint will cause the WDTIMER module to halt. 1 STATUS Module Status 0x10 0x00000000 0xFFFFFFFF KEYSTS Key Status. 0 1 read-only IDLE No keys have been processed by the interface. 0 READY The attention key has been received and the module is awaiting a command. 1 PRIVSTS Register Access Status. 1 1 read-only READ_ONLY The watchdog timer registers are currently read-only. 0 READ_WRITE A write transaction can be performed on the module registers. 1 EWI Early Warning Interrupt Flag. 2 1 NOT_SET Read: An early warning match did not occur. Write: Clear the early warning interrupt. 0 SET Read: An early warning match occurred and the interrupt is pending. Write: Force a watchdog timer early warning interrupt to occur. 1 RTHF Reset Threshold Flag. 3 1 read-only LT The counter is currently less than the reset threshold (RTH) value. 0 GTE The counter is currently greater than or equal to the reset threshold (RTH) value. 1 UPDSTS Watchdog Timer Threshold Update Status. 4 1 read-only IDLE An update completed or is not pending. The EWTH and RTH fields can be written. 0 UPDATING An update of the threshold register is occurring. The EWTH and RTH fields should not be modified until hardware clears UPDSTS to 0. 1 THRESHOLD Threshold Values 0x20 0xFFFF7FFF 0xFFFFFFFF EWTH Early Warning Threshold. 0 16 RTH Reset Threshold. 16 16 WDTKEY Module Key 0x30 0x00000000 0xFFFFFFFF KEY Watchdog Timer Key. 0 8 write-only ATTN Attention key to start the command sequence. 165 RESET Reset the watchdog timer. 204 DISABLE Disable the watchdog timer. 221 START Start the watchdog timer. 238 WRITE Allow one write access to the module registers. 241 LOCK Lock the module from any other writes until the next system reset. 255