Silicon Labs SLAB EFM32PG22C200F64IM32 EFM32 C Pearl Gecko 64k 8 32 32 read-write 0 4294967295 EMU_S 1 EMU_S Registers 0x40004000 0x00000000 0x00001000 registers EMU 6 EMUDG 29 EMUSE 30 DECBOD No Description 0x010 read-write 0x00000022 0x00000033 DECBODEN DECBOD enable 0 1 read-write DECBODMASK DECBOD Mask 1 1 read-write DECOVMBODEN Over Voltage Monitor enable 4 1 read-write DECOVMBODMASK Over Voltage Monitor Mask 5 1 read-write BOD3SENSE No Description 0x020 read-write 0x00000000 0x00000077 AVDDBODEN AVDD BOD enable 0 1 read-write VDDIO0BODEN VDDIO0 BOD enable 1 1 read-write VDDIO1BODEN VDDIO1 BOD enable 2 1 read-write VREGVDDCMPCTRL No Description 0x03C read-write 0x00000006 0x00000007 VREGINCMPEN VREGVDD comparator enable 0 1 read-write THRESSEL VREGVDD comparator threshold programming 1 2 read-write PD1PARETCTRL No Description 0x040 read-write 0x00000000 0x0000FFFF PD1PARETDIS Disable PD1 Partial Retention 0 16 read-write RETAIN Retain associated registers when in EM2/3 0 NORETAIN Do not retain associcated registers when in EM2/3 1 LOCK No Description 0x060 write-only 0x0000ADE8 0x0000FFFF LOCKKEY Lock Key 0 16 write-only UNLOCK Unlock EMU register 44520 IF No Description 0x064 read-write 0x00000000 0xEB070000 AVDDBOD AVDD BOD Interrupt flag 16 1 read-write IOVDD0BOD VDDIO0 BOD Interrupt flag 17 1 read-write EM23WAKEUP EM23 Wake up Interrupt flag 24 1 read-write VSCALEDONE Vscale done Interrupt flag 25 1 read-write TEMPAVG Temperature Average Interrupt flag 27 1 read-write TEMP Temperature Interrupt flag 29 1 read-write TEMPLOW Temperature low Interrupt flag 30 1 read-write TEMPHIGH Temperature high Interrupt flag 31 1 read-write IEN No Description 0x068 read-write 0x00000000 0xEB070000 AVDDBOD AVDD BOD Interrupt enable 16 1 read-write IOVDD0BOD VDDIO0 BOD Interrupt enable 17 1 read-write EM23WAKEUP EM23 Wake up Interrupt enable 24 1 read-write VSCALEDONE Vscale done Interrupt enable 25 1 read-write TEMPAVG Temperature Interrupt enable 27 1 read-write TEMP Temperature Interrupt enable 29 1 read-write TEMPLOW Temperature low Interrupt enable 30 1 read-write TEMPHIGH Temperature high Interrupt enable 31 1 read-write EM4CTRL No Description 0x06C read-write 0x00000000 0x00000133 EM4ENTRY EM4 entry request 0 2 read-write EM4IORETMODE EM4 IO retention mode 4 2 read-write DISABLE No Retention: Pads enter reset state when entering EM4 0 EM4EXIT Retention through EM4: Pads enter reset state when exiting EM4 1 SWUNLATCH Retention through EM4 and Wakeup: software writes UNLATCH register to remove retention 2 BOD3SENSEEM4WU Set BOD3SENSE as EM4 wakeup 8 1 read-write CMD No Description 0x070 write-only 0x00000000 0x00020E12 EM4UNLATCH EM4 unlatch 1 1 write-only TEMPAVGREQ Temperature Average Request 4 1 write-only EM01VSCALE1 Scale voltage to Vscale1 10 1 write-only EM01VSCALE2 Scale voltage to Vscale2 11 1 write-only RSTCAUSECLR Reset Cause Clear 17 1 write-only CTRL No Description 0x074 read-write 0x00000200 0xE0010309 EM2DBGEN Enable debugging in EM2 0 1 read-write TEMPAVGNUM Averaged Temperature samples num 3 1 read-write N16 16 measurements 0 N64 64 measurements 1 EM23VSCALE EM2/EM3 Vscale 8 2 read-write VSCALE0 VSCALE0. 0.9v 0 VSCALE1 VSCALE1. 1.0v 1 VSCALE2 VSCALE2. 1.1v 2 FLASHPWRUPONDEMAND Enable flash on demand wakeup 16 1 read-write EFPDIRECTMODEEN EFP Direct Mode Enable 29 1 read-write EFPDRVDECOUPLE EFP drives DECOUPLE 30 1 read-write EFPDRVDVDD EFP drives DVDD 31 1 read-write TEMPLIMITS No Description 0x078 read-write 0x01FF0000 0x01FF01FF TEMPLOW Temp Low limit 0 9 read-write TEMPHIGH Temp High limit 16 9 read-write STATUS No Description 0x084 read-only 0x00000080 0xFF0054FF LOCK Lock status 0 1 read-only UNLOCKED All EMU lockable registers are unlocked. 0 LOCKED All EMU lockable registers are locked. 1 FIRSTTEMPDONE First Temp done 1 1 read-only TEMPACTIVE Temp active 2 1 read-only TEMPAVGACTIVE Temp Average active 3 1 read-only VSCALEBUSY Vscale busy 4 1 read-only VSCALEFAILED Vscale failed 5 1 read-only VSCALE Vscale status 6 2 read-only VSCALE0 Voltage scaling set to 0.9v 0 VSCALE1 Voltage scaling set to 1.0v 1 VSCALE2 Voltage scaling set to 1.1v 2 EM4IORET EM4 IO retention status 12 1 read-only EM2ENTERED EM2 entered 14 1 read-only TEMP No Description 0x088 read-only 0x00000000 0x07FF07FF TEMPLSB Temperature measured decimal part 0 2 read-only TEMP Temperature measured 2 9 read-only TEMPAVG Averaged Temperature 16 11 read-only RSTCTRL No Description 0x090 read-write 0x40010407 0xC001C5CF WDOG0RMODE Enable WDOG0 reset 0 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset except some EMU registers 1 SYSRMODE Enable M33 System reset 2 1 read-write DISABLED Reset request is blocked 0 ENABLED Device is reset except some EMU registers 1 LOCKUPRMODE Enable M33 Lockup reset 3 1 read-write DISABLED Reset Request is Block 0 ENABLED The entire device is reset except some EMU registers 1 AVDDBODRMODE Enable AVDD BOD reset 6 1 read-write DISABLED Reset Request is block 0 ENABLED The entire device is reset except some EMU registers 1 IOVDD0BODRMODE Enable VDDIO0 BOD reset 7 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset except some EMU registers 1 DECBODRMODE Enable DECBOD reset 10 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset 1 DCIRMODE DCI System reset 16 1 read-write DISABLED Reset request blocked 0 ENABLED The entire device is reset except some EMU registers 1 RSTCAUSE No Description 0x094 read-only 0x00000000 0x8001FFFF POR Power On Reset 0 1 read-only PIN Pin Reset 1 1 read-only EM4 EM4 Wakeup Reset 2 1 read-only WDOG0 Watchdog 0 Reset 3 1 read-only LOCKUP M33 Core Lockup Reset 5 1 read-only SYSREQ M33 Core Sys Reset 6 1 read-only DVDDBOD HVBOD Reset 7 1 read-only DVDDLEBOD LEBOD Reset 8 1 read-only DECBOD LVBOD Reset 9 1 read-only AVDDBOD LEBOD1 Reset 10 1 read-only IOVDD0BOD LEBOD2 Reset 11 1 read-only DCI DCI reset 16 1 read-only VREGIN DCDC VREGIN comparator 31 1 read-only DGIF No Description 0x0A0 read-write 0x00000000 0xE1000000 EM23WAKEUPDGIF EM23 Wake up Interrupt flag 24 1 read-write TEMPDGIF Temperature Interrupt flag 29 1 read-write TEMPLOWDGIF Temperature low Interrupt flag 30 1 read-write TEMPHIGHDGIF Temperature high Interrupt flag 31 1 read-write DGIEN No Description 0x0A4 read-write 0x00000000 0xE1000000 EM23WAKEUPDGIEN EM23 Wake up Interrupt enable 24 1 read-write TEMPDGIEN Temperature Interrupt enable 29 1 read-write TEMPLOWDGIEN Temperature low Interrupt enable 30 1 read-write TEMPHIGHDGIEN Temperature high Interrupt enable 31 1 read-write EFPIF No Description 0x100 read-write 0x00000000 0x00000001 EFPIF EFP Interrupt Flag 0 1 read-write EFPIEN No Description 0x104 read-write 0x00000000 0x00000001 EFPIEN EFP Interrupt enable 0 1 read-write CMU_S 1 CMU_S Registers 0x40008000 0x00000000 0x00001000 registers CMU 46 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only STATUS No Description 0x008 read-only 0x00000000 0xC0030001 CALRDY Calibration Ready 0 1 read-only WDOGLOCK Configuration Lock Status for WDOG 30 1 read-only UNLOCKED WDOG configuration lock is unlocked 0 LOCKED WDOG configuration lock is locked 1 LOCK Configuration Lock Status 31 1 read-only UNLOCKED Configuration lock is unlocked 0 LOCKED Configuration lock is locked 1 LOCK No Description 0x010 write-only 0x000093F7 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write this value to unlock 37879 WDOGLOCK No Description 0x014 write-only 0x00005257 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write this value to unlock 37879 IF No Description 0x020 read-write 0x00000000 0x00000003 CALRDY Calibration Ready Interrupt Flag 0 1 read-write CALOF Calibration Overflow Interrupt Flag 1 1 read-write IEN No Description 0x024 read-write 0x00000000 0x00000003 CALRDY Calibration Ready Interrupt Enable 0 1 read-write CALOF Calibration Overflow Interrupt Enable 1 1 read-write CALCMD No Description 0x050 write-only 0x00000000 0x00000003 CALSTART Calibration Start 0 1 write-only CALSTOP Calibration Stop 1 1 write-only CALCTRL No Description 0x054 read-write 0x00000000 0xFF8FFFFF CALTOP Calibration Counter Top Value 0 20 read-write CONT Continuous Calibration 23 1 read-write UPSEL Calibration Up-counter Select 24 4 read-write DISABLED Up-counter is not clocked 0 PRS PRS CMU_CALUP consumer is clocking up-counter 1 HFXO HFXO is clocking up-counter 2 LFXO LFXO is clocking up-counter 3 HFRCODPLL HFRCODPLL is clocking up-counter 4 FSRCO FSRCO is clocking up-counter 8 LFRCO LFRCO is clocking up-counter 9 ULFRCO ULFRCO is clocking up-counter 10 DOWNSEL Calibration Down-counter Select 28 4 read-write DISABLED Down-counter is not clocked 0 HCLK HCLK is clocking down-counter 1 PRS PRS CMU_CALDN consumer is clocking down-counter 2 HFXO HFXO is clocking down-counter 3 LFXO LFXO is clocking down-counter 4 HFRCODPLL HFRCODPLL is clocking down-counter 5 FSRCO FSRCO is clocking down-counter 9 LFRCO LFRCO is clocking down-counter 10 ULFRCO ULFRCO is clocking down-counter 11 CALCNT No Description 0x058 read-only 0x00000000 0x000FFFFF CALCNT Calibration Result Counter Value 0 20 read-only CLKEN0 No Description 0x064 read-write 0x00000000 0xFFFFFFFF LDMA Enable Bus Clock 0 1 read-write LDMAXBAR Enable Bus Clock 1 1 read-write GPCRC Enable Bus Clock 3 1 read-write TIMER0 Enable Bus Clock 4 1 read-write TIMER1 Enable Bus Clock 5 1 read-write TIMER2 Enable Bus Clock 6 1 read-write TIMER3 Enable Bus Clock 7 1 read-write USART0 Enable Bus Clock 8 1 read-write USART1 Enable Bus Clock 9 1 read-write IADC0 Enable Bus Clock 10 1 read-write AMUXCP0 Enable Bus Clock 11 1 read-write LETIMER0 Enable Bus Clock 12 1 read-write WDOG0 Enable Bus Clock 13 1 read-write I2C0 Enable Bus Clock 14 1 read-write I2C1 Enable Bus Clock 15 1 read-write SYSCFG Enable Bus Clock 16 1 read-write DPLL0 Enable Bus Clock 17 1 read-write HFRCO0 Enable Bus Clock 18 1 read-write HFXO0 Enable Bus Clock 19 1 read-write FSRCO Enable Bus Clock 20 1 read-write LFRCO Enable Bus Clock 21 1 read-write LFXO Enable Bus Clock 22 1 read-write ULFRCO Enable Bus Clock 23 1 read-write EUART0 Enable Bus Clock 24 1 read-write PDM Enable Bus Clock 25 1 read-write GPIO Enable Bus Clock 26 1 read-write PRS Enable Bus Clock 27 1 read-write BURAM Enable Bus Clock 28 1 read-write BURTC Enable Bus Clock 29 1 read-write RTCC Enable Bus Clock 30 1 read-write DCDC Enable Bus Clock 31 1 read-write CLKEN1 No Description 0x068 read-write 0x00000000 0x0007FFFF CRYPTOACC Enable Bus Clock 13 1 read-write SMU Enable Bus Clock 15 1 read-write ICACHE0 Enable Bus Clock 16 1 read-write MSC Enable Bus Clock 17 1 read-write TIMER4 Enable Bus Clock 18 1 read-write SYSCLKCTRL No Description 0x070 read-write 0x00000001 0x0001F507 CLKSEL Clock Select 0 3 read-write FSRCO FSRCO is clocking SYSCLK 1 HFRCODPLL HFRCODPLL is clocking SYSCLK 2 HFXO HFXO is clocking SYSCLK 3 CLKIN0 CLKIN0 is clocking SYSCLK 4 PCLKPRESC PCLK Prescaler 10 1 read-write DIV1 PCLK is HCLK divided by 1 0 DIV2 PCLK is HCLK divided by 2 1 HCLKPRESC HCLK Prescaler 12 4 read-write DIV1 HCLK is SYSCLK divided by 1 0 DIV2 HCLK is SYSCLK divided by 2 1 DIV4 HCLK is SYSCLK divided by 4 3 DIV8 HCLK is SYSCLK divided by 8 7 DIV16 HCLK is SYSCLK divided by 16 15 TRACECLKCTRL No Description 0x080 read-write 0x00000000 0x00000030 PRESC TRACECLK Prescaler 4 2 read-write DIV1 TRACECLK is SYSCLK divided by 1 0 DIV2 TRACECLK is SYSCLK divided by 2 1 DIV4 TRACECLK is SYSCLK divided by 4 3 EXPORTCLKCTRL No Description 0x090 read-write 0x00000000 0x1F0F0F0F CLKOUTSEL0 Clock Output Select 0 0 4 read-write DISABLED CLKOUT0 is not clocked 0 HCLK HCLK is clocking CLKOUT0 1 HFEXPCLK EXPORTCLK is clocking CLKOUT0 2 ULFRCO ULFRCO is clocking CLKOUT0 3 LFRCO LFRCO is clocking CLKOUT0 4 LFXO LFXO is clocking CLKOUT0 5 HFRCODPLL HFRCODPLL is clocking CLKOUT0 6 HFXO HFXO is clocking CLKOUT0 7 FSRCO FSRCO is clocking CLKOUT0 8 CLKOUTSEL1 Clock Output Select 1 8 4 read-write DISABLED CLKOUT1 is not clocked 0 HCLK HCLK is clocking CLKOUT1 1 HFEXPCLK EXPORTCLK is clocking CLKOUT1 2 ULFRCO ULFRCO is clocking CLKOUT1 3 LFRCO LFRCO is clocking CLKOUT1 4 LFXO LFXO is clocking CLKOUT1 5 HFRCODPLL HFRCODPLL is clocking CLKOUT1 6 HFXO HFXO is clocking CLKOUT1 7 FSRCO FSRCO is clocking CLKOUT1 8 CLKOUTSEL2 Clock Output Select 2 16 4 read-write DISABLED CLKOUT2 is not clocked 0 HCLK HCLK is clocking CLKOUT2 1 HFEXPCLK EXPORTCLK is clocking CLKOUT2 2 ULFRCO ULFRCO is clocking CLKOUT2 3 LFRCO LFRCO is clocking CLKOUT2 4 LFXO LFXO is clocking CLKOUT2 5 HFRCODPLL HFRCODPLL is clocking CLKOUT2 6 HFXO HFXO is clocking CLKOUT2 7 FSRCO FSRCO is clocking CLKOUT2 8 PRESC EXPORTCLK Prescaler 24 5 read-write DPLLREFCLKCTRL No Description 0x100 read-write 0x00000000 0x00000003 CLKSEL Clock Select 0 2 read-write DISABLED DPLLREFCLK is not clocked 0 HFXO HFXO is clocking DPLLREFCLK 1 LFXO LFXO is clocking DPLLREFCLK 2 CLKIN0 CLKIN0 is clocking DPLLREFCLK 3 EM01GRPACLKCTRL No Description 0x120 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write HFRCODPLL HFRCODPLL is clocking EM01GRPACLK 1 HFXO HFXO is clocking EM01GRPACLK 2 FSRCO FSRCO is clocking EM01GRPACLK 3 EM01GRPBCLKCTRL No Description 0x124 read-write 0x00000001 0x00000007 CLKSEL Clock Select 0 3 read-write HFRCODPLL HFRCODPLL is clocking EM01GRPBCLK 1 HFXO HFXO is clocking EM01GRPBCLK 2 FSRCO FSRCO is clocking EM01GRPBCLK 3 CLKIN0 CLKIN0 is clocking EM01GRPBCLK 4 HFRCODPLLRT HFRCODPLL (re-timed) is clocking EM01GRPBCLK 5 HFXORT HFXO (re-timed) is clocking EM01GRPBCLK 6 EM23GRPACLKCTRL No Description 0x140 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking EM23GRPACLK 1 LFXO LFXO is clocking EM23GRPACLK 2 ULFRCO ULFRCO is clocking EM23GRPACLK 3 EM4GRPACLKCTRL No Description 0x160 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking EM4GRPACLK 1 LFXO LFXO is clocking EM4GRPACLK 2 ULFRCO ULFRCO is clocking EM4GRPACLK 3 IADCCLKCTRL No Description 0x180 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write EM01GRPACLK EM01GRPACLK is clocking IADCCLK 1 FSRCO FSRCO is clocking IADCCLK 2 WDOG0CLKCTRL No Description 0x200 read-write 0x00000001 0x00000007 CLKSEL Clock Select 0 3 read-write LFRCO LFRCO is clocking WDOG0CLK 1 LFXO LFXO is clocking WDOG0CLK 2 ULFRCO ULFRCO is clocking WDOG0CLK 3 HCLKDIV1024 HCLKDIV1024 is clocking WDOG0CLK 4 EUART0CLKCTRL No Description 0x220 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write DISABLED UART is not clocked 0 EM01GRPACLK EM01GRPACLK is clocking UART 1 EM23GRPACLK EM23GRPACLK is clocking UART 2 RTCCCLKCTRL No Description 0x240 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking RTCCCLK 1 LFXO LFXO is clocking RTCCCLK 2 ULFRCO ULFRCO is clocking RTCCCLK 3 CRYPTOACCCLKCTRL No Description 0x260 read-write 0x00000000 0x00000003 PKEN PK Enable 0 1 read-write AESEN AES Enable 1 1 read-write HFXO0_S 2 HFXO0_S Registers 0x4000C000 0x00000000 0x00001000 registers HFXO0 44 IPVERSION No Description 0x000 read-only 0x00000002 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only XTALCFG No Description 0x010 read-write 0x044334CB 0x0FFFFFFF COREBIASSTARTUPI Intermediate Startup Core Bias Current 0 6 read-write COREBIASSTARTUP Startup Core Bias Current 6 6 read-write CTUNEXISTARTUP Startup Tuning Capacitance on XI 12 4 read-write CTUNEXOSTARTUP Startup Tuning Capacitance on XO 16 4 read-write TIMEOUTSTEADY Steady State Timeout 20 4 read-write T16US The steady state timeout is set to 16 us minimum. The maximum can be +40%. 0 T41US The steady state timeout is set to 41 us minimum. The maximum can be +40%. 1 T83US The steady state timeout is set to 83 us minimum. The maximum can be +40%. 2 T125US The steady state timeout is set to 125 us minimum. The maximum can be +40%. 3 T166US The steady state timeout is set to 166 us minimum. The maximum can be +40%. 4 T208US The steady state timeout is set to 208 us minimum. The maximum can be +40%. 5 T250US The steady state timeout is set to 250 us minimum. The maximum can be +40%. 6 T333US The steady state timeout is set to 333 us minimum. The maximum can be +40%. 7 T416US The steady state timeout is set to 416 us minimum. The maximum can be +40%. 8 T500US The steady state timeout is set to 500 us minimum. The maximum can be +40%. 9 T666US The steady state timeout is set to 666 us minimum. The maximum can be +40%. 10 T833US The steady state timeout is set to 833 us minimum. The maximum can be +40%. 11 T1666US The steady state timeout is set to 1666 us minimum. The maximum can be +40%. 12 T2500US The steady state timeout is set to 2500 us minimum. The maximum can be +40%. 13 T4166US The steady state timeout is set to 4166 us minimum. The maximum can be +40%. 14 T7500US The steady state timeout is set to 7500 us minimum. The maximum can be +40%. 15 TIMEOUTCBLSB Core Bias LSB Change Timeout 24 4 read-write T8US The core bias LSB change timeout is set to 8 us minimum. The maximum can be +40%. 0 T20US The core bias LSB change timeout is set to 20 us minimum. The maximum can be +40%. 1 T41US The core bias LSB change timeout is set to 41 us minimum. The maximum can be +40%. 2 T62US The core bias LSB change timeout is set to 62 us minimum. The maximum can be +40%. 3 T83US The core bias LSB change timeout is set to 83 us minimum. The maximum can be +40%. 4 T104US The core bias LSB change timeout is set to 104 us minimum. The maximum can be +40%. 5 T125US The core bias LSB change timeout is set to 125 us minimum. The maximum can be +40%. 6 T166US The core bias LSB change timeout is set to 166 us minimum. The maximum can be +40%. 7 T208US The core bias LSB change timeout is set to 208 us minimum. The maximum can be +40%. 8 T250US The core bias LSB change timeout is set to 250 us minimum. The maximum can be +40%. 9 T333US The core bias LSB change timeout is set to 333 us minimum. The maximum can be +40%. 10 T416US The core bias LSB change timeout is set to 416 us minimum. The maximum can be +40%. 11 T833US The core bias LSB change timeout is set to 833 us minimum. The maximum can be +40%. 12 T1250US The core bias LSB change timeout is set to 1250 us minimum. The maximum can be +40%. 13 T2083US The core bias LSB change timeout is set to 2083 us minimum. The maximum can be +40%. 14 T3750US The core bias LSB change timeout is set to 3750 us minimum. The maximum can be +40%. 15 XTALCTRL No Description 0x018 read-write 0x0F8C8C10 0x8FFFFFFF COREBIASANA Core Bias Current 0 8 read-write CTUNEXIANA Tuning Capacitance on XI 8 8 read-write CTUNEXOANA Tuning Capacitance on XO 16 8 read-write CTUNEFIXANA Fixed Tuning Capacitance 24 2 read-write NONE Remove fixed capacitance on XI and XO nodes 0 XI Adds fixed capacitance on XI node 1 XO Adds fixed capacitance on XO node 2 BOTH Adds fixed capacitance on both XI and XO nodes 3 COREDGENANA Core Degeneration 26 2 read-write NONE Do not apply core degeneration resistence 0 DGEN33 Apply 33 ohm core degeneration resistence 1 DGEN50 Apply 50 ohm core degeneration resistence 2 DGEN100 Apply 100 ohm core degeneration resistence 3 SKIPCOREBIASOPT Skip Core Bias Optimization 31 1 read-write CFG No Description 0x020 read-write 0x10000000 0xF000000D MODE Crystal Oscillator Mode 0 1 read-write XTAL crystal oscillator 0 EXTCLK external sinusoidal clock can be supplied on XI pin. 1 ENXIDCBIASANA Enable XI Internal DC Bias 2 1 read-write SQBUFSCHTRGANA Squaring Buffer Schmitt Trigger 3 1 read-write DISABLE Squaring buffer schmitt trigger is disabled 0 ENABLE Squaring buffer schmitt trigger is enabled 1 CTRL No Description 0x028 read-write 0x00000002 0x80000037 FORCEEN Force Enable 0 1 read-write DISONDEMAND Disable On-demand Mode 1 1 read-write KEEPWARM Keep Warm 2 1 read-write FORCEXI2GNDANA Force XI Pin to Ground 4 1 read-write DISABLE Disabled (not pulled) 0 ENABLE Enabled (pulled) 1 FORCEXO2GNDANA Force XO Pin to Ground 5 1 read-write DISABLE Disabled (not pulled) 0 ENABLE Enabled (pulled) 1 CMD No Description 0x050 write-only 0x00000000 0x00000003 COREBIASOPT Core Bias Optimizaton 0 1 write-only MANUALOVERRIDE Manual Override 1 1 write-only STATUS No Description 0x058 read-only 0x00000000 0xC00F0003 RDY Ready Status 0 1 read-only COREBIASOPTRDY Core Bias Optimization Ready 1 1 read-only ENS Enabled Status 16 1 read-only HWREQ Oscillator Requested by Hardware 17 1 read-only ISWARM Oscillator Is Kept Warm 19 1 read-only FSMLOCK FSM Lock Status 30 1 read-only UNLOCKED FSM lock is unlocked 0 LOCKED FSM lock is locked 1 LOCK Configuration Lock Status 31 1 read-only UNLOCKED Configuration lock is unlocked 0 LOCKED Configuration lock is locked 1 IF No Description 0x070 read-write 0x00000000 0xE0000003 RDY Ready Interrupt 0 1 read-write COREBIASOPTRDY Core Bias Optimization Ready Interrupt 1 1 read-write DNSERR Did Not Start Error Interrupt 29 1 read-write COREBIASOPTERR Core Bias Optimization Error Interrupt 31 1 read-write IEN No Description 0x074 read-write 0x00000000 0xE0000003 RDY Ready Interrupt 0 1 read-write COREBIASOPTRDY Core Bias Optimization Ready Interrupt 1 1 read-write DNSERR Did Not Start Error Interrupt 29 1 read-write COREBIASOPTERR Core Bias Optimization Error Interrupt 31 1 read-write LOCK No Description 0x080 write-only 0x0000580E 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write this value to unlock 22542 HFRCO0_S 1 HFRCO0_S Registers 0x40010000 0x00000000 0x00001000 registers HFRCO0 45 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only CTRL No Description 0x004 read-write 0x00000000 0x00000003 FORCEEN Force Enable 0 1 read-write DISONDEMAND Disable On-demand 1 1 read-write CAL No Description 0x008 read-write 0xA8689F7F 0xFFFFBF7F TUNING Tuning Value 0 7 read-write FINETUNING Fine Tuning Value 8 6 read-write LDOHP LDO High Power Mode 15 1 read-write FREQRANGE Frequency Range 16 5 read-write CMPBIAS Comparator Bias Current 21 3 read-write CLKDIV Locally Divide HFRCO Clock Output 24 2 read-write DIV1 Divide by 1. 0 DIV2 Divide by 2. 1 DIV4 Divide by 4. 2 CMPSEL Comparator Load Select 26 2 read-write IREFTC Tempco Trim on Comparator Current 28 4 read-write STATUS No Description 0x00C read-only 0x00000000 0x80010007 RDY Ready 0 1 read-only FREQBSY Frequency Updating Busy 1 1 read-only SYNCBUSY Synchronization Busy 2 1 read-only ENS Enable Status 16 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED HFRCO is unlocked 0 LOCKED HFRCO is locked 1 IF No Description 0x010 read-write 0x00000000 0x00000001 RDY Ready Interrupt Flag 0 1 read-write IEN No Description 0x014 read-write 0x00000000 0x00000001 RDY RDY Interrupt Enable 0 1 read-write LOCK No Description 0x01C write-only 0x00008195 0x0000FFFF LOCKKEY Lock Key 0 16 write-only UNLOCK Unlock code 33173 FSRCO_S 0 FSRCO_S Registers 0x40018000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version 0 32 read-only DPLL0_S 0 DPLL0_S Registers 0x4001C000 0x00000000 0x00001000 registers DPLL0 50 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Module Enable 0 1 read-write CFG No Description 0x008 read-write 0x00000000 0x00000047 MODE Operating Mode Control 0 1 read-write FLL Frequency Lock Mode 0 PLL Phase Lock Mode 1 EDGESEL Reference Edge Select 1 1 read-write AUTORECOVER Automatic Recovery Control 2 1 read-write DITHEN Dither Enable Control 6 1 read-write CFG1 No Description 0x00C read-write 0x00000000 0x0FFF0FFF M Factor M 0 12 read-write N Factor N 16 12 read-write IF No Description 0x010 read-write 0x00000000 0x00000007 LOCK Lock Interrupt Flag 0 1 read-write LOCKFAILLOW Lock Failure Low Interrupt Flag 1 1 read-write LOCKFAILHIGH Lock Failure High Interrupt Flag 2 1 read-write IEN No Description 0x014 read-write 0x00000000 0x00000007 LOCK LOCK interrupt Enable 0 1 read-write LOCKFAILLOW LOCKFAILLOW Interrupe Enable 1 1 read-write LOCKFAILHIGH LOCKFAILHIGH Interrupt Enable 2 1 read-write STATUS No Description 0x018 read-only 0x00000000 0x80000003 RDY Ready Status 0 1 read-only ENS Enable Status 1 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED 0 LOCKED 1 LOCK No Description 0x024 write-only 0x00007102 0x0000FFFF LOCKKEY Lock Key 0 16 write-only UNLOCK 28930 LFXO_S 0 LFXO_S Registers 0x40020000 0x00000000 0x00001000 registers LFXO 22 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CTRL No Description 0x004 read-write 0x00000002 0x00000033 FORCEEN LFXO Force Enable 0 1 read-write DISONDEMAND LFXO Disable On-demand requests 1 1 read-write FAILDETEN LFXO Failure Detection Enable 4 1 read-write FAILDETEM4WUEN LFXO Failure Detection EM4WU Enable 5 1 read-write CFG Do not write to this register unless the oscillator is forced off. The oscillator is forced off if DISONDEMAND is set and FORCEEN is cleared. 0x008 read-write 0x00000701 0x00000733 AGC LFXO AGC Enable 0 1 read-write HIGHAMPL LFXO High Amplitude Enable 1 1 read-write MODE LFXO Mode 4 2 read-write XTAL A 32768Hz crystal should be connected to the LF crystal pads. Voltage must not exceed VDDIO. 0 BUFEXTCLK An external sine source with minimum amplitude 100mv (zero-to-peak) and maximum amplitude 500mV (zero-to-peak) should be connected in series with LFXTAL_I pin. Minimum voltage should be larger than ground and maximum voltage smaller than VDDIO. The sine source does not need to be ac coupled externally as it is ac couples inside LFXO. LFXTAL_O is free to be used as a general purpose GPIO. 1 DIGEXTCLK An external 32KHz CMOS clock should be provided on LFXTAL_I. LFXTAL_O is free to be used as a general purpose GPIO. 2 TIMEOUT LFXO Start-up Delay 8 3 read-write CYCLES2 Timeout period of 2 cycles 0 CYCLES256 Timeout period of 256 cycles 1 CYCLES1K Timeout period of 1024 cycles 2 CYCLES2K Timeout period of 2048 cycles 3 CYCLES4K Timeout period of 4096 cycles 4 CYCLES8K Timeout period of 8192 cycles 5 CYCLES16K Timeout period of 16384 cycles 6 CYCLES32K Timeout period of 32768 cycles 7 STATUS No Description 0x010 read-only 0x00000000 0x80010001 RDY LFXO Ready Status 0 1 read-only ENS LFXO Enable Status 16 1 read-only LOCK LFXO Locked Status 31 1 read-only UNLOCKED LFXO lockable registers are not locked 0 LOCKED LFXO lockable registers are locked 1 CAL Do not write to this register unless CALBSY in SYNCBUSY register is low. 0x014 read-write 0x00000200 0x0000037F CAPTUNE Internal Capacitance Tuning 0 7 read-write GAIN LFXO Startup Gain 8 2 read-write IF No Description 0x018 read-write 0x00000000 0x0000000F RDY LFXO Ready Interrupt Flag 0 1 read-write POSEDGE Rising Edge Interrupt Flag 1 1 read-write NEGEDGE Falling Edge Interrupt Flag 2 1 read-write FAIL LFXO Failure Interrupt Flag 3 1 read-write IEN No Description 0x01C read-write 0x00000000 0x0000000F RDY LFXO Ready Interrupt Enable 0 1 read-write POSEDGE Rising Edge Interrupt Enable 1 1 read-write NEGEDGE Falling Edge Interrupt Enable 2 1 read-write FAIL LFXO Failure Interrupt Enable 3 1 read-write SYNCBUSY No Description 0x020 read-only 0x00000000 0x00000001 CAL LFXO Synchronization status 0 1 read-only LOCK No Description 0x024 write-only 0x00001A20 0x0000FFFF LOCKKEY Lock Key 0 16 write-only UNLOCK Unlock LFXO lockable registers 6688 LFRCO_S 1 LFRCO_S Registers 0x40024000 0x00000000 0x00001000 registers LFRCO 23 IPVERSION Contains the LFRCO ip version 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only CTRL Control register 0x004 read-write 0x00000000 0x00000003 FORCEEN Force Enable 0 1 read-write DISONDEMAND Disable On-Demand 1 1 read-write STATUS Status register 0x008 read-only 0x00000000 0x80010001 RDY Ready Status 0 1 read-only ENS Enabled Status 16 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED Access to configuration registers not locked 0 LOCKED Access to configuration registers locked 1 IF Interrupt flag register 0x014 read-write 0x00000000 0x00070707 RDY Ready Flag 0 1 read-write POSEDGE Rising Edge Flag 1 1 read-write NEGEDGE Falling Edge Flag 2 1 read-write TCDONE Temperature Check Done Flag 8 1 read-write CALDONE Calibration Done Flag 9 1 read-write TEMPCHANGE Temperature Change Flag 10 1 read-write SCHEDERR Scheduling Error Flag 16 1 read-write TCOOR Temperature Check Out Of Range Flag 17 1 read-write CALOOR Calibration Out Of Range Flag 18 1 read-write IEN Interrupt enable register 0x018 read-write 0x00000000 0x00070707 RDY Ready Enable 0 1 read-write POSEDGE Rising Edge Enable 1 1 read-write NEGEDGE Falling Edge Enable 2 1 read-write TCDONE Temperature Check Done Enable 8 1 read-write CALDONE Calibration Done Enable 9 1 read-write TEMPCHANGE Temperature Change Enable 10 1 read-write SCHEDERR Scheduling Error Enable 16 1 read-write TCOOR Temperature Check Out Of Range Enable 17 1 read-write CALOOR Calibration Out Of Range Enable 18 1 read-write LOCK Configuration lock register. Locks and unlocks access to configuration registers. 0x020 write-only 0x00000000 0x0000FFFF LOCKKEY Lock Key 0 16 write-only LOCK Lock Configuration Registers 0 UNLOCK Unlock Configuration Registers 3987 CFG Configuration register 0x024 read-write 0x00000000 0x00000001 HIGHPRECEN High Precision Enable 0 1 read-write NOMCAL Nominal calibration register 0x02C read-write 0x0005B8D8 0x001FFFFF NOMCALCNT Nominal Calibration Count 0 21 read-write NOMCALINV Nominal calibration inverted register 0x030 read-write 0x0000597A 0x0001FFFF NOMCALCNTINV Nominal Calibration Count Inverted 0 17 read-write CMD Command register 0x034 write-only 0x00000000 0x00000001 REDUCETCINT Reduce Temperature Check Interval 0 1 write-only ULFRCO_S 0 ULFRCO_S Registers 0x40028000 0x00000000 0x00001000 registers ULFRCO 24 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION ULFRCO IP version 0 32 read-only STATUS No Description 0x008 read-only 0x00000000 0x00010001 RDY Ready Status 0 1 read-only ENS Enable Status 16 1 read-only IF No Description 0x014 read-write 0x00000000 0x00000007 RDY Ready Interrupt Flag 0 1 read-write POSEDGE Positive Edge Interrupt Flag 1 1 read-write NEGEDGE Negative Edge Interrupt Flag 2 1 read-write IEN No Description 0x018 read-write 0x00000000 0x00000007 RDY Enable Ready Interrupt 0 1 read-write POSEDGE Enable Positive Edge Interrupt 1 1 read-write NEGEDGE Enable Negative Edge Interrupt 2 1 read-write MSC_S 1 MSC_S Registers 0x40030000 0x00000000 0x00001000 registers MSC 49 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only READCTRL No Description 0x008 read-write 0x00200000 0x00301002 DOUTBUFEN Flash dout pipeline buffer enable 12 1 read-write MODE Read Mode 20 2 read-write WS0 Zero wait-states inserted in fetch or read transfers 0 WS1 One wait-state inserted for each fetch or read transfer 1 WS2 Two wait-states inserted for eatch fetch or read transfer 2 WS3 Three wait-states inserted for eatch fetch or read transfer 3 WRITECTRL No Description 0x00C read-write 0x00000000 0x0000000B WREN Enable Write/Erase Controller 0 1 read-write IRQERASEABORT Abort Page Erase on Interrupt 1 1 read-write LPWRITE Low-Power Erase 3 1 read-write WRITECMD No Description 0x010 write-only 0x00000000 0x00001126 ERASEPAGE Erase Page 1 1 write-only WRITEEND End Write Mode 2 1 write-only ERASEABORT Abort erase sequence 5 1 write-only ERASEMAIN0 Mass erase region 0 8 1 write-only CLEARWDATA Clear WDATA state 12 1 write-only ADDRB No Description 0x014 read-write 0x00000000 0xFFFFFFFF ADDRB Page Erase or Write Address Buffer 0 32 read-write WDATA No Description 0x018 read-write 0x00000000 0xFFFFFFFF DATAW Write Data 0 32 read-write STATUS No Description 0x01C read-only 0x08000008 0xF901007F BUSY Erase/Write Busy 0 1 read-only LOCKED Access Locked 1 1 read-only INVADDR Invalid Write Address or Erase Page 2 1 read-only WDATAREADY WDATA Write Ready 3 1 read-only ERASEABORTED Erase Operation Aborted 4 1 read-only PENDING Write Command In Queue 5 1 read-only TIMEOUT Write Command Timeout 6 1 read-only REGLOCK Register Lock Status 16 1 read-only UNLOCKED Register lock is unlocked 0 LOCKED Register lock is locked. 1 PWRON Flash Power On Status 24 1 read-only WREADY Flash Write Ready 27 1 read-only PWRUPCKBDFAILCOUNT Flash power up checkerboard pattern chec 28 4 read-only IF No Description 0x020 read-write 0x00000000 0x00000307 ERASE Host Erase Done Interrupt Read Flag 0 1 read-write WRITE Host Write Done Interrupt Read Flag 1 1 read-write WDATAOV Host write buffer overflow 2 1 read-write PWRUPF Flash Power Up Sequence Complete Flag 8 1 read-write PWROFF Flash Power Off Sequence Complete Flag 9 1 read-write IEN No Description 0x024 read-write 0x00000000 0x00000307 ERASE Erase Done Interrupt enable 0 1 read-write WRITE Write Done Interrupt enable 1 1 read-write WDATAOV write data buffer overflow irq enable 2 1 read-write PWRUPF Flash Power Up Seq done irq enable 8 1 read-write PWROFF Flash Power Off Seq done irq enable 9 1 read-write USERDATASIZE No Description 0x034 read-only 0x00000004 0x0000003F USERDATASIZE User Data Size 0 6 read-only CMD No Description 0x038 write-only 0x00000000 0x00000011 PWRUP Flash Power Up Command 0 1 write-only PWROFF Flash power off/sleep command 4 1 write-only LOCK No Description 0x03C write-only 0x00000000 0x0000FFFF LOCKKEY Configuration Lock 0 16 write-only LOCK Key to lock the register lock 0 UNLOCK Key to unlock the register lock. 7025 MISCLOCKWORD No Description 0x040 read-write 0x00000011 0x00000011 MELOCKBIT Mass Erase Lock 0 1 read-write UDLOCKBIT User Data Lock 4 1 read-write PWRCTRL No Description 0x050 read-write 0x00100002 0x00FF0013 PWROFFONEM1ENTRY Power down Flash macro when enter EM1 0 1 read-write PWROFFENTRYAGAIN POWER down flash again in EM1/EM1p 4 1 read-write PWROFFDLY Power down delay 16 8 read-write PAGELOCK0 No Description 0x120 read-write 0x00000000 0xFFFFFFFF LOCKBIT page lock bit 0 32 read-write PAGELOCK1 No Description 0x124 read-write 0x00000000 0xFFFFFFFF LOCKBIT page lock bit 0 32 read-write ICACHE0_S 0 ICACHE0_S Registers 0x40034000 0x00000000 0x00001000 registers ICACHE0 17 IPVERSION The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION. 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only CTRL No Description 0x004 read-write 0x00000000 0x00000007 CACHEDIS Cache Disable 0 1 read-write USEMPU Use MPU 1 1 read-write AUTOFLUSHDIS Automatic Flushing Disable 2 1 read-write PCHITS No Description 0x008 read-only 0x00000000 0xFFFFFFFF PCHITS Performance Counter Hits 0 32 read-only PCMISSES No Description 0x00C read-only 0x00000000 0xFFFFFFFF PCMISSES Performance Counter Misses 0 32 read-only PCAHITS No Description 0x010 read-only 0x00000000 0xFFFFFFFF PCAHITS Performance Counter Advanced Hits 0 32 read-only STATUS No Description 0x014 read-only 0x00000000 0x00000001 PCRUNNING PC Running 0 1 read-only CMD No Description 0x018 write-only 0x00000000 0x00000007 FLUSH Flush 0 1 write-only STARTPC Start Performance Counters 1 1 write-only STOPPC Stop Performance Counters 2 1 write-only LPMODE No Description 0x01C read-write 0x00000023 0x000000F3 LPLEVEL Low Power Level 0 2 read-write BASIC Base instruction cache functionality 0 ADVANCED Advanced buffering mode, where the cache uses the fetch pattern to predict highly accessed data and store it in low-energy memory 1 MINACTIVITY Minimum activity mode, which allows the cache to minimize activity in logic that it predicts has a low probability being used. This mode can introduce wait-states into the instruction fetch stream when the cache exits one of its low-activity states. The number of wait-states introduced is small, but users running with 0-wait-state memory and wishing to reduce the variability that the cache might introduce with additional wait-states may wish to lower the cache low-power level. Note, this mode includes the advanced buffering mode functionality. 3 NESTFACTOR Low Power Nest Factor 4 4 read-write IF No Description 0x020 read-write 0x00000000 0x00000107 HITOF Hit Overflow Interrupt Flag 0 1 read-write MISSOF Miss Overflow Interrupt Flag 1 1 read-write AHITOF Advanced Hit Overflow Interrupt Flag 2 1 read-write RAMERROR RAM error Interrupt Flag 8 1 read-write IEN No Description 0x024 read-write 0x00000000 0x00000107 HITOF Hit Overflow Interrupt Enable 0 1 read-write MISSOF Miss Overflow Interrupt Enable 1 1 read-write AHITOF Advanced Hit Overflow Interrupt Enable 2 1 read-write RAMERROR RAM error Interrupt Enable 8 1 read-write PRS_S 1 PRS_S Registers 0x40038000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only ASYNC_SWPULSE No Description 0x008 write-only 0x00000000 0x00000FFF CH0PULSE Channel pulse 0 1 write-only CH1PULSE Channel pulse 1 1 write-only CH2PULSE Channel pulse 2 1 write-only CH3PULSE Channel pulse 3 1 write-only CH4PULSE Channel pulse 4 1 write-only CH5PULSE Channel pulse 5 1 write-only CH6PULSE Channel pulse 6 1 write-only CH7PULSE Channel pulse 7 1 write-only CH8PULSE Channel pulse 8 1 write-only CH9PULSE Channel pulse 9 1 write-only CH10PULSE Channel pulse 10 1 write-only CH11PULSE Channel pulse 11 1 write-only ASYNC_SWLEVEL No Description 0x00C read-write 0x00000000 0x00000FFF CH0LEVEL Channel Level 0 1 read-write CH1LEVEL Channel Level 1 1 read-write CH2LEVEL Channel Level 2 1 read-write CH3LEVEL Channel Level 3 1 read-write CH4LEVEL Channel Level 4 1 read-write CH5LEVEL Channel Level 5 1 read-write CH6LEVEL Channel Level 6 1 read-write CH7LEVEL Channel Level 7 1 read-write CH8LEVEL Channel Level 8 1 read-write CH9LEVEL Channel Level 9 1 read-write CH10LEVEL Channel Level 10 1 read-write CH11LEVEL Channel Level 11 1 read-write ASYNC_PEEK No Description 0x010 read-only 0x00000000 0x00000FFF CH0VAL Channel 0 Current Value 0 1 read-only CH1VAL Channel 1 Current Value 1 1 read-only CH2VAL Channel 2 Current Value 2 1 read-only CH3VAL Channel 3 Current Value 3 1 read-only CH4VAL Channel 4 Current Value 4 1 read-only CH5VAL Channel 5 Current Value 5 1 read-only CH6VAL Channel 6 Current Value 6 1 read-only CH7VAL Channel 7 Current Value 7 1 read-only CH8VAL Channel 8 Current Value 8 1 read-only CH9VAL Channel 9 Current Value 9 1 read-only CH10VAL Channel 10 Current Value 10 1 read-only CH11VAL Channel 11 Current Value 11 1 read-only SYNC_PEEK No Description 0x014 read-only 0x00000000 0x0000000F CH0VAL Channel Value 0 1 read-only CH1VAL Channel Value 1 1 read-only CH2VAL Channel Value 2 1 read-only CH3VAL Channel Value 3 1 read-only ASYNC_CH0_CTRL No Description 0x018 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH1_CTRL No Description 0x01C read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH2_CTRL No Description 0x020 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH3_CTRL No Description 0x024 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH4_CTRL No Description 0x028 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH5_CTRL No Description 0x02C read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH6_CTRL No Description 0x030 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH7_CTRL No Description 0x034 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH8_CTRL No Description 0x038 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH9_CTRL No Description 0x03C read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH10_CTRL No Description 0x040 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH11_CTRL No Description 0x044 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write SYNC_CH0_CTRL No Description 0x048 read-write 0x00000000 0x00007F07 SIGSEL Signal Select 0 3 read-write SOURCESEL Source Select 8 7 read-write SYNC_CH1_CTRL No Description 0x04C read-write 0x00000000 0x00007F07 SIGSEL Signal Select 0 3 read-write SOURCESEL Source Select 8 7 read-write SYNC_CH2_CTRL No Description 0x050 read-write 0x00000000 0x00007F07 SIGSEL Signal Select 0 3 read-write SOURCESEL Source Select 8 7 read-write SYNC_CH3_CTRL No Description 0x054 read-write 0x00000000 0x00007F07 SIGSEL Signal Select 0 3 read-write SOURCESEL Source Select 8 7 read-write CONSUMER_CMU_CALDN CALDN Consumer Register 0x058 read-write 0x00000000 0x0000000F PRSSEL CALDN async channel select 0 4 read-write CONSUMER_CMU_CALUP CALUP Consumer Register 0x05C read-write 0x00000000 0x0000000F PRSSEL CALUP async channel select 0 4 read-write CONSUMER_IADC0_SCANTRIGGER SCAN Consumer Register 0x064 read-write 0x00000000 0x0000030F PRSSEL SCAN async channel select 0 4 read-write SPRSSEL SCAN sync channel select 8 2 read-write CONSUMER_IADC0_SINGLETRIGGER SINGLE Consumer Register 0x068 read-write 0x00000000 0x0000030F PRSSEL SINGLE async channel select 0 4 read-write SPRSSEL SINGLE sync channel select 8 2 read-write CONSUMER_LDMAXBAR_DMAREQ0 DMAREQ0 Consumer Register 0x06C read-write 0x00000000 0x0000000F PRSSEL DMAREQ0 async channel select 0 4 read-write CONSUMER_LDMAXBAR_DMAREQ1 DMAREQ1 Consumer Register 0x070 read-write 0x00000000 0x0000000F PRSSEL DMAREQ1 async channel select 0 4 read-write CONSUMER_LETIMER0_CLEAR CLEAR Consumer Register 0x074 read-write 0x00000000 0x0000000F PRSSEL CLEAR async channel select 0 4 read-write CONSUMER_LETIMER0_START START Consumer Register 0x078 read-write 0x00000000 0x0000000F PRSSEL START async channel select 0 4 read-write CONSUMER_LETIMER0_STOP STOP Consumer Register 0x07C read-write 0x00000000 0x0000000F PRSSEL STOP async channel select 0 4 read-write CONSUMER_EUART0_RX RX Consumer Register 0x080 read-write 0x00000000 0x0000000F PRSSEL RX async channel select 0 4 read-write CONSUMER_EUART0_TRIGGER TRIGGER Consumer Register 0x084 read-write 0x00000000 0x0000000F PRSSEL TRIGGER async channel select 0 4 read-write CONSUMER_RTCC_CC0 CC0 Consumer Register 0x0E8 read-write 0x00000000 0x0000000F PRSSEL CC0 async channel select 0 4 read-write CONSUMER_RTCC_CC1 CC1 Consumer Register 0x0EC read-write 0x00000000 0x0000000F PRSSEL CC1 async channel select 0 4 read-write CONSUMER_RTCC_CC2 CC2 Consumer Register 0x0F0 read-write 0x00000000 0x0000000F PRSSEL CC2 async channel select 0 4 read-write CONSUMER_CORE_CTIIN0 CTI Consumer Register 0x0F8 read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_CORE_CTIIN1 CTI Consumer Register 0x0FC read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_CORE_CTIIN2 CTI Consumer Register 0x100 read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_CORE_CTIIN3 CTI Consumer Register 0x104 read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_CORE_M33RXEV M33 Consumer Register 0x108 read-write 0x00000000 0x0000000F PRSSEL M33 async channel select 0 4 read-write CONSUMER_TIMER0_CC0 CC0 Consumer Register 0x10C read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER0_CC1 CC1 Consumer Register 0x110 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER0_CC2 CC2 Consumer Register 0x114 read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER0_DTI DTI Consumer Register 0x118 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER0_DTIFS1 DTI Consumer Register 0x11C read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER0_DTIFS2 DTI Consumer Register 0x120 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER1_CC0 CC0 Consumer Register 0x124 read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER1_CC1 CC1 Consumer Register 0x128 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER1_CC2 CC2 Consumer Register 0x12C read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER1_DTI DTI Consumer Register 0x130 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER1_DTIFS1 DTI Consumer Register 0x134 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER1_DTIFS2 DTI Consumer Register 0x138 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER2_CC0 CC0 Consumer Register 0x13C read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER2_CC1 CC1 Consumer Register 0x140 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER2_CC2 CC2 Consumer Register 0x144 read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER2_DTI DTI Consumer Register 0x148 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER2_DTIFS1 DTI Consumer Register 0x14C read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER2_DTIFS2 DTI Consumer Register 0x150 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER3_CC0 CC0 Consumer Register 0x154 read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER3_CC1 CC1 Consumer Register 0x158 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER3_CC2 CC2 Consumer Register 0x15C read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER3_DTI DTI Consumer Register 0x160 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER3_DTIFS1 DTI Consumer Register 0x164 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER3_DTIFS2 DTI Consumer Register 0x168 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER4_CC0 CC0 Consumer Register 0x16C read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER4_CC1 CC1 Consumer Register 0x170 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER4_CC2 CC2 Consumer Register 0x174 read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER4_DTI DTI Consumer Register 0x178 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER4_DTIFS1 DTI Consumer Register 0x17C read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER4_DTIFS2 DTI Consumer Register 0x180 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_USART0_CLK CLK Consumer Register 0x184 read-write 0x00000000 0x0000000F PRSSEL CLK async channel select 0 4 read-write CONSUMER_USART0_IR IR Consumer Register 0x188 read-write 0x00000000 0x0000000F PRSSEL IR async channel select 0 4 read-write CONSUMER_USART0_RX RX Consumer Register 0x18C read-write 0x00000000 0x0000000F PRSSEL RX async channel select 0 4 read-write CONSUMER_USART0_TRIGGER TRIGGER Consumer Register 0x190 read-write 0x00000000 0x0000000F PRSSEL TRIGGER async channel select 0 4 read-write CONSUMER_USART1_CLK CLK Consumer Register 0x194 read-write 0x00000000 0x0000000F PRSSEL CLK async channel select 0 4 read-write CONSUMER_USART1_IR IR Consumer Register 0x198 read-write 0x00000000 0x0000000F PRSSEL IR async channel select 0 4 read-write CONSUMER_USART1_RX RX Consumer Register 0x19C read-write 0x00000000 0x0000000F PRSSEL RX async channel select 0 4 read-write CONSUMER_USART1_TRIGGER TRIGGER Consumer Register 0x1A0 read-write 0x00000000 0x0000000F PRSSEL TRIGGER async channel select 0 4 read-write CONSUMER_WDOG0_SRC0 SRC0 Consumer Register 0x1A4 read-write 0x00000000 0x0000000F PRSSEL SRC0 async channel select 0 4 read-write CONSUMER_WDOG0_SRC1 SRC1 Consumer Register 0x1A8 read-write 0x00000000 0x0000000F PRSSEL SRC1 async channel select 0 4 read-write GPIO_S 1 GPIO_S Registers 0x4003C000 0x00000000 0x00001000 registers GPIO_ODD 25 GPIO_EVEN 26 PORTA_CTRL Port control 0x000 read-write 0x00400040 0x10701070 SLEWRATE Slew Rate 4 3 read-write DINDIS Data In Disable 12 1 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write DINDISALT Data In Disable Alt 28 1 read-write PORTA_MODEL mode low 0x004 read-write 0x00000000 0xFFFFFFFF MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE4 MODE n 16 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE5 MODE n 20 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE6 MODE n 24 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE7 MODE n 28 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTA_MODEH mode high 0x00C read-write 0x00000000 0x0000000F MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTA_DOUT data out 0x010 read-write 0x00000000 0x000001FF DOUT Data output 0 9 read-write PORTA_DIN data in 0x014 read-only 0x00000000 0x000001FF DIN Data input 0 9 read-only PORTB_CTRL Port control 0x030 read-write 0x00400040 0x10701070 SLEWRATE Slew Rate 4 3 read-write DINDIS Data In Disable 12 1 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write DINDISALT Data In Disable Alt 28 1 read-write PORTB_MODEL mode low 0x034 read-write 0x00000000 0x000FFFFF MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE4 MODE n 16 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTB_DOUT data out 0x040 read-write 0x00000000 0x0000001F DOUT Data output 0 5 read-write PORTB_DIN data in 0x044 read-only 0x00000000 0x0000001F DIN Data input 0 5 read-only PORTC_CTRL Port control 0x060 read-write 0x00400040 0x10701070 SLEWRATE Slew Rate 4 3 read-write DINDIS Data In Disable 12 1 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write DINDISALT Data In Disable Alt 28 1 read-write PORTC_MODEL mode low 0x064 read-write 0x00000000 0xFFFFFFFF MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE4 MODE n 16 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE5 MODE n 20 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE6 MODE n 24 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE7 MODE n 28 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTC_DOUT data out 0x070 read-write 0x00000000 0x000000FF DOUT Data output 0 8 read-write PORTC_DIN data in 0x074 read-only 0x00000000 0x000000FF DIN Data input 0 8 read-only PORTD_CTRL Port control 0x090 read-write 0x00400040 0x10701070 SLEWRATE Slew Rate 4 3 read-write DINDIS Data In Disable 12 1 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write DINDISALT Data In Disable Alt 28 1 read-write PORTD_MODEL mode low 0x094 read-write 0x00000000 0x0000FFFF MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTD_DOUT data out 0x0A0 read-write 0x00000000 0x0000000F DOUT Data output 0 4 read-write PORTD_DIN data in 0x0A4 read-only 0x00000000 0x0000000F DIN Data input 0 4 read-only LOCK No Description 0x300 write-only 0x0000A534 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Unlock code 42292 GPIOLOCKSTATUS No Description 0x310 read-only 0x00000000 0x00000001 LOCK GPIO LOCK status 0 1 read-only UNLOCKED Registers are unlocked 0 LOCKED Registers are locked 1 ABUSALLOC A Bus allocation 0x320 read-write 0x00000000 0x0F0F0F0F AEVEN0 A Bus Even 0 0 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 AEVEN1 A Bus Even 1 8 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 AODD0 A Bus Odd 0 16 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 AODD1 A Bus Odd 1 24 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 BBUSALLOC B Bus allocation 0x324 read-write 0x00000000 0x0F0F0F0F BEVEN0 B Bus Even 0 0 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 BEVEN1 B Bus Even 1 8 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 BODD0 B Bus Odd 0 16 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 BODD1 B Bus Odd 1 24 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 CDBUSALLOC CD Bus allocation 0x328 read-write 0x00000000 0x0F0F0F0F CDEVEN0 CD Bus Even 0 0 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 CDEVEN1 CD Bus Even 1 8 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 CDODD0 CD Bus Odd 0 16 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 CDODD1 CD Bus Odd 1 24 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 EXTIPSELL External Interrupt Port Select Low 0x400 read-write 0x00000000 0x33333333 EXTIPSEL0 External Interrupt Port Select 0 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL1 External Interrupt Port Select 4 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL2 External Interrupt Port Select 8 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL3 External Interrupt Port Select 12 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL4 External Interrupt Port Select 16 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL5 External Interrupt Port Select 20 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL6 External Interrupt Port Select 24 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL7 External Interrupt Port Select 28 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSELH External interrupt Port Select High 0x404 read-write 0x00000000 0x00003333 EXTIPSEL0 External Interrupt Port Select 0 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL1 External Interrupt Port Select 4 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL2 External Interrupt Port Select 8 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL3 External Interrupt Port Select 12 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPINSELL External Interrupt Pin Select Low 0x408 read-write 0x00000000 0x33333333 EXTIPINSEL0 External Interrupt Pin select 0 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL1 External Interrupt Pin select 4 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL2 External Interrupt Pin select 8 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL3 External Interrupt Pin select 12 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL4 External Interrupt Pin select 16 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL5 External Interrupt Pin select 20 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL6 External Interrupt Pin select 24 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL7 External Interrupt Pin select 28 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSELH External Interrupt Pin Select High 0x40C read-write 0x00000000 0x00003333 EXTIPINSEL0 External Interrupt Pin select 0 2 read-write OFFSET8 OFFSET=8 0 OFFSET9 OFFSET=9 1 OFFSET10 OFFSET=10 2 OFFSET11 OFFSET=11 3 EXTIPINSEL1 External Interrupt Pin select 4 2 read-write OFFSET8 OFFSET=8 0 OFFSET9 OFFSET=9 1 OFFSET10 OFFSET=10 2 OFFSET11 OFFSET=11 3 EXTIPINSEL2 External Interrupt Pin select 8 2 read-write OFFSET8 OFFSET=8 0 OFFSET9 OFFSET=9 1 OFFSET10 OFFSET=10 2 OFFSET11 OFFSET=11 3 EXTIPINSEL3 External Interrupt Pin select 12 2 read-write OFFSET8 OFFSET=8 0 OFFSET9 OFFSET=9 1 OFFSET10 OFFSET=10 2 OFFSET11 OFFSET=11 3 EXTIRISE External Interrupt Rising Edge Trigger 0x410 read-write 0x00000000 0x00000FFF EXTIRISE EXT Int Rise 0 12 read-write EXTIFALL External Interrupt Falling Edge Trigger 0x414 read-write 0x00000000 0x00000FFF EXTIFALL EXT Int FALL 0 12 read-write IF Interrupt Flag 0x420 read-write 0x00000000 0x0FFF0FFF EXTIF0 External Pin Flag 0 1 read-write EXTIF1 External Pin Flag 1 1 read-write EXTIF2 External Pin Flag 2 1 read-write EXTIF3 External Pin Flag 3 1 read-write EXTIF4 External Pin Flag 4 1 read-write EXTIF5 External Pin Flag 5 1 read-write EXTIF6 External Pin Flag 6 1 read-write EXTIF7 External Pin Flag 7 1 read-write EXTIF8 External Pin Flag 8 1 read-write EXTIF9 External Pin Flag 9 1 read-write EXTIF10 External Pin Flag 10 1 read-write EXTIF11 External Pin Flag 11 1 read-write EM4WU EM4 wake up 16 12 read-write IEN Interrupt Enable 0x424 read-write 0x00000000 0x0FFF0FFF EXTIEN0 External Pin Enable 0 1 read-write EXTIEN1 External Pin Enable 1 1 read-write EXTIEN2 External Pin Enable 2 1 read-write EXTIEN3 External Pin Enable 3 1 read-write EXTIEN4 External Pin Enable 4 1 read-write EXTIEN5 External Pin Enable 5 1 read-write EXTIEN6 External Pin Enable 6 1 read-write EXTIEN7 External Pin Enable 7 1 read-write EXTIEN8 External Pin Enable 8 1 read-write EXTIEN9 External Pin Enable 9 1 read-write EXTIEN10 External Pin Enable 10 1 read-write EXTIEN11 External Pin Enable 11 1 read-write EM4WUIEN0 EM4 Wake Up Interrupt En 16 1 read-write EM4WUIEN1 EM4 Wake Up Interrupt En 17 1 read-write EM4WUIEN2 EM4 Wake Up Interrupt En 18 1 read-write EM4WUIEN3 EM4 Wake Up Interrupt En 19 1 read-write EM4WUIEN4 EM4 Wake Up Interrupt En 20 1 read-write EM4WUIEN5 EM4 Wake Up Interrupt En 21 1 read-write EM4WUIEN6 EM4 Wake Up Interrupt En 22 1 read-write EM4WUIEN7 EM4 Wake Up Interrupt En 23 1 read-write EM4WUIEN8 EM4 Wake Up Interrupt En 24 1 read-write EM4WUIEN9 EM4 Wake Up Interrupt En 25 1 read-write EM4WUIEN10 EM4 Wake Up Interrupt En 26 1 read-write EM4WUIEN11 EM4 Wake Up Interrupt En 27 1 read-write EM4WUEN No Description 0x42C read-write 0x00000000 0x0FFF0000 EM4WUEN EM4 wake up enable 16 12 read-write EM4WUPOL No Description 0x430 read-write 0x00000000 0x0FFF0000 EM4WUPOL EM4 Wake-Up Polarity 16 12 read-write DBGROUTEPEN No Description 0x440 read-write 0x0000000F 0x0000000F SWCLKTCKPEN Route Pin Enable 0 1 read-write SWDIOTMSPEN Route Location 0 1 1 read-write TDOPEN JTAG Test Debug Output Pin Enable 2 1 read-write TDIPEN JTAG Test Debug Input Pin Enable 3 1 read-write TRACEROUTEPEN No Description 0x444 read-write 0x00000000 0x00000007 SWVPEN Serial Wire Viewer Output Pin Enable 0 1 read-write TRACECLKPEN Trace Clk Pin Enable 1 1 read-write TRACEDATA0PEN Trace Data0 Pin Enable 2 1 read-write CMU_ROUTEEN CMU pin enable 0x450 read-write 0x00000000 0x0000000F CLKOUT0PEN CLKOUT0 pin enable control bit 0 1 read-write CLKOUT1PEN CLKOUT1 pin enable control bit 1 1 read-write CLKOUT2PEN CLKOUT2 pin enable control bit 2 1 read-write CMU_CLKIN0ROUTE CLKIN0 port/pin select 0x454 read-write 0x00000000 0x000F0003 PORT CLKIN0 port select register 0 2 read-write PIN CLKIN0 pin select register 16 4 read-write CMU_CLKOUT0ROUTE CLKOUT0 port/pin select 0x458 read-write 0x00000000 0x000F0003 PORT CLKOUT0 port select register 0 2 read-write PIN CLKOUT0 pin select register 16 4 read-write CMU_CLKOUT1ROUTE CLKOUT1 port/pin select 0x45C read-write 0x00000000 0x000F0003 PORT CLKOUT1 port select register 0 2 read-write PIN CLKOUT1 pin select register 16 4 read-write CMU_CLKOUT2ROUTE CLKOUT2 port/pin select 0x460 read-write 0x00000000 0x000F0003 PORT CLKOUT2 port select register 0 2 read-write PIN CLKOUT2 pin select register 16 4 read-write DCDC_ROUTEEN DCDC pin enable 0x46C read-write 0x00000000 0x00000003 DCDCCOREHIDDENPEN DCDCCOREHIDDEN pin enable control bit 0 1 read-write I2C0_ROUTEEN I2C0 pin enable 0x490 read-write 0x00000000 0x00000003 SCLPEN SCL pin enable control bit 0 1 read-write SDAPEN SDA pin enable control bit 1 1 read-write I2C0_SCLROUTE SCL port/pin select 0x494 read-write 0x00000000 0x000F0003 PORT SCL port select register 0 2 read-write PIN SCL pin select register 16 4 read-write I2C0_SDAROUTE SDA port/pin select 0x498 read-write 0x00000000 0x000F0003 PORT SDA port select register 0 2 read-write PIN SDA pin select register 16 4 read-write I2C1_ROUTEEN I2C1 pin enable 0x4A0 read-write 0x00000000 0x00000003 SCLPEN SCL pin enable control bit 0 1 read-write SDAPEN SDA pin enable control bit 1 1 read-write I2C1_SCLROUTE SCL port/pin select 0x4A4 read-write 0x00000000 0x000F0003 PORT SCL port select register 0 2 read-write PIN SCL pin select register 16 4 read-write I2C1_SDAROUTE SDA port/pin select 0x4A8 read-write 0x00000000 0x000F0003 PORT SDA port select register 0 2 read-write PIN SDA pin select register 16 4 read-write LETIMER0_ROUTEEN LETIMER pin enable 0x4B0 read-write 0x00000000 0x00000003 OUT0PEN OUT0 pin enable control bit 0 1 read-write OUT1PEN OUT1 pin enable control bit 1 1 read-write LETIMER0_OUT0ROUTE OUT0 port/pin select 0x4B4 read-write 0x00000000 0x000F0003 PORT OUT0 port select register 0 2 read-write PIN OUT0 pin select register 16 4 read-write LETIMER0_OUT1ROUTE OUT1 port/pin select 0x4B8 read-write 0x00000000 0x000F0003 PORT OUT1 port select register 0 2 read-write PIN OUT1 pin select register 16 4 read-write EUART0_ROUTEEN EUART pin enable 0x4C0 read-write 0x00000000 0x00000003 RTSPEN RTS pin enable control bit 0 1 read-write TXPEN TX pin enable control bit 1 1 read-write EUART0_CTSROUTE CTS port/pin select 0x4C4 read-write 0x00000000 0x000F0003 PORT CTS port select register 0 2 read-write PIN CTS pin select register 16 4 read-write EUART0_RTSROUTE RTS port/pin select 0x4C8 read-write 0x00000000 0x000F0003 PORT RTS port select register 0 2 read-write PIN RTS pin select register 16 4 read-write EUART0_RXROUTE RX port/pin select 0x4CC read-write 0x00000000 0x000F0003 PORT RX port select register 0 2 read-write PIN RX pin select register 16 4 read-write EUART0_TXROUTE TX port/pin select 0x4D0 read-write 0x00000000 0x000F0003 PORT TX port select register 0 2 read-write PIN TX pin select register 16 4 read-write PDM_ROUTEEN PDM pin enable 0x520 read-write 0x00000000 0x00000001 CLKPEN CLK pin enable control bit 0 1 read-write PDM_CLKROUTE CLK port/pin select 0x524 read-write 0x00000000 0x000F0003 PORT CLK port select register 0 2 read-write PIN CLK pin select register 16 4 read-write PDM_DAT0ROUTE DAT0 port/pin select 0x528 read-write 0x00000000 0x000F0003 PORT DAT0 port select register 0 2 read-write PIN DAT0 pin select register 16 4 read-write PDM_DAT1ROUTE DAT1 port/pin select 0x52C read-write 0x00000000 0x000F0003 PORT DAT1 port select register 0 2 read-write PIN DAT1 pin select register 16 4 read-write PRS0_ROUTEEN PRS0 pin enable 0x534 read-write 0x00000000 0x0000FFFF ASYNCH0PEN ASYNCH0 pin enable control bit 0 1 read-write ASYNCH1PEN ASYNCH1 pin enable control bit 1 1 read-write ASYNCH2PEN ASYNCH2 pin enable control bit 2 1 read-write ASYNCH3PEN ASYNCH3 pin enable control bit 3 1 read-write ASYNCH4PEN ASYNCH4 pin enable control bit 4 1 read-write ASYNCH5PEN ASYNCH5 pin enable control bit 5 1 read-write ASYNCH6PEN ASYNCH6 pin enable control bit 6 1 read-write ASYNCH7PEN ASYNCH7 pin enable control bit 7 1 read-write ASYNCH8PEN ASYNCH8 pin enable control bit 8 1 read-write ASYNCH9PEN ASYNCH9 pin enable control bit 9 1 read-write ASYNCH10PEN ASYNCH10 pin enable control bit 10 1 read-write ASYNCH11PEN ASYNCH11 pin enable control bit 11 1 read-write SYNCH0PEN SYNCH0 pin enable control bit 12 1 read-write SYNCH1PEN SYNCH1 pin enable control bit 13 1 read-write SYNCH2PEN SYNCH2 pin enable control bit 14 1 read-write SYNCH3PEN SYNCH3 pin enable control bit 15 1 read-write PRS0_ASYNCH0ROUTE ASYNCH0 port/pin select 0x538 read-write 0x00000000 0x000F0003 PORT ASYNCH0 port select register 0 2 read-write PIN ASYNCH0 pin select register 16 4 read-write PRS0_ASYNCH1ROUTE ASYNCH1 port/pin select 0x53C read-write 0x00000000 0x000F0003 PORT ASYNCH1 port select register 0 2 read-write PIN ASYNCH1 pin select register 16 4 read-write PRS0_ASYNCH2ROUTE ASYNCH2 port/pin select 0x540 read-write 0x00000000 0x000F0003 PORT ASYNCH2 port select register 0 2 read-write PIN ASYNCH2 pin select register 16 4 read-write PRS0_ASYNCH3ROUTE ASYNCH3 port/pin select 0x544 read-write 0x00000000 0x000F0003 PORT ASYNCH3 port select register 0 2 read-write PIN ASYNCH3 pin select register 16 4 read-write PRS0_ASYNCH4ROUTE ASYNCH4 port/pin select 0x548 read-write 0x00000000 0x000F0003 PORT ASYNCH4 port select register 0 2 read-write PIN ASYNCH4 pin select register 16 4 read-write PRS0_ASYNCH5ROUTE ASYNCH5 port/pin select 0x54C read-write 0x00000000 0x000F0003 PORT ASYNCH5 port select register 0 2 read-write PIN ASYNCH5 pin select register 16 4 read-write PRS0_ASYNCH6ROUTE ASYNCH6 port/pin select 0x550 read-write 0x00000000 0x000F0003 PORT ASYNCH6 port select register 0 2 read-write PIN ASYNCH6 pin select register 16 4 read-write PRS0_ASYNCH7ROUTE ASYNCH7 port/pin select 0x554 read-write 0x00000000 0x000F0003 PORT ASYNCH7 port select register 0 2 read-write PIN ASYNCH7 pin select register 16 4 read-write PRS0_ASYNCH8ROUTE ASYNCH8 port/pin select 0x558 read-write 0x00000000 0x000F0003 PORT ASYNCH8 port select register 0 2 read-write PIN ASYNCH8 pin select register 16 4 read-write PRS0_ASYNCH9ROUTE ASYNCH9 port/pin select 0x55C read-write 0x00000000 0x000F0003 PORT ASYNCH9 port select register 0 2 read-write PIN ASYNCH9 pin select register 16 4 read-write PRS0_ASYNCH10ROUTE ASYNCH10 port/pin select 0x560 read-write 0x00000000 0x000F0003 PORT ASYNCH10 port select register 0 2 read-write PIN ASYNCH10 pin select register 16 4 read-write PRS0_ASYNCH11ROUTE ASYNCH11 port/pin select 0x564 read-write 0x00000000 0x000F0003 PORT ASYNCH11 port select register 0 2 read-write PIN ASYNCH11 pin select register 16 4 read-write PRS0_SYNCH0ROUTE SYNCH0 port/pin select 0x568 read-write 0x00000000 0x000F0003 PORT SYNCH0 port select register 0 2 read-write PIN SYNCH0 pin select register 16 4 read-write PRS0_SYNCH1ROUTE SYNCH1 port/pin select 0x56C read-write 0x00000000 0x000F0003 PORT SYNCH1 port select register 0 2 read-write PIN SYNCH1 pin select register 16 4 read-write PRS0_SYNCH2ROUTE SYNCH2 port/pin select 0x570 read-write 0x00000000 0x000F0003 PORT SYNCH2 port select register 0 2 read-write PIN SYNCH2 pin select register 16 4 read-write PRS0_SYNCH3ROUTE SYNCH3 port/pin select 0x574 read-write 0x00000000 0x000F0003 PORT SYNCH3 port select register 0 2 read-write PIN SYNCH3 pin select register 16 4 read-write TIMER0_ROUTEEN TIMER0 pin enable 0x57C read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER0_CC0ROUTE CC0 port/pin select 0x580 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER0_CC1ROUTE CC1 port/pin select 0x584 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER0_CC2ROUTE CC2 port/pin select 0x588 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER0_CDTI0ROUTE CDTI0 port/pin select 0x58C read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER0_CDTI1ROUTE CDTI1 port/pin select 0x590 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER0_CDTI2ROUTE CDTI2 port/pin select 0x594 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write TIMER1_ROUTEEN TIMER1 pin enable 0x59C read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER1_CC0ROUTE CC0 port/pin select 0x5A0 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER1_CC1ROUTE CC1 port/pin select 0x5A4 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER1_CC2ROUTE CC2 port/pin select 0x5A8 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER1_CDTI0ROUTE CDTI0 port/pin select 0x5AC read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER1_CDTI1ROUTE CDTI1 port/pin select 0x5B0 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER1_CDTI2ROUTE CDTI2 port/pin select 0x5B4 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write TIMER2_ROUTEEN TIMER2 pin enable 0x5BC read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER2_CC0ROUTE CC0 port/pin select 0x5C0 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER2_CC1ROUTE CC1 port/pin select 0x5C4 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER2_CC2ROUTE CC2 port/pin select 0x5C8 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER2_CDTI0ROUTE CDTI0 port/pin select 0x5CC read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER2_CDTI1ROUTE CDTI1 port/pin select 0x5D0 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER2_CDTI2ROUTE CDTI2 port/pin select 0x5D4 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write TIMER3_ROUTEEN TIMER3 pin enable 0x5DC read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER3_CC0ROUTE CC0 port/pin select 0x5E0 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER3_CC1ROUTE CC1 port/pin select 0x5E4 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER3_CC2ROUTE CC2 port/pin select 0x5E8 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER3_CDTI0ROUTE CDTI0 port/pin select 0x5EC read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER3_CDTI1ROUTE CDTI1 port/pin select 0x5F0 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER3_CDTI2ROUTE CDTI2 port/pin select 0x5F4 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write TIMER4_ROUTEEN TIMER4 pin enable 0x5FC read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER4_CC0ROUTE CC0 port/pin select 0x600 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER4_CC1ROUTE CC1 port/pin select 0x604 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER4_CC2ROUTE CC2 port/pin select 0x608 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER4_CDTI0ROUTE CDTI0 port/pin select 0x60C read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER4_CDTI1ROUTE CDTI1 port/pin select 0x610 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER4_CDTI2ROUTE CDTI2 port/pin select 0x614 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write USART0_ROUTEEN USART0 pin enable 0x61C read-write 0x00000000 0x0000001F CSPEN CS pin enable control bit 0 1 read-write RTSPEN RTS pin enable control bit 1 1 read-write RXPEN RX pin enable control bit 2 1 read-write CLKPEN SCLK pin enable control bit 3 1 read-write TXPEN TX pin enable control bit 4 1 read-write USART0_CSROUTE CS port/pin select 0x620 read-write 0x00000000 0x000F0003 PORT CS port select register 0 2 read-write PIN CS pin select register 16 4 read-write USART0_CTSROUTE CTS port/pin select 0x624 read-write 0x00000000 0x000F0003 PORT CTS port select register 0 2 read-write PIN CTS pin select register 16 4 read-write USART0_RTSROUTE RTS port/pin select 0x628 read-write 0x00000000 0x000F0003 PORT RTS port select register 0 2 read-write PIN RTS pin select register 16 4 read-write USART0_RXROUTE RX port/pin select 0x62C read-write 0x00000000 0x000F0003 PORT RX port select register 0 2 read-write PIN RX pin select register 16 4 read-write USART0_CLKROUTE SCLK port/pin select 0x630 read-write 0x00000000 0x000F0003 PORT SCLK port select register 0 2 read-write PIN SCLK pin select register 16 4 read-write USART0_TXROUTE TX port/pin select 0x634 read-write 0x00000000 0x000F0003 PORT TX port select register 0 2 read-write PIN TX pin select register 16 4 read-write USART1_ROUTEEN USART1 pin enable 0x63C read-write 0x00000000 0x0000001F CSPEN CS pin enable control bit 0 1 read-write RTSPEN RTS pin enable control bit 1 1 read-write RXPEN RX pin enable control bit 2 1 read-write CLKPEN SCLK pin enable control bit 3 1 read-write TXPEN TX pin enable control bit 4 1 read-write USART1_CSROUTE CS port/pin select 0x640 read-write 0x00000000 0x000F0003 PORT CS port select register 0 2 read-write PIN CS pin select register 16 4 read-write USART1_CTSROUTE CTS port/pin select 0x644 read-write 0x00000000 0x000F0003 PORT CTS port select register 0 2 read-write PIN CTS pin select register 16 4 read-write USART1_RTSROUTE RTS port/pin select 0x648 read-write 0x00000000 0x000F0003 PORT RTS port select register 0 2 read-write PIN RTS pin select register 16 4 read-write USART1_RXROUTE RX port/pin select 0x64C read-write 0x00000000 0x000F0003 PORT RX port select register 0 2 read-write PIN RX pin select register 16 4 read-write USART1_CLKROUTE SCLK port/pin select 0x650 read-write 0x00000000 0x000F0003 PORT SCLK port select register 0 2 read-write PIN SCLK pin select register 16 4 read-write USART1_TXROUTE TX port/pin select 0x654 read-write 0x00000000 0x000F0003 PORT TX port select register 0 2 read-write PIN TX pin select register 16 4 read-write LDMA_S 0 LDMA_S Registers 0x40040000 0x00000000 0x00001000 registers LDMA 21 IPVERSION No Description 0x000 read-only 0x00000000 0x000000FF IPVERSION IPVERSION 0 8 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN LDMA module enable and disable register 0 1 read-write CTRL No Description 0x008 read-write 0x1E000000 0x9F000000 NUMFIXED Number of Fixed Priority Channels 24 5 read-write CORERST Reset DMA controller 31 1 read-write STATUS No Description 0x00C read-only 0x1F100000 0x1F1F1FFB ANYBUSY Any DMA Channel Busy 0 1 read-only ANYREQ Any DMA Channel Request Pending 1 1 read-only CHGRANT Granted Channel Number 3 5 read-only CHERROR Errant Channel Number 8 5 read-only FIFOLEVEL FIFO Level 16 5 read-only CHNUM Number of Channels 24 5 read-only SYNCSWSET No Description 0x010 write-only 0x00000000 0x000000FF SYNCSWSET DMA SYNC Software Trigger Set 0 8 write-only SYNCSWCLR No Description 0x014 write-only 0x00000000 0x000000FF SYNCSWCLR DMA SYNC Software Trigger Clear 0 8 write-only SYNCHWEN No Description 0x018 read-write 0x00000000 0x00FF00FF SYNCSETEN Hardware Sync Trigger Set Enable 0 8 read-write SYNCCLREN Hardware Sync Trigger Clear Enable 16 8 read-write SYNCHWSEL No Description 0x01C read-write 0x00000000 0x00FF00FF SYNCSETEDGE Hardware Sync Trigger Set Edge Select 0 8 read-write RISE Use rising edge detection 0 FALL Use falling edge detection 1 SYNCCLREDGE Hardware Sync Trigger Clear Edge Select 16 8 read-write RISE Use rising edge detection 0 FALL Use falling edge detection 1 SYNCSTATUS No Description 0x020 read-only 0x00000000 0x000000FF SYNCTRIG sync trig status 0 8 read-only CHEN No Description 0x024 write-only 0x00000000 0x000000FF CHEN Channel Enables 0 8 write-only CHDIS No Description 0x028 write-only 0x00000000 0x000000FF CHDIS DMA Channel disable 0 8 write-only CHSTATUS No Description 0x02C read-only 0x00000000 0x000000FF CHSTATUS DMA Channel Status 0 8 read-only CHBUSY No Description 0x030 read-only 0x00000000 0x000000FF BUSY Channels Busy 0 8 read-only CHDONE No Description 0x034 read-write 0x00000000 0x000000FF CHDONE0 DMA Channel Link done intr flag 0 1 read-write CHDONE1 DMA Channel Link done intr flag 1 1 read-write CHDONE2 DMA Channel Link done intr flag 2 1 read-write CHDONE3 DMA Channel Link done intr flag 3 1 read-write CHDONE4 DMA Channel Link done intr flag 4 1 read-write CHDONE5 DMA Channel Link done intr flag 5 1 read-write CHDONE6 DMA Channel Link done intr flag 6 1 read-write CHDONE7 DMA Channel Link done intr flag 7 1 read-write DBGHALT No Description 0x038 read-write 0x00000000 0x000000FF DBGHALT DMA Debug Halt 0 8 read-write SWREQ No Description 0x03C write-only 0x00000000 0x000000FF SWREQ Software Transfer Requests 0 8 write-only REQDIS No Description 0x040 read-write 0x00000000 0x000000FF REQDIS DMA Request Disables 0 8 read-write REQPEND No Description 0x044 read-only 0x00000000 0x000000FF REQPEND DMA Requests Pending 0 8 read-only LINKLOAD No Description 0x048 write-only 0x00000000 0x000000FF LINKLOAD DMA Link Loads 0 8 write-only REQCLEAR No Description 0x04C write-only 0x00000000 0x000000FF REQCLEAR DMA Request Clear 0 8 write-only IF No Description 0x050 read-write 0x00000000 0x800000FF DONE0 DMA Structure Operation Done 0 1 read-write DONE1 DMA Structure Operation Done 1 1 read-write DONE2 DMA Structure Operation Done 2 1 read-write DONE3 DMA Structure Operation Done 3 1 read-write DONE4 DMA Structure Operation Done 4 1 read-write DONE5 DMA Structure Operation Done 5 1 read-write DONE6 DMA Structure Operation Done 6 1 read-write DONE7 DMA Structure Operation Done 7 1 read-write ERROR Error Flag 31 1 read-write IEN No Description 0x054 read-write 0x00000000 0x800000FF CHDONE Enable or disable the done interrupt 0 8 read-write ERROR Enable or disable the error interrupt 31 1 read-write CH0_CFG No Description 0x05C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH0_LOOP No Description 0x060 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH0_CTRL No Description 0x064 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH0_SRC No Description 0x068 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH0_DST No Description 0x06C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH0_LINK No Description 0x070 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH1_CFG No Description 0x08C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH1_LOOP No Description 0x090 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH1_CTRL No Description 0x094 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH1_SRC No Description 0x098 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH1_DST No Description 0x09C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH1_LINK No Description 0x0A0 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH2_CFG No Description 0x0BC read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH2_LOOP No Description 0x0C0 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH2_CTRL No Description 0x0C4 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH2_SRC No Description 0x0C8 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH2_DST No Description 0x0CC read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH2_LINK No Description 0x0D0 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH3_CFG No Description 0x0EC read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH3_LOOP No Description 0x0F0 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH3_CTRL No Description 0x0F4 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH3_SRC No Description 0x0F8 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH3_DST No Description 0x0FC read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH3_LINK No Description 0x100 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH4_CFG No Description 0x11C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH4_LOOP No Description 0x120 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH4_CTRL No Description 0x124 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH4_SRC No Description 0x128 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH4_DST No Description 0x12C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH4_LINK No Description 0x130 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH5_CFG No Description 0x14C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH5_LOOP No Description 0x150 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH5_CTRL No Description 0x154 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH5_SRC No Description 0x158 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH5_DST No Description 0x15C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH5_LINK No Description 0x160 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH6_CFG No Description 0x17C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH6_LOOP No Description 0x180 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH6_CTRL No Description 0x184 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH6_SRC No Description 0x188 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH6_DST No Description 0x18C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH6_LINK No Description 0x190 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH7_CFG No Description 0x1AC read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH7_LOOP No Description 0x1B0 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH7_CTRL No Description 0x1B4 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH7_SRC No Description 0x1B8 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH7_DST No Description 0x1BC read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH7_LINK No Description 0x1C0 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LDMAXBAR_S 1 LDMAXBAR_S Registers 0x40044000 0x00000000 0x00001000 registers CH0_REQSEL No Description 0x000 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH1_REQSEL No Description 0x004 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH2_REQSEL No Description 0x008 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH3_REQSEL No Description 0x00C read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH4_REQSEL No Description 0x010 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH5_REQSEL No Description 0x014 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH6_REQSEL No Description 0x018 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH7_REQSEL No Description 0x01C read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write TIMER0_S 0 TIMER0_S Registers 0x40048000 0x00000000 0x00001000 registers TIMER0 7 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0xFFFFFFFF TOP Counter Top Value 0 32 read-write TOPB No Description 0x020 read-write 0x00000000 0xFFFFFFFF TOPB Counter Top Buffer Register 0 32 read-write CNT No Description 0x024 read-write 0x00000000 0xFFFFFFFF CNT Counter Value 0 32 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0xFFFFFFFF OCB Output Compare Value Buffer 0 32 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0xFFFFFFFF ICF Input Capture FIFO 0 32 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0xFFFFFFFF ICOF Input Capture FIFO Overflow 0 32 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0xFFFFFFFF OCB Output Compare Value Buffer 0 32 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0xFFFFFFFF ICF Input Capture FIFO 0 32 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0xFFFFFFFF ICOF Input Capture FIFO Overflow 0 32 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0xFFFFFFFF OCB Output Compare Value Buffer 0 32 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0xFFFFFFFF ICF Input Capture FIFO 0 32 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0xFFFFFFFF ICOF Input Capture FIFO Overflow 0 32 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 TIMER1_S 0 TIMER1_S Registers 0x4004C000 0x00000000 0x00001000 registers TIMER1 8 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0x0000FFFF TOP Counter Top Value 0 16 read-write TOPB No Description 0x020 read-write 0x00000000 0x0000FFFF TOPB Counter Top Buffer Register 0 16 read-write CNT No Description 0x024 read-write 0x00000000 0x0000FFFF CNT Counter Value 0 16 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 TIMER2_S 0 TIMER2_S Registers 0x40050000 0x00000000 0x00001000 registers TIMER2 9 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0x0000FFFF TOP Counter Top Value 0 16 read-write TOPB No Description 0x020 read-write 0x00000000 0x0000FFFF TOPB Counter Top Buffer Register 0 16 read-write CNT No Description 0x024 read-write 0x00000000 0x0000FFFF CNT Counter Value 0 16 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 TIMER3_S 0 TIMER3_S Registers 0x40054000 0x00000000 0x00001000 registers TIMER3 10 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0x0000FFFF TOP Counter Top Value 0 16 read-write TOPB No Description 0x020 read-write 0x00000000 0x0000FFFF TOPB Counter Top Buffer Register 0 16 read-write CNT No Description 0x024 read-write 0x00000000 0x0000FFFF CNT Counter Value 0 16 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 TIMER4_S 0 TIMER4_S Registers 0x40058000 0x00000000 0x00001000 registers TIMER4 11 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0x0000FFFF TOP Counter Top Value 0 16 read-write TOPB No Description 0x020 read-write 0x00000000 0x0000FFFF TOPB Counter Top Buffer Register 0 16 read-write CNT No Description 0x024 read-write 0x00000000 0x0000FFFF CNT Counter Value 0 16 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 USART0_S 0 USART0_S Registers 0x4005C000 0x00000000 0x00001000 registers USART0_RX 13 USART0_TX 14 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IPVERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN USART Enable 0 1 read-write CTRL No Description 0x008 read-write 0x00000000 0xF3FFFF7F SYNC USART Synchronous Mode 0 1 read-write DISABLE The USART operates in asynchronous mode 0 ENABLE The USART operates in synchronous mode 1 LOOPBK Loopback Enable 1 1 read-write DISABLE The receiver is connected to and receives data from U(S)n_RX 0 ENABLE The receiver is connected to and receives data from U(S)n_TX 1 CCEN Collision Check Enable 2 1 read-write DISABLE Collision check is disabled 0 ENABLE Collision check is enabled. The receiver must be enabled for the check to be performed 1 MPM Multi-Processor Mode 3 1 read-write DISABLE The 9th bit of incoming frames has no special function 0 ENABLE An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set 1 MPAB Multi-Processor Address-Bit 4 1 read-write OVS Oversampling 5 2 read-write X16 Regular UART mode with 16X oversampling in asynchronous mode 0 X8 Double speed with 8X oversampling in asynchronous mode 1 X6 6X oversampling in asynchronous mode 2 X4 Quadruple speed with 4X oversampling in asynchronous mode 3 CLKPOL Clock Polarity 8 1 read-write IDLELOW The bus clock used in synchronous mode has a low base value 0 IDLEHIGH The bus clock used in synchronous mode has a high base value 1 CLKPHA Clock Edge For Setup/Sample 9 1 read-write SAMPLELEADING Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode 0 SAMPLETRAILING Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode 1 MSBF Most Significant Bit First 10 1 read-write DISABLE Data is sent with the least significant bit first 0 ENABLE Data is sent with the most significant bit first 1 CSMA Action On Chip Select In Main Mode 11 1 read-write NOACTION No action taken 0 GOTOSLAVEMODE Go to secondary mode 1 TXBIL TX Buffer Interrupt Level 12 1 read-write EMPTY TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALFFULL TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full. 1 RXINV Receiver Input Invert 13 1 read-write DISABLE Input is passed directly to the receiver 0 ENABLE Input is inverted before it is passed to the receiver 1 TXINV Transmitter output Invert 14 1 read-write DISABLE Output from the transmitter is passed unchanged to U(S)n_TX 0 ENABLE Output from the transmitter is inverted before it is passed to U(S)n_TX 1 CSINV Chip Select Invert 15 1 read-write DISABLE Chip select is active low 0 ENABLE Chip select is active high 1 AUTOCS Automatic Chip Select 16 1 read-write AUTOTRI Automatic TX Tristate 17 1 read-write DISABLE The output on U(S)n_TX when the transmitter is idle is defined by TXINV 0 ENABLE U(S)n_TX is tristated whenever the transmitter is idle 1 SCMODE SmartCard Mode 18 1 read-write SCRETRANS SmartCard Retransmit 19 1 read-write SKIPPERRF Skip Parity Error Frames 20 1 read-write BIT8DV Bit 8 Default Value 21 1 read-write ERRSDMA Halt DMA On Error 22 1 read-write DISABLE Framing and parity errors have no effect on DMA requests from the USART 0 ENABLE DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set 1 ERRSRX Disable RX On Error 23 1 read-write DISABLE Framing and parity errors have no effect on receiver 0 ENABLE Framing and parity errors disable the receiver 1 ERRSTX Disable TX On Error 24 1 read-write DISABLE Received framing and parity errors have no effect on transmitter 0 ENABLE Received framing and parity errors disable the transmitter 1 SSSEARLY Synchronous Secondary Setup Early 25 1 read-write BYTESWAP Byteswap In Double Accesses 28 1 read-write DISABLE Normal byte order 0 ENABLE Byte order swapped 1 AUTOTX Always Transmit When RX Not Full 29 1 read-write MVDIS Majority Vote Disable 30 1 read-write SMSDELAY Synchronous Main Sample Delay 31 1 read-write FRAME No Description 0x00C read-write 0x00001005 0x0000330F DATABITS Data-Bit Mode 0 4 read-write FOUR Each frame contains 4 data bits 1 FIVE Each frame contains 5 data bits 2 SIX Each frame contains 6 data bits 3 SEVEN Each frame contains 7 data bits 4 EIGHT Each frame contains 8 data bits 5 NINE Each frame contains 9 data bits 6 TEN Each frame contains 10 data bits 7 ELEVEN Each frame contains 11 data bits 8 TWELVE Each frame contains 12 data bits 9 THIRTEEN Each frame contains 13 data bits 10 FOURTEEN Each frame contains 14 data bits 11 FIFTEEN Each frame contains 15 data bits 12 SIXTEEN Each frame contains 16 data bits 13 PARITY Parity-Bit Mode 8 2 read-write NONE Parity bits are not used 0 EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. 2 ODD Odd parity is used. Parity bits are automatically generated and checked by hardware. 3 STOPBITS Stop-Bit Mode 12 2 read-write HALF The transmitter generates a half stop bit. Stop-bits are not verified by receiver 0 ONE One stop bit is generated and verified 1 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies the first stop bit 2 TWO The transmitter generates two stop bits. The receiver checks the first stop-bit only 3 TRIGCTRL No Description 0x010 read-write 0x00000000 0x00001FF0 RXTEN Receive Trigger Enable 4 1 read-write TXTEN Transmit Trigger Enable 5 1 read-write AUTOTXTEN AUTOTX Trigger Enable 6 1 read-write TXARX0EN Enable Transmit Trigger after RX End of 7 1 read-write TXARX1EN Enable Transmit Trigger after RX End of 8 1 read-write TXARX2EN Enable Transmit Trigger after RX End of 9 1 read-write RXATX0EN Enable Receive Trigger after TX end of f 10 1 read-write RXATX1EN Enable Receive Trigger after TX end of f 11 1 read-write RXATX2EN Enable Receive Trigger after TX end of f 12 1 read-write CMD No Description 0x014 write-only 0x00000000 0x00000FFF RXEN Receiver Enable 0 1 write-only RXDIS Receiver Disable 1 1 write-only TXEN Transmitter Enable 2 1 write-only TXDIS Transmitter Disable 3 1 write-only MASTEREN Main Mode Enable 4 1 write-only MASTERDIS Main Mode Disable 5 1 write-only RXBLOCKEN Receiver Block Enable 6 1 write-only RXBLOCKDIS Receiver Block Disable 7 1 write-only TXTRIEN Transmitter Tristate Enable 8 1 write-only TXTRIDIS Transmitter Tristate Disable 9 1 write-only CLEARTX Clear TX 10 1 write-only CLEARRX Clear RX 11 1 write-only STATUS No Description 0x018 read-only 0x00002040 0x00037FFF RXENS Receiver Enable Status 0 1 read-only TXENS Transmitter Enable Status 1 1 read-only MASTER SPI Main Mode 2 1 read-only RXBLOCK Block Incoming Data 3 1 read-only TXTRI Transmitter Tristated 4 1 read-only TXC TX Complete 5 1 read-only TXBL TX Buffer Level 6 1 read-only RXDATAV RX Data Valid 7 1 read-only RXFULL RX FIFO Full 8 1 read-only TXBDRIGHT TX Buffer Expects Double Right Data 9 1 read-only TXBSRIGHT TX Buffer Expects Single Right Data 10 1 read-only RXDATAVRIGHT RX Data Right 11 1 read-only RXFULLRIGHT RX Full of Right Data 12 1 read-only TXIDLE TX Idle 13 1 read-only TIMERRESTARTED The USART Timer restarted itself 14 1 read-only TXBUFCNT TX Buffer Count 16 2 read-only CLKDIV No Description 0x01C read-write 0x00000000 0x807FFFF8 DIV Fractional Clock Divider 3 20 read-write AUTOBAUDEN AUTOBAUD detection enable 31 1 read-write RXDATAX No Description 0x020 read-only 0x00000000 0x0000C1FF RXDATA RX Data 0 9 read-only PERR Data Parity Error 14 1 read-only FERR Data Framing Error 15 1 read-only RXDATA No Description 0x024 read-only 0x00000000 0x000000FF RXDATA RX Data 0 8 read-only RXDOUBLEX No Description 0x028 read-only 0x00000000 0xC1FFC1FF RXDATA0 RX Data 0 0 9 read-only PERR0 Data Parity Error 0 14 1 read-only FERR0 Data Framing Error 0 15 1 read-only RXDATA1 RX Data 1 16 9 read-only PERR1 Data Parity Error 1 30 1 read-only FERR1 Data Framing Error 1 31 1 read-only RXDOUBLE No Description 0x02C read-only 0x00000000 0x0000FFFF RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDATAXP No Description 0x030 read-only 0x00000000 0x0000C1FF RXDATAP RX Data Peek 0 9 read-only PERRP Data Parity Error Peek 14 1 read-only FERRP Data Framing Error Peek 15 1 read-only RXDOUBLEXP No Description 0x034 read-only 0x00000000 0xC1FFC1FF RXDATAP0 RX Data 0 Peek 0 9 read-only PERRP0 Data Parity Error 0 Peek 14 1 read-only FERRP0 Data Framing Error 0 Peek 15 1 read-only RXDATAP1 RX Data 1 Peek 16 9 read-only PERRP1 Data Parity Error 1 Peek 30 1 read-only FERRP1 Data Framing Error 1 Peek 31 1 read-only TXDATAX No Description 0x038 write-only 0x00000000 0x0000F9FF TXDATAX TX Data 0 9 write-only UBRXAT Unblock RX After Transmission 11 1 write-only TXTRIAT Set TXTRI After Transmission 12 1 write-only TXBREAK Transmit Data As Break 13 1 write-only TXDISAT Clear TXEN After Transmission 14 1 write-only RXENAT Enable RX After Transmission 15 1 write-only TXDATA No Description 0x03C write-only 0x00000000 0x000000FF TXDATA TX Data 0 8 write-only TXDOUBLEX No Description 0x040 write-only 0x00000000 0xF9FFF9FF TXDATA0 TX Data 0 9 write-only UBRXAT0 Unblock RX After Transmission 11 1 write-only TXTRIAT0 Set TXTRI After Transmission 12 1 write-only TXBREAK0 Transmit Data As Break 13 1 write-only TXDISAT0 Clear TXEN After Transmission 14 1 write-only RXENAT0 Enable RX After Transmission 15 1 write-only TXDATA1 TX Data 16 9 write-only UBRXAT1 Unblock RX After Transmission 27 1 write-only TXTRIAT1 Set TXTRI After Transmission 28 1 write-only TXBREAK1 Transmit Data As Break 29 1 write-only TXDISAT1 Clear TXEN After Transmission 30 1 write-only RXENAT1 Enable RX After Transmission 31 1 write-only TXDOUBLE No Description 0x044 write-only 0x00000000 0x0000FFFF TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only IF No Description 0x048 read-write 0x00000002 0x0001FFFF TXC TX Complete Interrupt Flag 0 1 read-write TXBL TX Buffer Level Interrupt Flag 1 1 read-write RXDATAV RX Data Valid Interrupt Flag 2 1 read-write RXFULL RX Buffer Full Interrupt Flag 3 1 read-write RXOF RX Overflow Interrupt Flag 4 1 read-write RXUF RX Underflow Interrupt Flag 5 1 read-write TXOF TX Overflow Interrupt Flag 6 1 read-write TXUF TX Underflow Interrupt Flag 7 1 read-write PERR Parity Error Interrupt Flag 8 1 read-write FERR Framing Error Interrupt Flag 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write SSM Chip-Select In Main Mode Interrupt Flag 11 1 read-write CCF Collision Check Fail Interrupt Flag 12 1 read-write TXIDLE TX Idle Interrupt Flag 13 1 read-write TCMP0 Timer comparator 0 Interrupt Flag 14 1 read-write TCMP1 Timer comparator 1 Interrupt Flag 15 1 read-write TCMP2 Timer comparator 2 Interrupt Flag 16 1 read-write IEN No Description 0x04C read-write 0x00000000 0x0001FFFF TXC TX Complete Interrupt Enable 0 1 read-write TXBL TX Buffer Level Interrupt Enable 1 1 read-write RXDATAV RX Data Valid Interrupt Enable 2 1 read-write RXFULL RX Buffer Full Interrupt Enable 3 1 read-write RXOF RX Overflow Interrupt Enable 4 1 read-write RXUF RX Underflow Interrupt Enable 5 1 read-write TXOF TX Overflow Interrupt Enable 6 1 read-write TXUF TX Underflow Interrupt Enable 7 1 read-write PERR Parity Error Interrupt Enable 8 1 read-write FERR Framing Error Interrupt Enable 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write SSM Chip-Select In Main Mode Interrupt Flag 11 1 read-write CCF Collision Check Fail Interrupt Enable 12 1 read-write TXIDLE TX Idle Interrupt Enable 13 1 read-write TCMP0 Timer comparator 0 Interrupt Enable 14 1 read-write TCMP1 Timer comparator 1 Interrupt Enable 15 1 read-write TCMP2 Timer comparator 2 Interrupt Enable 16 1 read-write IRCTRL No Description 0x050 read-write 0x00000000 0x0000008F IREN Enable IrDA Module 0 1 read-write IRPW IrDA TX Pulse Width 1 2 read-write ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 0 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 2 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 3 IRFILT IrDA RX Filter 3 1 read-write DISABLE No filter enabled 0 ENABLE Filter enabled. IrDA pulse must be high for at least 5 consecutive clock cycles to be detected 1 I2SCTRL No Description 0x054 read-write 0x00000000 0x0000071F EN Enable I2S Mode 0 1 read-write MONO Stero or Mono 1 1 read-write JUSTIFY Justification of I2S Data 2 1 read-write LEFT Data is left-justified 0 RIGHT Data is right-justified 1 DMASPLIT Separate DMA Request For Left/Right Data 3 1 read-write DELAY Delay on I2S data 4 1 read-write FORMAT I2S Word Format 8 3 read-write W32D32 32-bit word, 32-bit data 0 W32D24M 32-bit word, 32-bit data with 8 lsb masked 1 W32D24 32-bit word, 24-bit data 2 W32D16 32-bit word, 16-bit data 3 W32D8 32-bit word, 8-bit data 4 W16D16 16-bit word, 16-bit data 5 W16D8 16-bit word, 8-bit data 6 W8D8 8-bit word, 8-bit data 7 TIMING No Description 0x058 read-write 0x00000000 0x77770000 TXDELAY TX frame start delay 16 3 read-write DISABLE Disable - TXDELAY in USARTn_CTRL can be used for legacy 0 ONE Start of transmission is delayed for 1 baud-times 1 TWO Start of transmission is delayed for 2 baud-times 2 THREE Start of transmission is delayed for 3 baud-times 3 SEVEN Start of transmission is delayed for 7 baud-times 4 TCMP0 Start of transmission is delayed for TCMPVAL0 baud-times 5 TCMP1 Start of transmission is delayed for TCMPVAL1 baud-times 6 TCMP2 Start of transmission is delayed for TCMPVAL2 baud-times 7 CSSETUP Chip Select Setup 20 3 read-write ZERO CS is not asserted before start of transmission 0 ONE CS is asserted for 1 baud-times before start of transmission 1 TWO CS is asserted for 2 baud-times before start of transmission 2 THREE CS is asserted for 3 baud-times before start of transmission 3 SEVEN CS is asserted for 7 baud-times before start of transmission 4 TCMP0 CS is asserted before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted before the start of transmission for TCMPVAL2 baud-times 7 ICS Inter-character spacing 24 3 read-write ZERO There is no space between charcters 0 ONE Create a space of 1 baud-times before start of transmission 1 TWO Create a space of 2 baud-times before start of transmission 2 THREE Create a space of 3 baud-times before start of transmission 3 SEVEN Create a space of 7 baud-times before start of transmission 4 TCMP0 Create a space of before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 Create a space of before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 Create a space of before the start of transmission for TCMPVAL2 baud-times 7 CSHOLD Chip Select Hold 28 3 read-write ZERO Disable CS being asserted after the end of transmission 0 ONE CS is asserted for 1 baud-times after the end of transmission 1 TWO CS is asserted for 2 baud-times after the end of transmission 2 THREE CS is asserted for 3 baud-times after the end of transmission 3 SEVEN CS is asserted for 7 baud-times after the end of transmission 4 TCMP0 CS is asserted after the end of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted after the end of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted after the end of transmission for TCMPVAL2 baud-times 7 CTRLX No Description 0x05C read-write 0x00000000 0x8000808F DBGHALT Debug halt 0 1 read-write DISABLE Continue to transmit until TX buffer is empty 0 ENABLE Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock; otherwise, each single step could transmit multiple frames instead of just transmitting one frame. 1 CTSINV CTS Pin Inversion 1 1 read-write DISABLE The USn_CTS pin is low true 0 ENABLE The USn_CTS pin is high true 1 CTSEN CTS Function enabled 2 1 read-write DISABLE Ingore CTS 0 ENABLE Stop transmitting when CTS is negated 1 RTSINV RTS Pin Inversion 3 1 read-write DISABLE The USn_RTS pin is low true 0 ENABLE The USn_RTS pin is high true 1 RXPRSEN PRS RX Enable 7 1 read-write CLKPRSEN PRS CLK Enable 15 1 read-write TIMECMP0 No Description 0x060 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 0. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 0 is disabled 0 TXEOF Comparator 0 and timer are started at TX end of frame 1 TXC Comparator 0 and timer are started at TX Complete 2 RXACT Comparator 0 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 0 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 0 20 3 read-write TCMP0 Comparator 0 is disabled when the counter equals TCMPVAL and triggers a TCMP0 event 0 TXST Comparator 0 is disabled at TX start TX Engine 1 RXACT Comparator 0 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 0 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP0 24 1 read-write DISABLE Disable the timer restarting on TCMP0 0 ENABLE Enable the timer restarting on TCMP0 1 TIMECMP1 No Description 0x064 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 1. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 1 is disabled 0 TXEOF Comparator 1 and timer are started at TX end of frame 1 TXC Comparator 1 and timer are started at TX Complete 2 RXACT Comparator 1 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 1 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 1 20 3 read-write TCMP1 Comparator 1 is disabled when the counter equals TCMPVAL and triggers a TCMP1 event 0 TXST Comparator 1 is disabled at TX start TX Engine 1 RXACT Comparator 1 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 1 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP1 24 1 read-write DISABLE Disable the timer restarting on TCMP1 0 ENABLE Enable the timer restarting on TCMP1 1 TIMECMP2 No Description 0x068 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 2. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 2 is disabled 0 TXEOF Comparator 2 and timer are started at TX end of frame 1 TXC Comparator 2 and timer are started at TX Complete 2 RXACT Comparator 2 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 2 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 2 20 3 read-write TCMP2 Comparator 2 is disabled when the counter equals TCMPVAL and triggers a TCMP2 event 0 TXST Comparator 2 is disabled at TX start TX Engine 1 RXACT Comparator 2 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 2 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP2 24 1 read-write DISABLE Disable the timer restarting on TCMP2 0 ENABLE Enable the timer restarting on TCMP2 1 USART1_S 0 USART1_S Registers 0x40060000 0x00000000 0x00001000 registers USART1_RX 15 USART1_TX 16 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IPVERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN USART Enable 0 1 read-write CTRL No Description 0x008 read-write 0x00000000 0xF3FFFF7F SYNC USART Synchronous Mode 0 1 read-write DISABLE The USART operates in asynchronous mode 0 ENABLE The USART operates in synchronous mode 1 LOOPBK Loopback Enable 1 1 read-write DISABLE The receiver is connected to and receives data from U(S)n_RX 0 ENABLE The receiver is connected to and receives data from U(S)n_TX 1 CCEN Collision Check Enable 2 1 read-write DISABLE Collision check is disabled 0 ENABLE Collision check is enabled. The receiver must be enabled for the check to be performed 1 MPM Multi-Processor Mode 3 1 read-write DISABLE The 9th bit of incoming frames has no special function 0 ENABLE An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set 1 MPAB Multi-Processor Address-Bit 4 1 read-write OVS Oversampling 5 2 read-write X16 Regular UART mode with 16X oversampling in asynchronous mode 0 X8 Double speed with 8X oversampling in asynchronous mode 1 X6 6X oversampling in asynchronous mode 2 X4 Quadruple speed with 4X oversampling in asynchronous mode 3 CLKPOL Clock Polarity 8 1 read-write IDLELOW The bus clock used in synchronous mode has a low base value 0 IDLEHIGH The bus clock used in synchronous mode has a high base value 1 CLKPHA Clock Edge For Setup/Sample 9 1 read-write SAMPLELEADING Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode 0 SAMPLETRAILING Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode 1 MSBF Most Significant Bit First 10 1 read-write DISABLE Data is sent with the least significant bit first 0 ENABLE Data is sent with the most significant bit first 1 CSMA Action On Chip Select In Main Mode 11 1 read-write NOACTION No action taken 0 GOTOSLAVEMODE Go to secondary mode 1 TXBIL TX Buffer Interrupt Level 12 1 read-write EMPTY TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALFFULL TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full. 1 RXINV Receiver Input Invert 13 1 read-write DISABLE Input is passed directly to the receiver 0 ENABLE Input is inverted before it is passed to the receiver 1 TXINV Transmitter output Invert 14 1 read-write DISABLE Output from the transmitter is passed unchanged to U(S)n_TX 0 ENABLE Output from the transmitter is inverted before it is passed to U(S)n_TX 1 CSINV Chip Select Invert 15 1 read-write DISABLE Chip select is active low 0 ENABLE Chip select is active high 1 AUTOCS Automatic Chip Select 16 1 read-write AUTOTRI Automatic TX Tristate 17 1 read-write DISABLE The output on U(S)n_TX when the transmitter is idle is defined by TXINV 0 ENABLE U(S)n_TX is tristated whenever the transmitter is idle 1 SCMODE SmartCard Mode 18 1 read-write SCRETRANS SmartCard Retransmit 19 1 read-write SKIPPERRF Skip Parity Error Frames 20 1 read-write BIT8DV Bit 8 Default Value 21 1 read-write ERRSDMA Halt DMA On Error 22 1 read-write DISABLE Framing and parity errors have no effect on DMA requests from the USART 0 ENABLE DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set 1 ERRSRX Disable RX On Error 23 1 read-write DISABLE Framing and parity errors have no effect on receiver 0 ENABLE Framing and parity errors disable the receiver 1 ERRSTX Disable TX On Error 24 1 read-write DISABLE Received framing and parity errors have no effect on transmitter 0 ENABLE Received framing and parity errors disable the transmitter 1 SSSEARLY Synchronous Secondary Setup Early 25 1 read-write BYTESWAP Byteswap In Double Accesses 28 1 read-write DISABLE Normal byte order 0 ENABLE Byte order swapped 1 AUTOTX Always Transmit When RX Not Full 29 1 read-write MVDIS Majority Vote Disable 30 1 read-write SMSDELAY Synchronous Main Sample Delay 31 1 read-write FRAME No Description 0x00C read-write 0x00001005 0x0000330F DATABITS Data-Bit Mode 0 4 read-write FOUR Each frame contains 4 data bits 1 FIVE Each frame contains 5 data bits 2 SIX Each frame contains 6 data bits 3 SEVEN Each frame contains 7 data bits 4 EIGHT Each frame contains 8 data bits 5 NINE Each frame contains 9 data bits 6 TEN Each frame contains 10 data bits 7 ELEVEN Each frame contains 11 data bits 8 TWELVE Each frame contains 12 data bits 9 THIRTEEN Each frame contains 13 data bits 10 FOURTEEN Each frame contains 14 data bits 11 FIFTEEN Each frame contains 15 data bits 12 SIXTEEN Each frame contains 16 data bits 13 PARITY Parity-Bit Mode 8 2 read-write NONE Parity bits are not used 0 EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. 2 ODD Odd parity is used. Parity bits are automatically generated and checked by hardware. 3 STOPBITS Stop-Bit Mode 12 2 read-write HALF The transmitter generates a half stop bit. Stop-bits are not verified by receiver 0 ONE One stop bit is generated and verified 1 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies the first stop bit 2 TWO The transmitter generates two stop bits. The receiver checks the first stop-bit only 3 TRIGCTRL No Description 0x010 read-write 0x00000000 0x00001FF0 RXTEN Receive Trigger Enable 4 1 read-write TXTEN Transmit Trigger Enable 5 1 read-write AUTOTXTEN AUTOTX Trigger Enable 6 1 read-write TXARX0EN Enable Transmit Trigger after RX End of 7 1 read-write TXARX1EN Enable Transmit Trigger after RX End of 8 1 read-write TXARX2EN Enable Transmit Trigger after RX End of 9 1 read-write RXATX0EN Enable Receive Trigger after TX end of f 10 1 read-write RXATX1EN Enable Receive Trigger after TX end of f 11 1 read-write RXATX2EN Enable Receive Trigger after TX end of f 12 1 read-write CMD No Description 0x014 write-only 0x00000000 0x00000FFF RXEN Receiver Enable 0 1 write-only RXDIS Receiver Disable 1 1 write-only TXEN Transmitter Enable 2 1 write-only TXDIS Transmitter Disable 3 1 write-only MASTEREN Main Mode Enable 4 1 write-only MASTERDIS Main Mode Disable 5 1 write-only RXBLOCKEN Receiver Block Enable 6 1 write-only RXBLOCKDIS Receiver Block Disable 7 1 write-only TXTRIEN Transmitter Tristate Enable 8 1 write-only TXTRIDIS Transmitter Tristate Disable 9 1 write-only CLEARTX Clear TX 10 1 write-only CLEARRX Clear RX 11 1 write-only STATUS No Description 0x018 read-only 0x00002040 0x00037FFF RXENS Receiver Enable Status 0 1 read-only TXENS Transmitter Enable Status 1 1 read-only MASTER SPI Main Mode 2 1 read-only RXBLOCK Block Incoming Data 3 1 read-only TXTRI Transmitter Tristated 4 1 read-only TXC TX Complete 5 1 read-only TXBL TX Buffer Level 6 1 read-only RXDATAV RX Data Valid 7 1 read-only RXFULL RX FIFO Full 8 1 read-only TXBDRIGHT TX Buffer Expects Double Right Data 9 1 read-only TXBSRIGHT TX Buffer Expects Single Right Data 10 1 read-only RXDATAVRIGHT RX Data Right 11 1 read-only RXFULLRIGHT RX Full of Right Data 12 1 read-only TXIDLE TX Idle 13 1 read-only TIMERRESTARTED The USART Timer restarted itself 14 1 read-only TXBUFCNT TX Buffer Count 16 2 read-only CLKDIV No Description 0x01C read-write 0x00000000 0x807FFFF8 DIV Fractional Clock Divider 3 20 read-write AUTOBAUDEN AUTOBAUD detection enable 31 1 read-write RXDATAX No Description 0x020 read-only 0x00000000 0x0000C1FF RXDATA RX Data 0 9 read-only PERR Data Parity Error 14 1 read-only FERR Data Framing Error 15 1 read-only RXDATA No Description 0x024 read-only 0x00000000 0x000000FF RXDATA RX Data 0 8 read-only RXDOUBLEX No Description 0x028 read-only 0x00000000 0xC1FFC1FF RXDATA0 RX Data 0 0 9 read-only PERR0 Data Parity Error 0 14 1 read-only FERR0 Data Framing Error 0 15 1 read-only RXDATA1 RX Data 1 16 9 read-only PERR1 Data Parity Error 1 30 1 read-only FERR1 Data Framing Error 1 31 1 read-only RXDOUBLE No Description 0x02C read-only 0x00000000 0x0000FFFF RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDATAXP No Description 0x030 read-only 0x00000000 0x0000C1FF RXDATAP RX Data Peek 0 9 read-only PERRP Data Parity Error Peek 14 1 read-only FERRP Data Framing Error Peek 15 1 read-only RXDOUBLEXP No Description 0x034 read-only 0x00000000 0xC1FFC1FF RXDATAP0 RX Data 0 Peek 0 9 read-only PERRP0 Data Parity Error 0 Peek 14 1 read-only FERRP0 Data Framing Error 0 Peek 15 1 read-only RXDATAP1 RX Data 1 Peek 16 9 read-only PERRP1 Data Parity Error 1 Peek 30 1 read-only FERRP1 Data Framing Error 1 Peek 31 1 read-only TXDATAX No Description 0x038 write-only 0x00000000 0x0000F9FF TXDATAX TX Data 0 9 write-only UBRXAT Unblock RX After Transmission 11 1 write-only TXTRIAT Set TXTRI After Transmission 12 1 write-only TXBREAK Transmit Data As Break 13 1 write-only TXDISAT Clear TXEN After Transmission 14 1 write-only RXENAT Enable RX After Transmission 15 1 write-only TXDATA No Description 0x03C write-only 0x00000000 0x000000FF TXDATA TX Data 0 8 write-only TXDOUBLEX No Description 0x040 write-only 0x00000000 0xF9FFF9FF TXDATA0 TX Data 0 9 write-only UBRXAT0 Unblock RX After Transmission 11 1 write-only TXTRIAT0 Set TXTRI After Transmission 12 1 write-only TXBREAK0 Transmit Data As Break 13 1 write-only TXDISAT0 Clear TXEN After Transmission 14 1 write-only RXENAT0 Enable RX After Transmission 15 1 write-only TXDATA1 TX Data 16 9 write-only UBRXAT1 Unblock RX After Transmission 27 1 write-only TXTRIAT1 Set TXTRI After Transmission 28 1 write-only TXBREAK1 Transmit Data As Break 29 1 write-only TXDISAT1 Clear TXEN After Transmission 30 1 write-only RXENAT1 Enable RX After Transmission 31 1 write-only TXDOUBLE No Description 0x044 write-only 0x00000000 0x0000FFFF TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only IF No Description 0x048 read-write 0x00000002 0x0001FFFF TXC TX Complete Interrupt Flag 0 1 read-write TXBL TX Buffer Level Interrupt Flag 1 1 read-write RXDATAV RX Data Valid Interrupt Flag 2 1 read-write RXFULL RX Buffer Full Interrupt Flag 3 1 read-write RXOF RX Overflow Interrupt Flag 4 1 read-write RXUF RX Underflow Interrupt Flag 5 1 read-write TXOF TX Overflow Interrupt Flag 6 1 read-write TXUF TX Underflow Interrupt Flag 7 1 read-write PERR Parity Error Interrupt Flag 8 1 read-write FERR Framing Error Interrupt Flag 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write SSM Chip-Select In Main Mode Interrupt Flag 11 1 read-write CCF Collision Check Fail Interrupt Flag 12 1 read-write TXIDLE TX Idle Interrupt Flag 13 1 read-write TCMP0 Timer comparator 0 Interrupt Flag 14 1 read-write TCMP1 Timer comparator 1 Interrupt Flag 15 1 read-write TCMP2 Timer comparator 2 Interrupt Flag 16 1 read-write IEN No Description 0x04C read-write 0x00000000 0x0001FFFF TXC TX Complete Interrupt Enable 0 1 read-write TXBL TX Buffer Level Interrupt Enable 1 1 read-write RXDATAV RX Data Valid Interrupt Enable 2 1 read-write RXFULL RX Buffer Full Interrupt Enable 3 1 read-write RXOF RX Overflow Interrupt Enable 4 1 read-write RXUF RX Underflow Interrupt Enable 5 1 read-write TXOF TX Overflow Interrupt Enable 6 1 read-write TXUF TX Underflow Interrupt Enable 7 1 read-write PERR Parity Error Interrupt Enable 8 1 read-write FERR Framing Error Interrupt Enable 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write SSM Chip-Select In Main Mode Interrupt Flag 11 1 read-write CCF Collision Check Fail Interrupt Enable 12 1 read-write TXIDLE TX Idle Interrupt Enable 13 1 read-write TCMP0 Timer comparator 0 Interrupt Enable 14 1 read-write TCMP1 Timer comparator 1 Interrupt Enable 15 1 read-write TCMP2 Timer comparator 2 Interrupt Enable 16 1 read-write IRCTRL No Description 0x050 read-write 0x00000000 0x0000008F IREN Enable IrDA Module 0 1 read-write IRPW IrDA TX Pulse Width 1 2 read-write ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 0 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 2 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 3 IRFILT IrDA RX Filter 3 1 read-write DISABLE No filter enabled 0 ENABLE Filter enabled. IrDA pulse must be high for at least 5 consecutive clock cycles to be detected 1 I2SCTRL No Description 0x054 read-write 0x00000000 0x0000071F EN Enable I2S Mode 0 1 read-write MONO Stero or Mono 1 1 read-write JUSTIFY Justification of I2S Data 2 1 read-write LEFT Data is left-justified 0 RIGHT Data is right-justified 1 DMASPLIT Separate DMA Request For Left/Right Data 3 1 read-write DELAY Delay on I2S data 4 1 read-write FORMAT I2S Word Format 8 3 read-write W32D32 32-bit word, 32-bit data 0 W32D24M 32-bit word, 32-bit data with 8 lsb masked 1 W32D24 32-bit word, 24-bit data 2 W32D16 32-bit word, 16-bit data 3 W32D8 32-bit word, 8-bit data 4 W16D16 16-bit word, 16-bit data 5 W16D8 16-bit word, 8-bit data 6 W8D8 8-bit word, 8-bit data 7 TIMING No Description 0x058 read-write 0x00000000 0x77770000 TXDELAY TX frame start delay 16 3 read-write DISABLE Disable - TXDELAY in USARTn_CTRL can be used for legacy 0 ONE Start of transmission is delayed for 1 baud-times 1 TWO Start of transmission is delayed for 2 baud-times 2 THREE Start of transmission is delayed for 3 baud-times 3 SEVEN Start of transmission is delayed for 7 baud-times 4 TCMP0 Start of transmission is delayed for TCMPVAL0 baud-times 5 TCMP1 Start of transmission is delayed for TCMPVAL1 baud-times 6 TCMP2 Start of transmission is delayed for TCMPVAL2 baud-times 7 CSSETUP Chip Select Setup 20 3 read-write ZERO CS is not asserted before start of transmission 0 ONE CS is asserted for 1 baud-times before start of transmission 1 TWO CS is asserted for 2 baud-times before start of transmission 2 THREE CS is asserted for 3 baud-times before start of transmission 3 SEVEN CS is asserted for 7 baud-times before start of transmission 4 TCMP0 CS is asserted before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted before the start of transmission for TCMPVAL2 baud-times 7 ICS Inter-character spacing 24 3 read-write ZERO There is no space between charcters 0 ONE Create a space of 1 baud-times before start of transmission 1 TWO Create a space of 2 baud-times before start of transmission 2 THREE Create a space of 3 baud-times before start of transmission 3 SEVEN Create a space of 7 baud-times before start of transmission 4 TCMP0 Create a space of before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 Create a space of before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 Create a space of before the start of transmission for TCMPVAL2 baud-times 7 CSHOLD Chip Select Hold 28 3 read-write ZERO Disable CS being asserted after the end of transmission 0 ONE CS is asserted for 1 baud-times after the end of transmission 1 TWO CS is asserted for 2 baud-times after the end of transmission 2 THREE CS is asserted for 3 baud-times after the end of transmission 3 SEVEN CS is asserted for 7 baud-times after the end of transmission 4 TCMP0 CS is asserted after the end of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted after the end of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted after the end of transmission for TCMPVAL2 baud-times 7 CTRLX No Description 0x05C read-write 0x00000000 0x8000808F DBGHALT Debug halt 0 1 read-write DISABLE Continue to transmit until TX buffer is empty 0 ENABLE Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock; otherwise, each single step could transmit multiple frames instead of just transmitting one frame. 1 CTSINV CTS Pin Inversion 1 1 read-write DISABLE The USn_CTS pin is low true 0 ENABLE The USn_CTS pin is high true 1 CTSEN CTS Function enabled 2 1 read-write DISABLE Ingore CTS 0 ENABLE Stop transmitting when CTS is negated 1 RTSINV RTS Pin Inversion 3 1 read-write DISABLE The USn_RTS pin is low true 0 ENABLE The USn_RTS pin is high true 1 RXPRSEN PRS RX Enable 7 1 read-write CLKPRSEN PRS CLK Enable 15 1 read-write TIMECMP0 No Description 0x060 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 0. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 0 is disabled 0 TXEOF Comparator 0 and timer are started at TX end of frame 1 TXC Comparator 0 and timer are started at TX Complete 2 RXACT Comparator 0 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 0 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 0 20 3 read-write TCMP0 Comparator 0 is disabled when the counter equals TCMPVAL and triggers a TCMP0 event 0 TXST Comparator 0 is disabled at TX start TX Engine 1 RXACT Comparator 0 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 0 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP0 24 1 read-write DISABLE Disable the timer restarting on TCMP0 0 ENABLE Enable the timer restarting on TCMP0 1 TIMECMP1 No Description 0x064 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 1. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 1 is disabled 0 TXEOF Comparator 1 and timer are started at TX end of frame 1 TXC Comparator 1 and timer are started at TX Complete 2 RXACT Comparator 1 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 1 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 1 20 3 read-write TCMP1 Comparator 1 is disabled when the counter equals TCMPVAL and triggers a TCMP1 event 0 TXST Comparator 1 is disabled at TX start TX Engine 1 RXACT Comparator 1 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 1 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP1 24 1 read-write DISABLE Disable the timer restarting on TCMP1 0 ENABLE Enable the timer restarting on TCMP1 1 TIMECMP2 No Description 0x068 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 2. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 2 is disabled 0 TXEOF Comparator 2 and timer are started at TX end of frame 1 TXC Comparator 2 and timer are started at TX Complete 2 RXACT Comparator 2 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 2 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 2 20 3 read-write TCMP2 Comparator 2 is disabled when the counter equals TCMPVAL and triggers a TCMP2 event 0 TXST Comparator 2 is disabled at TX start TX Engine 1 RXACT Comparator 2 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 2 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP2 24 1 read-write DISABLE Disable the timer restarting on TCMP2 0 ENABLE Enable the timer restarting on TCMP2 1 BURTC_S 0 BURTC_S Registers 0x40064000 0x00000000 0x00001000 registers BURTC 18 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN BURTC Enable 0 1 read-write CFG No Description 0x008 read-write 0x00000000 0x000000F3 DEBUGRUN Debug Mode Run Enable 0 1 read-write DISABLE BURTC is frozen in debug mode 0 ENABLE BURTC is running in debug mode 1 COMPTOP Compare Channel is Top Value 1 1 read-write DISABLE The top value of the BURTC is 4294967295 (0xFFFFFFFF) 0 ENABLE The top value of the BURTC is given by COMP 1 CNTPRESC Counter prescaler value. 4 4 read-write DIV1 CLK_CNT = (BURTC LF CLK)/1 0 DIV2 CLK_CNT = (BURTC LF CLK)/2 1 DIV4 CLK_CNT = (BURTC LF CLK)/4 2 DIV8 CLK_CNT = (BURTC LF CLK)/8 3 DIV16 CLK_CNT = (BURTC LF CLK)/16 4 DIV32 CLK_CNT = (BURTC LF CLK)/32 5 DIV64 CLK_CNT = (BURTC LF CLK)/64 6 DIV128 CLK_CNT = (BURTC LF CLK)/128 7 DIV256 CLK_CNT = (BURTC LF CLK)/256 8 DIV512 CLK_CNT = (BURTC LF CLK)/512 9 DIV1024 CLK_CNT = (BURTC LF CLK)/1024 10 DIV2048 CLK_CNT = (BURTC LF CLK)/2048 11 DIV4096 CLK_CNT = (BURTC LF CLK)/4096 12 DIV8192 CLK_CNT = (BURTC LF CLK)/8192 13 DIV16384 CLK_CNT = (BURTC LF CLK)/16384 14 DIV32768 CLK_CNT = (BURTC LF CLK)/32768 15 CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start BURTC counter 0 1 write-only STOP Stop BURTC counter 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x00000003 RUNNING BURTC running status 0 1 read-only LOCK Configuration Lock Status 1 1 read-only UNLOCKED All BURTC lockable registers are unlocked. 0 LOCKED All BURTC lockable registers are locked. 1 IF No Description 0x014 read-write 0x00000000 0x00000003 OF Overflow Interrupt Flag 0 1 read-write COMP Compare Match Interrupt Flag 1 1 read-write IEN No Description 0x018 read-write 0x00000000 0x00000003 OF Overflow Interrupt Flag 0 1 read-write COMP Compare Match Interrupt Flag 1 1 read-write PRECNT No Description 0x01C read-write 0x00000000 0x00007FFF PRECNT Pre-Counter Value 0 15 read-write CNT No Description 0x020 read-write 0x00000000 0xFFFFFFFF CNT Counter Value 0 32 read-write EM4WUEN No Description 0x024 read-write 0x00000000 0x00000003 OFEM4WUEN Overflow EM4 Wakeup Enable 0 1 read-write COMPEM4WUEN Compare Match EM4 Wakeup Enable 1 1 read-write SYNCBUSY No Description 0x028 read-only 0x00000000 0x0000003F START Sync busy for START 0 1 read-only STOP Sync busy for STOP 1 1 read-only PRECNT Sync busy for PRECNT 2 1 read-only CNT Sync busy for CNT 3 1 read-only COMP Sync busy for COMP 4 1 read-only EN Sync busy for EN 5 1 read-only LOCK No Description 0x02C write-only 0x0000AEE8 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write to unlock all BURTC lockable registers 44776 COMP No Description 0x030 read-write 0x00000000 0xFFFFFFFF COMP Compare Value 0 32 read-write I2C1_S 0 I2C1_S Registers 0x40068000 0x00000000 0x00001000 registers I2C1 28 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN module enable 0 1 read-write DISABLE Disable Peripheral Clock 0 ENABLE Enable Peripheral Clock 1 CTRL No Description 0x008 read-write 0x00000000 0x0037B3FF CORERST Soft Reset the internal state registers 0 1 read-write DISABLE No change to internal state registers 0 ENABLE Reset the internal state registers 1 SLAVE Addressable as Follower 1 1 read-write DISABLE All addresses will be responded to with a NACK 0 ENABLE Addresses matching the programmed follower address or the general call address (if enabled) require a response from software. Other addresses are automatically responded to with a NACK. 1 AUTOACK Automatic Acknowledge 2 1 read-write DISABLE Software must give one ACK command for each ACK transmitted on the I2C bus. 0 ENABLE Addresses that are not automatically NACK'ed, and all data is automatically acknowledged. 1 AUTOSE Automatic STOP when Empty 3 1 read-write DISABLE A stop must be sent manually when no more data is to be transmitted. 0 ENABLE The leader automatically sends a STOP when no more data is available for transmission. 1 AUTOSN Automatic STOP on NACK 4 1 read-write DISABLE Stop is not automatically sent if a NACK is received from a follower. 0 ENABLE The leader automatically sends a STOP if a NACK is received from a follower. 1 ARBDIS Arbitration Disable 5 1 read-write DISABLE When a device loses arbitration, the ARBIF interrupt flag is set and the bus is released. 0 ENABLE When a device loses arbitration, the ARBIF interrupt flag is set, but communication proceeds. 1 GCAMEN General Call Address Match Enable 6 1 read-write DISABLE General call address will be NACK'ed if it is not included by the follower address and address mask. 0 ENABLE When a general call address is received, a software response is required 1 TXBIL TX Buffer Interrupt Level 7 1 read-write EMPTY TXBL status and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALF_FULL TXBL status and the TXBL interrupt flag are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full 1 CLHR Clock Low High Ratio 8 2 read-write STANDARD Nlow=4 and Nhigh=4, and the Nlow:Nhigh ratio is 4:4 0 ASYMMETRIC Nlow=6 and Nhigh=3, and the Nlow:Nhigh ratio is 6:3 1 FAST Nlow=11 and Nhigh=6, and the Nlow:Nhigh ratio is 11:6 2 BITO Bus Idle Timeout 12 2 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 GIBITO Go Idle on Bus Idle Timeout 15 1 read-write DISABLE A bus idle timeout has no effect on the bus state. 0 ENABLE A bus idle timeout tells the I2C module that the bus is idle, allowing new transfers to be initiated. 1 CLTO Clock Low Timeout 16 3 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 I2C320PCC Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout. 4 I2C1024PCC Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout. 5 SCLMONEN SCL Monitor Enable 20 1 read-write DISABLE Disable SCL monitor 0 ENABLE Enable SCL monitor 1 SDAMONEN SDA Monitor Enable 21 1 read-write DISABLE Disable SDA Monitor 0 ENABLE Enable SDA Monitor 1 CMD No Description 0x00C write-only 0x00000000 0x000000FF START Send start condition 0 1 write-only STOP Send stop condition 1 1 write-only ACK Send ACK 2 1 write-only NACK Send NACK 3 1 write-only CONT Continue transmission 4 1 write-only ABORT Abort transmission 5 1 write-only CLEARTX Clear TX 6 1 write-only CLEARPC Clear Pending Commands 7 1 write-only STATE No Description 0x010 read-only 0x00000001 0x000000FF BUSY Bus Busy 0 1 read-only MASTER Leader 1 1 read-only TRANSMITTER Transmitter 2 1 read-only NACKED Nack Received 3 1 read-only BUSHOLD Bus Held 4 1 read-only STATE Transmission State 5 3 read-only IDLE No transmission is being performed. 0 WAIT Waiting for idle. Will send a start condition as soon as the bus is idle. 1 START Start transmit phase 2 ADDR Address transmit or receive phase 3 ADDRACK Address ack/nack transmit or receive phase 4 DATA Data transmit or receive phase 5 DATAACK Data ack/nack transmit or receive phase 6 STATUS No Description 0x014 read-only 0x00000080 0x00000FFF PSTART Pending START 0 1 read-only PSTOP Pending STOP 1 1 read-only PACK Pending ACK 2 1 read-only PNACK Pending NACK 3 1 read-only PCONT Pending continue 4 1 read-only PABORT Pending abort 5 1 read-only TXC TX Complete 6 1 read-only TXBL TX Buffer Level 7 1 read-only RXDATAV RX Data Valid 8 1 read-only RXFULL RX FIFO Full 9 1 read-only TXBUFCNT TX Buffer Count 10 2 read-only CLKDIV No Description 0x018 read-write 0x00000000 0x000001FF DIV Clock Divider 0 9 read-write SADDR No Description 0x01C read-write 0x00000000 0x000000FE ADDR Follower address 1 7 read-write SADDRMASK No Description 0x020 read-write 0x00000000 0x000000FE SADDRMASK Follower Address Mask 1 7 read-write RXDATA No Description 0x024 read-only 0x00000000 0x000000FF RXDATA RX Data 0 8 read-only RXDOUBLE No Description 0x028 read-only 0x00000000 0x0000FFFF RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDATAP No Description 0x02C read-only 0x00000000 0x000000FF RXDATAP RX Data Peek 0 8 read-only RXDOUBLEP No Description 0x030 read-only 0x00000000 0x0000FFFF RXDATAP0 RX Data 0 Peek 0 8 read-only RXDATAP1 RX Data 1 Peek 8 8 read-only TXDATA No Description 0x034 write-only 0x00000000 0x000000FF TXDATA TX Data 0 8 write-only TXDOUBLE No Description 0x038 write-only 0x00000000 0x0000FFFF TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only IF No Description 0x03C read-write 0x00000000 0x001FFFFF START START condition Interrupt Flag 0 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write ADDR Address Interrupt Flag 2 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write ACK Acknowledge Received Interrupt Flag 6 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write MSTOP Leader STOP Condition Interrupt Flag 8 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write SSTOP Follower STOP condition Interrupt Flag 16 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write IEN No Description 0x040 read-write 0x00000000 0x001FFFFF START START condition Interrupt Flag 0 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write ADDR Address Interrupt Flag 2 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write ACK Acknowledge Received Interrupt Flag 6 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write MSTOP Leader STOP Condition Interrupt Flag 8 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write SSTOP Follower STOP condition Interrupt Flag 16 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write SYSCFG_S_CFGNS 1 SYSCFG_S_CFGNS Registers 0x40078000 0x00000000 0x00001000 registers SYSCFG 20 SW0 52 SW1 53 SW2 54 SW3 55 CFGNSTCALIB Configure to define the system tick for the M33. 0x01C read-write 0x01004A37 0x03FFFFFF TENMS Ten Milliseconds 0 24 read-write SKEW Skew 24 1 read-write NOREF No Reference 25 1 read-write REF Reference clock is implemented 0 NOREF Reference clock is not implemented 1 ROOTNSDATA0 Generic data space for user to pass to root, e.g., address of struct in mem 0x600 read-write 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write ROOTNSDATA1 Generic data space for user to pass to root, e.g., address of struct in mem 0x604 read-write 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write SYSCFG_S 1 SYSCFG_S Registers 0x4007C000 0x00000000 0x00001000 registers SYSCFG 20 SW0 52 SW1 53 SW2 54 SW3 55 IF Read to get system status. 0x000 read-write 0x00000000 0x3303000F SW0 Software Interrupt 0 0 1 read-write SW1 Software Interrupt 1 1 1 read-write SW2 Software Interrupt 2 2 1 read-write SW3 Software Interrupt 3 3 1 read-write RAMERR1B RAM 1-Bit Error Interrupt Flag 16 1 read-write RAMERR2B RAM 2-Bit Error Interrupt Flag 17 1 read-write IEN Write to enable interrupts. 0x004 read-write 0x00000000 0x3303000F SW0 Software interrupt 0 0 1 read-write SW1 Software interrupt 1 1 1 read-write SW2 Software interrupt 2 2 1 read-write SW3 Software interrupt 3 3 1 read-write RAMERR1B RAM 1-bit Error Interrupt Enable 16 1 read-write RAMERR2B RAM 2-bit Error Interrupt Enable 17 1 read-write CHIPREVHW Read to get the hard-wired chip revision. 0x010 read-write 0x00000C01 0xFF0FFFFF MAJOR Hardwired Chip Revision Major value 0 6 read-write FAMILY Hardwired Chip Family value 6 6 read-write MINOR Hardwired Chip Revision Minor value 12 8 read-write CHIPREV Read to get the chip revision programmed by feature configuration. 0x014 read-write 0x00000000 0x000FFFFF MAJOR Chip Revision Major value 0 6 read-write FAMILY Chip Family value 6 6 read-write MINOR Chip Revision Minor value 12 8 read-write CFGSYSTIC Configure the source of the system tick for the M33. 0x020 read-write 0x00000000 0x00000001 SYSTICEXTCLKEN SysTick External Clock Enable 0 1 read-write CTRL Configure to provide general RAM configuration. 0x200 read-write 0x00000021 0x00000021 ADDRFAULTEN Invalid Address Bus Fault Response Enable 0 1 read-write RAMECCERRFAULTEN Two bit ECC Error Bus Fault Response Enable 5 1 read-write DMEM0RETNCTRL Configure to provide general RAM retention configuration. 0x208 read-write 0x00000000 0x00000003 RAMRETNCTRL DMEM0 blockset retention control 0 2 read-write ALLON None of the RAM blocks powered down 0 BLK0 Power down RAM block 0 1 BLK1 Power down RAM block 1 2 DMEM0ECCADDR Read to get status of the DMEM0 ECC error address. 0x210 read-only 0x00000000 0xFFFFFFFF DMEM0ECCADDR DMEM0 RAM ECC Error Address 0 32 read-only DMEM0ECCCTRL Configure to set RAM ECC control. 0x214 read-write 0x00000000 0x00000003 RAMECCEN RAM ECC Enable 0 1 read-write RAMECCEWEN RAM ECC Error Writeback Enable 1 1 read-write ROOTDATA0 Data in this register is passed to the trusted root firmware upon reset. 0x600 read-write 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write ROOTDATA1 Data in this register is passed to the trusted root firmware upon reset. 0x604 read-write 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write ROOTLOCKSTATUS This register returns the status of the SE managed locks. 0x608 read-only 0x011F0107 0x011F0117 BUSLOCK Bus Lock 0 1 read-only REGLOCK Register Lock 1 1 read-only MFRLOCK Manufacture Lock 2 1 read-only ROOTMODELOCK Root Mode Lock 4 1 read-only ROOTDBGLOCK Root Debug Lock 8 1 read-only USERDBGLOCK User Invasive Debug Lock 16 1 read-only USERNIDLOCK User Non-invasive Debug Lock 17 1 read-only USERSPIDLOCK User Secure Invasive Debug Lock 18 1 read-only USERSPNIDLOCK User Secure Non-invasive Debug Lock 19 1 read-only USERDBGAPLOCK User Debug Access Port Lock 20 1 read-only BURAM_S 0 BURAM_S Registers 0x40080000 0x00000000 0x00001000 registers RET0_REG No Description 0x000 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET1_REG No Description 0x004 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET2_REG No Description 0x008 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET3_REG No Description 0x00C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET4_REG No Description 0x010 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET5_REG No Description 0x014 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET6_REG No Description 0x018 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET7_REG No Description 0x01C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET8_REG No Description 0x020 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET9_REG No Description 0x024 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET10_REG No Description 0x028 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET11_REG No Description 0x02C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET12_REG No Description 0x030 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET13_REG No Description 0x034 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET14_REG No Description 0x038 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET15_REG No Description 0x03C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET16_REG No Description 0x040 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET17_REG No Description 0x044 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET18_REG No Description 0x048 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET19_REG No Description 0x04C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET20_REG No Description 0x050 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET21_REG No Description 0x054 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET22_REG No Description 0x058 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET23_REG No Description 0x05C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET24_REG No Description 0x060 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET25_REG No Description 0x064 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET26_REG No Description 0x068 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET27_REG No Description 0x06C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET28_REG No Description 0x070 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET29_REG No Description 0x074 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET30_REG No Description 0x078 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET31_REG No Description 0x07C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write GPCRC_S 0 GPCRC_S Registers 0x40088000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN CRC Enable 0 1 read-write DISABLE Disable CRC function. Reordering functions are still available. Only BITREVERSE and BYTEREVERSE bits are configurable in this mode. 0 ENABLE Writes to INPUTDATA registers will result in CRC operations. 1 CTRL No Description 0x008 read-write 0x00000000 0x00002710 POLYSEL Polynomial Select 4 1 read-write CRC32 CRC-32 (0x04C11DB7) polynomial selected 0 CRC16 16-bit CRC programmable polynomial selected 1 BYTEMODE Byte Mode Enable 8 1 read-write BITREVERSE Byte-level Bit Reverse Enable 9 1 read-write NORMAL No reverse 0 REVERSED Reverse bit order in each byte 1 BYTEREVERSE Byte Reverse Mode 10 1 read-write NORMAL No reverse: B3, B2, B1, B0 0 REVERSED Reverse byte order. For 32-bit: B0, B1, B2, B3; For 16-bit: 0, 0, B0, B1 1 AUTOINIT Auto Init Enable 13 1 read-write CMD No Description 0x00C write-only 0x00000000 0x80000001 INIT Initialization Enable 0 1 write-only INIT No Description 0x010 read-write 0x00000000 0xFFFFFFFF INIT CRC Initialization Value 0 32 read-write POLY No Description 0x014 read-write 0x00000000 0x0000FFFF POLY CRC Polynomial Value 0 16 read-write INPUTDATA No Description 0x018 write-only 0x00000000 0xFFFFFFFF INPUTDATA Input Data for 32-bit 0 32 write-only INPUTDATAHWORD No Description 0x01C write-only 0x00000000 0x0000FFFF INPUTDATAHWORD Input Data for 16-bit 0 16 write-only INPUTDATABYTE No Description 0x020 write-only 0x00000000 0x000000FF INPUTDATABYTE Input Data for 8-bit 0 8 write-only DATA No Description 0x024 read-only 0x00000000 0xFFFFFFFF DATA CRC Data Register 0 32 read-only DATAREV No Description 0x028 read-only 0x00000000 0xFFFFFFFF DATAREV Data Reverse Value 0 32 read-only DATABYTEREV No Description 0x02C read-only 0x00000000 0xFFFFFFFF DATABYTEREV Data Byte Reverse Value 0 32 read-only DCDC_S 0 DCDC_S Registers 0x40094000 0x00000000 0x00001000 registers IPVERSION IPVERSION 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IPVERSION 0 32 read-only EN Enable 0x004 read-write 0x00000000 0x00000001 EN Enable 0 1 read-write DISABLE Disable 0 ENABLE Enable 1 CTRL Control 0x008 read-write 0x00000044 0x00000077 MODE DCDC/Bypass Mode Control 0 1 read-write BYPASS DCDC is OFF, bypass switch is enabled 0 DCDCREGULATION Request DCDC regulation, bypass switch disabled 1 DCMONLYEN DCDC DCM Only Enable 2 1 read-write DUALMODE Support higher load current at lower battery voltage by working in CCM mode 0 DCMONLYEN DCM only mode for normal operation, this is the default setting 1 IPKTMAXCTRL Peak Current Timeout Control 4 3 read-write OFF Ton_max disabled 0 TMAX_0P35us 0.35us 1 TMAX_0P63us 0.63us 2 TMAX_0P91us 0.91us 3 TMAX_1P19us 1.19us 4 TMAX_1P47us 1.47us 5 TMAX_1P75us 1.75us 6 TMAX_2P03us 2.03us 7 EM01CTRL0 EM01 Configurations 0x010 read-write 0x00000109 0x0000030F IPKVAL EM01 Peak Current Setting 0 4 read-write Load36mA Ipeak = 90mA, IL = 36mA 3 Load40mA Ipeak = 100mA, IL = 40mA 4 Load44mA Ipeak = 110mA, IL = 44mA 5 Load48mA Ipeak = 120mA, IL = 48mA 6 Load52mA Ipeak = 130mA, IL = 52mA 7 Load56mA Ipeak = 140mA, IL = 56mA 8 Load60mA Ipeak = 150mA, IL = 60mA 9 DRVSPEED EM01 Drive Speed Setting 8 2 read-write BEST_EMI Lowest Efficiency, Lowest EMI.. Small decrease in efficiency from default setting 0 DEFAULT_SETTING Default Efficiency, Acceptable EMI level 1 INTERMEDIATE Small increase in efficiency from the default setting 2 BEST_EFFICIENCY Highest Efficiency, Highest EMI.. Small increase in efficiency from INTERMEDIATE setting 3 EM23CTRL0 EM23 Configurations 0x014 read-write 0x00000103 0x0000030F IPKVAL EM23 Peak Current Setting 0 4 read-write LOAD5MA Ipeak = 90mA, IL = 5 mA 3 LOAD10MA Ipeak = 150mA, IL = 10 mA 9 DRVSPEED EM23 Drive Speed Setting 8 2 read-write BEST_EMI Lowest Efficiency, Lowest EMI.. Small decrease in efficiency from default setting 0 DEFAULT_SETTING Default Efficiency, Acceptable EMI level 1 INTERMEDIATE Small increase in efficiency from the default setting 2 BEST_EFFICIENCY Highest Efficiency, Highest EMI.. Small increase in efficiency from INTERMEDIATE setting 3 IF Interrupt Flags 0x024 read-write 0x00000000 0x000000FF BYPSW Bypass Switch Enabled 0 1 read-write WARM DCDC Warmup Time Done 1 1 read-write RUNNING DCDC Running 2 1 read-write VREGINLOW VREGVDD below threshold 3 1 read-write VREGINHIGH VREGVDD above threshold 4 1 read-write REGULATION DCDC in regulation 5 1 read-write TMAX Ton_max Timeout Reached 6 1 read-write EM4ERR EM4 Entry Request Error 7 1 read-write IEN Interrupt Enable 0x028 read-write 0x00000000 0x000000FF BYPSW Bypass Switch Enabled Interrupt Enable 0 1 read-write WARM DCDC Warmup Time Done Interrupt Enable 1 1 read-write RUNNING DCDC Running Interrupt Enable 2 1 read-write VREGINLOW VREGVDD below threshold Interrupt Enable 3 1 read-write VREGINHIGH VREGVDD above threshold Interrupt Enable 4 1 read-write REGULATION DCDC in Regulation Interrupt Enable 5 1 read-write TMAX Ton_max Timeout Interrupt Enable 6 1 read-write EM4ERR EM4 Entry Req Interrupt Enable 7 1 read-write STATUS DCDC Status Register 0x02C read-only 0x00000000 0x0000001F BYPSW Bypass Switch is currently enabled 0 1 read-only WARM DCDC Warmup Done 1 1 read-only RUNNING DCDC is running 2 1 read-only VREGIN VREGVDD comparator status 3 1 read-only BYPCMPOUT Bypass Comparator Output 4 1 read-only LOCK No Description 0x040 write-only 0x00000000 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCKKEY Value to write to unlock 43981 LOCKSTATUS No Description 0x044 read-only 0x00000000 0x00000001 LOCK Lock Status 0 1 read-only UNLOCKED Unlocked State 0 LOCKED LOCKED STATE 1 PDM_S 0 PDM_S Registers 0x40098000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP VERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN PDM enable 0 1 read-write DISABLE Disable module 0 ENABLE Enable module 1 CTRL No Description 0x008 read-write 0x00000000 0x000FFF1F GAIN Selects Gain factor of DCF 0 5 read-write DSR Down sampling rate of Decimation filter 8 12 read-write CMD No Description 0x00C write-only 0x00000000 0x00010111 START Start DCF 0 1 write-only STOP Stop DCF 4 1 write-only CLEAR Clear DCF 8 1 write-only FIFOFL FIFO Flush 16 1 write-only STATUS No Description 0x010 read-only 0x00000020 0x00000731 ACT PDM is active 0 1 read-only FULL FIFO FULL Status 4 1 read-only EMPTY FIFO EMPTY Status 5 1 read-only FIFOCNT FIFO CNT 8 3 read-only CFG0 No Description 0x014 read-write 0x00000000 0x03013713 FORDER Filter order 0 2 read-write SECOND Second order filter. 0 THIRD Third order filter. 1 FOURTH Fourth order filter. 2 FIFTH Fifth order filter. 3 NUMCH Number of Channels 4 1 read-write ONE One channel. 0 TWO Two channels. 1 DATAFORMAT Filter output format 8 3 read-write RIGHT16 Right aligned 16-bit, left bits are sign extended. 0 DOUBLE16 Pack two 16-bit samples into one 32-bit word. 1 RIGHT24 Right aligned 24bit, left bits are sign extended. 2 FULL32BIT 32 bit data. 3 LEFT16 Left aligned 16-bit, right bits are zeros. 4 LEFT24 Left aligned 24-bit, right bits are zeros. 5 RAW32BIT RAW 32 bit data from Integrator. 6 FIFODVL Data Valid level in FIFO 12 2 read-write ONE Atleast one word. 0 TWO Two words. 1 THREE Three words. 2 FOUR Four words. 3 STEREOMODECH01 Stereo mode CH01 16 1 read-write DISABLE No Stereo mode. 0 CH01ENABLE CH0 and CH1 in Stereo mode. 1 CH0CLKPOL CH0 CLK Polarity 24 1 read-write NORMAL Input data clocked on rising clock edge. 0 INVERT Input data clocked on falling clock edge. 1 CH1CLKPOL CH1 CLK Polarity 25 1 read-write NORMAL Input data clocked on rising clock edge. 0 INVERT Input data clocked on falling clock edge. 1 CFG1 No Description 0x018 read-write 0x00000000 0x030003FF PRESC Prescalar Setting for PDM sample 0 10 read-write DLYMUXSEL Data delay buffer mux selection 24 2 read-write RXDATA No Description 0x020 read-only 0x00000000 0xFFFFFFFF RXDATA PDM received data 0 32 read-only IF No Description 0x040 read-write 0x00000000 0x0000000F DV Data Valid Interrupt Flag 0 1 read-write DVL Data Valid Level Interrupt Flag 1 1 read-write OF FIFO Overflow Interrupt Flag 2 1 read-write UF FIFO Undeflow Interrupt Flag 3 1 read-write IEN No Description 0x044 read-write 0x00000000 0x0000000F DV Data Valid Interrupt Enable 0 1 read-write DVL Data Valid Level Interrupt Enable 1 1 read-write OF FIFO Overflow Interrupt Enable 2 1 read-write UF FIFO Undeflow Interrupt Enable 3 1 read-write SYNCBUSY No Description 0x060 read-only 0x00000000 0x00000009 SYNCBUSY sync busy 0 1 read-only FIFOFLBUSY FIFO Flush Sync busy 3 1 read-only SMU_S 1 SMU_S Registers 0x44008000 0x00000000 0x00001000 registers SMU_SECURE 3 SMU_PRIVILEGED 4 IPVERSION The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION. 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only STATUS Read to get SMU status. 0x004 read-only 0x00000000 0x00000003 SMULOCK SMU Lock 0 1 read-only UNLOCKED SMULOCK is Unlocked 0 LOCKED SMULOCK is Locked 1 SMUPRGERR SMU Programming Error 1 1 read-only LOCK Access to Lock/unlock the SMU Configuration. 0x008 write-only 0x00000000 0x00FFFFFF SMULOCKKEY SMU Lock/Key 0 24 write-only UNLOCK Unlocks Registers 11325013 IF Read to get status of SMU interrupts. 0x00C read-write 0x00000000 0x00030005 PPUPRIV PPU Privilege Interrupt Flag 0 1 read-write PPUINST PPU Instruction Interrupt Flag 2 1 read-write PPUSEC PPU Security Interrupt Flag 16 1 read-write BMPUSEC BMPU Security Interrupt Flag 17 1 read-write IEN Write to Enable/Disable SMU interrupts. 0x010 read-write 0x00000000 0x00030005 PPUPRIV PPU Privilege Interrupt Enable 0 1 read-write PPUINST PPU Instruction Interrupt Enable 2 1 read-write PPUSEC PPU Security Interrupt Enable 16 1 read-write BMPUSEC BMPU Security Interrupt Enable 17 1 read-write M33CTRL Holds the M33 control settings. 0x020 read-write 0x00000000 0x0000001F LOCKSVTAIRCR LOCKSVTAIRCR control of M33 CPU 0 1 read-write LOCKNSVTOR LOCKNSVTOR control of M33 CPU 1 1 read-write LOCKSMPU LOCKSMPU control of M33 CPU 2 1 read-write LOCKNSMPU LOCKNSMPU control of M33 CPU 3 1 read-write LOCKSAU LOCKSAU control of M33 CPU 4 1 read-write PPUPATD0 Set peripheral bits to 1 to mark as privileged access only. 0x040 read-write 0xFFFFFFFF 0xFFFFFFFF EMU EMU Privileged Access 1 1 read-write CMU CMU Privileged Access 2 1 read-write HFXO0 HFXO0 Privileged Access 3 1 read-write HFRCO0 HFRCO0 Privileged Access 4 1 read-write FSRCO FSRCO Privileged Access 5 1 read-write DPLL0 DPLL0 Privileged Access 6 1 read-write LFXO LFXO Privileged Access 7 1 read-write LFRCO LFRCO Privileged Access 8 1 read-write ULFRCO ULFRCO Privileged Access 9 1 read-write MSC MSC Privileged Access 10 1 read-write ICACHE0 ICACHE0 Privileged Access 11 1 read-write PRS PRS Privileged Access 12 1 read-write GPIO GPIO Privileged Access 13 1 read-write LDMA LDMA Privileged Access 14 1 read-write LDMAXBAR LDMAXBAR Privileged Access 15 1 read-write TIMER0 TIMER0 Privileged Access 16 1 read-write TIMER1 TIMER1 Privileged Access 17 1 read-write TIMER2 TIMER2 Privileged Access 18 1 read-write TIMER3 TIMER3 Privileged Access 19 1 read-write TIMER4 TIMER4 Privileged Access 20 1 read-write USART0 USART0 Privileged Access 21 1 read-write USART1 USART1 Privileged Access 22 1 read-write BURTC BURTC Privileged Access 23 1 read-write I2C1 I2C1 Privileged Access 24 1 read-write CHIPTESTCTRL CHIPTESTCTRL Privileged Access 25 1 read-write SYSCFGCFGNS SYSCFGCFGNS Privileged Access 26 1 read-write SYSCFG SYSCFG Privileged Access 27 1 read-write BURAM BURAM Privileged Access 28 1 read-write GPCRC GPCRC Privileged Access 30 1 read-write DCI DCI Privileged Access 31 1 read-write PPUPATD1 Set peripheral bits to 1 to mark as privileged access only. 0x044 read-write 0x0000FFFF 0x0000FFFF DCDC DCDC Privileged Access 1 1 read-write PDM PDM Privileged Access 2 1 read-write SMU SMU Privileged Access 5 1 read-write SMUCFGNS SMUCFGNS Privileged Access 6 1 read-write RTCC RTCC Privileged Access 7 1 read-write LETIMER0 LETIMER0 Privileged Access 8 1 read-write IADC0 IADC0 Privileged Access 9 1 read-write I2C0 I2C0 Privileged Access 10 1 read-write WDOG0 WDOG0 Privileged Access 11 1 read-write AMUXCP0 AMUXCP0 Privileged Access 12 1 read-write EUART0 EUART0 Privileged Access 13 1 read-write CRYPTOACC CRYPTOACC Privileged Access 14 1 read-write PPUSATD0 Set peripheral bits to 1 to mark as secure access only. 0x060 read-write 0xFFFFFFFF 0xFFFFFFFF EMU EMU Secure Access 1 1 read-write CMU CMU Secure Access 2 1 read-write HFXO0 HFXO0 Secure Access 3 1 read-write HFRCO0 HFRCO0 Secure Access 4 1 read-write FSRCO FSRCO Secure Access 5 1 read-write DPLL0 DPLL0 Secure Access 6 1 read-write LFXO LFXO Secure Access 7 1 read-write LFRCO LFRCO Secure Access 8 1 read-write ULFRCO ULFRCO Secure Access 9 1 read-write MSC MSC Secure Access 10 1 read-write ICACHE0 ICACHE0 Secure Access 11 1 read-write PRS PRS Secure Access 12 1 read-write GPIO GPIO Secure Access 13 1 read-write LDMA LDMA Secure Access 14 1 read-write LDMAXBAR LDMAXBAR Secure Access 15 1 read-write TIMER0 TIMER0 Secure Access 16 1 read-write TIMER1 TIMER1 Secure Access 17 1 read-write TIMER2 TIMER2 Secure Access 18 1 read-write TIMER3 TIMER3 Secure Access 19 1 read-write TIMER4 TIMER4 Secure Access 20 1 read-write USART0 USART0 Secure Access 21 1 read-write USART1 USART1 Secure Access 22 1 read-write BURTC BURTC Secure Access 23 1 read-write I2C1 I2C1 Secure Access 24 1 read-write CHIPTESTCTRL CHIPTESTCTRL Secure Access 25 1 read-write SYSCFGCFGNS SYSCFGCFGNS Secure Access 26 1 read-write SYSCFG SYSCFG Secure Access 27 1 read-write BURAM BURAM Secure Access 28 1 read-write GPCRC GPCRC Secure Access 30 1 read-write DCI DCI Secure Access 31 1 read-write PPUSATD1 Set peripheral bits to 1 to mark as secure access only. 0x064 read-write 0x0000FFFF 0x0000FFFF DCDC DCDC Secure Access 1 1 read-write PDM PDM Secure Access 2 1 read-write SMU SMU Secure Access 5 1 read-write SMUCFGNS SMUCFGNS Secure Access 6 1 read-write RTCC RTCC Secure Access 7 1 read-write LETIMER0 LETIMER0 Secure Access 8 1 read-write IADC0 IADC0 Secure Access 9 1 read-write I2C0 I2C0 Secure Access 10 1 read-write WDOG0 WDOG0 Secure Access 11 1 read-write AMUXCP0 AMUXCP0 Secure Access 12 1 read-write EUART0 EUART0 Secure Access 13 1 read-write CRYPTOACC CRYPTOACC Secure Access 14 1 read-write PPUFS Read to get fault status of SMU. 0x140 read-only 0x00000000 0x000000FF PPUFSPERIPHID Peripheral ID 0 8 read-only BMPUPATD0 Set master bits to 1 to mark as a privileged master. 0x150 read-write 0x0000001F 0x0000001F CRYPTOACC CRYPTOACC DMA privileged mode 1 1 read-write LDMA MCU LDMA privileged mode 4 1 read-write BMPUSATD0 Set master bits to 1 to mark as a secure master. 0x170 read-write 0x0000001F 0x0000001F CRYPTOACC CRYPTOACC DMA secure mode 1 1 read-write LDMA MCU LDMA secure mode 4 1 read-write BMPUFS Read to get status about the master that triggered a fault. 0x250 read-only 0x00000000 0x000000FF BMPUFSMASTERID Master ID 0 8 read-only BMPUFSADDR Read to get the access address that triggered a fault. 0x254 read-only 0x00000000 0xFFFFFFFF BMPUFSADDR Fault Address 0 32 read-only ESAURTYPES0 Write to specify if a region is secure or non-secure. 0x260 read-write 0x00000000 0x00001000 ESAUR3NS Region 3 Non-Secure Type 12 1 read-write ESAURTYPES1 Write to specify if a region is secure or non-secure. 0x264 read-write 0x00000000 0x00001000 ESAUR11NS Region 11 Non-Secure Type 12 1 read-write ESAUMRB01 Specify the boundary between regions 0 and 1. 0x270 read-write 0x02000000 0x0FFFF000 ESAUMRB01 Moveable Region Boundary 0-1 12 16 read-write ESAUMRB12 Specify the boundary between regions 1 and 2. 0x274 read-write 0x04000000 0x0FFFF000 ESAUMRB12 Moveable Region Boundary 1-2 12 16 read-write ESAUMRB45 Specify the boundary between regions 4 and 5. 0x280 read-write 0x02000000 0x0FFFF000 ESAUMRB45 Moveable Region Boundary 4-5 12 16 read-write ESAUMRB56 Specify the boundary between regions 5 and 6. 0x284 read-write 0x04000000 0x0FFFF000 ESAUMRB56 Moveable Region Boundary 5-6 12 16 read-write SMU_S_CFGNS 1 SMU_S_CFGNS Registers 0x4400C000 0x00000000 0x00001000 registers SMU_SECURE 3 SMU_PRIVILEGED 4 NSSTATUS Register for status flags. 0x004 read-only 0x00000000 0x00000001 SMUNSLOCK SMUNS Lock Status 0 1 read-only UNLOCKED SMUNSLOCK Unlocked 0 LOCKED SMUNSLOCK Locked 1 NSLOCK Register used to lock/unlock access to the register file. 0x008 write-only 0x00000000 0x00FFFFFF SMUNSLOCKKEY SMU Non-Secure Lock/Key 0 24 write-only UNLOCK Unlocks Registers 11325013 NSIF Register for interrupt status flags. 0x00C read-write 0x00000000 0x00000005 PPUNSPRIVIF PPUNS Privilege Interrupt Flag 0 1 read-write PPUNSINSTIF PPUNS Instruction Interrupt Flag 2 1 read-write NSIEN Register used for enabling/disabling interrupts. 0x010 read-write 0x00000000 0x00000005 PPUNSPRIVIEN PPUNS Privilege Interrupt Enable 0 1 read-write PPUNSINSTIEN PPUNS Instruction Interrupt Enable 2 1 read-write PPUNSPATD0 Set peripheral bits to 1 to mark as privileged access only. 0x040 read-write 0x00000000 0xFFFFFFFF EMU EMU Privileged Access 1 1 read-write CMU CMU Privileged Access 2 1 read-write HFXO0 HFXO0 Privileged Access 3 1 read-write HFRCO0 HFRCO0 Privileged Access 4 1 read-write FSRCO FSRCO Privileged Access 5 1 read-write DPLL0 DPLL0 Privileged Access 6 1 read-write LFXO LFXO Privileged Access 7 1 read-write LFRCO LFRCO Privileged Access 8 1 read-write ULFRCO ULFRCO Privileged Access 9 1 read-write MSC MSC Privileged Access 10 1 read-write ICACHE0 ICACHE0 Privileged Access 11 1 read-write PRS PRS Privileged Access 12 1 read-write GPIO GPIO Privileged Access 13 1 read-write LDMA LDMA Privileged Access 14 1 read-write LDMAXBAR LDMAXBAR Privileged Access 15 1 read-write TIMER0 TIMER0 Privileged Access 16 1 read-write TIMER1 TIMER1 Privileged Access 17 1 read-write TIMER2 TIMER2 Privileged Access 18 1 read-write TIMER3 TIMER3 Privileged Access 19 1 read-write TIMER4 TIMER4 Privileged Access 20 1 read-write USART0 USART0 Privileged Access 21 1 read-write USART1 USART1 Privileged Access 22 1 read-write BURTC BURTC Privileged Access 23 1 read-write I2C1 I2C1 Privileged Access 24 1 read-write CHIPTESTCTRL CHIPTESTCTRL Privileged Access 25 1 read-write SYSCFGCFGNS SYSCFGCFGNS Privileged Access 26 1 read-write SYSCFG SYSCFG Privileged Access 27 1 read-write BURAM BURAM Privileged Access 28 1 read-write GPCRC GPCRC Privileged Access 30 1 read-write DCI DCI Privileged Access 31 1 read-write PPUNSPATD1 Set peripheral bits to 1 to mark as privileged access only. 0x044 read-write 0x00000000 0x0000FFFF DCDC DCDC Privileged Access 1 1 read-write PDM PDM Privileged Access 2 1 read-write SMU SMU Privileged Access 5 1 read-write SMUCFGNS SMUCFGNS Privileged Access 6 1 read-write RTCC RTCC Privileged Access 7 1 read-write LETIMER0 LETIMER0 Privileged Access 8 1 read-write IADC0 IADC0 Privileged Access 9 1 read-write I2C0 I2C0 Privileged Access 10 1 read-write WDOG0 WDOG0 Privileged Access 11 1 read-write AMUXCP0 AMUXCP0 Privileged Access 12 1 read-write EUART0 EUART0 Privileged Access 13 1 read-write CRYPTOACC CRYPTOACC Privileged Access 14 1 read-write PPUNSFS Read this register to query the fault status. 0x140 read-only 0x00000000 0x000000FF PPUFSPERIPHID Peripheral ID 0 8 read-only BMPUNSPATD0 Write to set BMPU priveledged attributes. 0x150 read-write 0x00000000 0x0000001F CRYPTOACC CRYPTOACC DMA privileged mode 1 1 read-write LDMA MCU LDMA privileged mode 4 1 read-write RTCC_S 1 RTCC_S Registers 0x48000000 0x00000000 0x00001000 registers RTCC 12 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP VERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN RTCC Enable 0 1 read-write CFG No Description 0x008 read-write 0x00000000 0x000000FF DEBUGRUN Debug Mode Run Enable 0 1 read-write X0 RTCC is frozen in debug mode 0 X1 RTCC is running in debug mode 1 PRECNTCCV0TOP Pre-counter CCV0 top value enable. 1 1 read-write CNTCCV1TOP CCV1 top value enable 2 1 read-write CNTTICK Counter prescaler mode. 3 1 read-write PRESC CNT register ticks according to configuration in CNTPRESC. 0 CCV0MATCH CNT register ticks when PRECNT matches RTCC_CC0_OC[14:0] 1 CNTPRESC Counter prescaler value. 4 4 read-write DIV1 CLK_CNT = (RTCC LF CLK)/1 0 DIV2 CLK_CNT = (RTCC LF CLK)/2 1 DIV4 CLK_CNT = (RTCC LF CLK)/4 2 DIV8 CLK_CNT = (RTCC LF CLK)/8 3 DIV16 CLK_CNT = (RTCC LF CLK)/16 4 DIV32 CLK_CNT = (RTCC LF CLK)/32 5 DIV64 CLK_CNT = (RTCC LF CLK)/64 6 DIV128 CLK_CNT = (RTCC LF CLK)/128 7 DIV256 CLK_CNT = (RTCC LF CLK)/256 8 DIV512 CLK_CNT = (RTCC LF CLK)/512 9 DIV1024 CLK_CNT = (RTCC LF CLK)/1024 10 DIV2048 CLK_CNT = (RTCC LF CLK)/2048 11 DIV4096 CLK_CNT = (RTCC LF CLK)/4096 12 DIV8192 CLK_CNT = (RTCC LF CLK)/8192 13 DIV16384 CLK_CNT = (RTCC LF CLK)/16384 14 DIV32768 CLK_CNT = (RTCC LF CLK)/32768 15 CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start RTCC main counter 0 1 write-only STOP Stop RTCC main counter 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x00000003 RUNNING RTCC running status 0 1 read-only RTCCLOCKSTATUS Lock Status 1 1 read-only UNLOCKED RTCC registers are unlocked 0 LOCKED RTCC registers are locked 1 IF No Description 0x014 read-write 0x00000000 0x000003FF OF Overflow Interrupt Flag 0 1 read-write CNTTICK Main counter tick 1 1 read-write CC0 CC Channel n Interrupt Flag 4 1 read-write CC1 CC Channel n Interrupt Flag 6 1 read-write CC2 CC Channel n Interrupt Flag 8 1 read-write IEN No Description 0x018 read-write 0x00000000 0x000003FF OF OF Interrupt Enable 0 1 read-write CNTTICK CNTTICK Interrupt Enable 1 1 read-write CC0 CC Channel n Interrupt Enable 4 1 read-write CC1 CC Channel n Interrupt Enable 6 1 read-write CC2 CC Channel n Interrupt Enable 8 1 read-write PRECNT No Description 0x01C read-write 0x00000000 0x00007FFF PRECNT Pre-Counter Value 0 15 read-write CNT No Description 0x020 read-write 0x00000000 0xFFFFFFFF CNT Counter Value 0 32 read-write COMBCNT No Description 0x024 read-only 0x00000000 0xFFFFFFFF PRECNT Pre-Counter Value 0 15 read-only CNTLSB Counter Value 15 17 read-only SYNCBUSY No Description 0x028 read-only 0x00000000 0x0000000F START Sync busy for START 0 1 read-only STOP Sync busy for STOP 1 1 read-only PRECNT Sync busy for PRECNT 2 1 read-only CNT Sync busy for CNT 3 1 read-only LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write to unlock RTCC lockable registers 44776 CC0_CTRL No Description 0x030 read-write 0x00000000 0x000000FF MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 CC0_OCVALUE No Description 0x034 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC0_ICVALUE No Description 0x038 read-only 0x00000000 0xFFFFFFFF IC Input Capture Value 0 32 read-only CC1_CTRL No Description 0x03C read-write 0x00000000 0x000000FF MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 CC1_OCVALUE No Description 0x040 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC1_ICVALUE No Description 0x044 read-only 0x00000000 0xFFFFFFFF IC Input Capture Value 0 32 read-only CC2_CTRL No Description 0x048 read-write 0x00000000 0x000000FF MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 CC2_OCVALUE No Description 0x04C read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC2_ICVALUE No Description 0x050 read-only 0x00000000 0xFFFFFFFF IC Input Capture Value 0 32 read-only LETIMER0_S 0 LETIMER0_S Registers 0x4A000000 0x00000000 0x00001000 registers LETIMER0 19 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN module en 0 1 read-write CTRL No Description 0x008 read-write 0x00000000 0x000F13FF REPMODE Repeat Mode 0 2 read-write FREE When started, the LETIMER counts down until it is stopped by software 0 ONESHOT The counter counts REP0 times. When REP0 reaches zero, the counter stops 1 BUFFERED The counter counts REP0 times. If REP1 has been written, it is loaded into REP0 when REP0 reaches zero, otherwise the counter stops 2 DOUBLE Both REP0 and REP1 are decremented when the LETIMER wraps around. The LETIMER counts until both REP0 and REP1 are zero 3 UFOA0 Underflow Output Action 0 2 2 read-write NONE LETIMERn_OUT0 is held at its idle value as defined by OPOL0 0 TOGGLE LETIMERn_OUT0 is toggled on CNT underflow 1 PULSE LETIMERn_OUT0 is held active for one LETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL0 2 PWM LETIMERn_OUT0 is set idle on CNT underflow, and active on compare match with COMP1 3 UFOA1 Underflow Output Action 1 4 2 read-write NONE LETIMERn_OUT1 is held at its idle value as defined by OPOL1 0 TOGGLE LETIMERn_OUT1 is toggled on CNT underflow 1 PULSE LETIMERn_OUT1 is held active for one LETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL1 2 PWM LETIMERn_OUT1 is set idle on CNT underflow, and active on compare match with COMP1 3 OPOL0 Output 0 Polarity 6 1 read-write OPOL1 Output 1 Polarity 7 1 read-write BUFTOP Buffered Top 8 1 read-write DISABLE TOP is only written by software 0 ENABLE TOP is set to TOPBUFF value when REP0 reaches 0 1 CNTTOPEN Compare Value 0 Is Top Value 9 1 read-write DISABLE The top value of the LETIMER is 16777215 (0xFFFFFF) 0 ENABLE The top value of the LETIMER is given by TOP 1 DEBUGRUN Debug Mode Run Enable 12 1 read-write DISABLE LETIMER is frozen in debug mode 0 ENABLE LETIMER is running in debug mode 1 CNTPRESC Counter prescaler value 16 4 read-write DIV1 CLK_CNT = (LETIMER LF CLK)/1 0 DIV2 CLK_CNT = (LETIMER LF CLK)/2 1 DIV4 CLK_CNT = (LETIMER LF CLK)/4 2 DIV8 CLK_CNT = (LETIMER LF CLK)/8 3 DIV16 CLK_CNT = (LETIMER LF CLK)/16 4 DIV32 CLK_CNT = (LETIMER LF CLK)/32 5 DIV64 CLK_CNT = (LETIMER LF CLK)/64 6 DIV128 CLK_CNT = (LETIMER LF CLK)/128 7 DIV256 CLK_CNT = (LETIMER LF CLK)/256 8 CMD No Description 0x00C write-only 0x00000000 0x0000001F START Start LETIMER 0 1 write-only STOP Stop LETIMER 1 1 write-only CLEAR Clear LETIMER 2 1 write-only CTO0 Clear Toggle Output 0 3 1 write-only CTO1 Clear Toggle Output 1 4 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x00000001 RUNNING LETIMER Running 0 1 read-only CNT No Description 0x018 read-write 0x00000000 0x00FFFFFF CNT Counter Value 0 24 read-write COMP0 No Description 0x01C read-write 0x00000000 0x00FFFFFF COMP0 Compare Value 0 0 24 read-write COMP1 No Description 0x020 read-write 0x00000000 0x00FFFFFF COMP1 Compare Value 1 0 24 read-write TOP No Description 0x024 read-write 0x00000000 0x00FFFFFF TOP Counter TOP Value 0 24 read-write TOPBUFF No Description 0x028 read-write 0x00000000 0x00FFFFFF TOPBUFF Buffered Counter TOP Value 0 24 read-write REP0 No Description 0x02C read-write 0x00000000 0x000000FF REP0 Repeat Counter 0 0 8 read-write REP1 No Description 0x030 read-write 0x00000000 0x000000FF REP1 Repeat Counter 1 0 8 read-write IF No Description 0x034 read-write 0x00000000 0x0000001F COMP0 Compare Match 0 Interrupt Flag 0 1 read-write COMP1 Compare Match 1 Interrupt Flag 1 1 read-write UF Underflow Interrupt Flag 2 1 read-write REP0 Repeat Counter 0 Interrupt Flag 3 1 read-write REP1 Repeat Counter 1 Interrupt Flag 4 1 read-write IEN No Description 0x038 read-write 0x00000000 0x0000001F COMP0 Compare Match 0 Interrupt Enable 0 1 read-write COMP1 Compare Match 1 Interrupt Enable 1 1 read-write UF Underflow Interrupt Enable 2 1 read-write REP0 Repeat Counter 0 Interrupt Enable 3 1 read-write REP1 Repeat Counter 1 Interrupt Enable 4 1 read-write SYNCBUSY No Description 0x040 read-only 0x00000000 0x000003FD CNT Sync busy for CNT 0 1 read-only TOP Sync busy for TOP 2 1 read-only REP0 Sync busy for REP0 3 1 read-only REP1 Sync busy for REP1 4 1 read-only START Sync busy for START 5 1 read-only STOP Sync busy for STOP 6 1 read-only CLEAR Sync busy for CLEAR 7 1 read-only CTO0 Sync busy for CTO0 8 1 read-only CTO1 Sync busy for CTO1 9 1 read-only PRSMODE No Description 0x050 read-write 0x00000000 0x0CCC0000 PRSSTARTMODE PRS Start Mode 18 2 read-write NONE PRS cannot start the LETIMER 0 RISING Rising edge of selected PRS input can start the LETIMER 1 FALLING Falling edge of selected PRS input can start the LETIMER 2 BOTH Both the rising or falling edge of the selected PRS input can start the LETIMER 3 PRSSTOPMODE PRS Stop Mode 22 2 read-write NONE PRS cannot stop the LETIMER 0 RISING Rising edge of selected PRS input can stop the LETIMER 1 FALLING Falling edge of selected PRS input can stop the LETIMER 2 BOTH Both the rising or falling edge of the selected PRS input can stop the LETIMER 3 PRSCLEARMODE PRS Clear Mode 26 2 read-write NONE PRS cannot clear the LETIMER 0 RISING Rising edge of selected PRS input can clear the LETIMER 1 FALLING Falling edge of selected PRS input can clear the LETIMER 2 BOTH Both the rising or falling edge of the selected PRS input can clear the LETIMER 3 IADC0_S 1 IADC0_S Registers 0x4A004000 0x00000000 0x00001000 registers IADC 48 IPVERSION IPVERSION 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only EN Enable 0x004 read-write 0x00000000 0x00000001 EN Enable IADC Module 0 1 read-write DISABLE Disable 0 ENABLE Enable 1 CTRL Control 0x008 read-write 0x00000000 0x707F003F EM23WUCONVERT EM23 Wakeup on Conversion 0 1 read-write WUDVL When using suspend mode, conversions performed in EM2 or EM3 should not wake up the DMA until the FIFO's DVL setting is reached. This saves more power for large OSR settings or infrequent sampling. 0 WUCONVERT When using suspend mode, conversions performed in EM2 or EM3 will wake up the DMA and keep it awake until the conversions are done, regardless of the DVL setting. This mode burns more power, but it is useful when the conversion rate is faster than the time for the DMA to cycle through wake up and going back to sleep as it converts more than 4 scan table entries. Without using the wake up on conversion mode, the FIFO may overflow while the DMA is going in and out of sleep. 1 ADCCLKSUSPEND0 ADC_CLK Suspend - PRS0 1 1 read-write PRSWUDIS Normal mode which does not disable the ADC_CLK. 0 PRSWUEN ADCCLKWUEN will gate off ADC_CLK until the trigger is detected provided the internal timer is not selected as the trigger. Once the trigger is detected the ADC_CLK will be started, the band gap will be started, the ADC will be warmed up, and the SCAN Table and the Single entry will be converted. Once the conversions are done, the ADC_CLK will be gated off. 1 ADCCLKSUSPEND1 ADC_CLK Suspend - PRS1 2 1 read-write PRSWUDIS Normal mode which does not disable the ADC_CLK. 0 PRSWUEN ADCCLKWUEN will gate off ADC_CLK until the trigger is detected provided the internal timer is not selected as the trigger. Once the trigger is detected the ADC_CLK will be started, the band gap will be started, the ADC will be warmed up, and the SCAN Table and the Single entry will be converted. Once the conversions are done, the ADC_CLK will be gated off. 1 DBGHALT Debug Halt 3 1 read-write NORMAL Continue operation as normal during debug mode 0 HALT Complete the current conversion and then halt during debug mode 1 WARMUPMODE Warmup Mode 4 2 read-write NORMAL Shut down the IADC after conversions have completed. 0 KEEPINSTANDBY Switch to standby mode after conversions have completed. The next warmup time will require 1us. 1 KEEPWARM Keep IADC fully powered after conversions have completed. 2 TIMEBASE Time Base 16 7 read-write HSCLKRATE High Speed Clock Rate 28 3 read-write DIV1 Use CMU_CLK_ADC directly. The source clock must be 40 MHz or less. 0 DIV2 Divide CMU_CLK_ADC by 2 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 1 DIV3 Divide CMU_CLK_ADC by 3 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 2 DIV4 Divide CMU_CLK_ADC by 4 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 3 CMD Command 0x00C write-only 0x00000000 0x0303001B SINGLESTART Single Queue Start 0 1 write-only SINGLESTOP Single Queue Stop 1 1 write-only SCANSTART Scan Queue Start 3 1 write-only SCANSTOP Scan Queue Stop 4 1 write-only TIMEREN Timer Enable 16 1 write-only TIMERDIS Timer Disable 17 1 write-only SINGLEFIFOFLUSH Flush the Single FIFO 24 1 write-only SCANFIFOFLUSH Flush the Scan FIFO 25 1 write-only TIMER Timer 0x010 read-write 0x00000000 0x0000FFFF TIMER Timer Period 0 16 read-write STATUS Status 0x014 read-only 0x00000000 0x4131CF5B SINGLEQEN Single Queue Enabled 0 1 read-only SINGLEQUEUEPENDING Single Queue Pending 1 1 read-only SCANQEN Scan Queued Enabled 3 1 read-only SCANQUEUEPENDING Scan Queue Pending 4 1 read-only CONVERTING Converting 6 1 read-only SINGLEFIFODV SINGLEFIFO Data Valid 8 1 read-only SCANFIFODV SCANFIFO Data Valid 9 1 read-only SINGLEFIFOFLUSHING The Single FIFO is flushing 14 1 read-only SCANFIFOFLUSHING The Scan FIFO is flushing 15 1 read-only TIMERACTIVE Timer Active 16 1 read-only SINGLEWRITEPENDING SINGLE write pending 20 1 read-only MASKREQWRITEPENDING MASKREQ write pending 21 1 read-only SYNCBUSY SYNCBUSY 24 1 read-only ADCWARM ADCWARM 30 1 read-only MASKREQ Mask Request 0x018 read-write 0x00000000 0x0000FFFF MASKREQ Scan Queue Mask Request 0 16 read-write STMASK Scan Table Mask 0x01C read-only 0x00000000 0x0000FFFF STMASK Scan Table Mask 0 16 read-only CMPTHR Comparator Threshold 0x020 read-write 0x00000000 0xFFFFFFFF ADLT ADC Less Than or Equal to Threshold 0 16 read-write ADGT ADC Greater Than or Equal to Threshold 16 16 read-write IF Interrupt Flag 0x024 read-write 0x00000000 0x800F338F SINGLEFIFODVL Single FIFO Data Valid Level 0 1 read-write SCANFIFODVL Scan FIFO Data Valid Level 1 1 read-write SINGLECMP Single Result Window Compare 2 1 read-write SCANCMP Scan Result Window Compare 3 1 read-write SCANENTRYDONE Scan Entry Done 7 1 read-write SCANTABLEDONE Scan Table Done 8 1 read-write SINGLEDONE Single Conversion Done 9 1 read-write POLARITYERR Polarity Error 12 1 read-write PORTALLOCERR Port Allocation Error 13 1 read-write SINGLEFIFOOF Single FIFO Overflow 16 1 read-write SCANFIFOOF Scan FIFO Overflow 17 1 read-write SINGLEFIFOUF Single FIFO Underflow 18 1 read-write SCANFIFOUF Scan FIFO Underflow 19 1 read-write EM23ABORTERROR EM2/3 Abort Error 31 1 read-write IEN Interrupt Enable 0x028 read-write 0x00000000 0x800F338F SINGLEFIFODVL Single FIFO Data Valid Level Enable 0 1 read-write SCANFIFODVL Scan FIFO Data Valid Level Enable 1 1 read-write SINGLECMP Single Result Window Compare Enable 2 1 read-write SCANCMP Scan Result Window Compare Enable 3 1 read-write SCANENTRYDONE Scan Entry Done Enable 7 1 read-write SCANTABLEDONE Scan Table Done Enable 8 1 read-write SINGLEDONE Single Conversion Done Enable 9 1 read-write POLARITYERR Polarity Error Enable 12 1 read-write PORTALLOCERR Port Allocation Error Enable 13 1 read-write SINGLEFIFOOF Single FIFO Overflow Enable 16 1 read-write SCANFIFOOF Scan FIFO Overflow Enable 17 1 read-write SINGLEFIFOUF Single FIFO Underflow Enable 18 1 read-write SCANFIFOUF Scan FIFO Underflow Enable 19 1 read-write EM23ABORTERROR EM2/3 Abort Error Enable 31 1 read-write TRIGGER Trigger 0x02C read-write 0x00000000 0x00011717 SCANTRIGSEL Scan Trigger Select 0 3 read-write IMMEDIATE Immediate triggering. The scan queue will be disabled once all conversions in the scan table are complete, unless TRIGGERACTION is set to continuous. 0 TIMER Triggers when the local timer count reaches zero. 1 PRSCLKGRP Triggers on PRS0 from a timer module that is using the same clock group as the ADC and has been programmed to use the same clock source as the ADC. The prescale may be different between the ADC and the timer module. 2 PRSPOS Triggers on asynchronous PRS0 positive edge. Requires PRS0 to go low for 3 ADC_CLKs before another positive edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. 3 PRSNEG Triggers on asynchronous PRS0 negative edge. Requires PRS0 to go high for 3 ADC_CLKs before another negative edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. PRSNEG should only be used when the trigger source is from a module that remains powered during EM23. For modules (ie: TIMER) that power down during EM23, PRSPOS should be used for an asynchronous trigger, and PRSCLKGRP should be used for a synchronous trigger. 4 SCANTRIGACTION Scan Trigger Action 4 1 read-write ONCE For TRIGSEL=IMMEDIATE, goes through the scan table once and disables queue. For TRIGSEL = TIMER, PRSCLKGRP, PRSPOS, PRSNEG, goes through the scan table once per trigger. 0 CONTINUOUS Goes through the scan table, converts each entry with a mask bit set, and puts it back into the scan queue to repeat again continuously. The queues are first come first serve. If both queues are triggered, the single queue will get to convert after each scan table completes. The scan queue will get to convert after each single conversion completes. 1 SINGLETRIGSEL Single Trigger Select 8 3 read-write IMMEDIATE Immediate triggering. The single queue will be disabled once the conversion is complete, unless TRIGGERACTION is set to continuous. 0 TIMER Triggers when the local timer count reaches zero. 1 PRSCLKGRP Triggers on PRS1 from a timer module that is using the same clock group as the ADC and has been programmed to use the same clock source as the ADC. The prescale may be different between the ADC and the timer module. 2 PRSPOS Triggers on asynchronous PRS1 positive edge. Requires PRS1 to go low for 3 ADC_CLKs before another positive edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. 3 PRSNEG Triggers on asynchronous PRS1 negative edge. Requires PRS1 to go high for 3 ADC_CLKs before another negative edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. PRSNEG should only be used when the trigger source is from a module that remains powered during EM23. For modules (ie: TIMER) that power down during EM23, PRSPOS should be used for an asynchronous trigger, and PRSCLKGRP should be used for a synchronous trigger. 4 SINGLETRIGACTION Single Trigger Action 12 1 read-write ONCE For TRIGSEL=IMMEDIATE, converts the single queue once and disables queue. For TRIGSEL = TIMER, PRSCLKGRP, PRSPOS, PRSNEG, converts the single queue once per trigger.ask. 0 CONTINUOUS Converts the single queue, then checks for a pending scan queue before converting the single queue again continuously. The queues are first come first serve. If both queues are continuous, the IADC alternates between them. 1 SINGLETAILGATE Single Tailgate Enable 16 1 read-write TAILGATEOFF The single queue is ready to start warming up and converting once the trigger had been detected. 0 TAILGATEON After the single queue's trigger is detected, it must wait until the end of a scan operation before the Single queue can be converted. 1 CFG0 Configration 0x048 read-write 0x00002060 0x30E770FF ADCMODE ADC Mode 0 2 read-write NORMAL High speed mode with a maximum CLK_ADC of 10 MHz. 0 OSRHS High Speed OSR 2 3 read-write HISPD2 High speed over sampling of 2x. 0 HISPD4 High speed over sampling of 4x. 1 HISPD8 High speed over sampling of 8x. 2 HISPD16 High speed over sampling of 16x. 3 HISPD32 HIgh speed over sampling of 32x. 4 HISPD64 High speed over sampling of 64x. 5 ANALOGGAIN Analog Gain 12 3 read-write ANAGAIN0P5 Analog gain of 0.5x. 1 ANAGAIN1 Analog gain of 1x. 2 ANAGAIN2 Analog gain of 2x. 3 ANAGAIN3 Analog gain of 3x. 4 ANAGAIN4 Analog gain of 4x. 5 REFSEL Reference Select 16 3 read-write VBGR Internal 1.21 V reference. 0 VREF External Reference. (Calibrated for 1.25V nominal.) 1 VDDX AVDD (unbuffered) 3 VDDX0P8BUF AVDD (buffered) * 0.8 4 DIGAVG Digital Averaging 21 3 read-write AVG1 Collect one output word (no digital averaging). 0 AVG2 Collect and average 2 digital output words. 1 AVG4 Collect and average 4 digital output words. 2 AVG8 Collect and average 8 digital output words. 3 AVG16 Collect and average 16 digital output words. 4 TWOSCOMPL Two's Complement 28 2 read-write AUTO Automatic: Single ended measurements are reported as unipolar and differential measurements are reported as bipolar. 0 FORCEUNIPOLAR Force all measurements to result in unipolar output. Negative differential numbers will saturate to 0. 1 FORCEBIPOLAR Force all measurements to result in bipolar output. Single ended measurements are half the range, but allow for small negative measurements. 2 SCALE0 Scale 0x050 read-write 0x8002C000 0xFFFFFFFF OFFSET Offset 0 18 read-write GAIN13LSB Gain 13 LSBs 18 13 read-write GAIN3MSB Gain 3 MSBs 31 1 read-write GAIN011 Upper 3 bits of gain = 011 (0.75x) 0 GAIN100 Upper 3 bits of gain = 100 (1.00x) 1 SCHED0 Scheduling 0x054 read-write 0x00000000 0x000003FF PRESCALE Prescale 0 10 read-write CFG1 Configration 0x058 read-write 0x00002060 0x30E770FF ADCMODE ADC Mode 0 2 read-write NORMAL High speed mode with a maximum CLK_ADC of 10 MHz. 0 OSRHS High Speed OSR 2 3 read-write HISPD2 High speed over sampling of 2x. 0 HISPD4 High speed over sampling of 4x. 1 HISPD8 High speed over sampling of 8x. 2 HISPD16 High speed over sampling of 16x. 3 HISPD32 HIgh speed over sampling of 32x. 4 HISPD64 High speed over sampling of 64x. 5 ANALOGGAIN Analog Gain 12 3 read-write ANAGAIN0P5 Analog gain of 0.5x. 1 ANAGAIN1 Analog gain of 1x. 2 ANAGAIN2 Analog gain of 2x. 3 ANAGAIN3 Analog gain of 3x. 4 ANAGAIN4 Analog gain of 4x. 5 REFSEL Reference Select 16 3 read-write VBGR Internal 1.21 V reference. 0 VREF External Reference. (Calibrated for 1.25V nominal.) 1 VDDX AVDD (unbuffered) 3 VDDX0P8BUF AVDD (buffered) * 0.8 4 DIGAVG Digital Averaging 21 3 read-write AVG1 Collect one output word (no digital averaging). 0 AVG2 Collect and average 2 digital output words. 1 AVG4 Collect and average 4 digital output words. 2 AVG8 Collect and average 8 digital output words. 3 AVG16 Collect and average 16 digital output words. 4 TWOSCOMPL Two's Complement 28 2 read-write AUTO Automatic: Single ended measurements are reported as unipolar and differential measurements are reported as bipolar. 0 FORCEUNIPOLAR Force all measurements to result in unipolar output. Negative differential numbers will saturate to 0. 1 FORCEBIPOLAR Force all measurements to result in bipolar output. Single ended measurements are half the range, but allow for small negative measurements. 2 SCALE1 Scale 0x060 read-write 0x8002C000 0xFFFFFFFF OFFSET Offset 0 18 read-write GAIN13LSB Gain 13 LSBs 18 13 read-write GAIN3MSB Gain 3 MSBs 31 1 read-write GAIN011 Upper 3 bits of gain = 011 (0.75x) 0 GAIN100 Upper 3 bits of gain = 100 (1.00x) 1 SCHED1 Scheduling 0x064 read-write 0x00000000 0x000003FF PRESCALE Prescale 0 10 read-write SINGLEFIFOCFG Single FIFO Configuration 0x070 read-write 0x00000030 0x0000013F ALIGNMENT Alignment 0 3 read-write RIGHT12 ID[7:0], SIGN_EXT, DATA[11:0] 0 RIGHT16 ID[7:0], SIGN_EXT, DATA[15:0] 1 RIGHT20 ID[7:0], SIGN_EXT, DATA[19:0] 2 LEFT12 DATA[11:0], 000000000000, ID[7:0] 3 LEFT16 DATA[15:0], 00000000, ID[7:0] 4 LEFT20 DATA[19:0], 0000, ID[7:0] 5 SHOWID Show ID 3 1 read-write DVL Data Valid Level 4 2 read-write VALID1 When 1 entry in the single FIFO is valid, set the SINGLEFIFODVL interrupt and request DMA. 0 VALID2 When 2 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 1 VALID3 When 3 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 2 VALID4 When 4 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 3 DMAWUFIFOSINGLE Single FIFO DMA wakeup. 8 1 read-write DISABLED While in EM2 or EM3, the DMA controller will not be requested. 0 ENABLED While in EM2 or EM3, the DMA controller will be requested when the single FIFO reaches its Data Valid Level. [DVL must be set to 0 (VALID1).] 1 SINGLEFIFODATA Read the oldest valid data from the single FIFO and pop the FIFO 0x074 read-only 0x00000000 0xFFFFFFFF DATA Single FIFO Read Data 0 32 read-only SINGLEFIFOSTAT Single FIFO status 0x078 read-only 0x00000000 0x00000007 FIFOREADCNT FIFO Read Count 0 3 read-only SINGLEDATA latest single queue conversion data 0x07C read-only 0x00000000 0xFFFFFFFF DATA Data 0 32 read-only SCANFIFOCFG Scan FIFO Configuration 0x080 read-write 0x00000030 0x0000013F ALIGNMENT Alignment 0 3 read-write RIGHT12 ID[7:0], SIGN_EXT, DATA[11:0] 0 RIGHT16 ID[7:0], SIGN_EXT, DATA[15:0] 1 RIGHT20 ID[7:0], SIGN_EXT, DATA[19:0] 2 LEFT12 DATA[11:0], 000000000000, ID[7:0] 3 LEFT16 DATA[15:0], 00000000, ID[7:0] 4 LEFT20 DATA[19:0], 0000, ID[7:0] 5 SHOWID Show ID 3 1 read-write DVL Data Valid Level 4 2 read-write VALID1 When 1 entry in the scan FIFO is valid, set the SCANFIFODVL interrupt and request DMA. 0 VALID2 When 2 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA. 1 VALID3 When 3 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA. 2 VALID4 When 4 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA. 3 DMAWUFIFOSCAN Scan FIFO DMA Wakeup 8 1 read-write DISABLED While in EM2 or EM3, the DMA controller will not be requested. 0 ENABLED While in EM2 or EM3, the DMA controller will be requested when the scan FIFO reaches its Data Valid Level. [DVL must be set to 0 (VALID1).] 1 SCANFIFODATA Read the oldest valid data from the scan FIFO and pop the FIFO 0x084 read-only 0x00000000 0xFFFFFFFF DATA Data 0 32 read-only SCANFIFOSTAT Scan FIFO status 0x088 read-only 0x00000000 0x00000007 FIFOREADCNT FIFO Read Count 0 3 read-only SCANDATA Most recent data data from scan queue conversion 0x08C read-only 0x00000000 0xFFFFFFFF DATA Data 0 32 read-only SINGLE No Description 0x098 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN0 No Description 0x0A0 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN1 No Description 0x0A4 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN2 No Description 0x0A8 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN3 No Description 0x0AC read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN4 No Description 0x0B0 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN5 No Description 0x0B4 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN6 No Description 0x0B8 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN7 No Description 0x0BC read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN8 No Description 0x0C0 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN9 No Description 0x0C4 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN10 No Description 0x0C8 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN11 No Description 0x0CC read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN12 No Description 0x0D0 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN13 No Description 0x0D4 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN14 No Description 0x0D8 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN15 No Description 0x0DC read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write I2C0_S 0 I2C0_S Registers 0x4A010000 0x00000000 0x00001000 registers I2C0 27 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN module enable 0 1 read-write DISABLE Disable Peripheral Clock 0 ENABLE Enable Peripheral Clock 1 CTRL No Description 0x008 read-write 0x00000000 0x0037B3FF CORERST Soft Reset the internal state registers 0 1 read-write DISABLE No change to internal state registers 0 ENABLE Reset the internal state registers 1 SLAVE Addressable as Follower 1 1 read-write DISABLE All addresses will be responded to with a NACK 0 ENABLE Addresses matching the programmed follower address or the general call address (if enabled) require a response from software. Other addresses are automatically responded to with a NACK. 1 AUTOACK Automatic Acknowledge 2 1 read-write DISABLE Software must give one ACK command for each ACK transmitted on the I2C bus. 0 ENABLE Addresses that are not automatically NACK'ed, and all data is automatically acknowledged. 1 AUTOSE Automatic STOP when Empty 3 1 read-write DISABLE A stop must be sent manually when no more data is to be transmitted. 0 ENABLE The leader automatically sends a STOP when no more data is available for transmission. 1 AUTOSN Automatic STOP on NACK 4 1 read-write DISABLE Stop is not automatically sent if a NACK is received from a follower. 0 ENABLE The leader automatically sends a STOP if a NACK is received from a follower. 1 ARBDIS Arbitration Disable 5 1 read-write DISABLE When a device loses arbitration, the ARBIF interrupt flag is set and the bus is released. 0 ENABLE When a device loses arbitration, the ARBIF interrupt flag is set, but communication proceeds. 1 GCAMEN General Call Address Match Enable 6 1 read-write DISABLE General call address will be NACK'ed if it is not included by the follower address and address mask. 0 ENABLE When a general call address is received, a software response is required 1 TXBIL TX Buffer Interrupt Level 7 1 read-write EMPTY TXBL status and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALF_FULL TXBL status and the TXBL interrupt flag are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full 1 CLHR Clock Low High Ratio 8 2 read-write STANDARD Nlow=4 and Nhigh=4, and the Nlow:Nhigh ratio is 4:4 0 ASYMMETRIC Nlow=6 and Nhigh=3, and the Nlow:Nhigh ratio is 6:3 1 FAST Nlow=11 and Nhigh=6, and the Nlow:Nhigh ratio is 11:6 2 BITO Bus Idle Timeout 12 2 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 GIBITO Go Idle on Bus Idle Timeout 15 1 read-write DISABLE A bus idle timeout has no effect on the bus state. 0 ENABLE A bus idle timeout tells the I2C module that the bus is idle, allowing new transfers to be initiated. 1 CLTO Clock Low Timeout 16 3 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 I2C320PCC Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout. 4 I2C1024PCC Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout. 5 SCLMONEN SCL Monitor Enable 20 1 read-write DISABLE Disable SCL monitor 0 ENABLE Enable SCL monitor 1 SDAMONEN SDA Monitor Enable 21 1 read-write DISABLE Disable SDA Monitor 0 ENABLE Enable SDA Monitor 1 CMD No Description 0x00C write-only 0x00000000 0x000000FF START Send start condition 0 1 write-only STOP Send stop condition 1 1 write-only ACK Send ACK 2 1 write-only NACK Send NACK 3 1 write-only CONT Continue transmission 4 1 write-only ABORT Abort transmission 5 1 write-only CLEARTX Clear TX 6 1 write-only CLEARPC Clear Pending Commands 7 1 write-only STATE No Description 0x010 read-only 0x00000001 0x000000FF BUSY Bus Busy 0 1 read-only MASTER Leader 1 1 read-only TRANSMITTER Transmitter 2 1 read-only NACKED Nack Received 3 1 read-only BUSHOLD Bus Held 4 1 read-only STATE Transmission State 5 3 read-only IDLE No transmission is being performed. 0 WAIT Waiting for idle. Will send a start condition as soon as the bus is idle. 1 START Start transmit phase 2 ADDR Address transmit or receive phase 3 ADDRACK Address ack/nack transmit or receive phase 4 DATA Data transmit or receive phase 5 DATAACK Data ack/nack transmit or receive phase 6 STATUS No Description 0x014 read-only 0x00000080 0x00000FFF PSTART Pending START 0 1 read-only PSTOP Pending STOP 1 1 read-only PACK Pending ACK 2 1 read-only PNACK Pending NACK 3 1 read-only PCONT Pending continue 4 1 read-only PABORT Pending abort 5 1 read-only TXC TX Complete 6 1 read-only TXBL TX Buffer Level 7 1 read-only RXDATAV RX Data Valid 8 1 read-only RXFULL RX FIFO Full 9 1 read-only TXBUFCNT TX Buffer Count 10 2 read-only CLKDIV No Description 0x018 read-write 0x00000000 0x000001FF DIV Clock Divider 0 9 read-write SADDR No Description 0x01C read-write 0x00000000 0x000000FE ADDR Follower address 1 7 read-write SADDRMASK No Description 0x020 read-write 0x00000000 0x000000FE SADDRMASK Follower Address Mask 1 7 read-write RXDATA No Description 0x024 read-only 0x00000000 0x000000FF RXDATA RX Data 0 8 read-only RXDOUBLE No Description 0x028 read-only 0x00000000 0x0000FFFF RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDATAP No Description 0x02C read-only 0x00000000 0x000000FF RXDATAP RX Data Peek 0 8 read-only RXDOUBLEP No Description 0x030 read-only 0x00000000 0x0000FFFF RXDATAP0 RX Data 0 Peek 0 8 read-only RXDATAP1 RX Data 1 Peek 8 8 read-only TXDATA No Description 0x034 write-only 0x00000000 0x000000FF TXDATA TX Data 0 8 write-only TXDOUBLE No Description 0x038 write-only 0x00000000 0x0000FFFF TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only IF No Description 0x03C read-write 0x00000000 0x001FFFFF START START condition Interrupt Flag 0 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write ADDR Address Interrupt Flag 2 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write ACK Acknowledge Received Interrupt Flag 6 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write MSTOP Leader STOP Condition Interrupt Flag 8 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write SSTOP Follower STOP condition Interrupt Flag 16 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write IEN No Description 0x040 read-write 0x00000000 0x001FFFFF START START condition Interrupt Flag 0 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write ADDR Address Interrupt Flag 2 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write ACK Acknowledge Received Interrupt Flag 6 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write MSTOP Leader STOP Condition Interrupt Flag 8 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write SSTOP Follower STOP condition Interrupt Flag 16 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write WDOG0_S 0 WDOG0_S Registers 0x4A018000 0x00000000 0x00001000 registers WDOG0 43 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Module Enable 0 1 read-write CFG No Description 0x008 read-write 0x000F0000 0x730F071F CLRSRC WDOG Clear Source 0 1 read-write SW A write to the clear bit will clear the WDOG counter 0 PRSSRC0 A rising edge on the PRS Source 0 will clear the WDOG counter 1 EM2RUN EM2 Run 1 1 read-write DISABLE WDOG timer is frozen in EM2. 0 ENABLE WDOG timer is running in EM2. 1 EM3RUN EM3 Run 2 1 read-write DISABLE WDOG timer is frozen in EM3. 0 ENABLE WDOG timer is running in EM3. 1 EM4BLOCK EM4 Block 3 1 read-write DISABLE EM4 can be entered by software. See EMU for detailed description. 0 ENABLE EM4 cannot be entered by software. 1 DEBUGRUN Debug Mode Run 4 1 read-write DISABLE WDOG timer is frozen in debug mode 0 ENABLE WDOG timer is running in debug mode 1 WDOGRSTDIS WDOG Reset Disable 8 1 read-write EN A timeout will cause a WDOG reset 0 DIS A timeout will not cause a WDOG reset 1 PRS0MISSRSTEN PRS Src0 Missing Event WDOG Reset 9 1 read-write PRS1MISSRSTEN PRS Src1 Missing Event WDOG Reset 10 1 read-write PERSEL WDOG Timeout Period Select 16 4 read-write SEL0 Timeout period of 9 wdog cycles 0 SEL1 Timeout period of 17 wdog cycles 1 SEL2 Timeout period of 33 wdog cycles 2 SEL3 Timeout period of 65 wdog cycles 3 SEL4 Timeout period of 129 wdog cycles 4 SEL5 Timeout period of 257 wdog cycles 5 SEL6 Timeout period of 513 wdog cycles 6 SEL7 Timeout period of 1k wdog cycles 7 SEL8 Timeout period of 2k wdog cycles 8 SEL9 Timeout period of 4k wdog cycles 9 SEL10 Timeout period of 8k wdog cycles 10 SEL11 Timeout period of 16k wdog cycles 11 SEL12 Timeout period of 32k wdog cycles 12 SEL13 Timeout period of 64k wdog cycles 13 SEL14 Timeout period of 128k wdog cycles 14 SEL15 Timeout period of 256k wdog cycles 15 WARNSEL WDOG Warning Period Select 24 2 read-write DIS Disable 0 SEL1 Warning timeout is 25% of the Timeout. 1 SEL2 Warning timeout is 50% of the Timeout. 2 SEL3 Warning timeout is 75% of the Timeout. 3 WINSEL WDOG Illegal Window Select 28 3 read-write DIS Disabled. 0 SEL1 Window timeout is 12.5% of the Timeout. 1 SEL2 Window timeout is 25% of the Timeout. 2 SEL3 Window timeout is 37.5% of the Timeout. 3 SEL4 Window timeout is 50% of the Timeout. 4 SEL5 Window timeout is 62.5% of the Timeout. 5 SEL6 Window timeout is 75.5% of the Timeout. 6 SEL7 Window timeout is 87.5% of the Timeout. 7 CMD No Description 0x00C write-only 0x00000000 0x00000001 CLEAR WDOG Timer Clear 0 1 write-only UNCHANGED WDOG timer is unchanged. 0 CLEARED WDOG timer is cleared to 0. 1 STATUS No Description 0x014 read-only 0x00000000 0x80000000 LOCK WDOG Configuration Lock Status 31 1 read-only UNLOCKED All WDOG lockable registers are unlocked. 0 LOCKED All WDOG lockable registers are locked. 1 IF No Description 0x018 read-write 0x00000000 0x0000001F TOUT WDOG Timeout Interrupt Flag 0 1 read-write WARN WDOG Warning Timeout Interrupt Flag 1 1 read-write WIN WDOG Window Interrupt Flag 2 1 read-write PEM0 PRS Src0 Event Missing Interrupt Flag 3 1 read-write PEM1 PRS Src1 Event Missing Interrupt Flag 4 1 read-write IEN No Description 0x01C read-write 0x00000000 0x0000001F TOUT WDOG Timeout Interrupt Enable 0 1 read-write WARN WDOG Warning Timeout Interrupt Enable 1 1 read-write WIN WDOG Window Interrupt Enable 2 1 read-write PEM0 PRS Src0 Event Missing Interrupt Enable 3 1 read-write PEM1 PRS Src1 Event Missing Interrupt Enable 4 1 read-write LOCK No Description 0x020 write-only 0x0000ABE8 0x0000FFFF LOCKKEY WDOG Configuration Lock 0 16 write-only LOCK Lock WDOG lockable registers 0 UNLOCK Unlock WDOG lockable registers 44008 SYNCBUSY No Description 0x024 read-only 0x00000000 0x00000001 CMD Sync Busy for Cmd Register 0 1 read-only AMUXCP0_S 1 AMUXCP0_S Registers 0x4A020000 0x00000000 0x00001000 registers IPVERSION IPVERSION 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IPVERSION 0 32 read-only CTRL Control 0x008 read-write 0x00000000 0x00000033 FORCEHP Force High Power 0 1 read-write FORCELP Force Low Power 1 1 read-write FORCERUN Force run 4 1 read-write FORCESTOP Force stop 5 1 read-write STATUS Status 0x00C read-only 0x00000000 0x00000003 RUN running 0 1 read-only HICAP high cap 1 1 read-only TEST Test 0x010 read-write 0x00000000 0x80003313 SYNCCLK Sync Clock 0 1 read-write SYNCMODE Sync Mode 1 1 read-write FORCEREQUEST Force Request 4 1 read-write FORCEHICAP Force high capacitance driver 8 1 read-write FORCELOCAP Force low capacitance driver 9 1 read-write FORCEBOOSTON Force Boost On 12 1 read-write FORCEBOOSTOFF Force Boost Off 13 1 read-write STATUSEN Enable write to status bits 31 1 read-write TRIM Trim 0x014 read-write 0x77E44AA1 0x77FFEFFF WARMUPTIME Warm up time 0 2 read-write WUCYCLES72 Warm up cycle = 72; 3.6us @20 MHz 0 WUCYCLES96 Warm up cycle = 96; 4.8us @ 20 MHz 1 WUCYCLES128 Warm up cycle = 128; 6.4us @ 20 MHz 2 WUCYCLES160 Warm up cycle = 160; 8.0us @ 20 MHz 3 FLOATVDDCPLO Float VDDCP Low Power 2 1 read-write FLOATVDDCPHI Float VDDCP High Power 3 1 read-write BYPASSDIV2LO Bypass Div2 Low Power 4 1 read-write BYPASSDIV2HI Bypass Div2 High Power 5 1 read-write BUMP0P5XLO Bump 0.5X Low Power 6 1 read-write BUMP0P5XHI Bump 0.5X High Power 7 1 read-write BIAS2XLO Bias 2x Low Power 8 1 read-write BIAS2XHI Bias 2x High Power 9 1 read-write VOLTAGECTRLLO Charge Pump Voltage Control Low Power 10 2 read-write VOLTAGECTRLHI Charge Pump Voltage Control High Power 13 2 read-write BIASCTRLLO Bias Control Low Power 15 3 read-write BIASCTRLLOCONT Bias Control Low Power Continuous 18 3 read-write BIASCTRLHI Bias Control High Power 21 3 read-write PUMPCAPLO Pump Cap Low Power 24 3 read-write PUMPCAPHI Pump Cap High Power 28 3 read-write EUART0_S 0 EUART0_S Registers 0x4A030000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Module enable 0 1 read-write CFG0 No Description 0x008 read-write 0x00000000 0xC1D264FE LOOPBK Loopback Enable 1 1 read-write DISABLE The receiver is connected to and receives data from UARTn_RX 0 ENABLE The receiver is connected to and receives data from UARTn_TX 1 CCEN Collision Check Enable 2 1 read-write DISABLE Collision check is disabled 0 ENABLE Collision check is enabled. The receiver must be enabled for the check to be performed 1 MPM Multi-Processor Mode 3 1 read-write DISABLE The 9th bit of incoming frames has no special function 0 ENABLE An incoming frame with the 9th bit equal to MPAB will be loaded into the RX FIFO regardless of RXBLOCK and will result in the MPAB interrupt flag being set 1 MPAB Multi-Processor Address-Bit 4 1 read-write OVS Oversampling 5 3 read-write X16 16X oversampling 0 X8 8X oversampling 1 X6 6X oversampling 2 X4 4X oversampling 3 DISABLE Disable oversampling (for LF operation) 4 MSBF Most Significant Bit First 10 1 read-write DISABLE Data is sent with the least significant bit first 0 ENABLE Data is sent with the most significant bit first 1 RXINV Receiver Input Invert 13 1 read-write DISABLE Input is passed directly to the receiver 0 ENABLE Input is inverted before it is passed to the receiver 1 TXINV Transmitter output Invert 14 1 read-write DISABLE Output from the transmitter is passed unchanged to UARTn_TX 0 ENABLE Output from the transmitter is inverted before it is passed to UARTn_TX 1 AUTOTRI Automatic TX Tristate 17 1 read-write DISABLE The output on UARTn_TX when the transmitter is idle is defined by TXINV 0 ENABLE UARTn_TX is tristated whenever the transmitter is idle 1 SKIPPERRF Skip Parity Error Frames 20 1 read-write ERRSDMA Halt DMA Read On Error 22 1 read-write DISABLE Framing and parity errors have no effect on DMA requests from the UART 0 ENABLE DMA requests from the UART are blocked while the PERR or FERR interrupt flags are set 1 ERRSRX Disable RX On Error 23 1 read-write DISABLE Framing and parity errors have no effect on receiver 0 ENABLE Framing and parity errors disable the receiver 1 ERRSTX Disable TX On Error 24 1 read-write DISABLE Received framing and parity errors have no effect on transmitter 0 ENABLE Received framing and parity errors disable the transmitter 1 MVDIS Majority Vote Disable 30 1 read-write AUTOBAUDEN AUTOBAUD detection enable 31 1 read-write CFG1 No Description 0x00C read-write 0x00000000 0x00DB8E0F DBGHALT Debug halt 0 1 read-write DISABLE Continue normal UART operation even if core is halted 0 ENABLE If core is halted, receive one frame and then halt reception by deactivating RTS. Next frame reception happens when the core is unhalted during single stepping. 1 CTSINV Clear-to-send Invert Enable 1 1 read-write DISABLE The CTS pin is active low 0 ENABLE The CTS pin is active high 1 CTSEN Clear-to-send Enable 2 1 read-write DISABLE Ignore CTS 0 ENABLE Stop transmitting when CTS is inactive 1 RTSINV Request-to-send Invert Enable 3 1 read-write DISABLE The RTS pin is active low 0 ENABLE The RTS pin is active high 1 TXDMAWU Transmitter DMA Wakeup 9 1 read-write RXDMAWU Receiver DMA Wakeup 10 1 read-write SFUBRX Start Frame Unblock Receiver 11 1 read-write RXPRSEN PRS RX Enable 15 1 read-write TXFIW TX FIFO Interrupt Watermark 16 2 read-write ONEFRAME TXFL status flag and IF are set when the TX FIFO has space for at least one more frame. 0 TWOFRAMES TXFL status flag and IF are set when the TX FIFO has space for at least two more frames. 1 THREEFRAMES TXFL status flag and IF are set when the TX FIFO has space for at least three more frames. 2 FOURFRAMES TXFL status flag and IF are set when the TX FIFO has space for at least four more frames. 3 RXFIW RX FIFO Interrupt Watermark 19 2 read-write ONEFRAME RXFL status flag and IF are set when the RX FIFO has at least one frame in it. 0 TWOFRAMES RXFL status flag and IF are set when the RX FIFO has at least two frames in it. 1 THREEFRAMES RXFL status flag and IF are set when the RX FIFO has at least three frames in it. 2 FOURFRAMES RXFL status flag and IF are set when the RX FIFO has four frames in it. 3 RTSRXFW Request-to-send RX FIFO Watermark 22 2 read-write ONEFRAME RTS is set if there is space for at least one more frame in the RX FIFO. 0 TWOFRAMES RTS is set if there is space for at least two more frames in the RX FIFO. 1 THREEFRAMES RTS is set if there is space for at least three more frames in the RX FIFO. 2 FOURFRAMES RTS is set if there is space for four more frames in the RX FIFO. 3 FRAMECFG No Description 0x010 read-write 0x00001002 0x00003303 DATABITS Data-Bit Mode 0 2 read-write SEVEN Each frame contains 7 data bits 1 EIGHT Each frame contains 8 data bits 2 NINE Each frame contains 9 data bits 3 PARITY Parity-Bit Mode 8 2 read-write NONE Parity bits are not used 0 EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. 2 ODD Odd parity is used. Parity bits are automatically generated and checked by hardware. 3 STOPBITS Stop-Bit Mode 12 2 read-write HALF The transmitter generates a half stop bit. Stop-bits are not verified by receiver 0 ONE One stop bit is generated and verified 1 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies the first stop bit 2 TWO The transmitter generates two stop bits. The receiver checks the first stop-bit only 3 IRHFCFG No Description 0x014 read-write 0x00000000 0x0000000F IRHFEN Enable IrDA Module 0 1 read-write IRHFPW IrDA TX Pulse Width 1 2 read-write ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 0 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 2 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 3 IRHFFILT IrDA RX Filter 3 1 read-write DISABLE No filter enabled 0 ENABLE Filter enabled. IrDA pulse must be high for at least 4 consecutive clock cycles to be detected 1 IRLFCFG No Description 0x018 read-write 0x00000000 0x00000001 IRLFEN Pulse Generator/Extender Enable 0 1 read-write TIMINGCFG No Description 0x01C read-write 0x00000000 0x00000003 TXDELAY TX Delay Transmission 0 2 read-write NONE Frames are transmitted immediately. 0 SINGLE Transmission of new frames is delayed by a single bit period. 1 DOUBLE Transmission of new frames is delayed by a two bit periods. 2 TRIPPLE Transmission of new frames is delayed by a three bit periods. 3 STARTFRAMECFG No Description 0x020 read-write 0x00000000 0x000001FF STARTFRAME Start Frame 0 9 read-write SIGFRAMECFG No Description 0x024 read-write 0x00000000 0x000001FF SIGFRAME Signal Frame Value 0 9 read-write CLKDIV No Description 0x028 read-write 0x00000000 0x007FFFF8 DIV Fractional Clock Divider 3 20 read-write TRIGCTRL No Description 0x02C read-write 0x00000000 0x00000003 RXTEN Receive Trigger Enable 0 1 read-write TXTEN Transmit Trigger Enable 1 1 read-write CMD No Description 0x030 write-only 0x00000000 0x000001FF RXEN Receiver Enable 0 1 write-only RXDIS Receiver Disable 1 1 write-only TXEN Transmitter Enable 2 1 write-only TXDIS Transmitter Disable 3 1 write-only RXBLOCKEN Receiver Block Enable 4 1 write-only RXBLOCKDIS Receiver Block Disable 5 1 write-only TXTRIEN Transmitter Tristate Enable 6 1 write-only TXTRIDIS Transmitter Tristate Disable 7 1 write-only CLEARTX Clear TX FIFO 8 1 write-only RXDATA No Description 0x034 read-only 0x00000000 0x000007FF RXDATA RX Data 0 9 read-only PERR Parity Error 9 1 read-only FERR Framing Error 10 1 read-only RXDATAP No Description 0x038 read-only 0x00000000 0x000007FF RXDATAP RX Data Peek 0 9 read-only PERRP Parity Error Peek 9 1 read-only FERRP Framing Error Peek 10 1 read-only TXDATA No Description 0x03C write-only 0x00000000 0x00003FFF TXDATA TX Data 0 9 write-only UBRXAT Unblock RX After Transmission 9 1 write-only TXTRIAT Set TXTRI After Transmisssion 10 1 write-only TXBREAK Transit Data as Break 11 1 write-only TXDISAT Clear TXEN After Transmission 12 1 write-only RXENAT Enable RXEN After Transmission 13 1 write-only STATUS No Description 0x040 read-only 0x00003040 0x010F31FB RXENS Receiver Enable Status 0 1 read-only TXENS Transmitter Enable Status 1 1 read-only RXBLOCK Block Incoming Data 3 1 read-only TXTRI Transmitter Tristated 4 1 read-only TXC TX Complete 5 1 read-only TXFL TX FIFO Level 6 1 read-only RXFL RX FIFO Level 7 1 read-only RXFULL RX FIFO Full 8 1 read-only RXIDLE RX Idle 12 1 read-only TXIDLE TX Idle 13 1 read-only TXFCNT Valid entries in TX FIFO 16 3 read-only CLEARTXBUSY TX FIFO Clear Busy 19 1 read-only AUTOBAUDDONE Auto Baud Rate Detection Completed 24 1 read-only IF No Description 0x044 read-write 0x00000000 0x010C377F TXC TX Complete Interrupt Flag 0 1 read-write TXFL TX FIFO Level Interrupt Flag 1 1 read-write RXFL RX FIFO Level Interrupt Flag 2 1 read-write RXFULL RX FIFO Full Interrupt Flag 3 1 read-write RXOF RX FIFO Overflow Interrupt Flag 4 1 read-write RXUF RX FIFO Underflow Interrupt Flag 5 1 read-write TXOF TX FIFO Overflow Interrupt Flag 6 1 read-write PERR Parity Error Interrupt Flag 8 1 read-write FERR Framing Error Interrupt Flag 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write CCF Collision Check Fail Interrupt Flag 12 1 read-write TXIDLE TX Idle Interrupt Flag 13 1 read-write STARTF Start Frame Interrupt Flag 18 1 read-write SIGF Signal Frame Interrupt Flag 19 1 read-write AUTOBAUDDONE Auto Baud Complete Interrupt Flag 24 1 read-write IEN No Description 0x048 read-write 0x00000000 0x010C377F TXC TX Complete IEN 0 1 read-write TXFL TX FIFO Level IEN 1 1 read-write RXFL RX FIFO Level IEN 2 1 read-write RXFULL RX FIFO Full IEN 3 1 read-write RXOF RX FIFO Overflow IEN 4 1 read-write RXUF RX FIFO Underflow IEN 5 1 read-write TXOF TX FIFO Overflow IEN 6 1 read-write PERR Parity Error IEN 8 1 read-write FERR Framing Error IEN 9 1 read-write MPAF Multi-Processor Addr Frame IEN 10 1 read-write CCF Collision Check Fail IEN 12 1 read-write TXIDLE TX IDLE IEN 13 1 read-write STARTF Start Frame IEN 18 1 read-write SIGF Signal Frame IEN 19 1 read-write AUTOBAUDDONE Auto Baud Complete IEN 24 1 read-write SYNCBUSY No Description 0x04C read-only 0x00000000 0x000007FF DIV SYNCBUSY for DIV in CLKDIV 0 1 read-only RXTEN SYNCBUSY for RXTEN in TRIGCTRL 1 1 read-only TXTEN SYNCBUSY for TXTEN in TRIGCTRL 2 1 read-only RXEN SYNCBUSY for RXEN in CMD 3 1 read-only RXDIS SYNCBUSY for RXDIS in CMD 4 1 read-only TXEN SYNCBUSY for TXEN in CMD 5 1 read-only TXDIS SYNCBUSY for TXDIS in CMD 6 1 read-only RXBLOCKEN SYNCBUSY for RXBLOCKEN in CMD 7 1 read-only RXBLOCKDIS SYNCBUSY for RXBLOCKDIS in CMD 8 1 read-only TXTRIEN SYNCBUSY for TXTRIEN in CMD 9 1 read-only TXTRIDIS SYNCBUSY in TXTRIDIS in CMD 10 1 read-only CRYPTOACC_S 1 CRYPTOACC_S Registers 0x4C020000 0x00000000 0x00001000 registers CRYPTOACC 0 TRNG 1 PKE 2 FETCHADDR Fetcher: Start address of data block. In direct mode, this register is written by the software. In scatter-gather mode, this register is updated after each processed descriptor. 0x000 read-write 0x00000000 0xFFFFFFFF ADDR Start address of data block 0 32 read-write FETCHLEN Fetcher: Length of data block. In direct mode, this register is written by the software. In scatter-gather mode, this register is not used. 0x008 read-write 0x00000000 0x3FFFFFFF LENGTH Length of data block 0 28 read-write CONSTADDR Constant address 28 1 read-write REALIGN Realign length 29 1 read-write FETCHTAG Fetcher: User tag. In direct mode, this register is written by the software. In scatter-gather mode, this register is not used. 0x00C read-write 0x00000000 0xFFFFFFFF TAG User tag 0 32 read-write PUSHADDR Pusher: Start address of data block (LSB). In direct mode, this register is written by the software. In scatter-gather mode, this register is updated after each processed descriptor. 0x010 read-write 0x00000000 0xFFFFFFFF ADDR Start address of data block 0 32 read-write PUSHLEN Pusher: Length of data block. In direct mode, this register is written by the software. In scatter-gather mode, this register is not used. 0x018 read-write 0x00000000 0x7FFFFFFF LENGTH Start address of data block 0 28 read-write CONSTADDR Constant address 28 1 read-write REALIGN Realign length 29 1 read-write DISCARD Discard data 30 1 read-write IEN Interrupt enable 0x01C read-write 0x00000000 0x0000003F FETCHERENDOFBLOCK End of block interrupt enable 0 1 read-write FETCHERSTOPPED Stopped interrupt enable 1 1 read-write FETCHERERROR Error interrupt enable 2 1 read-write PUSHERENDOFBLOCK End of block interrupt enable 3 1 read-write PUSHERSTOPPED Stopped interrupt enable 4 1 read-write PUSHERERROR Error interrupt enable 5 1 read-write IF Interrupt flag register 0x028 read-only 0x00000000 0x0000003F FETCHERENDOFBLOCK End of block interrupt flag 0 1 read-only FETCHERSTOPPED Stopped interrupt flag 1 1 read-only FETCHERERROR Error interrupt flag 2 1 read-only PUSHERENDOFBLOCK End of block interrupt flag 3 1 read-only PUSHERSTOPPED Stopped interrupt flag 4 1 read-only PUSHERERROR Error interrupt flag 5 1 read-only IF_CLR Writing a '1' clears the interrupt status. Writing a '0' has no effect. 0x030 write-only 0x00000000 0x0000003F FETCHERENDOFBLOCK End of block interrupt flag clear 0 1 write-only FETCHERSTOPPED Stopped interrupt flag clear 1 1 write-only FETCHERERROR Error interrupt flag clear 2 1 write-only PUSHERENDOFBLOCK End of block interrupt flag clear 3 1 write-only PUSHERSTOPPED Stopped interrupt flag clear 4 1 write-only PUSHERERROR Error interrupt flag clear 5 1 write-only CTRL Control register, called CONFIG in Barco datasheet. 0x034 read-write 0x00000000 0x0000001F FETCHERSCATTERGATHER Fetcher scatter/gather 0 1 read-write PUSHERSCATTERGATHER Pusher scatter/gather 1 1 read-write STOPFETCHER Stop fetcher 2 1 read-write STOPPUSHER Stop pusher 3 1 read-write SWRESET Software reset 4 1 read-write CMD Command register for starting the fetcher and pusher 0x038 write-only 0x00000000 0x00000003 STARTFETCHER Start fetch 0 1 write-only STARTPUSHER Start push 1 1 write-only STATUS Status register 0x03C read-only 0x00000000 0xFFFF0073 FETCHERBSY Fetcher busy 0 1 read-only PUSHERBSY Pusher busy 1 1 read-only NOTEMPTY Not empty flag from input FIFO (fetcher) 4 1 read-only WAITING Pusher waiting for FIFO 5 1 read-only SOFTRSTBSY Software reset busy 6 1 read-only FIFODATANUM Number of data in output FIFO 16 16 read-only INCL_IPS_HW_CFG No Description 0x400 read-only 0x00000611 0x000007FF g_IncludeAES Generic g_IncludeAES value 0 1 read-only g_IncludeAESGCM Generic g_IncludeAESGCM value 1 1 read-only g_IncludeAESXTS Generic g_IncludeAESXTS value 2 1 read-only g_IncludeDES Generic g_IncludeDES value 3 1 read-only g_IncludeHASH Generic g_IncludeHASH value 4 1 read-only g_IncludeChachaPoly Generic g_IncludeChachaPoly value 5 1 read-only g_IncludeSHA3 Generic g_IncludeSHA3 value 6 1 read-only g_IncludeZUC Generic g_IncludeZUC value 7 1 read-only g_IncludeSM4 Generic g_IncludeSM4 value 8 1 read-only g_IncludePKE Generic g_IncludePKE value 9 1 read-only g_IncludeNDRNG Generic g_IncludeNDRNG value 10 1 read-only BA411E_HW_CFG_1 No Description 0x404 read-only 0x0700017F 0x070301FF g_AesModesPoss AES Modes Supported 0 9 read-only g_CS Generic g_CS value 16 1 read-only g_UseMasking Generic g_UseMasking value 17 1 read-only g_Keysize Generic g_Keysize value 24 3 read-only BA411E_HW_CFG_2 No Description 0x408 read-only 0x00000080 0x0000FFFF g_CtrSize Generic g_CtrSize value 0 16 read-only BA413_HW_CFG No Description 0x40C read-only 0x0003007F 0x0007007F g_HashMaskFunc Generic g_HashMaskFunc value 0 7 read-only g_HashPadding Generic g_HashPadding value 16 1 read-only g_HMAC_enabled Generic g_HMAC_enabled value 17 1 read-only g_HashVerifyDigest Generic g_HashVerifyDigest value 18 1 read-only BA418_HW_CFG No Description 0x410 read-only 0x00000001 0x00000001 g_Sha3CtxtEn Generic g_Sha3CtxtEn value 0 1 read-only BA419_HW_CFG No Description 0x414 read-only 0x0000005F 0x0000007F g_SM4ModesPoss Generic g_SM4ModesPoss value 0 7 read-only CRYPTOACC_S_RNGCTRL 1 CRYPTOACC_S_RNGCTRL Registers 0x4C021000 0x00000000 0x00001000 registers CRYPTOACC 0 TRNG 1 PKE 2 RNGCTRL No Description 0x000 read-write 0x00040000 0x001FFFFF ENABLE TRNG Module Enable 0 1 read-write DISABLED Module disabled 0 ENABLED Module enabled 1 TESTEN Test Enable 2 1 read-write NOISE Non-determinsitc random number generation 0 TESTDATA Pseudo-random number generation 1 CONDBYPASS Conditioning Bypass 3 1 read-write NORMAL The conditionig function is used 0 BYPASS The conditioning function is bypassed 1 REPCOUNTIEN IRQ enable for Repetition Count Test 4 1 read-write APT64IEN IRQ enable for APT64IF 5 1 read-write APT4096IEN IRQ enable for APT4096IF 6 1 read-write FULLIEN IRQ enable for FIFO full 7 1 read-write SOFTRESET Software Reset 8 1 read-write NORMAL Module not in reset 0 RESET The continuous test, the conditioning function and the FIFO are reset 1 PREIEN IRQ enable for AIS31 prelim. noise alarm 9 1 read-write ALMIEN IRQ enable for AIS31 noise alarm 10 1 read-write FORCERUN Oscillator Force Run 11 1 read-write NORMAL Oscillators will shut down when FIFO is full 0 RUN Oscillators will continue to run even after FIFO is full 1 BYPNIST NIST Start-up Test Bypass. 12 1 read-write NORMAL NIST-800-90B startup test is applied. No data will be written to the FIFO until the test passes. 0 BYPASS NIST-800-90B startup test is bypassed. 1 BYPAIS31 AIS31 Start-up Test Bypass. 13 1 read-write NORMAL AIS31 startup test is applied. No data will be written to the FIFO until the test passes. 0 BYPASS AIS31 startup test is bypassed. 1 HEALTHTESTSEL Health test input select 14 1 read-write BEFORE Before conditioning 0 AFTER After conditioning 1 AIS31TESTSEL AIS31 test input select 15 1 read-write BEFORE Before conditioning 0 AFTER After conditioning 1 NB128BITBLOCKS Number of 128b blocks in AES-CBCMAC 16 4 read-write FIFOWRSTARTUP Fifo Write Start Up 20 1 read-write FIFOLEVEL Number of 32 bits words of random available in the FIFO. Writing to this register clears the FIFO full interrupt 0x004 read-only 0x00000000 0xFFFFFFFF FIFOLEVEL FIFO Level 0 32 read-only FIFOTHRESH FIFO level at which the rings are restarted when in the FIFOFull_Off state, expressed in number of 128bit blocks 0x008 read-only 0x0000003F 0xFFFFFFFF FIFOTHRESH FIFO threshold level 0 32 read-only FIFODEPTH Maximum number of 32 bits words that can be stored in the FIFO: 2^g_fifodepth 0x00C read-only 0x00000040 0xFFFFFFFF FIFODEPTH FIFO Depth. 0 32 read-only KEY0 This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011... 0x010 read-write 0x00000000 0xFFFFFFFF KEY Key 0 32 read-write KEY1 This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011... 0x014 read-write 0x00000000 0xFFFFFFFF KEY Key 0 32 read-write KEY2 This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011... 0x018 read-write 0x00000000 0xFFFFFFFF KEY Key 0 32 read-write KEY3 This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011... 0x01C read-write 0x00000000 0xFFFFFFFF KEY Key 0 32 read-write TESTDATA This register is used to feed known data to the conditioning function or to the continuous tests. See manual 0x020 write-only 0x00000000 0xFFFFFFFF VALUE Test data input to conditioning tests 0 32 write-only RNGSTATUS No Description 0x030 read-write 0x00000000 0x000007FF TESTDATABUSY Test Data Busy 0 1 read-only IDLE TESTDATA write is finished processing or no test in progress. 0 BUSY TESTDATA write is still being processed. 1 STATE State of the control FSM 1 3 read-only RESET RESET State 0 STARTUP STARTUP State 1 FIFOFULLON FIFOFULLON State 2 FIFOFULLOFF FIFOFULLOFF State 3 RUNNING RUNNING State 4 ERROR ERROR State 5 UNUSED_6 UNUSED 6 UNUSED_7 UNUSED 7 REPCOUNTIF Repetition Count Test interrupt status 4 1 read-only APT64IF 64-sample window Adaptive Proportion IF 5 1 read-only APT4096IF 4096-sample window Adaptive Prop. IF 6 1 read-only FULLIF FIFO full interrupt status 7 1 read-only PREIF AIS31 Preliminary Noise Alarm IF 8 1 read-write ALMIF AIS31 Noise Alarm interrupt status 9 1 read-only INITWAITVAL No Description 0x034 read-write 0x0000FFFF 0x0000FFFF INITWAITVAL Wait counter value 0 16 read-write SWOFFTMRVAL Number of clk cycles to wait before stopping the rings after the FIFO is full 0x040 read-write 0x0000FFFF 0x0000FFFF SWOFFTMRVAL Switch Off Timer Value 0 16 read-write CLKDIV Sample clock divider. The frequency at which the outputs of the rings are sampled is given by Fs = Fpclk/(ClkDiv + 1) 0x044 read-write 0x00000000 0x000000FF VALUE Sample clock divider 0 8 read-write AIS31CONF0 No Description 0x048 read-write 0x43401040 0x7FFF7FFF STARTUPTHRES Start-up Threshold 0 15 read-write ONLINETHRESH Online Threshold 16 15 read-write AIS31CONF1 No Description 0x04C read-write 0x03C00680 0x7FFF7FFF HEXPECTEDVALUE Expected History Value 0 15 read-write ONLINEREPTHRESH Online Repeat Threshold 16 15 read-write AIS31CONF2 No Description 0x050 read-write 0x04400340 0x7FFF7FFF HMIN Minimum Allowed History Value 0 15 read-write HMAX Maximum Allowed History Value 16 15 read-write AIS31STATUS This register is used to obtain diagnostic information about the AIS31 start-up and online tests when g_AIS31=True. Writing to this register clears all fields 0x054 read-write 0x00000000 0x0003FFFF NUMPRELIMALARMS Number of preliminary alarms 0 16 read-write PRELIMNOISEALARMRNG Preliminary noise alarm RNG 16 1 read-write PRELIMNOISEALARMREP Preliminary noise alarm Rep 17 1 read-write CRYPTOACC_S_PKCTRL 1 CRYPTOACC_S_PKCTRL Registers 0x4C022000 0x00000000 0x00001000 registers CRYPTOACC 0 TRNG 1 PKE 2 POINTER No Description 0x000 read-write 0x00000000 0x0F0F0F0F OPPTRA OpPtrA 0 4 read-write OPPTRB OpPtrB 8 4 read-write OPPTRC OpPtrC 16 4 read-write OPPTRN OpPtrN 24 4 read-write COMMAND No Description 0x004 read-write 0x00000000 0xFC77FFFF OPERATION Type of Operation 0 7 read-write FIELD Field 7 1 read-write GFP Field is GF(p) 0 GF2M Field is GF(2^m) 1 SIZE Size of Operands in data memory 8 11 read-write SELCURVE Select Curve 20 3 read-write NONE No acceleration 0 P256 P256 1 P192 P192 4 EDWARDS Edwards Curve Enable 26 1 read-write BUFSEL Buffer Select 27 1 read-write MEM0 use data in data memory 0 0 SWAPBYTES Swap bytes 28 1 read-write NATIVE Native format (little endian) 0 SWAPPED Byte swapped (big endian) 1 FLAGA Flag A 29 1 read-write FLAGB Flag B 30 1 read-write CALCR2 Calculate R2 31 1 read-write FALSE don't recalculate R² mod N 0 TRUE re-calculate R² mod N 1 PKCTRL No Description 0x008 write-only 0x00000000 0x00000003 PKSTART PK Start 0 1 write-only IFC ClearIRQ 1 1 write-only PKSTATUS No Description 0x00C read-only 0x00000000 0x00033FFF FAILADDR Fail Address 0 4 read-only NOTONCURVE Point Px not on curve 4 1 read-only ATINFINITY Point Px at infinity 5 1 read-only COUPLENOTVALID Couple not valid 6 1 read-only PARAMNNOTVALID Param n not valid 7 1 read-only NOTIMPLEMENTED Not implemented 8 1 read-only SIGNOTVALID Signature not valid 9 1 read-only PARAMABNOTVALID Param AB not valid 10 1 read-only NOTINVERTIBLE Not invertible 11 1 read-only COMPOSITE Composite 12 1 read-only FALSE random number under test is probably prime 0 TRUE random number under test is composite 1 NOTQUAD Not quadratic residue 13 1 read-only PKBUSY PK busy 16 1 read-only PKIF Interrupt status 17 1 read-only VERSION No Description 0x010 read-only 0x00000000 0x0000FFFF SW Software version number 0 8 read-only HW Hardware version number 8 8 read-only TIMER No Description 0x014 read-only 0x00000000 0xFFFFFFFF TIMER Timer 0 32 read-only EMU_NS 1 EMU_NS Registers 0x50004000 0x00000000 0x00001000 registers EMU 6 EMUDG 29 EMUSE 30 DECBOD No Description 0x010 read-write 0x00000022 0x00000033 DECBODEN DECBOD enable 0 1 read-write DECBODMASK DECBOD Mask 1 1 read-write DECOVMBODEN Over Voltage Monitor enable 4 1 read-write DECOVMBODMASK Over Voltage Monitor Mask 5 1 read-write BOD3SENSE No Description 0x020 read-write 0x00000000 0x00000077 AVDDBODEN AVDD BOD enable 0 1 read-write VDDIO0BODEN VDDIO0 BOD enable 1 1 read-write VDDIO1BODEN VDDIO1 BOD enable 2 1 read-write VREGVDDCMPCTRL No Description 0x03C read-write 0x00000006 0x00000007 VREGINCMPEN VREGVDD comparator enable 0 1 read-write THRESSEL VREGVDD comparator threshold programming 1 2 read-write PD1PARETCTRL No Description 0x040 read-write 0x00000000 0x0000FFFF PD1PARETDIS Disable PD1 Partial Retention 0 16 read-write RETAIN Retain associated registers when in EM2/3 0 NORETAIN Do not retain associcated registers when in EM2/3 1 LOCK No Description 0x060 write-only 0x0000ADE8 0x0000FFFF LOCKKEY Lock Key 0 16 write-only UNLOCK Unlock EMU register 44520 IF No Description 0x064 read-write 0x00000000 0xEB070000 AVDDBOD AVDD BOD Interrupt flag 16 1 read-write IOVDD0BOD VDDIO0 BOD Interrupt flag 17 1 read-write EM23WAKEUP EM23 Wake up Interrupt flag 24 1 read-write VSCALEDONE Vscale done Interrupt flag 25 1 read-write TEMPAVG Temperature Average Interrupt flag 27 1 read-write TEMP Temperature Interrupt flag 29 1 read-write TEMPLOW Temperature low Interrupt flag 30 1 read-write TEMPHIGH Temperature high Interrupt flag 31 1 read-write IEN No Description 0x068 read-write 0x00000000 0xEB070000 AVDDBOD AVDD BOD Interrupt enable 16 1 read-write IOVDD0BOD VDDIO0 BOD Interrupt enable 17 1 read-write EM23WAKEUP EM23 Wake up Interrupt enable 24 1 read-write VSCALEDONE Vscale done Interrupt enable 25 1 read-write TEMPAVG Temperature Interrupt enable 27 1 read-write TEMP Temperature Interrupt enable 29 1 read-write TEMPLOW Temperature low Interrupt enable 30 1 read-write TEMPHIGH Temperature high Interrupt enable 31 1 read-write EM4CTRL No Description 0x06C read-write 0x00000000 0x00000133 EM4ENTRY EM4 entry request 0 2 read-write EM4IORETMODE EM4 IO retention mode 4 2 read-write DISABLE No Retention: Pads enter reset state when entering EM4 0 EM4EXIT Retention through EM4: Pads enter reset state when exiting EM4 1 SWUNLATCH Retention through EM4 and Wakeup: software writes UNLATCH register to remove retention 2 BOD3SENSEEM4WU Set BOD3SENSE as EM4 wakeup 8 1 read-write CMD No Description 0x070 write-only 0x00000000 0x00020E12 EM4UNLATCH EM4 unlatch 1 1 write-only TEMPAVGREQ Temperature Average Request 4 1 write-only EM01VSCALE1 Scale voltage to Vscale1 10 1 write-only EM01VSCALE2 Scale voltage to Vscale2 11 1 write-only RSTCAUSECLR Reset Cause Clear 17 1 write-only CTRL No Description 0x074 read-write 0x00000200 0xE0010309 EM2DBGEN Enable debugging in EM2 0 1 read-write TEMPAVGNUM Averaged Temperature samples num 3 1 read-write N16 16 measurements 0 N64 64 measurements 1 EM23VSCALE EM2/EM3 Vscale 8 2 read-write VSCALE0 VSCALE0. 0.9v 0 VSCALE1 VSCALE1. 1.0v 1 VSCALE2 VSCALE2. 1.1v 2 FLASHPWRUPONDEMAND Enable flash on demand wakeup 16 1 read-write EFPDIRECTMODEEN EFP Direct Mode Enable 29 1 read-write EFPDRVDECOUPLE EFP drives DECOUPLE 30 1 read-write EFPDRVDVDD EFP drives DVDD 31 1 read-write TEMPLIMITS No Description 0x078 read-write 0x01FF0000 0x01FF01FF TEMPLOW Temp Low limit 0 9 read-write TEMPHIGH Temp High limit 16 9 read-write STATUS No Description 0x084 read-only 0x00000080 0xFF0054FF LOCK Lock status 0 1 read-only UNLOCKED All EMU lockable registers are unlocked. 0 LOCKED All EMU lockable registers are locked. 1 FIRSTTEMPDONE First Temp done 1 1 read-only TEMPACTIVE Temp active 2 1 read-only TEMPAVGACTIVE Temp Average active 3 1 read-only VSCALEBUSY Vscale busy 4 1 read-only VSCALEFAILED Vscale failed 5 1 read-only VSCALE Vscale status 6 2 read-only VSCALE0 Voltage scaling set to 0.9v 0 VSCALE1 Voltage scaling set to 1.0v 1 VSCALE2 Voltage scaling set to 1.1v 2 EM4IORET EM4 IO retention status 12 1 read-only EM2ENTERED EM2 entered 14 1 read-only TEMP No Description 0x088 read-only 0x00000000 0x07FF07FF TEMPLSB Temperature measured decimal part 0 2 read-only TEMP Temperature measured 2 9 read-only TEMPAVG Averaged Temperature 16 11 read-only RSTCTRL No Description 0x090 read-write 0x40010407 0xC001C5CF WDOG0RMODE Enable WDOG0 reset 0 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset except some EMU registers 1 SYSRMODE Enable M33 System reset 2 1 read-write DISABLED Reset request is blocked 0 ENABLED Device is reset except some EMU registers 1 LOCKUPRMODE Enable M33 Lockup reset 3 1 read-write DISABLED Reset Request is Block 0 ENABLED The entire device is reset except some EMU registers 1 AVDDBODRMODE Enable AVDD BOD reset 6 1 read-write DISABLED Reset Request is block 0 ENABLED The entire device is reset except some EMU registers 1 IOVDD0BODRMODE Enable VDDIO0 BOD reset 7 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset except some EMU registers 1 DECBODRMODE Enable DECBOD reset 10 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset 1 DCIRMODE DCI System reset 16 1 read-write DISABLED Reset request blocked 0 ENABLED The entire device is reset except some EMU registers 1 RSTCAUSE No Description 0x094 read-only 0x00000000 0x8001FFFF POR Power On Reset 0 1 read-only PIN Pin Reset 1 1 read-only EM4 EM4 Wakeup Reset 2 1 read-only WDOG0 Watchdog 0 Reset 3 1 read-only LOCKUP M33 Core Lockup Reset 5 1 read-only SYSREQ M33 Core Sys Reset 6 1 read-only DVDDBOD HVBOD Reset 7 1 read-only DVDDLEBOD LEBOD Reset 8 1 read-only DECBOD LVBOD Reset 9 1 read-only AVDDBOD LEBOD1 Reset 10 1 read-only IOVDD0BOD LEBOD2 Reset 11 1 read-only DCI DCI reset 16 1 read-only VREGIN DCDC VREGIN comparator 31 1 read-only DGIF No Description 0x0A0 read-write 0x00000000 0xE1000000 EM23WAKEUPDGIF EM23 Wake up Interrupt flag 24 1 read-write TEMPDGIF Temperature Interrupt flag 29 1 read-write TEMPLOWDGIF Temperature low Interrupt flag 30 1 read-write TEMPHIGHDGIF Temperature high Interrupt flag 31 1 read-write DGIEN No Description 0x0A4 read-write 0x00000000 0xE1000000 EM23WAKEUPDGIEN EM23 Wake up Interrupt enable 24 1 read-write TEMPDGIEN Temperature Interrupt enable 29 1 read-write TEMPLOWDGIEN Temperature low Interrupt enable 30 1 read-write TEMPHIGHDGIEN Temperature high Interrupt enable 31 1 read-write EFPIF No Description 0x100 read-write 0x00000000 0x00000001 EFPIF EFP Interrupt Flag 0 1 read-write EFPIEN No Description 0x104 read-write 0x00000000 0x00000001 EFPIEN EFP Interrupt enable 0 1 read-write CMU_NS 1 CMU_NS Registers 0x50008000 0x00000000 0x00001000 registers CMU 46 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only STATUS No Description 0x008 read-only 0x00000000 0xC0030001 CALRDY Calibration Ready 0 1 read-only WDOGLOCK Configuration Lock Status for WDOG 30 1 read-only UNLOCKED WDOG configuration lock is unlocked 0 LOCKED WDOG configuration lock is locked 1 LOCK Configuration Lock Status 31 1 read-only UNLOCKED Configuration lock is unlocked 0 LOCKED Configuration lock is locked 1 LOCK No Description 0x010 write-only 0x000093F7 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write this value to unlock 37879 WDOGLOCK No Description 0x014 write-only 0x00005257 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write this value to unlock 37879 IF No Description 0x020 read-write 0x00000000 0x00000003 CALRDY Calibration Ready Interrupt Flag 0 1 read-write CALOF Calibration Overflow Interrupt Flag 1 1 read-write IEN No Description 0x024 read-write 0x00000000 0x00000003 CALRDY Calibration Ready Interrupt Enable 0 1 read-write CALOF Calibration Overflow Interrupt Enable 1 1 read-write CALCMD No Description 0x050 write-only 0x00000000 0x00000003 CALSTART Calibration Start 0 1 write-only CALSTOP Calibration Stop 1 1 write-only CALCTRL No Description 0x054 read-write 0x00000000 0xFF8FFFFF CALTOP Calibration Counter Top Value 0 20 read-write CONT Continuous Calibration 23 1 read-write UPSEL Calibration Up-counter Select 24 4 read-write DISABLED Up-counter is not clocked 0 PRS PRS CMU_CALUP consumer is clocking up-counter 1 HFXO HFXO is clocking up-counter 2 LFXO LFXO is clocking up-counter 3 HFRCODPLL HFRCODPLL is clocking up-counter 4 FSRCO FSRCO is clocking up-counter 8 LFRCO LFRCO is clocking up-counter 9 ULFRCO ULFRCO is clocking up-counter 10 DOWNSEL Calibration Down-counter Select 28 4 read-write DISABLED Down-counter is not clocked 0 HCLK HCLK is clocking down-counter 1 PRS PRS CMU_CALDN consumer is clocking down-counter 2 HFXO HFXO is clocking down-counter 3 LFXO LFXO is clocking down-counter 4 HFRCODPLL HFRCODPLL is clocking down-counter 5 FSRCO FSRCO is clocking down-counter 9 LFRCO LFRCO is clocking down-counter 10 ULFRCO ULFRCO is clocking down-counter 11 CALCNT No Description 0x058 read-only 0x00000000 0x000FFFFF CALCNT Calibration Result Counter Value 0 20 read-only CLKEN0 No Description 0x064 read-write 0x00000000 0xFFFFFFFF LDMA Enable Bus Clock 0 1 read-write LDMAXBAR Enable Bus Clock 1 1 read-write GPCRC Enable Bus Clock 3 1 read-write TIMER0 Enable Bus Clock 4 1 read-write TIMER1 Enable Bus Clock 5 1 read-write TIMER2 Enable Bus Clock 6 1 read-write TIMER3 Enable Bus Clock 7 1 read-write USART0 Enable Bus Clock 8 1 read-write USART1 Enable Bus Clock 9 1 read-write IADC0 Enable Bus Clock 10 1 read-write AMUXCP0 Enable Bus Clock 11 1 read-write LETIMER0 Enable Bus Clock 12 1 read-write WDOG0 Enable Bus Clock 13 1 read-write I2C0 Enable Bus Clock 14 1 read-write I2C1 Enable Bus Clock 15 1 read-write SYSCFG Enable Bus Clock 16 1 read-write DPLL0 Enable Bus Clock 17 1 read-write HFRCO0 Enable Bus Clock 18 1 read-write HFXO0 Enable Bus Clock 19 1 read-write FSRCO Enable Bus Clock 20 1 read-write LFRCO Enable Bus Clock 21 1 read-write LFXO Enable Bus Clock 22 1 read-write ULFRCO Enable Bus Clock 23 1 read-write EUART0 Enable Bus Clock 24 1 read-write PDM Enable Bus Clock 25 1 read-write GPIO Enable Bus Clock 26 1 read-write PRS Enable Bus Clock 27 1 read-write BURAM Enable Bus Clock 28 1 read-write BURTC Enable Bus Clock 29 1 read-write RTCC Enable Bus Clock 30 1 read-write DCDC Enable Bus Clock 31 1 read-write CLKEN1 No Description 0x068 read-write 0x00000000 0x0007FFFF CRYPTOACC Enable Bus Clock 13 1 read-write SMU Enable Bus Clock 15 1 read-write ICACHE0 Enable Bus Clock 16 1 read-write MSC Enable Bus Clock 17 1 read-write TIMER4 Enable Bus Clock 18 1 read-write SYSCLKCTRL No Description 0x070 read-write 0x00000001 0x0001F507 CLKSEL Clock Select 0 3 read-write FSRCO FSRCO is clocking SYSCLK 1 HFRCODPLL HFRCODPLL is clocking SYSCLK 2 HFXO HFXO is clocking SYSCLK 3 CLKIN0 CLKIN0 is clocking SYSCLK 4 PCLKPRESC PCLK Prescaler 10 1 read-write DIV1 PCLK is HCLK divided by 1 0 DIV2 PCLK is HCLK divided by 2 1 HCLKPRESC HCLK Prescaler 12 4 read-write DIV1 HCLK is SYSCLK divided by 1 0 DIV2 HCLK is SYSCLK divided by 2 1 DIV4 HCLK is SYSCLK divided by 4 3 DIV8 HCLK is SYSCLK divided by 8 7 DIV16 HCLK is SYSCLK divided by 16 15 TRACECLKCTRL No Description 0x080 read-write 0x00000000 0x00000030 PRESC TRACECLK Prescaler 4 2 read-write DIV1 TRACECLK is SYSCLK divided by 1 0 DIV2 TRACECLK is SYSCLK divided by 2 1 DIV4 TRACECLK is SYSCLK divided by 4 3 EXPORTCLKCTRL No Description 0x090 read-write 0x00000000 0x1F0F0F0F CLKOUTSEL0 Clock Output Select 0 0 4 read-write DISABLED CLKOUT0 is not clocked 0 HCLK HCLK is clocking CLKOUT0 1 HFEXPCLK EXPORTCLK is clocking CLKOUT0 2 ULFRCO ULFRCO is clocking CLKOUT0 3 LFRCO LFRCO is clocking CLKOUT0 4 LFXO LFXO is clocking CLKOUT0 5 HFRCODPLL HFRCODPLL is clocking CLKOUT0 6 HFXO HFXO is clocking CLKOUT0 7 FSRCO FSRCO is clocking CLKOUT0 8 CLKOUTSEL1 Clock Output Select 1 8 4 read-write DISABLED CLKOUT1 is not clocked 0 HCLK HCLK is clocking CLKOUT1 1 HFEXPCLK EXPORTCLK is clocking CLKOUT1 2 ULFRCO ULFRCO is clocking CLKOUT1 3 LFRCO LFRCO is clocking CLKOUT1 4 LFXO LFXO is clocking CLKOUT1 5 HFRCODPLL HFRCODPLL is clocking CLKOUT1 6 HFXO HFXO is clocking CLKOUT1 7 FSRCO FSRCO is clocking CLKOUT1 8 CLKOUTSEL2 Clock Output Select 2 16 4 read-write DISABLED CLKOUT2 is not clocked 0 HCLK HCLK is clocking CLKOUT2 1 HFEXPCLK EXPORTCLK is clocking CLKOUT2 2 ULFRCO ULFRCO is clocking CLKOUT2 3 LFRCO LFRCO is clocking CLKOUT2 4 LFXO LFXO is clocking CLKOUT2 5 HFRCODPLL HFRCODPLL is clocking CLKOUT2 6 HFXO HFXO is clocking CLKOUT2 7 FSRCO FSRCO is clocking CLKOUT2 8 PRESC EXPORTCLK Prescaler 24 5 read-write DPLLREFCLKCTRL No Description 0x100 read-write 0x00000000 0x00000003 CLKSEL Clock Select 0 2 read-write DISABLED DPLLREFCLK is not clocked 0 HFXO HFXO is clocking DPLLREFCLK 1 LFXO LFXO is clocking DPLLREFCLK 2 CLKIN0 CLKIN0 is clocking DPLLREFCLK 3 EM01GRPACLKCTRL No Description 0x120 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write HFRCODPLL HFRCODPLL is clocking EM01GRPACLK 1 HFXO HFXO is clocking EM01GRPACLK 2 FSRCO FSRCO is clocking EM01GRPACLK 3 EM01GRPBCLKCTRL No Description 0x124 read-write 0x00000001 0x00000007 CLKSEL Clock Select 0 3 read-write HFRCODPLL HFRCODPLL is clocking EM01GRPBCLK 1 HFXO HFXO is clocking EM01GRPBCLK 2 FSRCO FSRCO is clocking EM01GRPBCLK 3 CLKIN0 CLKIN0 is clocking EM01GRPBCLK 4 HFRCODPLLRT HFRCODPLL (re-timed) is clocking EM01GRPBCLK 5 HFXORT HFXO (re-timed) is clocking EM01GRPBCLK 6 EM23GRPACLKCTRL No Description 0x140 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking EM23GRPACLK 1 LFXO LFXO is clocking EM23GRPACLK 2 ULFRCO ULFRCO is clocking EM23GRPACLK 3 EM4GRPACLKCTRL No Description 0x160 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking EM4GRPACLK 1 LFXO LFXO is clocking EM4GRPACLK 2 ULFRCO ULFRCO is clocking EM4GRPACLK 3 IADCCLKCTRL No Description 0x180 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write EM01GRPACLK EM01GRPACLK is clocking IADCCLK 1 FSRCO FSRCO is clocking IADCCLK 2 WDOG0CLKCTRL No Description 0x200 read-write 0x00000001 0x00000007 CLKSEL Clock Select 0 3 read-write LFRCO LFRCO is clocking WDOG0CLK 1 LFXO LFXO is clocking WDOG0CLK 2 ULFRCO ULFRCO is clocking WDOG0CLK 3 HCLKDIV1024 HCLKDIV1024 is clocking WDOG0CLK 4 EUART0CLKCTRL No Description 0x220 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write DISABLED UART is not clocked 0 EM01GRPACLK EM01GRPACLK is clocking UART 1 EM23GRPACLK EM23GRPACLK is clocking UART 2 RTCCCLKCTRL No Description 0x240 read-write 0x00000001 0x00000003 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking RTCCCLK 1 LFXO LFXO is clocking RTCCCLK 2 ULFRCO ULFRCO is clocking RTCCCLK 3 CRYPTOACCCLKCTRL No Description 0x260 read-write 0x00000000 0x00000003 PKEN PK Enable 0 1 read-write AESEN AES Enable 1 1 read-write HFXO0_NS 2 HFXO0_NS Registers 0x5000C000 0x00000000 0x00001000 registers HFXO0 44 IPVERSION No Description 0x000 read-only 0x00000002 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only XTALCFG No Description 0x010 read-write 0x044334CB 0x0FFFFFFF COREBIASSTARTUPI Intermediate Startup Core Bias Current 0 6 read-write COREBIASSTARTUP Startup Core Bias Current 6 6 read-write CTUNEXISTARTUP Startup Tuning Capacitance on XI 12 4 read-write CTUNEXOSTARTUP Startup Tuning Capacitance on XO 16 4 read-write TIMEOUTSTEADY Steady State Timeout 20 4 read-write T16US The steady state timeout is set to 16 us minimum. The maximum can be +40%. 0 T41US The steady state timeout is set to 41 us minimum. The maximum can be +40%. 1 T83US The steady state timeout is set to 83 us minimum. The maximum can be +40%. 2 T125US The steady state timeout is set to 125 us minimum. The maximum can be +40%. 3 T166US The steady state timeout is set to 166 us minimum. The maximum can be +40%. 4 T208US The steady state timeout is set to 208 us minimum. The maximum can be +40%. 5 T250US The steady state timeout is set to 250 us minimum. The maximum can be +40%. 6 T333US The steady state timeout is set to 333 us minimum. The maximum can be +40%. 7 T416US The steady state timeout is set to 416 us minimum. The maximum can be +40%. 8 T500US The steady state timeout is set to 500 us minimum. The maximum can be +40%. 9 T666US The steady state timeout is set to 666 us minimum. The maximum can be +40%. 10 T833US The steady state timeout is set to 833 us minimum. The maximum can be +40%. 11 T1666US The steady state timeout is set to 1666 us minimum. The maximum can be +40%. 12 T2500US The steady state timeout is set to 2500 us minimum. The maximum can be +40%. 13 T4166US The steady state timeout is set to 4166 us minimum. The maximum can be +40%. 14 T7500US The steady state timeout is set to 7500 us minimum. The maximum can be +40%. 15 TIMEOUTCBLSB Core Bias LSB Change Timeout 24 4 read-write T8US The core bias LSB change timeout is set to 8 us minimum. The maximum can be +40%. 0 T20US The core bias LSB change timeout is set to 20 us minimum. The maximum can be +40%. 1 T41US The core bias LSB change timeout is set to 41 us minimum. The maximum can be +40%. 2 T62US The core bias LSB change timeout is set to 62 us minimum. The maximum can be +40%. 3 T83US The core bias LSB change timeout is set to 83 us minimum. The maximum can be +40%. 4 T104US The core bias LSB change timeout is set to 104 us minimum. The maximum can be +40%. 5 T125US The core bias LSB change timeout is set to 125 us minimum. The maximum can be +40%. 6 T166US The core bias LSB change timeout is set to 166 us minimum. The maximum can be +40%. 7 T208US The core bias LSB change timeout is set to 208 us minimum. The maximum can be +40%. 8 T250US The core bias LSB change timeout is set to 250 us minimum. The maximum can be +40%. 9 T333US The core bias LSB change timeout is set to 333 us minimum. The maximum can be +40%. 10 T416US The core bias LSB change timeout is set to 416 us minimum. The maximum can be +40%. 11 T833US The core bias LSB change timeout is set to 833 us minimum. The maximum can be +40%. 12 T1250US The core bias LSB change timeout is set to 1250 us minimum. The maximum can be +40%. 13 T2083US The core bias LSB change timeout is set to 2083 us minimum. The maximum can be +40%. 14 T3750US The core bias LSB change timeout is set to 3750 us minimum. The maximum can be +40%. 15 XTALCTRL No Description 0x018 read-write 0x0F8C8C10 0x8FFFFFFF COREBIASANA Core Bias Current 0 8 read-write CTUNEXIANA Tuning Capacitance on XI 8 8 read-write CTUNEXOANA Tuning Capacitance on XO 16 8 read-write CTUNEFIXANA Fixed Tuning Capacitance 24 2 read-write NONE Remove fixed capacitance on XI and XO nodes 0 XI Adds fixed capacitance on XI node 1 XO Adds fixed capacitance on XO node 2 BOTH Adds fixed capacitance on both XI and XO nodes 3 COREDGENANA Core Degeneration 26 2 read-write NONE Do not apply core degeneration resistence 0 DGEN33 Apply 33 ohm core degeneration resistence 1 DGEN50 Apply 50 ohm core degeneration resistence 2 DGEN100 Apply 100 ohm core degeneration resistence 3 SKIPCOREBIASOPT Skip Core Bias Optimization 31 1 read-write CFG No Description 0x020 read-write 0x10000000 0xF000000D MODE Crystal Oscillator Mode 0 1 read-write XTAL crystal oscillator 0 EXTCLK external sinusoidal clock can be supplied on XI pin. 1 ENXIDCBIASANA Enable XI Internal DC Bias 2 1 read-write SQBUFSCHTRGANA Squaring Buffer Schmitt Trigger 3 1 read-write DISABLE Squaring buffer schmitt trigger is disabled 0 ENABLE Squaring buffer schmitt trigger is enabled 1 CTRL No Description 0x028 read-write 0x00000002 0x80000037 FORCEEN Force Enable 0 1 read-write DISONDEMAND Disable On-demand Mode 1 1 read-write KEEPWARM Keep Warm 2 1 read-write FORCEXI2GNDANA Force XI Pin to Ground 4 1 read-write DISABLE Disabled (not pulled) 0 ENABLE Enabled (pulled) 1 FORCEXO2GNDANA Force XO Pin to Ground 5 1 read-write DISABLE Disabled (not pulled) 0 ENABLE Enabled (pulled) 1 CMD No Description 0x050 write-only 0x00000000 0x00000003 COREBIASOPT Core Bias Optimizaton 0 1 write-only MANUALOVERRIDE Manual Override 1 1 write-only STATUS No Description 0x058 read-only 0x00000000 0xC00F0003 RDY Ready Status 0 1 read-only COREBIASOPTRDY Core Bias Optimization Ready 1 1 read-only ENS Enabled Status 16 1 read-only HWREQ Oscillator Requested by Hardware 17 1 read-only ISWARM Oscillator Is Kept Warm 19 1 read-only FSMLOCK FSM Lock Status 30 1 read-only UNLOCKED FSM lock is unlocked 0 LOCKED FSM lock is locked 1 LOCK Configuration Lock Status 31 1 read-only UNLOCKED Configuration lock is unlocked 0 LOCKED Configuration lock is locked 1 IF No Description 0x070 read-write 0x00000000 0xE0000003 RDY Ready Interrupt 0 1 read-write COREBIASOPTRDY Core Bias Optimization Ready Interrupt 1 1 read-write DNSERR Did Not Start Error Interrupt 29 1 read-write COREBIASOPTERR Core Bias Optimization Error Interrupt 31 1 read-write IEN No Description 0x074 read-write 0x00000000 0xE0000003 RDY Ready Interrupt 0 1 read-write COREBIASOPTRDY Core Bias Optimization Ready Interrupt 1 1 read-write DNSERR Did Not Start Error Interrupt 29 1 read-write COREBIASOPTERR Core Bias Optimization Error Interrupt 31 1 read-write LOCK No Description 0x080 write-only 0x0000580E 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write this value to unlock 22542 HFRCO0_NS 1 HFRCO0_NS Registers 0x50010000 0x00000000 0x00001000 registers HFRCO0 45 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only CTRL No Description 0x004 read-write 0x00000000 0x00000003 FORCEEN Force Enable 0 1 read-write DISONDEMAND Disable On-demand 1 1 read-write CAL No Description 0x008 read-write 0xA8689F7F 0xFFFFBF7F TUNING Tuning Value 0 7 read-write FINETUNING Fine Tuning Value 8 6 read-write LDOHP LDO High Power Mode 15 1 read-write FREQRANGE Frequency Range 16 5 read-write CMPBIAS Comparator Bias Current 21 3 read-write CLKDIV Locally Divide HFRCO Clock Output 24 2 read-write DIV1 Divide by 1. 0 DIV2 Divide by 2. 1 DIV4 Divide by 4. 2 CMPSEL Comparator Load Select 26 2 read-write IREFTC Tempco Trim on Comparator Current 28 4 read-write STATUS No Description 0x00C read-only 0x00000000 0x80010007 RDY Ready 0 1 read-only FREQBSY Frequency Updating Busy 1 1 read-only SYNCBUSY Synchronization Busy 2 1 read-only ENS Enable Status 16 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED HFRCO is unlocked 0 LOCKED HFRCO is locked 1 IF No Description 0x010 read-write 0x00000000 0x00000001 RDY Ready Interrupt Flag 0 1 read-write IEN No Description 0x014 read-write 0x00000000 0x00000001 RDY RDY Interrupt Enable 0 1 read-write LOCK No Description 0x01C write-only 0x00008195 0x0000FFFF LOCKKEY Lock Key 0 16 write-only UNLOCK Unlock code 33173 FSRCO_NS 0 FSRCO_NS Registers 0x50018000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version 0 32 read-only DPLL0_NS 0 DPLL0_NS Registers 0x5001C000 0x00000000 0x00001000 registers DPLL0 50 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Module Enable 0 1 read-write CFG No Description 0x008 read-write 0x00000000 0x00000047 MODE Operating Mode Control 0 1 read-write FLL Frequency Lock Mode 0 PLL Phase Lock Mode 1 EDGESEL Reference Edge Select 1 1 read-write AUTORECOVER Automatic Recovery Control 2 1 read-write DITHEN Dither Enable Control 6 1 read-write CFG1 No Description 0x00C read-write 0x00000000 0x0FFF0FFF M Factor M 0 12 read-write N Factor N 16 12 read-write IF No Description 0x010 read-write 0x00000000 0x00000007 LOCK Lock Interrupt Flag 0 1 read-write LOCKFAILLOW Lock Failure Low Interrupt Flag 1 1 read-write LOCKFAILHIGH Lock Failure High Interrupt Flag 2 1 read-write IEN No Description 0x014 read-write 0x00000000 0x00000007 LOCK LOCK interrupt Enable 0 1 read-write LOCKFAILLOW LOCKFAILLOW Interrupe Enable 1 1 read-write LOCKFAILHIGH LOCKFAILHIGH Interrupt Enable 2 1 read-write STATUS No Description 0x018 read-only 0x00000000 0x80000003 RDY Ready Status 0 1 read-only ENS Enable Status 1 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED 0 LOCKED 1 LOCK No Description 0x024 write-only 0x00007102 0x0000FFFF LOCKKEY Lock Key 0 16 write-only UNLOCK 28930 LFXO_NS 0 LFXO_NS Registers 0x50020000 0x00000000 0x00001000 registers LFXO 22 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CTRL No Description 0x004 read-write 0x00000002 0x00000033 FORCEEN LFXO Force Enable 0 1 read-write DISONDEMAND LFXO Disable On-demand requests 1 1 read-write FAILDETEN LFXO Failure Detection Enable 4 1 read-write FAILDETEM4WUEN LFXO Failure Detection EM4WU Enable 5 1 read-write CFG Do not write to this register unless the oscillator is forced off. The oscillator is forced off if DISONDEMAND is set and FORCEEN is cleared. 0x008 read-write 0x00000701 0x00000733 AGC LFXO AGC Enable 0 1 read-write HIGHAMPL LFXO High Amplitude Enable 1 1 read-write MODE LFXO Mode 4 2 read-write XTAL A 32768Hz crystal should be connected to the LF crystal pads. Voltage must not exceed VDDIO. 0 BUFEXTCLK An external sine source with minimum amplitude 100mv (zero-to-peak) and maximum amplitude 500mV (zero-to-peak) should be connected in series with LFXTAL_I pin. Minimum voltage should be larger than ground and maximum voltage smaller than VDDIO. The sine source does not need to be ac coupled externally as it is ac couples inside LFXO. LFXTAL_O is free to be used as a general purpose GPIO. 1 DIGEXTCLK An external 32KHz CMOS clock should be provided on LFXTAL_I. LFXTAL_O is free to be used as a general purpose GPIO. 2 TIMEOUT LFXO Start-up Delay 8 3 read-write CYCLES2 Timeout period of 2 cycles 0 CYCLES256 Timeout period of 256 cycles 1 CYCLES1K Timeout period of 1024 cycles 2 CYCLES2K Timeout period of 2048 cycles 3 CYCLES4K Timeout period of 4096 cycles 4 CYCLES8K Timeout period of 8192 cycles 5 CYCLES16K Timeout period of 16384 cycles 6 CYCLES32K Timeout period of 32768 cycles 7 STATUS No Description 0x010 read-only 0x00000000 0x80010001 RDY LFXO Ready Status 0 1 read-only ENS LFXO Enable Status 16 1 read-only LOCK LFXO Locked Status 31 1 read-only UNLOCKED LFXO lockable registers are not locked 0 LOCKED LFXO lockable registers are locked 1 CAL Do not write to this register unless CALBSY in SYNCBUSY register is low. 0x014 read-write 0x00000200 0x0000037F CAPTUNE Internal Capacitance Tuning 0 7 read-write GAIN LFXO Startup Gain 8 2 read-write IF No Description 0x018 read-write 0x00000000 0x0000000F RDY LFXO Ready Interrupt Flag 0 1 read-write POSEDGE Rising Edge Interrupt Flag 1 1 read-write NEGEDGE Falling Edge Interrupt Flag 2 1 read-write FAIL LFXO Failure Interrupt Flag 3 1 read-write IEN No Description 0x01C read-write 0x00000000 0x0000000F RDY LFXO Ready Interrupt Enable 0 1 read-write POSEDGE Rising Edge Interrupt Enable 1 1 read-write NEGEDGE Falling Edge Interrupt Enable 2 1 read-write FAIL LFXO Failure Interrupt Enable 3 1 read-write SYNCBUSY No Description 0x020 read-only 0x00000000 0x00000001 CAL LFXO Synchronization status 0 1 read-only LOCK No Description 0x024 write-only 0x00001A20 0x0000FFFF LOCKKEY Lock Key 0 16 write-only UNLOCK Unlock LFXO lockable registers 6688 LFRCO_NS 1 LFRCO_NS Registers 0x50024000 0x00000000 0x00001000 registers LFRCO 23 IPVERSION Contains the LFRCO ip version 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only CTRL Control register 0x004 read-write 0x00000000 0x00000003 FORCEEN Force Enable 0 1 read-write DISONDEMAND Disable On-Demand 1 1 read-write STATUS Status register 0x008 read-only 0x00000000 0x80010001 RDY Ready Status 0 1 read-only ENS Enabled Status 16 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED Access to configuration registers not locked 0 LOCKED Access to configuration registers locked 1 IF Interrupt flag register 0x014 read-write 0x00000000 0x00070707 RDY Ready Flag 0 1 read-write POSEDGE Rising Edge Flag 1 1 read-write NEGEDGE Falling Edge Flag 2 1 read-write TCDONE Temperature Check Done Flag 8 1 read-write CALDONE Calibration Done Flag 9 1 read-write TEMPCHANGE Temperature Change Flag 10 1 read-write SCHEDERR Scheduling Error Flag 16 1 read-write TCOOR Temperature Check Out Of Range Flag 17 1 read-write CALOOR Calibration Out Of Range Flag 18 1 read-write IEN Interrupt enable register 0x018 read-write 0x00000000 0x00070707 RDY Ready Enable 0 1 read-write POSEDGE Rising Edge Enable 1 1 read-write NEGEDGE Falling Edge Enable 2 1 read-write TCDONE Temperature Check Done Enable 8 1 read-write CALDONE Calibration Done Enable 9 1 read-write TEMPCHANGE Temperature Change Enable 10 1 read-write SCHEDERR Scheduling Error Enable 16 1 read-write TCOOR Temperature Check Out Of Range Enable 17 1 read-write CALOOR Calibration Out Of Range Enable 18 1 read-write LOCK Configuration lock register. Locks and unlocks access to configuration registers. 0x020 write-only 0x00000000 0x0000FFFF LOCKKEY Lock Key 0 16 write-only LOCK Lock Configuration Registers 0 UNLOCK Unlock Configuration Registers 3987 CFG Configuration register 0x024 read-write 0x00000000 0x00000001 HIGHPRECEN High Precision Enable 0 1 read-write NOMCAL Nominal calibration register 0x02C read-write 0x0005B8D8 0x001FFFFF NOMCALCNT Nominal Calibration Count 0 21 read-write NOMCALINV Nominal calibration inverted register 0x030 read-write 0x0000597A 0x0001FFFF NOMCALCNTINV Nominal Calibration Count Inverted 0 17 read-write CMD Command register 0x034 write-only 0x00000000 0x00000001 REDUCETCINT Reduce Temperature Check Interval 0 1 write-only ULFRCO_NS 0 ULFRCO_NS Registers 0x50028000 0x00000000 0x00001000 registers ULFRCO 24 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION ULFRCO IP version 0 32 read-only STATUS No Description 0x008 read-only 0x00000000 0x00010001 RDY Ready Status 0 1 read-only ENS Enable Status 16 1 read-only IF No Description 0x014 read-write 0x00000000 0x00000007 RDY Ready Interrupt Flag 0 1 read-write POSEDGE Positive Edge Interrupt Flag 1 1 read-write NEGEDGE Negative Edge Interrupt Flag 2 1 read-write IEN No Description 0x018 read-write 0x00000000 0x00000007 RDY Enable Ready Interrupt 0 1 read-write POSEDGE Enable Positive Edge Interrupt 1 1 read-write NEGEDGE Enable Negative Edge Interrupt 2 1 read-write MSC_NS 1 MSC_NS Registers 0x50030000 0x00000000 0x00001000 registers MSC 49 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only READCTRL No Description 0x008 read-write 0x00200000 0x00301002 DOUTBUFEN Flash dout pipeline buffer enable 12 1 read-write MODE Read Mode 20 2 read-write WS0 Zero wait-states inserted in fetch or read transfers 0 WS1 One wait-state inserted for each fetch or read transfer 1 WS2 Two wait-states inserted for eatch fetch or read transfer 2 WS3 Three wait-states inserted for eatch fetch or read transfer 3 WRITECTRL No Description 0x00C read-write 0x00000000 0x0000000B WREN Enable Write/Erase Controller 0 1 read-write IRQERASEABORT Abort Page Erase on Interrupt 1 1 read-write LPWRITE Low-Power Erase 3 1 read-write WRITECMD No Description 0x010 write-only 0x00000000 0x00001126 ERASEPAGE Erase Page 1 1 write-only WRITEEND End Write Mode 2 1 write-only ERASEABORT Abort erase sequence 5 1 write-only ERASEMAIN0 Mass erase region 0 8 1 write-only CLEARWDATA Clear WDATA state 12 1 write-only ADDRB No Description 0x014 read-write 0x00000000 0xFFFFFFFF ADDRB Page Erase or Write Address Buffer 0 32 read-write WDATA No Description 0x018 read-write 0x00000000 0xFFFFFFFF DATAW Write Data 0 32 read-write STATUS No Description 0x01C read-only 0x08000008 0xF901007F BUSY Erase/Write Busy 0 1 read-only LOCKED Access Locked 1 1 read-only INVADDR Invalid Write Address or Erase Page 2 1 read-only WDATAREADY WDATA Write Ready 3 1 read-only ERASEABORTED Erase Operation Aborted 4 1 read-only PENDING Write Command In Queue 5 1 read-only TIMEOUT Write Command Timeout 6 1 read-only REGLOCK Register Lock Status 16 1 read-only UNLOCKED Register lock is unlocked 0 LOCKED Register lock is locked. 1 PWRON Flash Power On Status 24 1 read-only WREADY Flash Write Ready 27 1 read-only PWRUPCKBDFAILCOUNT Flash power up checkerboard pattern chec 28 4 read-only IF No Description 0x020 read-write 0x00000000 0x00000307 ERASE Host Erase Done Interrupt Read Flag 0 1 read-write WRITE Host Write Done Interrupt Read Flag 1 1 read-write WDATAOV Host write buffer overflow 2 1 read-write PWRUPF Flash Power Up Sequence Complete Flag 8 1 read-write PWROFF Flash Power Off Sequence Complete Flag 9 1 read-write IEN No Description 0x024 read-write 0x00000000 0x00000307 ERASE Erase Done Interrupt enable 0 1 read-write WRITE Write Done Interrupt enable 1 1 read-write WDATAOV write data buffer overflow irq enable 2 1 read-write PWRUPF Flash Power Up Seq done irq enable 8 1 read-write PWROFF Flash Power Off Seq done irq enable 9 1 read-write USERDATASIZE No Description 0x034 read-only 0x00000004 0x0000003F USERDATASIZE User Data Size 0 6 read-only CMD No Description 0x038 write-only 0x00000000 0x00000011 PWRUP Flash Power Up Command 0 1 write-only PWROFF Flash power off/sleep command 4 1 write-only LOCK No Description 0x03C write-only 0x00000000 0x0000FFFF LOCKKEY Configuration Lock 0 16 write-only LOCK Key to lock the register lock 0 UNLOCK Key to unlock the register lock. 7025 MISCLOCKWORD No Description 0x040 read-write 0x00000011 0x00000011 MELOCKBIT Mass Erase Lock 0 1 read-write UDLOCKBIT User Data Lock 4 1 read-write PWRCTRL No Description 0x050 read-write 0x00100002 0x00FF0013 PWROFFONEM1ENTRY Power down Flash macro when enter EM1 0 1 read-write PWROFFENTRYAGAIN POWER down flash again in EM1/EM1p 4 1 read-write PWROFFDLY Power down delay 16 8 read-write PAGELOCK0 No Description 0x120 read-write 0x00000000 0xFFFFFFFF LOCKBIT page lock bit 0 32 read-write PAGELOCK1 No Description 0x124 read-write 0x00000000 0xFFFFFFFF LOCKBIT page lock bit 0 32 read-write ICACHE0_NS 0 ICACHE0_NS Registers 0x50034000 0x00000000 0x00001000 registers ICACHE0 17 IPVERSION The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION. 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only CTRL No Description 0x004 read-write 0x00000000 0x00000007 CACHEDIS Cache Disable 0 1 read-write USEMPU Use MPU 1 1 read-write AUTOFLUSHDIS Automatic Flushing Disable 2 1 read-write PCHITS No Description 0x008 read-only 0x00000000 0xFFFFFFFF PCHITS Performance Counter Hits 0 32 read-only PCMISSES No Description 0x00C read-only 0x00000000 0xFFFFFFFF PCMISSES Performance Counter Misses 0 32 read-only PCAHITS No Description 0x010 read-only 0x00000000 0xFFFFFFFF PCAHITS Performance Counter Advanced Hits 0 32 read-only STATUS No Description 0x014 read-only 0x00000000 0x00000001 PCRUNNING PC Running 0 1 read-only CMD No Description 0x018 write-only 0x00000000 0x00000007 FLUSH Flush 0 1 write-only STARTPC Start Performance Counters 1 1 write-only STOPPC Stop Performance Counters 2 1 write-only LPMODE No Description 0x01C read-write 0x00000023 0x000000F3 LPLEVEL Low Power Level 0 2 read-write BASIC Base instruction cache functionality 0 ADVANCED Advanced buffering mode, where the cache uses the fetch pattern to predict highly accessed data and store it in low-energy memory 1 MINACTIVITY Minimum activity mode, which allows the cache to minimize activity in logic that it predicts has a low probability being used. This mode can introduce wait-states into the instruction fetch stream when the cache exits one of its low-activity states. The number of wait-states introduced is small, but users running with 0-wait-state memory and wishing to reduce the variability that the cache might introduce with additional wait-states may wish to lower the cache low-power level. Note, this mode includes the advanced buffering mode functionality. 3 NESTFACTOR Low Power Nest Factor 4 4 read-write IF No Description 0x020 read-write 0x00000000 0x00000107 HITOF Hit Overflow Interrupt Flag 0 1 read-write MISSOF Miss Overflow Interrupt Flag 1 1 read-write AHITOF Advanced Hit Overflow Interrupt Flag 2 1 read-write RAMERROR RAM error Interrupt Flag 8 1 read-write IEN No Description 0x024 read-write 0x00000000 0x00000107 HITOF Hit Overflow Interrupt Enable 0 1 read-write MISSOF Miss Overflow Interrupt Enable 1 1 read-write AHITOF Advanced Hit Overflow Interrupt Enable 2 1 read-write RAMERROR RAM error Interrupt Enable 8 1 read-write PRS_NS 1 PRS_NS Registers 0x50038000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only ASYNC_SWPULSE No Description 0x008 write-only 0x00000000 0x00000FFF CH0PULSE Channel pulse 0 1 write-only CH1PULSE Channel pulse 1 1 write-only CH2PULSE Channel pulse 2 1 write-only CH3PULSE Channel pulse 3 1 write-only CH4PULSE Channel pulse 4 1 write-only CH5PULSE Channel pulse 5 1 write-only CH6PULSE Channel pulse 6 1 write-only CH7PULSE Channel pulse 7 1 write-only CH8PULSE Channel pulse 8 1 write-only CH9PULSE Channel pulse 9 1 write-only CH10PULSE Channel pulse 10 1 write-only CH11PULSE Channel pulse 11 1 write-only ASYNC_SWLEVEL No Description 0x00C read-write 0x00000000 0x00000FFF CH0LEVEL Channel Level 0 1 read-write CH1LEVEL Channel Level 1 1 read-write CH2LEVEL Channel Level 2 1 read-write CH3LEVEL Channel Level 3 1 read-write CH4LEVEL Channel Level 4 1 read-write CH5LEVEL Channel Level 5 1 read-write CH6LEVEL Channel Level 6 1 read-write CH7LEVEL Channel Level 7 1 read-write CH8LEVEL Channel Level 8 1 read-write CH9LEVEL Channel Level 9 1 read-write CH10LEVEL Channel Level 10 1 read-write CH11LEVEL Channel Level 11 1 read-write ASYNC_PEEK No Description 0x010 read-only 0x00000000 0x00000FFF CH0VAL Channel 0 Current Value 0 1 read-only CH1VAL Channel 1 Current Value 1 1 read-only CH2VAL Channel 2 Current Value 2 1 read-only CH3VAL Channel 3 Current Value 3 1 read-only CH4VAL Channel 4 Current Value 4 1 read-only CH5VAL Channel 5 Current Value 5 1 read-only CH6VAL Channel 6 Current Value 6 1 read-only CH7VAL Channel 7 Current Value 7 1 read-only CH8VAL Channel 8 Current Value 8 1 read-only CH9VAL Channel 9 Current Value 9 1 read-only CH10VAL Channel 10 Current Value 10 1 read-only CH11VAL Channel 11 Current Value 11 1 read-only SYNC_PEEK No Description 0x014 read-only 0x00000000 0x0000000F CH0VAL Channel Value 0 1 read-only CH1VAL Channel Value 1 1 read-only CH2VAL Channel Value 2 1 read-only CH3VAL Channel Value 3 1 read-only ASYNC_CH0_CTRL No Description 0x018 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH1_CTRL No Description 0x01C read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH2_CTRL No Description 0x020 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH3_CTRL No Description 0x024 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH4_CTRL No Description 0x028 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH5_CTRL No Description 0x02C read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH6_CTRL No Description 0x030 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH7_CTRL No Description 0x034 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH8_CTRL No Description 0x038 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH9_CTRL No Description 0x03C read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH10_CTRL No Description 0x040 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write ASYNC_CH11_CTRL No Description 0x044 read-write 0x000C0000 0x0F0F7F07 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 AUXSEL Auxiliary LUT Input Select 24 4 read-write SYNC_CH0_CTRL No Description 0x048 read-write 0x00000000 0x00007F07 SIGSEL Signal Select 0 3 read-write SOURCESEL Source Select 8 7 read-write SYNC_CH1_CTRL No Description 0x04C read-write 0x00000000 0x00007F07 SIGSEL Signal Select 0 3 read-write SOURCESEL Source Select 8 7 read-write SYNC_CH2_CTRL No Description 0x050 read-write 0x00000000 0x00007F07 SIGSEL Signal Select 0 3 read-write SOURCESEL Source Select 8 7 read-write SYNC_CH3_CTRL No Description 0x054 read-write 0x00000000 0x00007F07 SIGSEL Signal Select 0 3 read-write SOURCESEL Source Select 8 7 read-write CONSUMER_CMU_CALDN CALDN Consumer Register 0x058 read-write 0x00000000 0x0000000F PRSSEL CALDN async channel select 0 4 read-write CONSUMER_CMU_CALUP CALUP Consumer Register 0x05C read-write 0x00000000 0x0000000F PRSSEL CALUP async channel select 0 4 read-write CONSUMER_IADC0_SCANTRIGGER SCAN Consumer Register 0x064 read-write 0x00000000 0x0000030F PRSSEL SCAN async channel select 0 4 read-write SPRSSEL SCAN sync channel select 8 2 read-write CONSUMER_IADC0_SINGLETRIGGER SINGLE Consumer Register 0x068 read-write 0x00000000 0x0000030F PRSSEL SINGLE async channel select 0 4 read-write SPRSSEL SINGLE sync channel select 8 2 read-write CONSUMER_LDMAXBAR_DMAREQ0 DMAREQ0 Consumer Register 0x06C read-write 0x00000000 0x0000000F PRSSEL DMAREQ0 async channel select 0 4 read-write CONSUMER_LDMAXBAR_DMAREQ1 DMAREQ1 Consumer Register 0x070 read-write 0x00000000 0x0000000F PRSSEL DMAREQ1 async channel select 0 4 read-write CONSUMER_LETIMER0_CLEAR CLEAR Consumer Register 0x074 read-write 0x00000000 0x0000000F PRSSEL CLEAR async channel select 0 4 read-write CONSUMER_LETIMER0_START START Consumer Register 0x078 read-write 0x00000000 0x0000000F PRSSEL START async channel select 0 4 read-write CONSUMER_LETIMER0_STOP STOP Consumer Register 0x07C read-write 0x00000000 0x0000000F PRSSEL STOP async channel select 0 4 read-write CONSUMER_EUART0_RX RX Consumer Register 0x080 read-write 0x00000000 0x0000000F PRSSEL RX async channel select 0 4 read-write CONSUMER_EUART0_TRIGGER TRIGGER Consumer Register 0x084 read-write 0x00000000 0x0000000F PRSSEL TRIGGER async channel select 0 4 read-write CONSUMER_RTCC_CC0 CC0 Consumer Register 0x0E8 read-write 0x00000000 0x0000000F PRSSEL CC0 async channel select 0 4 read-write CONSUMER_RTCC_CC1 CC1 Consumer Register 0x0EC read-write 0x00000000 0x0000000F PRSSEL CC1 async channel select 0 4 read-write CONSUMER_RTCC_CC2 CC2 Consumer Register 0x0F0 read-write 0x00000000 0x0000000F PRSSEL CC2 async channel select 0 4 read-write CONSUMER_CORE_CTIIN0 CTI Consumer Register 0x0F8 read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_CORE_CTIIN1 CTI Consumer Register 0x0FC read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_CORE_CTIIN2 CTI Consumer Register 0x100 read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_CORE_CTIIN3 CTI Consumer Register 0x104 read-write 0x00000000 0x0000000F PRSSEL CTI async channel select 0 4 read-write CONSUMER_CORE_M33RXEV M33 Consumer Register 0x108 read-write 0x00000000 0x0000000F PRSSEL M33 async channel select 0 4 read-write CONSUMER_TIMER0_CC0 CC0 Consumer Register 0x10C read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER0_CC1 CC1 Consumer Register 0x110 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER0_CC2 CC2 Consumer Register 0x114 read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER0_DTI DTI Consumer Register 0x118 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER0_DTIFS1 DTI Consumer Register 0x11C read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER0_DTIFS2 DTI Consumer Register 0x120 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER1_CC0 CC0 Consumer Register 0x124 read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER1_CC1 CC1 Consumer Register 0x128 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER1_CC2 CC2 Consumer Register 0x12C read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER1_DTI DTI Consumer Register 0x130 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER1_DTIFS1 DTI Consumer Register 0x134 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER1_DTIFS2 DTI Consumer Register 0x138 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER2_CC0 CC0 Consumer Register 0x13C read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER2_CC1 CC1 Consumer Register 0x140 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER2_CC2 CC2 Consumer Register 0x144 read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER2_DTI DTI Consumer Register 0x148 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER2_DTIFS1 DTI Consumer Register 0x14C read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER2_DTIFS2 DTI Consumer Register 0x150 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER3_CC0 CC0 Consumer Register 0x154 read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER3_CC1 CC1 Consumer Register 0x158 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER3_CC2 CC2 Consumer Register 0x15C read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER3_DTI DTI Consumer Register 0x160 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER3_DTIFS1 DTI Consumer Register 0x164 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER3_DTIFS2 DTI Consumer Register 0x168 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER4_CC0 CC0 Consumer Register 0x16C read-write 0x00000000 0x0000030F PRSSEL CC0 async channel select 0 4 read-write SPRSSEL CC0 sync channel select 8 2 read-write CONSUMER_TIMER4_CC1 CC1 Consumer Register 0x170 read-write 0x00000000 0x0000030F PRSSEL CC1 async channel select 0 4 read-write SPRSSEL CC1 sync channel select 8 2 read-write CONSUMER_TIMER4_CC2 CC2 Consumer Register 0x174 read-write 0x00000000 0x0000030F PRSSEL CC2 async channel select 0 4 read-write SPRSSEL CC2 sync channel select 8 2 read-write CONSUMER_TIMER4_DTI DTI Consumer Register 0x178 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER4_DTIFS1 DTI Consumer Register 0x17C read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_TIMER4_DTIFS2 DTI Consumer Register 0x180 read-write 0x00000000 0x0000000F PRSSEL DTI async channel select 0 4 read-write CONSUMER_USART0_CLK CLK Consumer Register 0x184 read-write 0x00000000 0x0000000F PRSSEL CLK async channel select 0 4 read-write CONSUMER_USART0_IR IR Consumer Register 0x188 read-write 0x00000000 0x0000000F PRSSEL IR async channel select 0 4 read-write CONSUMER_USART0_RX RX Consumer Register 0x18C read-write 0x00000000 0x0000000F PRSSEL RX async channel select 0 4 read-write CONSUMER_USART0_TRIGGER TRIGGER Consumer Register 0x190 read-write 0x00000000 0x0000000F PRSSEL TRIGGER async channel select 0 4 read-write CONSUMER_USART1_CLK CLK Consumer Register 0x194 read-write 0x00000000 0x0000000F PRSSEL CLK async channel select 0 4 read-write CONSUMER_USART1_IR IR Consumer Register 0x198 read-write 0x00000000 0x0000000F PRSSEL IR async channel select 0 4 read-write CONSUMER_USART1_RX RX Consumer Register 0x19C read-write 0x00000000 0x0000000F PRSSEL RX async channel select 0 4 read-write CONSUMER_USART1_TRIGGER TRIGGER Consumer Register 0x1A0 read-write 0x00000000 0x0000000F PRSSEL TRIGGER async channel select 0 4 read-write CONSUMER_WDOG0_SRC0 SRC0 Consumer Register 0x1A4 read-write 0x00000000 0x0000000F PRSSEL SRC0 async channel select 0 4 read-write CONSUMER_WDOG0_SRC1 SRC1 Consumer Register 0x1A8 read-write 0x00000000 0x0000000F PRSSEL SRC1 async channel select 0 4 read-write GPIO_NS 1 GPIO_NS Registers 0x5003C000 0x00000000 0x00001000 registers GPIO_ODD 25 GPIO_EVEN 26 PORTA_CTRL Port control 0x000 read-write 0x00400040 0x10701070 SLEWRATE Slew Rate 4 3 read-write DINDIS Data In Disable 12 1 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write DINDISALT Data In Disable Alt 28 1 read-write PORTA_MODEL mode low 0x004 read-write 0x00000000 0xFFFFFFFF MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE4 MODE n 16 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE5 MODE n 20 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE6 MODE n 24 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE7 MODE n 28 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTA_MODEH mode high 0x00C read-write 0x00000000 0x0000000F MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTA_DOUT data out 0x010 read-write 0x00000000 0x000001FF DOUT Data output 0 9 read-write PORTA_DIN data in 0x014 read-only 0x00000000 0x000001FF DIN Data input 0 9 read-only PORTB_CTRL Port control 0x030 read-write 0x00400040 0x10701070 SLEWRATE Slew Rate 4 3 read-write DINDIS Data In Disable 12 1 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write DINDISALT Data In Disable Alt 28 1 read-write PORTB_MODEL mode low 0x034 read-write 0x00000000 0x000FFFFF MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE4 MODE n 16 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTB_DOUT data out 0x040 read-write 0x00000000 0x0000001F DOUT Data output 0 5 read-write PORTB_DIN data in 0x044 read-only 0x00000000 0x0000001F DIN Data input 0 5 read-only PORTC_CTRL Port control 0x060 read-write 0x00400040 0x10701070 SLEWRATE Slew Rate 4 3 read-write DINDIS Data In Disable 12 1 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write DINDISALT Data In Disable Alt 28 1 read-write PORTC_MODEL mode low 0x064 read-write 0x00000000 0xFFFFFFFF MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE4 MODE n 16 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE5 MODE n 20 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE6 MODE n 24 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE7 MODE n 28 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTC_DOUT data out 0x070 read-write 0x00000000 0x000000FF DOUT Data output 0 8 read-write PORTC_DIN data in 0x074 read-only 0x00000000 0x000000FF DIN Data input 0 8 read-only PORTD_CTRL Port control 0x090 read-write 0x00400040 0x10701070 SLEWRATE Slew Rate 4 3 read-write DINDIS Data In Disable 12 1 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write DINDISALT Data In Disable Alt 28 1 read-write PORTD_MODEL mode low 0x094 read-write 0x00000000 0x0000FFFF MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 PORTD_DOUT data out 0x0A0 read-write 0x00000000 0x0000000F DOUT Data output 0 4 read-write PORTD_DIN data in 0x0A4 read-only 0x00000000 0x0000000F DIN Data input 0 4 read-only LOCK No Description 0x300 write-only 0x0000A534 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Unlock code 42292 GPIOLOCKSTATUS No Description 0x310 read-only 0x00000000 0x00000001 LOCK GPIO LOCK status 0 1 read-only UNLOCKED Registers are unlocked 0 LOCKED Registers are locked 1 ABUSALLOC A Bus allocation 0x320 read-write 0x00000000 0x0F0F0F0F AEVEN0 A Bus Even 0 0 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 AEVEN1 A Bus Even 1 8 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 AODD0 A Bus Odd 0 16 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 AODD1 A Bus Odd 1 24 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 BBUSALLOC B Bus allocation 0x324 read-write 0x00000000 0x0F0F0F0F BEVEN0 B Bus Even 0 0 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 BEVEN1 B Bus Even 1 8 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 BODD0 B Bus Odd 0 16 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 BODD1 B Bus Odd 1 24 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 CDBUSALLOC CD Bus allocation 0x328 read-write 0x00000000 0x0F0F0F0F CDEVEN0 CD Bus Even 0 0 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 CDEVEN1 CD Bus Even 1 8 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 CDODD0 CD Bus Odd 0 16 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 CDODD1 CD Bus Odd 1 24 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 EXTIPSELL External Interrupt Port Select Low 0x400 read-write 0x00000000 0x33333333 EXTIPSEL0 External Interrupt Port Select 0 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL1 External Interrupt Port Select 4 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL2 External Interrupt Port Select 8 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL3 External Interrupt Port Select 12 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL4 External Interrupt Port Select 16 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL5 External Interrupt Port Select 20 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL6 External Interrupt Port Select 24 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL7 External Interrupt Port Select 28 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSELH External interrupt Port Select High 0x404 read-write 0x00000000 0x00003333 EXTIPSEL0 External Interrupt Port Select 0 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL1 External Interrupt Port Select 4 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL2 External Interrupt Port Select 8 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL3 External Interrupt Port Select 12 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPINSELL External Interrupt Pin Select Low 0x408 read-write 0x00000000 0x33333333 EXTIPINSEL0 External Interrupt Pin select 0 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL1 External Interrupt Pin select 4 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL2 External Interrupt Pin select 8 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL3 External Interrupt Pin select 12 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL4 External Interrupt Pin select 16 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL5 External Interrupt Pin select 20 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL6 External Interrupt Pin select 24 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL7 External Interrupt Pin select 28 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSELH External Interrupt Pin Select High 0x40C read-write 0x00000000 0x00003333 EXTIPINSEL0 External Interrupt Pin select 0 2 read-write OFFSET8 OFFSET=8 0 OFFSET9 OFFSET=9 1 OFFSET10 OFFSET=10 2 OFFSET11 OFFSET=11 3 EXTIPINSEL1 External Interrupt Pin select 4 2 read-write OFFSET8 OFFSET=8 0 OFFSET9 OFFSET=9 1 OFFSET10 OFFSET=10 2 OFFSET11 OFFSET=11 3 EXTIPINSEL2 External Interrupt Pin select 8 2 read-write OFFSET8 OFFSET=8 0 OFFSET9 OFFSET=9 1 OFFSET10 OFFSET=10 2 OFFSET11 OFFSET=11 3 EXTIPINSEL3 External Interrupt Pin select 12 2 read-write OFFSET8 OFFSET=8 0 OFFSET9 OFFSET=9 1 OFFSET10 OFFSET=10 2 OFFSET11 OFFSET=11 3 EXTIRISE External Interrupt Rising Edge Trigger 0x410 read-write 0x00000000 0x00000FFF EXTIRISE EXT Int Rise 0 12 read-write EXTIFALL External Interrupt Falling Edge Trigger 0x414 read-write 0x00000000 0x00000FFF EXTIFALL EXT Int FALL 0 12 read-write IF Interrupt Flag 0x420 read-write 0x00000000 0x0FFF0FFF EXTIF0 External Pin Flag 0 1 read-write EXTIF1 External Pin Flag 1 1 read-write EXTIF2 External Pin Flag 2 1 read-write EXTIF3 External Pin Flag 3 1 read-write EXTIF4 External Pin Flag 4 1 read-write EXTIF5 External Pin Flag 5 1 read-write EXTIF6 External Pin Flag 6 1 read-write EXTIF7 External Pin Flag 7 1 read-write EXTIF8 External Pin Flag 8 1 read-write EXTIF9 External Pin Flag 9 1 read-write EXTIF10 External Pin Flag 10 1 read-write EXTIF11 External Pin Flag 11 1 read-write EM4WU EM4 wake up 16 12 read-write IEN Interrupt Enable 0x424 read-write 0x00000000 0x0FFF0FFF EXTIEN0 External Pin Enable 0 1 read-write EXTIEN1 External Pin Enable 1 1 read-write EXTIEN2 External Pin Enable 2 1 read-write EXTIEN3 External Pin Enable 3 1 read-write EXTIEN4 External Pin Enable 4 1 read-write EXTIEN5 External Pin Enable 5 1 read-write EXTIEN6 External Pin Enable 6 1 read-write EXTIEN7 External Pin Enable 7 1 read-write EXTIEN8 External Pin Enable 8 1 read-write EXTIEN9 External Pin Enable 9 1 read-write EXTIEN10 External Pin Enable 10 1 read-write EXTIEN11 External Pin Enable 11 1 read-write EM4WUIEN0 EM4 Wake Up Interrupt En 16 1 read-write EM4WUIEN1 EM4 Wake Up Interrupt En 17 1 read-write EM4WUIEN2 EM4 Wake Up Interrupt En 18 1 read-write EM4WUIEN3 EM4 Wake Up Interrupt En 19 1 read-write EM4WUIEN4 EM4 Wake Up Interrupt En 20 1 read-write EM4WUIEN5 EM4 Wake Up Interrupt En 21 1 read-write EM4WUIEN6 EM4 Wake Up Interrupt En 22 1 read-write EM4WUIEN7 EM4 Wake Up Interrupt En 23 1 read-write EM4WUIEN8 EM4 Wake Up Interrupt En 24 1 read-write EM4WUIEN9 EM4 Wake Up Interrupt En 25 1 read-write EM4WUIEN10 EM4 Wake Up Interrupt En 26 1 read-write EM4WUIEN11 EM4 Wake Up Interrupt En 27 1 read-write EM4WUEN No Description 0x42C read-write 0x00000000 0x0FFF0000 EM4WUEN EM4 wake up enable 16 12 read-write EM4WUPOL No Description 0x430 read-write 0x00000000 0x0FFF0000 EM4WUPOL EM4 Wake-Up Polarity 16 12 read-write DBGROUTEPEN No Description 0x440 read-write 0x0000000F 0x0000000F SWCLKTCKPEN Route Pin Enable 0 1 read-write SWDIOTMSPEN Route Location 0 1 1 read-write TDOPEN JTAG Test Debug Output Pin Enable 2 1 read-write TDIPEN JTAG Test Debug Input Pin Enable 3 1 read-write TRACEROUTEPEN No Description 0x444 read-write 0x00000000 0x00000007 SWVPEN Serial Wire Viewer Output Pin Enable 0 1 read-write TRACECLKPEN Trace Clk Pin Enable 1 1 read-write TRACEDATA0PEN Trace Data0 Pin Enable 2 1 read-write CMU_ROUTEEN CMU pin enable 0x450 read-write 0x00000000 0x0000000F CLKOUT0PEN CLKOUT0 pin enable control bit 0 1 read-write CLKOUT1PEN CLKOUT1 pin enable control bit 1 1 read-write CLKOUT2PEN CLKOUT2 pin enable control bit 2 1 read-write CMU_CLKIN0ROUTE CLKIN0 port/pin select 0x454 read-write 0x00000000 0x000F0003 PORT CLKIN0 port select register 0 2 read-write PIN CLKIN0 pin select register 16 4 read-write CMU_CLKOUT0ROUTE CLKOUT0 port/pin select 0x458 read-write 0x00000000 0x000F0003 PORT CLKOUT0 port select register 0 2 read-write PIN CLKOUT0 pin select register 16 4 read-write CMU_CLKOUT1ROUTE CLKOUT1 port/pin select 0x45C read-write 0x00000000 0x000F0003 PORT CLKOUT1 port select register 0 2 read-write PIN CLKOUT1 pin select register 16 4 read-write CMU_CLKOUT2ROUTE CLKOUT2 port/pin select 0x460 read-write 0x00000000 0x000F0003 PORT CLKOUT2 port select register 0 2 read-write PIN CLKOUT2 pin select register 16 4 read-write DCDC_ROUTEEN DCDC pin enable 0x46C read-write 0x00000000 0x00000003 DCDCCOREHIDDENPEN DCDCCOREHIDDEN pin enable control bit 0 1 read-write I2C0_ROUTEEN I2C0 pin enable 0x490 read-write 0x00000000 0x00000003 SCLPEN SCL pin enable control bit 0 1 read-write SDAPEN SDA pin enable control bit 1 1 read-write I2C0_SCLROUTE SCL port/pin select 0x494 read-write 0x00000000 0x000F0003 PORT SCL port select register 0 2 read-write PIN SCL pin select register 16 4 read-write I2C0_SDAROUTE SDA port/pin select 0x498 read-write 0x00000000 0x000F0003 PORT SDA port select register 0 2 read-write PIN SDA pin select register 16 4 read-write I2C1_ROUTEEN I2C1 pin enable 0x4A0 read-write 0x00000000 0x00000003 SCLPEN SCL pin enable control bit 0 1 read-write SDAPEN SDA pin enable control bit 1 1 read-write I2C1_SCLROUTE SCL port/pin select 0x4A4 read-write 0x00000000 0x000F0003 PORT SCL port select register 0 2 read-write PIN SCL pin select register 16 4 read-write I2C1_SDAROUTE SDA port/pin select 0x4A8 read-write 0x00000000 0x000F0003 PORT SDA port select register 0 2 read-write PIN SDA pin select register 16 4 read-write LETIMER0_ROUTEEN LETIMER pin enable 0x4B0 read-write 0x00000000 0x00000003 OUT0PEN OUT0 pin enable control bit 0 1 read-write OUT1PEN OUT1 pin enable control bit 1 1 read-write LETIMER0_OUT0ROUTE OUT0 port/pin select 0x4B4 read-write 0x00000000 0x000F0003 PORT OUT0 port select register 0 2 read-write PIN OUT0 pin select register 16 4 read-write LETIMER0_OUT1ROUTE OUT1 port/pin select 0x4B8 read-write 0x00000000 0x000F0003 PORT OUT1 port select register 0 2 read-write PIN OUT1 pin select register 16 4 read-write EUART0_ROUTEEN EUART pin enable 0x4C0 read-write 0x00000000 0x00000003 RTSPEN RTS pin enable control bit 0 1 read-write TXPEN TX pin enable control bit 1 1 read-write EUART0_CTSROUTE CTS port/pin select 0x4C4 read-write 0x00000000 0x000F0003 PORT CTS port select register 0 2 read-write PIN CTS pin select register 16 4 read-write EUART0_RTSROUTE RTS port/pin select 0x4C8 read-write 0x00000000 0x000F0003 PORT RTS port select register 0 2 read-write PIN RTS pin select register 16 4 read-write EUART0_RXROUTE RX port/pin select 0x4CC read-write 0x00000000 0x000F0003 PORT RX port select register 0 2 read-write PIN RX pin select register 16 4 read-write EUART0_TXROUTE TX port/pin select 0x4D0 read-write 0x00000000 0x000F0003 PORT TX port select register 0 2 read-write PIN TX pin select register 16 4 read-write PDM_ROUTEEN PDM pin enable 0x520 read-write 0x00000000 0x00000001 CLKPEN CLK pin enable control bit 0 1 read-write PDM_CLKROUTE CLK port/pin select 0x524 read-write 0x00000000 0x000F0003 PORT CLK port select register 0 2 read-write PIN CLK pin select register 16 4 read-write PDM_DAT0ROUTE DAT0 port/pin select 0x528 read-write 0x00000000 0x000F0003 PORT DAT0 port select register 0 2 read-write PIN DAT0 pin select register 16 4 read-write PDM_DAT1ROUTE DAT1 port/pin select 0x52C read-write 0x00000000 0x000F0003 PORT DAT1 port select register 0 2 read-write PIN DAT1 pin select register 16 4 read-write PRS0_ROUTEEN PRS0 pin enable 0x534 read-write 0x00000000 0x0000FFFF ASYNCH0PEN ASYNCH0 pin enable control bit 0 1 read-write ASYNCH1PEN ASYNCH1 pin enable control bit 1 1 read-write ASYNCH2PEN ASYNCH2 pin enable control bit 2 1 read-write ASYNCH3PEN ASYNCH3 pin enable control bit 3 1 read-write ASYNCH4PEN ASYNCH4 pin enable control bit 4 1 read-write ASYNCH5PEN ASYNCH5 pin enable control bit 5 1 read-write ASYNCH6PEN ASYNCH6 pin enable control bit 6 1 read-write ASYNCH7PEN ASYNCH7 pin enable control bit 7 1 read-write ASYNCH8PEN ASYNCH8 pin enable control bit 8 1 read-write ASYNCH9PEN ASYNCH9 pin enable control bit 9 1 read-write ASYNCH10PEN ASYNCH10 pin enable control bit 10 1 read-write ASYNCH11PEN ASYNCH11 pin enable control bit 11 1 read-write SYNCH0PEN SYNCH0 pin enable control bit 12 1 read-write SYNCH1PEN SYNCH1 pin enable control bit 13 1 read-write SYNCH2PEN SYNCH2 pin enable control bit 14 1 read-write SYNCH3PEN SYNCH3 pin enable control bit 15 1 read-write PRS0_ASYNCH0ROUTE ASYNCH0 port/pin select 0x538 read-write 0x00000000 0x000F0003 PORT ASYNCH0 port select register 0 2 read-write PIN ASYNCH0 pin select register 16 4 read-write PRS0_ASYNCH1ROUTE ASYNCH1 port/pin select 0x53C read-write 0x00000000 0x000F0003 PORT ASYNCH1 port select register 0 2 read-write PIN ASYNCH1 pin select register 16 4 read-write PRS0_ASYNCH2ROUTE ASYNCH2 port/pin select 0x540 read-write 0x00000000 0x000F0003 PORT ASYNCH2 port select register 0 2 read-write PIN ASYNCH2 pin select register 16 4 read-write PRS0_ASYNCH3ROUTE ASYNCH3 port/pin select 0x544 read-write 0x00000000 0x000F0003 PORT ASYNCH3 port select register 0 2 read-write PIN ASYNCH3 pin select register 16 4 read-write PRS0_ASYNCH4ROUTE ASYNCH4 port/pin select 0x548 read-write 0x00000000 0x000F0003 PORT ASYNCH4 port select register 0 2 read-write PIN ASYNCH4 pin select register 16 4 read-write PRS0_ASYNCH5ROUTE ASYNCH5 port/pin select 0x54C read-write 0x00000000 0x000F0003 PORT ASYNCH5 port select register 0 2 read-write PIN ASYNCH5 pin select register 16 4 read-write PRS0_ASYNCH6ROUTE ASYNCH6 port/pin select 0x550 read-write 0x00000000 0x000F0003 PORT ASYNCH6 port select register 0 2 read-write PIN ASYNCH6 pin select register 16 4 read-write PRS0_ASYNCH7ROUTE ASYNCH7 port/pin select 0x554 read-write 0x00000000 0x000F0003 PORT ASYNCH7 port select register 0 2 read-write PIN ASYNCH7 pin select register 16 4 read-write PRS0_ASYNCH8ROUTE ASYNCH8 port/pin select 0x558 read-write 0x00000000 0x000F0003 PORT ASYNCH8 port select register 0 2 read-write PIN ASYNCH8 pin select register 16 4 read-write PRS0_ASYNCH9ROUTE ASYNCH9 port/pin select 0x55C read-write 0x00000000 0x000F0003 PORT ASYNCH9 port select register 0 2 read-write PIN ASYNCH9 pin select register 16 4 read-write PRS0_ASYNCH10ROUTE ASYNCH10 port/pin select 0x560 read-write 0x00000000 0x000F0003 PORT ASYNCH10 port select register 0 2 read-write PIN ASYNCH10 pin select register 16 4 read-write PRS0_ASYNCH11ROUTE ASYNCH11 port/pin select 0x564 read-write 0x00000000 0x000F0003 PORT ASYNCH11 port select register 0 2 read-write PIN ASYNCH11 pin select register 16 4 read-write PRS0_SYNCH0ROUTE SYNCH0 port/pin select 0x568 read-write 0x00000000 0x000F0003 PORT SYNCH0 port select register 0 2 read-write PIN SYNCH0 pin select register 16 4 read-write PRS0_SYNCH1ROUTE SYNCH1 port/pin select 0x56C read-write 0x00000000 0x000F0003 PORT SYNCH1 port select register 0 2 read-write PIN SYNCH1 pin select register 16 4 read-write PRS0_SYNCH2ROUTE SYNCH2 port/pin select 0x570 read-write 0x00000000 0x000F0003 PORT SYNCH2 port select register 0 2 read-write PIN SYNCH2 pin select register 16 4 read-write PRS0_SYNCH3ROUTE SYNCH3 port/pin select 0x574 read-write 0x00000000 0x000F0003 PORT SYNCH3 port select register 0 2 read-write PIN SYNCH3 pin select register 16 4 read-write TIMER0_ROUTEEN TIMER0 pin enable 0x57C read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER0_CC0ROUTE CC0 port/pin select 0x580 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER0_CC1ROUTE CC1 port/pin select 0x584 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER0_CC2ROUTE CC2 port/pin select 0x588 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER0_CDTI0ROUTE CDTI0 port/pin select 0x58C read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER0_CDTI1ROUTE CDTI1 port/pin select 0x590 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER0_CDTI2ROUTE CDTI2 port/pin select 0x594 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write TIMER1_ROUTEEN TIMER1 pin enable 0x59C read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER1_CC0ROUTE CC0 port/pin select 0x5A0 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER1_CC1ROUTE CC1 port/pin select 0x5A4 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER1_CC2ROUTE CC2 port/pin select 0x5A8 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER1_CDTI0ROUTE CDTI0 port/pin select 0x5AC read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER1_CDTI1ROUTE CDTI1 port/pin select 0x5B0 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER1_CDTI2ROUTE CDTI2 port/pin select 0x5B4 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write TIMER2_ROUTEEN TIMER2 pin enable 0x5BC read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER2_CC0ROUTE CC0 port/pin select 0x5C0 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER2_CC1ROUTE CC1 port/pin select 0x5C4 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER2_CC2ROUTE CC2 port/pin select 0x5C8 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER2_CDTI0ROUTE CDTI0 port/pin select 0x5CC read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER2_CDTI1ROUTE CDTI1 port/pin select 0x5D0 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER2_CDTI2ROUTE CDTI2 port/pin select 0x5D4 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write TIMER3_ROUTEEN TIMER3 pin enable 0x5DC read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER3_CC0ROUTE CC0 port/pin select 0x5E0 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER3_CC1ROUTE CC1 port/pin select 0x5E4 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER3_CC2ROUTE CC2 port/pin select 0x5E8 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER3_CDTI0ROUTE CDTI0 port/pin select 0x5EC read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER3_CDTI1ROUTE CDTI1 port/pin select 0x5F0 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER3_CDTI2ROUTE CDTI2 port/pin select 0x5F4 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write TIMER4_ROUTEEN TIMER4 pin enable 0x5FC read-write 0x00000000 0x0000003F CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CCC0PEN CCC0 pin enable control bit 3 1 read-write CCC1PEN CCC1 pin enable control bit 4 1 read-write CCC2PEN CCC2 pin enable control bit 5 1 read-write TIMER4_CC0ROUTE CC0 port/pin select 0x600 read-write 0x00000000 0x000F0003 PORT CC0 port select register 0 2 read-write PIN CC0 pin select register 16 4 read-write TIMER4_CC1ROUTE CC1 port/pin select 0x604 read-write 0x00000000 0x000F0003 PORT CC1 port select register 0 2 read-write PIN CC1 pin select register 16 4 read-write TIMER4_CC2ROUTE CC2 port/pin select 0x608 read-write 0x00000000 0x000F0003 PORT CC2 port select register 0 2 read-write PIN CC2 pin select register 16 4 read-write TIMER4_CDTI0ROUTE CDTI0 port/pin select 0x60C read-write 0x00000000 0x000F0003 PORT CCC0 port select register 0 2 read-write PIN CCC0 pin select register 16 4 read-write TIMER4_CDTI1ROUTE CDTI1 port/pin select 0x610 read-write 0x00000000 0x000F0003 PORT CCC1 port select register 0 2 read-write PIN CCC1 pin select register 16 4 read-write TIMER4_CDTI2ROUTE CDTI2 port/pin select 0x614 read-write 0x00000000 0x000F0003 PORT CCC2 port select register 0 2 read-write PIN CCC2 pin select register 16 4 read-write USART0_ROUTEEN USART0 pin enable 0x61C read-write 0x00000000 0x0000001F CSPEN CS pin enable control bit 0 1 read-write RTSPEN RTS pin enable control bit 1 1 read-write RXPEN RX pin enable control bit 2 1 read-write CLKPEN SCLK pin enable control bit 3 1 read-write TXPEN TX pin enable control bit 4 1 read-write USART0_CSROUTE CS port/pin select 0x620 read-write 0x00000000 0x000F0003 PORT CS port select register 0 2 read-write PIN CS pin select register 16 4 read-write USART0_CTSROUTE CTS port/pin select 0x624 read-write 0x00000000 0x000F0003 PORT CTS port select register 0 2 read-write PIN CTS pin select register 16 4 read-write USART0_RTSROUTE RTS port/pin select 0x628 read-write 0x00000000 0x000F0003 PORT RTS port select register 0 2 read-write PIN RTS pin select register 16 4 read-write USART0_RXROUTE RX port/pin select 0x62C read-write 0x00000000 0x000F0003 PORT RX port select register 0 2 read-write PIN RX pin select register 16 4 read-write USART0_CLKROUTE SCLK port/pin select 0x630 read-write 0x00000000 0x000F0003 PORT SCLK port select register 0 2 read-write PIN SCLK pin select register 16 4 read-write USART0_TXROUTE TX port/pin select 0x634 read-write 0x00000000 0x000F0003 PORT TX port select register 0 2 read-write PIN TX pin select register 16 4 read-write USART1_ROUTEEN USART1 pin enable 0x63C read-write 0x00000000 0x0000001F CSPEN CS pin enable control bit 0 1 read-write RTSPEN RTS pin enable control bit 1 1 read-write RXPEN RX pin enable control bit 2 1 read-write CLKPEN SCLK pin enable control bit 3 1 read-write TXPEN TX pin enable control bit 4 1 read-write USART1_CSROUTE CS port/pin select 0x640 read-write 0x00000000 0x000F0003 PORT CS port select register 0 2 read-write PIN CS pin select register 16 4 read-write USART1_CTSROUTE CTS port/pin select 0x644 read-write 0x00000000 0x000F0003 PORT CTS port select register 0 2 read-write PIN CTS pin select register 16 4 read-write USART1_RTSROUTE RTS port/pin select 0x648 read-write 0x00000000 0x000F0003 PORT RTS port select register 0 2 read-write PIN RTS pin select register 16 4 read-write USART1_RXROUTE RX port/pin select 0x64C read-write 0x00000000 0x000F0003 PORT RX port select register 0 2 read-write PIN RX pin select register 16 4 read-write USART1_CLKROUTE SCLK port/pin select 0x650 read-write 0x00000000 0x000F0003 PORT SCLK port select register 0 2 read-write PIN SCLK pin select register 16 4 read-write USART1_TXROUTE TX port/pin select 0x654 read-write 0x00000000 0x000F0003 PORT TX port select register 0 2 read-write PIN TX pin select register 16 4 read-write LDMA_NS 0 LDMA_NS Registers 0x50040000 0x00000000 0x00001000 registers LDMA 21 IPVERSION No Description 0x000 read-only 0x00000000 0x000000FF IPVERSION IPVERSION 0 8 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN LDMA module enable and disable register 0 1 read-write CTRL No Description 0x008 read-write 0x1E000000 0x9F000000 NUMFIXED Number of Fixed Priority Channels 24 5 read-write CORERST Reset DMA controller 31 1 read-write STATUS No Description 0x00C read-only 0x1F100000 0x1F1F1FFB ANYBUSY Any DMA Channel Busy 0 1 read-only ANYREQ Any DMA Channel Request Pending 1 1 read-only CHGRANT Granted Channel Number 3 5 read-only CHERROR Errant Channel Number 8 5 read-only FIFOLEVEL FIFO Level 16 5 read-only CHNUM Number of Channels 24 5 read-only SYNCSWSET No Description 0x010 write-only 0x00000000 0x000000FF SYNCSWSET DMA SYNC Software Trigger Set 0 8 write-only SYNCSWCLR No Description 0x014 write-only 0x00000000 0x000000FF SYNCSWCLR DMA SYNC Software Trigger Clear 0 8 write-only SYNCHWEN No Description 0x018 read-write 0x00000000 0x00FF00FF SYNCSETEN Hardware Sync Trigger Set Enable 0 8 read-write SYNCCLREN Hardware Sync Trigger Clear Enable 16 8 read-write SYNCHWSEL No Description 0x01C read-write 0x00000000 0x00FF00FF SYNCSETEDGE Hardware Sync Trigger Set Edge Select 0 8 read-write RISE Use rising edge detection 0 FALL Use falling edge detection 1 SYNCCLREDGE Hardware Sync Trigger Clear Edge Select 16 8 read-write RISE Use rising edge detection 0 FALL Use falling edge detection 1 SYNCSTATUS No Description 0x020 read-only 0x00000000 0x000000FF SYNCTRIG sync trig status 0 8 read-only CHEN No Description 0x024 write-only 0x00000000 0x000000FF CHEN Channel Enables 0 8 write-only CHDIS No Description 0x028 write-only 0x00000000 0x000000FF CHDIS DMA Channel disable 0 8 write-only CHSTATUS No Description 0x02C read-only 0x00000000 0x000000FF CHSTATUS DMA Channel Status 0 8 read-only CHBUSY No Description 0x030 read-only 0x00000000 0x000000FF BUSY Channels Busy 0 8 read-only CHDONE No Description 0x034 read-write 0x00000000 0x000000FF CHDONE0 DMA Channel Link done intr flag 0 1 read-write CHDONE1 DMA Channel Link done intr flag 1 1 read-write CHDONE2 DMA Channel Link done intr flag 2 1 read-write CHDONE3 DMA Channel Link done intr flag 3 1 read-write CHDONE4 DMA Channel Link done intr flag 4 1 read-write CHDONE5 DMA Channel Link done intr flag 5 1 read-write CHDONE6 DMA Channel Link done intr flag 6 1 read-write CHDONE7 DMA Channel Link done intr flag 7 1 read-write DBGHALT No Description 0x038 read-write 0x00000000 0x000000FF DBGHALT DMA Debug Halt 0 8 read-write SWREQ No Description 0x03C write-only 0x00000000 0x000000FF SWREQ Software Transfer Requests 0 8 write-only REQDIS No Description 0x040 read-write 0x00000000 0x000000FF REQDIS DMA Request Disables 0 8 read-write REQPEND No Description 0x044 read-only 0x00000000 0x000000FF REQPEND DMA Requests Pending 0 8 read-only LINKLOAD No Description 0x048 write-only 0x00000000 0x000000FF LINKLOAD DMA Link Loads 0 8 write-only REQCLEAR No Description 0x04C write-only 0x00000000 0x000000FF REQCLEAR DMA Request Clear 0 8 write-only IF No Description 0x050 read-write 0x00000000 0x800000FF DONE0 DMA Structure Operation Done 0 1 read-write DONE1 DMA Structure Operation Done 1 1 read-write DONE2 DMA Structure Operation Done 2 1 read-write DONE3 DMA Structure Operation Done 3 1 read-write DONE4 DMA Structure Operation Done 4 1 read-write DONE5 DMA Structure Operation Done 5 1 read-write DONE6 DMA Structure Operation Done 6 1 read-write DONE7 DMA Structure Operation Done 7 1 read-write ERROR Error Flag 31 1 read-write IEN No Description 0x054 read-write 0x00000000 0x800000FF CHDONE Enable or disable the done interrupt 0 8 read-write ERROR Enable or disable the error interrupt 31 1 read-write CH0_CFG No Description 0x05C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH0_LOOP No Description 0x060 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH0_CTRL No Description 0x064 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH0_SRC No Description 0x068 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH0_DST No Description 0x06C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH0_LINK No Description 0x070 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH1_CFG No Description 0x08C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH1_LOOP No Description 0x090 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH1_CTRL No Description 0x094 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH1_SRC No Description 0x098 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH1_DST No Description 0x09C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH1_LINK No Description 0x0A0 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH2_CFG No Description 0x0BC read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH2_LOOP No Description 0x0C0 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH2_CTRL No Description 0x0C4 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH2_SRC No Description 0x0C8 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH2_DST No Description 0x0CC read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH2_LINK No Description 0x0D0 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH3_CFG No Description 0x0EC read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH3_LOOP No Description 0x0F0 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH3_CTRL No Description 0x0F4 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH3_SRC No Description 0x0F8 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH3_DST No Description 0x0FC read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH3_LINK No Description 0x100 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH4_CFG No Description 0x11C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH4_LOOP No Description 0x120 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH4_CTRL No Description 0x124 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH4_SRC No Description 0x128 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH4_DST No Description 0x12C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH4_LINK No Description 0x130 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH5_CFG No Description 0x14C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH5_LOOP No Description 0x150 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH5_CTRL No Description 0x154 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH5_SRC No Description 0x158 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH5_DST No Description 0x15C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH5_LINK No Description 0x160 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH6_CFG No Description 0x17C read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH6_LOOP No Description 0x180 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH6_CTRL No Description 0x184 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH6_SRC No Description 0x188 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH6_DST No Description 0x18C read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH6_LINK No Description 0x190 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write CH7_CFG No Description 0x1AC read-write 0x00000000 0x00330000 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 CH7_LOOP No Description 0x1B0 read-write 0x00000000 0x000000FF LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH7_CTRL No Description 0x1B4 read-write 0x00000000 0xFFFFFFFB STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 STRUCTREQ Structure DMA Transfer Request 3 1 read-only XFERCNT DMA Unit Data Transfer Count 4 11 read-write BYTESWAP Endian Byte Swap 15 1 read-write BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 DECLOOPCNT Decrement Loop Count 22 1 read-write IGNORESREQ Ignore Sreq 23 1 read-write SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 CH7_SRC No Description 0x1B8 read-write 0x00000000 0xFFFFFFFF SRCADDR Source Data Address 0 32 read-write CH7_DST No Description 0x1BC read-write 0x00000000 0xFFFFFFFF DSTADDR Destination Data Address 0 32 read-write CH7_LINK No Description 0x1C0 read-write 0x00000000 0xFFFFFFFF LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LDMAXBAR_NS 1 LDMAXBAR_NS Registers 0x50044000 0x00000000 0x00001000 registers CH0_REQSEL No Description 0x000 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH1_REQSEL No Description 0x004 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH2_REQSEL No Description 0x008 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH3_REQSEL No Description 0x00C read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH4_REQSEL No Description 0x010 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH5_REQSEL No Description 0x014 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH6_REQSEL No Description 0x018 read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH7_REQSEL No Description 0x01C read-write 0x00000000 0x003F000F SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write TIMER0_NS 0 TIMER0_NS Registers 0x50048000 0x00000000 0x00001000 registers TIMER0 7 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0xFFFFFFFF TOP Counter Top Value 0 32 read-write TOPB No Description 0x020 read-write 0x00000000 0xFFFFFFFF TOPB Counter Top Buffer Register 0 32 read-write CNT No Description 0x024 read-write 0x00000000 0xFFFFFFFF CNT Counter Value 0 32 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0xFFFFFFFF OCB Output Compare Value Buffer 0 32 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0xFFFFFFFF ICF Input Capture FIFO 0 32 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0xFFFFFFFF ICOF Input Capture FIFO Overflow 0 32 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0xFFFFFFFF OCB Output Compare Value Buffer 0 32 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0xFFFFFFFF ICF Input Capture FIFO 0 32 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0xFFFFFFFF ICOF Input Capture FIFO Overflow 0 32 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0xFFFFFFFF OCB Output Compare Value Buffer 0 32 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0xFFFFFFFF ICF Input Capture FIFO 0 32 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0xFFFFFFFF ICOF Input Capture FIFO Overflow 0 32 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 TIMER1_NS 0 TIMER1_NS Registers 0x5004C000 0x00000000 0x00001000 registers TIMER1 8 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0x0000FFFF TOP Counter Top Value 0 16 read-write TOPB No Description 0x020 read-write 0x00000000 0x0000FFFF TOPB Counter Top Buffer Register 0 16 read-write CNT No Description 0x024 read-write 0x00000000 0x0000FFFF CNT Counter Value 0 16 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 TIMER2_NS 0 TIMER2_NS Registers 0x50050000 0x00000000 0x00001000 registers TIMER2 9 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0x0000FFFF TOP Counter Top Value 0 16 read-write TOPB No Description 0x020 read-write 0x00000000 0x0000FFFF TOPB Counter Top Buffer Register 0 16 read-write CNT No Description 0x024 read-write 0x00000000 0x0000FFFF CNT Counter Value 0 16 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 TIMER3_NS 0 TIMER3_NS Registers 0x50054000 0x00000000 0x00001000 registers TIMER3 10 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0x0000FFFF TOP Counter Top Value 0 16 read-write TOPB No Description 0x020 read-write 0x00000000 0x0000FFFF TOPB Counter Top Buffer Register 0 16 read-write CNT No Description 0x024 read-write 0x00000000 0x0000FFFF CNT Counter Value 0 16 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 TIMER4_NS 0 TIMER4_NS Registers 0x50058000 0x00000000 0x00001000 registers TIMER4 11 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only CFG No Description 0x004 read-write 0x00000000 0x0FFF1FFB MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 OSMEN One-shot Mode Enable 4 1 read-write QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DMACLRACT DMA Request Clear on Active 7 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 ATI Always Track Inputs 16 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV4 Prescale by 4 3 DIV8 Prescale by 8 7 DIV16 Prescale by 16 15 DIV32 Prescale by 32 31 DIV64 Prescale by 64 63 DIV128 Prescale by 128 127 DIV256 Prescale by 256 255 DIV512 Prescale by 512 511 DIV1024 Prescale by 1024 1023 CTRL No Description 0x008 read-write 0x00000000 0x0000001F RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x07070777 RUNNING Running 0 1 read-only DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 TOPBV TOP Buffer Valid 2 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 SYNCBUSY Sync Busy 6 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 IF No Description 0x014 read-write 0x00000000 0x07770077 OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write IEN No Description 0x018 read-write 0x00000000 0x07770077 OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write TOP No Description 0x01C read-write 0x0000FFFF 0x0000FFFF TOP Counter Top Value 0 16 read-write TOPB No Description 0x020 read-write 0x00000000 0x0000FFFF TOPB Counter Top Buffer Register 0 16 read-write CNT No Description 0x024 read-write 0x00000000 0x0000FFFF CNT Counter Value 0 16 read-write LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 EN No Description 0x030 read-write 0x00000000 0x00000001 EN Timer Module Enable 0 1 read-write CC0_CFG No Description 0x060 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC0_CTRL No Description 0x064 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC0_OC No Description 0x068 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x070 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC0_ICF No Description 0x074 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x078 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC1_CFG No Description 0x080 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC1_CTRL No Description 0x084 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC1_OC No Description 0x088 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x090 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC1_ICF No Description 0x094 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x098 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only CC2_CFG No Description 0x0A0 read-write 0x00000000 0x003E0013 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 COIST Compare Output Initial State 4 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write CC2_CTRL No Description 0x0A4 read-write 0x00000000 0x0F003F04 OUTINV Output Invert 2 1 read-write CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 CC2_OC No Description 0x0A8 read-write 0x00000000 0x0000FFFF OC Output Compare Value 0 16 read-write CC2_OCB No Description 0x0B0 read-write 0x00000000 0x0000FFFF OCB Output Compare Value Buffer 0 16 read-write CC2_ICF No Description 0x0B4 read-only 0x00000000 0x0000FFFF ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0x0B8 read-only 0x00000000 0x0000FFFF ICOF Input Capture FIFO Overflow 0 16 read-only DTCFG No Description 0x0E0 read-write 0x00000000 0x00000E03 DTEN DTI Enable 0 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTAR DTI Always Run 9 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTTIMECFG No Description 0x0E4 read-write 0x00000000 0x003FFFFF DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write DTFALLT DTI Fall-time 16 6 read-write DTFCFG No Description 0x0E8 read-write 0x00000000 0x1F030000 DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTCTRL No Description 0x0EC read-write 0x00000000 0x00000003 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTOGEN No Description 0x0F0 read-write 0x00000000 0x0000003F DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTFAULT No Description 0x0F4 read-only 0x00000000 0x0000001F DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTDBGF DTI Debugger Fault 2 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTFAULTC No Description 0x0F8 write-only 0x00000000 0x0000001F DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCK No Description 0x0FC write-only 0x00000000 0x0000FFFF DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 USART0_NS 0 USART0_NS Registers 0x5005C000 0x00000000 0x00001000 registers USART0_RX 13 USART0_TX 14 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IPVERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN USART Enable 0 1 read-write CTRL No Description 0x008 read-write 0x00000000 0xF3FFFF7F SYNC USART Synchronous Mode 0 1 read-write DISABLE The USART operates in asynchronous mode 0 ENABLE The USART operates in synchronous mode 1 LOOPBK Loopback Enable 1 1 read-write DISABLE The receiver is connected to and receives data from U(S)n_RX 0 ENABLE The receiver is connected to and receives data from U(S)n_TX 1 CCEN Collision Check Enable 2 1 read-write DISABLE Collision check is disabled 0 ENABLE Collision check is enabled. The receiver must be enabled for the check to be performed 1 MPM Multi-Processor Mode 3 1 read-write DISABLE The 9th bit of incoming frames has no special function 0 ENABLE An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set 1 MPAB Multi-Processor Address-Bit 4 1 read-write OVS Oversampling 5 2 read-write X16 Regular UART mode with 16X oversampling in asynchronous mode 0 X8 Double speed with 8X oversampling in asynchronous mode 1 X6 6X oversampling in asynchronous mode 2 X4 Quadruple speed with 4X oversampling in asynchronous mode 3 CLKPOL Clock Polarity 8 1 read-write IDLELOW The bus clock used in synchronous mode has a low base value 0 IDLEHIGH The bus clock used in synchronous mode has a high base value 1 CLKPHA Clock Edge For Setup/Sample 9 1 read-write SAMPLELEADING Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode 0 SAMPLETRAILING Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode 1 MSBF Most Significant Bit First 10 1 read-write DISABLE Data is sent with the least significant bit first 0 ENABLE Data is sent with the most significant bit first 1 CSMA Action On Chip Select In Main Mode 11 1 read-write NOACTION No action taken 0 GOTOSLAVEMODE Go to secondary mode 1 TXBIL TX Buffer Interrupt Level 12 1 read-write EMPTY TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALFFULL TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full. 1 RXINV Receiver Input Invert 13 1 read-write DISABLE Input is passed directly to the receiver 0 ENABLE Input is inverted before it is passed to the receiver 1 TXINV Transmitter output Invert 14 1 read-write DISABLE Output from the transmitter is passed unchanged to U(S)n_TX 0 ENABLE Output from the transmitter is inverted before it is passed to U(S)n_TX 1 CSINV Chip Select Invert 15 1 read-write DISABLE Chip select is active low 0 ENABLE Chip select is active high 1 AUTOCS Automatic Chip Select 16 1 read-write AUTOTRI Automatic TX Tristate 17 1 read-write DISABLE The output on U(S)n_TX when the transmitter is idle is defined by TXINV 0 ENABLE U(S)n_TX is tristated whenever the transmitter is idle 1 SCMODE SmartCard Mode 18 1 read-write SCRETRANS SmartCard Retransmit 19 1 read-write SKIPPERRF Skip Parity Error Frames 20 1 read-write BIT8DV Bit 8 Default Value 21 1 read-write ERRSDMA Halt DMA On Error 22 1 read-write DISABLE Framing and parity errors have no effect on DMA requests from the USART 0 ENABLE DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set 1 ERRSRX Disable RX On Error 23 1 read-write DISABLE Framing and parity errors have no effect on receiver 0 ENABLE Framing and parity errors disable the receiver 1 ERRSTX Disable TX On Error 24 1 read-write DISABLE Received framing and parity errors have no effect on transmitter 0 ENABLE Received framing and parity errors disable the transmitter 1 SSSEARLY Synchronous Secondary Setup Early 25 1 read-write BYTESWAP Byteswap In Double Accesses 28 1 read-write DISABLE Normal byte order 0 ENABLE Byte order swapped 1 AUTOTX Always Transmit When RX Not Full 29 1 read-write MVDIS Majority Vote Disable 30 1 read-write SMSDELAY Synchronous Main Sample Delay 31 1 read-write FRAME No Description 0x00C read-write 0x00001005 0x0000330F DATABITS Data-Bit Mode 0 4 read-write FOUR Each frame contains 4 data bits 1 FIVE Each frame contains 5 data bits 2 SIX Each frame contains 6 data bits 3 SEVEN Each frame contains 7 data bits 4 EIGHT Each frame contains 8 data bits 5 NINE Each frame contains 9 data bits 6 TEN Each frame contains 10 data bits 7 ELEVEN Each frame contains 11 data bits 8 TWELVE Each frame contains 12 data bits 9 THIRTEEN Each frame contains 13 data bits 10 FOURTEEN Each frame contains 14 data bits 11 FIFTEEN Each frame contains 15 data bits 12 SIXTEEN Each frame contains 16 data bits 13 PARITY Parity-Bit Mode 8 2 read-write NONE Parity bits are not used 0 EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. 2 ODD Odd parity is used. Parity bits are automatically generated and checked by hardware. 3 STOPBITS Stop-Bit Mode 12 2 read-write HALF The transmitter generates a half stop bit. Stop-bits are not verified by receiver 0 ONE One stop bit is generated and verified 1 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies the first stop bit 2 TWO The transmitter generates two stop bits. The receiver checks the first stop-bit only 3 TRIGCTRL No Description 0x010 read-write 0x00000000 0x00001FF0 RXTEN Receive Trigger Enable 4 1 read-write TXTEN Transmit Trigger Enable 5 1 read-write AUTOTXTEN AUTOTX Trigger Enable 6 1 read-write TXARX0EN Enable Transmit Trigger after RX End of 7 1 read-write TXARX1EN Enable Transmit Trigger after RX End of 8 1 read-write TXARX2EN Enable Transmit Trigger after RX End of 9 1 read-write RXATX0EN Enable Receive Trigger after TX end of f 10 1 read-write RXATX1EN Enable Receive Trigger after TX end of f 11 1 read-write RXATX2EN Enable Receive Trigger after TX end of f 12 1 read-write CMD No Description 0x014 write-only 0x00000000 0x00000FFF RXEN Receiver Enable 0 1 write-only RXDIS Receiver Disable 1 1 write-only TXEN Transmitter Enable 2 1 write-only TXDIS Transmitter Disable 3 1 write-only MASTEREN Main Mode Enable 4 1 write-only MASTERDIS Main Mode Disable 5 1 write-only RXBLOCKEN Receiver Block Enable 6 1 write-only RXBLOCKDIS Receiver Block Disable 7 1 write-only TXTRIEN Transmitter Tristate Enable 8 1 write-only TXTRIDIS Transmitter Tristate Disable 9 1 write-only CLEARTX Clear TX 10 1 write-only CLEARRX Clear RX 11 1 write-only STATUS No Description 0x018 read-only 0x00002040 0x00037FFF RXENS Receiver Enable Status 0 1 read-only TXENS Transmitter Enable Status 1 1 read-only MASTER SPI Main Mode 2 1 read-only RXBLOCK Block Incoming Data 3 1 read-only TXTRI Transmitter Tristated 4 1 read-only TXC TX Complete 5 1 read-only TXBL TX Buffer Level 6 1 read-only RXDATAV RX Data Valid 7 1 read-only RXFULL RX FIFO Full 8 1 read-only TXBDRIGHT TX Buffer Expects Double Right Data 9 1 read-only TXBSRIGHT TX Buffer Expects Single Right Data 10 1 read-only RXDATAVRIGHT RX Data Right 11 1 read-only RXFULLRIGHT RX Full of Right Data 12 1 read-only TXIDLE TX Idle 13 1 read-only TIMERRESTARTED The USART Timer restarted itself 14 1 read-only TXBUFCNT TX Buffer Count 16 2 read-only CLKDIV No Description 0x01C read-write 0x00000000 0x807FFFF8 DIV Fractional Clock Divider 3 20 read-write AUTOBAUDEN AUTOBAUD detection enable 31 1 read-write RXDATAX No Description 0x020 read-only 0x00000000 0x0000C1FF RXDATA RX Data 0 9 read-only PERR Data Parity Error 14 1 read-only FERR Data Framing Error 15 1 read-only RXDATA No Description 0x024 read-only 0x00000000 0x000000FF RXDATA RX Data 0 8 read-only RXDOUBLEX No Description 0x028 read-only 0x00000000 0xC1FFC1FF RXDATA0 RX Data 0 0 9 read-only PERR0 Data Parity Error 0 14 1 read-only FERR0 Data Framing Error 0 15 1 read-only RXDATA1 RX Data 1 16 9 read-only PERR1 Data Parity Error 1 30 1 read-only FERR1 Data Framing Error 1 31 1 read-only RXDOUBLE No Description 0x02C read-only 0x00000000 0x0000FFFF RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDATAXP No Description 0x030 read-only 0x00000000 0x0000C1FF RXDATAP RX Data Peek 0 9 read-only PERRP Data Parity Error Peek 14 1 read-only FERRP Data Framing Error Peek 15 1 read-only RXDOUBLEXP No Description 0x034 read-only 0x00000000 0xC1FFC1FF RXDATAP0 RX Data 0 Peek 0 9 read-only PERRP0 Data Parity Error 0 Peek 14 1 read-only FERRP0 Data Framing Error 0 Peek 15 1 read-only RXDATAP1 RX Data 1 Peek 16 9 read-only PERRP1 Data Parity Error 1 Peek 30 1 read-only FERRP1 Data Framing Error 1 Peek 31 1 read-only TXDATAX No Description 0x038 write-only 0x00000000 0x0000F9FF TXDATAX TX Data 0 9 write-only UBRXAT Unblock RX After Transmission 11 1 write-only TXTRIAT Set TXTRI After Transmission 12 1 write-only TXBREAK Transmit Data As Break 13 1 write-only TXDISAT Clear TXEN After Transmission 14 1 write-only RXENAT Enable RX After Transmission 15 1 write-only TXDATA No Description 0x03C write-only 0x00000000 0x000000FF TXDATA TX Data 0 8 write-only TXDOUBLEX No Description 0x040 write-only 0x00000000 0xF9FFF9FF TXDATA0 TX Data 0 9 write-only UBRXAT0 Unblock RX After Transmission 11 1 write-only TXTRIAT0 Set TXTRI After Transmission 12 1 write-only TXBREAK0 Transmit Data As Break 13 1 write-only TXDISAT0 Clear TXEN After Transmission 14 1 write-only RXENAT0 Enable RX After Transmission 15 1 write-only TXDATA1 TX Data 16 9 write-only UBRXAT1 Unblock RX After Transmission 27 1 write-only TXTRIAT1 Set TXTRI After Transmission 28 1 write-only TXBREAK1 Transmit Data As Break 29 1 write-only TXDISAT1 Clear TXEN After Transmission 30 1 write-only RXENAT1 Enable RX After Transmission 31 1 write-only TXDOUBLE No Description 0x044 write-only 0x00000000 0x0000FFFF TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only IF No Description 0x048 read-write 0x00000002 0x0001FFFF TXC TX Complete Interrupt Flag 0 1 read-write TXBL TX Buffer Level Interrupt Flag 1 1 read-write RXDATAV RX Data Valid Interrupt Flag 2 1 read-write RXFULL RX Buffer Full Interrupt Flag 3 1 read-write RXOF RX Overflow Interrupt Flag 4 1 read-write RXUF RX Underflow Interrupt Flag 5 1 read-write TXOF TX Overflow Interrupt Flag 6 1 read-write TXUF TX Underflow Interrupt Flag 7 1 read-write PERR Parity Error Interrupt Flag 8 1 read-write FERR Framing Error Interrupt Flag 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write SSM Chip-Select In Main Mode Interrupt Flag 11 1 read-write CCF Collision Check Fail Interrupt Flag 12 1 read-write TXIDLE TX Idle Interrupt Flag 13 1 read-write TCMP0 Timer comparator 0 Interrupt Flag 14 1 read-write TCMP1 Timer comparator 1 Interrupt Flag 15 1 read-write TCMP2 Timer comparator 2 Interrupt Flag 16 1 read-write IEN No Description 0x04C read-write 0x00000000 0x0001FFFF TXC TX Complete Interrupt Enable 0 1 read-write TXBL TX Buffer Level Interrupt Enable 1 1 read-write RXDATAV RX Data Valid Interrupt Enable 2 1 read-write RXFULL RX Buffer Full Interrupt Enable 3 1 read-write RXOF RX Overflow Interrupt Enable 4 1 read-write RXUF RX Underflow Interrupt Enable 5 1 read-write TXOF TX Overflow Interrupt Enable 6 1 read-write TXUF TX Underflow Interrupt Enable 7 1 read-write PERR Parity Error Interrupt Enable 8 1 read-write FERR Framing Error Interrupt Enable 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write SSM Chip-Select In Main Mode Interrupt Flag 11 1 read-write CCF Collision Check Fail Interrupt Enable 12 1 read-write TXIDLE TX Idle Interrupt Enable 13 1 read-write TCMP0 Timer comparator 0 Interrupt Enable 14 1 read-write TCMP1 Timer comparator 1 Interrupt Enable 15 1 read-write TCMP2 Timer comparator 2 Interrupt Enable 16 1 read-write IRCTRL No Description 0x050 read-write 0x00000000 0x0000008F IREN Enable IrDA Module 0 1 read-write IRPW IrDA TX Pulse Width 1 2 read-write ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 0 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 2 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 3 IRFILT IrDA RX Filter 3 1 read-write DISABLE No filter enabled 0 ENABLE Filter enabled. IrDA pulse must be high for at least 5 consecutive clock cycles to be detected 1 I2SCTRL No Description 0x054 read-write 0x00000000 0x0000071F EN Enable I2S Mode 0 1 read-write MONO Stero or Mono 1 1 read-write JUSTIFY Justification of I2S Data 2 1 read-write LEFT Data is left-justified 0 RIGHT Data is right-justified 1 DMASPLIT Separate DMA Request For Left/Right Data 3 1 read-write DELAY Delay on I2S data 4 1 read-write FORMAT I2S Word Format 8 3 read-write W32D32 32-bit word, 32-bit data 0 W32D24M 32-bit word, 32-bit data with 8 lsb masked 1 W32D24 32-bit word, 24-bit data 2 W32D16 32-bit word, 16-bit data 3 W32D8 32-bit word, 8-bit data 4 W16D16 16-bit word, 16-bit data 5 W16D8 16-bit word, 8-bit data 6 W8D8 8-bit word, 8-bit data 7 TIMING No Description 0x058 read-write 0x00000000 0x77770000 TXDELAY TX frame start delay 16 3 read-write DISABLE Disable - TXDELAY in USARTn_CTRL can be used for legacy 0 ONE Start of transmission is delayed for 1 baud-times 1 TWO Start of transmission is delayed for 2 baud-times 2 THREE Start of transmission is delayed for 3 baud-times 3 SEVEN Start of transmission is delayed for 7 baud-times 4 TCMP0 Start of transmission is delayed for TCMPVAL0 baud-times 5 TCMP1 Start of transmission is delayed for TCMPVAL1 baud-times 6 TCMP2 Start of transmission is delayed for TCMPVAL2 baud-times 7 CSSETUP Chip Select Setup 20 3 read-write ZERO CS is not asserted before start of transmission 0 ONE CS is asserted for 1 baud-times before start of transmission 1 TWO CS is asserted for 2 baud-times before start of transmission 2 THREE CS is asserted for 3 baud-times before start of transmission 3 SEVEN CS is asserted for 7 baud-times before start of transmission 4 TCMP0 CS is asserted before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted before the start of transmission for TCMPVAL2 baud-times 7 ICS Inter-character spacing 24 3 read-write ZERO There is no space between charcters 0 ONE Create a space of 1 baud-times before start of transmission 1 TWO Create a space of 2 baud-times before start of transmission 2 THREE Create a space of 3 baud-times before start of transmission 3 SEVEN Create a space of 7 baud-times before start of transmission 4 TCMP0 Create a space of before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 Create a space of before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 Create a space of before the start of transmission for TCMPVAL2 baud-times 7 CSHOLD Chip Select Hold 28 3 read-write ZERO Disable CS being asserted after the end of transmission 0 ONE CS is asserted for 1 baud-times after the end of transmission 1 TWO CS is asserted for 2 baud-times after the end of transmission 2 THREE CS is asserted for 3 baud-times after the end of transmission 3 SEVEN CS is asserted for 7 baud-times after the end of transmission 4 TCMP0 CS is asserted after the end of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted after the end of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted after the end of transmission for TCMPVAL2 baud-times 7 CTRLX No Description 0x05C read-write 0x00000000 0x8000808F DBGHALT Debug halt 0 1 read-write DISABLE Continue to transmit until TX buffer is empty 0 ENABLE Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock; otherwise, each single step could transmit multiple frames instead of just transmitting one frame. 1 CTSINV CTS Pin Inversion 1 1 read-write DISABLE The USn_CTS pin is low true 0 ENABLE The USn_CTS pin is high true 1 CTSEN CTS Function enabled 2 1 read-write DISABLE Ingore CTS 0 ENABLE Stop transmitting when CTS is negated 1 RTSINV RTS Pin Inversion 3 1 read-write DISABLE The USn_RTS pin is low true 0 ENABLE The USn_RTS pin is high true 1 RXPRSEN PRS RX Enable 7 1 read-write CLKPRSEN PRS CLK Enable 15 1 read-write TIMECMP0 No Description 0x060 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 0. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 0 is disabled 0 TXEOF Comparator 0 and timer are started at TX end of frame 1 TXC Comparator 0 and timer are started at TX Complete 2 RXACT Comparator 0 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 0 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 0 20 3 read-write TCMP0 Comparator 0 is disabled when the counter equals TCMPVAL and triggers a TCMP0 event 0 TXST Comparator 0 is disabled at TX start TX Engine 1 RXACT Comparator 0 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 0 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP0 24 1 read-write DISABLE Disable the timer restarting on TCMP0 0 ENABLE Enable the timer restarting on TCMP0 1 TIMECMP1 No Description 0x064 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 1. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 1 is disabled 0 TXEOF Comparator 1 and timer are started at TX end of frame 1 TXC Comparator 1 and timer are started at TX Complete 2 RXACT Comparator 1 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 1 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 1 20 3 read-write TCMP1 Comparator 1 is disabled when the counter equals TCMPVAL and triggers a TCMP1 event 0 TXST Comparator 1 is disabled at TX start TX Engine 1 RXACT Comparator 1 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 1 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP1 24 1 read-write DISABLE Disable the timer restarting on TCMP1 0 ENABLE Enable the timer restarting on TCMP1 1 TIMECMP2 No Description 0x068 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 2. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 2 is disabled 0 TXEOF Comparator 2 and timer are started at TX end of frame 1 TXC Comparator 2 and timer are started at TX Complete 2 RXACT Comparator 2 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 2 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 2 20 3 read-write TCMP2 Comparator 2 is disabled when the counter equals TCMPVAL and triggers a TCMP2 event 0 TXST Comparator 2 is disabled at TX start TX Engine 1 RXACT Comparator 2 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 2 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP2 24 1 read-write DISABLE Disable the timer restarting on TCMP2 0 ENABLE Enable the timer restarting on TCMP2 1 USART1_NS 0 USART1_NS Registers 0x50060000 0x00000000 0x00001000 registers USART1_RX 15 USART1_TX 16 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IPVERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN USART Enable 0 1 read-write CTRL No Description 0x008 read-write 0x00000000 0xF3FFFF7F SYNC USART Synchronous Mode 0 1 read-write DISABLE The USART operates in asynchronous mode 0 ENABLE The USART operates in synchronous mode 1 LOOPBK Loopback Enable 1 1 read-write DISABLE The receiver is connected to and receives data from U(S)n_RX 0 ENABLE The receiver is connected to and receives data from U(S)n_TX 1 CCEN Collision Check Enable 2 1 read-write DISABLE Collision check is disabled 0 ENABLE Collision check is enabled. The receiver must be enabled for the check to be performed 1 MPM Multi-Processor Mode 3 1 read-write DISABLE The 9th bit of incoming frames has no special function 0 ENABLE An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set 1 MPAB Multi-Processor Address-Bit 4 1 read-write OVS Oversampling 5 2 read-write X16 Regular UART mode with 16X oversampling in asynchronous mode 0 X8 Double speed with 8X oversampling in asynchronous mode 1 X6 6X oversampling in asynchronous mode 2 X4 Quadruple speed with 4X oversampling in asynchronous mode 3 CLKPOL Clock Polarity 8 1 read-write IDLELOW The bus clock used in synchronous mode has a low base value 0 IDLEHIGH The bus clock used in synchronous mode has a high base value 1 CLKPHA Clock Edge For Setup/Sample 9 1 read-write SAMPLELEADING Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode 0 SAMPLETRAILING Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode 1 MSBF Most Significant Bit First 10 1 read-write DISABLE Data is sent with the least significant bit first 0 ENABLE Data is sent with the most significant bit first 1 CSMA Action On Chip Select In Main Mode 11 1 read-write NOACTION No action taken 0 GOTOSLAVEMODE Go to secondary mode 1 TXBIL TX Buffer Interrupt Level 12 1 read-write EMPTY TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALFFULL TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full. 1 RXINV Receiver Input Invert 13 1 read-write DISABLE Input is passed directly to the receiver 0 ENABLE Input is inverted before it is passed to the receiver 1 TXINV Transmitter output Invert 14 1 read-write DISABLE Output from the transmitter is passed unchanged to U(S)n_TX 0 ENABLE Output from the transmitter is inverted before it is passed to U(S)n_TX 1 CSINV Chip Select Invert 15 1 read-write DISABLE Chip select is active low 0 ENABLE Chip select is active high 1 AUTOCS Automatic Chip Select 16 1 read-write AUTOTRI Automatic TX Tristate 17 1 read-write DISABLE The output on U(S)n_TX when the transmitter is idle is defined by TXINV 0 ENABLE U(S)n_TX is tristated whenever the transmitter is idle 1 SCMODE SmartCard Mode 18 1 read-write SCRETRANS SmartCard Retransmit 19 1 read-write SKIPPERRF Skip Parity Error Frames 20 1 read-write BIT8DV Bit 8 Default Value 21 1 read-write ERRSDMA Halt DMA On Error 22 1 read-write DISABLE Framing and parity errors have no effect on DMA requests from the USART 0 ENABLE DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set 1 ERRSRX Disable RX On Error 23 1 read-write DISABLE Framing and parity errors have no effect on receiver 0 ENABLE Framing and parity errors disable the receiver 1 ERRSTX Disable TX On Error 24 1 read-write DISABLE Received framing and parity errors have no effect on transmitter 0 ENABLE Received framing and parity errors disable the transmitter 1 SSSEARLY Synchronous Secondary Setup Early 25 1 read-write BYTESWAP Byteswap In Double Accesses 28 1 read-write DISABLE Normal byte order 0 ENABLE Byte order swapped 1 AUTOTX Always Transmit When RX Not Full 29 1 read-write MVDIS Majority Vote Disable 30 1 read-write SMSDELAY Synchronous Main Sample Delay 31 1 read-write FRAME No Description 0x00C read-write 0x00001005 0x0000330F DATABITS Data-Bit Mode 0 4 read-write FOUR Each frame contains 4 data bits 1 FIVE Each frame contains 5 data bits 2 SIX Each frame contains 6 data bits 3 SEVEN Each frame contains 7 data bits 4 EIGHT Each frame contains 8 data bits 5 NINE Each frame contains 9 data bits 6 TEN Each frame contains 10 data bits 7 ELEVEN Each frame contains 11 data bits 8 TWELVE Each frame contains 12 data bits 9 THIRTEEN Each frame contains 13 data bits 10 FOURTEEN Each frame contains 14 data bits 11 FIFTEEN Each frame contains 15 data bits 12 SIXTEEN Each frame contains 16 data bits 13 PARITY Parity-Bit Mode 8 2 read-write NONE Parity bits are not used 0 EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. 2 ODD Odd parity is used. Parity bits are automatically generated and checked by hardware. 3 STOPBITS Stop-Bit Mode 12 2 read-write HALF The transmitter generates a half stop bit. Stop-bits are not verified by receiver 0 ONE One stop bit is generated and verified 1 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies the first stop bit 2 TWO The transmitter generates two stop bits. The receiver checks the first stop-bit only 3 TRIGCTRL No Description 0x010 read-write 0x00000000 0x00001FF0 RXTEN Receive Trigger Enable 4 1 read-write TXTEN Transmit Trigger Enable 5 1 read-write AUTOTXTEN AUTOTX Trigger Enable 6 1 read-write TXARX0EN Enable Transmit Trigger after RX End of 7 1 read-write TXARX1EN Enable Transmit Trigger after RX End of 8 1 read-write TXARX2EN Enable Transmit Trigger after RX End of 9 1 read-write RXATX0EN Enable Receive Trigger after TX end of f 10 1 read-write RXATX1EN Enable Receive Trigger after TX end of f 11 1 read-write RXATX2EN Enable Receive Trigger after TX end of f 12 1 read-write CMD No Description 0x014 write-only 0x00000000 0x00000FFF RXEN Receiver Enable 0 1 write-only RXDIS Receiver Disable 1 1 write-only TXEN Transmitter Enable 2 1 write-only TXDIS Transmitter Disable 3 1 write-only MASTEREN Main Mode Enable 4 1 write-only MASTERDIS Main Mode Disable 5 1 write-only RXBLOCKEN Receiver Block Enable 6 1 write-only RXBLOCKDIS Receiver Block Disable 7 1 write-only TXTRIEN Transmitter Tristate Enable 8 1 write-only TXTRIDIS Transmitter Tristate Disable 9 1 write-only CLEARTX Clear TX 10 1 write-only CLEARRX Clear RX 11 1 write-only STATUS No Description 0x018 read-only 0x00002040 0x00037FFF RXENS Receiver Enable Status 0 1 read-only TXENS Transmitter Enable Status 1 1 read-only MASTER SPI Main Mode 2 1 read-only RXBLOCK Block Incoming Data 3 1 read-only TXTRI Transmitter Tristated 4 1 read-only TXC TX Complete 5 1 read-only TXBL TX Buffer Level 6 1 read-only RXDATAV RX Data Valid 7 1 read-only RXFULL RX FIFO Full 8 1 read-only TXBDRIGHT TX Buffer Expects Double Right Data 9 1 read-only TXBSRIGHT TX Buffer Expects Single Right Data 10 1 read-only RXDATAVRIGHT RX Data Right 11 1 read-only RXFULLRIGHT RX Full of Right Data 12 1 read-only TXIDLE TX Idle 13 1 read-only TIMERRESTARTED The USART Timer restarted itself 14 1 read-only TXBUFCNT TX Buffer Count 16 2 read-only CLKDIV No Description 0x01C read-write 0x00000000 0x807FFFF8 DIV Fractional Clock Divider 3 20 read-write AUTOBAUDEN AUTOBAUD detection enable 31 1 read-write RXDATAX No Description 0x020 read-only 0x00000000 0x0000C1FF RXDATA RX Data 0 9 read-only PERR Data Parity Error 14 1 read-only FERR Data Framing Error 15 1 read-only RXDATA No Description 0x024 read-only 0x00000000 0x000000FF RXDATA RX Data 0 8 read-only RXDOUBLEX No Description 0x028 read-only 0x00000000 0xC1FFC1FF RXDATA0 RX Data 0 0 9 read-only PERR0 Data Parity Error 0 14 1 read-only FERR0 Data Framing Error 0 15 1 read-only RXDATA1 RX Data 1 16 9 read-only PERR1 Data Parity Error 1 30 1 read-only FERR1 Data Framing Error 1 31 1 read-only RXDOUBLE No Description 0x02C read-only 0x00000000 0x0000FFFF RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDATAXP No Description 0x030 read-only 0x00000000 0x0000C1FF RXDATAP RX Data Peek 0 9 read-only PERRP Data Parity Error Peek 14 1 read-only FERRP Data Framing Error Peek 15 1 read-only RXDOUBLEXP No Description 0x034 read-only 0x00000000 0xC1FFC1FF RXDATAP0 RX Data 0 Peek 0 9 read-only PERRP0 Data Parity Error 0 Peek 14 1 read-only FERRP0 Data Framing Error 0 Peek 15 1 read-only RXDATAP1 RX Data 1 Peek 16 9 read-only PERRP1 Data Parity Error 1 Peek 30 1 read-only FERRP1 Data Framing Error 1 Peek 31 1 read-only TXDATAX No Description 0x038 write-only 0x00000000 0x0000F9FF TXDATAX TX Data 0 9 write-only UBRXAT Unblock RX After Transmission 11 1 write-only TXTRIAT Set TXTRI After Transmission 12 1 write-only TXBREAK Transmit Data As Break 13 1 write-only TXDISAT Clear TXEN After Transmission 14 1 write-only RXENAT Enable RX After Transmission 15 1 write-only TXDATA No Description 0x03C write-only 0x00000000 0x000000FF TXDATA TX Data 0 8 write-only TXDOUBLEX No Description 0x040 write-only 0x00000000 0xF9FFF9FF TXDATA0 TX Data 0 9 write-only UBRXAT0 Unblock RX After Transmission 11 1 write-only TXTRIAT0 Set TXTRI After Transmission 12 1 write-only TXBREAK0 Transmit Data As Break 13 1 write-only TXDISAT0 Clear TXEN After Transmission 14 1 write-only RXENAT0 Enable RX After Transmission 15 1 write-only TXDATA1 TX Data 16 9 write-only UBRXAT1 Unblock RX After Transmission 27 1 write-only TXTRIAT1 Set TXTRI After Transmission 28 1 write-only TXBREAK1 Transmit Data As Break 29 1 write-only TXDISAT1 Clear TXEN After Transmission 30 1 write-only RXENAT1 Enable RX After Transmission 31 1 write-only TXDOUBLE No Description 0x044 write-only 0x00000000 0x0000FFFF TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only IF No Description 0x048 read-write 0x00000002 0x0001FFFF TXC TX Complete Interrupt Flag 0 1 read-write TXBL TX Buffer Level Interrupt Flag 1 1 read-write RXDATAV RX Data Valid Interrupt Flag 2 1 read-write RXFULL RX Buffer Full Interrupt Flag 3 1 read-write RXOF RX Overflow Interrupt Flag 4 1 read-write RXUF RX Underflow Interrupt Flag 5 1 read-write TXOF TX Overflow Interrupt Flag 6 1 read-write TXUF TX Underflow Interrupt Flag 7 1 read-write PERR Parity Error Interrupt Flag 8 1 read-write FERR Framing Error Interrupt Flag 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write SSM Chip-Select In Main Mode Interrupt Flag 11 1 read-write CCF Collision Check Fail Interrupt Flag 12 1 read-write TXIDLE TX Idle Interrupt Flag 13 1 read-write TCMP0 Timer comparator 0 Interrupt Flag 14 1 read-write TCMP1 Timer comparator 1 Interrupt Flag 15 1 read-write TCMP2 Timer comparator 2 Interrupt Flag 16 1 read-write IEN No Description 0x04C read-write 0x00000000 0x0001FFFF TXC TX Complete Interrupt Enable 0 1 read-write TXBL TX Buffer Level Interrupt Enable 1 1 read-write RXDATAV RX Data Valid Interrupt Enable 2 1 read-write RXFULL RX Buffer Full Interrupt Enable 3 1 read-write RXOF RX Overflow Interrupt Enable 4 1 read-write RXUF RX Underflow Interrupt Enable 5 1 read-write TXOF TX Overflow Interrupt Enable 6 1 read-write TXUF TX Underflow Interrupt Enable 7 1 read-write PERR Parity Error Interrupt Enable 8 1 read-write FERR Framing Error Interrupt Enable 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write SSM Chip-Select In Main Mode Interrupt Flag 11 1 read-write CCF Collision Check Fail Interrupt Enable 12 1 read-write TXIDLE TX Idle Interrupt Enable 13 1 read-write TCMP0 Timer comparator 0 Interrupt Enable 14 1 read-write TCMP1 Timer comparator 1 Interrupt Enable 15 1 read-write TCMP2 Timer comparator 2 Interrupt Enable 16 1 read-write IRCTRL No Description 0x050 read-write 0x00000000 0x0000008F IREN Enable IrDA Module 0 1 read-write IRPW IrDA TX Pulse Width 1 2 read-write ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 0 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 2 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 3 IRFILT IrDA RX Filter 3 1 read-write DISABLE No filter enabled 0 ENABLE Filter enabled. IrDA pulse must be high for at least 5 consecutive clock cycles to be detected 1 I2SCTRL No Description 0x054 read-write 0x00000000 0x0000071F EN Enable I2S Mode 0 1 read-write MONO Stero or Mono 1 1 read-write JUSTIFY Justification of I2S Data 2 1 read-write LEFT Data is left-justified 0 RIGHT Data is right-justified 1 DMASPLIT Separate DMA Request For Left/Right Data 3 1 read-write DELAY Delay on I2S data 4 1 read-write FORMAT I2S Word Format 8 3 read-write W32D32 32-bit word, 32-bit data 0 W32D24M 32-bit word, 32-bit data with 8 lsb masked 1 W32D24 32-bit word, 24-bit data 2 W32D16 32-bit word, 16-bit data 3 W32D8 32-bit word, 8-bit data 4 W16D16 16-bit word, 16-bit data 5 W16D8 16-bit word, 8-bit data 6 W8D8 8-bit word, 8-bit data 7 TIMING No Description 0x058 read-write 0x00000000 0x77770000 TXDELAY TX frame start delay 16 3 read-write DISABLE Disable - TXDELAY in USARTn_CTRL can be used for legacy 0 ONE Start of transmission is delayed for 1 baud-times 1 TWO Start of transmission is delayed for 2 baud-times 2 THREE Start of transmission is delayed for 3 baud-times 3 SEVEN Start of transmission is delayed for 7 baud-times 4 TCMP0 Start of transmission is delayed for TCMPVAL0 baud-times 5 TCMP1 Start of transmission is delayed for TCMPVAL1 baud-times 6 TCMP2 Start of transmission is delayed for TCMPVAL2 baud-times 7 CSSETUP Chip Select Setup 20 3 read-write ZERO CS is not asserted before start of transmission 0 ONE CS is asserted for 1 baud-times before start of transmission 1 TWO CS is asserted for 2 baud-times before start of transmission 2 THREE CS is asserted for 3 baud-times before start of transmission 3 SEVEN CS is asserted for 7 baud-times before start of transmission 4 TCMP0 CS is asserted before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted before the start of transmission for TCMPVAL2 baud-times 7 ICS Inter-character spacing 24 3 read-write ZERO There is no space between charcters 0 ONE Create a space of 1 baud-times before start of transmission 1 TWO Create a space of 2 baud-times before start of transmission 2 THREE Create a space of 3 baud-times before start of transmission 3 SEVEN Create a space of 7 baud-times before start of transmission 4 TCMP0 Create a space of before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 Create a space of before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 Create a space of before the start of transmission for TCMPVAL2 baud-times 7 CSHOLD Chip Select Hold 28 3 read-write ZERO Disable CS being asserted after the end of transmission 0 ONE CS is asserted for 1 baud-times after the end of transmission 1 TWO CS is asserted for 2 baud-times after the end of transmission 2 THREE CS is asserted for 3 baud-times after the end of transmission 3 SEVEN CS is asserted for 7 baud-times after the end of transmission 4 TCMP0 CS is asserted after the end of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted after the end of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted after the end of transmission for TCMPVAL2 baud-times 7 CTRLX No Description 0x05C read-write 0x00000000 0x8000808F DBGHALT Debug halt 0 1 read-write DISABLE Continue to transmit until TX buffer is empty 0 ENABLE Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock; otherwise, each single step could transmit multiple frames instead of just transmitting one frame. 1 CTSINV CTS Pin Inversion 1 1 read-write DISABLE The USn_CTS pin is low true 0 ENABLE The USn_CTS pin is high true 1 CTSEN CTS Function enabled 2 1 read-write DISABLE Ingore CTS 0 ENABLE Stop transmitting when CTS is negated 1 RTSINV RTS Pin Inversion 3 1 read-write DISABLE The USn_RTS pin is low true 0 ENABLE The USn_RTS pin is high true 1 RXPRSEN PRS RX Enable 7 1 read-write CLKPRSEN PRS CLK Enable 15 1 read-write TIMECMP0 No Description 0x060 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 0. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 0 is disabled 0 TXEOF Comparator 0 and timer are started at TX end of frame 1 TXC Comparator 0 and timer are started at TX Complete 2 RXACT Comparator 0 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 0 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 0 20 3 read-write TCMP0 Comparator 0 is disabled when the counter equals TCMPVAL and triggers a TCMP0 event 0 TXST Comparator 0 is disabled at TX start TX Engine 1 RXACT Comparator 0 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 0 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP0 24 1 read-write DISABLE Disable the timer restarting on TCMP0 0 ENABLE Enable the timer restarting on TCMP0 1 TIMECMP1 No Description 0x064 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 1. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 1 is disabled 0 TXEOF Comparator 1 and timer are started at TX end of frame 1 TXC Comparator 1 and timer are started at TX Complete 2 RXACT Comparator 1 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 1 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 1 20 3 read-write TCMP1 Comparator 1 is disabled when the counter equals TCMPVAL and triggers a TCMP1 event 0 TXST Comparator 1 is disabled at TX start TX Engine 1 RXACT Comparator 1 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 1 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP1 24 1 read-write DISABLE Disable the timer restarting on TCMP1 0 ENABLE Enable the timer restarting on TCMP1 1 TIMECMP2 No Description 0x068 read-write 0x00000000 0x017700FF TCMPVAL Timer comparator 2. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 2 is disabled 0 TXEOF Comparator 2 and timer are started at TX end of frame 1 TXC Comparator 2 and timer are started at TX Complete 2 RXACT Comparator 2 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 2 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 2 20 3 read-write TCMP2 Comparator 2 is disabled when the counter equals TCMPVAL and triggers a TCMP2 event 0 TXST Comparator 2 is disabled at TX start TX Engine 1 RXACT Comparator 2 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 2 is disabled on RX going Inactive 3 RESTARTEN Restart Timer on TCMP2 24 1 read-write DISABLE Disable the timer restarting on TCMP2 0 ENABLE Enable the timer restarting on TCMP2 1 BURTC_NS 0 BURTC_NS Registers 0x50064000 0x00000000 0x00001000 registers BURTC 18 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN BURTC Enable 0 1 read-write CFG No Description 0x008 read-write 0x00000000 0x000000F3 DEBUGRUN Debug Mode Run Enable 0 1 read-write DISABLE BURTC is frozen in debug mode 0 ENABLE BURTC is running in debug mode 1 COMPTOP Compare Channel is Top Value 1 1 read-write DISABLE The top value of the BURTC is 4294967295 (0xFFFFFFFF) 0 ENABLE The top value of the BURTC is given by COMP 1 CNTPRESC Counter prescaler value. 4 4 read-write DIV1 CLK_CNT = (BURTC LF CLK)/1 0 DIV2 CLK_CNT = (BURTC LF CLK)/2 1 DIV4 CLK_CNT = (BURTC LF CLK)/4 2 DIV8 CLK_CNT = (BURTC LF CLK)/8 3 DIV16 CLK_CNT = (BURTC LF CLK)/16 4 DIV32 CLK_CNT = (BURTC LF CLK)/32 5 DIV64 CLK_CNT = (BURTC LF CLK)/64 6 DIV128 CLK_CNT = (BURTC LF CLK)/128 7 DIV256 CLK_CNT = (BURTC LF CLK)/256 8 DIV512 CLK_CNT = (BURTC LF CLK)/512 9 DIV1024 CLK_CNT = (BURTC LF CLK)/1024 10 DIV2048 CLK_CNT = (BURTC LF CLK)/2048 11 DIV4096 CLK_CNT = (BURTC LF CLK)/4096 12 DIV8192 CLK_CNT = (BURTC LF CLK)/8192 13 DIV16384 CLK_CNT = (BURTC LF CLK)/16384 14 DIV32768 CLK_CNT = (BURTC LF CLK)/32768 15 CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start BURTC counter 0 1 write-only STOP Stop BURTC counter 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x00000003 RUNNING BURTC running status 0 1 read-only LOCK Configuration Lock Status 1 1 read-only UNLOCKED All BURTC lockable registers are unlocked. 0 LOCKED All BURTC lockable registers are locked. 1 IF No Description 0x014 read-write 0x00000000 0x00000003 OF Overflow Interrupt Flag 0 1 read-write COMP Compare Match Interrupt Flag 1 1 read-write IEN No Description 0x018 read-write 0x00000000 0x00000003 OF Overflow Interrupt Flag 0 1 read-write COMP Compare Match Interrupt Flag 1 1 read-write PRECNT No Description 0x01C read-write 0x00000000 0x00007FFF PRECNT Pre-Counter Value 0 15 read-write CNT No Description 0x020 read-write 0x00000000 0xFFFFFFFF CNT Counter Value 0 32 read-write EM4WUEN No Description 0x024 read-write 0x00000000 0x00000003 OFEM4WUEN Overflow EM4 Wakeup Enable 0 1 read-write COMPEM4WUEN Compare Match EM4 Wakeup Enable 1 1 read-write SYNCBUSY No Description 0x028 read-only 0x00000000 0x0000003F START Sync busy for START 0 1 read-only STOP Sync busy for STOP 1 1 read-only PRECNT Sync busy for PRECNT 2 1 read-only CNT Sync busy for CNT 3 1 read-only COMP Sync busy for COMP 4 1 read-only EN Sync busy for EN 5 1 read-only LOCK No Description 0x02C write-only 0x0000AEE8 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write to unlock all BURTC lockable registers 44776 COMP No Description 0x030 read-write 0x00000000 0xFFFFFFFF COMP Compare Value 0 32 read-write I2C1_NS 0 I2C1_NS Registers 0x50068000 0x00000000 0x00001000 registers I2C1 28 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN module enable 0 1 read-write DISABLE Disable Peripheral Clock 0 ENABLE Enable Peripheral Clock 1 CTRL No Description 0x008 read-write 0x00000000 0x0037B3FF CORERST Soft Reset the internal state registers 0 1 read-write DISABLE No change to internal state registers 0 ENABLE Reset the internal state registers 1 SLAVE Addressable as Follower 1 1 read-write DISABLE All addresses will be responded to with a NACK 0 ENABLE Addresses matching the programmed follower address or the general call address (if enabled) require a response from software. Other addresses are automatically responded to with a NACK. 1 AUTOACK Automatic Acknowledge 2 1 read-write DISABLE Software must give one ACK command for each ACK transmitted on the I2C bus. 0 ENABLE Addresses that are not automatically NACK'ed, and all data is automatically acknowledged. 1 AUTOSE Automatic STOP when Empty 3 1 read-write DISABLE A stop must be sent manually when no more data is to be transmitted. 0 ENABLE The leader automatically sends a STOP when no more data is available for transmission. 1 AUTOSN Automatic STOP on NACK 4 1 read-write DISABLE Stop is not automatically sent if a NACK is received from a follower. 0 ENABLE The leader automatically sends a STOP if a NACK is received from a follower. 1 ARBDIS Arbitration Disable 5 1 read-write DISABLE When a device loses arbitration, the ARBIF interrupt flag is set and the bus is released. 0 ENABLE When a device loses arbitration, the ARBIF interrupt flag is set, but communication proceeds. 1 GCAMEN General Call Address Match Enable 6 1 read-write DISABLE General call address will be NACK'ed if it is not included by the follower address and address mask. 0 ENABLE When a general call address is received, a software response is required 1 TXBIL TX Buffer Interrupt Level 7 1 read-write EMPTY TXBL status and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALF_FULL TXBL status and the TXBL interrupt flag are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full 1 CLHR Clock Low High Ratio 8 2 read-write STANDARD Nlow=4 and Nhigh=4, and the Nlow:Nhigh ratio is 4:4 0 ASYMMETRIC Nlow=6 and Nhigh=3, and the Nlow:Nhigh ratio is 6:3 1 FAST Nlow=11 and Nhigh=6, and the Nlow:Nhigh ratio is 11:6 2 BITO Bus Idle Timeout 12 2 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 GIBITO Go Idle on Bus Idle Timeout 15 1 read-write DISABLE A bus idle timeout has no effect on the bus state. 0 ENABLE A bus idle timeout tells the I2C module that the bus is idle, allowing new transfers to be initiated. 1 CLTO Clock Low Timeout 16 3 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 I2C320PCC Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout. 4 I2C1024PCC Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout. 5 SCLMONEN SCL Monitor Enable 20 1 read-write DISABLE Disable SCL monitor 0 ENABLE Enable SCL monitor 1 SDAMONEN SDA Monitor Enable 21 1 read-write DISABLE Disable SDA Monitor 0 ENABLE Enable SDA Monitor 1 CMD No Description 0x00C write-only 0x00000000 0x000000FF START Send start condition 0 1 write-only STOP Send stop condition 1 1 write-only ACK Send ACK 2 1 write-only NACK Send NACK 3 1 write-only CONT Continue transmission 4 1 write-only ABORT Abort transmission 5 1 write-only CLEARTX Clear TX 6 1 write-only CLEARPC Clear Pending Commands 7 1 write-only STATE No Description 0x010 read-only 0x00000001 0x000000FF BUSY Bus Busy 0 1 read-only MASTER Leader 1 1 read-only TRANSMITTER Transmitter 2 1 read-only NACKED Nack Received 3 1 read-only BUSHOLD Bus Held 4 1 read-only STATE Transmission State 5 3 read-only IDLE No transmission is being performed. 0 WAIT Waiting for idle. Will send a start condition as soon as the bus is idle. 1 START Start transmit phase 2 ADDR Address transmit or receive phase 3 ADDRACK Address ack/nack transmit or receive phase 4 DATA Data transmit or receive phase 5 DATAACK Data ack/nack transmit or receive phase 6 STATUS No Description 0x014 read-only 0x00000080 0x00000FFF PSTART Pending START 0 1 read-only PSTOP Pending STOP 1 1 read-only PACK Pending ACK 2 1 read-only PNACK Pending NACK 3 1 read-only PCONT Pending continue 4 1 read-only PABORT Pending abort 5 1 read-only TXC TX Complete 6 1 read-only TXBL TX Buffer Level 7 1 read-only RXDATAV RX Data Valid 8 1 read-only RXFULL RX FIFO Full 9 1 read-only TXBUFCNT TX Buffer Count 10 2 read-only CLKDIV No Description 0x018 read-write 0x00000000 0x000001FF DIV Clock Divider 0 9 read-write SADDR No Description 0x01C read-write 0x00000000 0x000000FE ADDR Follower address 1 7 read-write SADDRMASK No Description 0x020 read-write 0x00000000 0x000000FE SADDRMASK Follower Address Mask 1 7 read-write RXDATA No Description 0x024 read-only 0x00000000 0x000000FF RXDATA RX Data 0 8 read-only RXDOUBLE No Description 0x028 read-only 0x00000000 0x0000FFFF RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDATAP No Description 0x02C read-only 0x00000000 0x000000FF RXDATAP RX Data Peek 0 8 read-only RXDOUBLEP No Description 0x030 read-only 0x00000000 0x0000FFFF RXDATAP0 RX Data 0 Peek 0 8 read-only RXDATAP1 RX Data 1 Peek 8 8 read-only TXDATA No Description 0x034 write-only 0x00000000 0x000000FF TXDATA TX Data 0 8 write-only TXDOUBLE No Description 0x038 write-only 0x00000000 0x0000FFFF TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only IF No Description 0x03C read-write 0x00000000 0x001FFFFF START START condition Interrupt Flag 0 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write ADDR Address Interrupt Flag 2 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write ACK Acknowledge Received Interrupt Flag 6 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write MSTOP Leader STOP Condition Interrupt Flag 8 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write SSTOP Follower STOP condition Interrupt Flag 16 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write IEN No Description 0x040 read-write 0x00000000 0x001FFFFF START START condition Interrupt Flag 0 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write ADDR Address Interrupt Flag 2 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write ACK Acknowledge Received Interrupt Flag 6 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write MSTOP Leader STOP Condition Interrupt Flag 8 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write SSTOP Follower STOP condition Interrupt Flag 16 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write SYSCFG_NS_CFGNS 1 SYSCFG_NS_CFGNS Registers 0x50078000 0x00000000 0x00001000 registers SYSCFG 20 SW0 52 SW1 53 SW2 54 SW3 55 CFGNSTCALIB Configure to define the system tick for the M33. 0x01C read-write 0x01004A37 0x03FFFFFF TENMS Ten Milliseconds 0 24 read-write SKEW Skew 24 1 read-write NOREF No Reference 25 1 read-write REF Reference clock is implemented 0 NOREF Reference clock is not implemented 1 ROOTNSDATA0 Generic data space for user to pass to root, e.g., address of struct in mem 0x600 read-write 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write ROOTNSDATA1 Generic data space for user to pass to root, e.g., address of struct in mem 0x604 read-write 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write SYSCFG_NS 1 SYSCFG_NS Registers 0x5007C000 0x00000000 0x00001000 registers SYSCFG 20 SW0 52 SW1 53 SW2 54 SW3 55 IF Read to get system status. 0x000 read-write 0x00000000 0x3303000F SW0 Software Interrupt 0 0 1 read-write SW1 Software Interrupt 1 1 1 read-write SW2 Software Interrupt 2 2 1 read-write SW3 Software Interrupt 3 3 1 read-write RAMERR1B RAM 1-Bit Error Interrupt Flag 16 1 read-write RAMERR2B RAM 2-Bit Error Interrupt Flag 17 1 read-write IEN Write to enable interrupts. 0x004 read-write 0x00000000 0x3303000F SW0 Software interrupt 0 0 1 read-write SW1 Software interrupt 1 1 1 read-write SW2 Software interrupt 2 2 1 read-write SW3 Software interrupt 3 3 1 read-write RAMERR1B RAM 1-bit Error Interrupt Enable 16 1 read-write RAMERR2B RAM 2-bit Error Interrupt Enable 17 1 read-write CHIPREVHW Read to get the hard-wired chip revision. 0x010 read-write 0x00000C01 0xFF0FFFFF MAJOR Hardwired Chip Revision Major value 0 6 read-write FAMILY Hardwired Chip Family value 6 6 read-write MINOR Hardwired Chip Revision Minor value 12 8 read-write CHIPREV Read to get the chip revision programmed by feature configuration. 0x014 read-write 0x00000000 0x000FFFFF MAJOR Chip Revision Major value 0 6 read-write FAMILY Chip Family value 6 6 read-write MINOR Chip Revision Minor value 12 8 read-write CFGSYSTIC Configure the source of the system tick for the M33. 0x020 read-write 0x00000000 0x00000001 SYSTICEXTCLKEN SysTick External Clock Enable 0 1 read-write CTRL Configure to provide general RAM configuration. 0x200 read-write 0x00000021 0x00000021 ADDRFAULTEN Invalid Address Bus Fault Response Enable 0 1 read-write RAMECCERRFAULTEN Two bit ECC Error Bus Fault Response Enable 5 1 read-write DMEM0RETNCTRL Configure to provide general RAM retention configuration. 0x208 read-write 0x00000000 0x00000003 RAMRETNCTRL DMEM0 blockset retention control 0 2 read-write ALLON None of the RAM blocks powered down 0 BLK0 Power down RAM block 0 1 BLK1 Power down RAM block 1 2 DMEM0ECCADDR Read to get status of the DMEM0 ECC error address. 0x210 read-only 0x00000000 0xFFFFFFFF DMEM0ECCADDR DMEM0 RAM ECC Error Address 0 32 read-only DMEM0ECCCTRL Configure to set RAM ECC control. 0x214 read-write 0x00000000 0x00000003 RAMECCEN RAM ECC Enable 0 1 read-write RAMECCEWEN RAM ECC Error Writeback Enable 1 1 read-write ROOTDATA0 Data in this register is passed to the trusted root firmware upon reset. 0x600 read-write 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write ROOTDATA1 Data in this register is passed to the trusted root firmware upon reset. 0x604 read-write 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write ROOTLOCKSTATUS This register returns the status of the SE managed locks. 0x608 read-only 0x011F0107 0x011F0117 BUSLOCK Bus Lock 0 1 read-only REGLOCK Register Lock 1 1 read-only MFRLOCK Manufacture Lock 2 1 read-only ROOTMODELOCK Root Mode Lock 4 1 read-only ROOTDBGLOCK Root Debug Lock 8 1 read-only USERDBGLOCK User Invasive Debug Lock 16 1 read-only USERNIDLOCK User Non-invasive Debug Lock 17 1 read-only USERSPIDLOCK User Secure Invasive Debug Lock 18 1 read-only USERSPNIDLOCK User Secure Non-invasive Debug Lock 19 1 read-only USERDBGAPLOCK User Debug Access Port Lock 20 1 read-only BURAM_NS 0 BURAM_NS Registers 0x50080000 0x00000000 0x00001000 registers RET0_REG No Description 0x000 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET1_REG No Description 0x004 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET2_REG No Description 0x008 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET3_REG No Description 0x00C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET4_REG No Description 0x010 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET5_REG No Description 0x014 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET6_REG No Description 0x018 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET7_REG No Description 0x01C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET8_REG No Description 0x020 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET9_REG No Description 0x024 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET10_REG No Description 0x028 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET11_REG No Description 0x02C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET12_REG No Description 0x030 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET13_REG No Description 0x034 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET14_REG No Description 0x038 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET15_REG No Description 0x03C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET16_REG No Description 0x040 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET17_REG No Description 0x044 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET18_REG No Description 0x048 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET19_REG No Description 0x04C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET20_REG No Description 0x050 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET21_REG No Description 0x054 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET22_REG No Description 0x058 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET23_REG No Description 0x05C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET24_REG No Description 0x060 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET25_REG No Description 0x064 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET26_REG No Description 0x068 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET27_REG No Description 0x06C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET28_REG No Description 0x070 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET29_REG No Description 0x074 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET30_REG No Description 0x078 read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write RET31_REG No Description 0x07C read-write 0x00000000 0xFFFFFFFF RETREG Latch based Retention register 0 32 read-write GPCRC_NS 0 GPCRC_NS Registers 0x50088000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN CRC Enable 0 1 read-write DISABLE Disable CRC function. Reordering functions are still available. Only BITREVERSE and BYTEREVERSE bits are configurable in this mode. 0 ENABLE Writes to INPUTDATA registers will result in CRC operations. 1 CTRL No Description 0x008 read-write 0x00000000 0x00002710 POLYSEL Polynomial Select 4 1 read-write CRC32 CRC-32 (0x04C11DB7) polynomial selected 0 CRC16 16-bit CRC programmable polynomial selected 1 BYTEMODE Byte Mode Enable 8 1 read-write BITREVERSE Byte-level Bit Reverse Enable 9 1 read-write NORMAL No reverse 0 REVERSED Reverse bit order in each byte 1 BYTEREVERSE Byte Reverse Mode 10 1 read-write NORMAL No reverse: B3, B2, B1, B0 0 REVERSED Reverse byte order. For 32-bit: B0, B1, B2, B3; For 16-bit: 0, 0, B0, B1 1 AUTOINIT Auto Init Enable 13 1 read-write CMD No Description 0x00C write-only 0x00000000 0x80000001 INIT Initialization Enable 0 1 write-only INIT No Description 0x010 read-write 0x00000000 0xFFFFFFFF INIT CRC Initialization Value 0 32 read-write POLY No Description 0x014 read-write 0x00000000 0x0000FFFF POLY CRC Polynomial Value 0 16 read-write INPUTDATA No Description 0x018 write-only 0x00000000 0xFFFFFFFF INPUTDATA Input Data for 32-bit 0 32 write-only INPUTDATAHWORD No Description 0x01C write-only 0x00000000 0x0000FFFF INPUTDATAHWORD Input Data for 16-bit 0 16 write-only INPUTDATABYTE No Description 0x020 write-only 0x00000000 0x000000FF INPUTDATABYTE Input Data for 8-bit 0 8 write-only DATA No Description 0x024 read-only 0x00000000 0xFFFFFFFF DATA CRC Data Register 0 32 read-only DATAREV No Description 0x028 read-only 0x00000000 0xFFFFFFFF DATAREV Data Reverse Value 0 32 read-only DATABYTEREV No Description 0x02C read-only 0x00000000 0xFFFFFFFF DATABYTEREV Data Byte Reverse Value 0 32 read-only DCDC_NS 0 DCDC_NS Registers 0x50094000 0x00000000 0x00001000 registers IPVERSION IPVERSION 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IPVERSION 0 32 read-only EN Enable 0x004 read-write 0x00000000 0x00000001 EN Enable 0 1 read-write DISABLE Disable 0 ENABLE Enable 1 CTRL Control 0x008 read-write 0x00000044 0x00000077 MODE DCDC/Bypass Mode Control 0 1 read-write BYPASS DCDC is OFF, bypass switch is enabled 0 DCDCREGULATION Request DCDC regulation, bypass switch disabled 1 DCMONLYEN DCDC DCM Only Enable 2 1 read-write DUALMODE Support higher load current at lower battery voltage by working in CCM mode 0 DCMONLYEN DCM only mode for normal operation, this is the default setting 1 IPKTMAXCTRL Peak Current Timeout Control 4 3 read-write OFF Ton_max disabled 0 TMAX_0P35us 0.35us 1 TMAX_0P63us 0.63us 2 TMAX_0P91us 0.91us 3 TMAX_1P19us 1.19us 4 TMAX_1P47us 1.47us 5 TMAX_1P75us 1.75us 6 TMAX_2P03us 2.03us 7 EM01CTRL0 EM01 Configurations 0x010 read-write 0x00000109 0x0000030F IPKVAL EM01 Peak Current Setting 0 4 read-write Load36mA Ipeak = 90mA, IL = 36mA 3 Load40mA Ipeak = 100mA, IL = 40mA 4 Load44mA Ipeak = 110mA, IL = 44mA 5 Load48mA Ipeak = 120mA, IL = 48mA 6 Load52mA Ipeak = 130mA, IL = 52mA 7 Load56mA Ipeak = 140mA, IL = 56mA 8 Load60mA Ipeak = 150mA, IL = 60mA 9 DRVSPEED EM01 Drive Speed Setting 8 2 read-write BEST_EMI Lowest Efficiency, Lowest EMI.. Small decrease in efficiency from default setting 0 DEFAULT_SETTING Default Efficiency, Acceptable EMI level 1 INTERMEDIATE Small increase in efficiency from the default setting 2 BEST_EFFICIENCY Highest Efficiency, Highest EMI.. Small increase in efficiency from INTERMEDIATE setting 3 EM23CTRL0 EM23 Configurations 0x014 read-write 0x00000103 0x0000030F IPKVAL EM23 Peak Current Setting 0 4 read-write LOAD5MA Ipeak = 90mA, IL = 5 mA 3 LOAD10MA Ipeak = 150mA, IL = 10 mA 9 DRVSPEED EM23 Drive Speed Setting 8 2 read-write BEST_EMI Lowest Efficiency, Lowest EMI.. Small decrease in efficiency from default setting 0 DEFAULT_SETTING Default Efficiency, Acceptable EMI level 1 INTERMEDIATE Small increase in efficiency from the default setting 2 BEST_EFFICIENCY Highest Efficiency, Highest EMI.. Small increase in efficiency from INTERMEDIATE setting 3 IF Interrupt Flags 0x024 read-write 0x00000000 0x000000FF BYPSW Bypass Switch Enabled 0 1 read-write WARM DCDC Warmup Time Done 1 1 read-write RUNNING DCDC Running 2 1 read-write VREGINLOW VREGVDD below threshold 3 1 read-write VREGINHIGH VREGVDD above threshold 4 1 read-write REGULATION DCDC in regulation 5 1 read-write TMAX Ton_max Timeout Reached 6 1 read-write EM4ERR EM4 Entry Request Error 7 1 read-write IEN Interrupt Enable 0x028 read-write 0x00000000 0x000000FF BYPSW Bypass Switch Enabled Interrupt Enable 0 1 read-write WARM DCDC Warmup Time Done Interrupt Enable 1 1 read-write RUNNING DCDC Running Interrupt Enable 2 1 read-write VREGINLOW VREGVDD below threshold Interrupt Enable 3 1 read-write VREGINHIGH VREGVDD above threshold Interrupt Enable 4 1 read-write REGULATION DCDC in Regulation Interrupt Enable 5 1 read-write TMAX Ton_max Timeout Interrupt Enable 6 1 read-write EM4ERR EM4 Entry Req Interrupt Enable 7 1 read-write STATUS DCDC Status Register 0x02C read-only 0x00000000 0x0000001F BYPSW Bypass Switch is currently enabled 0 1 read-only WARM DCDC Warmup Done 1 1 read-only RUNNING DCDC is running 2 1 read-only VREGIN VREGVDD comparator status 3 1 read-only BYPCMPOUT Bypass Comparator Output 4 1 read-only LOCK No Description 0x040 write-only 0x00000000 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCKKEY Value to write to unlock 43981 LOCKSTATUS No Description 0x044 read-only 0x00000000 0x00000001 LOCK Lock Status 0 1 read-only UNLOCKED Unlocked State 0 LOCKED LOCKED STATE 1 PDM_NS 0 PDM_NS Registers 0x50098000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP VERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN PDM enable 0 1 read-write DISABLE Disable module 0 ENABLE Enable module 1 CTRL No Description 0x008 read-write 0x00000000 0x000FFF1F GAIN Selects Gain factor of DCF 0 5 read-write DSR Down sampling rate of Decimation filter 8 12 read-write CMD No Description 0x00C write-only 0x00000000 0x00010111 START Start DCF 0 1 write-only STOP Stop DCF 4 1 write-only CLEAR Clear DCF 8 1 write-only FIFOFL FIFO Flush 16 1 write-only STATUS No Description 0x010 read-only 0x00000020 0x00000731 ACT PDM is active 0 1 read-only FULL FIFO FULL Status 4 1 read-only EMPTY FIFO EMPTY Status 5 1 read-only FIFOCNT FIFO CNT 8 3 read-only CFG0 No Description 0x014 read-write 0x00000000 0x03013713 FORDER Filter order 0 2 read-write SECOND Second order filter. 0 THIRD Third order filter. 1 FOURTH Fourth order filter. 2 FIFTH Fifth order filter. 3 NUMCH Number of Channels 4 1 read-write ONE One channel. 0 TWO Two channels. 1 DATAFORMAT Filter output format 8 3 read-write RIGHT16 Right aligned 16-bit, left bits are sign extended. 0 DOUBLE16 Pack two 16-bit samples into one 32-bit word. 1 RIGHT24 Right aligned 24bit, left bits are sign extended. 2 FULL32BIT 32 bit data. 3 LEFT16 Left aligned 16-bit, right bits are zeros. 4 LEFT24 Left aligned 24-bit, right bits are zeros. 5 RAW32BIT RAW 32 bit data from Integrator. 6 FIFODVL Data Valid level in FIFO 12 2 read-write ONE Atleast one word. 0 TWO Two words. 1 THREE Three words. 2 FOUR Four words. 3 STEREOMODECH01 Stereo mode CH01 16 1 read-write DISABLE No Stereo mode. 0 CH01ENABLE CH0 and CH1 in Stereo mode. 1 CH0CLKPOL CH0 CLK Polarity 24 1 read-write NORMAL Input data clocked on rising clock edge. 0 INVERT Input data clocked on falling clock edge. 1 CH1CLKPOL CH1 CLK Polarity 25 1 read-write NORMAL Input data clocked on rising clock edge. 0 INVERT Input data clocked on falling clock edge. 1 CFG1 No Description 0x018 read-write 0x00000000 0x030003FF PRESC Prescalar Setting for PDM sample 0 10 read-write DLYMUXSEL Data delay buffer mux selection 24 2 read-write RXDATA No Description 0x020 read-only 0x00000000 0xFFFFFFFF RXDATA PDM received data 0 32 read-only IF No Description 0x040 read-write 0x00000000 0x0000000F DV Data Valid Interrupt Flag 0 1 read-write DVL Data Valid Level Interrupt Flag 1 1 read-write OF FIFO Overflow Interrupt Flag 2 1 read-write UF FIFO Undeflow Interrupt Flag 3 1 read-write IEN No Description 0x044 read-write 0x00000000 0x0000000F DV Data Valid Interrupt Enable 0 1 read-write DVL Data Valid Level Interrupt Enable 1 1 read-write OF FIFO Overflow Interrupt Enable 2 1 read-write UF FIFO Undeflow Interrupt Enable 3 1 read-write SYNCBUSY No Description 0x060 read-only 0x00000000 0x00000009 SYNCBUSY sync busy 0 1 read-only FIFOFLBUSY FIFO Flush Sync busy 3 1 read-only SMU_NS 1 SMU_NS Registers 0x54008000 0x00000000 0x00001000 registers SMU_SECURE 3 SMU_PRIVILEGED 4 IPVERSION The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION. 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP Version 0 32 read-only STATUS Read to get SMU status. 0x004 read-only 0x00000000 0x00000003 SMULOCK SMU Lock 0 1 read-only UNLOCKED SMULOCK is Unlocked 0 LOCKED SMULOCK is Locked 1 SMUPRGERR SMU Programming Error 1 1 read-only LOCK Access to Lock/unlock the SMU Configuration. 0x008 write-only 0x00000000 0x00FFFFFF SMULOCKKEY SMU Lock/Key 0 24 write-only UNLOCK Unlocks Registers 11325013 IF Read to get status of SMU interrupts. 0x00C read-write 0x00000000 0x00030005 PPUPRIV PPU Privilege Interrupt Flag 0 1 read-write PPUINST PPU Instruction Interrupt Flag 2 1 read-write PPUSEC PPU Security Interrupt Flag 16 1 read-write BMPUSEC BMPU Security Interrupt Flag 17 1 read-write IEN Write to Enable/Disable SMU interrupts. 0x010 read-write 0x00000000 0x00030005 PPUPRIV PPU Privilege Interrupt Enable 0 1 read-write PPUINST PPU Instruction Interrupt Enable 2 1 read-write PPUSEC PPU Security Interrupt Enable 16 1 read-write BMPUSEC BMPU Security Interrupt Enable 17 1 read-write M33CTRL Holds the M33 control settings. 0x020 read-write 0x00000000 0x0000001F LOCKSVTAIRCR LOCKSVTAIRCR control of M33 CPU 0 1 read-write LOCKNSVTOR LOCKNSVTOR control of M33 CPU 1 1 read-write LOCKSMPU LOCKSMPU control of M33 CPU 2 1 read-write LOCKNSMPU LOCKNSMPU control of M33 CPU 3 1 read-write LOCKSAU LOCKSAU control of M33 CPU 4 1 read-write PPUPATD0 Set peripheral bits to 1 to mark as privileged access only. 0x040 read-write 0xFFFFFFFF 0xFFFFFFFF EMU EMU Privileged Access 1 1 read-write CMU CMU Privileged Access 2 1 read-write HFXO0 HFXO0 Privileged Access 3 1 read-write HFRCO0 HFRCO0 Privileged Access 4 1 read-write FSRCO FSRCO Privileged Access 5 1 read-write DPLL0 DPLL0 Privileged Access 6 1 read-write LFXO LFXO Privileged Access 7 1 read-write LFRCO LFRCO Privileged Access 8 1 read-write ULFRCO ULFRCO Privileged Access 9 1 read-write MSC MSC Privileged Access 10 1 read-write ICACHE0 ICACHE0 Privileged Access 11 1 read-write PRS PRS Privileged Access 12 1 read-write GPIO GPIO Privileged Access 13 1 read-write LDMA LDMA Privileged Access 14 1 read-write LDMAXBAR LDMAXBAR Privileged Access 15 1 read-write TIMER0 TIMER0 Privileged Access 16 1 read-write TIMER1 TIMER1 Privileged Access 17 1 read-write TIMER2 TIMER2 Privileged Access 18 1 read-write TIMER3 TIMER3 Privileged Access 19 1 read-write TIMER4 TIMER4 Privileged Access 20 1 read-write USART0 USART0 Privileged Access 21 1 read-write USART1 USART1 Privileged Access 22 1 read-write BURTC BURTC Privileged Access 23 1 read-write I2C1 I2C1 Privileged Access 24 1 read-write CHIPTESTCTRL CHIPTESTCTRL Privileged Access 25 1 read-write SYSCFGCFGNS SYSCFGCFGNS Privileged Access 26 1 read-write SYSCFG SYSCFG Privileged Access 27 1 read-write BURAM BURAM Privileged Access 28 1 read-write GPCRC GPCRC Privileged Access 30 1 read-write DCI DCI Privileged Access 31 1 read-write PPUPATD1 Set peripheral bits to 1 to mark as privileged access only. 0x044 read-write 0x0000FFFF 0x0000FFFF DCDC DCDC Privileged Access 1 1 read-write PDM PDM Privileged Access 2 1 read-write SMU SMU Privileged Access 5 1 read-write SMUCFGNS SMUCFGNS Privileged Access 6 1 read-write RTCC RTCC Privileged Access 7 1 read-write LETIMER0 LETIMER0 Privileged Access 8 1 read-write IADC0 IADC0 Privileged Access 9 1 read-write I2C0 I2C0 Privileged Access 10 1 read-write WDOG0 WDOG0 Privileged Access 11 1 read-write AMUXCP0 AMUXCP0 Privileged Access 12 1 read-write EUART0 EUART0 Privileged Access 13 1 read-write CRYPTOACC CRYPTOACC Privileged Access 14 1 read-write PPUSATD0 Set peripheral bits to 1 to mark as secure access only. 0x060 read-write 0xFFFFFFFF 0xFFFFFFFF EMU EMU Secure Access 1 1 read-write CMU CMU Secure Access 2 1 read-write HFXO0 HFXO0 Secure Access 3 1 read-write HFRCO0 HFRCO0 Secure Access 4 1 read-write FSRCO FSRCO Secure Access 5 1 read-write DPLL0 DPLL0 Secure Access 6 1 read-write LFXO LFXO Secure Access 7 1 read-write LFRCO LFRCO Secure Access 8 1 read-write ULFRCO ULFRCO Secure Access 9 1 read-write MSC MSC Secure Access 10 1 read-write ICACHE0 ICACHE0 Secure Access 11 1 read-write PRS PRS Secure Access 12 1 read-write GPIO GPIO Secure Access 13 1 read-write LDMA LDMA Secure Access 14 1 read-write LDMAXBAR LDMAXBAR Secure Access 15 1 read-write TIMER0 TIMER0 Secure Access 16 1 read-write TIMER1 TIMER1 Secure Access 17 1 read-write TIMER2 TIMER2 Secure Access 18 1 read-write TIMER3 TIMER3 Secure Access 19 1 read-write TIMER4 TIMER4 Secure Access 20 1 read-write USART0 USART0 Secure Access 21 1 read-write USART1 USART1 Secure Access 22 1 read-write BURTC BURTC Secure Access 23 1 read-write I2C1 I2C1 Secure Access 24 1 read-write CHIPTESTCTRL CHIPTESTCTRL Secure Access 25 1 read-write SYSCFGCFGNS SYSCFGCFGNS Secure Access 26 1 read-write SYSCFG SYSCFG Secure Access 27 1 read-write BURAM BURAM Secure Access 28 1 read-write GPCRC GPCRC Secure Access 30 1 read-write DCI DCI Secure Access 31 1 read-write PPUSATD1 Set peripheral bits to 1 to mark as secure access only. 0x064 read-write 0x0000FFFF 0x0000FFFF DCDC DCDC Secure Access 1 1 read-write PDM PDM Secure Access 2 1 read-write SMU SMU Secure Access 5 1 read-write SMUCFGNS SMUCFGNS Secure Access 6 1 read-write RTCC RTCC Secure Access 7 1 read-write LETIMER0 LETIMER0 Secure Access 8 1 read-write IADC0 IADC0 Secure Access 9 1 read-write I2C0 I2C0 Secure Access 10 1 read-write WDOG0 WDOG0 Secure Access 11 1 read-write AMUXCP0 AMUXCP0 Secure Access 12 1 read-write EUART0 EUART0 Secure Access 13 1 read-write CRYPTOACC CRYPTOACC Secure Access 14 1 read-write PPUFS Read to get fault status of SMU. 0x140 read-only 0x00000000 0x000000FF PPUFSPERIPHID Peripheral ID 0 8 read-only BMPUPATD0 Set master bits to 1 to mark as a privileged master. 0x150 read-write 0x0000001F 0x0000001F CRYPTOACC CRYPTOACC DMA privileged mode 1 1 read-write LDMA MCU LDMA privileged mode 4 1 read-write BMPUSATD0 Set master bits to 1 to mark as a secure master. 0x170 read-write 0x0000001F 0x0000001F CRYPTOACC CRYPTOACC DMA secure mode 1 1 read-write LDMA MCU LDMA secure mode 4 1 read-write BMPUFS Read to get status about the master that triggered a fault. 0x250 read-only 0x00000000 0x000000FF BMPUFSMASTERID Master ID 0 8 read-only BMPUFSADDR Read to get the access address that triggered a fault. 0x254 read-only 0x00000000 0xFFFFFFFF BMPUFSADDR Fault Address 0 32 read-only ESAURTYPES0 Write to specify if a region is secure or non-secure. 0x260 read-write 0x00000000 0x00001000 ESAUR3NS Region 3 Non-Secure Type 12 1 read-write ESAURTYPES1 Write to specify if a region is secure or non-secure. 0x264 read-write 0x00000000 0x00001000 ESAUR11NS Region 11 Non-Secure Type 12 1 read-write ESAUMRB01 Specify the boundary between regions 0 and 1. 0x270 read-write 0x02000000 0x0FFFF000 ESAUMRB01 Moveable Region Boundary 0-1 12 16 read-write ESAUMRB12 Specify the boundary between regions 1 and 2. 0x274 read-write 0x04000000 0x0FFFF000 ESAUMRB12 Moveable Region Boundary 1-2 12 16 read-write ESAUMRB45 Specify the boundary between regions 4 and 5. 0x280 read-write 0x02000000 0x0FFFF000 ESAUMRB45 Moveable Region Boundary 4-5 12 16 read-write ESAUMRB56 Specify the boundary between regions 5 and 6. 0x284 read-write 0x04000000 0x0FFFF000 ESAUMRB56 Moveable Region Boundary 5-6 12 16 read-write SMU_NS_CFGNS 1 SMU_NS_CFGNS Registers 0x5400C000 0x00000000 0x00001000 registers SMU_SECURE 3 SMU_PRIVILEGED 4 NSSTATUS Register for status flags. 0x004 read-only 0x00000000 0x00000001 SMUNSLOCK SMUNS Lock Status 0 1 read-only UNLOCKED SMUNSLOCK Unlocked 0 LOCKED SMUNSLOCK Locked 1 NSLOCK Register used to lock/unlock access to the register file. 0x008 write-only 0x00000000 0x00FFFFFF SMUNSLOCKKEY SMU Non-Secure Lock/Key 0 24 write-only UNLOCK Unlocks Registers 11325013 NSIF Register for interrupt status flags. 0x00C read-write 0x00000000 0x00000005 PPUNSPRIVIF PPUNS Privilege Interrupt Flag 0 1 read-write PPUNSINSTIF PPUNS Instruction Interrupt Flag 2 1 read-write NSIEN Register used for enabling/disabling interrupts. 0x010 read-write 0x00000000 0x00000005 PPUNSPRIVIEN PPUNS Privilege Interrupt Enable 0 1 read-write PPUNSINSTIEN PPUNS Instruction Interrupt Enable 2 1 read-write PPUNSPATD0 Set peripheral bits to 1 to mark as privileged access only. 0x040 read-write 0x00000000 0xFFFFFFFF EMU EMU Privileged Access 1 1 read-write CMU CMU Privileged Access 2 1 read-write HFXO0 HFXO0 Privileged Access 3 1 read-write HFRCO0 HFRCO0 Privileged Access 4 1 read-write FSRCO FSRCO Privileged Access 5 1 read-write DPLL0 DPLL0 Privileged Access 6 1 read-write LFXO LFXO Privileged Access 7 1 read-write LFRCO LFRCO Privileged Access 8 1 read-write ULFRCO ULFRCO Privileged Access 9 1 read-write MSC MSC Privileged Access 10 1 read-write ICACHE0 ICACHE0 Privileged Access 11 1 read-write PRS PRS Privileged Access 12 1 read-write GPIO GPIO Privileged Access 13 1 read-write LDMA LDMA Privileged Access 14 1 read-write LDMAXBAR LDMAXBAR Privileged Access 15 1 read-write TIMER0 TIMER0 Privileged Access 16 1 read-write TIMER1 TIMER1 Privileged Access 17 1 read-write TIMER2 TIMER2 Privileged Access 18 1 read-write TIMER3 TIMER3 Privileged Access 19 1 read-write TIMER4 TIMER4 Privileged Access 20 1 read-write USART0 USART0 Privileged Access 21 1 read-write USART1 USART1 Privileged Access 22 1 read-write BURTC BURTC Privileged Access 23 1 read-write I2C1 I2C1 Privileged Access 24 1 read-write CHIPTESTCTRL CHIPTESTCTRL Privileged Access 25 1 read-write SYSCFGCFGNS SYSCFGCFGNS Privileged Access 26 1 read-write SYSCFG SYSCFG Privileged Access 27 1 read-write BURAM BURAM Privileged Access 28 1 read-write GPCRC GPCRC Privileged Access 30 1 read-write DCI DCI Privileged Access 31 1 read-write PPUNSPATD1 Set peripheral bits to 1 to mark as privileged access only. 0x044 read-write 0x00000000 0x0000FFFF DCDC DCDC Privileged Access 1 1 read-write PDM PDM Privileged Access 2 1 read-write SMU SMU Privileged Access 5 1 read-write SMUCFGNS SMUCFGNS Privileged Access 6 1 read-write RTCC RTCC Privileged Access 7 1 read-write LETIMER0 LETIMER0 Privileged Access 8 1 read-write IADC0 IADC0 Privileged Access 9 1 read-write I2C0 I2C0 Privileged Access 10 1 read-write WDOG0 WDOG0 Privileged Access 11 1 read-write AMUXCP0 AMUXCP0 Privileged Access 12 1 read-write EUART0 EUART0 Privileged Access 13 1 read-write CRYPTOACC CRYPTOACC Privileged Access 14 1 read-write PPUNSFS Read this register to query the fault status. 0x140 read-only 0x00000000 0x000000FF PPUFSPERIPHID Peripheral ID 0 8 read-only BMPUNSPATD0 Write to set BMPU priveledged attributes. 0x150 read-write 0x00000000 0x0000001F CRYPTOACC CRYPTOACC DMA privileged mode 1 1 read-write LDMA MCU LDMA privileged mode 4 1 read-write RTCC_NS 1 RTCC_NS Registers 0x58000000 0x00000000 0x00001000 registers RTCC 12 IPVERSION No Description 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP VERSION 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN RTCC Enable 0 1 read-write CFG No Description 0x008 read-write 0x00000000 0x000000FF DEBUGRUN Debug Mode Run Enable 0 1 read-write X0 RTCC is frozen in debug mode 0 X1 RTCC is running in debug mode 1 PRECNTCCV0TOP Pre-counter CCV0 top value enable. 1 1 read-write CNTCCV1TOP CCV1 top value enable 2 1 read-write CNTTICK Counter prescaler mode. 3 1 read-write PRESC CNT register ticks according to configuration in CNTPRESC. 0 CCV0MATCH CNT register ticks when PRECNT matches RTCC_CC0_OC[14:0] 1 CNTPRESC Counter prescaler value. 4 4 read-write DIV1 CLK_CNT = (RTCC LF CLK)/1 0 DIV2 CLK_CNT = (RTCC LF CLK)/2 1 DIV4 CLK_CNT = (RTCC LF CLK)/4 2 DIV8 CLK_CNT = (RTCC LF CLK)/8 3 DIV16 CLK_CNT = (RTCC LF CLK)/16 4 DIV32 CLK_CNT = (RTCC LF CLK)/32 5 DIV64 CLK_CNT = (RTCC LF CLK)/64 6 DIV128 CLK_CNT = (RTCC LF CLK)/128 7 DIV256 CLK_CNT = (RTCC LF CLK)/256 8 DIV512 CLK_CNT = (RTCC LF CLK)/512 9 DIV1024 CLK_CNT = (RTCC LF CLK)/1024 10 DIV2048 CLK_CNT = (RTCC LF CLK)/2048 11 DIV4096 CLK_CNT = (RTCC LF CLK)/4096 12 DIV8192 CLK_CNT = (RTCC LF CLK)/8192 13 DIV16384 CLK_CNT = (RTCC LF CLK)/16384 14 DIV32768 CLK_CNT = (RTCC LF CLK)/32768 15 CMD No Description 0x00C write-only 0x00000000 0x00000003 START Start RTCC main counter 0 1 write-only STOP Stop RTCC main counter 1 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x00000003 RUNNING RTCC running status 0 1 read-only RTCCLOCKSTATUS Lock Status 1 1 read-only UNLOCKED RTCC registers are unlocked 0 LOCKED RTCC registers are locked 1 IF No Description 0x014 read-write 0x00000000 0x000003FF OF Overflow Interrupt Flag 0 1 read-write CNTTICK Main counter tick 1 1 read-write CC0 CC Channel n Interrupt Flag 4 1 read-write CC1 CC Channel n Interrupt Flag 6 1 read-write CC2 CC Channel n Interrupt Flag 8 1 read-write IEN No Description 0x018 read-write 0x00000000 0x000003FF OF OF Interrupt Enable 0 1 read-write CNTTICK CNTTICK Interrupt Enable 1 1 read-write CC0 CC Channel n Interrupt Enable 4 1 read-write CC1 CC Channel n Interrupt Enable 6 1 read-write CC2 CC Channel n Interrupt Enable 8 1 read-write PRECNT No Description 0x01C read-write 0x00000000 0x00007FFF PRECNT Pre-Counter Value 0 15 read-write CNT No Description 0x020 read-write 0x00000000 0xFFFFFFFF CNT Counter Value 0 32 read-write COMBCNT No Description 0x024 read-only 0x00000000 0xFFFFFFFF PRECNT Pre-Counter Value 0 15 read-only CNTLSB Counter Value 15 17 read-only SYNCBUSY No Description 0x028 read-only 0x00000000 0x0000000F START Sync busy for START 0 1 read-only STOP Sync busy for STOP 1 1 read-only PRECNT Sync busy for PRECNT 2 1 read-only CNT Sync busy for CNT 3 1 read-only LOCK No Description 0x02C write-only 0x00000000 0x0000FFFF LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write to unlock RTCC lockable registers 44776 CC0_CTRL No Description 0x030 read-write 0x00000000 0x000000FF MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 CC0_OCVALUE No Description 0x034 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC0_ICVALUE No Description 0x038 read-only 0x00000000 0xFFFFFFFF IC Input Capture Value 0 32 read-only CC1_CTRL No Description 0x03C read-write 0x00000000 0x000000FF MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 CC1_OCVALUE No Description 0x040 read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC1_ICVALUE No Description 0x044 read-only 0x00000000 0xFFFFFFFF IC Input Capture Value 0 32 read-only CC2_CTRL No Description 0x048 read-write 0x00000000 0x000000FF MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 CC2_OCVALUE No Description 0x04C read-write 0x00000000 0xFFFFFFFF OC Output Compare Value 0 32 read-write CC2_ICVALUE No Description 0x050 read-only 0x00000000 0xFFFFFFFF IC Input Capture Value 0 32 read-only LETIMER0_NS 0 LETIMER0_NS Registers 0x5A000000 0x00000000 0x00001000 registers LETIMER0 19 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN module en 0 1 read-write CTRL No Description 0x008 read-write 0x00000000 0x000F13FF REPMODE Repeat Mode 0 2 read-write FREE When started, the LETIMER counts down until it is stopped by software 0 ONESHOT The counter counts REP0 times. When REP0 reaches zero, the counter stops 1 BUFFERED The counter counts REP0 times. If REP1 has been written, it is loaded into REP0 when REP0 reaches zero, otherwise the counter stops 2 DOUBLE Both REP0 and REP1 are decremented when the LETIMER wraps around. The LETIMER counts until both REP0 and REP1 are zero 3 UFOA0 Underflow Output Action 0 2 2 read-write NONE LETIMERn_OUT0 is held at its idle value as defined by OPOL0 0 TOGGLE LETIMERn_OUT0 is toggled on CNT underflow 1 PULSE LETIMERn_OUT0 is held active for one LETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL0 2 PWM LETIMERn_OUT0 is set idle on CNT underflow, and active on compare match with COMP1 3 UFOA1 Underflow Output Action 1 4 2 read-write NONE LETIMERn_OUT1 is held at its idle value as defined by OPOL1 0 TOGGLE LETIMERn_OUT1 is toggled on CNT underflow 1 PULSE LETIMERn_OUT1 is held active for one LETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL1 2 PWM LETIMERn_OUT1 is set idle on CNT underflow, and active on compare match with COMP1 3 OPOL0 Output 0 Polarity 6 1 read-write OPOL1 Output 1 Polarity 7 1 read-write BUFTOP Buffered Top 8 1 read-write DISABLE TOP is only written by software 0 ENABLE TOP is set to TOPBUFF value when REP0 reaches 0 1 CNTTOPEN Compare Value 0 Is Top Value 9 1 read-write DISABLE The top value of the LETIMER is 16777215 (0xFFFFFF) 0 ENABLE The top value of the LETIMER is given by TOP 1 DEBUGRUN Debug Mode Run Enable 12 1 read-write DISABLE LETIMER is frozen in debug mode 0 ENABLE LETIMER is running in debug mode 1 CNTPRESC Counter prescaler value 16 4 read-write DIV1 CLK_CNT = (LETIMER LF CLK)/1 0 DIV2 CLK_CNT = (LETIMER LF CLK)/2 1 DIV4 CLK_CNT = (LETIMER LF CLK)/4 2 DIV8 CLK_CNT = (LETIMER LF CLK)/8 3 DIV16 CLK_CNT = (LETIMER LF CLK)/16 4 DIV32 CLK_CNT = (LETIMER LF CLK)/32 5 DIV64 CLK_CNT = (LETIMER LF CLK)/64 6 DIV128 CLK_CNT = (LETIMER LF CLK)/128 7 DIV256 CLK_CNT = (LETIMER LF CLK)/256 8 CMD No Description 0x00C write-only 0x00000000 0x0000001F START Start LETIMER 0 1 write-only STOP Stop LETIMER 1 1 write-only CLEAR Clear LETIMER 2 1 write-only CTO0 Clear Toggle Output 0 3 1 write-only CTO1 Clear Toggle Output 1 4 1 write-only STATUS No Description 0x010 read-only 0x00000000 0x00000001 RUNNING LETIMER Running 0 1 read-only CNT No Description 0x018 read-write 0x00000000 0x00FFFFFF CNT Counter Value 0 24 read-write COMP0 No Description 0x01C read-write 0x00000000 0x00FFFFFF COMP0 Compare Value 0 0 24 read-write COMP1 No Description 0x020 read-write 0x00000000 0x00FFFFFF COMP1 Compare Value 1 0 24 read-write TOP No Description 0x024 read-write 0x00000000 0x00FFFFFF TOP Counter TOP Value 0 24 read-write TOPBUFF No Description 0x028 read-write 0x00000000 0x00FFFFFF TOPBUFF Buffered Counter TOP Value 0 24 read-write REP0 No Description 0x02C read-write 0x00000000 0x000000FF REP0 Repeat Counter 0 0 8 read-write REP1 No Description 0x030 read-write 0x00000000 0x000000FF REP1 Repeat Counter 1 0 8 read-write IF No Description 0x034 read-write 0x00000000 0x0000001F COMP0 Compare Match 0 Interrupt Flag 0 1 read-write COMP1 Compare Match 1 Interrupt Flag 1 1 read-write UF Underflow Interrupt Flag 2 1 read-write REP0 Repeat Counter 0 Interrupt Flag 3 1 read-write REP1 Repeat Counter 1 Interrupt Flag 4 1 read-write IEN No Description 0x038 read-write 0x00000000 0x0000001F COMP0 Compare Match 0 Interrupt Enable 0 1 read-write COMP1 Compare Match 1 Interrupt Enable 1 1 read-write UF Underflow Interrupt Enable 2 1 read-write REP0 Repeat Counter 0 Interrupt Enable 3 1 read-write REP1 Repeat Counter 1 Interrupt Enable 4 1 read-write SYNCBUSY No Description 0x040 read-only 0x00000000 0x000003FD CNT Sync busy for CNT 0 1 read-only TOP Sync busy for TOP 2 1 read-only REP0 Sync busy for REP0 3 1 read-only REP1 Sync busy for REP1 4 1 read-only START Sync busy for START 5 1 read-only STOP Sync busy for STOP 6 1 read-only CLEAR Sync busy for CLEAR 7 1 read-only CTO0 Sync busy for CTO0 8 1 read-only CTO1 Sync busy for CTO1 9 1 read-only PRSMODE No Description 0x050 read-write 0x00000000 0x0CCC0000 PRSSTARTMODE PRS Start Mode 18 2 read-write NONE PRS cannot start the LETIMER 0 RISING Rising edge of selected PRS input can start the LETIMER 1 FALLING Falling edge of selected PRS input can start the LETIMER 2 BOTH Both the rising or falling edge of the selected PRS input can start the LETIMER 3 PRSSTOPMODE PRS Stop Mode 22 2 read-write NONE PRS cannot stop the LETIMER 0 RISING Rising edge of selected PRS input can stop the LETIMER 1 FALLING Falling edge of selected PRS input can stop the LETIMER 2 BOTH Both the rising or falling edge of the selected PRS input can stop the LETIMER 3 PRSCLEARMODE PRS Clear Mode 26 2 read-write NONE PRS cannot clear the LETIMER 0 RISING Rising edge of selected PRS input can clear the LETIMER 1 FALLING Falling edge of selected PRS input can clear the LETIMER 2 BOTH Both the rising or falling edge of the selected PRS input can clear the LETIMER 3 IADC0_NS 1 IADC0_NS Registers 0x5A004000 0x00000000 0x00001000 registers IADC 48 IPVERSION IPVERSION 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only EN Enable 0x004 read-write 0x00000000 0x00000001 EN Enable IADC Module 0 1 read-write DISABLE Disable 0 ENABLE Enable 1 CTRL Control 0x008 read-write 0x00000000 0x707F003F EM23WUCONVERT EM23 Wakeup on Conversion 0 1 read-write WUDVL When using suspend mode, conversions performed in EM2 or EM3 should not wake up the DMA until the FIFO's DVL setting is reached. This saves more power for large OSR settings or infrequent sampling. 0 WUCONVERT When using suspend mode, conversions performed in EM2 or EM3 will wake up the DMA and keep it awake until the conversions are done, regardless of the DVL setting. This mode burns more power, but it is useful when the conversion rate is faster than the time for the DMA to cycle through wake up and going back to sleep as it converts more than 4 scan table entries. Without using the wake up on conversion mode, the FIFO may overflow while the DMA is going in and out of sleep. 1 ADCCLKSUSPEND0 ADC_CLK Suspend - PRS0 1 1 read-write PRSWUDIS Normal mode which does not disable the ADC_CLK. 0 PRSWUEN ADCCLKWUEN will gate off ADC_CLK until the trigger is detected provided the internal timer is not selected as the trigger. Once the trigger is detected the ADC_CLK will be started, the band gap will be started, the ADC will be warmed up, and the SCAN Table and the Single entry will be converted. Once the conversions are done, the ADC_CLK will be gated off. 1 ADCCLKSUSPEND1 ADC_CLK Suspend - PRS1 2 1 read-write PRSWUDIS Normal mode which does not disable the ADC_CLK. 0 PRSWUEN ADCCLKWUEN will gate off ADC_CLK until the trigger is detected provided the internal timer is not selected as the trigger. Once the trigger is detected the ADC_CLK will be started, the band gap will be started, the ADC will be warmed up, and the SCAN Table and the Single entry will be converted. Once the conversions are done, the ADC_CLK will be gated off. 1 DBGHALT Debug Halt 3 1 read-write NORMAL Continue operation as normal during debug mode 0 HALT Complete the current conversion and then halt during debug mode 1 WARMUPMODE Warmup Mode 4 2 read-write NORMAL Shut down the IADC after conversions have completed. 0 KEEPINSTANDBY Switch to standby mode after conversions have completed. The next warmup time will require 1us. 1 KEEPWARM Keep IADC fully powered after conversions have completed. 2 TIMEBASE Time Base 16 7 read-write HSCLKRATE High Speed Clock Rate 28 3 read-write DIV1 Use CMU_CLK_ADC directly. The source clock must be 40 MHz or less. 0 DIV2 Divide CMU_CLK_ADC by 2 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 1 DIV3 Divide CMU_CLK_ADC by 3 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 2 DIV4 Divide CMU_CLK_ADC by 4 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 3 CMD Command 0x00C write-only 0x00000000 0x0303001B SINGLESTART Single Queue Start 0 1 write-only SINGLESTOP Single Queue Stop 1 1 write-only SCANSTART Scan Queue Start 3 1 write-only SCANSTOP Scan Queue Stop 4 1 write-only TIMEREN Timer Enable 16 1 write-only TIMERDIS Timer Disable 17 1 write-only SINGLEFIFOFLUSH Flush the Single FIFO 24 1 write-only SCANFIFOFLUSH Flush the Scan FIFO 25 1 write-only TIMER Timer 0x010 read-write 0x00000000 0x0000FFFF TIMER Timer Period 0 16 read-write STATUS Status 0x014 read-only 0x00000000 0x4131CF5B SINGLEQEN Single Queue Enabled 0 1 read-only SINGLEQUEUEPENDING Single Queue Pending 1 1 read-only SCANQEN Scan Queued Enabled 3 1 read-only SCANQUEUEPENDING Scan Queue Pending 4 1 read-only CONVERTING Converting 6 1 read-only SINGLEFIFODV SINGLEFIFO Data Valid 8 1 read-only SCANFIFODV SCANFIFO Data Valid 9 1 read-only SINGLEFIFOFLUSHING The Single FIFO is flushing 14 1 read-only SCANFIFOFLUSHING The Scan FIFO is flushing 15 1 read-only TIMERACTIVE Timer Active 16 1 read-only SINGLEWRITEPENDING SINGLE write pending 20 1 read-only MASKREQWRITEPENDING MASKREQ write pending 21 1 read-only SYNCBUSY SYNCBUSY 24 1 read-only ADCWARM ADCWARM 30 1 read-only MASKREQ Mask Request 0x018 read-write 0x00000000 0x0000FFFF MASKREQ Scan Queue Mask Request 0 16 read-write STMASK Scan Table Mask 0x01C read-only 0x00000000 0x0000FFFF STMASK Scan Table Mask 0 16 read-only CMPTHR Comparator Threshold 0x020 read-write 0x00000000 0xFFFFFFFF ADLT ADC Less Than or Equal to Threshold 0 16 read-write ADGT ADC Greater Than or Equal to Threshold 16 16 read-write IF Interrupt Flag 0x024 read-write 0x00000000 0x800F338F SINGLEFIFODVL Single FIFO Data Valid Level 0 1 read-write SCANFIFODVL Scan FIFO Data Valid Level 1 1 read-write SINGLECMP Single Result Window Compare 2 1 read-write SCANCMP Scan Result Window Compare 3 1 read-write SCANENTRYDONE Scan Entry Done 7 1 read-write SCANTABLEDONE Scan Table Done 8 1 read-write SINGLEDONE Single Conversion Done 9 1 read-write POLARITYERR Polarity Error 12 1 read-write PORTALLOCERR Port Allocation Error 13 1 read-write SINGLEFIFOOF Single FIFO Overflow 16 1 read-write SCANFIFOOF Scan FIFO Overflow 17 1 read-write SINGLEFIFOUF Single FIFO Underflow 18 1 read-write SCANFIFOUF Scan FIFO Underflow 19 1 read-write EM23ABORTERROR EM2/3 Abort Error 31 1 read-write IEN Interrupt Enable 0x028 read-write 0x00000000 0x800F338F SINGLEFIFODVL Single FIFO Data Valid Level Enable 0 1 read-write SCANFIFODVL Scan FIFO Data Valid Level Enable 1 1 read-write SINGLECMP Single Result Window Compare Enable 2 1 read-write SCANCMP Scan Result Window Compare Enable 3 1 read-write SCANENTRYDONE Scan Entry Done Enable 7 1 read-write SCANTABLEDONE Scan Table Done Enable 8 1 read-write SINGLEDONE Single Conversion Done Enable 9 1 read-write POLARITYERR Polarity Error Enable 12 1 read-write PORTALLOCERR Port Allocation Error Enable 13 1 read-write SINGLEFIFOOF Single FIFO Overflow Enable 16 1 read-write SCANFIFOOF Scan FIFO Overflow Enable 17 1 read-write SINGLEFIFOUF Single FIFO Underflow Enable 18 1 read-write SCANFIFOUF Scan FIFO Underflow Enable 19 1 read-write EM23ABORTERROR EM2/3 Abort Error Enable 31 1 read-write TRIGGER Trigger 0x02C read-write 0x00000000 0x00011717 SCANTRIGSEL Scan Trigger Select 0 3 read-write IMMEDIATE Immediate triggering. The scan queue will be disabled once all conversions in the scan table are complete, unless TRIGGERACTION is set to continuous. 0 TIMER Triggers when the local timer count reaches zero. 1 PRSCLKGRP Triggers on PRS0 from a timer module that is using the same clock group as the ADC and has been programmed to use the same clock source as the ADC. The prescale may be different between the ADC and the timer module. 2 PRSPOS Triggers on asynchronous PRS0 positive edge. Requires PRS0 to go low for 3 ADC_CLKs before another positive edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. 3 PRSNEG Triggers on asynchronous PRS0 negative edge. Requires PRS0 to go high for 3 ADC_CLKs before another negative edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. PRSNEG should only be used when the trigger source is from a module that remains powered during EM23. For modules (ie: TIMER) that power down during EM23, PRSPOS should be used for an asynchronous trigger, and PRSCLKGRP should be used for a synchronous trigger. 4 SCANTRIGACTION Scan Trigger Action 4 1 read-write ONCE For TRIGSEL=IMMEDIATE, goes through the scan table once and disables queue. For TRIGSEL = TIMER, PRSCLKGRP, PRSPOS, PRSNEG, goes through the scan table once per trigger. 0 CONTINUOUS Goes through the scan table, converts each entry with a mask bit set, and puts it back into the scan queue to repeat again continuously. The queues are first come first serve. If both queues are triggered, the single queue will get to convert after each scan table completes. The scan queue will get to convert after each single conversion completes. 1 SINGLETRIGSEL Single Trigger Select 8 3 read-write IMMEDIATE Immediate triggering. The single queue will be disabled once the conversion is complete, unless TRIGGERACTION is set to continuous. 0 TIMER Triggers when the local timer count reaches zero. 1 PRSCLKGRP Triggers on PRS1 from a timer module that is using the same clock group as the ADC and has been programmed to use the same clock source as the ADC. The prescale may be different between the ADC and the timer module. 2 PRSPOS Triggers on asynchronous PRS1 positive edge. Requires PRS1 to go low for 3 ADC_CLKs before another positive edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. 3 PRSNEG Triggers on asynchronous PRS1 negative edge. Requires PRS1 to go high for 3 ADC_CLKs before another negative edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. PRSNEG should only be used when the trigger source is from a module that remains powered during EM23. For modules (ie: TIMER) that power down during EM23, PRSPOS should be used for an asynchronous trigger, and PRSCLKGRP should be used for a synchronous trigger. 4 SINGLETRIGACTION Single Trigger Action 12 1 read-write ONCE For TRIGSEL=IMMEDIATE, converts the single queue once and disables queue. For TRIGSEL = TIMER, PRSCLKGRP, PRSPOS, PRSNEG, converts the single queue once per trigger.ask. 0 CONTINUOUS Converts the single queue, then checks for a pending scan queue before converting the single queue again continuously. The queues are first come first serve. If both queues are continuous, the IADC alternates between them. 1 SINGLETAILGATE Single Tailgate Enable 16 1 read-write TAILGATEOFF The single queue is ready to start warming up and converting once the trigger had been detected. 0 TAILGATEON After the single queue's trigger is detected, it must wait until the end of a scan operation before the Single queue can be converted. 1 CFG0 Configration 0x048 read-write 0x00002060 0x30E770FF ADCMODE ADC Mode 0 2 read-write NORMAL High speed mode with a maximum CLK_ADC of 10 MHz. 0 OSRHS High Speed OSR 2 3 read-write HISPD2 High speed over sampling of 2x. 0 HISPD4 High speed over sampling of 4x. 1 HISPD8 High speed over sampling of 8x. 2 HISPD16 High speed over sampling of 16x. 3 HISPD32 HIgh speed over sampling of 32x. 4 HISPD64 High speed over sampling of 64x. 5 ANALOGGAIN Analog Gain 12 3 read-write ANAGAIN0P5 Analog gain of 0.5x. 1 ANAGAIN1 Analog gain of 1x. 2 ANAGAIN2 Analog gain of 2x. 3 ANAGAIN3 Analog gain of 3x. 4 ANAGAIN4 Analog gain of 4x. 5 REFSEL Reference Select 16 3 read-write VBGR Internal 1.21 V reference. 0 VREF External Reference. (Calibrated for 1.25V nominal.) 1 VDDX AVDD (unbuffered) 3 VDDX0P8BUF AVDD (buffered) * 0.8 4 DIGAVG Digital Averaging 21 3 read-write AVG1 Collect one output word (no digital averaging). 0 AVG2 Collect and average 2 digital output words. 1 AVG4 Collect and average 4 digital output words. 2 AVG8 Collect and average 8 digital output words. 3 AVG16 Collect and average 16 digital output words. 4 TWOSCOMPL Two's Complement 28 2 read-write AUTO Automatic: Single ended measurements are reported as unipolar and differential measurements are reported as bipolar. 0 FORCEUNIPOLAR Force all measurements to result in unipolar output. Negative differential numbers will saturate to 0. 1 FORCEBIPOLAR Force all measurements to result in bipolar output. Single ended measurements are half the range, but allow for small negative measurements. 2 SCALE0 Scale 0x050 read-write 0x8002C000 0xFFFFFFFF OFFSET Offset 0 18 read-write GAIN13LSB Gain 13 LSBs 18 13 read-write GAIN3MSB Gain 3 MSBs 31 1 read-write GAIN011 Upper 3 bits of gain = 011 (0.75x) 0 GAIN100 Upper 3 bits of gain = 100 (1.00x) 1 SCHED0 Scheduling 0x054 read-write 0x00000000 0x000003FF PRESCALE Prescale 0 10 read-write CFG1 Configration 0x058 read-write 0x00002060 0x30E770FF ADCMODE ADC Mode 0 2 read-write NORMAL High speed mode with a maximum CLK_ADC of 10 MHz. 0 OSRHS High Speed OSR 2 3 read-write HISPD2 High speed over sampling of 2x. 0 HISPD4 High speed over sampling of 4x. 1 HISPD8 High speed over sampling of 8x. 2 HISPD16 High speed over sampling of 16x. 3 HISPD32 HIgh speed over sampling of 32x. 4 HISPD64 High speed over sampling of 64x. 5 ANALOGGAIN Analog Gain 12 3 read-write ANAGAIN0P5 Analog gain of 0.5x. 1 ANAGAIN1 Analog gain of 1x. 2 ANAGAIN2 Analog gain of 2x. 3 ANAGAIN3 Analog gain of 3x. 4 ANAGAIN4 Analog gain of 4x. 5 REFSEL Reference Select 16 3 read-write VBGR Internal 1.21 V reference. 0 VREF External Reference. (Calibrated for 1.25V nominal.) 1 VDDX AVDD (unbuffered) 3 VDDX0P8BUF AVDD (buffered) * 0.8 4 DIGAVG Digital Averaging 21 3 read-write AVG1 Collect one output word (no digital averaging). 0 AVG2 Collect and average 2 digital output words. 1 AVG4 Collect and average 4 digital output words. 2 AVG8 Collect and average 8 digital output words. 3 AVG16 Collect and average 16 digital output words. 4 TWOSCOMPL Two's Complement 28 2 read-write AUTO Automatic: Single ended measurements are reported as unipolar and differential measurements are reported as bipolar. 0 FORCEUNIPOLAR Force all measurements to result in unipolar output. Negative differential numbers will saturate to 0. 1 FORCEBIPOLAR Force all measurements to result in bipolar output. Single ended measurements are half the range, but allow for small negative measurements. 2 SCALE1 Scale 0x060 read-write 0x8002C000 0xFFFFFFFF OFFSET Offset 0 18 read-write GAIN13LSB Gain 13 LSBs 18 13 read-write GAIN3MSB Gain 3 MSBs 31 1 read-write GAIN011 Upper 3 bits of gain = 011 (0.75x) 0 GAIN100 Upper 3 bits of gain = 100 (1.00x) 1 SCHED1 Scheduling 0x064 read-write 0x00000000 0x000003FF PRESCALE Prescale 0 10 read-write SINGLEFIFOCFG Single FIFO Configuration 0x070 read-write 0x00000030 0x0000013F ALIGNMENT Alignment 0 3 read-write RIGHT12 ID[7:0], SIGN_EXT, DATA[11:0] 0 RIGHT16 ID[7:0], SIGN_EXT, DATA[15:0] 1 RIGHT20 ID[7:0], SIGN_EXT, DATA[19:0] 2 LEFT12 DATA[11:0], 000000000000, ID[7:0] 3 LEFT16 DATA[15:0], 00000000, ID[7:0] 4 LEFT20 DATA[19:0], 0000, ID[7:0] 5 SHOWID Show ID 3 1 read-write DVL Data Valid Level 4 2 read-write VALID1 When 1 entry in the single FIFO is valid, set the SINGLEFIFODVL interrupt and request DMA. 0 VALID2 When 2 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 1 VALID3 When 3 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 2 VALID4 When 4 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 3 DMAWUFIFOSINGLE Single FIFO DMA wakeup. 8 1 read-write DISABLED While in EM2 or EM3, the DMA controller will not be requested. 0 ENABLED While in EM2 or EM3, the DMA controller will be requested when the single FIFO reaches its Data Valid Level. [DVL must be set to 0 (VALID1).] 1 SINGLEFIFODATA Read the oldest valid data from the single FIFO and pop the FIFO 0x074 read-only 0x00000000 0xFFFFFFFF DATA Single FIFO Read Data 0 32 read-only SINGLEFIFOSTAT Single FIFO status 0x078 read-only 0x00000000 0x00000007 FIFOREADCNT FIFO Read Count 0 3 read-only SINGLEDATA latest single queue conversion data 0x07C read-only 0x00000000 0xFFFFFFFF DATA Data 0 32 read-only SCANFIFOCFG Scan FIFO Configuration 0x080 read-write 0x00000030 0x0000013F ALIGNMENT Alignment 0 3 read-write RIGHT12 ID[7:0], SIGN_EXT, DATA[11:0] 0 RIGHT16 ID[7:0], SIGN_EXT, DATA[15:0] 1 RIGHT20 ID[7:0], SIGN_EXT, DATA[19:0] 2 LEFT12 DATA[11:0], 000000000000, ID[7:0] 3 LEFT16 DATA[15:0], 00000000, ID[7:0] 4 LEFT20 DATA[19:0], 0000, ID[7:0] 5 SHOWID Show ID 3 1 read-write DVL Data Valid Level 4 2 read-write VALID1 When 1 entry in the scan FIFO is valid, set the SCANFIFODVL interrupt and request DMA. 0 VALID2 When 2 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA. 1 VALID3 When 3 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA. 2 VALID4 When 4 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA. 3 DMAWUFIFOSCAN Scan FIFO DMA Wakeup 8 1 read-write DISABLED While in EM2 or EM3, the DMA controller will not be requested. 0 ENABLED While in EM2 or EM3, the DMA controller will be requested when the scan FIFO reaches its Data Valid Level. [DVL must be set to 0 (VALID1).] 1 SCANFIFODATA Read the oldest valid data from the scan FIFO and pop the FIFO 0x084 read-only 0x00000000 0xFFFFFFFF DATA Data 0 32 read-only SCANFIFOSTAT Scan FIFO status 0x088 read-only 0x00000000 0x00000007 FIFOREADCNT FIFO Read Count 0 3 read-only SCANDATA Most recent data data from scan queue conversion 0x08C read-only 0x00000000 0xFFFFFFFF DATA Data 0 32 read-only SINGLE No Description 0x098 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN0 No Description 0x0A0 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN1 No Description 0x0A4 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN2 No Description 0x0A8 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN3 No Description 0x0AC read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN4 No Description 0x0B0 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN5 No Description 0x0B4 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN6 No Description 0x0B8 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN7 No Description 0x0BC read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN8 No Description 0x0C0 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN9 No Description 0x0C4 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN10 No Description 0x0C8 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN11 No Description 0x0CC read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN12 No Description 0x0D0 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN13 No Description 0x0D4 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN14 No Description 0x0D8 read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write SCAN15 No Description 0x0DC read-write 0x00000000 0x0003FFFF PINNEG Negative Pin Select 0 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PINPOS Positive Pin Select 8 4 read-write PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write I2C0_NS 0 I2C0_NS Registers 0x5A010000 0x00000000 0x00001000 registers I2C0 27 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN module enable 0 1 read-write DISABLE Disable Peripheral Clock 0 ENABLE Enable Peripheral Clock 1 CTRL No Description 0x008 read-write 0x00000000 0x0037B3FF CORERST Soft Reset the internal state registers 0 1 read-write DISABLE No change to internal state registers 0 ENABLE Reset the internal state registers 1 SLAVE Addressable as Follower 1 1 read-write DISABLE All addresses will be responded to with a NACK 0 ENABLE Addresses matching the programmed follower address or the general call address (if enabled) require a response from software. Other addresses are automatically responded to with a NACK. 1 AUTOACK Automatic Acknowledge 2 1 read-write DISABLE Software must give one ACK command for each ACK transmitted on the I2C bus. 0 ENABLE Addresses that are not automatically NACK'ed, and all data is automatically acknowledged. 1 AUTOSE Automatic STOP when Empty 3 1 read-write DISABLE A stop must be sent manually when no more data is to be transmitted. 0 ENABLE The leader automatically sends a STOP when no more data is available for transmission. 1 AUTOSN Automatic STOP on NACK 4 1 read-write DISABLE Stop is not automatically sent if a NACK is received from a follower. 0 ENABLE The leader automatically sends a STOP if a NACK is received from a follower. 1 ARBDIS Arbitration Disable 5 1 read-write DISABLE When a device loses arbitration, the ARBIF interrupt flag is set and the bus is released. 0 ENABLE When a device loses arbitration, the ARBIF interrupt flag is set, but communication proceeds. 1 GCAMEN General Call Address Match Enable 6 1 read-write DISABLE General call address will be NACK'ed if it is not included by the follower address and address mask. 0 ENABLE When a general call address is received, a software response is required 1 TXBIL TX Buffer Interrupt Level 7 1 read-write EMPTY TXBL status and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALF_FULL TXBL status and the TXBL interrupt flag are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full 1 CLHR Clock Low High Ratio 8 2 read-write STANDARD Nlow=4 and Nhigh=4, and the Nlow:Nhigh ratio is 4:4 0 ASYMMETRIC Nlow=6 and Nhigh=3, and the Nlow:Nhigh ratio is 6:3 1 FAST Nlow=11 and Nhigh=6, and the Nlow:Nhigh ratio is 11:6 2 BITO Bus Idle Timeout 12 2 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 GIBITO Go Idle on Bus Idle Timeout 15 1 read-write DISABLE A bus idle timeout has no effect on the bus state. 0 ENABLE A bus idle timeout tells the I2C module that the bus is idle, allowing new transfers to be initiated. 1 CLTO Clock Low Timeout 16 3 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 I2C320PCC Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout. 4 I2C1024PCC Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout. 5 SCLMONEN SCL Monitor Enable 20 1 read-write DISABLE Disable SCL monitor 0 ENABLE Enable SCL monitor 1 SDAMONEN SDA Monitor Enable 21 1 read-write DISABLE Disable SDA Monitor 0 ENABLE Enable SDA Monitor 1 CMD No Description 0x00C write-only 0x00000000 0x000000FF START Send start condition 0 1 write-only STOP Send stop condition 1 1 write-only ACK Send ACK 2 1 write-only NACK Send NACK 3 1 write-only CONT Continue transmission 4 1 write-only ABORT Abort transmission 5 1 write-only CLEARTX Clear TX 6 1 write-only CLEARPC Clear Pending Commands 7 1 write-only STATE No Description 0x010 read-only 0x00000001 0x000000FF BUSY Bus Busy 0 1 read-only MASTER Leader 1 1 read-only TRANSMITTER Transmitter 2 1 read-only NACKED Nack Received 3 1 read-only BUSHOLD Bus Held 4 1 read-only STATE Transmission State 5 3 read-only IDLE No transmission is being performed. 0 WAIT Waiting for idle. Will send a start condition as soon as the bus is idle. 1 START Start transmit phase 2 ADDR Address transmit or receive phase 3 ADDRACK Address ack/nack transmit or receive phase 4 DATA Data transmit or receive phase 5 DATAACK Data ack/nack transmit or receive phase 6 STATUS No Description 0x014 read-only 0x00000080 0x00000FFF PSTART Pending START 0 1 read-only PSTOP Pending STOP 1 1 read-only PACK Pending ACK 2 1 read-only PNACK Pending NACK 3 1 read-only PCONT Pending continue 4 1 read-only PABORT Pending abort 5 1 read-only TXC TX Complete 6 1 read-only TXBL TX Buffer Level 7 1 read-only RXDATAV RX Data Valid 8 1 read-only RXFULL RX FIFO Full 9 1 read-only TXBUFCNT TX Buffer Count 10 2 read-only CLKDIV No Description 0x018 read-write 0x00000000 0x000001FF DIV Clock Divider 0 9 read-write SADDR No Description 0x01C read-write 0x00000000 0x000000FE ADDR Follower address 1 7 read-write SADDRMASK No Description 0x020 read-write 0x00000000 0x000000FE SADDRMASK Follower Address Mask 1 7 read-write RXDATA No Description 0x024 read-only 0x00000000 0x000000FF RXDATA RX Data 0 8 read-only RXDOUBLE No Description 0x028 read-only 0x00000000 0x0000FFFF RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDATAP No Description 0x02C read-only 0x00000000 0x000000FF RXDATAP RX Data Peek 0 8 read-only RXDOUBLEP No Description 0x030 read-only 0x00000000 0x0000FFFF RXDATAP0 RX Data 0 Peek 0 8 read-only RXDATAP1 RX Data 1 Peek 8 8 read-only TXDATA No Description 0x034 write-only 0x00000000 0x000000FF TXDATA TX Data 0 8 write-only TXDOUBLE No Description 0x038 write-only 0x00000000 0x0000FFFF TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only IF No Description 0x03C read-write 0x00000000 0x001FFFFF START START condition Interrupt Flag 0 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write ADDR Address Interrupt Flag 2 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write ACK Acknowledge Received Interrupt Flag 6 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write MSTOP Leader STOP Condition Interrupt Flag 8 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write SSTOP Follower STOP condition Interrupt Flag 16 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write IEN No Description 0x040 read-write 0x00000000 0x001FFFFF START START condition Interrupt Flag 0 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write ADDR Address Interrupt Flag 2 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write ACK Acknowledge Received Interrupt Flag 6 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write MSTOP Leader STOP Condition Interrupt Flag 8 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write SSTOP Follower STOP condition Interrupt Flag 16 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write WDOG0_NS 0 WDOG0_NS Registers 0x5A018000 0x00000000 0x00001000 registers WDOG0 43 IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP Version 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Module Enable 0 1 read-write CFG No Description 0x008 read-write 0x000F0000 0x730F071F CLRSRC WDOG Clear Source 0 1 read-write SW A write to the clear bit will clear the WDOG counter 0 PRSSRC0 A rising edge on the PRS Source 0 will clear the WDOG counter 1 EM2RUN EM2 Run 1 1 read-write DISABLE WDOG timer is frozen in EM2. 0 ENABLE WDOG timer is running in EM2. 1 EM3RUN EM3 Run 2 1 read-write DISABLE WDOG timer is frozen in EM3. 0 ENABLE WDOG timer is running in EM3. 1 EM4BLOCK EM4 Block 3 1 read-write DISABLE EM4 can be entered by software. See EMU for detailed description. 0 ENABLE EM4 cannot be entered by software. 1 DEBUGRUN Debug Mode Run 4 1 read-write DISABLE WDOG timer is frozen in debug mode 0 ENABLE WDOG timer is running in debug mode 1 WDOGRSTDIS WDOG Reset Disable 8 1 read-write EN A timeout will cause a WDOG reset 0 DIS A timeout will not cause a WDOG reset 1 PRS0MISSRSTEN PRS Src0 Missing Event WDOG Reset 9 1 read-write PRS1MISSRSTEN PRS Src1 Missing Event WDOG Reset 10 1 read-write PERSEL WDOG Timeout Period Select 16 4 read-write SEL0 Timeout period of 9 wdog cycles 0 SEL1 Timeout period of 17 wdog cycles 1 SEL2 Timeout period of 33 wdog cycles 2 SEL3 Timeout period of 65 wdog cycles 3 SEL4 Timeout period of 129 wdog cycles 4 SEL5 Timeout period of 257 wdog cycles 5 SEL6 Timeout period of 513 wdog cycles 6 SEL7 Timeout period of 1k wdog cycles 7 SEL8 Timeout period of 2k wdog cycles 8 SEL9 Timeout period of 4k wdog cycles 9 SEL10 Timeout period of 8k wdog cycles 10 SEL11 Timeout period of 16k wdog cycles 11 SEL12 Timeout period of 32k wdog cycles 12 SEL13 Timeout period of 64k wdog cycles 13 SEL14 Timeout period of 128k wdog cycles 14 SEL15 Timeout period of 256k wdog cycles 15 WARNSEL WDOG Warning Period Select 24 2 read-write DIS Disable 0 SEL1 Warning timeout is 25% of the Timeout. 1 SEL2 Warning timeout is 50% of the Timeout. 2 SEL3 Warning timeout is 75% of the Timeout. 3 WINSEL WDOG Illegal Window Select 28 3 read-write DIS Disabled. 0 SEL1 Window timeout is 12.5% of the Timeout. 1 SEL2 Window timeout is 25% of the Timeout. 2 SEL3 Window timeout is 37.5% of the Timeout. 3 SEL4 Window timeout is 50% of the Timeout. 4 SEL5 Window timeout is 62.5% of the Timeout. 5 SEL6 Window timeout is 75.5% of the Timeout. 6 SEL7 Window timeout is 87.5% of the Timeout. 7 CMD No Description 0x00C write-only 0x00000000 0x00000001 CLEAR WDOG Timer Clear 0 1 write-only UNCHANGED WDOG timer is unchanged. 0 CLEARED WDOG timer is cleared to 0. 1 STATUS No Description 0x014 read-only 0x00000000 0x80000000 LOCK WDOG Configuration Lock Status 31 1 read-only UNLOCKED All WDOG lockable registers are unlocked. 0 LOCKED All WDOG lockable registers are locked. 1 IF No Description 0x018 read-write 0x00000000 0x0000001F TOUT WDOG Timeout Interrupt Flag 0 1 read-write WARN WDOG Warning Timeout Interrupt Flag 1 1 read-write WIN WDOG Window Interrupt Flag 2 1 read-write PEM0 PRS Src0 Event Missing Interrupt Flag 3 1 read-write PEM1 PRS Src1 Event Missing Interrupt Flag 4 1 read-write IEN No Description 0x01C read-write 0x00000000 0x0000001F TOUT WDOG Timeout Interrupt Enable 0 1 read-write WARN WDOG Warning Timeout Interrupt Enable 1 1 read-write WIN WDOG Window Interrupt Enable 2 1 read-write PEM0 PRS Src0 Event Missing Interrupt Enable 3 1 read-write PEM1 PRS Src1 Event Missing Interrupt Enable 4 1 read-write LOCK No Description 0x020 write-only 0x0000ABE8 0x0000FFFF LOCKKEY WDOG Configuration Lock 0 16 write-only LOCK Lock WDOG lockable registers 0 UNLOCK Unlock WDOG lockable registers 44008 SYNCBUSY No Description 0x024 read-only 0x00000000 0x00000001 CMD Sync Busy for Cmd Register 0 1 read-only AMUXCP0_NS 1 AMUXCP0_NS Registers 0x5A020000 0x00000000 0x00001000 registers IPVERSION IPVERSION 0x000 read-only 0x00000001 0xFFFFFFFF IPVERSION IPVERSION 0 32 read-only CTRL Control 0x008 read-write 0x00000000 0x00000033 FORCEHP Force High Power 0 1 read-write FORCELP Force Low Power 1 1 read-write FORCERUN Force run 4 1 read-write FORCESTOP Force stop 5 1 read-write STATUS Status 0x00C read-only 0x00000000 0x00000003 RUN running 0 1 read-only HICAP high cap 1 1 read-only TEST Test 0x010 read-write 0x00000000 0x80003313 SYNCCLK Sync Clock 0 1 read-write SYNCMODE Sync Mode 1 1 read-write FORCEREQUEST Force Request 4 1 read-write FORCEHICAP Force high capacitance driver 8 1 read-write FORCELOCAP Force low capacitance driver 9 1 read-write FORCEBOOSTON Force Boost On 12 1 read-write FORCEBOOSTOFF Force Boost Off 13 1 read-write STATUSEN Enable write to status bits 31 1 read-write TRIM Trim 0x014 read-write 0x77E44AA1 0x77FFEFFF WARMUPTIME Warm up time 0 2 read-write WUCYCLES72 Warm up cycle = 72; 3.6us @20 MHz 0 WUCYCLES96 Warm up cycle = 96; 4.8us @ 20 MHz 1 WUCYCLES128 Warm up cycle = 128; 6.4us @ 20 MHz 2 WUCYCLES160 Warm up cycle = 160; 8.0us @ 20 MHz 3 FLOATVDDCPLO Float VDDCP Low Power 2 1 read-write FLOATVDDCPHI Float VDDCP High Power 3 1 read-write BYPASSDIV2LO Bypass Div2 Low Power 4 1 read-write BYPASSDIV2HI Bypass Div2 High Power 5 1 read-write BUMP0P5XLO Bump 0.5X Low Power 6 1 read-write BUMP0P5XHI Bump 0.5X High Power 7 1 read-write BIAS2XLO Bias 2x Low Power 8 1 read-write BIAS2XHI Bias 2x High Power 9 1 read-write VOLTAGECTRLLO Charge Pump Voltage Control Low Power 10 2 read-write VOLTAGECTRLHI Charge Pump Voltage Control High Power 13 2 read-write BIASCTRLLO Bias Control Low Power 15 3 read-write BIASCTRLLOCONT Bias Control Low Power Continuous 18 3 read-write BIASCTRLHI Bias Control High Power 21 3 read-write PUMPCAPLO Pump Cap Low Power 24 3 read-write PUMPCAPHI Pump Cap High Power 28 3 read-write EUART0_NS 0 EUART0_NS Registers 0x5A030000 0x00000000 0x00001000 registers IPVERSION No Description 0x000 read-only 0x00000000 0xFFFFFFFF IPVERSION IP version ID 0 32 read-only EN No Description 0x004 read-write 0x00000000 0x00000001 EN Module enable 0 1 read-write CFG0 No Description 0x008 read-write 0x00000000 0xC1D264FE LOOPBK Loopback Enable 1 1 read-write DISABLE The receiver is connected to and receives data from UARTn_RX 0 ENABLE The receiver is connected to and receives data from UARTn_TX 1 CCEN Collision Check Enable 2 1 read-write DISABLE Collision check is disabled 0 ENABLE Collision check is enabled. The receiver must be enabled for the check to be performed 1 MPM Multi-Processor Mode 3 1 read-write DISABLE The 9th bit of incoming frames has no special function 0 ENABLE An incoming frame with the 9th bit equal to MPAB will be loaded into the RX FIFO regardless of RXBLOCK and will result in the MPAB interrupt flag being set 1 MPAB Multi-Processor Address-Bit 4 1 read-write OVS Oversampling 5 3 read-write X16 16X oversampling 0 X8 8X oversampling 1 X6 6X oversampling 2 X4 4X oversampling 3 DISABLE Disable oversampling (for LF operation) 4 MSBF Most Significant Bit First 10 1 read-write DISABLE Data is sent with the least significant bit first 0 ENABLE Data is sent with the most significant bit first 1 RXINV Receiver Input Invert 13 1 read-write DISABLE Input is passed directly to the receiver 0 ENABLE Input is inverted before it is passed to the receiver 1 TXINV Transmitter output Invert 14 1 read-write DISABLE Output from the transmitter is passed unchanged to UARTn_TX 0 ENABLE Output from the transmitter is inverted before it is passed to UARTn_TX 1 AUTOTRI Automatic TX Tristate 17 1 read-write DISABLE The output on UARTn_TX when the transmitter is idle is defined by TXINV 0 ENABLE UARTn_TX is tristated whenever the transmitter is idle 1 SKIPPERRF Skip Parity Error Frames 20 1 read-write ERRSDMA Halt DMA Read On Error 22 1 read-write DISABLE Framing and parity errors have no effect on DMA requests from the UART 0 ENABLE DMA requests from the UART are blocked while the PERR or FERR interrupt flags are set 1 ERRSRX Disable RX On Error 23 1 read-write DISABLE Framing and parity errors have no effect on receiver 0 ENABLE Framing and parity errors disable the receiver 1 ERRSTX Disable TX On Error 24 1 read-write DISABLE Received framing and parity errors have no effect on transmitter 0 ENABLE Received framing and parity errors disable the transmitter 1 MVDIS Majority Vote Disable 30 1 read-write AUTOBAUDEN AUTOBAUD detection enable 31 1 read-write CFG1 No Description 0x00C read-write 0x00000000 0x00DB8E0F DBGHALT Debug halt 0 1 read-write DISABLE Continue normal UART operation even if core is halted 0 ENABLE If core is halted, receive one frame and then halt reception by deactivating RTS. Next frame reception happens when the core is unhalted during single stepping. 1 CTSINV Clear-to-send Invert Enable 1 1 read-write DISABLE The CTS pin is active low 0 ENABLE The CTS pin is active high 1 CTSEN Clear-to-send Enable 2 1 read-write DISABLE Ignore CTS 0 ENABLE Stop transmitting when CTS is inactive 1 RTSINV Request-to-send Invert Enable 3 1 read-write DISABLE The RTS pin is active low 0 ENABLE The RTS pin is active high 1 TXDMAWU Transmitter DMA Wakeup 9 1 read-write RXDMAWU Receiver DMA Wakeup 10 1 read-write SFUBRX Start Frame Unblock Receiver 11 1 read-write RXPRSEN PRS RX Enable 15 1 read-write TXFIW TX FIFO Interrupt Watermark 16 2 read-write ONEFRAME TXFL status flag and IF are set when the TX FIFO has space for at least one more frame. 0 TWOFRAMES TXFL status flag and IF are set when the TX FIFO has space for at least two more frames. 1 THREEFRAMES TXFL status flag and IF are set when the TX FIFO has space for at least three more frames. 2 FOURFRAMES TXFL status flag and IF are set when the TX FIFO has space for at least four more frames. 3 RXFIW RX FIFO Interrupt Watermark 19 2 read-write ONEFRAME RXFL status flag and IF are set when the RX FIFO has at least one frame in it. 0 TWOFRAMES RXFL status flag and IF are set when the RX FIFO has at least two frames in it. 1 THREEFRAMES RXFL status flag and IF are set when the RX FIFO has at least three frames in it. 2 FOURFRAMES RXFL status flag and IF are set when the RX FIFO has four frames in it. 3 RTSRXFW Request-to-send RX FIFO Watermark 22 2 read-write ONEFRAME RTS is set if there is space for at least one more frame in the RX FIFO. 0 TWOFRAMES RTS is set if there is space for at least two more frames in the RX FIFO. 1 THREEFRAMES RTS is set if there is space for at least three more frames in the RX FIFO. 2 FOURFRAMES RTS is set if there is space for four more frames in the RX FIFO. 3 FRAMECFG No Description 0x010 read-write 0x00001002 0x00003303 DATABITS Data-Bit Mode 0 2 read-write SEVEN Each frame contains 7 data bits 1 EIGHT Each frame contains 8 data bits 2 NINE Each frame contains 9 data bits 3 PARITY Parity-Bit Mode 8 2 read-write NONE Parity bits are not used 0 EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. 2 ODD Odd parity is used. Parity bits are automatically generated and checked by hardware. 3 STOPBITS Stop-Bit Mode 12 2 read-write HALF The transmitter generates a half stop bit. Stop-bits are not verified by receiver 0 ONE One stop bit is generated and verified 1 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies the first stop bit 2 TWO The transmitter generates two stop bits. The receiver checks the first stop-bit only 3 IRHFCFG No Description 0x014 read-write 0x00000000 0x0000000F IRHFEN Enable IrDA Module 0 1 read-write IRHFPW IrDA TX Pulse Width 1 2 read-write ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 0 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 2 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 3 IRHFFILT IrDA RX Filter 3 1 read-write DISABLE No filter enabled 0 ENABLE Filter enabled. IrDA pulse must be high for at least 4 consecutive clock cycles to be detected 1 IRLFCFG No Description 0x018 read-write 0x00000000 0x00000001 IRLFEN Pulse Generator/Extender Enable 0 1 read-write TIMINGCFG No Description 0x01C read-write 0x00000000 0x00000003 TXDELAY TX Delay Transmission 0 2 read-write NONE Frames are transmitted immediately. 0 SINGLE Transmission of new frames is delayed by a single bit period. 1 DOUBLE Transmission of new frames is delayed by a two bit periods. 2 TRIPPLE Transmission of new frames is delayed by a three bit periods. 3 STARTFRAMECFG No Description 0x020 read-write 0x00000000 0x000001FF STARTFRAME Start Frame 0 9 read-write SIGFRAMECFG No Description 0x024 read-write 0x00000000 0x000001FF SIGFRAME Signal Frame Value 0 9 read-write CLKDIV No Description 0x028 read-write 0x00000000 0x007FFFF8 DIV Fractional Clock Divider 3 20 read-write TRIGCTRL No Description 0x02C read-write 0x00000000 0x00000003 RXTEN Receive Trigger Enable 0 1 read-write TXTEN Transmit Trigger Enable 1 1 read-write CMD No Description 0x030 write-only 0x00000000 0x000001FF RXEN Receiver Enable 0 1 write-only RXDIS Receiver Disable 1 1 write-only TXEN Transmitter Enable 2 1 write-only TXDIS Transmitter Disable 3 1 write-only RXBLOCKEN Receiver Block Enable 4 1 write-only RXBLOCKDIS Receiver Block Disable 5 1 write-only TXTRIEN Transmitter Tristate Enable 6 1 write-only TXTRIDIS Transmitter Tristate Disable 7 1 write-only CLEARTX Clear TX FIFO 8 1 write-only RXDATA No Description 0x034 read-only 0x00000000 0x000007FF RXDATA RX Data 0 9 read-only PERR Parity Error 9 1 read-only FERR Framing Error 10 1 read-only RXDATAP No Description 0x038 read-only 0x00000000 0x000007FF RXDATAP RX Data Peek 0 9 read-only PERRP Parity Error Peek 9 1 read-only FERRP Framing Error Peek 10 1 read-only TXDATA No Description 0x03C write-only 0x00000000 0x00003FFF TXDATA TX Data 0 9 write-only UBRXAT Unblock RX After Transmission 9 1 write-only TXTRIAT Set TXTRI After Transmisssion 10 1 write-only TXBREAK Transit Data as Break 11 1 write-only TXDISAT Clear TXEN After Transmission 12 1 write-only RXENAT Enable RXEN After Transmission 13 1 write-only STATUS No Description 0x040 read-only 0x00003040 0x010F31FB RXENS Receiver Enable Status 0 1 read-only TXENS Transmitter Enable Status 1 1 read-only RXBLOCK Block Incoming Data 3 1 read-only TXTRI Transmitter Tristated 4 1 read-only TXC TX Complete 5 1 read-only TXFL TX FIFO Level 6 1 read-only RXFL RX FIFO Level 7 1 read-only RXFULL RX FIFO Full 8 1 read-only RXIDLE RX Idle 12 1 read-only TXIDLE TX Idle 13 1 read-only TXFCNT Valid entries in TX FIFO 16 3 read-only CLEARTXBUSY TX FIFO Clear Busy 19 1 read-only AUTOBAUDDONE Auto Baud Rate Detection Completed 24 1 read-only IF No Description 0x044 read-write 0x00000000 0x010C377F TXC TX Complete Interrupt Flag 0 1 read-write TXFL TX FIFO Level Interrupt Flag 1 1 read-write RXFL RX FIFO Level Interrupt Flag 2 1 read-write RXFULL RX FIFO Full Interrupt Flag 3 1 read-write RXOF RX FIFO Overflow Interrupt Flag 4 1 read-write RXUF RX FIFO Underflow Interrupt Flag 5 1 read-write TXOF TX FIFO Overflow Interrupt Flag 6 1 read-write PERR Parity Error Interrupt Flag 8 1 read-write FERR Framing Error Interrupt Flag 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write CCF Collision Check Fail Interrupt Flag 12 1 read-write TXIDLE TX Idle Interrupt Flag 13 1 read-write STARTF Start Frame Interrupt Flag 18 1 read-write SIGF Signal Frame Interrupt Flag 19 1 read-write AUTOBAUDDONE Auto Baud Complete Interrupt Flag 24 1 read-write IEN No Description 0x048 read-write 0x00000000 0x010C377F TXC TX Complete IEN 0 1 read-write TXFL TX FIFO Level IEN 1 1 read-write RXFL RX FIFO Level IEN 2 1 read-write RXFULL RX FIFO Full IEN 3 1 read-write RXOF RX FIFO Overflow IEN 4 1 read-write RXUF RX FIFO Underflow IEN 5 1 read-write TXOF TX FIFO Overflow IEN 6 1 read-write PERR Parity Error IEN 8 1 read-write FERR Framing Error IEN 9 1 read-write MPAF Multi-Processor Addr Frame IEN 10 1 read-write CCF Collision Check Fail IEN 12 1 read-write TXIDLE TX IDLE IEN 13 1 read-write STARTF Start Frame IEN 18 1 read-write SIGF Signal Frame IEN 19 1 read-write AUTOBAUDDONE Auto Baud Complete IEN 24 1 read-write SYNCBUSY No Description 0x04C read-only 0x00000000 0x000007FF DIV SYNCBUSY for DIV in CLKDIV 0 1 read-only RXTEN SYNCBUSY for RXTEN in TRIGCTRL 1 1 read-only TXTEN SYNCBUSY for TXTEN in TRIGCTRL 2 1 read-only RXEN SYNCBUSY for RXEN in CMD 3 1 read-only RXDIS SYNCBUSY for RXDIS in CMD 4 1 read-only TXEN SYNCBUSY for TXEN in CMD 5 1 read-only TXDIS SYNCBUSY for TXDIS in CMD 6 1 read-only RXBLOCKEN SYNCBUSY for RXBLOCKEN in CMD 7 1 read-only RXBLOCKDIS SYNCBUSY for RXBLOCKDIS in CMD 8 1 read-only TXTRIEN SYNCBUSY for TXTRIEN in CMD 9 1 read-only TXTRIDIS SYNCBUSY in TXTRIDIS in CMD 10 1 read-only CRYPTOACC_NS 1 CRYPTOACC_NS Registers 0x5C020000 0x00000000 0x00001000 registers CRYPTOACC 0 TRNG 1 PKE 2 FETCHADDR Fetcher: Start address of data block. In direct mode, this register is written by the software. In scatter-gather mode, this register is updated after each processed descriptor. 0x000 read-write 0x00000000 0xFFFFFFFF ADDR Start address of data block 0 32 read-write FETCHLEN Fetcher: Length of data block. In direct mode, this register is written by the software. In scatter-gather mode, this register is not used. 0x008 read-write 0x00000000 0x3FFFFFFF LENGTH Length of data block 0 28 read-write CONSTADDR Constant address 28 1 read-write REALIGN Realign length 29 1 read-write FETCHTAG Fetcher: User tag. In direct mode, this register is written by the software. In scatter-gather mode, this register is not used. 0x00C read-write 0x00000000 0xFFFFFFFF TAG User tag 0 32 read-write PUSHADDR Pusher: Start address of data block (LSB). In direct mode, this register is written by the software. In scatter-gather mode, this register is updated after each processed descriptor. 0x010 read-write 0x00000000 0xFFFFFFFF ADDR Start address of data block 0 32 read-write PUSHLEN Pusher: Length of data block. In direct mode, this register is written by the software. In scatter-gather mode, this register is not used. 0x018 read-write 0x00000000 0x7FFFFFFF LENGTH Start address of data block 0 28 read-write CONSTADDR Constant address 28 1 read-write REALIGN Realign length 29 1 read-write DISCARD Discard data 30 1 read-write IEN Interrupt enable 0x01C read-write 0x00000000 0x0000003F FETCHERENDOFBLOCK End of block interrupt enable 0 1 read-write FETCHERSTOPPED Stopped interrupt enable 1 1 read-write FETCHERERROR Error interrupt enable 2 1 read-write PUSHERENDOFBLOCK End of block interrupt enable 3 1 read-write PUSHERSTOPPED Stopped interrupt enable 4 1 read-write PUSHERERROR Error interrupt enable 5 1 read-write IF Interrupt flag register 0x028 read-only 0x00000000 0x0000003F FETCHERENDOFBLOCK End of block interrupt flag 0 1 read-only FETCHERSTOPPED Stopped interrupt flag 1 1 read-only FETCHERERROR Error interrupt flag 2 1 read-only PUSHERENDOFBLOCK End of block interrupt flag 3 1 read-only PUSHERSTOPPED Stopped interrupt flag 4 1 read-only PUSHERERROR Error interrupt flag 5 1 read-only IF_CLR Writing a '1' clears the interrupt status. Writing a '0' has no effect. 0x030 write-only 0x00000000 0x0000003F FETCHERENDOFBLOCK End of block interrupt flag clear 0 1 write-only FETCHERSTOPPED Stopped interrupt flag clear 1 1 write-only FETCHERERROR Error interrupt flag clear 2 1 write-only PUSHERENDOFBLOCK End of block interrupt flag clear 3 1 write-only PUSHERSTOPPED Stopped interrupt flag clear 4 1 write-only PUSHERERROR Error interrupt flag clear 5 1 write-only CTRL Control register, called CONFIG in Barco datasheet. 0x034 read-write 0x00000000 0x0000001F FETCHERSCATTERGATHER Fetcher scatter/gather 0 1 read-write PUSHERSCATTERGATHER Pusher scatter/gather 1 1 read-write STOPFETCHER Stop fetcher 2 1 read-write STOPPUSHER Stop pusher 3 1 read-write SWRESET Software reset 4 1 read-write CMD Command register for starting the fetcher and pusher 0x038 write-only 0x00000000 0x00000003 STARTFETCHER Start fetch 0 1 write-only STARTPUSHER Start push 1 1 write-only STATUS Status register 0x03C read-only 0x00000000 0xFFFF0073 FETCHERBSY Fetcher busy 0 1 read-only PUSHERBSY Pusher busy 1 1 read-only NOTEMPTY Not empty flag from input FIFO (fetcher) 4 1 read-only WAITING Pusher waiting for FIFO 5 1 read-only SOFTRSTBSY Software reset busy 6 1 read-only FIFODATANUM Number of data in output FIFO 16 16 read-only INCL_IPS_HW_CFG No Description 0x400 read-only 0x00000611 0x000007FF g_IncludeAES Generic g_IncludeAES value 0 1 read-only g_IncludeAESGCM Generic g_IncludeAESGCM value 1 1 read-only g_IncludeAESXTS Generic g_IncludeAESXTS value 2 1 read-only g_IncludeDES Generic g_IncludeDES value 3 1 read-only g_IncludeHASH Generic g_IncludeHASH value 4 1 read-only g_IncludeChachaPoly Generic g_IncludeChachaPoly value 5 1 read-only g_IncludeSHA3 Generic g_IncludeSHA3 value 6 1 read-only g_IncludeZUC Generic g_IncludeZUC value 7 1 read-only g_IncludeSM4 Generic g_IncludeSM4 value 8 1 read-only g_IncludePKE Generic g_IncludePKE value 9 1 read-only g_IncludeNDRNG Generic g_IncludeNDRNG value 10 1 read-only BA411E_HW_CFG_1 No Description 0x404 read-only 0x0700017F 0x070301FF g_AesModesPoss AES Modes Supported 0 9 read-only g_CS Generic g_CS value 16 1 read-only g_UseMasking Generic g_UseMasking value 17 1 read-only g_Keysize Generic g_Keysize value 24 3 read-only BA411E_HW_CFG_2 No Description 0x408 read-only 0x00000080 0x0000FFFF g_CtrSize Generic g_CtrSize value 0 16 read-only BA413_HW_CFG No Description 0x40C read-only 0x0003007F 0x0007007F g_HashMaskFunc Generic g_HashMaskFunc value 0 7 read-only g_HashPadding Generic g_HashPadding value 16 1 read-only g_HMAC_enabled Generic g_HMAC_enabled value 17 1 read-only g_HashVerifyDigest Generic g_HashVerifyDigest value 18 1 read-only BA418_HW_CFG No Description 0x410 read-only 0x00000001 0x00000001 g_Sha3CtxtEn Generic g_Sha3CtxtEn value 0 1 read-only BA419_HW_CFG No Description 0x414 read-only 0x0000005F 0x0000007F g_SM4ModesPoss Generic g_SM4ModesPoss value 0 7 read-only CRYPTOACC_NS_RNGCTRL 1 CRYPTOACC_NS_RNGCTRL Registers 0x5C021000 0x00000000 0x00001000 registers CRYPTOACC 0 TRNG 1 PKE 2 RNGCTRL No Description 0x000 read-write 0x00040000 0x001FFFFF ENABLE TRNG Module Enable 0 1 read-write DISABLED Module disabled 0 ENABLED Module enabled 1 TESTEN Test Enable 2 1 read-write NOISE Non-determinsitc random number generation 0 TESTDATA Pseudo-random number generation 1 CONDBYPASS Conditioning Bypass 3 1 read-write NORMAL The conditionig function is used 0 BYPASS The conditioning function is bypassed 1 REPCOUNTIEN IRQ enable for Repetition Count Test 4 1 read-write APT64IEN IRQ enable for APT64IF 5 1 read-write APT4096IEN IRQ enable for APT4096IF 6 1 read-write FULLIEN IRQ enable for FIFO full 7 1 read-write SOFTRESET Software Reset 8 1 read-write NORMAL Module not in reset 0 RESET The continuous test, the conditioning function and the FIFO are reset 1 PREIEN IRQ enable for AIS31 prelim. noise alarm 9 1 read-write ALMIEN IRQ enable for AIS31 noise alarm 10 1 read-write FORCERUN Oscillator Force Run 11 1 read-write NORMAL Oscillators will shut down when FIFO is full 0 RUN Oscillators will continue to run even after FIFO is full 1 BYPNIST NIST Start-up Test Bypass. 12 1 read-write NORMAL NIST-800-90B startup test is applied. No data will be written to the FIFO until the test passes. 0 BYPASS NIST-800-90B startup test is bypassed. 1 BYPAIS31 AIS31 Start-up Test Bypass. 13 1 read-write NORMAL AIS31 startup test is applied. No data will be written to the FIFO until the test passes. 0 BYPASS AIS31 startup test is bypassed. 1 HEALTHTESTSEL Health test input select 14 1 read-write BEFORE Before conditioning 0 AFTER After conditioning 1 AIS31TESTSEL AIS31 test input select 15 1 read-write BEFORE Before conditioning 0 AFTER After conditioning 1 NB128BITBLOCKS Number of 128b blocks in AES-CBCMAC 16 4 read-write FIFOWRSTARTUP Fifo Write Start Up 20 1 read-write FIFOLEVEL Number of 32 bits words of random available in the FIFO. Writing to this register clears the FIFO full interrupt 0x004 read-only 0x00000000 0xFFFFFFFF FIFOLEVEL FIFO Level 0 32 read-only FIFOTHRESH FIFO level at which the rings are restarted when in the FIFOFull_Off state, expressed in number of 128bit blocks 0x008 read-only 0x0000003F 0xFFFFFFFF FIFOTHRESH FIFO threshold level 0 32 read-only FIFODEPTH Maximum number of 32 bits words that can be stored in the FIFO: 2^g_fifodepth 0x00C read-only 0x00000040 0xFFFFFFFF FIFODEPTH FIFO Depth. 0 32 read-only KEY0 This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011... 0x010 read-write 0x00000000 0xFFFFFFFF KEY Key 0 32 read-write KEY1 This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011... 0x014 read-write 0x00000000 0xFFFFFFFF KEY Key 0 32 read-write KEY2 This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011... 0x018 read-write 0x00000000 0xFFFFFFFF KEY Key 0 32 read-write KEY3 This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011... 0x01C read-write 0x00000000 0xFFFFFFFF KEY Key 0 32 read-write TESTDATA This register is used to feed known data to the conditioning function or to the continuous tests. See manual 0x020 write-only 0x00000000 0xFFFFFFFF VALUE Test data input to conditioning tests 0 32 write-only RNGSTATUS No Description 0x030 read-write 0x00000000 0x000007FF TESTDATABUSY Test Data Busy 0 1 read-only IDLE TESTDATA write is finished processing or no test in progress. 0 BUSY TESTDATA write is still being processed. 1 STATE State of the control FSM 1 3 read-only RESET RESET State 0 STARTUP STARTUP State 1 FIFOFULLON FIFOFULLON State 2 FIFOFULLOFF FIFOFULLOFF State 3 RUNNING RUNNING State 4 ERROR ERROR State 5 UNUSED_6 UNUSED 6 UNUSED_7 UNUSED 7 REPCOUNTIF Repetition Count Test interrupt status 4 1 read-only APT64IF 64-sample window Adaptive Proportion IF 5 1 read-only APT4096IF 4096-sample window Adaptive Prop. IF 6 1 read-only FULLIF FIFO full interrupt status 7 1 read-only PREIF AIS31 Preliminary Noise Alarm IF 8 1 read-write ALMIF AIS31 Noise Alarm interrupt status 9 1 read-only INITWAITVAL No Description 0x034 read-write 0x0000FFFF 0x0000FFFF INITWAITVAL Wait counter value 0 16 read-write SWOFFTMRVAL Number of clk cycles to wait before stopping the rings after the FIFO is full 0x040 read-write 0x0000FFFF 0x0000FFFF SWOFFTMRVAL Switch Off Timer Value 0 16 read-write CLKDIV Sample clock divider. The frequency at which the outputs of the rings are sampled is given by Fs = Fpclk/(ClkDiv + 1) 0x044 read-write 0x00000000 0x000000FF VALUE Sample clock divider 0 8 read-write AIS31CONF0 No Description 0x048 read-write 0x43401040 0x7FFF7FFF STARTUPTHRES Start-up Threshold 0 15 read-write ONLINETHRESH Online Threshold 16 15 read-write AIS31CONF1 No Description 0x04C read-write 0x03C00680 0x7FFF7FFF HEXPECTEDVALUE Expected History Value 0 15 read-write ONLINEREPTHRESH Online Repeat Threshold 16 15 read-write AIS31CONF2 No Description 0x050 read-write 0x04400340 0x7FFF7FFF HMIN Minimum Allowed History Value 0 15 read-write HMAX Maximum Allowed History Value 16 15 read-write AIS31STATUS This register is used to obtain diagnostic information about the AIS31 start-up and online tests when g_AIS31=True. Writing to this register clears all fields 0x054 read-write 0x00000000 0x0003FFFF NUMPRELIMALARMS Number of preliminary alarms 0 16 read-write PRELIMNOISEALARMRNG Preliminary noise alarm RNG 16 1 read-write PRELIMNOISEALARMREP Preliminary noise alarm Rep 17 1 read-write CRYPTOACC_NS_PKCTRL 1 CRYPTOACC_NS_PKCTRL Registers 0x5C022000 0x00000000 0x00001000 registers CRYPTOACC 0 TRNG 1 PKE 2 POINTER No Description 0x000 read-write 0x00000000 0x0F0F0F0F OPPTRA OpPtrA 0 4 read-write OPPTRB OpPtrB 8 4 read-write OPPTRC OpPtrC 16 4 read-write OPPTRN OpPtrN 24 4 read-write COMMAND No Description 0x004 read-write 0x00000000 0xFC77FFFF OPERATION Type of Operation 0 7 read-write FIELD Field 7 1 read-write GFP Field is GF(p) 0 GF2M Field is GF(2^m) 1 SIZE Size of Operands in data memory 8 11 read-write SELCURVE Select Curve 20 3 read-write NONE No acceleration 0 P256 P256 1 P192 P192 4 EDWARDS Edwards Curve Enable 26 1 read-write BUFSEL Buffer Select 27 1 read-write MEM0 use data in data memory 0 0 SWAPBYTES Swap bytes 28 1 read-write NATIVE Native format (little endian) 0 SWAPPED Byte swapped (big endian) 1 FLAGA Flag A 29 1 read-write FLAGB Flag B 30 1 read-write CALCR2 Calculate R2 31 1 read-write FALSE don't recalculate R² mod N 0 TRUE re-calculate R² mod N 1 PKCTRL No Description 0x008 write-only 0x00000000 0x00000003 PKSTART PK Start 0 1 write-only IFC ClearIRQ 1 1 write-only PKSTATUS No Description 0x00C read-only 0x00000000 0x00033FFF FAILADDR Fail Address 0 4 read-only NOTONCURVE Point Px not on curve 4 1 read-only ATINFINITY Point Px at infinity 5 1 read-only COUPLENOTVALID Couple not valid 6 1 read-only PARAMNNOTVALID Param n not valid 7 1 read-only NOTIMPLEMENTED Not implemented 8 1 read-only SIGNOTVALID Signature not valid 9 1 read-only PARAMABNOTVALID Param AB not valid 10 1 read-only NOTINVERTIBLE Not invertible 11 1 read-only COMPOSITE Composite 12 1 read-only FALSE random number under test is probably prime 0 TRUE random number under test is composite 1 NOTQUAD Not quadratic residue 13 1 read-only PKBUSY PK busy 16 1 read-only PKIF Interrupt status 17 1 read-only VERSION No Description 0x010 read-only 0x00000000 0x0000FFFF SW Software version number 0 8 read-only HW Hardware version number 8 8 read-only TIMER No Description 0x014 read-only 0x00000000 0xFFFFFFFF TIMER Timer 0 32 read-only DEVINFO 1 DEVINFO Registers 0x0FE08000 0x00000000 0x00001000 registers INFO Version of the device info structure being used 0x000 read-only 0x07000000 0xFFFFFFFF CRC CRC 0 16 read-only PRODREV Production Revision 16 8 read-only DEVINFOREV DI Page Version 24 8 read-only PART Part description 0x004 read-only 0x00000000 0x3F3FFFFF DEVICENUM Device Number 0 16 read-only FAMILYNUM Device Family 16 6 read-only FAMILY Device Family 24 6 read-only FG Flex Gecko 0 MG Mighty Gecko 1 BG Blue Gecko 2 PG Pearl Gecko 5 MEMINFO Flash page size and misc. chip information 0x008 read-only 0x00000000 0xFFFFFFFF FLASHPAGESIZE Flash Page Size 0 8 read-only UDPAGESIZE User Data Page Size 8 8 read-only DILEN Length of DI Page 16 16 read-only MSIZE Flash and SRAM Memory size in kB 0x00C read-only 0x00000000 0x07FFFFFF FLASH Flash Size 0 16 read-only SRAM Sram Size 16 11 read-only PKGINFO Miscellaneous device information 0x010 read-only 0x00000000 0x00FFFFFF TEMPGRADE Temperature Grade 0 8 read-only N40TO85 -40 to 85 degC 0 N40TO125 -40 to 125 degC 1 N40TO105 -40 to 105 degC 2 N0TO70 0 to 70 degC 3 PKGTYPE Package Type 8 8 read-only WLCSP WLCSP package 74 BGA BGA package 76 QFN QFN package 77 QFP QFP package 81 PINCOUNT Pin Count 16 8 read-only CUSTOMINFO Custom information 0x014 read-only 0x00000000 0xFFFF0000 PARTNO Part Number 16 16 read-only SWFIX Used to track s/w workaround info 0x018 read-only 0xFFFFFFFF 0xFFFFFFFF RSV Reserved 0 32 read-only SWCAPA0 Software Capability Vector 0 0x01C read-only 0x00000000 0x00333333 ZIGBEE Zigbee Capability 0 2 read-only LEVEL0 Zigbee stack capability not available 0 LEVEL1 Green Power only 1 LEVEL2 Zigbee and Green Power 2 LEVEL3 Zigbee Only 3 THREAD Thread Capability 4 2 read-only LEVEL0 Thread stack capability not available 0 LEVEL1 Thread stack enabled 1 LEVEL2 N/A 2 LEVEL3 N/A 3 RF4CE RF4CE Capability 8 2 read-only LEVEL0 RF4CE stack capability not available 0 LEVEL1 RF4CE stack enabled 1 LEVEL2 N/A 2 LEVEL3 N/A 3 BTSMART Bluetooth Smart Capability 12 2 read-only LEVEL0 Bluetooth SMART stack capability not available 0 LEVEL1 Bluetooth SMART enabled 1 LEVEL2 N/A 2 LEVEL3 N/A 3 CONNECT Connect Capability 16 2 read-only LEVEL0 Connect stack capability not available 0 LEVEL1 Connect enabled 1 LEVEL2 N/A 2 LEVEL3 N/A 3 SRI RAIL Capability 20 2 read-only LEVEL0 RAIL capability not available 0 LEVEL1 RAIL enabled 1 LEVEL2 N/A 2 LEVEL3 N/A 3 SWCAPA1 Software Capability Vector 1 0x020 read-only 0x00000000 0x00000007 RFMCUEN RF-MCU 0 1 read-only NCPEN NCP 1 1 read-only GWEN Gateway 2 1 read-only EXTINFO External component description 0x028 read-only 0x00000000 0x00FFFFFF TYPE Type 0 8 read-only NONE 255 CONNECTION Connection 8 8 read-only SPI SPI control interface 0 NONE No interface 255 REV Revision 16 8 read-only EUI48L MA-L compliant EUI48 OUI (low bits) and Unique Identifier (24-bit) 0x040 read-only 0x00000000 0xFFFFFFFF UNIQUEID Unique ID 0 24 read-only OUI48L OUI48L 24 8 read-only EUI48H MA-L compliant EUI48 OUI (high bits) 0x044 read-only 0xFFFF0000 0xFFFFFFFF OUI48H OUI48H 0 16 read-only RESERVED RESERVED 16 16 read-only EUI64L MA-L compliant EUI64 Unique Identifier (low bits) 0x048 read-only 0x00000000 0xFFFFFFFF UNIQUEL UNIQUEL 0 32 read-only EUI64H MA-L compliant EUI64 OUI and Unique Identifier (high bits) 0x04C read-only 0x00000000 0xFFFFFFFF UNIQUEH UNIQUEH 0 8 read-only OUI64 OUI64 8 24 read-only CALTEMP Calibration Temperature Information 0x050 read-only 0x00000000 0x000000FF TEMP Cal Temp 0 8 read-only EMUTEMP EMU Temperature Sensor Calibration 0x054 read-only 0x00000000 0x1FFF07FC EMUTEMPROOM Emu Room Temperature 2 9 read-only HFRCODPLLCAL0 HFRCODPLL Calibration 0x058 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL1 HFRCODPLL Calibration 0x05C read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL2 HFRCODPLL Calibration 0x060 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL3 HFRCODPLL Calibration 0x064 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL4 HFRCODPLL Calibration 0x068 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL5 HFRCODPLL Calibration 0x06C read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL6 HFRCODPLL Calibration 0x070 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL7 HFRCODPLL Calibration 0x074 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL8 HFRCODPLL Calibration 0x078 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL9 HFRCODPLL Calibration 0x07C read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL10 HFRCODPLL Calibration 0x080 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL11 HFRCODPLL Calibration 0x084 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL12 HFRCODPLL Calibration 0x088 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL13 HFRCODPLL Calibration 0x08C read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL14 HFRCODPLL Calibration 0x090 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL15 HFRCODPLL Calibration 0x094 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL16 HFRCODPLL Calibration 0x098 read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only HFRCODPLLCAL17 HFRCODPLL Calibration 0x09C read-only 0x00000000 0xFFFFBF7F TUNING 0 7 read-only FINETUNING 8 6 read-only LDOHP 15 1 read-only FREQRANGE 16 5 read-only CMPBIAS 21 3 read-only CLKDIV 24 2 read-only CMPSEL 26 2 read-only IREFTC 28 4 read-only MODULENAME0 Characters 1-4 of Module Name stored as a null terminated string 0x130 read-only 0xFFFFFFFF 0xFFFFFFFF MODCHAR1 0 8 read-only MODCHAR2 8 8 read-only MODCHAR3 16 8 read-only MODCHAR4 24 8 read-only MODULENAME1 Characters 5-8 of Module Name stored as a null terminated string 0x134 read-only 0xFFFFFFFF 0xFFFFFFFF MODCHAR5 0 8 read-only MODCHAR6 8 8 read-only MODCHAR7 16 8 read-only MODCHAR8 24 8 read-only MODULENAME2 Characters 9-12 of Module Name stored as a null terminated string 0x138 read-only 0xFFFFFFFF 0xFFFFFFFF MODCHAR9 0 8 read-only MODCHAR10 8 8 read-only MODCHAR11 16 8 read-only MODCHAR12 24 8 read-only MODULENAME3 Characters 13-16 of Module Name stored as a null terminated string 0x13C read-only 0xFFFFFFFF 0xFFFFFFFF MODCHAR13 0 8 read-only MODCHAR14 8 8 read-only MODCHAR15 16 8 read-only MODCHAR16 24 8 read-only MODULENAME4 Characters 17-20 of Module Name stored as a null terminated string 0x140 read-only 0xFFFFFFFF 0xFFFFFFFF MODCHAR17 0 8 read-only MODCHAR18 8 8 read-only MODCHAR19 16 8 read-only MODCHAR20 24 8 read-only MODULENAME5 Characters 21-24 of Module Name stored as a null terminated string 0x144 read-only 0xFFFFFFFF 0xFFFFFFFF MODCHAR21 0 8 read-only MODCHAR22 8 8 read-only MODCHAR23 16 8 read-only MODCHAR24 24 8 read-only MODULENAME6 Characters 25-26 of Module Name stored as a null terminated string 0x148 read-only 0xFFFFFFFF 0xFFFFFFFF MODCHAR25 0 8 read-only MODCHAR26 8 8 read-only RSV 16 16 read-only MODULEINFO Module Information 0x14C read-only 0xFFFFFFFF 0xFFFFFFFF HWREV 0 5 read-only ANTENNA 5 3 read-only BUILTIN Built-in Antenna 0 CONNECTOR RF Connector 1 RFPAD RF Pad 2 INVERTEDF F-invert PCB 3 MODNUMBER 8 7 read-only TYPE 15 1 read-only PCB PCB 0 SIP SIP 1 LFXO 16 1 read-only NONE LFXO is not installed 0 PRESENT LFXO is installed 1 EXPRESS 17 1 read-only SUPPORTED Blue Gecko Express is supported 0 NONE Blue Gecko Express is not supported 1 LFXOCALVAL 18 1 read-only VALID LFXO Tuning in MODXOCAL is valid 0 NOTVALID LFXO Tuning value in MODXOCAL is not valid 1 HFXOCALVAL 19 1 read-only VALID HFXO calibration in MODXOCAL is valid 0 NOTVALID HFXO calibration in MODXOCAL is not valid 1 MODNUMBERMSB 20 9 read-only PADCDC 29 1 read-only VDCDC PAVDD connected to Vdcdc 0 OTHER PAVDD connected to Vdd or other 1 PHYLIMITED 30 1 read-only LIMITED 0 UNLIMITED 1 EXTVALID 31 1 read-only EXTUSED EXT used 0 EXTUNUSED EXT not used 1 MODXOCAL Module Crystal Oscillator Calibration 0x150 read-only 0x007FFFFF 0x007FFFFF HFXOCTUNEXIANA 0 8 read-only HFXOCTUNEXOANA 8 8 read-only LFXOCAPTUNE 16 7 read-only IADC0GAIN0 IADC0 Gain Calibration Info 0x180 read-only 0x00000000 0xFFFFFFFF GAINCANA1 0 16 read-only GAINCANA2 16 16 read-only IADC0GAIN1 IADC0 Gain Calibration Info 0x184 read-only 0x00000000 0xFFFFFFFF GAINCANA3 0 16 read-only GAINCANA4 16 16 read-only IADC0OFFSETCAL0 IADC0 Offset Calibration Info 0x188 read-only 0x00000000 0xFFFFFFFF OFFSETANABASE 0 16 read-only OFFSETANA1HIACC 16 16 read-only IADC0NORMALOFFSETCAL0 IADC0 Normal Offset Calibration Info 0x18C read-only 0x00000000 0xFFFFFFFF OFFSETANA1NORM 0 16 read-only OFFSETANA2NORM 16 16 read-only IADC0NORMALOFFSETCAL1 IADC0 Normal Offset Calibration Info 0x190 read-only 0x00000000 0x0000FFFF OFFSETANA3NORM 0 16 read-only IADC0HISPDOFFSETCAL0 IADC High Speed Offset Calibration Info 0x194 read-only 0x00000000 0xFFFFFFFF OFFSETANA1HISPD 0 16 read-only OFFSETANA2HISPD 16 16 read-only IADC0HISPDOFFSETCAL1 IADC High Speed Offset Calibration Info 0x198 read-only 0x00000000 0x0000FFFF OFFSETANA3HISPD 0 16 read-only LEGACY This is the legacy device detection information for tools compatability 0x1FC read-only 0x00800000 0x00FF0000 DEVICEFAMILY Device Family 16 8 read-only EFR32MG1P EFR32 Mighty Gecko Family Series 1 Device Config 1 16 EFR32MG1B EFR32 Mighty Gecko Family Series 1 Device Config 1 17 EFR32MG1V EFR32 Mighty Gecko Family Series 1 Device Config 1 18 EFR32BG1P EFR32 Blue Gecko Family Series 1 Device Config 1 19 EFR32BG1B EFR32 Blue Gecko Family Series 1 Device Config 1 20 EFR32BG1V EFR32 Blue Gecko Family Series 1 Device Config 1 21 EFR32FG1P EFR32 Flex Gecko Family Series 1 Device Config 1 25 EFR32FG1B EFR32 Flex Gecko Family Series 1 Device Config 1 26 EFR32FG1V EFR32 Flex Gecko Family Series 1 Device Config 1 27 EFR32MG12P EFR32 Mighty Gecko Family Series 1 Device Config 2 28 EFR32MG12B EFR32 Mighty Gecko Family Series 1 Device Config 2 29 EFR32MG12V EFR32 Mighty Gecko Family Series 1 Device Config 2 30 EFR32BG12P EFR32 Blue Gecko Family Series 1 Device Config 2 31 EFR32BG12B EFR32 Blue Gecko Family Series 1 Device Config 2 32 EFR32BG12V EFR32 Blue Gecko Family Series 1 Device Config 2 33 EFR32FG12P EFR32 Flex Gecko Family Series 1 Device Config 2 37 EFR32FG12B EFR32 Flex Gecko Family Series 1 Device Config 2 38 EFR32FG12V EFR32 Flex Gecko Family Series 1 Device Config 2 39 EFR32MG13P EFR32 Mighty Gecko Family Series 13 Device Config 3 40 EFR32MG13B EFR32 Mighty Gecko Family Series 13 Device Config 3 41 EFR32MG13V EFR32 Mighty Gecko Family Series 1 Device Config 3 42 EFR32BG13P EFR32 Blue Gecko Family Series 1 Device Config 3 43 EFR32BG13B EFR32 Blue Gecko Family Series 1 Device Config 3 44 EFR32BG13V EFR32 Blue Gecko Family Series 1 Device Config 3 45 EFR32FG13P EFR32 Flex Gecko Family Series 1 Device Config 3 49 EFR32FG13B EFR32 Flex Gecko Family Series 1 Device Config 3 50 EFR32FG13V EFR32 Flex Gecko Family Series 1 Device Config 3 51 EFR32MG14P EFR32 Mighty Gecko Family Series 1 Device Config 4 52 EFR32MG14B EFR32 Mighty Gecko Family Series 1 Device Config 4 53 EFR32MG14V EFR32 Mighty Gecko Family Series 1 Device Config 4 54 EFR32BG14P EFR32 Blue Gecko Family Series 1 Device Config 4 55 EFR32BG14B EFR32 Blue Gecko Family Series 1 Device Config 4 56 EFR32BG14V EFR32 Blue Gecko Family Series 1 Device Config 4 57 EFR32FG14P EFR32 Flex Gecko Family Series 1 Device Config 4 61 EFR32FG14B EFR32 Flex Gecko Family Series 1 Device Config 4 62 EFR32FG14V EFR32 Flex Gecko Family Series 1 Device Config 4 63 EFM32G EFM32 Gecko Device Family 71 EFM32GG EFM32 Giant Gecko Device Family 72 EFM32TG EFM32 Tiny Gecko Device Family 73 EFM32LG EFM32 Leopard Gecko Device Family 74 EFM32WG EFM32 Wonder Gecko Device Family 75 EFM32ZG EFM32 Zero Gecko Device Family 76 EFM32HG EFM32 Happy Gecko Device Family 77 EFM32PG1B EFM32 Pearl Gecko Device Family Series 1 Device Config 1 81 EFM32JG1B EFM32 Jade Gecko Device Family Series 1 Device Config 1 83 EFM32PG12B EFM32 Pearl Gecko Device Family Series 1 Device Config 2 85 EFM32JG12B EFM32 Jade Gecko Device Family Series 1 Device Config 2 87 EFM32PG13B EFM32 Pearl Gecko Device Family Series 1 Device Config 3 89 EFM32JG13B EFM32 Jade Gecko Device Family Series 1 Device Config 3 91 EFM32GG11B EFM32 Giant Gecko Device Family Series 1 Device Config 1 100 EFM32TG11B EFM32 Giant Gecko Device Family Series 1 Device Config 1 103 EZR32LG EZR32 Leopard Gecko Device Family 120 EZR32WG EZR32 Wonder Gecko Device Family 121 EZR32HG EZR32 Happy Gecko Device Family 122 SERIES2V0 DI page is encoded with the series 2 layout. Check alternate location. 128 RTHERM Thermistor Calibrated Internal Resistance 0x25C read-only 0x00000000 0x0000FFFF RTHERM 0 16 read-only Copyright 2018 Silicon Laboratories, Inc. 0x00000000 0x00080000 rx 0x0FE00000 0x00000400 rx 0x0FE08000 0x00000400 rx 0x0FE0E000 0x00000600 rx 0x20000000 0x00008000 rwx 0x4C024000 0x00004000 rwx 0x4C028000 0x00001000 rwx 0x5C024000 0x00004000 rwx 0x5C028000 0x00001000 rwx 0xA0000000 0x00004000 rwx 0xA0004000 0x00001000 rwx 0xB0000000 0x00004000 rwx 0xB0004000 0x00001000 rwx